generic_dram
============
Predefined DRAM tests. DRAM is called "Memory" in AVL.

Inherit
-------
- :doc:`base.test_list <base.test_list>`

MemorySize
----------
pytest_name
```````````
:doc:`memory_size <../pytests/memory_size>`

ProbeDram
---------
pytest_name
```````````
:doc:`probe.probe <../pytests/probe.probe>`

args
````
``component_list``
  ::
  
    [
      "dram"
    ]
    

``config_file``
  ::
  
    "/usr/local/factory/py/hwid/v3/default_probe_statement.json"
    

``overridden_rules``
  ::
  
    [
      [
        "dram",
        ">",
        0
      ]
    ]
    

StressAppTest
-------------
pytest_name
```````````
:doc:`stressapptest <../pytests/stressapptest>`



MRCCache
--------
Serial subtests
```````````````
-  ::
  
    {
      "args": {
        "mode": "create"
      },
      "label": "i18n! Create Cache",
      "pytest_name": "mrc_cache"
    }
    


- RebootStep


-  ::
  
    {
      "args": {
        "mode": "verify_update"
      },
      "label": "i18n! Verify Cache Update",
      "pytest_name": "mrc_cache"
    }
    


- RebootStep


-  ::
  
    {
      "args": {
        "mode": "verify_no_update"
      },
      "label": "i18n! Verify Cache No Update",
      "pytest_name": "mrc_cache"
    }