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1 : // Copyright 2014 the V8 project authors. All rights reserved.
2 : // Use of this source code is governed by a BSD-style license that can be
3 : // found in the LICENSE file.
4 :
5 : #ifndef V8_COMPILER_INSTRUCTION_CODES_H_
6 : #define V8_COMPILER_INSTRUCTION_CODES_H_
7 :
8 : #include <iosfwd>
9 :
10 : #if V8_TARGET_ARCH_ARM
11 : #include "src/compiler/arm/instruction-codes-arm.h"
12 : #elif V8_TARGET_ARCH_ARM64
13 : #include "src/compiler/arm64/instruction-codes-arm64.h"
14 : #elif V8_TARGET_ARCH_IA32
15 : #include "src/compiler/ia32/instruction-codes-ia32.h"
16 : #elif V8_TARGET_ARCH_MIPS
17 : #include "src/compiler/mips/instruction-codes-mips.h"
18 : #elif V8_TARGET_ARCH_MIPS64
19 : #include "src/compiler/mips64/instruction-codes-mips64.h"
20 : #elif V8_TARGET_ARCH_X64
21 : #include "src/compiler/x64/instruction-codes-x64.h"
22 : #elif V8_TARGET_ARCH_PPC
23 : #include "src/compiler/ppc/instruction-codes-ppc.h"
24 : #elif V8_TARGET_ARCH_S390
25 : #include "src/compiler/s390/instruction-codes-s390.h"
26 : #elif V8_TARGET_ARCH_X87
27 : #include "src/compiler/x87/instruction-codes-x87.h"
28 : #else
29 : #define TARGET_ARCH_OPCODE_LIST(V)
30 : #define TARGET_ADDRESSING_MODE_LIST(V)
31 : #endif
32 : #include "src/globals.h"
33 : #include "src/utils.h"
34 :
35 : namespace v8 {
36 : namespace internal {
37 : namespace compiler {
38 :
39 : // Modes for ArchStoreWithWriteBarrier below.
40 : enum class RecordWriteMode { kValueIsMap, kValueIsPointer, kValueIsAny };
41 :
42 :
43 : // Target-specific opcodes that specify which assembly sequence to emit.
44 : // Most opcodes specify a single instruction.
45 : #define COMMON_ARCH_OPCODE_LIST(V) \
46 : V(ArchCallCodeObject) \
47 : V(ArchTailCallCodeObjectFromJSFunction) \
48 : V(ArchTailCallCodeObject) \
49 : V(ArchCallJSFunction) \
50 : V(ArchTailCallJSFunctionFromJSFunction) \
51 : V(ArchTailCallAddress) \
52 : V(ArchPrepareCallCFunction) \
53 : V(ArchCallCFunction) \
54 : V(ArchPrepareTailCall) \
55 : V(ArchJmp) \
56 : V(ArchLookupSwitch) \
57 : V(ArchTableSwitch) \
58 : V(ArchNop) \
59 : V(ArchDebugBreak) \
60 : V(ArchComment) \
61 : V(ArchThrowTerminator) \
62 : V(ArchDeoptimize) \
63 : V(ArchRet) \
64 : V(ArchStackPointer) \
65 : V(ArchFramePointer) \
66 : V(ArchParentFramePointer) \
67 : V(ArchTruncateDoubleToI) \
68 : V(ArchStoreWithWriteBarrier) \
69 : V(CheckedLoadInt8) \
70 : V(CheckedLoadUint8) \
71 : V(CheckedLoadInt16) \
72 : V(CheckedLoadUint16) \
73 : V(CheckedLoadWord32) \
74 : V(CheckedLoadWord64) \
75 : V(CheckedLoadFloat32) \
76 : V(CheckedLoadFloat64) \
77 : V(CheckedStoreWord8) \
78 : V(CheckedStoreWord16) \
79 : V(CheckedStoreWord32) \
80 : V(CheckedStoreWord64) \
81 : V(CheckedStoreFloat32) \
82 : V(CheckedStoreFloat64) \
83 : V(ArchStackSlot) \
84 : V(AtomicLoadInt8) \
85 : V(AtomicLoadUint8) \
86 : V(AtomicLoadInt16) \
87 : V(AtomicLoadUint16) \
88 : V(AtomicLoadWord32) \
89 : V(AtomicStoreWord8) \
90 : V(AtomicStoreWord16) \
91 : V(AtomicStoreWord32) \
92 : V(AtomicExchangeInt8) \
93 : V(AtomicExchangeUint8) \
94 : V(AtomicExchangeInt16) \
95 : V(AtomicExchangeUint16) \
96 : V(AtomicExchangeWord32) \
97 : V(AtomicCompareExchangeInt8) \
98 : V(AtomicCompareExchangeUint8) \
99 : V(AtomicCompareExchangeInt16) \
100 : V(AtomicCompareExchangeUint16) \
101 : V(AtomicCompareExchangeWord32) \
102 : V(AtomicAddInt8) \
103 : V(AtomicAddUint8) \
104 : V(AtomicAddInt16) \
105 : V(AtomicAddUint16) \
106 : V(AtomicAddWord32) \
107 : V(AtomicSubInt8) \
108 : V(AtomicSubUint8) \
109 : V(AtomicSubInt16) \
110 : V(AtomicSubUint16) \
111 : V(AtomicSubWord32) \
112 : V(AtomicAndInt8) \
113 : V(AtomicAndUint8) \
114 : V(AtomicAndInt16) \
115 : V(AtomicAndUint16) \
116 : V(AtomicAndWord32) \
117 : V(AtomicOrInt8) \
118 : V(AtomicOrUint8) \
119 : V(AtomicOrInt16) \
120 : V(AtomicOrUint16) \
121 : V(AtomicOrWord32) \
122 : V(AtomicXorInt8) \
123 : V(AtomicXorUint8) \
124 : V(AtomicXorInt16) \
125 : V(AtomicXorUint16) \
126 : V(AtomicXorWord32) \
127 : V(Ieee754Float64Acos) \
128 : V(Ieee754Float64Acosh) \
129 : V(Ieee754Float64Asin) \
130 : V(Ieee754Float64Asinh) \
131 : V(Ieee754Float64Atan) \
132 : V(Ieee754Float64Atanh) \
133 : V(Ieee754Float64Atan2) \
134 : V(Ieee754Float64Cbrt) \
135 : V(Ieee754Float64Cos) \
136 : V(Ieee754Float64Cosh) \
137 : V(Ieee754Float64Exp) \
138 : V(Ieee754Float64Expm1) \
139 : V(Ieee754Float64Log) \
140 : V(Ieee754Float64Log1p) \
141 : V(Ieee754Float64Log10) \
142 : V(Ieee754Float64Log2) \
143 : V(Ieee754Float64Pow) \
144 : V(Ieee754Float64Sin) \
145 : V(Ieee754Float64Sinh) \
146 : V(Ieee754Float64Tan) \
147 : V(Ieee754Float64Tanh)
148 :
149 : #define ARCH_OPCODE_LIST(V) \
150 : COMMON_ARCH_OPCODE_LIST(V) \
151 : TARGET_ARCH_OPCODE_LIST(V)
152 :
153 : enum ArchOpcode {
154 : #define DECLARE_ARCH_OPCODE(Name) k##Name,
155 : ARCH_OPCODE_LIST(DECLARE_ARCH_OPCODE)
156 : #undef DECLARE_ARCH_OPCODE
157 : #define COUNT_ARCH_OPCODE(Name) +1
158 : kLastArchOpcode = -1 ARCH_OPCODE_LIST(COUNT_ARCH_OPCODE)
159 : #undef COUNT_ARCH_OPCODE
160 : };
161 :
162 : V8_EXPORT_PRIVATE std::ostream& operator<<(std::ostream& os,
163 : const ArchOpcode& ao);
164 :
165 : // Addressing modes represent the "shape" of inputs to an instruction.
166 : // Many instructions support multiple addressing modes. Addressing modes
167 : // are encoded into the InstructionCode of the instruction and tell the
168 : // code generator after register allocation which assembler method to call.
169 : #define ADDRESSING_MODE_LIST(V) \
170 : V(None) \
171 : TARGET_ADDRESSING_MODE_LIST(V)
172 :
173 : enum AddressingMode {
174 : #define DECLARE_ADDRESSING_MODE(Name) kMode_##Name,
175 : ADDRESSING_MODE_LIST(DECLARE_ADDRESSING_MODE)
176 : #undef DECLARE_ADDRESSING_MODE
177 : #define COUNT_ADDRESSING_MODE(Name) +1
178 : kLastAddressingMode = -1 ADDRESSING_MODE_LIST(COUNT_ADDRESSING_MODE)
179 : #undef COUNT_ADDRESSING_MODE
180 : };
181 :
182 : V8_EXPORT_PRIVATE std::ostream& operator<<(std::ostream& os,
183 : const AddressingMode& am);
184 :
185 : // The mode of the flags continuation (see below).
186 : enum FlagsMode {
187 : kFlags_none = 0,
188 : kFlags_branch = 1,
189 : kFlags_deoptimize = 2,
190 : kFlags_set = 3,
191 : kFlags_trap = 4
192 : };
193 :
194 : V8_EXPORT_PRIVATE std::ostream& operator<<(std::ostream& os,
195 : const FlagsMode& fm);
196 :
197 : // The condition of flags continuation (see below).
198 : enum FlagsCondition {
199 : kEqual,
200 : kNotEqual,
201 : kSignedLessThan,
202 : kSignedGreaterThanOrEqual,
203 : kSignedLessThanOrEqual,
204 : kSignedGreaterThan,
205 : kUnsignedLessThan,
206 : kUnsignedGreaterThanOrEqual,
207 : kUnsignedLessThanOrEqual,
208 : kUnsignedGreaterThan,
209 : kFloatLessThanOrUnordered,
210 : kFloatGreaterThanOrEqual,
211 : kFloatLessThanOrEqual,
212 : kFloatGreaterThanOrUnordered,
213 : kFloatLessThan,
214 : kFloatGreaterThanOrEqualOrUnordered,
215 : kFloatLessThanOrEqualOrUnordered,
216 : kFloatGreaterThan,
217 : kUnorderedEqual,
218 : kUnorderedNotEqual,
219 : kOverflow,
220 : kNotOverflow,
221 : kPositiveOrZero,
222 : kNegative
223 : };
224 :
225 : inline FlagsCondition NegateFlagsCondition(FlagsCondition condition) {
226 1666343 : return static_cast<FlagsCondition>(condition ^ 1);
227 : }
228 :
229 : FlagsCondition CommuteFlagsCondition(FlagsCondition condition);
230 :
231 : V8_EXPORT_PRIVATE std::ostream& operator<<(std::ostream& os,
232 : const FlagsCondition& fc);
233 :
234 : // The InstructionCode is an opaque, target-specific integer that encodes
235 : // what code to emit for an instruction in the code generator. It is not
236 : // interesting to the register allocator, as the inputs and flags on the
237 : // instructions specify everything of interest.
238 : typedef int32_t InstructionCode;
239 :
240 : // Helpers for encoding / decoding InstructionCode into the fields needed
241 : // for code generation. We encode the instruction, addressing mode, and flags
242 : // continuation into a single InstructionCode which is stored as part of
243 : // the instruction.
244 : typedef BitField<ArchOpcode, 0, 9> ArchOpcodeField;
245 : typedef BitField<AddressingMode, 9, 5> AddressingModeField;
246 : typedef BitField<FlagsMode, 14, 3> FlagsModeField;
247 : typedef BitField<FlagsCondition, 17, 5> FlagsConditionField;
248 : typedef BitField<int, 22, 10> MiscField;
249 :
250 : } // namespace compiler
251 : } // namespace internal
252 : } // namespace v8
253 :
254 : #endif // V8_COMPILER_INSTRUCTION_CODES_H_
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