Line data Source code
1 : // Copyright (c) 1994-2006 Sun Microsystems Inc.
2 : // All Rights Reserved.
3 : //
4 : // Redistribution and use in source and binary forms, with or without
5 : // modification, are permitted provided that the following conditions are
6 : // met:
7 : //
8 : // - Redistributions of source code must retain the above copyright notice,
9 : // this list of conditions and the following disclaimer.
10 : //
11 : // - Redistribution in binary form must reproduce the above copyright
12 : // notice, this list of conditions and the following disclaimer in the
13 : // documentation and/or other materials provided with the distribution.
14 : //
15 : // - Neither the name of Sun Microsystems or the names of contributors may
16 : // be used to endorse or promote products derived from this software without
17 : // specific prior written permission.
18 : //
19 : // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
20 : // IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
21 : // THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 : // PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
23 : // CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
24 : // EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
25 : // PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
26 : // PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
27 : // LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
28 : // NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
29 : // SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 :
31 : // The original source code covered by the above license above has been
32 : // modified significantly by Google Inc.
33 : // Copyright 2012 the V8 project authors. All rights reserved.
34 :
35 : // A lightweight X64 Assembler.
36 :
37 : #ifndef V8_X64_ASSEMBLER_X64_H_
38 : #define V8_X64_ASSEMBLER_X64_H_
39 :
40 : #include <deque>
41 : #include <map>
42 : #include <vector>
43 :
44 : #include "src/assembler.h"
45 : #include "src/label.h"
46 : #include "src/objects/smi.h"
47 : #include "src/x64/constants-x64.h"
48 : #include "src/x64/register-x64.h"
49 : #include "src/x64/sse-instr.h"
50 :
51 : namespace v8 {
52 : namespace internal {
53 :
54 : class SafepointTableBuilder;
55 :
56 : // Utility functions
57 :
58 : enum Condition {
59 : // any value < 0 is considered no_condition
60 : no_condition = -1,
61 :
62 : overflow = 0,
63 : no_overflow = 1,
64 : below = 2,
65 : above_equal = 3,
66 : equal = 4,
67 : not_equal = 5,
68 : below_equal = 6,
69 : above = 7,
70 : negative = 8,
71 : positive = 9,
72 : parity_even = 10,
73 : parity_odd = 11,
74 : less = 12,
75 : greater_equal = 13,
76 : less_equal = 14,
77 : greater = 15,
78 :
79 : // Fake conditions that are handled by the
80 : // opcodes using them.
81 : always = 16,
82 : never = 17,
83 : // aliases
84 : carry = below,
85 : not_carry = above_equal,
86 : zero = equal,
87 : not_zero = not_equal,
88 : sign = negative,
89 : not_sign = positive,
90 : last_condition = greater
91 : };
92 :
93 :
94 : // Returns the equivalent of !cc.
95 : // Negation of the default no_condition (-1) results in a non-default
96 : // no_condition value (-2). As long as tests for no_condition check
97 : // for condition < 0, this will work as expected.
98 0 : inline Condition NegateCondition(Condition cc) {
99 463852 : return static_cast<Condition>(cc ^ 1);
100 : }
101 :
102 :
103 : enum RoundingMode {
104 : kRoundToNearest = 0x0,
105 : kRoundDown = 0x1,
106 : kRoundUp = 0x2,
107 : kRoundToZero = 0x3
108 : };
109 :
110 :
111 : // -----------------------------------------------------------------------------
112 : // Machine instruction Immediates
113 :
114 : class Immediate {
115 : public:
116 1251513 : explicit constexpr Immediate(int32_t value) : value_(value) {}
117 : explicit constexpr Immediate(int32_t value, RelocInfo::Mode rmode)
118 : : value_(value), rmode_(rmode) {}
119 : explicit Immediate(Smi value)
120 0 : : value_(static_cast<int32_t>(static_cast<intptr_t>(value.ptr()))) {
121 : DCHECK(SmiValuesAre31Bits()); // Only available for 31-bit SMI.
122 : }
123 :
124 : private:
125 : const int32_t value_;
126 : const RelocInfo::Mode rmode_ = RelocInfo::NONE;
127 :
128 : friend class Assembler;
129 : };
130 : ASSERT_TRIVIALLY_COPYABLE(Immediate);
131 : static_assert(sizeof(Immediate) <= kSystemPointerSize,
132 : "Immediate must be small enough to pass it by value");
133 :
134 : class Immediate64 {
135 : public:
136 : explicit constexpr Immediate64(int64_t value) : value_(value) {}
137 : explicit constexpr Immediate64(int64_t value, RelocInfo::Mode rmode)
138 : : value_(value), rmode_(rmode) {}
139 : explicit constexpr Immediate64(Address value, RelocInfo::Mode rmode)
140 55656840 : : value_(static_cast<int64_t>(value)), rmode_(rmode) {}
141 :
142 : private:
143 : const int64_t value_;
144 : const RelocInfo::Mode rmode_ = RelocInfo::NONE;
145 :
146 : friend class Assembler;
147 : };
148 :
149 : // -----------------------------------------------------------------------------
150 : // Machine instruction Operands
151 :
152 : enum ScaleFactor : int8_t {
153 : times_1 = 0,
154 : times_2 = 1,
155 : times_4 = 2,
156 : times_8 = 3,
157 : times_int_size = times_4,
158 : times_system_pointer_size = (kSystemPointerSize == 8) ? times_8 : times_4,
159 : times_tagged_size = (kTaggedSize == 8) ? times_8 : times_4,
160 : };
161 :
162 : class V8_EXPORT_PRIVATE Operand {
163 : public:
164 55739348 : struct Data {
165 : byte rex = 0;
166 : byte buf[9];
167 : byte len = 1; // number of bytes of buf_ in use.
168 : int8_t addend; // for rip + offset + addend.
169 : };
170 :
171 : // [base + disp/r]
172 : Operand(Register base, int32_t disp);
173 :
174 : // [base + index*scale + disp/r]
175 : Operand(Register base,
176 : Register index,
177 : ScaleFactor scale,
178 : int32_t disp);
179 :
180 : // [index*scale + disp/r]
181 : Operand(Register index,
182 : ScaleFactor scale,
183 : int32_t disp);
184 :
185 : // Offset from existing memory operand.
186 : // Offset is added to existing displacement as 32-bit signed values and
187 : // this must not overflow.
188 : Operand(Operand base, int32_t offset);
189 :
190 : // [rip + disp/r]
191 : explicit Operand(Label* label, int addend = 0);
192 :
193 : Operand(const Operand&) V8_NOEXCEPT = default;
194 :
195 : // Checks whether either base or index register is the given register.
196 : // Does not check the "reg" part of the Operand.
197 : bool AddressUsesRegister(Register reg) const;
198 :
199 : // Queries related to the size of the generated instruction.
200 : // Whether the generated instruction will have a REX prefix.
201 : bool requires_rex() const { return data_.rex != 0; }
202 : // Size of the ModR/M, SIB and displacement parts of the generated
203 : // instruction.
204 : int operand_size() const { return data_.len; }
205 :
206 : const Data& data() const { return data_; }
207 :
208 : private:
209 : const Data data_;
210 : };
211 : ASSERT_TRIVIALLY_COPYABLE(Operand);
212 : static_assert(sizeof(Operand) <= 2 * kSystemPointerSize,
213 : "Operand must be small enough to pass it by value");
214 :
215 : #define ASSEMBLER_INSTRUCTION_LIST(V) \
216 : V(add) \
217 : V(and) \
218 : V(cmp) \
219 : V(cmpxchg) \
220 : V(dec) \
221 : V(idiv) \
222 : V(div) \
223 : V(imul) \
224 : V(inc) \
225 : V(lea) \
226 : V(mov) \
227 : V(movzxb) \
228 : V(movzxw) \
229 : V(neg) \
230 : V(not) \
231 : V(or) \
232 : V(repmovs) \
233 : V(sbb) \
234 : V(sub) \
235 : V(test) \
236 : V(xchg) \
237 : V(xor)
238 :
239 : // Shift instructions on operands/registers with kInt32Size and kInt64Size.
240 : #define SHIFT_INSTRUCTION_LIST(V) \
241 : V(rol, 0x0) \
242 : V(ror, 0x1) \
243 : V(rcl, 0x2) \
244 : V(rcr, 0x3) \
245 : V(shl, 0x4) \
246 : V(shr, 0x5) \
247 : V(sar, 0x7)
248 :
249 : // Partial Constant Pool
250 : // Different from complete constant pool (like arm does), partial constant pool
251 : // only takes effects for shareable constants in order to reduce code size.
252 : // Partial constant pool does not emit constant pool entries at the end of each
253 : // code object. Instead, it keeps the first shareable constant inlined in the
254 : // instructions and uses rip-relative memory loadings for the same constants in
255 : // subsequent instructions. These rip-relative memory loadings will target at
256 : // the position of the first inlined constant. For example:
257 : //
258 : // REX.W movq r10,0x7f9f75a32c20 ; 10 bytes
259 : // …
260 : // REX.W movq r10,0x7f9f75a32c20 ; 10 bytes
261 : // …
262 : //
263 : // turns into
264 : //
265 : // REX.W movq r10,0x7f9f75a32c20 ; 10 bytes
266 : // …
267 : // REX.W movq r10,[rip+0xffffff96] ; 7 bytes
268 : // …
269 :
270 41471444 : class ConstPool {
271 : public:
272 41476083 : explicit ConstPool(Assembler* assm) : assm_(assm) {}
273 : // Returns true when partial constant pool is valid for this entry.
274 : bool TryRecordEntry(intptr_t data, RelocInfo::Mode mode);
275 : bool IsEmpty() const { return entries_.empty(); }
276 :
277 : void PatchEntries();
278 : // Discard any pending pool entries.
279 : void Clear();
280 :
281 : private:
282 : // Adds a shared entry to entries_. Returns true if this is not the first time
283 : // we add this entry, false otherwise.
284 : bool AddSharedEntry(uint64_t data, int offset);
285 :
286 : // Check if the instruction is a rip-relative move.
287 : bool IsMoveRipRelative(Address instr);
288 :
289 : Assembler* assm_;
290 :
291 : // Values, pc offsets of entries.
292 : typedef std::multimap<uint64_t, int> EntryMap;
293 : EntryMap entries_;
294 :
295 : // Number of bytes taken up by the displacement of rip-relative addressing.
296 : static constexpr int kRipRelativeDispSize = 4; // 32-bit displacement.
297 : // Distance between the address of the displacement in the rip-relative move
298 : // instruction and the head address of the instruction.
299 : static constexpr int kMoveRipRelativeDispOffset =
300 : 3; // REX Opcode ModRM Displacement
301 : // Distance between the address of the imm64 in the 'movq reg, imm64'
302 : // instruction and the head address of the instruction.
303 : static constexpr int kMoveImm64Offset = 2; // REX Opcode imm64
304 : // A mask for rip-relative move instruction.
305 : static constexpr uint32_t kMoveRipRelativeMask = 0x00C7FFFB;
306 : // The bits for a rip-relative move instruction after mask.
307 : static constexpr uint32_t kMoveRipRelativeInstr = 0x00058B48;
308 : };
309 :
310 : class V8_EXPORT_PRIVATE Assembler : public AssemblerBase {
311 : private:
312 : // We check before assembling an instruction that there is sufficient
313 : // space to write an instruction and its relocation information.
314 : // The relocation writer's position must be kGap bytes above the end of
315 : // the generated instructions. This leaves enough space for the
316 : // longest possible x64 instruction, 15 bytes, and the longest possible
317 : // relocation information encoding, RelocInfoWriter::kMaxLength == 16.
318 : // (There is a 15 byte limit on x64 instruction length that rules out some
319 : // otherwise valid instructions.)
320 : // This allows for a single, fast space check per instruction.
321 : static constexpr int kGap = 32;
322 :
323 : public:
324 : // Create an assembler. Instructions and relocation information are emitted
325 : // into a buffer, with the instructions starting from the beginning and the
326 : // relocation information starting from the end of the buffer. See CodeDesc
327 : // for a detailed comment on the layout (globals.h).
328 : //
329 : // If the provided buffer is nullptr, the assembler allocates and grows its
330 : // own buffer. Otherwise it takes ownership of the provided buffer.
331 : explicit Assembler(const AssemblerOptions&,
332 : std::unique_ptr<AssemblerBuffer> = {});
333 82947786 : ~Assembler() override = default;
334 :
335 : // GetCode emits any pending (non-emitted) code and fills the descriptor desc.
336 : static constexpr int kNoHandlerTable = 0;
337 : static constexpr SafepointTableBuilder* kNoSafepointTable = nullptr;
338 : void GetCode(Isolate* isolate, CodeDesc* desc,
339 : SafepointTableBuilder* safepoint_table_builder,
340 : int handler_table_offset);
341 :
342 : // Convenience wrapper for code without safepoint or handler tables.
343 100296 : void GetCode(Isolate* isolate, CodeDesc* desc) {
344 312681 : GetCode(isolate, desc, kNoSafepointTable, kNoHandlerTable);
345 100296 : }
346 :
347 : void FinalizeJumpOptimizationInfo();
348 :
349 : // Unused on this architecture.
350 : void MaybeEmitOutOfLineConstantPool() {}
351 :
352 : // Read/Modify the code target in the relative branch/call instruction at pc.
353 : // On the x64 architecture, we use relative jumps with a 32-bit displacement
354 : // to jump to other Code objects in the Code space in the heap.
355 : // Jumps to C functions are done indirectly through a 64-bit register holding
356 : // the absolute address of the target.
357 : // These functions convert between absolute Addresses of Code objects and
358 : // the relative displacements stored in the code.
359 : // The isolate argument is unused (and may be nullptr) when skipping flushing.
360 : static inline Address target_address_at(Address pc, Address constant_pool);
361 : static inline void set_target_address_at(
362 : Address pc, Address constant_pool, Address target,
363 : ICacheFlushMode icache_flush_mode = FLUSH_ICACHE_IF_NEEDED);
364 :
365 : // Return the code target address at a call site from the return address
366 : // of that call in the instruction stream.
367 : static inline Address target_address_from_return_address(Address pc);
368 :
369 : // This sets the branch destination (which is in the instruction on x64).
370 : // This is for calls and branches within generated code.
371 : inline static void deserialization_set_special_target_at(
372 : Address instruction_payload, Code code, Address target);
373 :
374 : // Get the size of the special target encoded at 'instruction_payload'.
375 : inline static int deserialization_special_target_size(
376 : Address instruction_payload);
377 :
378 : // This sets the internal reference at the pc.
379 : inline static void deserialization_set_target_internal_reference_at(
380 : Address pc, Address target,
381 : RelocInfo::Mode mode = RelocInfo::INTERNAL_REFERENCE);
382 :
383 : inline Handle<Code> code_target_object_handle_at(Address pc);
384 : inline Address runtime_entry_at(Address pc);
385 :
386 : // Number of bytes taken up by the branch target in the code.
387 : static constexpr int kSpecialTargetSize = 4; // 32-bit displacement.
388 : // Distance between the address of the code target in the call instruction
389 : // and the return address pushed on the stack.
390 : static constexpr int kCallTargetAddressOffset = 4; // 32-bit displacement.
391 :
392 : // One byte opcode for test eax,0xXXXXXXXX.
393 : static constexpr byte kTestEaxByte = 0xA9;
394 : // One byte opcode for test al, 0xXX.
395 : static constexpr byte kTestAlByte = 0xA8;
396 : // One byte opcode for nop.
397 : static constexpr byte kNopByte = 0x90;
398 :
399 : // One byte prefix for a short conditional jump.
400 : static constexpr byte kJccShortPrefix = 0x70;
401 : static constexpr byte kJncShortOpcode = kJccShortPrefix | not_carry;
402 : static constexpr byte kJcShortOpcode = kJccShortPrefix | carry;
403 : static constexpr byte kJnzShortOpcode = kJccShortPrefix | not_zero;
404 : static constexpr byte kJzShortOpcode = kJccShortPrefix | zero;
405 :
406 : // VEX prefix encodings.
407 : enum SIMDPrefix { kNone = 0x0, k66 = 0x1, kF3 = 0x2, kF2 = 0x3 };
408 : enum VectorLength { kL128 = 0x0, kL256 = 0x4, kLIG = kL128, kLZ = kL128 };
409 : enum VexW { kW0 = 0x0, kW1 = 0x80, kWIG = kW0 };
410 : enum LeadingOpcode { k0F = 0x1, k0F38 = 0x2, k0F3A = 0x3 };
411 :
412 : // ---------------------------------------------------------------------------
413 : // Code generation
414 : //
415 : // Function names correspond one-to-one to x64 instruction mnemonics.
416 : // Unless specified otherwise, instructions operate on 64-bit operands.
417 : //
418 : // If we need versions of an assembly instruction that operate on different
419 : // width arguments, we add a single-letter suffix specifying the width.
420 : // This is done for the following instructions: mov, cmp, inc, dec,
421 : // add, sub, and test.
422 : // There are no versions of these instructions without the suffix.
423 : // - Instructions on 8-bit (byte) operands/registers have a trailing 'b'.
424 : // - Instructions on 16-bit (word) operands/registers have a trailing 'w'.
425 : // - Instructions on 32-bit (doubleword) operands/registers use 'l'.
426 : // - Instructions on 64-bit (quadword) operands/registers use 'q'.
427 : // - Instructions on operands/registers with pointer size use 'p'.
428 :
429 : #define DECLARE_INSTRUCTION(instruction) \
430 : template <class P1> \
431 : void instruction##_tagged(P1 p1) { \
432 : emit_##instruction(p1, kTaggedSize); \
433 : } \
434 : \
435 : template <class P1> \
436 : void instruction##l(P1 p1) { \
437 : emit_##instruction(p1, kInt32Size); \
438 : } \
439 : \
440 : template <class P1> \
441 : void instruction##q(P1 p1) { \
442 : emit_##instruction(p1, kInt64Size); \
443 : } \
444 : \
445 : template <class P1, class P2> \
446 : void instruction##_tagged(P1 p1, P2 p2) { \
447 : emit_##instruction(p1, p2, kTaggedSize); \
448 : } \
449 : \
450 : template <class P1, class P2> \
451 : void instruction##l(P1 p1, P2 p2) { \
452 : emit_##instruction(p1, p2, kInt32Size); \
453 : } \
454 : \
455 : template <class P1, class P2> \
456 : void instruction##q(P1 p1, P2 p2) { \
457 : emit_##instruction(p1, p2, kInt64Size); \
458 : } \
459 : \
460 : template <class P1, class P2, class P3> \
461 : void instruction##l(P1 p1, P2 p2, P3 p3) { \
462 : emit_##instruction(p1, p2, p3, kInt32Size); \
463 : } \
464 : \
465 : template <class P1, class P2, class P3> \
466 : void instruction##q(P1 p1, P2 p2, P3 p3) { \
467 : emit_##instruction(p1, p2, p3, kInt64Size); \
468 : }
469 136596948 : ASSEMBLER_INSTRUCTION_LIST(DECLARE_INSTRUCTION)
470 : #undef DECLARE_INSTRUCTION
471 :
472 : // Insert the smallest number of nop instructions
473 : // possible to align the pc offset to a multiple
474 : // of m, where m must be a power of 2.
475 : void Align(int m);
476 : // Insert the smallest number of zero bytes possible to align the pc offset
477 : // to a mulitple of m. m must be a power of 2 (>= 2).
478 : void DataAlign(int m);
479 : void Nop(int bytes = 1);
480 : // Aligns code to something that's optimal for a jump target for the platform.
481 : void CodeTargetAlign();
482 :
483 : // Stack
484 : void pushfq();
485 : void popfq();
486 :
487 : void pushq(Immediate value);
488 : // Push a 32 bit integer, and guarantee that it is actually pushed as a
489 : // 32 bit value, the normal push will optimize the 8 bit case.
490 : void pushq_imm32(int32_t imm32);
491 : void pushq(Register src);
492 : void pushq(Operand src);
493 :
494 : void popq(Register dst);
495 : void popq(Operand dst);
496 :
497 : void enter(Immediate size);
498 : void leave();
499 :
500 : // Moves
501 : void movb(Register dst, Operand src);
502 : void movb(Register dst, Immediate imm);
503 : void movb(Operand dst, Register src);
504 : void movb(Operand dst, Immediate imm);
505 :
506 : // Move the low 16 bits of a 64-bit register value to a 16-bit
507 : // memory location.
508 : void movw(Register dst, Operand src);
509 : void movw(Operand dst, Register src);
510 : void movw(Operand dst, Immediate imm);
511 :
512 : // Move the offset of the label location relative to the current
513 : // position (after the move) to the destination.
514 : void movl(Operand dst, Label* src);
515 :
516 : // Load a heap number into a register.
517 : // The heap number will not be allocated and embedded into the code right
518 : // away. Instead, we emit the load of a dummy object. Later, when calling
519 : // Assembler::GetCode, the heap number will be allocated and the code will be
520 : // patched by replacing the dummy with the actual object. The RelocInfo for
521 : // the embedded object gets already recorded correctly when emitting the dummy
522 : // move.
523 : void movq_heap_number(Register dst, double value);
524 :
525 : void movq_string(Register dst, const StringConstantBase* str);
526 :
527 : // Loads a 64-bit immediate into a register.
528 : void movq(Register dst, int64_t value) { movq(dst, Immediate64(value)); }
529 : void movq(Register dst, uint64_t value) {
530 1592138 : movq(dst, Immediate64(static_cast<int64_t>(value)));
531 : }
532 :
533 : void movsxbl(Register dst, Register src);
534 : void movsxbl(Register dst, Operand src);
535 : void movsxbq(Register dst, Register src);
536 : void movsxbq(Register dst, Operand src);
537 : void movsxwl(Register dst, Register src);
538 : void movsxwl(Register dst, Operand src);
539 : void movsxwq(Register dst, Register src);
540 : void movsxwq(Register dst, Operand src);
541 : void movsxlq(Register dst, Register src);
542 : void movsxlq(Register dst, Operand src);
543 :
544 : // Repeated moves.
545 :
546 : void repmovsb();
547 : void repmovsw();
548 : void repmovsl() { emit_repmovs(kInt32Size); }
549 : void repmovsq() { emit_repmovs(kInt64Size); }
550 :
551 : // Instruction to load from an immediate 64-bit pointer into RAX.
552 : void load_rax(Address value, RelocInfo::Mode rmode);
553 : void load_rax(ExternalReference ext);
554 :
555 : // Conditional moves.
556 : void cmovq(Condition cc, Register dst, Register src);
557 : void cmovq(Condition cc, Register dst, Operand src);
558 : void cmovl(Condition cc, Register dst, Register src);
559 : void cmovl(Condition cc, Register dst, Operand src);
560 :
561 336 : void cmpb(Register dst, Immediate src) {
562 7070 : immediate_arithmetic_op_8(0x7, dst, src);
563 336 : }
564 :
565 : void cmpb_al(Immediate src);
566 :
567 : void cmpb(Register dst, Register src) {
568 3358 : arithmetic_op_8(0x3A, dst, src);
569 : }
570 :
571 453 : void cmpb(Register dst, Operand src) { arithmetic_op_8(0x3A, dst, src); }
572 :
573 460 : void cmpb(Operand dst, Register src) { arithmetic_op_8(0x38, src, dst); }
574 :
575 168 : void cmpb(Operand dst, Immediate src) {
576 14791 : immediate_arithmetic_op_8(0x7, dst, src);
577 168 : }
578 :
579 : void cmpw(Operand dst, Immediate src) {
580 223291 : immediate_arithmetic_op_16(0x7, dst, src);
581 : }
582 :
583 : void cmpw(Register dst, Immediate src) {
584 154537 : immediate_arithmetic_op_16(0x7, dst, src);
585 : }
586 :
587 60 : void cmpw(Register dst, Operand src) { arithmetic_op_16(0x3B, dst, src); }
588 :
589 : void cmpw(Register dst, Register src) {
590 448 : arithmetic_op_16(0x3B, dst, src);
591 : }
592 :
593 455 : void cmpw(Operand dst, Register src) { arithmetic_op_16(0x39, src, dst); }
594 :
595 0 : void testb(Register reg, Operand op) { testb(op, reg); }
596 :
597 0 : void testw(Register reg, Operand op) { testw(op, reg); }
598 :
599 : void andb(Register dst, Immediate src) {
600 : immediate_arithmetic_op_8(0x4, dst, src);
601 : }
602 :
603 : void decb(Register dst);
604 : void decb(Operand dst);
605 :
606 : // Lock prefix.
607 : void lock();
608 :
609 : void xchgb(Register reg, Operand op);
610 : void xchgw(Register reg, Operand op);
611 :
612 : void cmpxchgb(Operand dst, Register src);
613 : void cmpxchgw(Operand dst, Register src);
614 :
615 : // Sign-extends rax into rdx:rax.
616 : void cqo();
617 : // Sign-extends eax into edx:eax.
618 : void cdq();
619 :
620 : // Multiply eax by src, put the result in edx:eax.
621 : void mull(Register src);
622 : void mull(Operand src);
623 : // Multiply rax by src, put the result in rdx:rax.
624 : void mulq(Register src);
625 :
626 : #define DECLARE_SHIFT_INSTRUCTION(instruction, subcode) \
627 : void instruction##l(Register dst, Immediate imm8) { \
628 : shift(dst, imm8, subcode, kInt32Size); \
629 : } \
630 : \
631 : void instruction##q(Register dst, Immediate imm8) { \
632 : shift(dst, imm8, subcode, kInt64Size); \
633 : } \
634 : \
635 : void instruction##l(Operand dst, Immediate imm8) { \
636 : shift(dst, imm8, subcode, kInt32Size); \
637 : } \
638 : \
639 : void instruction##q(Operand dst, Immediate imm8) { \
640 : shift(dst, imm8, subcode, kInt64Size); \
641 : } \
642 : \
643 : void instruction##l_cl(Register dst) { shift(dst, subcode, kInt32Size); } \
644 : \
645 : void instruction##q_cl(Register dst) { shift(dst, subcode, kInt64Size); } \
646 : \
647 : void instruction##l_cl(Operand dst) { shift(dst, subcode, kInt32Size); } \
648 : \
649 : void instruction##q_cl(Operand dst) { shift(dst, subcode, kInt64Size); }
650 1434893 : SHIFT_INSTRUCTION_LIST(DECLARE_SHIFT_INSTRUCTION)
651 : #undef DECLARE_SHIFT_INSTRUCTION
652 :
653 : // Shifts dst:src left by cl bits, affecting only dst.
654 : void shld(Register dst, Register src);
655 :
656 : // Shifts src:dst right by cl bits, affecting only dst.
657 : void shrd(Register dst, Register src);
658 :
659 : void store_rax(Address dst, RelocInfo::Mode mode);
660 : void store_rax(ExternalReference ref);
661 :
662 : void subb(Register dst, Immediate src) {
663 2334 : immediate_arithmetic_op_8(0x5, dst, src);
664 : }
665 :
666 : void sub_sp_32(uint32_t imm);
667 :
668 : void testb(Register dst, Register src);
669 : void testb(Register reg, Immediate mask);
670 : void testb(Operand op, Immediate mask);
671 : void testb(Operand op, Register reg);
672 :
673 : void testw(Register dst, Register src);
674 : void testw(Register reg, Immediate mask);
675 : void testw(Operand op, Immediate mask);
676 : void testw(Operand op, Register reg);
677 :
678 : // Bit operations.
679 : void bswapl(Register dst);
680 : void bswapq(Register dst);
681 : void btq(Operand dst, Register src);
682 : void btsq(Operand dst, Register src);
683 : void btsq(Register dst, Immediate imm8);
684 : void btrq(Register dst, Immediate imm8);
685 : void bsrq(Register dst, Register src);
686 : void bsrq(Register dst, Operand src);
687 : void bsrl(Register dst, Register src);
688 : void bsrl(Register dst, Operand src);
689 : void bsfq(Register dst, Register src);
690 : void bsfq(Register dst, Operand src);
691 : void bsfl(Register dst, Register src);
692 : void bsfl(Register dst, Operand src);
693 :
694 : // Miscellaneous
695 : void clc();
696 : void cld();
697 : void cpuid();
698 : void hlt();
699 : void int3();
700 : void nop();
701 : void ret(int imm16);
702 : void ud2();
703 : void setcc(Condition cc, Register reg);
704 :
705 : void pshufw(XMMRegister dst, XMMRegister src, uint8_t shuffle);
706 : void pshufw(XMMRegister dst, Operand src, uint8_t shuffle);
707 : void pblendw(XMMRegister dst, Operand src, uint8_t mask);
708 : void pblendw(XMMRegister dst, XMMRegister src, uint8_t mask);
709 : void palignr(XMMRegister dst, Operand src, uint8_t mask);
710 : void palignr(XMMRegister dst, XMMRegister src, uint8_t mask);
711 :
712 : // Label operations & relative jumps (PPUM Appendix D)
713 : //
714 : // Takes a branch opcode (cc) and a label (L) and generates
715 : // either a backward branch or a forward branch and links it
716 : // to the label fixup chain. Usage:
717 : //
718 : // Label L; // unbound label
719 : // j(cc, &L); // forward branch to unbound label
720 : // bind(&L); // bind label to the current pc
721 : // j(cc, &L); // backward branch to bound label
722 : // bind(&L); // illegal: a label may be bound only once
723 : //
724 : // Note: The same Label can be used for forward and backward branches
725 : // but it may be bound only once.
726 :
727 : void bind(Label* L); // binds an unbound label L to the current code position
728 :
729 : // Calls
730 : // Call near relative 32-bit displacement, relative to next instruction.
731 : void call(Label* L);
732 : void call(Address entry, RelocInfo::Mode rmode);
733 : void near_call(Address entry, RelocInfo::Mode rmode);
734 : void near_jmp(Address entry, RelocInfo::Mode rmode);
735 : void call(Handle<Code> target,
736 : RelocInfo::Mode rmode = RelocInfo::CODE_TARGET);
737 :
738 : // Calls directly to the given address using a relative offset.
739 : // Should only ever be used in Code objects for calls within the
740 : // same Code object. Should not be used when generating new code (use labels),
741 : // but only when patching existing code.
742 : void call(Address target);
743 :
744 : // Call near absolute indirect, address in register
745 : void call(Register adr);
746 :
747 : // Jumps
748 : // Jump short or near relative.
749 : // Use a 32-bit signed displacement.
750 : // Unconditional jump to L
751 : void jmp(Label* L, Label::Distance distance = Label::kFar);
752 : void jmp(Handle<Code> target, RelocInfo::Mode rmode);
753 :
754 : // Jump near absolute indirect (r64)
755 : void jmp(Register adr);
756 : void jmp(Operand src);
757 :
758 : // Conditional jumps
759 : void j(Condition cc,
760 : Label* L,
761 : Label::Distance distance = Label::kFar);
762 : void j(Condition cc, Address entry, RelocInfo::Mode rmode);
763 : void j(Condition cc, Handle<Code> target, RelocInfo::Mode rmode);
764 :
765 : // Floating-point operations
766 : void fld(int i);
767 :
768 : void fld1();
769 : void fldz();
770 : void fldpi();
771 : void fldln2();
772 :
773 : void fld_s(Operand adr);
774 : void fld_d(Operand adr);
775 :
776 : void fstp_s(Operand adr);
777 : void fstp_d(Operand adr);
778 : void fstp(int index);
779 :
780 : void fild_s(Operand adr);
781 : void fild_d(Operand adr);
782 :
783 : void fist_s(Operand adr);
784 :
785 : void fistp_s(Operand adr);
786 : void fistp_d(Operand adr);
787 :
788 : void fisttp_s(Operand adr);
789 : void fisttp_d(Operand adr);
790 :
791 : void fabs();
792 : void fchs();
793 :
794 : void fadd(int i);
795 : void fsub(int i);
796 : void fmul(int i);
797 : void fdiv(int i);
798 :
799 : void fisub_s(Operand adr);
800 :
801 : void faddp(int i = 1);
802 : void fsubp(int i = 1);
803 : void fsubrp(int i = 1);
804 : void fmulp(int i = 1);
805 : void fdivp(int i = 1);
806 : void fprem();
807 : void fprem1();
808 :
809 : void fxch(int i = 1);
810 : void fincstp();
811 : void ffree(int i = 0);
812 :
813 : void ftst();
814 : void fucomp(int i);
815 : void fucompp();
816 : void fucomi(int i);
817 : void fucomip();
818 :
819 : void fcompp();
820 : void fnstsw_ax();
821 : void fwait();
822 : void fnclex();
823 :
824 : void fsin();
825 : void fcos();
826 : void fptan();
827 : void fyl2x();
828 : void f2xm1();
829 : void fscale();
830 : void fninit();
831 :
832 : void frndint();
833 :
834 : void sahf();
835 :
836 : // SSE instructions
837 : void addss(XMMRegister dst, XMMRegister src);
838 : void addss(XMMRegister dst, Operand src);
839 : void subss(XMMRegister dst, XMMRegister src);
840 : void subss(XMMRegister dst, Operand src);
841 : void mulss(XMMRegister dst, XMMRegister src);
842 : void mulss(XMMRegister dst, Operand src);
843 : void divss(XMMRegister dst, XMMRegister src);
844 : void divss(XMMRegister dst, Operand src);
845 :
846 : void maxss(XMMRegister dst, XMMRegister src);
847 : void maxss(XMMRegister dst, Operand src);
848 : void minss(XMMRegister dst, XMMRegister src);
849 : void minss(XMMRegister dst, Operand src);
850 :
851 : void sqrtss(XMMRegister dst, XMMRegister src);
852 : void sqrtss(XMMRegister dst, Operand src);
853 :
854 : void ucomiss(XMMRegister dst, XMMRegister src);
855 : void ucomiss(XMMRegister dst, Operand src);
856 : void movaps(XMMRegister dst, XMMRegister src);
857 :
858 : // Don't use this unless it's important to keep the
859 : // top half of the destination register unchanged.
860 : // Use movaps when moving float values and movd for integer
861 : // values in xmm registers.
862 : void movss(XMMRegister dst, XMMRegister src);
863 :
864 : void movss(XMMRegister dst, Operand src);
865 : void movss(Operand dst, XMMRegister src);
866 : void shufps(XMMRegister dst, XMMRegister src, byte imm8);
867 :
868 : void cvttss2si(Register dst, Operand src);
869 : void cvttss2si(Register dst, XMMRegister src);
870 : void cvtlsi2ss(XMMRegister dst, Operand src);
871 : void cvtlsi2ss(XMMRegister dst, Register src);
872 :
873 : void andps(XMMRegister dst, XMMRegister src);
874 : void andps(XMMRegister dst, Operand src);
875 : void orps(XMMRegister dst, XMMRegister src);
876 : void orps(XMMRegister dst, Operand src);
877 : void xorps(XMMRegister dst, XMMRegister src);
878 : void xorps(XMMRegister dst, Operand src);
879 :
880 : void addps(XMMRegister dst, XMMRegister src);
881 : void addps(XMMRegister dst, Operand src);
882 : void subps(XMMRegister dst, XMMRegister src);
883 : void subps(XMMRegister dst, Operand src);
884 : void mulps(XMMRegister dst, XMMRegister src);
885 : void mulps(XMMRegister dst, Operand src);
886 : void divps(XMMRegister dst, XMMRegister src);
887 : void divps(XMMRegister dst, Operand src);
888 :
889 : void movmskps(Register dst, XMMRegister src);
890 :
891 : void vinstr(byte op, XMMRegister dst, XMMRegister src1, XMMRegister src2,
892 : SIMDPrefix pp, LeadingOpcode m, VexW w);
893 : void vinstr(byte op, XMMRegister dst, XMMRegister src1, Operand src2,
894 : SIMDPrefix pp, LeadingOpcode m, VexW w);
895 :
896 : // SSE2 instructions
897 : void sse2_instr(XMMRegister dst, XMMRegister src, byte prefix, byte escape,
898 : byte opcode);
899 : void sse2_instr(XMMRegister dst, Operand src, byte prefix, byte escape,
900 : byte opcode);
901 : #define DECLARE_SSE2_INSTRUCTION(instruction, prefix, escape, opcode) \
902 : void instruction(XMMRegister dst, XMMRegister src) { \
903 : sse2_instr(dst, src, 0x##prefix, 0x##escape, 0x##opcode); \
904 : } \
905 : void instruction(XMMRegister dst, Operand src) { \
906 : sse2_instr(dst, src, 0x##prefix, 0x##escape, 0x##opcode); \
907 : }
908 :
909 3905 : SSE2_INSTRUCTION_LIST(DECLARE_SSE2_INSTRUCTION)
910 : #undef DECLARE_SSE2_INSTRUCTION
911 :
912 : #define DECLARE_SSE2_AVX_INSTRUCTION(instruction, prefix, escape, opcode) \
913 : void v##instruction(XMMRegister dst, XMMRegister src1, XMMRegister src2) { \
914 : vinstr(0x##opcode, dst, src1, src2, k##prefix, k##escape, kW0); \
915 : } \
916 : void v##instruction(XMMRegister dst, XMMRegister src1, Operand src2) { \
917 : vinstr(0x##opcode, dst, src1, src2, k##prefix, k##escape, kW0); \
918 : }
919 :
920 281031 : SSE2_INSTRUCTION_LIST(DECLARE_SSE2_AVX_INSTRUCTION)
921 : #undef DECLARE_SSE2_AVX_INSTRUCTION
922 :
923 : // SSE3
924 : void lddqu(XMMRegister dst, Operand src);
925 :
926 : // SSSE3
927 : void ssse3_instr(XMMRegister dst, XMMRegister src, byte prefix, byte escape1,
928 : byte escape2, byte opcode);
929 : void ssse3_instr(XMMRegister dst, Operand src, byte prefix, byte escape1,
930 : byte escape2, byte opcode);
931 :
932 : #define DECLARE_SSSE3_INSTRUCTION(instruction, prefix, escape1, escape2, \
933 : opcode) \
934 : void instruction(XMMRegister dst, XMMRegister src) { \
935 : ssse3_instr(dst, src, 0x##prefix, 0x##escape1, 0x##escape2, 0x##opcode); \
936 : } \
937 : void instruction(XMMRegister dst, Operand src) { \
938 : ssse3_instr(dst, src, 0x##prefix, 0x##escape1, 0x##escape2, 0x##opcode); \
939 : }
940 :
941 2566 : SSSE3_INSTRUCTION_LIST(DECLARE_SSSE3_INSTRUCTION)
942 : #undef DECLARE_SSSE3_INSTRUCTION
943 :
944 : // SSE4
945 : void sse4_instr(XMMRegister dst, XMMRegister src, byte prefix, byte escape1,
946 : byte escape2, byte opcode);
947 : void sse4_instr(XMMRegister dst, Operand src, byte prefix, byte escape1,
948 : byte escape2, byte opcode);
949 : #define DECLARE_SSE4_INSTRUCTION(instruction, prefix, escape1, escape2, \
950 : opcode) \
951 : void instruction(XMMRegister dst, XMMRegister src) { \
952 : sse4_instr(dst, src, 0x##prefix, 0x##escape1, 0x##escape2, 0x##opcode); \
953 : } \
954 : void instruction(XMMRegister dst, Operand src) { \
955 : sse4_instr(dst, src, 0x##prefix, 0x##escape1, 0x##escape2, 0x##opcode); \
956 : }
957 :
958 560 : SSE4_INSTRUCTION_LIST(DECLARE_SSE4_INSTRUCTION)
959 : #undef DECLARE_SSE4_INSTRUCTION
960 :
961 : #define DECLARE_SSE34_AVX_INSTRUCTION(instruction, prefix, escape1, escape2, \
962 : opcode) \
963 : void v##instruction(XMMRegister dst, XMMRegister src1, XMMRegister src2) { \
964 : vinstr(0x##opcode, dst, src1, src2, k##prefix, k##escape1##escape2, kW0); \
965 : } \
966 : void v##instruction(XMMRegister dst, XMMRegister src1, Operand src2) { \
967 : vinstr(0x##opcode, dst, src1, src2, k##prefix, k##escape1##escape2, kW0); \
968 : }
969 :
970 90 : SSSE3_INSTRUCTION_LIST(DECLARE_SSE34_AVX_INSTRUCTION)
971 150 : SSE4_INSTRUCTION_LIST(DECLARE_SSE34_AVX_INSTRUCTION)
972 : #undef DECLARE_SSE34_AVX_INSTRUCTION
973 :
974 : void movd(XMMRegister dst, Register src);
975 : void movd(XMMRegister dst, Operand src);
976 : void movd(Register dst, XMMRegister src);
977 : void movq(XMMRegister dst, Register src);
978 : void movq(Register dst, XMMRegister src);
979 : void movq(XMMRegister dst, XMMRegister src);
980 :
981 : // Don't use this unless it's important to keep the
982 : // top half of the destination register unchanged.
983 : // Use movapd when moving double values and movq for integer
984 : // values in xmm registers.
985 : void movsd(XMMRegister dst, XMMRegister src);
986 :
987 : void movsd(Operand dst, XMMRegister src);
988 : void movsd(XMMRegister dst, Operand src);
989 :
990 : void movdqa(Operand dst, XMMRegister src);
991 : void movdqa(XMMRegister dst, Operand src);
992 :
993 : void movdqu(Operand dst, XMMRegister src);
994 : void movdqu(XMMRegister dst, Operand src);
995 :
996 : void movapd(XMMRegister dst, XMMRegister src);
997 : void movupd(XMMRegister dst, Operand src);
998 : void movupd(Operand dst, XMMRegister src);
999 :
1000 : void psllq(XMMRegister reg, byte imm8);
1001 : void psrlq(XMMRegister reg, byte imm8);
1002 : void psllw(XMMRegister reg, byte imm8);
1003 : void pslld(XMMRegister reg, byte imm8);
1004 : void psrlw(XMMRegister reg, byte imm8);
1005 : void psrld(XMMRegister reg, byte imm8);
1006 : void psraw(XMMRegister reg, byte imm8);
1007 : void psrad(XMMRegister reg, byte imm8);
1008 :
1009 : void cvttsd2si(Register dst, Operand src);
1010 : void cvttsd2si(Register dst, XMMRegister src);
1011 : void cvttss2siq(Register dst, XMMRegister src);
1012 : void cvttss2siq(Register dst, Operand src);
1013 : void cvttsd2siq(Register dst, XMMRegister src);
1014 : void cvttsd2siq(Register dst, Operand src);
1015 : void cvttps2dq(XMMRegister dst, Operand src);
1016 : void cvttps2dq(XMMRegister dst, XMMRegister src);
1017 :
1018 : void cvtlsi2sd(XMMRegister dst, Operand src);
1019 : void cvtlsi2sd(XMMRegister dst, Register src);
1020 :
1021 : void cvtqsi2ss(XMMRegister dst, Operand src);
1022 : void cvtqsi2ss(XMMRegister dst, Register src);
1023 :
1024 : void cvtqsi2sd(XMMRegister dst, Operand src);
1025 : void cvtqsi2sd(XMMRegister dst, Register src);
1026 :
1027 :
1028 : void cvtss2sd(XMMRegister dst, XMMRegister src);
1029 : void cvtss2sd(XMMRegister dst, Operand src);
1030 : void cvtsd2ss(XMMRegister dst, XMMRegister src);
1031 : void cvtsd2ss(XMMRegister dst, Operand src);
1032 :
1033 : void cvtsd2si(Register dst, XMMRegister src);
1034 : void cvtsd2siq(Register dst, XMMRegister src);
1035 :
1036 : void addsd(XMMRegister dst, XMMRegister src);
1037 : void addsd(XMMRegister dst, Operand src);
1038 : void subsd(XMMRegister dst, XMMRegister src);
1039 : void subsd(XMMRegister dst, Operand src);
1040 : void mulsd(XMMRegister dst, XMMRegister src);
1041 : void mulsd(XMMRegister dst, Operand src);
1042 : void divsd(XMMRegister dst, XMMRegister src);
1043 : void divsd(XMMRegister dst, Operand src);
1044 :
1045 : void maxsd(XMMRegister dst, XMMRegister src);
1046 : void maxsd(XMMRegister dst, Operand src);
1047 : void minsd(XMMRegister dst, XMMRegister src);
1048 : void minsd(XMMRegister dst, Operand src);
1049 :
1050 : void andpd(XMMRegister dst, XMMRegister src);
1051 : void andpd(XMMRegister dst, Operand src);
1052 : void orpd(XMMRegister dst, XMMRegister src);
1053 : void orpd(XMMRegister dst, Operand src);
1054 : void xorpd(XMMRegister dst, XMMRegister src);
1055 : void xorpd(XMMRegister dst, Operand src);
1056 : void sqrtsd(XMMRegister dst, XMMRegister src);
1057 : void sqrtsd(XMMRegister dst, Operand src);
1058 :
1059 : void haddps(XMMRegister dst, XMMRegister src);
1060 : void haddps(XMMRegister dst, Operand src);
1061 :
1062 : void ucomisd(XMMRegister dst, XMMRegister src);
1063 : void ucomisd(XMMRegister dst, Operand src);
1064 : void cmpltsd(XMMRegister dst, XMMRegister src);
1065 :
1066 : void movmskpd(Register dst, XMMRegister src);
1067 :
1068 : // SSE 4.1 instruction
1069 : void insertps(XMMRegister dst, XMMRegister src, byte imm8);
1070 : void insertps(XMMRegister dst, Operand src, byte imm8);
1071 : void extractps(Register dst, XMMRegister src, byte imm8);
1072 : void pextrb(Register dst, XMMRegister src, int8_t imm8);
1073 : void pextrb(Operand dst, XMMRegister src, int8_t imm8);
1074 : void pextrw(Register dst, XMMRegister src, int8_t imm8);
1075 : void pextrw(Operand dst, XMMRegister src, int8_t imm8);
1076 : void pextrd(Register dst, XMMRegister src, int8_t imm8);
1077 : void pextrd(Operand dst, XMMRegister src, int8_t imm8);
1078 : void pinsrb(XMMRegister dst, Register src, int8_t imm8);
1079 : void pinsrb(XMMRegister dst, Operand src, int8_t imm8);
1080 : void pinsrw(XMMRegister dst, Register src, int8_t imm8);
1081 : void pinsrw(XMMRegister dst, Operand src, int8_t imm8);
1082 : void pinsrd(XMMRegister dst, Register src, int8_t imm8);
1083 : void pinsrd(XMMRegister dst, Operand src, int8_t imm8);
1084 :
1085 : void roundss(XMMRegister dst, XMMRegister src, RoundingMode mode);
1086 : void roundsd(XMMRegister dst, XMMRegister src, RoundingMode mode);
1087 :
1088 : void cmpps(XMMRegister dst, XMMRegister src, int8_t cmp);
1089 : void cmpps(XMMRegister dst, Operand src, int8_t cmp);
1090 : void cmppd(XMMRegister dst, XMMRegister src, int8_t cmp);
1091 : void cmppd(XMMRegister dst, Operand src, int8_t cmp);
1092 :
1093 : #define SSE_CMP_P(instr, imm8) \
1094 : void instr##ps(XMMRegister dst, XMMRegister src) { cmpps(dst, src, imm8); } \
1095 : void instr##ps(XMMRegister dst, Operand src) { cmpps(dst, src, imm8); } \
1096 : void instr##pd(XMMRegister dst, XMMRegister src) { cmppd(dst, src, imm8); } \
1097 : void instr##pd(XMMRegister dst, Operand src) { cmppd(dst, src, imm8); }
1098 :
1099 24 : SSE_CMP_P(cmpeq, 0x0)
1100 28 : SSE_CMP_P(cmplt, 0x1)
1101 32 : SSE_CMP_P(cmple, 0x2)
1102 20 : SSE_CMP_P(cmpneq, 0x4)
1103 20 : SSE_CMP_P(cmpnlt, 0x5)
1104 20 : SSE_CMP_P(cmpnle, 0x6)
1105 :
1106 : #undef SSE_CMP_P
1107 :
1108 : void minps(XMMRegister dst, XMMRegister src);
1109 : void minps(XMMRegister dst, Operand src);
1110 : void maxps(XMMRegister dst, XMMRegister src);
1111 : void maxps(XMMRegister dst, Operand src);
1112 : void rcpps(XMMRegister dst, XMMRegister src);
1113 : void rcpps(XMMRegister dst, Operand src);
1114 : void rsqrtps(XMMRegister dst, XMMRegister src);
1115 : void rsqrtps(XMMRegister dst, Operand src);
1116 : void sqrtps(XMMRegister dst, XMMRegister src);
1117 : void sqrtps(XMMRegister dst, Operand src);
1118 : void movups(XMMRegister dst, XMMRegister src);
1119 : void movups(XMMRegister dst, Operand src);
1120 : void movups(Operand dst, XMMRegister src);
1121 : void psrldq(XMMRegister dst, uint8_t shift);
1122 : void pshufd(XMMRegister dst, XMMRegister src, uint8_t shuffle);
1123 : void pshufd(XMMRegister dst, Operand src, uint8_t shuffle);
1124 : void pshufhw(XMMRegister dst, XMMRegister src, uint8_t shuffle);
1125 : void pshufhw(XMMRegister dst, Operand src, uint8_t shuffle);
1126 : void pshuflw(XMMRegister dst, XMMRegister src, uint8_t shuffle);
1127 : void pshuflw(XMMRegister dst, Operand src, uint8_t shuffle);
1128 : void cvtdq2ps(XMMRegister dst, XMMRegister src);
1129 : void cvtdq2ps(XMMRegister dst, Operand src);
1130 :
1131 : // AVX instruction
1132 : void vfmadd132sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1133 0 : vfmasd(0x99, dst, src1, src2);
1134 : }
1135 : void vfmadd213sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1136 0 : vfmasd(0xa9, dst, src1, src2);
1137 : }
1138 : void vfmadd231sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1139 0 : vfmasd(0xb9, dst, src1, src2);
1140 : }
1141 : void vfmadd132sd(XMMRegister dst, XMMRegister src1, Operand src2) {
1142 0 : vfmasd(0x99, dst, src1, src2);
1143 : }
1144 : void vfmadd213sd(XMMRegister dst, XMMRegister src1, Operand src2) {
1145 0 : vfmasd(0xa9, dst, src1, src2);
1146 : }
1147 : void vfmadd231sd(XMMRegister dst, XMMRegister src1, Operand src2) {
1148 0 : vfmasd(0xb9, dst, src1, src2);
1149 : }
1150 : void vfmsub132sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1151 0 : vfmasd(0x9b, dst, src1, src2);
1152 : }
1153 : void vfmsub213sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1154 0 : vfmasd(0xab, dst, src1, src2);
1155 : }
1156 : void vfmsub231sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1157 0 : vfmasd(0xbb, dst, src1, src2);
1158 : }
1159 : void vfmsub132sd(XMMRegister dst, XMMRegister src1, Operand src2) {
1160 0 : vfmasd(0x9b, dst, src1, src2);
1161 : }
1162 : void vfmsub213sd(XMMRegister dst, XMMRegister src1, Operand src2) {
1163 0 : vfmasd(0xab, dst, src1, src2);
1164 : }
1165 : void vfmsub231sd(XMMRegister dst, XMMRegister src1, Operand src2) {
1166 0 : vfmasd(0xbb, dst, src1, src2);
1167 : }
1168 : void vfnmadd132sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1169 0 : vfmasd(0x9d, dst, src1, src2);
1170 : }
1171 : void vfnmadd213sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1172 0 : vfmasd(0xad, dst, src1, src2);
1173 : }
1174 : void vfnmadd231sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1175 0 : vfmasd(0xbd, dst, src1, src2);
1176 : }
1177 : void vfnmadd132sd(XMMRegister dst, XMMRegister src1, Operand src2) {
1178 0 : vfmasd(0x9d, dst, src1, src2);
1179 : }
1180 : void vfnmadd213sd(XMMRegister dst, XMMRegister src1, Operand src2) {
1181 0 : vfmasd(0xad, dst, src1, src2);
1182 : }
1183 : void vfnmadd231sd(XMMRegister dst, XMMRegister src1, Operand src2) {
1184 0 : vfmasd(0xbd, dst, src1, src2);
1185 : }
1186 : void vfnmsub132sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1187 0 : vfmasd(0x9f, dst, src1, src2);
1188 : }
1189 : void vfnmsub213sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1190 0 : vfmasd(0xaf, dst, src1, src2);
1191 : }
1192 : void vfnmsub231sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1193 0 : vfmasd(0xbf, dst, src1, src2);
1194 : }
1195 : void vfnmsub132sd(XMMRegister dst, XMMRegister src1, Operand src2) {
1196 0 : vfmasd(0x9f, dst, src1, src2);
1197 : }
1198 : void vfnmsub213sd(XMMRegister dst, XMMRegister src1, Operand src2) {
1199 0 : vfmasd(0xaf, dst, src1, src2);
1200 : }
1201 : void vfnmsub231sd(XMMRegister dst, XMMRegister src1, Operand src2) {
1202 0 : vfmasd(0xbf, dst, src1, src2);
1203 : }
1204 : void vfmasd(byte op, XMMRegister dst, XMMRegister src1, XMMRegister src2);
1205 : void vfmasd(byte op, XMMRegister dst, XMMRegister src1, Operand src2);
1206 :
1207 : void vfmadd132ss(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1208 0 : vfmass(0x99, dst, src1, src2);
1209 : }
1210 : void vfmadd213ss(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1211 0 : vfmass(0xa9, dst, src1, src2);
1212 : }
1213 : void vfmadd231ss(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1214 0 : vfmass(0xb9, dst, src1, src2);
1215 : }
1216 : void vfmadd132ss(XMMRegister dst, XMMRegister src1, Operand src2) {
1217 0 : vfmass(0x99, dst, src1, src2);
1218 : }
1219 : void vfmadd213ss(XMMRegister dst, XMMRegister src1, Operand src2) {
1220 0 : vfmass(0xa9, dst, src1, src2);
1221 : }
1222 : void vfmadd231ss(XMMRegister dst, XMMRegister src1, Operand src2) {
1223 0 : vfmass(0xb9, dst, src1, src2);
1224 : }
1225 : void vfmsub132ss(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1226 0 : vfmass(0x9b, dst, src1, src2);
1227 : }
1228 : void vfmsub213ss(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1229 0 : vfmass(0xab, dst, src1, src2);
1230 : }
1231 : void vfmsub231ss(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1232 0 : vfmass(0xbb, dst, src1, src2);
1233 : }
1234 : void vfmsub132ss(XMMRegister dst, XMMRegister src1, Operand src2) {
1235 0 : vfmass(0x9b, dst, src1, src2);
1236 : }
1237 : void vfmsub213ss(XMMRegister dst, XMMRegister src1, Operand src2) {
1238 0 : vfmass(0xab, dst, src1, src2);
1239 : }
1240 : void vfmsub231ss(XMMRegister dst, XMMRegister src1, Operand src2) {
1241 0 : vfmass(0xbb, dst, src1, src2);
1242 : }
1243 : void vfnmadd132ss(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1244 0 : vfmass(0x9d, dst, src1, src2);
1245 : }
1246 : void vfnmadd213ss(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1247 0 : vfmass(0xad, dst, src1, src2);
1248 : }
1249 : void vfnmadd231ss(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1250 0 : vfmass(0xbd, dst, src1, src2);
1251 : }
1252 : void vfnmadd132ss(XMMRegister dst, XMMRegister src1, Operand src2) {
1253 0 : vfmass(0x9d, dst, src1, src2);
1254 : }
1255 : void vfnmadd213ss(XMMRegister dst, XMMRegister src1, Operand src2) {
1256 0 : vfmass(0xad, dst, src1, src2);
1257 : }
1258 : void vfnmadd231ss(XMMRegister dst, XMMRegister src1, Operand src2) {
1259 0 : vfmass(0xbd, dst, src1, src2);
1260 : }
1261 : void vfnmsub132ss(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1262 0 : vfmass(0x9f, dst, src1, src2);
1263 : }
1264 : void vfnmsub213ss(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1265 0 : vfmass(0xaf, dst, src1, src2);
1266 : }
1267 : void vfnmsub231ss(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1268 0 : vfmass(0xbf, dst, src1, src2);
1269 : }
1270 : void vfnmsub132ss(XMMRegister dst, XMMRegister src1, Operand src2) {
1271 0 : vfmass(0x9f, dst, src1, src2);
1272 : }
1273 : void vfnmsub213ss(XMMRegister dst, XMMRegister src1, Operand src2) {
1274 0 : vfmass(0xaf, dst, src1, src2);
1275 : }
1276 : void vfnmsub231ss(XMMRegister dst, XMMRegister src1, Operand src2) {
1277 0 : vfmass(0xbf, dst, src1, src2);
1278 : }
1279 : void vfmass(byte op, XMMRegister dst, XMMRegister src1, XMMRegister src2);
1280 : void vfmass(byte op, XMMRegister dst, XMMRegister src1, Operand src2);
1281 :
1282 : void vmovd(XMMRegister dst, Register src);
1283 : void vmovd(XMMRegister dst, Operand src);
1284 : void vmovd(Register dst, XMMRegister src);
1285 : void vmovq(XMMRegister dst, Register src);
1286 : void vmovq(XMMRegister dst, Operand src);
1287 : void vmovq(Register dst, XMMRegister src);
1288 :
1289 103035 : void vmovsd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1290 : vsd(0x10, dst, src1, src2);
1291 103038 : }
1292 3089091 : void vmovsd(XMMRegister dst, Operand src) { vsd(0x10, dst, xmm0, src); }
1293 2801518 : void vmovsd(Operand dst, XMMRegister src) { vsd(0x11, src, xmm0, dst); }
1294 :
1295 : #define AVX_SP_3(instr, opcode) \
1296 : AVX_S_3(instr, opcode) \
1297 : AVX_P_3(instr, opcode)
1298 :
1299 : #define AVX_S_3(instr, opcode) \
1300 : AVX_3(instr##ss, opcode, vss) \
1301 : AVX_3(instr##sd, opcode, vsd)
1302 :
1303 : #define AVX_P_3(instr, opcode) \
1304 : AVX_3(instr##ps, opcode, vps) \
1305 : AVX_3(instr##pd, opcode, vpd)
1306 :
1307 : #define AVX_3(instr, opcode, impl) \
1308 : void instr(XMMRegister dst, XMMRegister src1, XMMRegister src2) { \
1309 : impl(opcode, dst, src1, src2); \
1310 : } \
1311 : void instr(XMMRegister dst, XMMRegister src1, Operand src2) { \
1312 : impl(opcode, dst, src1, src2); \
1313 : }
1314 :
1315 1280 : AVX_SP_3(vsqrt, 0x51)
1316 163255 : AVX_SP_3(vadd, 0x58)
1317 46822 : AVX_SP_3(vsub, 0x5c)
1318 26229 : AVX_SP_3(vmul, 0x59)
1319 27035 : AVX_SP_3(vdiv, 0x5e)
1320 42 : AVX_SP_3(vmin, 0x5d)
1321 42 : AVX_SP_3(vmax, 0x5f)
1322 784 : AVX_P_3(vand, 0x54)
1323 14 : AVX_P_3(vor, 0x56)
1324 585908 : AVX_P_3(vxor, 0x57)
1325 36021 : AVX_3(vcvtsd2ss, 0x5a, vsd)
1326 20 : AVX_3(vhaddps, 0x7c, vsd)
1327 :
1328 : #undef AVX_3
1329 : #undef AVX_S_3
1330 : #undef AVX_P_3
1331 : #undef AVX_SP_3
1332 :
1333 : void vpsrlq(XMMRegister dst, XMMRegister src, byte imm8) {
1334 189976 : vpd(0x73, xmm2, dst, src);
1335 : emit(imm8);
1336 : }
1337 : void vpsllq(XMMRegister dst, XMMRegister src, byte imm8) {
1338 220614 : vpd(0x73, xmm6, dst, src);
1339 : emit(imm8);
1340 : }
1341 : void vcvtss2sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1342 9188 : vinstr(0x5a, dst, src1, src2, kF3, k0F, kWIG);
1343 : }
1344 : void vcvtss2sd(XMMRegister dst, XMMRegister src1, Operand src2) {
1345 11358 : vinstr(0x5a, dst, src1, src2, kF3, k0F, kWIG);
1346 : }
1347 : void vcvtlsi2sd(XMMRegister dst, XMMRegister src1, Register src2) {
1348 373279 : XMMRegister isrc2 = XMMRegister::from_code(src2.code());
1349 373279 : vinstr(0x2a, dst, src1, isrc2, kF2, k0F, kW0);
1350 : }
1351 : void vcvtlsi2sd(XMMRegister dst, XMMRegister src1, Operand src2) {
1352 57517 : vinstr(0x2a, dst, src1, src2, kF2, k0F, kW0);
1353 : }
1354 : void vcvtlsi2ss(XMMRegister dst, XMMRegister src1, Register src2) {
1355 1122 : XMMRegister isrc2 = XMMRegister::from_code(src2.code());
1356 1122 : vinstr(0x2a, dst, src1, isrc2, kF3, k0F, kW0);
1357 : }
1358 : void vcvtlsi2ss(XMMRegister dst, XMMRegister src1, Operand src2) {
1359 8 : vinstr(0x2a, dst, src1, src2, kF3, k0F, kW0);
1360 : }
1361 : void vcvtqsi2ss(XMMRegister dst, XMMRegister src1, Register src2) {
1362 396 : XMMRegister isrc2 = XMMRegister::from_code(src2.code());
1363 396 : vinstr(0x2a, dst, src1, isrc2, kF3, k0F, kW1);
1364 : }
1365 : void vcvtqsi2ss(XMMRegister dst, XMMRegister src1, Operand src2) {
1366 0 : vinstr(0x2a, dst, src1, src2, kF3, k0F, kW1);
1367 : }
1368 : void vcvtqsi2sd(XMMRegister dst, XMMRegister src1, Register src2) {
1369 20558 : XMMRegister isrc2 = XMMRegister::from_code(src2.code());
1370 20558 : vinstr(0x2a, dst, src1, isrc2, kF2, k0F, kW1);
1371 : }
1372 : void vcvtqsi2sd(XMMRegister dst, XMMRegister src1, Operand src2) {
1373 1981 : vinstr(0x2a, dst, src1, src2, kF2, k0F, kW1);
1374 : }
1375 : void vcvttss2si(Register dst, XMMRegister src) {
1376 460 : XMMRegister idst = XMMRegister::from_code(dst.code());
1377 460 : vinstr(0x2c, idst, xmm0, src, kF3, k0F, kW0);
1378 : }
1379 : void vcvttss2si(Register dst, Operand src) {
1380 0 : XMMRegister idst = XMMRegister::from_code(dst.code());
1381 0 : vinstr(0x2c, idst, xmm0, src, kF3, k0F, kW0);
1382 : }
1383 : void vcvttsd2si(Register dst, XMMRegister src) {
1384 107725 : XMMRegister idst = XMMRegister::from_code(dst.code());
1385 107725 : vinstr(0x2c, idst, xmm0, src, kF2, k0F, kW0);
1386 : }
1387 : void vcvttsd2si(Register dst, Operand src) {
1388 20339 : XMMRegister idst = XMMRegister::from_code(dst.code());
1389 20339 : vinstr(0x2c, idst, xmm0, src, kF2, k0F, kW0);
1390 : }
1391 : void vcvttss2siq(Register dst, XMMRegister src) {
1392 364 : XMMRegister idst = XMMRegister::from_code(dst.code());
1393 364 : vinstr(0x2c, idst, xmm0, src, kF3, k0F, kW1);
1394 : }
1395 : void vcvttss2siq(Register dst, Operand src) {
1396 0 : XMMRegister idst = XMMRegister::from_code(dst.code());
1397 0 : vinstr(0x2c, idst, xmm0, src, kF3, k0F, kW1);
1398 : }
1399 : void vcvttsd2siq(Register dst, XMMRegister src) {
1400 63582 : XMMRegister idst = XMMRegister::from_code(dst.code());
1401 63582 : vinstr(0x2c, idst, xmm0, src, kF2, k0F, kW1);
1402 : }
1403 : void vcvttsd2siq(Register dst, Operand src) {
1404 10 : XMMRegister idst = XMMRegister::from_code(dst.code());
1405 10 : vinstr(0x2c, idst, xmm0, src, kF2, k0F, kW1);
1406 : }
1407 : void vcvtsd2si(Register dst, XMMRegister src) {
1408 9 : XMMRegister idst = XMMRegister::from_code(dst.code());
1409 9 : vinstr(0x2d, idst, xmm0, src, kF2, k0F, kW0);
1410 : }
1411 : void vucomisd(XMMRegister dst, XMMRegister src) {
1412 236897 : vinstr(0x2e, dst, xmm0, src, k66, k0F, kWIG);
1413 : }
1414 : void vucomisd(XMMRegister dst, Operand src) {
1415 20717 : vinstr(0x2e, dst, xmm0, src, k66, k0F, kWIG);
1416 : }
1417 : void vroundss(XMMRegister dst, XMMRegister src1, XMMRegister src2,
1418 : RoundingMode mode) {
1419 583 : vinstr(0x0a, dst, src1, src2, k66, k0F3A, kWIG);
1420 586 : emit(static_cast<byte>(mode) | 0x8); // Mask precision exception.
1421 : }
1422 : void vroundsd(XMMRegister dst, XMMRegister src1, XMMRegister src2,
1423 : RoundingMode mode) {
1424 46193 : vinstr(0x0b, dst, src1, src2, k66, k0F3A, kWIG);
1425 46193 : emit(static_cast<byte>(mode) | 0x8); // Mask precision exception.
1426 : }
1427 :
1428 : void vsd(byte op, XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1429 235683 : vinstr(op, dst, src1, src2, kF2, k0F, kWIG);
1430 : }
1431 243239 : void vsd(byte op, XMMRegister dst, XMMRegister src1, Operand src2) {
1432 3080831 : vinstr(op, dst, src1, src2, kF2, k0F, kWIG);
1433 243239 : }
1434 :
1435 : void vmovss(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1436 96428 : vss(0x10, dst, src1, src2);
1437 : }
1438 25319 : void vmovss(XMMRegister dst, Operand src) { vss(0x10, dst, xmm0, src); }
1439 685626 : void vmovss(Operand dst, XMMRegister src) { vss(0x11, src, xmm0, dst); }
1440 : void vucomiss(XMMRegister dst, XMMRegister src);
1441 : void vucomiss(XMMRegister dst, Operand src);
1442 : void vss(byte op, XMMRegister dst, XMMRegister src1, XMMRegister src2);
1443 : void vss(byte op, XMMRegister dst, XMMRegister src1, Operand src2);
1444 :
1445 362 : void vmovaps(XMMRegister dst, XMMRegister src) { vps(0x28, dst, xmm0, src); }
1446 1757 : void vmovups(XMMRegister dst, XMMRegister src) { vps(0x10, dst, xmm0, src); }
1447 6435 : void vmovups(XMMRegister dst, Operand src) { vps(0x10, dst, xmm0, src); }
1448 10671 : void vmovups(Operand dst, XMMRegister src) { vps(0x11, src, xmm0, dst); }
1449 131517 : void vmovapd(XMMRegister dst, XMMRegister src) { vpd(0x28, dst, xmm0, src); }
1450 5 : void vmovupd(XMMRegister dst, Operand src) { vpd(0x10, dst, xmm0, src); }
1451 5 : void vmovupd(Operand dst, XMMRegister src) { vpd(0x11, src, xmm0, dst); }
1452 : void vmovmskps(Register dst, XMMRegister src) {
1453 192 : XMMRegister idst = XMMRegister::from_code(dst.code());
1454 192 : vps(0x50, idst, xmm0, src);
1455 : }
1456 : void vmovmskpd(Register dst, XMMRegister src) {
1457 665 : XMMRegister idst = XMMRegister::from_code(dst.code());
1458 665 : vpd(0x50, idst, xmm0, src);
1459 : }
1460 : void vcmpps(XMMRegister dst, XMMRegister src1, XMMRegister src2, int8_t cmp) {
1461 35 : vps(0xC2, dst, src1, src2);
1462 : emit(cmp);
1463 : }
1464 : void vcmpps(XMMRegister dst, XMMRegister src1, Operand src2, int8_t cmp) {
1465 35 : vps(0xC2, dst, src1, src2);
1466 : emit(cmp);
1467 : }
1468 : void vcmppd(XMMRegister dst, XMMRegister src1, XMMRegister src2, int8_t cmp) {
1469 35 : vpd(0xC2, dst, src1, src2);
1470 : emit(cmp);
1471 : }
1472 : void vcmppd(XMMRegister dst, XMMRegister src1, Operand src2, int8_t cmp) {
1473 35 : vpd(0xC2, dst, src1, src2);
1474 : emit(cmp);
1475 : }
1476 :
1477 : #define AVX_CMP_P(instr, imm8) \
1478 : void instr##ps(XMMRegister dst, XMMRegister src1, XMMRegister src2) { \
1479 : vcmpps(dst, src1, src2, imm8); \
1480 : } \
1481 : void instr##ps(XMMRegister dst, XMMRegister src1, Operand src2) { \
1482 : vcmpps(dst, src1, src2, imm8); \
1483 : } \
1484 : void instr##pd(XMMRegister dst, XMMRegister src1, XMMRegister src2) { \
1485 : vcmppd(dst, src1, src2, imm8); \
1486 : } \
1487 : void instr##pd(XMMRegister dst, XMMRegister src1, Operand src2) { \
1488 : vcmppd(dst, src1, src2, imm8); \
1489 : }
1490 :
1491 40 : AVX_CMP_P(vcmpeq, 0x0)
1492 40 : AVX_CMP_P(vcmplt, 0x1)
1493 40 : AVX_CMP_P(vcmple, 0x2)
1494 40 : AVX_CMP_P(vcmpneq, 0x4)
1495 40 : AVX_CMP_P(vcmpnlt, 0x5)
1496 40 : AVX_CMP_P(vcmpnle, 0x6)
1497 :
1498 : #undef AVX_CMP_P
1499 :
1500 : void vlddqu(XMMRegister dst, Operand src) {
1501 5 : vinstr(0xF0, dst, xmm0, src, kF2, k0F, kWIG);
1502 : }
1503 : void vpsllw(XMMRegister dst, XMMRegister src, uint8_t imm8) {
1504 5 : vinstr(0x71, xmm6, dst, src, k66, k0F, kWIG);
1505 : emit(imm8);
1506 : }
1507 : void vpsrlw(XMMRegister dst, XMMRegister src, uint8_t imm8) {
1508 5 : vinstr(0x71, xmm2, dst, src, k66, k0F, kWIG);
1509 : emit(imm8);
1510 : }
1511 : void vpsraw(XMMRegister dst, XMMRegister src, uint8_t imm8) {
1512 5 : vinstr(0x71, xmm4, dst, src, k66, k0F, kWIG);
1513 : emit(imm8);
1514 : }
1515 : void vpslld(XMMRegister dst, XMMRegister src, uint8_t imm8) {
1516 49104 : vinstr(0x72, xmm6, dst, src, k66, k0F, kWIG);
1517 : emit(imm8);
1518 : }
1519 : void vpsrld(XMMRegister dst, XMMRegister src, uint8_t imm8) {
1520 37200 : vinstr(0x72, xmm2, dst, src, k66, k0F, kWIG);
1521 : emit(imm8);
1522 : }
1523 : void vpsrad(XMMRegister dst, XMMRegister src, uint8_t imm8) {
1524 5 : vinstr(0x72, xmm4, dst, src, k66, k0F, kWIG);
1525 : emit(imm8);
1526 : }
1527 5 : void vpextrb(Register dst, XMMRegister src, uint8_t imm8) {
1528 5 : XMMRegister idst = XMMRegister::from_code(dst.code());
1529 5 : vinstr(0x14, src, xmm0, idst, k66, k0F3A, kW0);
1530 : emit(imm8);
1531 5 : }
1532 : void vpextrb(Operand dst, XMMRegister src, uint8_t imm8) {
1533 5 : vinstr(0x14, src, xmm0, dst, k66, k0F3A, kW0);
1534 : emit(imm8);
1535 : }
1536 5 : void vpextrw(Register dst, XMMRegister src, uint8_t imm8) {
1537 5 : XMMRegister idst = XMMRegister::from_code(dst.code());
1538 5 : vinstr(0xc5, idst, xmm0, src, k66, k0F, kW0);
1539 : emit(imm8);
1540 5 : }
1541 : void vpextrw(Operand dst, XMMRegister src, uint8_t imm8) {
1542 5 : vinstr(0x15, src, xmm0, dst, k66, k0F3A, kW0);
1543 : emit(imm8);
1544 : }
1545 5 : void vpextrd(Register dst, XMMRegister src, uint8_t imm8) {
1546 5 : XMMRegister idst = XMMRegister::from_code(dst.code());
1547 5 : vinstr(0x16, src, xmm0, idst, k66, k0F3A, kW0);
1548 : emit(imm8);
1549 5 : }
1550 : void vpextrd(Operand dst, XMMRegister src, uint8_t imm8) {
1551 5 : vinstr(0x16, src, xmm0, dst, k66, k0F3A, kW0);
1552 : emit(imm8);
1553 : }
1554 : void vpinsrb(XMMRegister dst, XMMRegister src1, Register src2, uint8_t imm8) {
1555 5 : XMMRegister isrc = XMMRegister::from_code(src2.code());
1556 5 : vinstr(0x20, dst, src1, isrc, k66, k0F3A, kW0);
1557 : emit(imm8);
1558 : }
1559 : void vpinsrb(XMMRegister dst, XMMRegister src1, Operand src2, uint8_t imm8) {
1560 5 : vinstr(0x20, dst, src1, src2, k66, k0F3A, kW0);
1561 : emit(imm8);
1562 : }
1563 : void vpinsrw(XMMRegister dst, XMMRegister src1, Register src2, uint8_t imm8) {
1564 5 : XMMRegister isrc = XMMRegister::from_code(src2.code());
1565 5 : vinstr(0xc4, dst, src1, isrc, k66, k0F, kW0);
1566 : emit(imm8);
1567 : }
1568 : void vpinsrw(XMMRegister dst, XMMRegister src1, Operand src2, uint8_t imm8) {
1569 5 : vinstr(0xc4, dst, src1, src2, k66, k0F, kW0);
1570 : emit(imm8);
1571 : }
1572 : void vpinsrd(XMMRegister dst, XMMRegister src1, Register src2, uint8_t imm8) {
1573 5 : XMMRegister isrc = XMMRegister::from_code(src2.code());
1574 5 : vinstr(0x22, dst, src1, isrc, k66, k0F3A, kW0);
1575 : emit(imm8);
1576 : }
1577 : void vpinsrd(XMMRegister dst, XMMRegister src1, Operand src2, uint8_t imm8) {
1578 5 : vinstr(0x22, dst, src1, src2, k66, k0F3A, kW0);
1579 : emit(imm8);
1580 : }
1581 : void vpshufd(XMMRegister dst, XMMRegister src, uint8_t imm8) {
1582 5 : vinstr(0x70, dst, xmm0, src, k66, k0F, kWIG);
1583 : emit(imm8);
1584 : }
1585 :
1586 : void vps(byte op, XMMRegister dst, XMMRegister src1, XMMRegister src2);
1587 : void vps(byte op, XMMRegister dst, XMMRegister src1, Operand src2);
1588 : void vpd(byte op, XMMRegister dst, XMMRegister src1, XMMRegister src2);
1589 : void vpd(byte op, XMMRegister dst, XMMRegister src1, Operand src2);
1590 :
1591 : // BMI instruction
1592 : void andnq(Register dst, Register src1, Register src2) {
1593 0 : bmi1q(0xf2, dst, src1, src2);
1594 : }
1595 : void andnq(Register dst, Register src1, Operand src2) {
1596 0 : bmi1q(0xf2, dst, src1, src2);
1597 : }
1598 : void andnl(Register dst, Register src1, Register src2) {
1599 0 : bmi1l(0xf2, dst, src1, src2);
1600 : }
1601 : void andnl(Register dst, Register src1, Operand src2) {
1602 0 : bmi1l(0xf2, dst, src1, src2);
1603 : }
1604 : void bextrq(Register dst, Register src1, Register src2) {
1605 0 : bmi1q(0xf7, dst, src2, src1);
1606 : }
1607 : void bextrq(Register dst, Operand src1, Register src2) {
1608 0 : bmi1q(0xf7, dst, src2, src1);
1609 : }
1610 : void bextrl(Register dst, Register src1, Register src2) {
1611 0 : bmi1l(0xf7, dst, src2, src1);
1612 : }
1613 : void bextrl(Register dst, Operand src1, Register src2) {
1614 0 : bmi1l(0xf7, dst, src2, src1);
1615 : }
1616 0 : void blsiq(Register dst, Register src) { bmi1q(0xf3, rbx, dst, src); }
1617 0 : void blsiq(Register dst, Operand src) { bmi1q(0xf3, rbx, dst, src); }
1618 0 : void blsil(Register dst, Register src) { bmi1l(0xf3, rbx, dst, src); }
1619 0 : void blsil(Register dst, Operand src) { bmi1l(0xf3, rbx, dst, src); }
1620 0 : void blsmskq(Register dst, Register src) { bmi1q(0xf3, rdx, dst, src); }
1621 0 : void blsmskq(Register dst, Operand src) { bmi1q(0xf3, rdx, dst, src); }
1622 0 : void blsmskl(Register dst, Register src) { bmi1l(0xf3, rdx, dst, src); }
1623 0 : void blsmskl(Register dst, Operand src) { bmi1l(0xf3, rdx, dst, src); }
1624 0 : void blsrq(Register dst, Register src) { bmi1q(0xf3, rcx, dst, src); }
1625 0 : void blsrq(Register dst, Operand src) { bmi1q(0xf3, rcx, dst, src); }
1626 0 : void blsrl(Register dst, Register src) { bmi1l(0xf3, rcx, dst, src); }
1627 0 : void blsrl(Register dst, Operand src) { bmi1l(0xf3, rcx, dst, src); }
1628 : void tzcntq(Register dst, Register src);
1629 : void tzcntq(Register dst, Operand src);
1630 : void tzcntl(Register dst, Register src);
1631 : void tzcntl(Register dst, Operand src);
1632 :
1633 : void lzcntq(Register dst, Register src);
1634 : void lzcntq(Register dst, Operand src);
1635 : void lzcntl(Register dst, Register src);
1636 : void lzcntl(Register dst, Operand src);
1637 :
1638 : void popcntq(Register dst, Register src);
1639 : void popcntq(Register dst, Operand src);
1640 : void popcntl(Register dst, Register src);
1641 : void popcntl(Register dst, Operand src);
1642 :
1643 : void bzhiq(Register dst, Register src1, Register src2) {
1644 0 : bmi2q(kNone, 0xf5, dst, src2, src1);
1645 : }
1646 : void bzhiq(Register dst, Operand src1, Register src2) {
1647 0 : bmi2q(kNone, 0xf5, dst, src2, src1);
1648 : }
1649 : void bzhil(Register dst, Register src1, Register src2) {
1650 0 : bmi2l(kNone, 0xf5, dst, src2, src1);
1651 : }
1652 : void bzhil(Register dst, Operand src1, Register src2) {
1653 0 : bmi2l(kNone, 0xf5, dst, src2, src1);
1654 : }
1655 : void mulxq(Register dst1, Register dst2, Register src) {
1656 0 : bmi2q(kF2, 0xf6, dst1, dst2, src);
1657 : }
1658 : void mulxq(Register dst1, Register dst2, Operand src) {
1659 0 : bmi2q(kF2, 0xf6, dst1, dst2, src);
1660 : }
1661 : void mulxl(Register dst1, Register dst2, Register src) {
1662 0 : bmi2l(kF2, 0xf6, dst1, dst2, src);
1663 : }
1664 : void mulxl(Register dst1, Register dst2, Operand src) {
1665 0 : bmi2l(kF2, 0xf6, dst1, dst2, src);
1666 : }
1667 : void pdepq(Register dst, Register src1, Register src2) {
1668 0 : bmi2q(kF2, 0xf5, dst, src1, src2);
1669 : }
1670 : void pdepq(Register dst, Register src1, Operand src2) {
1671 0 : bmi2q(kF2, 0xf5, dst, src1, src2);
1672 : }
1673 : void pdepl(Register dst, Register src1, Register src2) {
1674 0 : bmi2l(kF2, 0xf5, dst, src1, src2);
1675 : }
1676 : void pdepl(Register dst, Register src1, Operand src2) {
1677 0 : bmi2l(kF2, 0xf5, dst, src1, src2);
1678 : }
1679 : void pextq(Register dst, Register src1, Register src2) {
1680 0 : bmi2q(kF3, 0xf5, dst, src1, src2);
1681 : }
1682 : void pextq(Register dst, Register src1, Operand src2) {
1683 0 : bmi2q(kF3, 0xf5, dst, src1, src2);
1684 : }
1685 : void pextl(Register dst, Register src1, Register src2) {
1686 0 : bmi2l(kF3, 0xf5, dst, src1, src2);
1687 : }
1688 : void pextl(Register dst, Register src1, Operand src2) {
1689 0 : bmi2l(kF3, 0xf5, dst, src1, src2);
1690 : }
1691 : void sarxq(Register dst, Register src1, Register src2) {
1692 0 : bmi2q(kF3, 0xf7, dst, src2, src1);
1693 : }
1694 : void sarxq(Register dst, Operand src1, Register src2) {
1695 0 : bmi2q(kF3, 0xf7, dst, src2, src1);
1696 : }
1697 : void sarxl(Register dst, Register src1, Register src2) {
1698 0 : bmi2l(kF3, 0xf7, dst, src2, src1);
1699 : }
1700 : void sarxl(Register dst, Operand src1, Register src2) {
1701 0 : bmi2l(kF3, 0xf7, dst, src2, src1);
1702 : }
1703 : void shlxq(Register dst, Register src1, Register src2) {
1704 0 : bmi2q(k66, 0xf7, dst, src2, src1);
1705 : }
1706 : void shlxq(Register dst, Operand src1, Register src2) {
1707 0 : bmi2q(k66, 0xf7, dst, src2, src1);
1708 : }
1709 : void shlxl(Register dst, Register src1, Register src2) {
1710 0 : bmi2l(k66, 0xf7, dst, src2, src1);
1711 : }
1712 : void shlxl(Register dst, Operand src1, Register src2) {
1713 0 : bmi2l(k66, 0xf7, dst, src2, src1);
1714 : }
1715 : void shrxq(Register dst, Register src1, Register src2) {
1716 0 : bmi2q(kF2, 0xf7, dst, src2, src1);
1717 : }
1718 : void shrxq(Register dst, Operand src1, Register src2) {
1719 0 : bmi2q(kF2, 0xf7, dst, src2, src1);
1720 : }
1721 : void shrxl(Register dst, Register src1, Register src2) {
1722 0 : bmi2l(kF2, 0xf7, dst, src2, src1);
1723 : }
1724 : void shrxl(Register dst, Operand src1, Register src2) {
1725 0 : bmi2l(kF2, 0xf7, dst, src2, src1);
1726 : }
1727 : void rorxq(Register dst, Register src, byte imm8);
1728 : void rorxq(Register dst, Operand src, byte imm8);
1729 : void rorxl(Register dst, Register src, byte imm8);
1730 : void rorxl(Register dst, Operand src, byte imm8);
1731 :
1732 : void lfence();
1733 : void pause();
1734 :
1735 : // Check the code size generated from label to here.
1736 : int SizeOfCodeGeneratedSince(Label* label) {
1737 : return pc_offset() - label->pos();
1738 : }
1739 :
1740 : // Record a deoptimization reason that can be used by a log or cpu profiler.
1741 : // Use --trace-deopt to enable.
1742 : void RecordDeoptReason(DeoptimizeReason reason, SourcePosition position,
1743 : int id);
1744 :
1745 :
1746 : // Writes a single word of data in the code stream.
1747 : // Used for inline tables, e.g., jump-tables.
1748 : void db(uint8_t data);
1749 : void dd(uint32_t data);
1750 : void dq(uint64_t data);
1751 : void dp(uintptr_t data) { dq(data); }
1752 : void dq(Label* label);
1753 :
1754 : // Patch entries for partial constant pool.
1755 : void PatchConstPool();
1756 :
1757 : // Check if use partial constant pool for this rmode.
1758 : static bool UseConstPoolFor(RelocInfo::Mode rmode);
1759 :
1760 : // Check if there is less than kGap bytes available in the buffer.
1761 : // If this is the case, we need to grow the buffer before emitting
1762 : // an instruction or relocation information.
1763 : inline bool buffer_overflow() const {
1764 373973681 : return pc_ >= reloc_info_writer.pos() - kGap;
1765 : }
1766 :
1767 : // Get the number of bytes available in the buffer.
1768 : inline int available_space() const {
1769 : return static_cast<int>(reloc_info_writer.pos() - pc_);
1770 : }
1771 :
1772 : static bool IsNop(Address addr);
1773 :
1774 : // Avoid overflows for displacements etc.
1775 : static constexpr int kMaximalBufferSize = 512 * MB;
1776 :
1777 : byte byte_at(int pos) { return buffer_start_[pos]; }
1778 1758003 : void set_byte_at(int pos, byte value) { buffer_start_[pos] = value; }
1779 :
1780 : protected:
1781 : // Call near indirect
1782 : void call(Operand operand);
1783 :
1784 : private:
1785 : Address addr_at(int pos) {
1786 62772883 : return reinterpret_cast<Address>(buffer_start_ + pos);
1787 : }
1788 : uint32_t long_at(int pos) {
1789 : return ReadUnalignedValue<uint32_t>(addr_at(pos));
1790 : }
1791 : void long_at_put(int pos, uint32_t x) {
1792 : WriteUnalignedValue(addr_at(pos), x);
1793 : }
1794 :
1795 : // code emission
1796 : void GrowBuffer();
1797 :
1798 529957900 : void emit(byte x) { *pc_++ = x; }
1799 : inline void emitl(uint32_t x);
1800 : inline void emitq(uint64_t x);
1801 : inline void emitw(uint16_t x);
1802 : inline void emit_runtime_entry(Address entry, RelocInfo::Mode rmode);
1803 : inline void emit(Immediate x);
1804 : inline void emit(Immediate64 x);
1805 :
1806 : // Emits a REX prefix that encodes a 64-bit operand size and
1807 : // the top bit of both register codes.
1808 : // High bit of reg goes to REX.R, high bit of rm_reg goes to REX.B.
1809 : // REX.W is set.
1810 : inline void emit_rex_64(XMMRegister reg, Register rm_reg);
1811 : inline void emit_rex_64(Register reg, XMMRegister rm_reg);
1812 : inline void emit_rex_64(Register reg, Register rm_reg);
1813 : inline void emit_rex_64(XMMRegister reg, XMMRegister rm_reg);
1814 :
1815 : // Emits a REX prefix that encodes a 64-bit operand size and
1816 : // the top bit of the destination, index, and base register codes.
1817 : // The high bit of reg is used for REX.R, the high bit of op's base
1818 : // register is used for REX.B, and the high bit of op's index register
1819 : // is used for REX.X. REX.W is set.
1820 : inline void emit_rex_64(Register reg, Operand op);
1821 : inline void emit_rex_64(XMMRegister reg, Operand op);
1822 :
1823 : // Emits a REX prefix that encodes a 64-bit operand size and
1824 : // the top bit of the register code.
1825 : // The high bit of register is used for REX.B.
1826 : // REX.W is set and REX.R and REX.X are clear.
1827 : inline void emit_rex_64(Register rm_reg);
1828 :
1829 : // Emits a REX prefix that encodes a 64-bit operand size and
1830 : // the top bit of the index and base register codes.
1831 : // The high bit of op's base register is used for REX.B, and the high
1832 : // bit of op's index register is used for REX.X.
1833 : // REX.W is set and REX.R clear.
1834 : inline void emit_rex_64(Operand op);
1835 :
1836 : // Emit a REX prefix that only sets REX.W to choose a 64-bit operand size.
1837 : void emit_rex_64() { emit(0x48); }
1838 :
1839 : // High bit of reg goes to REX.R, high bit of rm_reg goes to REX.B.
1840 : // REX.W is clear.
1841 : inline void emit_rex_32(Register reg, Register rm_reg);
1842 :
1843 : // The high bit of reg is used for REX.R, the high bit of op's base
1844 : // register is used for REX.B, and the high bit of op's index register
1845 : // is used for REX.X. REX.W is cleared.
1846 : inline void emit_rex_32(Register reg, Operand op);
1847 :
1848 : // High bit of rm_reg goes to REX.B.
1849 : // REX.W, REX.R and REX.X are clear.
1850 : inline void emit_rex_32(Register rm_reg);
1851 :
1852 : // High bit of base goes to REX.B and high bit of index to REX.X.
1853 : // REX.W and REX.R are clear.
1854 : inline void emit_rex_32(Operand op);
1855 :
1856 : // High bit of reg goes to REX.R, high bit of rm_reg goes to REX.B.
1857 : // REX.W is cleared. If no REX bits are set, no byte is emitted.
1858 : inline void emit_optional_rex_32(Register reg, Register rm_reg);
1859 :
1860 : // The high bit of reg is used for REX.R, the high bit of op's base
1861 : // register is used for REX.B, and the high bit of op's index register
1862 : // is used for REX.X. REX.W is cleared. If no REX bits are set, nothing
1863 : // is emitted.
1864 : inline void emit_optional_rex_32(Register reg, Operand op);
1865 :
1866 : // As for emit_optional_rex_32(Register, Register), except that
1867 : // the registers are XMM registers.
1868 : inline void emit_optional_rex_32(XMMRegister reg, XMMRegister base);
1869 :
1870 : // As for emit_optional_rex_32(Register, Register), except that
1871 : // one of the registers is an XMM registers.
1872 : inline void emit_optional_rex_32(XMMRegister reg, Register base);
1873 :
1874 : // As for emit_optional_rex_32(Register, Register), except that
1875 : // one of the registers is an XMM registers.
1876 : inline void emit_optional_rex_32(Register reg, XMMRegister base);
1877 :
1878 : // As for emit_optional_rex_32(Register, Operand), except that
1879 : // the register is an XMM register.
1880 : inline void emit_optional_rex_32(XMMRegister reg, Operand op);
1881 :
1882 : // Optionally do as emit_rex_32(Register) if the register number has
1883 : // the high bit set.
1884 : inline void emit_optional_rex_32(Register rm_reg);
1885 : inline void emit_optional_rex_32(XMMRegister rm_reg);
1886 :
1887 : // Optionally do as emit_rex_32(Operand) if the operand register
1888 : // numbers have a high bit set.
1889 : inline void emit_optional_rex_32(Operand op);
1890 :
1891 : void emit_rex(int size) {
1892 0 : if (size == kInt64Size) {
1893 : emit_rex_64();
1894 : } else {
1895 : DCHECK_EQ(size, kInt32Size);
1896 : }
1897 : }
1898 :
1899 : template<class P1>
1900 : void emit_rex(P1 p1, int size) {
1901 79618593 : if (size == kInt64Size) {
1902 : emit_rex_64(p1);
1903 : } else {
1904 : DCHECK_EQ(size, kInt32Size);
1905 : emit_optional_rex_32(p1);
1906 : }
1907 : }
1908 :
1909 : template<class P1, class P2>
1910 33787533 : void emit_rex(P1 p1, P2 p2, int size) {
1911 79786612 : if (size == kInt64Size) {
1912 : emit_rex_64(p1, p2);
1913 : } else {
1914 : DCHECK_EQ(size, kInt32Size);
1915 : emit_optional_rex_32(p1, p2);
1916 : }
1917 33787533 : }
1918 :
1919 : // Emit vex prefix
1920 : void emit_vex2_byte0() { emit(0xc5); }
1921 : inline void emit_vex2_byte1(XMMRegister reg, XMMRegister v, VectorLength l,
1922 : SIMDPrefix pp);
1923 : void emit_vex3_byte0() { emit(0xc4); }
1924 : inline void emit_vex3_byte1(XMMRegister reg, XMMRegister rm, LeadingOpcode m);
1925 : inline void emit_vex3_byte1(XMMRegister reg, Operand rm, LeadingOpcode m);
1926 : inline void emit_vex3_byte2(VexW w, XMMRegister v, VectorLength l,
1927 : SIMDPrefix pp);
1928 : inline void emit_vex_prefix(XMMRegister reg, XMMRegister v, XMMRegister rm,
1929 : VectorLength l, SIMDPrefix pp, LeadingOpcode m,
1930 : VexW w);
1931 : inline void emit_vex_prefix(Register reg, Register v, Register rm,
1932 : VectorLength l, SIMDPrefix pp, LeadingOpcode m,
1933 : VexW w);
1934 : inline void emit_vex_prefix(XMMRegister reg, XMMRegister v, Operand rm,
1935 : VectorLength l, SIMDPrefix pp, LeadingOpcode m,
1936 : VexW w);
1937 : inline void emit_vex_prefix(Register reg, Register v, Operand rm,
1938 : VectorLength l, SIMDPrefix pp, LeadingOpcode m,
1939 : VexW w);
1940 :
1941 : // Emit the ModR/M byte, and optionally the SIB byte and
1942 : // 1- or 4-byte offset for a memory operand. Also encodes
1943 : // the second operand of the operation, a register or operation
1944 : // subcode, into the reg field of the ModR/M byte.
1945 : void emit_operand(Register reg, Operand adr) {
1946 56978105 : emit_operand(reg.low_bits(), adr);
1947 : }
1948 :
1949 : // Emit the ModR/M byte, and optionally the SIB byte and
1950 : // 1- or 4-byte offset for a memory operand. Also used to encode
1951 : // a three-bit opcode extension into the ModR/M byte.
1952 : void emit_operand(int rm, Operand adr);
1953 :
1954 : // Emit a ModR/M byte with registers coded in the reg and rm_reg fields.
1955 : void emit_modrm(Register reg, Register rm_reg) {
1956 41467615 : emit(0xC0 | reg.low_bits() << 3 | rm_reg.low_bits());
1957 : }
1958 :
1959 : // Emit a ModR/M byte with an operation subcode in the reg field and
1960 : // a register in the rm_reg field.
1961 : void emit_modrm(int code, Register rm_reg) {
1962 : DCHECK(is_uint3(code));
1963 83518311 : emit(0xC0 | code << 3 | rm_reg.low_bits());
1964 : }
1965 :
1966 : // Emit the code-object-relative offset of the label's position
1967 : inline void emit_code_relative_offset(Label* label);
1968 :
1969 : // The first argument is the reg field, the second argument is the r/m field.
1970 : void emit_sse_operand(XMMRegister dst, XMMRegister src);
1971 : void emit_sse_operand(XMMRegister reg, Operand adr);
1972 : void emit_sse_operand(Register reg, Operand adr);
1973 : void emit_sse_operand(XMMRegister dst, Register src);
1974 : void emit_sse_operand(Register dst, XMMRegister src);
1975 : void emit_sse_operand(XMMRegister dst);
1976 :
1977 : // Emit machine code for one of the operations ADD, ADC, SUB, SBC,
1978 : // AND, OR, XOR, or CMP. The encodings of these operations are all
1979 : // similar, differing just in the opcode or in the reg field of the
1980 : // ModR/M byte.
1981 : void arithmetic_op_8(byte opcode, Register reg, Register rm_reg);
1982 : void arithmetic_op_8(byte opcode, Register reg, Operand rm_reg);
1983 : void arithmetic_op_16(byte opcode, Register reg, Register rm_reg);
1984 : void arithmetic_op_16(byte opcode, Register reg, Operand rm_reg);
1985 : // Operate on operands/registers with pointer size, 32-bit or 64-bit size.
1986 : void arithmetic_op(byte opcode, Register reg, Register rm_reg, int size);
1987 : void arithmetic_op(byte opcode, Register reg, Operand rm_reg, int size);
1988 : // Operate on a byte in memory or register.
1989 : void immediate_arithmetic_op_8(byte subcode,
1990 : Register dst,
1991 : Immediate src);
1992 : void immediate_arithmetic_op_8(byte subcode, Operand dst, Immediate src);
1993 : // Operate on a word in memory or register.
1994 : void immediate_arithmetic_op_16(byte subcode,
1995 : Register dst,
1996 : Immediate src);
1997 : void immediate_arithmetic_op_16(byte subcode, Operand dst, Immediate src);
1998 : // Operate on operands/registers with pointer size, 32-bit or 64-bit size.
1999 : void immediate_arithmetic_op(byte subcode,
2000 : Register dst,
2001 : Immediate src,
2002 : int size);
2003 : void immediate_arithmetic_op(byte subcode, Operand dst, Immediate src,
2004 : int size);
2005 :
2006 : // Emit machine code for a shift operation.
2007 : void shift(Operand dst, Immediate shift_amount, int subcode, int size);
2008 : void shift(Register dst, Immediate shift_amount, int subcode, int size);
2009 : // Shift dst by cl % 64 bits.
2010 : void shift(Register dst, int subcode, int size);
2011 : void shift(Operand dst, int subcode, int size);
2012 :
2013 : void emit_farith(int b1, int b2, int i);
2014 :
2015 : // labels
2016 : // void print(Label* L);
2017 : void bind_to(Label* L, int pos);
2018 :
2019 : // record reloc info for current pc_
2020 : void RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data = 0);
2021 :
2022 : // Arithmetics
2023 784 : void emit_add(Register dst, Register src, int size) {
2024 6172799 : arithmetic_op(0x03, dst, src, size);
2025 784 : }
2026 :
2027 840 : void emit_add(Register dst, Immediate src, int size) {
2028 2239332 : immediate_arithmetic_op(0x0, dst, src, size);
2029 840 : }
2030 :
2031 244 : void emit_add(Register dst, Operand src, int size) {
2032 6853 : arithmetic_op(0x03, dst, src, size);
2033 244 : }
2034 :
2035 : void emit_add(Operand dst, Register src, int size) {
2036 164146 : arithmetic_op(0x1, src, dst, size);
2037 : }
2038 :
2039 336 : void emit_add(Operand dst, Immediate src, int size) {
2040 6476 : immediate_arithmetic_op(0x0, dst, src, size);
2041 336 : }
2042 :
2043 : void emit_and(Register dst, Register src, int size) {
2044 3762505 : arithmetic_op(0x23, dst, src, size);
2045 : }
2046 :
2047 : void emit_and(Register dst, Operand src, int size) {
2048 3880 : arithmetic_op(0x23, dst, src, size);
2049 : }
2050 :
2051 : void emit_and(Operand dst, Register src, int size) {
2052 : arithmetic_op(0x21, src, dst, size);
2053 : }
2054 :
2055 112 : void emit_and(Register dst, Immediate src, int size) {
2056 4063151 : immediate_arithmetic_op(0x4, dst, src, size);
2057 112 : }
2058 :
2059 : void emit_and(Operand dst, Immediate src, int size) {
2060 0 : immediate_arithmetic_op(0x4, dst, src, size);
2061 : }
2062 :
2063 2016 : void emit_cmp(Register dst, Register src, int size) {
2064 2023297 : arithmetic_op(0x3B, dst, src, size);
2065 2016 : }
2066 :
2067 168 : void emit_cmp(Register dst, Operand src, int size) {
2068 860103 : arithmetic_op(0x3B, dst, src, size);
2069 168 : }
2070 :
2071 : void emit_cmp(Operand dst, Register src, int size) {
2072 1402406 : arithmetic_op(0x39, src, dst, size);
2073 : }
2074 :
2075 784 : void emit_cmp(Register dst, Immediate src, int size) {
2076 2931298 : immediate_arithmetic_op(0x7, dst, src, size);
2077 784 : }
2078 :
2079 34059 : void emit_cmp(Operand dst, Immediate src, int size) {
2080 159213 : immediate_arithmetic_op(0x7, dst, src, size);
2081 34059 : }
2082 :
2083 : // Compare {al,ax,eax,rax} with src. If equal, set ZF and write dst into
2084 : // src. Otherwise clear ZF and write src into {al,ax,eax,rax}. This
2085 : // operation is only atomic if prefixed by the lock instruction.
2086 : void emit_cmpxchg(Operand dst, Register src, int size);
2087 :
2088 : void emit_dec(Register dst, int size);
2089 : void emit_dec(Operand dst, int size);
2090 :
2091 : // Divide rdx:rax by src. Quotient in rax, remainder in rdx when size is 64.
2092 : // Divide edx:eax by lower 32 bits of src. Quotient in eax, remainder in edx
2093 : // when size is 32.
2094 : void emit_idiv(Register src, int size);
2095 : void emit_div(Register src, int size);
2096 :
2097 : // Signed multiply instructions.
2098 : // rdx:rax = rax * src when size is 64 or edx:eax = eax * src when size is 32.
2099 : void emit_imul(Register src, int size);
2100 : void emit_imul(Operand src, int size);
2101 : void emit_imul(Register dst, Register src, int size);
2102 : void emit_imul(Register dst, Operand src, int size);
2103 : void emit_imul(Register dst, Register src, Immediate imm, int size);
2104 : void emit_imul(Register dst, Operand src, Immediate imm, int size);
2105 :
2106 : void emit_inc(Register dst, int size);
2107 : void emit_inc(Operand dst, int size);
2108 :
2109 : void emit_lea(Register dst, Operand src, int size);
2110 :
2111 : void emit_mov(Register dst, Operand src, int size);
2112 : void emit_mov(Register dst, Register src, int size);
2113 : void emit_mov(Operand dst, Register src, int size);
2114 : void emit_mov(Register dst, Immediate value, int size);
2115 : void emit_mov(Operand dst, Immediate value, int size);
2116 : void emit_mov(Register dst, Immediate64 value, int size);
2117 :
2118 : void emit_movzxb(Register dst, Operand src, int size);
2119 : void emit_movzxb(Register dst, Register src, int size);
2120 : void emit_movzxw(Register dst, Operand src, int size);
2121 : void emit_movzxw(Register dst, Register src, int size);
2122 :
2123 : void emit_neg(Register dst, int size);
2124 : void emit_neg(Operand dst, int size);
2125 :
2126 : void emit_not(Register dst, int size);
2127 : void emit_not(Operand dst, int size);
2128 :
2129 : void emit_or(Register dst, Register src, int size) {
2130 130508 : arithmetic_op(0x0B, dst, src, size);
2131 : }
2132 :
2133 : void emit_or(Register dst, Operand src, int size) {
2134 924 : arithmetic_op(0x0B, dst, src, size);
2135 : }
2136 :
2137 : void emit_or(Operand dst, Register src, int size) {
2138 4 : arithmetic_op(0x9, src, dst, size);
2139 : }
2140 :
2141 : void emit_or(Register dst, Immediate src, int size) {
2142 72271 : immediate_arithmetic_op(0x1, dst, src, size);
2143 : }
2144 :
2145 : void emit_or(Operand dst, Immediate src, int size) {
2146 0 : immediate_arithmetic_op(0x1, dst, src, size);
2147 : }
2148 :
2149 : void emit_repmovs(int size);
2150 :
2151 : void emit_sbb(Register dst, Register src, int size) {
2152 5 : arithmetic_op(0x1b, dst, src, size);
2153 : }
2154 :
2155 1344 : void emit_sub(Register dst, Register src, int size) {
2156 211682 : arithmetic_op(0x2B, dst, src, size);
2157 1344 : }
2158 :
2159 784 : void emit_sub(Register dst, Immediate src, int size) {
2160 4029052 : immediate_arithmetic_op(0x5, dst, src, size);
2161 784 : }
2162 :
2163 : void emit_sub(Register dst, Operand src, int size) {
2164 170469 : arithmetic_op(0x2B, dst, src, size);
2165 : }
2166 :
2167 : void emit_sub(Operand dst, Register src, int size) {
2168 164150 : arithmetic_op(0x29, src, dst, size);
2169 : }
2170 :
2171 112 : void emit_sub(Operand dst, Immediate src, int size) {
2172 117 : immediate_arithmetic_op(0x5, dst, src, size);
2173 112 : }
2174 :
2175 : void emit_test(Register dst, Register src, int size);
2176 : void emit_test(Register reg, Immediate mask, int size);
2177 : void emit_test(Operand op, Register reg, int size);
2178 : void emit_test(Operand op, Immediate mask, int size);
2179 : void emit_test(Register reg, Operand op, int size) {
2180 28 : return emit_test(op, reg, size);
2181 : }
2182 :
2183 : void emit_xchg(Register dst, Register src, int size);
2184 : void emit_xchg(Register dst, Operand src, int size);
2185 :
2186 3101566 : void emit_xor(Register dst, Register src, int size) {
2187 3108671 : if (size == kInt64Size && dst.code() == src.code()) {
2188 : // 32 bit operations zero the top 32 bits of 64 bit registers. Therefore
2189 : // there is no need to make this a 64 bit operation.
2190 3865 : arithmetic_op(0x33, dst, src, kInt32Size);
2191 : } else {
2192 3097701 : arithmetic_op(0x33, dst, src, size);
2193 : }
2194 3101533 : }
2195 :
2196 : void emit_xor(Register dst, Operand src, int size) {
2197 655 : arithmetic_op(0x33, dst, src, size);
2198 : }
2199 :
2200 : void emit_xor(Register dst, Immediate src, int size) {
2201 22985 : immediate_arithmetic_op(0x6, dst, src, size);
2202 : }
2203 :
2204 : void emit_xor(Operand dst, Immediate src, int size) {
2205 0 : immediate_arithmetic_op(0x6, dst, src, size);
2206 : }
2207 :
2208 : void emit_xor(Operand dst, Register src, int size) {
2209 4 : arithmetic_op(0x31, src, dst, size);
2210 : }
2211 :
2212 : // Most BMI instructions are similar.
2213 : void bmi1q(byte op, Register reg, Register vreg, Register rm);
2214 : void bmi1q(byte op, Register reg, Register vreg, Operand rm);
2215 : void bmi1l(byte op, Register reg, Register vreg, Register rm);
2216 : void bmi1l(byte op, Register reg, Register vreg, Operand rm);
2217 : void bmi2q(SIMDPrefix pp, byte op, Register reg, Register vreg, Register rm);
2218 : void bmi2q(SIMDPrefix pp, byte op, Register reg, Register vreg, Operand rm);
2219 : void bmi2l(SIMDPrefix pp, byte op, Register reg, Register vreg, Register rm);
2220 : void bmi2l(SIMDPrefix pp, byte op, Register reg, Register vreg, Operand rm);
2221 :
2222 : // record the position of jmp/jcc instruction
2223 : void record_farjmp_position(Label* L, int pos);
2224 :
2225 : bool is_optimizable_farjmp(int idx);
2226 :
2227 : void AllocateAndInstallRequestedHeapObjects(Isolate* isolate);
2228 :
2229 : int WriteCodeComments();
2230 :
2231 : friend class EnsureSpace;
2232 : friend class RegExpMacroAssemblerX64;
2233 :
2234 : // code generation
2235 : RelocInfoWriter reloc_info_writer;
2236 :
2237 : // Internal reference positions, required for (potential) patching in
2238 : // GrowBuffer(); contains only those internal references whose labels
2239 : // are already bound.
2240 : std::deque<int> internal_reference_positions_;
2241 :
2242 : // Variables for this instance of assembler
2243 : int farjmp_num_ = 0;
2244 : std::deque<int> farjmp_positions_;
2245 : std::map<Label*, std::vector<int>> label_farjmp_maps_;
2246 :
2247 : ConstPool constpool_;
2248 :
2249 : friend class ConstPool;
2250 : };
2251 :
2252 :
2253 : // Helper class that ensures that there is enough space for generating
2254 : // instructions and relocation information. The constructor makes
2255 : // sure that there is enough space and (in debug mode) the destructor
2256 : // checks that we did not generate too much.
2257 : class EnsureSpace {
2258 : public:
2259 : explicit EnsureSpace(Assembler* assembler) : assembler_(assembler) {
2260 373973681 : if (assembler_->buffer_overflow()) assembler_->GrowBuffer();
2261 : #ifdef DEBUG
2262 : space_before_ = assembler_->available_space();
2263 : #endif
2264 : }
2265 :
2266 : #ifdef DEBUG
2267 : ~EnsureSpace() {
2268 : int bytes_generated = space_before_ - assembler_->available_space();
2269 : DCHECK(bytes_generated < assembler_->kGap);
2270 : }
2271 : #endif
2272 :
2273 : private:
2274 : Assembler* assembler_;
2275 : #ifdef DEBUG
2276 : int space_before_;
2277 : #endif
2278 : };
2279 :
2280 : } // namespace internal
2281 : } // namespace v8
2282 :
2283 : #endif // V8_X64_ASSEMBLER_X64_H_
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