{
  "affected": [
    {
      "ranges": [
        {
          "database_specific": {
            "versions": [
              {
                "introduced": "0"
              },
              {
                "last_affected": "1.6"
              }
            ]
          },
          "events": [
            {
              "introduced": "0"
            },
            {
              "last_affected": "44b0b8249279d25bd75ea693b725d9ff1b96e2ab"
            }
          ],
          "repo": "https://github.com/chipsalliance/rocket-chip",
          "type": "GIT"
        }
      ]
    }
  ],
  "details": "A vulnerability was discovered in RISC-V Rocket-Chip v1.6 and before implementation where the SRET (Supervisor-mode Exception Return) instruction fails to correctly transition the processor's privilege level. Instead of downgrading from Machine-mode (M-mode) to Supervisor-mode (S-mode) as specified by the sstatus.SPP bit, the processor incorrectly remains in M-mode, leading to a critical privilege retention vulnerability.",
  "id": "CVE-2025-63384",
  "modified": "2026-03-10T21:51:46.202466735Z",
  "published": "2025-11-10T20:15:49.013Z",
  "references": [
    {
      "type": "PACKAGE",
      "url": "https://github.com/chipsalliance/rocket-chip.git"
    },
    {
      "type": "EVIDENCE",
      "url": "https://github.com/107040503/RISC-V-Vulnerability-Disclosure_SRET"
    }
  ],
  "severity": [
    {
      "score": "CVSS:3.1/AV:N/AC:L/PR:L/UI:N/S:U/C:H/I:N/A:N",
      "type": "CVSS_V3"
    }
  ]
}