LCOV - code coverage report

Current view: top level - disco/quic - fd_tpu.h (source / functions) Hit Total Coverage Test: cov.lcov Lines: 0 53 0.0 % Date: 2026-03-19 18:19:27 Functions: 0 70 0.0 %

Function Name	Hit count
fd_quic_tile.c:fd_tpu_reasm_acquire	0
fd_quic_tile.c:fd_tpu_reasm_key_hash	0
fd_quic_tile.c:fd_tpu_reasm_peek_tail	0
fd_quic_tile.c:fd_tpu_reasm_pub_slots_laddr	0
fd_quic_tile.c:fd_tpu_reasm_req_data_sz	0
fd_quic_tile.c:fd_tpu_reasm_slots_laddr	0
fd_quic_tile.c:fd_tpu_reasm_slots_laddr_const	0
fd_quic_trace_frame.c:fd_tpu_reasm_acquire	0
fd_quic_trace_frame.c:fd_tpu_reasm_key_hash	0
fd_quic_trace_frame.c:fd_tpu_reasm_peek_tail	0
fd_quic_trace_frame.c:fd_tpu_reasm_pub_slots_laddr	0
fd_quic_trace_frame.c:fd_tpu_reasm_req_data_sz	0
fd_quic_trace_frame.c:fd_tpu_reasm_slots_laddr	0
fd_quic_trace_frame.c:fd_tpu_reasm_slots_laddr_const	0
fd_quic_trace_log_tile.c:fd_tpu_reasm_acquire	0
fd_quic_trace_log_tile.c:fd_tpu_reasm_key_hash	0
fd_quic_trace_log_tile.c:fd_tpu_reasm_peek_tail	0
fd_quic_trace_log_tile.c:fd_tpu_reasm_pub_slots_laddr	0
fd_quic_trace_log_tile.c:fd_tpu_reasm_req_data_sz	0
fd_quic_trace_log_tile.c:fd_tpu_reasm_slots_laddr	0
fd_quic_trace_log_tile.c:fd_tpu_reasm_slots_laddr_const	0
fd_quic_trace_main.c:fd_tpu_reasm_acquire	0
fd_quic_trace_main.c:fd_tpu_reasm_key_hash	0
fd_quic_trace_main.c:fd_tpu_reasm_peek_tail	0
fd_quic_trace_main.c:fd_tpu_reasm_pub_slots_laddr	0
fd_quic_trace_main.c:fd_tpu_reasm_req_data_sz	0
fd_quic_trace_main.c:fd_tpu_reasm_slots_laddr	0
fd_quic_trace_main.c:fd_tpu_reasm_slots_laddr_const	0
fd_quic_trace_rx_tile.c:fd_tpu_reasm_acquire	0
fd_quic_trace_rx_tile.c:fd_tpu_reasm_key_hash	0
fd_quic_trace_rx_tile.c:fd_tpu_reasm_peek_tail	0
fd_quic_trace_rx_tile.c:fd_tpu_reasm_pub_slots_laddr	0
fd_quic_trace_rx_tile.c:fd_tpu_reasm_req_data_sz	0
fd_quic_trace_rx_tile.c:fd_tpu_reasm_slots_laddr	0
fd_quic_trace_rx_tile.c:fd_tpu_reasm_slots_laddr_const	0
fd_tpu_reasm.c:fd_tpu_reasm_acquire	0
fd_tpu_reasm.c:fd_tpu_reasm_key_hash	0
fd_tpu_reasm.c:fd_tpu_reasm_peek_tail	0
fd_tpu_reasm.c:fd_tpu_reasm_pub_slots_laddr	0
fd_tpu_reasm.c:fd_tpu_reasm_req_data_sz	0
fd_tpu_reasm.c:fd_tpu_reasm_slots_laddr	0
fd_tpu_reasm.c:fd_tpu_reasm_slots_laddr_const	0
repair.c:fd_tpu_reasm_acquire	0
repair.c:fd_tpu_reasm_key_hash	0
repair.c:fd_tpu_reasm_peek_tail	0
repair.c:fd_tpu_reasm_pub_slots_laddr	0
repair.c:fd_tpu_reasm_req_data_sz	0
repair.c:fd_tpu_reasm_slots_laddr	0
repair.c:fd_tpu_reasm_slots_laddr_const	0
test_tpu_reasm.c:fd_tpu_reasm_acquire	0
test_tpu_reasm.c:fd_tpu_reasm_key_hash	0
test_tpu_reasm.c:fd_tpu_reasm_peek_tail	0
test_tpu_reasm.c:fd_tpu_reasm_pub_slots_laddr	0
test_tpu_reasm.c:fd_tpu_reasm_req_data_sz	0
test_tpu_reasm.c:fd_tpu_reasm_slots_laddr	0
test_tpu_reasm.c:fd_tpu_reasm_slots_laddr_const	0
test_verify_tile.c:fd_tpu_reasm_acquire	0
test_verify_tile.c:fd_tpu_reasm_key_hash	0
test_verify_tile.c:fd_tpu_reasm_peek_tail	0
test_verify_tile.c:fd_tpu_reasm_pub_slots_laddr	0
test_verify_tile.c:fd_tpu_reasm_req_data_sz	0
test_verify_tile.c:fd_tpu_reasm_slots_laddr	0
test_verify_tile.c:fd_tpu_reasm_slots_laddr_const	0
topology.c:fd_tpu_reasm_acquire	0
topology.c:fd_tpu_reasm_key_hash	0
topology.c:fd_tpu_reasm_peek_tail	0
topology.c:fd_tpu_reasm_pub_slots_laddr	0
topology.c:fd_tpu_reasm_req_data_sz	0
topology.c:fd_tpu_reasm_slots_laddr	0
topology.c:fd_tpu_reasm_slots_laddr_const	0

Generated by: LCOV version 1.14