pic24_ecan.h

00001 /*
00002  * "Copyright (c) 2008 Robert B. Reese, Bryan A. Jones, J. W. Bruce ("AUTHORS")"
00003  * All rights reserved.
00004  * (R. Reese, reese_AT_ece.msstate.edu, Mississippi State University)
00005  * (B. A. Jones, bjones_AT_ece.msstate.edu, Mississippi State University)
00006  * (J. W. Bruce, jwbruce_AT_ece.msstate.edu, Mississippi State University)
00007  *
00008  * Permission to use, copy, modify, and distribute this software and its
00009  * documentation for any purpose, without fee, and without written agreement is
00010  * hereby granted, provided that the above copyright notice, the following
00011  * two paragraphs and the authors appear in all copies of this software.
00012  *
00013  * IN NO EVENT SHALL THE "AUTHORS" BE LIABLE TO ANY PARTY FOR
00014  * DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES ARISING OUT
00015  * OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF THE "AUTHORS"
00016  * HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00017  *
00018  * THE "AUTHORS" SPECIFICALLY DISCLAIMS ANY WARRANTIES,
00019  * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
00020  * AND FITNESS FOR A PARTICULAR PURPOSE.  THE SOFTWARE PROVIDED HEREUNDER IS
00021  * ON AN "AS IS" BASIS, AND THE "AUTHORS" HAS NO OBLIGATION TO
00022  * PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS."
00023  *
00024  * Please maintain this header in its entirety when copying/modifying
00025  * these files.
00026  *
00027  *
00028  */
00029 
00030 #ifndef _PIC24_ECAN1_H_
00031 #define _PIC24_ECAN1_H_
00032 
00033 // Only include if this ECAN Module exists.
00034 #if (NUM_ECAN_MODS >= 1)
00035 
00036 // Documentation for this file. If the \file tag isn't present,
00037 // this file won't be documented.
00038 // Note: place this comment below the #if NUM_ECAN_MODS so Doxygen
00039 // will only see it once.
00044 #ifndef ECAN_1TIME_HEADER_DEFS
00045 
00046 #define ECAN_MODE_NORMAL 0
00047 #define ECAN_MODE_DISABLED 1
00048 #define ECAN_MODE_LOOPBACK 2
00049 #define ECAN_MODE_LISTEN_ONLY 3
00050 #define ECAN_MODE_CONFIGURE 4
00051 #define ECAN_LISTEN_ALL_MESSAGES 7
00052 
00053 #define ECAN_FCAN_IS_FCY 1
00054 #define ECAN_FCAN_IS_OSC 0
00055 
00056 
00057 //CiCFG2 register  (Baud rate config 2 register)
00058 #define ECAN_NO_WAKEUP 0x4000
00059 #define ECAN_SEG2PH_8TQ (0x0007 << 8)
00060 #define ECAN_SEG2PH_7TQ (0x0006 << 8)
00061 #define ECAN_SEG2PH_6TQ (0x0005 << 8)
00062 #define ECAN_SEG2PH_5TQ (0x0004 << 8)
00063 #define ECAN_SEG2PH_4TQ (0x0003 << 8)
00064 #define ECAN_SEG2PH_3TQ (0x0002 << 8)
00065 #define ECAN_SEG2PH_2TQ (0x0001 << 8)
00066 #define ECAN_SEG2PH_1TQ (0x0000 << 8)
00067 
00068 #define ECAN_SEG2_PROGRAMMABLE 0x0080
00069 #define ECAN_SEG2_FIXED        0x0000
00070 
00071 #define ECAN_SAMPLE_3TIMES 0x0040
00072 #define ECAN_SAMPLE_1TIMES 0x0000
00073 
00074 #define ECAN_SEG1PH_8TQ (0x0007 << 3)
00075 #define ECAN_SEG1PH_7TQ (0x0006 << 3)
00076 #define ECAN_SEG1PH_6TQ (0x0005 << 3)
00077 #define ECAN_SEG1PH_5TQ (0x0004 << 3)
00078 #define ECAN_SEG1PH_4TQ (0x0003 << 3)
00079 #define ECAN_SEG1PH_3TQ (0x0002 << 3)
00080 #define ECAN_SEG1PH_2TQ (0x0001 << 3)
00081 #define ECAN_SEG1PH_1TQ (0x0000 << 3)
00082 
00083 #define ECAN_PRSEG_8TQ 0x0007
00084 #define ECAN_PRSEG_7TQ 0x0006
00085 #define ECAN_PRSEG_6TQ 0x0005
00086 #define ECAN_PRSEG_5TQ 0x0004
00087 #define ECAN_PRSEG_4TQ 0x0003
00088 #define ECAN_PRSEG_3TQ 0x0002
00089 #define ECAN_PRSEG_2TQ 0x0001
00090 #define ECAN_PRSEG_1TQ 0x0000
00091 
00092 //CiCFG1 register (Baud rate config 1 register)
00093 #define ECAN_SYNC_JUMP_4   (0x0003 << 6)
00094 #define ECAN_SYNC_JUMP_3   (0x0002 << 6)
00095 #define ECAN_SYNC_JUMP_2   (0x0001 << 6)
00096 #define ECAN_SYNC_JUMP_1   (0x0000 << 6)
00097 
00098 #define ECAN_PRE_2x64 0x003f
00099 #define ECAN_PRE_2x63 0x003e
00100 #define ECAN_PRE_2x62 0x003d
00101 #define ECAN_PRE_2x61 0x003c
00102 #define ECAN_PRE_2x60 0x003b
00103 #define ECAN_PRE_2x59 0x003a
00104 #define ECAN_PRE_2x58 0x0039
00105 #define ECAN_PRE_2x57 0x0038
00106 #define ECAN_PRE_2x56 0x0037
00107 #define ECAN_PRE_2x55 0x0036
00108 #define ECAN_PRE_2x54 0x0035
00109 #define ECAN_PRE_2x53 0x0034
00110 #define ECAN_PRE_2x52 0x0033
00111 #define ECAN_PRE_2x51 0x0032
00112 #define ECAN_PRE_2x50 0x0031
00113 #define ECAN_PRE_2x49 0x0030
00114 #define ECAN_PRE_2x48 0x002f
00115 #define ECAN_PRE_2x47 0x002e
00116 #define ECAN_PRE_2x46 0x002d
00117 #define ECAN_PRE_2x45 0x002c
00118 #define ECAN_PRE_2x44 0x002b
00119 #define ECAN_PRE_2x43 0x002a
00120 #define ECAN_PRE_2x42 0x0029
00121 #define ECAN_PRE_2x41 0x0028
00122 #define ECAN_PRE_2x40 0x0027
00123 #define ECAN_PRE_2x39 0x0026
00124 #define ECAN_PRE_2x38 0x0025
00125 #define ECAN_PRE_2x37 0x0024
00126 #define ECAN_PRE_2x36 0x0023
00127 #define ECAN_PRE_2x35 0x0022
00128 #define ECAN_PRE_2x34 0x0021
00129 #define ECAN_PRE_2x33 0x0020
00130 #define ECAN_PRE_2x32 0x001f
00131 #define ECAN_PRE_2x31 0x001e
00132 #define ECAN_PRE_2x30 0x001d
00133 #define ECAN_PRE_2x29 0x001c
00134 #define ECAN_PRE_2x28 0x001b
00135 #define ECAN_PRE_2x27 0x001a
00136 #define ECAN_PRE_2x26 0x0019
00137 #define ECAN_PRE_2x25 0x0018
00138 #define ECAN_PRE_2x24 0x0017
00139 #define ECAN_PRE_2x23 0x0016
00140 #define ECAN_PRE_2x22 0x0015
00141 #define ECAN_PRE_2x21 0x0014
00142 #define ECAN_PRE_2x20 0x0013
00143 #define ECAN_PRE_2x19 0x0012
00144 #define ECAN_PRE_2x18 0x0011
00145 #define ECAN_PRE_2x17 0x0010
00146 #define ECAN_PRE_2x16 0x000f
00147 #define ECAN_PRE_2x15 0x000e
00148 #define ECAN_PRE_2x14 0x000d
00149 #define ECAN_PRE_2x13 0x000c
00150 #define ECAN_PRE_2x12 0x000b
00151 #define ECAN_PRE_2x11 0x000a
00152 #define ECAN_PRE_2x10 0x0009
00153 #define ECAN_PRE_2x9 0x0008
00154 #define ECAN_PRE_2x8 0x0007
00155 #define ECAN_PRE_2x7 0x0006
00156 #define ECAN_PRE_2x6 0x0005
00157 #define ECAN_PRE_2x5 0x0004
00158 #define ECAN_PRE_2x4 0x0003
00159 #define ECAN_PRE_2x3 0x0002
00160 #define ECAN_PRE_2x2 0x0001
00161 #define ECAN_PRE_2x1 0x0000
00162 
00163 //CiFCTRL register (FIFO Control register)
00164 #define ECAN_DMA_BUF_SIZE_32 (0x0006 << 13)
00165 #define ECAN_DMA_BUF_SIZE_24 (0x0005 << 13)
00166 #define ECAN_DMA_BUF_SIZE_16 (0x0004 << 13)
00167 #define ECAN_DMA_BUF_SIZE_12 (0x0003 << 13)
00168 #define ECAN_DMA_BUF_SIZE_8 (0x0002 << 13)
00169 #define ECAN_DMA_BUF_SIZE_6 (0x0001 << 13)
00170 #define ECAN_DMA_BUF_SIZE_4 (0x0000 << 13)
00171 
00172 
00173 #define ECAN_FIFO_START_AREA_31 31
00174 #define ECAN_FIFO_START_AREA_30 30
00175 #define ECAN_FIFO_START_AREA_29 29
00176 #define ECAN_FIFO_START_AREA_28 28
00177 #define ECAN_FIFO_START_AREA_27 27
00178 #define ECAN_FIFO_START_AREA_26 26
00179 #define ECAN_FIFO_START_AREA_25 25
00180 #define ECAN_FIFO_START_AREA_24 24
00181 #define ECAN_FIFO_START_AREA_23 23
00182 #define ECAN_FIFO_START_AREA_22 22
00183 #define ECAN_FIFO_START_AREA_21 21
00184 #define ECAN_FIFO_START_AREA_20 20
00185 #define ECAN_FIFO_START_AREA_19 19
00186 #define ECAN_FIFO_START_AREA_18 18
00187 #define ECAN_FIFO_START_AREA_17 17
00188 #define ECAN_FIFO_START_AREA_16 16
00189 #define ECAN_FIFO_START_AREA_15 15
00190 #define ECAN_FIFO_START_AREA_14 14
00191 #define ECAN_FIFO_START_AREA_13 13
00192 #define ECAN_FIFO_START_AREA_12 12
00193 #define ECAN_FIFO_START_AREA_11 11
00194 #define ECAN_FIFO_START_AREA_10 10
00195 #define ECAN_FIFO_START_AREA_9 9
00196 #define ECAN_FIFO_START_AREA_8 8
00197 #define ECAN_FIFO_START_AREA_7 7
00198 #define ECAN_FIFO_START_AREA_6 6
00199 #define ECAN_FIFO_START_AREA_5 5
00200 #define ECAN_FIFO_START_AREA_4 4
00201 #define ECAN_FIFO_START_AREA_3 3
00202 #define ECAN_FIFO_START_AREA_2 2
00203 #define ECAN_FIFO_START_AREA_1 1
00204 #define ECAN_FIFO_START_AREA_0 0
00205 
00206 //CiRXFnSID  register
00207 #define ECAN_MATCH_EID   0x0008
00208 #define ECAN_MATCH_SID   0x0000
00209 
00210 #define ECAN_USE_FIFO   0xF
00211 
00212 //CiTRmnCON  TXRX buffer control
00213 #define ECAN_RX_BUFF 0   
00214 #define ECAN_TX_BUFF 1
00215 
00216  
00217 //Data structure for ECAN Data Frame
00218 typedef struct _ECANW0 {
00219     unsigned IDE: 1;
00220     unsigned SRR:1;
00221     unsigned SID:11;
00222 }ECANW0;
00223 typedef struct _ECANW1 {
00224     unsigned EID17_6: 12;
00225 }ECANW1;
00226 
00227 typedef struct _ECANW2 {
00228     unsigned DLC:4;
00229     unsigned RB0:1;
00230     unsigned :3;
00231     unsigned RB1:1;
00232     unsigned RTR:1;
00233     unsigned EID5_0:6;
00234 }ECANW2;
00235 
00236 typedef struct _ECANW7 {
00237     unsigned :8;
00238     unsigned FILHIT:5;
00239     unsigned :3;
00240 }ECANW7;
00241 
00242 
00243 
00244 typedef struct _ECANMSG {
00245    ECANW0 w0;
00246    ECANW1 w1;
00247    ECANW2 w2;
00248    union64 data;
00249    ECANW7  w7;
00250 }ECANMSG;
00251 
00252 
00253 void formatStandardDataFrameECAN (ECANMSG* p_ecanmsg, uint16 u16_id, uint8 u8_len);
00254 void formatExtendedDataFrameECAN (ECANMSG* p_ecanmsg, uint32 u32_id, uint8 u8_len);
00255 uint32 getIdExtendedDataFrameECAN (ECANMSG* p_ecanmsg);
00256 
00257 #define ECAN_1TIME_HEADER_DEFS
00258 #endif
00259 
00260 
00261 
00262 
00263 #ifdef _C1IF
00264 
00265 inline static void CHANGE_MODE_ECAN1(mode) {
00266   C1CTRL1bits.REQOP = mode;
00267   while(C1CTRL1bits.OPMODE != mode); 
00268 }
00269 
00272 #define GET_FIFO_READBUFFER_ECAN1() (C1FIFO & 0x1F)   
00273 
00274 void clrRxFullFlagECAN1(uint8 u8_bufNum);
00275 uint8 getRxFullFlagECAN1(uint8 u8_bufNum);
00276 void clrRxFullOvfFlagsECAN1(void);
00277 void configTxRxBufferECAN1(uint8 u8_bufNum, uint8 u8_type, uint8 u8_priority);
00278 void configRxFilterECAN1(uint8 u8_filtNum, uint32 u32_id, uint8 u8_idType, uint8 u8_bufnum, uint8 u8_maskReg);
00279 void configRxMaskECAN1(uint8 u8_maskNum, uint32 u32_idMask, uint8 u8_idType, uint8 u8_matchType);
00280 void startTxECAN1(uint8 u8_bufNum);
00281 uint8 getTxInProgressECAN1(uint8 u8_bufNum);
00282 
00283 #endif
00284 
00285  
00286 #endif // #if (NUM_ECAN_MODS >= 1)
00287 #endif // #define _PIC24_ECAN1_H_
00288 
00289 
00290 
00291 /*
00292  * "Copyright (c) 2008 Robert B. Reese, Bryan A. Jones, J. W. Bruce ("AUTHORS")"
00293  * All rights reserved.
00294  * (R. Reese, reese_AT_ece.msstate.edu, Mississippi State University)
00295  * (B. A. Jones, bjones_AT_ece.msstate.edu, Mississippi State University)
00296  * (J. W. Bruce, jwbruce_AT_ece.msstate.edu, Mississippi State University)
00297  *
00298  * Permission to use, copy, modify, and distribute this software and its
00299  * documentation for any purpose, without fee, and without written agreement is
00300  * hereby granted, provided that the above copyright notice, the following
00301  * two paragraphs and the authors appear in all copies of this software.
00302  *
00303  * IN NO EVENT SHALL THE "AUTHORS" BE LIABLE TO ANY PARTY FOR
00304  * DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES ARISING OUT
00305  * OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF THE "AUTHORS"
00306  * HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00307  *
00308  * THE "AUTHORS" SPECIFICALLY DISCLAIMS ANY WARRANTIES,
00309  * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
00310  * AND FITNESS FOR A PARTICULAR PURPOSE.  THE SOFTWARE PROVIDED HEREUNDER IS
00311  * ON AN "AS IS" BASIS, AND THE "AUTHORS" HAS NO OBLIGATION TO
00312  * PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS."
00313  *
00314  * Please maintain this header in its entirety when copying/modifying
00315  * these files.
00316  *
00317  *
00318  */
00319 
00320 #ifndef _PIC24_ECAN2_H_
00321 #define _PIC24_ECAN2_H_
00322 
00323 // Only include if this ECAN Module exists.
00324 #if (NUM_ECAN_MODS >= 2)
00325 
00326 // Documentation for this file. If the \file tag isn't present,
00327 // this file won't be documented.
00328 // Note: place this comment below the #if NUM_ECAN_MODS so Doxygen
00329 // will only see it once.
00334 #ifndef ECAN_1TIME_HEADER_DEFS
00335 
00336 #define ECAN_MODE_NORMAL 0
00337 #define ECAN_MODE_DISABLED 1
00338 #define ECAN_MODE_LOOPBACK 2
00339 #define ECAN_MODE_LISTEN_ONLY 3
00340 #define ECAN_MODE_CONFIGURE 4
00341 #define ECAN_LISTEN_ALL_MESSAGES 7
00342 
00343 #define ECAN_FCAN_IS_FCY 1
00344 #define ECAN_FCAN_IS_OSC 0
00345 
00346 
00347 //CiCFG2 register  (Baud rate config 2 register)
00348 #define ECAN_NO_WAKEUP 0x4000
00349 #define ECAN_SEG2PH_8TQ (0x0007 << 8)
00350 #define ECAN_SEG2PH_7TQ (0x0006 << 8)
00351 #define ECAN_SEG2PH_6TQ (0x0005 << 8)
00352 #define ECAN_SEG2PH_5TQ (0x0004 << 8)
00353 #define ECAN_SEG2PH_4TQ (0x0003 << 8)
00354 #define ECAN_SEG2PH_3TQ (0x0002 << 8)
00355 #define ECAN_SEG2PH_2TQ (0x0001 << 8)
00356 #define ECAN_SEG2PH_1TQ (0x0000 << 8)
00357 
00358 #define ECAN_SEG2_PROGRAMMABLE 0x0080
00359 #define ECAN_SEG2_FIXED        0x0000
00360 
00361 #define ECAN_SAMPLE_3TIMES 0x0040
00362 #define ECAN_SAMPLE_1TIMES 0x0000
00363 
00364 #define ECAN_SEG1PH_8TQ (0x0007 << 3)
00365 #define ECAN_SEG1PH_7TQ (0x0006 << 3)
00366 #define ECAN_SEG1PH_6TQ (0x0005 << 3)
00367 #define ECAN_SEG1PH_5TQ (0x0004 << 3)
00368 #define ECAN_SEG1PH_4TQ (0x0003 << 3)
00369 #define ECAN_SEG1PH_3TQ (0x0002 << 3)
00370 #define ECAN_SEG1PH_2TQ (0x0001 << 3)
00371 #define ECAN_SEG1PH_1TQ (0x0000 << 3)
00372 
00373 #define ECAN_PRSEG_8TQ 0x0007
00374 #define ECAN_PRSEG_7TQ 0x0006
00375 #define ECAN_PRSEG_6TQ 0x0005
00376 #define ECAN_PRSEG_5TQ 0x0004
00377 #define ECAN_PRSEG_4TQ 0x0003
00378 #define ECAN_PRSEG_3TQ 0x0002
00379 #define ECAN_PRSEG_2TQ 0x0001
00380 #define ECAN_PRSEG_1TQ 0x0000
00381 
00382 //CiCFG1 register (Baud rate config 1 register)
00383 #define ECAN_SYNC_JUMP_4   (0x0003 << 6)
00384 #define ECAN_SYNC_JUMP_3   (0x0002 << 6)
00385 #define ECAN_SYNC_JUMP_2   (0x0001 << 6)
00386 #define ECAN_SYNC_JUMP_1   (0x0000 << 6)
00387 
00388 #define ECAN_PRE_2x64 0x003f
00389 #define ECAN_PRE_2x63 0x003e
00390 #define ECAN_PRE_2x62 0x003d
00391 #define ECAN_PRE_2x61 0x003c
00392 #define ECAN_PRE_2x60 0x003b
00393 #define ECAN_PRE_2x59 0x003a
00394 #define ECAN_PRE_2x58 0x0039
00395 #define ECAN_PRE_2x57 0x0038
00396 #define ECAN_PRE_2x56 0x0037
00397 #define ECAN_PRE_2x55 0x0036
00398 #define ECAN_PRE_2x54 0x0035
00399 #define ECAN_PRE_2x53 0x0034
00400 #define ECAN_PRE_2x52 0x0033
00401 #define ECAN_PRE_2x51 0x0032
00402 #define ECAN_PRE_2x50 0x0031
00403 #define ECAN_PRE_2x49 0x0030
00404 #define ECAN_PRE_2x48 0x002f
00405 #define ECAN_PRE_2x47 0x002e
00406 #define ECAN_PRE_2x46 0x002d
00407 #define ECAN_PRE_2x45 0x002c
00408 #define ECAN_PRE_2x44 0x002b
00409 #define ECAN_PRE_2x43 0x002a
00410 #define ECAN_PRE_2x42 0x0029
00411 #define ECAN_PRE_2x41 0x0028
00412 #define ECAN_PRE_2x40 0x0027
00413 #define ECAN_PRE_2x39 0x0026
00414 #define ECAN_PRE_2x38 0x0025
00415 #define ECAN_PRE_2x37 0x0024
00416 #define ECAN_PRE_2x36 0x0023
00417 #define ECAN_PRE_2x35 0x0022
00418 #define ECAN_PRE_2x34 0x0021
00419 #define ECAN_PRE_2x33 0x0020
00420 #define ECAN_PRE_2x32 0x001f
00421 #define ECAN_PRE_2x31 0x001e
00422 #define ECAN_PRE_2x30 0x001d
00423 #define ECAN_PRE_2x29 0x001c
00424 #define ECAN_PRE_2x28 0x001b
00425 #define ECAN_PRE_2x27 0x001a
00426 #define ECAN_PRE_2x26 0x0019
00427 #define ECAN_PRE_2x25 0x0018
00428 #define ECAN_PRE_2x24 0x0017
00429 #define ECAN_PRE_2x23 0x0016
00430 #define ECAN_PRE_2x22 0x0015
00431 #define ECAN_PRE_2x21 0x0014
00432 #define ECAN_PRE_2x20 0x0013
00433 #define ECAN_PRE_2x19 0x0012
00434 #define ECAN_PRE_2x18 0x0011
00435 #define ECAN_PRE_2x17 0x0010
00436 #define ECAN_PRE_2x16 0x000f
00437 #define ECAN_PRE_2x15 0x000e
00438 #define ECAN_PRE_2x14 0x000d
00439 #define ECAN_PRE_2x13 0x000c
00440 #define ECAN_PRE_2x12 0x000b
00441 #define ECAN_PRE_2x11 0x000a
00442 #define ECAN_PRE_2x10 0x0009
00443 #define ECAN_PRE_2x9 0x0008
00444 #define ECAN_PRE_2x8 0x0007
00445 #define ECAN_PRE_2x7 0x0006
00446 #define ECAN_PRE_2x6 0x0005
00447 #define ECAN_PRE_2x5 0x0004
00448 #define ECAN_PRE_2x4 0x0003
00449 #define ECAN_PRE_2x3 0x0002
00450 #define ECAN_PRE_2x2 0x0001
00451 #define ECAN_PRE_2x1 0x0000
00452 
00453 //CiFCTRL register (FIFO Control register)
00454 #define ECAN_DMA_BUF_SIZE_32 (0x0006 << 13)
00455 #define ECAN_DMA_BUF_SIZE_24 (0x0005 << 13)
00456 #define ECAN_DMA_BUF_SIZE_16 (0x0004 << 13)
00457 #define ECAN_DMA_BUF_SIZE_12 (0x0003 << 13)
00458 #define ECAN_DMA_BUF_SIZE_8 (0x0002 << 13)
00459 #define ECAN_DMA_BUF_SIZE_6 (0x0001 << 13)
00460 #define ECAN_DMA_BUF_SIZE_4 (0x0000 << 13)
00461 
00462 
00463 #define ECAN_FIFO_START_AREA_31 31
00464 #define ECAN_FIFO_START_AREA_30 30
00465 #define ECAN_FIFO_START_AREA_29 29
00466 #define ECAN_FIFO_START_AREA_28 28
00467 #define ECAN_FIFO_START_AREA_27 27
00468 #define ECAN_FIFO_START_AREA_26 26
00469 #define ECAN_FIFO_START_AREA_25 25
00470 #define ECAN_FIFO_START_AREA_24 24
00471 #define ECAN_FIFO_START_AREA_23 23
00472 #define ECAN_FIFO_START_AREA_22 22
00473 #define ECAN_FIFO_START_AREA_21 21
00474 #define ECAN_FIFO_START_AREA_20 20
00475 #define ECAN_FIFO_START_AREA_19 19
00476 #define ECAN_FIFO_START_AREA_18 18
00477 #define ECAN_FIFO_START_AREA_17 17
00478 #define ECAN_FIFO_START_AREA_16 16
00479 #define ECAN_FIFO_START_AREA_15 15
00480 #define ECAN_FIFO_START_AREA_14 14
00481 #define ECAN_FIFO_START_AREA_13 13
00482 #define ECAN_FIFO_START_AREA_12 12
00483 #define ECAN_FIFO_START_AREA_11 11
00484 #define ECAN_FIFO_START_AREA_10 10
00485 #define ECAN_FIFO_START_AREA_9 9
00486 #define ECAN_FIFO_START_AREA_8 8
00487 #define ECAN_FIFO_START_AREA_7 7
00488 #define ECAN_FIFO_START_AREA_6 6
00489 #define ECAN_FIFO_START_AREA_5 5
00490 #define ECAN_FIFO_START_AREA_4 4
00491 #define ECAN_FIFO_START_AREA_3 3
00492 #define ECAN_FIFO_START_AREA_2 2
00493 #define ECAN_FIFO_START_AREA_1 1
00494 #define ECAN_FIFO_START_AREA_0 0
00495 
00496 //CiRXFnSID  register
00497 #define ECAN_MATCH_EID   0x0008
00498 #define ECAN_MATCH_SID   0x0000
00499 
00500 #define ECAN_USE_FIFO   0xF
00501 
00502 //CiTRmnCON  TXRX buffer control
00503 #define ECAN_RX_BUFF 0   
00504 #define ECAN_TX_BUFF 1
00505 
00506  
00507 //Data structure for ECAN Data Frame
00508 typedef struct _ECANW0 {
00509     unsigned IDE: 1;
00510     unsigned SRR:1;
00511     unsigned SID:11;
00512 }ECANW0;
00513 typedef struct _ECANW1 {
00514     unsigned EID17_6: 12;
00515 }ECANW1;
00516 
00517 typedef struct _ECANW2 {
00518     unsigned DLC:4;
00519     unsigned RB0:1;
00520     unsigned :3;
00521     unsigned RB1:1;
00522     unsigned RTR:1;
00523     unsigned EID5_0:6;
00524 }ECANW2;
00525 
00526 typedef struct _ECANW7 {
00527     unsigned :8;
00528     unsigned FILHIT:5;
00529     unsigned :3;
00530 }ECANW7;
00531 
00532 
00533 
00534 typedef struct _ECANMSG {
00535    ECANW0 w0;
00536    ECANW1 w1;
00537    ECANW2 w2;
00538    union64 data;
00539    ECANW7  w7;
00540 }ECANMSG;
00541 
00542 
00543 void formatStandardDataFrameECAN (ECANMSG* p_ecanmsg, uint16 u16_id, uint8 u8_len);
00544 void formatExtendedDataFrameECAN (ECANMSG* p_ecanmsg, uint32 u32_id, uint8 u8_len);
00545 uint32 getIdExtendedDataFrameECAN (ECANMSG* p_ecanmsg);
00546 
00547 #define ECAN_1TIME_HEADER_DEFS
00548 #endif
00549 
00550 
00551 
00552 
00553 #ifdef _C2IF
00554 
00555 inline static void CHANGE_MODE_ECAN2(mode) {
00556   C2CTRL1bits.REQOP = mode;
00557   while(C2CTRL1bits.OPMODE != mode); 
00558 }
00559 
00562 #define GET_FIFO_READBUFFER_ECAN2() (C2FIFO & 0x1F)   
00563 
00564 void clrRxFullFlagECAN2(uint8 u8_bufNum);
00565 uint8 getRxFullFlagECAN2(uint8 u8_bufNum);
00566 void clrRxFullOvfFlagsECAN2(void);
00567 void configTxRxBufferECAN2(uint8 u8_bufNum, uint8 u8_type, uint8 u8_priority);
00568 void configRxFilterECAN2(uint8 u8_filtNum, uint32 u32_id, uint8 u8_idType, uint8 u8_bufnum, uint8 u8_maskReg);
00569 void configRxMaskECAN2(uint8 u8_maskNum, uint32 u32_idMask, uint8 u8_idType, uint8 u8_matchType);
00570 void startTxECAN2(uint8 u8_bufNum);
00571 uint8 getTxInProgressECAN2(uint8 u8_bufNum);
00572 
00573 #endif
00574 
00575  
00576 #endif // #if (NUM_ECAN_MODS >= 2)
00577 #endif // #define _PIC24_ECAN2_H_
00578 
00579 
00580 

Generated on Mon Oct 18 07:40:47 2010 for Python-on-a-chip by  doxygen 1.5.9