00001 //*---------------------------------------------------------------------------- 00002 //* ATMEL Microcontroller Software Support - ROUSSET - 00003 //*---------------------------------------------------------------------------- 00004 //* The software is delivered "AS IS" without warranty or condition of any 00005 //* kind, either express, implied or statutory. This includes without 00006 //* limitation any warranty or condition with respect to merchantability or 00007 //* fitness for any particular purpose, or against the infringements of 00008 //* intellectual property rights of others. 00009 //*---------------------------------------------------------------------------- 00010 //* File Name : Cstartup_SAM7.c 00011 //* Object : Low level initializations written in C for GCC Tools 00012 //* Creation : 12/Jun/04 00013 //* 1.2 28/Feb/05 JPP : LIB change AT91C_WDTC_WDDIS & PLL 00014 //* 1.3 21/Mar/05 JPP : Change PLL Wait time 00015 //*---------------------------------------------------------------------------- 00016 00017 // Include the board file description 00018 #include "Board.h" 00019 00020 // The following functions must be write in ARM mode this function called directly 00021 // by exception vector 00022 extern void AT91F_Spurious_handler(void); 00023 extern void AT91F_Default_IRQ_handler(void); 00024 extern void AT91F_Default_FIQ_handler(void); 00025 00026 //*---------------------------------------------------------------------------- 00027 //* \fn AT91F_LowLevelInit 00028 //* \brief This function performs very low level HW initialization 00029 //* this function can be use a Stack, depending the compilation 00030 //* optimization mode 00031 //*---------------------------------------------------------------------------- 00032 void AT91F_LowLevelInit( void) 00033 { 00034 int i; 00035 AT91PS_PMC pPMC = AT91C_BASE_PMC; 00036 //* Set Flash Waite sate 00037 // Single Cycle Access at Up to 30 MHz, or 40 00038 // if MCK = 47923200 I have 50 Cycle for 1 usecond ( flied MC_FMR->FMCN 00039 AT91C_BASE_MC->MC_FMR = ((AT91C_MC_FMCN)&(48 <<16)) | AT91C_MC_FWS_1FWS ; 00040 00041 //* Watchdog Disable 00042 AT91C_BASE_WDTC->WDTC_WDMR= AT91C_WDTC_WDDIS; 00043 00044 //* Set MCK at 47 923 200 00045 // 1 Enabling the Main Oscillator: 00046 // SCK = 1/32768 = 30.51 uSecond 00047 // Start up time = 8 * 6 / SCK = 56 * 30.51 = 1,46484375 ms 00048 pPMC->PMC_MOR = ( (AT91C_CKGR_OSCOUNT) & (0x06 <<8)) | AT91C_CKGR_MOSCEN ; 00049 // Wait the startup time 00050 while(!(pPMC->PMC_SR & AT91C_PMC_MOSCS)); 00051 // 2 Checking the Main Oscillator Frequency (Optional) 00052 // 3 Setting PLL and divider: 00053 // - div by 5 Fin = 3,6864 =(18,432 / 5) 00054 // - Mul 25+1: Fout = 95,8464 =(3,6864 *26) 00055 // for 96 MHz the erroe is 0.16% 00056 // Field out NOT USED = 0 00057 // PLLCOUNT pll startup time estimate at : 0.844 ms 00058 // PLLCOUNT 28 = 0.000844 /(1/32768) 00059 pPMC->PMC_PLLR = ((AT91C_CKGR_DIV & 0x05) | 00060 (AT91C_CKGR_PLLCOUNT & (28<<8)) | 00061 (AT91C_CKGR_MUL & (25<<16))); 00062 00063 // Wait the startup time 00064 while(!(pPMC->PMC_SR & AT91C_PMC_LOCK)); 00065 while(!(pPMC->PMC_SR & AT91C_PMC_MCKRDY)); 00066 // 4. Selection of Master Clock and Processor Clock 00067 // select the PLL clock divided by 2 00068 pPMC->PMC_MCKR = AT91C_PMC_PRES_CLK_2 ; 00069 while(!(pPMC->PMC_SR & AT91C_PMC_MCKRDY)); 00070 00071 pPMC->PMC_MCKR |= AT91C_PMC_CSS_PLL_CLK ; 00072 while(!(pPMC->PMC_SR & AT91C_PMC_MCKRDY)); 00073 00074 // Set up the default interrupts handler vectors 00075 AT91C_BASE_AIC->AIC_SVR[0] = (int) AT91F_Default_FIQ_handler ; 00076 for (i=1;i < 31; i++) 00077 { 00078 AT91C_BASE_AIC->AIC_SVR[i] = (int) AT91F_Default_IRQ_handler ; 00079 } 00080 AT91C_BASE_AIC->AIC_SPU = (int) AT91F_Spurious_handler ; 00081 00082 } 00083