pic24_timer.h

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00001 /* Standard copyright does not go in this file because
00002 * of the use of Microchip provided macros, see comments below.
00003 */
00004 // Documentation for this file. If the \file tag isn't present,
00005 // this file won't be documented.
00010 #ifndef  _PIC24_TIMER_H_
00011 #define _PIC24_TIMER_H_
00012 
00020 #define getTimerPrescale(TxCONbits) getTimerPrescaleBits(TxCONbits.TCKPS)
00021 
00022 #define MS_TO_TICKS(ms, pre) ((FCY/1000L/(pre))*ms)
00023 uint16 msToU16Ticks(uint16 u16_ms, uint16 u16_pre);
00024 uint16 usToU16Ticks(uint16 u16_us, uint16 u16_pre);
00025 uint32 usToU32Ticks(uint32 u32_us, uint16 u16_pre);
00026 uint16 getTimerPrescaleBits(uint8 u8_TCKPS);
00027 uint32 ticksToMs (uint32 u32_ticks, uint16 u16_tmrPre);
00028 uint32 ticksToUs (uint32 u32_ticks, uint16 u16_tmrPre);
00029 uint32 ticksToNs (uint32 u32_ticks, uint16 u16_tmrPre);
00030 uint32 computeDeltaTicksLong(uint16 u16_start, uint16 u16_end, uint16 u16_tmrPR, uint16 u16_oflows);
00031 uint16 computeDeltaTicks(uint16 u16_start, uint16 u16_end, uint16 u16_tmrPR);
00032 
00033 /*
00034 The following macros are a subset of the AND/OR macros found in the
00035 the MPLAB C30/src/peripheral_24F/timer.h file and placed
00036 in this header for use solely and exclusively on Microchip
00037 PICmicro Microcontroller products as
00038 specified in the MPLAB C30/src/peripheral_24F/timer.h header.
00039 
00040 Edits have been made in the comments to correct some
00041 minor typos.
00042 */
00043 
00044 /* T1CON: TIMER1 CONTROL REGISTER */
00045 #define T1_ON               0x8000 /* Timer1 ON */
00046 #define T1_OFF              0x0000 /* Timer1 OFF */
00047 #define T1_OFF_ON_MASK      (~T1_ON)
00048 
00049 #define T1_IDLE_STOP        0x2000 /* stop operation during sleep */
00050 #define T1_IDLE_CON         0x0000 /* operate during sleep */
00051 #define T1_IDLE_MASK        (~T1_IDLE_STOP)
00052 
00053 #define T1_GATE_ON          0x0040 /* Timer Gate time accumulation enabled */
00054 #define T1_GATE_OFF         0x0000 /* Timer Gate time accumulation disabled */
00055 #define T1_GATE_MASK        (~T1_GATE_ON)
00056 
00057 #define T1_PS_1_1           0x0000 /* Prescaler 1:1 */
00058 #define T1_PS_1_8           0x0010 /*           1:8 */
00059 #define T1_PS_1_64          0x0020 /*          1:64 */
00060 #define T1_PS_1_256         0x0030 /*         1:256 */
00061 #define T1_PS_MASK          (~T1_PS_1_256)
00062 
00063 #define T1_SYNC_EXT_ON      0x0004 /* Synch external clk input */
00064 #define T1_SYNC_EXT_OFF     0x0000 /* Do not synch external clk input */
00065 #define T1_SYNC_EXT_MASK    (~T1_SYNC_EXT_ON)
00066 
00067 #define T1_SOURCE_EXT       0x0002 /* External clock source */
00068 #define T1_SOURCE_INT       0x0000 /* Internal clock source */
00069 #define T1_SOURCE_MASK      (~T1_SOURCE_EXT)
00070 
00071 #ifdef _T2IF
00072 /* T2CON: TIMER2 CONTROL REGISTER */
00073 #define T2_ON               0x8000      /* Timer2 ON */
00074 #define T2_OFF              0x0000      /* Timer2 OFF */
00075 #define T2_OFF_ON_MASK      (~T2_ON)
00076 
00077 #define T2_IDLE_STOP        0x2000 /* stop operation during sleep */
00078 #define T2_IDLE_CON         0x0000 /* operate during sleep */
00079 #define T2_IDLE_MASK        (~T2_IDLE_STOP)
00080 
00081 #define T2_GATE_ON          0x0040 /* Timer Gate time accumulation enabled */
00082 #define T2_GATE_OFF         0x0000 /* Timer Gate time accumulation disabled */
00083 #define T2_GATE_MASK        (~T2_GATE_ON)
00084 
00085 #define T2_PS_1_1           0x0000      /* Prescaler 1:1 */
00086 #define T2_PS_1_8           0x0010      /*           1:8 */
00087 #define T2_PS_1_64          0x0020      /*          1:64 */
00088 #define T2_PS_1_256         0x0030      /*         1:256 */
00089 #define T2_PS_MASK          (~T2_PS_1_256)
00090 
00091 #define T2_32BIT_MODE_ON    0x0008      /* Timer 2 and Timer 3 form a 32 bit Timer */
00092 #define T2_32BIT_MODE_OFF   0x0000
00093 #define T2_32BIT_MODE_MASK   (~T2_32BIT_MODE_ON)
00094 
00095 #define T2_SOURCE_EXT       0x0002 /* External clock source */
00096 #define T2_SOURCE_INT       0x0000 /* Internal clock source */
00097 #define T2_SOURCE_MASK      (~T2_SOURCE_EXT)
00098 #endif
00099 
00100 #ifdef _T3IF
00101 /* T3CON: TIMER3 CONTROL REGISTER */
00102 #define T3_ON               0x8000      /* Timer3 ON */
00103 #define T3_OFF              0x0000      /* Timer3 OFF */
00104 #define T3_OFF_ON_MASK      (~T3_ON)
00105 
00106 #define T3_IDLE_STOP        0x2000 /* operate during sleep */
00107 #define T3_IDLE_CON         0x0000 /* stop operation during sleep */
00108 #define T3_IDLE_MASK        (~T3_IDLE_STOP)
00109 
00110 #define T3_GATE_ON          0x0040 /* Timer Gate time accumulation enabled */
00111 #define T3_GATE_OFF         0x0000 /* Timer Gate time accumulation disabled */
00112 #define T3_GATE_MASK        (~T3_GATE_ON)
00113 
00114 #define T3_PS_1_1           0x0000      /* Prescaler 1:1 */
00115 #define T3_PS_1_8           0x0010      /*           1:8 */
00116 #define T3_PS_1_64          0x0020      /*          1:64 */
00117 #define T3_PS_1_256         0x0030      /*         1:256 */
00118 #define T3_PS_MASK          (~T3_PS_1_256)
00119 
00120 #define T3_SOURCE_EXT       0x0002 /* External clock source */
00121 #define T3_SOURCE_INT       0x0000 /* Internal clock source */
00122 #define T3_SOURCE_MASK      (~T3_SOURCE_EXT)
00123 #endif
00124 
00125 #ifdef _T4IF
00126 /* T4CON: TIMER4 CONTROL REGISTER */
00127 #define T4_ON               0x8000      /* Timer4 ON */
00128 #define T4_OFF              0x0000      /* Timer4 OFF */
00129 #define T4_OFF_ON_MASK      (~T4_ON)
00130 
00131 #define T4_IDLE_STOP        0x2000 /* operate during sleep */
00132 #define T4_IDLE_CON         0x0000 /* stop operation during sleep */
00133 #define T4_IDLE_MASK        (~T4_IDLE_STOP)
00134 
00135 #define T4_GATE_ON          0x0040 /* Timer Gate time accumulation enabled */
00136 #define T4_GATE_OFF         0x0000 /* Timer Gate time accumulation disabled */
00137 #define T4_GATE_MASK        (~T4_GATE_ON)
00138 
00139 #define T4_PS_1_1           0x0000      /* Prescaler 1:1 */
00140 #define T4_PS_1_8           0x0010      /*           1:8 */
00141 #define T4_PS_1_64          0x0020      /*          1:64 */
00142 #define T4_PS_1_256         0x0030      /*         1:256 */
00143 #define T4_PS_MASK          (~T4_PS_1_256)
00144 
00145 #define T4_32BIT_MODE_ON    0x0008      /* Timer 4 and Timer 5 form a 32 bit Timer */
00146 #define T4_32BIT_MODE_OFF   0x0000
00147 #define T4_32BIT_MODE_MASK   (~T4_32BIT_MODE_ON)
00148 
00149 #define T4_SOURCE_EXT       0x0002 /* External clock source */
00150 #define T4_SOURCE_INT       0x0000 /* Internal clock source */
00151 #define T4_SOURCE_MASK      (~T4_SOURCE_EXT)
00152 #endif
00153 
00154 #ifdef _T5IF
00155 /* T5CON: TIMER5 CONTROL REGISTER */
00156 #define T5_ON               0x8000      /* Timer5 ON */
00157 #define T5_OFF              0x0000      /* Timer5 OFF */
00158 #define T5_OFF_ON_MASK      (~T5_ON)
00159 
00160 #define T5_IDLE_STOP        0x2000 /* operate during sleep */
00161 #define T5_IDLE_CON         0x0000 /* stop operation during sleep */
00162 #define T5_IDLE_MASK        (~T5_IDLE_STOP)
00163 
00164 #define T5_GATE_ON          0x0040 /* Timer Gate time accumulation enabled */
00165 #define T5_GATE_OFF         0x0000 /* Timer Gate time accumulation disabled */
00166 #define T5_GATE_MASK        (~T5_GATE_ON)
00167 
00168 #define T5_PS_1_1           0x0000      /* Prescaler 1:1 */
00169 #define T5_PS_1_8           0x0010      /*           1:8 */
00170 #define T5_PS_1_64          0x0020      /*          1:64 */
00171 #define T5_PS_1_256         0x0030      /*         1:256 */
00172 #define T5_PS_MASK          (~T5_PS_1_256)
00173 
00174 #define T5_SOURCE_EXT       0x0002 /* External clock source */
00175 #define T5_SOURCE_INT       0x0000 /* Internal clock source */
00176 #define T5_SOURCE_MASK      (~T5_SOURCE_EXT)
00177 #endif
00178 
00179 #ifdef _T6IF
00180 /* T6CON: TIMER6 CONTROL REGISTER */
00181 #define T6_ON               0x8000      /* Timer6 ON */
00182 #define T6_OFF              0x0000      /* Timer6 OFF */
00183 #define T6_OFF_ON_MASK      (~T6_ON)
00184 
00185 #define T6_IDLE_STOP        0x2000 /* operate during sleep */
00186 #define T6_IDLE_CON         0x0000 /* stop operation during sleep */
00187 #define T6_IDLE_MASK        (~T6_IDLE_STOP)
00188 
00189 #define T6_GATE_ON          0x0040 /* Timer Gate time accumulation enabled */
00190 #define T6_GATE_OFF         0x0000 /* Timer Gate time accumulation disabled */
00191 #define T6_GATE_MASK        (~T6_GATE_ON)
00192 
00193 #define T6_PS_1_1           0x0000      /* Prescaler 1:1 */
00194 #define T6_PS_1_8           0x0010      /*           1:8 */
00195 #define T6_PS_1_64          0x0020      /*          1:64 */
00196 #define T6_PS_1_256         0x0030      /*         1:256 */
00197 #define T6_PS_MASK          (~T6_PS_1_256)
00198 
00199 #define T6_32BIT_MODE_ON    0x0008      /* Timer 6 and Timer 7 form a 32 bit Timer */
00200 #define T6_32BIT_MODE_OFF   0x0000
00201 #define T6_32BIT_MODE_MASK   (~T6_32BIT_MODE_ON)
00202 
00203 #define T6_SOURCE_EXT       0x0002 /* External clock source */
00204 #define T6_SOURCE_INT       0x0000 /* Internal clock source */
00205 #define T6_SOURCE_MASK      (~T6_SOURCE_EXT)
00206 #endif
00207 
00208 #ifdef _T7IF
00209 /* T7CON: TIMER7 CONTROL REGISTER */
00210 #define T7_ON               0x8000      /* Timer7 ON */
00211 #define T7_OFF              0x0000      /* Timer7 OFF */
00212 #define T7_OFF_ON_MASK      (~T7_ON)
00213 
00214 #define T7_IDLE_STOP        0x2000 /* operate during sleep */
00215 #define T7_IDLE_CON         0x0000 /* stop operation during sleep */
00216 #define T7_IDLE_MASK        (~T7_IDLE_STOP)
00217 
00218 #define T7_GATE_ON          0x0040 /* Timer Gate time accumulation enabled */
00219 #define T7_GATE_OFF         0x0000 /* Timer Gate time accumulation disabled */
00220 #define T7_GATE_MASK        (~T7_GATE_ON)
00221 
00222 #define T7_PS_1_1           0x0000      /* Prescaler 1:1 */
00223 #define T7_PS_1_8           0x0010      /*           1:8 */
00224 #define T7_PS_1_64          0x0020      /*          1:64 */
00225 #define T7_PS_1_256         0x0030      /*         1:256 */
00226 #define T7_PS_MASK          (~T7_PS_1_256)
00227 
00228 #define T7_SOURCE_EXT       0x0002 /* External clock source */
00229 #define T7_SOURCE_INT       0x0000 /* Internal clock source */
00230 #define T7_SOURCE_MASK      (~T7_SOURCE_EXT)
00231 #endif
00232 
00233 #ifdef _T8IF
00234 /* T8CON: TIMER8 CONTROL REGISTER */
00235 #define T8_ON               0x8000      /* Timer8 ON */
00236 #define T8_OFF              0x0000      /* Timer8 OFF */
00237 #define T8_OFF_ON_MASK      (~T8_ON)
00238 
00239 #define T8_IDLE_STOP        0x2000 /* operate during sleep */
00240 #define T8_IDLE_CON         0x0000 /* stop operation during sleep */
00241 #define T8_IDLE_MASK        (~T8_IDLE_STOP)
00242 
00243 #define T8_GATE_ON          0x0040 /* Timer Gate time accumulation enabled */
00244 #define T8_GATE_OFF         0x0000 /* Timer Gate time accumulation disabled */
00245 #define T8_GATE_MASK        (~T8_GATE_ON)
00246 
00247 #define T8_PS_1_1           0x0000      /* Prescaler 1:1 */
00248 #define T8_PS_1_8           0x0010      /*           1:8 */
00249 #define T8_PS_1_64          0x0020      /*          1:64 */
00250 #define T8_PS_1_256         0x0030      /*         1:256 */
00251 #define T8_PS_MASK          (~T8_PS_1_256)
00252 
00253 #define T8_32BIT_MODE_ON    0x0008      /* Timer 8 and Timer 9 form a 32 bit Timer */
00254 #define T8_32BIT_MODE_OFF   0x0000
00255 #define T8_32BIT_MODE_MASK   (~T8_32BIT_MODE_ON)
00256 
00257 #define T8_SOURCE_EXT       0x0002 /* External clock source */
00258 #define T8_SOURCE_INT       0x0000 /* Internal clock source */
00259 #define T8_SOURCE_MASK      (~T8_SOURCE_EXT)
00260 #endif
00261 
00262 #ifdef _T9IF
00263 /* T9CON: TIMER9 CONTROL REGISTER */
00264 #define T9_ON               0x8000      /* Timer9 ON */
00265 #define T9_OFF              0x0000      /* Timer9 OFF */
00266 #define T9_OFF_ON_MASK      (~T9_ON)
00267 
00268 #define T9_IDLE_STOP        0x2000 /* operate during sleep */
00269 #define T9_IDLE_CON         0x0000 /* stop operation during sleep */
00270 #define T9_IDLE_MASK        (~T9_IDLE_STOP)
00271 
00272 #define T9_GATE_ON          0x0040 /* Timer Gate time accumulation enabled */
00273 #define T9_GATE_OFF         0x0000 /* Timer Gate time accumulation disabled */
00274 #define T9_GATE_MASK        (~T9_GATE_ON)
00275 
00276 #define T9_PS_1_1           0x0000      /* Prescaler 1:1 */
00277 #define T9_PS_1_8           0x0010      /*           1:8 */
00278 #define T9_PS_1_64          0x0020      /*          1:64 */
00279 #define T9_PS_1_256         0x0030      /*         1:256 */
00280 #define T9_PS_MASK          (~T9_PS_1_256)
00281 
00282 #define T9_SOURCE_EXT       0x0002 /* External clock source */
00283 #define T9_SOURCE_INT       0x0000 /* Internal clock source */
00284 #define T9_SOURCE_MASK      (~T9_SOURCE_EXT)
00285 #endif
00286 
00287 //Input Capture macros
00288 
00289 /*
00290 The following macros are a subset of the AND/OR macros found in the
00291 the MPLAB C30/src/peripheral_24F/incap.h file and placed
00292 in this header for use solely and exclusively on Microchip
00293 PICmicro Microcontroller products as
00294 specified in the MPLAB C30/src/peripheral_24F/incap.h header.
00295 */
00296 
00297 #define IC_IDLE_STOP            0x2000 /* IC stop in sleep mode */
00298 #define IC_IDLE_CON             0x0000 /* IC operate in sleep mode */
00299 #define IC_IDLE_MASK            (~IC_IDLE_STOP)
00300 
00301 #define IC_TIMER2_SRC           0x0080 /* Timer2 is the clock source for Capture */
00302 #define IC_TIMER3_SRC           0x0000 /* Timer3 is the clock source for Capture */
00303 #define IC_TIMER_SRC_MASK       (~IC_TIMER2_SRC)
00304 
00305 #define IC_INT_4CAPTURE         0x0060  /* Interrupt on fourth Capture*/
00306 #define IC_INT_3CAPTURE         0x0040 /* Interrupt on third Capture */
00307 #define IC_INT_2CAPTURE         0x0020 /* Interrupt on second Capture*/
00308 #define IC_INT_1CAPTURE         0x0000 /* Interrupt on first Capture */
00309 #define IC_INT_CAPTURE_MASK     (~IC_INT_4CAPTURE)
00310 
00311 #define IC_INTERRUPT            0x0007 /* Interrupt pin only in CPU sleep and idle mode */
00312 #define IC_EVERY_16_RISE_EDGE   0x0005 /* Every 16th rising edge */
00313 #define IC_EVERY_4_RISE_EDGE    0x0004 /* Every 4th rising edge  */
00314 #define IC_EVERY_RISE_EDGE      0x0003 /* Every rising edge      */
00315 #define IC_EVERY_FALL_EDGE      0x0002 /* Every falling edge      */
00316 #define IC_EVERY_EDGE           0x0001 /* Every rising/falling edge */
00317 #define IC_INPUTCAP_OFF         0x0000 /* Input Capture Off      */
00318 #define IC_CAPTURE_MODE_MASK    (~IC_INTERRUPT)
00319 
00320 //Output Compare macros
00321 
00322 /*
00323 The following macros are a subset of the AND/OR macros found in the
00324 the MPLAB C30/src/peripheral_24F/outcompare.h file and placed
00325 in this header for use solely and exclusively on Microchip
00326 PICmicro Microcontroller products as
00327 specified in the MPLAB C30/src/peripheral_24F/outcompare.h header.
00328 */
00329 
00330 /* Section : Output Compare Stop in Idle mode Bit defines */
00331 #define OC_IDLE_CON                0x0000 /*  continue operation in idle mode */
00332 #define OC_IDLE_STOP               0x2000 /* stop in idle mode */
00333 #define OC_IDLE_MASK               (~OC_IDLE_STOP)
00334 
00335 /*Section :  Output Compare timer select Bit Defines */
00336 #define OC_TIMER2_SRC               0x0000 /* Timer2 is the clock source for OutputCompare */
00337 #define OC_TIMER3_SRC               0x0008 /* Timer3 is the clock source for OutputCompare */
00338 #define OC_TIMER_SRC_MASK           (~OC_TIMER3_SRC)
00339 
00340 #define OC_PWM_FAULT_PIN_ENABLE     0x0007 /* PWM Mode on OCx, fault pin enabled, (TxIF bit is set for PWM, OCxIF is set for fault)*/
00341 #define OC_PWM_FAULT_PIN_DISABLE    0x0006 /* PWM Mode on OCx, fault pin disabled */
00342 #define OC_CONTINUE_PULSE           0x0005 /* Generates Continuous Output pulse on OCx Pin */
00343 #define OC_SINGLE_PULSE             0x0004 /* Generates Single Output pulse on OCx Pin */
00344 #define OC_TOGGLE_PULSE             0x0003 /* Compare1 toggles  OCx pin*/
00345 #define OC_HIGH_LOW                 0x0002 /* Compare1 forces   OCx pin Low*/
00346 #define OC_LOW_HIGH                 0x0001 /* Compare1 forces  OCx pin High*/
00347 #define OC_OFF                      0x0000 /* OutputCompare x Off*/
00348 #define OC_PWM_MODE_MASK            (~OC_PWM_FAULT_PIN_ENABLE)
00349 
00350 
00351 #endif
00352 

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