How do we decode errors before they become computation?
Designing decoding architectures and pipelines — MWPM, Union-Find, and belief propagation — for low-latency, resource-aware FPGA deployment.
Hi, I’m Sai.
I started in computer science and kept chasing problems closer to the machine — until quantum hardware caught me. What I love is the narrow gap between an elegant algorithm and the silicon that has to run it on a real-time deadline, where physics, maths, and engineering are all forced to agree. I graduated my M.Tech in Quantum Technology at IISc, with distinction.
What keeps me curious
I began in computer science, moving through networks, optimisation, sensing, and quantum computing. The common thread is clear: I’m happiest when I can learn very different parts of a problem and bring them together into one working system.
Designing decoding architectures and pipelines — MWPM, Union-Find, and belief propagation — for low-latency, resource-aware FPGA deployment.
Hardware-optimised tensor-network kernels mapped onto parameterised systolic fabrics, with explicit timing, resource, and precision trade-offs.
Automating transmon characterisation and benchmarking quantum functions across fidelity, runtime, and noise sensitivity.
How I got here
I did not begin with a fixed plan to work on quantum hardware. I followed the problems that kept pulling me closer to the machine.
At Amrita Vishwa Vidyapeetham I fell for algorithms, systems, and machine learning — the habits of thinking that still shape how I work today. I left as college gold medallist.
B.Tech Computer Science · Amritapuri · Gold MedalAmrita, IIT Kanpur, Penn State, and IIIT Hyderabad took me through complex networks, sensing, scheduling, and bandit algorithms. Each lab taught me another way to ask whether an idea actually works.
Four labs · several ways of seeingMy M.Tech drew the threads together — algorithms, physical noise, and hardware limits. An internship at IBM Quantum let me probe real backends with benchmarking and adversarial circuits. I graduated with distinction.
M.Tech Quantum Technology · IISc · DistinctionI joined SINESys Lab as a Research Assistant to keep building: decoding architectures and pipelines for quantum error correction, and hardware optimisations for simulating quantum dynamics — where nanoseconds and DSP slices become part of the algorithm.
SINESys Lab · DESE · IIScWhere the foundations were laid
The numbers matter less than what they made possible — but here they are, in their proper place.
Indian Institute of Science (IISc), Bengaluru
Quantum error correction, hardware-aware algorithms, and the architectures that run them.
Amrita Vishwa Vidyapeetham, Amritapuri
Algorithms, systems, networks, and machine learning — the grounding for everything since.
What I actually do
Surface codes, syndrome extraction, and logical-error analysis with Stim.
MWPM, Union-Find & belief propagation — as algorithms and as pipelines.
Verilog RTL, Vitis HLS, ASIC/FPGA flows, timing- and resource-aware design.
Tensor-network dynamics, Qiskit, and hardware-optimised simulation kernels.
Randomised & approximation algorithms, scheduling, bandits, complexity.
Calibration, sensing, and link prediction with TensorFlow & scikit-learn.
Python · C / C++ · Java · Scala · Haskell · SQL
Verilog · Vitis HLS · Vivado · LLVM / MLIR · 45 nm ASIC
Qiskit · Stim · PyVISA · cavity-QED fitting
TensorFlow · Keras · scikit-learn · Django · React · PyQt6 · REST
The pattern I recognise now
My two theses look unrelated at first: one is quantum decoder hardware, the other a social movie game. What connects them is the kind of work I gravitate toward — crossing layers, comparing approaches, and making the pieces meet in a complete system.
Individual thesis · Quantum Technology · Indian Institute of Science · Distinction
I studied surface-code decoding from two connected viewpoints: whether an algorithm suppresses logical errors, and whether its hardware can meet a real-time latency budget.
MWPM, Union-Find, and belief propagation · Stim-based logical-error studies · profiling-driven kernel selection · verified Verilog RTL · 45 nm ASIC synthesis · ZCU104 FPGA implementation · Vitis HLS comparison
The central lesson: accuracy and speed must be measured separately, then combined honestly. Fewer cycles do not mean faster hardware if the critical path destroys the clock.
Read the M.Tech thesis ↗Team thesis · Computer Science & Engineering · Amrita Vishwa Vidyapeetham
We began with a simple human goal: help friends have a good time together. Building the game meant creating the entire path from raw movie data to a playable web experience.
Web scraping and public datasets · NLP keyword-extractor benchmarking · image processing and object detection · similarity mapping · Django application architecture · cloud deployment
What I learned: integration is its own kind of problem solving. A clever component matters only when it fits the data, the interface, and the person using it.
Read the B.Tech thesis ↗What I’ve been building
Results stay with the work that produced them. This is where the numbers, trade-offs, and technical detail belong.
SINESys Lab · DESE · IISc
A combined algorithm-and-hardware study of MWPM, Union-Find, and belief-propagation decoders across logical error rate, wall-clock latency, code-distance scaling, and hardware cost — built as reusable pipelines from syndrome to correction.
Course project · IISc
Parameterised 4×4 to 32×32 GEMM fabric on Xilinx ZCU104, joining Verilog compute cores to a Vitis HLS tensor-network layer for hardware-accelerated dynamics.
IBM Quantum
An implementation-benchmarking suite for Qiskit Functions, and an evolutionary search that breeds adversarial circuits to maximise error across hardware backends.
Experience record
Implementation-benchmarking suite for Qiskit Functions; evolutionary search for adversarial circuits that maximise error across hardware backends.
Multi-objective scheduling theory and delay-aware multi-arm bandit optimisation for a large recommendation system.
Deep-learning calibration for 2D-semiconductor chemical sensors; neuromorphic CSP algorithms for 2D devices.
Quicksort implementation profiling and a stable-matching algorithm for departmental TA allocation.
Link prediction with SBMs and MLE in complex networks; influential-node identification via mPageRank.
Things I’ve built
Beyond the research — tools, hackathon builds, and applications taken end-to-end.
Transmon Reliability, Automated Characterisation & Estimation for Qubits. A lab-instrument GUI that fits VNA/IQ data to extract internal quality factor, anharmonicity, and dispersive shifts automatically.
A Windows desktop client that layers Quantum Key Distribution over ordinary email. Application-layer encryption for messages and attachments with REST-based key management — post-quantum secure mail.
An online multiplayer trivia where players guess movies from generated image clues. Full pipeline: web-scraped datasets, NLP keyword extraction, similarity mapping, a Django backend, and a React front end.
Predicting links in directed and multiplex social networks using stochastic block models, MAP estimation over motifs, and m-PageRank influence clustering — the basis of three publications.
Shipped & online right now
Self-hosted side projects — deployed, public, and serving traffic as you read this.
A medieval-styled research journal — projects, journal entries, tasks, meetings, and materials, bound together like an illuminated manuscript for modern research.
A “Solo Leveling”-inspired learning RPG. Turn studying into quests, gain XP, level up, and watch your stats climb — a void-black, gamified system for self-driven learning.
This very site — nasapakri.com — hand-built and self-hosted on Cloud Storage with an HTTPS load balancer, managed SSL, and a global CDN.
nasapakri.com ↗A few things I’m proud of
These mark parts of the journey. They are not substitutes for the work above.
The rank that brought me to IISc and into quantum technology.
A long-standing love for competitive algorithms and problem solving.
Among the teams advancing through the ACM-ICPC regionals.
My first immersive summer research experience.
Writing & evidence
Peer-reviewed work in complex networks, information extraction, and directed motifs.
BDCC · 2023 · 7(1), 31
PiCET · 2024
ISTA · 2023 · Accepted
Research is a community practice
Teaching Assistant at IISc, supporting tutorials and mentoring students through the mathematical foundations of quantum computation.
Aug 2025—PresentLed a five-member team across speaker invitations, session delivery, logistics, and hackathon judging for the IBM Quantum / IQTI / QuRP-sponsored event.
Lead organiser · 2025Representing the M.Tech cohort, running the IAP seminar series, and coordinating student-wellness initiatives through SWAN.
IISc · 2024—PresentIf our questions overlap
I’m always happy to talk about quantum error correction, decoding architectures, hardware-aware algorithms, FPGA acceleration, teaching, or a possible research collaboration.