ONHS Report: 26S1358

STATE OF THE ART (SOTA) MICROELECTRONICS (ME) ADOPTION BROAD AGENCY ANNOUNCEMENT (BAA) FULL TEXT GENERAL ANNOUNCEMENT

Solicitation ID: 26S1358

Agency: SAF/AQC

Type: Special Notice

Deadline: N/A

Eligibility: Maybe (Topic Dependent)

Funding: N/A

Doc Type: BAA

Clearance: Secret

Program Manager: matthew.karijolic@us.af.mil

Last Updated: 2026-06-24 19:06

Analyzed File: API_Description.txt

Eligibility Reasoning

No proposals or White Papers shall be submitted against this BAA general announcement. Proposal or White Paper due dates and times will be specified in each individual Topic Call.

Note: This is an AI-generated summary...

Summary

[Analyzed from API Fallback] This document is a general Broad Agency Announcement (BAA) for the 'State of the Art (SOTA) Microelectronics (ME) Adoption' program (26-S-1358) from SAF/AQC. It establishes a framework for future funding opportunities and does not accept proposals itself. Instead, specific requirements will be detailed in separate 'Topic Calls' issued on SAM.gov. The program's goal is to accelerate the US Government's adoption of trusted, state-of-the-art domestic microelectronics, with a focus on Intel 18A technology and advanced packaging. The BAA outlines five key mission areas for potential research: 1) Advanced & Secure Microelectronics Design and Production; 2) Next-Generation Assembly, Packaging, and Test; 3) Novel Microelectronics for Disruptive USG Capabilities; 4) Advanced Test, Validation, and Mission Qualification; and 5) building an Accessible & Affordable Microelectronics Ecosystem. Awards under future Topic Calls may be procurement contracts or Other Transaction Agreements (OTAs). Only U.S. organizations are eligible to participate.

Overall Technical Areas

Microelectronics Design (Analog/Digital)AI/ML Hardware ArchitecturesSecure Electronic Design Automation (EDA)Radiation-Hardened by Design (RHBD)Chiplet-Based & System-in-Package (SiP) DesignAdvanced Microelectronics PackagingHeterogeneous Integration (2.5D/3D)Secure SoC and SiP Test MethodologiesMicroelectronics Thermal ManagementHigh-Performance Edge ComputingNext-Generation RF & Mixed-Signal ElectronicsHardware Acceleration for CryptographyResilient PNT MicroelectronicsMicroelectronics Security VerificationDigital Twin Frameworks for Microelectronics

Probable LBNL Areas

CSAESAETAPSA

Focus Areas

Example Priorities:

Novel architectures for artificial intelligence (AI) and/or machine learning (ML), signal processing, and other functions at the tactical edge.
Development of secure design methodologies and Electronic Design Automation (EDA) tools that prevent the insertion of malicious hardware.
Radiation-hardened by design (RHBD) techniques for space and strategic applications.
Exploration of chiplet-based and System-in-Package (SiP) designs for rapid and modular system development.

Specific Technical Skills:

Microelectronics DesignAI/ML ArchitecturesSecure Design MethodologiesElectronic Design Automation (EDA)Hardware SecurityRadiation-Hardened by Design (RHBD)Chiplet ArchitectureSystem-in-Package (SiP) DesignDigital and Analog DesignSignal Processing

Potential PIs for this Area:

Name	Score	Organization
Hasita Veluri	0.72	CSA \| AMCR \| Computer Science
Aikaterini Papadopoulou	0.70	PSA \| Engineering \| Electronic Engineering
Georgios Michelogiannakis	0.70	CSA \| AMCR \| Computer Science
Meriam Gay Bautista-Jurney	0.70	CSA \| AMCR \| Computer Science
Jason Lowe-Power	0.69	CSA \| SciData \| Data Science Applications
Luisa Gonzalez	0.69	CSA \| AMCR \| Computer Science
Jyothisraj Johnson	0.69	PSA \| Engineering \| Electronic Engineering
Nirmalendu Patra	0.69	CSA \| AMCR \| Computer Science
Farzad Fatollahi-Fard	0.69	CSA \| AMCR \| Computer Science
Venkatesh Akella	0.69	CSA \| SciData \| Data Science Applications

Example Priorities:

Advanced packaging techniques, including 2D, 2.5D/3D heterogeneous integration, for combining different technologies (e.g., logic, memory, RF) into a single, compact system.
Automated and secure test methodologies for complex SoCs and SiPs to identify defects and hidden logic.
Methods for non-destructively verifying the integrity and security of packaged components.
Thermal management solutions for high-power and densely packaged microelectronics.

Specific Technical Skills:

Advanced Packaging3D Heterogeneous IntegrationSystem-on-Chip (SoC) TestingSystem-in-Package (SiP) TestingAutomated Test MethodologiesHardware Security VerificationNon-Destructive EvaluationThermal ManagementMicroelectronics AssemblyPost-Fabrication Processes

Potential PIs for this Area:

Name	Score	Organization
Asir Intisar Khan	0.69	ESA \| MSD \| Material Physics
Luisa Gonzalez	0.69	CSA \| AMCR \| Computer Science
Chris Anderson	0.68	ESA \| MSD \| Center for X-Ray Optics
Dipak Ghosal	0.68	CSA \| ESNET \| Tech Adv and Engagement
Jason Lowe-Power	0.68	CSA \| SciData \| Data Science Applications
Zhi Yao	0.68	CSA \| AMCR \| Applied Mathematics
Roya Maboudian	0.68	ESA \| MF \| MF Inorganic Facility
Hasita Veluri	0.68	CSA \| AMCR \| Computer Science
Michael Chin	0.68	PSA \| Engineering \| Electronic Engineering
Aikaterini Papadopoulou	0.68	PSA \| Engineering \| Electronic Engineering

Example Priorities:

Low-power, high-performance edge computing for systems, and on-platform sensor fusion.
Next-generation RF and mixed-signal electronics for advanced communications, electronic warfare (EW), and C5ISR.
Hardware accelerators for real-time data analysis, cryptography, and secure computation.
Microelectronics for resilient positioning, navigation, and timing (PNT).

Specific Technical Skills:

Edge ComputingSensor FusionRF ElectronicsMixed-Signal ElectronicsElectronic Warfare (EW)C5ISR SystemsHardware AccelerationCryptographyResilient PNTLow-Power Design

Potential PIs for this Area:

Name	Score	Organization
Venkatesh Akella	0.70	CSA \| SciData \| Data Science Applications
Nirmalendu Patra	0.70	CSA \| AMCR \| Computer Science
Jason Lowe-Power	0.70	CSA \| SciData \| Data Science Applications
Hasita Veluri	0.69	CSA \| AMCR \| Computer Science
Meriam Gay Bautista-Jurney	0.69	CSA \| AMCR \| Computer Science
Dipak Ghosal	0.69	CSA \| ESNET \| Tech Adv and Engagement
Stijn (Stan) Wielandt	0.69	PSA \| Engineering \| Electronic Engineering
Daniel Gerber	0.69	ETA \| Building Tech. & Urban Sys. \| Bldg Technologies Dept
Christopher Tracy	0.69	CSA \| ESNET \| Tech Adv and Engagement
Lavanya Ramakrishnan	0.68	CSA \| SciData \| Data Science Applications

Example Priorities:

High-throughput security verification techniques
Development of test environments that emulate mission-specific conditions (e.g., radiation, extreme temperatures, vibration).
Standardized benchmarking processes and "test vehicles" for objectively comparing SOTA process nodes.
The objective is to build trust in these components and create a clear pathway for their qualification for insertion into critical USG systems.

Specific Technical Skills:

Security VerificationTest Environment EmulationMission-Specific TestingMicroelectronics ReliabilityPerformance BenchmarkingTest Vehicle DesignSOTA Process ValidationMission QualificationSystem ValidationIntel 18A Process

Potential PIs for this Area:

Name	Score	Organization
Jason Lowe-Power	0.70	CSA \| SciData \| Data Science Applications
Hasita Veluri	0.69	CSA \| AMCR \| Computer Science
Meriam Gay Bautista-Jurney	0.69	CSA \| AMCR \| Computer Science
Nirmalendu Patra	0.69	CSA \| AMCR \| Computer Science
Scott Beamer	0.68	CSA \| AMCR \| Computer Science
Aikaterini Papadopoulou	0.68	PSA \| Engineering \| Electronic Engineering
Luisa Gonzalez	0.68	CSA \| AMCR \| Computer Science
Michael Chin	0.68	PSA \| Engineering \| Electronic Engineering
Russell Wilcox	0.68	PSA \| Engineering \| Electronic Engineering
Venkatesh Akella	0.68	CSA \| SciData \| Data Science Applications

Example Priorities:

Establishment of a USG-curated chiplet library based on open standards (e.g., UCIe) to enable rapid, modular system design.
Novel acquisition and business models for aggregating demand across multiple programs to reduce per-unit costs.
Development of "digital twin" frameworks for microelectronic systems to improve sustainment, modernization planning, and lifecycle management.
Shared infrastructure models for access to common Intellectual Property (IP) blocks and secure Electronic Design Automation (EDA) tools, reducing duplicative costs for individual programs.

Specific Technical Skills:

Ecosystem DevelopmentChiplet Libraries (UCIe)Digital Twin FrameworksSupply Chain ManagementAcquisition StrategyDemand AggregationIntellectual Property (IP) ManagementOpen StandardsLifecycle ManagementModular System Design

Potential PIs for this Area:

Name	Score	Organization
Alex Newkirk	0.70	ETA \| Building Tech. & Urban Sys. \| Bldg & Industrial App Dpt
Nirmalendu Patra	0.69	CSA \| AMCR \| Computer Science
Jason Lowe-Power	0.69	CSA \| SciData \| Data Science Applications
Georgios Michelogiannakis	0.69	CSA \| AMCR \| Computer Science
Cynthia Regnier	0.68	ETA \| Building Tech. & Urban Sys. \| Whole Building Sys Dept
Aikaterini Papadopoulou	0.68	PSA \| Engineering \| Electronic Engineering
Luisa Gonzalez	0.68	CSA \| AMCR \| Computer Science
Dipak Ghosal	0.68	CSA \| ESNET \| Tech Adv and Engagement
Anastasiia Butko	0.68	CSA \| AMCR \| Computer Science
Meriam Gay Bautista-Jurney	0.68	CSA \| AMCR \| Computer Science

Potential LBNL PIs (Overall)

Note on PI Matching: These suggestions are generated through an AI-driven semantic analysis of LBNL staff profiles.

Name	Score	Organization
Luisa Gonzalez	0.77	CSA \| AMCR \| Computer Science · AI/ML Hardware Architectures
Venkatesh Akella	0.75	CSA \| SciData \| Data Science Applications · High-Performance Edge Computing
Panagiotis Zarkos	0.75	PSA \| Engineering \| Electronic Engineering · Microelectronics Design (Analog/Digital)
Georgios Michelogiannakis	0.75	CSA \| AMCR \| Computer Science · Chiplet-Based & System-in-Package (SiP) Design
Angelos Ioannou	0.75	CSA \| AMCR \| Computer Science · Hardware Acceleration for Cryptography
Jason Lowe-Power	0.74	CSA \| SciData \| Data Science Applications · Secure Electronic Design Automation (EDA)
Asir Intisar Khan	0.74	ESA \| MSD \| Material Physics · Heterogeneous Integration (2.5D/3D)
Dario Gnani	0.74	PSA \| Engineering \| Electronic Engineering · Radiation-Hardened by Design (RHBD)
Zhi Jackie Yao	0.73	CSA \| AMCR \| Applied Mathematics · Digital Twin Frameworks for Microelectronics
Ravi Prasher	0.73	ETA \| ESDR \| Energy Storage & Dist Dpt · Microelectronics Thermal Management

Fundamental Research Exemption (FRE)

Not Mentioned