Coverage Report

Created: 2023-08-28 06:23

/src/binutils-gdb/opcodes/arm-dis.c
Line
Count
Source (jump to first uncovered line)
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/* Instruction printing code for the ARM
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   Copyright (C) 1994-2023 Free Software Foundation, Inc.
3
   Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4
   Modification by James G. Smith (jsmith@cygnus.co.uk)
5
6
   This file is part of libopcodes.
7
8
   This library is free software; you can redistribute it and/or modify
9
   it under the terms of the GNU General Public License as published by
10
   the Free Software Foundation; either version 3 of the License, or
11
   (at your option) any later version.
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13
   It is distributed in the hope that it will be useful, but WITHOUT
14
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
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   License for more details.
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18
   You should have received a copy of the GNU General Public License
19
   along with this program; if not, write to the Free Software
20
   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21
   MA 02110-1301, USA.  */
22
23
#include "sysdep.h"
24
#include <assert.h>
25
26
#include "disassemble.h"
27
#include "opcode/arm.h"
28
#include "opintl.h"
29
#include "safe-ctype.h"
30
#include "libiberty.h"
31
#include "floatformat.h"
32
33
/* FIXME: This shouldn't be done here.  */
34
#include "coff/internal.h"
35
#include "libcoff.h"
36
#include "bfd.h"
37
#include "elf-bfd.h"
38
#include "elf/internal.h"
39
#include "elf/arm.h"
40
#include "mach-o.h"
41
42
/* Cached mapping symbol state.  */
43
enum map_type
44
{
45
  MAP_ARM,
46
  MAP_THUMB,
47
  MAP_DATA
48
};
49
50
struct arm_private_data
51
{
52
  /* The features to use when disassembling optional instructions.  */
53
  arm_feature_set features;
54
55
  /* Track the last type (although this doesn't seem to be useful) */
56
  enum map_type last_type;
57
58
  /* Tracking symbol table information */
59
  int last_mapping_sym;
60
61
  /* The end range of the current range being disassembled.  */
62
  bfd_vma last_stop_offset;
63
  bfd_vma last_mapping_addr;
64
};
65
66
enum mve_instructions
67
{
68
  MVE_VPST,
69
  MVE_VPT_FP_T1,
70
  MVE_VPT_FP_T2,
71
  MVE_VPT_VEC_T1,
72
  MVE_VPT_VEC_T2,
73
  MVE_VPT_VEC_T3,
74
  MVE_VPT_VEC_T4,
75
  MVE_VPT_VEC_T5,
76
  MVE_VPT_VEC_T6,
77
  MVE_VCMP_FP_T1,
78
  MVE_VCMP_FP_T2,
79
  MVE_VCMP_VEC_T1,
80
  MVE_VCMP_VEC_T2,
81
  MVE_VCMP_VEC_T3,
82
  MVE_VCMP_VEC_T4,
83
  MVE_VCMP_VEC_T5,
84
  MVE_VCMP_VEC_T6,
85
  MVE_VDUP,
86
  MVE_VEOR,
87
  MVE_VFMAS_FP_SCALAR,
88
  MVE_VFMA_FP_SCALAR,
89
  MVE_VFMA_FP,
90
  MVE_VFMS_FP,
91
  MVE_VHADD_T1,
92
  MVE_VHADD_T2,
93
  MVE_VHSUB_T1,
94
  MVE_VHSUB_T2,
95
  MVE_VRHADD,
96
  MVE_VLD2,
97
  MVE_VLD4,
98
  MVE_VST2,
99
  MVE_VST4,
100
  MVE_VLDRB_T1,
101
  MVE_VLDRH_T2,
102
  MVE_VLDRB_T5,
103
  MVE_VLDRH_T6,
104
  MVE_VLDRW_T7,
105
  MVE_VSTRB_T1,
106
  MVE_VSTRH_T2,
107
  MVE_VSTRB_T5,
108
  MVE_VSTRH_T6,
109
  MVE_VSTRW_T7,
110
  MVE_VLDRB_GATHER_T1,
111
  MVE_VLDRH_GATHER_T2,
112
  MVE_VLDRW_GATHER_T3,
113
  MVE_VLDRD_GATHER_T4,
114
  MVE_VLDRW_GATHER_T5,
115
  MVE_VLDRD_GATHER_T6,
116
  MVE_VSTRB_SCATTER_T1,
117
  MVE_VSTRH_SCATTER_T2,
118
  MVE_VSTRW_SCATTER_T3,
119
  MVE_VSTRD_SCATTER_T4,
120
  MVE_VSTRW_SCATTER_T5,
121
  MVE_VSTRD_SCATTER_T6,
122
  MVE_VCVT_FP_FIX_VEC,
123
  MVE_VCVT_BETWEEN_FP_INT,
124
  MVE_VCVT_FP_HALF_FP,
125
  MVE_VCVT_FROM_FP_TO_INT,
126
  MVE_VRINT_FP,
127
  MVE_VMOV_HFP_TO_GP,
128
  MVE_VMOV_GP_TO_VEC_LANE,
129
  MVE_VMOV_IMM_TO_VEC,
130
  MVE_VMOV_VEC_TO_VEC,
131
  MVE_VMOV2_VEC_LANE_TO_GP,
132
  MVE_VMOV2_GP_TO_VEC_LANE,
133
  MVE_VMOV_VEC_LANE_TO_GP,
134
  MVE_VMVN_IMM,
135
  MVE_VMVN_REG,
136
  MVE_VORR_IMM,
137
  MVE_VORR_REG,
138
  MVE_VORN,
139
  MVE_VBIC_IMM,
140
  MVE_VBIC_REG,
141
  MVE_VMOVX,
142
  MVE_VMOVL,
143
  MVE_VMOVN,
144
  MVE_VMULL_INT,
145
  MVE_VMULL_POLY,
146
  MVE_VQDMULL_T1,
147
  MVE_VQDMULL_T2,
148
  MVE_VQMOVN,
149
  MVE_VQMOVUN,
150
  MVE_VADDV,
151
  MVE_VMLADAV_T1,
152
  MVE_VMLADAV_T2,
153
  MVE_VMLALDAV,
154
  MVE_VMLAS,
155
  MVE_VADDLV,
156
  MVE_VMLSDAV_T1,
157
  MVE_VMLSDAV_T2,
158
  MVE_VMLSLDAV,
159
  MVE_VRMLALDAVH,
160
  MVE_VRMLSLDAVH,
161
  MVE_VQDMLADH,
162
  MVE_VQRDMLADH,
163
  MVE_VQDMLAH,
164
  MVE_VQRDMLAH,
165
  MVE_VQDMLASH,
166
  MVE_VQRDMLASH,
167
  MVE_VQDMLSDH,
168
  MVE_VQRDMLSDH,
169
  MVE_VQDMULH_T1,
170
  MVE_VQRDMULH_T2,
171
  MVE_VQDMULH_T3,
172
  MVE_VQRDMULH_T4,
173
  MVE_VDDUP,
174
  MVE_VDWDUP,
175
  MVE_VIWDUP,
176
  MVE_VIDUP,
177
  MVE_VCADD_FP,
178
  MVE_VCADD_VEC,
179
  MVE_VHCADD,
180
  MVE_VCMLA_FP,
181
  MVE_VCMUL_FP,
182
  MVE_VQRSHL_T1,
183
  MVE_VQRSHL_T2,
184
  MVE_VQRSHRN,
185
  MVE_VQRSHRUN,
186
  MVE_VQSHL_T1,
187
  MVE_VQSHL_T2,
188
  MVE_VQSHLU_T3,
189
  MVE_VQSHL_T4,
190
  MVE_VQSHRN,
191
  MVE_VQSHRUN,
192
  MVE_VRSHL_T1,
193
  MVE_VRSHL_T2,
194
  MVE_VRSHR,
195
  MVE_VRSHRN,
196
  MVE_VSHL_T1,
197
  MVE_VSHL_T2,
198
  MVE_VSHL_T3,
199
  MVE_VSHLC,
200
  MVE_VSHLL_T1,
201
  MVE_VSHLL_T2,
202
  MVE_VSHR,
203
  MVE_VSHRN,
204
  MVE_VSLI,
205
  MVE_VSRI,
206
  MVE_VADC,
207
  MVE_VABAV,
208
  MVE_VABD_FP,
209
  MVE_VABD_VEC,
210
  MVE_VABS_FP,
211
  MVE_VABS_VEC,
212
  MVE_VADD_FP_T1,
213
  MVE_VADD_FP_T2,
214
  MVE_VADD_VEC_T1,
215
  MVE_VADD_VEC_T2,
216
  MVE_VSBC,
217
  MVE_VSUB_FP_T1,
218
  MVE_VSUB_FP_T2,
219
  MVE_VSUB_VEC_T1,
220
  MVE_VSUB_VEC_T2,
221
  MVE_VAND,
222
  MVE_VBRSR,
223
  MVE_VCLS,
224
  MVE_VCLZ,
225
  MVE_VCTP,
226
  MVE_VMAX,
227
  MVE_VMAXA,
228
  MVE_VMAXNM_FP,
229
  MVE_VMAXNMA_FP,
230
  MVE_VMAXNMV_FP,
231
  MVE_VMAXNMAV_FP,
232
  MVE_VMAXV,
233
  MVE_VMAXAV,
234
  MVE_VMIN,
235
  MVE_VMINA,
236
  MVE_VMINNM_FP,
237
  MVE_VMINNMA_FP,
238
  MVE_VMINNMV_FP,
239
  MVE_VMINNMAV_FP,
240
  MVE_VMINV,
241
  MVE_VMINAV,
242
  MVE_VMLA,
243
  MVE_VMUL_FP_T1,
244
  MVE_VMUL_FP_T2,
245
  MVE_VMUL_VEC_T1,
246
  MVE_VMUL_VEC_T2,
247
  MVE_VMULH,
248
  MVE_VRMULH,
249
  MVE_VNEG_FP,
250
  MVE_VNEG_VEC,
251
  MVE_VPNOT,
252
  MVE_VPSEL,
253
  MVE_VQABS,
254
  MVE_VQADD_T1,
255
  MVE_VQADD_T2,
256
  MVE_VQSUB_T1,
257
  MVE_VQSUB_T2,
258
  MVE_VQNEG,
259
  MVE_VREV16,
260
  MVE_VREV32,
261
  MVE_VREV64,
262
  MVE_LSLL,
263
  MVE_LSLLI,
264
  MVE_LSRL,
265
  MVE_ASRL,
266
  MVE_ASRLI,
267
  MVE_SQRSHRL,
268
  MVE_SQRSHR,
269
  MVE_UQRSHL,
270
  MVE_UQRSHLL,
271
  MVE_UQSHL,
272
  MVE_UQSHLL,
273
  MVE_URSHRL,
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  MVE_URSHR,
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  MVE_SRSHRL,
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  MVE_SRSHR,
277
  MVE_SQSHLL,
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  MVE_SQSHL,
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  MVE_CINC,
280
  MVE_CINV,
281
  MVE_CNEG,
282
  MVE_CSINC,
283
  MVE_CSINV,
284
  MVE_CSET,
285
  MVE_CSETM,
286
  MVE_CSNEG,
287
  MVE_CSEL,
288
  MVE_NONE
289
};
290
291
enum mve_unpredictable
292
{
293
  UNPRED_IT_BLOCK,    /* Unpredictable because mve insn in it block.
294
         */
295
  UNPRED_FCA_0_FCB_1,   /* Unpredictable because fcA = 0 and
296
           fcB = 1 (vpt).  */
297
  UNPRED_R13,     /* Unpredictable because r13 (sp) or
298
           r15 (sp) used.  */
299
  UNPRED_R15,     /* Unpredictable because r15 (pc) is used.  */
300
  UNPRED_Q_GT_4,    /* Unpredictable because
301
           vec reg start > 4 (vld4/st4).  */
302
  UNPRED_Q_GT_6,    /* Unpredictable because
303
           vec reg start > 6 (vld2/st2).  */
304
  UNPRED_R13_AND_WB,    /* Unpredictable becase gp reg = r13
305
           and WB bit = 1.  */
306
  UNPRED_Q_REGS_EQUAL,    /* Unpredictable because vector registers are
307
           equal.  */
308
  UNPRED_OS,      /* Unpredictable because offset scaled == 1.  */
309
  UNPRED_GP_REGS_EQUAL,   /* Unpredictable because gp registers are the
310
           same.  */
311
  UNPRED_Q_REGS_EQ_AND_SIZE_1,  /* Unpredictable because q regs equal and
312
           size = 1.  */
313
  UNPRED_Q_REGS_EQ_AND_SIZE_2,  /* Unpredictable because q regs equal and
314
           size = 2.  */
315
  UNPRED_NONE     /* No unpredictable behavior.  */
316
};
317
318
enum mve_undefined
319
{
320
  UNDEF_SIZE,     /* undefined size.  */
321
  UNDEF_SIZE_0,     /* undefined because size == 0.  */
322
  UNDEF_SIZE_2,     /* undefined because size == 2.  */
323
  UNDEF_SIZE_3,     /* undefined because size == 3.  */
324
  UNDEF_SIZE_LE_1,    /* undefined because size <= 1.  */
325
  UNDEF_SIZE_NOT_0,   /* undefined because size != 0.  */
326
  UNDEF_SIZE_NOT_2,   /* undefined because size != 2.  */
327
  UNDEF_SIZE_NOT_3,   /* undefined because size != 3.  */
328
  UNDEF_NOT_UNS_SIZE_0,   /* undefined because U == 0 and
329
           size == 0.  */
330
  UNDEF_NOT_UNS_SIZE_1,   /* undefined because U == 0 and
331
           size == 1.  */
332
  UNDEF_NOT_UNSIGNED,   /* undefined because U == 0.  */
333
  UNDEF_VCVT_IMM6,    /* imm6 < 32.  */
334
  UNDEF_VCVT_FSI_IMM6,    /* fsi = 0 and 32 >= imm6 <= 47.  */
335
  UNDEF_BAD_OP1_OP2,    /* undefined with op2 = 2 and
336
           op1 == (0 or 1).  */
337
  UNDEF_BAD_U_OP1_OP2,    /* undefined with U = 1 and
338
           op2 == 0 and op1 == (0 or 1).  */
339
  UNDEF_OP_0_BAD_CMODE,   /* undefined because op == 0 and cmode
340
           in {0xx1, x0x1}.  */
341
  UNDEF_XCHG_UNS,   /* undefined because X == 1 and U == 1.  */
342
  UNDEF_NONE      /* no undefined behavior.  */
343
};
344
345
struct opcode32
346
{
347
  arm_feature_set arch;   /* Architecture defining this insn.  */
348
  unsigned long value;    /* If arch is 0 then value is a sentinel.  */
349
  unsigned long mask;   /* Recognise insn if (op & mask) == value.  */
350
  const char *  assembler;  /* How to disassemble this insn.  */
351
};
352
353
struct cdeopcode32
354
{
355
  arm_feature_set arch;   /* Architecture defining this insn.  */
356
  uint8_t coproc_shift;   /* coproc is this far into op.  */
357
  uint16_t coproc_mask;   /* Length of coproc field in op.  */
358
  unsigned long value;    /* If arch is 0 then value is a sentinel.  */
359
  unsigned long mask;   /* Recognise insn if (op & mask) == value.  */
360
  const char *  assembler;  /* How to disassemble this insn.  */
361
};
362
363
/* MVE opcodes.  */
364
365
struct mopcode32
366
{
367
  arm_feature_set arch;   /* Architecture defining this insn.  */
368
  enum mve_instructions mve_op;  /* Specific mve instruction for faster
369
            decoding.  */
370
  unsigned long value;    /* If arch is 0 then value is a sentinel.  */
371
  unsigned long mask;   /* Recognise insn if (op & mask) == value.  */
372
  const char *  assembler;  /* How to disassemble this insn.  */
373
};
374
375
enum isa {
376
  ANY,
377
  T32,
378
  ARM
379
};
380
381
382
/* Shared (between Arm and Thumb mode) opcode.  */
383
struct sopcode32
384
{
385
  enum isa isa;     /* Execution mode instruction availability.  */
386
  arm_feature_set arch;   /* Architecture defining this insn.  */
387
  unsigned long value;    /* If arch is 0 then value is a sentinel.  */
388
  unsigned long mask;   /* Recognise insn if (op & mask) == value.  */
389
  const char *  assembler;  /* How to disassemble this insn.  */
390
};
391
392
struct opcode16
393
{
394
  arm_feature_set arch;   /* Architecture defining this insn.  */
395
  unsigned short value, mask; /* Recognise insn if (op & mask) == value.  */
396
  const char *assembler;  /* How to disassemble this insn.  */
397
};
398
399
/* print_insn_coprocessor recognizes the following format control codes:
400
401
   %%     %
402
403
   %c     print condition code (always bits 28-31 in ARM mode)
404
   %b     print condition code allowing cp_num == 9
405
   %q     print shifter argument
406
   %u     print condition code (unconditional in ARM mode,
407
                          UNPREDICTABLE if not AL in Thumb)
408
   %A     print address for ldc/stc/ldf/stf instruction
409
   %B     print vstm/vldm register list
410
   %C     print vscclrm register list
411
   %I                   print cirrus signed shift immediate: bits 0..3|4..6
412
   %J     print register for VLDR instruction
413
   %K     print address for VLDR instruction
414
   %F     print the COUNT field of a LFM/SFM instruction.
415
   %P     print floating point precision in arithmetic insn
416
   %Q     print floating point precision in ldf/stf insn
417
   %R     print floating point rounding mode
418
419
   %<bitfield>c   print as a condition code (for vsel)
420
   %<bitfield>r   print as an ARM register
421
   %<bitfield>R   as %<>r but r15 is UNPREDICTABLE
422
   %<bitfield>ru        as %<>r but each u register must be unique.
423
   %<bitfield>d   print the bitfield in decimal
424
   %<bitfield>k   print immediate for VFPv3 conversion instruction
425
   %<bitfield>x   print the bitfield in hex
426
   %<bitfield>X   print the bitfield as 1 hex digit without leading "0x"
427
   %<bitfield>f   print a floating point constant if >7 else a
428
      floating point register
429
   %<bitfield>w         print as an iWMMXt width field - [bhwd]ss/us
430
   %<bitfield>g         print as an iWMMXt 64-bit register
431
   %<bitfield>G         print as an iWMMXt general purpose or control register
432
   %<bitfield>D   print as a NEON D register
433
   %<bitfield>Q   print as a NEON Q register
434
   %<bitfield>V   print as a NEON D or Q register
435
   %<bitfield>E   print a quarter-float immediate value
436
437
   %y<code>   print a single precision VFP reg.
438
        Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
439
   %z<code>   print a double precision VFP reg
440
        Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
441
442
   %<bitfield>'c  print specified char iff bitfield is all ones
443
   %<bitfield>`c  print specified char iff bitfield is all zeroes
444
   %<bitfield>?ab...    select from array of values in big endian order
445
446
   %L     print as an iWMMXt N/M width field.
447
   %Z     print the Immediate of a WSHUFH instruction.
448
   %l     like 'A' except use byte offsets for 'B' & 'H'
449
      versions.
450
   %i     print 5-bit immediate in bits 8,3..0
451
      (print "32" when 0)
452
   %r     print register offset address for wldt/wstr instruction.  */
453
454
enum opcode_sentinel_enum
455
{
456
  SENTINEL_IWMMXT_START = 1,
457
  SENTINEL_IWMMXT_END,
458
  SENTINEL_GENERIC_START
459
} opcode_sentinels;
460
461
#define UNDEFINED_INSTRUCTION      "\t\t@ <UNDEFINED> instruction: %0-31x"
462
0
#define UNKNOWN_INSTRUCTION_32BIT  "\t\t@ <UNDEFINED> instruction: %08x"
463
0
#define UNKNOWN_INSTRUCTION_16BIT  "\t\t@ <UNDEFINED> instruction: %04x"
464
0
#define UNPREDICTABLE_INSTRUCTION  "\t@ <UNPREDICTABLE>"
465
466
/* Common coprocessor opcodes shared between Arm and Thumb-2.  */
467
468
/* print_insn_cde recognizes the following format control codes:
469
470
   %%     %
471
472
   %a     print 'a' iff bit 28 is 1
473
   %p     print bits 8-10 as coprocessor
474
   %<bitfield>d   print as decimal
475
   %<bitfield>r   print as an ARM register
476
   %<bitfield>n   print as an ARM register but r15 is APSR_nzcv
477
   %<bitfield>T   print as an ARM register + 1
478
   %<bitfield>R   as %r but r13 is UNPREDICTABLE
479
   %<bitfield>S   as %r but rX where X > 10 is UNPREDICTABLE
480
   %j     print immediate taken from bits (16..21,7,0..5)
481
   %k     print immediate taken from bits (20..21,7,0..5).
482
   %l     print immediate taken from bits (20..22,7,4..5).  */
483
484
/* At the moment there is only one valid position for the coprocessor number,
485
   and hence that's encoded in the macro below.  */
486
#define CDE_OPCODE(ARCH, VALUE, MASK, ASM) \
487
  { ARCH, 8, 7, VALUE, MASK, ASM }
488
static const struct cdeopcode32 cde_opcodes[] =
489
{
490
  /* Custom Datapath Extension instructions.  */
491
  CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
492
        0xee000000, 0xefc00840,
493
        "cx1%a\t%p, %12-15n, %{I:#%0-5,7,16-21d%}"),
494
  CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
495
        0xee000040, 0xefc00840,
496
        "cx1d%a\t%p, %12-15S, %12-15T, %{I:#%0-5,7,16-21d%}"),
497
498
  CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
499
        0xee400000, 0xefc00840,
500
        "cx2%a\t%p, %12-15n, %16-19n, %{I:#%0-5,7,20-21d%}"),
501
  CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
502
        0xee400040, 0xefc00840,
503
        "cx2d%a\t%p, %12-15S, %12-15T, %16-19n, %{I:#%0-5,7,20-21d%}"),
504
505
  CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
506
        0xee800000, 0xef800840,
507
        "cx3%a\t%p, %0-3n, %16-19n, %12-15n, %{I:#%4-5,7,20-22d%}"),
508
  CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
509
        0xee800040, 0xef800840,
510
       "cx3d%a\t%p, %0-3S, %0-3T, %16-19n, %12-15n, %{I:#%4-5,7,20-22d%}"),
511
512
  CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
513
        0xec200000, 0xeeb00840,
514
        "vcx1%a\t%p, %12-15,22V, %{I:#%0-5,7,16-19d%}"),
515
  CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
516
        0xec200040, 0xeeb00840,
517
        "vcx1%a\t%p, %12-15,22V, %{I:#%0-5,7,16-19,24d%}"),
518
519
  CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
520
        0xec300000, 0xeeb00840,
521
        "vcx2%a\t%p, %12-15,22V, %0-3,5V, %{I:#%4,7,16-19d%}"),
522
  CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
523
        0xec300040, 0xeeb00840,
524
        "vcx2%a\t%p, %12-15,22V, %0-3,5V, %{I:#%4,7,16-19,24d%}"),
525
526
  CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
527
        0xec800000, 0xee800840,
528
        "vcx3%a\t%p, %12-15,22V, %16-19,7V, %0-3,5V, %{I:#%4,20-21d%}"),
529
  CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
530
        0xec800040, 0xee800840,
531
        "vcx3%a\t%p, %12-15,22V, %16-19,7V, %0-3,5V, %{I:#%4,20-21,24d%}"),
532
533
  CDE_OPCODE (ARM_FEATURE_CORE_LOW (0), 0, 0, 0)
534
535
};
536
537
static const struct sopcode32 coprocessor_opcodes[] =
538
{
539
  /* XScale instructions.  */
540
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
541
    0x0e200010, 0x0fff0ff0,
542
    "mia%c\t%{R:acc0%}, %0-3r, %12-15r"},
543
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
544
    0x0e280010, 0x0fff0ff0,
545
    "miaph%c\t%{R:acc0%}, %0-3r, %12-15r"},
546
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
547
    0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\t%{R:acc0%}, %0-3r, %12-15r"},
548
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
549
    0x0c400000, 0x0ff00fff, "mar%c\t%{R:acc0%}, %12-15r, %16-19r"},
550
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
551
    0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, %{R:acc0%}"},
552
553
  /* Intel Wireless MMX technology instructions.  */
554
  {ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START, 0, "" },
555
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT),
556
    0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
557
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
558
    0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
559
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
560
    0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, %{I:#%0-2d%}"},
561
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
562
    0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, %{I:#%0-2d%}"},
563
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
564
    0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, %{I:#%0-2d%}"},
565
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
566
    0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
567
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
568
    0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
569
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
570
    0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
571
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
572
    0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
573
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
574
    0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
575
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
576
    0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
577
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
578
    0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
579
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
580
    0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
581
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
582
    0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
583
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
584
    0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
585
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
586
    0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
587
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
588
    0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
589
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
590
    0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
591
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
592
    0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
593
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
594
    0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
595
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
596
    0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, %{I:#%20-22d%}"},
597
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
598
    0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
599
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
600
    0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
601
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
602
    0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
603
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
604
    0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"},
605
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
606
    0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
607
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
608
    0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
609
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
610
    0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"},
611
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
612
    0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
613
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
614
    0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
615
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
616
    0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
617
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
618
    0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"},
619
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
620
    0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"},
621
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
622
    0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
623
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
624
    0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, %{I:#%21-23d%}"},
625
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
626
    0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
627
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
628
    0x0e800120, 0x0f800ff0,
629
    "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
630
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
631
    0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
632
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
633
    0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"},
634
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
635
    0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"},
636
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
637
    0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"},
638
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
639
    0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"},
640
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
641
    0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"},
642
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
643
    0x0e8000a0, 0x0f800ff0,
644
    "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
645
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
646
    0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"},
647
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
648
    0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"},
649
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
650
    0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
651
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
652
    0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
653
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
654
    0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, %{I:#%i%}"},
655
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
656
    0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
657
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
658
    0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"},
659
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
660
    0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
661
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
662
    0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, %{I:#%Z%}"},
663
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
664
    0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, %{I:#%i%}"},
665
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
666
    0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
667
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
668
    0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
669
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
670
    0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, %{I:#%i%}"},
671
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
672
    0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
673
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
674
    0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
675
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
676
    0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, %{I:#%i%}"},
677
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
678
    0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
679
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
680
    0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
681
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
682
    0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"},
683
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
684
    0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
685
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
686
    0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
687
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
688
    0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
689
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
690
    0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"},
691
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
692
    0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"},
693
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
694
    0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"},
695
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
696
    0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"},
697
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
698
    0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
699
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
700
    0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
701
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
702
    0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
703
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
704
    0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
705
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
706
    0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
707
  {ANY, ARM_FEATURE_CORE_LOW (0),
708
    SENTINEL_IWMMXT_END, 0, "" },
709
710
  /* Floating point coprocessor (FPA) instructions.  */
711
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
712
    0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
713
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
714
    0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
715
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
716
    0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
717
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
718
    0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
719
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
720
    0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
721
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
722
    0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
723
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
724
    0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
725
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
726
    0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
727
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
728
    0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
729
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
730
    0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
731
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
732
    0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
733
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
734
    0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
735
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
736
    0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
737
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
738
    0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
739
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
740
    0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
741
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
742
    0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
743
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
744
    0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
745
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
746
    0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
747
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
748
    0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
749
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
750
    0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
751
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
752
    0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
753
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
754
    0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
755
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
756
    0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
757
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
758
    0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
759
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
760
    0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
761
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
762
    0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
763
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
764
    0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
765
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
766
    0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
767
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
768
    0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
769
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
770
    0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
771
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
772
    0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
773
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
774
    0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
775
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
776
    0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
777
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
778
    0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
779
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
780
    0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
781
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
782
    0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
783
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
784
    0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
785
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
786
    0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
787
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
788
    0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
789
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
790
    0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
791
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
792
    0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
793
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
794
    0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
795
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
796
    0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
797
798
  /* Armv8.1-M Mainline instructions.  */
799
  {T32, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
800
    0xec9f0b00, 0xffbf0f01, "vscclrm%c\t%C"},
801
  {T32, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
802
    0xec9f0a00, 0xffbf0f00, "vscclrm%c\t%C"},
803
804
  /* ARMv8-M Mainline Security Extensions instructions.  */
805
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
806
    0xec300a00, 0xfff0ffff, "vlldm\t%16-19r"},
807
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
808
    0xec200a00, 0xfff0ffff, "vlstm\t%16-19r"},
809
810
  /* Register load/store.  */
811
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
812
    0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
813
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
814
    0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"},
815
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
816
    0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"},
817
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
818
    0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
819
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
820
    0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"},
821
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
822
    0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
823
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
824
    0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"},
825
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
826
    0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"},
827
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
828
    0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"},
829
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
830
    0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"},
831
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
832
    0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"},
833
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
834
    0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"},
835
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
836
    0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"},
837
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
838
    0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"},
839
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
840
    0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"},
841
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
842
    0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"},
843
  {ANY, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN),
844
    0xec100f80, 0xfe101f80, "vldr%c\t%J, %K"},
845
  {ANY, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN),
846
    0xec000f80, 0xfe101f80, "vstr%c\t%J, %K"},
847
848
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
849
    0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t@ Deprecated"},
850
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
851
    0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t@ Deprecated"},
852
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
853
    0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t@ Deprecated"},
854
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
855
    0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t@ Deprecated"},
856
857
  /* Data transfer between ARM and NEON registers.  */
858
  {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
859
    0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
860
  {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
861
    0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
862
  {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
863
    0x0e000b10, 0x0fd00f70, "vmov%c.32\t%{R:%16-19,7D[%21d]%}, %12-15r"},
864
  {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
865
    0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %{R:%16-19,7D[%21d]%}"},
866
  {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
867
    0x0e000b30, 0x0fd00f30, "vmov%c.16\t%{R:%16-19,7D[%6,21d]%}, %12-15r"},
868
  {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
869
    0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %{R:%16-19,7D[%6,21d]%}"},
870
  {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
871
    0x0e400b10, 0x0fd00f10, "vmov%c.8\t%{R:%16-19,7D[%5,6,21d]%}, %12-15r"},
872
  {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
873
    0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %{R:%16-19,7D[%5,6,21d]%}"},
874
  /* Half-precision conversion instructions.  */
875
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
876
    0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"},
877
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
878
    0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"},
879
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
880
    0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"},
881
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
882
    0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"},
883
884
  /* Floating point coprocessor (VFP) instructions.  */
885
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
886
    0x0ee00a10, 0x0fff0fff, "vmsr%c\t%{R:fpsid%}, %12-15r"},
887
  {ANY, ARM_FEATURE (0, ARM_EXT2_V8_1M_MAIN, FPU_VFP_EXT_V1xD),
888
    0x0ee10a10, 0x0fff0fff, "vmsr%c\t%{R:fpscr%}, %12-15r"},
889
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
890
    0x0ee20a10, 0x0fff0fff, "vmsr%c\t%{R:fpscr_nzcvqc%}, %12-15r"},
891
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
892
    0x0ee60a10, 0x0fff0fff, "vmsr%c\t%{R:mvfr1%}, %12-15r"},
893
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
894
    0x0ee70a10, 0x0fff0fff, "vmsr%c\t%{R:mvfr0%}, %12-15r"},
895
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
896
    0x0ee50a10, 0x0fff0fff, "vmsr%c\t%{R:mvfr2%}, %12-15r"},
897
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
898
    0x0ee80a10, 0x0fff0fff, "vmsr%c\t%{R:fpexc%}, %12-15r"},
899
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
900
    0x0ee90a10, 0x0fff0fff, "vmsr%c\t%{R:fpinst%}, %12-15r\t@ Impl def"},
901
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
902
    0x0eea0a10, 0x0fff0fff, "vmsr%c\t%{R:fpinst2%}, %12-15r\t@ Impl def"},
903
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
904
    0x0eec0a10, 0x0fff0fff, "vmsr%c\t%{R:vpr%}, %12-15r"},
905
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
906
    0x0eed0a10, 0x0fff0fff, "vmsr%c\t%{R:p0%}, %12-15r"},
907
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
908
    0x0eee0a10, 0x0fff0fff, "vmsr%c\t%{R:fpcxt_ns%}, %12-15r"},
909
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
910
    0x0eef0a10, 0x0fff0fff, "vmsr%c\t%{R:fpcxt_s%}, %12-15r"},
911
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
912
    0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpsid%}"},
913
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
914
    0x0ef1fa10, 0x0fffffff, "vmrs%c\t%{R:APSR_nzcv%}, %{R:fpscr%}"},
915
  {ANY, ARM_FEATURE (0, ARM_EXT2_V8_1M_MAIN, FPU_VFP_EXT_V1xD),
916
    0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpscr%}"},
917
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
918
    0x0ef20a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpscr_nzcvqc%}"},
919
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
920
    0x0ef50a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:mvfr2%}"},
921
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
922
    0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:mvfr1%}"},
923
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
924
    0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:mvfr0%}"},
925
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
926
    0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpexc%}"},
927
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
928
    0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpinst%}\t@ Impl def"},
929
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
930
    0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpinst2%}\t@ Impl def"},
931
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
932
    0x0efc0a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:vpr%}"},
933
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
934
    0x0efd0a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:p0%}"},
935
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
936
    0x0efe0a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpcxt_ns%}"},
937
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
938
    0x0eff0a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpcxt_s%}"},
939
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
940
    0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%{I:%21d%}], %12-15r"},
941
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
942
    0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%{I:%21d%}]"},
943
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
944
    0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"},
945
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
946
    0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"},
947
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
948
    0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"},
949
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
950
    0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"},
951
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
952
    0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, %{I:#0.0%}"},
953
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
954
    0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, %{I:#0.0%}"},
955
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
956
    0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"},
957
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
958
    0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"},
959
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
960
    0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"},
961
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
962
    0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"},
963
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
964
    0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"},
965
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
966
    0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"},
967
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
968
    0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"},
969
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
970
    0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"},
971
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
972
    0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"},
973
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
974
    0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"},
975
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
976
    0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"},
977
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
978
    0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"},
979
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
980
    0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"},
981
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
982
    0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"},
983
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
984
    0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, %{I:#%5,0-3k%}"},
985
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
986
    0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, %{I:#%5,0-3k%}"},
987
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
988
    0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"},
989
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
990
    0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"},
991
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
992
    0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, %{I:#%5,0-3k%}"},
993
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
994
    0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, %{I:#%5,0-3k%}"},
995
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
996
    0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"},
997
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
998
    0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, %{I:#%0-3,16-19E%}"},
999
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
1000
    0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, %{I:#%0-3,16-19E%}"},
1001
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
1002
    0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"},
1003
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
1004
    0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"},
1005
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
1006
    0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"},
1007
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
1008
    0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"},
1009
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
1010
    0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"},
1011
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
1012
    0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"},
1013
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
1014
    0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"},
1015
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
1016
    0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"},
1017
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
1018
    0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"},
1019
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
1020
    0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"},
1021
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
1022
    0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"},
1023
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
1024
    0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"},
1025
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
1026
    0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"},
1027
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
1028
    0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"},
1029
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
1030
    0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"},
1031
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
1032
    0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"},
1033
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
1034
    0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"},
1035
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
1036
    0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"},
1037
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
1038
    0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"},
1039
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
1040
    0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"},
1041
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
1042
    0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"},
1043
1044
  /* Cirrus coprocessor instructions.  */
1045
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1046
    0x0d100400, 0x0f500f00, "cfldrs%c\t%{R:mvf%12-15d%}, %A"},
1047
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1048
    0x0c100400, 0x0f500f00, "cfldrs%c\t%{R:mvf%12-15d%}, %A"},
1049
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1050
    0x0d500400, 0x0f500f00, "cfldrd%c\t%{R:mvd%12-15d%}, %A"},
1051
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1052
    0x0c500400, 0x0f500f00, "cfldrd%c\t%{R:mvd%12-15d%}, %A"},
1053
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1054
    0x0d100500, 0x0f500f00, "cfldr32%c\t%{R:mvfx%12-15d%}, %A"},
1055
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1056
    0x0c100500, 0x0f500f00, "cfldr32%c\t%{R:mvfx%12-15d%}, %A"},
1057
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1058
    0x0d500500, 0x0f500f00, "cfldr64%c\t%{R:mvdx%12-15d%}, %A"},
1059
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1060
    0x0c500500, 0x0f500f00, "cfldr64%c\t%{R:mvdx%12-15d%}, %A"},
1061
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1062
    0x0d000400, 0x0f500f00, "cfstrs%c\t%{R:mvf%12-15d%}, %A"},
1063
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1064
    0x0c000400, 0x0f500f00, "cfstrs%c\t%{R:mvf%12-15d%}, %A"},
1065
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1066
    0x0d400400, 0x0f500f00, "cfstrd%c\t%{R:mvd%12-15d%}, %A"},
1067
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1068
    0x0c400400, 0x0f500f00, "cfstrd%c\t%{R:mvd%12-15d%}, %A"},
1069
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1070
    0x0d000500, 0x0f500f00, "cfstr32%c\t%{R:mvfx%12-15d%}, %A"},
1071
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1072
    0x0c000500, 0x0f500f00, "cfstr32%c\t%{R:mvfx%12-15d%}, %A"},
1073
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1074
    0x0d400500, 0x0f500f00, "cfstr64%c\t%{R:mvdx%12-15d%}, %A"},
1075
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1076
    0x0c400500, 0x0f500f00, "cfstr64%c\t%{R:mvdx%12-15d%}, %A"},
1077
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1078
    0x0e000450, 0x0ff00ff0, "cfmvsr%c\t%{R:mvf%16-19d%}, %12-15r"},
1079
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1080
    0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, %{R:mvf%16-19d%}"},
1081
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1082
    0x0e000410, 0x0ff00ff0, "cfmvdlr%c\t%{R:mvd%16-19d%}, %12-15r"},
1083
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1084
    0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, %{R:mvd%16-19d%}"},
1085
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1086
    0x0e000430, 0x0ff00ff0, "cfmvdhr%c\t%{R:mvd%16-19d%}, %12-15r"},
1087
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1088
    0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, %{R:mvd%16-19d%}"},
1089
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1090
    0x0e000510, 0x0ff00fff, "cfmv64lr%c\t%{R:mvdx%16-19d%}, %12-15r"},
1091
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1092
    0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, %{R:mvdx%16-19d%}"},
1093
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1094
    0x0e000530, 0x0ff00fff, "cfmv64hr%c\t%{R:mvdx%16-19d%}, %12-15r"},
1095
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1096
    0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, %{R:mvdx%16-19d%}"},
1097
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1098
    0x0e200440, 0x0ff00fff, "cfmval32%c\t%{R:mvax%12-15d%}, %{R:mvfx%16-19d%}"},
1099
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1100
    0x0e100440, 0x0ff00fff, "cfmv32al%c\t%{R:mvfx%12-15d%}, %{R:mvax%16-19d%}"},
1101
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1102
    0x0e200460, 0x0ff00fff, "cfmvam32%c\t%{R:mvax%12-15d%}, %{R:mvfx%16-19d%}"},
1103
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1104
    0x0e100460, 0x0ff00fff, "cfmv32am%c\t%{R:mvfx%12-15d%}, %{R:mvax%16-19d%}"},
1105
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1106
    0x0e200480, 0x0ff00fff, "cfmvah32%c\t%{R:mvax%12-15d%}, %{R:mvfx%16-19d%}"},
1107
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1108
    0x0e100480, 0x0ff00fff, "cfmv32ah%c\t%{R:mvfx%12-15d%}, %{R:mvax%16-19d%}"},
1109
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1110
    0x0e2004a0, 0x0ff00fff, "cfmva32%c\t%{R:mvax%12-15d%}, %{R:mvfx%16-19d%}"},
1111
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1112
    0x0e1004a0, 0x0ff00fff, "cfmv32a%c\t%{R:mvfx%12-15d%}, %{R:mvax%16-19d%}"},
1113
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1114
    0x0e2004c0, 0x0ff00fff, "cfmva64%c\t%{R:mvax%12-15d%}, %{R:mvdx%16-19d%}"},
1115
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1116
    0x0e1004c0, 0x0ff00fff, "cfmv64a%c\t%{R:mvdx%12-15d%}, %{R:mvax%16-19d%}"},
1117
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1118
    0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\t%{R:dspsc%}, %{R:mvdx%12-15d%}"},
1119
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1120
    0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\t%{R:mvdx%12-15d%}, %{R:dspsc%}"},
1121
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1122
    0x0e000400, 0x0ff00fff, "cfcpys%c\t%{R:mvf%12-15d%}, %{R:mvf%16-19d%}"},
1123
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1124
    0x0e000420, 0x0ff00fff, "cfcpyd%c\t%{R:mvd%12-15d%}, %{R:mvd%16-19d%}"},
1125
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1126
    0x0e000460, 0x0ff00fff, "cfcvtsd%c\t%{R:mvd%12-15d%}, %{R:mvf%16-19d%}"},
1127
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1128
    0x0e000440, 0x0ff00fff, "cfcvtds%c\t%{R:mvf%12-15d%}, %{R:mvd%16-19d%}"},
1129
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1130
    0x0e000480, 0x0ff00fff, "cfcvt32s%c\t%{R:mvf%12-15d%}, %{R:mvfx%16-19d%}"},
1131
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1132
    0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\t%{R:mvd%12-15d%}, %{R:mvfx%16-19d%}"},
1133
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1134
    0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\t%{R:mvf%12-15d%}, %{R:mvdx%16-19d%}"},
1135
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1136
    0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\t%{R:mvd%12-15d%}, %{R:mvdx%16-19d%}"},
1137
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1138
    0x0e100580, 0x0ff00fff, "cfcvts32%c\t%{R:mvfx%12-15d%}, %{R:mvf%16-19d%}"},
1139
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1140
    0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\t%{R:mvfx%12-15d%}, %{R:mvd%16-19d%}"},
1141
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1142
    0x0e1005c0, 0x0ff00fff, "cftruncs32%c\t%{R:mvfx%12-15d%}, %{R:mvf%16-19d%}"},
1143
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1144
    0x0e1005e0, 0x0ff00fff, "cftruncd32%c\t%{R:mvfx%12-15d%}, %{R:mvd%16-19d%}"},
1145
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1146
    0x0e000550, 0x0ff00ff0, "cfrshl32%c\t%{R:mvfx%16-19d%}, %{R:mvfx%0-3d%}, %12-15r"},
1147
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1148
    0x0e000570, 0x0ff00ff0, "cfrshl64%c\t%{R:mvdx%16-19d%}, %{R:mvdx%0-3d%}, %12-15r"},
1149
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1150
    0x0e000500, 0x0ff00f10, "cfsh32%c\t%{R:mvfx%12-15d%}, %{R:mvfx%16-19d%}, %{I:#%I%}"},
1151
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1152
    0x0e200500, 0x0ff00f10, "cfsh64%c\t%{R:mvdx%12-15d%}, %{R:mvdx%16-19d%}, %{I:#%I%}"},
1153
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1154
    0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, %{R:mvf%16-19d%}, %{R:mvf%0-3d%}"},
1155
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1156
    0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, %{R:mvd%16-19d%}, %{R:mvd%0-3d%}"},
1157
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1158
    0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, %{R:mvfx%16-19d%}, %{R:mvfx%0-3d%}"},
1159
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1160
    0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, %{R:mvdx%16-19d%}, %{R:mvdx%0-3d%}"},
1161
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1162
    0x0e300400, 0x0ff00fff, "cfabss%c\t%{R:mvf%12-15d%}, %{R:mvf%16-19d%}"},
1163
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1164
    0x0e300420, 0x0ff00fff, "cfabsd%c\t%{R:mvd%12-15d%}, %{R:mvd%16-19d%}"},
1165
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1166
    0x0e300440, 0x0ff00fff, "cfnegs%c\t%{R:mvf%12-15d%}, %{R:mvf%16-19d%}"},
1167
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1168
    0x0e300460, 0x0ff00fff, "cfnegd%c\t%{R:mvd%12-15d%}, %{R:mvd%16-19d%}"},
1169
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1170
    0x0e300480, 0x0ff00ff0, "cfadds%c\t%{R:mvf%12-15d%}, %{R:mvf%16-19d%}, %{R:mvf%0-3d%}"},
1171
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1172
    0x0e3004a0, 0x0ff00ff0, "cfaddd%c\t%{R:mvd%12-15d%}, %{R:mvd%16-19d%}, %{R:mvd%0-3d%}"},
1173
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1174
    0x0e3004c0, 0x0ff00ff0, "cfsubs%c\t%{R:mvf%12-15d%}, %{R:mvf%16-19d%}, %{R:mvf%0-3d%}"},
1175
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1176
    0x0e3004e0, 0x0ff00ff0, "cfsubd%c\t%{R:mvd%12-15d%}, %{R:mvd%16-19d%}, %{R:mvd%0-3d%}"},
1177
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1178
    0x0e100400, 0x0ff00ff0, "cfmuls%c\t%{R:mvf%12-15d%}, %{R:mvf%16-19d%}, %{R:mvf%0-3d%}"},
1179
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1180
    0x0e100420, 0x0ff00ff0, "cfmuld%c\t%{R:mvd%12-15d%}, %{R:mvd%16-19d%}, %{R:mvd%0-3d%}"},
1181
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1182
    0x0e300500, 0x0ff00fff, "cfabs32%c\t%{R:mvfx%12-15d%}, %{R:mvfx%16-19d%}"},
1183
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1184
    0x0e300520, 0x0ff00fff, "cfabs64%c\t%{R:mvdx%12-15d%}, %{R:mvdx%16-19d%}"},
1185
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1186
    0x0e300540, 0x0ff00fff, "cfneg32%c\t%{R:mvfx%12-15d%}, %{R:mvfx%16-19d%}"},
1187
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1188
    0x0e300560, 0x0ff00fff, "cfneg64%c\t%{R:mvdx%12-15d%}, %{R:mvdx%16-19d%}"},
1189
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1190
    0x0e300580, 0x0ff00ff0, "cfadd32%c\t%{R:mvfx%12-15d%}, %{R:mvfx%16-19d%}, %{R:mvfx%0-3d%}"},
1191
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1192
    0x0e3005a0, 0x0ff00ff0, "cfadd64%c\t%{R:mvdx%12-15d%}, %{R:mvdx%16-19d%}, %{R:mvdx%0-3d%}"},
1193
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1194
    0x0e3005c0, 0x0ff00ff0, "cfsub32%c\t%{R:mvfx%12-15d%}, %{R:mvfx%16-19d%}, %{R:mvfx%0-3d%}"},
1195
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1196
    0x0e3005e0, 0x0ff00ff0, "cfsub64%c\t%{R:mvdx%12-15d%}, %{R:mvdx%16-19d%}, %{R:mvdx%0-3d%}"},
1197
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1198
    0x0e100500, 0x0ff00ff0, "cfmul32%c\t%{R:mvfx%12-15d%}, %{R:mvfx%16-19d%}, %{R:mvfx%0-3d%}"},
1199
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1200
    0x0e100520, 0x0ff00ff0, "cfmul64%c\t%{R:mvdx%12-15d%}, %{R:mvdx%16-19d%}, %{R:mvdx%0-3d%}"},
1201
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1202
    0x0e100540, 0x0ff00ff0, "cfmac32%c\t%{R:mvfx%12-15d%}, %{R:mvfx%16-19d%}, %{R:mvfx%0-3d%}"},
1203
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1204
    0x0e100560, 0x0ff00ff0, "cfmsc32%c\t%{R:mvfx%12-15d%}, %{R:mvfx%16-19d%}, %{R:mvfx%0-3d%}"},
1205
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1206
    0x0e000600, 0x0ff00f10,
1207
    "cfmadd32%c\t%{R:mvax%5-7d%}, %{R:mvfx%12-15d%}, %{R:mvfx%16-19d%}, %{R:mvfx%0-3d%}"},
1208
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1209
    0x0e100600, 0x0ff00f10,
1210
    "cfmsub32%c\t%{R:mvax%5-7d%}, %{R:mvfx%12-15d%}, %{R:mvfx%16-19d%}, %{R:mvfx%0-3d%}"},
1211
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1212
    0x0e200600, 0x0ff00f10,
1213
    "cfmadda32%c\t%{R:mvax%5-7d%}, %{R:mvax%12-15d%}, %{R:mvfx%16-19d%}, %{R:mvfx%0-3d%}"},
1214
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1215
    0x0e300600, 0x0ff00f10,
1216
    "cfmsuba32%c\t%{R:mvax%5-7d%}, %{R:mvax%12-15d%}, %{R:mvfx%16-19d%}, %{R:mvfx%0-3d%}"},
1217
1218
  /* VFP Fused multiply add instructions.  */
1219
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
1220
    0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"},
1221
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
1222
    0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"},
1223
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
1224
    0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"},
1225
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
1226
    0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"},
1227
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
1228
    0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"},
1229
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
1230
    0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"},
1231
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
1232
    0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"},
1233
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
1234
    0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"},
1235
1236
  /* FP v5.  */
1237
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1238
    0xfe000a00, 0xff800f50, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
1239
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1240
    0xfe000b00, 0xff800f50, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
1241
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1242
    0xfe800a00, 0xffb00f50, "vmaxnm%u.f32\t%y1, %y2, %y0"},
1243
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1244
    0xfe800b00, 0xffb00f50, "vmaxnm%u.f64\t%z1, %z2, %z0"},
1245
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1246
    0xfe800a40, 0xffb00f50, "vminnm%u.f32\t%y1, %y2, %y0"},
1247
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1248
    0xfe800b40, 0xffb00f50, "vminnm%u.f64\t%z1, %z2, %z0"},
1249
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1250
    0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"},
1251
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1252
    0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"},
1253
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1254
    0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"},
1255
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1256
    0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"},
1257
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1258
    0xfeb80a40, 0xffbc0fd0, "vrint%16-17?mpna%u.f32\t%y1, %y0"},
1259
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1260
    0xfeb80b40, 0xffbc0fd0, "vrint%16-17?mpna%u.f64\t%z1, %z0"},
1261
1262
  {ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START, 0, "" },
1263
  /* ARMv8.3 AdvSIMD instructions in the space of coprocessor 8.  */
1264
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1265
    0xfc800800, 0xfeb00f10, "vcadd%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, %{I:#%24?29%24'70%}"},
1266
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1267
    0xfc900800, 0xfeb00f10, "vcadd%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, %{I:#%24?29%24'70%}"},
1268
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1269
    0xfc200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, %{I:#%23'90%}"},
1270
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1271
    0xfd200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, %{I:#%23?21%23?780%}"},
1272
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1273
    0xfc300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, %{I:#%23'90%}"},
1274
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1275
    0xfd300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, %{I:#%23?21%23?780%}"},
1276
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1277
    0xfe000800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %{R:%0-3D[%5?10]%}, %{I:#%20'90%}"},
1278
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1279
    0xfe200800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %{R:%0-3D[%5?10]%}, %{I:#%20?21%20?780%}"},
1280
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1281
    0xfe800800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %{R:%0-3,5D[0]%}, %{I:#%20'90%}"},
1282
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1283
    0xfea00800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %{R:%0-3,5D[0]%}, %{I:#%20?21%20?780%}"},
1284
1285
  /* BFloat16 instructions.  */
1286
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1287
    0x0eb30940, 0x0fbf0f50, "vcvt%7?tb%b.bf16.f32\t%y1, %y0"},
1288
1289
  /* Dot Product instructions in the space of coprocessor 13.  */
1290
  {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
1291
    0xfc200d00, 0xffb00f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3,5V"},
1292
  {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
1293
    0xfe200d00, 0xff200f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %{R:%0-3D[%5?10]%}"},
1294
1295
  /* ARMv8.2 FMAC Long instructions in the space of coprocessor 8.  */
1296
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1297
    0xfc200810, 0xffb00f50, "vfmal.f16\t%12-15,22D, %{R:s%7,16-19d%}, %{R:s%5,0-3d%}"},
1298
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1299
    0xfca00810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, %{R:s%7,16-19d%}, %{R:s%5,0-3d%}"},
1300
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1301
    0xfc200850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, %{R:d%16-19,7d%}, %{R:d%0-3,5d%}"},
1302
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1303
    0xfca00850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, %{R:d%16-19,7d%}, %{R:d%0-3,5d%}"},
1304
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1305
    0xfe000810, 0xffb00f50, "vfmal.f16\t%12-15,22D, %{R:s%7,16-19d%}, %{R:s%5,0-2d[%3d]%}"},
1306
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1307
    0xfe100810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, %{R:s%7,16-19d%}, %{R:s%5,0-2d[%3d]%}"},
1308
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1309
    0xfe000850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, %{R:d%16-19,7d%}, %{R:d%0-2d[%3,5d]%}"},
1310
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1311
    0xfe100850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, %{R:d%16-19,7d%}, %{R:d%0-2d[%3,5d]%}"},
1312
1313
  /* ARMv8.2 half-precision Floating point coprocessor 9 (VFP) instructions.
1314
     cp_num: bit <11:8> == 0b1001.
1315
     cond: bit <31:28> == 0b1110, otherwise, it's UNPREDICTABLE.  */
1316
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1317
    0x0eb009c0, 0x0fbf0fd0, "vabs%c.f16\t%y1, %y0"},
1318
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1319
    0x0e300900, 0x0fb00f50, "vadd%c.f16\t%y1, %y2, %y0"},
1320
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1321
    0x0eb40940, 0x0fbf0f50, "vcmp%7'e%c.f16\t%y1, %y0"},
1322
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1323
    0x0eb50940, 0x0fbf0f70, "vcmp%7'e%c.f16\t%y1, %{I:#0.0%}"},
1324
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1325
    0x0eba09c0, 0x0fbe0fd0, "vcvt%c.f16.%16?us%7?31%7?26\t%y1, %y1, %{I:#%5,0-3k%}"},
1326
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1327
    0x0ebe09c0, 0x0fbe0fd0, "vcvt%c.%16?us%7?31%7?26.f16\t%y1, %y1, %{I:#%5,0-3k%}"},
1328
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1329
    0x0ebc0940, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f16\t%y1, %y0"},
1330
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1331
    0x0eb80940, 0x0fbf0f50, "vcvt%c.f16.%7?su32\t%y1, %y0"},
1332
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1333
    0xfebc0940, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f16\t%y1, %y0"},
1334
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1335
    0x0e800900, 0x0fb00f50, "vdiv%c.f16\t%y1, %y2, %y0"},
1336
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1337
    0x0ea00900, 0x0fb00f50, "vfma%c.f16\t%y1, %y2, %y0"},
1338
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1339
    0x0ea00940, 0x0fb00f50, "vfms%c.f16\t%y1, %y2, %y0"},
1340
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1341
    0x0e900940, 0x0fb00f50, "vfnma%c.f16\t%y1, %y2, %y0"},
1342
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1343
    0x0e900900, 0x0fb00f50, "vfnms%c.f16\t%y1, %y2, %y0"},
1344
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1345
    0xfeb00ac0, 0xffbf0fd0, "vins.f16\t%y1, %y0"},
1346
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1347
    0xfeb00a40, 0xffbf0fd0, "vmovx%c.f16\t%y1, %y0"},
1348
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1349
    0x0d100900, 0x0f300f00, "vldr%c.16\t%y1, %A"},
1350
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1351
    0x0d000900, 0x0f300f00, "vstr%c.16\t%y1, %A"},
1352
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1353
    0xfe800900, 0xffb00f50, "vmaxnm%c.f16\t%y1, %y2, %y0"},
1354
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1355
    0xfe800940, 0xffb00f50, "vminnm%c.f16\t%y1, %y2, %y0"},
1356
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1357
    0x0e000900, 0x0fb00f50, "vmla%c.f16\t%y1, %y2, %y0"},
1358
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1359
    0x0e000940, 0x0fb00f50, "vmls%c.f16\t%y1, %y2, %y0"},
1360
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1361
    0x0e100910, 0x0ff00f7f, "vmov%c.f16\t%12-15r, %y2"},
1362
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1363
    0x0e000910, 0x0ff00f7f, "vmov%c.f16\t%y2, %12-15r"},
1364
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1365
    0xeb00900, 0x0fb00ff0, "vmov%c.f16\t%y1, %{I:#%0-3,16-19E%}"},
1366
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1367
    0x0e200900, 0x0fb00f50, "vmul%c.f16\t%y1, %y2, %y0"},
1368
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1369
    0x0eb10940, 0x0fbf0fd0, "vneg%c.f16\t%y1, %y0"},
1370
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1371
    0x0e100940, 0x0fb00f50, "vnmla%c.f16\t%y1, %y2, %y0"},
1372
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1373
    0x0e100900, 0x0fb00f50, "vnmls%c.f16\t%y1, %y2, %y0"},
1374
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1375
    0x0e200940, 0x0fb00f50, "vnmul%c.f16\t%y1, %y2, %y0"},
1376
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1377
    0x0eb60940, 0x0fbe0f50, "vrint%7,16??xzr%c.f16\t%y1, %y0"},
1378
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1379
    0xfeb80940, 0xffbc0fd0, "vrint%16-17?mpna%u.f16\t%y1, %y0"},
1380
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1381
    0xfe000900, 0xff800f50, "vsel%20-21c%u.f16\t%y1, %y2, %y0"},
1382
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1383
    0x0eb109c0, 0x0fbf0fd0, "vsqrt%c.f16\t%y1, %y0"},
1384
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1385
    0x0e300940, 0x0fb00f50, "vsub%c.f16\t%y1, %y2, %y0"},
1386
1387
  /* ARMv8.3 javascript conversion instruction.  */
1388
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1389
    0x0eb90bc0, 0x0fbf0fd0, "vjcvt%c.s32.f64\t%y1, %z0"},
1390
1391
  {ANY, ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
1392
};
1393
1394
/* Generic coprocessor instructions.  These are only matched if a more specific
1395
   SIMD or co-processor instruction does not match first.  */
1396
1397
static const struct sopcode32 generic_coprocessor_opcodes[] =
1398
{
1399
  /* Generic coprocessor instructions.  */
1400
  {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
1401
    0x0c400000, 0x0ff00000, "mcrr%c\t%{I:%8-11d%}, %{I:%4-7d%}, %12-15R, %16-19r, %{R:cr%0-3d%}"},
1402
  {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
1403
    0x0c500000, 0x0ff00000,
1404
    "mrrc%c\t%{I:%8-11d%}, %{I:%4-7d%}, %12-15Ru, %16-19Ru, %{R:cr%0-3d%}"},
1405
  {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1406
    0x0e000000, 0x0f000010,
1407
    "cdp%c\t%{I:%8-11d%}, %{I:%20-23d%}, %{R:cr%12-15d%}, %{R:cr%16-19d%}, %{R:cr%0-3d%}, {%{I:%5-7d%}}"},
1408
  {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1409
    0x0e10f010, 0x0f10f010,
1410
    "mrc%c\t%{I:%8-11d%}, %{I:%21-23d%}, %{R:APSR_nzcv%}, %{R:cr%16-19d%}, %{R:cr%0-3d%}, {%{I:%5-7d%}}"},
1411
  {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1412
    0x0e100010, 0x0f100010,
1413
    "mrc%c\t%{I:%8-11d%}, %{I:%21-23d%}, %12-15r, %{R:cr%16-19d%}, %{R:cr%0-3d%}, {%{I:%5-7d%}}"},
1414
  {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1415
    0x0e000010, 0x0f100010,
1416
    "mcr%c\t%{I:%8-11d%}, %{I:%21-23d%}, %12-15R, %{R:cr%16-19d%}, %{R:cr%0-3d%}, {%{I:%5-7d%}}"},
1417
  {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1418
    0x0c000000, 0x0e100000, "stc%22'l%c\t%{I:%8-11d%}, %{R:cr%12-15d%}, %A"},
1419
  {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1420
    0x0c100000, 0x0e100000, "ldc%22'l%c\t%{I:%8-11d%}, %{R:cr%12-15d%}, %A"},
1421
1422
  /* V6 coprocessor instructions.  */
1423
  {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1424
    0xfc500000, 0xfff00000,
1425
    "mrrc2%c\t%{I:%8-11d%}, %{I:%4-7d%}, %12-15Ru, %16-19Ru, %{R:cr%0-3d%}"},
1426
  {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1427
    0xfc400000, 0xfff00000,
1428
    "mcrr2%c\t%{I:%8-11d%}, %{I:%4-7d%}, %12-15R, %16-19R, %{R:cr%0-3d%}"},
1429
1430
  /* V5 coprocessor instructions.  */
1431
  {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1432
    0xfc100000, 0xfe100000, "ldc2%22'l%c\t%{I:%8-11d%}, %{R:cr%12-15d%}, %A"},
1433
  {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1434
    0xfc000000, 0xfe100000, "stc2%22'l%c\t%{I:%8-11d%}, %{R:cr%12-15d%}, %A"},
1435
  {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1436
    0xfe000000, 0xff000010,
1437
    "cdp2%c\t%{I:%8-11d%}, %{I:%20-23d%}, %{R:cr%12-15d%}, %{R:cr%16-19d%}, %{R:cr%0-3d%}, {%{I:%5-7d%}}"},
1438
  {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1439
    0xfe000010, 0xff100010,
1440
    "mcr2%c\t%{I:%8-11d%}, %{I:%21-23d%}, %12-15R, %{R:cr%16-19d%}, %{R:cr%0-3d%}, {%{I:%5-7d%}}"},
1441
  {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1442
    0xfe100010, 0xff100010,
1443
    "mrc2%c\t%{I:%8-11d%}, %{I:%21-23d%}, %12-15r, %{R:cr%16-19d%}, %{R:cr%0-3d%}, {%{I:%5-7d%}}"},
1444
1445
  {ANY, ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
1446
};
1447
1448
/* Neon opcode table:  This does not encode the top byte -- that is
1449
   checked by the print_insn_neon routine, as it depends on whether we are
1450
   doing thumb32 or arm32 disassembly.  */
1451
1452
/* print_insn_neon recognizes the following format control codes:
1453
1454
   %%     %
1455
1456
   %c     print condition code
1457
   %u     print condition code (unconditional in ARM mode,
1458
                          UNPREDICTABLE if not AL in Thumb)
1459
   %A     print v{st,ld}[1234] operands
1460
   %B     print v{st,ld}[1234] any one operands
1461
   %C     print v{st,ld}[1234] single->all operands
1462
   %D     print scalar
1463
   %E     print vmov, vmvn, vorr, vbic encoded constant
1464
   %F     print vtbl,vtbx register list
1465
1466
   %<bitfield>r   print as an ARM register
1467
   %<bitfield>d   print the bitfield in decimal
1468
   %<bitfield>e         print the 2^N - bitfield in decimal
1469
   %<bitfield>D   print as a NEON D register
1470
   %<bitfield>Q   print as a NEON Q register
1471
   %<bitfield>R   print as a NEON D or Q register
1472
   %<bitfield>Sn  print byte scaled width limited by n
1473
   %<bitfield>Tn  print short scaled width limited by n
1474
   %<bitfield>Un  print long scaled width limited by n
1475
1476
   %<bitfield>'c  print specified char iff bitfield is all ones
1477
   %<bitfield>`c  print specified char iff bitfield is all zeroes
1478
   %<bitfield>?ab...    select from array of values in big endian order.  */
1479
1480
static const struct opcode32 neon_opcodes[] =
1481
{
1482
  /* Extract.  */
1483
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1484
    0xf2b00840, 0xffb00850,
1485
    "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, %{I:#%8-11d%}"},
1486
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1487
    0xf2b00000, 0xffb00810,
1488
    "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, %{I:#%8-11d%}"},
1489
1490
  /* Data transfer between ARM and NEON registers.  */
1491
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1492
    0x0e800b10, 0x0ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
1493
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1494
    0x0e800b30, 0x0ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
1495
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1496
    0x0ea00b10, 0x0ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
1497
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1498
    0x0ea00b30, 0x0ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
1499
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1500
    0x0ec00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
1501
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1502
    0x0ee00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
1503
1504
  /* Move data element to all lanes.  */
1505
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1506
    0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %{R:%0-3,5D[%19d]%}"},
1507
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1508
    0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %{R:%0-3,5D[%18-19d]%}"},
1509
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1510
    0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %{R:%0-3,5D[%17-19d]%}"},
1511
1512
  /* Table lookup.  */
1513
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1514
    0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"},
1515
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1516
    0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"},
1517
1518
  /* Half-precision conversions.  */
1519
  {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1520
    0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"},
1521
  {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1522
    0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"},
1523
1524
  /* NEON fused multiply add instructions.  */
1525
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
1526
    0xf2000c10, 0xffb00f10, "vfma%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1527
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1528
    0xf2100c10, 0xffb00f10, "vfma%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1529
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
1530
    0xf2200c10, 0xffb00f10, "vfms%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1531
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1532
    0xf2300c10, 0xffb00f10, "vfms%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1533
1534
  /* BFloat16 instructions.  */
1535
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1536
    0xfc000d00, 0xffb00f10, "vdot.bf16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1537
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1538
    0xfe000d00, 0xffb00f10, "vdot.bf16\t%12-15,22R, %16-19,7R, %{R:d%0-3d[%5d]%}"},
1539
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1540
    0xfc000c40, 0xffb00f50, "vmmla.bf16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1541
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1542
    0xf3b60640, 0xffbf0fd0, "vcvt%c.bf16.f32\t%12-15,22D, %0-3,5Q"},
1543
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1544
    0xfc300810, 0xffb00f10, "vfma%6?tb.bf16\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1545
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1546
    0xfe300810, 0xffb00f10, "vfma%6?tb.bf16\t%12-15,22Q, %16-19,7Q, %{R:%0-2D[%3,5d]%}"},
1547
1548
  /* Matrix Multiply instructions.  */
1549
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
1550
    0xfc200c40, 0xffb00f50, "vsmmla.s8\t%12-15,22R, %16-19,7R, %0-3,5R"},
1551
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
1552
    0xfc200c50, 0xffb00f50, "vummla.u8\t%12-15,22R, %16-19,7R, %0-3,5R"},
1553
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
1554
    0xfca00c40, 0xffb00f50, "vusmmla.s8\t%12-15,22R, %16-19,7R, %0-3,5R"},
1555
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
1556
    0xfca00d00, 0xffb00f10, "vusdot.s8\t%12-15,22R, %16-19,7R, %0-3,5R"},
1557
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
1558
    0xfe800d00, 0xffb00f10, "vusdot.s8\t%12-15,22R, %16-19,7R, %{R:d%0-3d[%5d]%}"},
1559
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
1560
    0xfe800d10, 0xffb00f10, "vsudot.u8\t%12-15,22R, %16-19,7R, %{R:d%0-3d[%5d]%}"},
1561
1562
  /* Two registers, miscellaneous.  */
1563
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1564
    0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"},
1565
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1566
    0xf3b60400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f16\t%12-15,22R, %0-3,5R"},
1567
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1568
    0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"},
1569
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1570
    0xf3b70000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us16.f16\t%12-15,22R, %0-3,5R"},
1571
  {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1572
    0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"},
1573
  {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1574
    0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"},
1575
  {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1576
    0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"},
1577
  {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1578
    0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"},
1579
  {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1580
    0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"},
1581
  {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1582
    0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"},
1583
  {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1584
    0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"},
1585
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1586
    0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
1587
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1588
    0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
1589
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1590
    0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
1591
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1592
    0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"},
1593
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1594
    0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"},
1595
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1596
    0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"},
1597
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1598
    0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"},
1599
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1600
    0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1601
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1602
    0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1603
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1604
    0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
1605
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1606
    0xf3b20300, 0xffb30fd0,
1607
    "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, %{I:#%18-19S2%}"},
1608
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1609
    0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1610
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1611
    0xf3b70400, 0xffbf0e90, "vrecpe%c.%8?fu16\t%12-15,22R, %0-3,5R"},
1612
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1613
    0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1614
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1615
    0xf3b70480, 0xffbf0e90, "vrsqrte%c.%8?fu16\t%12-15,22R, %0-3,5R"},
1616
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1617
    0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1618
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1619
    0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1620
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1621
    0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1622
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1623
    0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1624
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1625
    0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"},
1626
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1627
    0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1628
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1629
    0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1630
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1631
    0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1632
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1633
    0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1634
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1635
    0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1636
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1637
    0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, %{I:#0%}"},
1638
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1639
    0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, %{I:#0%}"},
1640
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1641
    0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, %{I:#0%}"},
1642
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1643
    0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, %{I:#0%}"},
1644
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1645
    0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, %{I:#0%}"},
1646
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1647
    0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1648
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1649
    0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1650
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1651
    0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1652
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1653
    0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1654
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1655
    0xf3bb0600, 0xffbf0e10,
1656
    "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
1657
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1658
    0xf3b70600, 0xffbf0e10,
1659
    "vcvt%c.%7-8?usff16.%7-8?ffus16\t%12-15,22R, %0-3,5R"},
1660
1661
  /* Three registers of the same length.  */
1662
  {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1663
    0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1664
  {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1665
    0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1666
  {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1667
    0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1668
  {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1669
    0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1670
  {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1671
    0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1672
  {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1673
    0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1674
  {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1675
    0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1676
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1677
    0xf3000f10, 0xffb00f10, "vmaxnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1678
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1679
    0xf3100f10, 0xffb00f10, "vmaxnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1680
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1681
    0xf3200f10, 0xffb00f10, "vminnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1682
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1683
    0xf3300f10, 0xffb00f10, "vminnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1684
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1685
    0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1686
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1687
    0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1688
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1689
    0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1690
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1691
    0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1692
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1693
    0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1694
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1695
    0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1696
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1697
    0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1698
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1699
    0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1700
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1701
    0xf2000d00, 0xffb00f10, "vadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1702
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1703
    0xf2100d00, 0xffb00f10, "vadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1704
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1705
    0xf2000d10, 0xffb00f10, "vmla%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1706
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1707
    0xf2100d10, 0xffb00f10, "vmla%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1708
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1709
    0xf2000e00, 0xffb00f10, "vceq%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1710
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1711
    0xf2100e00, 0xffb00f10, "vceq%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1712
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1713
    0xf2000f00, 0xffb00f10, "vmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1714
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1715
    0xf2100f00, 0xffb00f10, "vmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1716
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1717
    0xf2000f10, 0xffb00f10, "vrecps%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1718
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1719
    0xf2100f10, 0xffb00f10, "vrecps%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1720
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1721
    0xf2200d00, 0xffb00f10, "vsub%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1722
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1723
    0xf2300d00, 0xffb00f10, "vsub%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1724
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1725
    0xf2200d10, 0xffb00f10, "vmls%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1726
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1727
    0xf2300d10, 0xffb00f10, "vmls%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1728
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1729
    0xf2200f00, 0xffb00f10, "vmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1730
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1731
    0xf2300f00, 0xffb00f10, "vmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1732
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1733
    0xf2200f10, 0xffb00f10, "vrsqrts%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1734
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1735
    0xf2300f10, 0xffb00f10, "vrsqrts%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1736
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1737
    0xf3000d00, 0xffb00f10, "vpadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1738
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1739
    0xf3100d00, 0xffb00f10, "vpadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1740
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1741
    0xf3000d10, 0xffb00f10, "vmul%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1742
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1743
    0xf3100d10, 0xffb00f10, "vmul%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1744
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1745
    0xf3000e00, 0xffb00f10, "vcge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1746
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1747
    0xf3100e00, 0xffb00f10, "vcge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1748
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1749
    0xf3000e10, 0xffb00f10, "vacge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1750
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1751
    0xf3100e10, 0xffb00f10, "vacge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1752
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1753
    0xf3000f00, 0xffb00f10, "vpmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1754
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1755
    0xf3100f00, 0xffb00f10, "vpmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1756
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1757
    0xf3200d00, 0xffb00f10, "vabd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1758
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1759
    0xf3300d00, 0xffb00f10, "vabd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1760
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1761
    0xf3200e00, 0xffb00f10, "vcgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1762
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1763
    0xf3300e00, 0xffb00f10, "vcgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1764
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1765
    0xf3200e10, 0xffb00f10, "vacgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1766
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1767
    0xf3300e10, 0xffb00f10, "vacgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1768
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1769
    0xf3200f00, 0xffb00f10, "vpmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1770
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1771
    0xf3300f00, 0xffb00f10, "vpmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1772
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1773
    0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1774
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1775
    0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1776
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1777
    0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1778
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1779
    0xf2000b00, 0xff800f10,
1780
    "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1781
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1782
    0xf2000b10, 0xff800f10,
1783
    "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1784
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1785
    0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1786
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1787
    0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1788
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1789
    0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1790
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1791
    0xf3000b00, 0xff800f10,
1792
    "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1793
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1794
    0xf2000000, 0xfe800f10,
1795
    "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1796
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1797
    0xf2000010, 0xfe800f10,
1798
    "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1799
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1800
    0xf2000100, 0xfe800f10,
1801
    "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1802
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1803
    0xf2000200, 0xfe800f10,
1804
    "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1805
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1806
    0xf2000210, 0xfe800f10,
1807
    "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1808
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1809
    0xf2000300, 0xfe800f10,
1810
    "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1811
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1812
    0xf2000310, 0xfe800f10,
1813
    "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1814
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1815
    0xf2000400, 0xfe800f10,
1816
    "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1817
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1818
    0xf2000410, 0xfe800f10,
1819
    "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1820
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1821
    0xf2000500, 0xfe800f10,
1822
    "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1823
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1824
    0xf2000510, 0xfe800f10,
1825
    "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1826
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1827
    0xf2000600, 0xfe800f10,
1828
    "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1829
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1830
    0xf2000610, 0xfe800f10,
1831
    "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1832
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1833
    0xf2000700, 0xfe800f10,
1834
    "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1835
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1836
    0xf2000710, 0xfe800f10,
1837
    "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1838
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1839
    0xf2000910, 0xfe800f10,
1840
    "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1841
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1842
    0xf2000a00, 0xfe800f10,
1843
    "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1844
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1845
    0xf2000a10, 0xfe800f10,
1846
    "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1847
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1848
    0xf3000b10, 0xff800f10,
1849
    "vqrdmlah%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1850
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1851
    0xf3000c10, 0xff800f10,
1852
    "vqrdmlsh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1853
1854
  /* One register and an immediate value.  */
1855
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1856
    0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"},
1857
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1858
    0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"},
1859
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1860
    0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"},
1861
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1862
    0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"},
1863
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1864
    0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"},
1865
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1866
    0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"},
1867
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1868
    0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"},
1869
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1870
    0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"},
1871
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1872
    0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"},
1873
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1874
    0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"},
1875
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1876
    0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"},
1877
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1878
    0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"},
1879
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1880
    0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"},
1881
1882
  /* Two registers and a shift amount.  */
1883
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1884
    0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, %{I:#%16-18e%}"},
1885
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1886
    0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, %{I:#%16-18e%}"},
1887
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1888
    0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, %{I:#%16-18e%}"},
1889
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1890
    0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, %{I:#%16-18e%}"},
1891
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1892
    0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, %{I:#%16-18e%}"},
1893
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1894
    0xf2880950, 0xfeb80fd0,
1895
    "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, %{I:#%16-18e%}"},
1896
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1897
    0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, %{I:#%16-18d%}"},
1898
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1899
    0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, %{I:#%16-19e%}"},
1900
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1901
    0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, %{I:#%16-19e%}"},
1902
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1903
    0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, %{I:#%16-18d%}"},
1904
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1905
    0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, %{I:#%16-18e%}"},
1906
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1907
    0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, %{I:#%16-18d%}"},
1908
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1909
    0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, %{I:#%16-18d%}"},
1910
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1911
    0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, %{I:#%16-19e%}"},
1912
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1913
    0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, %{I:#%16-19e%}"},
1914
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1915
    0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, %{I:#%16-19e%}"},
1916
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1917
    0xf2900950, 0xfeb00fd0,
1918
    "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, %{I:#%16-19e%}"},
1919
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1920
    0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, %{I:#%16-19d%}"},
1921
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1922
    0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, %{I:#%16-18e%}"},
1923
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1924
    0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, %{I:#%16-18e%}"},
1925
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1926
    0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, %{I:#%16-18e%}"},
1927
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1928
    0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, %{I:#%16-18e%}"},
1929
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1930
    0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, %{I:#%16-18d%}"},
1931
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1932
    0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, %{I:#%16-20e%}"},
1933
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1934
    0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, %{I:#%16-20e%}"},
1935
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1936
    0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, %{I:#%16-19d%}"},
1937
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1938
    0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, %{I:#%16-19e%}"},
1939
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1940
    0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, %{I:#%16-19d%}"},
1941
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1942
    0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, %{I:#%16-19d%}"},
1943
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1944
    0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, %{I:#%16-20d%}"},
1945
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1946
    0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, %{I:#%16-19e%}"},
1947
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1948
    0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, %{I:#%16-19e%}"},
1949
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1950
    0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, %{I:#%16-19e%}"},
1951
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1952
    0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, %{I:#%16-19e%}"},
1953
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1954
    0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, %{I:#%16-19d%}"},
1955
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1956
    0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, %{I:#%16-20e%}"},
1957
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1958
    0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, %{I:#%16-20e%}"},
1959
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1960
    0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, %{I:#%16-20e%}"},
1961
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1962
    0xf2a00950, 0xfea00fd0,
1963
    "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, %{I:#%16-20e%}"},
1964
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1965
    0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, %{I:#%16-20d%}"},
1966
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1967
    0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, %{I:#%16-20e%}"},
1968
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1969
    0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, %{I:#%16-20d%}"},
1970
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1971
    0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, %{I:#%16-20d%}"},
1972
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1973
    0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, %{I:#%16-20e%}"},
1974
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1975
    0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, %{I:#%16-20e%}"},
1976
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1977
    0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, %{I:#%16-20e%}"},
1978
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1979
    0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, %{I:#%16-20e%}"},
1980
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1981
    0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, %{I:#%16-20d%}"},
1982
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1983
    0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, %{I:#%16-21d%}"},
1984
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1985
    0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, %{I:#%16-21e%}"},
1986
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1987
    0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, %{I:#%16-21d%}"},
1988
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1989
    0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, %{I:#%16-21d%}"},
1990
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1991
    0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, %{I:#%16-21e%}"},
1992
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1993
    0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, %{I:#%16-21e%}"},
1994
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1995
    0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, %{I:#%16-21e%}"},
1996
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1997
    0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, %{I:#%16-21e%}"},
1998
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1999
    0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, %{I:#%16-21d%}"},
2000
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2001
    0xf2a00e10, 0xfea00e90,
2002
    "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, %{I:#%16-20e%}"},
2003
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
2004
    0xf2a00c10, 0xfea00e90,
2005
    "vcvt%c.%24,8?usff16.%24,8?ffus16\t%12-15,22R, %0-3,5R, %{I:#%16-20e%}"},
2006
2007
  /* Three registers of different lengths.  */
2008
  {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
2009
    0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2010
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2011
    0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2012
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2013
    0xf2800400, 0xff800f50,
2014
    "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
2015
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2016
    0xf2800600, 0xff800f50,
2017
    "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
2018
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2019
    0xf2800900, 0xff800f50,
2020
    "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2021
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2022
    0xf2800b00, 0xff800f50,
2023
    "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2024
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2025
    0xf2800d00, 0xff800f50,
2026
    "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2027
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2028
    0xf3800400, 0xff800f50,
2029
    "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
2030
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2031
    0xf3800600, 0xff800f50,
2032
    "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
2033
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2034
    0xf2800000, 0xfe800f50,
2035
    "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2036
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2037
    0xf2800100, 0xfe800f50,
2038
    "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
2039
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2040
    0xf2800200, 0xfe800f50,
2041
    "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2042
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2043
    0xf2800300, 0xfe800f50,
2044
    "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
2045
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2046
    0xf2800500, 0xfe800f50,
2047
    "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2048
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2049
    0xf2800700, 0xfe800f50,
2050
    "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2051
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2052
    0xf2800800, 0xfe800f50,
2053
    "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2054
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2055
    0xf2800a00, 0xfe800f50,
2056
    "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2057
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2058
    0xf2800c00, 0xfe800f50,
2059
    "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2060
2061
  /* Two registers and a scalar.  */
2062
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2063
    0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2064
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2065
    0xf2800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
2066
  {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
2067
    0xf2900140, 0xffb00f50, "vmla%c.f16\t%12-15,22D, %16-19,7D, %D"},
2068
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2069
    0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2070
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2071
    0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2072
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2073
    0xf2800540, 0xff900f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2074
  {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
2075
    0xf2900540, 0xffb00f50, "vmls%c.f16\t%12-15,22D, %16-19,7D, %D"},
2076
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2077
    0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2078
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2079
    0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2080
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2081
    0xf2800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
2082
  {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
2083
    0xf2900940, 0xffb00f50, "vmul%c.f16\t%12-15,22D, %16-19,7D, %D"},
2084
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2085
    0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2086
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2087
    0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2088
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2089
    0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2090
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2091
    0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2092
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2093
    0xf3800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
2094
  {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
2095
    0xf3900140, 0xffb00f50, "vmla%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
2096
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2097
    0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2098
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2099
    0xf3800540, 0xff900f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
2100
  {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
2101
    0xf3900540, 0xffb00f50, "vmls%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
2102
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2103
    0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2104
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2105
    0xf3800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
2106
  {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
2107
    0xf3900940, 0xffb00f50, "vmul%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
2108
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2109
    0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2110
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2111
    0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2112
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2113
    0xf2800240, 0xfe800f50,
2114
    "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2115
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2116
    0xf2800640, 0xfe800f50,
2117
    "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2118
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2119
    0xf2800a40, 0xfe800f50,
2120
    "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2121
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
2122
    0xf2800e40, 0xff800f50,
2123
   "vqrdmlah%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2124
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
2125
    0xf2800f40, 0xff800f50,
2126
   "vqrdmlsh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2127
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
2128
    0xf3800e40, 0xff800f50,
2129
   "vqrdmlah%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2130
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
2131
    0xf3800f40, 0xff800f50,
2132
   "vqrdmlsh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"
2133
  },
2134
2135
  /* Element and structure load/store.  */
2136
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2137
    0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"},
2138
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2139
    0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"},
2140
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2141
    0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"},
2142
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2143
    0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"},
2144
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2145
    0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"},
2146
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2147
    0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
2148
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2149
    0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
2150
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2151
    0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
2152
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2153
    0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
2154
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2155
    0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
2156
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2157
    0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
2158
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2159
    0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
2160
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2161
    0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
2162
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2163
    0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
2164
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2165
    0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"},
2166
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2167
    0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"},
2168
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2169
    0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"},
2170
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2171
    0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"},
2172
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2173
    0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"},
2174
2175
  {ARM_FEATURE_CORE_LOW (0), 0 ,0, 0}
2176
};
2177
2178
/* mve opcode table.  */
2179
2180
/* print_insn_mve recognizes the following format control codes:
2181
2182
   %%     %
2183
2184
   %a     print '+' or '-' or imm offset in vldr[bhwd] and
2185
      vstr[bhwd]
2186
   %c     print condition code
2187
   %d     print addr mode of MVE vldr[bhw] and vstr[bhw]
2188
   %u     print 'U' (unsigned) or 'S' for various mve instructions
2189
   %i     print MVE predicate(s) for vpt and vpst
2190
   %j     print a 5-bit immediate from hw2[14:12,7:6]
2191
   %k     print 48 if the 7th position bit is set else print 64.
2192
   %m     print rounding mode for vcvt and vrint
2193
   %n     print vector comparison code for predicated instruction
2194
   %s     print size for various vcvt instructions
2195
   %v     print vector predicate for instruction in predicated
2196
      block
2197
   %o     print offset scaled for vldr[hwd] and vstr[hwd]
2198
   %w     print writeback mode for MVE v{st,ld}[24]
2199
   %B     print v{st,ld}[24] any one operands
2200
   %E     print vmov, vmvn, vorr, vbic encoded constant
2201
   %N     print generic index for vmov
2202
   %T     print bottom ('b') or top ('t') of source register
2203
   %X     print exchange field in vmla* instructions
2204
2205
   %<bitfield>r   print as an ARM register
2206
   %<bitfield>d   print the bitfield in decimal
2207
   %<bitfield>A   print accumulate or not
2208
   %<bitfield>c   print bitfield as a condition code
2209
   %<bitfield>C   print bitfield as an inverted condition code
2210
   %<bitfield>Q   print as a MVE Q register
2211
   %<bitfield>F   print as a MVE S register
2212
   %<bitfield>Z   as %<>r but r15 is ZR instead of PC and r13 is
2213
      UNPREDICTABLE
2214
2215
   %<bitfield>S   as %<>r but r15 or r13 is UNPREDICTABLE
2216
   %<bitfield>s   print size for vector predicate & non VMOV instructions
2217
   %<bitfield>I   print carry flag or not
2218
   %<bitfield>i   print immediate for vstr/vldr reg +/- imm
2219
   %<bitfield>h   print high half of 64-bit destination reg
2220
   %<bitfield>k   print immediate for vector conversion instruction
2221
   %<bitfield>l   print low half of 64-bit destination reg
2222
   %<bitfield>o   print rotate value for vcmul
2223
   %<bitfield>u   print immediate value for vddup/vdwdup
2224
   %<bitfield>x   print the bitfield in hex.
2225
  */
2226
2227
static const struct mopcode32 mve_opcodes[] =
2228
{
2229
  /* MVE.  */
2230
2231
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2232
   MVE_VPST,
2233
   0xfe310f4d, 0xffbf1fff,
2234
   "vpst%i"
2235
  },
2236
2237
  /* Floating point VPT T1.  */
2238
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2239
   MVE_VPT_FP_T1,
2240
   0xee310f00, 0xefb10f50,
2241
   "vpt%i.f%28s\t%n, %17-19Q, %1-3,5Q"},
2242
  /* Floating point VPT T2.  */
2243
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2244
   MVE_VPT_FP_T2,
2245
   0xee310f40, 0xefb10f50,
2246
   "vpt%i.f%28s\t%n, %17-19Q, %0-3Z"},
2247
2248
  /* Vector VPT T1.  */
2249
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2250
   MVE_VPT_VEC_T1,
2251
   0xfe010f00, 0xff811f51,
2252
   "vpt%i.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
2253
  /* Vector VPT T2.  */
2254
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2255
   MVE_VPT_VEC_T2,
2256
   0xfe010f01, 0xff811f51,
2257
   "vpt%i.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
2258
  /* Vector VPT T3.  */
2259
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2260
   MVE_VPT_VEC_T3,
2261
   0xfe011f00, 0xff811f50,
2262
   "vpt%i.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
2263
  /* Vector VPT T4.  */
2264
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2265
   MVE_VPT_VEC_T4,
2266
   0xfe010f40, 0xff811f70,
2267
   "vpt%i.i%20-21s\t%n, %17-19Q, %0-3Z"},
2268
  /* Vector VPT T5.  */
2269
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2270
   MVE_VPT_VEC_T5,
2271
   0xfe010f60, 0xff811f70,
2272
   "vpt%i.u%20-21s\t%n, %17-19Q, %0-3Z"},
2273
  /* Vector VPT T6.  */
2274
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2275
   MVE_VPT_VEC_T6,
2276
   0xfe011f40, 0xff811f50,
2277
   "vpt%i.s%20-21s\t%n, %17-19Q, %0-3Z"},
2278
2279
  /* Vector VBIC immediate.  */
2280
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2281
   MVE_VBIC_IMM,
2282
   0xef800070, 0xefb81070,
2283
   "vbic%v.i%8-11s\t%13-15,22Q, %E"},
2284
2285
  /* Vector VBIC register.  */
2286
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2287
   MVE_VBIC_REG,
2288
   0xef100150, 0xffb11f51,
2289
   "vbic%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2290
2291
  /* Vector VABAV.  */
2292
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2293
   MVE_VABAV,
2294
   0xee800f01, 0xefc10f51,
2295
   "vabav%v.%u%20-21s\t%12-15r, %17-19,7Q, %1-3,5Q"},
2296
2297
  /* Vector VABD floating point.  */
2298
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2299
   MVE_VABD_FP,
2300
   0xff200d40, 0xffa11f51,
2301
   "vabd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2302
2303
  /* Vector VABD.  */
2304
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2305
   MVE_VABD_VEC,
2306
   0xef000740, 0xef811f51,
2307
   "vabd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2308
2309
  /* Vector VABS floating point.  */
2310
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2311
   MVE_VABS_FP,
2312
   0xFFB10740, 0xFFB31FD1,
2313
   "vabs%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
2314
  /* Vector VABS.  */
2315
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2316
   MVE_VABS_VEC,
2317
   0xffb10340, 0xffb31fd1,
2318
   "vabs%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2319
2320
  /* Vector VADD floating point T1.  */
2321
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2322
   MVE_VADD_FP_T1,
2323
   0xef000d40, 0xffa11f51,
2324
   "vadd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2325
  /* Vector VADD floating point T2.  */
2326
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2327
   MVE_VADD_FP_T2,
2328
   0xee300f40, 0xefb11f70,
2329
   "vadd%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2330
  /* Vector VADD T1.  */
2331
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2332
   MVE_VADD_VEC_T1,
2333
   0xef000840, 0xff811f51,
2334
   "vadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2335
  /* Vector VADD T2.  */
2336
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2337
   MVE_VADD_VEC_T2,
2338
   0xee010f40, 0xff811f70,
2339
   "vadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2340
2341
  /* Vector VADDLV.  */
2342
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2343
   MVE_VADDLV,
2344
   0xee890f00, 0xef8f1fd1,
2345
   "vaddlv%5A%v.%u32\t%13-15l, %20-22h, %1-3Q"},
2346
2347
  /* Vector VADDV.  */
2348
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2349
   MVE_VADDV,
2350
   0xeef10f00, 0xeff31fd1,
2351
   "vaddv%5A%v.%u%18-19s\t%13-15l, %1-3Q"},
2352
2353
  /* Vector VADC.  */
2354
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2355
   MVE_VADC,
2356
   0xee300f00, 0xffb10f51,
2357
   "vadc%12I%v.i32\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2358
2359
  /* Vector VAND.  */
2360
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2361
   MVE_VAND,
2362
   0xef000150, 0xffb11f51,
2363
   "vand%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2364
2365
  /* Vector VBRSR register.  */
2366
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2367
   MVE_VBRSR,
2368
   0xfe011e60, 0xff811f70,
2369
   "vbrsr%v.%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2370
2371
  /* Vector VCADD floating point.  */
2372
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2373
   MVE_VCADD_FP,
2374
   0xfc800840, 0xfea11f51,
2375
   "vcadd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, %{I:#%24o%}"},
2376
2377
  /* Vector VCADD.  */
2378
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2379
   MVE_VCADD_VEC,
2380
   0xfe000f00, 0xff810f51,
2381
   "vcadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, %{I:#%12o%}"},
2382
2383
  /* Vector VCLS.  */
2384
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2385
   MVE_VCLS,
2386
   0xffb00440, 0xffb31fd1,
2387
   "vcls%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2388
2389
  /* Vector VCLZ.  */
2390
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2391
   MVE_VCLZ,
2392
   0xffb004c0, 0xffb31fd1,
2393
   "vclz%v.i%18-19s\t%13-15,22Q, %1-3,5Q"},
2394
2395
  /* Vector VCMLA.  */
2396
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2397
   MVE_VCMLA_FP,
2398
   0xfc200840, 0xfe211f51,
2399
   "vcmla%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, %{I:#%23-24o%}"},
2400
2401
  /* Vector VCMP floating point T1.  */
2402
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2403
   MVE_VCMP_FP_T1,
2404
   0xee310f00, 0xeff1ef50,
2405
   "vcmp%v.f%28s\t%n, %17-19Q, %1-3,5Q"},
2406
2407
  /* Vector VCMP floating point T2.  */
2408
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2409
   MVE_VCMP_FP_T2,
2410
   0xee310f40, 0xeff1ef50,
2411
   "vcmp%v.f%28s\t%n, %17-19Q, %0-3Z"},
2412
2413
  /* Vector VCMP T1.  */
2414
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2415
   MVE_VCMP_VEC_T1,
2416
   0xfe010f00, 0xffc1ff51,
2417
   "vcmp%v.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
2418
  /* Vector VCMP T2.  */
2419
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2420
   MVE_VCMP_VEC_T2,
2421
   0xfe010f01, 0xffc1ff51,
2422
   "vcmp%v.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
2423
  /* Vector VCMP T3.  */
2424
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2425
   MVE_VCMP_VEC_T3,
2426
   0xfe011f00, 0xffc1ff50,
2427
   "vcmp%v.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
2428
  /* Vector VCMP T4.  */
2429
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2430
   MVE_VCMP_VEC_T4,
2431
   0xfe010f40, 0xffc1ff70,
2432
   "vcmp%v.i%20-21s\t%n, %17-19Q, %0-3Z"},
2433
  /* Vector VCMP T5.  */
2434
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2435
   MVE_VCMP_VEC_T5,
2436
   0xfe010f60, 0xffc1ff70,
2437
   "vcmp%v.u%20-21s\t%n, %17-19Q, %0-3Z"},
2438
  /* Vector VCMP T6.  */
2439
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2440
   MVE_VCMP_VEC_T6,
2441
   0xfe011f40, 0xffc1ff50,
2442
   "vcmp%v.s%20-21s\t%n, %17-19Q, %0-3Z"},
2443
2444
  /* Vector VDUP.  */
2445
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2446
   MVE_VDUP,
2447
   0xeea00b10, 0xffb10f5f,
2448
   "vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
2449
2450
  /* Vector VEOR.  */
2451
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2452
   MVE_VEOR,
2453
   0xff000150, 0xffd11f51,
2454
   "veor%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2455
2456
  /* Vector VFMA, vector * scalar.  */
2457
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2458
   MVE_VFMA_FP_SCALAR,
2459
   0xee310e40, 0xefb11f70,
2460
   "vfma%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2461
2462
  /* Vector VFMA floating point.  */
2463
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2464
   MVE_VFMA_FP,
2465
   0xef000c50, 0xffa11f51,
2466
   "vfma%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2467
2468
  /* Vector VFMS floating point.  */
2469
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2470
   MVE_VFMS_FP,
2471
   0xef200c50, 0xffa11f51,
2472
   "vfms%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2473
2474
  /* Vector VFMAS, vector * scalar.  */
2475
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2476
   MVE_VFMAS_FP_SCALAR,
2477
   0xee311e40, 0xefb11f70,
2478
   "vfmas%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2479
2480
  /* Vector VHADD T1.  */
2481
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2482
   MVE_VHADD_T1,
2483
   0xef000040, 0xef811f51,
2484
   "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2485
2486
  /* Vector VHADD T2.  */
2487
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2488
   MVE_VHADD_T2,
2489
   0xee000f40, 0xef811f70,
2490
   "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2491
2492
  /* Vector VHSUB T1.  */
2493
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2494
   MVE_VHSUB_T1,
2495
   0xef000240, 0xef811f51,
2496
   "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2497
2498
  /* Vector VHSUB T2.  */
2499
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2500
   MVE_VHSUB_T2,
2501
   0xee001f40, 0xef811f70,
2502
   "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2503
2504
  /* Vector VCMUL.  */
2505
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2506
   MVE_VCMUL_FP,
2507
   0xee300e00, 0xefb10f50,
2508
   "vcmul%v.f%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, %{I:#%0,12o%}"},
2509
2510
   /* Vector VCTP.  */
2511
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2512
   MVE_VCTP,
2513
   0xf000e801, 0xffc0ffff,
2514
   "vctp%v.%20-21s\t%16-19r"},
2515
2516
  /* Vector VDUP.  */
2517
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2518
   MVE_VDUP,
2519
   0xeea00b10, 0xffb10f5f,
2520
   "vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
2521
2522
  /* Vector VRHADD.  */
2523
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2524
   MVE_VRHADD,
2525
   0xef000140, 0xef811f51,
2526
   "vrhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2527
2528
  /* Vector VCVT.  */
2529
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2530
   MVE_VCVT_FP_FIX_VEC,
2531
   0xef800c50, 0xef801cd1,
2532
   "vcvt%v.%s\t%13-15,22Q, %1-3,5Q, %{I:#%16-21k%}"},
2533
2534
  /* Vector VCVT.  */
2535
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2536
   MVE_VCVT_BETWEEN_FP_INT,
2537
   0xffb30640, 0xffb31e51,
2538
   "vcvt%v.%s\t%13-15,22Q, %1-3,5Q"},
2539
2540
  /* Vector VCVT between single and half-precision float, bottom half.  */
2541
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2542
   MVE_VCVT_FP_HALF_FP,
2543
   0xee3f0e01, 0xefbf1fd1,
2544
   "vcvtb%v.%s\t%13-15,22Q, %1-3,5Q"},
2545
2546
  /* Vector VCVT between single and half-precision float, top half.  */
2547
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2548
   MVE_VCVT_FP_HALF_FP,
2549
   0xee3f1e01, 0xefbf1fd1,
2550
   "vcvtt%v.%s\t%13-15,22Q, %1-3,5Q"},
2551
2552
  /* Vector VCVT.  */
2553
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2554
   MVE_VCVT_FROM_FP_TO_INT,
2555
   0xffb30040, 0xffb31c51,
2556
   "vcvt%m%v.%s\t%13-15,22Q, %1-3,5Q"},
2557
2558
  /* Vector VDDUP.  */
2559
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2560
   MVE_VDDUP,
2561
   0xee011f6e, 0xff811f7e,
2562
   "vddup%v.u%20-21s\t%13-15,22Q, %17-19l, %{I:#%0,7u%}"},
2563
2564
  /* Vector VDWDUP.  */
2565
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2566
   MVE_VDWDUP,
2567
   0xee011f60, 0xff811f70,
2568
   "vdwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, %{I:#%0,7u%}"},
2569
2570
  /* Vector VHCADD.  */
2571
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2572
   MVE_VHCADD,
2573
   0xee000f00, 0xff810f51,
2574
   "vhcadd%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, %{I:#%12o%}"},
2575
2576
  /* Vector VIWDUP.  */
2577
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2578
   MVE_VIWDUP,
2579
   0xee010f60, 0xff811f70,
2580
   "viwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, %{I:#%0,7u%}"},
2581
2582
  /* Vector VIDUP.  */
2583
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2584
   MVE_VIDUP,
2585
   0xee010f6e, 0xff811f7e,
2586
   "vidup%v.u%20-21s\t%13-15,22Q, %17-19l, %{I:#%0,7u%}"},
2587
2588
  /* Vector VLD2.  */
2589
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2590
   MVE_VLD2,
2591
   0xfc901e00, 0xff901e5f,
2592
   "vld2%5d.%7-8s\t%B, [%16-19r]%w"},
2593
2594
  /* Vector VLD4.  */
2595
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2596
   MVE_VLD4,
2597
   0xfc901e01, 0xff901e1f,
2598
   "vld4%5-6d.%7-8s\t%B, [%16-19r]%w"},
2599
2600
  /* Vector VLDRB gather load.  */
2601
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2602
   MVE_VLDRB_GATHER_T1,
2603
   0xec900e00, 0xefb01e50,
2604
   "vldrb%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"},
2605
2606
  /* Vector VLDRH gather load.  */
2607
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2608
   MVE_VLDRH_GATHER_T2,
2609
   0xec900e10, 0xefb01e50,
2610
   "vldrh%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2611
2612
  /* Vector VLDRW gather load.  */
2613
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2614
   MVE_VLDRW_GATHER_T3,
2615
   0xfc900f40, 0xffb01fd0,
2616
   "vldrw%v.u32\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2617
2618
  /* Vector VLDRD gather load.  */
2619
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2620
   MVE_VLDRD_GATHER_T4,
2621
   0xec900fd0, 0xefb01fd0,
2622
   "vldrd%v.u64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2623
2624
  /* Vector VLDRW gather load.  */
2625
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2626
   MVE_VLDRW_GATHER_T5,
2627
   0xfd101e00, 0xff111f00,
2628
   "vldrw%v.u32\t%13-15,22Q, [%17-19,7Q, %{I:#%a%0-6i%}]%w"},
2629
2630
  /* Vector VLDRD gather load, variant T6.  */
2631
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2632
   MVE_VLDRD_GATHER_T6,
2633
   0xfd101f00, 0xff111f00,
2634
   "vldrd%v.u64\t%13-15,22Q, [%17-19,7Q, %{I:#%a%0-6i%}]%w"},
2635
2636
  /* Vector VLDRB.  */
2637
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2638
   MVE_VLDRB_T1,
2639
   0xec100e00, 0xee581e00,
2640
   "vldrb%v.%u%7-8s\t%13-15Q, %d"},
2641
2642
  /* Vector VLDRH.  */
2643
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2644
   MVE_VLDRH_T2,
2645
   0xec180e00, 0xee581e00,
2646
   "vldrh%v.%u%7-8s\t%13-15Q, %d"},
2647
2648
  /* Vector VLDRB unsigned, variant T5.  */
2649
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2650
   MVE_VLDRB_T5,
2651
   0xec101e00, 0xfe101f80,
2652
   "vldrb%v.u8\t%13-15,22Q, %d"},
2653
2654
  /* Vector VLDRH unsigned, variant T6.  */
2655
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2656
   MVE_VLDRH_T6,
2657
   0xec101e80, 0xfe101f80,
2658
   "vldrh%v.u16\t%13-15,22Q, %d"},
2659
2660
  /* Vector VLDRW unsigned, variant T7.  */
2661
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2662
   MVE_VLDRW_T7,
2663
   0xec101f00, 0xfe101f80,
2664
   "vldrw%v.u32\t%13-15,22Q, %d"},
2665
2666
  /* Vector VMAX.  */
2667
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2668
   MVE_VMAX,
2669
   0xef000640, 0xef811f51,
2670
   "vmax%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2671
2672
  /* Vector VMAXA.  */
2673
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2674
   MVE_VMAXA,
2675
   0xee330e81, 0xffb31fd1,
2676
   "vmaxa%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2677
2678
  /* Vector VMAXNM floating point.  */
2679
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2680
   MVE_VMAXNM_FP,
2681
   0xff000f50, 0xffa11f51,
2682
   "vmaxnm%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2683
2684
  /* Vector VMAXNMA floating point.  */
2685
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2686
   MVE_VMAXNMA_FP,
2687
   0xee3f0e81, 0xefbf1fd1,
2688
   "vmaxnma%v.f%28s\t%13-15,22Q, %1-3,5Q"},
2689
2690
  /* Vector VMAXNMV floating point.  */
2691
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2692
   MVE_VMAXNMV_FP,
2693
   0xeeee0f00, 0xefff0fd1,
2694
   "vmaxnmv%v.f%28s\t%12-15r, %1-3,5Q"},
2695
2696
  /* Vector VMAXNMAV floating point.  */
2697
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2698
   MVE_VMAXNMAV_FP,
2699
   0xeeec0f00, 0xefff0fd1,
2700
   "vmaxnmav%v.f%28s\t%12-15r, %1-3,5Q"},
2701
2702
  /* Vector VMAXV.  */
2703
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2704
   MVE_VMAXV,
2705
   0xeee20f00, 0xeff30fd1,
2706
   "vmaxv%v.%u%18-19s\t%12-15r, %1-3,5Q"},
2707
2708
  /* Vector VMAXAV.  */
2709
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2710
   MVE_VMAXAV,
2711
   0xeee00f00, 0xfff30fd1,
2712
   "vmaxav%v.s%18-19s\t%12-15r, %1-3,5Q"},
2713
2714
  /* Vector VMIN.  */
2715
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2716
   MVE_VMIN,
2717
   0xef000650, 0xef811f51,
2718
   "vmin%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2719
2720
  /* Vector VMINA.  */
2721
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2722
   MVE_VMINA,
2723
   0xee331e81, 0xffb31fd1,
2724
   "vmina%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2725
2726
  /* Vector VMINNM floating point.  */
2727
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2728
   MVE_VMINNM_FP,
2729
   0xff200f50, 0xffa11f51,
2730
   "vminnm%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2731
2732
  /* Vector VMINNMA floating point.  */
2733
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2734
   MVE_VMINNMA_FP,
2735
   0xee3f1e81, 0xefbf1fd1,
2736
   "vminnma%v.f%28s\t%13-15,22Q, %1-3,5Q"},
2737
2738
  /* Vector VMINNMV floating point.  */
2739
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2740
   MVE_VMINNMV_FP,
2741
   0xeeee0f80, 0xefff0fd1,
2742
   "vminnmv%v.f%28s\t%12-15r, %1-3,5Q"},
2743
2744
  /* Vector VMINNMAV floating point.  */
2745
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2746
   MVE_VMINNMAV_FP,
2747
   0xeeec0f80, 0xefff0fd1,
2748
   "vminnmav%v.f%28s\t%12-15r, %1-3,5Q"},
2749
2750
  /* Vector VMINV.  */
2751
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2752
   MVE_VMINV,
2753
   0xeee20f80, 0xeff30fd1,
2754
   "vminv%v.%u%18-19s\t%12-15r, %1-3,5Q"},
2755
2756
  /* Vector VMINAV.  */
2757
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2758
   MVE_VMINAV,
2759
   0xeee00f80, 0xfff30fd1,
2760
   "vminav%v.s%18-19s\t%12-15r, %1-3,5Q"},
2761
2762
  /* Vector VMLA.  */
2763
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2764
   MVE_VMLA,
2765
   0xee010e40, 0xef811f70,
2766
   "vmla%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2767
2768
  /* Vector VMLALDAV.  Note must appear before VMLADAV due to instruction
2769
     opcode aliasing.  */
2770
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2771
   MVE_VMLALDAV,
2772
   0xee801e00, 0xef801f51,
2773
   "vmlaldav%5Ax%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2774
2775
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2776
   MVE_VMLALDAV,
2777
   0xee800e00, 0xef801f51,
2778
   "vmlalv%5A%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2779
2780
  /* Vector VMLAV T1 variant, same as VMLADAV but with X == 0.  */
2781
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2782
   MVE_VMLADAV_T1,
2783
   0xeef00e00, 0xeff01f51,
2784
   "vmlav%5A%v.%u%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2785
2786
  /* Vector VMLAV T2 variant, same as VMLADAV but with X == 0.  */
2787
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2788
   MVE_VMLADAV_T2,
2789
   0xeef00f00, 0xeff11f51,
2790
   "vmlav%5A%v.%u8\t%13-15l, %17-19,7Q, %1-3Q"},
2791
2792
  /* Vector VMLADAV T1 variant.  */
2793
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2794
   MVE_VMLADAV_T1,
2795
   0xeef01e00, 0xeff01f51,
2796
   "vmladav%5Ax%v.%u%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2797
2798
  /* Vector VMLADAV T2 variant.  */
2799
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2800
   MVE_VMLADAV_T2,
2801
   0xeef01f00, 0xeff11f51,
2802
   "vmladav%5Ax%v.%u8\t%13-15l, %17-19,7Q, %1-3Q"},
2803
2804
  /* Vector VMLAS.  */
2805
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2806
   MVE_VMLAS,
2807
   0xee011e40, 0xef811f70,
2808
   "vmlas%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2809
2810
  /* Vector VRMLSLDAVH.  Note must appear before VMLSDAV due to instruction
2811
     opcode aliasing.  */
2812
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2813
   MVE_VRMLSLDAVH,
2814
   0xfe800e01, 0xff810f51,
2815
   "vrmlsldavh%5A%X%v.s32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2816
2817
  /* Vector VMLSLDAV.  Note must appear before VMLSDAV due to instruction
2818
     opcdoe aliasing.  */
2819
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2820
   MVE_VMLSLDAV,
2821
   0xee800e01, 0xff800f51,
2822
   "vmlsldav%5A%X%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2823
2824
  /* Vector VMLSDAV T1 Variant.  */
2825
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2826
   MVE_VMLSDAV_T1,
2827
   0xeef00e01, 0xfff00f51,
2828
   "vmlsdav%5A%X%v.s%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2829
2830
  /* Vector VMLSDAV T2 Variant.  */
2831
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2832
   MVE_VMLSDAV_T2,
2833
   0xfef00e01, 0xfff10f51,
2834
   "vmlsdav%5A%X%v.s8\t%13-15l, %17-19,7Q, %1-3Q"},
2835
2836
  /* Vector VMOV between gpr and half precision register, op == 0.  */
2837
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2838
   MVE_VMOV_HFP_TO_GP,
2839
   0xee000910, 0xfff00f7f,
2840
   "vmov.f16\t%7,16-19F, %12-15r"},
2841
2842
  /* Vector VMOV between gpr and half precision register, op == 1.  */
2843
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2844
   MVE_VMOV_HFP_TO_GP,
2845
   0xee100910, 0xfff00f7f,
2846
   "vmov.f16\t%12-15r, %7,16-19F"},
2847
2848
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2849
   MVE_VMOV_GP_TO_VEC_LANE,
2850
   0xee000b10, 0xff900f1f,
2851
   "vmov%c.%5-6,21-22s\t%{R:%17-19,7Q[%N]%}, %12-15r"},
2852
2853
  /* Vector VORR immediate to vector.
2854
     NOTE: MVE_VORR_IMM must appear in the table
2855
     before MVE_VMOV_IMM_TO_VEC due to opcode aliasing.  */
2856
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2857
   MVE_VORR_IMM,
2858
   0xef800050, 0xefb810f0,
2859
   "vorr%v.i%8-11s\t%13-15,22Q, %E"},
2860
2861
  /* Vector VQSHL T2 Variant.
2862
     NOTE: MVE_VQSHL_T2 must appear in the table before
2863
     before MVE_VMOV_IMM_TO_VEC due to opcode aliasing.  */
2864
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2865
   MVE_VQSHL_T2,
2866
   0xef800750, 0xef801fd1,
2867
   "vqshl%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
2868
2869
  /* Vector VQSHLU T3 Variant
2870
     NOTE: MVE_VQSHL_T2 must appear in the table before
2871
     before MVE_VMOV_IMM_TO_VEC due to opcode aliasing.  */
2872
2873
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2874
   MVE_VQSHLU_T3,
2875
   0xff800650, 0xff801fd1,
2876
   "vqshlu%v.s%19-21s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
2877
2878
  /* Vector VRSHR
2879
     NOTE: MVE_VRSHR must appear in the table before
2880
     before MVE_VMOV_IMM_TO_VEC due to opcode aliasing.  */
2881
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2882
   MVE_VRSHR,
2883
   0xef800250, 0xef801fd1,
2884
   "vrshr%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
2885
2886
  /* Vector VSHL.
2887
     NOTE: MVE_VSHL must appear in the table before
2888
     before MVE_VMOV_IMM_TO_VEC due to opcode aliasing.  */
2889
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2890
   MVE_VSHL_T1,
2891
   0xef800550, 0xff801fd1,
2892
   "vshl%v.i%19-21s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
2893
2894
  /* Vector VSHR
2895
     NOTE: MVE_VSHR must appear in the table before
2896
     before MVE_VMOV_IMM_TO_VEC due to opcode aliasing.  */
2897
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2898
   MVE_VSHR,
2899
   0xef800050, 0xef801fd1,
2900
   "vshr%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
2901
2902
  /* Vector VSLI
2903
     NOTE: MVE_VSLI must appear in the table before
2904
     before MVE_VMOV_IMM_TO_VEC due to opcode aliasing.  */
2905
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2906
   MVE_VSLI,
2907
   0xff800550, 0xff801fd1,
2908
   "vsli%v.%19-21s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
2909
2910
  /* Vector VSRI
2911
     NOTE: MVE_VSRI must appear in the table before
2912
     before MVE_VMOV_IMM_TO_VEC due to opcode aliasing.  */
2913
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2914
   MVE_VSRI,
2915
   0xff800450, 0xff801fd1,
2916
   "vsri%v.%19-21s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
2917
2918
  /* Vector VMOV immediate to vector,
2919
     undefinded for cmode == 1111 */
2920
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2921
   MVE_VMVN_IMM, 0xef800f70, 0xefb81ff0, UNDEFINED_INSTRUCTION},
2922
2923
  /* Vector VMOV immediate to vector,
2924
     cmode == 1101 */
2925
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2926
   MVE_VMOV_IMM_TO_VEC, 0xef800d50, 0xefb81fd0,
2927
   "vmov%v.%5,8-11s\t%13-15,22Q, %E"},
2928
2929
  /* Vector VMOV immediate to vector.  */
2930
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2931
   MVE_VMOV_IMM_TO_VEC,
2932
   0xef800050, 0xefb810d0,
2933
   "vmov%v.%5,8-11s\t%13-15,22Q, %E"},
2934
2935
  /* Vector VMOV two 32-bit lanes to two gprs, idx = 0.  */
2936
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2937
   MVE_VMOV2_VEC_LANE_TO_GP,
2938
   0xec000f00, 0xffb01ff0,
2939
   "vmov%c\t%0-3r, %16-19r, %{R:%13-15,22Q[2]%}, %{R:%13-15,22Q[0]%}"},
2940
2941
  /* Vector VMOV two 32-bit lanes to two gprs, idx = 1.  */
2942
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2943
   MVE_VMOV2_VEC_LANE_TO_GP,
2944
   0xec000f10, 0xffb01ff0,
2945
   "vmov%c\t%0-3r, %16-19r, %{R:%13-15,22Q[3]%}, %{R:%13-15,22Q[1]%}"},
2946
2947
  /* Vector VMOV Two gprs to two 32-bit lanes, idx = 0.  */
2948
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2949
   MVE_VMOV2_GP_TO_VEC_LANE,
2950
   0xec100f00, 0xffb01ff0,
2951
   "vmov%c\t%{R:%13-15,22Q[2]%}, %{R:%13-15,22Q[0]%}, %0-3r, %16-19r"},
2952
2953
  /* Vector VMOV Two gprs to two 32-bit lanes, idx = 1.  */
2954
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2955
   MVE_VMOV2_GP_TO_VEC_LANE,
2956
   0xec100f10, 0xffb01ff0,
2957
   "vmov%c\t%{R:%13-15,22Q[3]%}, %{R:%13-15,22Q[1]%}, %0-3r, %16-19r"},
2958
2959
  /* Vector VMOV Vector lane to gpr.  */
2960
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2961
   MVE_VMOV_VEC_LANE_TO_GP,
2962
   0xee100b10, 0xff100f1f,
2963
   "vmov%c.%u%5-6,21-22s\t%12-15r, %{R:%17-19,7Q[%N]%}"},
2964
2965
  /* Vector VSHLL T1 Variant.  Note: VSHLL T1 must appear before MVE_VMOVL due
2966
     to instruction opcode aliasing.  */
2967
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2968
   MVE_VSHLL_T1,
2969
   0xeea00f40, 0xefa00fd1,
2970
   "vshll%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
2971
2972
  /* Vector VMOVL long.  */
2973
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2974
   MVE_VMOVL,
2975
   0xeea00f40, 0xefa70fd1,
2976
   "vmovl%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q"},
2977
2978
  /* Vector VMOV and narrow.  */
2979
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2980
   MVE_VMOVN,
2981
   0xfe310e81, 0xffb30fd1,
2982
   "vmovn%T%v.i%18-19s\t%13-15,22Q, %1-3,5Q"},
2983
2984
  /* Floating point move extract.  */
2985
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2986
   MVE_VMOVX,
2987
   0xfeb00a40, 0xffbf0fd0,
2988
   "vmovx.f16\t%22,12-15F, %5,0-3F"},
2989
2990
  /* Vector VMUL floating-point T1 variant.  */
2991
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2992
   MVE_VMUL_FP_T1,
2993
   0xff000d50, 0xffa11f51,
2994
   "vmul%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2995
2996
  /* Vector VMUL floating-point T2 variant.  */
2997
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2998
   MVE_VMUL_FP_T2,
2999
   0xee310e60, 0xefb11f70,
3000
   "vmul%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3001
3002
  /* Vector VMUL T1 variant.  */
3003
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3004
   MVE_VMUL_VEC_T1,
3005
   0xef000950, 0xff811f51,
3006
   "vmul%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3007
3008
  /* Vector VMUL T2 variant.  */
3009
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3010
   MVE_VMUL_VEC_T2,
3011
   0xee011e60, 0xff811f70,
3012
   "vmul%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3013
3014
  /* Vector VMULH.  */
3015
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3016
   MVE_VMULH,
3017
   0xee010e01, 0xef811f51,
3018
   "vmulh%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3019
3020
  /* Vector VRMULH.  */
3021
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3022
   MVE_VRMULH,
3023
   0xee011e01, 0xef811f51,
3024
   "vrmulh%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3025
3026
  /* Vector VMULL integer.  */
3027
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3028
   MVE_VMULL_INT,
3029
   0xee010e00, 0xef810f51,
3030
   "vmull%T%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3031
3032
  /* Vector VMULL polynomial.  */
3033
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3034
   MVE_VMULL_POLY,
3035
   0xee310e00, 0xefb10f51,
3036
   "vmull%T%v.%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3037
3038
  /* Vector VMVN immediate to vector.  */
3039
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3040
   MVE_VMVN_IMM,
3041
   0xef800070, 0xefb810f0,
3042
   "vmvn%v.i%8-11s\t%13-15,22Q, %E"},
3043
3044
  /* Vector VMVN register.  */
3045
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3046
   MVE_VMVN_REG,
3047
   0xffb005c0, 0xffbf1fd1,
3048
   "vmvn%v\t%13-15,22Q, %1-3,5Q"},
3049
3050
  /* Vector VNEG floating point.  */
3051
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
3052
   MVE_VNEG_FP,
3053
   0xffb107c0, 0xffb31fd1,
3054
   "vneg%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
3055
3056
  /* Vector VNEG.  */
3057
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3058
   MVE_VNEG_VEC,
3059
   0xffb103c0, 0xffb31fd1,
3060
   "vneg%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
3061
3062
  /* Vector VORN, vector bitwise or not.  */
3063
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3064
   MVE_VORN,
3065
   0xef300150, 0xffb11f51,
3066
   "vorn%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3067
3068
  /* Vector VORR register.  */
3069
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3070
   MVE_VORR_REG,
3071
   0xef200150, 0xffb11f51,
3072
   "vorr%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3073
3074
  /* Vector VMOV, vector to vector move. While decoding MVE_VORR_REG if
3075
     "Qm==Qn", VORR should replaced by its alias VMOV. For that to happen
3076
     MVE_VMOV_VEC_TO_VEC need to placed after MVE_VORR_REG in this mve_opcodes
3077
     array.  */
3078
3079
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3080
   MVE_VMOV_VEC_TO_VEC,
3081
   0xef200150, 0xffb11f51,
3082
   "vmov%v\t%13-15,22Q, %17-19,7Q"},
3083
3084
  /* Vector VQDMULL T1 variant.  */
3085
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3086
   MVE_VQDMULL_T1,
3087
   0xee300f01, 0xefb10f51,
3088
   "vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3089
3090
  /* Vector VPNOT.  */
3091
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3092
   MVE_VPNOT,
3093
   0xfe310f4d, 0xffffffff,
3094
   "vpnot%v"},
3095
3096
  /* Vector VPSEL.  */
3097
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3098
   MVE_VPSEL,
3099
   0xfe310f01, 0xffb11f51,
3100
   "vpsel%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3101
3102
  /* Vector VQABS.  */
3103
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3104
   MVE_VQABS,
3105
   0xffb00740, 0xffb31fd1,
3106
   "vqabs%v.s%18-19s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3107
3108
  /* Vector VQADD T1 variant.  */
3109
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3110
   MVE_VQADD_T1,
3111
   0xef000050, 0xef811f51,
3112
   "vqadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3113
3114
  /* Vector VQADD T2 variant.  */
3115
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3116
   MVE_VQADD_T2,
3117
   0xee000f60, 0xef811f70,
3118
   "vqadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3119
3120
  /* Vector VQDMULL T2 variant.  */
3121
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3122
   MVE_VQDMULL_T2,
3123
   0xee300f60, 0xefb10f70,
3124
   "vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3125
3126
  /* Vector VQMOVN.  */
3127
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3128
   MVE_VQMOVN,
3129
   0xee330e01, 0xefb30fd1,
3130
   "vqmovn%T%v.%u%18-19s\t%13-15,22Q, %1-3,5Q"},
3131
3132
  /* Vector VQMOVUN.  */
3133
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3134
   MVE_VQMOVUN,
3135
   0xee310e81, 0xffb30fd1,
3136
   "vqmovun%T%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
3137
3138
  /* Vector VQDMLADH.  */
3139
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3140
   MVE_VQDMLADH,
3141
   0xee000e00, 0xff810f51,
3142
   "vqdmladh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3143
3144
  /* Vector VQRDMLADH.  */
3145
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3146
   MVE_VQRDMLADH,
3147
   0xee000e01, 0xff810f51,
3148
   "vqrdmladh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3149
3150
  /* Vector VQDMLAH.  */
3151
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3152
   MVE_VQDMLAH,
3153
   0xee000e60, 0xff811f70,
3154
   "vqdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3155
3156
  /* Vector VQRDMLAH.  */
3157
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3158
   MVE_VQRDMLAH,
3159
   0xee000e40, 0xff811f70,
3160
   "vqrdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3161
3162
  /* Vector VQDMLASH.  */
3163
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3164
   MVE_VQDMLASH,
3165
   0xee001e60, 0xff811f70,
3166
   "vqdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3167
3168
  /* Vector VQRDMLASH.  */
3169
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3170
   MVE_VQRDMLASH,
3171
   0xee001e40, 0xff811f70,
3172
   "vqrdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3173
3174
  /* Vector VQDMLSDH.  */
3175
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3176
   MVE_VQDMLSDH,
3177
   0xfe000e00, 0xff810f51,
3178
   "vqdmlsdh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3179
3180
  /* Vector VQRDMLSDH.  */
3181
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3182
   MVE_VQRDMLSDH,
3183
   0xfe000e01, 0xff810f51,
3184
   "vqrdmlsdh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3185
3186
  /* Vector VQDMULH T1 variant.  */
3187
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3188
   MVE_VQDMULH_T1,
3189
   0xef000b40, 0xff811f51,
3190
   "vqdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3191
3192
  /* Vector VQRDMULH T2 variant.  */
3193
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3194
   MVE_VQRDMULH_T2,
3195
   0xff000b40, 0xff811f51,
3196
   "vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3197
3198
  /* Vector VQDMULH T3 variant.  */
3199
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3200
   MVE_VQDMULH_T3,
3201
   0xee010e60, 0xff811f70,
3202
   "vqdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3203
3204
  /* Vector VQRDMULH T4 variant.  */
3205
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3206
   MVE_VQRDMULH_T4,
3207
   0xfe010e60, 0xff811f70,
3208
   "vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3209
3210
  /* Vector VQNEG.  */
3211
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3212
   MVE_VQNEG,
3213
   0xffb007c0, 0xffb31fd1,
3214
   "vqneg%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
3215
3216
  /* Vector VQRSHL T1 variant.  */
3217
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3218
   MVE_VQRSHL_T1,
3219
   0xef000550, 0xef811f51,
3220
   "vqrshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3221
3222
  /* Vector VQRSHL T2 variant.  */
3223
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3224
   MVE_VQRSHL_T2,
3225
   0xee331ee0, 0xefb31ff0,
3226
   "vqrshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3227
3228
  /* Vector VQRSHRN.  */
3229
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3230
   MVE_VQRSHRN,
3231
   0xee800f41, 0xefa00fd1,
3232
   "vqrshrn%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
3233
3234
  /* Vector VQRSHRUN.  */
3235
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3236
   MVE_VQRSHRUN,
3237
   0xfe800fc0, 0xffa00fd1,
3238
   "vqrshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
3239
3240
  /* Vector VQSHL T1 Variant.  */
3241
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3242
   MVE_VQSHL_T1,
3243
   0xee311ee0, 0xefb31ff0,
3244
   "vqshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3245
3246
  /* Vector VQSHL T4 Variant.  */
3247
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3248
   MVE_VQSHL_T4,
3249
   0xef000450, 0xef811f51,
3250
   "vqshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3251
3252
  /* Vector VQSHRN.  */
3253
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3254
   MVE_VQSHRN,
3255
   0xee800f40, 0xefa00fd1,
3256
   "vqshrn%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
3257
3258
  /* Vector VQSHRUN.  */
3259
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3260
   MVE_VQSHRUN,
3261
   0xee800fc0, 0xffa00fd1,
3262
   "vqshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
3263
3264
  /* Vector VQSUB T1 Variant.  */
3265
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3266
   MVE_VQSUB_T1,
3267
   0xef000250, 0xef811f51,
3268
   "vqsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3269
3270
  /* Vector VQSUB T2 Variant.  */
3271
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3272
   MVE_VQSUB_T2,
3273
   0xee001f60, 0xef811f70,
3274
   "vqsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3275
3276
  /* Vector VREV16.  */
3277
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3278
   MVE_VREV16,
3279
   0xffb00140, 0xffb31fd1,
3280
   "vrev16%v.8\t%13-15,22Q, %1-3,5Q"},
3281
3282
  /* Vector VREV32.  */
3283
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3284
   MVE_VREV32,
3285
   0xffb000c0, 0xffb31fd1,
3286
   "vrev32%v.%18-19s\t%13-15,22Q, %1-3,5Q"},
3287
3288
  /* Vector VREV64.  */
3289
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3290
   MVE_VREV64,
3291
   0xffb00040, 0xffb31fd1,
3292
   "vrev64%v.%18-19s\t%13-15,22Q, %1-3,5Q"},
3293
3294
  /* Vector VRINT floating point.  */
3295
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
3296
   MVE_VRINT_FP,
3297
   0xffb20440, 0xffb31c51,
3298
   "vrint%m%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
3299
3300
  /* Vector VRMLALDAVH.  */
3301
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3302
   MVE_VRMLALDAVH,
3303
   0xee800f00, 0xef811f51,
3304
   "vrmlalvh%5A%v.%u32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
3305
3306
  /* Vector VRMLALDAVH.  */
3307
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3308
   MVE_VRMLALDAVH,
3309
   0xee801f00, 0xef811f51,
3310
   "vrmlaldavh%5Ax%v.%u32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
3311
3312
  /* Vector VRSHL T1 Variant.  */
3313
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3314
   MVE_VRSHL_T1,
3315
   0xef000540, 0xef811f51,
3316
   "vrshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3317
3318
  /* Vector VRSHL T2 Variant.  */
3319
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3320
   MVE_VRSHL_T2,
3321
   0xee331e60, 0xefb31ff0,
3322
   "vrshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3323
3324
  /* Vector VRSHRN.  */
3325
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3326
   MVE_VRSHRN,
3327
   0xfe800fc1, 0xffa00fd1,
3328
   "vrshrn%T%v.i%19-20s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
3329
3330
  /* Vector VSBC.  */
3331
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3332
   MVE_VSBC,
3333
   0xfe300f00, 0xffb10f51,
3334
   "vsbc%12I%v.i32\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3335
3336
  /* Vector VSHL T2 Variant.  */
3337
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3338
   MVE_VSHL_T2,
3339
   0xee311e60, 0xefb31ff0,
3340
   "vshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3341
3342
  /* Vector VSHL T3 Variant.  */
3343
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3344
   MVE_VSHL_T3,
3345
   0xef000440, 0xef811f51,
3346
   "vshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3347
3348
  /* Vector VSHLC.  */
3349
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3350
   MVE_VSHLC,
3351
   0xeea00fc0, 0xffa01ff0,
3352
   "vshlc%v\t%13-15,22Q, %0-3r, %{I:#%16-20d%}"},
3353
3354
  /* Vector VSHLL T2 Variant.  */
3355
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3356
   MVE_VSHLL_T2,
3357
   0xee310e01, 0xefb30fd1,
3358
   "vshll%T%v.%u%18-19s\t%13-15,22Q, %1-3,5Q, %{I:#%18-19d%}"},
3359
3360
  /* Vector VSHRN.  */
3361
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3362
   MVE_VSHRN,
3363
   0xee800fc1, 0xffa00fd1,
3364
   "vshrn%T%v.i%19-20s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
3365
3366
  /* Vector VST2 no writeback.  */
3367
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3368
   MVE_VST2,
3369
   0xfc801e00, 0xffb01e5f,
3370
   "vst2%5d.%7-8s\t%B, [%16-19r]"},
3371
3372
  /* Vector VST2 writeback.  */
3373
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3374
   MVE_VST2,
3375
   0xfca01e00, 0xffb01e5f,
3376
   "vst2%5d.%7-8s\t%B, [%16-19r]!"},
3377
3378
  /* Vector VST4 no writeback.  */
3379
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3380
   MVE_VST4,
3381
   0xfc801e01, 0xffb01e1f,
3382
   "vst4%5-6d.%7-8s\t%B, [%16-19r]"},
3383
3384
  /* Vector VST4 writeback.  */
3385
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3386
   MVE_VST4,
3387
   0xfca01e01, 0xffb01e1f,
3388
   "vst4%5-6d.%7-8s\t%B, [%16-19r]!"},
3389
3390
  /* Vector VSTRB scatter store, T1 variant.  */
3391
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3392
   MVE_VSTRB_SCATTER_T1,
3393
   0xec800e00, 0xffb01e50,
3394
   "vstrb%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"},
3395
3396
  /* Vector VSTRH scatter store, T2 variant.  */
3397
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3398
   MVE_VSTRH_SCATTER_T2,
3399
   0xec800e10, 0xffb01e50,
3400
   "vstrh%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
3401
3402
  /* Vector VSTRW scatter store, T3 variant.  */
3403
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3404
   MVE_VSTRW_SCATTER_T3,
3405
   0xec800e40, 0xffb01e50,
3406
   "vstrw%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
3407
3408
  /* Vector VSTRD scatter store, T4 variant.  */
3409
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3410
   MVE_VSTRD_SCATTER_T4,
3411
   0xec800fd0, 0xffb01fd0,
3412
   "vstrd%v.64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
3413
3414
  /* Vector VSTRW scatter store, T5 variant.  */
3415
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3416
   MVE_VSTRW_SCATTER_T5,
3417
   0xfd001e00, 0xff111f00,
3418
   "vstrw%v.32\t%13-15,22Q, [%17-19,7Q, %{I:#%a%0-6i%}]%w"},
3419
3420
  /* Vector VSTRD scatter store, T6 variant.  */
3421
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3422
   MVE_VSTRD_SCATTER_T6,
3423
   0xfd001f00, 0xff111f00,
3424
   "vstrd%v.64\t%13-15,22Q, [%17-19,7Q, %{I:#%a%0-6i%}]%w"},
3425
3426
  /* Vector VSTRB.  */
3427
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3428
   MVE_VSTRB_T1,
3429
   0xec000e00, 0xfe581e00,
3430
   "vstrb%v.%7-8s\t%13-15Q, %d"},
3431
3432
  /* Vector VSTRH.  */
3433
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3434
   MVE_VSTRH_T2,
3435
   0xec080e00, 0xfe581e00,
3436
   "vstrh%v.%7-8s\t%13-15Q, %d"},
3437
3438
  /* Vector VSTRB variant T5.  */
3439
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3440
   MVE_VSTRB_T5,
3441
   0xec001e00, 0xfe101f80,
3442
   "vstrb%v.8\t%13-15,22Q, %d"},
3443
3444
  /* Vector VSTRH variant T6.  */
3445
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3446
   MVE_VSTRH_T6,
3447
   0xec001e80, 0xfe101f80,
3448
   "vstrh%v.16\t%13-15,22Q, %d"},
3449
3450
  /* Vector VSTRW variant T7.  */
3451
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3452
   MVE_VSTRW_T7,
3453
   0xec001f00, 0xfe101f80,
3454
   "vstrw%v.32\t%13-15,22Q, %d"},
3455
3456
  /* Vector VSUB floating point T1 variant.  */
3457
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
3458
   MVE_VSUB_FP_T1,
3459
   0xef200d40, 0xffa11f51,
3460
   "vsub%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3461
3462
  /* Vector VSUB floating point T2 variant.  */
3463
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
3464
   MVE_VSUB_FP_T2,
3465
   0xee301f40, 0xefb11f70,
3466
   "vsub%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3467
3468
  /* Vector VSUB T1 variant.  */
3469
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3470
   MVE_VSUB_VEC_T1,
3471
   0xff000840, 0xff811f51,
3472
   "vsub%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3473
3474
  /* Vector VSUB T2 variant.  */
3475
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3476
   MVE_VSUB_VEC_T2,
3477
   0xee011f40, 0xff811f70,
3478
   "vsub%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3479
3480
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3481
   MVE_ASRLI,
3482
   0xea50012f, 0xfff1813f,
3483
   "asrl%c\t%17-19l, %9-11h, %j"},
3484
3485
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3486
   MVE_ASRL,
3487
   0xea50012d, 0xfff101ff,
3488
   "asrl%c\t%17-19l, %9-11h, %12-15S"},
3489
3490
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3491
   MVE_LSLLI,
3492
   0xea50010f, 0xfff1813f,
3493
   "lsll%c\t%17-19l, %9-11h, %j"},
3494
3495
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3496
   MVE_LSLL,
3497
   0xea50010d, 0xfff101ff,
3498
   "lsll%c\t%17-19l, %9-11h, %12-15S"},
3499
3500
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3501
   MVE_LSRL,
3502
   0xea50011f, 0xfff1813f,
3503
   "lsrl%c\t%17-19l, %9-11h, %j"},
3504
3505
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3506
   MVE_SQRSHRL,
3507
   0xea51012d, 0xfff1017f,
3508
   "sqrshrl%c\t%17-19l, %9-11h, %k, %12-15S"},
3509
3510
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3511
   MVE_SQRSHR,
3512
   0xea500f2d, 0xfff00fff,
3513
   "sqrshr%c\t%16-19S, %12-15S"},
3514
3515
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3516
   MVE_SQSHLL,
3517
   0xea51013f, 0xfff1813f,
3518
   "sqshll%c\t%17-19l, %9-11h, %j"},
3519
3520
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3521
   MVE_SQSHL,
3522
   0xea500f3f, 0xfff08f3f,
3523
   "sqshl%c\t%16-19S, %j"},
3524
3525
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3526
   MVE_SRSHRL,
3527
   0xea51012f, 0xfff1813f,
3528
   "srshrl%c\t%17-19l, %9-11h, %j"},
3529
3530
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3531
   MVE_SRSHR,
3532
   0xea500f2f, 0xfff08f3f,
3533
   "srshr%c\t%16-19S, %j"},
3534
3535
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3536
   MVE_UQRSHLL,
3537
   0xea51010d, 0xfff1017f,
3538
   "uqrshll%c\t%17-19l, %9-11h, %k, %12-15S"},
3539
3540
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3541
   MVE_UQRSHL,
3542
   0xea500f0d, 0xfff00fff,
3543
   "uqrshl%c\t%16-19S, %12-15S"},
3544
3545
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3546
   MVE_UQSHLL,
3547
    0xea51010f, 0xfff1813f,
3548
   "uqshll%c\t%17-19l, %9-11h, %j"},
3549
3550
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3551
   MVE_UQSHL,
3552
   0xea500f0f, 0xfff08f3f,
3553
   "uqshl%c\t%16-19S, %j"},
3554
3555
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3556
   MVE_URSHRL,
3557
    0xea51011f, 0xfff1813f,
3558
   "urshrl%c\t%17-19l, %9-11h, %j"},
3559
3560
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3561
   MVE_URSHR,
3562
   0xea500f1f, 0xfff08f3f,
3563
   "urshr%c\t%16-19S, %j"},
3564
3565
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3566
   MVE_CSINC,
3567
   0xea509000, 0xfff0f000,
3568
   "csinc\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3569
3570
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3571
   MVE_CSINV,
3572
   0xea50a000, 0xfff0f000,
3573
   "csinv\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3574
3575
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3576
   MVE_CSET,
3577
   0xea5f900f, 0xfffff00f,
3578
   "cset\t%8-11S, %4-7C"},
3579
3580
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3581
   MVE_CSETM,
3582
   0xea5fa00f, 0xfffff00f,
3583
   "csetm\t%8-11S, %4-7C"},
3584
3585
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3586
   MVE_CSEL,
3587
   0xea508000, 0xfff0f000,
3588
   "csel\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3589
3590
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3591
   MVE_CSNEG,
3592
   0xea50b000, 0xfff0f000,
3593
   "csneg\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3594
3595
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3596
   MVE_CINC,
3597
   0xea509000, 0xfff0f000,
3598
   "cinc\t%8-11S, %16-19Z, %4-7C"},
3599
3600
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3601
   MVE_CINV,
3602
   0xea50a000, 0xfff0f000,
3603
   "cinv\t%8-11S, %16-19Z, %4-7C"},
3604
3605
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3606
   MVE_CNEG,
3607
   0xea50b000, 0xfff0f000,
3608
   "cneg\t%8-11S, %16-19Z, %4-7C"},
3609
3610
  {ARM_FEATURE_CORE_LOW (0),
3611
   MVE_NONE,
3612
   0x00000000, 0x00000000, 0}
3613
};
3614
3615
/* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb.  All three are partially
3616
   ordered: they must be searched linearly from the top to obtain a correct
3617
   match.  */
3618
3619
/* print_insn_arm recognizes the following format control codes:
3620
3621
   %%     %
3622
3623
   %a     print address for ldr/str instruction
3624
   %s                   print address for ldr/str halfword/signextend instruction
3625
   %S                   like %s but allow UNPREDICTABLE addressing
3626
   %b     print branch destination
3627
   %c     print condition code (always bits 28-31)
3628
   %m     print register mask for ldm/stm instruction
3629
   %o     print operand2 (immediate or register + shift)
3630
   %p     print 'p' iff bits 12-15 are 15
3631
   %t     print 't' iff bit 21 set and bit 24 clear
3632
   %B     print arm BLX(1) destination
3633
   %C     print the PSR sub type.
3634
   %U     print barrier type.
3635
   %P     print address for pli instruction.
3636
3637
   %<bitfield>r   print as an ARM register
3638
   %<bitfield>T   print as an ARM register + 1
3639
   %<bitfield>R   as %r but r15 is UNPREDICTABLE
3640
   %<bitfield>{r|R}u    as %{r|R} but if matches the other %u field then is UNPREDICTABLE
3641
   %<bitfield>{r|R}U    as %{r|R} but if matches the other %U field then is UNPREDICTABLE
3642
   %<bitfield>d   print the bitfield in decimal
3643
   %<bitfield>W         print the bitfield plus one in decimal
3644
   %<bitfield>x   print the bitfield in hex
3645
   %<bitfield>X   print the bitfield as 1 hex digit without leading "0x"
3646
3647
   %<bitfield>'c  print specified char iff bitfield is all ones
3648
   %<bitfield>`c  print specified char iff bitfield is all zeroes
3649
   %<bitfield>?ab...    select from array of values in big endian order
3650
3651
   %e                   print arm SMI operand (bits 0..7,8..19).
3652
   %E     print the LSB and WIDTH fields of a BFI or BFC instruction.
3653
   %V                   print the 16-bit immediate field of a MOVT or MOVW instruction.
3654
   %R     print the SPSR/CPSR or banked register of an MRS.  */
3655
3656
static const struct opcode32 arm_opcodes[] =
3657
{
3658
  /* ARM instructions.  */
3659
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3660
    0xe1a00000, 0xffffffff, "nop\t\t\t@ (mov r0, r0)"},
3661
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3662
    0xe7f000f0, 0xfff000f0, "udf\t%{I:#%e%}"},
3663
3664
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T | ARM_EXT_V5),
3665
    0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
3666
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
3667
    0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"},
3668
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
3669
    0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3670
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V2S),
3671
    0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"},
3672
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
3673
    0x00800090, 0x0fa000f0,
3674
    "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3675
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
3676
    0x00a00090, 0x0fa000f0,
3677
    "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3678
3679
  /* V8.2 RAS extension instructions.  */
3680
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
3681
    0xe320f010, 0xffffffff, "esb"},
3682
3683
  /* V8-R instructions.  */
3684
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8R),
3685
    0xf57ff04c, 0xffffffff, "dfb"},
3686
3687
  /* V8 instructions.  */
3688
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3689
    0x0320f005, 0x0fffffff, "sevl"},
3690
  /* Defined in V8 but is in NOP space so available to all arch.  */
3691
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3692
    0xe1000070, 0xfff000f0, "hlt\t%{I:0x%16-19X%12-15X%8-11X%0-3X%}"},
3693
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS),
3694
    0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"},
3695
  {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3696
    0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
3697
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3698
    0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"},
3699
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3700
    0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"},
3701
  {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3702
    0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"},
3703
  {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3704
    0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
3705
  {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3706
    0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"},
3707
  {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3708
    0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
3709
  {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3710
    0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"},
3711
  {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3712
    0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"},
3713
  {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3714
    0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"},
3715
  {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3716
    0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"},
3717
  {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3718
    0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"},
3719
  {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3720
    0x01f00c9f, 0x0ff00fff, "ldah%c\t%12-15r, [%16-19R]"},
3721
  /* CRC32 instructions.  */
3722
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
3723
    0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"},
3724
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
3725
    0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"},
3726
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
3727
    0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"},
3728
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
3729
    0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"},
3730
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
3731
    0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"},
3732
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
3733
    0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"},
3734
3735
  /* Privileged Access Never extension instructions.  */
3736
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),
3737
    0xf1100000, 0xfffffdff, "setpan\t%{I:#%9-9d%}"},
3738
3739
  /* Virtualization Extension instructions.  */
3740
  {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x0160006e, 0x0fffffff, "eret%c"},
3741
  {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x01400070, 0x0ff000f0, "hvc%c\t%e"},
3742
3743
  /* Integer Divide Extension instructions.  */
3744
  {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
3745
    0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"},
3746
  {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
3747
    0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"},
3748
3749
  /* MP Extension instructions.  */
3750
  {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf410f000, 0xfc70f000, "pldw\t%a"},
3751
3752
  /* Speculation Barriers.  */
3753
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xe320f014, 0xffffffff, "csdb"},
3754
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff040, 0xffffffff, "ssbb"},
3755
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff044, 0xffffffff, "pssbb"},
3756
3757
  /* V7 instructions.  */
3758
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf450f000, 0xfd70f000, "pli\t%P"},
3759
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0x0320f0f0, 0x0ffffff0, "dbg%c\t%{I:#%0-3d%}"},
3760
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff051, 0xfffffff3, "dmb\t%U"},
3761
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff041, 0xfffffff3, "dsb\t%U"},
3762
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff050, 0xfffffff0, "dmb\t%U"},
3763
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff040, 0xfffffff0, "dsb\t%U"},
3764
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff060, 0xfffffff0, "isb\t%U"},
3765
   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
3766
    0x0320f000, 0x0fffffff, "nop%c\t{%{I:%0-7d%}}"},
3767
3768
  /* ARM V6T2 instructions.  */
3769
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3770
    0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"},
3771
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3772
    0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"},
3773
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3774
    0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3775
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3776
    0x002000b0, 0x0f3000f0, "strht%c\t%12-15R, %S"},
3777
3778
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3779
    0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION },
3780
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3781
    0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"},
3782
3783
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3784
    0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"},
3785
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3786
    0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"},
3787
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3788
    0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"},
3789
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3790
    0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, %{I:#%7-11d%}, %{I:#%16-20W%}"},
3791
3792
  /* ARM Security extension instructions.  */
3793
  {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
3794
    0x01600070, 0x0ff000f0, "smc%c\t%e"},
3795
3796
  /* ARM V6K instructions.  */
3797
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3798
    0xf57ff01f, 0xffffffff, "clrex"},
3799
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3800
    0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"},
3801
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3802
    0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"},
3803
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3804
    0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"},
3805
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3806
    0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"},
3807
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3808
    0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"},
3809
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3810
    0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"},
3811
3812
  /* ARMv8.5-A instructions.  */
3813
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf57ff070, 0xffffffff, "sb"},
3814
3815
  /* ARM V6K NOP hints.  */
3816
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3817
    0x0320f001, 0x0fffffff, "yield%c"},
3818
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3819
    0x0320f002, 0x0fffffff, "wfe%c"},
3820
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3821
    0x0320f003, 0x0fffffff, "wfi%c"},
3822
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3823
    0x0320f004, 0x0fffffff, "sev%c"},
3824
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3825
    0x0320f000, 0x0fffff00, "nop%c\t{%{I:%0-7d%}}"},
3826
3827
  /* ARM V6 instructions.  */
3828
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3829
    0xf1080000, 0xfffffe3f, "cpsie\t%{B:%8'a%7'i%6'f%}"},
3830
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3831
    0xf10a0000, 0xfffffe20, "cpsie\t%{B:%8'a%7'i%6'f%}, %{I:#%0-4d%}"},
3832
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3833
    0xf10C0000, 0xfffffe3f, "cpsid\t%{B:%8'a%7'i%6'f%}"},
3834
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3835
    0xf10e0000, 0xfffffe20, "cpsid\t%{B:%8'a%7'i%6'f%}, %{I:#%0-4d%}"},
3836
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3837
    0xf1000000, 0xfff1fe20, "cps\t%{I:#%0-4d%}"},
3838
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3839
    0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"},
3840
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3841
    0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, %{B:lsl%} %{I:#%7-11d%}"},
3842
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3843
    0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, %{B:asr%} %{I:#32%}"},
3844
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3845
    0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, %{B:asr%} %{I:#%7-11d%}"},
3846
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3847
    0x01900f9f, 0x0ff00fff, "ldrex%c\t%{R:r%12-15d%}, [%16-19R]"},
3848
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3849
    0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"},
3850
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3851
    0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"},
3852
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3853
    0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"},
3854
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3855
    0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"},
3856
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3857
    0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"},
3858
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3859
    0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"},
3860
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3861
    0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"},
3862
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3863
    0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"},
3864
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3865
    0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"},
3866
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3867
    0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"},
3868
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3869
    0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"},
3870
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3871
    0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"},
3872
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3873
    0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"},
3874
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3875
    0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"},
3876
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3877
    0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"},
3878
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3879
    0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"},
3880
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3881
    0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"},
3882
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3883
    0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"},
3884
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3885
    0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"},
3886
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3887
    0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"},
3888
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3889
    0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"},
3890
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3891
    0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"},
3892
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3893
    0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"},
3894
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3895
    0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"},
3896
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3897
    0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"},
3898
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3899
    0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"},
3900
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3901
    0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"},
3902
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3903
    0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"},
3904
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3905
    0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"},
3906
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3907
    0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"},
3908
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3909
    0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"},
3910
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3911
    0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"},
3912
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3913
    0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"},
3914
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3915
    0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"},
3916
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3917
    0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"},
3918
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3919
    0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"},
3920
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3921
    0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"},
3922
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3923
    0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"},
3924
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3925
    0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"},
3926
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3927
    0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"},
3928
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3929
    0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"},
3930
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3931
    0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, %{B:ror%} %{I:#8%}"},
3932
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3933
    0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, %{B:ror%} %{I:#16%}"},
3934
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3935
    0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, %{B:ror%} %{I:#24%}"},
3936
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3937
    0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"},
3938
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3939
    0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, %{B:ror%} %{I:#8%}"},
3940
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3941
    0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, %{B:ror%} %{I:#16%}"},
3942
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3943
    0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, %{B:ror%} %{I:#24%}"},
3944
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3945
    0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"},
3946
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3947
    0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, %{B:ror%} %{I:#8%}"},
3948
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3949
    0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, %{B:ror%} %{I:#16%}"},
3950
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3951
    0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, %{B:ror%} %{I:#24%}"},
3952
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3953
    0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"},
3954
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3955
    0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, %{B:ror%} %{I:#8%}"},
3956
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3957
    0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, %{B:ror%} %{I:#16%}"},
3958
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3959
    0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, %{B:ror%} %{I:#24%}"},
3960
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3961
    0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"},
3962
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3963
    0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, %{B:ror%} %{I:#8%}"},
3964
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3965
    0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, %{B:ror%} %{I:#16%}"},
3966
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3967
    0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, %{B:ror%} %{I:#24%}"},
3968
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3969
    0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"},
3970
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3971
    0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, %{B:ror%} %{I:#8%}"},
3972
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3973
    0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, %{B:ror%} %{I:#16%}"},
3974
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3975
    0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, %{B:ror%} %{I:#24%}"},
3976
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3977
    0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"},
3978
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3979
    0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#8%}"},
3980
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3981
    0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#16%}"},
3982
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3983
    0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#24%}"},
3984
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3985
    0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"},
3986
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3987
    0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#8%}"},
3988
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3989
    0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#16%}"},
3990
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3991
    0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#24%}"},
3992
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3993
    0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"},
3994
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3995
    0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#8%}"},
3996
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3997
    0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#16%}"},
3998
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3999
    0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#24%}"},
4000
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4001
    0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"},
4002
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4003
    0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#8%}"},
4004
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4005
    0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#16%}"},
4006
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4007
    0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#24%}"},
4008
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4009
    0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"},
4010
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4011
    0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#8%}"},
4012
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4013
    0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#16%}"},
4014
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4015
    0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR %{I:#24%}"},
4016
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4017
    0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"},
4018
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4019
    0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#8%}"},
4020
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4021
    0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#16%}"},
4022
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4023
    0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#24%}"},
4024
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4025
    0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"},
4026
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4027
    0xf1010000, 0xfffffc00, "setend\t%{B:%9?ble%}"},
4028
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4029
    0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"},
4030
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4031
    0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"},
4032
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4033
    0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4034
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4035
    0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
4036
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4037
    0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4038
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4039
    0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
4040
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4041
    0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"},
4042
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4043
    0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4044
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4045
    0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4046
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4047
    0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, %{I:#%0-4d%}"},
4048
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4049
    0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, %{I:#%16-20W%}, %0-3R"},
4050
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4051
    0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, %{I:#%16-20W%}, %0-3R, %{B:lsl%} %{I:#%7-11d%}"},
4052
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4053
    0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, %{I:#%16-20W%}, %0-3R, %{B:asr%} %{I:#%7-11d%}"},
4054
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4055
    0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, %{I:#%16-19W%}, %0-3r"},
4056
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4057
    0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"},
4058
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4059
    0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"},
4060
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4061
    0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"},
4062
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4063
    0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4064
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4065
    0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, %{I:#%16-20d%}, %0-3R"},
4066
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4067
    0x06e00010, 0x0fe00070, "usat%c\t%12-15R, %{I:#%16-20d%}, %0-3R, %{B:lsl%} %{I:#%7-11d%}"},
4068
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4069
    0x06e00050, 0x0fe00070, "usat%c\t%12-15R, %{I:#%16-20d%}, %0-3R, %{B:asr%} %{I:#%7-11d%}"},
4070
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4071
    0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, %{I:#%16-19d%}, %0-3R"},
4072
4073
  /* V5J instruction.  */
4074
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5J),
4075
    0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"},
4076
4077
  /* V5 Instructions.  */
4078
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
4079
    0xe1200070, 0xfff000f0,
4080
    "bkpt\t%{I:0x%16-19X%12-15X%8-11X%0-3X%}"},
4081
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
4082
    0xfa000000, 0xfe000000, "blx\t%B"},
4083
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
4084
    0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"},
4085
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
4086
    0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"},
4087
4088
  /* V5E "El Segundo" Instructions.  */
4089
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
4090
    0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"},
4091
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
4092
    0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"},
4093
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
4094
    0xf450f000, 0xfc70f000, "pld\t%a"},
4095
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4096
    0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4097
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4098
    0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4099
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4100
    0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4101
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4102
    0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"},
4103
4104
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4105
    0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4106
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4107
    0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"},
4108
4109
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4110
    0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
4111
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4112
    0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
4113
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4114
    0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
4115
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4116
    0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
4117
4118
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4119
    0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"},
4120
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4121
    0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"},
4122
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4123
    0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"},
4124
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4125
    0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"},
4126
4127
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4128
    0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"},
4129
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4130
    0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"},
4131
4132
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4133
    0x01000050, 0x0ff00ff0,  "qadd%c\t%12-15R, %0-3R, %16-19R"},
4134
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4135
    0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"},
4136
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4137
    0x01200050, 0x0ff00ff0,  "qsub%c\t%12-15R, %0-3R, %16-19R"},
4138
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4139
    0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"},
4140
4141
  /* ARM Instructions.  */
4142
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4143
    0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t@ (str%c %12-15r, %a)"},
4144
4145
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4146
    0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"},
4147
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4148
    0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"},
4149
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4150
    0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"},
4151
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4152
    0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"},
4153
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4154
    0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"},
4155
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4156
    0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"},
4157
4158
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4159
    0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"},
4160
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4161
    0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"},
4162
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4163
    0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"},
4164
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4165
    0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"},
4166
4167
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4168
    0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION},
4169
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4170
    0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"},
4171
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4172
    0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION},
4173
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4174
    0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"},
4175
4176
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4177
    0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"},
4178
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4179
    0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"},
4180
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4181
    0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"},
4182
4183
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4184
    0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"},
4185
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4186
    0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"},
4187
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4188
    0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"},
4189
4190
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4191
    0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"},
4192
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4193
    0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"},
4194
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4195
    0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"},
4196
4197
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4198
    0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"},
4199
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4200
    0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"},
4201
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4202
    0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"},
4203
4204
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4205
    0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"},
4206
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4207
    0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"},
4208
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4209
    0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"},
4210
4211
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4212
    0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"},
4213
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4214
    0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"},
4215
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4216
    0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"},
4217
4218
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4219
    0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"},
4220
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4221
    0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"},
4222
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4223
    0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"},
4224
4225
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4226
    0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"},
4227
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4228
    0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"},
4229
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4230
    0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"},
4231
4232
  {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT),
4233
    0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"},
4234
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
4235
    0x0120f000, 0x0db0f000, "msr%c\t%C, %o"},
4236
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
4237
    0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"},
4238
4239
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4240
    0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"},
4241
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4242
    0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"},
4243
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4244
    0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"},
4245
4246
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4247
    0x03300000, 0x0ff00000, "teq%p%c\t%16-19r, %o"},
4248
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4249
    0x01300000, 0x0ff00010, "teq%p%c\t%16-19r, %o"},
4250
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4251
    0x01300010, 0x0ff00010, "teq%p%c\t%16-19R, %o"},
4252
4253
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4254
    0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"},
4255
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4256
    0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"},
4257
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4258
    0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"},
4259
4260
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4261
    0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"},
4262
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4263
    0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"},
4264
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4265
    0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"},
4266
4267
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4268
    0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"},
4269
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4270
    0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"},
4271
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4272
    0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"},
4273
4274
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4275
    0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"},
4276
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4277
    0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"},
4278
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4279
    0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"},
4280
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4281
    0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"},
4282
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4283
    0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"},
4284
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4285
    0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"},
4286
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4287
    0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"},
4288
4289
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4290
    0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"},
4291
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4292
    0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"},
4293
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4294
    0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"},
4295
4296
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4297
    0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"},
4298
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4299
    0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"},
4300
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4301
    0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"},
4302
4303
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4304
    0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION},
4305
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4306
    0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t@ (ldr%c %12-15r, %a)"},
4307
4308
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4309
    0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"},
4310
4311
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4312
    0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"},
4313
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4314
    0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"},
4315
4316
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4317
    0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4318
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4319
    0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4320
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4321
    0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4322
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4323
    0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4324
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4325
    0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4326
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4327
    0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4328
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4329
    0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4330
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4331
    0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4332
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4333
    0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4334
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4335
    0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4336
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4337
    0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4338
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4339
    0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4340
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4341
    0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4342
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4343
    0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4344
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4345
    0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4346
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4347
    0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4348
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4349
    0x092d0000, 0x0fff0000, "push%c\t%m"},
4350
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4351
    0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"},
4352
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4353
    0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
4354
4355
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4356
    0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4357
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4358
    0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4359
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4360
    0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4361
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4362
    0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4363
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4364
    0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4365
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4366
    0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4367
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4368
    0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4369
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4370
    0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4371
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4372
    0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4373
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4374
    0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4375
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4376
    0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4377
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4378
    0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4379
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4380
    0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4381
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4382
    0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4383
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4384
    0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4385
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4386
    0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4387
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4388
    0x08bd0000, 0x0fff0000, "pop%c\t%m"},
4389
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4390
    0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"},
4391
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4392
    0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
4393
4394
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4395
    0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
4396
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4397
    0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
4398
4399
  /* The rest.  */
4400
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
4401
    0x03200000, 0x0fff00ff, "nop%c\t{%{I:%0-7d%}}" UNPREDICTABLE_INSTRUCTION},
4402
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4403
    0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
4404
  {ARM_FEATURE_CORE_LOW (0),
4405
    0x00000000, 0x00000000, 0}
4406
};
4407
4408
/* print_insn_thumb16 recognizes the following format control codes:
4409
4410
   %S                   print Thumb register (bits 3..5 as high number if bit 6 set)
4411
   %D                   print Thumb register (bits 0..2 as high number if bit 7 set)
4412
   %<bitfield>I         print bitfield as a signed decimal
4413
          (top bit of range being the sign bit)
4414
   %N                   print Thumb register mask (with LR)
4415
   %O                   print Thumb register mask (with PC)
4416
   %M                   print Thumb register mask
4417
   %b     print CZB's 6-bit unsigned branch destination
4418
   %s     print Thumb right-shift immediate (6..10; 0 == 32).
4419
   %c     print the condition code
4420
   %C     print the condition code, or "s" if not conditional
4421
   %x     print warning if conditional an not at end of IT block"
4422
   %X     print "\t@ unpredictable <IT:code>" if conditional
4423
   %I     print IT instruction suffix and operands
4424
   %W     print Thumb Writeback indicator for LDMIA
4425
   %<bitfield>r   print bitfield as an ARM register
4426
   %<bitfield>d   print bitfield as a decimal
4427
   %<bitfield>H         print (bitfield * 2) as a decimal
4428
   %<bitfield>W         print (bitfield * 4) as a decimal
4429
   %<bitfield>a         print (bitfield * 4) as a pc-rel offset + decoded symbol
4430
   %<bitfield>B         print Thumb branch destination (signed displacement)
4431
   %<bitfield>c         print bitfield as a condition code
4432
   %<bitnum>'c    print specified char iff bit is one
4433
   %<bitnum>?ab   print a if bit is one else print b.  */
4434
4435
static const struct opcode16 thumb_opcodes[] =
4436
{
4437
  /* Thumb instructions.  */
4438
4439
  /* ARMv8-M Security Extensions instructions.  */
4440
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4784, 0xff87, "blxns\t%3-6r"},
4441
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4704, 0xff87, "bxns\t%3-6r"},
4442
4443
  /* ARM V8 instructions.  */
4444
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),  0xbf50, 0xffff, "sevl%c"},
4445
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),  0xba80, 0xffc0, "hlt\t%0-5x"},
4446
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),  0xb610, 0xfff7, "setpan\t%{I:#%3-3d%}"},
4447
4448
  /* ARM V6K no-argument instructions.  */
4449
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xffff, "nop%c"},
4450
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf10, 0xffff, "yield%c"},
4451
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf20, 0xffff, "wfe%c"},
4452
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf30, 0xffff, "wfi%c"},
4453
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf40, 0xffff, "sev%c"},
4454
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xff0f, "nop%c\t{%4-7d}"},
4455
4456
  /* ARM V6T2 instructions.  */
4457
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4458
    0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"},
4459
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4460
    0xb100, 0xfd00, "cbz\t%0-2r, %b%X"},
4461
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xbf00, 0xff00, "it%I%X"},
4462
4463
  /* ARM V6.  */
4464
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb660, 0xfff8, "cpsie\t%{B:%2'a%1'i%0'f%}%X"},
4465
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb670, 0xfff8, "cpsid\t%{B:%2'a%1'i%0'f%}%X"},
4466
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"},
4467
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"},
4468
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"},
4469
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"},
4470
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb650, 0xfff7, "setend\t%{B:%3?ble%}%X"},
4471
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"},
4472
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"},
4473
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"},
4474
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"},
4475
4476
  /* ARM V5 ISA extends Thumb.  */
4477
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
4478
    0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional.  */
4479
  /* This is BLX(2).  BLX(1) is a 32-bit instruction.  */
4480
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
4481
    0x4780, 0xff87, "blx%c\t%3-6r%x"},  /* note: 4 bit register number.  */
4482
  /* ARM V4T ISA (Thumb v1).  */
4483
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4484
    0x46C0, 0xFFFF, "nop%c\t\t\t@ (mov r8, r8)"},
4485
  /* Format 4.  */
4486
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
4487
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
4488
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"},
4489
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"},
4490
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"},
4491
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"},
4492
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"},
4493
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"},
4494
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"},
4495
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"},
4496
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"},
4497
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"},
4498
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"},
4499
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"},
4500
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"},
4501
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"},
4502
  /* format 13 */
4503
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB000, 0xFF80, "add%c\t%{R:sp%}, %{I:#%0-6W%}"},
4504
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB080, 0xFF80, "sub%c\t%{R:sp%}, %{I:#%0-6W%}"},
4505
  /* format 5 */
4506
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4700, 0xFF80, "bx%c\t%S%x"},
4507
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4400, 0xFF00, "add%c\t%D, %S"},
4508
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4500, 0xFF00, "cmp%c\t%D, %S"},
4509
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4600, 0xFF00, "mov%c\t%D, %S"},
4510
  /* format 14 */
4511
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB400, 0xFE00, "push%c\t%N"},
4512
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xBC00, 0xFE00, "pop%c\t%O"},
4513
  /* format 2 */
4514
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4515
    0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"},
4516
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4517
    0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"},
4518
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4519
    0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, %{I:#%6-8d%}"},
4520
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4521
    0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, %{I:#%6-8d%}"},
4522
  /* format 8 */
4523
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4524
    0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"},
4525
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4526
    0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"},
4527
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4528
    0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"},
4529
  /* format 7 */
4530
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4531
    0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
4532
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4533
    0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
4534
  /* format 1 */
4535
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"},
4536
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4537
    0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, %{I:#%6-10d%}"},
4538
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"},
4539
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"},
4540
  /* format 3 */
4541
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2000, 0xF800, "mov%C\t%8-10r, %{I:#%0-7d%}"},
4542
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2800, 0xF800, "cmp%c\t%8-10r, %{I:#%0-7d%}"},
4543
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3000, 0xF800, "add%C\t%8-10r, %{I:#%0-7d%}"},
4544
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3800, 0xF800, "sub%C\t%8-10r, %{I:#%0-7d%}"},
4545
  /* format 6 */
4546
  /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
4547
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4548
    0x4800, 0xF800,
4549
    "ldr%c\t%8-10r, [%{R:pc%}, %{I:#%0-7W%}]\t@ (%0-7a)"},
4550
  /* format 9 */
4551
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4552
    0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, %{I:#%6-10W%}]"},
4553
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4554
    0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, %{I:#%6-10W%}]"},
4555
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4556
    0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, %{I:#%6-10d%}]"},
4557
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4558
    0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, %{I:#%6-10d%}]"},
4559
  /* format 10 */
4560
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4561
    0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, %{I:#%6-10H%}]"},
4562
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4563
    0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, %{I:#%6-10H%}]"},
4564
  /* format 11 */
4565
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4566
    0x9000, 0xF800, "str%c\t%8-10r, [%{R:sp%}, %{I:#%0-7W%}]"},
4567
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4568
    0x9800, 0xF800, "ldr%c\t%8-10r, [%{R:sp%}, %{I:#%0-7W%}]"},
4569
  /* format 12 */
4570
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4571
    0xA000, 0xF800, "add%c\t%8-10r, %{R:pc%}, %{I:#%0-7W%}\t@ (adr %8-10r, %0-7a)"},
4572
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4573
    0xA800, 0xF800, "add%c\t%8-10r, %{R:sp%}, %{I:#%0-7W%}"},
4574
  /* format 15 */
4575
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
4576
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"},
4577
  /* format 17 */
4578
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDF00, 0xFF00, "svc%c\t%0-7d"},
4579
  /* format 16 */
4580
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFF00, "udf%c\t%{I:#%0-7d%}"},
4581
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION},
4582
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
4583
  /* format 18 */
4584
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xE000, 0xF800, "b%c.n\t%0-10B%x"},
4585
4586
  /* The E800 .. FFFF range is unconditionally redirected to the
4587
     32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
4588
     are processed via that table.  Thus, we can never encounter a
4589
     bare "second half of BL/BLX(1)" instruction here.  */
4590
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),  0x0000, 0x0000, UNDEFINED_INSTRUCTION},
4591
  {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
4592
};
4593
4594
/* Thumb32 opcodes use the same table structure as the ARM opcodes.
4595
   We adopt the convention that hw1 is the high 16 bits of .value and
4596
   .mask, hw2 the low 16 bits.
4597
4598
   print_insn_thumb32 recognizes the following format control codes:
4599
4600
       %%   %
4601
4602
       %I   print a 12-bit immediate from hw1[10],hw2[14:12,7:0]
4603
       %M   print a modified 12-bit immediate (same location)
4604
       %J   print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0]
4605
       %K   print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4]
4606
       %H   print a 16-bit immediate from hw2[3:0],hw1[11:0]
4607
       %S   print a possibly-shifted Rm
4608
4609
       %L   print address for a ldrd/strd instruction
4610
       %a   print the address of a plain load/store
4611
       %w   print the width and signedness of a core load/store
4612
       %m   print register mask for ldm/stm
4613
       %n   print register mask for clrm
4614
4615
       %E   print the lsb and width fields of a bfc/bfi instruction
4616
       %F   print the lsb and width fields of a sbfx/ubfx instruction
4617
       %G   print a fallback offset for Branch Future instructions
4618
       %W   print an offset for BF instruction
4619
       %Y   print an offset for BFL instruction
4620
       %Z   print an offset for BFCSEL instruction
4621
       %Q   print an offset for Low Overhead Loop instructions
4622
       %P   print an offset for Low Overhead Loop end instructions
4623
       %b   print a conditional branch offset
4624
       %B   print an unconditional branch offset
4625
       %s   print the shift field of an SSAT instruction
4626
       %R   print the rotation field of an SXT instruction
4627
       %U   print barrier type.
4628
       %P   print address for pli instruction.
4629
       %c   print the condition code
4630
       %x   print warning if conditional an not at end of IT block"
4631
       %X   print "\t@ unpredictable <IT:code>" if conditional
4632
4633
       %<bitfield>d print bitfield in decimal
4634
       %<bitfield>D     print bitfield plus one in decimal
4635
       %<bitfield>W print bitfield*4 in decimal
4636
       %<bitfield>r print bitfield as an ARM register
4637
       %<bitfield>R as %<>r but r15 is UNPREDICTABLE
4638
       %<bitfield>S as %<>r but r13 and r15 is UNPREDICTABLE
4639
       %<bitfield>c print bitfield as a condition code
4640
4641
       %<bitfield>'c  print specified char iff bitfield is all ones
4642
       %<bitfield>`c  print specified char iff bitfield is all zeroes
4643
       %<bitfield>?ab... select from array of values in big endian order
4644
4645
   With one exception at the bottom (done because BL and BLX(1) need
4646
   to come dead last), this table was machine-sorted first in
4647
   decreasing order of number of bits set in the mask, then in
4648
   increasing numeric order of mask, then in increasing numeric order
4649
   of opcode.  This order is not the clearest for a human reader, but
4650
   is guaranteed never to catch a special-case bit pattern with a more
4651
   general mask, which is important, because this instruction encoding
4652
   makes heavy use of special-case bit patterns.  */
4653
static const struct opcode32 thumb32_opcodes[] =
4654
{
4655
  /* Arm v8.1-M Mainline Pointer Authentication and Branch Target
4656
     Identification Extension.  */
4657
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4658
   0xf3af802d, 0xffffffff, "aut\t%{R:r12%}, %{R:lr%}, %{R:sp%}"},
4659
  {ARM_FEATURE_CORE_HIGH_HIGH (ARM_EXT3_PACBTI),
4660
   0xfb500f00, 0xfff00ff0, "autg%c\t%12-15r, %16-19r, %0-3r"},
4661
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4662
   0xf3af800f, 0xffffffff, "bti"},
4663
  {ARM_FEATURE_CORE_HIGH_HIGH (ARM_EXT3_PACBTI),
4664
   0xfb500f10, 0xfff00ff0, "bxaut%c\t%12-15r, %16-19r, %0-3r"},
4665
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4666
   0xf3af801d, 0xffffffff, "pac\t%{R:r12%}, %{R:lr%}, %{R:sp%}"},
4667
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4668
   0xf3af800d, 0xffffffff, "pacbti\t%{R:r12%}, %{R:lr%}, %{R:sp%}"},
4669
  {ARM_FEATURE_CORE_HIGH_HIGH (ARM_EXT3_PACBTI),
4670
   0xfb60f000, 0xfff0f0f0, "pacg%c\t%8-11r, %16-19r, %0-3r"},
4671
4672
  /* Armv8.1-M Mainline and Armv8.1-M Mainline Security Extensions
4673
     instructions.  */
4674
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4675
    0xf00fe001, 0xffffffff, "lctp%c"},
4676
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4677
    0xf02fc001, 0xfffff001, "le\t%P"},
4678
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4679
    0xf00fc001, 0xfffff001, "le\t%{R:lr%}, %P"},
4680
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4681
    0xf01fc001, 0xfffff001, "letp\t%{R:lr%}, %P"},
4682
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4683
    0xf040c001, 0xfff0f001, "wls\t%{R:lr%}, %16-19S, %Q"},
4684
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4685
    0xf000c001, 0xffc0f001, "wlstp.%20-21s\t%{R:lr%}, %16-19S, %Q"},
4686
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4687
    0xf040e001, 0xfff0ffff, "dls\t%{R:lr%}, %16-19S"},
4688
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4689
    0xf000e001, 0xffc0ffff, "dlstp.%20-21s\t%{R:lr%}, %16-19S"},
4690
4691
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4692
    0xf040e001, 0xf860f001, "bf%c\t%G, %W"},
4693
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4694
    0xf060e001, 0xf8f0f001, "bfx%c\t%G, %16-19S"},
4695
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4696
    0xf000c001, 0xf800f001, "bfl%c\t%G, %Y"},
4697
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4698
    0xf070e001, 0xf8f0f001, "bflx%c\t%G, %16-19S"},
4699
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4700
    0xf000e001, 0xf840f001, "bfcsel\t%G, %Z, %{B:%18-21c%}"},
4701
4702
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4703
    0xe89f0000, 0xffff2000, "clrm%c\t%n"},
4704
4705
  /* ARMv8-M and ARMv8-M Security Extensions instructions.  */
4706
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0xe97fe97f, 0xffffffff, "sg"},
4707
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4708
    0xe840f000, 0xfff0f0ff, "tt\t%8-11r, %16-19r"},
4709
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4710
    0xe840f040, 0xfff0f0ff, "ttt\t%8-11r, %16-19r"},
4711
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4712
    0xe840f080, 0xfff0f0ff, "tta\t%8-11r, %16-19r"},
4713
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4714
    0xe840f0c0, 0xfff0f0ff, "ttat\t%8-11r, %16-19r"},
4715
4716
  /* ARM V8.2 RAS extension instructions.  */
4717
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
4718
    0xf3af8010, 0xffffffff, "esb"},
4719
4720
  /* V8 instructions.  */
4721
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4722
    0xf3af8005, 0xffffffff, "sevl%c.w"},
4723
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4724
    0xf78f8000, 0xfffffffc, "dcps%0-1d"},
4725
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4726
    0xe8c00f8f, 0xfff00fff, "stlb%c\t%12-15r, [%16-19R]"},
4727
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4728
    0xe8c00f9f, 0xfff00fff, "stlh%c\t%12-15r, [%16-19R]"},
4729
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4730
    0xe8c00faf, 0xfff00fff, "stl%c\t%12-15r, [%16-19R]"},
4731
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4732
    0xe8c00fc0, 0xfff00ff0, "stlexb%c\t%0-3r, %12-15r, [%16-19R]"},
4733
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4734
    0xe8c00fd0, 0xfff00ff0, "stlexh%c\t%0-3r, %12-15r, [%16-19R]"},
4735
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4736
    0xe8c00fe0, 0xfff00ff0, "stlex%c\t%0-3r, %12-15r, [%16-19R]"},
4737
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4738
    0xe8c000f0, 0xfff000f0, "stlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"},
4739
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4740
    0xe8d00f8f, 0xfff00fff, "ldab%c\t%12-15r, [%16-19R]"},
4741
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4742
    0xe8d00f9f, 0xfff00fff, "ldah%c\t%12-15r, [%16-19R]"},
4743
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4744
    0xe8d00faf, 0xfff00fff, "lda%c\t%12-15r, [%16-19R]"},
4745
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4746
    0xe8d00fcf, 0xfff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
4747
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4748
    0xe8d00fdf, 0xfff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
4749
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4750
    0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
4751
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4752
    0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"},
4753
4754
  /* V8-R instructions.  */
4755
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8R),
4756
    0xf3bf8f4c, 0xffffffff, "dfb%c"},
4757
4758
  /* CRC32 instructions.  */
4759
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
4760
    0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11R, %16-19R, %0-3R"},
4761
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
4762
    0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11R, %16-19R, %0-3R"},
4763
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
4764
    0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11R, %16-19R, %0-3R"},
4765
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
4766
    0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11R, %16-19R, %0-3R"},
4767
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
4768
    0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11R, %16-19R, %0-3R"},
4769
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
4770
    0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11R, %16-19R, %0-3R"},
4771
4772
  /* Speculation Barriers.  */
4773
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8014, 0xffffffff, "csdb"},
4774
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f40, 0xffffffff, "ssbb"},
4775
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f44, 0xffffffff, "pssbb"},
4776
4777
  /* V7 instructions.  */
4778
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf910f000, 0xff70f000, "pli%c\t%a"},
4779
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3af80f0, 0xfffffff0, "dbg%c\t%{I:#%0-3d%}"},
4780
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"},
4781
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"},
4782
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"},
4783
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"},
4784
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"},
4785
  {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
4786
    0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"},
4787
  {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
4788
    0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"},
4789
4790
  /* Virtualization Extension instructions.  */
4791
  {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0xf7e08000, 0xfff0f000, "hvc%c\t%V"},
4792
  /* We skip ERET as that is SUBS pc, lr, #0.  */
4793
4794
  /* MP Extension instructions.  */
4795
  {ARM_FEATURE_CORE_LOW (ARM_EXT_MP),   0xf830f000, 0xff70f000, "pldw%c\t%a"},
4796
4797
  /* Security extension instructions.  */
4798
  {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),  0xf7f08000, 0xfff0f000, "smc%c\t%K"},
4799
4800
  /* ARMv8.5-A instructions.  */
4801
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf3bf8f70, 0xffffffff, "sb"},
4802
4803
  /* Instructions defined in the basic V6T2 set.  */
4804
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8000, 0xffffffff, "nop%c.w"},
4805
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8001, 0xffffffff, "yield%c.w"},
4806
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8002, 0xffffffff, "wfe%c.w"},
4807
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8003, 0xffffffff, "wfi%c.w"},
4808
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8004, 0xffffffff, "sev%c.w"},
4809
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4810
    0xf3af8000, 0xffffff00, "nop%c.w\t{%{I:%0-7d%}}"},
4811
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf7f0a000, 0xfff0f000, "udf%c.w\t%H"},
4812
4813
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4814
    0xf3bf8f2f, 0xffffffff, "clrex%c"},
4815
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4816
    0xf3af8400, 0xffffff1f, "cpsie.w\t%{B:%7'a%6'i%5'f%}%X"},
4817
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4818
    0xf3af8600, 0xffffff1f, "cpsid.w\t%{B:%7'a%6'i%5'f%}%X"},
4819
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4820
    0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"},
4821
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4822
    0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"},
4823
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4824
    0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"},
4825
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4826
    0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"},
4827
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4828
    0xf3af8100, 0xffffffe0, "cps\t%{I:#%0-4d%}%X"},
4829
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4830
    0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"},
4831
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4832
    0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, %{B:lsl%} %{I:#1%}]%x"},
4833
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4834
    0xf3af8500, 0xffffff00, "cpsie\t%{B:%7'a%6'i%5'f%}, %{I:#%0-4d%}%X"},
4835
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4836
    0xf3af8700, 0xffffff00, "cpsid\t%{B:%7'a%6'i%5'f%}, %{I:#%0-4d%}%X"},
4837
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4838
    0xf3de8f00, 0xffffff00, "subs%c\t%{R:pc%}, %{R:lr%}, %{I:#%0-7d%}"},
4839
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4840
    0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"},
4841
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4842
    0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"},
4843
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4844
    0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"},
4845
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4846
    0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, %{I:#%0-4d%}"},
4847
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4848
    0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, %{I:#%0-4d%}"},
4849
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4850
    0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"},
4851
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4852
    0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"},
4853
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4854
    0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"},
4855
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4856
    0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"},
4857
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4858
    0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"},
4859
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4860
    0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"},
4861
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4862
    0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"},
4863
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4864
    0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"},
4865
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4866
    0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"},
4867
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4868
    0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"},
4869
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4870
    0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"},
4871
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4872
    0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"},
4873
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4874
    0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"},
4875
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4876
    0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"},
4877
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4878
    0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"},
4879
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4880
    0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"},
4881
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4882
    0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"},
4883
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4884
    0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"},
4885
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4886
    0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"},
4887
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4888
    0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"},
4889
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4890
    0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"},
4891
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4892
    0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"},
4893
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4894
    0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"},
4895
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4896
    0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"},
4897
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4898
    0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"},
4899
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4900
    0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"},
4901
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4902
    0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"},
4903
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4904
    0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"},
4905
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4906
    0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"},
4907
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4908
    0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"},
4909
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4910
    0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"},
4911
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4912
    0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"},
4913
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4914
    0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"},
4915
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4916
    0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"},
4917
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4918
    0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"},
4919
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4920
    0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"},
4921
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4922
    0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"},
4923
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4924
    0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"},
4925
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4926
    0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"},
4927
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4928
    0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"},
4929
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4930
    0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"},
4931
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4932
    0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"},
4933
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4934
    0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"},
4935
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4936
    0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"},
4937
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4938
    0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"},
4939
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4940
    0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"},
4941
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4942
    0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"},
4943
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4944
    0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"},
4945
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4946
    0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"},
4947
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4948
    0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"},
4949
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4950
    0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"},
4951
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4952
    0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"},
4953
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4954
    0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"},
4955
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4956
    0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"},
4957
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4958
    0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"},
4959
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4960
    0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"},
4961
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4962
    0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4963
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4964
    0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4965
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4966
    0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4967
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4968
    0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"},
4969
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4970
    0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"},
4971
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4972
    0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, %{I:#%0-4D%}, %16-19r"},
4973
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4974
    0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, %{I:#%0-4d%}, %16-19r"},
4975
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4976
    0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"},
4977
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4978
    0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"},
4979
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4980
    0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"},
4981
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4982
    0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"},
4983
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4984
    0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"},
4985
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4986
    0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"},
4987
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4988
    0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
4989
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4990
    0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
4991
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4992
    0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"},
4993
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4994
    0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"},
4995
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4996
    0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"},
4997
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4998
    0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"},
4999
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5000
    0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"},
5001
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5002
    0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"},
5003
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5004
    0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"},
5005
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5006
    0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"},
5007
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5008
    0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"},
5009
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5010
    0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"},
5011
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5012
    0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"},
5013
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5014
    0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"},
5015
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5016
    0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"},
5017
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5018
    0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"},
5019
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5020
    0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"},
5021
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5022
    0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
5023
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5024
    0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
5025
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5026
    0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
5027
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5028
    0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
5029
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5030
    0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
5031
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5032
    0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
5033
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5034
    0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
5035
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5036
    0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
5037
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
5038
    0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, %{I:#%0-7W%}]"},
5039
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5040
    0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"},
5041
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5042
    0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"},
5043
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5044
    0xf810f000, 0xff70f000, "pld%c\t%a"},
5045
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5046
    0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
5047
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5048
    0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
5049
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5050
    0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
5051
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5052
    0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
5053
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5054
    0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
5055
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5056
    0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
5057
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5058
    0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
5059
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5060
    0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"},
5061
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5062
    0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"},
5063
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5064
    0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"},
5065
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5066
    0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"},
5067
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5068
    0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"},
5069
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5070
    0xfb100000, 0xfff000c0,
5071
    "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
5072
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5073
    0xfbc00080, 0xfff000c0,
5074
    "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
5075
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5076
    0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"},
5077
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5078
    0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"},
5079
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5080
    0xf3000000, 0xffd08020, "ssat%c\t%8-11r, %{I:#%0-4D%}, %16-19r%s"},
5081
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5082
    0xf3800000, 0xffd08020, "usat%c\t%8-11r, %{I:#%0-4d%}, %16-19r%s"},
5083
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5084
    0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"},
5085
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
5086
    0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"},
5087
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5088
    0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"},
5089
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
5090
    0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"},
5091
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5092
    0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"},
5093
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5094
    0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"},
5095
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5096
    0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"},
5097
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5098
    0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"},
5099
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5100
    0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"},
5101
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5102
    0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"},
5103
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5104
    0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"},
5105
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5106
    0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"},
5107
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5108
    0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"},
5109
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5110
    0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"},
5111
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
5112
    0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, %{I:#%0-7W%}]"},
5113
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5114
    0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"},
5115
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5116
    0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"},
5117
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5118
    0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"},
5119
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5120
    0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"},
5121
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5122
    0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"},
5123
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5124
    0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"},
5125
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5126
    0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"},
5127
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5128
    0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"},
5129
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5130
    0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"},
5131
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5132
    0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"},
5133
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5134
    0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"},
5135
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5136
    0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"},
5137
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5138
    0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"},
5139
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5140
    0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"},
5141
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5142
    0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"},
5143
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5144
    0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"},
5145
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5146
    0xe9400000, 0xff500000,
5147
    "strd%c\t%12-15r, %8-11r, [%16-19r, %{I:#%23`-%0-7W%}]%21'!%L"},
5148
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5149
    0xe9500000, 0xff500000,
5150
    "ldrd%c\t%12-15r, %8-11r, [%16-19r, %{I:#%23`-%0-7W%}]%21'!%L"},
5151
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5152
    0xe8600000, 0xff700000,
5153
    "strd%c\t%12-15r, %8-11r, [%16-19r], %{I:#%23`-%0-7W%}%L"},
5154
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5155
    0xe8700000, 0xff700000,
5156
    "ldrd%c\t%12-15r, %8-11r, [%16-19r], %{I:#%23`-%0-7W%}%L"},
5157
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5158
    0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"},
5159
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5160
    0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"},
5161
5162
  /* Filter out Bcc with cond=E or F, which are used for other instructions.  */
5163
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5164
    0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"},
5165
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5166
    0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"},
5167
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5168
    0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"},
5169
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5170
    0xf0009000, 0xf800d000, "b%c.w\t%B%x"},
5171
5172
  /* These have been 32-bit since the invention of Thumb.  */
5173
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
5174
     0xf000c000, 0xf800d001, "blx%c\t%B%x"},
5175
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
5176
     0xf000d000, 0xf800d000, "bl%c\t%B%x"},
5177
5178
  /* Fallback.  */
5179
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
5180
      0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
5181
  {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
5182
};
5183
5184
static const char *const arm_conditional[] =
5185
{"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
5186
 "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""};
5187
5188
static const char *const arm_fp_const[] =
5189
{"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
5190
5191
static const char *const arm_shift[] =
5192
{"lsl", "lsr", "asr", "ror"};
5193
5194
typedef struct
5195
{
5196
  const char *name;
5197
  const char *description;
5198
  const char *reg_names[16];
5199
}
5200
arm_regname;
5201
5202
static const arm_regname regnames[] =
5203
{
5204
  { "reg-names-raw", N_("Select raw register names"),
5205
    { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
5206
  { "reg-names-gcc", N_("Select register names used by GCC"),
5207
    { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl",  "fp",  "ip",  "sp",  "lr",  "pc" }},
5208
  { "reg-names-std", N_("Select register names used in ARM's ISA documentation"),
5209
    { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp",  "lr",  "pc" }},
5210
  { "force-thumb", N_("Assume all insns are Thumb insns"), {NULL} },
5211
  { "no-force-thumb", N_("Examine preceding label to determine an insn's type"), {NULL} },
5212
  { "reg-names-apcs", N_("Select register names used in the APCS"),
5213
    { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl",  "fp",  "ip",  "sp",  "lr",  "pc" }},
5214
  { "reg-names-atpcs", N_("Select register names used in the ATPCS"),
5215
    { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7",  "v8",  "IP",  "SP",  "LR",  "PC" }},
5216
  { "reg-names-special-atpcs", N_("Select special register names used in the ATPCS"),
5217
    { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL",  "FP",  "IP",  "SP",  "LR",  "PC" }},
5218
  { "coproc<N>=(cde|generic)", N_("Enable CDE extensions for coprocessor N space"), { NULL } }
5219
};
5220
5221
static const char *const iwmmxt_wwnames[] =
5222
{"b", "h", "w", "d"};
5223
5224
static const char *const iwmmxt_wwssnames[] =
5225
{"b", "bus", "bc", "bss",
5226
 "h", "hus", "hc", "hss",
5227
 "w", "wus", "wc", "wss",
5228
 "d", "dus", "dc", "dss"
5229
};
5230
5231
static const char *const iwmmxt_regnames[] =
5232
{ "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7",
5233
  "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"
5234
};
5235
5236
static const char *const iwmmxt_cregnames[] =
5237
{ "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved",
5238
  "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"
5239
};
5240
5241
static const char *const vec_condnames[] =
5242
{ "eq", "ne", "cs", "hi", "ge", "lt", "gt", "le"
5243
};
5244
5245
static const char *const mve_predicatenames[] =
5246
{ "", "ttt", "tt", "tte", "t", "tee", "te", "tet", "",
5247
  "eee", "ee", "eet", "e", "ett", "et", "ete"
5248
};
5249
5250
/* Names for 2-bit size field for mve vector isntructions.  */
5251
static const char *const mve_vec_sizename[] =
5252
  { "8", "16", "32", "64"};
5253
5254
/* Indicates whether we are processing a then predicate,
5255
   else predicate or none at all.  */
5256
enum vpt_pred_state
5257
{
5258
  PRED_NONE,
5259
  PRED_THEN,
5260
  PRED_ELSE
5261
};
5262
5263
/* Information used to process a vpt block and subsequent instructions.  */
5264
struct vpt_block
5265
{
5266
  /* Are we in a vpt block.  */
5267
  bool in_vpt_block;
5268
5269
  /* Next predicate state if in vpt block.  */
5270
  enum vpt_pred_state next_pred_state;
5271
5272
  /* Mask from vpt/vpst instruction.  */
5273
  long predicate_mask;
5274
5275
  /* Instruction number in vpt block.  */
5276
  long current_insn_num;
5277
5278
  /* Number of instructions in vpt block..   */
5279
  long num_pred_insn;
5280
};
5281
5282
static struct vpt_block vpt_block_state =
5283
{
5284
  false,
5285
  PRED_NONE,
5286
  0,
5287
  0,
5288
  0
5289
};
5290
5291
/* Default to GCC register name set.  */
5292
static unsigned int regname_selected = 1;
5293
5294
0
#define NUM_ARM_OPTIONS   ARRAY_SIZE (regnames)
5295
0
#define arm_regnames      regnames[regname_selected].reg_names
5296
5297
static bool force_thumb = false;
5298
static uint16_t cde_coprocs = 0;
5299
5300
/* Current IT instruction state.  This contains the same state as the IT
5301
   bits in the CPSR.  */
5302
static unsigned int ifthen_state;
5303
/* IT state for the next instruction.  */
5304
static unsigned int ifthen_next_state;
5305
/* The address of the insn for which the IT state is valid.  */
5306
static bfd_vma ifthen_address;
5307
0
#define IFTHEN_COND ((ifthen_state >> 4) & 0xf)
5308
/* Indicates that the current Conditional state is unconditional or outside
5309
   an IT block.  */
5310
0
#define COND_UNCOND 16
5311
5312

5313
/* Functions.  */
5314
/* Extract the predicate mask for a VPT or VPST instruction.
5315
   The mask is composed of bits 13-15 (Mkl) and bit 22 (Mkh).  */
5316
5317
static long
5318
mve_extract_pred_mask (long given)
5319
0
{
5320
0
  return ((given & 0x00400000) >> 19) | ((given & 0xe000) >> 13);
5321
0
}
5322
5323
/* Return the number of instructions in a MVE predicate block.  */
5324
static long
5325
num_instructions_vpt_block (long given)
5326
0
{
5327
0
  long mask = mve_extract_pred_mask (given);
5328
0
  if (mask == 0)
5329
0
    return 0;
5330
5331
0
  if (mask == 8)
5332
0
    return 1;
5333
5334
0
  if ((mask & 7) == 4)
5335
0
    return 2;
5336
5337
0
  if ((mask & 3) == 2)
5338
0
    return 3;
5339
5340
0
  if ((mask & 1) == 1)
5341
0
    return 4;
5342
5343
0
  return 0;
5344
0
}
5345
5346
static void
5347
mark_outside_vpt_block (void)
5348
0
{
5349
0
  vpt_block_state.in_vpt_block = false;
5350
0
  vpt_block_state.next_pred_state = PRED_NONE;
5351
0
  vpt_block_state.predicate_mask = 0;
5352
0
  vpt_block_state.current_insn_num = 0;
5353
0
  vpt_block_state.num_pred_insn = 0;
5354
0
}
5355
5356
static void
5357
mark_inside_vpt_block (long given)
5358
0
{
5359
0
  vpt_block_state.in_vpt_block = true;
5360
0
  vpt_block_state.next_pred_state = PRED_THEN;
5361
0
  vpt_block_state.predicate_mask = mve_extract_pred_mask (given);
5362
0
  vpt_block_state.current_insn_num = 0;
5363
0
  vpt_block_state.num_pred_insn = num_instructions_vpt_block (given);
5364
0
  assert (vpt_block_state.num_pred_insn >= 1);
5365
0
}
5366
5367
static enum vpt_pred_state
5368
invert_next_predicate_state (enum vpt_pred_state astate)
5369
0
{
5370
0
  if (astate == PRED_THEN)
5371
0
    return PRED_ELSE;
5372
0
  else if (astate == PRED_ELSE)
5373
0
    return PRED_THEN;
5374
0
  else
5375
0
    return PRED_NONE;
5376
0
}
5377
5378
static enum vpt_pred_state
5379
update_next_predicate_state (void)
5380
0
{
5381
0
  long pred_mask = vpt_block_state.predicate_mask;
5382
0
  long mask_for_insn = 0;
5383
5384
0
  switch (vpt_block_state.current_insn_num)
5385
0
    {
5386
0
    case 1:
5387
0
      mask_for_insn = 8;
5388
0
      break;
5389
5390
0
    case 2:
5391
0
      mask_for_insn = 4;
5392
0
      break;
5393
5394
0
    case 3:
5395
0
      mask_for_insn = 2;
5396
0
      break;
5397
5398
0
    case 4:
5399
0
      return PRED_NONE;
5400
0
    }
5401
5402
0
  if (pred_mask & mask_for_insn)
5403
0
    return invert_next_predicate_state (vpt_block_state.next_pred_state);
5404
0
  else
5405
0
    return vpt_block_state.next_pred_state;
5406
0
}
5407
5408
static void
5409
update_vpt_block_state (void)
5410
0
{
5411
0
  vpt_block_state.current_insn_num++;
5412
0
  if (vpt_block_state.current_insn_num == vpt_block_state.num_pred_insn)
5413
0
    {
5414
      /* No more instructions to process in vpt block.  */
5415
0
      mark_outside_vpt_block ();
5416
0
      return;
5417
0
    }
5418
5419
0
  vpt_block_state.next_pred_state = update_next_predicate_state ();
5420
0
}
5421
5422
/* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?.
5423
   Returns pointer to following character of the format string and
5424
   fills in *VALUEP and *WIDTHP with the extracted value and number of
5425
   bits extracted.  WIDTHP can be NULL.  */
5426
5427
static const char *
5428
arm_decode_bitfield (const char *ptr,
5429
         unsigned long insn,
5430
         unsigned long *valuep,
5431
         int *widthp)
5432
0
{
5433
0
  unsigned long value = 0;
5434
0
  int width = 0;
5435
5436
0
  do
5437
0
    {
5438
0
      int start, end;
5439
0
      int bits;
5440
5441
0
      for (start = 0; *ptr >= '0' && *ptr <= '9'; ptr++)
5442
0
  start = start * 10 + *ptr - '0';
5443
0
      if (*ptr == '-')
5444
0
  for (end = 0, ptr++; *ptr >= '0' && *ptr <= '9'; ptr++)
5445
0
    end = end * 10 + *ptr - '0';
5446
0
      else
5447
0
  end = start;
5448
0
      bits = end - start;
5449
0
      if (bits < 0)
5450
0
  abort ();
5451
0
      value |= ((insn >> start) & ((2ul << bits) - 1)) << width;
5452
0
      width += bits + 1;
5453
0
    }
5454
0
  while (*ptr++ == ',');
5455
0
  *valuep = value;
5456
0
  if (widthp)
5457
0
    *widthp = width;
5458
0
  return ptr - 1;
5459
0
}
5460
5461
static void
5462
arm_decode_shift (long given, fprintf_styled_ftype func, void *stream,
5463
      bool print_shift)
5464
0
{
5465
0
  func (stream, dis_style_register, "%s", arm_regnames[given & 0xf]);
5466
5467
0
  if ((given & 0xff0) != 0)
5468
0
    {
5469
0
      if ((given & 0x10) == 0)
5470
0
  {
5471
0
    int amount = (given & 0xf80) >> 7;
5472
0
    int shift = (given & 0x60) >> 5;
5473
5474
0
    if (amount == 0)
5475
0
      {
5476
0
        if (shift == 3)
5477
0
    {
5478
0
      func (stream, dis_style_text, ", ");
5479
0
      func (stream, dis_style_sub_mnemonic, "rrx");
5480
0
      return;
5481
0
    }
5482
5483
0
        amount = 32;
5484
0
      }
5485
5486
0
    if (print_shift)
5487
0
      {
5488
0
        func (stream, dis_style_text, ", ");
5489
0
        func (stream, dis_style_sub_mnemonic, "%s ", arm_shift[shift]);
5490
0
        func (stream, dis_style_immediate, "#%d", amount);
5491
0
      }
5492
0
    else
5493
0
      {
5494
0
        func (stream, dis_style_text, ", ");
5495
0
        func (stream, dis_style_immediate, "#%d", amount);
5496
0
      }
5497
0
  }
5498
0
      else if ((given & 0x80) == 0x80)
5499
0
  func (stream, dis_style_comment_start,
5500
0
        "\t@ <illegal shifter operand>");
5501
0
      else if (print_shift)
5502
0
  {
5503
0
    func (stream, dis_style_text, ", ");
5504
0
    func (stream, dis_style_sub_mnemonic, "%s ",
5505
0
    arm_shift[(given & 0x60) >> 5]);
5506
0
    func (stream, dis_style_register, "%s",
5507
0
    arm_regnames[(given & 0xf00) >> 8]);
5508
0
  }
5509
0
      else
5510
0
  {
5511
0
    func (stream, dis_style_text, ", ");
5512
0
    func (stream, dis_style_register, "%s",
5513
0
    arm_regnames[(given & 0xf00) >> 8]);
5514
0
  }
5515
0
    }
5516
0
}
5517
5518
/* Return TRUE if the MATCHED_INSN can be inside an IT block.  */
5519
5520
static bool
5521
is_mve_okay_in_it (enum mve_instructions matched_insn)
5522
0
{
5523
0
  switch (matched_insn)
5524
0
    {
5525
0
    case MVE_VMOV_GP_TO_VEC_LANE:
5526
0
    case MVE_VMOV2_VEC_LANE_TO_GP:
5527
0
    case MVE_VMOV2_GP_TO_VEC_LANE:
5528
0
    case MVE_VMOV_VEC_LANE_TO_GP:
5529
0
    case MVE_LSLL:
5530
0
    case MVE_LSLLI:
5531
0
    case MVE_LSRL:
5532
0
    case MVE_ASRL:
5533
0
    case MVE_ASRLI:
5534
0
    case MVE_SQRSHRL:
5535
0
    case MVE_SQRSHR:
5536
0
    case MVE_UQRSHL:
5537
0
    case MVE_UQRSHLL:
5538
0
    case MVE_UQSHL:
5539
0
    case MVE_UQSHLL:
5540
0
    case MVE_URSHRL:
5541
0
    case MVE_URSHR:
5542
0
    case MVE_SRSHRL:
5543
0
    case MVE_SRSHR:
5544
0
    case MVE_SQSHLL:
5545
0
    case MVE_SQSHL:
5546
0
      return true;
5547
0
    default:
5548
0
      return false;
5549
0
    }
5550
0
}
5551
5552
static bool
5553
is_mve_architecture (struct disassemble_info *info)
5554
0
{
5555
0
  struct arm_private_data *private_data = info->private_data;
5556
0
  arm_feature_set allowed_arches = private_data->features;
5557
5558
0
  arm_feature_set arm_ext_v8_1m_main
5559
0
    = ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN);
5560
5561
0
  if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
5562
0
      && !ARM_CPU_IS_ANY (allowed_arches))
5563
0
    return true;
5564
0
  else
5565
0
    return false;
5566
0
}
5567
5568
static bool
5569
is_vpt_instruction (long given)
5570
0
{
5571
5572
  /* If mkh:mkl is '0000' then its not a vpt/vpst instruction.  */
5573
0
  if ((given & 0x0040e000) == 0)
5574
0
    return false;
5575
5576
  /* VPT floating point T1 variant.  */
5577
0
  if (((given & 0xefb10f50) == 0xee310f00 && ((given & 0x1001) != 0x1))
5578
  /* VPT floating point T2 variant.  */
5579
0
      || ((given & 0xefb10f50) == 0xee310f40)
5580
  /* VPT vector T1 variant.  */
5581
0
      || ((given & 0xff811f51) == 0xfe010f00)
5582
  /* VPT vector T2 variant.  */
5583
0
      || ((given & 0xff811f51) == 0xfe010f01
5584
0
    && ((given & 0x300000) != 0x300000))
5585
  /* VPT vector T3 variant.  */
5586
0
      || ((given & 0xff811f50) == 0xfe011f00)
5587
  /* VPT vector T4 variant.  */
5588
0
      || ((given & 0xff811f70) == 0xfe010f40)
5589
  /* VPT vector T5 variant.  */
5590
0
      || ((given & 0xff811f70) == 0xfe010f60)
5591
  /* VPT vector T6 variant.  */
5592
0
      || ((given & 0xff811f50) == 0xfe011f40)
5593
  /* VPST vector T variant.  */
5594
0
      || ((given & 0xffbf1fff) == 0xfe310f4d))
5595
0
    return true;
5596
0
  else
5597
0
    return false;
5598
0
}
5599
5600
/* Decode a bitfield from opcode GIVEN, with starting bitfield = START
5601
   and ending bitfield = END.  END must be greater than START.  */
5602
5603
static unsigned long
5604
arm_decode_field (unsigned long given, unsigned int start, unsigned int end)
5605
0
{
5606
0
  int bits = end - start;
5607
5608
0
  if (bits < 0)
5609
0
    abort ();
5610
5611
0
  return ((given >> start) & ((2ul << bits) - 1));
5612
0
}
5613
5614
/* Decode a bitfield from opcode GIVEN, with multiple bitfields:
5615
   START:END and START2:END2.  END/END2 must be greater than
5616
   START/START2.  */
5617
5618
static unsigned long
5619
arm_decode_field_multiple (unsigned long given, unsigned int start,
5620
         unsigned int end, unsigned int start2,
5621
         unsigned int end2)
5622
0
{
5623
0
  int bits = end - start;
5624
0
  int bits2 = end2 - start2;
5625
0
  unsigned long value = 0;
5626
0
  int width = 0;
5627
5628
0
  if (bits2 < 0)
5629
0
    abort ();
5630
5631
0
  value = arm_decode_field (given, start, end);
5632
0
  width += bits + 1;
5633
5634
0
  value |= ((given >> start2) & ((2ul << bits2) - 1)) << width;
5635
0
  return value;
5636
0
}
5637
5638
/* Return TRUE if the GIVEN encoding should not be decoded as MATCHED_INSN.
5639
   This helps us decode instructions that change mnemonic depending on specific
5640
   operand values/encodings.  */
5641
5642
static bool
5643
is_mve_encoding_conflict (unsigned long given,
5644
        enum mve_instructions matched_insn)
5645
0
{
5646
0
  switch (matched_insn)
5647
0
    {
5648
0
    case MVE_VPST:
5649
0
      if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
5650
0
  return true;
5651
0
      else
5652
0
  return false;
5653
5654
0
    case MVE_VPT_FP_T1:
5655
0
      if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
5656
0
  return true;
5657
0
      if ((arm_decode_field (given, 12, 12) == 0)
5658
0
    && (arm_decode_field (given, 0, 0) == 1))
5659
0
  return true;
5660
0
      return false;
5661
5662
0
    case MVE_VPT_FP_T2:
5663
0
      if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
5664
0
  return true;
5665
0
      if (arm_decode_field (given, 0, 3) == 0xd)
5666
0
  return true;
5667
0
      return false;
5668
5669
0
    case MVE_VPT_VEC_T1:
5670
0
    case MVE_VPT_VEC_T2:
5671
0
    case MVE_VPT_VEC_T3:
5672
0
    case MVE_VPT_VEC_T4:
5673
0
    case MVE_VPT_VEC_T5:
5674
0
    case MVE_VPT_VEC_T6:
5675
0
      if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
5676
0
  return true;
5677
0
      if (arm_decode_field (given, 20, 21) == 3)
5678
0
  return true;
5679
0
      return false;
5680
5681
0
    case MVE_VCMP_FP_T1:
5682
0
      if ((arm_decode_field (given, 12, 12) == 0)
5683
0
    && (arm_decode_field (given, 0, 0) == 1))
5684
0
  return true;
5685
0
      else
5686
0
  return false;
5687
5688
0
    case MVE_VCMP_FP_T2:
5689
0
      if (arm_decode_field (given, 0, 3) == 0xd)
5690
0
  return true;
5691
0
      else
5692
0
  return false;
5693
5694
0
    case MVE_VQADD_T2:
5695
0
    case MVE_VQSUB_T2:
5696
0
    case MVE_VMUL_VEC_T2:
5697
0
    case MVE_VMULH:
5698
0
    case MVE_VRMULH:
5699
0
    case MVE_VMLA:
5700
0
    case MVE_VMAX:
5701
0
    case MVE_VMIN:
5702
0
    case MVE_VBRSR:
5703
0
    case MVE_VADD_VEC_T2:
5704
0
    case MVE_VSUB_VEC_T2:
5705
0
    case MVE_VABAV:
5706
0
    case MVE_VQRSHL_T1:
5707
0
    case MVE_VQSHL_T4:
5708
0
    case MVE_VRSHL_T1:
5709
0
    case MVE_VSHL_T3:
5710
0
    case MVE_VCADD_VEC:
5711
0
    case MVE_VHCADD:
5712
0
    case MVE_VDDUP:
5713
0
    case MVE_VIDUP:
5714
0
    case MVE_VQRDMLADH:
5715
0
    case MVE_VQDMLAH:
5716
0
    case MVE_VQRDMLAH:
5717
0
    case MVE_VQDMLASH:
5718
0
    case MVE_VQRDMLASH:
5719
0
    case MVE_VQDMLSDH:
5720
0
    case MVE_VQRDMLSDH:
5721
0
    case MVE_VQDMULH_T3:
5722
0
    case MVE_VQRDMULH_T4:
5723
0
    case MVE_VQDMLADH:
5724
0
    case MVE_VMLAS:
5725
0
    case MVE_VMULL_INT:
5726
0
    case MVE_VHADD_T2:
5727
0
    case MVE_VHSUB_T2:
5728
0
    case MVE_VCMP_VEC_T1:
5729
0
    case MVE_VCMP_VEC_T2:
5730
0
    case MVE_VCMP_VEC_T3:
5731
0
    case MVE_VCMP_VEC_T4:
5732
0
    case MVE_VCMP_VEC_T5:
5733
0
    case MVE_VCMP_VEC_T6:
5734
0
      if (arm_decode_field (given, 20, 21) == 3)
5735
0
  return true;
5736
0
      else
5737
0
  return false;
5738
5739
0
    case MVE_VLD2:
5740
0
    case MVE_VLD4:
5741
0
    case MVE_VST2:
5742
0
    case MVE_VST4:
5743
0
      if (arm_decode_field (given, 7, 8) == 3)
5744
0
  return true;
5745
0
      else
5746
0
  return false;
5747
5748
0
    case MVE_VSTRB_T1:
5749
0
    case MVE_VSTRH_T2:
5750
0
      if ((arm_decode_field (given, 24, 24) == 0)
5751
0
    && (arm_decode_field (given, 21, 21) == 0))
5752
0
  {
5753
0
      return true;
5754
0
  }
5755
0
      else if ((arm_decode_field (given, 7, 8) == 3))
5756
0
  return true;
5757
0
      else
5758
0
  return false;
5759
5760
0
    case MVE_VLDRB_T1:
5761
0
    case MVE_VLDRH_T2:
5762
0
    case MVE_VLDRW_T7:
5763
0
    case MVE_VSTRB_T5:
5764
0
    case MVE_VSTRH_T6:
5765
0
    case MVE_VSTRW_T7:
5766
0
      if ((arm_decode_field (given, 24, 24) == 0)
5767
0
    && (arm_decode_field (given, 21, 21) == 0))
5768
0
  {
5769
0
      return true;
5770
0
  }
5771
0
      else
5772
0
  return false;
5773
5774
0
    case MVE_VCVT_FP_FIX_VEC:
5775
0
      return (arm_decode_field (given, 16, 21) & 0x38) == 0;
5776
5777
0
    case MVE_VBIC_IMM:
5778
0
    case MVE_VORR_IMM:
5779
0
      {
5780
0
  unsigned long cmode = arm_decode_field (given, 8, 11);
5781
5782
0
  if ((cmode & 1) == 0)
5783
0
    return true;
5784
0
  else if ((cmode & 0xc) == 0xc)
5785
0
    return true;
5786
0
  else
5787
0
    return false;
5788
0
      }
5789
5790
0
    case MVE_VMVN_IMM:
5791
0
      {
5792
0
  unsigned long cmode = arm_decode_field (given, 8, 11);
5793
5794
0
  if (cmode == 0xe)
5795
0
    return true;
5796
0
  else if ((cmode & 0x9) == 1)
5797
0
    return true;
5798
0
  else if ((cmode & 0xd) == 9)
5799
0
    return true;
5800
0
  else
5801
0
    return false;
5802
0
      }
5803
5804
0
    case MVE_VMOV_IMM_TO_VEC:
5805
0
      if ((arm_decode_field (given, 5, 5) == 1)
5806
0
    && (arm_decode_field (given, 8, 11) != 0xe))
5807
0
  return true;
5808
0
      else
5809
0
  return false;
5810
5811
0
    case MVE_VMOVL:
5812
0
      {
5813
0
  unsigned long size = arm_decode_field (given, 19, 20);
5814
0
  if ((size == 0) || (size == 3))
5815
0
    return true;
5816
0
  else
5817
0
    return false;
5818
0
      }
5819
5820
0
    case MVE_VMAXA:
5821
0
    case MVE_VMINA:
5822
0
    case MVE_VMAXV:
5823
0
    case MVE_VMAXAV:
5824
0
    case MVE_VMINV:
5825
0
    case MVE_VMINAV:
5826
0
    case MVE_VQRSHL_T2:
5827
0
    case MVE_VQSHL_T1:
5828
0
    case MVE_VRSHL_T2:
5829
0
    case MVE_VSHL_T2:
5830
0
    case MVE_VSHLL_T2:
5831
0
    case MVE_VADDV:
5832
0
    case MVE_VMOVN:
5833
0
    case MVE_VQMOVUN:
5834
0
    case MVE_VQMOVN:
5835
0
      if (arm_decode_field (given, 18, 19) == 3)
5836
0
  return true;
5837
0
      else
5838
0
  return false;
5839
5840
0
    case MVE_VMLSLDAV:
5841
0
    case MVE_VRMLSLDAVH:
5842
0
    case MVE_VMLALDAV:
5843
0
    case MVE_VADDLV:
5844
0
      if (arm_decode_field (given, 20, 22) == 7)
5845
0
  return true;
5846
0
      else
5847
0
  return false;
5848
5849
0
    case MVE_VRMLALDAVH:
5850
0
      if ((arm_decode_field (given, 20, 22) & 6) == 6)
5851
0
  return true;
5852
0
      else
5853
0
  return false;
5854
5855
0
    case MVE_VDWDUP:
5856
0
    case MVE_VIWDUP:
5857
0
      if ((arm_decode_field (given, 20, 21) == 3)
5858
0
    || (arm_decode_field (given, 1, 3) == 7))
5859
0
  return true;
5860
0
      else
5861
0
  return false;
5862
5863
5864
0
    case MVE_VSHLL_T1:
5865
0
      if (arm_decode_field (given, 16, 18) == 0)
5866
0
  {
5867
0
    unsigned long sz = arm_decode_field (given, 19, 20);
5868
5869
0
    if ((sz == 1) || (sz == 2))
5870
0
      return true;
5871
0
    else
5872
0
      return false;
5873
0
  }
5874
0
      else
5875
0
  return false;
5876
5877
0
    case MVE_VQSHL_T2:
5878
0
    case MVE_VQSHLU_T3:
5879
0
    case MVE_VRSHR:
5880
0
    case MVE_VSHL_T1:
5881
0
    case MVE_VSHR:
5882
0
    case MVE_VSLI:
5883
0
    case MVE_VSRI:
5884
0
      if (arm_decode_field (given, 19, 21) == 0)
5885
0
  return true;
5886
0
      else
5887
0
  return false;
5888
5889
0
    case MVE_VCTP:
5890
0
    if (arm_decode_field (given, 16, 19) == 0xf)
5891
0
      return true;
5892
0
    else
5893
0
      return false;
5894
5895
0
    case MVE_ASRLI:
5896
0
    case MVE_ASRL:
5897
0
    case MVE_LSLLI:
5898
0
    case MVE_LSLL:
5899
0
    case MVE_LSRL:
5900
0
    case MVE_SQRSHRL:
5901
0
    case MVE_SQSHLL:
5902
0
    case MVE_SRSHRL:
5903
0
    case MVE_UQRSHLL:
5904
0
    case MVE_UQSHLL:
5905
0
    case MVE_URSHRL:
5906
0
      if (arm_decode_field (given, 9, 11) == 0x7)
5907
0
  return true;
5908
0
      else
5909
0
  return false;
5910
5911
0
    case MVE_CSINC:
5912
0
    case MVE_CSINV:
5913
0
      {
5914
0
  unsigned long rm, rn;
5915
0
  rm = arm_decode_field (given, 0, 3);
5916
0
  rn = arm_decode_field (given, 16, 19);
5917
  /* CSET/CSETM.  */
5918
0
  if (rm == 0xf && rn == 0xf)
5919
0
    return true;
5920
  /* CINC/CINV.  */
5921
0
  else if (rn == rm && rn != 0xf)
5922
0
    return true;
5923
0
      }
5924
    /* Fall through.  */
5925
0
    case MVE_CSEL:
5926
0
    case MVE_CSNEG:
5927
0
      if (arm_decode_field (given, 0, 3) == 0xd)
5928
0
  return true;
5929
      /* CNEG.  */
5930
0
      else if (matched_insn == MVE_CSNEG)
5931
0
  if (arm_decode_field (given, 0, 3) == arm_decode_field (given, 16, 19))
5932
0
    return true;
5933
0
      return false;
5934
5935
0
    default:
5936
0
    case MVE_VADD_FP_T1:
5937
0
    case MVE_VADD_FP_T2:
5938
0
    case MVE_VADD_VEC_T1:
5939
0
      return false;
5940
5941
0
    }
5942
0
}
5943
5944
static void
5945
print_mve_vld_str_addr (struct disassemble_info *info,
5946
      unsigned long given,
5947
      enum mve_instructions matched_insn)
5948
0
{
5949
0
  void *stream = info->stream;
5950
0
  fprintf_styled_ftype func = info->fprintf_styled_func;
5951
5952
0
  unsigned long p, w, gpr, imm, add, mod_imm;
5953
5954
0
  imm = arm_decode_field (given, 0, 6);
5955
0
  mod_imm = imm;
5956
5957
0
  switch (matched_insn)
5958
0
    {
5959
0
    case MVE_VLDRB_T1:
5960
0
    case MVE_VSTRB_T1:
5961
0
      gpr = arm_decode_field (given, 16, 18);
5962
0
      break;
5963
5964
0
    case MVE_VLDRH_T2:
5965
0
    case MVE_VSTRH_T2:
5966
0
      gpr = arm_decode_field (given, 16, 18);
5967
0
      mod_imm = imm << 1;
5968
0
      break;
5969
5970
0
    case MVE_VLDRH_T6:
5971
0
    case MVE_VSTRH_T6:
5972
0
      gpr = arm_decode_field (given, 16, 19);
5973
0
      mod_imm = imm << 1;
5974
0
      break;
5975
5976
0
    case MVE_VLDRW_T7:
5977
0
    case MVE_VSTRW_T7:
5978
0
      gpr = arm_decode_field (given, 16, 19);
5979
0
      mod_imm = imm << 2;
5980
0
      break;
5981
5982
0
    case MVE_VLDRB_T5:
5983
0
    case MVE_VSTRB_T5:
5984
0
      gpr = arm_decode_field (given, 16, 19);
5985
0
      break;
5986
5987
0
    default:
5988
0
      return;
5989
0
    }
5990
5991
0
  p = arm_decode_field (given, 24, 24);
5992
0
  w = arm_decode_field (given, 21, 21);
5993
5994
0
  add = arm_decode_field (given, 23, 23);
5995
5996
0
  char * add_sub;
5997
5998
  /* Don't print anything for '+' as it is implied.  */
5999
0
  if (add == 1)
6000
0
    add_sub = "";
6001
0
  else
6002
0
    add_sub = "-";
6003
6004
0
  func (stream, dis_style_text, "[");
6005
0
  func (stream, dis_style_register, "%s", arm_regnames[gpr]);
6006
0
  if (p == 1)
6007
0
    {
6008
0
      func (stream, dis_style_text, ", ");
6009
0
      func (stream, dis_style_immediate, "#%s%lu", add_sub, mod_imm);
6010
      /* Offset mode.  */
6011
0
      if (w == 0)
6012
0
  func (stream, dis_style_text, "]");
6013
      /* Pre-indexed mode.  */
6014
0
      else
6015
0
  func (stream, dis_style_text, "]!");
6016
0
    }
6017
0
  else if ((p == 0) && (w == 1))
6018
0
    {
6019
      /* Post-index mode.  */
6020
0
      func (stream, dis_style_text, "], ");
6021
0
      func (stream, dis_style_immediate, "#%s%lu", add_sub, mod_imm);
6022
0
    }
6023
0
}
6024
6025
/* Return FALSE if GIVEN is not an undefined encoding for MATCHED_INSN.
6026
   Otherwise, return TRUE and set UNDEFINED_CODE to give a reason as to why
6027
   this encoding is undefined.  */
6028
6029
static bool
6030
is_mve_undefined (unsigned long given, enum mve_instructions matched_insn,
6031
      enum mve_undefined *undefined_code)
6032
0
{
6033
0
  *undefined_code = UNDEF_NONE;
6034
6035
0
  switch (matched_insn)
6036
0
    {
6037
0
    case MVE_VDUP:
6038
0
      if (arm_decode_field_multiple (given, 5, 5, 22, 22) == 3)
6039
0
  {
6040
0
    *undefined_code = UNDEF_SIZE_3;
6041
0
    return true;
6042
0
  }
6043
0
      else
6044
0
  return false;
6045
6046
0
    case MVE_VQADD_T1:
6047
0
    case MVE_VQSUB_T1:
6048
0
    case MVE_VMUL_VEC_T1:
6049
0
    case MVE_VABD_VEC:
6050
0
    case MVE_VADD_VEC_T1:
6051
0
    case MVE_VSUB_VEC_T1:
6052
0
    case MVE_VQDMULH_T1:
6053
0
    case MVE_VQRDMULH_T2:
6054
0
    case MVE_VRHADD:
6055
0
    case MVE_VHADD_T1:
6056
0
    case MVE_VHSUB_T1:
6057
0
      if (arm_decode_field (given, 20, 21) == 3)
6058
0
  {
6059
0
    *undefined_code = UNDEF_SIZE_3;
6060
0
    return true;
6061
0
  }
6062
0
      else
6063
0
  return false;
6064
6065
0
    case MVE_VLDRB_T1:
6066
0
      if (arm_decode_field (given, 7, 8) == 3)
6067
0
  {
6068
0
    *undefined_code = UNDEF_SIZE_3;
6069
0
    return true;
6070
0
  }
6071
0
      else
6072
0
  return false;
6073
6074
0
    case MVE_VLDRH_T2:
6075
0
      if (arm_decode_field (given, 7, 8) <= 1)
6076
0
  {
6077
0
    *undefined_code = UNDEF_SIZE_LE_1;
6078
0
    return true;
6079
0
  }
6080
0
      else
6081
0
  return false;
6082
6083
0
    case MVE_VSTRB_T1:
6084
0
      if ((arm_decode_field (given, 7, 8) == 0))
6085
0
  {
6086
0
    *undefined_code = UNDEF_SIZE_0;
6087
0
    return true;
6088
0
  }
6089
0
      else
6090
0
  return false;
6091
6092
0
    case MVE_VSTRH_T2:
6093
0
      if ((arm_decode_field (given, 7, 8) <= 1))
6094
0
  {
6095
0
    *undefined_code = UNDEF_SIZE_LE_1;
6096
0
    return true;
6097
0
  }
6098
0
      else
6099
0
  return false;
6100
6101
0
    case MVE_VLDRB_GATHER_T1:
6102
0
      if (arm_decode_field (given, 7, 8) == 3)
6103
0
  {
6104
0
    *undefined_code = UNDEF_SIZE_3;
6105
0
    return true;
6106
0
  }
6107
0
      else if ((arm_decode_field (given, 28, 28) == 0)
6108
0
         && (arm_decode_field (given, 7, 8) == 0))
6109
0
  {
6110
0
    *undefined_code = UNDEF_NOT_UNS_SIZE_0;
6111
0
    return true;
6112
0
  }
6113
0
      else
6114
0
  return false;
6115
6116
0
    case MVE_VLDRH_GATHER_T2:
6117
0
      if (arm_decode_field (given, 7, 8) == 3)
6118
0
  {
6119
0
    *undefined_code = UNDEF_SIZE_3;
6120
0
    return true;
6121
0
  }
6122
0
      else if ((arm_decode_field (given, 28, 28) == 0)
6123
0
         && (arm_decode_field (given, 7, 8) == 1))
6124
0
  {
6125
0
    *undefined_code = UNDEF_NOT_UNS_SIZE_1;
6126
0
    return true;
6127
0
  }
6128
0
      else if (arm_decode_field (given, 7, 8) == 0)
6129
0
  {
6130
0
    *undefined_code = UNDEF_SIZE_0;
6131
0
    return true;
6132
0
  }
6133
0
      else
6134
0
  return false;
6135
6136
0
    case MVE_VLDRW_GATHER_T3:
6137
0
      if (arm_decode_field (given, 7, 8) != 2)
6138
0
  {
6139
0
    *undefined_code = UNDEF_SIZE_NOT_2;
6140
0
    return true;
6141
0
  }
6142
0
      else if (arm_decode_field (given, 28, 28) == 0)
6143
0
  {
6144
0
    *undefined_code = UNDEF_NOT_UNSIGNED;
6145
0
    return true;
6146
0
  }
6147
0
      else
6148
0
  return false;
6149
6150
0
    case MVE_VLDRD_GATHER_T4:
6151
0
      if (arm_decode_field (given, 7, 8) != 3)
6152
0
  {
6153
0
    *undefined_code = UNDEF_SIZE_NOT_3;
6154
0
    return true;
6155
0
  }
6156
0
      else if (arm_decode_field (given, 28, 28) == 0)
6157
0
  {
6158
0
    *undefined_code = UNDEF_NOT_UNSIGNED;
6159
0
    return true;
6160
0
  }
6161
0
      else
6162
0
  return false;
6163
6164
0
    case MVE_VSTRB_SCATTER_T1:
6165
0
      if (arm_decode_field (given, 7, 8) == 3)
6166
0
  {
6167
0
    *undefined_code = UNDEF_SIZE_3;
6168
0
    return true;
6169
0
  }
6170
0
      else
6171
0
  return false;
6172
6173
0
    case MVE_VSTRH_SCATTER_T2:
6174
0
      {
6175
0
  unsigned long size = arm_decode_field (given, 7, 8);
6176
0
  if (size == 3)
6177
0
    {
6178
0
      *undefined_code = UNDEF_SIZE_3;
6179
0
      return true;
6180
0
    }
6181
0
  else if (size == 0)
6182
0
    {
6183
0
      *undefined_code = UNDEF_SIZE_0;
6184
0
      return true;
6185
0
    }
6186
0
  else
6187
0
    return false;
6188
0
      }
6189
6190
0
    case MVE_VSTRW_SCATTER_T3:
6191
0
      if (arm_decode_field (given, 7, 8) != 2)
6192
0
  {
6193
0
    *undefined_code = UNDEF_SIZE_NOT_2;
6194
0
    return true;
6195
0
  }
6196
0
      else
6197
0
  return false;
6198
6199
0
    case MVE_VSTRD_SCATTER_T4:
6200
0
      if (arm_decode_field (given, 7, 8) != 3)
6201
0
  {
6202
0
    *undefined_code = UNDEF_SIZE_NOT_3;
6203
0
    return true;
6204
0
  }
6205
0
      else
6206
0
  return false;
6207
6208
0
    case MVE_VCVT_FP_FIX_VEC:
6209
0
      {
6210
0
  unsigned long imm6 = arm_decode_field (given, 16, 21);
6211
0
  if ((imm6 & 0x20) == 0)
6212
0
    {
6213
0
      *undefined_code = UNDEF_VCVT_IMM6;
6214
0
      return true;
6215
0
    }
6216
6217
0
  if ((arm_decode_field (given, 9, 9) == 0)
6218
0
      && ((imm6 & 0x30) == 0x20))
6219
0
    {
6220
0
      *undefined_code = UNDEF_VCVT_FSI_IMM6;
6221
0
      return true;
6222
0
    }
6223
6224
0
  return false;
6225
0
      }
6226
6227
0
    case MVE_VNEG_FP:
6228
0
    case MVE_VABS_FP:
6229
0
    case MVE_VCVT_BETWEEN_FP_INT:
6230
0
    case MVE_VCVT_FROM_FP_TO_INT:
6231
0
      {
6232
0
  unsigned long size = arm_decode_field (given, 18, 19);
6233
0
  if (size == 0)
6234
0
    {
6235
0
      *undefined_code = UNDEF_SIZE_0;
6236
0
      return true;
6237
0
    }
6238
0
  else if (size == 3)
6239
0
    {
6240
0
      *undefined_code = UNDEF_SIZE_3;
6241
0
      return true;
6242
0
    }
6243
0
  else
6244
0
    return false;
6245
0
      }
6246
6247
0
    case MVE_VMOV_VEC_LANE_TO_GP:
6248
0
      {
6249
0
  unsigned long op1 = arm_decode_field (given, 21, 22);
6250
0
  unsigned long op2 = arm_decode_field (given, 5, 6);
6251
0
  unsigned long u = arm_decode_field (given, 23, 23);
6252
6253
0
  if ((op2 == 0) && (u == 1))
6254
0
    {
6255
0
      if ((op1 == 0) || (op1 == 1))
6256
0
        {
6257
0
    *undefined_code = UNDEF_BAD_U_OP1_OP2;
6258
0
    return true;
6259
0
        }
6260
0
      else
6261
0
        return false;
6262
0
    }
6263
0
  else if (op2 == 2)
6264
0
    {
6265
0
      if ((op1 == 0) || (op1 == 1))
6266
0
        {
6267
0
    *undefined_code = UNDEF_BAD_OP1_OP2;
6268
0
    return true;
6269
0
        }
6270
0
      else
6271
0
        return false;
6272
0
    }
6273
6274
0
  return false;
6275
0
      }
6276
6277
0
    case MVE_VMOV_GP_TO_VEC_LANE:
6278
0
      if (arm_decode_field (given, 5, 6) == 2)
6279
0
  {
6280
0
    unsigned long op1 = arm_decode_field (given, 21, 22);
6281
0
    if ((op1 == 0) || (op1 == 1))
6282
0
      {
6283
0
        *undefined_code = UNDEF_BAD_OP1_OP2;
6284
0
        return true;
6285
0
      }
6286
0
    else
6287
0
      return false;
6288
0
  }
6289
0
      else
6290
0
  return false;
6291
6292
0
    case MVE_VMOV_VEC_TO_VEC:
6293
0
      if ((arm_decode_field (given, 5, 5) == 1)
6294
0
    || (arm_decode_field (given, 22, 22) == 1))
6295
0
    return true;
6296
0
      return false;
6297
6298
0
    case MVE_VMOV_IMM_TO_VEC:
6299
0
      if (arm_decode_field (given, 5, 5) == 0)
6300
0
      {
6301
0
  unsigned long cmode = arm_decode_field (given, 8, 11);
6302
6303
0
  if (((cmode & 9) == 1) || ((cmode & 5) == 1))
6304
0
    {
6305
0
      *undefined_code = UNDEF_OP_0_BAD_CMODE;
6306
0
      return true;
6307
0
    }
6308
0
  else
6309
0
    return false;
6310
0
      }
6311
0
      else
6312
0
  return false;
6313
6314
0
    case MVE_VSHLL_T2:
6315
0
    case MVE_VMOVN:
6316
0
      if (arm_decode_field (given, 18, 19) == 2)
6317
0
  {
6318
0
    *undefined_code = UNDEF_SIZE_2;
6319
0
    return true;
6320
0
  }
6321
0
      else
6322
0
  return false;
6323
6324
0
    case MVE_VRMLALDAVH:
6325
0
    case MVE_VMLADAV_T1:
6326
0
    case MVE_VMLADAV_T2:
6327
0
    case MVE_VMLALDAV:
6328
0
      if ((arm_decode_field (given, 28, 28) == 1)
6329
0
    && (arm_decode_field (given, 12, 12) == 1))
6330
0
  {
6331
0
    *undefined_code = UNDEF_XCHG_UNS;
6332
0
    return true;
6333
0
  }
6334
0
      else
6335
0
  return false;
6336
6337
0
    case MVE_VQSHRN:
6338
0
    case MVE_VQSHRUN:
6339
0
    case MVE_VSHLL_T1:
6340
0
    case MVE_VSHRN:
6341
0
      {
6342
0
  unsigned long sz = arm_decode_field (given, 19, 20);
6343
0
  if (sz == 1)
6344
0
    return false;
6345
0
  else if ((sz & 2) == 2)
6346
0
    return false;
6347
0
  else
6348
0
    {
6349
0
      *undefined_code = UNDEF_SIZE;
6350
0
      return true;
6351
0
    }
6352
0
      }
6353
0
      break;
6354
6355
0
    case MVE_VQSHL_T2:
6356
0
    case MVE_VQSHLU_T3:
6357
0
    case MVE_VRSHR:
6358
0
    case MVE_VSHL_T1:
6359
0
    case MVE_VSHR:
6360
0
    case MVE_VSLI:
6361
0
    case MVE_VSRI:
6362
0
      {
6363
0
  unsigned long sz = arm_decode_field (given, 19, 21);
6364
0
  if ((sz & 7) == 1)
6365
0
    return false;
6366
0
  else if ((sz & 6) == 2)
6367
0
    return false;
6368
0
  else if ((sz & 4) == 4)
6369
0
    return false;
6370
0
  else
6371
0
    {
6372
0
      *undefined_code = UNDEF_SIZE;
6373
0
      return true;
6374
0
    }
6375
0
      }
6376
6377
0
    case MVE_VQRSHRN:
6378
0
    case MVE_VQRSHRUN:
6379
0
      if (arm_decode_field (given, 19, 20) == 0)
6380
0
  {
6381
0
    *undefined_code = UNDEF_SIZE_0;
6382
0
    return true;
6383
0
  }
6384
0
      else
6385
0
  return false;
6386
6387
0
    case MVE_VABS_VEC:
6388
0
  if (arm_decode_field (given, 18, 19) == 3)
6389
0
  {
6390
0
    *undefined_code = UNDEF_SIZE_3;
6391
0
    return true;
6392
0
  }
6393
0
  else
6394
0
    return false;
6395
6396
0
    case MVE_VQNEG:
6397
0
    case MVE_VQABS:
6398
0
    case MVE_VNEG_VEC:
6399
0
    case MVE_VCLS:
6400
0
    case MVE_VCLZ:
6401
0
      if (arm_decode_field (given, 18, 19) == 3)
6402
0
  {
6403
0
    *undefined_code = UNDEF_SIZE_3;
6404
0
    return true;
6405
0
  }
6406
0
      else
6407
0
  return false;
6408
6409
0
    case MVE_VREV16:
6410
0
      if (arm_decode_field (given, 18, 19) == 0)
6411
0
  return false;
6412
0
      else
6413
0
  {
6414
0
    *undefined_code = UNDEF_SIZE_NOT_0;
6415
0
    return true;
6416
0
  }
6417
6418
0
    case MVE_VREV32:
6419
0
      {
6420
0
  unsigned long size = arm_decode_field (given, 18, 19);
6421
0
  if ((size & 2) == 2)
6422
0
    {
6423
0
      *undefined_code = UNDEF_SIZE_2;
6424
0
      return true;
6425
0
    }
6426
0
  else
6427
0
    return false;
6428
0
      }
6429
6430
0
    case MVE_VREV64:
6431
0
      if (arm_decode_field (given, 18, 19) != 3)
6432
0
  return false;
6433
0
      else
6434
0
  {
6435
0
    *undefined_code = UNDEF_SIZE_3;
6436
0
    return true;
6437
0
  }
6438
6439
0
    default:
6440
0
      return false;
6441
0
    }
6442
0
}
6443
6444
/* Return FALSE if GIVEN is not an unpredictable encoding for MATCHED_INSN.
6445
   Otherwise, return TRUE and set UNPREDICTABLE_CODE to give a reason as to
6446
   why this encoding is unpredictable.  */
6447
6448
static bool
6449
is_mve_unpredictable (unsigned long given, enum mve_instructions matched_insn,
6450
          enum mve_unpredictable *unpredictable_code)
6451
0
{
6452
0
  *unpredictable_code = UNPRED_NONE;
6453
6454
0
  switch (matched_insn)
6455
0
    {
6456
0
    case MVE_VCMP_FP_T2:
6457
0
    case MVE_VPT_FP_T2:
6458
0
      if ((arm_decode_field (given, 12, 12) == 0)
6459
0
    && (arm_decode_field (given, 5, 5) == 1))
6460
0
  {
6461
0
    *unpredictable_code = UNPRED_FCA_0_FCB_1;
6462
0
    return true;
6463
0
  }
6464
0
      else
6465
0
  return false;
6466
6467
0
    case MVE_VPT_VEC_T4:
6468
0
    case MVE_VPT_VEC_T5:
6469
0
    case MVE_VPT_VEC_T6:
6470
0
    case MVE_VCMP_VEC_T4:
6471
0
    case MVE_VCMP_VEC_T5:
6472
0
    case MVE_VCMP_VEC_T6:
6473
0
      if (arm_decode_field (given, 0, 3) == 0xd)
6474
0
  {
6475
0
    *unpredictable_code = UNPRED_R13;
6476
0
    return true;
6477
0
  }
6478
0
      else
6479
0
  return false;
6480
6481
0
    case MVE_VDUP:
6482
0
      {
6483
0
  unsigned long gpr = arm_decode_field (given, 12, 15);
6484
0
  if (gpr == 0xd)
6485
0
    {
6486
0
      *unpredictable_code = UNPRED_R13;
6487
0
      return true;
6488
0
    }
6489
0
  else if (gpr == 0xf)
6490
0
    {
6491
0
      *unpredictable_code = UNPRED_R15;
6492
0
      return true;
6493
0
    }
6494
6495
0
  return false;
6496
0
      }
6497
6498
0
    case MVE_VQADD_T2:
6499
0
    case MVE_VQSUB_T2:
6500
0
    case MVE_VMUL_FP_T2:
6501
0
    case MVE_VMUL_VEC_T2:
6502
0
    case MVE_VMLA:
6503
0
    case MVE_VBRSR:
6504
0
    case MVE_VADD_FP_T2:
6505
0
    case MVE_VSUB_FP_T2:
6506
0
    case MVE_VADD_VEC_T2:
6507
0
    case MVE_VSUB_VEC_T2:
6508
0
    case MVE_VQRSHL_T2:
6509
0
    case MVE_VQSHL_T1:
6510
0
    case MVE_VRSHL_T2:
6511
0
    case MVE_VSHL_T2:
6512
0
    case MVE_VSHLC:
6513
0
    case MVE_VQDMLAH:
6514
0
    case MVE_VQRDMLAH:
6515
0
    case MVE_VQDMLASH:
6516
0
    case MVE_VQRDMLASH:
6517
0
    case MVE_VQDMULH_T3:
6518
0
    case MVE_VQRDMULH_T4:
6519
0
    case MVE_VMLAS:
6520
0
    case MVE_VFMA_FP_SCALAR:
6521
0
    case MVE_VFMAS_FP_SCALAR:
6522
0
    case MVE_VHADD_T2:
6523
0
    case MVE_VHSUB_T2:
6524
0
      {
6525
0
  unsigned long gpr = arm_decode_field (given, 0, 3);
6526
0
  if (gpr == 0xd)
6527
0
    {
6528
0
      *unpredictable_code = UNPRED_R13;
6529
0
      return true;
6530
0
    }
6531
0
  else if (gpr == 0xf)
6532
0
    {
6533
0
      *unpredictable_code = UNPRED_R15;
6534
0
      return true;
6535
0
    }
6536
6537
0
  return false;
6538
0
      }
6539
6540
0
    case MVE_VLD2:
6541
0
    case MVE_VST2:
6542
0
      {
6543
0
  unsigned long rn = arm_decode_field (given, 16, 19);
6544
6545
0
  if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
6546
0
    {
6547
0
      *unpredictable_code = UNPRED_R13_AND_WB;
6548
0
      return true;
6549
0
    }
6550
6551
0
  if (rn == 0xf)
6552
0
    {
6553
0
      *unpredictable_code = UNPRED_R15;
6554
0
      return true;
6555
0
    }
6556
6557
0
  if (arm_decode_field_multiple (given, 13, 15, 22, 22) > 6)
6558
0
    {
6559
0
      *unpredictable_code = UNPRED_Q_GT_6;
6560
0
      return true;
6561
0
    }
6562
0
  else
6563
0
    return false;
6564
0
      }
6565
6566
0
    case MVE_VLD4:
6567
0
    case MVE_VST4:
6568
0
      {
6569
0
  unsigned long rn = arm_decode_field (given, 16, 19);
6570
6571
0
  if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
6572
0
    {
6573
0
      *unpredictable_code = UNPRED_R13_AND_WB;
6574
0
      return true;
6575
0
    }
6576
6577
0
  if (rn == 0xf)
6578
0
    {
6579
0
      *unpredictable_code = UNPRED_R15;
6580
0
      return true;
6581
0
    }
6582
6583
0
  if (arm_decode_field_multiple (given, 13, 15, 22, 22) > 4)
6584
0
    {
6585
0
      *unpredictable_code = UNPRED_Q_GT_4;
6586
0
      return true;
6587
0
    }
6588
0
  else
6589
0
    return false;
6590
0
      }
6591
6592
0
    case MVE_VLDRB_T5:
6593
0
    case MVE_VLDRH_T6:
6594
0
    case MVE_VLDRW_T7:
6595
0
    case MVE_VSTRB_T5:
6596
0
    case MVE_VSTRH_T6:
6597
0
    case MVE_VSTRW_T7:
6598
0
      {
6599
0
  unsigned long rn = arm_decode_field (given, 16, 19);
6600
6601
0
  if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
6602
0
    {
6603
0
      *unpredictable_code = UNPRED_R13_AND_WB;
6604
0
      return true;
6605
0
    }
6606
0
  else if (rn == 0xf)
6607
0
    {
6608
0
      *unpredictable_code = UNPRED_R15;
6609
0
      return true;
6610
0
    }
6611
0
  else
6612
0
    return false;
6613
0
      }
6614
6615
0
    case MVE_VLDRB_GATHER_T1:
6616
0
      if (arm_decode_field (given, 0, 0) == 1)
6617
0
  {
6618
0
    *unpredictable_code = UNPRED_OS;
6619
0
    return true;
6620
0
  }
6621
6622
      /*  fall through.  */
6623
      /* To handle common code with T2-T4 variants.  */
6624
0
    case MVE_VLDRH_GATHER_T2:
6625
0
    case MVE_VLDRW_GATHER_T3:
6626
0
    case MVE_VLDRD_GATHER_T4:
6627
0
      {
6628
0
  unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6629
0
  unsigned long qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6630
6631
0
  if (qd == qm)
6632
0
    {
6633
0
      *unpredictable_code = UNPRED_Q_REGS_EQUAL;
6634
0
      return true;
6635
0
    }
6636
6637
0
  if (arm_decode_field (given, 16, 19) == 0xf)
6638
0
    {
6639
0
      *unpredictable_code = UNPRED_R15;
6640
0
      return true;
6641
0
    }
6642
6643
0
  return false;
6644
0
      }
6645
6646
0
    case MVE_VLDRW_GATHER_T5:
6647
0
    case MVE_VLDRD_GATHER_T6:
6648
0
      {
6649
0
  unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6650
0
  unsigned long qm = arm_decode_field_multiple (given, 17, 19, 7, 7);
6651
6652
0
  if (qd == qm)
6653
0
    {
6654
0
      *unpredictable_code = UNPRED_Q_REGS_EQUAL;
6655
0
      return true;
6656
0
    }
6657
0
  else
6658
0
    return false;
6659
0
      }
6660
6661
0
    case MVE_VSTRB_SCATTER_T1:
6662
0
      if (arm_decode_field (given, 16, 19) == 0xf)
6663
0
  {
6664
0
    *unpredictable_code = UNPRED_R15;
6665
0
    return true;
6666
0
  }
6667
0
      else if (arm_decode_field (given, 0, 0) == 1)
6668
0
  {
6669
0
    *unpredictable_code = UNPRED_OS;
6670
0
    return true;
6671
0
  }
6672
0
      else
6673
0
  return false;
6674
6675
0
    case MVE_VSTRH_SCATTER_T2:
6676
0
    case MVE_VSTRW_SCATTER_T3:
6677
0
    case MVE_VSTRD_SCATTER_T4:
6678
0
      if (arm_decode_field (given, 16, 19) == 0xf)
6679
0
  {
6680
0
    *unpredictable_code = UNPRED_R15;
6681
0
    return true;
6682
0
  }
6683
0
      else
6684
0
  return false;
6685
6686
0
    case MVE_VMOV2_VEC_LANE_TO_GP:
6687
0
    case MVE_VMOV2_GP_TO_VEC_LANE:
6688
0
    case MVE_VCVT_BETWEEN_FP_INT:
6689
0
    case MVE_VCVT_FROM_FP_TO_INT:
6690
0
      {
6691
0
  unsigned long rt = arm_decode_field (given, 0, 3);
6692
0
  unsigned long rt2 = arm_decode_field (given, 16, 19);
6693
6694
0
  if ((rt == 0xd) || (rt2 == 0xd))
6695
0
    {
6696
0
      *unpredictable_code = UNPRED_R13;
6697
0
      return true;
6698
0
    }
6699
0
  else if ((rt == 0xf) || (rt2 == 0xf))
6700
0
    {
6701
0
      *unpredictable_code = UNPRED_R15;
6702
0
      return true;
6703
0
    }
6704
0
  else if (rt == rt2 && matched_insn != MVE_VMOV2_GP_TO_VEC_LANE)
6705
0
    {
6706
0
      *unpredictable_code = UNPRED_GP_REGS_EQUAL;
6707
0
      return true;
6708
0
    }
6709
6710
0
  return false;
6711
0
      }
6712
6713
0
    case MVE_VMAXV:
6714
0
    case MVE_VMAXAV:
6715
0
    case MVE_VMAXNMV_FP:
6716
0
    case MVE_VMAXNMAV_FP:
6717
0
    case MVE_VMINNMV_FP:
6718
0
    case MVE_VMINNMAV_FP:
6719
0
    case MVE_VMINV:
6720
0
    case MVE_VMINAV:
6721
0
    case MVE_VABAV:
6722
0
    case MVE_VMOV_HFP_TO_GP:
6723
0
    case MVE_VMOV_GP_TO_VEC_LANE:
6724
0
    case MVE_VMOV_VEC_LANE_TO_GP:
6725
0
      {
6726
0
  unsigned long rda = arm_decode_field (given, 12, 15);
6727
0
  if (rda == 0xd)
6728
0
    {
6729
0
      *unpredictable_code = UNPRED_R13;
6730
0
      return true;
6731
0
    }
6732
0
  else if (rda == 0xf)
6733
0
    {
6734
0
      *unpredictable_code = UNPRED_R15;
6735
0
      return true;
6736
0
    }
6737
6738
0
  return false;
6739
0
      }
6740
6741
0
    case MVE_VMULL_INT:
6742
0
      {
6743
0
  unsigned long Qd;
6744
0
  unsigned long Qm;
6745
0
  unsigned long Qn;
6746
6747
0
  if (arm_decode_field (given, 20, 21) == 2)
6748
0
    {
6749
0
      Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6750
0
      Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6751
0
      Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6752
6753
0
      if ((Qd == Qn) || (Qd == Qm))
6754
0
        {
6755
0
    *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_2;
6756
0
    return true;
6757
0
        }
6758
0
      else
6759
0
        return false;
6760
0
    }
6761
0
  else
6762
0
    return false;
6763
0
      }
6764
6765
0
    case MVE_VCMUL_FP:
6766
0
    case MVE_VQDMULL_T1:
6767
0
      {
6768
0
  unsigned long Qd;
6769
0
  unsigned long Qm;
6770
0
  unsigned long Qn;
6771
6772
0
  if (arm_decode_field (given, 28, 28) == 1)
6773
0
    {
6774
0
      Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6775
0
      Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6776
0
      Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6777
6778
0
      if ((Qd == Qn) || (Qd == Qm))
6779
0
        {
6780
0
    *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
6781
0
    return true;
6782
0
        }
6783
0
      else
6784
0
        return false;
6785
0
    }
6786
0
  else
6787
0
    return false;
6788
0
      }
6789
6790
0
    case MVE_VQDMULL_T2:
6791
0
      {
6792
0
  unsigned long gpr = arm_decode_field (given, 0, 3);
6793
0
  if (gpr == 0xd)
6794
0
    {
6795
0
      *unpredictable_code = UNPRED_R13;
6796
0
      return true;
6797
0
    }
6798
0
  else if (gpr == 0xf)
6799
0
    {
6800
0
      *unpredictable_code = UNPRED_R15;
6801
0
      return true;
6802
0
    }
6803
6804
0
  if (arm_decode_field (given, 28, 28) == 1)
6805
0
    {
6806
0
      unsigned long Qd
6807
0
        = arm_decode_field_multiple (given, 13, 15, 22, 22);
6808
0
      unsigned long Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6809
6810
0
      if (Qd == Qn)
6811
0
        {
6812
0
    *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
6813
0
    return true;
6814
0
        }
6815
0
      else
6816
0
        return false;
6817
0
    }
6818
6819
0
  return false;
6820
0
      }
6821
6822
0
    case MVE_VMLSLDAV:
6823
0
    case MVE_VRMLSLDAVH:
6824
0
    case MVE_VMLALDAV:
6825
0
    case MVE_VADDLV:
6826
0
      if (arm_decode_field (given, 20, 22) == 6)
6827
0
  {
6828
0
    *unpredictable_code = UNPRED_R13;
6829
0
    return true;
6830
0
  }
6831
0
      else
6832
0
  return false;
6833
6834
0
    case MVE_VDWDUP:
6835
0
    case MVE_VIWDUP:
6836
0
      if (arm_decode_field (given, 1, 3) == 6)
6837
0
  {
6838
0
    *unpredictable_code = UNPRED_R13;
6839
0
    return true;
6840
0
  }
6841
0
      else
6842
0
  return false;
6843
6844
0
    case MVE_VCADD_VEC:
6845
0
    case MVE_VHCADD:
6846
0
      {
6847
0
  unsigned long Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6848
0
  unsigned long Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6849
0
  if ((Qd == Qm) && arm_decode_field (given, 20, 21) == 2)
6850
0
    {
6851
0
      *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_2;
6852
0
      return true;
6853
0
    }
6854
0
  else
6855
0
    return false;
6856
0
      }
6857
6858
0
    case MVE_VCADD_FP:
6859
0
      {
6860
0
  unsigned long Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6861
0
  unsigned long Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6862
0
  if ((Qd == Qm) && arm_decode_field (given, 20, 20) == 1)
6863
0
    {
6864
0
      *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
6865
0
      return true;
6866
0
    }
6867
0
  else
6868
0
    return false;
6869
0
      }
6870
6871
0
    case MVE_VCMLA_FP:
6872
0
      {
6873
0
  unsigned long Qda;
6874
0
  unsigned long Qm;
6875
0
  unsigned long Qn;
6876
6877
0
  if (arm_decode_field (given, 20, 20) == 1)
6878
0
    {
6879
0
      Qda = arm_decode_field_multiple (given, 13, 15, 22, 22);
6880
0
      Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6881
0
      Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6882
6883
0
      if ((Qda == Qn) || (Qda == Qm))
6884
0
        {
6885
0
    *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
6886
0
    return true;
6887
0
        }
6888
0
      else
6889
0
        return false;
6890
0
    }
6891
0
  else
6892
0
    return false;
6893
6894
0
      }
6895
6896
0
    case MVE_VCTP:
6897
0
      if (arm_decode_field (given, 16, 19) == 0xd)
6898
0
  {
6899
0
    *unpredictable_code = UNPRED_R13;
6900
0
    return true;
6901
0
  }
6902
0
      else
6903
0
  return false;
6904
6905
0
    case MVE_VREV64:
6906
0
      {
6907
0
  unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6908
0
  unsigned long qm = arm_decode_field_multiple (given, 1, 3, 6, 6);
6909
6910
0
  if (qd == qm)
6911
0
    {
6912
0
      *unpredictable_code = UNPRED_Q_REGS_EQUAL;
6913
0
      return true;
6914
0
    }
6915
0
  else
6916
0
    return false;
6917
0
      }
6918
6919
0
    case MVE_LSLL:
6920
0
    case MVE_LSLLI:
6921
0
    case MVE_LSRL:
6922
0
    case MVE_ASRL:
6923
0
    case MVE_ASRLI:
6924
0
    case MVE_UQSHLL:
6925
0
    case MVE_UQRSHLL:
6926
0
    case MVE_URSHRL:
6927
0
    case MVE_SRSHRL:
6928
0
    case MVE_SQSHLL:
6929
0
    case MVE_SQRSHRL:
6930
0
      {
6931
0
  unsigned long gpr = arm_decode_field (given, 9, 11);
6932
0
  gpr = ((gpr << 1) | 1);
6933
0
  if (gpr == 0xd)
6934
0
    {
6935
0
      *unpredictable_code = UNPRED_R13;
6936
0
      return true;
6937
0
    }
6938
0
  else if (gpr == 0xf)
6939
0
    {
6940
0
      *unpredictable_code = UNPRED_R15;
6941
0
      return true;
6942
0
    }
6943
6944
0
  return false;
6945
0
      }
6946
6947
0
    default:
6948
0
      return false;
6949
0
    }
6950
0
}
6951
6952
static void
6953
print_mve_vmov_index (struct disassemble_info *info, unsigned long given)
6954
0
{
6955
0
  unsigned long op1 = arm_decode_field (given, 21, 22);
6956
0
  unsigned long op2 = arm_decode_field (given, 5, 6);
6957
0
  unsigned long h = arm_decode_field (given, 16, 16);
6958
0
  unsigned long index_operand, esize, targetBeat, idx;
6959
0
  void *stream = info->stream;
6960
0
  fprintf_styled_ftype func = info->fprintf_styled_func;
6961
6962
0
  if ((op1 & 0x2) == 0x2)
6963
0
    {
6964
0
      index_operand = op2;
6965
0
      esize = 8;
6966
0
    }
6967
0
  else if (((op1 & 0x2) == 0x0) && ((op2 & 0x1) == 0x1))
6968
0
    {
6969
0
      index_operand = op2  >> 1;
6970
0
      esize = 16;
6971
0
    }
6972
0
  else if (((op1 & 0x2) == 0) && ((op2 & 0x3) == 0))
6973
0
    {
6974
0
      index_operand = 0;
6975
0
      esize = 32;
6976
0
    }
6977
0
  else
6978
0
    {
6979
0
      func (stream, dis_style_text, "<undefined index>");
6980
0
      return;
6981
0
    }
6982
6983
0
  targetBeat =  (op1 & 0x1) | (h << 1);
6984
0
  idx = index_operand + targetBeat * (32/esize);
6985
6986
0
  func (stream, dis_style_immediate, "%lu", idx);
6987
0
}
6988
6989
/* Print neon and mve 8-bit immediate that can be a 8, 16, 32, or 64-bits
6990
   in length and integer of floating-point type.  */
6991
static void
6992
print_simd_imm8 (struct disassemble_info *info, unsigned long given,
6993
     unsigned int ibit_loc, const struct mopcode32 *insn)
6994
0
{
6995
0
  int bits = 0;
6996
0
  int cmode = (given >> 8) & 0xf;
6997
0
  int op = (given >> 5) & 0x1;
6998
0
  unsigned long value = 0, hival = 0;
6999
0
  unsigned shift;
7000
0
  int size = 0;
7001
0
  int isfloat = 0;
7002
0
  void *stream = info->stream;
7003
0
  fprintf_styled_ftype func = info->fprintf_styled_func;
7004
7005
  /* On Neon the 'i' bit is at bit 24, on mve it is
7006
     at bit 28.  */
7007
0
  bits |= ((given >> ibit_loc) & 1) << 7;
7008
0
  bits |= ((given >> 16) & 7) << 4;
7009
0
  bits |= ((given >> 0) & 15) << 0;
7010
7011
0
  if (cmode < 8)
7012
0
    {
7013
0
      shift = (cmode >> 1) & 3;
7014
0
      value = (unsigned long) bits << (8 * shift);
7015
0
      size = 32;
7016
0
    }
7017
0
  else if (cmode < 12)
7018
0
    {
7019
0
      shift = (cmode >> 1) & 1;
7020
0
      value = (unsigned long) bits << (8 * shift);
7021
0
      size = 16;
7022
0
    }
7023
0
  else if (cmode < 14)
7024
0
    {
7025
0
      shift = (cmode & 1) + 1;
7026
0
      value = (unsigned long) bits << (8 * shift);
7027
0
      value |= (1ul << (8 * shift)) - 1;
7028
0
      size = 32;
7029
0
    }
7030
0
  else if (cmode == 14)
7031
0
    {
7032
0
      if (op)
7033
0
  {
7034
    /* Bit replication into bytes.  */
7035
0
    int ix;
7036
0
    unsigned long mask;
7037
7038
0
    value = 0;
7039
0
    hival = 0;
7040
0
    for (ix = 7; ix >= 0; ix--)
7041
0
      {
7042
0
        mask = ((bits >> ix) & 1) ? 0xff : 0;
7043
0
        if (ix <= 3)
7044
0
    value = (value << 8) | mask;
7045
0
        else
7046
0
    hival = (hival << 8) | mask;
7047
0
      }
7048
0
    size = 64;
7049
0
  }
7050
0
      else
7051
0
  {
7052
    /* Byte replication.  */
7053
0
    value = (unsigned long) bits;
7054
0
    size = 8;
7055
0
  }
7056
0
    }
7057
0
  else if (!op)
7058
0
    {
7059
      /* Floating point encoding.  */
7060
0
      int tmp;
7061
7062
0
      value = (unsigned long)  (bits & 0x7f) << 19;
7063
0
      value |= (unsigned long) (bits & 0x80) << 24;
7064
0
      tmp = bits & 0x40 ? 0x3c : 0x40;
7065
0
      value |= (unsigned long) tmp << 24;
7066
0
      size = 32;
7067
0
      isfloat = 1;
7068
0
    }
7069
0
  else
7070
0
    {
7071
0
      func (stream, dis_style_text, "<illegal constant %.8x:%x:%x>",
7072
0
      bits, cmode, op);
7073
0
      size = 32;
7074
0
      return;
7075
0
    }
7076
7077
  /* printU determines whether the immediate value should be printed as
7078
     unsigned.  */
7079
0
  unsigned printU = 0;
7080
0
  switch (insn->mve_op)
7081
0
    {
7082
0
    default:
7083
0
      break;
7084
    /* We want this for instructions that don't have a 'signed' type.  */
7085
0
    case MVE_VBIC_IMM:
7086
0
    case MVE_VORR_IMM:
7087
0
    case MVE_VMVN_IMM:
7088
0
    case MVE_VMOV_IMM_TO_VEC:
7089
0
      printU = 1;
7090
0
      break;
7091
0
    }
7092
0
  switch (size)
7093
0
    {
7094
0
    case 8:
7095
0
      func (stream, dis_style_immediate, "#%ld", value);
7096
0
      func (stream, dis_style_comment_start, "\t@ 0x%.2lx", value);
7097
0
      break;
7098
7099
0
    case 16:
7100
0
      func (stream, dis_style_immediate, printU ? "#%lu" : "#%ld", value);
7101
0
      func (stream, dis_style_comment_start, "\t@ 0x%.4lx", value);
7102
0
      break;
7103
7104
0
    case 32:
7105
0
      if (isfloat)
7106
0
  {
7107
0
    unsigned char valbytes[4];
7108
0
    double fvalue;
7109
7110
    /* Do this a byte at a time so we don't have to
7111
       worry about the host's endianness.  */
7112
0
    valbytes[0] = value & 0xff;
7113
0
    valbytes[1] = (value >> 8) & 0xff;
7114
0
    valbytes[2] = (value >> 16) & 0xff;
7115
0
    valbytes[3] = (value >> 24) & 0xff;
7116
7117
0
    floatformat_to_double
7118
0
      (& floatformat_ieee_single_little, valbytes,
7119
0
       & fvalue);
7120
7121
0
    func (stream, dis_style_immediate, "#%.7g", fvalue);
7122
0
    func (stream, dis_style_comment_start, "\t@ 0x%.8lx", value);
7123
0
  }
7124
0
      else
7125
0
  {
7126
0
    func (stream, dis_style_immediate,
7127
0
    printU ? "#%lu" : "#%ld",
7128
0
    (long) (((value & 0x80000000L) != 0)
7129
0
      && !printU
7130
0
      ? value | ~0xffffffffL : value));
7131
0
    func (stream, dis_style_comment_start, "\t@ 0x%.8lx", value);
7132
0
  }
7133
0
      break;
7134
7135
0
    case 64:
7136
0
      func (stream, dis_style_immediate, "#0x%.8lx%.8lx", hival, value);
7137
0
      break;
7138
7139
0
    default:
7140
0
      abort ();
7141
0
    }
7142
7143
0
}
7144
7145
static void
7146
print_mve_undefined (struct disassemble_info *info,
7147
         enum mve_undefined undefined_code)
7148
0
{
7149
0
  void *stream = info->stream;
7150
0
  fprintf_styled_ftype func = info->fprintf_styled_func;
7151
  /* Initialize REASON to avoid compiler warning about uninitialized
7152
     usage, though such usage should be impossible.  */
7153
0
  const char *reason = "??";
7154
7155
0
  switch (undefined_code)
7156
0
    {
7157
0
    case UNDEF_SIZE:
7158
0
      reason = "illegal size";
7159
0
      break;
7160
7161
0
    case UNDEF_SIZE_0:
7162
0
      reason = "size equals zero";
7163
0
      break;
7164
7165
0
    case UNDEF_SIZE_2:
7166
0
      reason = "size equals two";
7167
0
      break;
7168
7169
0
    case UNDEF_SIZE_3:
7170
0
      reason = "size equals three";
7171
0
      break;
7172
7173
0
    case UNDEF_SIZE_LE_1:
7174
0
      reason = "size <= 1";
7175
0
      break;
7176
7177
0
    case UNDEF_SIZE_NOT_0:
7178
0
      reason = "size not equal to 0";
7179
0
      break;
7180
7181
0
    case UNDEF_SIZE_NOT_2:
7182
0
      reason = "size not equal to 2";
7183
0
      break;
7184
7185
0
    case UNDEF_SIZE_NOT_3:
7186
0
      reason = "size not equal to 3";
7187
0
      break;
7188
7189
0
    case UNDEF_NOT_UNS_SIZE_0:
7190
0
      reason = "not unsigned and size = zero";
7191
0
      break;
7192
7193
0
    case UNDEF_NOT_UNS_SIZE_1:
7194
0
      reason = "not unsigned and size = one";
7195
0
      break;
7196
7197
0
    case UNDEF_NOT_UNSIGNED:
7198
0
      reason = "not unsigned";
7199
0
      break;
7200
7201
0
    case UNDEF_VCVT_IMM6:
7202
0
      reason = "invalid imm6";
7203
0
      break;
7204
7205
0
    case UNDEF_VCVT_FSI_IMM6:
7206
0
      reason = "fsi = 0 and invalid imm6";
7207
0
      break;
7208
7209
0
    case UNDEF_BAD_OP1_OP2:
7210
0
      reason = "bad size with op2 = 2 and op1 = 0 or 1";
7211
0
      break;
7212
7213
0
    case UNDEF_BAD_U_OP1_OP2:
7214
0
      reason = "unsigned with op2 = 0 and op1 = 0 or 1";
7215
0
      break;
7216
7217
0
    case UNDEF_OP_0_BAD_CMODE:
7218
0
      reason = "op field equal 0 and bad cmode";
7219
0
      break;
7220
7221
0
    case UNDEF_XCHG_UNS:
7222
0
      reason = "exchange and unsigned together";
7223
0
      break;
7224
7225
0
    case UNDEF_NONE:
7226
0
      reason = "";
7227
0
      break;
7228
0
    }
7229
7230
0
  func (stream, dis_style_text, "\t\tundefined instruction: %s", reason);
7231
0
}
7232
7233
static void
7234
print_mve_unpredictable (struct disassemble_info *info,
7235
       enum mve_unpredictable unpredict_code)
7236
0
{
7237
0
  void *stream = info->stream;
7238
0
  fprintf_styled_ftype func = info->fprintf_styled_func;
7239
  /* Initialize REASON to avoid compiler warning about uninitialized
7240
     usage, though such usage should be impossible.  */
7241
0
  const char *reason = "??";
7242
7243
0
  switch (unpredict_code)
7244
0
    {
7245
0
    case UNPRED_IT_BLOCK:
7246
0
      reason = "mve instruction in it block";
7247
0
      break;
7248
7249
0
    case UNPRED_FCA_0_FCB_1:
7250
0
      reason = "condition bits, fca = 0 and fcb = 1";
7251
0
      break;
7252
7253
0
    case UNPRED_R13:
7254
0
      reason = "use of r13 (sp)";
7255
0
      break;
7256
7257
0
    case UNPRED_R15:
7258
0
      reason = "use of r15 (pc)";
7259
0
      break;
7260
7261
0
    case UNPRED_Q_GT_4:
7262
0
      reason = "start register block > r4";
7263
0
      break;
7264
7265
0
    case UNPRED_Q_GT_6:
7266
0
      reason = "start register block > r6";
7267
0
      break;
7268
7269
0
    case UNPRED_R13_AND_WB:
7270
0
      reason = "use of r13 and write back";
7271
0
      break;
7272
7273
0
    case UNPRED_Q_REGS_EQUAL:
7274
0
      reason = "same vector register used for destination and other operand";
7275
0
      break;
7276
7277
0
    case UNPRED_OS:
7278
0
      reason = "use of offset scaled";
7279
0
      break;
7280
7281
0
    case UNPRED_GP_REGS_EQUAL:
7282
0
      reason = "same general-purpose register used for both operands";
7283
0
      break;
7284
7285
0
    case UNPRED_Q_REGS_EQ_AND_SIZE_1:
7286
0
      reason = "use of identical q registers and size = 1";
7287
0
      break;
7288
7289
0
    case UNPRED_Q_REGS_EQ_AND_SIZE_2:
7290
0
      reason = "use of identical q registers and size = 1";
7291
0
      break;
7292
7293
0
    case UNPRED_NONE:
7294
0
      reason = "";
7295
0
      break;
7296
0
    }
7297
7298
0
  func (stream, dis_style_comment_start, "%s: %s",
7299
0
  UNPREDICTABLE_INSTRUCTION, reason);
7300
0
}
7301
7302
/* Print register block operand for mve vld2/vld4/vst2/vld4.  */
7303
7304
static void
7305
print_mve_register_blocks (struct disassemble_info *info,
7306
         unsigned long given,
7307
         enum mve_instructions matched_insn)
7308
0
{
7309
0
  void *stream = info->stream;
7310
0
  fprintf_styled_ftype func = info->fprintf_styled_func;
7311
7312
0
  unsigned long q_reg_start = arm_decode_field_multiple (given,
7313
0
               13, 15,
7314
0
               22, 22);
7315
0
  switch (matched_insn)
7316
0
    {
7317
0
    case MVE_VLD2:
7318
0
    case MVE_VST2:
7319
0
      if (q_reg_start <= 6)
7320
0
  {
7321
0
    func (stream, dis_style_text, "{");
7322
0
    func (stream, dis_style_register, "q%ld", q_reg_start);
7323
0
    func (stream, dis_style_text, ", ");
7324
0
    func (stream, dis_style_register, "q%ld", q_reg_start + 1);
7325
0
    func (stream, dis_style_text, "}");
7326
0
  }
7327
0
      else
7328
0
  func (stream, dis_style_text, "<illegal reg q%ld>", q_reg_start);
7329
0
      break;
7330
7331
0
    case MVE_VLD4:
7332
0
    case MVE_VST4:
7333
0
      if (q_reg_start <= 4)
7334
0
  {
7335
0
    func (stream, dis_style_text, "{");
7336
0
    func (stream, dis_style_register, "q%ld", q_reg_start);
7337
0
    func (stream, dis_style_text, ", ");
7338
0
    func (stream, dis_style_register, "q%ld", q_reg_start + 1);
7339
0
    func (stream, dis_style_text, ", ");
7340
0
    func (stream, dis_style_register, "q%ld", q_reg_start + 2);
7341
0
    func (stream, dis_style_text, ", ");
7342
0
    func (stream, dis_style_register, "q%ld", q_reg_start + 3);
7343
0
    func (stream, dis_style_text, "}");
7344
0
  }
7345
0
      else
7346
0
  func (stream, dis_style_text, "<illegal reg q%ld>", q_reg_start);
7347
0
      break;
7348
7349
0
    default:
7350
0
      break;
7351
0
    }
7352
0
}
7353
7354
static void
7355
print_mve_rounding_mode (struct disassemble_info *info,
7356
       unsigned long given,
7357
       enum mve_instructions matched_insn)
7358
0
{
7359
0
  void *stream = info->stream;
7360
0
  fprintf_styled_ftype func = info->fprintf_styled_func;
7361
7362
0
  switch (matched_insn)
7363
0
    {
7364
0
    case MVE_VCVT_FROM_FP_TO_INT:
7365
0
      {
7366
0
  switch (arm_decode_field (given, 8, 9))
7367
0
    {
7368
0
    case 0:
7369
0
      func (stream, dis_style_mnemonic, "a");
7370
0
      break;
7371
7372
0
    case 1:
7373
0
      func (stream, dis_style_mnemonic, "n");
7374
0
      break;
7375
7376
0
    case 2:
7377
0
      func (stream, dis_style_mnemonic, "p");
7378
0
      break;
7379
7380
0
    case 3:
7381
0
      func (stream, dis_style_mnemonic, "m");
7382
0
      break;
7383
7384
0
    default:
7385
0
      break;
7386
0
    }
7387
0
      }
7388
0
      break;
7389
7390
0
    case MVE_VRINT_FP:
7391
0
      {
7392
0
  switch (arm_decode_field (given, 7, 9))
7393
0
    {
7394
0
    case 0:
7395
0
      func (stream, dis_style_mnemonic, "n");
7396
0
      break;
7397
7398
0
    case 1:
7399
0
      func (stream, dis_style_mnemonic, "x");
7400
0
      break;
7401
7402
0
    case 2:
7403
0
      func (stream, dis_style_mnemonic, "a");
7404
0
      break;
7405
7406
0
    case 3:
7407
0
      func (stream, dis_style_mnemonic, "z");
7408
0
      break;
7409
7410
0
    case 5:
7411
0
      func (stream, dis_style_mnemonic, "m");
7412
0
      break;
7413
7414
0
    case 7:
7415
0
      func (stream, dis_style_mnemonic, "p");
7416
7417
0
    case 4:
7418
0
    case 6:
7419
0
    default:
7420
0
      break;
7421
0
    }
7422
0
      }
7423
0
      break;
7424
7425
0
    default:
7426
0
      break;
7427
0
    }
7428
0
}
7429
7430
static void
7431
print_mve_vcvt_size (struct disassemble_info *info,
7432
         unsigned long given,
7433
         enum mve_instructions matched_insn)
7434
0
{
7435
0
  unsigned long mode = 0;
7436
0
  void *stream = info->stream;
7437
0
  fprintf_styled_ftype func = info->fprintf_styled_func;
7438
7439
0
  switch (matched_insn)
7440
0
    {
7441
0
    case MVE_VCVT_FP_FIX_VEC:
7442
0
      {
7443
0
  mode = (((given & 0x200) >> 7)
7444
0
    | ((given & 0x10000000) >> 27)
7445
0
    | ((given & 0x100) >> 8));
7446
7447
0
  switch (mode)
7448
0
    {
7449
0
    case 0:
7450
0
      func (stream, dis_style_mnemonic, "f16.s16");
7451
0
      break;
7452
7453
0
    case 1:
7454
0
      func (stream, dis_style_mnemonic, "s16.f16");
7455
0
      break;
7456
7457
0
    case 2:
7458
0
      func (stream, dis_style_mnemonic, "f16.u16");
7459
0
      break;
7460
7461
0
    case 3:
7462
0
      func (stream, dis_style_mnemonic, "u16.f16");
7463
0
      break;
7464
7465
0
    case 4:
7466
0
      func (stream, dis_style_mnemonic, "f32.s32");
7467
0
      break;
7468
7469
0
    case 5:
7470
0
      func (stream, dis_style_mnemonic, "s32.f32");
7471
0
      break;
7472
7473
0
    case 6:
7474
0
      func (stream, dis_style_mnemonic, "f32.u32");
7475
0
      break;
7476
7477
0
    case 7:
7478
0
      func (stream, dis_style_mnemonic, "u32.f32");
7479
0
      break;
7480
7481
0
    default:
7482
0
      break;
7483
0
    }
7484
0
  break;
7485
0
      }
7486
0
    case MVE_VCVT_BETWEEN_FP_INT:
7487
0
      {
7488
0
  unsigned long size = arm_decode_field (given, 18, 19);
7489
0
  unsigned long op = arm_decode_field (given, 7, 8);
7490
7491
0
  if (size == 1)
7492
0
    {
7493
0
      switch (op)
7494
0
        {
7495
0
        case 0:
7496
0
    func (stream, dis_style_mnemonic, "f16.s16");
7497
0
    break;
7498
7499
0
        case 1:
7500
0
    func (stream, dis_style_mnemonic, "f16.u16");
7501
0
    break;
7502
7503
0
        case 2:
7504
0
    func (stream, dis_style_mnemonic, "s16.f16");
7505
0
    break;
7506
7507
0
        case 3:
7508
0
    func (stream, dis_style_mnemonic, "u16.f16");
7509
0
    break;
7510
7511
0
        default:
7512
0
    break;
7513
0
        }
7514
0
    }
7515
0
  else if (size == 2)
7516
0
    {
7517
0
      switch (op)
7518
0
        {
7519
0
        case 0:
7520
0
    func (stream, dis_style_mnemonic, "f32.s32");
7521
0
    break;
7522
7523
0
        case 1:
7524
0
    func (stream, dis_style_mnemonic, "f32.u32");
7525
0
    break;
7526
7527
0
        case 2:
7528
0
    func (stream, dis_style_mnemonic, "s32.f32");
7529
0
    break;
7530
7531
0
        case 3:
7532
0
    func (stream, dis_style_mnemonic, "u32.f32");
7533
0
    break;
7534
0
        }
7535
0
    }
7536
0
      }
7537
0
      break;
7538
7539
0
    case MVE_VCVT_FP_HALF_FP:
7540
0
      {
7541
0
  unsigned long op = arm_decode_field (given, 28, 28);
7542
0
  if (op == 0)
7543
0
    func (stream, dis_style_mnemonic, "f16.f32");
7544
0
  else if (op == 1)
7545
0
    func (stream, dis_style_mnemonic, "f32.f16");
7546
0
      }
7547
0
      break;
7548
7549
0
    case MVE_VCVT_FROM_FP_TO_INT:
7550
0
      {
7551
0
  unsigned long size = arm_decode_field_multiple (given, 7, 7, 18, 19);
7552
7553
0
  switch (size)
7554
0
    {
7555
0
    case 2:
7556
0
      func (stream, dis_style_mnemonic, "s16.f16");
7557
0
      break;
7558
7559
0
    case 3:
7560
0
      func (stream, dis_style_mnemonic, "u16.f16");
7561
0
      break;
7562
7563
0
    case 4:
7564
0
      func (stream, dis_style_mnemonic, "s32.f32");
7565
0
      break;
7566
7567
0
    case 5:
7568
0
      func (stream, dis_style_mnemonic, "u32.f32");
7569
0
      break;
7570
7571
0
    default:
7572
0
      break;
7573
0
    }
7574
0
      }
7575
0
      break;
7576
7577
0
    default:
7578
0
      break;
7579
0
    }
7580
0
}
7581
7582
static void
7583
print_mve_rotate (struct disassemble_info *info, unsigned long rot,
7584
      unsigned long rot_width)
7585
0
{
7586
0
  void *stream = info->stream;
7587
0
  fprintf_styled_ftype func = info->fprintf_styled_func;
7588
7589
0
  if (rot_width == 1)
7590
0
    {
7591
0
      switch (rot)
7592
0
  {
7593
0
  case 0:
7594
0
    func (stream, dis_style_immediate, "90");
7595
0
    break;
7596
0
  case 1:
7597
0
    func (stream, dis_style_immediate, "270");
7598
0
    break;
7599
0
  default:
7600
0
    break;
7601
0
  }
7602
0
    }
7603
0
  else if (rot_width == 2)
7604
0
    {
7605
0
      switch (rot)
7606
0
  {
7607
0
  case 0:
7608
0
    func (stream, dis_style_immediate, "0");
7609
0
    break;
7610
0
  case 1:
7611
0
    func (stream, dis_style_immediate, "90");
7612
0
    break;
7613
0
  case 2:
7614
0
    func (stream, dis_style_immediate, "180");
7615
0
    break;
7616
0
  case 3:
7617
0
    func (stream, dis_style_immediate, "270");
7618
0
    break;
7619
0
  default:
7620
0
    break;
7621
0
  }
7622
0
    }
7623
0
}
7624
7625
static void
7626
print_instruction_predicate (struct disassemble_info *info)
7627
0
{
7628
0
  void *stream = info->stream;
7629
0
  fprintf_styled_ftype func = info->fprintf_styled_func;
7630
7631
0
  if (vpt_block_state.next_pred_state == PRED_THEN)
7632
0
    func (stream, dis_style_mnemonic, "t");
7633
0
  else if (vpt_block_state.next_pred_state == PRED_ELSE)
7634
0
    func (stream, dis_style_mnemonic, "e");
7635
0
}
7636
7637
static void
7638
print_mve_size (struct disassemble_info *info,
7639
    unsigned long size,
7640
    enum mve_instructions matched_insn)
7641
0
{
7642
0
  void *stream = info->stream;
7643
0
  fprintf_styled_ftype func = info->fprintf_styled_func;
7644
7645
0
  switch (matched_insn)
7646
0
    {
7647
0
    case MVE_VABAV:
7648
0
    case MVE_VABD_VEC:
7649
0
    case MVE_VABS_FP:
7650
0
    case MVE_VABS_VEC:
7651
0
    case MVE_VADD_VEC_T1:
7652
0
    case MVE_VADD_VEC_T2:
7653
0
    case MVE_VADDV:
7654
0
    case MVE_VBRSR:
7655
0
    case MVE_VCADD_VEC:
7656
0
    case MVE_VCLS:
7657
0
    case MVE_VCLZ:
7658
0
    case MVE_VCMP_VEC_T1:
7659
0
    case MVE_VCMP_VEC_T2:
7660
0
    case MVE_VCMP_VEC_T3:
7661
0
    case MVE_VCMP_VEC_T4:
7662
0
    case MVE_VCMP_VEC_T5:
7663
0
    case MVE_VCMP_VEC_T6:
7664
0
    case MVE_VCTP:
7665
0
    case MVE_VDDUP:
7666
0
    case MVE_VDWDUP:
7667
0
    case MVE_VHADD_T1:
7668
0
    case MVE_VHADD_T2:
7669
0
    case MVE_VHCADD:
7670
0
    case MVE_VHSUB_T1:
7671
0
    case MVE_VHSUB_T2:
7672
0
    case MVE_VIDUP:
7673
0
    case MVE_VIWDUP:
7674
0
    case MVE_VLD2:
7675
0
    case MVE_VLD4:
7676
0
    case MVE_VLDRB_GATHER_T1:
7677
0
    case MVE_VLDRH_GATHER_T2:
7678
0
    case MVE_VLDRW_GATHER_T3:
7679
0
    case MVE_VLDRD_GATHER_T4:
7680
0
    case MVE_VLDRB_T1:
7681
0
    case MVE_VLDRH_T2:
7682
0
    case MVE_VMAX:
7683
0
    case MVE_VMAXA:
7684
0
    case MVE_VMAXV:
7685
0
    case MVE_VMAXAV:
7686
0
    case MVE_VMIN:
7687
0
    case MVE_VMINA:
7688
0
    case MVE_VMINV:
7689
0
    case MVE_VMINAV:
7690
0
    case MVE_VMLA:
7691
0
    case MVE_VMLAS:
7692
0
    case MVE_VMUL_VEC_T1:
7693
0
    case MVE_VMUL_VEC_T2:
7694
0
    case MVE_VMULH:
7695
0
    case MVE_VRMULH:
7696
0
    case MVE_VMULL_INT:
7697
0
    case MVE_VNEG_FP:
7698
0
    case MVE_VNEG_VEC:
7699
0
    case MVE_VPT_VEC_T1:
7700
0
    case MVE_VPT_VEC_T2:
7701
0
    case MVE_VPT_VEC_T3:
7702
0
    case MVE_VPT_VEC_T4:
7703
0
    case MVE_VPT_VEC_T5:
7704
0
    case MVE_VPT_VEC_T6:
7705
0
    case MVE_VQABS:
7706
0
    case MVE_VQADD_T1:
7707
0
    case MVE_VQADD_T2:
7708
0
    case MVE_VQDMLADH:
7709
0
    case MVE_VQRDMLADH:
7710
0
    case MVE_VQDMLAH:
7711
0
    case MVE_VQRDMLAH:
7712
0
    case MVE_VQDMLASH:
7713
0
    case MVE_VQRDMLASH:
7714
0
    case MVE_VQDMLSDH:
7715
0
    case MVE_VQRDMLSDH:
7716
0
    case MVE_VQDMULH_T1:
7717
0
    case MVE_VQRDMULH_T2:
7718
0
    case MVE_VQDMULH_T3:
7719
0
    case MVE_VQRDMULH_T4:
7720
0
    case MVE_VQNEG:
7721
0
    case MVE_VQRSHL_T1:
7722
0
    case MVE_VQRSHL_T2:
7723
0
    case MVE_VQSHL_T1:
7724
0
    case MVE_VQSHL_T4:
7725
0
    case MVE_VQSUB_T1:
7726
0
    case MVE_VQSUB_T2:
7727
0
    case MVE_VREV32:
7728
0
    case MVE_VREV64:
7729
0
    case MVE_VRHADD:
7730
0
    case MVE_VRINT_FP:
7731
0
    case MVE_VRSHL_T1:
7732
0
    case MVE_VRSHL_T2:
7733
0
    case MVE_VSHL_T2:
7734
0
    case MVE_VSHL_T3:
7735
0
    case MVE_VSHLL_T2:
7736
0
    case MVE_VST2:
7737
0
    case MVE_VST4:
7738
0
    case MVE_VSTRB_SCATTER_T1:
7739
0
    case MVE_VSTRH_SCATTER_T2:
7740
0
    case MVE_VSTRW_SCATTER_T3:
7741
0
    case MVE_VSTRB_T1:
7742
0
    case MVE_VSTRH_T2:
7743
0
    case MVE_VSUB_VEC_T1:
7744
0
    case MVE_VSUB_VEC_T2:
7745
0
      if (size <= 3)
7746
0
  func (stream, dis_style_mnemonic, "%s", mve_vec_sizename[size]);
7747
0
      else
7748
0
  func (stream, dis_style_text, "<undef size>");
7749
0
      break;
7750
7751
0
    case MVE_VABD_FP:
7752
0
    case MVE_VADD_FP_T1:
7753
0
    case MVE_VADD_FP_T2:
7754
0
    case MVE_VSUB_FP_T1:
7755
0
    case MVE_VSUB_FP_T2:
7756
0
    case MVE_VCMP_FP_T1:
7757
0
    case MVE_VCMP_FP_T2:
7758
0
    case MVE_VFMA_FP_SCALAR:
7759
0
    case MVE_VFMA_FP:
7760
0
    case MVE_VFMS_FP:
7761
0
    case MVE_VFMAS_FP_SCALAR:
7762
0
    case MVE_VMAXNM_FP:
7763
0
    case MVE_VMAXNMA_FP:
7764
0
    case MVE_VMAXNMV_FP:
7765
0
    case MVE_VMAXNMAV_FP:
7766
0
    case MVE_VMINNM_FP:
7767
0
    case MVE_VMINNMA_FP:
7768
0
    case MVE_VMINNMV_FP:
7769
0
    case MVE_VMINNMAV_FP:
7770
0
    case MVE_VMUL_FP_T1:
7771
0
    case MVE_VMUL_FP_T2:
7772
0
    case MVE_VPT_FP_T1:
7773
0
    case MVE_VPT_FP_T2:
7774
0
      if (size == 0)
7775
0
  func (stream, dis_style_mnemonic, "32");
7776
0
      else if (size == 1)
7777
0
  func (stream, dis_style_mnemonic, "16");
7778
0
      break;
7779
7780
0
    case MVE_VCADD_FP:
7781
0
    case MVE_VCMLA_FP:
7782
0
    case MVE_VCMUL_FP:
7783
0
    case MVE_VMLADAV_T1:
7784
0
    case MVE_VMLALDAV:
7785
0
    case MVE_VMLSDAV_T1:
7786
0
    case MVE_VMLSLDAV:
7787
0
    case MVE_VMOVN:
7788
0
    case MVE_VQDMULL_T1:
7789
0
    case MVE_VQDMULL_T2:
7790
0
    case MVE_VQMOVN:
7791
0
    case MVE_VQMOVUN:
7792
0
      if (size == 0)
7793
0
  func (stream, dis_style_mnemonic, "16");
7794
0
      else if (size == 1)
7795
0
  func (stream, dis_style_mnemonic, "32");
7796
0
      break;
7797
7798
0
    case MVE_VMOVL:
7799
0
      if (size == 1)
7800
0
  func (stream, dis_style_mnemonic, "8");
7801
0
      else if (size == 2)
7802
0
  func (stream, dis_style_mnemonic, "16");
7803
0
      break;
7804
7805
0
    case MVE_VDUP:
7806
0
      switch (size)
7807
0
  {
7808
0
  case 0:
7809
0
    func (stream, dis_style_mnemonic, "32");
7810
0
    break;
7811
0
  case 1:
7812
0
    func (stream, dis_style_mnemonic, "16");
7813
0
    break;
7814
0
  case 2:
7815
0
    func (stream, dis_style_mnemonic, "8");
7816
0
    break;
7817
0
  default:
7818
0
    break;
7819
0
  }
7820
0
      break;
7821
7822
0
    case MVE_VMOV_GP_TO_VEC_LANE:
7823
0
    case MVE_VMOV_VEC_LANE_TO_GP:
7824
0
      switch (size)
7825
0
  {
7826
0
  case 0: case 4:
7827
0
    func (stream, dis_style_mnemonic, "32");
7828
0
    break;
7829
7830
0
  case 1: case 3:
7831
0
  case 5: case 7:
7832
0
    func (stream, dis_style_mnemonic, "16");
7833
0
    break;
7834
7835
0
  case 8: case 9: case 10: case 11:
7836
0
  case 12: case 13: case 14: case 15:
7837
0
    func (stream, dis_style_mnemonic, "8");
7838
0
    break;
7839
7840
0
  default:
7841
0
    break;
7842
0
  }
7843
0
      break;
7844
7845
0
    case MVE_VMOV_IMM_TO_VEC:
7846
0
      switch (size)
7847
0
  {
7848
0
  case 0: case 4: case 8:
7849
0
  case 12: case 24: case 26:
7850
0
    func (stream, dis_style_mnemonic, "i32");
7851
0
    break;
7852
0
  case 16: case 20:
7853
0
    func (stream, dis_style_mnemonic, "i16");
7854
0
    break;
7855
0
  case 28:
7856
0
    func (stream, dis_style_mnemonic, "i8");
7857
0
    break;
7858
0
  case 29:
7859
0
    func (stream, dis_style_mnemonic, "i64");
7860
0
    break;
7861
0
  case 30:
7862
0
    func (stream, dis_style_mnemonic, "f32");
7863
0
    break;
7864
0
  default:
7865
0
    break;
7866
0
  }
7867
0
      break;
7868
7869
0
    case MVE_VMULL_POLY:
7870
0
      if (size == 0)
7871
0
  func (stream, dis_style_mnemonic, "p8");
7872
0
      else if (size == 1)
7873
0
  func (stream, dis_style_mnemonic, "p16");
7874
0
      break;
7875
7876
0
    case MVE_VMVN_IMM:
7877
0
      switch (size)
7878
0
  {
7879
0
  case 0: case 2: case 4:
7880
0
  case 6: case 12: case 13:
7881
0
    func (stream, dis_style_mnemonic, "32");
7882
0
    break;
7883
7884
0
  case 8: case 10:
7885
0
    func (stream, dis_style_mnemonic, "16");
7886
0
    break;
7887
7888
0
  default:
7889
0
    break;
7890
0
  }
7891
0
      break;
7892
7893
0
    case MVE_VBIC_IMM:
7894
0
    case MVE_VORR_IMM:
7895
0
      switch (size)
7896
0
  {
7897
0
  case 1: case 3:
7898
0
  case 5: case 7:
7899
0
    func (stream, dis_style_mnemonic, "32");
7900
0
    break;
7901
7902
0
  case 9: case 11:
7903
0
    func (stream, dis_style_mnemonic, "16");
7904
0
    break;
7905
7906
0
  default:
7907
0
    break;
7908
0
  }
7909
0
      break;
7910
7911
0
    case MVE_VQSHRN:
7912
0
    case MVE_VQSHRUN:
7913
0
    case MVE_VQRSHRN:
7914
0
    case MVE_VQRSHRUN:
7915
0
    case MVE_VRSHRN:
7916
0
    case MVE_VSHRN:
7917
0
      {
7918
0
  switch (size)
7919
0
  {
7920
0
  case 1:
7921
0
    func (stream, dis_style_mnemonic, "16");
7922
0
    break;
7923
7924
0
  case 2: case 3:
7925
0
    func (stream, dis_style_mnemonic, "32");
7926
0
    break;
7927
7928
0
  default:
7929
0
    break;
7930
0
  }
7931
0
      }
7932
0
      break;
7933
7934
0
    case MVE_VQSHL_T2:
7935
0
    case MVE_VQSHLU_T3:
7936
0
    case MVE_VRSHR:
7937
0
    case MVE_VSHL_T1:
7938
0
    case MVE_VSHLL_T1:
7939
0
    case MVE_VSHR:
7940
0
    case MVE_VSLI:
7941
0
    case MVE_VSRI:
7942
0
      {
7943
0
  switch (size)
7944
0
  {
7945
0
  case 1:
7946
0
    func (stream, dis_style_mnemonic, "8");
7947
0
    break;
7948
7949
0
  case 2: case 3:
7950
0
    func (stream, dis_style_mnemonic, "16");
7951
0
    break;
7952
7953
0
  case 4: case 5: case 6: case 7:
7954
0
    func (stream, dis_style_mnemonic, "32");
7955
0
    break;
7956
7957
0
  default:
7958
0
    break;
7959
0
  }
7960
0
      }
7961
0
      break;
7962
7963
0
    default:
7964
0
      break;
7965
0
    }
7966
0
}
7967
7968
static void
7969
print_mve_shift_n (struct disassemble_info *info, long given,
7970
       enum mve_instructions matched_insn)
7971
0
{
7972
0
  void *stream = info->stream;
7973
0
  fprintf_styled_ftype func = info->fprintf_styled_func;
7974
7975
0
  int startAt0
7976
0
    = matched_insn == MVE_VQSHL_T2
7977
0
      || matched_insn == MVE_VQSHLU_T3
7978
0
      || matched_insn == MVE_VSHL_T1
7979
0
      || matched_insn == MVE_VSHLL_T1
7980
0
      || matched_insn == MVE_VSLI;
7981
7982
0
  unsigned imm6 = (given & 0x3f0000) >> 16;
7983
7984
0
  if (matched_insn == MVE_VSHLL_T1)
7985
0
    imm6 &= 0x1f;
7986
7987
0
  unsigned shiftAmount = 0;
7988
0
  if ((imm6 & 0x20) != 0)
7989
0
    shiftAmount = startAt0 ? imm6 - 32 : 64 - imm6;
7990
0
  else if ((imm6 & 0x10) != 0)
7991
0
    shiftAmount = startAt0 ? imm6 - 16 : 32 - imm6;
7992
0
  else if ((imm6 & 0x08) != 0)
7993
0
    shiftAmount = startAt0 ? imm6 - 8 : 16 - imm6;
7994
0
  else
7995
0
    print_mve_undefined (info, UNDEF_SIZE_0);
7996
7997
0
  func (stream, dis_style_immediate, "%u", shiftAmount);
7998
0
}
7999
8000
static void
8001
print_vec_condition (struct disassemble_info *info, long given,
8002
         enum mve_instructions matched_insn)
8003
0
{
8004
0
  void *stream = info->stream;
8005
0
  fprintf_styled_ftype func = info->fprintf_styled_func;
8006
0
  long vec_cond = 0;
8007
8008
0
  switch (matched_insn)
8009
0
    {
8010
0
    case MVE_VPT_FP_T1:
8011
0
    case MVE_VCMP_FP_T1:
8012
0
      vec_cond = (((given & 0x1000) >> 10)
8013
0
      | ((given & 1) << 1)
8014
0
      | ((given & 0x0080) >> 7));
8015
0
      func (stream, dis_style_sub_mnemonic, "%s", vec_condnames[vec_cond]);
8016
0
      break;
8017
8018
0
    case MVE_VPT_FP_T2:
8019
0
    case MVE_VCMP_FP_T2:
8020
0
      vec_cond = (((given & 0x1000) >> 10)
8021
0
      | ((given & 0x0020) >> 4)
8022
0
      | ((given & 0x0080) >> 7));
8023
0
      func (stream, dis_style_sub_mnemonic, "%s", vec_condnames[vec_cond]);
8024
0
      break;
8025
8026
0
    case MVE_VPT_VEC_T1:
8027
0
    case MVE_VCMP_VEC_T1:
8028
0
      vec_cond = (given & 0x0080) >> 7;
8029
0
      func (stream, dis_style_sub_mnemonic, "%s", vec_condnames[vec_cond]);
8030
0
      break;
8031
8032
0
    case MVE_VPT_VEC_T2:
8033
0
    case MVE_VCMP_VEC_T2:
8034
0
      vec_cond = 2 | ((given & 0x0080) >> 7);
8035
0
      func (stream, dis_style_sub_mnemonic, "%s", vec_condnames[vec_cond]);
8036
0
      break;
8037
8038
0
    case MVE_VPT_VEC_T3:
8039
0
    case MVE_VCMP_VEC_T3:
8040
0
      vec_cond = 4 | ((given & 1) << 1) | ((given & 0x0080) >> 7);
8041
0
      func (stream, dis_style_sub_mnemonic, "%s", vec_condnames[vec_cond]);
8042
0
      break;
8043
8044
0
    case MVE_VPT_VEC_T4:
8045
0
    case MVE_VCMP_VEC_T4:
8046
0
      vec_cond = (given & 0x0080) >> 7;
8047
0
      func (stream, dis_style_sub_mnemonic, "%s", vec_condnames[vec_cond]);
8048
0
      break;
8049
8050
0
    case MVE_VPT_VEC_T5:
8051
0
    case MVE_VCMP_VEC_T5:
8052
0
      vec_cond = 2 | ((given & 0x0080) >> 7);
8053
0
      func (stream, dis_style_sub_mnemonic, "%s", vec_condnames[vec_cond]);
8054
0
      break;
8055
8056
0
    case MVE_VPT_VEC_T6:
8057
0
    case MVE_VCMP_VEC_T6:
8058
0
      vec_cond = 4 | ((given & 0x0020) >> 4) | ((given & 0x0080) >> 7);
8059
0
      func (stream, dis_style_sub_mnemonic, "%s", vec_condnames[vec_cond]);
8060
0
      break;
8061
8062
0
    case MVE_NONE:
8063
0
    case MVE_VPST:
8064
0
    default:
8065
0
      break;
8066
0
    }
8067
0
}
8068
8069
0
#define W_BIT 21
8070
0
#define I_BIT 22
8071
0
#define U_BIT 23
8072
0
#define P_BIT 24
8073
8074
0
#define WRITEBACK_BIT_SET (given & (1 << W_BIT))
8075
0
#define IMMEDIATE_BIT_SET (given & (1 << I_BIT))
8076
0
#define NEGATIVE_BIT_SET  ((given & (1 << U_BIT)) == 0)
8077
0
#define PRE_BIT_SET   (given & (1 << P_BIT))
8078
8079
/* The assembler string for an instruction can include %{X:...%} patterns,
8080
   where the 'X' is one of the characters understood by this function.
8081
8082
   This function takes the X character, and returns a new style.  This new
8083
   style will be used by the caller to temporarily change the current base
8084
   style.  */
8085
8086
static enum disassembler_style
8087
decode_base_style (const char x)
8088
0
{
8089
0
  switch (x)
8090
0
    {
8091
0
    case 'A': return dis_style_address;
8092
0
    case 'B': return dis_style_sub_mnemonic;
8093
0
    case 'C': return dis_style_comment_start;
8094
0
    case 'D': return dis_style_assembler_directive;
8095
0
    case 'I': return dis_style_immediate;
8096
0
    case 'M': return dis_style_mnemonic;
8097
0
    case 'O': return dis_style_address_offset;
8098
0
    case 'R': return dis_style_register;
8099
0
    case 'S': return dis_style_symbol;
8100
0
    case 'T': return dis_style_text;
8101
0
    default:
8102
0
      abort ();
8103
0
    }
8104
0
}
8105
8106
/* Print one coprocessor instruction on INFO->STREAM.
8107
   Return TRUE if the instuction matched, FALSE if this is not a
8108
   recognised coprocessor instruction.  */
8109
8110
static bool
8111
print_insn_coprocessor_1 (const struct sopcode32 *opcodes,
8112
        bfd_vma pc,
8113
        struct disassemble_info *info,
8114
        long given,
8115
        bool thumb)
8116
0
{
8117
0
  const struct sopcode32 *insn;
8118
0
  void *stream = info->stream;
8119
0
  fprintf_styled_ftype func = info->fprintf_styled_func;
8120
0
  unsigned long mask;
8121
0
  unsigned long value = 0;
8122
0
  int cond;
8123
0
  int cp_num;
8124
0
  struct arm_private_data *private_data = info->private_data;
8125
0
  arm_feature_set allowed_arches = ARM_ARCH_NONE;
8126
0
  arm_feature_set arm_ext_v8_1m_main =
8127
0
    ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN);
8128
0
  enum disassembler_style base_style = dis_style_mnemonic;
8129
0
  enum disassembler_style old_base_style = base_style;
8130
8131
0
  allowed_arches = private_data->features;
8132
8133
0
  for (insn = opcodes; insn->assembler; insn++)
8134
0
    {
8135
0
      unsigned long u_reg = 16;
8136
0
      bool is_unpredictable = false;
8137
0
      signed long value_in_comment = 0;
8138
0
      const char *c;
8139
8140
0
      if (ARM_FEATURE_ZERO (insn->arch))
8141
0
  switch (insn->value)
8142
0
    {
8143
0
    case SENTINEL_IWMMXT_START:
8144
0
      if (info->mach != bfd_mach_arm_XScale
8145
0
    && info->mach != bfd_mach_arm_iWMMXt
8146
0
    && info->mach != bfd_mach_arm_iWMMXt2)
8147
0
        do
8148
0
    insn++;
8149
0
        while ((! ARM_FEATURE_ZERO (insn->arch))
8150
0
         && insn->value != SENTINEL_IWMMXT_END);
8151
0
      continue;
8152
8153
0
    case SENTINEL_IWMMXT_END:
8154
0
      continue;
8155
8156
0
    case SENTINEL_GENERIC_START:
8157
0
      allowed_arches = private_data->features;
8158
0
      continue;
8159
8160
0
    default:
8161
0
      abort ();
8162
0
    }
8163
8164
0
      mask = insn->mask;
8165
0
      value = insn->value;
8166
0
      cp_num = (given >> 8) & 0xf;
8167
8168
0
      if (thumb)
8169
0
  {
8170
    /* The high 4 bits are 0xe for Arm conditional instructions, and
8171
       0xe for arm unconditional instructions.  The rest of the
8172
       encoding is the same.  */
8173
0
    mask |= 0xf0000000;
8174
0
    value |= 0xe0000000;
8175
0
    if (ifthen_state)
8176
0
      cond = IFTHEN_COND;
8177
0
    else
8178
0
      cond = COND_UNCOND;
8179
0
  }
8180
0
      else
8181
0
  {
8182
    /* Only match unconditional instuctions against unconditional
8183
       patterns.  */
8184
0
    if ((given & 0xf0000000) == 0xf0000000)
8185
0
      {
8186
0
        mask |= 0xf0000000;
8187
0
        cond = COND_UNCOND;
8188
0
      }
8189
0
    else
8190
0
      {
8191
0
        cond = (given >> 28) & 0xf;
8192
0
        if (cond == 0xe)
8193
0
    cond = COND_UNCOND;
8194
0
      }
8195
0
  }
8196
8197
0
      if ((insn->isa == T32 && !thumb)
8198
0
    || (insn->isa == ARM && thumb))
8199
0
  continue;
8200
8201
0
      if ((given & mask) != value)
8202
0
  continue;
8203
8204
0
      if (! ARM_CPU_HAS_FEATURE (insn->arch, allowed_arches))
8205
0
  continue;
8206
8207
0
      if (insn->value == 0xfe000010     /* mcr2  */
8208
0
    || insn->value == 0xfe100010  /* mrc2  */
8209
0
    || insn->value == 0xfc100000  /* ldc2  */
8210
0
    || insn->value == 0xfc000000) /* stc2  */
8211
0
  {
8212
0
    if (cp_num == 9 || cp_num == 10 || cp_num == 11)
8213
0
      is_unpredictable = true;
8214
8215
    /* Armv8.1-M Mainline FP & MVE instructions.  */
8216
0
    if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
8217
0
        && !ARM_CPU_IS_ANY (allowed_arches)
8218
0
        && (cp_num == 8 || cp_num == 14 || cp_num == 15))
8219
0
      continue;
8220
8221
0
  }
8222
0
      else if (insn->value == 0x0e000000     /* cdp  */
8223
0
         || insn->value == 0xfe000000  /* cdp2  */
8224
0
         || insn->value == 0x0e000010  /* mcr  */
8225
0
         || insn->value == 0x0e100010  /* mrc  */
8226
0
         || insn->value == 0x0c100000  /* ldc  */
8227
0
         || insn->value == 0x0c000000) /* stc  */
8228
0
  {
8229
    /* Floating-point instructions.  */
8230
0
    if (cp_num == 9 || cp_num == 10 || cp_num == 11)
8231
0
      continue;
8232
8233
    /* Armv8.1-M Mainline FP & MVE instructions.  */
8234
0
    if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
8235
0
        && !ARM_CPU_IS_ANY (allowed_arches)
8236
0
        && (cp_num == 8 || cp_num == 14 || cp_num == 15))
8237
0
      continue;
8238
0
  }
8239
0
      else if ((insn->value == 0xec100f80      /* vldr (system register) */
8240
0
    || insn->value == 0xec000f80)  /* vstr (system register) */
8241
0
         && arm_decode_field (given, 24, 24) == 0
8242
0
         && arm_decode_field (given, 21, 21) == 0)
8243
  /* If the P and W bits are both 0 then these encodings match the MVE
8244
     VLDR and VSTR instructions, these are in a different table, so we
8245
     don't let it match here.  */
8246
0
  continue;
8247
8248
0
      for (c = insn->assembler; *c; c++)
8249
0
  {
8250
0
    if (*c == '%')
8251
0
      {
8252
0
        const char mod = *++c;
8253
8254
0
        switch (mod)
8255
0
    {
8256
0
    case '{':
8257
0
      ++c;
8258
0
      if (*c == '\0')
8259
0
        abort ();
8260
0
      old_base_style = base_style;
8261
0
      base_style = decode_base_style (*c);
8262
0
      ++c;
8263
0
      if (*c != ':')
8264
0
        abort ();
8265
0
      break;
8266
8267
0
    case '}':
8268
0
      base_style = old_base_style;
8269
0
      break;
8270
8271
0
    case '%':
8272
0
      func (stream, base_style, "%%");
8273
0
      break;
8274
8275
0
    case 'A':
8276
0
    case 'K':
8277
0
      {
8278
0
        int rn = (given >> 16) & 0xf;
8279
0
        bfd_vma offset = given & 0xff;
8280
8281
0
        if (mod == 'K')
8282
0
          offset = given & 0x7f;
8283
8284
0
        func (stream, dis_style_text, "[");
8285
0
        func (stream, dis_style_register, "%s",
8286
0
        arm_regnames [(given >> 16) & 0xf]);
8287
8288
0
        if (PRE_BIT_SET || WRITEBACK_BIT_SET)
8289
0
          {
8290
      /* Not unindexed.  The offset is scaled.  */
8291
0
      if (cp_num == 9)
8292
        /* vldr.16/vstr.16 will shift the address
8293
           left by 1 bit only.  */
8294
0
        offset = offset * 2;
8295
0
      else
8296
0
        offset = offset * 4;
8297
8298
0
      if (NEGATIVE_BIT_SET)
8299
0
        offset = - offset;
8300
0
      if (rn != 15)
8301
0
        value_in_comment = offset;
8302
0
          }
8303
8304
0
        if (PRE_BIT_SET)
8305
0
          {
8306
0
      if (offset)
8307
0
        {
8308
0
          func (stream, dis_style_text, ", ");
8309
0
          func (stream, dis_style_immediate, "#%d",
8310
0
          (int) offset);
8311
0
          func (stream, dis_style_text, "]%s",
8312
0
          WRITEBACK_BIT_SET ? "!" : "");
8313
0
        }
8314
0
      else if (NEGATIVE_BIT_SET)
8315
0
        {
8316
0
          func (stream, dis_style_text, ", ");
8317
0
          func (stream, dis_style_immediate, "#-0");
8318
0
          func (stream, dis_style_text, "]");
8319
0
        }
8320
0
      else
8321
0
        func (stream, dis_style_text, "]");
8322
0
          }
8323
0
        else
8324
0
          {
8325
0
      func (stream, dis_style_text, "]");
8326
8327
0
      if (WRITEBACK_BIT_SET)
8328
0
        {
8329
0
          if (offset)
8330
0
            {
8331
0
        func (stream, dis_style_text, ", ");
8332
0
        func (stream, dis_style_immediate,
8333
0
              "#%d", (int) offset);
8334
0
            }
8335
0
          else if (NEGATIVE_BIT_SET)
8336
0
            {
8337
0
        func (stream, dis_style_text, ", ");
8338
0
        func (stream, dis_style_immediate, "#-0");
8339
0
            }
8340
0
        }
8341
0
      else
8342
0
        {
8343
0
          func (stream, dis_style_text, ", {");
8344
0
          func (stream, dis_style_immediate, "%s%d",
8345
0
          (NEGATIVE_BIT_SET && !offset) ? "-" : "",
8346
0
          (int) offset);
8347
0
          func (stream, dis_style_text, "}");
8348
0
          value_in_comment = offset;
8349
0
        }
8350
0
          }
8351
0
        if (rn == 15 && (PRE_BIT_SET || WRITEBACK_BIT_SET))
8352
0
          {
8353
0
      func (stream, dis_style_comment_start, "\t@ ");
8354
      /* For unaligned PCs, apply off-by-alignment
8355
         correction.  */
8356
0
      info->print_address_func (offset + pc
8357
0
              + info->bytes_per_chunk * 2
8358
0
              - (pc & 3),
8359
0
              info);
8360
0
          }
8361
0
      }
8362
0
      break;
8363
8364
0
    case 'B':
8365
0
      {
8366
0
        int regno = ((given >> 12) & 0xf) | ((given >> (22 - 4)) & 0x10);
8367
0
        int offset = (given >> 1) & 0x3f;
8368
8369
0
        func (stream, dis_style_text, "{");
8370
0
        if (offset == 1)
8371
0
          func (stream, dis_style_register, "d%d", regno);
8372
0
        else if (regno + offset > 32)
8373
0
          {
8374
0
      func (stream, dis_style_register, "d%d", regno);
8375
0
      func (stream, dis_style_text, "-<overflow reg d%d>",
8376
0
            regno + offset - 1);
8377
0
          }
8378
0
        else
8379
0
          {
8380
0
      func (stream, dis_style_register, "d%d", regno);
8381
0
      func (stream, dis_style_text, "-");
8382
0
      func (stream, dis_style_register, "d%d",
8383
0
            regno + offset - 1);
8384
0
          }
8385
0
        func (stream, dis_style_text, "}");
8386
0
      }
8387
0
      break;
8388
8389
0
    case 'C':
8390
0
      {
8391
0
        bool single = ((given >> 8) & 1) == 0;
8392
0
        char reg_prefix = single ? 's' : 'd';
8393
0
        int Dreg = (given >> 22) & 0x1;
8394
0
        int Vdreg = (given >> 12) & 0xf;
8395
0
        int reg = single ? ((Vdreg << 1) | Dreg)
8396
0
             : ((Dreg << 4) | Vdreg);
8397
0
        int num = (given >> (single ? 0 : 1)) & 0x7f;
8398
0
        int maxreg = single ? 31 : 15;
8399
0
        int topreg = reg + num - 1;
8400
8401
0
        func (stream, dis_style_text, "{");
8402
0
        if (!num)
8403
0
          {
8404
      /* Nothing.  */
8405
0
          }
8406
0
        else if (num == 1)
8407
0
          {
8408
0
      func (stream, dis_style_register,
8409
0
            "%c%d", reg_prefix, reg);
8410
0
      func (stream, dis_style_text, ", ");
8411
0
          }
8412
0
        else if (topreg > maxreg)
8413
0
          {
8414
0
      func (stream, dis_style_register, "%c%d",
8415
0
            reg_prefix, reg);
8416
0
      func (stream, dis_style_text, "-<overflow reg d%d, ",
8417
0
            single ? topreg >> 1 : topreg);
8418
0
          }
8419
0
        else
8420
0
          {
8421
0
      func (stream, dis_style_register,
8422
0
            "%c%d", reg_prefix, reg);
8423
0
      func (stream, dis_style_text, "-");
8424
0
      func (stream, dis_style_register, "%c%d",
8425
0
            reg_prefix, topreg);
8426
0
      func (stream, dis_style_text, ", ");
8427
0
          }
8428
0
        func (stream, dis_style_register, "VPR");
8429
0
        func (stream, dis_style_text, "}");
8430
0
      }
8431
0
      break;
8432
8433
0
    case 'u':
8434
0
      if (cond != COND_UNCOND)
8435
0
        is_unpredictable = true;
8436
8437
      /* Fall through.  */
8438
0
    case 'c':
8439
0
      if (cond != COND_UNCOND && cp_num == 9)
8440
0
        is_unpredictable = true;
8441
8442
      /* Fall through.  */
8443
0
    case 'b':
8444
0
      func (stream, dis_style_mnemonic, "%s",
8445
0
      arm_conditional[cond]);
8446
0
      break;
8447
8448
0
    case 'I':
8449
      /* Print a Cirrus/DSP shift immediate.  */
8450
      /* Immediates are 7bit signed ints with bits 0..3 in
8451
         bits 0..3 of opcode and bits 4..6 in bits 5..7
8452
         of opcode.  */
8453
0
      {
8454
0
        int imm;
8455
8456
0
        imm = (given & 0xf) | ((given & 0xe0) >> 1);
8457
8458
        /* Is ``imm'' a negative number?  */
8459
0
        if (imm & 0x40)
8460
0
          imm -= 0x80;
8461
8462
0
        func (stream, dis_style_immediate, "%d", imm);
8463
0
      }
8464
8465
0
      break;
8466
8467
0
    case 'J':
8468
0
      {
8469
0
        unsigned long regno
8470
0
          = arm_decode_field_multiple (given, 13, 15, 22, 22);
8471
8472
0
        switch (regno)
8473
0
          {
8474
0
          case 0x1:
8475
0
      func (stream, dis_style_register, "FPSCR");
8476
0
      break;
8477
0
          case 0x2:
8478
0
      func (stream, dis_style_register, "FPSCR_nzcvqc");
8479
0
      break;
8480
0
          case 0xc:
8481
0
      func (stream, dis_style_register, "VPR");
8482
0
      break;
8483
0
          case 0xd:
8484
0
      func (stream, dis_style_register, "P0");
8485
0
      break;
8486
0
          case 0xe:
8487
0
      func (stream, dis_style_register, "FPCXTNS");
8488
0
      break;
8489
0
          case 0xf:
8490
0
      func (stream, dis_style_register, "FPCXTS");
8491
0
      break;
8492
0
          default:
8493
0
      func (stream, dis_style_text, "<invalid reg %lu>",
8494
0
            regno);
8495
0
      break;
8496
0
          }
8497
0
      }
8498
0
      break;
8499
8500
0
    case 'F':
8501
0
      switch (given & 0x00408000)
8502
0
        {
8503
0
        case 0:
8504
0
          func (stream, dis_style_immediate, "4");
8505
0
          break;
8506
0
        case 0x8000:
8507
0
          func (stream, dis_style_immediate, "1");
8508
0
          break;
8509
0
        case 0x00400000:
8510
0
          func (stream, dis_style_immediate, "2");
8511
0
          break;
8512
0
        default:
8513
0
          func (stream, dis_style_immediate, "3");
8514
0
        }
8515
0
      break;
8516
8517
0
    case 'P':
8518
0
      switch (given & 0x00080080)
8519
0
        {
8520
0
        case 0:
8521
0
          func (stream, dis_style_mnemonic, "s");
8522
0
          break;
8523
0
        case 0x80:
8524
0
          func (stream, dis_style_mnemonic, "d");
8525
0
          break;
8526
0
        case 0x00080000:
8527
0
          func (stream, dis_style_mnemonic, "e");
8528
0
          break;
8529
0
        default:
8530
0
          func (stream, dis_style_text, _("<illegal precision>"));
8531
0
          break;
8532
0
        }
8533
0
      break;
8534
8535
0
    case 'Q':
8536
0
      switch (given & 0x00408000)
8537
0
        {
8538
0
        case 0:
8539
0
          func (stream, dis_style_mnemonic, "s");
8540
0
          break;
8541
0
        case 0x8000:
8542
0
          func (stream, dis_style_mnemonic, "d");
8543
0
          break;
8544
0
        case 0x00400000:
8545
0
          func (stream, dis_style_mnemonic, "e");
8546
0
          break;
8547
0
        default:
8548
0
          func (stream, dis_style_mnemonic, "p");
8549
0
          break;
8550
0
        }
8551
0
      break;
8552
8553
0
    case 'R':
8554
0
      switch (given & 0x60)
8555
0
        {
8556
0
        case 0:
8557
0
          break;
8558
0
        case 0x20:
8559
0
          func (stream, dis_style_mnemonic, "p");
8560
0
          break;
8561
0
        case 0x40:
8562
0
          func (stream, dis_style_mnemonic, "m");
8563
0
          break;
8564
0
        default:
8565
0
          func (stream, dis_style_mnemonic, "z");
8566
0
          break;
8567
0
        }
8568
0
      break;
8569
8570
0
    case '0': case '1': case '2': case '3': case '4':
8571
0
    case '5': case '6': case '7': case '8': case '9':
8572
0
      {
8573
0
        int width;
8574
8575
0
        c = arm_decode_bitfield (c, given, &value, &width);
8576
8577
0
        switch (*c)
8578
0
          {
8579
0
          case 'R':
8580
0
      if (value == 15)
8581
0
        is_unpredictable = true;
8582
      /* Fall through.  */
8583
0
          case 'r':
8584
0
      if (c[1] == 'u')
8585
0
        {
8586
          /* Eat the 'u' character.  */
8587
0
          ++ c;
8588
8589
0
          if (u_reg == value)
8590
0
            is_unpredictable = true;
8591
0
          u_reg = value;
8592
0
        }
8593
0
      func (stream, dis_style_register, "%s",
8594
0
            arm_regnames[value]);
8595
0
      break;
8596
0
          case 'V':
8597
0
      if (given & (1 << 6))
8598
0
        goto Q;
8599
      /* FALLTHROUGH */
8600
0
          case 'D':
8601
0
      func (stream, dis_style_register, "d%ld", value);
8602
0
      break;
8603
0
          case 'Q':
8604
0
          Q:
8605
0
      if (value & 1)
8606
0
        func (stream, dis_style_text,
8607
0
        "<illegal reg q%ld.5>", value >> 1);
8608
0
      else
8609
0
        func (stream, dis_style_register,
8610
0
        "q%ld", value >> 1);
8611
0
      break;
8612
0
          case 'd':
8613
0
      func (stream, base_style, "%ld", value);
8614
0
      value_in_comment = value;
8615
0
      break;
8616
0
          case 'E':
8617
0
                        {
8618
        /* Converts immediate 8 bit back to float value.  */
8619
0
        unsigned floatVal = (value & 0x80) << 24
8620
0
          | (value & 0x3F) << 19
8621
0
          | ((value & 0x40) ? (0xF8 << 22) : (1 << 30));
8622
8623
        /* Quarter float have a maximum value of 31.0.
8624
           Get floating point value multiplied by 1e7.
8625
           The maximum value stays in limit of a 32-bit int.  */
8626
0
        unsigned decVal =
8627
0
          (78125 << (((floatVal >> 23) & 0xFF) - 124)) *
8628
0
          (16 + (value & 0xF));
8629
8630
0
        if (!(decVal % 1000000))
8631
0
          {
8632
0
            func (stream, dis_style_immediate, "%ld", value);
8633
0
            func (stream, dis_style_comment_start,
8634
0
            "\t@ 0x%08x %c%u.%01u",
8635
0
            floatVal, value & 0x80 ? '-' : ' ',
8636
0
            decVal / 10000000,
8637
0
            decVal % 10000000 / 1000000);
8638
0
          }
8639
0
        else if (!(decVal % 10000))
8640
0
          {
8641
0
            func (stream, dis_style_immediate, "%ld", value);
8642
0
            func (stream, dis_style_comment_start,
8643
0
            "\t@ 0x%08x %c%u.%03u",
8644
0
            floatVal, value & 0x80 ? '-' : ' ',
8645
0
            decVal / 10000000,
8646
0
            decVal % 10000000 / 10000);
8647
0
          }
8648
0
        else
8649
0
          {
8650
0
            func (stream, dis_style_immediate, "%ld", value);
8651
0
            func (stream, dis_style_comment_start,
8652
0
            "\t@ 0x%08x %c%u.%07u",
8653
0
            floatVal, value & 0x80 ? '-' : ' ',
8654
0
            decVal / 10000000, decVal % 10000000);
8655
0
          }
8656
0
        break;
8657
0
      }
8658
0
          case 'k':
8659
0
      {
8660
0
        int from = (given & (1 << 7)) ? 32 : 16;
8661
0
        func (stream, dis_style_immediate, "%ld",
8662
0
        from - value);
8663
0
      }
8664
0
      break;
8665
8666
0
          case 'f':
8667
0
      if (value > 7)
8668
0
        func (stream, dis_style_immediate, "#%s",
8669
0
        arm_fp_const[value & 7]);
8670
0
      else
8671
0
        func (stream, dis_style_register, "f%ld", value);
8672
0
      break;
8673
8674
0
          case 'w':
8675
0
      if (width == 2)
8676
0
        func (stream, dis_style_mnemonic, "%s",
8677
0
        iwmmxt_wwnames[value]);
8678
0
      else
8679
0
        func (stream, dis_style_mnemonic, "%s",
8680
0
        iwmmxt_wwssnames[value]);
8681
0
      break;
8682
8683
0
          case 'g':
8684
0
      func (stream, dis_style_register, "%s",
8685
0
            iwmmxt_regnames[value]);
8686
0
      break;
8687
0
          case 'G':
8688
0
      func (stream, dis_style_register, "%s",
8689
0
            iwmmxt_cregnames[value]);
8690
0
      break;
8691
8692
0
          case 'x':
8693
0
      func (stream, dis_style_immediate, "0x%lx",
8694
0
            (value & 0xffffffffUL));
8695
0
      break;
8696
8697
0
          case 'c':
8698
0
      switch (value)
8699
0
        {
8700
0
        case 0:
8701
0
          func (stream, dis_style_mnemonic, "eq");
8702
0
          break;
8703
8704
0
        case 1:
8705
0
          func (stream, dis_style_mnemonic, "vs");
8706
0
          break;
8707
8708
0
        case 2:
8709
0
          func (stream, dis_style_mnemonic, "ge");
8710
0
          break;
8711
8712
0
        case 3:
8713
0
          func (stream, dis_style_mnemonic, "gt");
8714
0
          break;
8715
8716
0
        default:
8717
0
          func (stream, dis_style_text, "??");
8718
0
          break;
8719
0
        }
8720
0
      break;
8721
8722
0
          case '`':
8723
0
      c++;
8724
0
      if (value == 0)
8725
0
        func (stream, dis_style_mnemonic, "%c", *c);
8726
0
      break;
8727
0
          case '\'':
8728
0
      c++;
8729
0
      if (value == ((1ul << width) - 1))
8730
0
        func (stream, base_style, "%c", *c);
8731
0
      break;
8732
0
          case '?':
8733
0
      func (stream, base_style, "%c",
8734
0
            c[(1 << width) - (int) value]);
8735
0
      c += 1 << width;
8736
0
      break;
8737
0
          default:
8738
0
      abort ();
8739
0
          }
8740
0
      }
8741
0
      break;
8742
8743
0
    case 'y':
8744
0
    case 'z':
8745
0
      {
8746
0
        int single = *c++ == 'y';
8747
0
        int regno;
8748
8749
0
        switch (*c)
8750
0
          {
8751
0
          case '4': /* Sm pair */
8752
0
          case '0': /* Sm, Dm */
8753
0
      regno = given & 0x0000000f;
8754
0
      if (single)
8755
0
        {
8756
0
          regno <<= 1;
8757
0
          regno += (given >> 5) & 1;
8758
0
        }
8759
0
      else
8760
0
        regno += ((given >> 5) & 1) << 4;
8761
0
      break;
8762
8763
0
          case '1': /* Sd, Dd */
8764
0
      regno = (given >> 12) & 0x0000000f;
8765
0
      if (single)
8766
0
        {
8767
0
          regno <<= 1;
8768
0
          regno += (given >> 22) & 1;
8769
0
        }
8770
0
      else
8771
0
        regno += ((given >> 22) & 1) << 4;
8772
0
      break;
8773
8774
0
          case '2': /* Sn, Dn */
8775
0
      regno = (given >> 16) & 0x0000000f;
8776
0
      if (single)
8777
0
        {
8778
0
          regno <<= 1;
8779
0
          regno += (given >> 7) & 1;
8780
0
        }
8781
0
      else
8782
0
        regno += ((given >> 7) & 1) << 4;
8783
0
      break;
8784
8785
0
          case '3': /* List */
8786
0
      func (stream, dis_style_text, "{");
8787
0
      regno = (given >> 12) & 0x0000000f;
8788
0
      if (single)
8789
0
        {
8790
0
          regno <<= 1;
8791
0
          regno += (given >> 22) & 1;
8792
0
        }
8793
0
      else
8794
0
        regno += ((given >> 22) & 1) << 4;
8795
0
      break;
8796
8797
0
          default:
8798
0
      abort ();
8799
0
          }
8800
8801
0
        func (stream, dis_style_register, "%c%d",
8802
0
        single ? 's' : 'd', regno);
8803
8804
0
        if (*c == '3')
8805
0
          {
8806
0
      int count = given & 0xff;
8807
8808
0
      if (single == 0)
8809
0
        count >>= 1;
8810
8811
0
      if (--count)
8812
0
        {
8813
0
          func (stream, dis_style_text, "-");
8814
0
          func (stream, dis_style_register, "%c%d",
8815
0
          single ? 's' : 'd',
8816
0
          regno + count);
8817
0
        }
8818
8819
0
      func (stream, dis_style_text, "}");
8820
0
          }
8821
0
        else if (*c == '4')
8822
0
          {
8823
0
      func (stream, dis_style_text, ", ");
8824
0
      func (stream, dis_style_register, "%c%d",
8825
0
            single ? 's' : 'd', regno + 1);
8826
0
          }
8827
0
      }
8828
0
      break;
8829
8830
0
    case 'L':
8831
0
      switch (given & 0x00400100)
8832
0
        {
8833
0
        case 0x00000000:
8834
0
          func (stream, dis_style_mnemonic, "b");
8835
0
          break;
8836
0
        case 0x00400000:
8837
0
          func (stream, dis_style_mnemonic, "h");
8838
0
          break;
8839
0
        case 0x00000100:
8840
0
          func (stream, dis_style_mnemonic, "w");
8841
0
          break;
8842
0
        case 0x00400100:
8843
0
          func (stream, dis_style_mnemonic, "d");
8844
0
          break;
8845
0
        default:
8846
0
          break;
8847
0
        }
8848
0
      break;
8849
8850
0
    case 'Z':
8851
0
      {
8852
        /* given (20, 23) | given (0, 3) */
8853
0
        value = ((given >> 16) & 0xf0) | (given & 0xf);
8854
0
        func (stream, dis_style_immediate, "%d", (int) value);
8855
0
      }
8856
0
      break;
8857
8858
0
    case 'l':
8859
      /* This is like the 'A' operator, except that if
8860
         the width field "M" is zero, then the offset is
8861
         *not* multiplied by four.  */
8862
0
      {
8863
0
        int offset = given & 0xff;
8864
0
        int multiplier = (given & 0x00000100) ? 4 : 1;
8865
8866
0
        func (stream, dis_style_text, "[");
8867
0
        func (stream, dis_style_register, "%s",
8868
0
        arm_regnames [(given >> 16) & 0xf]);
8869
8870
0
        if (multiplier > 1)
8871
0
          {
8872
0
      value_in_comment = offset * multiplier;
8873
0
      if (NEGATIVE_BIT_SET)
8874
0
        value_in_comment = - value_in_comment;
8875
0
          }
8876
8877
0
        if (offset)
8878
0
          {
8879
0
      if (PRE_BIT_SET)
8880
0
        {
8881
0
          func (stream, dis_style_text, ", ");
8882
0
          func (stream, dis_style_immediate, "#%s%d",
8883
0
          NEGATIVE_BIT_SET ? "-" : "",
8884
0
          offset * multiplier);
8885
0
          func (stream, dis_style_text, "]%s",
8886
0
          WRITEBACK_BIT_SET ? "!" : "");
8887
0
        }
8888
0
      else
8889
0
        {
8890
0
          func (stream, dis_style_text, "], ");
8891
0
          func (stream, dis_style_immediate, "#%s%d",
8892
0
          NEGATIVE_BIT_SET ? "-" : "",
8893
0
          offset * multiplier);
8894
0
        }
8895
0
          }
8896
0
        else
8897
0
          func (stream, dis_style_text, "]");
8898
0
      }
8899
0
      break;
8900
8901
0
    case 'r':
8902
0
      {
8903
0
        int imm4 = (given >> 4) & 0xf;
8904
0
        int puw_bits = ((given >> 22) & 6) | ((given >> W_BIT) & 1);
8905
0
        int ubit = ! NEGATIVE_BIT_SET;
8906
0
        const char *rm = arm_regnames [given & 0xf];
8907
0
        const char *rn = arm_regnames [(given >> 16) & 0xf];
8908
8909
0
        switch (puw_bits)
8910
0
          {
8911
0
          case 1:
8912
0
          case 3:
8913
0
      func (stream, dis_style_text, "[");
8914
0
      func (stream, dis_style_register, "%s", rn);
8915
0
      func (stream, dis_style_text, "], ");
8916
0
      func (stream, dis_style_text, "%c", ubit ? '+' : '-');
8917
0
      func (stream, dis_style_register, "%s", rm);
8918
0
      if (imm4)
8919
0
        {
8920
0
          func (stream, dis_style_text, ", ");
8921
0
          func (stream, dis_style_sub_mnemonic, "lsl ");
8922
0
          func (stream, dis_style_immediate, "#%d", imm4);
8923
0
        }
8924
0
      break;
8925
8926
0
          case 4:
8927
0
          case 5:
8928
0
          case 6:
8929
0
          case 7:
8930
0
      func (stream, dis_style_text, "[");
8931
0
      func (stream, dis_style_register, "%s", rn);
8932
0
      func (stream, dis_style_text, ", ");
8933
0
      func (stream, dis_style_text, "%c", ubit ? '+' : '-');
8934
0
      func (stream, dis_style_register, "%s", rm);
8935
0
      if (imm4 > 0)
8936
0
        {
8937
0
          func (stream, dis_style_text, ", ");
8938
0
          func (stream, dis_style_sub_mnemonic, "lsl ");
8939
0
          func (stream, dis_style_immediate, "#%d", imm4);
8940
0
        }
8941
0
      func (stream, dis_style_text, "]");
8942
0
      if (puw_bits == 5 || puw_bits == 7)
8943
0
        func (stream, dis_style_text, "!");
8944
0
      break;
8945
8946
0
          default:
8947
0
      func (stream, dis_style_text, "INVALID");
8948
0
          }
8949
0
      }
8950
0
      break;
8951
8952
0
    case 'i':
8953
0
      {
8954
0
        long imm5;
8955
0
        imm5 = ((given & 0x100) >> 4) | (given & 0xf);
8956
0
        func (stream, dis_style_immediate, "%ld",
8957
0
        (imm5 == 0) ? 32 : imm5);
8958
0
      }
8959
0
      break;
8960
8961
0
    default:
8962
0
      abort ();
8963
0
    }
8964
0
      }
8965
0
    else
8966
0
      {
8967
0
        if (*c == '@')
8968
0
    base_style = dis_style_comment_start;
8969
8970
0
        if (*c == '\t')
8971
0
    base_style = dis_style_text;
8972
8973
0
        func (stream, base_style, "%c", *c);
8974
0
      }
8975
0
  }
8976
8977
0
      if (value_in_comment > 32 || value_in_comment < -16)
8978
0
  func (stream, dis_style_comment_start, "\t@ 0x%lx",
8979
0
        (value_in_comment & 0xffffffffUL));
8980
8981
0
      if (is_unpredictable)
8982
0
  func (stream, dis_style_comment_start, UNPREDICTABLE_INSTRUCTION);
8983
8984
0
      return true;
8985
0
    }
8986
0
  return false;
8987
0
}
8988
8989
static bool
8990
print_insn_coprocessor (bfd_vma pc,
8991
      struct disassemble_info *info,
8992
      long given,
8993
      bool thumb)
8994
0
{
8995
0
  return print_insn_coprocessor_1 (coprocessor_opcodes,
8996
0
           pc, info, given, thumb);
8997
0
}
8998
8999
static bool
9000
print_insn_generic_coprocessor (bfd_vma pc,
9001
        struct disassemble_info *info,
9002
        long given,
9003
        bool thumb)
9004
0
{
9005
0
  return print_insn_coprocessor_1 (generic_coprocessor_opcodes,
9006
0
           pc, info, given, thumb);
9007
0
}
9008
9009
/* Decodes and prints ARM addressing modes.  Returns the offset
9010
   used in the address, if any, if it is worthwhile printing the
9011
   offset as a hexadecimal value in a comment at the end of the
9012
   line of disassembly.  */
9013
9014
static signed long
9015
print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
9016
0
{
9017
0
  void *stream = info->stream;
9018
0
  fprintf_styled_ftype func = info->fprintf_styled_func;
9019
0
  bfd_vma offset = 0;
9020
9021
0
  if (((given & 0x000f0000) == 0x000f0000)
9022
0
      && ((given & 0x02000000) == 0))
9023
0
    {
9024
0
      offset = given & 0xfff;
9025
9026
0
      func (stream, dis_style_text, "[");
9027
0
      func (stream, dis_style_register, "pc");
9028
9029
0
      if (PRE_BIT_SET)
9030
0
  {
9031
    /* Pre-indexed.  Elide offset of positive zero when
9032
       non-writeback.  */
9033
0
    if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
9034
0
      {
9035
0
        func (stream, dis_style_text, ", ");
9036
0
        func (stream, dis_style_immediate, "#%s%d",
9037
0
        NEGATIVE_BIT_SET ? "-" : "", (int) offset);
9038
0
      }
9039
9040
0
    if (NEGATIVE_BIT_SET)
9041
0
      offset = -offset;
9042
9043
0
    offset += pc + 8;
9044
9045
    /* Cope with the possibility of write-back
9046
       being used.  Probably a very dangerous thing
9047
       for the programmer to do, but who are we to
9048
       argue ?  */
9049
0
    func (stream, dis_style_text, "]%s", WRITEBACK_BIT_SET ? "!" : "");
9050
0
  }
9051
0
      else  /* Post indexed.  */
9052
0
  {
9053
0
    func (stream, dis_style_text, "], ");
9054
0
    func (stream, dis_style_immediate, "#%s%d",
9055
0
    NEGATIVE_BIT_SET ? "-" : "", (int) offset);
9056
9057
    /* Ie ignore the offset.  */
9058
0
    offset = pc + 8;
9059
0
  }
9060
9061
0
      func (stream, dis_style_comment_start, "\t@ ");
9062
0
      info->print_address_func (offset, info);
9063
0
      offset = 0;
9064
0
    }
9065
0
  else
9066
0
    {
9067
0
      func (stream, dis_style_text, "[");
9068
0
      func (stream, dis_style_register, "%s",
9069
0
      arm_regnames[(given >> 16) & 0xf]);
9070
9071
0
      if (PRE_BIT_SET)
9072
0
  {
9073
0
    if ((given & 0x02000000) == 0)
9074
0
      {
9075
        /* Elide offset of positive zero when non-writeback.  */
9076
0
        offset = given & 0xfff;
9077
0
        if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
9078
0
    {
9079
0
      func (stream, dis_style_text, ", ");
9080
0
      func (stream, dis_style_immediate, "#%s%d",
9081
0
      NEGATIVE_BIT_SET ? "-" : "", (int) offset);
9082
0
    }
9083
0
      }
9084
0
    else
9085
0
      {
9086
0
        func (stream, dis_style_text, ", %s",
9087
0
        NEGATIVE_BIT_SET ? "-" : "");
9088
0
        arm_decode_shift (given, func, stream, true);
9089
0
      }
9090
9091
0
    func (stream, dis_style_text, "]%s",
9092
0
    WRITEBACK_BIT_SET ? "!" : "");
9093
0
  }
9094
0
      else
9095
0
  {
9096
0
    if ((given & 0x02000000) == 0)
9097
0
      {
9098
        /* Always show offset.  */
9099
0
        offset = given & 0xfff;
9100
0
        func (stream, dis_style_text, "], ");
9101
0
        func (stream, dis_style_immediate, "#%s%d",
9102
0
        NEGATIVE_BIT_SET ? "-" : "", (int) offset);
9103
0
      }
9104
0
    else
9105
0
      {
9106
0
        func (stream, dis_style_text, "], %s",
9107
0
        NEGATIVE_BIT_SET ? "-" : "");
9108
0
        arm_decode_shift (given, func, stream, true);
9109
0
      }
9110
0
  }
9111
0
      if (NEGATIVE_BIT_SET)
9112
0
  offset = -offset;
9113
0
    }
9114
9115
0
  return (signed long) offset;
9116
0
}
9117
9118
9119
/* Print one cde instruction on INFO->STREAM.
9120
   Return TRUE if the instuction matched, FALSE if this is not a
9121
   recognised cde instruction.  */
9122
static bool
9123
print_insn_cde (struct disassemble_info *info, long given, bool thumb)
9124
0
{
9125
0
  const struct cdeopcode32 *insn;
9126
0
  void *stream = info->stream;
9127
0
  fprintf_styled_ftype func = info->fprintf_styled_func;
9128
0
  enum disassembler_style base_style = dis_style_mnemonic;
9129
0
  enum disassembler_style old_base_style = base_style;
9130
9131
0
  if (thumb)
9132
0
  {
9133
    /* Manually extract the coprocessor code from a known point.
9134
       This position is the same across all CDE instructions.  */
9135
0
    for (insn = cde_opcodes; insn->assembler; insn++)
9136
0
    {
9137
0
      uint16_t coproc = (given >> insn->coproc_shift) & insn->coproc_mask;
9138
0
      uint16_t coproc_mask = 1 << coproc;
9139
0
      if (! (coproc_mask & cde_coprocs))
9140
0
  continue;
9141
9142
0
      if ((given & insn->mask) == insn->value)
9143
0
      {
9144
0
  bool is_unpredictable = false;
9145
0
  const char *c;
9146
9147
0
  for (c = insn->assembler; *c; c++)
9148
0
  {
9149
0
    if (*c == '%')
9150
0
    {
9151
0
      switch (*++c)
9152
0
      {
9153
0
        case '{':
9154
0
    ++c;
9155
0
    if (*c == '\0')
9156
0
      abort ();
9157
0
    old_base_style = base_style;
9158
0
    base_style = decode_base_style (*c);
9159
0
    ++c;
9160
0
    if (*c != ':')
9161
0
      abort ();
9162
0
    break;
9163
9164
0
        case '}':
9165
0
    base_style = old_base_style;
9166
0
    break;
9167
9168
0
        case '%':
9169
0
    func (stream, base_style, "%%");
9170
0
    break;
9171
9172
0
        case '0': case '1': case '2': case '3': case '4':
9173
0
        case '5': case '6': case '7': case '8': case '9':
9174
0
        {
9175
0
    int width;
9176
0
    unsigned long value;
9177
9178
0
    c = arm_decode_bitfield (c, given, &value, &width);
9179
9180
0
    switch (*c)
9181
0
    {
9182
0
      case 'S':
9183
0
        if (value > 10)
9184
0
          is_unpredictable = true;
9185
        /* Fall through.  */
9186
0
      case 'R':
9187
0
        if (value == 13)
9188
0
          is_unpredictable = true;
9189
        /* Fall through.  */
9190
0
      case 'r':
9191
0
        func (stream, dis_style_register, "%s",
9192
0
        arm_regnames[value]);
9193
0
        break;
9194
9195
0
      case 'n':
9196
0
        if (value == 15)
9197
0
          func (stream, dis_style_register, "%s", "APSR_nzcv");
9198
0
        else
9199
0
          func (stream, dis_style_register, "%s",
9200
0
          arm_regnames[value]);
9201
0
        break;
9202
9203
0
      case 'T':
9204
0
        func (stream, dis_style_register, "%s",
9205
0
        arm_regnames[(value + 1) & 15]);
9206
0
        break;
9207
9208
0
      case 'd':
9209
0
        func (stream, dis_style_immediate, "%ld", value);
9210
0
        break;
9211
9212
0
      case 'V':
9213
0
        if (given & (1 << 6))
9214
0
          func (stream, dis_style_register, "q%ld", value >> 1);
9215
0
        else if (given & (1 << 24))
9216
0
          func (stream, dis_style_register, "d%ld", value);
9217
0
        else
9218
0
          {
9219
      /* Encoding for S register is different than for D and
9220
         Q registers.  S registers are encoded using the top
9221
         single bit in position 22 as the lowest bit of the
9222
         register number, while for Q and D it represents the
9223
         highest bit of the register number.  */
9224
0
      uint8_t top_bit = (value >> 4) & 1;
9225
0
      uint8_t tmp = (value << 1) & 0x1e;
9226
0
      uint8_t res = tmp | top_bit;
9227
0
      func (stream, dis_style_register, "s%u", res);
9228
0
          }
9229
0
        break;
9230
9231
0
    default:
9232
0
      abort ();
9233
0
    }
9234
0
        }
9235
0
      break;
9236
9237
0
      case 'p':
9238
0
        {
9239
0
    uint8_t proc_number = (given >> 8) & 0x7;
9240
0
    func (stream, dis_style_register, "p%u", proc_number);
9241
0
    break;
9242
0
        }
9243
9244
0
      case 'a':
9245
0
        {
9246
0
    uint8_t a_offset = 28;
9247
0
    if (given & (1 << a_offset))
9248
0
      func (stream, dis_style_mnemonic, "a");
9249
0
    break;
9250
0
        }
9251
0
    default:
9252
0
      abort ();
9253
0
    }
9254
0
  }
9255
0
  else
9256
0
    {
9257
0
      if (*c == '@')
9258
0
        base_style = dis_style_comment_start;
9259
0
      if (*c == '\t')
9260
0
        base_style = dis_style_text;
9261
9262
0
      func (stream, base_style, "%c", *c);
9263
0
    }
9264
0
      }
9265
9266
0
      if (is_unpredictable)
9267
0
  func (stream, dis_style_comment_start, UNPREDICTABLE_INSTRUCTION);
9268
9269
0
      return true;
9270
0
      }
9271
0
    }
9272
0
    return false;
9273
0
  }
9274
0
  else
9275
0
    return false;
9276
0
}
9277
9278
9279
/* Print one neon instruction on INFO->STREAM.
9280
   Return TRUE if the instuction matched, FALSE if this is not a
9281
   recognised neon instruction.  */
9282
9283
static bool
9284
print_insn_neon (struct disassemble_info *info, long given, bool thumb)
9285
0
{
9286
0
  const struct opcode32 *insn;
9287
0
  void *stream = info->stream;
9288
0
  fprintf_styled_ftype func = info->fprintf_styled_func;
9289
0
  enum disassembler_style base_style = dis_style_mnemonic;
9290
0
  enum disassembler_style old_base_style = base_style;
9291
9292
0
  if (thumb)
9293
0
    {
9294
0
      if ((given & 0xef000000) == 0xef000000)
9295
0
  {
9296
    /* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding.  */
9297
0
    unsigned long bit28 = given & (1 << 28);
9298
9299
0
    given &= 0x00ffffff;
9300
0
    if (bit28)
9301
0
            given |= 0xf3000000;
9302
0
          else
9303
0
      given |= 0xf2000000;
9304
0
  }
9305
0
      else if ((given & 0xff000000) == 0xf9000000)
9306
0
  given ^= 0xf9000000 ^ 0xf4000000;
9307
      /* BFloat16 neon instructions without special top byte handling.  */
9308
0
      else if ((given & 0xff000000) == 0xfe000000
9309
0
         || (given & 0xff000000) == 0xfc000000)
9310
0
  ;
9311
      /* vdup is also a valid neon instruction.  */
9312
0
      else if ((given & 0xff900f5f) != 0xee800b10)
9313
0
  return false;
9314
0
    }
9315
9316
0
  for (insn = neon_opcodes; insn->assembler; insn++)
9317
0
    {
9318
0
      unsigned long cond_mask = insn->mask;
9319
0
      unsigned long cond_value = insn->value;
9320
0
      int cond;
9321
9322
0
      if (thumb)
9323
0
        {
9324
0
          if ((cond_mask & 0xf0000000) == 0) {
9325
              /* For the entries in neon_opcodes, an opcode mask/value with
9326
                 the high 4 bits equal to 0 indicates a conditional
9327
                 instruction. For thumb however, we need to include those
9328
                 bits in the instruction matching.  */
9329
0
              cond_mask |= 0xf0000000;
9330
              /* Furthermore, the thumb encoding of a conditional instruction
9331
                 will have the high 4 bits equal to 0xe.  */
9332
0
              cond_value |= 0xe0000000;
9333
0
          }
9334
0
          if (ifthen_state)
9335
0
            cond = IFTHEN_COND;
9336
0
          else
9337
0
            cond = COND_UNCOND;
9338
0
        }
9339
0
      else
9340
0
        {
9341
0
          if ((given & 0xf0000000) == 0xf0000000)
9342
0
            {
9343
              /* If the instruction is unconditional, update the mask to only
9344
                 match against unconditional opcode values.  */
9345
0
              cond_mask |= 0xf0000000;
9346
0
              cond = COND_UNCOND;
9347
0
            }
9348
0
          else
9349
0
            {
9350
0
              cond = (given >> 28) & 0xf;
9351
0
              if (cond == 0xe)
9352
0
                cond = COND_UNCOND;
9353
0
            }
9354
0
        }
9355
9356
0
      if ((given & cond_mask) == cond_value)
9357
0
  {
9358
0
    signed long value_in_comment = 0;
9359
0
    bool is_unpredictable = false;
9360
0
    const char *c;
9361
9362
0
    for (c = insn->assembler; *c; c++)
9363
0
      {
9364
0
        if (*c == '%')
9365
0
    {
9366
0
      switch (*++c)
9367
0
        {
9368
0
        case '{':
9369
0
          ++c;
9370
0
          if (*c == '\0')
9371
0
      abort ();
9372
0
          old_base_style = base_style;
9373
0
          base_style = decode_base_style (*c);
9374
0
          ++c;
9375
0
          if (*c != ':')
9376
0
      abort ();
9377
0
          break;
9378
9379
0
        case '}':
9380
0
          base_style = old_base_style;
9381
0
          break;
9382
9383
0
        case '%':
9384
0
          func (stream, base_style, "%%");
9385
0
          break;
9386
9387
0
        case 'u':
9388
0
          if (thumb && ifthen_state)
9389
0
      is_unpredictable = true;
9390
9391
          /* Fall through.  */
9392
0
        case 'c':
9393
0
          func (stream, dis_style_mnemonic, "%s",
9394
0
          arm_conditional[cond]);
9395
0
          break;
9396
9397
0
        case 'A':
9398
0
          {
9399
0
      static const unsigned char enc[16] =
9400
0
      {
9401
0
        0x4, 0x14, /* st4 0,1 */
9402
0
        0x4, /* st1 2 */
9403
0
        0x4, /* st2 3 */
9404
0
        0x3, /* st3 4 */
9405
0
        0x13, /* st3 5 */
9406
0
        0x3, /* st1 6 */
9407
0
        0x1, /* st1 7 */
9408
0
        0x2, /* st2 8 */
9409
0
        0x12, /* st2 9 */
9410
0
        0x2, /* st1 10 */
9411
0
        0, 0, 0, 0, 0
9412
0
      };
9413
0
      int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
9414
0
      int rn = ((given >> 16) & 0xf);
9415
0
      int rm = ((given >> 0) & 0xf);
9416
0
      int align = ((given >> 4) & 0x3);
9417
0
      int type = ((given >> 8) & 0xf);
9418
0
      int n = enc[type] & 0xf;
9419
0
      int stride = (enc[type] >> 4) + 1;
9420
0
      int ix;
9421
9422
0
      func (stream, dis_style_text, "{");
9423
0
      if (stride > 1)
9424
0
        for (ix = 0; ix != n; ix++)
9425
0
          {
9426
0
            if (ix > 0)
9427
0
        func (stream, dis_style_text, ",");
9428
0
            func (stream, dis_style_register, "d%d",
9429
0
            rd + ix * stride);
9430
0
          }
9431
0
      else if (n == 1)
9432
0
        func (stream, dis_style_register, "d%d", rd);
9433
0
      else
9434
0
        {
9435
0
          func (stream, dis_style_register, "d%d", rd);
9436
0
          func (stream, dis_style_text, "-");
9437
0
          func (stream, dis_style_register, "d%d",
9438
0
          rd + n - 1);
9439
0
        }
9440
0
      func (stream, dis_style_text, "}, [");
9441
0
      func (stream, dis_style_register, "%s",
9442
0
            arm_regnames[rn]);
9443
0
      if (align)
9444
0
        {
9445
0
          func (stream, dis_style_text, " :");
9446
0
          func (stream, dis_style_immediate, "%d",
9447
0
          32 << align);
9448
0
        }
9449
0
      func (stream, dis_style_text, "]");
9450
0
      if (rm == 0xd)
9451
0
        func (stream, dis_style_text, "!");
9452
0
      else if (rm != 0xf)
9453
0
        {
9454
0
          func (stream, dis_style_text, ", ");
9455
0
          func (stream, dis_style_register, "%s",
9456
0
          arm_regnames[rm]);
9457
0
        }
9458
0
          }
9459
0
          break;
9460
9461
0
        case 'B':
9462
0
          {
9463
0
      int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
9464
0
      int rn = ((given >> 16) & 0xf);
9465
0
      int rm = ((given >> 0) & 0xf);
9466
0
      int idx_align = ((given >> 4) & 0xf);
9467
0
                        int align = 0;
9468
0
      int size = ((given >> 10) & 0x3);
9469
0
      int idx = idx_align >> (size + 1);
9470
0
                        int length = ((given >> 8) & 3) + 1;
9471
0
                        int stride = 1;
9472
0
                        int i;
9473
9474
0
                        if (length > 1 && size > 0)
9475
0
                          stride = (idx_align & (1 << size)) ? 2 : 1;
9476
9477
0
                        switch (length)
9478
0
                          {
9479
0
                          case 1:
9480
0
                            {
9481
0
                              int amask = (1 << size) - 1;
9482
0
                              if ((idx_align & (1 << size)) != 0)
9483
0
                                return false;
9484
0
                              if (size > 0)
9485
0
                                {
9486
0
                                  if ((idx_align & amask) == amask)
9487
0
                                    align = 8 << size;
9488
0
                                  else if ((idx_align & amask) != 0)
9489
0
                                    return false;
9490
0
                                }
9491
0
                              }
9492
0
                            break;
9493
9494
0
                          case 2:
9495
0
                            if (size == 2 && (idx_align & 2) != 0)
9496
0
                              return false;
9497
0
                            align = (idx_align & 1) ? 16 << size : 0;
9498
0
                            break;
9499
9500
0
                          case 3:
9501
0
                            if ((size == 2 && (idx_align & 3) != 0)
9502
0
                                || (idx_align & 1) != 0)
9503
0
                              return false;
9504
0
                            break;
9505
9506
0
                          case 4:
9507
0
                            if (size == 2)
9508
0
                              {
9509
0
                                if ((idx_align & 3) == 3)
9510
0
                                  return false;
9511
0
                                align = (idx_align & 3) * 64;
9512
0
                              }
9513
0
                            else
9514
0
                              align = (idx_align & 1) ? 32 << size : 0;
9515
0
                            break;
9516
9517
0
                          default:
9518
0
                            abort ();
9519
0
                          }
9520
9521
0
      func (stream, dis_style_text, "{");
9522
0
                        for (i = 0; i < length; i++)
9523
0
        {
9524
0
          if (i > 0)
9525
0
            func (stream, dis_style_text, ",");
9526
0
          func (stream, dis_style_register, "d%d[%d]",
9527
0
          rd + i * stride, idx);
9528
0
        }
9529
0
      func (stream, dis_style_text, "}, [");
9530
0
      func (stream, dis_style_register, "%s",
9531
0
            arm_regnames[rn]);
9532
0
      if (align)
9533
0
        {
9534
0
          func (stream, dis_style_text, " :");
9535
0
          func (stream, dis_style_immediate, "%d", align);
9536
0
        }
9537
0
      func (stream, dis_style_text, "]");
9538
0
      if (rm == 0xd)
9539
0
        func (stream, dis_style_text, "!");
9540
0
      else if (rm != 0xf)
9541
0
        {
9542
0
          func (stream, dis_style_text, ", ");
9543
0
          func (stream, dis_style_register, "%s",
9544
0
          arm_regnames[rm]);
9545
0
        }
9546
0
          }
9547
0
          break;
9548
9549
0
        case 'C':
9550
0
          {
9551
0
      int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
9552
0
      int rn = ((given >> 16) & 0xf);
9553
0
      int rm = ((given >> 0) & 0xf);
9554
0
      int align = ((given >> 4) & 0x1);
9555
0
      int size = ((given >> 6) & 0x3);
9556
0
      int type = ((given >> 8) & 0x3);
9557
0
      int n = type + 1;
9558
0
      int stride = ((given >> 5) & 0x1);
9559
0
      int ix;
9560
9561
0
      if (stride && (n == 1))
9562
0
        n++;
9563
0
      else
9564
0
        stride++;
9565
9566
0
      func (stream, dis_style_text, "{");
9567
0
      if (stride > 1)
9568
0
        for (ix = 0; ix != n; ix++)
9569
0
          {
9570
0
            if (ix > 0)
9571
0
        func (stream, dis_style_text, ",");
9572
0
            func (stream, dis_style_register, "d%d[]",
9573
0
            rd + ix * stride);
9574
0
          }
9575
0
      else if (n == 1)
9576
0
        func (stream, dis_style_register, "d%d[]", rd);
9577
0
      else
9578
0
        {
9579
0
          func (stream, dis_style_register, "d%d[]", rd);
9580
0
          func (stream, dis_style_text, "-");
9581
0
          func (stream, dis_style_register, "d%d[]",
9582
0
          rd + n - 1);
9583
0
        }
9584
0
      func (stream, dis_style_text, "}, [");
9585
0
      func (stream, dis_style_register, "%s",
9586
0
            arm_regnames[rn]);
9587
0
      if (align)
9588
0
        {
9589
0
                            align = (8 * (type + 1)) << size;
9590
0
                            if (type == 3)
9591
0
                              align = (size > 1) ? align >> 1 : align;
9592
0
          if (type == 2 || (type == 0 && !size))
9593
0
            func (stream, dis_style_text,
9594
0
            " :<bad align %d>", align);
9595
0
          else
9596
0
            {
9597
0
        func (stream, dis_style_text, " :");
9598
0
        func (stream, dis_style_immediate,
9599
0
              "%d", align);
9600
0
            }
9601
0
        }
9602
0
      func (stream, dis_style_text, "]");
9603
0
      if (rm == 0xd)
9604
0
        func (stream, dis_style_text, "!");
9605
0
      else if (rm != 0xf)
9606
0
        {
9607
0
          func (stream, dis_style_text, ", ");
9608
0
          func (stream, dis_style_register, "%s",
9609
0
          arm_regnames[rm]);
9610
0
        }
9611
0
          }
9612
0
          break;
9613
9614
0
        case 'D':
9615
0
          {
9616
0
      int raw_reg = (given & 0xf) | ((given >> 1) & 0x10);
9617
0
      int size = (given >> 20) & 3;
9618
0
      int reg = raw_reg & ((4 << size) - 1);
9619
0
      int ix = raw_reg >> size >> 2;
9620
9621
0
      func (stream, dis_style_register, "d%d[%d]", reg, ix);
9622
0
          }
9623
0
          break;
9624
9625
0
        case 'E':
9626
          /* Neon encoded constant for mov, mvn, vorr, vbic.  */
9627
0
          {
9628
0
      int bits = 0;
9629
0
      int cmode = (given >> 8) & 0xf;
9630
0
      int op = (given >> 5) & 0x1;
9631
0
      unsigned long value = 0, hival = 0;
9632
0
      unsigned shift;
9633
0
                        int size = 0;
9634
0
                        int isfloat = 0;
9635
9636
0
      bits |= ((given >> 24) & 1) << 7;
9637
0
      bits |= ((given >> 16) & 7) << 4;
9638
0
      bits |= ((given >> 0) & 15) << 0;
9639
9640
0
      if (cmode < 8)
9641
0
        {
9642
0
          shift = (cmode >> 1) & 3;
9643
0
          value = (unsigned long) bits << (8 * shift);
9644
0
                            size = 32;
9645
0
        }
9646
0
      else if (cmode < 12)
9647
0
        {
9648
0
          shift = (cmode >> 1) & 1;
9649
0
          value = (unsigned long) bits << (8 * shift);
9650
0
                            size = 16;
9651
0
        }
9652
0
      else if (cmode < 14)
9653
0
        {
9654
0
          shift = (cmode & 1) + 1;
9655
0
          value = (unsigned long) bits << (8 * shift);
9656
0
          value |= (1ul << (8 * shift)) - 1;
9657
0
                            size = 32;
9658
0
        }
9659
0
      else if (cmode == 14)
9660
0
        {
9661
0
          if (op)
9662
0
            {
9663
        /* Bit replication into bytes.  */
9664
0
        int ix;
9665
0
        unsigned long mask;
9666
9667
0
        value = 0;
9668
0
                                hival = 0;
9669
0
        for (ix = 7; ix >= 0; ix--)
9670
0
          {
9671
0
            mask = ((bits >> ix) & 1) ? 0xff : 0;
9672
0
                                    if (ix <= 3)
9673
0
              value = (value << 8) | mask;
9674
0
                                    else
9675
0
                                      hival = (hival << 8) | mask;
9676
0
          }
9677
0
                                size = 64;
9678
0
            }
9679
0
                            else
9680
0
                              {
9681
                                /* Byte replication.  */
9682
0
                                value = (unsigned long) bits;
9683
0
                                size = 8;
9684
0
                              }
9685
0
        }
9686
0
      else if (!op)
9687
0
        {
9688
          /* Floating point encoding.  */
9689
0
          int tmp;
9690
9691
0
          value = (unsigned long)  (bits & 0x7f) << 19;
9692
0
          value |= (unsigned long) (bits & 0x80) << 24;
9693
0
          tmp = bits & 0x40 ? 0x3c : 0x40;
9694
0
          value |= (unsigned long) tmp << 24;
9695
0
                            size = 32;
9696
0
                            isfloat = 1;
9697
0
        }
9698
0
      else
9699
0
        {
9700
0
          func (stream, dis_style_text,
9701
0
          "<illegal constant %.8x:%x:%x>",
9702
0
                                  bits, cmode, op);
9703
0
                            size = 32;
9704
0
          break;
9705
0
        }
9706
0
                        switch (size)
9707
0
                          {
9708
0
                          case 8:
9709
0
          func (stream, dis_style_immediate, "#%ld", value);
9710
0
          func (stream, dis_style_comment_start,
9711
0
          "\t@ 0x%.2lx", value);
9712
0
                            break;
9713
9714
0
                          case 16:
9715
0
          func (stream, dis_style_immediate, "#%ld", value);
9716
0
          func (stream, dis_style_comment_start,
9717
0
          "\t@ 0x%.4lx", value);
9718
0
                            break;
9719
9720
0
                          case 32:
9721
0
                            if (isfloat)
9722
0
                              {
9723
0
                                unsigned char valbytes[4];
9724
0
                                double fvalue;
9725
9726
                                /* Do this a byte at a time so we don't have to
9727
                                   worry about the host's endianness.  */
9728
0
                                valbytes[0] = value & 0xff;
9729
0
                                valbytes[1] = (value >> 8) & 0xff;
9730
0
                                valbytes[2] = (value >> 16) & 0xff;
9731
0
                                valbytes[3] = (value >> 24) & 0xff;
9732
9733
0
                                floatformat_to_double
9734
0
                                  (& floatformat_ieee_single_little, valbytes,
9735
0
                                  & fvalue);
9736
9737
0
        func (stream, dis_style_immediate,
9738
0
              "#%.7g", fvalue);
9739
0
        func (stream, dis_style_comment_start,
9740
0
              "\t@ 0x%.8lx", value);
9741
0
                              }
9742
0
                            else
9743
0
            {
9744
0
        func (stream, dis_style_immediate, "#%ld",
9745
0
              (long) (((value & 0x80000000L) != 0)
9746
0
                ? value | ~0xffffffffL : value));
9747
0
        func (stream, dis_style_comment_start,
9748
0
              "\t@ 0x%.8lx", value);
9749
0
            }
9750
0
                            break;
9751
9752
0
                          case 64:
9753
0
          func (stream, dis_style_immediate,
9754
0
          "#0x%.8lx%.8lx", hival, value);
9755
0
                            break;
9756
9757
0
                          default:
9758
0
                            abort ();
9759
0
                          }
9760
0
          }
9761
0
          break;
9762
9763
0
        case 'F':
9764
0
          {
9765
0
      int regno = ((given >> 16) & 0xf) | ((given >> (7 - 4)) & 0x10);
9766
0
      int num = (given >> 8) & 0x3;
9767
9768
0
      func (stream, dis_style_text, "{");
9769
0
      if (!num)
9770
0
        func (stream, dis_style_register, "d%d", regno);
9771
0
      else if (num + regno >= 32)
9772
0
        {
9773
0
          func (stream, dis_style_register, "d%d", regno);
9774
0
          func (stream, dis_style_text, "-<overflow reg d%d",
9775
0
          regno + num);
9776
0
        }
9777
0
      else
9778
0
        {
9779
0
          func (stream, dis_style_register, "d%d", regno);
9780
0
          func (stream, dis_style_text, "-");
9781
0
          func (stream, dis_style_register, "d%d",
9782
0
          regno + num);
9783
0
        }
9784
0
      func (stream, dis_style_text, "}");
9785
0
          }
9786
0
          break;
9787
9788
9789
0
        case '0': case '1': case '2': case '3': case '4':
9790
0
        case '5': case '6': case '7': case '8': case '9':
9791
0
          {
9792
0
      int width;
9793
0
      unsigned long value;
9794
9795
0
      c = arm_decode_bitfield (c, given, &value, &width);
9796
9797
0
      switch (*c)
9798
0
        {
9799
0
        case 'r':
9800
0
          func (stream, dis_style_register, "%s",
9801
0
          arm_regnames[value]);
9802
0
          break;
9803
0
        case 'd':
9804
0
          func (stream, base_style, "%ld", value);
9805
0
          value_in_comment = value;
9806
0
          break;
9807
0
        case 'e':
9808
0
          func (stream, dis_style_immediate, "%ld",
9809
0
          (1ul << width) - value);
9810
0
          break;
9811
9812
0
        case 'S':
9813
0
        case 'T':
9814
0
        case 'U':
9815
          /* Various width encodings.  */
9816
0
          {
9817
0
            int base = 8 << (*c - 'S'); /* 8,16 or 32 */
9818
0
            int limit;
9819
0
            unsigned low, high;
9820
9821
0
            c++;
9822
0
            if (*c >= '0' && *c <= '9')
9823
0
        limit = *c - '0';
9824
0
            else if (*c >= 'a' && *c <= 'f')
9825
0
        limit = *c - 'a' + 10;
9826
0
            else
9827
0
        abort ();
9828
0
            low = limit >> 2;
9829
0
            high = limit & 3;
9830
9831
0
            if (value < low || value > high)
9832
0
        func (stream, dis_style_text,
9833
0
              "<illegal width %d>", base << value);
9834
0
            else
9835
0
        func (stream, base_style, "%d",
9836
0
              base << value);
9837
0
          }
9838
0
          break;
9839
0
        case 'R':
9840
0
          if (given & (1 << 6))
9841
0
            goto Q;
9842
          /* FALLTHROUGH */
9843
0
        case 'D':
9844
0
          func (stream, dis_style_register, "d%ld", value);
9845
0
          break;
9846
0
        case 'Q':
9847
0
        Q:
9848
0
          if (value & 1)
9849
0
            func (stream, dis_style_text,
9850
0
            "<illegal reg q%ld.5>", value >> 1);
9851
0
          else
9852
0
            func (stream, dis_style_register,
9853
0
            "q%ld", value >> 1);
9854
0
          break;
9855
9856
0
        case '`':
9857
0
          c++;
9858
0
          if (value == 0)
9859
0
            func (stream, dis_style_text, "%c", *c);
9860
0
          break;
9861
0
        case '\'':
9862
0
          c++;
9863
0
          if (value == ((1ul << width) - 1))
9864
0
            func (stream, dis_style_text, "%c", *c);
9865
0
          break;
9866
0
        case '?':
9867
0
          func (stream, dis_style_mnemonic, "%c",
9868
0
          c[(1 << width) - (int) value]);
9869
0
          c += 1 << width;
9870
0
          break;
9871
0
        default:
9872
0
          abort ();
9873
0
        }
9874
0
          }
9875
0
          break;
9876
9877
0
        default:
9878
0
          abort ();
9879
0
        }
9880
0
    }
9881
0
        else
9882
0
    {
9883
0
      if (*c == '@')
9884
0
        base_style = dis_style_comment_start;
9885
9886
0
      if (*c == '\t')
9887
0
        base_style = dis_style_text;
9888
9889
0
      func (stream, base_style, "%c", *c);
9890
9891
0
    }
9892
0
      }
9893
9894
0
    if (value_in_comment > 32 || value_in_comment < -16)
9895
0
      func (stream, dis_style_comment_start, "\t@ 0x%lx",
9896
0
      value_in_comment);
9897
9898
0
    if (is_unpredictable)
9899
0
      func (stream, dis_style_comment_start, UNPREDICTABLE_INSTRUCTION);
9900
9901
0
    return true;
9902
0
  }
9903
0
    }
9904
0
  return false;
9905
0
}
9906
9907
/* Print one mve instruction on INFO->STREAM.
9908
   Return TRUE if the instuction matched, FALSE if this is not a
9909
   recognised mve instruction.  */
9910
9911
static bool
9912
print_insn_mve (struct disassemble_info *info, long given)
9913
0
{
9914
0
  const struct mopcode32 *insn;
9915
0
  void *stream = info->stream;
9916
0
  fprintf_styled_ftype func = info->fprintf_styled_func;
9917
0
  enum disassembler_style base_style = dis_style_mnemonic;
9918
0
  enum disassembler_style old_base_style = base_style;
9919
9920
0
  for (insn = mve_opcodes; insn->assembler; insn++)
9921
0
    {
9922
0
      if (((given & insn->mask) == insn->value)
9923
0
    && !is_mve_encoding_conflict (given, insn->mve_op))
9924
0
  {
9925
0
    signed long value_in_comment = 0;
9926
0
    bool is_unpredictable = false;
9927
0
    bool is_undefined = false;
9928
0
    const char *c;
9929
0
    enum mve_unpredictable unpredictable_cond = UNPRED_NONE;
9930
0
    enum mve_undefined undefined_cond = UNDEF_NONE;
9931
9932
    /* Most vector mve instruction are illegal in a it block.
9933
       There are a few exceptions; check for them.  */
9934
0
    if (ifthen_state && !is_mve_okay_in_it (insn->mve_op))
9935
0
      {
9936
0
        is_unpredictable = true;
9937
0
        unpredictable_cond = UNPRED_IT_BLOCK;
9938
0
      }
9939
0
    else if (is_mve_unpredictable (given, insn->mve_op,
9940
0
           &unpredictable_cond))
9941
0
      is_unpredictable = true;
9942
9943
0
    if (is_mve_undefined (given, insn->mve_op, &undefined_cond))
9944
0
      is_undefined = true;
9945
9946
    /* In "VORR Qd, Qm, Qn", if Qm==Qn, VORR is nothing but VMOV,
9947
       i.e "VMOV Qd, Qm".  */
9948
0
    if ((insn->mve_op == MVE_VORR_REG)
9949
0
        && (arm_decode_field (given, 1, 3)
9950
0
      == arm_decode_field (given, 17, 19)))
9951
0
      continue;
9952
9953
0
    for (c = insn->assembler; *c; c++)
9954
0
      {
9955
0
        if (*c == '%')
9956
0
    {
9957
0
      switch (*++c)
9958
0
        {
9959
0
        case '{':
9960
0
          ++c;
9961
0
          if (*c == '\0')
9962
0
      abort ();
9963
0
          old_base_style = base_style;
9964
0
          base_style = decode_base_style (*c);
9965
0
          ++c;
9966
0
          if (*c != ':')
9967
0
      abort ();
9968
0
          break;
9969
9970
0
        case '}':
9971
0
          base_style = old_base_style;
9972
0
          break;
9973
9974
0
        case '%':
9975
0
          func (stream, base_style, "%%");
9976
0
          break;
9977
9978
0
        case 'a':
9979
          /* Don't print anything for '+' as it is implied.  */
9980
0
          if (arm_decode_field (given, 23, 23) == 0)
9981
0
      func (stream, dis_style_immediate, "-");
9982
0
          break;
9983
9984
0
        case 'c':
9985
0
          if (ifthen_state)
9986
0
      func (stream, dis_style_mnemonic, "%s",
9987
0
            arm_conditional[IFTHEN_COND]);
9988
0
          break;
9989
9990
0
        case 'd':
9991
0
          print_mve_vld_str_addr (info, given, insn->mve_op);
9992
0
          break;
9993
9994
0
        case 'i':
9995
0
          {
9996
0
      long mve_mask = mve_extract_pred_mask (given);
9997
0
      func (stream, dis_style_mnemonic, "%s",
9998
0
            mve_predicatenames[mve_mask]);
9999
0
          }
10000
0
          break;
10001
10002
0
        case 'j':
10003
0
          {
10004
0
      unsigned int imm5 = 0;
10005
0
      imm5 |= arm_decode_field (given, 6, 7);
10006
0
      imm5 |= (arm_decode_field (given, 12, 14) << 2);
10007
0
      func (stream, dis_style_immediate, "#%u",
10008
0
            (imm5 == 0) ? 32 : imm5);
10009
0
          }
10010
0
          break;
10011
10012
0
        case 'k':
10013
0
          func (stream, dis_style_immediate, "#%u",
10014
0
          (arm_decode_field (given, 7, 7) == 0) ? 64 : 48);
10015
0
          break;
10016
10017
0
        case 'n':
10018
0
          print_vec_condition (info, given, insn->mve_op);
10019
0
          break;
10020
10021
0
        case 'o':
10022
0
          if (arm_decode_field (given, 0, 0) == 1)
10023
0
      {
10024
0
        unsigned long size
10025
0
          = arm_decode_field (given, 4, 4)
10026
0
            | (arm_decode_field (given, 6, 6) << 1);
10027
10028
0
        func (stream, dis_style_text, ", ");
10029
0
        func (stream, dis_style_sub_mnemonic, "uxtw ");
10030
0
        func (stream, dis_style_immediate, "#%lu", size);
10031
0
      }
10032
0
          break;
10033
10034
0
        case 'm':
10035
0
          print_mve_rounding_mode (info, given, insn->mve_op);
10036
0
          break;
10037
10038
0
        case 's':
10039
0
          print_mve_vcvt_size (info, given, insn->mve_op);
10040
0
          break;
10041
10042
0
        case 'u':
10043
0
          {
10044
0
      unsigned long op1 = arm_decode_field (given, 21, 22);
10045
10046
0
      if ((insn->mve_op == MVE_VMOV_VEC_LANE_TO_GP))
10047
0
        {
10048
          /* Check for signed.  */
10049
0
          if (arm_decode_field (given, 23, 23) == 0)
10050
0
            {
10051
        /* We don't print 's' for S32.  */
10052
0
        if ((arm_decode_field (given, 5, 6) == 0)
10053
0
            && ((op1 == 0) || (op1 == 1)))
10054
0
          ;
10055
0
        else
10056
0
          func (stream, dis_style_mnemonic, "s");
10057
0
            }
10058
0
          else
10059
0
            func (stream, dis_style_mnemonic, "u");
10060
0
        }
10061
0
      else
10062
0
        {
10063
0
          if (arm_decode_field (given, 28, 28) == 0)
10064
0
            func (stream, dis_style_mnemonic, "s");
10065
0
          else
10066
0
            func (stream, dis_style_mnemonic, "u");
10067
0
        }
10068
0
          }
10069
0
          break;
10070
10071
0
        case 'v':
10072
0
          print_instruction_predicate (info);
10073
0
          break;
10074
10075
0
        case 'w':
10076
0
          if (arm_decode_field (given, 21, 21) == 1)
10077
0
      func (stream, dis_style_text, "!");
10078
0
          break;
10079
10080
0
        case 'B':
10081
0
          print_mve_register_blocks (info, given, insn->mve_op);
10082
0
          break;
10083
10084
0
        case 'E':
10085
          /* SIMD encoded constant for mov, mvn, vorr, vbic.  */
10086
10087
0
          print_simd_imm8 (info, given, 28, insn);
10088
0
          break;
10089
10090
0
        case 'N':
10091
0
          print_mve_vmov_index (info, given);
10092
0
          break;
10093
10094
0
        case 'T':
10095
0
          if (arm_decode_field (given, 12, 12) == 0)
10096
0
      func (stream, dis_style_mnemonic, "b");
10097
0
          else
10098
0
      func (stream, dis_style_mnemonic, "t");
10099
0
          break;
10100
10101
0
        case 'X':
10102
0
          if (arm_decode_field (given, 12, 12) == 1)
10103
0
      func (stream, dis_style_mnemonic, "x");
10104
0
          break;
10105
10106
0
        case '0': case '1': case '2': case '3': case '4':
10107
0
        case '5': case '6': case '7': case '8': case '9':
10108
0
          {
10109
0
      int width;
10110
0
      unsigned long value;
10111
10112
0
      c = arm_decode_bitfield (c, given, &value, &width);
10113
10114
0
      switch (*c)
10115
0
        {
10116
0
        case 'Z':
10117
0
          if (value == 13)
10118
0
            is_unpredictable = true;
10119
0
          else if (value == 15)
10120
0
            func (stream, dis_style_register, "zr");
10121
0
          else
10122
0
            func (stream, dis_style_register, "%s",
10123
0
            arm_regnames[value]);
10124
0
          break;
10125
10126
0
        case 'c':
10127
0
          func (stream, dis_style_sub_mnemonic, "%s",
10128
0
          arm_conditional[value]);
10129
0
          break;
10130
10131
0
        case 'C':
10132
0
          value ^= 1;
10133
0
          func (stream, dis_style_sub_mnemonic, "%s",
10134
0
          arm_conditional[value]);
10135
0
          break;
10136
10137
0
        case 'S':
10138
0
          if (value == 13 || value == 15)
10139
0
            is_unpredictable = true;
10140
0
          else
10141
0
            func (stream, dis_style_register, "%s",
10142
0
            arm_regnames[value]);
10143
0
          break;
10144
10145
0
        case 's':
10146
0
          print_mve_size (info,
10147
0
              value,
10148
0
              insn->mve_op);
10149
0
          break;
10150
0
        case 'I':
10151
0
          if (value == 1)
10152
0
            func (stream, dis_style_mnemonic, "i");
10153
0
          break;
10154
0
        case 'A':
10155
0
          if (value == 1)
10156
0
            func (stream, dis_style_mnemonic, "a");
10157
0
          break;
10158
0
        case 'h':
10159
0
          {
10160
0
            unsigned int odd_reg = (value << 1) | 1;
10161
0
            func (stream, dis_style_register, "%s",
10162
0
            arm_regnames[odd_reg]);
10163
0
          }
10164
0
          break;
10165
0
        case 'i':
10166
0
          {
10167
0
            unsigned long imm
10168
0
        = arm_decode_field (given, 0, 6);
10169
0
            unsigned long mod_imm = imm;
10170
10171
0
            switch (insn->mve_op)
10172
0
        {
10173
0
        case MVE_VLDRW_GATHER_T5:
10174
0
        case MVE_VSTRW_SCATTER_T5:
10175
0
          mod_imm = mod_imm << 2;
10176
0
          break;
10177
0
        case MVE_VSTRD_SCATTER_T6:
10178
0
        case MVE_VLDRD_GATHER_T6:
10179
0
          mod_imm = mod_imm << 3;
10180
0
          break;
10181
10182
0
        default:
10183
0
          break;
10184
0
        }
10185
10186
0
            func (stream, dis_style_immediate, "%lu",
10187
0
            mod_imm);
10188
0
          }
10189
0
          break;
10190
0
        case 'k':
10191
0
          func (stream, dis_style_immediate, "%lu",
10192
0
          64 - value);
10193
0
          break;
10194
0
        case 'l':
10195
0
          {
10196
0
            unsigned int even_reg = value << 1;
10197
0
            func (stream, dis_style_register, "%s",
10198
0
            arm_regnames[even_reg]);
10199
0
          }
10200
0
          break;
10201
0
        case 'u':
10202
0
          switch (value)
10203
0
            {
10204
0
            case 0:
10205
0
        func (stream, dis_style_immediate, "1");
10206
0
        break;
10207
0
            case 1:
10208
0
        func (stream, dis_style_immediate, "2");
10209
0
        break;
10210
0
            case 2:
10211
0
        func (stream, dis_style_immediate, "4");
10212
0
        break;
10213
0
            case 3:
10214
0
        func (stream, dis_style_immediate, "8");
10215
0
        break;
10216
0
            default:
10217
0
        break;
10218
0
            }
10219
0
          break;
10220
0
        case 'o':
10221
0
          print_mve_rotate (info, value, width);
10222
0
          break;
10223
0
        case 'r':
10224
0
          func (stream, dis_style_register, "%s",
10225
0
          arm_regnames[value]);
10226
0
          break;
10227
0
        case 'd':
10228
0
          if (insn->mve_op == MVE_VQSHL_T2
10229
0
        || insn->mve_op == MVE_VQSHLU_T3
10230
0
        || insn->mve_op == MVE_VRSHR
10231
0
        || insn->mve_op == MVE_VRSHRN
10232
0
        || insn->mve_op == MVE_VSHL_T1
10233
0
        || insn->mve_op == MVE_VSHLL_T1
10234
0
        || insn->mve_op == MVE_VSHR
10235
0
        || insn->mve_op == MVE_VSHRN
10236
0
        || insn->mve_op == MVE_VSLI
10237
0
        || insn->mve_op == MVE_VSRI)
10238
0
            print_mve_shift_n (info, given, insn->mve_op);
10239
0
          else if (insn->mve_op == MVE_VSHLL_T2)
10240
0
            {
10241
0
        switch (value)
10242
0
          {
10243
0
          case 0x00:
10244
0
            func (stream, dis_style_immediate, "8");
10245
0
            break;
10246
0
          case 0x01:
10247
0
            func (stream, dis_style_immediate, "16");
10248
0
            break;
10249
0
          case 0x10:
10250
0
            print_mve_undefined (info, UNDEF_SIZE_0);
10251
0
            break;
10252
0
          default:
10253
0
            assert (0);
10254
0
            break;
10255
0
          }
10256
0
            }
10257
0
          else
10258
0
            {
10259
0
        if (insn->mve_op == MVE_VSHLC && value == 0)
10260
0
          value = 32;
10261
0
        func (stream, base_style, "%ld", value);
10262
0
        value_in_comment = value;
10263
0
            }
10264
0
          break;
10265
0
        case 'F':
10266
0
          func (stream, dis_style_register, "s%ld", value);
10267
0
          break;
10268
0
        case 'Q':
10269
0
          if (value & 0x8)
10270
0
            func (stream, dis_style_text,
10271
0
            "<illegal reg q%ld.5>", value);
10272
0
          else
10273
0
            func (stream, dis_style_register, "q%ld", value);
10274
0
          break;
10275
0
        case 'x':
10276
0
          func (stream, dis_style_immediate,
10277
0
          "0x%08lx", value);
10278
0
          break;
10279
0
        default:
10280
0
          abort ();
10281
0
        }
10282
0
      break;
10283
0
          default:
10284
0
      abort ();
10285
0
          }
10286
0
        }
10287
0
    }
10288
0
        else
10289
0
    {
10290
0
      if (*c == '@')
10291
0
        base_style = dis_style_comment_start;
10292
10293
0
      if (*c == '\t')
10294
0
        base_style = dis_style_text;
10295
10296
0
      func (stream, base_style, "%c", *c);
10297
0
    }
10298
0
      }
10299
10300
0
    if (value_in_comment > 32 || value_in_comment < -16)
10301
0
      func (stream, dis_style_comment_start, "\t@ 0x%lx",
10302
0
      value_in_comment);
10303
10304
0
    if (is_unpredictable)
10305
0
      print_mve_unpredictable (info, unpredictable_cond);
10306
10307
0
    if (is_undefined)
10308
0
      print_mve_undefined (info, undefined_cond);
10309
10310
0
    if (!vpt_block_state.in_vpt_block
10311
0
        && !ifthen_state
10312
0
        && is_vpt_instruction (given))
10313
0
      mark_inside_vpt_block (given);
10314
0
    else if (vpt_block_state.in_vpt_block)
10315
0
      update_vpt_block_state ();
10316
10317
0
    return true;
10318
0
  }
10319
0
    }
10320
0
  return false;
10321
0
}
10322
10323
10324
/* Return the name of a v7A special register.  */
10325
10326
static const char *
10327
banked_regname (unsigned reg)
10328
0
{
10329
0
  switch (reg)
10330
0
    {
10331
0
      case 15: return "CPSR";
10332
0
      case 32: return "R8_usr";
10333
0
      case 33: return "R9_usr";
10334
0
      case 34: return "R10_usr";
10335
0
      case 35: return "R11_usr";
10336
0
      case 36: return "R12_usr";
10337
0
      case 37: return "SP_usr";
10338
0
      case 38: return "LR_usr";
10339
0
      case 40: return "R8_fiq";
10340
0
      case 41: return "R9_fiq";
10341
0
      case 42: return "R10_fiq";
10342
0
      case 43: return "R11_fiq";
10343
0
      case 44: return "R12_fiq";
10344
0
      case 45: return "SP_fiq";
10345
0
      case 46: return "LR_fiq";
10346
0
      case 48: return "LR_irq";
10347
0
      case 49: return "SP_irq";
10348
0
      case 50: return "LR_svc";
10349
0
      case 51: return "SP_svc";
10350
0
      case 52: return "LR_abt";
10351
0
      case 53: return "SP_abt";
10352
0
      case 54: return "LR_und";
10353
0
      case 55: return "SP_und";
10354
0
      case 60: return "LR_mon";
10355
0
      case 61: return "SP_mon";
10356
0
      case 62: return "ELR_hyp";
10357
0
      case 63: return "SP_hyp";
10358
0
      case 79: return "SPSR";
10359
0
      case 110: return "SPSR_fiq";
10360
0
      case 112: return "SPSR_irq";
10361
0
      case 114: return "SPSR_svc";
10362
0
      case 116: return "SPSR_abt";
10363
0
      case 118: return "SPSR_und";
10364
0
      case 124: return "SPSR_mon";
10365
0
      case 126: return "SPSR_hyp";
10366
0
      default: return NULL;
10367
0
    }
10368
0
}
10369
10370
/* Return the name of the DMB/DSB option.  */
10371
static const char *
10372
data_barrier_option (unsigned option)
10373
0
{
10374
0
  switch (option & 0xf)
10375
0
    {
10376
0
    case 0xf: return "sy";
10377
0
    case 0xe: return "st";
10378
0
    case 0xd: return "ld";
10379
0
    case 0xb: return "ish";
10380
0
    case 0xa: return "ishst";
10381
0
    case 0x9: return "ishld";
10382
0
    case 0x7: return "un";
10383
0
    case 0x6: return "unst";
10384
0
    case 0x5: return "nshld";
10385
0
    case 0x3: return "osh";
10386
0
    case 0x2: return "oshst";
10387
0
    case 0x1: return "oshld";
10388
0
    default:  return NULL;
10389
0
    }
10390
0
}
10391
10392
/* Print one ARM instruction from PC on INFO->STREAM.  */
10393
10394
static void
10395
print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
10396
0
{
10397
0
  const struct opcode32 *insn;
10398
0
  void *stream = info->stream;
10399
0
  fprintf_styled_ftype func = info->fprintf_styled_func;
10400
0
  struct arm_private_data *private_data = info->private_data;
10401
0
  enum disassembler_style base_style = dis_style_mnemonic;
10402
0
  enum disassembler_style old_base_style = base_style;
10403
10404
0
  if (print_insn_coprocessor (pc, info, given, false))
10405
0
    return;
10406
10407
0
  if (print_insn_neon (info, given, false))
10408
0
    return;
10409
10410
0
  if (print_insn_generic_coprocessor (pc, info, given, false))
10411
0
    return;
10412
10413
0
  for (insn = arm_opcodes; insn->assembler; insn++)
10414
0
    {
10415
0
      if ((given & insn->mask) != insn->value)
10416
0
  continue;
10417
10418
0
      if (! ARM_CPU_HAS_FEATURE (insn->arch, private_data->features))
10419
0
  continue;
10420
10421
      /* Special case: an instruction with all bits set in the condition field
10422
   (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
10423
   or by the catchall at the end of the table.  */
10424
0
      if ((given & 0xF0000000) != 0xF0000000
10425
0
    || (insn->mask & 0xF0000000) == 0xF0000000
10426
0
    || (insn->mask == 0 && insn->value == 0))
10427
0
  {
10428
0
    unsigned long u_reg = 16;
10429
0
    unsigned long U_reg = 16;
10430
0
    bool is_unpredictable = false;
10431
0
    signed long value_in_comment = 0;
10432
0
    const char *c;
10433
10434
0
    for (c = insn->assembler; *c; c++)
10435
0
      {
10436
0
        if (*c == '%')
10437
0
    {
10438
0
      bool allow_unpredictable = false;
10439
10440
0
      switch (*++c)
10441
0
        {
10442
0
        case '{':
10443
0
          ++c;
10444
0
          if (*c == '\0')
10445
0
      abort ();
10446
0
          old_base_style = base_style;
10447
0
          base_style = decode_base_style (*c);
10448
0
          ++c;
10449
0
          if (*c != ':')
10450
0
      abort ();
10451
0
          break;
10452
10453
0
        case '}':
10454
0
          base_style = old_base_style;
10455
0
          break;
10456
10457
0
        case '%':
10458
0
          func (stream, base_style, "%%");
10459
0
          break;
10460
10461
0
        case 'a':
10462
0
          value_in_comment = print_arm_address (pc, info, given);
10463
0
          break;
10464
10465
0
        case 'P':
10466
          /* Set P address bit and use normal address
10467
       printing routine.  */
10468
0
          value_in_comment = print_arm_address (pc, info, given | (1 << P_BIT));
10469
0
          break;
10470
10471
0
        case 'S':
10472
0
          allow_unpredictable = true;
10473
          /* Fall through.  */
10474
0
        case 's':
10475
0
                      if ((given & 0x004f0000) == 0x004f0000)
10476
0
      {
10477
                          /* PC relative with immediate offset.  */
10478
0
        bfd_vma offset = ((given & 0xf00) >> 4) | (given & 0xf);
10479
10480
0
        if (PRE_BIT_SET)
10481
0
          {
10482
            /* Elide positive zero offset.  */
10483
0
            if (offset || NEGATIVE_BIT_SET)
10484
0
        {
10485
0
          func (stream, dis_style_text, "[");
10486
0
          func (stream, dis_style_register, "pc");
10487
0
          func (stream, dis_style_text, ", ");
10488
0
          func (stream, dis_style_immediate, "#%s%d",
10489
0
          (NEGATIVE_BIT_SET ? "-" : ""),
10490
0
          (int) offset);
10491
0
          func (stream, dis_style_text, "]");
10492
0
        }
10493
0
            else
10494
0
        {
10495
0
          func (stream, dis_style_text, "[");
10496
0
          func (stream, dis_style_register, "pc");
10497
0
          func (stream, dis_style_text, "]");
10498
0
        }
10499
0
            if (NEGATIVE_BIT_SET)
10500
0
        offset = -offset;
10501
0
            func (stream, dis_style_comment_start, "\t@ ");
10502
0
            info->print_address_func (offset + pc + 8, info);
10503
0
          }
10504
0
        else
10505
0
          {
10506
            /* Always show the offset.  */
10507
0
            func (stream, dis_style_text, "[");
10508
0
            func (stream, dis_style_register, "pc");
10509
0
            func (stream, dis_style_text, "], ");
10510
0
            func (stream, dis_style_immediate, "#%s%d",
10511
0
            NEGATIVE_BIT_SET ? "-" : "", (int) offset);
10512
0
            if (! allow_unpredictable)
10513
0
        is_unpredictable = true;
10514
0
          }
10515
0
      }
10516
0
          else
10517
0
      {
10518
0
        int offset = ((given & 0xf00) >> 4) | (given & 0xf);
10519
10520
0
        func (stream, dis_style_text, "[");
10521
0
        func (stream, dis_style_register, "%s",
10522
0
        arm_regnames[(given >> 16) & 0xf]);
10523
10524
0
        if (PRE_BIT_SET)
10525
0
          {
10526
0
            if (IMMEDIATE_BIT_SET)
10527
0
        {
10528
          /* Elide offset for non-writeback
10529
             positive zero.  */
10530
0
          if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET
10531
0
              || offset)
10532
0
            {
10533
0
              func (stream, dis_style_text, ", ");
10534
0
              func (stream, dis_style_immediate,
10535
0
              "#%s%d",
10536
0
              (NEGATIVE_BIT_SET ? "-" : ""),
10537
0
              offset);
10538
0
            }
10539
10540
0
          if (NEGATIVE_BIT_SET)
10541
0
            offset = -offset;
10542
10543
0
          value_in_comment = offset;
10544
0
        }
10545
0
            else
10546
0
        {
10547
          /* Register Offset or Register Pre-Indexed.  */
10548
0
          func (stream, dis_style_text, ", %s",
10549
0
          NEGATIVE_BIT_SET ? "-" : "");
10550
0
          func (stream, dis_style_register, "%s",
10551
0
          arm_regnames[given & 0xf]);
10552
10553
          /* Writing back to the register that is the source/
10554
             destination of the load/store is unpredictable.  */
10555
0
          if (! allow_unpredictable
10556
0
              && WRITEBACK_BIT_SET
10557
0
              && ((given & 0xf) == ((given >> 12) & 0xf)))
10558
0
            is_unpredictable = true;
10559
0
        }
10560
10561
0
            func (stream, dis_style_text, "]%s",
10562
0
            WRITEBACK_BIT_SET ? "!" : "");
10563
0
          }
10564
0
        else
10565
0
          {
10566
0
            if (IMMEDIATE_BIT_SET)
10567
0
        {
10568
          /* Immediate Post-indexed.  */
10569
          /* PR 10924: Offset must be printed, even if it is zero.  */
10570
0
          func (stream, dis_style_text, "], ");
10571
0
          func (stream, dis_style_immediate, "#%s%d",
10572
0
          NEGATIVE_BIT_SET ? "-" : "", offset);
10573
0
          if (NEGATIVE_BIT_SET)
10574
0
            offset = -offset;
10575
0
          value_in_comment = offset;
10576
0
        }
10577
0
            else
10578
0
        {
10579
          /* Register Post-indexed.  */
10580
0
          func (stream, dis_style_text, "], %s",
10581
0
          NEGATIVE_BIT_SET ? "-" : "");
10582
0
          func (stream, dis_style_register, "%s",
10583
0
          arm_regnames[given & 0xf]);
10584
10585
          /* Writing back to the register that is the source/
10586
             destination of the load/store is unpredictable.  */
10587
0
          if (! allow_unpredictable
10588
0
              && (given & 0xf) == ((given >> 12) & 0xf))
10589
0
            is_unpredictable = true;
10590
0
        }
10591
10592
0
            if (! allow_unpredictable)
10593
0
        {
10594
          /* Writeback is automatically implied by post- addressing.
10595
             Setting the W bit is unnecessary and ARM specify it as
10596
             being unpredictable.  */
10597
0
          if (WRITEBACK_BIT_SET
10598
              /* Specifying the PC register as the post-indexed
10599
           registers is also unpredictable.  */
10600
0
              || (! IMMEDIATE_BIT_SET && ((given & 0xf) == 0xf)))
10601
0
            is_unpredictable = true;
10602
0
        }
10603
0
          }
10604
0
      }
10605
0
          break;
10606
10607
0
        case 'b':
10608
0
          {
10609
0
      bfd_vma disp = (((given & 0xffffff) ^ 0x800000) - 0x800000);
10610
0
      bfd_vma target = disp * 4 + pc + 8;
10611
0
      info->print_address_func (target, info);
10612
10613
      /* Fill in instruction information.  */
10614
0
      info->insn_info_valid = 1;
10615
0
      info->insn_type = dis_branch;
10616
0
      info->target = target;
10617
0
          }
10618
0
          break;
10619
10620
0
        case 'c':
10621
0
          if (((given >> 28) & 0xf) != 0xe)
10622
0
      func (stream, dis_style_mnemonic, "%s",
10623
0
            arm_conditional [(given >> 28) & 0xf]);
10624
0
          break;
10625
10626
0
        case 'm':
10627
0
          {
10628
0
      int started = 0;
10629
0
      int reg;
10630
10631
0
      func (stream, dis_style_text, "{");
10632
0
      for (reg = 0; reg < 16; reg++)
10633
0
        if ((given & (1 << reg)) != 0)
10634
0
          {
10635
0
            if (started)
10636
0
        func (stream, dis_style_text, ", ");
10637
0
            started = 1;
10638
0
            func (stream, dis_style_register, "%s",
10639
0
            arm_regnames[reg]);
10640
0
          }
10641
0
      func (stream, dis_style_text, "}");
10642
0
      if (! started)
10643
0
        is_unpredictable = true;
10644
0
          }
10645
0
          break;
10646
10647
0
        case 'q':
10648
0
          arm_decode_shift (given, func, stream, false);
10649
0
          break;
10650
10651
0
        case 'o':
10652
0
          if ((given & 0x02000000) != 0)
10653
0
      {
10654
0
        unsigned int rotate = (given & 0xf00) >> 7;
10655
0
        unsigned int immed = (given & 0xff);
10656
0
        unsigned int a, i;
10657
10658
0
        a = (immed << ((32 - rotate) & 31)
10659
0
             | immed >> rotate) & 0xffffffff;
10660
        /* If there is another encoding with smaller rotate,
10661
           the rotate should be specified directly.  */
10662
0
        for (i = 0; i < 32; i += 2)
10663
0
          if ((a << i | a >> ((32 - i) & 31)) <= 0xff)
10664
0
            break;
10665
10666
0
        if (i != rotate)
10667
0
          {
10668
0
            func (stream, dis_style_immediate, "#%d", immed);
10669
0
            func (stream, dis_style_text, ", ");
10670
0
            func (stream, dis_style_immediate, "%d", rotate);
10671
0
          }
10672
0
        else
10673
0
          func (stream, dis_style_immediate, "#%d", a);
10674
0
        value_in_comment = a;
10675
0
      }
10676
0
          else
10677
0
      arm_decode_shift (given, func, stream, true);
10678
0
          break;
10679
10680
0
        case 'p':
10681
0
          if ((given & 0x0000f000) == 0x0000f000)
10682
0
      {
10683
0
        arm_feature_set arm_ext_v6 =
10684
0
          ARM_FEATURE_CORE_LOW (ARM_EXT_V6);
10685
10686
        /* The p-variants of tst/cmp/cmn/teq are the pre-V6
10687
           mechanism for setting PSR flag bits.  They are
10688
           obsolete in V6 onwards.  */
10689
0
        if (! ARM_CPU_HAS_FEATURE (private_data->features, \
10690
0
                 arm_ext_v6))
10691
0
          func (stream, dis_style_mnemonic, "p");
10692
0
        else
10693
0
          is_unpredictable = true;
10694
0
      }
10695
0
          break;
10696
10697
0
        case 't':
10698
0
          if ((given & 0x01200000) == 0x00200000)
10699
0
      func (stream, dis_style_mnemonic, "t");
10700
0
          break;
10701
10702
0
        case 'A':
10703
0
          {
10704
0
      int offset = given & 0xff;
10705
10706
0
      value_in_comment = offset * 4;
10707
0
      if (NEGATIVE_BIT_SET)
10708
0
        value_in_comment = - value_in_comment;
10709
10710
0
      func (stream, dis_style_text, "[%s",
10711
0
            arm_regnames [(given >> 16) & 0xf]);
10712
10713
0
      if (PRE_BIT_SET)
10714
0
        {
10715
0
          if (offset)
10716
0
            func (stream, dis_style_text, ", #%d]%s",
10717
0
            (int) value_in_comment,
10718
0
            WRITEBACK_BIT_SET ? "!" : "");
10719
0
          else
10720
0
            func (stream, dis_style_text, "]");
10721
0
        }
10722
0
      else
10723
0
        {
10724
0
          func (stream, dis_style_text, "]");
10725
10726
0
          if (WRITEBACK_BIT_SET)
10727
0
            {
10728
0
        if (offset)
10729
0
          func (stream, dis_style_text,
10730
0
          ", #%d", (int) value_in_comment);
10731
0
            }
10732
0
          else
10733
0
            {
10734
0
        func (stream, dis_style_text,
10735
0
              ", {%d}", (int) offset);
10736
0
        value_in_comment = offset;
10737
0
            }
10738
0
        }
10739
0
          }
10740
0
          break;
10741
10742
0
        case 'B':
10743
          /* Print ARM V5 BLX(1) address: pc+25 bits.  */
10744
0
          {
10745
0
      bfd_vma address;
10746
0
      bfd_vma offset = 0;
10747
10748
0
      if (! NEGATIVE_BIT_SET)
10749
        /* Is signed, hi bits should be ones.  */
10750
0
        offset = (-1) ^ 0x00ffffff;
10751
10752
      /* Offset is (SignExtend(offset field)<<2).  */
10753
0
      offset += given & 0x00ffffff;
10754
0
      offset <<= 2;
10755
0
      address = offset + pc + 8;
10756
10757
0
      if (given & 0x01000000)
10758
        /* H bit allows addressing to 2-byte boundaries.  */
10759
0
        address += 2;
10760
10761
0
            info->print_address_func (address, info);
10762
10763
      /* Fill in instruction information.  */
10764
0
      info->insn_info_valid = 1;
10765
0
      info->insn_type = dis_branch;
10766
0
      info->target = address;
10767
0
          }
10768
0
          break;
10769
10770
0
        case 'C':
10771
0
          if ((given & 0x02000200) == 0x200)
10772
0
      {
10773
0
        const char * name;
10774
0
        unsigned sysm = (given & 0x004f0000) >> 16;
10775
10776
0
        sysm |= (given & 0x300) >> 4;
10777
0
        name = banked_regname (sysm);
10778
10779
0
        if (name != NULL)
10780
0
          func (stream, dis_style_register, "%s", name);
10781
0
        else
10782
0
          func (stream, dis_style_text,
10783
0
          "(UNDEF: %lu)", (unsigned long) sysm);
10784
0
      }
10785
0
          else
10786
0
      {
10787
0
        func (stream, dis_style_register, "%cPSR_",
10788
0
        (given & 0x00400000) ? 'S' : 'C');
10789
10790
0
        if (given & 0x80000)
10791
0
          func (stream, dis_style_register, "f");
10792
0
        if (given & 0x40000)
10793
0
          func (stream, dis_style_register, "s");
10794
0
        if (given & 0x20000)
10795
0
          func (stream, dis_style_register, "x");
10796
0
        if (given & 0x10000)
10797
0
          func (stream, dis_style_register, "c");
10798
0
      }
10799
0
          break;
10800
10801
0
        case 'U':
10802
0
          if ((given & 0xf0) == 0x60)
10803
0
      {
10804
0
        switch (given & 0xf)
10805
0
          {
10806
0
          case 0xf:
10807
0
            func (stream, dis_style_sub_mnemonic, "sy");
10808
0
            break;
10809
0
          default:
10810
0
            func (stream, dis_style_immediate, "#%d",
10811
0
            (int) given & 0xf);
10812
0
            break;
10813
0
          }
10814
0
      }
10815
0
          else
10816
0
      {
10817
0
        const char * opt = data_barrier_option (given & 0xf);
10818
0
        if (opt != NULL)
10819
0
          func (stream, dis_style_sub_mnemonic, "%s", opt);
10820
0
        else
10821
0
          func (stream, dis_style_immediate,
10822
0
          "#%d", (int) given & 0xf);
10823
0
      }
10824
0
          break;
10825
10826
0
        case '0': case '1': case '2': case '3': case '4':
10827
0
        case '5': case '6': case '7': case '8': case '9':
10828
0
          {
10829
0
      int width;
10830
0
      unsigned long value;
10831
10832
0
      c = arm_decode_bitfield (c, given, &value, &width);
10833
10834
0
      switch (*c)
10835
0
        {
10836
0
        case 'R':
10837
0
          if (value == 15)
10838
0
            is_unpredictable = true;
10839
          /* Fall through.  */
10840
0
        case 'r':
10841
0
        case 'T':
10842
          /* We want register + 1 when decoding T.  */
10843
0
          if (*c == 'T')
10844
0
            value = (value + 1) & 0xf;
10845
10846
0
          if (c[1] == 'u')
10847
0
            {
10848
        /* Eat the 'u' character.  */
10849
0
        ++ c;
10850
10851
0
        if (u_reg == value)
10852
0
          is_unpredictable = true;
10853
0
        u_reg = value;
10854
0
            }
10855
0
          if (c[1] == 'U')
10856
0
            {
10857
        /* Eat the 'U' character.  */
10858
0
        ++ c;
10859
10860
0
        if (U_reg == value)
10861
0
          is_unpredictable = true;
10862
0
        U_reg = value;
10863
0
            }
10864
0
          func (stream, dis_style_register, "%s",
10865
0
          arm_regnames[value]);
10866
0
          break;
10867
0
        case 'd':
10868
0
          func (stream, base_style, "%ld", value);
10869
0
          value_in_comment = value;
10870
0
          break;
10871
0
        case 'b':
10872
0
          func (stream, dis_style_immediate,
10873
0
          "%ld", value * 8);
10874
0
          value_in_comment = value * 8;
10875
0
          break;
10876
0
        case 'W':
10877
0
          func (stream, dis_style_immediate,
10878
0
          "%ld", value + 1);
10879
0
          value_in_comment = value + 1;
10880
0
          break;
10881
0
        case 'x':
10882
0
          func (stream, dis_style_immediate,
10883
0
          "0x%08lx", value);
10884
10885
          /* Some SWI instructions have special
10886
             meanings.  */
10887
0
          if ((given & 0x0fffffff) == 0x0FF00000)
10888
0
            func (stream, dis_style_comment_start,
10889
0
            "\t@ IMB");
10890
0
          else if ((given & 0x0fffffff) == 0x0FF00001)
10891
0
            func (stream, dis_style_comment_start,
10892
0
            "\t@ IMBRange");
10893
0
          break;
10894
0
        case 'X':
10895
0
          func (stream, dis_style_immediate,
10896
0
          "%01lx", value & 0xf);
10897
0
          value_in_comment = value;
10898
0
          break;
10899
0
        case '`':
10900
0
          c++;
10901
0
          if (value == 0)
10902
0
            func (stream, dis_style_text, "%c", *c);
10903
0
          break;
10904
0
        case '\'':
10905
0
          c++;
10906
0
          if (value == ((1ul << width) - 1))
10907
0
            func (stream, base_style, "%c", *c);
10908
0
          break;
10909
0
        case '?':
10910
0
          func (stream, base_style, "%c",
10911
0
          c[(1 << width) - (int) value]);
10912
0
          c += 1 << width;
10913
0
          break;
10914
0
        default:
10915
0
          abort ();
10916
0
        }
10917
0
          }
10918
0
          break;
10919
10920
0
        case 'e':
10921
0
          {
10922
0
      int imm;
10923
10924
0
      imm = (given & 0xf) | ((given & 0xfff00) >> 4);
10925
0
      func (stream, dis_style_immediate, "%d", imm);
10926
0
      value_in_comment = imm;
10927
0
          }
10928
0
          break;
10929
10930
0
        case 'E':
10931
          /* LSB and WIDTH fields of BFI or BFC.  The machine-
10932
       language instruction encodes LSB and MSB.  */
10933
0
          {
10934
0
      long msb = (given & 0x001f0000) >> 16;
10935
0
      long lsb = (given & 0x00000f80) >> 7;
10936
0
      long w = msb - lsb + 1;
10937
10938
0
      if (w > 0)
10939
0
        {
10940
0
          func (stream, dis_style_immediate, "#%lu", lsb);
10941
0
          func (stream, dis_style_text, ", ");
10942
0
          func (stream, dis_style_immediate, "#%lu", w);
10943
0
        }
10944
0
      else
10945
0
        func (stream, dis_style_text,
10946
0
        "(invalid: %lu:%lu)", lsb, msb);
10947
0
          }
10948
0
          break;
10949
10950
0
        case 'R':
10951
          /* Get the PSR/banked register name.  */
10952
0
          {
10953
0
      const char * name;
10954
0
      unsigned sysm = (given & 0x004f0000) >> 16;
10955
10956
0
      sysm |= (given & 0x300) >> 4;
10957
0
      name = banked_regname (sysm);
10958
10959
0
      if (name != NULL)
10960
0
        func (stream, dis_style_register, "%s", name);
10961
0
      else
10962
0
        func (stream, dis_style_text,
10963
0
        "(UNDEF: %lu)", (unsigned long) sysm);
10964
0
          }
10965
0
          break;
10966
10967
0
        case 'V':
10968
          /* 16-bit unsigned immediate from a MOVT or MOVW
10969
       instruction, encoded in bits 0:11 and 15:19.  */
10970
0
          {
10971
0
      long hi = (given & 0x000f0000) >> 4;
10972
0
      long lo = (given & 0x00000fff);
10973
0
      long imm16 = hi | lo;
10974
10975
0
      func (stream, dis_style_immediate, "#%lu", imm16);
10976
0
      value_in_comment = imm16;
10977
0
          }
10978
0
          break;
10979
10980
0
        default:
10981
0
          abort ();
10982
0
        }
10983
0
    }
10984
0
        else
10985
0
    {
10986
10987
0
      if (*c == '@')
10988
0
        base_style = dis_style_comment_start;
10989
10990
0
      if (*c == '\t')
10991
0
        base_style = dis_style_text;
10992
10993
0
      func (stream, base_style, "%c", *c);
10994
0
    }
10995
0
      }
10996
10997
0
    if (value_in_comment > 32 || value_in_comment < -16)
10998
0
      func (stream, dis_style_comment_start, "\t@ 0x%lx",
10999
0
      (value_in_comment & 0xffffffffUL));
11000
11001
0
    if (is_unpredictable)
11002
0
      func (stream, dis_style_comment_start, UNPREDICTABLE_INSTRUCTION);
11003
11004
0
    return;
11005
0
  }
11006
0
    }
11007
0
  func (stream, dis_style_comment_start, UNKNOWN_INSTRUCTION_32BIT,
11008
0
  (unsigned) given);
11009
0
  return;
11010
0
}
11011
11012
/* Print one 16-bit Thumb instruction from PC on INFO->STREAM.  */
11013
11014
static void
11015
print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
11016
0
{
11017
0
  const struct opcode16 *insn;
11018
0
  void *stream = info->stream;
11019
0
  fprintf_styled_ftype func = info->fprintf_styled_func;
11020
0
  enum disassembler_style base_style = dis_style_mnemonic;
11021
0
  enum disassembler_style old_base_style = base_style;
11022
11023
0
  for (insn = thumb_opcodes; insn->assembler; insn++)
11024
0
    if ((given & insn->mask) == insn->value)
11025
0
      {
11026
0
  signed long value_in_comment = 0;
11027
0
  const char *c = insn->assembler;
11028
11029
0
  for (; *c; c++)
11030
0
    {
11031
0
      int domaskpc = 0;
11032
0
      int domasklr = 0;
11033
11034
0
      if (*c != '%')
11035
0
        {
11036
0
    if (*c == '@')
11037
0
      base_style = dis_style_comment_start;
11038
11039
0
    if (*c == '\t')
11040
0
      base_style = dis_style_text;
11041
11042
0
    func (stream, base_style, "%c", *c);
11043
11044
0
    continue;
11045
0
        }
11046
11047
0
      switch (*++c)
11048
0
        {
11049
0
    case '{':
11050
0
      ++c;
11051
0
      if (*c == '\0')
11052
0
        abort ();
11053
0
      old_base_style = base_style;
11054
0
      base_style = decode_base_style (*c);
11055
0
      ++c;
11056
0
      if (*c != ':')
11057
0
        abort ();
11058
0
      break;
11059
11060
0
    case '}':
11061
0
      base_style = old_base_style;
11062
0
      break;
11063
11064
0
        case '%':
11065
0
    func (stream, base_style, "%%");
11066
0
    break;
11067
11068
0
        case 'c':
11069
0
    if (ifthen_state)
11070
0
      func (stream, dis_style_mnemonic, "%s",
11071
0
      arm_conditional[IFTHEN_COND]);
11072
0
    break;
11073
11074
0
        case 'C':
11075
0
    if (ifthen_state)
11076
0
      func (stream, dis_style_mnemonic, "%s",
11077
0
      arm_conditional[IFTHEN_COND]);
11078
0
    else
11079
0
      func (stream, dis_style_mnemonic, "s");
11080
0
    break;
11081
11082
0
        case 'I':
11083
0
    {
11084
0
      unsigned int tmp;
11085
11086
0
      ifthen_next_state = given & 0xff;
11087
0
      for (tmp = given << 1; tmp & 0xf; tmp <<= 1)
11088
0
        func (stream, dis_style_mnemonic,
11089
0
        ((given ^ tmp) & 0x10) ? "e" : "t");
11090
0
      func (stream, dis_style_text, "\t");
11091
0
      func (stream, dis_style_sub_mnemonic, "%s",
11092
0
      arm_conditional[(given >> 4) & 0xf]);
11093
0
    }
11094
0
    break;
11095
11096
0
        case 'x':
11097
0
    if (ifthen_next_state)
11098
0
      func (stream, dis_style_comment_start,
11099
0
      "\t@ unpredictable branch in IT block\n");
11100
0
    break;
11101
11102
0
        case 'X':
11103
0
    if (ifthen_state)
11104
0
      func (stream, dis_style_comment_start,
11105
0
      "\t@ unpredictable <IT:%s>",
11106
0
      arm_conditional[IFTHEN_COND]);
11107
0
    break;
11108
11109
0
        case 'S':
11110
0
    {
11111
0
      long reg;
11112
11113
0
      reg = (given >> 3) & 0x7;
11114
0
      if (given & (1 << 6))
11115
0
        reg += 8;
11116
11117
0
      func (stream, dis_style_register, "%s", arm_regnames[reg]);
11118
0
    }
11119
0
    break;
11120
11121
0
        case 'D':
11122
0
    {
11123
0
      long reg;
11124
11125
0
      reg = given & 0x7;
11126
0
      if (given & (1 << 7))
11127
0
        reg += 8;
11128
11129
0
      func (stream, dis_style_register, "%s", arm_regnames[reg]);
11130
0
    }
11131
0
    break;
11132
11133
0
        case 'N':
11134
0
    if (given & (1 << 8))
11135
0
      domasklr = 1;
11136
    /* Fall through.  */
11137
0
        case 'O':
11138
0
    if (*c == 'O' && (given & (1 << 8)))
11139
0
      domaskpc = 1;
11140
    /* Fall through.  */
11141
0
        case 'M':
11142
0
    {
11143
0
      int started = 0;
11144
0
      int reg;
11145
11146
0
      func (stream, dis_style_text, "{");
11147
11148
      /* It would be nice if we could spot
11149
         ranges, and generate the rS-rE format: */
11150
0
      for (reg = 0; (reg < 8); reg++)
11151
0
        if ((given & (1 << reg)) != 0)
11152
0
          {
11153
0
      if (started)
11154
0
        func (stream, dis_style_text, ", ");
11155
0
      started = 1;
11156
0
      func (stream, dis_style_register, "%s",
11157
0
            arm_regnames[reg]);
11158
0
          }
11159
11160
0
      if (domasklr)
11161
0
        {
11162
0
          if (started)
11163
0
      func (stream, dis_style_text, ", ");
11164
0
          started = 1;
11165
0
          func (stream, dis_style_register, "%s",
11166
0
          arm_regnames[14] /* "lr" */);
11167
0
        }
11168
11169
0
      if (domaskpc)
11170
0
        {
11171
0
          if (started)
11172
0
      func (stream, dis_style_text, ", ");
11173
0
          func (stream, dis_style_register, "%s",
11174
0
          arm_regnames[15] /* "pc" */);
11175
0
        }
11176
11177
0
      func (stream, dis_style_text, "}");
11178
0
    }
11179
0
    break;
11180
11181
0
        case 'W':
11182
    /* Print writeback indicator for a LDMIA.  We are doing a
11183
       writeback if the base register is not in the register
11184
       mask.  */
11185
0
    if ((given & (1 << ((given & 0x0700) >> 8))) == 0)
11186
0
      func (stream, dis_style_text, "!");
11187
0
    break;
11188
11189
0
        case 'b':
11190
    /* Print ARM V6T2 CZB address: pc+4+6 bits.  */
11191
0
    {
11192
0
      bfd_vma address = (pc + 4
11193
0
             + ((given & 0x00f8) >> 2)
11194
0
             + ((given & 0x0200) >> 3));
11195
0
      info->print_address_func (address, info);
11196
11197
      /* Fill in instruction information.  */
11198
0
      info->insn_info_valid = 1;
11199
0
      info->insn_type = dis_branch;
11200
0
      info->target = address;
11201
0
    }
11202
0
    break;
11203
11204
0
        case 's':
11205
    /* Right shift immediate -- bits 6..10; 1-31 print
11206
       as themselves, 0 prints as 32.  */
11207
0
    {
11208
0
      long imm = (given & 0x07c0) >> 6;
11209
0
      if (imm == 0)
11210
0
        imm = 32;
11211
0
      func (stream, dis_style_immediate, "#%ld", imm);
11212
0
    }
11213
0
    break;
11214
11215
0
        case '0': case '1': case '2': case '3': case '4':
11216
0
        case '5': case '6': case '7': case '8': case '9':
11217
0
    {
11218
0
      int bitstart = *c++ - '0';
11219
0
      int bitend = 0;
11220
11221
0
      while (*c >= '0' && *c <= '9')
11222
0
        bitstart = (bitstart * 10) + *c++ - '0';
11223
11224
0
      switch (*c)
11225
0
        {
11226
0
        case '-':
11227
0
          {
11228
0
      bfd_vma reg;
11229
11230
0
      c++;
11231
0
      while (*c >= '0' && *c <= '9')
11232
0
        bitend = (bitend * 10) + *c++ - '0';
11233
0
      if (!bitend)
11234
0
        abort ();
11235
0
      reg = given >> bitstart;
11236
0
      reg &= ((bfd_vma) 2 << (bitend - bitstart)) - 1;
11237
11238
0
      switch (*c)
11239
0
        {
11240
0
        case 'r':
11241
0
          func (stream, dis_style_register, "%s",
11242
0
          arm_regnames[reg]);
11243
0
          break;
11244
11245
0
        case 'd':
11246
0
          func (stream, dis_style_immediate, "%ld",
11247
0
          (long) reg);
11248
0
          value_in_comment = reg;
11249
0
          break;
11250
11251
0
        case 'H':
11252
0
          func (stream, dis_style_immediate, "%ld",
11253
0
          (long) (reg << 1));
11254
0
          value_in_comment = reg << 1;
11255
0
          break;
11256
11257
0
        case 'W':
11258
0
          func (stream, dis_style_immediate, "%ld",
11259
0
          (long) (reg << 2));
11260
0
          value_in_comment = reg << 2;
11261
0
          break;
11262
11263
0
        case 'a':
11264
          /* PC-relative address -- the bottom two
11265
             bits of the address are dropped
11266
             before the calculation.  */
11267
0
          info->print_address_func
11268
0
            (((pc + 4) & ~3) + (reg << 2), info);
11269
0
          value_in_comment = 0;
11270
0
          break;
11271
11272
0
        case 'x':
11273
0
          func (stream, dis_style_immediate, "0x%04lx",
11274
0
          (long) reg);
11275
0
          break;
11276
11277
0
        case 'B':
11278
0
          reg = ((reg ^ (1 << bitend)) - (1 << bitend));
11279
0
          bfd_vma target = reg * 2 + pc + 4;
11280
0
          info->print_address_func (target, info);
11281
0
          value_in_comment = 0;
11282
11283
          /* Fill in instruction information.  */
11284
0
          info->insn_info_valid = 1;
11285
0
          info->insn_type = dis_branch;
11286
0
          info->target = target;
11287
0
          break;
11288
11289
0
        case 'c':
11290
0
          func (stream, dis_style_mnemonic, "%s",
11291
0
          arm_conditional [reg]);
11292
0
          break;
11293
11294
0
        default:
11295
0
          abort ();
11296
0
        }
11297
0
          }
11298
0
          break;
11299
11300
0
        case '\'':
11301
0
          c++;
11302
0
          if ((given & (1 << bitstart)) != 0)
11303
0
      func (stream, base_style, "%c", *c);
11304
0
          break;
11305
11306
0
        case '?':
11307
0
          ++c;
11308
0
          if ((given & (1 << bitstart)) != 0)
11309
0
      func (stream, base_style, "%c", *c++);
11310
0
          else
11311
0
      func (stream, base_style, "%c", *++c);
11312
0
          break;
11313
11314
0
        default:
11315
0
          abort ();
11316
0
        }
11317
0
    }
11318
0
    break;
11319
11320
0
        default:
11321
0
    abort ();
11322
0
        }
11323
0
    }
11324
11325
0
  if (value_in_comment > 32 || value_in_comment < -16)
11326
0
    func (stream, dis_style_comment_start,
11327
0
    "\t@ 0x%lx", value_in_comment);
11328
0
  return;
11329
0
      }
11330
11331
  /* No match.  */
11332
0
  func (stream, dis_style_comment_start, UNKNOWN_INSTRUCTION_16BIT,
11333
0
  (unsigned) given);
11334
0
  return;
11335
0
}
11336
11337
/* Return the name of an V7M special register.  */
11338
11339
static const char *
11340
psr_name (int regno)
11341
0
{
11342
0
  switch (regno)
11343
0
    {
11344
0
    case 0x0: return "APSR";
11345
0
    case 0x1: return "IAPSR";
11346
0
    case 0x2: return "EAPSR";
11347
0
    case 0x3: return "PSR";
11348
0
    case 0x5: return "IPSR";
11349
0
    case 0x6: return "EPSR";
11350
0
    case 0x7: return "IEPSR";
11351
0
    case 0x8: return "MSP";
11352
0
    case 0x9: return "PSP";
11353
0
    case 0xa: return "MSPLIM";
11354
0
    case 0xb: return "PSPLIM";
11355
0
    case 0x10: return "PRIMASK";
11356
0
    case 0x11: return "BASEPRI";
11357
0
    case 0x12: return "BASEPRI_MAX";
11358
0
    case 0x13: return "FAULTMASK";
11359
0
    case 0x14: return "CONTROL";
11360
0
    case 0x88: return "MSP_NS";
11361
0
    case 0x89: return "PSP_NS";
11362
0
    case 0x8a: return "MSPLIM_NS";
11363
0
    case 0x8b: return "PSPLIM_NS";
11364
0
    case 0x90: return "PRIMASK_NS";
11365
0
    case 0x91: return "BASEPRI_NS";
11366
0
    case 0x93: return "FAULTMASK_NS";
11367
0
    case 0x94: return "CONTROL_NS";
11368
0
    case 0x98: return "SP_NS";
11369
0
    default: return "<unknown>";
11370
0
    }
11371
0
}
11372
11373
/* Print one 32-bit Thumb instruction from PC on INFO->STREAM.  */
11374
11375
static void
11376
print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
11377
0
{
11378
0
  const struct opcode32 *insn;
11379
0
  void *stream = info->stream;
11380
0
  fprintf_styled_ftype func = info->fprintf_styled_func;
11381
0
  bool is_mve = is_mve_architecture (info);
11382
0
  enum disassembler_style base_style = dis_style_mnemonic;
11383
0
  enum disassembler_style old_base_style = base_style;
11384
11385
0
  if (print_insn_coprocessor (pc, info, given, true))
11386
0
    return;
11387
11388
0
  if (!is_mve && print_insn_neon (info, given, true))
11389
0
    return;
11390
11391
0
  if (is_mve && print_insn_mve (info, given))
11392
0
    return;
11393
11394
0
  if (print_insn_cde (info, given, true))
11395
0
    return;
11396
11397
0
  if (print_insn_generic_coprocessor (pc, info, given, true))
11398
0
    return;
11399
11400
0
  for (insn = thumb32_opcodes; insn->assembler; insn++)
11401
0
    if ((given & insn->mask) == insn->value)
11402
0
      {
11403
0
  bool is_clrm = false;
11404
0
  bool is_unpredictable = false;
11405
0
  signed long value_in_comment = 0;
11406
0
  const char *c = insn->assembler;
11407
11408
0
  for (; *c; c++)
11409
0
    {
11410
0
      if (*c != '%')
11411
0
        {
11412
0
    if (*c == '@')
11413
0
      base_style = dis_style_comment_start;
11414
0
    if (*c == '\t')
11415
0
      base_style = dis_style_text;
11416
0
    func (stream, base_style, "%c", *c);
11417
0
    continue;
11418
0
        }
11419
11420
0
      switch (*++c)
11421
0
        {
11422
0
        case '{':
11423
0
    ++c;
11424
0
    if (*c == '\0')
11425
0
      abort ();
11426
0
    old_base_style = base_style;
11427
0
    base_style = decode_base_style (*c);
11428
0
    ++c;
11429
0
    if (*c != ':')
11430
0
      abort ();
11431
0
    break;
11432
11433
0
        case '}':
11434
0
    base_style = old_base_style;
11435
0
    break;
11436
11437
0
        case '%':
11438
0
    func (stream, base_style, "%%");
11439
0
    break;
11440
11441
0
        case 'c':
11442
0
    if (ifthen_state)
11443
0
      func (stream, dis_style_mnemonic, "%s",
11444
0
      arm_conditional[IFTHEN_COND]);
11445
0
    break;
11446
11447
0
        case 'x':
11448
0
    if (ifthen_next_state)
11449
0
      func (stream, dis_style_comment_start,
11450
0
      "\t@ unpredictable branch in IT block\n");
11451
0
    break;
11452
11453
0
        case 'X':
11454
0
    if (ifthen_state)
11455
0
      func (stream, dis_style_comment_start,
11456
0
      "\t@ unpredictable <IT:%s>",
11457
0
      arm_conditional[IFTHEN_COND]);
11458
0
    break;
11459
11460
0
        case 'I':
11461
0
    {
11462
0
      unsigned int imm12 = 0;
11463
11464
0
      imm12 |= (given & 0x000000ffu);
11465
0
      imm12 |= (given & 0x00007000u) >> 4;
11466
0
      imm12 |= (given & 0x04000000u) >> 15;
11467
0
      func (stream, dis_style_immediate, "#%u", imm12);
11468
0
      value_in_comment = imm12;
11469
0
    }
11470
0
    break;
11471
11472
0
        case 'M':
11473
0
    {
11474
0
      unsigned int bits = 0, imm, imm8, mod;
11475
11476
0
      bits |= (given & 0x000000ffu);
11477
0
      bits |= (given & 0x00007000u) >> 4;
11478
0
      bits |= (given & 0x04000000u) >> 15;
11479
0
      imm8 = (bits & 0x0ff);
11480
0
      mod = (bits & 0xf00) >> 8;
11481
0
      switch (mod)
11482
0
        {
11483
0
        case 0: imm = imm8; break;
11484
0
        case 1: imm = ((imm8 << 16) | imm8); break;
11485
0
        case 2: imm = ((imm8 << 24) | (imm8 << 8)); break;
11486
0
        case 3: imm = ((imm8 << 24) | (imm8 << 16) | (imm8 << 8) | imm8); break;
11487
0
        default:
11488
0
          mod  = (bits & 0xf80) >> 7;
11489
0
          imm8 = (bits & 0x07f) | 0x80;
11490
0
          imm  = (((imm8 << (32 - mod)) | (imm8 >> mod)) & 0xffffffff);
11491
0
        }
11492
0
      func (stream, dis_style_immediate, "#%u", imm);
11493
0
      value_in_comment = imm;
11494
0
    }
11495
0
    break;
11496
11497
0
        case 'J':
11498
0
    {
11499
0
      unsigned int imm = 0;
11500
11501
0
      imm |= (given & 0x000000ffu);
11502
0
      imm |= (given & 0x00007000u) >> 4;
11503
0
      imm |= (given & 0x04000000u) >> 15;
11504
0
      imm |= (given & 0x000f0000u) >> 4;
11505
0
      func (stream, dis_style_immediate, "#%u", imm);
11506
0
      value_in_comment = imm;
11507
0
    }
11508
0
    break;
11509
11510
0
        case 'K':
11511
0
    {
11512
0
      unsigned int imm = 0;
11513
11514
0
      imm |= (given & 0x000f0000u) >> 16;
11515
0
      imm |= (given & 0x00000ff0u) >> 0;
11516
0
      imm |= (given & 0x0000000fu) << 12;
11517
0
      func (stream, dis_style_immediate, "#%u", imm);
11518
0
      value_in_comment = imm;
11519
0
    }
11520
0
    break;
11521
11522
0
        case 'H':
11523
0
    {
11524
0
      unsigned int imm = 0;
11525
11526
0
      imm |= (given & 0x000f0000u) >> 4;
11527
0
      imm |= (given & 0x00000fffu) >> 0;
11528
0
      func (stream, dis_style_immediate, "#%u", imm);
11529
0
      value_in_comment = imm;
11530
0
    }
11531
0
    break;
11532
11533
0
        case 'V':
11534
0
    {
11535
0
      unsigned int imm = 0;
11536
11537
0
      imm |= (given & 0x00000fffu);
11538
0
      imm |= (given & 0x000f0000u) >> 4;
11539
0
      func (stream, dis_style_immediate, "#%u", imm);
11540
0
      value_in_comment = imm;
11541
0
    }
11542
0
    break;
11543
11544
0
        case 'S':
11545
0
    {
11546
0
      unsigned int reg = (given & 0x0000000fu);
11547
0
      unsigned int stp = (given & 0x00000030u) >> 4;
11548
0
      unsigned int imm = 0;
11549
0
      imm |= (given & 0x000000c0u) >> 6;
11550
0
      imm |= (given & 0x00007000u) >> 10;
11551
11552
0
      func (stream, dis_style_register, "%s", arm_regnames[reg]);
11553
0
      switch (stp)
11554
0
        {
11555
0
        case 0:
11556
0
          if (imm > 0)
11557
0
      {
11558
0
        func (stream, dis_style_text, ", ");
11559
0
        func (stream, dis_style_sub_mnemonic, "lsl ");
11560
0
        func (stream, dis_style_immediate, "#%u", imm);
11561
0
      }
11562
0
          break;
11563
11564
0
        case 1:
11565
0
          if (imm == 0)
11566
0
      imm = 32;
11567
0
          func (stream, dis_style_text, ", ");
11568
0
          func (stream, dis_style_sub_mnemonic, "lsr ");
11569
0
          func (stream, dis_style_immediate, "#%u", imm);
11570
0
          break;
11571
11572
0
        case 2:
11573
0
          if (imm == 0)
11574
0
      imm = 32;
11575
0
          func (stream, dis_style_text, ", ");
11576
0
          func (stream, dis_style_sub_mnemonic, "asr ");
11577
0
          func (stream, dis_style_immediate, "#%u", imm);
11578
0
          break;
11579
11580
0
        case 3:
11581
0
          if (imm == 0)
11582
0
      {
11583
0
        func (stream, dis_style_text, ", ");
11584
0
        func (stream, dis_style_sub_mnemonic, "rrx");
11585
0
      }
11586
0
          else
11587
0
      {
11588
0
        func (stream, dis_style_text, ", ");
11589
0
        func (stream, dis_style_sub_mnemonic, "ror ");
11590
0
        func (stream, dis_style_immediate, "#%u", imm);
11591
0
      }
11592
0
        }
11593
0
    }
11594
0
    break;
11595
11596
0
        case 'a':
11597
0
    {
11598
0
      unsigned int Rn  = (given & 0x000f0000) >> 16;
11599
0
      unsigned int U   = ! NEGATIVE_BIT_SET;
11600
0
      unsigned int op  = (given & 0x00000f00) >> 8;
11601
0
      unsigned int i12 = (given & 0x00000fff);
11602
0
      unsigned int i8  = (given & 0x000000ff);
11603
0
      bool writeback = false, postind = false;
11604
0
      bfd_vma offset = 0;
11605
11606
0
      func (stream, dis_style_text, "[");
11607
0
      func (stream, dis_style_register, "%s", arm_regnames[Rn]);
11608
0
      if (U) /* 12-bit positive immediate offset.  */
11609
0
        {
11610
0
          offset = i12;
11611
0
          if (Rn != 15)
11612
0
      value_in_comment = offset;
11613
0
        }
11614
0
      else if (Rn == 15) /* 12-bit negative immediate offset.  */
11615
0
        offset = - (int) i12;
11616
0
      else if (op == 0x0) /* Shifted register offset.  */
11617
0
        {
11618
0
          unsigned int Rm = (i8 & 0x0f);
11619
0
          unsigned int sh = (i8 & 0x30) >> 4;
11620
11621
0
          func (stream, dis_style_text, ", ");
11622
0
          func (stream, dis_style_register, "%s",
11623
0
          arm_regnames[Rm]);
11624
0
          if (sh)
11625
0
      {
11626
0
        func (stream, dis_style_text, ", ");
11627
0
        func (stream, dis_style_sub_mnemonic, "lsl ");
11628
0
        func (stream, dis_style_immediate, "#%u", sh);
11629
0
      }
11630
0
          func (stream, dis_style_text, "]");
11631
0
          break;
11632
0
        }
11633
0
      else switch (op)
11634
0
        {
11635
0
        case 0xE:  /* 8-bit positive immediate offset.  */
11636
0
          offset = i8;
11637
0
          break;
11638
11639
0
        case 0xC:  /* 8-bit negative immediate offset.  */
11640
0
          offset = -i8;
11641
0
          break;
11642
11643
0
        case 0xF:  /* 8-bit + preindex with wb.  */
11644
0
          offset = i8;
11645
0
          writeback = true;
11646
0
          break;
11647
11648
0
        case 0xD:  /* 8-bit - preindex with wb.  */
11649
0
          offset = -i8;
11650
0
          writeback = true;
11651
0
          break;
11652
11653
0
        case 0xB:  /* 8-bit + postindex.  */
11654
0
          offset = i8;
11655
0
          postind = true;
11656
0
          break;
11657
11658
0
        case 0x9:  /* 8-bit - postindex.  */
11659
0
          offset = -i8;
11660
0
          postind = true;
11661
0
          break;
11662
11663
0
        default:
11664
0
          func (stream, dis_style_text, ", <undefined>]");
11665
0
          goto skip;
11666
0
        }
11667
11668
0
      if (postind)
11669
0
        {
11670
0
          func (stream, dis_style_text, "], ");
11671
0
          func (stream, dis_style_immediate, "#%d", (int) offset);
11672
0
        }
11673
0
      else
11674
0
        {
11675
0
          if (offset)
11676
0
      {
11677
0
        func (stream, dis_style_text, ", ");
11678
0
        func (stream, dis_style_immediate, "#%d",
11679
0
        (int) offset);
11680
0
      }
11681
0
          func (stream, dis_style_text, writeback ? "]!" : "]");
11682
0
        }
11683
11684
0
      if (Rn == 15)
11685
0
        {
11686
0
          func (stream, dis_style_comment_start, "\t@ ");
11687
0
          info->print_address_func (((pc + 4) & ~3) + offset, info);
11688
0
        }
11689
0
    }
11690
0
        skip:
11691
0
    break;
11692
11693
0
        case 'A':
11694
0
    {
11695
0
      unsigned int U   = ! NEGATIVE_BIT_SET;
11696
0
      unsigned int W   = WRITEBACK_BIT_SET;
11697
0
      unsigned int Rn  = (given & 0x000f0000) >> 16;
11698
0
      unsigned int off = (given & 0x000000ff);
11699
11700
0
      func (stream, dis_style_text, "[");
11701
0
      func (stream, dis_style_register, "%s", arm_regnames[Rn]);
11702
11703
0
      if (PRE_BIT_SET)
11704
0
        {
11705
0
          if (off || !U)
11706
0
      {
11707
0
        func (stream, dis_style_text, ", ");
11708
0
        func (stream, dis_style_immediate, "#%c%u",
11709
0
        U ? '+' : '-', off * 4);
11710
0
        value_in_comment = off * 4 * (U ? 1 : -1);
11711
0
      }
11712
0
          func (stream, dis_style_text, "]");
11713
0
          if (W)
11714
0
      func (stream, dis_style_text, "!");
11715
0
        }
11716
0
      else
11717
0
        {
11718
0
          func (stream, dis_style_text, "], ");
11719
0
          if (W)
11720
0
      {
11721
0
        func (stream, dis_style_immediate, "#%c%u",
11722
0
        U ? '+' : '-', off * 4);
11723
0
        value_in_comment = off * 4 * (U ? 1 : -1);
11724
0
      }
11725
0
          else
11726
0
      {
11727
0
        func (stream, dis_style_text, "{");
11728
0
        func (stream, dis_style_immediate, "%u", off);
11729
0
        func (stream, dis_style_text, "}");
11730
0
        value_in_comment = off;
11731
0
      }
11732
0
        }
11733
0
    }
11734
0
    break;
11735
11736
0
        case 'w':
11737
0
    {
11738
0
      unsigned int Sbit = (given & 0x01000000) >> 24;
11739
0
      unsigned int type = (given & 0x00600000) >> 21;
11740
11741
0
      switch (type)
11742
0
        {
11743
0
        case 0:
11744
0
          func (stream, dis_style_mnemonic, Sbit ? "sb" : "b");
11745
0
          break;
11746
0
        case 1:
11747
0
          func (stream, dis_style_mnemonic, Sbit ? "sh" : "h");
11748
0
          break;
11749
0
        case 2:
11750
0
          if (Sbit)
11751
0
      func (stream, dis_style_text, "??");
11752
0
          break;
11753
0
        case 3:
11754
0
          func (stream, dis_style_text, "??");
11755
0
          break;
11756
0
        }
11757
0
    }
11758
0
    break;
11759
11760
0
        case 'n':
11761
0
    is_clrm = true;
11762
    /* Fall through.  */
11763
0
        case 'm':
11764
0
    {
11765
0
      int started = 0;
11766
0
      int reg;
11767
11768
0
      func (stream, dis_style_text, "{");
11769
0
      for (reg = 0; reg < 16; reg++)
11770
0
        if ((given & (1 << reg)) != 0)
11771
0
          {
11772
0
      if (started)
11773
0
        func (stream, dis_style_text, ", ");
11774
0
      started = 1;
11775
0
      if (is_clrm && reg == 13)
11776
0
        func (stream, dis_style_text, "(invalid: %s)",
11777
0
        arm_regnames[reg]);
11778
0
      else if (is_clrm && reg == 15)
11779
0
        func (stream, dis_style_register, "%s", "APSR");
11780
0
      else
11781
0
        func (stream, dis_style_register, "%s",
11782
0
        arm_regnames[reg]);
11783
0
          }
11784
0
      func (stream, dis_style_text, "}");
11785
0
    }
11786
0
    break;
11787
11788
0
        case 'E':
11789
0
    {
11790
0
      unsigned int msb = (given & 0x0000001f);
11791
0
      unsigned int lsb = 0;
11792
11793
0
      lsb |= (given & 0x000000c0u) >> 6;
11794
0
      lsb |= (given & 0x00007000u) >> 10;
11795
0
      func (stream, dis_style_immediate, "#%u", lsb);
11796
0
      func (stream, dis_style_text, ", ");
11797
0
      func (stream, dis_style_immediate, "#%u", msb - lsb + 1);
11798
0
    }
11799
0
    break;
11800
11801
0
        case 'F':
11802
0
    {
11803
0
      unsigned int width = (given & 0x0000001f) + 1;
11804
0
      unsigned int lsb = 0;
11805
11806
0
      lsb |= (given & 0x000000c0u) >> 6;
11807
0
      lsb |= (given & 0x00007000u) >> 10;
11808
0
      func (stream, dis_style_immediate, "#%u", lsb);
11809
0
      func (stream, dis_style_text, ", ");
11810
0
      func (stream, dis_style_immediate, "#%u", width);
11811
0
    }
11812
0
    break;
11813
11814
0
        case 'G':
11815
0
    {
11816
0
      unsigned int boff = (((given & 0x07800000) >> 23) << 1);
11817
0
      func (stream, dis_style_immediate, "%x", boff);
11818
0
    }
11819
0
    break;
11820
11821
0
        case 'W':
11822
0
    {
11823
0
      unsigned int immA = (given & 0x001f0000u) >> 16;
11824
0
      unsigned int immB = (given & 0x000007feu) >> 1;
11825
0
      unsigned int immC = (given & 0x00000800u) >> 11;
11826
0
      bfd_vma offset = 0;
11827
11828
0
      offset |= immA << 12;
11829
0
      offset |= immB << 2;
11830
0
      offset |= immC << 1;
11831
      /* Sign extend.  */
11832
0
      offset = (offset & 0x10000) ? offset - (1 << 17) : offset;
11833
11834
0
      info->print_address_func (pc + 4 + offset, info);
11835
0
    }
11836
0
    break;
11837
11838
0
        case 'Y':
11839
0
    {
11840
0
      unsigned int immA = (given & 0x007f0000u) >> 16;
11841
0
      unsigned int immB = (given & 0x000007feu) >> 1;
11842
0
      unsigned int immC = (given & 0x00000800u) >> 11;
11843
0
      bfd_vma offset = 0;
11844
11845
0
      offset |= immA << 12;
11846
0
      offset |= immB << 2;
11847
0
      offset |= immC << 1;
11848
      /* Sign extend.  */
11849
0
      offset = (offset & 0x40000) ? offset - (1 << 19) : offset;
11850
11851
0
      info->print_address_func (pc + 4 + offset, info);
11852
0
    }
11853
0
    break;
11854
11855
0
        case 'Z':
11856
0
    {
11857
0
      unsigned int immA = (given & 0x00010000u) >> 16;
11858
0
      unsigned int immB = (given & 0x000007feu) >> 1;
11859
0
      unsigned int immC = (given & 0x00000800u) >> 11;
11860
0
      bfd_vma offset = 0;
11861
11862
0
      offset |= immA << 12;
11863
0
      offset |= immB << 2;
11864
0
      offset |= immC << 1;
11865
      /* Sign extend.  */
11866
0
      offset = (offset & 0x1000) ? offset - (1 << 13) : offset;
11867
11868
0
      info->print_address_func (pc + 4 + offset, info);
11869
11870
0
      unsigned int T    = (given & 0x00020000u) >> 17;
11871
0
      unsigned int endoffset = (((given & 0x07800000) >> 23) << 1);
11872
0
      unsigned int boffset   = (T == 1) ? 4 : 2;
11873
0
      func (stream, dis_style_text, ", ");
11874
0
      func (stream, dis_style_immediate, "%x",
11875
0
      endoffset + boffset);
11876
0
    }
11877
0
    break;
11878
11879
0
        case 'Q':
11880
0
    {
11881
0
      unsigned int immh = (given & 0x000007feu) >> 1;
11882
0
      unsigned int imml = (given & 0x00000800u) >> 11;
11883
0
      bfd_vma imm32 = 0;
11884
11885
0
      imm32 |= immh << 2;
11886
0
      imm32 |= imml << 1;
11887
11888
0
      info->print_address_func (pc + 4 + imm32, info);
11889
0
    }
11890
0
    break;
11891
11892
0
        case 'P':
11893
0
    {
11894
0
      unsigned int immh = (given & 0x000007feu) >> 1;
11895
0
      unsigned int imml = (given & 0x00000800u) >> 11;
11896
0
      bfd_vma imm32 = 0;
11897
11898
0
      imm32 |= immh << 2;
11899
0
      imm32 |= imml << 1;
11900
11901
0
      info->print_address_func (pc + 4 - imm32, info);
11902
0
    }
11903
0
    break;
11904
11905
0
        case 'b':
11906
0
    {
11907
0
      unsigned int S = (given & 0x04000000u) >> 26;
11908
0
      unsigned int J1 = (given & 0x00002000u) >> 13;
11909
0
      unsigned int J2 = (given & 0x00000800u) >> 11;
11910
0
      bfd_vma offset = 0;
11911
11912
0
      offset |= !S << 20;
11913
0
      offset |= J2 << 19;
11914
0
      offset |= J1 << 18;
11915
0
      offset |= (given & 0x003f0000) >> 4;
11916
0
      offset |= (given & 0x000007ff) << 1;
11917
0
      offset -= (1 << 20);
11918
11919
0
      bfd_vma target = pc + 4 + offset;
11920
0
      info->print_address_func (target, info);
11921
11922
      /* Fill in instruction information.  */
11923
0
      info->insn_info_valid = 1;
11924
0
      info->insn_type = dis_branch;
11925
0
      info->target = target;
11926
0
    }
11927
0
    break;
11928
11929
0
        case 'B':
11930
0
    {
11931
0
      unsigned int S = (given & 0x04000000u) >> 26;
11932
0
      unsigned int I1 = (given & 0x00002000u) >> 13;
11933
0
      unsigned int I2 = (given & 0x00000800u) >> 11;
11934
0
      bfd_vma offset = 0;
11935
11936
0
      offset |= !S << 24;
11937
0
      offset |= !(I1 ^ S) << 23;
11938
0
      offset |= !(I2 ^ S) << 22;
11939
0
      offset |= (given & 0x03ff0000u) >> 4;
11940
0
      offset |= (given & 0x000007ffu) << 1;
11941
0
      offset -= (1 << 24);
11942
0
      offset += pc + 4;
11943
11944
      /* BLX target addresses are always word aligned.  */
11945
0
      if ((given & 0x00001000u) == 0)
11946
0
          offset &= ~2u;
11947
11948
0
      info->print_address_func (offset, info);
11949
11950
      /* Fill in instruction information.  */
11951
0
      info->insn_info_valid = 1;
11952
0
      info->insn_type = dis_branch;
11953
0
      info->target = offset;
11954
0
    }
11955
0
    break;
11956
11957
0
        case 's':
11958
0
    {
11959
0
      unsigned int shift = 0;
11960
11961
0
      shift |= (given & 0x000000c0u) >> 6;
11962
0
      shift |= (given & 0x00007000u) >> 10;
11963
0
      if (WRITEBACK_BIT_SET)
11964
0
        {
11965
0
          func (stream, dis_style_text, ", ");
11966
0
          func (stream, dis_style_sub_mnemonic, "asr ");
11967
0
          func (stream, dis_style_immediate, "#%u", shift);
11968
0
        }
11969
0
      else if (shift)
11970
0
        {
11971
0
          func (stream, dis_style_text, ", ");
11972
0
          func (stream, dis_style_sub_mnemonic, "lsl ");
11973
0
          func (stream, dis_style_immediate, "#%u", shift);
11974
0
        }
11975
      /* else print nothing - lsl #0 */
11976
0
    }
11977
0
    break;
11978
11979
0
        case 'R':
11980
0
    {
11981
0
      unsigned int rot = (given & 0x00000030) >> 4;
11982
11983
0
      if (rot)
11984
0
        {
11985
0
          func (stream, dis_style_text, ", ");
11986
0
          func (stream, dis_style_sub_mnemonic, "ror ");
11987
0
          func (stream, dis_style_immediate, "#%u", rot * 8);
11988
0
        }
11989
0
    }
11990
0
    break;
11991
11992
0
        case 'U':
11993
0
    if ((given & 0xf0) == 0x60)
11994
0
      {
11995
0
        switch (given & 0xf)
11996
0
          {
11997
0
          case 0xf:
11998
0
      func (stream, dis_style_sub_mnemonic, "sy");
11999
0
      break;
12000
0
          default:
12001
0
      func (stream, dis_style_immediate, "#%d",
12002
0
            (int) given & 0xf);
12003
0
      break;
12004
0
          }
12005
0
      }
12006
0
    else
12007
0
      {
12008
0
        const char * opt = data_barrier_option (given & 0xf);
12009
0
        if (opt != NULL)
12010
0
          func (stream, dis_style_sub_mnemonic, "%s", opt);
12011
0
        else
12012
0
          func (stream, dis_style_immediate, "#%d",
12013
0
          (int) given & 0xf);
12014
0
       }
12015
0
    break;
12016
12017
0
        case 'C':
12018
0
    if ((given & 0xff) == 0)
12019
0
      {
12020
0
        func (stream, dis_style_register, "%cPSR_",
12021
0
        (given & 0x100000) ? 'S' : 'C');
12022
12023
0
        if (given & 0x800)
12024
0
          func (stream, dis_style_register, "f");
12025
0
        if (given & 0x400)
12026
0
          func (stream, dis_style_register, "s");
12027
0
        if (given & 0x200)
12028
0
          func (stream, dis_style_register, "x");
12029
0
        if (given & 0x100)
12030
0
          func (stream, dis_style_register, "c");
12031
0
      }
12032
0
    else if ((given & 0x20) == 0x20)
12033
0
      {
12034
0
        char const* name;
12035
0
        unsigned sysm = (given & 0xf00) >> 8;
12036
12037
0
        sysm |= (given & 0x30);
12038
0
        sysm |= (given & 0x00100000) >> 14;
12039
0
        name = banked_regname (sysm);
12040
12041
0
        if (name != NULL)
12042
0
          func (stream, dis_style_register, "%s", name);
12043
0
        else
12044
0
          func (stream, dis_style_text,
12045
0
          "(UNDEF: %lu)", (unsigned long) sysm);
12046
0
      }
12047
0
    else
12048
0
      {
12049
0
        func (stream, dis_style_register, "%s",
12050
0
        psr_name (given & 0xff));
12051
0
      }
12052
0
    break;
12053
12054
0
        case 'D':
12055
0
    if (((given & 0xff) == 0)
12056
0
        || ((given & 0x20) == 0x20))
12057
0
      {
12058
0
        char const* name;
12059
0
        unsigned sm = (given & 0xf0000) >> 16;
12060
12061
0
        sm |= (given & 0x30);
12062
0
        sm |= (given & 0x00100000) >> 14;
12063
0
        name = banked_regname (sm);
12064
12065
0
        if (name != NULL)
12066
0
          func (stream, dis_style_register, "%s", name);
12067
0
        else
12068
0
          func (stream, dis_style_text,
12069
0
          "(UNDEF: %lu)", (unsigned long) sm);
12070
0
      }
12071
0
    else
12072
0
      func (stream, dis_style_register, "%s",
12073
0
      psr_name (given & 0xff));
12074
0
    break;
12075
12076
0
        case '0': case '1': case '2': case '3': case '4':
12077
0
        case '5': case '6': case '7': case '8': case '9':
12078
0
    {
12079
0
      int width;
12080
0
      unsigned long val;
12081
12082
0
      c = arm_decode_bitfield (c, given, &val, &width);
12083
12084
0
      switch (*c)
12085
0
        {
12086
0
        case 's':
12087
0
          if (val <= 3)
12088
0
      func (stream, dis_style_mnemonic, "%s",
12089
0
            mve_vec_sizename[val]);
12090
0
          else
12091
0
      func (stream, dis_style_text, "<undef size>");
12092
0
          break;
12093
12094
0
        case 'd':
12095
0
          func (stream, base_style, "%lu", val);
12096
0
          value_in_comment = val;
12097
0
          break;
12098
12099
0
        case 'D':
12100
0
          func (stream, dis_style_immediate, "%lu", val + 1);
12101
0
          value_in_comment = val + 1;
12102
0
          break;
12103
12104
0
        case 'W':
12105
0
          func (stream, dis_style_immediate, "%lu", val * 4);
12106
0
          value_in_comment = val * 4;
12107
0
          break;
12108
12109
0
        case 'S':
12110
0
          if (val == 13)
12111
0
      is_unpredictable = true;
12112
          /* Fall through.  */
12113
0
        case 'R':
12114
0
          if (val == 15)
12115
0
      is_unpredictable = true;
12116
          /* Fall through.  */
12117
0
        case 'r':
12118
0
          func (stream, dis_style_register, "%s",
12119
0
          arm_regnames[val]);
12120
0
          break;
12121
12122
0
        case 'c':
12123
0
          func (stream, base_style, "%s", arm_conditional[val]);
12124
0
          break;
12125
12126
0
        case '\'':
12127
0
          c++;
12128
0
          if (val == ((1ul << width) - 1))
12129
0
      func (stream, base_style, "%c", *c);
12130
0
          break;
12131
12132
0
        case '`':
12133
0
          c++;
12134
0
          if (val == 0)
12135
0
      func (stream, dis_style_immediate, "%c", *c);
12136
0
          break;
12137
12138
0
        case '?':
12139
0
          func (stream, dis_style_mnemonic, "%c",
12140
0
          c[(1 << width) - (int) val]);
12141
0
          c += 1 << width;
12142
0
          break;
12143
12144
0
        case 'x':
12145
0
          func (stream, dis_style_immediate, "0x%lx",
12146
0
          val & 0xffffffffUL);
12147
0
          break;
12148
12149
0
        default:
12150
0
          abort ();
12151
0
        }
12152
0
    }
12153
0
    break;
12154
12155
0
        case 'L':
12156
    /* PR binutils/12534
12157
       If we have a PC relative offset in an LDRD or STRD
12158
       instructions then display the decoded address.  */
12159
0
    if (((given >> 16) & 0xf) == 0xf)
12160
0
      {
12161
0
        bfd_vma offset = (given & 0xff) * 4;
12162
12163
0
        if ((given & (1 << 23)) == 0)
12164
0
          offset = - offset;
12165
0
        func (stream, dis_style_comment_start, "\t@ ");
12166
0
        info->print_address_func ((pc & ~3) + 4 + offset, info);
12167
0
      }
12168
0
    break;
12169
12170
0
        default:
12171
0
    abort ();
12172
0
        }
12173
0
    }
12174
12175
0
  if (value_in_comment > 32 || value_in_comment < -16)
12176
0
    func (stream, dis_style_comment_start, "\t@ 0x%lx",
12177
0
    value_in_comment);
12178
12179
0
  if (is_unpredictable)
12180
0
    func (stream, dis_style_comment_start, UNPREDICTABLE_INSTRUCTION);
12181
12182
0
  return;
12183
0
      }
12184
12185
  /* No match.  */
12186
0
  func (stream, dis_style_comment_start, UNKNOWN_INSTRUCTION_32BIT,
12187
0
  (unsigned) given);
12188
0
  return;
12189
0
}
12190
12191
/* Print data bytes on INFO->STREAM.  */
12192
12193
static void
12194
print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED,
12195
     struct disassemble_info *info,
12196
     long given)
12197
0
{
12198
0
  fprintf_styled_ftype func = info->fprintf_styled_func;
12199
12200
0
  switch (info->bytes_per_chunk)
12201
0
    {
12202
0
    case 1:
12203
0
      func (info->stream, dis_style_assembler_directive, ".byte");
12204
0
      func (info->stream, dis_style_text, "\t");
12205
0
      func (info->stream, dis_style_immediate, "0x%02lx", given);
12206
0
      break;
12207
0
    case 2:
12208
0
      func (info->stream, dis_style_assembler_directive, ".short");
12209
0
      func (info->stream, dis_style_text, "\t");
12210
0
      func (info->stream, dis_style_immediate, "0x%04lx", given);
12211
0
      break;
12212
0
    case 4:
12213
0
      func (info->stream, dis_style_assembler_directive, ".word");
12214
0
      func (info->stream, dis_style_text, "\t");
12215
0
      func (info->stream, dis_style_immediate, "0x%08lx", given);
12216
0
      break;
12217
0
    default:
12218
0
      abort ();
12219
0
    }
12220
0
}
12221
12222
/* Disallow mapping symbols ($a, $b, $d, $t etc) from
12223
   being displayed in symbol relative addresses.
12224
12225
   Also disallow private symbol, with __tagsym$$ prefix,
12226
   from ARM RVCT toolchain being displayed.  */
12227
12228
bool
12229
arm_symbol_is_valid (asymbol * sym,
12230
         struct disassemble_info * info ATTRIBUTE_UNUSED)
12231
0
{
12232
0
  const char * name;
12233
12234
0
  if (sym == NULL)
12235
0
    return false;
12236
12237
0
  name = bfd_asymbol_name (sym);
12238
12239
0
  return (name && *name != '$' && strncmp (name, "__tagsym$$", 10));
12240
0
}
12241
12242
/* Parse the string of disassembler options.  */
12243
12244
static void
12245
parse_arm_disassembler_options (const char *options)
12246
0
{
12247
0
  const char *opt;
12248
12249
0
  force_thumb = false;
12250
0
  FOR_EACH_DISASSEMBLER_OPTION (opt, options)
12251
0
    {
12252
0
      if (startswith (opt, "reg-names-"))
12253
0
  {
12254
0
    unsigned int i;
12255
0
    for (i = 0; i < NUM_ARM_OPTIONS; i++)
12256
0
      if (disassembler_options_cmp (opt, regnames[i].name) == 0)
12257
0
        {
12258
0
    regname_selected = i;
12259
0
    break;
12260
0
        }
12261
12262
0
    if (i >= NUM_ARM_OPTIONS)
12263
      /* xgettext: c-format */
12264
0
      opcodes_error_handler (_("unrecognised register name set: %s"),
12265
0
           opt);
12266
0
  }
12267
0
      else if (startswith (opt, "force-thumb"))
12268
0
  force_thumb = 1;
12269
0
      else if (startswith (opt, "no-force-thumb"))
12270
0
  force_thumb = 0;
12271
0
      else if (startswith (opt, "coproc"))
12272
0
  {
12273
0
    const char *procptr = opt + sizeof ("coproc") - 1;
12274
0
    char *endptr;
12275
0
    uint8_t coproc_number = strtol (procptr, &endptr, 10);
12276
0
    if (endptr != procptr + 1 || coproc_number > 7)
12277
0
      {
12278
0
        opcodes_error_handler (_("cde coprocessor not between 0-7: %s"),
12279
0
             opt);
12280
0
        continue;
12281
0
      }
12282
0
    if (*endptr != '=')
12283
0
      {
12284
0
        opcodes_error_handler (_("coproc must have an argument: %s"),
12285
0
             opt);
12286
0
        continue;
12287
0
      }
12288
0
    endptr += 1;
12289
0
    if (startswith (endptr, "generic"))
12290
0
      cde_coprocs &= ~(1 << coproc_number);
12291
0
    else if (startswith (endptr, "cde")
12292
0
       || startswith (endptr, "CDE"))
12293
0
      cde_coprocs |= (1 << coproc_number);
12294
0
    else
12295
0
      {
12296
0
        opcodes_error_handler (
12297
0
      _("coprocN argument takes options \"generic\","
12298
0
        " \"cde\", or \"CDE\": %s"), opt);
12299
0
      }
12300
0
  }
12301
0
      else
12302
  /* xgettext: c-format */
12303
0
  opcodes_error_handler (_("unrecognised disassembler option: %s"), opt);
12304
0
    }
12305
12306
0
  return;
12307
0
}
12308
12309
static bool
12310
mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
12311
       enum map_type *map_symbol);
12312
12313
/* Search back through the insn stream to determine if this instruction is
12314
   conditionally executed.  */
12315
12316
static void
12317
find_ifthen_state (bfd_vma pc,
12318
       struct disassemble_info *info,
12319
       bool little)
12320
0
{
12321
0
  unsigned char b[2];
12322
0
  unsigned int insn;
12323
0
  int status;
12324
  /* COUNT is twice the number of instructions seen.  It will be odd if we
12325
     just crossed an instruction boundary.  */
12326
0
  int count;
12327
0
  int it_count;
12328
0
  unsigned int seen_it;
12329
0
  bfd_vma addr;
12330
12331
0
  ifthen_address = pc;
12332
0
  ifthen_state = 0;
12333
12334
0
  addr = pc;
12335
0
  count = 1;
12336
0
  it_count = 0;
12337
0
  seen_it = 0;
12338
  /* Scan backwards looking for IT instructions, keeping track of where
12339
     instruction boundaries are.  We don't know if something is actually an
12340
     IT instruction until we find a definite instruction boundary.  */
12341
0
  for (;;)
12342
0
    {
12343
0
      if (addr == 0 || info->symbol_at_address_func (addr, info))
12344
0
  {
12345
    /* A symbol must be on an instruction boundary, and will not
12346
       be within an IT block.  */
12347
0
    if (seen_it && (count & 1))
12348
0
      break;
12349
12350
0
    return;
12351
0
  }
12352
0
      addr -= 2;
12353
0
      status = info->read_memory_func (addr, (bfd_byte *) b, 2, info);
12354
0
      if (status)
12355
0
  return;
12356
12357
0
      if (little)
12358
0
  insn = (b[0]) | (b[1] << 8);
12359
0
      else
12360
0
  insn = (b[1]) | (b[0] << 8);
12361
0
      if (seen_it)
12362
0
  {
12363
0
    if ((insn & 0xf800) < 0xe800)
12364
0
      {
12365
        /* Addr + 2 is an instruction boundary.  See if this matches
12366
           the expected boundary based on the position of the last
12367
     IT candidate.  */
12368
0
        if (count & 1)
12369
0
    break;
12370
0
        seen_it = 0;
12371
0
      }
12372
0
  }
12373
0
      if ((insn & 0xff00) == 0xbf00 && (insn & 0xf) != 0)
12374
0
  {
12375
0
    enum map_type type = MAP_ARM;
12376
0
    bool found = mapping_symbol_for_insn (addr, info, &type);
12377
12378
0
    if (!found || (found && type == MAP_THUMB))
12379
0
      {
12380
        /* This could be an IT instruction.  */
12381
0
        seen_it = insn;
12382
0
        it_count = count >> 1;
12383
0
      }
12384
0
  }
12385
0
      if ((insn & 0xf800) >= 0xe800)
12386
0
  count++;
12387
0
      else
12388
0
  count = (count + 2) | 1;
12389
      /* IT blocks contain at most 4 instructions.  */
12390
0
      if (count >= 8 && !seen_it)
12391
0
  return;
12392
0
    }
12393
  /* We found an IT instruction.  */
12394
0
  ifthen_state = (seen_it & 0xe0) | ((seen_it << it_count) & 0x1f);
12395
0
  if ((ifthen_state & 0xf) == 0)
12396
0
    ifthen_state = 0;
12397
0
}
12398
12399
/* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a
12400
   mapping symbol.  */
12401
12402
static int
12403
is_mapping_symbol (struct disassemble_info *info,
12404
       int n,
12405
       enum map_type *map_type)
12406
0
{
12407
0
  const char *name = bfd_asymbol_name (info->symtab[n]);
12408
12409
0
  if (name[0] == '$'
12410
0
      && (name[1] == 'a' || name[1] == 't' || name[1] == 'd')
12411
0
      && (name[2] == 0 || name[2] == '.'))
12412
0
    {
12413
0
      *map_type = ((name[1] == 'a') ? MAP_ARM
12414
0
       : (name[1] == 't') ? MAP_THUMB
12415
0
       : MAP_DATA);
12416
0
      return true;
12417
0
    }
12418
12419
0
  return false;
12420
0
}
12421
12422
/* Try to infer the code type (ARM or Thumb) from a mapping symbol.
12423
   Returns nonzero if *MAP_TYPE was set.  */
12424
12425
static int
12426
get_map_sym_type (struct disassemble_info *info,
12427
      int n,
12428
      enum map_type *map_type)
12429
0
{
12430
  /* If the symbol is in a different section, ignore it.  */
12431
0
  if (info->section != NULL && info->section != info->symtab[n]->section)
12432
0
    return false;
12433
12434
0
  return is_mapping_symbol (info, n, map_type);
12435
0
}
12436
12437
/* Try to infer the code type (ARM or Thumb) from a non-mapping symbol.
12438
   Returns nonzero if *MAP_TYPE was set.  */
12439
12440
static int
12441
get_sym_code_type (struct disassemble_info *info,
12442
       int n,
12443
       enum map_type *map_type)
12444
0
{
12445
0
  elf_symbol_type *es;
12446
0
  unsigned int type;
12447
0
  asymbol * sym;
12448
12449
  /* If the symbol is in a different section, ignore it.  */
12450
0
  if (info->section != NULL && info->section != info->symtab[n]->section)
12451
0
    return false;
12452
12453
  /* PR 30230: Reject non-ELF symbols, eg synthetic ones.  */
12454
0
  sym = info->symtab[n];
12455
0
  if (bfd_asymbol_flavour (sym) != bfd_target_elf_flavour)
12456
0
    return false;
12457
12458
0
  es = (elf_symbol_type *) sym;
12459
0
  type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
12460
12461
  /* If the symbol has function type then use that.  */
12462
0
  if (type == STT_FUNC || type == STT_GNU_IFUNC)
12463
0
    {
12464
0
      if (ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
12465
0
    == ST_BRANCH_TO_THUMB)
12466
0
  *map_type = MAP_THUMB;
12467
0
      else
12468
0
  *map_type = MAP_ARM;
12469
0
      return true;
12470
0
    }
12471
12472
0
  return false;
12473
0
}
12474
12475
/* Search the mapping symbol state for instruction at pc.  This is only
12476
   applicable for elf target.
12477
12478
   There is an assumption Here, info->private_data contains the correct AND
12479
   up-to-date information about current scan process.  The information will be
12480
   used to speed this search process.
12481
12482
   Return TRUE if the mapping state can be determined, and map_symbol
12483
   will be updated accordingly.  Otherwise, return FALSE.  */
12484
12485
static bool
12486
mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
12487
       enum map_type *map_symbol)
12488
0
{
12489
0
  bfd_vma addr, section_vma = 0;
12490
0
  int n, last_sym = -1;
12491
0
  bool found = false;
12492
0
  bool can_use_search_opt_p = false;
12493
12494
  /* Sanity check.  */
12495
0
  if (info == NULL)
12496
0
    return false;
12497
12498
  /* Default to DATA.  A text section is required by the ABI to contain an
12499
     INSN mapping symbol at the start.  A data section has no such
12500
     requirement, hence if no mapping symbol is found the section must
12501
     contain only data.  This however isn't very useful if the user has
12502
     fully stripped the binaries.  If this is the case use the section
12503
     attributes to determine the default.  If we have no section default to
12504
     INSN as well, as we may be disassembling some raw bytes on a baremetal
12505
     HEX file or similar.  */
12506
0
  enum map_type type = MAP_DATA;
12507
0
  if ((info->section && info->section->flags & SEC_CODE) || !info->section)
12508
0
    type = MAP_ARM;
12509
0
  struct arm_private_data *private_data;
12510
12511
0
  if (info->private_data == NULL || info->symtab == NULL
12512
0
      || info->symtab_size == 0
12513
0
      || bfd_asymbol_flavour (*info->symtab) != bfd_target_elf_flavour)
12514
0
    return false;
12515
12516
0
  private_data = info->private_data;
12517
12518
  /* First, look for mapping symbols.  */
12519
0
  if (pc <= private_data->last_mapping_addr)
12520
0
    private_data->last_mapping_sym = -1;
12521
12522
  /* Start scanning at the start of the function, or wherever
12523
     we finished last time.  */
12524
0
  n = info->symtab_pos + 1;
12525
12526
  /* If the last stop offset is different from the current one it means we
12527
     are disassembling a different glob of bytes.  As such the optimization
12528
     would not be safe and we should start over.  */
12529
0
  can_use_search_opt_p
12530
0
    = (private_data->last_mapping_sym >= 0
12531
0
       && info->stop_offset == private_data->last_stop_offset);
12532
12533
0
  if (n >= private_data->last_mapping_sym && can_use_search_opt_p)
12534
0
    n = private_data->last_mapping_sym;
12535
12536
  /* Look down while we haven't passed the location being disassembled.
12537
     The reason for this is that there's no defined order between a symbol
12538
     and an mapping symbol that may be at the same address.  We may have to
12539
     look at least one position ahead.  */
12540
0
  for (; n < info->symtab_size; n++)
12541
0
    {
12542
0
      addr = bfd_asymbol_value (info->symtab[n]);
12543
0
      if (addr > pc)
12544
0
  break;
12545
0
      if (get_map_sym_type (info, n, &type))
12546
0
  {
12547
0
    last_sym = n;
12548
0
    found = true;
12549
0
  }
12550
0
    }
12551
12552
0
  if (!found)
12553
0
    {
12554
0
      n = info->symtab_pos;
12555
0
      if (n >= private_data->last_mapping_sym && can_use_search_opt_p)
12556
0
  n = private_data->last_mapping_sym;
12557
12558
      /* No mapping symbol found at this address.  Look backwards
12559
   for a preceeding one, but don't go pass the section start
12560
   otherwise a data section with no mapping symbol can pick up
12561
   a text mapping symbol of a preceeding section.  The documentation
12562
   says section can be NULL, in which case we will seek up all the
12563
   way to the top.  */
12564
0
      if (info->section)
12565
0
  section_vma = info->section->vma;
12566
12567
0
      for (; n >= 0; n--)
12568
0
  {
12569
0
    addr = bfd_asymbol_value (info->symtab[n]);
12570
0
    if (addr < section_vma)
12571
0
      break;
12572
12573
0
    if (get_map_sym_type (info, n, &type))
12574
0
      {
12575
0
        last_sym = n;
12576
0
        found = true;
12577
0
        break;
12578
0
      }
12579
0
  }
12580
0
    }
12581
12582
  /* If no mapping symbol was found, try looking up without a mapping
12583
     symbol.  This is done by walking up from the current PC to the nearest
12584
     symbol.  We don't actually have to loop here since symtab_pos will
12585
     contain the nearest symbol already.  */
12586
0
  if (!found)
12587
0
    {
12588
0
      n = info->symtab_pos;
12589
0
      if (n >= 0 && get_sym_code_type (info, n, &type))
12590
0
  {
12591
0
    last_sym = n;
12592
0
    found = true;
12593
0
  }
12594
0
    }
12595
12596
0
  private_data->last_mapping_sym = last_sym;
12597
0
  private_data->last_type = type;
12598
0
  private_data->last_stop_offset = info->stop_offset;
12599
12600
0
  *map_symbol = type;
12601
0
  return found;
12602
0
}
12603
12604
/* Given a bfd_mach_arm_XXX value, this function fills in the fields
12605
   of the supplied arm_feature_set structure with bitmasks indicating
12606
   the supported base architectures and coprocessor extensions.
12607
12608
   FIXME: This could more efficiently implemented as a constant array,
12609
   although it would also be less robust.  */
12610
12611
static void
12612
select_arm_features (unsigned long mach,
12613
         arm_feature_set * features)
12614
0
{
12615
0
  arm_feature_set arch_fset;
12616
0
  const arm_feature_set fpu_any = FPU_ANY;
12617
12618
0
#undef ARM_SET_FEATURES
12619
0
#define ARM_SET_FEATURES(FSET) \
12620
0
  {             \
12621
0
    const arm_feature_set fset = FSET;      \
12622
0
    arch_fset = fset;         \
12623
0
  }
12624
12625
  /* When several architecture versions share the same bfd_mach_arm_XXX value
12626
     the most featureful is chosen.  */
12627
0
  switch (mach)
12628
0
    {
12629
0
    case bfd_mach_arm_2:  ARM_SET_FEATURES (ARM_ARCH_V2); break;
12630
0
    case bfd_mach_arm_2a:  ARM_SET_FEATURES (ARM_ARCH_V2S); break;
12631
0
    case bfd_mach_arm_3:  ARM_SET_FEATURES (ARM_ARCH_V3); break;
12632
0
    case bfd_mach_arm_3M:  ARM_SET_FEATURES (ARM_ARCH_V3M); break;
12633
0
    case bfd_mach_arm_4:  ARM_SET_FEATURES (ARM_ARCH_V4); break;
12634
0
    case bfd_mach_arm_4T:  ARM_SET_FEATURES (ARM_ARCH_V4T); break;
12635
0
    case bfd_mach_arm_5:  ARM_SET_FEATURES (ARM_ARCH_V5); break;
12636
0
    case bfd_mach_arm_5T:  ARM_SET_FEATURES (ARM_ARCH_V5T); break;
12637
0
    case bfd_mach_arm_5TE:  ARM_SET_FEATURES (ARM_ARCH_V5TE); break;
12638
0
    case bfd_mach_arm_XScale:  ARM_SET_FEATURES (ARM_ARCH_XSCALE); break;
12639
0
    case bfd_mach_arm_ep9312:
12640
0
  ARM_SET_FEATURES (ARM_FEATURE_LOW (ARM_AEXT_V4T,
12641
0
             ARM_CEXT_MAVERICK | FPU_MAVERICK));
12642
0
       break;
12643
0
    case bfd_mach_arm_iWMMXt:  ARM_SET_FEATURES (ARM_ARCH_IWMMXT); break;
12644
0
    case bfd_mach_arm_iWMMXt2:  ARM_SET_FEATURES (ARM_ARCH_IWMMXT2); break;
12645
0
    case bfd_mach_arm_5TEJ:  ARM_SET_FEATURES (ARM_ARCH_V5TEJ); break;
12646
0
    case bfd_mach_arm_6:  ARM_SET_FEATURES (ARM_ARCH_V6); break;
12647
0
    case bfd_mach_arm_6KZ:  ARM_SET_FEATURES (ARM_ARCH_V6KZ); break;
12648
0
    case bfd_mach_arm_6T2:  ARM_SET_FEATURES (ARM_ARCH_V6KZT2); break;
12649
0
    case bfd_mach_arm_6K:  ARM_SET_FEATURES (ARM_ARCH_V6K); break;
12650
0
    case bfd_mach_arm_7:  ARM_SET_FEATURES (ARM_ARCH_V7VE); break;
12651
0
    case bfd_mach_arm_6M:  ARM_SET_FEATURES (ARM_ARCH_V6M); break;
12652
0
    case bfd_mach_arm_6SM:  ARM_SET_FEATURES (ARM_ARCH_V6SM); break;
12653
0
    case bfd_mach_arm_7EM:  ARM_SET_FEATURES (ARM_ARCH_V7EM); break;
12654
0
    case bfd_mach_arm_8:
12655
0
  {
12656
    /* Add bits for extensions that Armv8.6-A recognizes.  */
12657
0
    arm_feature_set armv8_6_ext_fset
12658
0
      = ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST);
12659
0
    ARM_SET_FEATURES (ARM_ARCH_V8_6A);
12660
0
    ARM_MERGE_FEATURE_SETS (arch_fset, arch_fset, armv8_6_ext_fset);
12661
0
    break;
12662
0
  }
12663
0
    case bfd_mach_arm_8R:  ARM_SET_FEATURES (ARM_ARCH_V8R); break;
12664
0
    case bfd_mach_arm_8M_BASE:  ARM_SET_FEATURES (ARM_ARCH_V8M_BASE); break;
12665
0
    case bfd_mach_arm_8M_MAIN:  ARM_SET_FEATURES (ARM_ARCH_V8M_MAIN); break;
12666
0
    case bfd_mach_arm_8_1M_MAIN:
12667
0
      ARM_SET_FEATURES (ARM_ARCH_V8_1M_MAIN);
12668
0
      arm_feature_set mve_all
12669
0
  = ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE | ARM_EXT2_MVE_FP);
12670
0
      ARM_MERGE_FEATURE_SETS (arch_fset, arch_fset, mve_all);
12671
0
      force_thumb = 1;
12672
0
      break;
12673
0
    case bfd_mach_arm_9:         ARM_SET_FEATURES (ARM_ARCH_V9A); break;
12674
      /* If the machine type is unknown allow all architecture types and all
12675
   extensions, with the exception of MVE as that clashes with NEON.  */
12676
0
    case bfd_mach_arm_unknown:
12677
0
      ARM_SET_FEATURES (ARM_ARCH_UNKNOWN);
12678
0
      break;
12679
0
    default:
12680
0
      abort ();
12681
0
    }
12682
0
#undef ARM_SET_FEATURES
12683
12684
  /* None of the feature bits related to -mfpu have an impact on Tag_CPU_arch
12685
     and thus on bfd_mach_arm_XXX value.  Therefore for a given
12686
     bfd_mach_arm_XXX value all coprocessor feature bits should be allowed.  */
12687
0
  ARM_MERGE_FEATURE_SETS (*features, arch_fset, fpu_any);
12688
0
}
12689
12690
12691
/* NOTE: There are no checks in these routines that
12692
   the relevant number of data bytes exist.  */
12693
12694
static int
12695
print_insn (bfd_vma pc, struct disassemble_info *info, bool little)
12696
0
{
12697
0
  unsigned char b[4];
12698
0
  unsigned long given;
12699
0
  int status;
12700
0
  int is_thumb = false;
12701
0
  int is_data = false;
12702
0
  int little_code;
12703
0
  unsigned int  size = 4;
12704
0
  void (*printer) (bfd_vma, struct disassemble_info *, long);
12705
0
  bool found = false;
12706
0
  struct arm_private_data *private_data;
12707
12708
  /* Clear instruction information field.  */
12709
0
  info->insn_info_valid = 0;
12710
0
  info->branch_delay_insns = 0;
12711
0
  info->data_size = 0;
12712
0
  info->insn_type = dis_noninsn;
12713
0
  info->target = 0;
12714
0
  info->target2 = 0;
12715
12716
0
  if (info->disassembler_options)
12717
0
    {
12718
0
      parse_arm_disassembler_options (info->disassembler_options);
12719
12720
      /* To avoid repeated parsing of these options, we remove them here.  */
12721
0
      info->disassembler_options = NULL;
12722
0
    }
12723
12724
  /* PR 10288: Control which instructions will be disassembled.  */
12725
0
  if (info->private_data == NULL)
12726
0
    {
12727
0
      static struct arm_private_data private;
12728
12729
0
      if ((info->flags & USER_SPECIFIED_MACHINE_TYPE) == 0)
12730
  /* If the user did not use the -m command line switch then default to
12731
     disassembling all types of ARM instruction.
12732
12733
     The info->mach value has to be ignored as this will be based on
12734
     the default archictecture for the target and/or hints in the notes
12735
     section, but it will never be greater than the current largest arm
12736
     machine value (iWMMXt2), which is only equivalent to the V5TE
12737
     architecture.  ARM architectures have advanced beyond the machine
12738
     value encoding, and these newer architectures would be ignored if
12739
     the machine value was used.
12740
12741
     Ie the -m switch is used to restrict which instructions will be
12742
     disassembled.  If it is necessary to use the -m switch to tell
12743
     objdump that an ARM binary is being disassembled, eg because the
12744
     input is a raw binary file, but it is also desired to disassemble
12745
     all ARM instructions then use "-marm".  This will select the
12746
     "unknown" arm architecture which is compatible with any ARM
12747
     instruction.  */
12748
0
    info->mach = bfd_mach_arm_unknown;
12749
12750
      /* Compute the architecture bitmask from the machine number.
12751
   Note: This assumes that the machine number will not change
12752
   during disassembly....  */
12753
0
      select_arm_features (info->mach, & private.features);
12754
12755
0
      private.last_mapping_sym = -1;
12756
0
      private.last_mapping_addr = 0;
12757
0
      private.last_stop_offset = 0;
12758
12759
0
      info->private_data = & private;
12760
0
    }
12761
12762
0
  private_data = info->private_data;
12763
12764
  /* Decide if our code is going to be little-endian, despite what the
12765
     function argument might say.  */
12766
0
  little_code = ((info->endian_code == BFD_ENDIAN_LITTLE) || little);
12767
12768
  /* For ELF, consult the symbol table to determine what kind of code
12769
     or data we have.  */
12770
0
  if (info->symtab_size != 0
12771
0
      && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour)
12772
0
    {
12773
0
      bfd_vma addr;
12774
0
      int n;
12775
0
      int last_sym = -1;
12776
0
      enum map_type type = MAP_ARM;
12777
12778
0
      found = mapping_symbol_for_insn (pc, info, &type);
12779
0
      last_sym = private_data->last_mapping_sym;
12780
12781
0
      is_thumb = (private_data->last_type == MAP_THUMB);
12782
0
      is_data = (private_data->last_type == MAP_DATA);
12783
12784
      /* Look a little bit ahead to see if we should print out
12785
   two or four bytes of data.  If there's a symbol,
12786
   mapping or otherwise, after two bytes then don't
12787
   print more.  */
12788
0
      if (is_data)
12789
0
  {
12790
0
    size = 4 - (pc & 3);
12791
0
    for (n = last_sym + 1; n < info->symtab_size; n++)
12792
0
      {
12793
0
        addr = bfd_asymbol_value (info->symtab[n]);
12794
0
        if (addr > pc
12795
0
      && (info->section == NULL
12796
0
          || info->section == info->symtab[n]->section))
12797
0
    {
12798
0
      if (addr - pc < size)
12799
0
        size = addr - pc;
12800
0
      break;
12801
0
    }
12802
0
      }
12803
    /* If the next symbol is after three bytes, we need to
12804
       print only part of the data, so that we can use either
12805
       .byte or .short.  */
12806
0
    if (size == 3)
12807
0
      size = (pc & 1) ? 1 : 2;
12808
0
  }
12809
0
    }
12810
12811
0
  if (info->symbols != NULL)
12812
0
    {
12813
0
      if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour)
12814
0
  {
12815
0
    coff_symbol_type * cs;
12816
12817
0
    cs = coffsymbol (*info->symbols);
12818
0
    is_thumb = (   cs->native->u.syment.n_sclass == C_THUMBEXT
12819
0
          || cs->native->u.syment.n_sclass == C_THUMBSTAT
12820
0
          || cs->native->u.syment.n_sclass == C_THUMBLABEL
12821
0
          || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC
12822
0
          || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC);
12823
0
  }
12824
0
      else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour
12825
0
         && !found)
12826
0
  {
12827
    /* If no mapping symbol has been found then fall back to the type
12828
       of the function symbol.  */
12829
0
    elf_symbol_type *  es;
12830
0
    unsigned int       type;
12831
12832
0
    es = *(elf_symbol_type **)(info->symbols);
12833
0
    type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
12834
12835
0
    is_thumb =
12836
0
      ((ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
12837
0
        == ST_BRANCH_TO_THUMB) || type == STT_ARM_16BIT);
12838
0
  }
12839
0
      else if (bfd_asymbol_flavour (*info->symbols)
12840
0
         == bfd_target_mach_o_flavour)
12841
0
  {
12842
0
    bfd_mach_o_asymbol *asym = (bfd_mach_o_asymbol *)*info->symbols;
12843
12844
0
    is_thumb = (asym->n_desc & BFD_MACH_O_N_ARM_THUMB_DEF);
12845
0
  }
12846
0
    }
12847
12848
0
  if (force_thumb)
12849
0
    is_thumb = true;
12850
12851
0
  if (is_data)
12852
0
    info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
12853
0
  else
12854
0
    info->display_endian = little_code ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
12855
12856
0
  info->bytes_per_line = 4;
12857
12858
  /* PR 10263: Disassemble data if requested to do so by the user.  */
12859
0
  if (is_data && ((info->flags & DISASSEMBLE_DATA) == 0))
12860
0
    {
12861
0
      int i;
12862
12863
      /* Size was already set above.  */
12864
0
      info->bytes_per_chunk = size;
12865
0
      printer = print_insn_data;
12866
12867
0
      status = info->read_memory_func (pc, (bfd_byte *) b, size, info);
12868
0
      given = 0;
12869
0
      if (little)
12870
0
  for (i = size - 1; i >= 0; i--)
12871
0
    given = b[i] | (given << 8);
12872
0
      else
12873
0
  for (i = 0; i < (int) size; i++)
12874
0
    given = b[i] | (given << 8);
12875
0
    }
12876
0
  else if (!is_thumb)
12877
0
    {
12878
      /* In ARM mode endianness is a straightforward issue: the instruction
12879
   is four bytes long and is either ordered 0123 or 3210.  */
12880
0
      printer = print_insn_arm;
12881
0
      info->bytes_per_chunk = 4;
12882
0
      size = 4;
12883
12884
0
      status = info->read_memory_func (pc, (bfd_byte *) b, 4, info);
12885
0
      if (little_code)
12886
0
  given = (b[0]) | (b[1] << 8) | (b[2] << 16) | ((unsigned) b[3] << 24);
12887
0
      else
12888
0
  given = (b[3]) | (b[2] << 8) | (b[1] << 16) | ((unsigned) b[0] << 24);
12889
0
    }
12890
0
  else
12891
0
    {
12892
      /* In Thumb mode we have the additional wrinkle of two
12893
   instruction lengths.  Fortunately, the bits that determine
12894
   the length of the current instruction are always to be found
12895
   in the first two bytes.  */
12896
0
      printer = print_insn_thumb16;
12897
0
      info->bytes_per_chunk = 2;
12898
0
      size = 2;
12899
12900
0
      status = info->read_memory_func (pc, (bfd_byte *) b, 2, info);
12901
0
      if (little_code)
12902
0
  given = (b[0]) | (b[1] << 8);
12903
0
      else
12904
0
  given = (b[1]) | (b[0] << 8);
12905
12906
0
      if (!status)
12907
0
  {
12908
    /* These bit patterns signal a four-byte Thumb
12909
       instruction.  */
12910
0
    if ((given & 0xF800) == 0xF800
12911
0
        || (given & 0xF800) == 0xF000
12912
0
        || (given & 0xF800) == 0xE800)
12913
0
      {
12914
0
        status = info->read_memory_func (pc + 2, (bfd_byte *) b, 2, info);
12915
0
        if (little_code)
12916
0
    given = (b[0]) | (b[1] << 8) | (given << 16);
12917
0
        else
12918
0
    given = (b[1]) | (b[0] << 8) | (given << 16);
12919
12920
0
        printer = print_insn_thumb32;
12921
0
        size = 4;
12922
0
      }
12923
0
  }
12924
12925
0
      if (ifthen_address != pc)
12926
0
  find_ifthen_state (pc, info, little_code);
12927
12928
0
      if (ifthen_state)
12929
0
  {
12930
0
    if ((ifthen_state & 0xf) == 0x8)
12931
0
      ifthen_next_state = 0;
12932
0
    else
12933
0
      ifthen_next_state = (ifthen_state & 0xe0)
12934
0
        | ((ifthen_state & 0xf) << 1);
12935
0
  }
12936
0
    }
12937
12938
0
  if (status)
12939
0
    {
12940
0
      info->memory_error_func (status, pc, info);
12941
0
      return -1;
12942
0
    }
12943
0
  if (info->flags & INSN_HAS_RELOC)
12944
    /* If the instruction has a reloc associated with it, then
12945
       the offset field in the instruction will actually be the
12946
       addend for the reloc.  (We are using REL type relocs).
12947
       In such cases, we can ignore the pc when computing
12948
       addresses, since the addend is not currently pc-relative.  */
12949
0
    pc = 0;
12950
12951
0
  printer (pc, info, given);
12952
12953
0
  if (is_thumb)
12954
0
    {
12955
0
      ifthen_state = ifthen_next_state;
12956
0
      ifthen_address += size;
12957
0
    }
12958
0
  return size;
12959
0
}
12960
12961
int
12962
print_insn_big_arm (bfd_vma pc, struct disassemble_info *info)
12963
0
{
12964
  /* Detect BE8-ness and record it in the disassembler info.  */
12965
0
  if (info->flavour == bfd_target_elf_flavour
12966
0
      && info->section != NULL
12967
0
      && (elf_elfheader (info->section->owner)->e_flags & EF_ARM_BE8))
12968
0
    info->endian_code = BFD_ENDIAN_LITTLE;
12969
12970
0
  return print_insn (pc, info, false);
12971
0
}
12972
12973
int
12974
print_insn_little_arm (bfd_vma pc, struct disassemble_info *info)
12975
0
{
12976
0
  return print_insn (pc, info, true);
12977
0
}
12978
12979
const disasm_options_and_args_t *
12980
disassembler_options_arm (void)
12981
0
{
12982
0
  static disasm_options_and_args_t *opts_and_args;
12983
12984
0
  if (opts_and_args == NULL)
12985
0
    {
12986
0
      disasm_options_t *opts;
12987
0
      unsigned int i;
12988
12989
0
      opts_and_args = XNEW (disasm_options_and_args_t);
12990
0
      opts_and_args->args = NULL;
12991
12992
0
      opts = &opts_and_args->options;
12993
0
      opts->name = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
12994
0
      opts->description = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
12995
0
      opts->arg = NULL;
12996
0
      for (i = 0; i < NUM_ARM_OPTIONS; i++)
12997
0
  {
12998
0
    opts->name[i] = regnames[i].name;
12999
0
    if (regnames[i].description != NULL)
13000
0
      opts->description[i] = _(regnames[i].description);
13001
0
    else
13002
0
      opts->description[i] = NULL;
13003
0
  }
13004
      /* The array we return must be NULL terminated.  */
13005
0
      opts->name[i] = NULL;
13006
0
      opts->description[i] = NULL;
13007
0
    }
13008
13009
0
  return opts_and_args;
13010
0
}
13011
13012
void
13013
print_arm_disassembler_options (FILE *stream)
13014
0
{
13015
0
  unsigned int i, max_len = 0;
13016
0
  fprintf (stream, _("\n\
13017
0
The following ARM specific disassembler options are supported for use with\n\
13018
0
the -M switch:\n"));
13019
13020
0
  for (i = 0; i < NUM_ARM_OPTIONS; i++)
13021
0
    {
13022
0
      unsigned int len = strlen (regnames[i].name);
13023
0
      if (max_len < len)
13024
0
  max_len = len;
13025
0
    }
13026
13027
0
  for (i = 0, max_len++; i < NUM_ARM_OPTIONS; i++)
13028
0
    fprintf (stream, "  %s%*c %s\n",
13029
0
       regnames[i].name,
13030
0
       (int)(max_len - strlen (regnames[i].name)), ' ',
13031
0
       _(regnames[i].description));
13032
0
}