/* Print i386 instructions for GDB, the GNU debugger.

   Copyright (C) 1988-2023 Free Software Foundation, Inc.

   This file is part of the GNU opcodes library.

   This library is free software; you can redistribute it and/or modify

   it under the terms of the GNU General Public License as published by

   the Free Software Foundation; either version 3, or (at your option)

   any later version.

   It is distributed in the hope that it will be useful, but WITHOUT

   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY

   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public

   License for more details.

   You should have received a copy of the GNU General Public License

   along with this program; if not, write to the Free Software

   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,

   MA 02110-1301, USA.  */

/* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)

   July 1988

    modified by John Hassey (hassey@dg-rtp.dg.com)

    x86-64 support added by Jan Hubicka (jh@suse.cz)

    VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */

/* The main tables describing the instructions is essentially a copy

   of the "Opcode Map" chapter (Appendix A) of the Intel 80386

   Programmers Manual.  Usually, there is a capital letter, followed

   by a small letter.  The capital letter tell the addressing mode,

   and the small letter tells about the operand size.  Refer to

   the Intel manual for details.  */

#include "sysdep.h"

#include "disassemble.h"

#include "opintl.h"

#include "opcode/i386.h"

#include "libiberty.h"

#include "safe-ctype.h"

typedef struct instr_info instr_info;

static bool dofloat (instr_info *, int);

static int putop (instr_info *, const char *, int);

static void oappend_with_style (instr_info *, const char *,

        enum disassembler_style);

static bool OP_E (instr_info *, int, int);

static bool OP_E_memory (instr_info *, int, int);

static bool OP_indirE (instr_info *, int, int);

static bool OP_G (instr_info *, int, int);

static bool OP_ST (instr_info *, int, int);

static bool OP_STi (instr_info *, int, int);

static bool OP_Skip_MODRM (instr_info *, int, int);

static bool OP_REG (instr_info *, int, int);

static bool OP_IMREG (instr_info *, int, int);

static bool OP_I (instr_info *, int, int);

static bool OP_I64 (instr_info *, int, int);

static bool OP_sI (instr_info *, int, int);

static bool OP_J (instr_info *, int, int);

static bool OP_SEG (instr_info *, int, int);

static bool OP_DIR (instr_info *, int, int);

static bool OP_OFF (instr_info *, int, int);

static bool OP_OFF64 (instr_info *, int, int);

static bool OP_ESreg (instr_info *, int, int);

static bool OP_DSreg (instr_info *, int, int);

static bool OP_C (instr_info *, int, int);

static bool OP_D (instr_info *, int, int);

static bool OP_T (instr_info *, int, int);

static bool OP_MMX (instr_info *, int, int);

static bool OP_XMM (instr_info *, int, int);

static bool OP_EM (instr_info *, int, int);

static bool OP_EX (instr_info *, int, int);

static bool OP_EMC (instr_info *, int,int);

static bool OP_MXC (instr_info *, int,int);

static bool OP_R (instr_info *, int, int);

static bool OP_M (instr_info *, int, int);

static bool OP_VEX (instr_info *, int, int);

static bool OP_VexR (instr_info *, int, int);

static bool OP_VexW (instr_info *, int, int);

static bool OP_Rounding (instr_info *, int, int);

static bool OP_REG_VexI4 (instr_info *, int, int);

static bool OP_VexI4 (instr_info *, int, int);

static bool OP_0f07 (instr_info *, int, int);

static bool OP_Monitor (instr_info *, int, int);

static bool OP_Mwait (instr_info *, int, int);

static bool PCLMUL_Fixup (instr_info *, int, int);

static bool VPCMP_Fixup (instr_info *, int, int);

static bool VPCOM_Fixup (instr_info *, int, int);

static bool NOP_Fixup (instr_info *, int, int);

static bool OP_3DNowSuffix (instr_info *, int, int);

static bool CMP_Fixup (instr_info *, int, int);

static bool REP_Fixup (instr_info *, int, int);

static bool SEP_Fixup (instr_info *, int, int);

static bool BND_Fixup (instr_info *, int, int);

static bool NOTRACK_Fixup (instr_info *, int, int);

static bool HLE_Fixup1 (instr_info *, int, int);

static bool HLE_Fixup2 (instr_info *, int, int);

static bool HLE_Fixup3 (instr_info *, int, int);

static bool CMPXCHG8B_Fixup (instr_info *, int, int);

static bool XMM_Fixup (instr_info *, int, int);

static bool FXSAVE_Fixup (instr_info *, int, int);

static bool MOVSXD_Fixup (instr_info *, int, int);

static bool DistinctDest_Fixup (instr_info *, int, int);

static bool PREFETCHI_Fixup (instr_info *, int, int);

static void ATTRIBUTE_PRINTF_3 i386_dis_printf (const disassemble_info *,

            enum disassembler_style,

            const char *, ...);

/* This character is used to encode style information within the output

   buffers.  See oappend_insert_style for more details.  */

#define STYLE_MARKER_CHAR '\002'

/* The maximum operand buffer size.  */

#define MAX_OPERAND_BUFFER_SIZE 128

enum address_mode

{

  mode_16bit,

  mode_32bit,

  mode_64bit

};

static const char *prefix_name (enum address_mode, uint8_t, int);

enum x86_64_isa

{

  amd64 = 1,

  intel64

};

struct instr_info

{

  enum address_mode address_mode;

  /* Flags for the prefixes for the current instruction.  See below.  */

  int prefixes;

  /* REX prefix the current instruction.  See below.  */

  uint8_t rex;

  /* Bits of REX we've already used.  */

  uint8_t rex_used;

  bool need_modrm;

  unsigned char need_vex;

  bool has_sib;

  /* Flags for ins->prefixes which we somehow handled when printing the

     current instruction.  */

  int used_prefixes;

  /* Flags for EVEX bits which we somehow handled when printing the

     current instruction.  */

  int evex_used;

  char obuf[MAX_OPERAND_BUFFER_SIZE];

  char *obufp;

  char *mnemonicendp;

  const uint8_t *start_codep;

  uint8_t *codep;

  const uint8_t *end_codep;

  unsigned char nr_prefixes;

  signed char last_lock_prefix;

  signed char last_repz_prefix;

  signed char last_repnz_prefix;

  signed char last_data_prefix;

  signed char last_addr_prefix;

  signed char last_rex_prefix;

  signed char last_seg_prefix;

  signed char fwait_prefix;

  /* The active segment register prefix.  */

  unsigned char active_seg_prefix;

#define MAX_CODE_LENGTH 15

  /* We can up to 14 ins->prefixes since the maximum instruction length is

     15bytes.  */

  uint8_t all_prefixes[MAX_CODE_LENGTH - 1];

  disassemble_info *info;

  struct

  {

    int mod;

    int reg;

    int rm;

  }

  modrm;

  struct

  {

    int scale;

    int index;

    int base;

  }

  sib;

  struct

  {

    int register_specifier;

    int length;

    int prefix;

    int mask_register_specifier;

    int ll;

    bool w;

    bool evex;

    bool r;

    bool v;

    bool zeroing;

    bool b;

    bool no_broadcast;

  }

  vex;

  /* Remember if the current op is a jump instruction.  */

  bool op_is_jump;

  bool two_source_ops;

  /* Record whether EVEX masking is used incorrectly.  */

  bool illegal_masking;

  unsigned char op_ad;

  signed char op_index[MAX_OPERANDS];

  bool op_riprel[MAX_OPERANDS];

  char *op_out[MAX_OPERANDS];

  bfd_vma op_address[MAX_OPERANDS];

  bfd_vma start_pc;

  /* On the 386's of 1988, the maximum length of an instruction is 15 bytes.

   *   (see topic "Redundant ins->prefixes" in the "Differences from 8086"

   *   section of the "Virtual 8086 Mode" chapter.)

   * 'pc' should be the address of this instruction, it will

   *   be used to print the target address if this is a relative jump or call

   * The function returns the length of this instruction in bytes.

   */

  char intel_syntax;

  bool intel_mnemonic;

  char open_char;

  char close_char;

  char separator_char;

  char scale_char;

  enum x86_64_isa isa64;

};

struct dis_private {

  bfd_vma insn_start;

  int orig_sizeflag;

  /* Indexes first byte not fetched.  */

  unsigned int fetched;

  uint8_t the_buffer[2 * MAX_CODE_LENGTH - 1];

};

/* Mark parts used in the REX prefix.  When we are testing for

   empty prefix (for 8bit register REX extension), just mask it

   out.  Otherwise test for REX bit is excuse for existence of REX

   only in case value is nonzero.  */

#define USED_REX(value)         \

  {             \

    if (value)           \

      {             \

  if ((ins->rex & value))       \

    ins->rex_used |= (value) | REX_OPCODE; \

      }             \

    else            \

      ins->rex_used |= REX_OPCODE;     \

  }

#define EVEX_b_used 1

#define EVEX_len_used 2

/* Flags stored in PREFIXES.  */

#define PREFIX_REPZ 1

#define PREFIX_REPNZ 2

#define PREFIX_CS 4

#define PREFIX_SS 8

#define PREFIX_DS 0x10

#define PREFIX_ES 0x20

#define PREFIX_FS 0x40

#define PREFIX_GS 0x80

#define PREFIX_LOCK 0x100

#define PREFIX_DATA 0x200

#define PREFIX_ADDR 0x400

#define PREFIX_FWAIT 0x800

/* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)

   to ADDR (exclusive) are valid.  Returns true for success, false

   on error.  */

static bool

fetch_code (struct disassemble_info *info, const uint8_t *until)

{

  int status = -1;

  struct dis_private *priv = info->private_data;

  bfd_vma start = priv->insn_start + priv->fetched;

  uint8_t *fetch_end = priv->the_buffer + priv->fetched;

  ptrdiff_t needed = until - fetch_end;

  if (needed <= 0)

    return true;

  if (priv->fetched + (size_t) needed <= ARRAY_SIZE (priv->the_buffer))

    status = (*info->read_memory_func) (start, fetch_end, needed, info);

  if (status != 0)

    {

      /* If we did manage to read at least one byte, then

   print_insn_i386 will do something sensible.  Otherwise, print

   an error.  We do that here because this is where we know

   STATUS.  */

      if (!priv->fetched)

  (*info->memory_error_func) (status, start, info);

      return false;

    }

  priv->fetched += needed;

  return true;

}

static bool

fetch_modrm (instr_info *ins)

{

  if (!fetch_code (ins->info, ins->codep + 1))

    return false;

  ins->modrm.mod = (*ins->codep >> 6) & 3;

  ins->modrm.reg = (*ins->codep >> 3) & 7;

  ins->modrm.rm = *ins->codep & 7;

  return true;

}

static int

fetch_error (const instr_info *ins)

{

  /* Getting here means we tried for data but didn't get it.  That

     means we have an incomplete instruction of some sort.  Just

     print the first byte as a prefix or a .byte pseudo-op.  */

  const struct dis_private *priv = ins->info->private_data;

  const char *name = NULL;

  if (ins->codep <= priv->the_buffer)

    return -1;

  if (ins->prefixes || ins->fwait_prefix >= 0 || (ins->rex & REX_OPCODE))

    name = prefix_name (ins->address_mode, priv->the_buffer[0],

      priv->orig_sizeflag);

  if (name != NULL)

    i386_dis_printf (ins->info, dis_style_mnemonic, "%s", name);

  else

    {

      /* Just print the first byte as a .byte instruction.  */

      i386_dis_printf (ins->info, dis_style_assembler_directive, ".byte ");

      i386_dis_printf (ins->info, dis_style_immediate, "%#x",

           (unsigned int) priv->the_buffer[0]);

    }

  return 1;

}

/* Possible values for prefix requirement.  */

#define PREFIX_IGNORED_SHIFT  16

#define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)

#define PREFIX_IGNORED_REPNZ  (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)

#define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT)

#define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)

#define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)

/* Opcode prefixes.  */

#define PREFIX_OPCODE   (PREFIX_REPZ \

         | PREFIX_REPNZ \

         | PREFIX_DATA)

/* Prefixes ignored.  */

#define PREFIX_IGNORED    (PREFIX_IGNORED_REPZ \

         | PREFIX_IGNORED_REPNZ \

         | PREFIX_IGNORED_DATA)

#define XX { NULL, 0 }

#define Bad_Opcode NULL, { { NULL, 0 } }, 0

#define Eb { OP_E, b_mode }

#define Ebnd { OP_E, bnd_mode }

#define EbS { OP_E, b_swap_mode }

#define EbndS { OP_E, bnd_swap_mode }

#define Ev { OP_E, v_mode }

#define Eva { OP_E, va_mode }

#define Ev_bnd { OP_E, v_bnd_mode }

#define EvS { OP_E, v_swap_mode }

#define Ed { OP_E, d_mode }

#define Edq { OP_E, dq_mode }

#define Edb { OP_E, db_mode }

#define Edw { OP_E, dw_mode }

#define Eq { OP_E, q_mode }

#define indirEv { OP_indirE, indir_v_mode }

#define indirEp { OP_indirE, f_mode }

#define stackEv { OP_E, stack_v_mode }

#define Em { OP_E, m_mode }

#define Ew { OP_E, w_mode }

#define M { OP_M, 0 }   /* lea, lgdt, etc. */

#define Ma { OP_M, a_mode }

#define Mb { OP_M, b_mode }

#define Md { OP_M, d_mode }

#define Mdq { OP_M, dq_mode }

#define Mo { OP_M, o_mode }

#define Mp { OP_M, f_mode }   /* 32 or 48 bit memory operand for LDS, LES etc */

#define Mq { OP_M, q_mode }

#define Mv { OP_M, v_mode }

#define Mv_bnd { OP_M, v_bndmk_mode }

#define Mw { OP_M, w_mode }

#define Mx { OP_M, x_mode }

#define Mxmm { OP_M, xmm_mode }

#define Mymm { OP_M, ymm_mode }

#define Gb { OP_G, b_mode }

#define Gbnd { OP_G, bnd_mode }

#define Gv { OP_G, v_mode }

#define Gd { OP_G, d_mode }

#define Gdq { OP_G, dq_mode }

#define Gm { OP_G, m_mode }

#define Gva { OP_G, va_mode }

#define Gw { OP_G, w_mode }

#define Ib { OP_I, b_mode }

#define sIb { OP_sI, b_mode } /* sign extened byte */

#define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */

#define Iv { OP_I, v_mode }

#define sIv { OP_sI, v_mode }

#define Iv64 { OP_I64, v_mode }

#define Id { OP_I, d_mode }

#define Iw { OP_I, w_mode }

#define I1 { OP_I, const_1_mode }

#define Jb { OP_J, b_mode }

#define Jv { OP_J, v_mode }

#define Jdqw { OP_J, dqw_mode }

#define Cm { OP_C, m_mode }

#define Dm { OP_D, m_mode }

#define Td { OP_T, d_mode }

#define Skip_MODRM { OP_Skip_MODRM, 0 }

#define RMeAX { OP_REG, eAX_reg }

#define RMeBX { OP_REG, eBX_reg }

#define RMeCX { OP_REG, eCX_reg }

#define RMeDX { OP_REG, eDX_reg }

#define RMeSP { OP_REG, eSP_reg }

#define RMeBP { OP_REG, eBP_reg }

#define RMeSI { OP_REG, eSI_reg }

#define RMeDI { OP_REG, eDI_reg }

#define RMrAX { OP_REG, rAX_reg }

#define RMrBX { OP_REG, rBX_reg }

#define RMrCX { OP_REG, rCX_reg }

#define RMrDX { OP_REG, rDX_reg }

#define RMrSP { OP_REG, rSP_reg }

#define RMrBP { OP_REG, rBP_reg }

#define RMrSI { OP_REG, rSI_reg }

#define RMrDI { OP_REG, rDI_reg }

#define RMAL { OP_REG, al_reg }

#define RMCL { OP_REG, cl_reg }

#define RMDL { OP_REG, dl_reg }

#define RMBL { OP_REG, bl_reg }

#define RMAH { OP_REG, ah_reg }

#define RMCH { OP_REG, ch_reg }

#define RMDH { OP_REG, dh_reg }

#define RMBH { OP_REG, bh_reg }

#define RMAX { OP_REG, ax_reg }

#define RMDX { OP_REG, dx_reg }

#define eAX { OP_IMREG, eAX_reg }

#define AL { OP_IMREG, al_reg }

#define CL { OP_IMREG, cl_reg }

#define zAX { OP_IMREG, z_mode_ax_reg }

#define indirDX { OP_IMREG, indir_dx_reg }

#define Sw { OP_SEG, w_mode }

#define Sv { OP_SEG, v_mode }

#define Ap { OP_DIR, 0 }

#define Ob { OP_OFF64, b_mode }

#define Ov { OP_OFF64, v_mode }

#define Xb { OP_DSreg, eSI_reg }

#define Xv { OP_DSreg, eSI_reg }

#define Xz { OP_DSreg, eSI_reg }

#define Yb { OP_ESreg, eDI_reg }

#define Yv { OP_ESreg, eDI_reg }

#define DSBX { OP_DSreg, eBX_reg }

#define es { OP_REG, es_reg }

#define ss { OP_REG, ss_reg }

#define cs { OP_REG, cs_reg }

#define ds { OP_REG, ds_reg }

#define fs { OP_REG, fs_reg }

#define gs { OP_REG, gs_reg }

#define MX { OP_MMX, 0 }

#define XM { OP_XMM, 0 }

#define XMScalar { OP_XMM, scalar_mode }

#define XMGatherD { OP_XMM, vex_vsib_d_w_dq_mode }

#define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }

#define XMM { OP_XMM, xmm_mode }

#define TMM { OP_XMM, tmm_mode }

#define XMxmmq { OP_XMM, xmmq_mode }

#define EM { OP_EM, v_mode }

#define EMS { OP_EM, v_swap_mode }

#define EMd { OP_EM, d_mode }

#define EMx { OP_EM, x_mode }

#define EXbwUnit { OP_EX, bw_unit_mode }

#define EXb { OP_EX, b_mode }

#define EXw { OP_EX, w_mode }

#define EXd { OP_EX, d_mode }

#define EXdS { OP_EX, d_swap_mode }

#define EXwS { OP_EX, w_swap_mode }

#define EXq { OP_EX, q_mode }

#define EXqS { OP_EX, q_swap_mode }

#define EXdq { OP_EX, dq_mode }

#define EXx { OP_EX, x_mode }

#define EXxh { OP_EX, xh_mode }

#define EXxS { OP_EX, x_swap_mode }

#define EXxmm { OP_EX, xmm_mode }

#define EXymm { OP_EX, ymm_mode }

#define EXxmmq { OP_EX, xmmq_mode }

#define EXxmmqh { OP_EX, evex_half_bcst_xmmqh_mode }

#define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }

#define EXxmmdw { OP_EX, xmmdw_mode }

#define EXxmmqd { OP_EX, xmmqd_mode }

#define EXxmmqdh { OP_EX, evex_half_bcst_xmmqdh_mode }

#define EXymmq { OP_EX, ymmq_mode }

#define EXEvexXGscat { OP_EX, evex_x_gscat_mode }

#define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }

#define Rd { OP_R, d_mode }

#define Rdq { OP_R, dq_mode }

#define Nq { OP_R, q_mode }

#define Ux { OP_R, x_mode }

#define Uxmm { OP_R, xmm_mode }

#define Rxmmq { OP_R, xmmq_mode }

#define Rymm { OP_R, ymm_mode }

#define Rtmm { OP_R, tmm_mode }

#define EMCq { OP_EMC, q_mode }

#define MXC { OP_MXC, 0 }

#define OPSUF { OP_3DNowSuffix, 0 }

#define SEP { SEP_Fixup, 0 }

#define CMP { CMP_Fixup, 0 }

#define XMM0 { XMM_Fixup, 0 }

#define FXSAVE { FXSAVE_Fixup, 0 }

#define Vex { OP_VEX, x_mode }

#define VexW { OP_VexW, x_mode }

#define VexScalar { OP_VEX, scalar_mode }

#define VexScalarR { OP_VexR, scalar_mode }

#define VexGatherD { OP_VEX, vex_vsib_d_w_dq_mode }

#define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }

#define VexGdq { OP_VEX, dq_mode }

#define VexTmm { OP_VEX, tmm_mode }

#define XMVexI4 { OP_REG_VexI4, x_mode }

#define XMVexScalarI4 { OP_REG_VexI4, scalar_mode }

#define VexI4 { OP_VexI4, 0 }

#define PCLMUL { PCLMUL_Fixup, 0 }

#define VPCMP { VPCMP_Fixup, 0 }

#define VPCOM { VPCOM_Fixup, 0 }

#define EXxEVexR { OP_Rounding, evex_rounding_mode }

#define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }

#define EXxEVexS { OP_Rounding, evex_sae_mode }

#define MaskG { OP_G, mask_mode }

#define MaskE { OP_E, mask_mode }

#define MaskR { OP_R, mask_mode }

#define MaskBDE { OP_E, mask_bd_mode }

#define MaskVex { OP_VEX, mask_mode }

#define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }

#define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }

#define MVexSIBMEM { OP_M, vex_sibmem_mode }

/* Used handle "rep" prefix for string instructions.  */

#define Xbr { REP_Fixup, eSI_reg }

#define Xvr { REP_Fixup, eSI_reg }

#define Ybr { REP_Fixup, eDI_reg }

#define Yvr { REP_Fixup, eDI_reg }

#define Yzr { REP_Fixup, eDI_reg }

#define indirDXr { REP_Fixup, indir_dx_reg }

#define ALr { REP_Fixup, al_reg }

#define eAXr { REP_Fixup, eAX_reg }

/* Used handle HLE prefix for lockable instructions.  */

#define Ebh1 { HLE_Fixup1, b_mode }

#define Evh1 { HLE_Fixup1, v_mode }

#define Ebh2 { HLE_Fixup2, b_mode }

#define Evh2 { HLE_Fixup2, v_mode }

#define Ebh3 { HLE_Fixup3, b_mode }

#define Evh3 { HLE_Fixup3, v_mode }

#define BND { BND_Fixup, 0 }

#define NOTRACK { NOTRACK_Fixup, 0 }

#define cond_jump_flag { NULL, cond_jump_mode }

#define loop_jcxz_flag { NULL, loop_jcxz_mode }

/* bits in sizeflag */

#define SUFFIX_ALWAYS 4

#define AFLAG 2

#define DFLAG 1

enum

{

  /* byte operand */

  b_mode = 1,

  /* byte operand with operand swapped */

  b_swap_mode,

  /* byte operand, sign extend like 'T' suffix */

  b_T_mode,

  /* operand size depends on prefixes */

  v_mode,

  /* operand size depends on prefixes with operand swapped */

  v_swap_mode,

  /* operand size depends on address prefix */

  va_mode,

  /* word operand */

  w_mode,

  /* double word operand  */

  d_mode,

  /* word operand with operand swapped  */

  w_swap_mode,

  /* double word operand with operand swapped */

  d_swap_mode,

  /* quad word operand */

  q_mode,

  /* quad word operand with operand swapped */

  q_swap_mode,

  /* ten-byte operand */

  t_mode,

  /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with

     broadcast enabled.  */

  x_mode,

  /* Similar to x_mode, but with different EVEX mem shifts.  */

  evex_x_gscat_mode,

  /* Similar to x_mode, but with yet different EVEX mem shifts.  */

  bw_unit_mode,

  /* Similar to x_mode, but with disabled broadcast.  */

  evex_x_nobcst_mode,

  /* Similar to x_mode, but with operands swapped and disabled broadcast

     in EVEX.  */

  x_swap_mode,

  /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with

     broadcast of 16bit enabled.  */

  xh_mode,

  /* 16-byte XMM operand */

  xmm_mode,

  /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword

     memory operand (depending on vector length).  Broadcast isn't

     allowed.  */

  xmmq_mode,

  /* Same as xmmq_mode, but broadcast is allowed.  */

  evex_half_bcst_xmmq_mode,

  /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword

     memory operand (depending on vector length).  16bit broadcast.  */

  evex_half_bcst_xmmqh_mode,

  /* 16-byte XMM, word, double word or quad word operand.  */

  xmmdw_mode,

  /* 16-byte XMM, double word, quad word operand or xmm word operand.  */

  xmmqd_mode,

  /* 16-byte XMM, double word, quad word operand or xmm word operand.

     16bit broadcast.  */

  evex_half_bcst_xmmqdh_mode,

  /* 32-byte YMM operand */

  ymm_mode,

  /* quad word, ymmword or zmmword memory operand.  */

  ymmq_mode,

  /* TMM operand */

  tmm_mode,

  /* d_mode in 32bit, q_mode in 64bit mode.  */

  m_mode,

  /* pair of v_mode operands */

  a_mode,

  cond_jump_mode,

  loop_jcxz_mode,

  movsxd_mode,

  v_bnd_mode,

  /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode.  */

  v_bndmk_mode,

  /* operand size depends on REX.W / VEX.W.  */

  dq_mode,

  /* Displacements like v_mode without considering Intel64 ISA.  */

  dqw_mode,

  /* bounds operand */

  bnd_mode,

  /* bounds operand with operand swapped */

  bnd_swap_mode,

  /* 4- or 6-byte pointer operand */

  f_mode,

  const_1_mode,

  /* v_mode for indirect branch opcodes.  */

  indir_v_mode,

  /* v_mode for stack-related opcodes.  */

  stack_v_mode,

  /* non-quad operand size depends on prefixes */

  z_mode,

  /* 16-byte operand */

  o_mode,

  /* registers like d_mode, memory like b_mode.  */

  db_mode,

  /* registers like d_mode, memory like w_mode.  */

  dw_mode,

  /* Operand size depends on the VEX.W bit, with VSIB dword indices.  */

  vex_vsib_d_w_dq_mode,

  /* Operand size depends on the VEX.W bit, with VSIB qword indices.  */

  vex_vsib_q_w_dq_mode,

  /* mandatory non-vector SIB.  */

  vex_sibmem_mode,

  /* scalar, ignore vector length.  */

  scalar_mode,

  /* Static rounding.  */

  evex_rounding_mode,

  /* Static rounding, 64-bit mode only.  */

  evex_rounding_64_mode,

  /* Supress all exceptions.  */

  evex_sae_mode,

  /* Mask register operand.  */

  mask_mode,

  /* Mask register operand.  */

  mask_bd_mode,

  es_reg,

  cs_reg,

  ss_reg,

  ds_reg,

  fs_reg,

  gs_reg,

  eAX_reg,

  eCX_reg,

  eDX_reg,

  eBX_reg,

  eSP_reg,

  eBP_reg,

  eSI_reg,

  eDI_reg,

  al_reg,

  cl_reg,

  dl_reg,

  bl_reg,

  ah_reg,

  ch_reg,

  dh_reg,

  bh_reg,

  ax_reg,

  cx_reg,

  dx_reg,

  bx_reg,

  sp_reg,

  bp_reg,

  si_reg,

  di_reg,

  rAX_reg,

  rCX_reg,

  rDX_reg,

  rBX_reg,

  rSP_reg,

  rBP_reg,

  rSI_reg,

  rDI_reg,

  z_mode_ax_reg,

  indir_dx_reg

};

enum

{

  FLOATCODE = 1,

  USE_REG_TABLE,

  USE_MOD_TABLE,

  USE_RM_TABLE,

  USE_PREFIX_TABLE,

  USE_X86_64_TABLE,

  USE_3BYTE_TABLE,

  USE_XOP_8F_TABLE,

  USE_VEX_C4_TABLE,

  USE_VEX_C5_TABLE,

  USE_VEX_LEN_TABLE,

  USE_VEX_W_TABLE,

  USE_EVEX_TABLE,

  USE_EVEX_LEN_TABLE

};

#define FLOAT     NULL, { { NULL, FLOATCODE } }, 0

#define DIS386(T, I)    NULL, { { NULL, (T)}, { NULL,  (I) } }, 0

#define REG_TABLE(I)    DIS386 (USE_REG_TABLE, (I))

#define MOD_TABLE(I)    DIS386 (USE_MOD_TABLE, (I))

#define RM_TABLE(I)   DIS386 (USE_RM_TABLE, (I))

#define PREFIX_TABLE(I)   DIS386 (USE_PREFIX_TABLE, (I))

#define X86_64_TABLE(I)   DIS386 (USE_X86_64_TABLE, (I))

#define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))

#define XOP_8F_TABLE()    DIS386 (USE_XOP_8F_TABLE, 0)

#define VEX_C4_TABLE()    DIS386 (USE_VEX_C4_TABLE, 0)

#define VEX_C5_TABLE()    DIS386 (USE_VEX_C5_TABLE, 0)

#define VEX_LEN_TABLE(I)  DIS386 (USE_VEX_LEN_TABLE, (I))

#define VEX_W_TABLE(I)    DIS386 (USE_VEX_W_TABLE, (I))

#define EVEX_TABLE()    DIS386 (USE_EVEX_TABLE, 0)

#define EVEX_LEN_TABLE(I) DIS386 (USE_EVEX_LEN_TABLE, (I))

enum

{

  REG_80 = 0,

  REG_81,

  REG_83,

  REG_8F,

  REG_C0,

  REG_C1,

  REG_C6,

  REG_C7,

  REG_D0,

  REG_D1,

  REG_D2,

  REG_D3,

  REG_F6,

  REG_F7,

  REG_FE,

  REG_FF,

  REG_0F00,

  REG_0F01,

  REG_0F0D,

  REG_0F18,

  REG_0F1C_P_0_MOD_0,

  REG_0F1E_P_1_MOD_3,

  REG_0F38D8_PREFIX_1,

  REG_0F3A0F_P_1,

  REG_0F71,

  REG_0F72,

  REG_0F73,

  REG_0FA6,

  REG_0FA7,

  REG_0FAE,

  REG_0FBA,

  REG_0FC7,

  REG_VEX_0F71,

  REG_VEX_0F72,

  REG_VEX_0F73,

  REG_VEX_0FAE,

  REG_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0,

  REG_VEX_0F38F3_L_0,

  REG_XOP_09_01_L_0,

  REG_XOP_09_02_L_0,

  REG_XOP_09_12_L_0,

  REG_XOP_0A_12_L_0,

  REG_EVEX_0F71,

  REG_EVEX_0F72,

  REG_EVEX_0F73,

  REG_EVEX_0F38C6_L_2,

  REG_EVEX_0F38C7_L_2

};

enum

{

  MOD_62_32BIT = 0,

  MOD_C4_32BIT,

  MOD_C5_32BIT,

  MOD_0F01_REG_0,

  MOD_0F01_REG_1,

  MOD_0F01_REG_2,

  MOD_0F01_REG_3,

  MOD_0F01_REG_5,

  MOD_0F01_REG_7,

  MOD_0F12_PREFIX_0,

  MOD_0F16_PREFIX_0,

  MOD_0F18_REG_0,

  MOD_0F18_REG_1,

  MOD_0F18_REG_2,

  MOD_0F18_REG_3,

  MOD_0F18_REG_6,

  MOD_0F18_REG_7,

  MOD_0F1A_PREFIX_0,

  MOD_0F1B_PREFIX_0,

  MOD_0F1B_PREFIX_1,

  MOD_0F1C_PREFIX_0,

  MOD_0F1E_PREFIX_1,

  MOD_0FAE_REG_0,

  MOD_0FAE_REG_1,

  MOD_0FAE_REG_2,

  MOD_0FAE_REG_3,

  MOD_0FAE_REG_4,

  MOD_0FAE_REG_5,

  MOD_0FAE_REG_6,

  MOD_0FAE_REG_7,

  MOD_0FC7_REG_6,

  MOD_0FC7_REG_7,

  MOD_0F38DC_PREFIX_1,

  MOD_VEX_0F3849_X86_64_L_0_W_0,

};

enum

{

  RM_C6_REG_7 = 0,

  RM_C7_REG_7,

  RM_0F01_REG_0,

  RM_0F01_REG_1,

  RM_0F01_REG_2,

  RM_0F01_REG_3,

  RM_0F01_REG_5_MOD_3,

  RM_0F01_REG_7_MOD_3,

  RM_0F1E_P_1_MOD_3_REG_7,

  RM_0FAE_REG_6_MOD_3_P_0,

  RM_0FAE_REG_7_MOD_3,

  RM_0F3A0F_P_1_R_0,

  RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0_R_0,

  RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_3,

};

enum

{

  PREFIX_90 = 0,

  PREFIX_0F00_REG_6_X86_64,

  PREFIX_0F01_REG_0_MOD_3_RM_6,

  PREFIX_0F01_REG_0_MOD_3_RM_7,

  PREFIX_0F01_REG_1_RM_2,

  PREFIX_0F01_REG_1_RM_4,

  PREFIX_0F01_REG_1_RM_5,

  PREFIX_0F01_REG_1_RM_6,

  PREFIX_0F01_REG_1_RM_7,

  PREFIX_0F01_REG_3_RM_1,

  PREFIX_0F01_REG_5_MOD_0,

  PREFIX_0F01_REG_5_MOD_3_RM_0,

  PREFIX_0F01_REG_5_MOD_3_RM_1,

  PREFIX_0F01_REG_5_MOD_3_RM_2,

  PREFIX_0F01_REG_5_MOD_3_RM_4,

  PREFIX_0F01_REG_5_MOD_3_RM_5,

  PREFIX_0F01_REG_5_MOD_3_RM_6,

  PREFIX_0F01_REG_5_MOD_3_RM_7,

  PREFIX_0F01_REG_7_MOD_3_RM_2,

  PREFIX_0F01_REG_7_MOD_3_RM_5,

  PREFIX_0F01_REG_7_MOD_3_RM_6,

  PREFIX_0F01_REG_7_MOD_3_RM_7,

  PREFIX_0F09,

  PREFIX_0F10,

  PREFIX_0F11,

  PREFIX_0F12,

  PREFIX_0F16,

  PREFIX_0F18_REG_6_MOD_0_X86_64,

  PREFIX_0F18_REG_7_MOD_0_X86_64,

  PREFIX_0F1A,

  PREFIX_0F1B,

  PREFIX_0F1C,

  PREFIX_0F1E,

  PREFIX_0F2A,

  PREFIX_0F2B,

  PREFIX_0F2C,

  PREFIX_0F2D,

  PREFIX_0F2E,

  PREFIX_0F2F,

  PREFIX_0F51,

  PREFIX_0F52,

  PREFIX_0F53,

  PREFIX_0F58,

  PREFIX_0F59,

  PREFIX_0F5A,

  PREFIX_0F5B,

  PREFIX_0F5C,

  PREFIX_0F5D,

  PREFIX_0F5E,

  PREFIX_0F5F,

  PREFIX_0F60,

  PREFIX_0F61,

  PREFIX_0F62,

  PREFIX_0F6F,

  PREFIX_0F70,

  PREFIX_0F78,

  PREFIX_0F79,

  PREFIX_0F7C,

  PREFIX_0F7D,

  PREFIX_0F7E,

  PREFIX_0F7F,

  PREFIX_0FAE_REG_0_MOD_3,

  PREFIX_0FAE_REG_1_MOD_3,

  PREFIX_0FAE_REG_2_MOD_3,

  PREFIX_0FAE_REG_3_MOD_3,

  PREFIX_0FAE_REG_4_MOD_0,

  PREFIX_0FAE_REG_4_MOD_3,

  PREFIX_0FAE_REG_5_MOD_3,

  PREFIX_0FAE_REG_6_MOD_0,

  PREFIX_0FAE_REG_6_MOD_3,

  PREFIX_0FAE_REG_7_MOD_0,

  PREFIX_0FB8,

  PREFIX_0FBC,

  PREFIX_0FBD,

  PREFIX_0FC2,

  PREFIX_0FC7_REG_6_MOD_0,

  PREFIX_0FC7_REG_6_MOD_3,

  PREFIX_0FC7_REG_7_MOD_3,

  PREFIX_0FD0,

  PREFIX_0FD6,

  PREFIX_0FE6,

  PREFIX_0FE7,

  PREFIX_0FF0,

  PREFIX_0FF7,

  PREFIX_0F38D8,

  PREFIX_0F38DC,

  PREFIX_0F38DD,

  PREFIX_0F38DE,

  PREFIX_0F38DF,

  PREFIX_0F38F0,

  PREFIX_0F38F1,

  PREFIX_0F38F6,

  PREFIX_0F38F8,

  PREFIX_0F38FA,

  PREFIX_0F38FB,

  PREFIX_0F38FC,

  PREFIX_0F3A0F,

  PREFIX_VEX_0F12,

  PREFIX_VEX_0F16,

  PREFIX_VEX_0F2A,

  PREFIX_VEX_0F2C,

  PREFIX_VEX_0F2D,

  PREFIX_VEX_0F41_L_1_W_0,

  PREFIX_VEX_0F41_L_1_W_1,

  PREFIX_VEX_0F42_L_1_W_0,

  PREFIX_VEX_0F42_L_1_W_1,

  PREFIX_VEX_0F44_L_0_W_0,

  PREFIX_VEX_0F44_L_0_W_1,

  PREFIX_VEX_0F45_L_1_W_0,

  PREFIX_VEX_0F45_L_1_W_1,

  PREFIX_VEX_0F46_L_1_W_0,

  PREFIX_VEX_0F46_L_1_W_1,

  PREFIX_VEX_0F47_L_1_W_0,

  PREFIX_VEX_0F47_L_1_W_1,

  PREFIX_VEX_0F4A_L_1_W_0,

  PREFIX_VEX_0F4A_L_1_W_1,

  PREFIX_VEX_0F4B_L_1_W_0,

  PREFIX_VEX_0F4B_L_1_W_1,

  PREFIX_VEX_0F6F,

  PREFIX_VEX_0F70,

  PREFIX_VEX_0F7E,

  PREFIX_VEX_0F7F,

  PREFIX_VEX_0F90_L_0_W_0,

  PREFIX_VEX_0F90_L_0_W_1,

  PREFIX_VEX_0F91_L_0_W_0,

  PREFIX_VEX_0F91_L_0_W_1,

  PREFIX_VEX_0F92_L_0_W_0,

  PREFIX_VEX_0F92_L_0_W_1,

  PREFIX_VEX_0F93_L_0_W_0,

  PREFIX_VEX_0F93_L_0_W_1,

  PREFIX_VEX_0F98_L_0_W_0,

  PREFIX_VEX_0F98_L_0_W_1,

  PREFIX_VEX_0F99_L_0_W_0,

  PREFIX_VEX_0F99_L_0_W_1,

  PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_0,

  PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_1,

  PREFIX_VEX_0F384B_X86_64_L_0_W_0,

  PREFIX_VEX_0F3850_W_0,

  PREFIX_VEX_0F3851_W_0,

  PREFIX_VEX_0F385C_X86_64_L_0_W_0,

  PREFIX_VEX_0F385E_X86_64_L_0_W_0,

  PREFIX_VEX_0F386C_X86_64_L_0_W_0,

  PREFIX_VEX_0F3872,

  PREFIX_VEX_0F38B0_W_0,

  PREFIX_VEX_0F38B1_W_0,

  PREFIX_VEX_0F38D2_W_0,

  PREFIX_VEX_0F38D3_W_0,

  PREFIX_VEX_0F38CB,

  PREFIX_VEX_0F38CC,

  PREFIX_VEX_0F38CD,

  PREFIX_VEX_0F38DA_W_0,

  PREFIX_VEX_0F38F5_L_0,

  PREFIX_VEX_0F38F6_L_0,

  PREFIX_VEX_0F38F7_L_0,

  PREFIX_VEX_0F3AF0_L_0,

  PREFIX_EVEX_0F5B,

  PREFIX_EVEX_0F6F,

  PREFIX_EVEX_0F70,

  PREFIX_EVEX_0F78,

  PREFIX_EVEX_0F79,

  PREFIX_EVEX_0F7A,

  PREFIX_EVEX_0F7B,

  PREFIX_EVEX_0F7E,

  PREFIX_EVEX_0F7F,

  PREFIX_EVEX_0FC2,

  PREFIX_EVEX_0FE6,

  PREFIX_EVEX_0F3810,

  PREFIX_EVEX_0F3811,

  PREFIX_EVEX_0F3812,

  PREFIX_EVEX_0F3813,

  PREFIX_EVEX_0F3814,

  PREFIX_EVEX_0F3815,

  PREFIX_EVEX_0F3820,

  PREFIX_EVEX_0F3821,

  PREFIX_EVEX_0F3822,

  PREFIX_EVEX_0F3823,

  PREFIX_EVEX_0F3824,

  PREFIX_EVEX_0F3825,

  PREFIX_EVEX_0F3826,

  PREFIX_EVEX_0F3827,

  PREFIX_EVEX_0F3828,

  PREFIX_EVEX_0F3829,

  PREFIX_EVEX_0F382A,

  PREFIX_EVEX_0F3830,