/src/binutils-gdb/opcodes/dlx-dis.c

Source (jump to first uncovered line)
/* Instruction printing code for the DLX Microprocessor
   Copyright (C) 2002-2023 Free Software Foundation, Inc.
   Contributed by Kuang Hwa Lin.  Written by Kuang Hwa Lin, 03/2002.

   This file is part of the GNU opcodes library.

   This library is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 3, or (at your option)
   any later version.

   It is distributed in the hope that it will be useful, but WITHOUT
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
   License for more details.

   You should have received a copy of the GNU General Public License
   along with this program; if not, write to the Free Software
   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
   MA 02110-1301, USA.  */

#include "sysdep.h"
#include "disassemble.h"
#include "opcode/dlx.h"

#define R_ERROR     0x1
#define R_TYPE      0x2
#define ILD_TYPE    0x3
#define IST_TYPE    0x4
#define IAL_TYPE    0x5
#define IBR_TYPE    0x6
#define IJ_TYPE     0x7
#define IJR_TYPE    0x8
#define NIL         0x9

#define OPC(x)      ((x >> 26) & 0x3F)
#define FUNC(x)     (x & 0x7FF)

unsigned char opc, rs1, rs2, rd;
unsigned long imm26, imm16, func, current_insn_addr;

/* Print one instruction from MEMADDR on INFO->STREAM.
   Return the size of the instruction (always 4 on dlx).  */

static unsigned char
dlx_get_opcode (unsigned long opcode)
{
  return (unsigned char) ((opcode >> 26) & 0x3F);
}

static unsigned char
dlx_get_rs1 (unsigned long opcode)
{
  return (unsigned char) ((opcode >> 21) & 0x1F);
}

static unsigned char
dlx_get_rs2 (unsigned long opcode)
{
  return (unsigned char) ((opcode >> 16) & 0x1F);
}

static unsigned char
dlx_get_rdR (unsigned long opcode)
{
  return (unsigned char) ((opcode >> 11) & 0x1F);
}

static unsigned long
dlx_get_func (unsigned long opcode)
{
  return (unsigned char) (opcode & 0x7FF);
}

static unsigned long
dlx_get_imm16 (unsigned long opcode)
{
  return (unsigned long) (opcode & 0xFFFF);
}

static unsigned long
dlx_get_imm26 (unsigned long opcode)
{
  return (unsigned long) (opcode & 0x03FFFFFF);
}

/* Fill the opcode to the max length.  */

static void
operand_deliminator (struct disassemble_info *info, char *ptr)
{
  int difft = 8 - (int) strlen (ptr);

  while (difft > 0)
    {
      (*info->fprintf_func) (info->stream, "%c", ' ');
      difft -= 1;
    }
}

/* Process the R-type opcode.  */

static unsigned char
dlx_r_type (struct disassemble_info *info)
{
  unsigned char r_opc[] = { OPC(ALUOP) }; /* Fix ME */
  int r_opc_num = (sizeof r_opc) / (sizeof (char));
  struct _r_opcode
  {
    unsigned long func;
    char *name;
  }
  dlx_r_opcode[] =
  {
    { NOPF,     "nop"    },  /* NOP                          */
    { ADDF,     "add"    },  /* Add                          */
    { ADDUF,    "addu"   },  /* Add Unsigned                 */
    { SUBF,     "sub"    },  /* SUB                          */
    { SUBUF,    "subu"   },  /* Sub Unsigned                 */
    { MULTF,    "mult"   },  /* MULTIPLY                     */
    { MULTUF,   "multu"  },  /* MULTIPLY Unsigned            */
    { DIVF,     "div"    },  /* DIVIDE                       */
    { DIVUF,    "divu"   },  /* DIVIDE Unsigned              */
    { ANDF,     "and"    },  /* AND                          */
    { ORF,      "or"     },  /* OR                           */
    { XORF,     "xor"    },  /* Exclusive OR                 */
    { SLLF,     "sll"    },  /* SHIFT LEFT LOGICAL           */
    { SRAF,     "sra"    },  /* SHIFT RIGHT ARITHMETIC       */
    { SRLF,     "srl"    },  /* SHIFT RIGHT LOGICAL          */
    { SEQF,     "seq"    },  /* Set if equal                 */
    { SNEF,     "sne"    },  /* Set if not equal             */
    { SLTF,     "slt"    },  /* Set if less                  */
    { SGTF,     "sgt"    },  /* Set if greater               */
    { SLEF,     "sle"    },  /* Set if less or equal         */
    { SGEF,     "sge"    },  /* Set if greater or equal      */
    { SEQUF,    "sequ"   },  /* Set if equal                 */
    { SNEUF,    "sneu"   },  /* Set if not equal             */
    { SLTUF,    "sltu"   },  /* Set if less                  */
    { SGTUF,    "sgtu"   },  /* Set if greater               */
    { SLEUF,    "sleu"   },  /* Set if less or equal         */
    { SGEUF,    "sgeu"   },  /* Set if greater or equal      */
    { MVTSF,    "mvts"   },  /* Move to special register     */
    { MVFSF,    "mvfs"   },  /* Move from special register   */
    { BSWAPF,   "bswap"  },  /* Byte swap ??                 */
    { LUTF,     "lut"    }   /* ????????? ??                 */
  };
  int dlx_r_opcode_num = (sizeof dlx_r_opcode) / (sizeof dlx_r_opcode[0]);
  int idx;

  for (idx = 0; idx < r_opc_num; idx++)
    {
      if (r_opc[idx] != opc)
  continue;
      else
  break;
    }

  if (idx == r_opc_num)
    return NIL;

  for (idx = 0 ; idx < dlx_r_opcode_num; idx++)
    if (dlx_r_opcode[idx].func == func)
      {
  (*info->fprintf_func) (info->stream, "%s", dlx_r_opcode[idx].name);

  if (func != NOPF)
    {
      /* This is not a nop.  */
      operand_deliminator (info, dlx_r_opcode[idx].name);
      (*info->fprintf_func) (info->stream, "r%d,", (int)rd);
      (*info->fprintf_func) (info->stream, "r%d", (int)rs1);
      if (func != MVTSF && func != MVFSF)
        (*info->fprintf_func) (info->stream, ",r%d", (int)rs2);
    }
  return (unsigned char) R_TYPE;
      }

  return (unsigned char) R_ERROR;
}

/* Process the memory read opcode.  */

static unsigned char
dlx_load_type (struct disassemble_info* info)
{
  struct _load_opcode
  {
    unsigned long opcode;
    char *name;
  }
  dlx_load_opcode[] =
  {
    { OPC(LHIOP),   "lhi" },  /* Load HI to register.           */
    { OPC(LBOP),     "lb" },  /* load byte sign extended.       */
    { OPC(LBUOP),   "lbu" },  /* load byte unsigned.            */
    { OPC(LSBUOP),"ldstbu"},  /* load store byte unsigned.      */
    { OPC(LHOP),     "lh" },  /* load halfword sign extended.   */
    { OPC(LHUOP),   "lhu" },  /* load halfword unsigned.        */
    { OPC(LSHUOP),"ldsthu"},  /* load store halfword unsigned.  */
    { OPC(LWOP),     "lw" },  /* load word.                     */
    { OPC(LSWOP), "ldstw" }   /* load store word.               */
  };
  int dlx_load_opcode_num =
    (sizeof dlx_load_opcode) / (sizeof dlx_load_opcode[0]);
  int idx;

  for (idx = 0 ; idx < dlx_load_opcode_num; idx++)
    if (dlx_load_opcode[idx].opcode == opc)
      {
  if (opc == OPC (LHIOP))
    {
      (*info->fprintf_func) (info->stream, "%s", dlx_load_opcode[idx].name);
      operand_deliminator (info, dlx_load_opcode[idx].name);
      (*info->fprintf_func) (info->stream, "r%d,", (int)rs2);
      (*info->fprintf_func) (info->stream, "0x%04x", (int)imm16);
    }
  else
    {
      (*info->fprintf_func) (info->stream, "%s", dlx_load_opcode[idx].name);
      operand_deliminator (info, dlx_load_opcode[idx].name);
      (*info->fprintf_func) (info->stream, "r%d,", (int)rs2);
      (*info->fprintf_func) (info->stream, "0x%04x[r%d]", (int)imm16, (int)rs1);
    }

  return (unsigned char) ILD_TYPE;
    }

  return (unsigned char) NIL;
}

/* Process the memory store opcode.  */

static unsigned char
dlx_store_type (struct disassemble_info* info)
{
  struct _store_opcode
  {
    unsigned long opcode;
    char *name;
  }
  dlx_store_opcode[] =
  {
    { OPC(SBOP),     "sb" },  /* Store byte.      */
    { OPC(SHOP),     "sh" },  /* Store halfword.  */
    { OPC(SWOP),     "sw" },  /* Store word.      */
  };
  int dlx_store_opcode_num =
    (sizeof dlx_store_opcode) / (sizeof dlx_store_opcode[0]);
  int idx;

  for (idx = 0 ; idx < dlx_store_opcode_num; idx++)
    if (dlx_store_opcode[idx].opcode == opc)
      {
  (*info->fprintf_func) (info->stream, "%s", dlx_store_opcode[idx].name);
  operand_deliminator (info, dlx_store_opcode[idx].name);
  (*info->fprintf_func) (info->stream, "0x%04x[r%d],", (int)imm16, (int)rs1);
  (*info->fprintf_func) (info->stream, "r%d", (int)rs2);
  return (unsigned char) IST_TYPE;
      }

  return (unsigned char) NIL;
}

/* Process the Arithmetic and Logical I-TYPE opcode.  */

static unsigned char
dlx_aluI_type (struct disassemble_info* info)
{
  struct _aluI_opcode
  {
    unsigned long opcode;
    char *name;
  }
  dlx_aluI_opcode[] =
  {
    { OPC(ADDIOP),   "addi"  },  /* Store byte.      */
    { OPC(ADDUIOP),  "addui" },  /* Store halfword.  */
    { OPC(SUBIOP),   "subi"  },  /* Store word.      */
    { OPC(SUBUIOP),  "subui" },  /* Store word.      */
    { OPC(ANDIOP),   "andi"  },  /* Store word.      */
    { OPC(ORIOP),    "ori"   },  /* Store word.      */
    { OPC(XORIOP),   "xori"  },  /* Store word.      */
    { OPC(SLLIOP),   "slli"  },  /* Store word.      */
    { OPC(SRAIOP),   "srai"  },  /* Store word.      */
    { OPC(SRLIOP),   "srli"  },  /* Store word.      */
    { OPC(SEQIOP),   "seqi"  },  /* Store word.      */
    { OPC(SNEIOP),   "snei"  },  /* Store word.      */
    { OPC(SLTIOP),   "slti"  },  /* Store word.      */
    { OPC(SGTIOP),   "sgti"  },  /* Store word.      */
    { OPC(SLEIOP),   "slei"  },  /* Store word.      */
    { OPC(SGEIOP),   "sgei"  },  /* Store word.      */
    { OPC(SEQUIOP),  "sequi" },  /* Store word.      */
    { OPC(SNEUIOP),  "sneui" },  /* Store word.      */
    { OPC(SLTUIOP),  "sltui" },  /* Store word.      */
    { OPC(SGTUIOP),  "sgtui" },  /* Store word.      */
    { OPC(SLEUIOP),  "sleui" },  /* Store word.      */
    { OPC(SGEUIOP),  "sgeui" },  /* Store word.      */
#if 0
    { OPC(MVTSOP),   "mvts"  },  /* Store word.      */
    { OPC(MVFSOP),   "mvfs"  },  /* Store word.      */
#endif
  };
  int dlx_aluI_opcode_num =
    (sizeof dlx_aluI_opcode) / (sizeof dlx_aluI_opcode[0]);
  int idx;

  for (idx = 0 ; idx < dlx_aluI_opcode_num; idx++)
    if (dlx_aluI_opcode[idx].opcode == opc)
      {
  (*info->fprintf_func) (info->stream, "%s", dlx_aluI_opcode[idx].name);
  operand_deliminator (info, dlx_aluI_opcode[idx].name);
  (*info->fprintf_func) (info->stream, "r%d,", (int)rs2);
  (*info->fprintf_func) (info->stream, "r%d,", (int)rs1);
  (*info->fprintf_func) (info->stream, "0x%04x", (int)imm16);

  return (unsigned char) IAL_TYPE;
      }

  return (unsigned char) NIL;
}

/* Process the branch instruction.  */

static unsigned char
dlx_br_type (struct disassemble_info* info)
{
  struct _br_opcode
  {
    unsigned long opcode;
    char *name;
  }
  dlx_br_opcode[] =
  {
    { OPC(BEQOP), "beqz" }, /* Store byte.  */
    { OPC(BNEOP), "bnez" }  /* Store halfword.  */
  };
  int dlx_br_opcode_num =
    (sizeof dlx_br_opcode) / (sizeof dlx_br_opcode[0]);
  int idx;

  for (idx = 0 ; idx < dlx_br_opcode_num; idx++)
    if (dlx_br_opcode[idx].opcode == opc)
      {
  if (imm16 & 0x00008000)
    imm16 |= 0xFFFF0000;

  imm16 += (current_insn_addr + 4);
  (*info->fprintf_func) (info->stream, "%s", dlx_br_opcode[idx].name);
  operand_deliminator (info, dlx_br_opcode[idx].name);
  (*info->fprintf_func) (info->stream, "r%d,", (int) rs1);
  (*info->fprintf_func) (info->stream, "0x%08x", (int) imm16);

  return (unsigned char) IBR_TYPE;
      }

  return (unsigned char) NIL;
}

/* Process the jump instruction.  */

static unsigned char
dlx_jmp_type (struct disassemble_info* info)
{
  struct _jmp_opcode
  {
    unsigned long opcode;
    char *name;
  }
  dlx_jmp_opcode[] =
  {
    { OPC(JOP),         "j" },  /* Store byte.      */
    { OPC(JALOP),     "jal" },  /* Store halfword.  */
    { OPC(BREAKOP), "break" },  /* Store halfword.  */
    { OPC(TRAPOP),   "trap" },  /* Store halfword.  */
    { OPC(RFEOP),     "rfe" }   /* Store halfword.  */
  };
  int dlx_jmp_opcode_num =
    (sizeof dlx_jmp_opcode) / (sizeof dlx_jmp_opcode[0]);
  int idx;

  for (idx = 0 ; idx < dlx_jmp_opcode_num; idx++)
    if (dlx_jmp_opcode[idx].opcode == opc)
      {
  if (imm26 & 0x02000000)
    imm26 |= 0xFC000000;

  imm26 += (current_insn_addr + 4);

  (*info->fprintf_func) (info->stream, "%s", dlx_jmp_opcode[idx].name);
  operand_deliminator (info, dlx_jmp_opcode[idx].name);
  (*info->fprintf_func) (info->stream, "0x%08x", (int)imm26);

  return (unsigned char) IJ_TYPE;
      }

  return (unsigned char) NIL;
}

/* Process the jump register instruction.  */

static unsigned char
dlx_jr_type (struct disassemble_info* info)
{
  struct _jr_opcode
  {
    unsigned long opcode;
    char *name;
  }
  dlx_jr_opcode[] =
  {
    { OPC(JROP),   "jr"    },  /* Store byte.  */
    { OPC(JALROP), "jalr"  }   /* Store halfword.  */
  };
  int dlx_jr_opcode_num =
    (sizeof dlx_jr_opcode) / (sizeof dlx_jr_opcode[0]);
  int idx;

  for (idx = 0 ; idx < dlx_jr_opcode_num; idx++)
    if (dlx_jr_opcode[idx].opcode == opc)
      {
  (*info->fprintf_func) (info->stream, "%s", dlx_jr_opcode[idx].name);
  operand_deliminator (info, dlx_jr_opcode[idx].name);
  (*info->fprintf_func) (info->stream, "r%d", (int)rs1);
  return (unsigned char) IJR_TYPE;
      }

  return (unsigned char) NIL;
}

typedef unsigned char (* dlx_insn) (struct disassemble_info *);

/* This is the main DLX insn handling routine.  */

int
print_insn_dlx (bfd_vma memaddr, struct disassemble_info* info)
{
  bfd_byte buffer[4];
  int insn_idx;
  unsigned long insn_word;
  dlx_insn dlx_insn_type[] =
  {
    dlx_r_type,
    dlx_load_type,
    dlx_store_type,
    dlx_aluI_type,
    dlx_br_type,
    dlx_jmp_type,
    dlx_jr_type,
    (dlx_insn) NULL
  };
  int dlx_insn_type_num = ((sizeof dlx_insn_type) / (sizeof (dlx_insn))) - 1;
  int status =
    (*info->read_memory_func) (memaddr, (bfd_byte *) &buffer[0], 4, info);

  if (status != 0)
    {
      (*info->memory_error_func) (status, memaddr, info);
      return -1;
    }

  /* Now decode the insn    */
  insn_word = bfd_getb32 (buffer);
  opc  = dlx_get_opcode (insn_word);
  rs1  = dlx_get_rs1 (insn_word);
  rs2  = dlx_get_rs2 (insn_word);
  rd   = dlx_get_rdR (insn_word);
  func = dlx_get_func (insn_word);
  imm16= dlx_get_imm16 (insn_word);
  imm26= dlx_get_imm26 (insn_word);

#if 0
  printf ("print_insn_big_dlx: opc = 0x%02x\n"
    "                    rs1 = 0x%02x\n"
    "                    rs2 = 0x%02x\n"
    "                    rd  = 0x%02x\n"
    "                  func  = 0x%08x\n"
    "                 imm16  = 0x%08x\n"
    "                 imm26  = 0x%08x\n",
    opc, rs1, rs2, rd, func, imm16, imm26);
#endif

  /* Scan through all the insn type and print the insn out.  */
  current_insn_addr = (unsigned long) memaddr;

  for (insn_idx = 0; dlx_insn_type[insn_idx] != 0x0; insn_idx++)
    switch ((dlx_insn_type[insn_idx]) (info))
      {
  /* Found the correct opcode   */
      case R_TYPE:
      case ILD_TYPE:
      case IST_TYPE:
      case IAL_TYPE:
      case IBR_TYPE:
      case IJ_TYPE:
      case IJR_TYPE:
  return 4;

  /* Wrong insn type check next one. */
      default:
      case NIL:
  continue;

  /* All rest of the return code are not recongnized, treat it as error */
  /* we should never get here,  I hope! */
      case R_ERROR:
  return -1;
      }

  if (insn_idx ==  dlx_insn_type_num)
    /* Well, does not recoganize this opcode.  */
    (*info->fprintf_func) (info->stream, "<%s>", "Unrecognized Opcode");

  return 4;
}

Coverage Report

Created: 2023-08-28 06:30

Line	Count	Source (jump to first uncovered line)
1		/* Instruction printing code for the DLX Microprocessor
2		Copyright (C) 2002-2023 Free Software Foundation, Inc.
3		Contributed by Kuang Hwa Lin. Written by Kuang Hwa Lin, 03/2002.
4
5		This file is part of the GNU opcodes library.
6
7		This library is free software; you can redistribute it and/or modify
8		it under the terms of the GNU General Public License as published by
9		the Free Software Foundation; either version 3, or (at your option)
10		any later version.
11
12		It is distributed in the hope that it will be useful, but WITHOUT
13		ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14		or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15		License for more details.
16
17		You should have received a copy of the GNU General Public License
18		along with this program; if not, write to the Free Software
19		Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
20		MA 02110-1301, USA. */
21
22		#include "sysdep.h"
23		#include "disassemble.h"
24		#include "opcode/dlx.h"
25
26	0	#define R_ERROR 0x1
27	0	#define R_TYPE 0x2
28	0	#define ILD_TYPE 0x3
29	0	#define IST_TYPE 0x4
30	0	#define IAL_TYPE 0x5
31	0	#define IBR_TYPE 0x6
32	0	#define IJ_TYPE 0x7
33	0	#define IJR_TYPE 0x8
34	0	#define NIL 0x9
35
36	0	#define OPC(x) ((x >> 26) & 0x3F)
37		#define FUNC(x) (x & 0x7FF)
38
39		unsigned char opc, rs1, rs2, rd;
40		unsigned long imm26, imm16, func, current_insn_addr;
41
42		/* Print one instruction from MEMADDR on INFO->STREAM.
43		Return the size of the instruction (always 4 on dlx). */
44
45		static unsigned char
46		dlx_get_opcode (unsigned long opcode)
47	0	{
48	0	return (unsigned char) ((opcode >> 26) & 0x3F);
49	0	}
50
51		static unsigned char
52		dlx_get_rs1 (unsigned long opcode)
53	0	{
54	0	return (unsigned char) ((opcode >> 21) & 0x1F);
55	0	}
56
57		static unsigned char
58		dlx_get_rs2 (unsigned long opcode)
59	0	{
60	0	return (unsigned char) ((opcode >> 16) & 0x1F);
61	0	}
62
63		static unsigned char
64		dlx_get_rdR (unsigned long opcode)
65	0	{
66	0	return (unsigned char) ((opcode >> 11) & 0x1F);
67	0	}
68
69		static unsigned long
70		dlx_get_func (unsigned long opcode)
71	0	{
72	0	return (unsigned char) (opcode & 0x7FF);
73	0	}
74
75		static unsigned long
76		dlx_get_imm16 (unsigned long opcode)
77	0	{
78	0	return (unsigned long) (opcode & 0xFFFF);
79	0	}
80
81		static unsigned long
82		dlx_get_imm26 (unsigned long opcode)
83	0	{
84	0	return (unsigned long) (opcode & 0x03FFFFFF);
85	0	}
86
87		/* Fill the opcode to the max length. */
88
89		static void
90		operand_deliminator (struct disassemble_info info, char ptr)
91	0	{
92	0	int difft = 8 - (int) strlen (ptr);
93
94	0	while (difft > 0)
95	0	{
96	0	(*info->fprintf_func) (info->stream, "%c", ' ');
97	0	difft -= 1;
98	0	}
99	0	}
100
101		/* Process the R-type opcode. */
102
103		static unsigned char
104		dlx_r_type (struct disassemble_info *info)
105	0	{
106	0	unsigned char r_opc[] = { OPC(ALUOP) }; /* Fix ME */
107	0	int r_opc_num = (sizeof r_opc) / (sizeof (char));
108	0	struct _r_opcode
109	0	{
110	0	unsigned long func;
111	0	char *name;
112	0	}
113	0	dlx_r_opcode[] =
114	0	{
115	0	{ NOPF, "nop" }, /* NOP */
116	0	{ ADDF, "add" }, /* Add */
117	0	{ ADDUF, "addu" }, /* Add Unsigned */
118	0	{ SUBF, "sub" }, /* SUB */
119	0	{ SUBUF, "subu" }, /* Sub Unsigned */
120	0	{ MULTF, "mult" }, /* MULTIPLY */
121	0	{ MULTUF, "multu" }, /* MULTIPLY Unsigned */
122	0	{ DIVF, "div" }, /* DIVIDE */
123	0	{ DIVUF, "divu" }, /* DIVIDE Unsigned */
124	0	{ ANDF, "and" }, /* AND */
125	0	{ ORF, "or" }, /* OR */
126	0	{ XORF, "xor" }, /* Exclusive OR */
127	0	{ SLLF, "sll" }, /* SHIFT LEFT LOGICAL */
128	0	{ SRAF, "sra" }, /* SHIFT RIGHT ARITHMETIC */
129	0	{ SRLF, "srl" }, /* SHIFT RIGHT LOGICAL */
130	0	{ SEQF, "seq" }, /* Set if equal */
131	0	{ SNEF, "sne" }, /* Set if not equal */
132	0	{ SLTF, "slt" }, /* Set if less */
133	0	{ SGTF, "sgt" }, /* Set if greater */
134	0	{ SLEF, "sle" }, /* Set if less or equal */
135	0	{ SGEF, "sge" }, /* Set if greater or equal */
136	0	{ SEQUF, "sequ" }, /* Set if equal */
137	0	{ SNEUF, "sneu" }, /* Set if not equal */
138	0	{ SLTUF, "sltu" }, /* Set if less */
139	0	{ SGTUF, "sgtu" }, /* Set if greater */
140	0	{ SLEUF, "sleu" }, /* Set if less or equal */
141	0	{ SGEUF, "sgeu" }, /* Set if greater or equal */
142	0	{ MVTSF, "mvts" }, /* Move to special register */
143	0	{ MVFSF, "mvfs" }, /* Move from special register */
144	0	{ BSWAPF, "bswap" }, /* Byte swap ?? */
145	0	{ LUTF, "lut" } /* ????????? ?? */
146	0	};
147	0	int dlx_r_opcode_num = (sizeof dlx_r_opcode) / (sizeof dlx_r_opcode[0]);
148	0	int idx;
149
150	0	for (idx = 0; idx < r_opc_num; idx++)
151	0	{
152	0	if (r_opc[idx] != opc)
153	0	continue;
154	0	else
155	0	break;
156	0	}
157
158	0	if (idx == r_opc_num)
159	0	return NIL;
160
161	0	for (idx = 0 ; idx < dlx_r_opcode_num; idx++)
162	0	if (dlx_r_opcode[idx].func == func)
163	0	{
164	0	(*info->fprintf_func) (info->stream, "%s", dlx_r_opcode[idx].name);
165
166	0	if (func != NOPF)
167	0	{
168		/* This is not a nop. */
169	0	operand_deliminator (info, dlx_r_opcode[idx].name);
170	0	(*info->fprintf_func) (info->stream, "r%d,", (int)rd);
171	0	(*info->fprintf_func) (info->stream, "r%d", (int)rs1);
172	0	if (func != MVTSF && func != MVFSF)
173	0	(*info->fprintf_func) (info->stream, ",r%d", (int)rs2);
174	0	}
175	0	return (unsigned char) R_TYPE;
176	0	}
177
178	0	return (unsigned char) R_ERROR;
179	0	}
180
181		/* Process the memory read opcode. */
182
183		static unsigned char
184		dlx_load_type (struct disassemble_info* info)
185	0	{
186	0	struct _load_opcode
187	0	{
188	0	unsigned long opcode;
189	0	char *name;
190	0	}
191	0	dlx_load_opcode[] =
192	0	{
193	0	{ OPC(LHIOP), "lhi" }, /* Load HI to register. */
194	0	{ OPC(LBOP), "lb" }, /* load byte sign extended. */
195	0	{ OPC(LBUOP), "lbu" }, /* load byte unsigned. */
196	0	{ OPC(LSBUOP),"ldstbu"}, /* load store byte unsigned. */
197	0	{ OPC(LHOP), "lh" }, /* load halfword sign extended. */
198	0	{ OPC(LHUOP), "lhu" }, /* load halfword unsigned. */
199	0	{ OPC(LSHUOP),"ldsthu"}, /* load store halfword unsigned. */
200	0	{ OPC(LWOP), "lw" }, /* load word. */
201	0	{ OPC(LSWOP), "ldstw" } /* load store word. */
202	0	};
203	0	int dlx_load_opcode_num =
204	0	(sizeof dlx_load_opcode) / (sizeof dlx_load_opcode[0]);
205	0	int idx;
206
207	0	for (idx = 0 ; idx < dlx_load_opcode_num; idx++)
208	0	if (dlx_load_opcode[idx].opcode == opc)
209	0	{
210	0	if (opc == OPC (LHIOP))
211	0	{
212	0	(*info->fprintf_func) (info->stream, "%s", dlx_load_opcode[idx].name);
213	0	operand_deliminator (info, dlx_load_opcode[idx].name);
214	0	(*info->fprintf_func) (info->stream, "r%d,", (int)rs2);
215	0	(*info->fprintf_func) (info->stream, "0x%04x", (int)imm16);
216	0	}
217	0	else
218	0	{
219	0	(*info->fprintf_func) (info->stream, "%s", dlx_load_opcode[idx].name);
220	0	operand_deliminator (info, dlx_load_opcode[idx].name);
221	0	(*info->fprintf_func) (info->stream, "r%d,", (int)rs2);
222	0	(*info->fprintf_func) (info->stream, "0x%04x[r%d]", (int)imm16, (int)rs1);
223	0	}
224
225	0	return (unsigned char) ILD_TYPE;
226	0	}
227
228	0	return (unsigned char) NIL;
229	0	}
230
231		/* Process the memory store opcode. */
232
233		static unsigned char
234		dlx_store_type (struct disassemble_info* info)
235	0	{
236	0	struct _store_opcode
237	0	{
238	0	unsigned long opcode;
239	0	char *name;
240	0	}
241	0	dlx_store_opcode[] =
242	0	{
243	0	{ OPC(SBOP), "sb" }, /* Store byte. */
244	0	{ OPC(SHOP), "sh" }, /* Store halfword. */
245	0	{ OPC(SWOP), "sw" }, /* Store word. */
246	0	};
247	0	int dlx_store_opcode_num =
248	0	(sizeof dlx_store_opcode) / (sizeof dlx_store_opcode[0]);
249	0	int idx;
250
251	0	for (idx = 0 ; idx < dlx_store_opcode_num; idx++)
252	0	if (dlx_store_opcode[idx].opcode == opc)
253	0	{
254	0	(*info->fprintf_func) (info->stream, "%s", dlx_store_opcode[idx].name);
255	0	operand_deliminator (info, dlx_store_opcode[idx].name);
256	0	(*info->fprintf_func) (info->stream, "0x%04x[r%d],", (int)imm16, (int)rs1);
257	0	(*info->fprintf_func) (info->stream, "r%d", (int)rs2);
258	0	return (unsigned char) IST_TYPE;
259	0	}
260
261	0	return (unsigned char) NIL;
262	0	}
263
264		/* Process the Arithmetic and Logical I-TYPE opcode. */
265
266		static unsigned char
267		dlx_aluI_type (struct disassemble_info* info)
268	0	{
269	0	struct _aluI_opcode
270	0	{
271	0	unsigned long opcode;
272	0	char *name;
273	0	}
274	0	dlx_aluI_opcode[] =
275	0	{
276	0	{ OPC(ADDIOP), "addi" }, /* Store byte. */
277	0	{ OPC(ADDUIOP), "addui" }, /* Store halfword. */
278	0	{ OPC(SUBIOP), "subi" }, /* Store word. */
279	0	{ OPC(SUBUIOP), "subui" }, /* Store word. */
280	0	{ OPC(ANDIOP), "andi" }, /* Store word. */
281	0	{ OPC(ORIOP), "ori" }, /* Store word. */
282	0	{ OPC(XORIOP), "xori" }, /* Store word. */
283	0	{ OPC(SLLIOP), "slli" }, /* Store word. */
284	0	{ OPC(SRAIOP), "srai" }, /* Store word. */
285	0	{ OPC(SRLIOP), "srli" }, /* Store word. */
286	0	{ OPC(SEQIOP), "seqi" }, /* Store word. */
287	0	{ OPC(SNEIOP), "snei" }, /* Store word. */
288	0	{ OPC(SLTIOP), "slti" }, /* Store word. */
289	0	{ OPC(SGTIOP), "sgti" }, /* Store word. */
290	0	{ OPC(SLEIOP), "slei" }, /* Store word. */
291	0	{ OPC(SGEIOP), "sgei" }, /* Store word. */
292	0	{ OPC(SEQUIOP), "sequi" }, /* Store word. */
293	0	{ OPC(SNEUIOP), "sneui" }, /* Store word. */
294	0	{ OPC(SLTUIOP), "sltui" }, /* Store word. */
295	0	{ OPC(SGTUIOP), "sgtui" }, /* Store word. */
296	0	{ OPC(SLEUIOP), "sleui" }, /* Store word. */
297	0	{ OPC(SGEUIOP), "sgeui" }, /* Store word. */
298		#if 0
299		{ OPC(MVTSOP), "mvts" }, /* Store word. */
300		{ OPC(MVFSOP), "mvfs" }, /* Store word. */
301		#endif
302	0	};
303	0	int dlx_aluI_opcode_num =
304	0	(sizeof dlx_aluI_opcode) / (sizeof dlx_aluI_opcode[0]);
305	0	int idx;
306
307	0	for (idx = 0 ; idx < dlx_aluI_opcode_num; idx++)
308	0	if (dlx_aluI_opcode[idx].opcode == opc)
309	0	{
310	0	(*info->fprintf_func) (info->stream, "%s", dlx_aluI_opcode[idx].name);
311	0	operand_deliminator (info, dlx_aluI_opcode[idx].name);
312	0	(*info->fprintf_func) (info->stream, "r%d,", (int)rs2);
313	0	(*info->fprintf_func) (info->stream, "r%d,", (int)rs1);
314	0	(*info->fprintf_func) (info->stream, "0x%04x", (int)imm16);
315
316	0	return (unsigned char) IAL_TYPE;
317	0	}
318
319	0	return (unsigned char) NIL;
320	0	}
321
322		/* Process the branch instruction. */
323
324		static unsigned char
325		dlx_br_type (struct disassemble_info* info)
326	0	{
327	0	struct _br_opcode
328	0	{
329	0	unsigned long opcode;
330	0	char *name;
331	0	}
332	0	dlx_br_opcode[] =
333	0	{
334	0	{ OPC(BEQOP), "beqz" }, /* Store byte. */
335	0	{ OPC(BNEOP), "bnez" } /* Store halfword. */
336	0	};
337	0	int dlx_br_opcode_num =
338	0	(sizeof dlx_br_opcode) / (sizeof dlx_br_opcode[0]);
339	0	int idx;
340
341	0	for (idx = 0 ; idx < dlx_br_opcode_num; idx++)
342	0	if (dlx_br_opcode[idx].opcode == opc)
343	0	{
344	0	if (imm16 & 0x00008000)
345	0	imm16 \|= 0xFFFF0000;
346
347	0	imm16 += (current_insn_addr + 4);
348	0	(*info->fprintf_func) (info->stream, "%s", dlx_br_opcode[idx].name);
349	0	operand_deliminator (info, dlx_br_opcode[idx].name);
350	0	(*info->fprintf_func) (info->stream, "r%d,", (int) rs1);
351	0	(*info->fprintf_func) (info->stream, "0x%08x", (int) imm16);
352
353	0	return (unsigned char) IBR_TYPE;
354	0	}
355
356	0	return (unsigned char) NIL;
357	0	}
358
359		/* Process the jump instruction. */
360
361		static unsigned char
362		dlx_jmp_type (struct disassemble_info* info)
363	0	{
364	0	struct _jmp_opcode
365	0	{
366	0	unsigned long opcode;
367	0	char *name;
368	0	}
369	0	dlx_jmp_opcode[] =
370	0	{
371	0	{ OPC(JOP), "j" }, /* Store byte. */
372	0	{ OPC(JALOP), "jal" }, /* Store halfword. */
373	0	{ OPC(BREAKOP), "break" }, /* Store halfword. */
374	0	{ OPC(TRAPOP), "trap" }, /* Store halfword. */
375	0	{ OPC(RFEOP), "rfe" } /* Store halfword. */
376	0	};
377	0	int dlx_jmp_opcode_num =
378	0	(sizeof dlx_jmp_opcode) / (sizeof dlx_jmp_opcode[0]);
379	0	int idx;
380
381	0	for (idx = 0 ; idx < dlx_jmp_opcode_num; idx++)
382	0	if (dlx_jmp_opcode[idx].opcode == opc)
383	0	{
384	0	if (imm26 & 0x02000000)
385	0	imm26 \|= 0xFC000000;
386
387	0	imm26 += (current_insn_addr + 4);
388
389	0	(*info->fprintf_func) (info->stream, "%s", dlx_jmp_opcode[idx].name);
390	0	operand_deliminator (info, dlx_jmp_opcode[idx].name);
391	0	(*info->fprintf_func) (info->stream, "0x%08x", (int)imm26);
392
393	0	return (unsigned char) IJ_TYPE;
394	0	}
395
396	0	return (unsigned char) NIL;
397	0	}
398
399		/* Process the jump register instruction. */
400
401		static unsigned char
402		dlx_jr_type (struct disassemble_info* info)
403	0	{
404	0	struct _jr_opcode
405	0	{
406	0	unsigned long opcode;
407	0	char *name;
408	0	}
409	0	dlx_jr_opcode[] =
410	0	{
411	0	{ OPC(JROP), "jr" }, /* Store byte. */
412	0	{ OPC(JALROP), "jalr" } /* Store halfword. */
413	0	};
414	0	int dlx_jr_opcode_num =
415	0	(sizeof dlx_jr_opcode) / (sizeof dlx_jr_opcode[0]);
416	0	int idx;
417
418	0	for (idx = 0 ; idx < dlx_jr_opcode_num; idx++)
419	0	if (dlx_jr_opcode[idx].opcode == opc)
420	0	{
421	0	(*info->fprintf_func) (info->stream, "%s", dlx_jr_opcode[idx].name);
422	0	operand_deliminator (info, dlx_jr_opcode[idx].name);
423	0	(*info->fprintf_func) (info->stream, "r%d", (int)rs1);
424	0	return (unsigned char) IJR_TYPE;
425	0	}
426
427	0	return (unsigned char) NIL;
428	0	}
429
430		typedef unsigned char (* dlx_insn) (struct disassemble_info *);
431
432		/* This is the main DLX insn handling routine. */
433
434		int
435		print_insn_dlx (bfd_vma memaddr, struct disassemble_info* info)
436	0	{
437	0	bfd_byte buffer[4];
438	0	int insn_idx;
439	0	unsigned long insn_word;
440	0	dlx_insn dlx_insn_type[] =
441	0	{
442	0	dlx_r_type,
443	0	dlx_load_type,
444	0	dlx_store_type,
445	0	dlx_aluI_type,
446	0	dlx_br_type,
447	0	dlx_jmp_type,
448	0	dlx_jr_type,
449	0	(dlx_insn) NULL
450	0	};
451	0	int dlx_insn_type_num = ((sizeof dlx_insn_type) / (sizeof (dlx_insn))) - 1;
452	0	int status =
453	0	(info->read_memory_func) (memaddr, (bfd_byte ) &buffer[0], 4, info);
454
455	0	if (status != 0)
456	0	{
457	0	(*info->memory_error_func) (status, memaddr, info);
458	0	return -1;
459	0	}
460
461		/* Now decode the insn */
462	0	insn_word = bfd_getb32 (buffer);
463	0	opc = dlx_get_opcode (insn_word);
464	0	rs1 = dlx_get_rs1 (insn_word);
465	0	rs2 = dlx_get_rs2 (insn_word);
466	0	rd = dlx_get_rdR (insn_word);
467	0	func = dlx_get_func (insn_word);
468	0	imm16= dlx_get_imm16 (insn_word);
469	0	imm26= dlx_get_imm26 (insn_word);
470
471		#if 0
472		printf ("print_insn_big_dlx: opc = 0x%02x\n"
473		" rs1 = 0x%02x\n"
474		" rs2 = 0x%02x\n"
475		" rd = 0x%02x\n"
476		" func = 0x%08x\n"
477		" imm16 = 0x%08x\n"
478		" imm26 = 0x%08x\n",
479		opc, rs1, rs2, rd, func, imm16, imm26);
480		#endif
481
482		/* Scan through all the insn type and print the insn out. */
483	0	current_insn_addr = (unsigned long) memaddr;
484
485	0	for (insn_idx = 0; dlx_insn_type[insn_idx] != 0x0; insn_idx++)
486	0	switch ((dlx_insn_type[insn_idx]) (info))
487	0	{
488		/* Found the correct opcode */
489	0	case R_TYPE:
490	0	case ILD_TYPE:
491	0	case IST_TYPE:
492	0	case IAL_TYPE:
493	0	case IBR_TYPE:
494	0	case IJ_TYPE:
495	0	case IJR_TYPE:
496	0	return 4;
497
498		/* Wrong insn type check next one. */
499	0	default:
500	0	case NIL:
501	0	continue;
502
503		/* All rest of the return code are not recongnized, treat it as error */
504		/* we should never get here, I hope! */
505	0	case R_ERROR:
506	0	return -1;
507	0	}
508
509	0	if (insn_idx == dlx_insn_type_num)
510		/* Well, does not recoganize this opcode. */
511	0	(*info->fprintf_func) (info->stream, "<%s>", "Unrecognized Opcode");
512
513	0	return 4;
514	0	}