/src/binutils-gdb/opcodes/m32c-dis.c
Line | Count | Source (jump to first uncovered line) |
1 | | /* DO NOT EDIT! -*- buffer-read-only: t -*- vi:set ro: */ |
2 | | /* Disassembler interface for targets using CGEN. -*- C -*- |
3 | | CGEN: Cpu tools GENerator |
4 | | |
5 | | THIS FILE IS MACHINE GENERATED WITH CGEN. |
6 | | - the resultant file is machine generated, cgen-dis.in isn't |
7 | | |
8 | | Copyright (C) 1996-2023 Free Software Foundation, Inc. |
9 | | |
10 | | This file is part of libopcodes. |
11 | | |
12 | | This library is free software; you can redistribute it and/or modify |
13 | | it under the terms of the GNU General Public License as published by |
14 | | the Free Software Foundation; either version 3, or (at your option) |
15 | | any later version. |
16 | | |
17 | | It is distributed in the hope that it will be useful, but WITHOUT |
18 | | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY |
19 | | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public |
20 | | License for more details. |
21 | | |
22 | | You should have received a copy of the GNU General Public License |
23 | | along with this program; if not, write to the Free Software Foundation, Inc., |
24 | | 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ |
25 | | |
26 | | /* ??? Eventually more and more of this stuff can go to cpu-independent files. |
27 | | Keep that in mind. */ |
28 | | |
29 | | #include "sysdep.h" |
30 | | #include <stdio.h> |
31 | | #include "ansidecl.h" |
32 | | #include "disassemble.h" |
33 | | #include "bfd.h" |
34 | | #include "symcat.h" |
35 | | #include "libiberty.h" |
36 | | #include "m32c-desc.h" |
37 | | #include "m32c-opc.h" |
38 | | #include "opintl.h" |
39 | | |
40 | | /* Default text to print if an instruction isn't recognized. */ |
41 | 0 | #define UNKNOWN_INSN_MSG _("*unknown*") |
42 | | |
43 | | static void print_normal |
44 | | (CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int); |
45 | | static void print_address |
46 | | (CGEN_CPU_DESC, void *, bfd_vma, unsigned int, bfd_vma, int) ATTRIBUTE_UNUSED; |
47 | | static void print_keyword |
48 | | (CGEN_CPU_DESC, void *, CGEN_KEYWORD *, long, unsigned int) ATTRIBUTE_UNUSED; |
49 | | static void print_insn_normal |
50 | | (CGEN_CPU_DESC, void *, const CGEN_INSN *, CGEN_FIELDS *, bfd_vma, int); |
51 | | static int print_insn |
52 | | (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, unsigned); |
53 | | static int default_print_insn |
54 | | (CGEN_CPU_DESC, bfd_vma, disassemble_info *) ATTRIBUTE_UNUSED; |
55 | | static int read_insn |
56 | | (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, int, CGEN_EXTRACT_INFO *, |
57 | | unsigned long *); |
58 | | |
59 | | /* -- disassembler routines inserted here. */ |
60 | | |
61 | | /* -- dis.c */ |
62 | | |
63 | | #include "elf/m32c.h" |
64 | | #include "elf-bfd.h" |
65 | | |
66 | | /* Always print the short insn format suffix as ':<char>'. */ |
67 | | |
68 | | static void |
69 | | print_suffix (void * dis_info, char suffix) |
70 | 0 | { |
71 | 0 | disassemble_info *info = dis_info; |
72 | |
|
73 | 0 | (*info->fprintf_func) (info->stream, ":%c", suffix); |
74 | 0 | } |
75 | | |
76 | | static void |
77 | | print_S (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, |
78 | | void * dis_info, |
79 | | long value ATTRIBUTE_UNUSED, |
80 | | unsigned int attrs ATTRIBUTE_UNUSED, |
81 | | bfd_vma pc ATTRIBUTE_UNUSED, |
82 | | int length ATTRIBUTE_UNUSED) |
83 | 0 | { |
84 | 0 | print_suffix (dis_info, 's'); |
85 | 0 | } |
86 | | |
87 | | |
88 | | static void |
89 | | print_G (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, |
90 | | void * dis_info, |
91 | | long value ATTRIBUTE_UNUSED, |
92 | | unsigned int attrs ATTRIBUTE_UNUSED, |
93 | | bfd_vma pc ATTRIBUTE_UNUSED, |
94 | | int length ATTRIBUTE_UNUSED) |
95 | 0 | { |
96 | 0 | print_suffix (dis_info, 'g'); |
97 | 0 | } |
98 | | |
99 | | static void |
100 | | print_Q (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, |
101 | | void * dis_info, |
102 | | long value ATTRIBUTE_UNUSED, |
103 | | unsigned int attrs ATTRIBUTE_UNUSED, |
104 | | bfd_vma pc ATTRIBUTE_UNUSED, |
105 | | int length ATTRIBUTE_UNUSED) |
106 | 0 | { |
107 | 0 | print_suffix (dis_info, 'q'); |
108 | 0 | } |
109 | | |
110 | | static void |
111 | | print_Z (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, |
112 | | void * dis_info, |
113 | | long value ATTRIBUTE_UNUSED, |
114 | | unsigned int attrs ATTRIBUTE_UNUSED, |
115 | | bfd_vma pc ATTRIBUTE_UNUSED, |
116 | | int length ATTRIBUTE_UNUSED) |
117 | 0 | { |
118 | 0 | print_suffix (dis_info, 'z'); |
119 | 0 | } |
120 | | |
121 | | /* Print the empty suffix. */ |
122 | | |
123 | | static void |
124 | | print_X (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, |
125 | | void * dis_info ATTRIBUTE_UNUSED, |
126 | | long value ATTRIBUTE_UNUSED, |
127 | | unsigned int attrs ATTRIBUTE_UNUSED, |
128 | | bfd_vma pc ATTRIBUTE_UNUSED, |
129 | | int length ATTRIBUTE_UNUSED) |
130 | 0 | { |
131 | 0 | return; |
132 | 0 | } |
133 | | |
134 | | static void |
135 | | print_r0l_r0h (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, |
136 | | void * dis_info, |
137 | | long value, |
138 | | unsigned int attrs ATTRIBUTE_UNUSED, |
139 | | bfd_vma pc ATTRIBUTE_UNUSED, |
140 | | int length ATTRIBUTE_UNUSED) |
141 | 0 | { |
142 | 0 | disassemble_info *info = dis_info; |
143 | |
|
144 | 0 | if (value == 0) |
145 | 0 | (*info->fprintf_func) (info->stream, "r0h,r0l"); |
146 | 0 | else |
147 | 0 | (*info->fprintf_func) (info->stream, "r0l,r0h"); |
148 | 0 | } |
149 | | |
150 | | static void |
151 | | print_unsigned_bitbase (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, |
152 | | void * dis_info, |
153 | | unsigned long value, |
154 | | unsigned int attrs ATTRIBUTE_UNUSED, |
155 | | bfd_vma pc ATTRIBUTE_UNUSED, |
156 | | int length ATTRIBUTE_UNUSED) |
157 | 0 | { |
158 | 0 | disassemble_info *info = dis_info; |
159 | |
|
160 | 0 | (*info->fprintf_func) (info->stream, "%ld,0x%lx", value & 0x7, value >> 3); |
161 | 0 | } |
162 | | |
163 | | static void |
164 | | print_signed_bitbase (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, |
165 | | void * dis_info, |
166 | | signed long value, |
167 | | unsigned int attrs ATTRIBUTE_UNUSED, |
168 | | bfd_vma pc ATTRIBUTE_UNUSED, |
169 | | int length ATTRIBUTE_UNUSED) |
170 | 0 | { |
171 | 0 | disassemble_info *info = dis_info; |
172 | |
|
173 | 0 | (*info->fprintf_func) (info->stream, "%ld,%ld", value & 0x7, value >> 3); |
174 | 0 | } |
175 | | |
176 | | static void |
177 | | print_size (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, |
178 | | void * dis_info, |
179 | | long value ATTRIBUTE_UNUSED, |
180 | | unsigned int attrs ATTRIBUTE_UNUSED, |
181 | | bfd_vma pc ATTRIBUTE_UNUSED, |
182 | | int length ATTRIBUTE_UNUSED) |
183 | 0 | { |
184 | | /* Always print the size as '.w'. */ |
185 | 0 | disassemble_info *info = dis_info; |
186 | |
|
187 | 0 | (*info->fprintf_func) (info->stream, ".w"); |
188 | 0 | } |
189 | | |
190 | 0 | #define POP 0 |
191 | 0 | #define PUSH 1 |
192 | | |
193 | | static void print_pop_regset (CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int); |
194 | | static void print_push_regset (CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int); |
195 | | |
196 | | /* Print a set of registers, R0,R1,A0,A1,SB,FB. */ |
197 | | |
198 | | static void |
199 | | print_regset (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, |
200 | | void * dis_info, |
201 | | long value, |
202 | | unsigned int attrs ATTRIBUTE_UNUSED, |
203 | | bfd_vma pc ATTRIBUTE_UNUSED, |
204 | | int length ATTRIBUTE_UNUSED, |
205 | | int push) |
206 | 0 | { |
207 | 0 | static char * m16c_register_names [] = |
208 | 0 | { |
209 | 0 | "r0", "r1", "r2", "r3", "a0", "a1", "sb", "fb" |
210 | 0 | }; |
211 | 0 | disassemble_info *info = dis_info; |
212 | 0 | int mask; |
213 | 0 | int reg_index = 0; |
214 | 0 | char* comma = ""; |
215 | |
|
216 | 0 | if (push) |
217 | 0 | mask = 0x80; |
218 | 0 | else |
219 | 0 | mask = 1; |
220 | |
|
221 | 0 | if (value & mask) |
222 | 0 | { |
223 | 0 | (*info->fprintf_func) (info->stream, "%s", m16c_register_names [0]); |
224 | 0 | comma = ","; |
225 | 0 | } |
226 | |
|
227 | 0 | for (reg_index = 1; reg_index <= 7; ++reg_index) |
228 | 0 | { |
229 | 0 | if (push) |
230 | 0 | mask >>= 1; |
231 | 0 | else |
232 | 0 | mask <<= 1; |
233 | |
|
234 | 0 | if (value & mask) |
235 | 0 | { |
236 | 0 | (*info->fprintf_func) (info->stream, "%s%s", comma, |
237 | 0 | m16c_register_names [reg_index]); |
238 | 0 | comma = ","; |
239 | 0 | } |
240 | 0 | } |
241 | 0 | } |
242 | | |
243 | | static void |
244 | | print_pop_regset (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, |
245 | | void * dis_info, |
246 | | long value, |
247 | | unsigned int attrs ATTRIBUTE_UNUSED, |
248 | | bfd_vma pc ATTRIBUTE_UNUSED, |
249 | | int length ATTRIBUTE_UNUSED) |
250 | 0 | { |
251 | 0 | print_regset (cd, dis_info, value, attrs, pc, length, POP); |
252 | 0 | } |
253 | | |
254 | | static void |
255 | | print_push_regset (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, |
256 | | void * dis_info, |
257 | | long value, |
258 | | unsigned int attrs ATTRIBUTE_UNUSED, |
259 | | bfd_vma pc ATTRIBUTE_UNUSED, |
260 | | int length ATTRIBUTE_UNUSED) |
261 | 0 | { |
262 | 0 | print_regset (cd, dis_info, value, attrs, pc, length, PUSH); |
263 | 0 | } |
264 | | |
265 | | static void |
266 | | print_signed4n (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, |
267 | | void * dis_info, |
268 | | signed long value, |
269 | | unsigned int attrs ATTRIBUTE_UNUSED, |
270 | | bfd_vma pc ATTRIBUTE_UNUSED, |
271 | | int length ATTRIBUTE_UNUSED) |
272 | 0 | { |
273 | 0 | disassemble_info *info = dis_info; |
274 | |
|
275 | 0 | (*info->fprintf_func) (info->stream, "%ld", -value); |
276 | 0 | } |
277 | | |
278 | | void m32c_cgen_print_operand |
279 | | (CGEN_CPU_DESC, int, void *, CGEN_FIELDS *, void const *, bfd_vma, int); |
280 | | |
281 | | /* Main entry point for printing operands. |
282 | | XINFO is a `void *' and not a `disassemble_info *' to not put a requirement |
283 | | of dis-asm.h on cgen.h. |
284 | | |
285 | | This function is basically just a big switch statement. Earlier versions |
286 | | used tables to look up the function to use, but |
287 | | - if the table contains both assembler and disassembler functions then |
288 | | the disassembler contains much of the assembler and vice-versa, |
289 | | - there's a lot of inlining possibilities as things grow, |
290 | | - using a switch statement avoids the function call overhead. |
291 | | |
292 | | This function could be moved into `print_insn_normal', but keeping it |
293 | | separate makes clear the interface between `print_insn_normal' and each of |
294 | | the handlers. */ |
295 | | |
296 | | void |
297 | | m32c_cgen_print_operand (CGEN_CPU_DESC cd, |
298 | | int opindex, |
299 | | void * xinfo, |
300 | | CGEN_FIELDS *fields, |
301 | | void const *attrs ATTRIBUTE_UNUSED, |
302 | | bfd_vma pc, |
303 | | int length) |
304 | 0 | { |
305 | 0 | disassemble_info *info = (disassemble_info *) xinfo; |
306 | |
|
307 | 0 | switch (opindex) |
308 | 0 | { |
309 | 0 | case M32C_OPERAND_A0 : |
310 | 0 | print_keyword (cd, info, & m32c_cgen_opval_h_a0, 0, 0); |
311 | 0 | break; |
312 | 0 | case M32C_OPERAND_A1 : |
313 | 0 | print_keyword (cd, info, & m32c_cgen_opval_h_a1, 0, 0); |
314 | 0 | break; |
315 | 0 | case M32C_OPERAND_AN16_PUSH_S : |
316 | 0 | print_keyword (cd, info, & m32c_cgen_opval_h_ar_HI, fields->f_4_1, 0); |
317 | 0 | break; |
318 | 0 | case M32C_OPERAND_BIT16AN : |
319 | 0 | print_keyword (cd, info, & m32c_cgen_opval_h_ar, fields->f_dst16_an, 0); |
320 | 0 | break; |
321 | 0 | case M32C_OPERAND_BIT16RN : |
322 | 0 | print_keyword (cd, info, & m32c_cgen_opval_h_gr_HI, fields->f_dst16_rn, 0); |
323 | 0 | break; |
324 | 0 | case M32C_OPERAND_BIT3_S : |
325 | 0 | print_normal (cd, info, fields->f_imm3_S, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_VIRTUAL), pc, length); |
326 | 0 | break; |
327 | 0 | case M32C_OPERAND_BIT32ANPREFIXED : |
328 | 0 | print_keyword (cd, info, & m32c_cgen_opval_h_ar, fields->f_dst32_an_prefixed, 0); |
329 | 0 | break; |
330 | 0 | case M32C_OPERAND_BIT32ANUNPREFIXED : |
331 | 0 | print_keyword (cd, info, & m32c_cgen_opval_h_ar, fields->f_dst32_an_unprefixed, 0); |
332 | 0 | break; |
333 | 0 | case M32C_OPERAND_BIT32RNPREFIXED : |
334 | 0 | print_keyword (cd, info, & m32c_cgen_opval_h_gr_QI, fields->f_dst32_rn_prefixed_QI, 0); |
335 | 0 | break; |
336 | 0 | case M32C_OPERAND_BIT32RNUNPREFIXED : |
337 | 0 | print_keyword (cd, info, & m32c_cgen_opval_h_gr_QI, fields->f_dst32_rn_unprefixed_QI, 0); |
338 | 0 | break; |
339 | 0 | case M32C_OPERAND_BITBASE16_16_S8 : |
340 | 0 | print_signed_bitbase (cd, info, fields->f_dsp_16_s8, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); |
341 | 0 | break; |
342 | 0 | case M32C_OPERAND_BITBASE16_16_U16 : |
343 | 0 | print_unsigned_bitbase (cd, info, fields->f_dsp_16_u16, 0, pc, length); |
344 | 0 | break; |
345 | 0 | case M32C_OPERAND_BITBASE16_16_U8 : |
346 | 0 | print_unsigned_bitbase (cd, info, fields->f_dsp_16_u8, 0, pc, length); |
347 | 0 | break; |
348 | 0 | case M32C_OPERAND_BITBASE16_8_U11_S : |
349 | 0 | print_unsigned_bitbase (cd, info, fields->f_bitbase16_u11_S, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length); |
350 | 0 | break; |
351 | 0 | case M32C_OPERAND_BITBASE32_16_S11_UNPREFIXED : |
352 | 0 | print_signed_bitbase (cd, info, fields->f_bitbase32_16_s11_unprefixed, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_VIRTUAL), pc, length); |
353 | 0 | break; |
354 | 0 | case M32C_OPERAND_BITBASE32_16_S19_UNPREFIXED : |
355 | 0 | print_signed_bitbase (cd, info, fields->f_bitbase32_16_s19_unprefixed, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_VIRTUAL), pc, length); |
356 | 0 | break; |
357 | 0 | case M32C_OPERAND_BITBASE32_16_U11_UNPREFIXED : |
358 | 0 | print_unsigned_bitbase (cd, info, fields->f_bitbase32_16_u11_unprefixed, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length); |
359 | 0 | break; |
360 | 0 | case M32C_OPERAND_BITBASE32_16_U19_UNPREFIXED : |
361 | 0 | print_unsigned_bitbase (cd, info, fields->f_bitbase32_16_u19_unprefixed, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length); |
362 | 0 | break; |
363 | 0 | case M32C_OPERAND_BITBASE32_16_U27_UNPREFIXED : |
364 | 0 | print_unsigned_bitbase (cd, info, fields->f_bitbase32_16_u27_unprefixed, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length); |
365 | 0 | break; |
366 | 0 | case M32C_OPERAND_BITBASE32_24_S11_PREFIXED : |
367 | 0 | print_signed_bitbase (cd, info, fields->f_bitbase32_24_s11_prefixed, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_VIRTUAL), pc, length); |
368 | 0 | break; |
369 | 0 | case M32C_OPERAND_BITBASE32_24_S19_PREFIXED : |
370 | 0 | print_signed_bitbase (cd, info, fields->f_bitbase32_24_s19_prefixed, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_VIRTUAL), pc, length); |
371 | 0 | break; |
372 | 0 | case M32C_OPERAND_BITBASE32_24_U11_PREFIXED : |
373 | 0 | print_unsigned_bitbase (cd, info, fields->f_bitbase32_24_u11_prefixed, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length); |
374 | 0 | break; |
375 | 0 | case M32C_OPERAND_BITBASE32_24_U19_PREFIXED : |
376 | 0 | print_unsigned_bitbase (cd, info, fields->f_bitbase32_24_u19_prefixed, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length); |
377 | 0 | break; |
378 | 0 | case M32C_OPERAND_BITBASE32_24_U27_PREFIXED : |
379 | 0 | print_unsigned_bitbase (cd, info, fields->f_bitbase32_24_u27_prefixed, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length); |
380 | 0 | break; |
381 | 0 | case M32C_OPERAND_BITNO16R : |
382 | 0 | print_normal (cd, info, fields->f_dsp_16_u8, 0, pc, length); |
383 | 0 | break; |
384 | 0 | case M32C_OPERAND_BITNO32PREFIXED : |
385 | 0 | print_normal (cd, info, fields->f_bitno32_prefixed, 0, pc, length); |
386 | 0 | break; |
387 | 0 | case M32C_OPERAND_BITNO32UNPREFIXED : |
388 | 0 | print_normal (cd, info, fields->f_bitno32_unprefixed, 0, pc, length); |
389 | 0 | break; |
390 | 0 | case M32C_OPERAND_DSP_10_U6 : |
391 | 0 | print_normal (cd, info, fields->f_dsp_10_u6, 0, pc, length); |
392 | 0 | break; |
393 | 0 | case M32C_OPERAND_DSP_16_S16 : |
394 | 0 | print_normal (cd, info, fields->f_dsp_16_s16, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); |
395 | 0 | break; |
396 | 0 | case M32C_OPERAND_DSP_16_S8 : |
397 | 0 | print_normal (cd, info, fields->f_dsp_16_s8, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); |
398 | 0 | break; |
399 | 0 | case M32C_OPERAND_DSP_16_U16 : |
400 | 0 | print_normal (cd, info, fields->f_dsp_16_u16, 0, pc, length); |
401 | 0 | break; |
402 | 0 | case M32C_OPERAND_DSP_16_U20 : |
403 | 0 | print_normal (cd, info, fields->f_dsp_16_u24, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length); |
404 | 0 | break; |
405 | 0 | case M32C_OPERAND_DSP_16_U24 : |
406 | 0 | print_normal (cd, info, fields->f_dsp_16_u24, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length); |
407 | 0 | break; |
408 | 0 | case M32C_OPERAND_DSP_16_U8 : |
409 | 0 | print_normal (cd, info, fields->f_dsp_16_u8, 0, pc, length); |
410 | 0 | break; |
411 | 0 | case M32C_OPERAND_DSP_24_S16 : |
412 | 0 | print_normal (cd, info, fields->f_dsp_24_s16, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_VIRTUAL), pc, length); |
413 | 0 | break; |
414 | 0 | case M32C_OPERAND_DSP_24_S8 : |
415 | 0 | print_normal (cd, info, fields->f_dsp_24_s8, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); |
416 | 0 | break; |
417 | 0 | case M32C_OPERAND_DSP_24_U16 : |
418 | 0 | print_normal (cd, info, fields->f_dsp_24_u16, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length); |
419 | 0 | break; |
420 | 0 | case M32C_OPERAND_DSP_24_U20 : |
421 | 0 | print_normal (cd, info, fields->f_dsp_24_u24, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length); |
422 | 0 | break; |
423 | 0 | case M32C_OPERAND_DSP_24_U24 : |
424 | 0 | print_normal (cd, info, fields->f_dsp_24_u24, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length); |
425 | 0 | break; |
426 | 0 | case M32C_OPERAND_DSP_24_U8 : |
427 | 0 | print_normal (cd, info, fields->f_dsp_24_u8, 0, pc, length); |
428 | 0 | break; |
429 | 0 | case M32C_OPERAND_DSP_32_S16 : |
430 | 0 | print_normal (cd, info, fields->f_dsp_32_s16, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); |
431 | 0 | break; |
432 | 0 | case M32C_OPERAND_DSP_32_S8 : |
433 | 0 | print_normal (cd, info, fields->f_dsp_32_s8, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); |
434 | 0 | break; |
435 | 0 | case M32C_OPERAND_DSP_32_U16 : |
436 | 0 | print_normal (cd, info, fields->f_dsp_32_u16, 0, pc, length); |
437 | 0 | break; |
438 | 0 | case M32C_OPERAND_DSP_32_U20 : |
439 | 0 | print_normal (cd, info, fields->f_dsp_32_u24, 0, pc, length); |
440 | 0 | break; |
441 | 0 | case M32C_OPERAND_DSP_32_U24 : |
442 | 0 | print_normal (cd, info, fields->f_dsp_32_u24, 0, pc, length); |
443 | 0 | break; |
444 | 0 | case M32C_OPERAND_DSP_32_U8 : |
445 | 0 | print_normal (cd, info, fields->f_dsp_32_u8, 0, pc, length); |
446 | 0 | break; |
447 | 0 | case M32C_OPERAND_DSP_40_S16 : |
448 | 0 | print_normal (cd, info, fields->f_dsp_40_s16, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); |
449 | 0 | break; |
450 | 0 | case M32C_OPERAND_DSP_40_S8 : |
451 | 0 | print_normal (cd, info, fields->f_dsp_40_s8, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); |
452 | 0 | break; |
453 | 0 | case M32C_OPERAND_DSP_40_U16 : |
454 | 0 | print_normal (cd, info, fields->f_dsp_40_u16, 0, pc, length); |
455 | 0 | break; |
456 | 0 | case M32C_OPERAND_DSP_40_U20 : |
457 | 0 | print_normal (cd, info, fields->f_dsp_40_u20, 0, pc, length); |
458 | 0 | break; |
459 | 0 | case M32C_OPERAND_DSP_40_U24 : |
460 | 0 | print_normal (cd, info, fields->f_dsp_40_u24, 0, pc, length); |
461 | 0 | break; |
462 | 0 | case M32C_OPERAND_DSP_40_U8 : |
463 | 0 | print_normal (cd, info, fields->f_dsp_40_u8, 0, pc, length); |
464 | 0 | break; |
465 | 0 | case M32C_OPERAND_DSP_48_S16 : |
466 | 0 | print_normal (cd, info, fields->f_dsp_48_s16, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); |
467 | 0 | break; |
468 | 0 | case M32C_OPERAND_DSP_48_S8 : |
469 | 0 | print_normal (cd, info, fields->f_dsp_48_s8, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); |
470 | 0 | break; |
471 | 0 | case M32C_OPERAND_DSP_48_U16 : |
472 | 0 | print_normal (cd, info, fields->f_dsp_48_u16, 0, pc, length); |
473 | 0 | break; |
474 | 0 | case M32C_OPERAND_DSP_48_U20 : |
475 | 0 | print_normal (cd, info, fields->f_dsp_48_u20, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length); |
476 | 0 | break; |
477 | 0 | case M32C_OPERAND_DSP_48_U24 : |
478 | 0 | print_normal (cd, info, fields->f_dsp_48_u24, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length); |
479 | 0 | break; |
480 | 0 | case M32C_OPERAND_DSP_48_U8 : |
481 | 0 | print_normal (cd, info, fields->f_dsp_48_u8, 0, pc, length); |
482 | 0 | break; |
483 | 0 | case M32C_OPERAND_DSP_8_S24 : |
484 | 0 | print_normal (cd, info, fields->f_dsp_8_s24, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); |
485 | 0 | break; |
486 | 0 | case M32C_OPERAND_DSP_8_S8 : |
487 | 0 | print_normal (cd, info, fields->f_dsp_8_s8, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); |
488 | 0 | break; |
489 | 0 | case M32C_OPERAND_DSP_8_U16 : |
490 | 0 | print_normal (cd, info, fields->f_dsp_8_u16, 0, pc, length); |
491 | 0 | break; |
492 | 0 | case M32C_OPERAND_DSP_8_U24 : |
493 | 0 | print_normal (cd, info, fields->f_dsp_8_u24, 0, pc, length); |
494 | 0 | break; |
495 | 0 | case M32C_OPERAND_DSP_8_U6 : |
496 | 0 | print_normal (cd, info, fields->f_dsp_8_u6, 0, pc, length); |
497 | 0 | break; |
498 | 0 | case M32C_OPERAND_DSP_8_U8 : |
499 | 0 | print_normal (cd, info, fields->f_dsp_8_u8, 0, pc, length); |
500 | 0 | break; |
501 | 0 | case M32C_OPERAND_DST16AN : |
502 | 0 | print_keyword (cd, info, & m32c_cgen_opval_h_ar, fields->f_dst16_an, 0); |
503 | 0 | break; |
504 | 0 | case M32C_OPERAND_DST16AN_S : |
505 | 0 | print_keyword (cd, info, & m32c_cgen_opval_h_ar_HI, fields->f_dst16_an_s, 0); |
506 | 0 | break; |
507 | 0 | case M32C_OPERAND_DST16ANHI : |
508 | 0 | print_keyword (cd, info, & m32c_cgen_opval_h_ar_HI, fields->f_dst16_an, 0); |
509 | 0 | break; |
510 | 0 | case M32C_OPERAND_DST16ANQI : |
511 | 0 | print_keyword (cd, info, & m32c_cgen_opval_h_ar_QI, fields->f_dst16_an, 0); |
512 | 0 | break; |
513 | 0 | case M32C_OPERAND_DST16ANQI_S : |
514 | 0 | print_keyword (cd, info, & m32c_cgen_opval_h_ar_QI, fields->f_dst16_rn_QI_s, 0); |
515 | 0 | break; |
516 | 0 | case M32C_OPERAND_DST16ANSI : |
517 | 0 | print_keyword (cd, info, & m32c_cgen_opval_h_ar_SI, fields->f_dst16_an, 0); |
518 | 0 | break; |
519 | 0 | case M32C_OPERAND_DST16RNEXTQI : |
520 | 0 | print_keyword (cd, info, & m32c_cgen_opval_h_gr_ext_QI, fields->f_dst16_rn_ext, 0); |
521 | 0 | break; |
522 | 0 | case M32C_OPERAND_DST16RNHI : |
523 | 0 | print_keyword (cd, info, & m32c_cgen_opval_h_gr_HI, fields->f_dst16_rn, 0); |
524 | 0 | break; |
525 | 0 | case M32C_OPERAND_DST16RNQI : |
526 | 0 | print_keyword (cd, info, & m32c_cgen_opval_h_gr_QI, fields->f_dst16_rn, 0); |
527 | 0 | break; |
528 | 0 | case M32C_OPERAND_DST16RNQI_S : |
529 | 0 | print_keyword (cd, info, & m32c_cgen_opval_h_r0l_r0h, fields->f_dst16_rn_QI_s, 0); |
530 | 0 | break; |
531 | 0 | case M32C_OPERAND_DST16RNSI : |
532 | 0 | print_keyword (cd, info, & m32c_cgen_opval_h_gr_SI, fields->f_dst16_rn, 0); |
533 | 0 | break; |
534 | 0 | case M32C_OPERAND_DST32ANEXTUNPREFIXED : |
535 | 0 | print_keyword (cd, info, & m32c_cgen_opval_h_ar, fields->f_dst32_an_unprefixed, 0); |
536 | 0 | break; |
537 | 0 | case M32C_OPERAND_DST32ANPREFIXED : |
538 | 0 | print_keyword (cd, info, & m32c_cgen_opval_h_ar, fields->f_dst32_an_prefixed, 0); |
539 | 0 | break; |
540 | 0 | case M32C_OPERAND_DST32ANPREFIXEDHI : |
541 | 0 | print_keyword (cd, info, & m32c_cgen_opval_h_ar_HI, fields->f_dst32_an_prefixed, 0); |
542 | 0 | break; |
543 | 0 | case M32C_OPERAND_DST32ANPREFIXEDQI : |
544 | 0 | print_keyword (cd, info, & m32c_cgen_opval_h_ar_QI, fields->f_dst32_an_prefixed, 0); |
545 | 0 | break; |
546 | 0 | case M32C_OPERAND_DST32ANPREFIXEDSI : |
547 | 0 | print_keyword (cd, info, & m32c_cgen_opval_h_ar, fields->f_dst32_an_prefixed, 0); |
548 | 0 | break; |
549 | 0 | case M32C_OPERAND_DST32ANUNPREFIXED : |
550 | 0 | print_keyword (cd, info, & m32c_cgen_opval_h_ar, fields->f_dst32_an_unprefixed, 0); |
551 | 0 | break; |
552 | 0 | case M32C_OPERAND_DST32ANUNPREFIXEDHI : |
553 | 0 | print_keyword (cd, info, & m32c_cgen_opval_h_ar_HI, fields->f_dst32_an_unprefixed, 0); |
554 | 0 | break; |
555 | 0 | case M32C_OPERAND_DST32ANUNPREFIXEDQI : |
556 | 0 | print_keyword (cd, info, & m32c_cgen_opval_h_ar_QI, fields->f_dst32_an_unprefixed, 0); |
557 | 0 | break; |
558 | 0 | case M32C_OPERAND_DST32ANUNPREFIXEDSI : |
559 | 0 | print_keyword (cd, info, & m32c_cgen_opval_h_ar, fields->f_dst32_an_unprefixed, 0); |
560 | 0 | break; |
561 | 0 | case M32C_OPERAND_DST32R0HI_S : |
562 | 0 | print_keyword (cd, info, & m32c_cgen_opval_h_r0, 0, 0); |
563 | 0 | break; |
564 | 0 | case M32C_OPERAND_DST32R0QI_S : |
565 | 0 | print_keyword (cd, info, & m32c_cgen_opval_h_r0l, 0, 0); |
566 | 0 | break; |
567 | 0 | case M32C_OPERAND_DST32RNEXTUNPREFIXEDHI : |
568 | 0 | print_keyword (cd, info, & m32c_cgen_opval_h_gr_ext_HI, fields->f_dst32_rn_ext_unprefixed, 0); |
569 | 0 | break; |
570 | 0 | case M32C_OPERAND_DST32RNEXTUNPREFIXEDQI : |
571 | 0 | print_keyword (cd, info, & m32c_cgen_opval_h_gr_ext_QI, fields->f_dst32_rn_ext_unprefixed, 0); |
572 | 0 | break; |
573 | 0 | case M32C_OPERAND_DST32RNPREFIXEDHI : |
574 | 0 | print_keyword (cd, info, & m32c_cgen_opval_h_gr_HI, fields->f_dst32_rn_prefixed_HI, 0); |
575 | 0 | break; |
576 | 0 | case M32C_OPERAND_DST32RNPREFIXEDQI : |
577 | 0 | print_keyword (cd, info, & m32c_cgen_opval_h_gr_QI, fields->f_dst32_rn_prefixed_QI, 0); |
578 | 0 | break; |
579 | 0 | case M32C_OPERAND_DST32RNPREFIXEDSI : |
580 | 0 | print_keyword (cd, info, & m32c_cgen_opval_h_gr_SI, fields->f_dst32_rn_prefixed_SI, 0); |
581 | 0 | break; |
582 | 0 | case M32C_OPERAND_DST32RNUNPREFIXEDHI : |
583 | 0 | print_keyword (cd, info, & m32c_cgen_opval_h_gr_HI, fields->f_dst32_rn_unprefixed_HI, 0); |
584 | 0 | break; |
585 | 0 | case M32C_OPERAND_DST32RNUNPREFIXEDQI : |
586 | 0 | print_keyword (cd, info, & m32c_cgen_opval_h_gr_QI, fields->f_dst32_rn_unprefixed_QI, 0); |
587 | 0 | break; |
588 | 0 | case M32C_OPERAND_DST32RNUNPREFIXEDSI : |
589 | 0 | print_keyword (cd, info, & m32c_cgen_opval_h_gr_SI, fields->f_dst32_rn_unprefixed_SI, 0); |
590 | 0 | break; |
591 | 0 | case M32C_OPERAND_G : |
592 | 0 | print_G (cd, info, 0, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); |
593 | 0 | break; |
594 | 0 | case M32C_OPERAND_IMM_12_S4 : |
595 | 0 | print_normal (cd, info, fields->f_imm_12_s4, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); |
596 | 0 | break; |
597 | 0 | case M32C_OPERAND_IMM_12_S4N : |
598 | 0 | print_signed4n (cd, info, fields->f_imm_12_s4, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); |
599 | 0 | break; |
600 | 0 | case M32C_OPERAND_IMM_13_U3 : |
601 | 0 | print_normal (cd, info, fields->f_imm_13_u3, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); |
602 | 0 | break; |
603 | 0 | case M32C_OPERAND_IMM_16_HI : |
604 | 0 | print_normal (cd, info, fields->f_dsp_16_s16, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); |
605 | 0 | break; |
606 | 0 | case M32C_OPERAND_IMM_16_QI : |
607 | 0 | print_normal (cd, info, fields->f_dsp_16_s8, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); |
608 | 0 | break; |
609 | 0 | case M32C_OPERAND_IMM_16_SI : |
610 | 0 | print_normal (cd, info, fields->f_dsp_16_s32, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_VIRTUAL), pc, length); |
611 | 0 | break; |
612 | 0 | case M32C_OPERAND_IMM_20_S4 : |
613 | 0 | print_normal (cd, info, fields->f_imm_20_s4, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); |
614 | 0 | break; |
615 | 0 | case M32C_OPERAND_IMM_24_HI : |
616 | 0 | print_normal (cd, info, fields->f_dsp_24_s16, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_VIRTUAL), pc, length); |
617 | 0 | break; |
618 | 0 | case M32C_OPERAND_IMM_24_QI : |
619 | 0 | print_normal (cd, info, fields->f_dsp_24_s8, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); |
620 | 0 | break; |
621 | 0 | case M32C_OPERAND_IMM_24_SI : |
622 | 0 | print_normal (cd, info, fields->f_dsp_24_s32, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_VIRTUAL), pc, length); |
623 | 0 | break; |
624 | 0 | case M32C_OPERAND_IMM_32_HI : |
625 | 0 | print_normal (cd, info, fields->f_dsp_32_s16, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); |
626 | 0 | break; |
627 | 0 | case M32C_OPERAND_IMM_32_QI : |
628 | 0 | print_normal (cd, info, fields->f_dsp_32_s8, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); |
629 | 0 | break; |
630 | 0 | case M32C_OPERAND_IMM_32_SI : |
631 | 0 | print_normal (cd, info, fields->f_dsp_32_s32, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); |
632 | 0 | break; |
633 | 0 | case M32C_OPERAND_IMM_40_HI : |
634 | 0 | print_normal (cd, info, fields->f_dsp_40_s16, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); |
635 | 0 | break; |
636 | 0 | case M32C_OPERAND_IMM_40_QI : |
637 | 0 | print_normal (cd, info, fields->f_dsp_40_s8, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); |
638 | 0 | break; |
639 | 0 | case M32C_OPERAND_IMM_40_SI : |
640 | 0 | print_normal (cd, info, fields->f_dsp_40_s32, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_VIRTUAL), pc, length); |
641 | 0 | break; |
642 | 0 | case M32C_OPERAND_IMM_48_HI : |
643 | 0 | print_normal (cd, info, fields->f_dsp_48_s16, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); |
644 | 0 | break; |
645 | 0 | case M32C_OPERAND_IMM_48_QI : |
646 | 0 | print_normal (cd, info, fields->f_dsp_48_s8, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); |
647 | 0 | break; |
648 | 0 | case M32C_OPERAND_IMM_48_SI : |
649 | 0 | print_normal (cd, info, fields->f_dsp_48_s32, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_VIRTUAL), pc, length); |
650 | 0 | break; |
651 | 0 | case M32C_OPERAND_IMM_56_HI : |
652 | 0 | print_normal (cd, info, fields->f_dsp_56_s16, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_VIRTUAL), pc, length); |
653 | 0 | break; |
654 | 0 | case M32C_OPERAND_IMM_56_QI : |
655 | 0 | print_normal (cd, info, fields->f_dsp_56_s8, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); |
656 | 0 | break; |
657 | 0 | case M32C_OPERAND_IMM_64_HI : |
658 | 0 | print_normal (cd, info, fields->f_dsp_64_s16, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); |
659 | 0 | break; |
660 | 0 | case M32C_OPERAND_IMM_8_HI : |
661 | 0 | print_normal (cd, info, fields->f_dsp_8_s16, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); |
662 | 0 | break; |
663 | 0 | case M32C_OPERAND_IMM_8_QI : |
664 | 0 | print_normal (cd, info, fields->f_dsp_8_s8, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); |
665 | 0 | break; |
666 | 0 | case M32C_OPERAND_IMM_8_S4 : |
667 | 0 | print_normal (cd, info, fields->f_imm_8_s4, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); |
668 | 0 | break; |
669 | 0 | case M32C_OPERAND_IMM_8_S4N : |
670 | 0 | print_signed4n (cd, info, fields->f_imm_8_s4, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); |
671 | 0 | break; |
672 | 0 | case M32C_OPERAND_IMM_SH_12_S4 : |
673 | 0 | print_keyword (cd, info, & m32c_cgen_opval_h_shimm, fields->f_imm_12_s4, 0); |
674 | 0 | break; |
675 | 0 | case M32C_OPERAND_IMM_SH_20_S4 : |
676 | 0 | print_keyword (cd, info, & m32c_cgen_opval_h_shimm, fields->f_imm_20_s4, 0); |
677 | 0 | break; |
678 | 0 | case M32C_OPERAND_IMM_SH_8_S4 : |
679 | 0 | print_keyword (cd, info, & m32c_cgen_opval_h_shimm, fields->f_imm_8_s4, 0); |
680 | 0 | break; |
681 | 0 | case M32C_OPERAND_IMM1_S : |
682 | 0 | print_normal (cd, info, fields->f_imm1_S, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); |
683 | 0 | break; |
684 | 0 | case M32C_OPERAND_IMM3_S : |
685 | 0 | print_normal (cd, info, fields->f_imm3_S, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_VIRTUAL), pc, length); |
686 | 0 | break; |
687 | 0 | case M32C_OPERAND_LAB_16_8 : |
688 | 0 | print_address (cd, info, fields->f_lab_16_8, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length); |
689 | 0 | break; |
690 | 0 | case M32C_OPERAND_LAB_24_8 : |
691 | 0 | print_address (cd, info, fields->f_lab_24_8, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length); |
692 | 0 | break; |
693 | 0 | case M32C_OPERAND_LAB_32_8 : |
694 | 0 | print_address (cd, info, fields->f_lab_32_8, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length); |
695 | 0 | break; |
696 | 0 | case M32C_OPERAND_LAB_40_8 : |
697 | 0 | print_address (cd, info, fields->f_lab_40_8, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length); |
698 | 0 | break; |
699 | 0 | case M32C_OPERAND_LAB_5_3 : |
700 | 0 | print_address (cd, info, fields->f_lab_5_3, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length); |
701 | 0 | break; |
702 | 0 | case M32C_OPERAND_LAB_8_16 : |
703 | 0 | print_address (cd, info, fields->f_lab_8_16, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length); |
704 | 0 | break; |
705 | 0 | case M32C_OPERAND_LAB_8_24 : |
706 | 0 | print_address (cd, info, fields->f_lab_8_24, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_ABS_ADDR), pc, length); |
707 | 0 | break; |
708 | 0 | case M32C_OPERAND_LAB_8_8 : |
709 | 0 | print_address (cd, info, fields->f_lab_8_8, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length); |
710 | 0 | break; |
711 | 0 | case M32C_OPERAND_LAB32_JMP_S : |
712 | 0 | print_address (cd, info, fields->f_lab32_jmp_s, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_PCREL_ADDR)|(1<<CGEN_OPERAND_VIRTUAL), pc, length); |
713 | 0 | break; |
714 | 0 | case M32C_OPERAND_Q : |
715 | 0 | print_Q (cd, info, 0, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); |
716 | 0 | break; |
717 | 0 | case M32C_OPERAND_R0 : |
718 | 0 | print_keyword (cd, info, & m32c_cgen_opval_h_r0, 0, 0); |
719 | 0 | break; |
720 | 0 | case M32C_OPERAND_R0H : |
721 | 0 | print_keyword (cd, info, & m32c_cgen_opval_h_r0h, 0, 0); |
722 | 0 | break; |
723 | 0 | case M32C_OPERAND_R0L : |
724 | 0 | print_keyword (cd, info, & m32c_cgen_opval_h_r0l, 0, 0); |
725 | 0 | break; |
726 | 0 | case M32C_OPERAND_R1 : |
727 | 0 | print_keyword (cd, info, & m32c_cgen_opval_h_r1, 0, 0); |
728 | 0 | break; |
729 | 0 | case M32C_OPERAND_R1R2R0 : |
730 | 0 | print_keyword (cd, info, & m32c_cgen_opval_h_r1r2r0, 0, 0); |
731 | 0 | break; |
732 | 0 | case M32C_OPERAND_R2 : |
733 | 0 | print_keyword (cd, info, & m32c_cgen_opval_h_r2, 0, 0); |
734 | 0 | break; |
735 | 0 | case M32C_OPERAND_R2R0 : |
736 | 0 | print_keyword (cd, info, & m32c_cgen_opval_h_r2r0, 0, 0); |
737 | 0 | break; |
738 | 0 | case M32C_OPERAND_R3 : |
739 | 0 | print_keyword (cd, info, & m32c_cgen_opval_h_r3, 0, 0); |
740 | 0 | break; |
741 | 0 | case M32C_OPERAND_R3R1 : |
742 | 0 | print_keyword (cd, info, & m32c_cgen_opval_h_r3r1, 0, 0); |
743 | 0 | break; |
744 | 0 | case M32C_OPERAND_REGSETPOP : |
745 | 0 | print_pop_regset (cd, info, fields->f_8_8, 0, pc, length); |
746 | 0 | break; |
747 | 0 | case M32C_OPERAND_REGSETPUSH : |
748 | 0 | print_push_regset (cd, info, fields->f_8_8, 0, pc, length); |
749 | 0 | break; |
750 | 0 | case M32C_OPERAND_RN16_PUSH_S : |
751 | 0 | print_keyword (cd, info, & m32c_cgen_opval_h_gr_QI, fields->f_4_1, 0); |
752 | 0 | break; |
753 | 0 | case M32C_OPERAND_S : |
754 | 0 | print_S (cd, info, 0, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); |
755 | 0 | break; |
756 | 0 | case M32C_OPERAND_SRC16AN : |
757 | 0 | print_keyword (cd, info, & m32c_cgen_opval_h_ar, fields->f_src16_an, 0); |
758 | 0 | break; |
759 | 0 | case M32C_OPERAND_SRC16ANHI : |
760 | 0 | print_keyword (cd, info, & m32c_cgen_opval_h_ar_HI, fields->f_src16_an, 0); |
761 | 0 | break; |
762 | 0 | case M32C_OPERAND_SRC16ANQI : |
763 | 0 | print_keyword (cd, info, & m32c_cgen_opval_h_ar_QI, fields->f_src16_an, 0); |
764 | 0 | break; |
765 | 0 | case M32C_OPERAND_SRC16RNHI : |
766 | 0 | print_keyword (cd, info, & m32c_cgen_opval_h_gr_HI, fields->f_src16_rn, 0); |
767 | 0 | break; |
768 | 0 | case M32C_OPERAND_SRC16RNQI : |
769 | 0 | print_keyword (cd, info, & m32c_cgen_opval_h_gr_QI, fields->f_src16_rn, 0); |
770 | 0 | break; |
771 | 0 | case M32C_OPERAND_SRC32ANPREFIXED : |
772 | 0 | print_keyword (cd, info, & m32c_cgen_opval_h_ar, fields->f_src32_an_prefixed, 0); |
773 | 0 | break; |
774 | 0 | case M32C_OPERAND_SRC32ANPREFIXEDHI : |
775 | 0 | print_keyword (cd, info, & m32c_cgen_opval_h_ar_HI, fields->f_src32_an_prefixed, 0); |
776 | 0 | break; |
777 | 0 | case M32C_OPERAND_SRC32ANPREFIXEDQI : |
778 | 0 | print_keyword (cd, info, & m32c_cgen_opval_h_ar_QI, fields->f_src32_an_prefixed, 0); |
779 | 0 | break; |
780 | 0 | case M32C_OPERAND_SRC32ANPREFIXEDSI : |
781 | 0 | print_keyword (cd, info, & m32c_cgen_opval_h_ar, fields->f_src32_an_prefixed, 0); |
782 | 0 | break; |
783 | 0 | case M32C_OPERAND_SRC32ANUNPREFIXED : |
784 | 0 | print_keyword (cd, info, & m32c_cgen_opval_h_ar, fields->f_src32_an_unprefixed, 0); |
785 | 0 | break; |
786 | 0 | case M32C_OPERAND_SRC32ANUNPREFIXEDHI : |
787 | 0 | print_keyword (cd, info, & m32c_cgen_opval_h_ar_HI, fields->f_src32_an_unprefixed, 0); |
788 | 0 | break; |
789 | 0 | case M32C_OPERAND_SRC32ANUNPREFIXEDQI : |
790 | 0 | print_keyword (cd, info, & m32c_cgen_opval_h_ar_QI, fields->f_src32_an_unprefixed, 0); |
791 | 0 | break; |
792 | 0 | case M32C_OPERAND_SRC32ANUNPREFIXEDSI : |
793 | 0 | print_keyword (cd, info, & m32c_cgen_opval_h_ar, fields->f_src32_an_unprefixed, 0); |
794 | 0 | break; |
795 | 0 | case M32C_OPERAND_SRC32RNPREFIXEDHI : |
796 | 0 | print_keyword (cd, info, & m32c_cgen_opval_h_gr_HI, fields->f_src32_rn_prefixed_HI, 0); |
797 | 0 | break; |
798 | 0 | case M32C_OPERAND_SRC32RNPREFIXEDQI : |
799 | 0 | print_keyword (cd, info, & m32c_cgen_opval_h_gr_QI, fields->f_src32_rn_prefixed_QI, 0); |
800 | 0 | break; |
801 | 0 | case M32C_OPERAND_SRC32RNPREFIXEDSI : |
802 | 0 | print_keyword (cd, info, & m32c_cgen_opval_h_gr_SI, fields->f_src32_rn_prefixed_SI, 0); |
803 | 0 | break; |
804 | 0 | case M32C_OPERAND_SRC32RNUNPREFIXEDHI : |
805 | 0 | print_keyword (cd, info, & m32c_cgen_opval_h_gr_HI, fields->f_src32_rn_unprefixed_HI, 0); |
806 | 0 | break; |
807 | 0 | case M32C_OPERAND_SRC32RNUNPREFIXEDQI : |
808 | 0 | print_keyword (cd, info, & m32c_cgen_opval_h_gr_QI, fields->f_src32_rn_unprefixed_QI, 0); |
809 | 0 | break; |
810 | 0 | case M32C_OPERAND_SRC32RNUNPREFIXEDSI : |
811 | 0 | print_keyword (cd, info, & m32c_cgen_opval_h_gr_SI, fields->f_src32_rn_unprefixed_SI, 0); |
812 | 0 | break; |
813 | 0 | case M32C_OPERAND_SRCDST16_R0L_R0H_S_NORMAL : |
814 | 0 | print_r0l_r0h (cd, info, fields->f_5_1, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); |
815 | 0 | break; |
816 | 0 | case M32C_OPERAND_X : |
817 | 0 | print_X (cd, info, 0, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); |
818 | 0 | break; |
819 | 0 | case M32C_OPERAND_Z : |
820 | 0 | print_Z (cd, info, 0, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); |
821 | 0 | break; |
822 | 0 | case M32C_OPERAND_COND16_16 : |
823 | 0 | print_keyword (cd, info, & m32c_cgen_opval_h_cond16, fields->f_dsp_16_u8, 0); |
824 | 0 | break; |
825 | 0 | case M32C_OPERAND_COND16_24 : |
826 | 0 | print_keyword (cd, info, & m32c_cgen_opval_h_cond16, fields->f_dsp_24_u8, 0); |
827 | 0 | break; |
828 | 0 | case M32C_OPERAND_COND16_32 : |
829 | 0 | print_keyword (cd, info, & m32c_cgen_opval_h_cond16, fields->f_dsp_32_u8, 0); |
830 | 0 | break; |
831 | 0 | case M32C_OPERAND_COND16C : |
832 | 0 | print_keyword (cd, info, & m32c_cgen_opval_h_cond16c, fields->f_cond16, 0); |
833 | 0 | break; |
834 | 0 | case M32C_OPERAND_COND16J : |
835 | 0 | print_keyword (cd, info, & m32c_cgen_opval_h_cond16j, fields->f_cond16, 0); |
836 | 0 | break; |
837 | 0 | case M32C_OPERAND_COND16J5 : |
838 | 0 | print_keyword (cd, info, & m32c_cgen_opval_h_cond16j_5, fields->f_cond16j_5, 0); |
839 | 0 | break; |
840 | 0 | case M32C_OPERAND_COND32 : |
841 | 0 | print_keyword (cd, info, & m32c_cgen_opval_h_cond32, fields->f_cond32, 0|(1<<CGEN_OPERAND_VIRTUAL)); |
842 | 0 | break; |
843 | 0 | case M32C_OPERAND_COND32_16 : |
844 | 0 | print_keyword (cd, info, & m32c_cgen_opval_h_cond32, fields->f_dsp_16_u8, 0); |
845 | 0 | break; |
846 | 0 | case M32C_OPERAND_COND32_24 : |
847 | 0 | print_keyword (cd, info, & m32c_cgen_opval_h_cond32, fields->f_dsp_24_u8, 0); |
848 | 0 | break; |
849 | 0 | case M32C_OPERAND_COND32_32 : |
850 | 0 | print_keyword (cd, info, & m32c_cgen_opval_h_cond32, fields->f_dsp_32_u8, 0); |
851 | 0 | break; |
852 | 0 | case M32C_OPERAND_COND32_40 : |
853 | 0 | print_keyword (cd, info, & m32c_cgen_opval_h_cond32, fields->f_dsp_40_u8, 0); |
854 | 0 | break; |
855 | 0 | case M32C_OPERAND_COND32J : |
856 | 0 | print_keyword (cd, info, & m32c_cgen_opval_h_cond32, fields->f_cond32j, 0|(1<<CGEN_OPERAND_VIRTUAL)); |
857 | 0 | break; |
858 | 0 | case M32C_OPERAND_CR1_PREFIXED_32 : |
859 | 0 | print_keyword (cd, info, & m32c_cgen_opval_h_cr1_32, fields->f_21_3, 0); |
860 | 0 | break; |
861 | 0 | case M32C_OPERAND_CR1_UNPREFIXED_32 : |
862 | 0 | print_keyword (cd, info, & m32c_cgen_opval_h_cr1_32, fields->f_13_3, 0); |
863 | 0 | break; |
864 | 0 | case M32C_OPERAND_CR16 : |
865 | 0 | print_keyword (cd, info, & m32c_cgen_opval_h_cr_16, fields->f_9_3, 0); |
866 | 0 | break; |
867 | 0 | case M32C_OPERAND_CR2_32 : |
868 | 0 | print_keyword (cd, info, & m32c_cgen_opval_h_cr2_32, fields->f_13_3, 0); |
869 | 0 | break; |
870 | 0 | case M32C_OPERAND_CR3_PREFIXED_32 : |
871 | 0 | print_keyword (cd, info, & m32c_cgen_opval_h_cr3_32, fields->f_21_3, 0); |
872 | 0 | break; |
873 | 0 | case M32C_OPERAND_CR3_UNPREFIXED_32 : |
874 | 0 | print_keyword (cd, info, & m32c_cgen_opval_h_cr3_32, fields->f_13_3, 0); |
875 | 0 | break; |
876 | 0 | case M32C_OPERAND_FLAGS16 : |
877 | 0 | print_keyword (cd, info, & m32c_cgen_opval_h_flags, fields->f_9_3, 0); |
878 | 0 | break; |
879 | 0 | case M32C_OPERAND_FLAGS32 : |
880 | 0 | print_keyword (cd, info, & m32c_cgen_opval_h_flags, fields->f_13_3, 0); |
881 | 0 | break; |
882 | 0 | case M32C_OPERAND_SCCOND32 : |
883 | 0 | print_keyword (cd, info, & m32c_cgen_opval_h_cond32, fields->f_cond16, 0); |
884 | 0 | break; |
885 | 0 | case M32C_OPERAND_SIZE : |
886 | 0 | print_size (cd, info, 0, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); |
887 | 0 | break; |
888 | | |
889 | 0 | default : |
890 | | /* xgettext:c-format */ |
891 | 0 | opcodes_error_handler |
892 | 0 | (_("internal error: unrecognized field %d while printing insn"), |
893 | 0 | opindex); |
894 | 0 | abort (); |
895 | 0 | } |
896 | 0 | } |
897 | | |
898 | | cgen_print_fn * const m32c_cgen_print_handlers[] = |
899 | | { |
900 | | print_insn_normal, |
901 | | }; |
902 | | |
903 | | |
904 | | void |
905 | | m32c_cgen_init_dis (CGEN_CPU_DESC cd) |
906 | 0 | { |
907 | 0 | m32c_cgen_init_opcode_table (cd); |
908 | 0 | m32c_cgen_init_ibld_table (cd); |
909 | 0 | cd->print_handlers = & m32c_cgen_print_handlers[0]; |
910 | 0 | cd->print_operand = m32c_cgen_print_operand; |
911 | 0 | } |
912 | | |
913 | | |
914 | | /* Default print handler. */ |
915 | | |
916 | | static void |
917 | | print_normal (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, |
918 | | void *dis_info, |
919 | | long value, |
920 | | unsigned int attrs, |
921 | | bfd_vma pc ATTRIBUTE_UNUSED, |
922 | | int length ATTRIBUTE_UNUSED) |
923 | 0 | { |
924 | 0 | disassemble_info *info = (disassemble_info *) dis_info; |
925 | | |
926 | | /* Print the operand as directed by the attributes. */ |
927 | 0 | if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) |
928 | 0 | ; /* nothing to do */ |
929 | 0 | else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED)) |
930 | 0 | (*info->fprintf_func) (info->stream, "%ld", value); |
931 | 0 | else |
932 | 0 | (*info->fprintf_func) (info->stream, "0x%lx", value); |
933 | 0 | } |
934 | | |
935 | | /* Default address handler. */ |
936 | | |
937 | | static void |
938 | | print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, |
939 | | void *dis_info, |
940 | | bfd_vma value, |
941 | | unsigned int attrs, |
942 | | bfd_vma pc ATTRIBUTE_UNUSED, |
943 | | int length ATTRIBUTE_UNUSED) |
944 | 0 | { |
945 | 0 | disassemble_info *info = (disassemble_info *) dis_info; |
946 | | |
947 | | /* Print the operand as directed by the attributes. */ |
948 | 0 | if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) |
949 | 0 | ; /* Nothing to do. */ |
950 | 0 | else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR)) |
951 | 0 | (*info->print_address_func) (value, info); |
952 | 0 | else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR)) |
953 | 0 | (*info->print_address_func) (value, info); |
954 | 0 | else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED)) |
955 | 0 | (*info->fprintf_func) (info->stream, "%ld", (long) value); |
956 | 0 | else |
957 | 0 | (*info->fprintf_func) (info->stream, "0x%lx", (long) value); |
958 | 0 | } |
959 | | |
960 | | /* Keyword print handler. */ |
961 | | |
962 | | static void |
963 | | print_keyword (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, |
964 | | void *dis_info, |
965 | | CGEN_KEYWORD *keyword_table, |
966 | | long value, |
967 | | unsigned int attrs ATTRIBUTE_UNUSED) |
968 | 0 | { |
969 | 0 | disassemble_info *info = (disassemble_info *) dis_info; |
970 | 0 | const CGEN_KEYWORD_ENTRY *ke; |
971 | |
|
972 | 0 | ke = cgen_keyword_lookup_value (keyword_table, value); |
973 | 0 | if (ke != NULL) |
974 | 0 | (*info->fprintf_func) (info->stream, "%s", ke->name); |
975 | 0 | else |
976 | 0 | (*info->fprintf_func) (info->stream, "???"); |
977 | 0 | } |
978 | | |
979 | | /* Default insn printer. |
980 | | |
981 | | DIS_INFO is defined as `void *' so the disassembler needn't know anything |
982 | | about disassemble_info. */ |
983 | | |
984 | | static void |
985 | | print_insn_normal (CGEN_CPU_DESC cd, |
986 | | void *dis_info, |
987 | | const CGEN_INSN *insn, |
988 | | CGEN_FIELDS *fields, |
989 | | bfd_vma pc, |
990 | | int length) |
991 | 0 | { |
992 | 0 | const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); |
993 | 0 | disassemble_info *info = (disassemble_info *) dis_info; |
994 | 0 | const CGEN_SYNTAX_CHAR_TYPE *syn; |
995 | |
|
996 | 0 | CGEN_INIT_PRINT (cd); |
997 | |
|
998 | 0 | for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn) |
999 | 0 | { |
1000 | 0 | if (CGEN_SYNTAX_MNEMONIC_P (*syn)) |
1001 | 0 | { |
1002 | 0 | (*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn)); |
1003 | 0 | continue; |
1004 | 0 | } |
1005 | 0 | if (CGEN_SYNTAX_CHAR_P (*syn)) |
1006 | 0 | { |
1007 | 0 | (*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn)); |
1008 | 0 | continue; |
1009 | 0 | } |
1010 | | |
1011 | | /* We have an operand. */ |
1012 | 0 | m32c_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info, |
1013 | 0 | fields, CGEN_INSN_ATTRS (insn), pc, length); |
1014 | 0 | } |
1015 | 0 | } |
1016 | | |
1017 | | /* Subroutine of print_insn. Reads an insn into the given buffers and updates |
1018 | | the extract info. |
1019 | | Returns 0 if all is well, non-zero otherwise. */ |
1020 | | |
1021 | | static int |
1022 | | read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, |
1023 | | bfd_vma pc, |
1024 | | disassemble_info *info, |
1025 | | bfd_byte *buf, |
1026 | | int buflen, |
1027 | | CGEN_EXTRACT_INFO *ex_info, |
1028 | | unsigned long *insn_value) |
1029 | 0 | { |
1030 | 0 | int status = (*info->read_memory_func) (pc, buf, buflen, info); |
1031 | |
|
1032 | 0 | if (status != 0) |
1033 | 0 | { |
1034 | 0 | (*info->memory_error_func) (status, pc, info); |
1035 | 0 | return -1; |
1036 | 0 | } |
1037 | | |
1038 | 0 | ex_info->dis_info = info; |
1039 | 0 | ex_info->valid = (1 << buflen) - 1; |
1040 | 0 | ex_info->insn_bytes = buf; |
1041 | |
|
1042 | 0 | *insn_value = bfd_get_bits (buf, buflen * 8, info->endian == BFD_ENDIAN_BIG); |
1043 | 0 | return 0; |
1044 | 0 | } |
1045 | | |
1046 | | /* Utility to print an insn. |
1047 | | BUF is the base part of the insn, target byte order, BUFLEN bytes long. |
1048 | | The result is the size of the insn in bytes or zero for an unknown insn |
1049 | | or -1 if an error occurs fetching data (memory_error_func will have |
1050 | | been called). */ |
1051 | | |
1052 | | static int |
1053 | | print_insn (CGEN_CPU_DESC cd, |
1054 | | bfd_vma pc, |
1055 | | disassemble_info *info, |
1056 | | bfd_byte *buf, |
1057 | | unsigned int buflen) |
1058 | 0 | { |
1059 | 0 | CGEN_INSN_INT insn_value; |
1060 | 0 | const CGEN_INSN_LIST *insn_list; |
1061 | 0 | CGEN_EXTRACT_INFO ex_info; |
1062 | 0 | int basesize; |
1063 | | |
1064 | | /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */ |
1065 | 0 | basesize = cd->base_insn_bitsize < buflen * 8 ? |
1066 | 0 | cd->base_insn_bitsize : buflen * 8; |
1067 | 0 | insn_value = cgen_get_insn_value (cd, buf, basesize, cd->insn_endian); |
1068 | | |
1069 | | |
1070 | | /* Fill in ex_info fields like read_insn would. Don't actually call |
1071 | | read_insn, since the incoming buffer is already read (and possibly |
1072 | | modified a la m32r). */ |
1073 | 0 | ex_info.valid = (1 << buflen) - 1; |
1074 | 0 | ex_info.dis_info = info; |
1075 | 0 | ex_info.insn_bytes = buf; |
1076 | | |
1077 | | /* The instructions are stored in hash lists. |
1078 | | Pick the first one and keep trying until we find the right one. */ |
1079 | |
|
1080 | 0 | insn_list = CGEN_DIS_LOOKUP_INSN (cd, (char *) buf, insn_value); |
1081 | 0 | while (insn_list != NULL) |
1082 | 0 | { |
1083 | 0 | const CGEN_INSN *insn = insn_list->insn; |
1084 | 0 | CGEN_FIELDS fields; |
1085 | 0 | int length; |
1086 | 0 | unsigned long insn_value_cropped; |
1087 | |
|
1088 | 0 | #ifdef CGEN_VALIDATE_INSN_SUPPORTED |
1089 | | /* Not needed as insn shouldn't be in hash lists if not supported. */ |
1090 | | /* Supported by this cpu? */ |
1091 | 0 | if (! m32c_cgen_insn_supported (cd, insn)) |
1092 | 0 | { |
1093 | 0 | insn_list = CGEN_DIS_NEXT_INSN (insn_list); |
1094 | 0 | continue; |
1095 | 0 | } |
1096 | 0 | #endif |
1097 | | |
1098 | | /* Basic bit mask must be correct. */ |
1099 | | /* ??? May wish to allow target to defer this check until the extract |
1100 | | handler. */ |
1101 | | |
1102 | | /* Base size may exceed this instruction's size. Extract the |
1103 | | relevant part from the buffer. */ |
1104 | 0 | if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen && |
1105 | 0 | (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) |
1106 | 0 | insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn), |
1107 | 0 | info->endian == BFD_ENDIAN_BIG); |
1108 | 0 | else |
1109 | 0 | insn_value_cropped = insn_value; |
1110 | |
|
1111 | 0 | if ((insn_value_cropped & CGEN_INSN_BASE_MASK (insn)) |
1112 | 0 | == CGEN_INSN_BASE_VALUE (insn)) |
1113 | 0 | { |
1114 | | /* Printing is handled in two passes. The first pass parses the |
1115 | | machine insn and extracts the fields. The second pass prints |
1116 | | them. */ |
1117 | | |
1118 | | /* Make sure the entire insn is loaded into insn_value, if it |
1119 | | can fit. */ |
1120 | 0 | if (((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize) && |
1121 | 0 | (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) |
1122 | 0 | { |
1123 | 0 | unsigned long full_insn_value; |
1124 | 0 | int rc = read_insn (cd, pc, info, buf, |
1125 | 0 | CGEN_INSN_BITSIZE (insn) / 8, |
1126 | 0 | & ex_info, & full_insn_value); |
1127 | 0 | if (rc != 0) |
1128 | 0 | return rc; |
1129 | 0 | length = CGEN_EXTRACT_FN (cd, insn) |
1130 | 0 | (cd, insn, &ex_info, full_insn_value, &fields, pc); |
1131 | 0 | } |
1132 | 0 | else |
1133 | 0 | length = CGEN_EXTRACT_FN (cd, insn) |
1134 | 0 | (cd, insn, &ex_info, insn_value_cropped, &fields, pc); |
1135 | | |
1136 | | /* Length < 0 -> error. */ |
1137 | 0 | if (length < 0) |
1138 | 0 | return length; |
1139 | 0 | if (length > 0) |
1140 | 0 | { |
1141 | 0 | CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length); |
1142 | | /* Length is in bits, result is in bytes. */ |
1143 | 0 | return length / 8; |
1144 | 0 | } |
1145 | 0 | } |
1146 | | |
1147 | 0 | insn_list = CGEN_DIS_NEXT_INSN (insn_list); |
1148 | 0 | } |
1149 | | |
1150 | 0 | return 0; |
1151 | 0 | } |
1152 | | |
1153 | | /* Default value for CGEN_PRINT_INSN. |
1154 | | The result is the size of the insn in bytes or zero for an unknown insn |
1155 | | or -1 if an error occured fetching bytes. */ |
1156 | | |
1157 | | #ifndef CGEN_PRINT_INSN |
1158 | 0 | #define CGEN_PRINT_INSN default_print_insn |
1159 | | #endif |
1160 | | |
1161 | | static int |
1162 | | default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info) |
1163 | 0 | { |
1164 | 0 | bfd_byte buf[CGEN_MAX_INSN_SIZE]; |
1165 | 0 | int buflen; |
1166 | 0 | int status; |
1167 | | |
1168 | | /* Attempt to read the base part of the insn. */ |
1169 | 0 | buflen = cd->base_insn_bitsize / 8; |
1170 | 0 | status = (*info->read_memory_func) (pc, buf, buflen, info); |
1171 | | |
1172 | | /* Try again with the minimum part, if min < base. */ |
1173 | 0 | if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize)) |
1174 | 0 | { |
1175 | 0 | buflen = cd->min_insn_bitsize / 8; |
1176 | 0 | status = (*info->read_memory_func) (pc, buf, buflen, info); |
1177 | 0 | } |
1178 | |
|
1179 | 0 | if (status != 0) |
1180 | 0 | { |
1181 | 0 | (*info->memory_error_func) (status, pc, info); |
1182 | 0 | return -1; |
1183 | 0 | } |
1184 | | |
1185 | 0 | return print_insn (cd, pc, info, buf, buflen); |
1186 | 0 | } |
1187 | | |
1188 | | /* Main entry point. |
1189 | | Print one instruction from PC on INFO->STREAM. |
1190 | | Return the size of the instruction (in bytes). */ |
1191 | | |
1192 | | typedef struct cpu_desc_list |
1193 | | { |
1194 | | struct cpu_desc_list *next; |
1195 | | CGEN_BITSET *isa; |
1196 | | int mach; |
1197 | | int endian; |
1198 | | int insn_endian; |
1199 | | CGEN_CPU_DESC cd; |
1200 | | } cpu_desc_list; |
1201 | | |
1202 | | int |
1203 | | print_insn_m32c (bfd_vma pc, disassemble_info *info) |
1204 | 0 | { |
1205 | 0 | static cpu_desc_list *cd_list = 0; |
1206 | 0 | cpu_desc_list *cl = 0; |
1207 | 0 | static CGEN_CPU_DESC cd = 0; |
1208 | 0 | static CGEN_BITSET *prev_isa; |
1209 | 0 | static int prev_mach; |
1210 | 0 | static int prev_endian; |
1211 | 0 | static int prev_insn_endian; |
1212 | 0 | int length; |
1213 | 0 | CGEN_BITSET *isa; |
1214 | 0 | int mach; |
1215 | 0 | int endian = (info->endian == BFD_ENDIAN_BIG |
1216 | 0 | ? CGEN_ENDIAN_BIG |
1217 | 0 | : CGEN_ENDIAN_LITTLE); |
1218 | 0 | int insn_endian = (info->endian_code == BFD_ENDIAN_BIG |
1219 | 0 | ? CGEN_ENDIAN_BIG |
1220 | 0 | : CGEN_ENDIAN_LITTLE); |
1221 | 0 | enum bfd_architecture arch; |
1222 | | |
1223 | | /* ??? gdb will set mach but leave the architecture as "unknown" */ |
1224 | 0 | #ifndef CGEN_BFD_ARCH |
1225 | 0 | #define CGEN_BFD_ARCH bfd_arch_m32c |
1226 | 0 | #endif |
1227 | 0 | arch = info->arch; |
1228 | 0 | if (arch == bfd_arch_unknown) |
1229 | 0 | arch = CGEN_BFD_ARCH; |
1230 | | |
1231 | | /* There's no standard way to compute the machine or isa number |
1232 | | so we leave it to the target. */ |
1233 | | #ifdef CGEN_COMPUTE_MACH |
1234 | | mach = CGEN_COMPUTE_MACH (info); |
1235 | | #else |
1236 | 0 | mach = info->mach; |
1237 | 0 | #endif |
1238 | |
|
1239 | | #ifdef CGEN_COMPUTE_ISA |
1240 | | { |
1241 | | static CGEN_BITSET *permanent_isa; |
1242 | | |
1243 | | if (!permanent_isa) |
1244 | | permanent_isa = cgen_bitset_create (MAX_ISAS); |
1245 | | isa = permanent_isa; |
1246 | | cgen_bitset_clear (isa); |
1247 | | cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info)); |
1248 | | } |
1249 | | #else |
1250 | 0 | isa = info->private_data; |
1251 | 0 | #endif |
1252 | | |
1253 | | /* If we've switched cpu's, try to find a handle we've used before */ |
1254 | 0 | if (cd |
1255 | 0 | && (cgen_bitset_compare (isa, prev_isa) != 0 |
1256 | 0 | || mach != prev_mach |
1257 | 0 | || endian != prev_endian)) |
1258 | 0 | { |
1259 | 0 | cd = 0; |
1260 | 0 | for (cl = cd_list; cl; cl = cl->next) |
1261 | 0 | { |
1262 | 0 | if (cgen_bitset_compare (cl->isa, isa) == 0 && |
1263 | 0 | cl->mach == mach && |
1264 | 0 | cl->endian == endian) |
1265 | 0 | { |
1266 | 0 | cd = cl->cd; |
1267 | 0 | prev_isa = cd->isas; |
1268 | 0 | break; |
1269 | 0 | } |
1270 | 0 | } |
1271 | 0 | } |
1272 | | |
1273 | | /* If we haven't initialized yet, initialize the opcode table. */ |
1274 | 0 | if (! cd) |
1275 | 0 | { |
1276 | 0 | const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach); |
1277 | 0 | const char *mach_name; |
1278 | |
|
1279 | 0 | if (!arch_type) |
1280 | 0 | abort (); |
1281 | 0 | mach_name = arch_type->printable_name; |
1282 | |
|
1283 | 0 | prev_isa = cgen_bitset_copy (isa); |
1284 | 0 | prev_mach = mach; |
1285 | 0 | prev_endian = endian; |
1286 | 0 | prev_insn_endian = insn_endian; |
1287 | 0 | cd = m32c_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa, |
1288 | 0 | CGEN_CPU_OPEN_BFDMACH, mach_name, |
1289 | 0 | CGEN_CPU_OPEN_ENDIAN, prev_endian, |
1290 | 0 | CGEN_CPU_OPEN_INSN_ENDIAN, prev_insn_endian, |
1291 | 0 | CGEN_CPU_OPEN_END); |
1292 | 0 | if (!cd) |
1293 | 0 | abort (); |
1294 | | |
1295 | | /* Save this away for future reference. */ |
1296 | 0 | cl = xmalloc (sizeof (struct cpu_desc_list)); |
1297 | 0 | cl->cd = cd; |
1298 | 0 | cl->isa = prev_isa; |
1299 | 0 | cl->mach = mach; |
1300 | 0 | cl->endian = endian; |
1301 | 0 | cl->next = cd_list; |
1302 | 0 | cd_list = cl; |
1303 | |
|
1304 | 0 | m32c_cgen_init_dis (cd); |
1305 | 0 | } |
1306 | | |
1307 | | /* We try to have as much common code as possible. |
1308 | | But at this point some targets need to take over. */ |
1309 | | /* ??? Some targets may need a hook elsewhere. Try to avoid this, |
1310 | | but if not possible try to move this hook elsewhere rather than |
1311 | | have two hooks. */ |
1312 | 0 | length = CGEN_PRINT_INSN (cd, pc, info); |
1313 | 0 | if (length > 0) |
1314 | 0 | return length; |
1315 | 0 | if (length < 0) |
1316 | 0 | return -1; |
1317 | | |
1318 | 0 | (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG); |
1319 | 0 | return cd->default_insn_bitsize / 8; |
1320 | 0 | } |