/src/binutils-gdb/include/opcode/aarch64.h
Line | Count | Source (jump to first uncovered line) |
1 | | /* AArch64 assembler/disassembler support. |
2 | | |
3 | | Copyright (C) 2009-2023 Free Software Foundation, Inc. |
4 | | Contributed by ARM Ltd. |
5 | | |
6 | | This file is part of GNU Binutils. |
7 | | |
8 | | This program is free software; you can redistribute it and/or modify |
9 | | it under the terms of the GNU General Public License as published by |
10 | | the Free Software Foundation; either version 3 of the license, or |
11 | | (at your option) any later version. |
12 | | |
13 | | This program is distributed in the hope that it will be useful, |
14 | | but WITHOUT ANY WARRANTY; without even the implied warranty of |
15 | | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
16 | | GNU General Public License for more details. |
17 | | |
18 | | You should have received a copy of the GNU General Public License |
19 | | along with this program; see the file COPYING3. If not, |
20 | | see <http://www.gnu.org/licenses/>. */ |
21 | | |
22 | | #ifndef OPCODE_AARCH64_H |
23 | | #define OPCODE_AARCH64_H |
24 | | |
25 | | #include "bfd.h" |
26 | | #include <stdint.h> |
27 | | #include <assert.h> |
28 | | #include <stdlib.h> |
29 | | |
30 | | #include "dis-asm.h" |
31 | | |
32 | | #ifdef __cplusplus |
33 | | extern "C" { |
34 | | #endif |
35 | | |
36 | | /* The offset for pc-relative addressing is currently defined to be 0. */ |
37 | 2.09M | #define AARCH64_PCREL_OFFSET 0 |
38 | | |
39 | | typedef uint32_t aarch64_insn; |
40 | | |
41 | | /* The following bitmasks control CPU features. */ |
42 | | #define AARCH64_FEATURE_V8 (1ULL << 0) /* All processors. */ |
43 | | #define AARCH64_FEATURE_V8_6A (1ULL << 1) /* ARMv8.6 processors. */ |
44 | | #define AARCH64_FEATURE_BFLOAT16 (1ULL << 2) /* Bfloat16 insns. */ |
45 | 0 | #define AARCH64_FEATURE_V8A (1ULL << 3) /* Armv8-A processors. */ |
46 | 322 | #define AARCH64_FEATURE_SVE2 (1ULL << 4) /* SVE2 instructions. */ |
47 | | #define AARCH64_FEATURE_V8_2A (1ULL << 5) /* ARMv8.2 processors. */ |
48 | | #define AARCH64_FEATURE_V8_3A (1ULL << 6) /* ARMv8.3 processors. */ |
49 | | #define AARCH64_FEATURE_SVE2_AES (1ULL << 7) |
50 | | #define AARCH64_FEATURE_SVE2_BITPERM (1ULL << 8) |
51 | | #define AARCH64_FEATURE_SVE2_SM4 (1ULL << 9) |
52 | | #define AARCH64_FEATURE_SVE2_SHA3 (1ULL << 10) |
53 | | #define AARCH64_FEATURE_V8_4A (1ULL << 11) /* ARMv8.4 processors. */ |
54 | 2 | #define AARCH64_FEATURE_V8R (1ULL << 12) /* Armv8-R processors. */ |
55 | | #define AARCH64_FEATURE_V8_7A (1ULL << 13) /* Armv8.7 processors. */ |
56 | | #define AARCH64_FEATURE_SME (1ULL << 14) /* Scalable Matrix Extension. */ |
57 | | #define AARCH64_FEATURE_LS64 (1ULL << 15) /* Atomic 64-byte load/store. */ |
58 | | #define AARCH64_FEATURE_PAC (1ULL << 16) /* v8.3 Pointer Authentication. */ |
59 | | #define AARCH64_FEATURE_FP (1ULL << 17) /* FP instructions. */ |
60 | | #define AARCH64_FEATURE_SIMD (1ULL << 18) /* SIMD instructions. */ |
61 | | #define AARCH64_FEATURE_CRC (1ULL << 19) /* CRC instructions. */ |
62 | | #define AARCH64_FEATURE_LSE (1ULL << 20) /* LSE instructions. */ |
63 | | #define AARCH64_FEATURE_PAN (1ULL << 21) /* PAN instructions. */ |
64 | 0 | #define AARCH64_FEATURE_LOR (1ULL << 22) /* LOR instructions. */ |
65 | | #define AARCH64_FEATURE_RDMA (1ULL << 23) /* v8.1 SIMD instructions. */ |
66 | | #define AARCH64_FEATURE_V8_1A (1ULL << 24) /* v8.1 features. */ |
67 | | #define AARCH64_FEATURE_F16 (1ULL << 25) /* v8.2 FP16 instructions. */ |
68 | | #define AARCH64_FEATURE_RAS (1ULL << 26) /* RAS Extensions. */ |
69 | | #define AARCH64_FEATURE_PROFILE (1ULL << 27) /* Statistical Profiling. */ |
70 | 322 | #define AARCH64_FEATURE_SVE (1ULL << 28) /* SVE instructions. */ |
71 | | #define AARCH64_FEATURE_RCPC (1ULL << 29) /* RCPC instructions. */ |
72 | | #define AARCH64_FEATURE_COMPNUM (1ULL << 30) /* Complex # instructions. */ |
73 | | #define AARCH64_FEATURE_DOTPROD (1ULL << 31) /* Dot Product instructions. */ |
74 | | #define AARCH64_FEATURE_SM4 (1ULL << 32) /* SM3 & SM4 instructions. */ |
75 | | #define AARCH64_FEATURE_SHA2 (1ULL << 33) /* SHA2 instructions. */ |
76 | | #define AARCH64_FEATURE_SHA3 (1ULL << 34) /* SHA3 instructions. */ |
77 | | #define AARCH64_FEATURE_AES (1ULL << 35) /* AES instructions. */ |
78 | | #define AARCH64_FEATURE_F16_FML (1ULL << 36) /* v8.2 FP16FML ins. */ |
79 | | #define AARCH64_FEATURE_V8_5A (1ULL << 37) /* ARMv8.5 processors. */ |
80 | | #define AARCH64_FEATURE_FLAGMANIP (1ULL << 38) /* v8.5 Flag Manipulation version 2. */ |
81 | | #define AARCH64_FEATURE_FRINTTS (1ULL << 39) /* FRINT[32,64][Z,X] insns. */ |
82 | | #define AARCH64_FEATURE_SB (1ULL << 40) /* SB instruction. */ |
83 | | #define AARCH64_FEATURE_PREDRES (1ULL << 41) /* Execution and Data Prediction Restriction instructions. */ |
84 | | #define AARCH64_FEATURE_CVADP (1ULL << 42) /* DC CVADP. */ |
85 | | #define AARCH64_FEATURE_RNG (1ULL << 43) /* Random Number instructions. */ |
86 | | #define AARCH64_FEATURE_BTI (1ULL << 44) /* BTI instructions. */ |
87 | | #define AARCH64_FEATURE_SCXTNUM (1ULL << 45) /* SCXTNUM_ELx. */ |
88 | | #define AARCH64_FEATURE_ID_PFR2 (1ULL << 46) /* ID_PFR2 instructions. */ |
89 | | #define AARCH64_FEATURE_SSBS (1ULL << 47) /* SSBS mechanism enabled. */ |
90 | | #define AARCH64_FEATURE_MEMTAG (1ULL << 48) /* Memory Tagging Extension. */ |
91 | | #define AARCH64_FEATURE_TME (1ULL << 49) /* Transactional Memory Extension. */ |
92 | | #define AARCH64_FEATURE_MOPS (1ULL << 50) /* Standardization of memory operations. */ |
93 | | #define AARCH64_FEATURE_HBC (1ULL << 51) /* Hinted conditional branches. */ |
94 | | #define AARCH64_FEATURE_I8MM (1ULL << 52) /* Matrix Multiply instructions. */ |
95 | | #define AARCH64_FEATURE_F32MM (1ULL << 53) |
96 | | #define AARCH64_FEATURE_F64MM (1ULL << 54) |
97 | | #define AARCH64_FEATURE_FLAGM (1ULL << 55) /* v8.4 Flag Manipulation. */ |
98 | | #define AARCH64_FEATURE_V9A (1ULL << 56) /* Armv9.0-A processors. */ |
99 | | #define AARCH64_FEATURE_SME_F64F64 (1ULL << 57) /* SME F64F64. */ |
100 | | #define AARCH64_FEATURE_SME_I16I64 (1ULL << 58) /* SME I16I64. */ |
101 | | #define AARCH64_FEATURE_V8_8A (1ULL << 59) /* Armv8.8 processors. */ |
102 | | #define AARCH64_FEATURE_CSSC (1ULL << 60) /* Common Short Sequence Compression instructions. */ |
103 | | #define AARCH64_FEATURE_SME2 (1ULL << 61) /* SME2. */ |
104 | | |
105 | | /* Crypto instructions are the combination of AES and SHA2. */ |
106 | | #define AARCH64_FEATURE_CRYPTO (AARCH64_FEATURE_SHA2 | AARCH64_FEATURE_AES) |
107 | | |
108 | | #define AARCH64_ARCH_V8A_FEATURES (AARCH64_FEATURE_V8A \ |
109 | | | AARCH64_FEATURE_FP \ |
110 | | | AARCH64_FEATURE_RAS \ |
111 | | | AARCH64_FEATURE_SIMD) |
112 | | #define AARCH64_ARCH_V8_1A_FEATURES (AARCH64_FEATURE_V8_1A \ |
113 | | | AARCH64_FEATURE_CRC \ |
114 | | | AARCH64_FEATURE_LSE \ |
115 | | | AARCH64_FEATURE_PAN \ |
116 | | | AARCH64_FEATURE_LOR \ |
117 | | | AARCH64_FEATURE_RDMA) |
118 | | #define AARCH64_ARCH_V8_2A_FEATURES (AARCH64_FEATURE_V8_2A) |
119 | | #define AARCH64_ARCH_V8_3A_FEATURES (AARCH64_FEATURE_V8_3A \ |
120 | | | AARCH64_FEATURE_PAC \ |
121 | | | AARCH64_FEATURE_RCPC \ |
122 | | | AARCH64_FEATURE_COMPNUM) |
123 | | #define AARCH64_ARCH_V8_4A_FEATURES (AARCH64_FEATURE_V8_4A \ |
124 | | | AARCH64_FEATURE_DOTPROD \ |
125 | | | AARCH64_FEATURE_FLAGM \ |
126 | | | AARCH64_FEATURE_F16_FML) |
127 | | #define AARCH64_ARCH_V8_5A_FEATURES (AARCH64_FEATURE_V8_5A \ |
128 | | | AARCH64_FEATURE_FLAGMANIP \ |
129 | | | AARCH64_FEATURE_FRINTTS \ |
130 | | | AARCH64_FEATURE_SB \ |
131 | | | AARCH64_FEATURE_PREDRES \ |
132 | | | AARCH64_FEATURE_CVADP \ |
133 | | | AARCH64_FEATURE_BTI \ |
134 | | | AARCH64_FEATURE_SCXTNUM \ |
135 | | | AARCH64_FEATURE_ID_PFR2 \ |
136 | | | AARCH64_FEATURE_SSBS) |
137 | | #define AARCH64_ARCH_V8_6A_FEATURES (AARCH64_FEATURE_V8_6A \ |
138 | | | AARCH64_FEATURE_BFLOAT16 \ |
139 | | | AARCH64_FEATURE_I8MM) |
140 | | #define AARCH64_ARCH_V8_7A_FEATURES (AARCH64_FEATURE_V8_7A \ |
141 | | | AARCH64_FEATURE_LS64) |
142 | | #define AARCH64_ARCH_V8_8A_FEATURES (AARCH64_FEATURE_V8_8A \ |
143 | | | AARCH64_FEATURE_MOPS \ |
144 | | | AARCH64_FEATURE_HBC) |
145 | | |
146 | | #define AARCH64_ARCH_V9A_FEATURES (AARCH64_FEATURE_V9A \ |
147 | | | AARCH64_FEATURE_F16 \ |
148 | | | AARCH64_FEATURE_SVE \ |
149 | | | AARCH64_FEATURE_SVE2) |
150 | | #define AARCH64_ARCH_V9_1A_FEATURES (AARCH64_ARCH_V8_6A_FEATURES) |
151 | | #define AARCH64_ARCH_V9_2A_FEATURES (AARCH64_ARCH_V8_7A_FEATURES) |
152 | | #define AARCH64_ARCH_V9_3A_FEATURES (AARCH64_ARCH_V8_8A_FEATURES) |
153 | | |
154 | | /* Architectures are the sum of the base and extensions. */ |
155 | | #define AARCH64_ARCH_V8A AARCH64_FEATURE (AARCH64_FEATURE_V8, \ |
156 | | AARCH64_ARCH_V8A_FEATURES) |
157 | | #define AARCH64_ARCH_V8_1A AARCH64_FEATURE (AARCH64_ARCH_V8A, \ |
158 | | AARCH64_ARCH_V8_1A_FEATURES) |
159 | | #define AARCH64_ARCH_V8_2A AARCH64_FEATURE (AARCH64_ARCH_V8_1A, \ |
160 | | AARCH64_ARCH_V8_2A_FEATURES) |
161 | | #define AARCH64_ARCH_V8_3A AARCH64_FEATURE (AARCH64_ARCH_V8_2A, \ |
162 | | AARCH64_ARCH_V8_3A_FEATURES) |
163 | | #define AARCH64_ARCH_V8_4A AARCH64_FEATURE (AARCH64_ARCH_V8_3A, \ |
164 | | AARCH64_ARCH_V8_4A_FEATURES) |
165 | | #define AARCH64_ARCH_V8_5A AARCH64_FEATURE (AARCH64_ARCH_V8_4A, \ |
166 | | AARCH64_ARCH_V8_5A_FEATURES) |
167 | | #define AARCH64_ARCH_V8_6A AARCH64_FEATURE (AARCH64_ARCH_V8_5A, \ |
168 | | AARCH64_ARCH_V8_6A_FEATURES) |
169 | | #define AARCH64_ARCH_V8_7A AARCH64_FEATURE (AARCH64_ARCH_V8_6A, \ |
170 | | AARCH64_ARCH_V8_7A_FEATURES) |
171 | | #define AARCH64_ARCH_V8_8A AARCH64_FEATURE (AARCH64_ARCH_V8_7A, \ |
172 | | AARCH64_ARCH_V8_8A_FEATURES) |
173 | 0 | #define AARCH64_ARCH_V8R (AARCH64_FEATURE (AARCH64_ARCH_V8_4A, \ |
174 | 0 | AARCH64_FEATURE_V8R) \ |
175 | 0 | & ~(AARCH64_FEATURE_V8A | AARCH64_FEATURE_LOR)) |
176 | | |
177 | | #define AARCH64_ARCH_V9A AARCH64_FEATURE (AARCH64_ARCH_V8_5A, \ |
178 | | AARCH64_ARCH_V9A_FEATURES) |
179 | | #define AARCH64_ARCH_V9_1A AARCH64_FEATURE (AARCH64_ARCH_V9A, \ |
180 | | AARCH64_ARCH_V9_1A_FEATURES) |
181 | | #define AARCH64_ARCH_V9_2A AARCH64_FEATURE (AARCH64_ARCH_V9_1A, \ |
182 | | AARCH64_ARCH_V9_2A_FEATURES) |
183 | | #define AARCH64_ARCH_V9_3A AARCH64_FEATURE (AARCH64_ARCH_V9_2A, \ |
184 | | AARCH64_ARCH_V9_3A_FEATURES) |
185 | | |
186 | | #define AARCH64_ARCH_NONE AARCH64_FEATURE (0, 0) |
187 | 2 | #define AARCH64_ANY AARCH64_FEATURE (-1, 0) /* Any basic core. */ |
188 | | |
189 | | /* CPU-specific features. */ |
190 | | typedef unsigned long long aarch64_feature_set; |
191 | | |
192 | | #define AARCH64_CPU_HAS_ALL_FEATURES(CPU,FEAT) \ |
193 | 19.0M | ((~(CPU) & (FEAT)) == 0) |
194 | | |
195 | | #define AARCH64_CPU_HAS_ANY_FEATURES(CPU,FEAT) \ |
196 | | (((CPU) & (FEAT)) != 0) |
197 | | |
198 | | #define AARCH64_CPU_HAS_FEATURE(CPU,FEAT) \ |
199 | 9.48M | AARCH64_CPU_HAS_ALL_FEATURES (CPU,FEAT) |
200 | | |
201 | | #define AARCH64_MERGE_FEATURE_SETS(TARG,F1,F2) \ |
202 | | do \ |
203 | | { \ |
204 | | (TARG) = (F1) | (F2); \ |
205 | | } \ |
206 | | while (0) |
207 | | |
208 | | #define AARCH64_CLEAR_FEATURE(TARG,F1,F2) \ |
209 | | do \ |
210 | | { \ |
211 | | (TARG) = (F1) &~ (F2); \ |
212 | | } \ |
213 | | while (0) |
214 | | |
215 | 2 | #define AARCH64_FEATURE(core,coproc) ((core) | (coproc)) |
216 | | |
217 | | enum aarch64_operand_class |
218 | | { |
219 | | AARCH64_OPND_CLASS_NIL, |
220 | | AARCH64_OPND_CLASS_INT_REG, |
221 | | AARCH64_OPND_CLASS_MODIFIED_REG, |
222 | | AARCH64_OPND_CLASS_FP_REG, |
223 | | AARCH64_OPND_CLASS_SIMD_REG, |
224 | | AARCH64_OPND_CLASS_SIMD_ELEMENT, |
225 | | AARCH64_OPND_CLASS_SISD_REG, |
226 | | AARCH64_OPND_CLASS_SIMD_REGLIST, |
227 | | AARCH64_OPND_CLASS_SVE_REG, |
228 | | AARCH64_OPND_CLASS_SVE_REGLIST, |
229 | | AARCH64_OPND_CLASS_PRED_REG, |
230 | | AARCH64_OPND_CLASS_ZA_ACCESS, |
231 | | AARCH64_OPND_CLASS_ADDRESS, |
232 | | AARCH64_OPND_CLASS_IMMEDIATE, |
233 | | AARCH64_OPND_CLASS_SYSTEM, |
234 | | AARCH64_OPND_CLASS_COND, |
235 | | }; |
236 | | |
237 | | /* Operand code that helps both parsing and coding. |
238 | | Keep AARCH64_OPERANDS synced. */ |
239 | | |
240 | | enum aarch64_opnd |
241 | | { |
242 | | AARCH64_OPND_NIL, /* no operand---MUST BE FIRST!*/ |
243 | | |
244 | | AARCH64_OPND_Rd, /* Integer register as destination. */ |
245 | | AARCH64_OPND_Rn, /* Integer register as source. */ |
246 | | AARCH64_OPND_Rm, /* Integer register as source. */ |
247 | | AARCH64_OPND_Rt, /* Integer register used in ld/st instructions. */ |
248 | | AARCH64_OPND_Rt2, /* Integer register used in ld/st pair instructions. */ |
249 | | AARCH64_OPND_Rt_LS64, /* Integer register used in LS64 instructions. */ |
250 | | AARCH64_OPND_Rt_SP, /* Integer Rt or SP used in STG instructions. */ |
251 | | AARCH64_OPND_Rs, /* Integer register used in ld/st exclusive. */ |
252 | | AARCH64_OPND_Ra, /* Integer register used in ddp_3src instructions. */ |
253 | | AARCH64_OPND_Rt_SYS, /* Integer register used in system instructions. */ |
254 | | |
255 | | AARCH64_OPND_Rd_SP, /* Integer Rd or SP. */ |
256 | | AARCH64_OPND_Rn_SP, /* Integer Rn or SP. */ |
257 | | AARCH64_OPND_Rm_SP, /* Integer Rm or SP. */ |
258 | | AARCH64_OPND_PAIRREG, /* Paired register operand. */ |
259 | | AARCH64_OPND_Rm_EXT, /* Integer Rm extended. */ |
260 | | AARCH64_OPND_Rm_SFT, /* Integer Rm shifted. */ |
261 | | |
262 | | AARCH64_OPND_Fd, /* Floating-point Fd. */ |
263 | | AARCH64_OPND_Fn, /* Floating-point Fn. */ |
264 | | AARCH64_OPND_Fm, /* Floating-point Fm. */ |
265 | | AARCH64_OPND_Fa, /* Floating-point Fa. */ |
266 | | AARCH64_OPND_Ft, /* Floating-point Ft. */ |
267 | | AARCH64_OPND_Ft2, /* Floating-point Ft2. */ |
268 | | |
269 | | AARCH64_OPND_Sd, /* AdvSIMD Scalar Sd. */ |
270 | | AARCH64_OPND_Sn, /* AdvSIMD Scalar Sn. */ |
271 | | AARCH64_OPND_Sm, /* AdvSIMD Scalar Sm. */ |
272 | | |
273 | | AARCH64_OPND_Va, /* AdvSIMD Vector Va. */ |
274 | | AARCH64_OPND_Vd, /* AdvSIMD Vector Vd. */ |
275 | | AARCH64_OPND_Vn, /* AdvSIMD Vector Vn. */ |
276 | | AARCH64_OPND_Vm, /* AdvSIMD Vector Vm. */ |
277 | | AARCH64_OPND_VdD1, /* AdvSIMD <Vd>.D[1]; for FMOV only. */ |
278 | | AARCH64_OPND_VnD1, /* AdvSIMD <Vn>.D[1]; for FMOV only. */ |
279 | | AARCH64_OPND_Ed, /* AdvSIMD Vector Element Vd. */ |
280 | | AARCH64_OPND_En, /* AdvSIMD Vector Element Vn. */ |
281 | | AARCH64_OPND_Em, /* AdvSIMD Vector Element Vm. */ |
282 | | AARCH64_OPND_Em16, /* AdvSIMD Vector Element Vm restricted to V0 - V15 when |
283 | | qualifier is S_H. */ |
284 | | AARCH64_OPND_LVn, /* AdvSIMD Vector register list used in e.g. TBL. */ |
285 | | AARCH64_OPND_LVt, /* AdvSIMD Vector register list used in ld/st. */ |
286 | | AARCH64_OPND_LVt_AL, /* AdvSIMD Vector register list for loading single |
287 | | structure to all lanes. */ |
288 | | AARCH64_OPND_LEt, /* AdvSIMD Vector Element list. */ |
289 | | |
290 | | AARCH64_OPND_CRn, /* Co-processor register in CRn field. */ |
291 | | AARCH64_OPND_CRm, /* Co-processor register in CRm field. */ |
292 | | |
293 | | AARCH64_OPND_IDX, /* AdvSIMD EXT index operand. */ |
294 | | AARCH64_OPND_MASK, /* AdvSIMD EXT index operand. */ |
295 | | AARCH64_OPND_IMM_VLSL,/* Immediate for shifting vector registers left. */ |
296 | | AARCH64_OPND_IMM_VLSR,/* Immediate for shifting vector registers right. */ |
297 | | AARCH64_OPND_SIMD_IMM,/* AdvSIMD modified immediate without shift. */ |
298 | | AARCH64_OPND_SIMD_IMM_SFT, /* AdvSIMD modified immediate with shift. */ |
299 | | AARCH64_OPND_SIMD_FPIMM,/* AdvSIMD 8-bit fp immediate. */ |
300 | | AARCH64_OPND_SHLL_IMM,/* Immediate shift for AdvSIMD SHLL instruction |
301 | | (no encoding). */ |
302 | | AARCH64_OPND_IMM0, /* Immediate for #0. */ |
303 | | AARCH64_OPND_FPIMM0, /* Immediate for #0.0. */ |
304 | | AARCH64_OPND_FPIMM, /* Floating-point Immediate. */ |
305 | | AARCH64_OPND_IMMR, /* Immediate #<immr> in e.g. BFM. */ |
306 | | AARCH64_OPND_IMMS, /* Immediate #<imms> in e.g. BFM. */ |
307 | | AARCH64_OPND_WIDTH, /* Immediate #<width> in e.g. BFI. */ |
308 | | AARCH64_OPND_IMM, /* Immediate. */ |
309 | | AARCH64_OPND_IMM_2, /* Immediate. */ |
310 | | AARCH64_OPND_UIMM3_OP1,/* Unsigned 3-bit immediate in the op1 field. */ |
311 | | AARCH64_OPND_UIMM3_OP2,/* Unsigned 3-bit immediate in the op2 field. */ |
312 | | AARCH64_OPND_UIMM4, /* Unsigned 4-bit immediate in the CRm field. */ |
313 | | AARCH64_OPND_UIMM4_ADDG,/* Unsigned 4-bit immediate in addg/subg. */ |
314 | | AARCH64_OPND_UIMM7, /* Unsigned 7-bit immediate in the CRm:op2 fields. */ |
315 | | AARCH64_OPND_UIMM10, /* Unsigned 10-bit immediate in addg/subg. */ |
316 | | AARCH64_OPND_BIT_NUM, /* Immediate. */ |
317 | | AARCH64_OPND_EXCEPTION,/* imm16 operand in exception instructions. */ |
318 | | AARCH64_OPND_UNDEFINED,/* imm16 operand in undefined instruction. */ |
319 | | AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions. */ |
320 | | AARCH64_OPND_SIMM5, /* 5-bit signed immediate in the imm5 field. */ |
321 | | AARCH64_OPND_NZCV, /* Flag bit specifier giving an alternative value for |
322 | | each condition flag. */ |
323 | | |
324 | | AARCH64_OPND_LIMM, /* Logical Immediate. */ |
325 | | AARCH64_OPND_AIMM, /* Arithmetic immediate. */ |
326 | | AARCH64_OPND_HALF, /* #<imm16>{, LSL #<shift>} operand in move wide. */ |
327 | | AARCH64_OPND_FBITS, /* FP #<fbits> operand in e.g. SCVTF */ |
328 | | AARCH64_OPND_IMM_MOV, /* Immediate operand for the MOV alias. */ |
329 | | AARCH64_OPND_IMM_ROT1, /* Immediate rotate operand for FCMLA. */ |
330 | | AARCH64_OPND_IMM_ROT2, /* Immediate rotate operand for indexed FCMLA. */ |
331 | | AARCH64_OPND_IMM_ROT3, /* Immediate rotate operand for FCADD. */ |
332 | | |
333 | | AARCH64_OPND_COND, /* Standard condition as the last operand. */ |
334 | | AARCH64_OPND_COND1, /* Same as the above, but excluding AL and NV. */ |
335 | | |
336 | | AARCH64_OPND_ADDR_ADRP, /* Memory address for ADRP */ |
337 | | AARCH64_OPND_ADDR_PCREL14, /* 14-bit PC-relative address for e.g. TBZ. */ |
338 | | AARCH64_OPND_ADDR_PCREL19, /* 19-bit PC-relative address for e.g. LDR. */ |
339 | | AARCH64_OPND_ADDR_PCREL21, /* 21-bit PC-relative address for e.g. ADR. */ |
340 | | AARCH64_OPND_ADDR_PCREL26, /* 26-bit PC-relative address for e.g. BL. */ |
341 | | |
342 | | AARCH64_OPND_ADDR_SIMPLE, /* Address of ld/st exclusive. */ |
343 | | AARCH64_OPND_ADDR_REGOFF, /* Address of register offset. */ |
344 | | AARCH64_OPND_ADDR_SIMM7, /* Address of signed 7-bit immediate. */ |
345 | | AARCH64_OPND_ADDR_SIMM9, /* Address of signed 9-bit immediate. */ |
346 | | AARCH64_OPND_ADDR_SIMM9_2, /* Same as the above, but the immediate is |
347 | | negative or unaligned and there is |
348 | | no writeback allowed. This operand code |
349 | | is only used to support the programmer- |
350 | | friendly feature of using LDR/STR as the |
351 | | the mnemonic name for LDUR/STUR instructions |
352 | | wherever there is no ambiguity. */ |
353 | | AARCH64_OPND_ADDR_SIMM10, /* Address of signed 10-bit immediate. */ |
354 | | AARCH64_OPND_ADDR_SIMM11, /* Address with a signed 11-bit (multiple of |
355 | | 16) immediate. */ |
356 | | AARCH64_OPND_ADDR_UIMM12, /* Address of unsigned 12-bit immediate. */ |
357 | | AARCH64_OPND_ADDR_SIMM13, /* Address with a signed 13-bit (multiple of |
358 | | 16) immediate. */ |
359 | | AARCH64_OPND_SIMD_ADDR_SIMPLE,/* Address of ld/st multiple structures. */ |
360 | | AARCH64_OPND_ADDR_OFFSET, /* Address with an optional 9-bit immediate. */ |
361 | | AARCH64_OPND_SIMD_ADDR_POST, /* Address of ld/st multiple post-indexed. */ |
362 | | |
363 | | AARCH64_OPND_SYSREG, /* System register operand. */ |
364 | | AARCH64_OPND_PSTATEFIELD, /* PSTATE field name operand. */ |
365 | | AARCH64_OPND_SYSREG_AT, /* System register <at_op> operand. */ |
366 | | AARCH64_OPND_SYSREG_DC, /* System register <dc_op> operand. */ |
367 | | AARCH64_OPND_SYSREG_IC, /* System register <ic_op> operand. */ |
368 | | AARCH64_OPND_SYSREG_TLBI, /* System register <tlbi_op> operand. */ |
369 | | AARCH64_OPND_SYSREG_SR, /* System register RCTX operand. */ |
370 | | AARCH64_OPND_BARRIER, /* Barrier operand. */ |
371 | | AARCH64_OPND_BARRIER_DSB_NXS, /* Barrier operand for DSB nXS variant. */ |
372 | | AARCH64_OPND_BARRIER_ISB, /* Barrier operand for ISB. */ |
373 | | AARCH64_OPND_PRFOP, /* Prefetch operation. */ |
374 | | AARCH64_OPND_RPRFMOP, /* Range prefetch operation. */ |
375 | | AARCH64_OPND_BARRIER_PSB, /* Barrier operand for PSB. */ |
376 | | AARCH64_OPND_BTI_TARGET, /* BTI {<target>}. */ |
377 | | AARCH64_OPND_SVE_ADDR_RI_S4x16, /* SVE [<Xn|SP>, #<simm4>*16]. */ |
378 | | AARCH64_OPND_SVE_ADDR_RI_S4x32, /* SVE [<Xn|SP>, #<simm4>*32]. */ |
379 | | AARCH64_OPND_SVE_ADDR_RI_S4xVL, /* SVE [<Xn|SP>, #<simm4>, MUL VL]. */ |
380 | | AARCH64_OPND_SVE_ADDR_RI_S4x2xVL, /* SVE [<Xn|SP>, #<simm4>*2, MUL VL]. */ |
381 | | AARCH64_OPND_SVE_ADDR_RI_S4x3xVL, /* SVE [<Xn|SP>, #<simm4>*3, MUL VL]. */ |
382 | | AARCH64_OPND_SVE_ADDR_RI_S4x4xVL, /* SVE [<Xn|SP>, #<simm4>*4, MUL VL]. */ |
383 | | AARCH64_OPND_SVE_ADDR_RI_S6xVL, /* SVE [<Xn|SP>, #<simm6>, MUL VL]. */ |
384 | | AARCH64_OPND_SVE_ADDR_RI_S9xVL, /* SVE [<Xn|SP>, #<simm9>, MUL VL]. */ |
385 | | AARCH64_OPND_SVE_ADDR_RI_U6, /* SVE [<Xn|SP>, #<uimm6>]. */ |
386 | | AARCH64_OPND_SVE_ADDR_RI_U6x2, /* SVE [<Xn|SP>, #<uimm6>*2]. */ |
387 | | AARCH64_OPND_SVE_ADDR_RI_U6x4, /* SVE [<Xn|SP>, #<uimm6>*4]. */ |
388 | | AARCH64_OPND_SVE_ADDR_RI_U6x8, /* SVE [<Xn|SP>, #<uimm6>*8]. */ |
389 | | AARCH64_OPND_SVE_ADDR_R, /* SVE [<Xn|SP>]. */ |
390 | | AARCH64_OPND_SVE_ADDR_RR, /* SVE [<Xn|SP>, <Xm|XZR>]. */ |
391 | | AARCH64_OPND_SVE_ADDR_RR_LSL1, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #1]. */ |
392 | | AARCH64_OPND_SVE_ADDR_RR_LSL2, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #2]. */ |
393 | | AARCH64_OPND_SVE_ADDR_RR_LSL3, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #3]. */ |
394 | | AARCH64_OPND_SVE_ADDR_RR_LSL4, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #4]. */ |
395 | | AARCH64_OPND_SVE_ADDR_RX, /* SVE [<Xn|SP>, <Xm>]. */ |
396 | | AARCH64_OPND_SVE_ADDR_RX_LSL1, /* SVE [<Xn|SP>, <Xm>, LSL #1]. */ |
397 | | AARCH64_OPND_SVE_ADDR_RX_LSL2, /* SVE [<Xn|SP>, <Xm>, LSL #2]. */ |
398 | | AARCH64_OPND_SVE_ADDR_RX_LSL3, /* SVE [<Xn|SP>, <Xm>, LSL #3]. */ |
399 | | AARCH64_OPND_SVE_ADDR_ZX, /* SVE [Zn.<T>{, <Xm>}]. */ |
400 | | AARCH64_OPND_SVE_ADDR_RZ, /* SVE [<Xn|SP>, Zm.D]. */ |
401 | | AARCH64_OPND_SVE_ADDR_RZ_LSL1, /* SVE [<Xn|SP>, Zm.D, LSL #1]. */ |
402 | | AARCH64_OPND_SVE_ADDR_RZ_LSL2, /* SVE [<Xn|SP>, Zm.D, LSL #2]. */ |
403 | | AARCH64_OPND_SVE_ADDR_RZ_LSL3, /* SVE [<Xn|SP>, Zm.D, LSL #3]. */ |
404 | | AARCH64_OPND_SVE_ADDR_RZ_XTW_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW]. |
405 | | Bit 14 controls S/U choice. */ |
406 | | AARCH64_OPND_SVE_ADDR_RZ_XTW_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW]. |
407 | | Bit 22 controls S/U choice. */ |
408 | | AARCH64_OPND_SVE_ADDR_RZ_XTW1_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1]. |
409 | | Bit 14 controls S/U choice. */ |
410 | | AARCH64_OPND_SVE_ADDR_RZ_XTW1_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1]. |
411 | | Bit 22 controls S/U choice. */ |
412 | | AARCH64_OPND_SVE_ADDR_RZ_XTW2_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2]. |
413 | | Bit 14 controls S/U choice. */ |
414 | | AARCH64_OPND_SVE_ADDR_RZ_XTW2_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2]. |
415 | | Bit 22 controls S/U choice. */ |
416 | | AARCH64_OPND_SVE_ADDR_RZ_XTW3_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3]. |
417 | | Bit 14 controls S/U choice. */ |
418 | | AARCH64_OPND_SVE_ADDR_RZ_XTW3_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3]. |
419 | | Bit 22 controls S/U choice. */ |
420 | | AARCH64_OPND_SVE_ADDR_ZI_U5, /* SVE [Zn.<T>, #<uimm5>]. */ |
421 | | AARCH64_OPND_SVE_ADDR_ZI_U5x2, /* SVE [Zn.<T>, #<uimm5>*2]. */ |
422 | | AARCH64_OPND_SVE_ADDR_ZI_U5x4, /* SVE [Zn.<T>, #<uimm5>*4]. */ |
423 | | AARCH64_OPND_SVE_ADDR_ZI_U5x8, /* SVE [Zn.<T>, #<uimm5>*8]. */ |
424 | | AARCH64_OPND_SVE_ADDR_ZZ_LSL, /* SVE [Zn.<T>, Zm,<T>, LSL #<msz>]. */ |
425 | | AARCH64_OPND_SVE_ADDR_ZZ_SXTW, /* SVE [Zn.<T>, Zm,<T>, SXTW #<msz>]. */ |
426 | | AARCH64_OPND_SVE_ADDR_ZZ_UXTW, /* SVE [Zn.<T>, Zm,<T>, UXTW #<msz>]. */ |
427 | | AARCH64_OPND_SVE_AIMM, /* SVE unsigned arithmetic immediate. */ |
428 | | AARCH64_OPND_SVE_ASIMM, /* SVE signed arithmetic immediate. */ |
429 | | AARCH64_OPND_SVE_FPIMM8, /* SVE 8-bit floating-point immediate. */ |
430 | | AARCH64_OPND_SVE_I1_HALF_ONE, /* SVE choice between 0.5 and 1.0. */ |
431 | | AARCH64_OPND_SVE_I1_HALF_TWO, /* SVE choice between 0.5 and 2.0. */ |
432 | | AARCH64_OPND_SVE_I1_ZERO_ONE, /* SVE choice between 0.0 and 1.0. */ |
433 | | AARCH64_OPND_SVE_IMM_ROT1, /* SVE 1-bit rotate operand (90 or 270). */ |
434 | | AARCH64_OPND_SVE_IMM_ROT2, /* SVE 2-bit rotate operand (N*90). */ |
435 | | AARCH64_OPND_SVE_IMM_ROT3, /* SVE cadd 1-bit rotate (90 or 270). */ |
436 | | AARCH64_OPND_SVE_INV_LIMM, /* SVE inverted logical immediate. */ |
437 | | AARCH64_OPND_SVE_LIMM, /* SVE logical immediate. */ |
438 | | AARCH64_OPND_SVE_LIMM_MOV, /* SVE logical immediate for MOV. */ |
439 | | AARCH64_OPND_SVE_PATTERN, /* SVE vector pattern enumeration. */ |
440 | | AARCH64_OPND_SVE_PATTERN_SCALED, /* Likewise, with additional MUL factor. */ |
441 | | AARCH64_OPND_SVE_PRFOP, /* SVE prefetch operation. */ |
442 | | AARCH64_OPND_SVE_Pd, /* SVE p0-p15 in Pd. */ |
443 | | AARCH64_OPND_SVE_PNd, /* SVE pn0-pn15 in Pd. */ |
444 | | AARCH64_OPND_SVE_Pg3, /* SVE p0-p7 in Pg. */ |
445 | | AARCH64_OPND_SVE_Pg4_5, /* SVE p0-p15 in Pg, bits [8,5]. */ |
446 | | AARCH64_OPND_SVE_Pg4_10, /* SVE p0-p15 in Pg, bits [13,10]. */ |
447 | | AARCH64_OPND_SVE_PNg4_10, /* SVE pn0-pn15 in Pg, bits [13,10]. */ |
448 | | AARCH64_OPND_SVE_Pg4_16, /* SVE p0-p15 in Pg, bits [19,16]. */ |
449 | | AARCH64_OPND_SVE_Pm, /* SVE p0-p15 in Pm. */ |
450 | | AARCH64_OPND_SVE_Pn, /* SVE p0-p15 in Pn. */ |
451 | | AARCH64_OPND_SVE_PNn, /* SVE pn0-pn15 in Pn. */ |
452 | | AARCH64_OPND_SVE_Pt, /* SVE p0-p15 in Pt. */ |
453 | | AARCH64_OPND_SVE_PNt, /* SVE pn0-pn15 in Pt. */ |
454 | | AARCH64_OPND_SVE_Rm, /* Integer Rm or ZR, alt. SVE position. */ |
455 | | AARCH64_OPND_SVE_Rn_SP, /* Integer Rn or SP, alt. SVE position. */ |
456 | | AARCH64_OPND_SVE_SHLIMM_PRED, /* SVE shift left amount (predicated). */ |
457 | | AARCH64_OPND_SVE_SHLIMM_UNPRED, /* SVE shift left amount (unpredicated). */ |
458 | | AARCH64_OPND_SVE_SHLIMM_UNPRED_22, /* SVE 3 bit shift left unpred. */ |
459 | | AARCH64_OPND_SVE_SHRIMM_PRED, /* SVE shift right amount (predicated). */ |
460 | | AARCH64_OPND_SVE_SHRIMM_UNPRED, /* SVE shift right amount (unpredicated). */ |
461 | | AARCH64_OPND_SVE_SHRIMM_UNPRED_22, /* SVE 3 bit shift right unpred. */ |
462 | | AARCH64_OPND_SVE_SIMM5, /* SVE signed 5-bit immediate. */ |
463 | | AARCH64_OPND_SVE_SIMM5B, /* SVE secondary signed 5-bit immediate. */ |
464 | | AARCH64_OPND_SVE_SIMM6, /* SVE signed 6-bit immediate. */ |
465 | | AARCH64_OPND_SVE_SIMM8, /* SVE signed 8-bit immediate. */ |
466 | | AARCH64_OPND_SVE_UIMM3, /* SVE unsigned 3-bit immediate. */ |
467 | | AARCH64_OPND_SVE_UIMM7, /* SVE unsigned 7-bit immediate. */ |
468 | | AARCH64_OPND_SVE_UIMM8, /* SVE unsigned 8-bit immediate. */ |
469 | | AARCH64_OPND_SVE_UIMM8_53, /* SVE split unsigned 8-bit immediate. */ |
470 | | AARCH64_OPND_SVE_VZn, /* Scalar SIMD&FP register in Zn field. */ |
471 | | AARCH64_OPND_SVE_Vd, /* Scalar SIMD&FP register in Vd. */ |
472 | | AARCH64_OPND_SVE_Vm, /* Scalar SIMD&FP register in Vm. */ |
473 | | AARCH64_OPND_SVE_Vn, /* Scalar SIMD&FP register in Vn. */ |
474 | | AARCH64_OPND_SVE_Za_5, /* SVE vector register in Za, bits [9,5]. */ |
475 | | AARCH64_OPND_SVE_Za_16, /* SVE vector register in Za, bits [20,16]. */ |
476 | | AARCH64_OPND_SVE_Zd, /* SVE vector register in Zd. */ |
477 | | AARCH64_OPND_SVE_Zm_5, /* SVE vector register in Zm, bits [9,5]. */ |
478 | | AARCH64_OPND_SVE_Zm_16, /* SVE vector register in Zm, bits [20,16]. */ |
479 | | AARCH64_OPND_SVE_Zm3_INDEX, /* z0-z7[0-3] in Zm, bits [20,16]. */ |
480 | | AARCH64_OPND_SVE_Zm3_11_INDEX, /* z0-z7[0-7] in Zm3_INDEX plus bit 11. */ |
481 | | AARCH64_OPND_SVE_Zm3_19_INDEX, /* z0-z7[0-3] in Zm3_INDEX plus bit 19. */ |
482 | | AARCH64_OPND_SVE_Zm3_22_INDEX, /* z0-z7[0-7] in Zm3_INDEX plus bit 22. */ |
483 | | AARCH64_OPND_SVE_Zm4_11_INDEX, /* z0-z15[0-3] in Zm plus bit 11. */ |
484 | | AARCH64_OPND_SVE_Zm4_INDEX, /* z0-z15[0-1] in Zm, bits [20,16]. */ |
485 | | AARCH64_OPND_SVE_Zn, /* SVE vector register in Zn. */ |
486 | | AARCH64_OPND_SVE_Zn_INDEX, /* Indexed SVE vector register, for DUP. */ |
487 | | AARCH64_OPND_SVE_ZnxN, /* SVE vector register list in Zn. */ |
488 | | AARCH64_OPND_SVE_Zt, /* SVE vector register in Zt. */ |
489 | | AARCH64_OPND_SVE_ZtxN, /* SVE vector register list in Zt. */ |
490 | | AARCH64_OPND_SME_Zdnx2, /* SVE vector register list from [4:1]*2. */ |
491 | | AARCH64_OPND_SME_Zdnx4, /* SVE vector register list from [4:2]*4. */ |
492 | | AARCH64_OPND_SME_Zm, /* SVE vector register list in 4-bit Zm. */ |
493 | | AARCH64_OPND_SME_Zmx2, /* SVE vector register list from [20:17]*2. */ |
494 | | AARCH64_OPND_SME_Zmx4, /* SVE vector register list from [20:18]*4. */ |
495 | | AARCH64_OPND_SME_Znx2, /* SVE vector register list from [9:6]*2. */ |
496 | | AARCH64_OPND_SME_Znx4, /* SVE vector register list from [9:7]*4. */ |
497 | | AARCH64_OPND_SME_Ztx2_STRIDED, /* SVE vector register list in [4:0]&23. */ |
498 | | AARCH64_OPND_SME_Ztx4_STRIDED, /* SVE vector register list in [4:0]&19. */ |
499 | | AARCH64_OPND_SME_ZAda_2b, /* SME <ZAda>.S, 2-bits. */ |
500 | | AARCH64_OPND_SME_ZAda_3b, /* SME <ZAda>.D, 3-bits. */ |
501 | | AARCH64_OPND_SME_ZA_HV_idx_src, /* SME source ZA tile vector. */ |
502 | | AARCH64_OPND_SME_ZA_HV_idx_srcxN, /* SME N source ZA tile vectors. */ |
503 | | AARCH64_OPND_SME_ZA_HV_idx_dest, /* SME destination ZA tile vector. */ |
504 | | AARCH64_OPND_SME_ZA_HV_idx_destxN, /* SME N dest ZA tile vectors. */ |
505 | | AARCH64_OPND_SME_Pdx2, /* Predicate register list in [3:1]. */ |
506 | | AARCH64_OPND_SME_PdxN, /* Predicate register list in [3:0]. */ |
507 | | AARCH64_OPND_SME_Pm, /* SME scalable predicate register, bits [15:13]. */ |
508 | | AARCH64_OPND_SME_PNd3, /* Predicate-as-counter register, bits [3:0]. */ |
509 | | AARCH64_OPND_SME_PNg3, /* Predicate-as-counter register, bits [12:10]. */ |
510 | | AARCH64_OPND_SME_PNn, /* Predicate-as-counter register, bits [8:5]. */ |
511 | | AARCH64_OPND_SME_PNn3_INDEX1, /* Indexed pred-as-counter reg, bits [8:5]. */ |
512 | | AARCH64_OPND_SME_PNn3_INDEX2, /* Indexed pred-as-counter reg, bits [9:5]. */ |
513 | | AARCH64_OPND_SME_list_of_64bit_tiles, /* SME list of ZA tiles. */ |
514 | | AARCH64_OPND_SME_ZA_HV_idx_ldstr, /* SME destination ZA tile vector. */ |
515 | | AARCH64_OPND_SME_ZA_array_off1x4, /* SME ZA[<Wv>, #<imm1>*4:<imm1>*4+3]. */ |
516 | | AARCH64_OPND_SME_ZA_array_off2x2, /* SME ZA[<Wv>, #<imm2>*2:<imm2>*2+1]. */ |
517 | | AARCH64_OPND_SME_ZA_array_off2x4, /* SME ZA[<Wv>, #<imm2>*4:<imm2>*4+3]. */ |
518 | | AARCH64_OPND_SME_ZA_array_off3_0, /* SME ZA[<Wv>{, #<imm3>}]. */ |
519 | | AARCH64_OPND_SME_ZA_array_off3_5, /* SME ZA[<Wv>{, #<imm3>}]. */ |
520 | | AARCH64_OPND_SME_ZA_array_off3x2, /* SME ZA[<Wv>, #<imm3>*2:<imm3>*2+1]. */ |
521 | | AARCH64_OPND_SME_ZA_array_off4, /* SME ZA[<Wv>{, #<imm>}]. */ |
522 | | AARCH64_OPND_SME_ADDR_RI_U4xVL, /* SME [<Xn|SP>{, #<imm>, MUL VL}]. */ |
523 | | AARCH64_OPND_SME_SM_ZA, /* SME {SM | ZA}. */ |
524 | | AARCH64_OPND_SME_PnT_Wm_imm, /* SME <Pn>.<T>[<Wm>, #<imm>]. */ |
525 | | AARCH64_OPND_SME_SHRIMM4, /* 4-bit right shift, bits [19:16]. */ |
526 | | AARCH64_OPND_SME_SHRIMM5, /* size + 5-bit right shift, bits [23:22,20:16]. */ |
527 | | AARCH64_OPND_SME_Zm_INDEX1, /* Zn.T[index], bits [19:16,10]. */ |
528 | | AARCH64_OPND_SME_Zm_INDEX2, /* Zn.T[index], bits [19:16,11:10]. */ |
529 | | AARCH64_OPND_SME_Zm_INDEX3_1, /* Zn.T[index], bits [19:16,10,2:1]. */ |
530 | | AARCH64_OPND_SME_Zm_INDEX3_2, /* Zn.T[index], bits [19:16,11:10,2]. */ |
531 | | AARCH64_OPND_SME_Zm_INDEX3_10, /* Zn.T[index], bits [19:16,15,11:10]. */ |
532 | | AARCH64_OPND_SME_Zm_INDEX4_1, /* Zn.T[index], bits [19:16,11:10,2:1]. */ |
533 | | AARCH64_OPND_SME_Zm_INDEX4_10, /* Zn.T[index], bits [19:16,15,12:10]. */ |
534 | | AARCH64_OPND_SME_Zn_INDEX1_16, /* Zn[index], bits [9:5] and [16:16]. */ |
535 | | AARCH64_OPND_SME_Zn_INDEX2_15, /* Zn[index], bits [9:5] and [16:15]. */ |
536 | | AARCH64_OPND_SME_Zn_INDEX2_16, /* Zn[index], bits [9:5] and [17:16]. */ |
537 | | AARCH64_OPND_SME_Zn_INDEX3_14, /* Zn[index], bits [9:5] and [16:14]. */ |
538 | | AARCH64_OPND_SME_Zn_INDEX3_15, /* Zn[index], bits [9:5] and [17:15]. */ |
539 | | AARCH64_OPND_SME_Zn_INDEX4_14, /* Zn[index], bits [9:5] and [17:14]. */ |
540 | | AARCH64_OPND_SME_VLxN_10, /* VLx2 or VLx4, in bit 10. */ |
541 | | AARCH64_OPND_SME_VLxN_13, /* VLx2 or VLx4, in bit 13. */ |
542 | | AARCH64_OPND_SME_ZT0, /* The fixed token zt0/ZT0 (not encoded). */ |
543 | | AARCH64_OPND_SME_ZT0_INDEX, /* ZT0[<imm>], bits [14:12]. */ |
544 | | AARCH64_OPND_SME_ZT0_LIST, /* { zt0/ZT0 } (not encoded). */ |
545 | | AARCH64_OPND_TME_UIMM16, /* TME unsigned 16-bit immediate. */ |
546 | | AARCH64_OPND_SM3_IMM2, /* SM3 encodes lane in bits [13, 14]. */ |
547 | | AARCH64_OPND_MOPS_ADDR_Rd, /* [Rd]!, in bits [0, 4]. */ |
548 | | AARCH64_OPND_MOPS_ADDR_Rs, /* [Rs]!, in bits [16, 20]. */ |
549 | | AARCH64_OPND_MOPS_WB_Rn, /* Rn!, in bits [5, 9]. */ |
550 | | AARCH64_OPND_CSSC_SIMM8, /* CSSC signed 8-bit immediate. */ |
551 | | AARCH64_OPND_CSSC_UIMM8, /* CSSC unsigned 8-bit immediate. */ |
552 | | }; |
553 | | |
554 | | /* Qualifier constrains an operand. It either specifies a variant of an |
555 | | operand type or limits values available to an operand type. |
556 | | |
557 | | N.B. Order is important; keep aarch64_opnd_qualifiers synced. */ |
558 | | |
559 | | enum aarch64_opnd_qualifier |
560 | | { |
561 | | /* Indicating no further qualification on an operand. */ |
562 | | AARCH64_OPND_QLF_NIL, |
563 | | |
564 | | /* Qualifying an operand which is a general purpose (integer) register; |
565 | | indicating the operand data size or a specific register. */ |
566 | | AARCH64_OPND_QLF_W, /* Wn, WZR or WSP. */ |
567 | | AARCH64_OPND_QLF_X, /* Xn, XZR or XSP. */ |
568 | | AARCH64_OPND_QLF_WSP, /* WSP. */ |
569 | | AARCH64_OPND_QLF_SP, /* SP. */ |
570 | | |
571 | | /* Qualifying an operand which is a floating-point register, a SIMD |
572 | | vector element or a SIMD vector element list; indicating operand data |
573 | | size or the size of each SIMD vector element in the case of a SIMD |
574 | | vector element list. |
575 | | These qualifiers are also used to qualify an address operand to |
576 | | indicate the size of data element a load/store instruction is |
577 | | accessing. |
578 | | They are also used for the immediate shift operand in e.g. SSHR. Such |
579 | | a use is only for the ease of operand encoding/decoding and qualifier |
580 | | sequence matching; such a use should not be applied widely; use the value |
581 | | constraint qualifiers for immediate operands wherever possible. */ |
582 | | AARCH64_OPND_QLF_S_B, |
583 | | AARCH64_OPND_QLF_S_H, |
584 | | AARCH64_OPND_QLF_S_S, |
585 | | AARCH64_OPND_QLF_S_D, |
586 | | AARCH64_OPND_QLF_S_Q, |
587 | | /* These type qualifiers have a special meaning in that they mean 4 x 1 byte |
588 | | or 2 x 2 byte are selected by the instruction. Other than that they have |
589 | | no difference with AARCH64_OPND_QLF_S_B in encoding. They are here purely |
590 | | for syntactical reasons and is an exception from normal AArch64 |
591 | | disassembly scheme. */ |
592 | | AARCH64_OPND_QLF_S_4B, |
593 | | AARCH64_OPND_QLF_S_2H, |
594 | | |
595 | | /* Qualifying an operand which is a SIMD vector register or a SIMD vector |
596 | | register list; indicating register shape. |
597 | | They are also used for the immediate shift operand in e.g. SSHR. Such |
598 | | a use is only for the ease of operand encoding/decoding and qualifier |
599 | | sequence matching; such a use should not be applied widely; use the value |
600 | | constraint qualifiers for immediate operands wherever possible. */ |
601 | | AARCH64_OPND_QLF_V_4B, |
602 | | AARCH64_OPND_QLF_V_8B, |
603 | | AARCH64_OPND_QLF_V_16B, |
604 | | AARCH64_OPND_QLF_V_2H, |
605 | | AARCH64_OPND_QLF_V_4H, |
606 | | AARCH64_OPND_QLF_V_8H, |
607 | | AARCH64_OPND_QLF_V_2S, |
608 | | AARCH64_OPND_QLF_V_4S, |
609 | | AARCH64_OPND_QLF_V_1D, |
610 | | AARCH64_OPND_QLF_V_2D, |
611 | | AARCH64_OPND_QLF_V_1Q, |
612 | | |
613 | | AARCH64_OPND_QLF_P_Z, |
614 | | AARCH64_OPND_QLF_P_M, |
615 | | |
616 | | /* Used in scaled signed immediate that are scaled by a Tag granule |
617 | | like in stg, st2g, etc. */ |
618 | | AARCH64_OPND_QLF_imm_tag, |
619 | | |
620 | | /* Constraint on value. */ |
621 | | AARCH64_OPND_QLF_CR, /* CRn, CRm. */ |
622 | | AARCH64_OPND_QLF_imm_0_7, |
623 | | AARCH64_OPND_QLF_imm_0_15, |
624 | | AARCH64_OPND_QLF_imm_0_31, |
625 | | AARCH64_OPND_QLF_imm_0_63, |
626 | | AARCH64_OPND_QLF_imm_1_32, |
627 | | AARCH64_OPND_QLF_imm_1_64, |
628 | | |
629 | | /* Indicate whether an AdvSIMD modified immediate operand is shift-zeros |
630 | | or shift-ones. */ |
631 | | AARCH64_OPND_QLF_LSL, |
632 | | AARCH64_OPND_QLF_MSL, |
633 | | |
634 | | /* Special qualifier helping retrieve qualifier information during the |
635 | | decoding time (currently not in use). */ |
636 | | AARCH64_OPND_QLF_RETRIEVE, |
637 | | }; |
638 | | |
639 | | /* Instruction class. */ |
640 | | |
641 | | enum aarch64_insn_class |
642 | | { |
643 | | aarch64_misc, |
644 | | addsub_carry, |
645 | | addsub_ext, |
646 | | addsub_imm, |
647 | | addsub_shift, |
648 | | asimdall, |
649 | | asimddiff, |
650 | | asimdelem, |
651 | | asimdext, |
652 | | asimdimm, |
653 | | asimdins, |
654 | | asimdmisc, |
655 | | asimdperm, |
656 | | asimdsame, |
657 | | asimdshf, |
658 | | asimdtbl, |
659 | | asisddiff, |
660 | | asisdelem, |
661 | | asisdlse, |
662 | | asisdlsep, |
663 | | asisdlso, |
664 | | asisdlsop, |
665 | | asisdmisc, |
666 | | asisdone, |
667 | | asisdpair, |
668 | | asisdsame, |
669 | | asisdshf, |
670 | | bitfield, |
671 | | branch_imm, |
672 | | branch_reg, |
673 | | compbranch, |
674 | | condbranch, |
675 | | condcmp_imm, |
676 | | condcmp_reg, |
677 | | condsel, |
678 | | cryptoaes, |
679 | | cryptosha2, |
680 | | cryptosha3, |
681 | | dp_1src, |
682 | | dp_2src, |
683 | | dp_3src, |
684 | | exception, |
685 | | extract, |
686 | | float2fix, |
687 | | float2int, |
688 | | floatccmp, |
689 | | floatcmp, |
690 | | floatdp1, |
691 | | floatdp2, |
692 | | floatdp3, |
693 | | floatimm, |
694 | | floatsel, |
695 | | ldst_immpost, |
696 | | ldst_immpre, |
697 | | ldst_imm9, /* immpost or immpre */ |
698 | | ldst_imm10, /* LDRAA/LDRAB */ |
699 | | ldst_pos, |
700 | | ldst_regoff, |
701 | | ldst_unpriv, |
702 | | ldst_unscaled, |
703 | | ldstexcl, |
704 | | ldstnapair_offs, |
705 | | ldstpair_off, |
706 | | ldstpair_indexed, |
707 | | loadlit, |
708 | | log_imm, |
709 | | log_shift, |
710 | | lse_atomic, |
711 | | movewide, |
712 | | pcreladdr, |
713 | | ic_system, |
714 | | sme_fp_sd, |
715 | | sme_int_sd, |
716 | | sme_misc, |
717 | | sme_mov, |
718 | | sme_ldr, |
719 | | sme_psel, |
720 | | sme_shift, |
721 | | sme_size_12_bhs, |
722 | | sme_size_12_hs, |
723 | | sme_size_22, |
724 | | sme_size_22_hsd, |
725 | | sme_sz_23, |
726 | | sme_str, |
727 | | sme_start, |
728 | | sme_stop, |
729 | | sme2_mov, |
730 | | sve_cpy, |
731 | | sve_index, |
732 | | sve_limm, |
733 | | sve_misc, |
734 | | sve_movprfx, |
735 | | sve_pred_zm, |
736 | | sve_shift_pred, |
737 | | sve_shift_unpred, |
738 | | sve_size_bhs, |
739 | | sve_size_bhsd, |
740 | | sve_size_hsd, |
741 | | sve_size_hsd2, |
742 | | sve_size_sd, |
743 | | sve_size_bh, |
744 | | sve_size_sd2, |
745 | | sve_size_13, |
746 | | sve_shift_tsz_hsd, |
747 | | sve_shift_tsz_bhsd, |
748 | | sve_size_tsz_bhs, |
749 | | testbranch, |
750 | | cryptosm3, |
751 | | cryptosm4, |
752 | | dotproduct, |
753 | | bfloat16, |
754 | | cssc, |
755 | | }; |
756 | | |
757 | | /* Opcode enumerators. */ |
758 | | |
759 | | enum aarch64_op |
760 | | { |
761 | | OP_NIL, |
762 | | OP_STRB_POS, |
763 | | OP_LDRB_POS, |
764 | | OP_LDRSB_POS, |
765 | | OP_STRH_POS, |
766 | | OP_LDRH_POS, |
767 | | OP_LDRSH_POS, |
768 | | OP_STR_POS, |
769 | | OP_LDR_POS, |
770 | | OP_STRF_POS, |
771 | | OP_LDRF_POS, |
772 | | OP_LDRSW_POS, |
773 | | OP_PRFM_POS, |
774 | | |
775 | | OP_STURB, |
776 | | OP_LDURB, |
777 | | OP_LDURSB, |
778 | | OP_STURH, |
779 | | OP_LDURH, |
780 | | OP_LDURSH, |
781 | | OP_STUR, |
782 | | OP_LDUR, |
783 | | OP_STURV, |
784 | | OP_LDURV, |
785 | | OP_LDURSW, |
786 | | OP_PRFUM, |
787 | | |
788 | | OP_LDR_LIT, |
789 | | OP_LDRV_LIT, |
790 | | OP_LDRSW_LIT, |
791 | | OP_PRFM_LIT, |
792 | | |
793 | | OP_ADD, |
794 | | OP_B, |
795 | | OP_BL, |
796 | | |
797 | | OP_MOVN, |
798 | | OP_MOVZ, |
799 | | OP_MOVK, |
800 | | |
801 | | OP_MOV_IMM_LOG, /* MOV alias for moving bitmask immediate. */ |
802 | | OP_MOV_IMM_WIDE, /* MOV alias for moving wide immediate. */ |
803 | | OP_MOV_IMM_WIDEN, /* MOV alias for moving wide immediate (negated). */ |
804 | | |
805 | | OP_MOV_V, /* MOV alias for moving vector register. */ |
806 | | |
807 | | OP_ASR_IMM, |
808 | | OP_LSR_IMM, |
809 | | OP_LSL_IMM, |
810 | | |
811 | | OP_BIC, |
812 | | |
813 | | OP_UBFX, |
814 | | OP_BFXIL, |
815 | | OP_SBFX, |
816 | | OP_SBFIZ, |
817 | | OP_BFI, |
818 | | OP_BFC, /* ARMv8.2. */ |
819 | | OP_UBFIZ, |
820 | | OP_UXTB, |
821 | | OP_UXTH, |
822 | | OP_UXTW, |
823 | | |
824 | | OP_CINC, |
825 | | OP_CINV, |
826 | | OP_CNEG, |
827 | | OP_CSET, |
828 | | OP_CSETM, |
829 | | |
830 | | OP_FCVT, |
831 | | OP_FCVTN, |
832 | | OP_FCVTN2, |
833 | | OP_FCVTL, |
834 | | OP_FCVTL2, |
835 | | OP_FCVTXN_S, /* Scalar version. */ |
836 | | |
837 | | OP_ROR_IMM, |
838 | | |
839 | | OP_SXTL, |
840 | | OP_SXTL2, |
841 | | OP_UXTL, |
842 | | OP_UXTL2, |
843 | | |
844 | | OP_MOV_P_P, |
845 | | OP_MOV_PN_PN, |
846 | | OP_MOV_Z_P_Z, |
847 | | OP_MOV_Z_V, |
848 | | OP_MOV_Z_Z, |
849 | | OP_MOV_Z_Zi, |
850 | | OP_MOVM_P_P_P, |
851 | | OP_MOVS_P_P, |
852 | | OP_MOVZS_P_P_P, |
853 | | OP_MOVZ_P_P_P, |
854 | | OP_NOTS_P_P_P_Z, |
855 | | OP_NOT_P_P_P_Z, |
856 | | |
857 | | OP_FCMLA_ELEM, /* ARMv8.3, indexed element version. */ |
858 | | |
859 | | OP_TOTAL_NUM, /* Pseudo. */ |
860 | | }; |
861 | | |
862 | | /* Error types. */ |
863 | | enum err_type |
864 | | { |
865 | | ERR_OK, |
866 | | ERR_UND, |
867 | | ERR_UNP, |
868 | | ERR_NYI, |
869 | | ERR_VFI, |
870 | | ERR_NR_ENTRIES |
871 | | }; |
872 | | |
873 | | /* Maximum number of operands an instruction can have. */ |
874 | 234M | #define AARCH64_MAX_OPND_NUM 6 |
875 | | /* Maximum number of qualifier sequences an instruction can have. */ |
876 | 17.4M | #define AARCH64_MAX_QLF_SEQ_NUM 10 |
877 | | /* Operand qualifier typedef; optimized for the size. */ |
878 | | typedef unsigned char aarch64_opnd_qualifier_t; |
879 | | /* Operand qualifier sequence typedef. */ |
880 | | typedef aarch64_opnd_qualifier_t \ |
881 | | aarch64_opnd_qualifier_seq_t [AARCH64_MAX_OPND_NUM]; |
882 | | |
883 | | /* FIXME: improve the efficiency. */ |
884 | | static inline bool |
885 | | empty_qualifier_sequence_p (const aarch64_opnd_qualifier_t *qualifiers) |
886 | 5.07M | { |
887 | 5.07M | int i; |
888 | 5.58M | for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i) |
889 | 5.49M | if (qualifiers[i] != AARCH64_OPND_QLF_NIL) |
890 | 4.98M | return false; |
891 | 84.4k | return true; |
892 | 5.07M | } Unexecuted instantiation: aarch64-dis.c:empty_qualifier_sequence_p Unexecuted instantiation: aarch64-dis-2.c:empty_qualifier_sequence_p aarch64-opc.c:empty_qualifier_sequence_p Line | Count | Source | 886 | 5.07M | { | 887 | 5.07M | int i; | 888 | 5.58M | for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i) | 889 | 5.49M | if (qualifiers[i] != AARCH64_OPND_QLF_NIL) | 890 | 4.98M | return false; | 891 | 84.4k | return true; | 892 | 5.07M | } |
Unexecuted instantiation: aarch64-opc-2.c:empty_qualifier_sequence_p |
893 | | |
894 | | /* Forward declare error reporting type. */ |
895 | | typedef struct aarch64_operand_error aarch64_operand_error; |
896 | | /* Forward declare instruction sequence type. */ |
897 | | typedef struct aarch64_instr_sequence aarch64_instr_sequence; |
898 | | /* Forward declare instruction definition. */ |
899 | | typedef struct aarch64_inst aarch64_inst; |
900 | | |
901 | | /* This structure holds information for a particular opcode. */ |
902 | | |
903 | | struct aarch64_opcode |
904 | | { |
905 | | /* The name of the mnemonic. */ |
906 | | const char *name; |
907 | | |
908 | | /* The opcode itself. Those bits which will be filled in with |
909 | | operands are zeroes. */ |
910 | | aarch64_insn opcode; |
911 | | |
912 | | /* The opcode mask. This is used by the disassembler. This is a |
913 | | mask containing ones indicating those bits which must match the |
914 | | opcode field, and zeroes indicating those bits which need not |
915 | | match (and are presumably filled in by operands). */ |
916 | | aarch64_insn mask; |
917 | | |
918 | | /* Instruction class. */ |
919 | | enum aarch64_insn_class iclass; |
920 | | |
921 | | /* Enumerator identifier. */ |
922 | | enum aarch64_op op; |
923 | | |
924 | | /* Which architecture variant provides this instruction. */ |
925 | | const aarch64_feature_set *avariant; |
926 | | |
927 | | /* An array of operand codes. Each code is an index into the |
928 | | operand table. They appear in the order which the operands must |
929 | | appear in assembly code, and are terminated by a zero. */ |
930 | | enum aarch64_opnd operands[AARCH64_MAX_OPND_NUM]; |
931 | | |
932 | | /* A list of operand qualifier code sequence. Each operand qualifier |
933 | | code qualifies the corresponding operand code. Each operand |
934 | | qualifier sequence specifies a valid opcode variant and related |
935 | | constraint on operands. */ |
936 | | aarch64_opnd_qualifier_seq_t qualifiers_list[AARCH64_MAX_QLF_SEQ_NUM]; |
937 | | |
938 | | /* Flags providing information about this instruction */ |
939 | | uint64_t flags; |
940 | | |
941 | | /* Extra constraints on the instruction that the verifier checks. */ |
942 | | uint32_t constraints; |
943 | | |
944 | | /* If nonzero, this operand and operand 0 are both registers and |
945 | | are required to have the same register number. */ |
946 | | unsigned char tied_operand; |
947 | | |
948 | | /* If non-NULL, a function to verify that a given instruction is valid. */ |
949 | | enum err_type (* verifier) (const struct aarch64_inst *, const aarch64_insn, |
950 | | bfd_vma, bool, aarch64_operand_error *, |
951 | | struct aarch64_instr_sequence *); |
952 | | }; |
953 | | |
954 | | typedef struct aarch64_opcode aarch64_opcode; |
955 | | |
956 | | /* Table describing all the AArch64 opcodes. */ |
957 | | extern const aarch64_opcode aarch64_opcode_table[]; |
958 | | |
959 | | /* Opcode flags. */ |
960 | 2.29M | #define F_ALIAS (1 << 0) |
961 | 9.35M | #define F_HAS_ALIAS (1 << 1) |
962 | | /* Disassembly preference priority 1-3 (the larger the higher). If nothing |
963 | | is specified, it is the priority 0 by default, i.e. the lowest priority. */ |
964 | | #define F_P1 (1 << 2) |
965 | | #define F_P2 (2 << 2) |
966 | | #define F_P3 (3 << 2) |
967 | | /* Flag an instruction that is truly conditional executed, e.g. b.cond. */ |
968 | 32.6M | #define F_COND (1 << 4) |
969 | | /* Instruction has the field of 'sf'. */ |
970 | 15.4M | #define F_SF (1 << 5) |
971 | | /* Instruction has the field of 'size:Q'. */ |
972 | 15.3M | #define F_SIZEQ (1 << 6) |
973 | | /* Floating-point instruction has the field of 'type'. */ |
974 | 14.9M | #define F_FPTYPE (1 << 7) |
975 | | /* AdvSIMD scalar instruction has the field of 'size'. */ |
976 | 14.9M | #define F_SSIZE (1 << 8) |
977 | | /* AdvSIMD vector register arrangement specifier encoded in "imm5<3:0>:Q". */ |
978 | 14.9M | #define F_T (1 << 9) |
979 | | /* Size of GPR operand in AdvSIMD instructions encoded in Q. */ |
980 | 14.9M | #define F_GPRSIZE_IN_Q (1 << 10) |
981 | | /* Size of Rt load signed instruction encoded in opc[0], i.e. bit 22. */ |
982 | 14.9M | #define F_LDS_SIZE (1 << 11) |
983 | | /* Optional operand; assume maximum of 1 operand can be optional. */ |
984 | | #define F_OPD0_OPT (1 << 12) |
985 | | #define F_OPD1_OPT (2 << 12) |
986 | | #define F_OPD2_OPT (3 << 12) |
987 | | #define F_OPD3_OPT (4 << 12) |
988 | | #define F_OPD4_OPT (5 << 12) |
989 | | /* Default value for the optional operand when omitted from the assembly. */ |
990 | | #define F_DEFAULT(X) (((X) & 0x1f) << 15) |
991 | | /* Instruction that is an alias of another instruction needs to be |
992 | | encoded/decoded by converting it to/from the real form, followed by |
993 | | the encoding/decoding according to the rules of the real opcode. |
994 | | This compares to the direct coding using the alias's information. |
995 | | N.B. this flag requires F_ALIAS to be used together. */ |
996 | 1.22M | #define F_CONV (1 << 20) |
997 | | /* Use together with F_ALIAS to indicate an alias opcode is a programmer |
998 | | friendly pseudo instruction available only in the assembly code (thus will |
999 | | not show up in the disassembly). */ |
1000 | 2.29M | #define F_PSEUDO (1 << 21) |
1001 | | /* Instruction has miscellaneous encoding/decoding rules. */ |
1002 | 14.9M | #define F_MISC (1 << 22) |
1003 | | /* Instruction has the field of 'N'; used in conjunction with F_SF. */ |
1004 | 14.4M | #define F_N (1 << 23) |
1005 | | /* Opcode dependent field. */ |
1006 | | #define F_OD(X) (((X) & 0x7) << 24) |
1007 | | /* Instruction has the field of 'sz'. */ |
1008 | 15.3M | #define F_LSE_SZ (1 << 27) |
1009 | | /* Require an exact qualifier match, even for NIL qualifiers. */ |
1010 | 23.2M | #define F_STRICT (1ULL << 28) |
1011 | | /* This system instruction is used to read system registers. */ |
1012 | 24.1k | #define F_SYS_READ (1ULL << 29) |
1013 | | /* This system instruction is used to write system registers. */ |
1014 | 20.2k | #define F_SYS_WRITE (1ULL << 30) |
1015 | | /* This instruction has an extra constraint on it that imposes a requirement on |
1016 | | subsequent instructions. */ |
1017 | 246k | #define F_SCAN (1ULL << 31) |
1018 | | /* Next bit is 32. */ |
1019 | | |
1020 | | /* Instruction constraints. */ |
1021 | | /* This instruction has a predication constraint on the instruction at PC+4. */ |
1022 | 5.48k | #define C_SCAN_MOVPRFX (1U << 0) |
1023 | | /* This instruction's operation width is determined by the operand with the |
1024 | | largest element size. */ |
1025 | 38 | #define C_MAX_ELEM (1U << 1) |
1026 | 4.70k | #define C_SCAN_MOPS_P (1U << 2) |
1027 | 11.5k | #define C_SCAN_MOPS_M (2U << 2) |
1028 | | #define C_SCAN_MOPS_E (3U << 2) |
1029 | 259k | #define C_SCAN_MOPS_PME (3U << 2) |
1030 | | /* Next bit is 4. */ |
1031 | | |
1032 | | static inline bool |
1033 | | alias_opcode_p (const aarch64_opcode *opcode) |
1034 | 2.29M | { |
1035 | 2.29M | return (opcode->flags & F_ALIAS) != 0; |
1036 | 2.29M | } aarch64-dis.c:alias_opcode_p Line | Count | Source | 1034 | 2.29M | { | 1035 | 2.29M | return (opcode->flags & F_ALIAS) != 0; | 1036 | 2.29M | } |
Unexecuted instantiation: aarch64-dis-2.c:alias_opcode_p Unexecuted instantiation: aarch64-opc.c:alias_opcode_p Unexecuted instantiation: aarch64-opc-2.c:alias_opcode_p |
1037 | | |
1038 | | static inline bool |
1039 | | opcode_has_alias (const aarch64_opcode *opcode) |
1040 | 9.35M | { |
1041 | 9.35M | return (opcode->flags & F_HAS_ALIAS) != 0; |
1042 | 9.35M | } aarch64-dis.c:opcode_has_alias Line | Count | Source | 1040 | 9.35M | { | 1041 | 9.35M | return (opcode->flags & F_HAS_ALIAS) != 0; | 1042 | 9.35M | } |
Unexecuted instantiation: aarch64-dis-2.c:opcode_has_alias Unexecuted instantiation: aarch64-opc.c:opcode_has_alias Unexecuted instantiation: aarch64-opc-2.c:opcode_has_alias |
1043 | | |
1044 | | /* Priority for disassembling preference. */ |
1045 | | static inline int |
1046 | | opcode_priority (const aarch64_opcode *opcode) |
1047 | 0 | { |
1048 | 0 | return (opcode->flags >> 2) & 0x3; |
1049 | 0 | } Unexecuted instantiation: aarch64-dis.c:opcode_priority Unexecuted instantiation: aarch64-dis-2.c:opcode_priority Unexecuted instantiation: aarch64-opc.c:opcode_priority Unexecuted instantiation: aarch64-opc-2.c:opcode_priority |
1050 | | |
1051 | | static inline bool |
1052 | | pseudo_opcode_p (const aarch64_opcode *opcode) |
1053 | 2.29M | { |
1054 | 2.29M | return (opcode->flags & F_PSEUDO) != 0lu; |
1055 | 2.29M | } aarch64-dis.c:pseudo_opcode_p Line | Count | Source | 1053 | 2.29M | { | 1054 | 2.29M | return (opcode->flags & F_PSEUDO) != 0lu; | 1055 | 2.29M | } |
Unexecuted instantiation: aarch64-dis-2.c:pseudo_opcode_p Unexecuted instantiation: aarch64-opc.c:pseudo_opcode_p Unexecuted instantiation: aarch64-opc-2.c:pseudo_opcode_p |
1056 | | |
1057 | | static inline bool |
1058 | | optional_operand_p (const aarch64_opcode *opcode, unsigned int idx) |
1059 | 5.15M | { |
1060 | 5.15M | return ((opcode->flags >> 12) & 0x7) == idx + 1; |
1061 | 5.15M | } Unexecuted instantiation: aarch64-dis.c:optional_operand_p Unexecuted instantiation: aarch64-dis-2.c:optional_operand_p aarch64-opc.c:optional_operand_p Line | Count | Source | 1059 | 5.15M | { | 1060 | 5.15M | return ((opcode->flags >> 12) & 0x7) == idx + 1; | 1061 | 5.15M | } |
Unexecuted instantiation: aarch64-opc-2.c:optional_operand_p |
1062 | | |
1063 | | static inline aarch64_insn |
1064 | | get_optional_operand_default_value (const aarch64_opcode *opcode) |
1065 | 6.55k | { |
1066 | 6.55k | return (opcode->flags >> 15) & 0x1f; |
1067 | 6.55k | } Unexecuted instantiation: aarch64-dis.c:get_optional_operand_default_value Unexecuted instantiation: aarch64-dis-2.c:get_optional_operand_default_value aarch64-opc.c:get_optional_operand_default_value Line | Count | Source | 1065 | 6.55k | { | 1066 | 6.55k | return (opcode->flags >> 15) & 0x1f; | 1067 | 6.55k | } |
Unexecuted instantiation: aarch64-opc-2.c:get_optional_operand_default_value |
1068 | | |
1069 | | static inline unsigned int |
1070 | | get_opcode_dependent_value (const aarch64_opcode *opcode) |
1071 | 1.11M | { |
1072 | 1.11M | return (opcode->flags >> 24) & 0x7; |
1073 | 1.11M | } aarch64-dis.c:get_opcode_dependent_value Line | Count | Source | 1071 | 576k | { | 1072 | 576k | return (opcode->flags >> 24) & 0x7; | 1073 | 576k | } |
Unexecuted instantiation: aarch64-dis-2.c:get_opcode_dependent_value aarch64-opc.c:get_opcode_dependent_value Line | Count | Source | 1071 | 538k | { | 1072 | 538k | return (opcode->flags >> 24) & 0x7; | 1073 | 538k | } |
Unexecuted instantiation: aarch64-opc-2.c:get_opcode_dependent_value |
1074 | | |
1075 | | static inline bool |
1076 | | opcode_has_special_coder (const aarch64_opcode *opcode) |
1077 | 10.9M | { |
1078 | 10.9M | return (opcode->flags & (F_SF | F_LSE_SZ | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T |
1079 | 10.9M | | F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND)) != 0; |
1080 | 10.9M | } aarch64-dis.c:opcode_has_special_coder Line | Count | Source | 1077 | 10.9M | { | 1078 | 10.9M | return (opcode->flags & (F_SF | F_LSE_SZ | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T | 1079 | 10.9M | | F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND)) != 0; | 1080 | 10.9M | } |
Unexecuted instantiation: aarch64-dis-2.c:opcode_has_special_coder Unexecuted instantiation: aarch64-opc.c:opcode_has_special_coder Unexecuted instantiation: aarch64-opc-2.c:opcode_has_special_coder |
1081 | | |
1082 | | struct aarch64_name_value_pair |
1083 | | { |
1084 | | const char * name; |
1085 | | aarch64_insn value; |
1086 | | }; |
1087 | | |
1088 | | extern const struct aarch64_name_value_pair aarch64_operand_modifiers []; |
1089 | | extern const struct aarch64_name_value_pair aarch64_barrier_options [16]; |
1090 | | extern const struct aarch64_name_value_pair aarch64_barrier_dsb_nxs_options [4]; |
1091 | | extern const struct aarch64_name_value_pair aarch64_prfops [32]; |
1092 | | extern const struct aarch64_name_value_pair aarch64_hint_options []; |
1093 | | |
1094 | | #define AARCH64_MAX_SYSREG_NAME_LEN 32 |
1095 | | |
1096 | | typedef struct |
1097 | | { |
1098 | | const char * name; |
1099 | | aarch64_insn value; |
1100 | | uint32_t flags; |
1101 | | |
1102 | | /* A set of features, all of which are required for this system register to be |
1103 | | available. */ |
1104 | | aarch64_feature_set features; |
1105 | | } aarch64_sys_reg; |
1106 | | |
1107 | | extern const aarch64_sys_reg aarch64_sys_regs []; |
1108 | | extern const aarch64_sys_reg aarch64_pstatefields []; |
1109 | | extern bool aarch64_sys_reg_deprecated_p (const uint32_t); |
1110 | | extern bool aarch64_pstatefield_supported_p (const aarch64_feature_set, |
1111 | | const aarch64_sys_reg *); |
1112 | | |
1113 | | typedef struct |
1114 | | { |
1115 | | const char *name; |
1116 | | uint32_t value; |
1117 | | uint32_t flags ; |
1118 | | } aarch64_sys_ins_reg; |
1119 | | |
1120 | | extern bool aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *); |
1121 | | extern bool |
1122 | | aarch64_sys_ins_reg_supported_p (const aarch64_feature_set, |
1123 | | const char *reg_name, aarch64_insn, |
1124 | | uint32_t, aarch64_feature_set); |
1125 | | |
1126 | | extern const aarch64_sys_ins_reg aarch64_sys_regs_ic []; |
1127 | | extern const aarch64_sys_ins_reg aarch64_sys_regs_dc []; |
1128 | | extern const aarch64_sys_ins_reg aarch64_sys_regs_at []; |
1129 | | extern const aarch64_sys_ins_reg aarch64_sys_regs_tlbi []; |
1130 | | extern const aarch64_sys_ins_reg aarch64_sys_regs_sr []; |
1131 | | |
1132 | | /* Shift/extending operator kinds. |
1133 | | N.B. order is important; keep aarch64_operand_modifiers synced. */ |
1134 | | enum aarch64_modifier_kind |
1135 | | { |
1136 | | AARCH64_MOD_NONE, |
1137 | | AARCH64_MOD_MSL, |
1138 | | AARCH64_MOD_ROR, |
1139 | | AARCH64_MOD_ASR, |
1140 | | AARCH64_MOD_LSR, |
1141 | | AARCH64_MOD_LSL, |
1142 | | AARCH64_MOD_UXTB, |
1143 | | AARCH64_MOD_UXTH, |
1144 | | AARCH64_MOD_UXTW, |
1145 | | AARCH64_MOD_UXTX, |
1146 | | AARCH64_MOD_SXTB, |
1147 | | AARCH64_MOD_SXTH, |
1148 | | AARCH64_MOD_SXTW, |
1149 | | AARCH64_MOD_SXTX, |
1150 | | AARCH64_MOD_MUL, |
1151 | | AARCH64_MOD_MUL_VL, |
1152 | | }; |
1153 | | |
1154 | | bool |
1155 | | aarch64_extend_operator_p (enum aarch64_modifier_kind); |
1156 | | |
1157 | | enum aarch64_modifier_kind |
1158 | | aarch64_get_operand_modifier (const struct aarch64_name_value_pair *); |
1159 | | /* Condition. */ |
1160 | | |
1161 | | typedef struct |
1162 | | { |
1163 | | /* A list of names with the first one as the disassembly preference; |
1164 | | terminated by NULL if fewer than 3. */ |
1165 | | const char *names[4]; |
1166 | | aarch64_insn value; |
1167 | | } aarch64_cond; |
1168 | | |
1169 | | extern const aarch64_cond aarch64_conds[16]; |
1170 | | |
1171 | | const aarch64_cond* get_cond_from_value (aarch64_insn value); |
1172 | | const aarch64_cond* get_inverted_cond (const aarch64_cond *cond); |
1173 | | |
1174 | | /* Information about a reference to part of ZA. */ |
1175 | | struct aarch64_indexed_za |
1176 | | { |
1177 | | /* Which tile is being accessed. Unused (and 0) for an index into ZA. */ |
1178 | | int regno; |
1179 | | |
1180 | | struct |
1181 | | { |
1182 | | /* The 32-bit index register. */ |
1183 | | int regno; |
1184 | | |
1185 | | /* The first (or only) immediate offset. */ |
1186 | | int64_t imm; |
1187 | | |
1188 | | /* The last immediate offset minus the first immediate offset. |
1189 | | Unlike the range size, this is guaranteed not to overflow |
1190 | | when the end offset > the start offset. */ |
1191 | | uint64_t countm1; |
1192 | | } index; |
1193 | | |
1194 | | /* The vector group size, or 0 if none. */ |
1195 | | unsigned group_size : 8; |
1196 | | |
1197 | | /* True if a tile access is vertical, false if it is horizontal. |
1198 | | Unused (and 0) for an index into ZA. */ |
1199 | | unsigned v : 1; |
1200 | | }; |
1201 | | |
1202 | | /* Information about a list of registers. */ |
1203 | | struct aarch64_reglist |
1204 | | { |
1205 | | unsigned first_regno : 8; |
1206 | | unsigned num_regs : 8; |
1207 | | /* The difference between the nth and the n+1th register. */ |
1208 | | unsigned stride : 8; |
1209 | | /* 1 if it is a list of reg element. */ |
1210 | | unsigned has_index : 1; |
1211 | | /* Lane index; valid only when has_index is 1. */ |
1212 | | int64_t index; |
1213 | | }; |
1214 | | |
1215 | | /* Structure representing an operand. */ |
1216 | | |
1217 | | struct aarch64_opnd_info |
1218 | | { |
1219 | | enum aarch64_opnd type; |
1220 | | aarch64_opnd_qualifier_t qualifier; |
1221 | | int idx; |
1222 | | |
1223 | | union |
1224 | | { |
1225 | | struct |
1226 | | { |
1227 | | unsigned regno; |
1228 | | } reg; |
1229 | | struct |
1230 | | { |
1231 | | unsigned int regno; |
1232 | | int64_t index; |
1233 | | } reglane; |
1234 | | /* e.g. LVn. */ |
1235 | | struct aarch64_reglist reglist; |
1236 | | /* e.g. immediate or pc relative address offset. */ |
1237 | | struct |
1238 | | { |
1239 | | int64_t value; |
1240 | | unsigned is_fp : 1; |
1241 | | } imm; |
1242 | | /* e.g. address in STR (register offset). */ |
1243 | | struct |
1244 | | { |
1245 | | unsigned base_regno; |
1246 | | struct |
1247 | | { |
1248 | | union |
1249 | | { |
1250 | | int imm; |
1251 | | unsigned regno; |
1252 | | }; |
1253 | | unsigned is_reg; |
1254 | | } offset; |
1255 | | unsigned pcrel : 1; /* PC-relative. */ |
1256 | | unsigned writeback : 1; |
1257 | | unsigned preind : 1; /* Pre-indexed. */ |
1258 | | unsigned postind : 1; /* Post-indexed. */ |
1259 | | } addr; |
1260 | | |
1261 | | struct |
1262 | | { |
1263 | | /* The encoding of the system register. */ |
1264 | | aarch64_insn value; |
1265 | | |
1266 | | /* The system register flags. */ |
1267 | | uint32_t flags; |
1268 | | } sysreg; |
1269 | | |
1270 | | /* ZA tile vector, e.g. <ZAn><HV>.D[<Wv>{, <imm>}] */ |
1271 | | struct aarch64_indexed_za indexed_za; |
1272 | | |
1273 | | const aarch64_cond *cond; |
1274 | | /* The encoding of the PSTATE field. */ |
1275 | | aarch64_insn pstatefield; |
1276 | | const aarch64_sys_ins_reg *sysins_op; |
1277 | | const struct aarch64_name_value_pair *barrier; |
1278 | | const struct aarch64_name_value_pair *hint_option; |
1279 | | const struct aarch64_name_value_pair *prfop; |
1280 | | }; |
1281 | | |
1282 | | /* Operand shifter; in use when the operand is a register offset address, |
1283 | | add/sub extended reg, etc. e.g. <R><m>{, <extend> {#<amount>}}. */ |
1284 | | struct |
1285 | | { |
1286 | | enum aarch64_modifier_kind kind; |
1287 | | unsigned operator_present: 1; /* Only valid during encoding. */ |
1288 | | /* Value of the 'S' field in ld/st reg offset; used only in decoding. */ |
1289 | | unsigned amount_present: 1; |
1290 | | int64_t amount; |
1291 | | } shifter; |
1292 | | |
1293 | | unsigned skip:1; /* Operand is not completed if there is a fixup needed |
1294 | | to be done on it. In some (but not all) of these |
1295 | | cases, we need to tell libopcodes to skip the |
1296 | | constraint checking and the encoding for this |
1297 | | operand, so that the libopcodes can pick up the |
1298 | | right opcode before the operand is fixed-up. This |
1299 | | flag should only be used during the |
1300 | | assembling/encoding. */ |
1301 | | unsigned present:1; /* Whether this operand is present in the assembly |
1302 | | line; not used during the disassembly. */ |
1303 | | }; |
1304 | | |
1305 | | typedef struct aarch64_opnd_info aarch64_opnd_info; |
1306 | | |
1307 | | /* Structure representing an instruction. |
1308 | | |
1309 | | It is used during both the assembling and disassembling. The assembler |
1310 | | fills an aarch64_inst after a successful parsing and then passes it to the |
1311 | | encoding routine to do the encoding. During the disassembling, the |
1312 | | disassembler calls the decoding routine to decode a binary instruction; on a |
1313 | | successful return, such a structure will be filled with information of the |
1314 | | instruction; then the disassembler uses the information to print out the |
1315 | | instruction. */ |
1316 | | |
1317 | | struct aarch64_inst |
1318 | | { |
1319 | | /* The value of the binary instruction. */ |
1320 | | aarch64_insn value; |
1321 | | |
1322 | | /* Corresponding opcode entry. */ |
1323 | | const aarch64_opcode *opcode; |
1324 | | |
1325 | | /* Condition for a truly conditional-executed instrutions, e.g. b.cond. */ |
1326 | | const aarch64_cond *cond; |
1327 | | |
1328 | | /* Operands information. */ |
1329 | | aarch64_opnd_info operands[AARCH64_MAX_OPND_NUM]; |
1330 | | }; |
1331 | | |
1332 | | /* Defining the HINT #imm values for the aarch64_hint_options. */ |
1333 | | #define HINT_OPD_CSYNC 0x11 |
1334 | | #define HINT_OPD_C 0x22 |
1335 | | #define HINT_OPD_J 0x24 |
1336 | | #define HINT_OPD_JC 0x26 |
1337 | | #define HINT_OPD_NULL 0x00 |
1338 | | |
1339 | | |
1340 | | /* Diagnosis related declaration and interface. */ |
1341 | | |
1342 | | /* Operand error kind enumerators. |
1343 | | |
1344 | | AARCH64_OPDE_RECOVERABLE |
1345 | | Less severe error found during the parsing, very possibly because that |
1346 | | GAS has picked up a wrong instruction template for the parsing. |
1347 | | |
1348 | | AARCH64_OPDE_A_SHOULD_FOLLOW_B |
1349 | | The instruction forms (or is expected to form) part of a sequence, |
1350 | | but the preceding instruction in the sequence wasn't the expected one. |
1351 | | The message refers to two strings: the name of the current instruction, |
1352 | | followed by the name of the expected preceding instruction. |
1353 | | |
1354 | | AARCH64_OPDE_EXPECTED_A_AFTER_B |
1355 | | Same as AARCH64_OPDE_A_SHOULD_FOLLOW_B, but shifting the focus |
1356 | | so that the current instruction is assumed to be the incorrect one: |
1357 | | "since the previous instruction was B, the current one should be A". |
1358 | | |
1359 | | AARCH64_OPDE_SYNTAX_ERROR |
1360 | | General syntax error; it can be either a user error, or simply because |
1361 | | that GAS is trying a wrong instruction template. |
1362 | | |
1363 | | AARCH64_OPDE_FATAL_SYNTAX_ERROR |
1364 | | Definitely a user syntax error. |
1365 | | |
1366 | | AARCH64_OPDE_INVALID_VARIANT |
1367 | | No syntax error, but the operands are not a valid combination, e.g. |
1368 | | FMOV D0,S0 |
1369 | | |
1370 | | The following errors are only reported against an asm string that is |
1371 | | syntactically valid and that has valid operand qualifiers. |
1372 | | |
1373 | | AARCH64_OPDE_INVALID_VG_SIZE |
1374 | | Error about a "VGx<n>" modifier in a ZA index not having the |
1375 | | correct <n>. This error effectively forms a pair with |
1376 | | AARCH64_OPDE_REG_LIST_LENGTH, since both errors relate to the number |
1377 | | of vectors that an instruction operates on. However, the "VGx<n>" |
1378 | | modifier is optional, whereas a register list always has a known |
1379 | | and explicit length. It therefore seems better to place more |
1380 | | importance on the register list length when selecting an opcode table |
1381 | | entry. This in turn means that having an incorrect register length |
1382 | | should be more severe than having an incorrect "VGx<n>". |
1383 | | |
1384 | | AARCH64_OPDE_REG_LIST_LENGTH |
1385 | | Error about a register list operand having an unexpected number of |
1386 | | registers. This error is low severity because there might be another |
1387 | | opcode entry that supports the given number of registers. |
1388 | | |
1389 | | AARCH64_OPDE_REG_LIST_STRIDE |
1390 | | Error about a register list operand having the correct number |
1391 | | (and type) of registers, but an unexpected stride. This error is |
1392 | | more severe than AARCH64_OPDE_REG_LIST_LENGTH because it implies |
1393 | | that the length is known to be correct. However, it is lower than |
1394 | | many other errors, since some instructions have forms that share |
1395 | | the same number of registers but have different strides. |
1396 | | |
1397 | | AARCH64_OPDE_UNTIED_IMMS |
1398 | | The asm failed to use the same immediate for a destination operand |
1399 | | and a tied source operand. |
1400 | | |
1401 | | AARCH64_OPDE_UNTIED_OPERAND |
1402 | | The asm failed to use the same register for a destination operand |
1403 | | and a tied source operand. |
1404 | | |
1405 | | AARCH64_OPDE_OUT_OF_RANGE |
1406 | | Error about some immediate value out of a valid range. |
1407 | | |
1408 | | AARCH64_OPDE_UNALIGNED |
1409 | | Error about some immediate value not properly aligned (i.e. not being a |
1410 | | multiple times of a certain value). |
1411 | | |
1412 | | AARCH64_OPDE_OTHER_ERROR |
1413 | | Error of the highest severity and used for any severe issue that does not |
1414 | | fall into any of the above categories. |
1415 | | |
1416 | | AARCH64_OPDE_INVALID_REGNO |
1417 | | A register was syntactically valid and had the right type, but it was |
1418 | | outside the range supported by the associated operand field. This is |
1419 | | a high severity error because there are currently no instructions that |
1420 | | would accept the operands that precede the erroneous one (if any) and |
1421 | | yet still accept a wider range of registers. |
1422 | | |
1423 | | AARCH64_OPDE_RECOVERABLE, AARCH64_OPDE_SYNTAX_ERROR and |
1424 | | AARCH64_OPDE_FATAL_SYNTAX_ERROR are only deteced by GAS while the |
1425 | | AARCH64_OPDE_INVALID_VARIANT error can only be spotted by libopcodes as |
1426 | | only libopcodes has the information about the valid variants of each |
1427 | | instruction. |
1428 | | |
1429 | | The enumerators have an increasing severity. This is helpful when there are |
1430 | | multiple instruction templates available for a given mnemonic name (e.g. |
1431 | | FMOV); this mechanism will help choose the most suitable template from which |
1432 | | the generated diagnostics can most closely describe the issues, if any. |
1433 | | |
1434 | | This enum needs to be kept up-to-date with operand_mismatch_kind_names |
1435 | | in tc-aarch64.c. */ |
1436 | | |
1437 | | enum aarch64_operand_error_kind |
1438 | | { |
1439 | | AARCH64_OPDE_NIL, |
1440 | | AARCH64_OPDE_RECOVERABLE, |
1441 | | AARCH64_OPDE_A_SHOULD_FOLLOW_B, |
1442 | | AARCH64_OPDE_EXPECTED_A_AFTER_B, |
1443 | | AARCH64_OPDE_SYNTAX_ERROR, |
1444 | | AARCH64_OPDE_FATAL_SYNTAX_ERROR, |
1445 | | AARCH64_OPDE_INVALID_VARIANT, |
1446 | | AARCH64_OPDE_INVALID_VG_SIZE, |
1447 | | AARCH64_OPDE_REG_LIST_LENGTH, |
1448 | | AARCH64_OPDE_REG_LIST_STRIDE, |
1449 | | AARCH64_OPDE_UNTIED_IMMS, |
1450 | | AARCH64_OPDE_UNTIED_OPERAND, |
1451 | | AARCH64_OPDE_OUT_OF_RANGE, |
1452 | | AARCH64_OPDE_UNALIGNED, |
1453 | | AARCH64_OPDE_OTHER_ERROR, |
1454 | | AARCH64_OPDE_INVALID_REGNO |
1455 | | }; |
1456 | | |
1457 | | /* N.B. GAS assumes that this structure work well with shallow copy. */ |
1458 | | struct aarch64_operand_error |
1459 | | { |
1460 | | enum aarch64_operand_error_kind kind; |
1461 | | int index; |
1462 | | const char *error; |
1463 | | /* Some data for extra information. */ |
1464 | | union { |
1465 | | int i; |
1466 | | const char *s; |
1467 | | } data[3]; |
1468 | | bool non_fatal; |
1469 | | }; |
1470 | | |
1471 | | /* AArch64 sequence structure used to track instructions with F_SCAN |
1472 | | dependencies for both assembler and disassembler. */ |
1473 | | struct aarch64_instr_sequence |
1474 | | { |
1475 | | /* The instructions in the sequence, starting with the one that |
1476 | | caused it to be opened. */ |
1477 | | aarch64_inst *instr; |
1478 | | /* The number of instructions already in the sequence. */ |
1479 | | int num_added_insns; |
1480 | | /* The number of instructions allocated to the sequence. */ |
1481 | | int num_allocated_insns; |
1482 | | }; |
1483 | | |
1484 | | /* Encoding entrypoint. */ |
1485 | | |
1486 | | extern bool |
1487 | | aarch64_opcode_encode (const aarch64_opcode *, const aarch64_inst *, |
1488 | | aarch64_insn *, aarch64_opnd_qualifier_t *, |
1489 | | aarch64_operand_error *, aarch64_instr_sequence *); |
1490 | | |
1491 | | extern const aarch64_opcode * |
1492 | | aarch64_replace_opcode (struct aarch64_inst *, |
1493 | | const aarch64_opcode *); |
1494 | | |
1495 | | /* Given the opcode enumerator OP, return the pointer to the corresponding |
1496 | | opcode entry. */ |
1497 | | |
1498 | | extern const aarch64_opcode * |
1499 | | aarch64_get_opcode (enum aarch64_op); |
1500 | | |
1501 | | /* An instance of this structure is passed to aarch64_print_operand, and |
1502 | | the callback within this structure is used to apply styling to the |
1503 | | disassembler output. This structure encapsulates the callback and a |
1504 | | state pointer. */ |
1505 | | |
1506 | | struct aarch64_styler |
1507 | | { |
1508 | | /* The callback used to apply styling. Returns a string created from FMT |
1509 | | and ARGS with STYLE applied to the string. STYLER is a pointer back |
1510 | | to this object so that the callback can access the state member. |
1511 | | |
1512 | | The string returned from this callback must remain valid until the |
1513 | | call to aarch64_print_operand has completed. */ |
1514 | | const char *(*apply_style) (struct aarch64_styler *styler, |
1515 | | enum disassembler_style style, |
1516 | | const char *fmt, |
1517 | | va_list args); |
1518 | | |
1519 | | /* A pointer to a state object which can be used by the apply_style |
1520 | | callback function. */ |
1521 | | void *state; |
1522 | | }; |
1523 | | |
1524 | | /* Generate the string representation of an operand. */ |
1525 | | extern void |
1526 | | aarch64_print_operand (char *, size_t, bfd_vma, const aarch64_opcode *, |
1527 | | const aarch64_opnd_info *, int, int *, bfd_vma *, |
1528 | | char **, char *, size_t, |
1529 | | aarch64_feature_set features, |
1530 | | struct aarch64_styler *styler); |
1531 | | |
1532 | | /* Miscellaneous interface. */ |
1533 | | |
1534 | | extern int |
1535 | | aarch64_operand_index (const enum aarch64_opnd *, enum aarch64_opnd); |
1536 | | |
1537 | | extern aarch64_opnd_qualifier_t |
1538 | | aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *, int, |
1539 | | const aarch64_opnd_qualifier_t, int); |
1540 | | |
1541 | | extern bool |
1542 | | aarch64_is_destructive_by_operands (const aarch64_opcode *); |
1543 | | |
1544 | | extern int |
1545 | | aarch64_num_of_operands (const aarch64_opcode *); |
1546 | | |
1547 | | extern int |
1548 | | aarch64_stack_pointer_p (const aarch64_opnd_info *); |
1549 | | |
1550 | | extern int |
1551 | | aarch64_zero_register_p (const aarch64_opnd_info *); |
1552 | | |
1553 | | extern enum err_type |
1554 | | aarch64_decode_insn (aarch64_insn, aarch64_inst *, bool, |
1555 | | aarch64_operand_error *); |
1556 | | |
1557 | | extern void |
1558 | | init_insn_sequence (const struct aarch64_inst *, aarch64_instr_sequence *); |
1559 | | |
1560 | | /* Given an operand qualifier, return the expected data element size |
1561 | | of a qualified operand. */ |
1562 | | extern unsigned char |
1563 | | aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t); |
1564 | | |
1565 | | extern enum aarch64_operand_class |
1566 | | aarch64_get_operand_class (enum aarch64_opnd); |
1567 | | |
1568 | | extern const char * |
1569 | | aarch64_get_operand_name (enum aarch64_opnd); |
1570 | | |
1571 | | extern const char * |
1572 | | aarch64_get_operand_desc (enum aarch64_opnd); |
1573 | | |
1574 | | extern bool |
1575 | | aarch64_sve_dupm_mov_immediate_p (uint64_t, int); |
1576 | | |
1577 | | extern bool |
1578 | | aarch64_cpu_supports_inst_p (uint64_t, aarch64_inst *); |
1579 | | |
1580 | | #ifdef DEBUG_AARCH64 |
1581 | | extern int debug_dump; |
1582 | | |
1583 | | extern void |
1584 | | aarch64_verbose (const char *, ...) __attribute__ ((format (printf, 1, 2))); |
1585 | | |
1586 | | #define DEBUG_TRACE(M, ...) \ |
1587 | | { \ |
1588 | | if (debug_dump) \ |
1589 | | aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \ |
1590 | | } |
1591 | | |
1592 | | #define DEBUG_TRACE_IF(C, M, ...) \ |
1593 | | { \ |
1594 | | if (debug_dump && (C)) \ |
1595 | | aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \ |
1596 | | } |
1597 | | #else /* !DEBUG_AARCH64 */ |
1598 | 129M | #define DEBUG_TRACE(M, ...) ; |
1599 | 23.5M | #define DEBUG_TRACE_IF(C, M, ...) ; |
1600 | | #endif /* DEBUG_AARCH64 */ |
1601 | | |
1602 | | extern const char *const aarch64_sve_pattern_array[32]; |
1603 | | extern const char *const aarch64_sve_prfop_array[16]; |
1604 | | extern const char *const aarch64_rprfmop_array[64]; |
1605 | | extern const char *const aarch64_sme_vlxn_array[2]; |
1606 | | |
1607 | | #ifdef __cplusplus |
1608 | | } |
1609 | | #endif |
1610 | | |
1611 | | #endif /* OPCODE_AARCH64_H */ |