Coverage Report

Created: 2023-08-28 06:31

/src/binutils-gdb/opcodes/arm-dis.c
Line
Count
Source (jump to first uncovered line)
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/* Instruction printing code for the ARM
2
   Copyright (C) 1994-2023 Free Software Foundation, Inc.
3
   Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4
   Modification by James G. Smith (jsmith@cygnus.co.uk)
5
6
   This file is part of libopcodes.
7
8
   This library is free software; you can redistribute it and/or modify
9
   it under the terms of the GNU General Public License as published by
10
   the Free Software Foundation; either version 3 of the License, or
11
   (at your option) any later version.
12
13
   It is distributed in the hope that it will be useful, but WITHOUT
14
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
16
   License for more details.
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18
   You should have received a copy of the GNU General Public License
19
   along with this program; if not, write to the Free Software
20
   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21
   MA 02110-1301, USA.  */
22
23
#include "sysdep.h"
24
#include <assert.h>
25
26
#include "disassemble.h"
27
#include "opcode/arm.h"
28
#include "opintl.h"
29
#include "safe-ctype.h"
30
#include "libiberty.h"
31
#include "floatformat.h"
32
33
/* FIXME: This shouldn't be done here.  */
34
#include "coff/internal.h"
35
#include "libcoff.h"
36
#include "bfd.h"
37
#include "elf-bfd.h"
38
#include "elf/internal.h"
39
#include "elf/arm.h"
40
#include "mach-o.h"
41
42
/* Cached mapping symbol state.  */
43
enum map_type
44
{
45
  MAP_ARM,
46
  MAP_THUMB,
47
  MAP_DATA
48
};
49
50
struct arm_private_data
51
{
52
  /* The features to use when disassembling optional instructions.  */
53
  arm_feature_set features;
54
55
  /* Track the last type (although this doesn't seem to be useful) */
56
  enum map_type last_type;
57
58
  /* Tracking symbol table information */
59
  int last_mapping_sym;
60
61
  /* The end range of the current range being disassembled.  */
62
  bfd_vma last_stop_offset;
63
  bfd_vma last_mapping_addr;
64
};
65
66
enum mve_instructions
67
{
68
  MVE_VPST,
69
  MVE_VPT_FP_T1,
70
  MVE_VPT_FP_T2,
71
  MVE_VPT_VEC_T1,
72
  MVE_VPT_VEC_T2,
73
  MVE_VPT_VEC_T3,
74
  MVE_VPT_VEC_T4,
75
  MVE_VPT_VEC_T5,
76
  MVE_VPT_VEC_T6,
77
  MVE_VCMP_FP_T1,
78
  MVE_VCMP_FP_T2,
79
  MVE_VCMP_VEC_T1,
80
  MVE_VCMP_VEC_T2,
81
  MVE_VCMP_VEC_T3,
82
  MVE_VCMP_VEC_T4,
83
  MVE_VCMP_VEC_T5,
84
  MVE_VCMP_VEC_T6,
85
  MVE_VDUP,
86
  MVE_VEOR,
87
  MVE_VFMAS_FP_SCALAR,
88
  MVE_VFMA_FP_SCALAR,
89
  MVE_VFMA_FP,
90
  MVE_VFMS_FP,
91
  MVE_VHADD_T1,
92
  MVE_VHADD_T2,
93
  MVE_VHSUB_T1,
94
  MVE_VHSUB_T2,
95
  MVE_VRHADD,
96
  MVE_VLD2,
97
  MVE_VLD4,
98
  MVE_VST2,
99
  MVE_VST4,
100
  MVE_VLDRB_T1,
101
  MVE_VLDRH_T2,
102
  MVE_VLDRB_T5,
103
  MVE_VLDRH_T6,
104
  MVE_VLDRW_T7,
105
  MVE_VSTRB_T1,
106
  MVE_VSTRH_T2,
107
  MVE_VSTRB_T5,
108
  MVE_VSTRH_T6,
109
  MVE_VSTRW_T7,
110
  MVE_VLDRB_GATHER_T1,
111
  MVE_VLDRH_GATHER_T2,
112
  MVE_VLDRW_GATHER_T3,
113
  MVE_VLDRD_GATHER_T4,
114
  MVE_VLDRW_GATHER_T5,
115
  MVE_VLDRD_GATHER_T6,
116
  MVE_VSTRB_SCATTER_T1,
117
  MVE_VSTRH_SCATTER_T2,
118
  MVE_VSTRW_SCATTER_T3,
119
  MVE_VSTRD_SCATTER_T4,
120
  MVE_VSTRW_SCATTER_T5,
121
  MVE_VSTRD_SCATTER_T6,
122
  MVE_VCVT_FP_FIX_VEC,
123
  MVE_VCVT_BETWEEN_FP_INT,
124
  MVE_VCVT_FP_HALF_FP,
125
  MVE_VCVT_FROM_FP_TO_INT,
126
  MVE_VRINT_FP,
127
  MVE_VMOV_HFP_TO_GP,
128
  MVE_VMOV_GP_TO_VEC_LANE,
129
  MVE_VMOV_IMM_TO_VEC,
130
  MVE_VMOV_VEC_TO_VEC,
131
  MVE_VMOV2_VEC_LANE_TO_GP,
132
  MVE_VMOV2_GP_TO_VEC_LANE,
133
  MVE_VMOV_VEC_LANE_TO_GP,
134
  MVE_VMVN_IMM,
135
  MVE_VMVN_REG,
136
  MVE_VORR_IMM,
137
  MVE_VORR_REG,
138
  MVE_VORN,
139
  MVE_VBIC_IMM,
140
  MVE_VBIC_REG,
141
  MVE_VMOVX,
142
  MVE_VMOVL,
143
  MVE_VMOVN,
144
  MVE_VMULL_INT,
145
  MVE_VMULL_POLY,
146
  MVE_VQDMULL_T1,
147
  MVE_VQDMULL_T2,
148
  MVE_VQMOVN,
149
  MVE_VQMOVUN,
150
  MVE_VADDV,
151
  MVE_VMLADAV_T1,
152
  MVE_VMLADAV_T2,
153
  MVE_VMLALDAV,
154
  MVE_VMLAS,
155
  MVE_VADDLV,
156
  MVE_VMLSDAV_T1,
157
  MVE_VMLSDAV_T2,
158
  MVE_VMLSLDAV,
159
  MVE_VRMLALDAVH,
160
  MVE_VRMLSLDAVH,
161
  MVE_VQDMLADH,
162
  MVE_VQRDMLADH,
163
  MVE_VQDMLAH,
164
  MVE_VQRDMLAH,
165
  MVE_VQDMLASH,
166
  MVE_VQRDMLASH,
167
  MVE_VQDMLSDH,
168
  MVE_VQRDMLSDH,
169
  MVE_VQDMULH_T1,
170
  MVE_VQRDMULH_T2,
171
  MVE_VQDMULH_T3,
172
  MVE_VQRDMULH_T4,
173
  MVE_VDDUP,
174
  MVE_VDWDUP,
175
  MVE_VIWDUP,
176
  MVE_VIDUP,
177
  MVE_VCADD_FP,
178
  MVE_VCADD_VEC,
179
  MVE_VHCADD,
180
  MVE_VCMLA_FP,
181
  MVE_VCMUL_FP,
182
  MVE_VQRSHL_T1,
183
  MVE_VQRSHL_T2,
184
  MVE_VQRSHRN,
185
  MVE_VQRSHRUN,
186
  MVE_VQSHL_T1,
187
  MVE_VQSHL_T2,
188
  MVE_VQSHLU_T3,
189
  MVE_VQSHL_T4,
190
  MVE_VQSHRN,
191
  MVE_VQSHRUN,
192
  MVE_VRSHL_T1,
193
  MVE_VRSHL_T2,
194
  MVE_VRSHR,
195
  MVE_VRSHRN,
196
  MVE_VSHL_T1,
197
  MVE_VSHL_T2,
198
  MVE_VSHL_T3,
199
  MVE_VSHLC,
200
  MVE_VSHLL_T1,
201
  MVE_VSHLL_T2,
202
  MVE_VSHR,
203
  MVE_VSHRN,
204
  MVE_VSLI,
205
  MVE_VSRI,
206
  MVE_VADC,
207
  MVE_VABAV,
208
  MVE_VABD_FP,
209
  MVE_VABD_VEC,
210
  MVE_VABS_FP,
211
  MVE_VABS_VEC,
212
  MVE_VADD_FP_T1,
213
  MVE_VADD_FP_T2,
214
  MVE_VADD_VEC_T1,
215
  MVE_VADD_VEC_T2,
216
  MVE_VSBC,
217
  MVE_VSUB_FP_T1,
218
  MVE_VSUB_FP_T2,
219
  MVE_VSUB_VEC_T1,
220
  MVE_VSUB_VEC_T2,
221
  MVE_VAND,
222
  MVE_VBRSR,
223
  MVE_VCLS,
224
  MVE_VCLZ,
225
  MVE_VCTP,
226
  MVE_VMAX,
227
  MVE_VMAXA,
228
  MVE_VMAXNM_FP,
229
  MVE_VMAXNMA_FP,
230
  MVE_VMAXNMV_FP,
231
  MVE_VMAXNMAV_FP,
232
  MVE_VMAXV,
233
  MVE_VMAXAV,
234
  MVE_VMIN,
235
  MVE_VMINA,
236
  MVE_VMINNM_FP,
237
  MVE_VMINNMA_FP,
238
  MVE_VMINNMV_FP,
239
  MVE_VMINNMAV_FP,
240
  MVE_VMINV,
241
  MVE_VMINAV,
242
  MVE_VMLA,
243
  MVE_VMUL_FP_T1,
244
  MVE_VMUL_FP_T2,
245
  MVE_VMUL_VEC_T1,
246
  MVE_VMUL_VEC_T2,
247
  MVE_VMULH,
248
  MVE_VRMULH,
249
  MVE_VNEG_FP,
250
  MVE_VNEG_VEC,
251
  MVE_VPNOT,
252
  MVE_VPSEL,
253
  MVE_VQABS,
254
  MVE_VQADD_T1,
255
  MVE_VQADD_T2,
256
  MVE_VQSUB_T1,
257
  MVE_VQSUB_T2,
258
  MVE_VQNEG,
259
  MVE_VREV16,
260
  MVE_VREV32,
261
  MVE_VREV64,
262
  MVE_LSLL,
263
  MVE_LSLLI,
264
  MVE_LSRL,
265
  MVE_ASRL,
266
  MVE_ASRLI,
267
  MVE_SQRSHRL,
268
  MVE_SQRSHR,
269
  MVE_UQRSHL,
270
  MVE_UQRSHLL,
271
  MVE_UQSHL,
272
  MVE_UQSHLL,
273
  MVE_URSHRL,
274
  MVE_URSHR,
275
  MVE_SRSHRL,
276
  MVE_SRSHR,
277
  MVE_SQSHLL,
278
  MVE_SQSHL,
279
  MVE_CINC,
280
  MVE_CINV,
281
  MVE_CNEG,
282
  MVE_CSINC,
283
  MVE_CSINV,
284
  MVE_CSET,
285
  MVE_CSETM,
286
  MVE_CSNEG,
287
  MVE_CSEL,
288
  MVE_NONE
289
};
290
291
enum mve_unpredictable
292
{
293
  UNPRED_IT_BLOCK,    /* Unpredictable because mve insn in it block.
294
         */
295
  UNPRED_FCA_0_FCB_1,   /* Unpredictable because fcA = 0 and
296
           fcB = 1 (vpt).  */
297
  UNPRED_R13,     /* Unpredictable because r13 (sp) or
298
           r15 (sp) used.  */
299
  UNPRED_R15,     /* Unpredictable because r15 (pc) is used.  */
300
  UNPRED_Q_GT_4,    /* Unpredictable because
301
           vec reg start > 4 (vld4/st4).  */
302
  UNPRED_Q_GT_6,    /* Unpredictable because
303
           vec reg start > 6 (vld2/st2).  */
304
  UNPRED_R13_AND_WB,    /* Unpredictable becase gp reg = r13
305
           and WB bit = 1.  */
306
  UNPRED_Q_REGS_EQUAL,    /* Unpredictable because vector registers are
307
           equal.  */
308
  UNPRED_OS,      /* Unpredictable because offset scaled == 1.  */
309
  UNPRED_GP_REGS_EQUAL,   /* Unpredictable because gp registers are the
310
           same.  */
311
  UNPRED_Q_REGS_EQ_AND_SIZE_1,  /* Unpredictable because q regs equal and
312
           size = 1.  */
313
  UNPRED_Q_REGS_EQ_AND_SIZE_2,  /* Unpredictable because q regs equal and
314
           size = 2.  */
315
  UNPRED_NONE     /* No unpredictable behavior.  */
316
};
317
318
enum mve_undefined
319
{
320
  UNDEF_SIZE,     /* undefined size.  */
321
  UNDEF_SIZE_0,     /* undefined because size == 0.  */
322
  UNDEF_SIZE_2,     /* undefined because size == 2.  */
323
  UNDEF_SIZE_3,     /* undefined because size == 3.  */
324
  UNDEF_SIZE_LE_1,    /* undefined because size <= 1.  */
325
  UNDEF_SIZE_NOT_0,   /* undefined because size != 0.  */
326
  UNDEF_SIZE_NOT_2,   /* undefined because size != 2.  */
327
  UNDEF_SIZE_NOT_3,   /* undefined because size != 3.  */
328
  UNDEF_NOT_UNS_SIZE_0,   /* undefined because U == 0 and
329
           size == 0.  */
330
  UNDEF_NOT_UNS_SIZE_1,   /* undefined because U == 0 and
331
           size == 1.  */
332
  UNDEF_NOT_UNSIGNED,   /* undefined because U == 0.  */
333
  UNDEF_VCVT_IMM6,    /* imm6 < 32.  */
334
  UNDEF_VCVT_FSI_IMM6,    /* fsi = 0 and 32 >= imm6 <= 47.  */
335
  UNDEF_BAD_OP1_OP2,    /* undefined with op2 = 2 and
336
           op1 == (0 or 1).  */
337
  UNDEF_BAD_U_OP1_OP2,    /* undefined with U = 1 and
338
           op2 == 0 and op1 == (0 or 1).  */
339
  UNDEF_OP_0_BAD_CMODE,   /* undefined because op == 0 and cmode
340
           in {0xx1, x0x1}.  */
341
  UNDEF_XCHG_UNS,   /* undefined because X == 1 and U == 1.  */
342
  UNDEF_NONE      /* no undefined behavior.  */
343
};
344
345
struct opcode32
346
{
347
  arm_feature_set arch;   /* Architecture defining this insn.  */
348
  unsigned long value;    /* If arch is 0 then value is a sentinel.  */
349
  unsigned long mask;   /* Recognise insn if (op & mask) == value.  */
350
  const char *  assembler;  /* How to disassemble this insn.  */
351
};
352
353
struct cdeopcode32
354
{
355
  arm_feature_set arch;   /* Architecture defining this insn.  */
356
  uint8_t coproc_shift;   /* coproc is this far into op.  */
357
  uint16_t coproc_mask;   /* Length of coproc field in op.  */
358
  unsigned long value;    /* If arch is 0 then value is a sentinel.  */
359
  unsigned long mask;   /* Recognise insn if (op & mask) == value.  */
360
  const char *  assembler;  /* How to disassemble this insn.  */
361
};
362
363
/* MVE opcodes.  */
364
365
struct mopcode32
366
{
367
  arm_feature_set arch;   /* Architecture defining this insn.  */
368
  enum mve_instructions mve_op;  /* Specific mve instruction for faster
369
            decoding.  */
370
  unsigned long value;    /* If arch is 0 then value is a sentinel.  */
371
  unsigned long mask;   /* Recognise insn if (op & mask) == value.  */
372
  const char *  assembler;  /* How to disassemble this insn.  */
373
};
374
375
enum isa {
376
  ANY,
377
  T32,
378
  ARM
379
};
380
381
382
/* Shared (between Arm and Thumb mode) opcode.  */
383
struct sopcode32
384
{
385
  enum isa isa;     /* Execution mode instruction availability.  */
386
  arm_feature_set arch;   /* Architecture defining this insn.  */
387
  unsigned long value;    /* If arch is 0 then value is a sentinel.  */
388
  unsigned long mask;   /* Recognise insn if (op & mask) == value.  */
389
  const char *  assembler;  /* How to disassemble this insn.  */
390
};
391
392
struct opcode16
393
{
394
  arm_feature_set arch;   /* Architecture defining this insn.  */
395
  unsigned short value, mask; /* Recognise insn if (op & mask) == value.  */
396
  const char *assembler;  /* How to disassemble this insn.  */
397
};
398
399
/* print_insn_coprocessor recognizes the following format control codes:
400
401
   %%     %
402
403
   %c     print condition code (always bits 28-31 in ARM mode)
404
   %b     print condition code allowing cp_num == 9
405
   %q     print shifter argument
406
   %u     print condition code (unconditional in ARM mode,
407
                          UNPREDICTABLE if not AL in Thumb)
408
   %A     print address for ldc/stc/ldf/stf instruction
409
   %B     print vstm/vldm register list
410
   %C     print vscclrm register list
411
   %I                   print cirrus signed shift immediate: bits 0..3|4..6
412
   %J     print register for VLDR instruction
413
   %K     print address for VLDR instruction
414
   %F     print the COUNT field of a LFM/SFM instruction.
415
   %P     print floating point precision in arithmetic insn
416
   %Q     print floating point precision in ldf/stf insn
417
   %R     print floating point rounding mode
418
419
   %<bitfield>c   print as a condition code (for vsel)
420
   %<bitfield>r   print as an ARM register
421
   %<bitfield>R   as %<>r but r15 is UNPREDICTABLE
422
   %<bitfield>ru        as %<>r but each u register must be unique.
423
   %<bitfield>d   print the bitfield in decimal
424
   %<bitfield>k   print immediate for VFPv3 conversion instruction
425
   %<bitfield>x   print the bitfield in hex
426
   %<bitfield>X   print the bitfield as 1 hex digit without leading "0x"
427
   %<bitfield>f   print a floating point constant if >7 else a
428
      floating point register
429
   %<bitfield>w         print as an iWMMXt width field - [bhwd]ss/us
430
   %<bitfield>g         print as an iWMMXt 64-bit register
431
   %<bitfield>G         print as an iWMMXt general purpose or control register
432
   %<bitfield>D   print as a NEON D register
433
   %<bitfield>Q   print as a NEON Q register
434
   %<bitfield>V   print as a NEON D or Q register
435
   %<bitfield>E   print a quarter-float immediate value
436
437
   %y<code>   print a single precision VFP reg.
438
        Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
439
   %z<code>   print a double precision VFP reg
440
        Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
441
442
   %<bitfield>'c  print specified char iff bitfield is all ones
443
   %<bitfield>`c  print specified char iff bitfield is all zeroes
444
   %<bitfield>?ab...    select from array of values in big endian order
445
446
   %L     print as an iWMMXt N/M width field.
447
   %Z     print the Immediate of a WSHUFH instruction.
448
   %l     like 'A' except use byte offsets for 'B' & 'H'
449
      versions.
450
   %i     print 5-bit immediate in bits 8,3..0
451
      (print "32" when 0)
452
   %r     print register offset address for wldt/wstr instruction.  */
453
454
enum opcode_sentinel_enum
455
{
456
  SENTINEL_IWMMXT_START = 1,
457
  SENTINEL_IWMMXT_END,
458
  SENTINEL_GENERIC_START
459
} opcode_sentinels;
460
461
#define UNDEFINED_INSTRUCTION      "\t\t@ <UNDEFINED> instruction: %0-31x"
462
30.8k
#define UNKNOWN_INSTRUCTION_32BIT  "\t\t@ <UNDEFINED> instruction: %08x"
463
0
#define UNKNOWN_INSTRUCTION_16BIT  "\t\t@ <UNDEFINED> instruction: %04x"
464
195k
#define UNPREDICTABLE_INSTRUCTION  "\t@ <UNPREDICTABLE>"
465
466
/* Common coprocessor opcodes shared between Arm and Thumb-2.  */
467
468
/* print_insn_cde recognizes the following format control codes:
469
470
   %%     %
471
472
   %a     print 'a' iff bit 28 is 1
473
   %p     print bits 8-10 as coprocessor
474
   %<bitfield>d   print as decimal
475
   %<bitfield>r   print as an ARM register
476
   %<bitfield>n   print as an ARM register but r15 is APSR_nzcv
477
   %<bitfield>T   print as an ARM register + 1
478
   %<bitfield>R   as %r but r13 is UNPREDICTABLE
479
   %<bitfield>S   as %r but rX where X > 10 is UNPREDICTABLE
480
   %j     print immediate taken from bits (16..21,7,0..5)
481
   %k     print immediate taken from bits (20..21,7,0..5).
482
   %l     print immediate taken from bits (20..22,7,4..5).  */
483
484
/* At the moment there is only one valid position for the coprocessor number,
485
   and hence that's encoded in the macro below.  */
486
#define CDE_OPCODE(ARCH, VALUE, MASK, ASM) \
487
  { ARCH, 8, 7, VALUE, MASK, ASM }
488
static const struct cdeopcode32 cde_opcodes[] =
489
{
490
  /* Custom Datapath Extension instructions.  */
491
  CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
492
        0xee000000, 0xefc00840,
493
        "cx1%a\t%p, %12-15n, %{I:#%0-5,7,16-21d%}"),
494
  CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
495
        0xee000040, 0xefc00840,
496
        "cx1d%a\t%p, %12-15S, %12-15T, %{I:#%0-5,7,16-21d%}"),
497
498
  CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
499
        0xee400000, 0xefc00840,
500
        "cx2%a\t%p, %12-15n, %16-19n, %{I:#%0-5,7,20-21d%}"),
501
  CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
502
        0xee400040, 0xefc00840,
503
        "cx2d%a\t%p, %12-15S, %12-15T, %16-19n, %{I:#%0-5,7,20-21d%}"),
504
505
  CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
506
        0xee800000, 0xef800840,
507
        "cx3%a\t%p, %0-3n, %16-19n, %12-15n, %{I:#%4-5,7,20-22d%}"),
508
  CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
509
        0xee800040, 0xef800840,
510
       "cx3d%a\t%p, %0-3S, %0-3T, %16-19n, %12-15n, %{I:#%4-5,7,20-22d%}"),
511
512
  CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
513
        0xec200000, 0xeeb00840,
514
        "vcx1%a\t%p, %12-15,22V, %{I:#%0-5,7,16-19d%}"),
515
  CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
516
        0xec200040, 0xeeb00840,
517
        "vcx1%a\t%p, %12-15,22V, %{I:#%0-5,7,16-19,24d%}"),
518
519
  CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
520
        0xec300000, 0xeeb00840,
521
        "vcx2%a\t%p, %12-15,22V, %0-3,5V, %{I:#%4,7,16-19d%}"),
522
  CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
523
        0xec300040, 0xeeb00840,
524
        "vcx2%a\t%p, %12-15,22V, %0-3,5V, %{I:#%4,7,16-19,24d%}"),
525
526
  CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
527
        0xec800000, 0xee800840,
528
        "vcx3%a\t%p, %12-15,22V, %16-19,7V, %0-3,5V, %{I:#%4,20-21d%}"),
529
  CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
530
        0xec800040, 0xee800840,
531
        "vcx3%a\t%p, %12-15,22V, %16-19,7V, %0-3,5V, %{I:#%4,20-21,24d%}"),
532
533
  CDE_OPCODE (ARM_FEATURE_CORE_LOW (0), 0, 0, 0)
534
535
};
536
537
static const struct sopcode32 coprocessor_opcodes[] =
538
{
539
  /* XScale instructions.  */
540
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
541
    0x0e200010, 0x0fff0ff0,
542
    "mia%c\t%{R:acc0%}, %0-3r, %12-15r"},
543
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
544
    0x0e280010, 0x0fff0ff0,
545
    "miaph%c\t%{R:acc0%}, %0-3r, %12-15r"},
546
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
547
    0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\t%{R:acc0%}, %0-3r, %12-15r"},
548
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
549
    0x0c400000, 0x0ff00fff, "mar%c\t%{R:acc0%}, %12-15r, %16-19r"},
550
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
551
    0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, %{R:acc0%}"},
552
553
  /* Intel Wireless MMX technology instructions.  */
554
  {ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START, 0, "" },
555
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT),
556
    0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
557
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
558
    0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
559
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
560
    0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, %{I:#%0-2d%}"},
561
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
562
    0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, %{I:#%0-2d%}"},
563
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
564
    0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, %{I:#%0-2d%}"},
565
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
566
    0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
567
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
568
    0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
569
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
570
    0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
571
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
572
    0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
573
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
574
    0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
575
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
576
    0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
577
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
578
    0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
579
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
580
    0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
581
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
582
    0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
583
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
584
    0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
585
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
586
    0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
587
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
588
    0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
589
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
590
    0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
591
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
592
    0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
593
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
594
    0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
595
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
596
    0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, %{I:#%20-22d%}"},
597
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
598
    0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
599
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
600
    0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
601
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
602
    0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
603
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
604
    0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"},
605
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
606
    0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
607
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
608
    0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
609
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
610
    0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"},
611
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
612
    0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
613
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
614
    0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
615
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
616
    0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
617
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
618
    0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"},
619
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
620
    0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"},
621
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
622
    0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
623
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
624
    0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, %{I:#%21-23d%}"},
625
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
626
    0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
627
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
628
    0x0e800120, 0x0f800ff0,
629
    "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
630
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
631
    0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
632
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
633
    0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"},
634
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
635
    0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"},
636
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
637
    0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"},
638
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
639
    0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"},
640
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
641
    0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"},
642
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
643
    0x0e8000a0, 0x0f800ff0,
644
    "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
645
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
646
    0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"},
647
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
648
    0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"},
649
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
650
    0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
651
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
652
    0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
653
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
654
    0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, %{I:#%i%}"},
655
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
656
    0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
657
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
658
    0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"},
659
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
660
    0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
661
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
662
    0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, %{I:#%Z%}"},
663
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
664
    0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, %{I:#%i%}"},
665
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
666
    0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
667
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
668
    0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
669
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
670
    0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, %{I:#%i%}"},
671
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
672
    0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
673
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
674
    0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
675
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
676
    0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, %{I:#%i%}"},
677
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
678
    0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
679
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
680
    0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
681
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
682
    0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"},
683
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
684
    0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
685
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
686
    0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
687
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
688
    0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
689
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
690
    0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"},
691
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
692
    0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"},
693
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
694
    0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"},
695
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
696
    0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"},
697
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
698
    0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
699
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
700
    0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
701
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
702
    0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
703
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
704
    0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
705
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
706
    0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
707
  {ANY, ARM_FEATURE_CORE_LOW (0),
708
    SENTINEL_IWMMXT_END, 0, "" },
709
710
  /* Floating point coprocessor (FPA) instructions.  */
711
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
712
    0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
713
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
714
    0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
715
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
716
    0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
717
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
718
    0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
719
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
720
    0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
721
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
722
    0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
723
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
724
    0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
725
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
726
    0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
727
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
728
    0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
729
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
730
    0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
731
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
732
    0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
733
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
734
    0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
735
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
736
    0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
737
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
738
    0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
739
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
740
    0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
741
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
742
    0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
743
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
744
    0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
745
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
746
    0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
747
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
748
    0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
749
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
750
    0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
751
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
752
    0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
753
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
754
    0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
755
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
756
    0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
757
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
758
    0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
759
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
760
    0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
761
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
762
    0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
763
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
764
    0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
765
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
766
    0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
767
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
768
    0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
769
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
770
    0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
771
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
772
    0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
773
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
774
    0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
775
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
776
    0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
777
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
778
    0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
779
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
780
    0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
781
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
782
    0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
783
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
784
    0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
785
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
786
    0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
787
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
788
    0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
789
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
790
    0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
791
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
792
    0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
793
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
794
    0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
795
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
796
    0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
797
798
  /* Armv8.1-M Mainline instructions.  */
799
  {T32, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
800
    0xec9f0b00, 0xffbf0f01, "vscclrm%c\t%C"},
801
  {T32, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
802
    0xec9f0a00, 0xffbf0f00, "vscclrm%c\t%C"},
803
804
  /* ARMv8-M Mainline Security Extensions instructions.  */
805
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
806
    0xec300a00, 0xfff0ffff, "vlldm\t%16-19r"},
807
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
808
    0xec200a00, 0xfff0ffff, "vlstm\t%16-19r"},
809
810
  /* Register load/store.  */
811
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
812
    0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
813
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
814
    0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"},
815
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
816
    0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"},
817
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
818
    0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
819
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
820
    0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"},
821
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
822
    0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
823
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
824
    0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"},
825
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
826
    0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"},
827
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
828
    0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"},
829
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
830
    0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"},
831
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
832
    0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"},
833
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
834
    0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"},
835
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
836
    0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"},
837
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
838
    0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"},
839
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
840
    0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"},
841
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
842
    0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"},
843
  {ANY, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN),
844
    0xec100f80, 0xfe101f80, "vldr%c\t%J, %K"},
845
  {ANY, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN),
846
    0xec000f80, 0xfe101f80, "vstr%c\t%J, %K"},
847
848
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
849
    0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t@ Deprecated"},
850
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
851
    0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t@ Deprecated"},
852
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
853
    0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t@ Deprecated"},
854
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
855
    0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t@ Deprecated"},
856
857
  /* Data transfer between ARM and NEON registers.  */
858
  {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
859
    0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
860
  {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
861
    0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
862
  {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
863
    0x0e000b10, 0x0fd00f70, "vmov%c.32\t%{R:%16-19,7D[%21d]%}, %12-15r"},
864
  {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
865
    0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %{R:%16-19,7D[%21d]%}"},
866
  {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
867
    0x0e000b30, 0x0fd00f30, "vmov%c.16\t%{R:%16-19,7D[%6,21d]%}, %12-15r"},
868
  {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
869
    0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %{R:%16-19,7D[%6,21d]%}"},
870
  {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
871
    0x0e400b10, 0x0fd00f10, "vmov%c.8\t%{R:%16-19,7D[%5,6,21d]%}, %12-15r"},
872
  {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
873
    0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %{R:%16-19,7D[%5,6,21d]%}"},
874
  /* Half-precision conversion instructions.  */
875
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
876
    0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"},
877
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
878
    0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"},
879
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
880
    0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"},
881
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
882
    0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"},
883
884
  /* Floating point coprocessor (VFP) instructions.  */
885
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
886
    0x0ee00a10, 0x0fff0fff, "vmsr%c\t%{R:fpsid%}, %12-15r"},
887
  {ANY, ARM_FEATURE (0, ARM_EXT2_V8_1M_MAIN, FPU_VFP_EXT_V1xD),
888
    0x0ee10a10, 0x0fff0fff, "vmsr%c\t%{R:fpscr%}, %12-15r"},
889
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
890
    0x0ee20a10, 0x0fff0fff, "vmsr%c\t%{R:fpscr_nzcvqc%}, %12-15r"},
891
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
892
    0x0ee60a10, 0x0fff0fff, "vmsr%c\t%{R:mvfr1%}, %12-15r"},
893
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
894
    0x0ee70a10, 0x0fff0fff, "vmsr%c\t%{R:mvfr0%}, %12-15r"},
895
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
896
    0x0ee50a10, 0x0fff0fff, "vmsr%c\t%{R:mvfr2%}, %12-15r"},
897
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
898
    0x0ee80a10, 0x0fff0fff, "vmsr%c\t%{R:fpexc%}, %12-15r"},
899
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
900
    0x0ee90a10, 0x0fff0fff, "vmsr%c\t%{R:fpinst%}, %12-15r\t@ Impl def"},
901
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
902
    0x0eea0a10, 0x0fff0fff, "vmsr%c\t%{R:fpinst2%}, %12-15r\t@ Impl def"},
903
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
904
    0x0eec0a10, 0x0fff0fff, "vmsr%c\t%{R:vpr%}, %12-15r"},
905
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
906
    0x0eed0a10, 0x0fff0fff, "vmsr%c\t%{R:p0%}, %12-15r"},
907
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
908
    0x0eee0a10, 0x0fff0fff, "vmsr%c\t%{R:fpcxt_ns%}, %12-15r"},
909
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
910
    0x0eef0a10, 0x0fff0fff, "vmsr%c\t%{R:fpcxt_s%}, %12-15r"},
911
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
912
    0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpsid%}"},
913
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
914
    0x0ef1fa10, 0x0fffffff, "vmrs%c\t%{R:APSR_nzcv%}, %{R:fpscr%}"},
915
  {ANY, ARM_FEATURE (0, ARM_EXT2_V8_1M_MAIN, FPU_VFP_EXT_V1xD),
916
    0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpscr%}"},
917
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
918
    0x0ef20a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpscr_nzcvqc%}"},
919
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
920
    0x0ef50a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:mvfr2%}"},
921
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
922
    0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:mvfr1%}"},
923
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
924
    0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:mvfr0%}"},
925
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
926
    0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpexc%}"},
927
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
928
    0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpinst%}\t@ Impl def"},
929
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
930
    0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpinst2%}\t@ Impl def"},
931
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
932
    0x0efc0a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:vpr%}"},
933
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
934
    0x0efd0a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:p0%}"},
935
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
936
    0x0efe0a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpcxt_ns%}"},
937
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
938
    0x0eff0a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpcxt_s%}"},
939
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
940
    0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%{I:%21d%}], %12-15r"},
941
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
942
    0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%{I:%21d%}]"},
943
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
944
    0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"},
945
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
946
    0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"},
947
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
948
    0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"},
949
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
950
    0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"},
951
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
952
    0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, %{I:#0.0%}"},
953
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
954
    0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, %{I:#0.0%}"},
955
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
956
    0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"},
957
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
958
    0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"},
959
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
960
    0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"},
961
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
962
    0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"},
963
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
964
    0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"},
965
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
966
    0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"},
967
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
968
    0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"},
969
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
970
    0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"},
971
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
972
    0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"},
973
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
974
    0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"},
975
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
976
    0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"},
977
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
978
    0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"},
979
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
980
    0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"},
981
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
982
    0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"},
983
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
984
    0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, %{I:#%5,0-3k%}"},
985
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
986
    0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, %{I:#%5,0-3k%}"},
987
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
988
    0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"},
989
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
990
    0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"},
991
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
992
    0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, %{I:#%5,0-3k%}"},
993
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
994
    0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, %{I:#%5,0-3k%}"},
995
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
996
    0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"},
997
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
998
    0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, %{I:#%0-3,16-19E%}"},
999
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
1000
    0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, %{I:#%0-3,16-19E%}"},
1001
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
1002
    0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"},
1003
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
1004
    0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"},
1005
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
1006
    0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"},
1007
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
1008
    0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"},
1009
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
1010
    0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"},
1011
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
1012
    0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"},
1013
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
1014
    0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"},
1015
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
1016
    0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"},
1017
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
1018
    0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"},
1019
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
1020
    0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"},
1021
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
1022
    0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"},
1023
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
1024
    0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"},
1025
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
1026
    0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"},
1027
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
1028
    0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"},
1029
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
1030
    0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"},
1031
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
1032
    0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"},
1033
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
1034
    0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"},
1035
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
1036
    0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"},
1037
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
1038
    0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"},
1039
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
1040
    0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"},
1041
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
1042
    0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"},
1043
1044
  /* Cirrus coprocessor instructions.  */
1045
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1046
    0x0d100400, 0x0f500f00, "cfldrs%c\t%{R:mvf%12-15d%}, %A"},
1047
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1048
    0x0c100400, 0x0f500f00, "cfldrs%c\t%{R:mvf%12-15d%}, %A"},
1049
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1050
    0x0d500400, 0x0f500f00, "cfldrd%c\t%{R:mvd%12-15d%}, %A"},
1051
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1052
    0x0c500400, 0x0f500f00, "cfldrd%c\t%{R:mvd%12-15d%}, %A"},
1053
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1054
    0x0d100500, 0x0f500f00, "cfldr32%c\t%{R:mvfx%12-15d%}, %A"},
1055
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1056
    0x0c100500, 0x0f500f00, "cfldr32%c\t%{R:mvfx%12-15d%}, %A"},
1057
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1058
    0x0d500500, 0x0f500f00, "cfldr64%c\t%{R:mvdx%12-15d%}, %A"},
1059
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1060
    0x0c500500, 0x0f500f00, "cfldr64%c\t%{R:mvdx%12-15d%}, %A"},
1061
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1062
    0x0d000400, 0x0f500f00, "cfstrs%c\t%{R:mvf%12-15d%}, %A"},
1063
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1064
    0x0c000400, 0x0f500f00, "cfstrs%c\t%{R:mvf%12-15d%}, %A"},
1065
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1066
    0x0d400400, 0x0f500f00, "cfstrd%c\t%{R:mvd%12-15d%}, %A"},
1067
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1068
    0x0c400400, 0x0f500f00, "cfstrd%c\t%{R:mvd%12-15d%}, %A"},
1069
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1070
    0x0d000500, 0x0f500f00, "cfstr32%c\t%{R:mvfx%12-15d%}, %A"},
1071
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1072
    0x0c000500, 0x0f500f00, "cfstr32%c\t%{R:mvfx%12-15d%}, %A"},
1073
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1074
    0x0d400500, 0x0f500f00, "cfstr64%c\t%{R:mvdx%12-15d%}, %A"},
1075
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1076
    0x0c400500, 0x0f500f00, "cfstr64%c\t%{R:mvdx%12-15d%}, %A"},
1077
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1078
    0x0e000450, 0x0ff00ff0, "cfmvsr%c\t%{R:mvf%16-19d%}, %12-15r"},
1079
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1080
    0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, %{R:mvf%16-19d%}"},
1081
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1082
    0x0e000410, 0x0ff00ff0, "cfmvdlr%c\t%{R:mvd%16-19d%}, %12-15r"},
1083
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1084
    0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, %{R:mvd%16-19d%}"},
1085
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1086
    0x0e000430, 0x0ff00ff0, "cfmvdhr%c\t%{R:mvd%16-19d%}, %12-15r"},
1087
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1088
    0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, %{R:mvd%16-19d%}"},
1089
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1090
    0x0e000510, 0x0ff00fff, "cfmv64lr%c\t%{R:mvdx%16-19d%}, %12-15r"},
1091
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1092
    0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, %{R:mvdx%16-19d%}"},
1093
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1094
    0x0e000530, 0x0ff00fff, "cfmv64hr%c\t%{R:mvdx%16-19d%}, %12-15r"},
1095
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1096
    0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, %{R:mvdx%16-19d%}"},
1097
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1098
    0x0e200440, 0x0ff00fff, "cfmval32%c\t%{R:mvax%12-15d%}, %{R:mvfx%16-19d%}"},
1099
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1100
    0x0e100440, 0x0ff00fff, "cfmv32al%c\t%{R:mvfx%12-15d%}, %{R:mvax%16-19d%}"},
1101
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1102
    0x0e200460, 0x0ff00fff, "cfmvam32%c\t%{R:mvax%12-15d%}, %{R:mvfx%16-19d%}"},
1103
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1104
    0x0e100460, 0x0ff00fff, "cfmv32am%c\t%{R:mvfx%12-15d%}, %{R:mvax%16-19d%}"},
1105
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1106
    0x0e200480, 0x0ff00fff, "cfmvah32%c\t%{R:mvax%12-15d%}, %{R:mvfx%16-19d%}"},
1107
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1108
    0x0e100480, 0x0ff00fff, "cfmv32ah%c\t%{R:mvfx%12-15d%}, %{R:mvax%16-19d%}"},
1109
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1110
    0x0e2004a0, 0x0ff00fff, "cfmva32%c\t%{R:mvax%12-15d%}, %{R:mvfx%16-19d%}"},
1111
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1112
    0x0e1004a0, 0x0ff00fff, "cfmv32a%c\t%{R:mvfx%12-15d%}, %{R:mvax%16-19d%}"},
1113
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1114
    0x0e2004c0, 0x0ff00fff, "cfmva64%c\t%{R:mvax%12-15d%}, %{R:mvdx%16-19d%}"},
1115
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1116
    0x0e1004c0, 0x0ff00fff, "cfmv64a%c\t%{R:mvdx%12-15d%}, %{R:mvax%16-19d%}"},
1117
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1118
    0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\t%{R:dspsc%}, %{R:mvdx%12-15d%}"},
1119
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1120
    0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\t%{R:mvdx%12-15d%}, %{R:dspsc%}"},
1121
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1122
    0x0e000400, 0x0ff00fff, "cfcpys%c\t%{R:mvf%12-15d%}, %{R:mvf%16-19d%}"},
1123
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1124
    0x0e000420, 0x0ff00fff, "cfcpyd%c\t%{R:mvd%12-15d%}, %{R:mvd%16-19d%}"},
1125
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1126
    0x0e000460, 0x0ff00fff, "cfcvtsd%c\t%{R:mvd%12-15d%}, %{R:mvf%16-19d%}"},
1127
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1128
    0x0e000440, 0x0ff00fff, "cfcvtds%c\t%{R:mvf%12-15d%}, %{R:mvd%16-19d%}"},
1129
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1130
    0x0e000480, 0x0ff00fff, "cfcvt32s%c\t%{R:mvf%12-15d%}, %{R:mvfx%16-19d%}"},
1131
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1132
    0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\t%{R:mvd%12-15d%}, %{R:mvfx%16-19d%}"},
1133
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1134
    0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\t%{R:mvf%12-15d%}, %{R:mvdx%16-19d%}"},
1135
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1136
    0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\t%{R:mvd%12-15d%}, %{R:mvdx%16-19d%}"},
1137
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1138
    0x0e100580, 0x0ff00fff, "cfcvts32%c\t%{R:mvfx%12-15d%}, %{R:mvf%16-19d%}"},
1139
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1140
    0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\t%{R:mvfx%12-15d%}, %{R:mvd%16-19d%}"},
1141
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1142
    0x0e1005c0, 0x0ff00fff, "cftruncs32%c\t%{R:mvfx%12-15d%}, %{R:mvf%16-19d%}"},
1143
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1144
    0x0e1005e0, 0x0ff00fff, "cftruncd32%c\t%{R:mvfx%12-15d%}, %{R:mvd%16-19d%}"},
1145
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1146
    0x0e000550, 0x0ff00ff0, "cfrshl32%c\t%{R:mvfx%16-19d%}, %{R:mvfx%0-3d%}, %12-15r"},
1147
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1148
    0x0e000570, 0x0ff00ff0, "cfrshl64%c\t%{R:mvdx%16-19d%}, %{R:mvdx%0-3d%}, %12-15r"},
1149
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1150
    0x0e000500, 0x0ff00f10, "cfsh32%c\t%{R:mvfx%12-15d%}, %{R:mvfx%16-19d%}, %{I:#%I%}"},
1151
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1152
    0x0e200500, 0x0ff00f10, "cfsh64%c\t%{R:mvdx%12-15d%}, %{R:mvdx%16-19d%}, %{I:#%I%}"},
1153
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1154
    0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, %{R:mvf%16-19d%}, %{R:mvf%0-3d%}"},
1155
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1156
    0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, %{R:mvd%16-19d%}, %{R:mvd%0-3d%}"},
1157
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1158
    0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, %{R:mvfx%16-19d%}, %{R:mvfx%0-3d%}"},
1159
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1160
    0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, %{R:mvdx%16-19d%}, %{R:mvdx%0-3d%}"},
1161
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1162
    0x0e300400, 0x0ff00fff, "cfabss%c\t%{R:mvf%12-15d%}, %{R:mvf%16-19d%}"},
1163
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1164
    0x0e300420, 0x0ff00fff, "cfabsd%c\t%{R:mvd%12-15d%}, %{R:mvd%16-19d%}"},
1165
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1166
    0x0e300440, 0x0ff00fff, "cfnegs%c\t%{R:mvf%12-15d%}, %{R:mvf%16-19d%}"},
1167
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1168
    0x0e300460, 0x0ff00fff, "cfnegd%c\t%{R:mvd%12-15d%}, %{R:mvd%16-19d%}"},
1169
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1170
    0x0e300480, 0x0ff00ff0, "cfadds%c\t%{R:mvf%12-15d%}, %{R:mvf%16-19d%}, %{R:mvf%0-3d%}"},
1171
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1172
    0x0e3004a0, 0x0ff00ff0, "cfaddd%c\t%{R:mvd%12-15d%}, %{R:mvd%16-19d%}, %{R:mvd%0-3d%}"},
1173
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1174
    0x0e3004c0, 0x0ff00ff0, "cfsubs%c\t%{R:mvf%12-15d%}, %{R:mvf%16-19d%}, %{R:mvf%0-3d%}"},
1175
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1176
    0x0e3004e0, 0x0ff00ff0, "cfsubd%c\t%{R:mvd%12-15d%}, %{R:mvd%16-19d%}, %{R:mvd%0-3d%}"},
1177
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1178
    0x0e100400, 0x0ff00ff0, "cfmuls%c\t%{R:mvf%12-15d%}, %{R:mvf%16-19d%}, %{R:mvf%0-3d%}"},
1179
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1180
    0x0e100420, 0x0ff00ff0, "cfmuld%c\t%{R:mvd%12-15d%}, %{R:mvd%16-19d%}, %{R:mvd%0-3d%}"},
1181
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1182
    0x0e300500, 0x0ff00fff, "cfabs32%c\t%{R:mvfx%12-15d%}, %{R:mvfx%16-19d%}"},
1183
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1184
    0x0e300520, 0x0ff00fff, "cfabs64%c\t%{R:mvdx%12-15d%}, %{R:mvdx%16-19d%}"},
1185
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1186
    0x0e300540, 0x0ff00fff, "cfneg32%c\t%{R:mvfx%12-15d%}, %{R:mvfx%16-19d%}"},
1187
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1188
    0x0e300560, 0x0ff00fff, "cfneg64%c\t%{R:mvdx%12-15d%}, %{R:mvdx%16-19d%}"},
1189
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1190
    0x0e300580, 0x0ff00ff0, "cfadd32%c\t%{R:mvfx%12-15d%}, %{R:mvfx%16-19d%}, %{R:mvfx%0-3d%}"},
1191
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1192
    0x0e3005a0, 0x0ff00ff0, "cfadd64%c\t%{R:mvdx%12-15d%}, %{R:mvdx%16-19d%}, %{R:mvdx%0-3d%}"},
1193
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1194
    0x0e3005c0, 0x0ff00ff0, "cfsub32%c\t%{R:mvfx%12-15d%}, %{R:mvfx%16-19d%}, %{R:mvfx%0-3d%}"},
1195
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1196
    0x0e3005e0, 0x0ff00ff0, "cfsub64%c\t%{R:mvdx%12-15d%}, %{R:mvdx%16-19d%}, %{R:mvdx%0-3d%}"},
1197
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1198
    0x0e100500, 0x0ff00ff0, "cfmul32%c\t%{R:mvfx%12-15d%}, %{R:mvfx%16-19d%}, %{R:mvfx%0-3d%}"},
1199
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1200
    0x0e100520, 0x0ff00ff0, "cfmul64%c\t%{R:mvdx%12-15d%}, %{R:mvdx%16-19d%}, %{R:mvdx%0-3d%}"},
1201
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1202
    0x0e100540, 0x0ff00ff0, "cfmac32%c\t%{R:mvfx%12-15d%}, %{R:mvfx%16-19d%}, %{R:mvfx%0-3d%}"},
1203
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1204
    0x0e100560, 0x0ff00ff0, "cfmsc32%c\t%{R:mvfx%12-15d%}, %{R:mvfx%16-19d%}, %{R:mvfx%0-3d%}"},
1205
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1206
    0x0e000600, 0x0ff00f10,
1207
    "cfmadd32%c\t%{R:mvax%5-7d%}, %{R:mvfx%12-15d%}, %{R:mvfx%16-19d%}, %{R:mvfx%0-3d%}"},
1208
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1209
    0x0e100600, 0x0ff00f10,
1210
    "cfmsub32%c\t%{R:mvax%5-7d%}, %{R:mvfx%12-15d%}, %{R:mvfx%16-19d%}, %{R:mvfx%0-3d%}"},
1211
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1212
    0x0e200600, 0x0ff00f10,
1213
    "cfmadda32%c\t%{R:mvax%5-7d%}, %{R:mvax%12-15d%}, %{R:mvfx%16-19d%}, %{R:mvfx%0-3d%}"},
1214
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1215
    0x0e300600, 0x0ff00f10,
1216
    "cfmsuba32%c\t%{R:mvax%5-7d%}, %{R:mvax%12-15d%}, %{R:mvfx%16-19d%}, %{R:mvfx%0-3d%}"},
1217
1218
  /* VFP Fused multiply add instructions.  */
1219
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
1220
    0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"},
1221
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
1222
    0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"},
1223
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
1224
    0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"},
1225
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
1226
    0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"},
1227
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
1228
    0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"},
1229
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
1230
    0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"},
1231
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
1232
    0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"},
1233
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
1234
    0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"},
1235
1236
  /* FP v5.  */
1237
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1238
    0xfe000a00, 0xff800f50, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
1239
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1240
    0xfe000b00, 0xff800f50, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
1241
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1242
    0xfe800a00, 0xffb00f50, "vmaxnm%u.f32\t%y1, %y2, %y0"},
1243
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1244
    0xfe800b00, 0xffb00f50, "vmaxnm%u.f64\t%z1, %z2, %z0"},
1245
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1246
    0xfe800a40, 0xffb00f50, "vminnm%u.f32\t%y1, %y2, %y0"},
1247
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1248
    0xfe800b40, 0xffb00f50, "vminnm%u.f64\t%z1, %z2, %z0"},
1249
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1250
    0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"},
1251
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1252
    0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"},
1253
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1254
    0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"},
1255
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1256
    0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"},
1257
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1258
    0xfeb80a40, 0xffbc0fd0, "vrint%16-17?mpna%u.f32\t%y1, %y0"},
1259
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1260
    0xfeb80b40, 0xffbc0fd0, "vrint%16-17?mpna%u.f64\t%z1, %z0"},
1261
1262
  {ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START, 0, "" },
1263
  /* ARMv8.3 AdvSIMD instructions in the space of coprocessor 8.  */
1264
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1265
    0xfc800800, 0xfeb00f10, "vcadd%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, %{I:#%24?29%24'70%}"},
1266
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1267
    0xfc900800, 0xfeb00f10, "vcadd%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, %{I:#%24?29%24'70%}"},
1268
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1269
    0xfc200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, %{I:#%23'90%}"},
1270
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1271
    0xfd200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, %{I:#%23?21%23?780%}"},
1272
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1273
    0xfc300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, %{I:#%23'90%}"},
1274
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1275
    0xfd300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, %{I:#%23?21%23?780%}"},
1276
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1277
    0xfe000800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %{R:%0-3D[%5?10]%}, %{I:#%20'90%}"},
1278
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1279
    0xfe200800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %{R:%0-3D[%5?10]%}, %{I:#%20?21%20?780%}"},
1280
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1281
    0xfe800800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %{R:%0-3,5D[0]%}, %{I:#%20'90%}"},
1282
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1283
    0xfea00800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %{R:%0-3,5D[0]%}, %{I:#%20?21%20?780%}"},
1284
1285
  /* BFloat16 instructions.  */
1286
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1287
    0x0eb30940, 0x0fbf0f50, "vcvt%7?tb%b.bf16.f32\t%y1, %y0"},
1288
1289
  /* Dot Product instructions in the space of coprocessor 13.  */
1290
  {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
1291
    0xfc200d00, 0xffb00f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3,5V"},
1292
  {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
1293
    0xfe200d00, 0xff200f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %{R:%0-3D[%5?10]%}"},
1294
1295
  /* ARMv8.2 FMAC Long instructions in the space of coprocessor 8.  */
1296
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1297
    0xfc200810, 0xffb00f50, "vfmal.f16\t%12-15,22D, %{R:s%7,16-19d%}, %{R:s%5,0-3d%}"},
1298
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1299
    0xfca00810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, %{R:s%7,16-19d%}, %{R:s%5,0-3d%}"},
1300
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1301
    0xfc200850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, %{R:d%16-19,7d%}, %{R:d%0-3,5d%}"},
1302
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1303
    0xfca00850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, %{R:d%16-19,7d%}, %{R:d%0-3,5d%}"},
1304
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1305
    0xfe000810, 0xffb00f50, "vfmal.f16\t%12-15,22D, %{R:s%7,16-19d%}, %{R:s%5,0-2d[%3d]%}"},
1306
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1307
    0xfe100810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, %{R:s%7,16-19d%}, %{R:s%5,0-2d[%3d]%}"},
1308
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1309
    0xfe000850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, %{R:d%16-19,7d%}, %{R:d%0-2d[%3,5d]%}"},
1310
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1311
    0xfe100850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, %{R:d%16-19,7d%}, %{R:d%0-2d[%3,5d]%}"},
1312
1313
  /* ARMv8.2 half-precision Floating point coprocessor 9 (VFP) instructions.
1314
     cp_num: bit <11:8> == 0b1001.
1315
     cond: bit <31:28> == 0b1110, otherwise, it's UNPREDICTABLE.  */
1316
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1317
    0x0eb009c0, 0x0fbf0fd0, "vabs%c.f16\t%y1, %y0"},
1318
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1319
    0x0e300900, 0x0fb00f50, "vadd%c.f16\t%y1, %y2, %y0"},
1320
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1321
    0x0eb40940, 0x0fbf0f50, "vcmp%7'e%c.f16\t%y1, %y0"},
1322
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1323
    0x0eb50940, 0x0fbf0f70, "vcmp%7'e%c.f16\t%y1, %{I:#0.0%}"},
1324
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1325
    0x0eba09c0, 0x0fbe0fd0, "vcvt%c.f16.%16?us%7?31%7?26\t%y1, %y1, %{I:#%5,0-3k%}"},
1326
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1327
    0x0ebe09c0, 0x0fbe0fd0, "vcvt%c.%16?us%7?31%7?26.f16\t%y1, %y1, %{I:#%5,0-3k%}"},
1328
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1329
    0x0ebc0940, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f16\t%y1, %y0"},
1330
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1331
    0x0eb80940, 0x0fbf0f50, "vcvt%c.f16.%7?su32\t%y1, %y0"},
1332
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1333
    0xfebc0940, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f16\t%y1, %y0"},
1334
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1335
    0x0e800900, 0x0fb00f50, "vdiv%c.f16\t%y1, %y2, %y0"},
1336
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1337
    0x0ea00900, 0x0fb00f50, "vfma%c.f16\t%y1, %y2, %y0"},
1338
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1339
    0x0ea00940, 0x0fb00f50, "vfms%c.f16\t%y1, %y2, %y0"},
1340
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1341
    0x0e900940, 0x0fb00f50, "vfnma%c.f16\t%y1, %y2, %y0"},
1342
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1343
    0x0e900900, 0x0fb00f50, "vfnms%c.f16\t%y1, %y2, %y0"},
1344
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1345
    0xfeb00ac0, 0xffbf0fd0, "vins.f16\t%y1, %y0"},
1346
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1347
    0xfeb00a40, 0xffbf0fd0, "vmovx%c.f16\t%y1, %y0"},
1348
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1349
    0x0d100900, 0x0f300f00, "vldr%c.16\t%y1, %A"},
1350
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1351
    0x0d000900, 0x0f300f00, "vstr%c.16\t%y1, %A"},
1352
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1353
    0xfe800900, 0xffb00f50, "vmaxnm%c.f16\t%y1, %y2, %y0"},
1354
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1355
    0xfe800940, 0xffb00f50, "vminnm%c.f16\t%y1, %y2, %y0"},
1356
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1357
    0x0e000900, 0x0fb00f50, "vmla%c.f16\t%y1, %y2, %y0"},
1358
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1359
    0x0e000940, 0x0fb00f50, "vmls%c.f16\t%y1, %y2, %y0"},
1360
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1361
    0x0e100910, 0x0ff00f7f, "vmov%c.f16\t%12-15r, %y2"},
1362
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1363
    0x0e000910, 0x0ff00f7f, "vmov%c.f16\t%y2, %12-15r"},
1364
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1365
    0xeb00900, 0x0fb00ff0, "vmov%c.f16\t%y1, %{I:#%0-3,16-19E%}"},
1366
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1367
    0x0e200900, 0x0fb00f50, "vmul%c.f16\t%y1, %y2, %y0"},
1368
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1369
    0x0eb10940, 0x0fbf0fd0, "vneg%c.f16\t%y1, %y0"},
1370
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1371
    0x0e100940, 0x0fb00f50, "vnmla%c.f16\t%y1, %y2, %y0"},
1372
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1373
    0x0e100900, 0x0fb00f50, "vnmls%c.f16\t%y1, %y2, %y0"},
1374
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1375
    0x0e200940, 0x0fb00f50, "vnmul%c.f16\t%y1, %y2, %y0"},
1376
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1377
    0x0eb60940, 0x0fbe0f50, "vrint%7,16??xzr%c.f16\t%y1, %y0"},
1378
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1379
    0xfeb80940, 0xffbc0fd0, "vrint%16-17?mpna%u.f16\t%y1, %y0"},
1380
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1381
    0xfe000900, 0xff800f50, "vsel%20-21c%u.f16\t%y1, %y2, %y0"},
1382
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1383
    0x0eb109c0, 0x0fbf0fd0, "vsqrt%c.f16\t%y1, %y0"},
1384
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1385
    0x0e300940, 0x0fb00f50, "vsub%c.f16\t%y1, %y2, %y0"},
1386
1387
  /* ARMv8.3 javascript conversion instruction.  */
1388
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1389
    0x0eb90bc0, 0x0fbf0fd0, "vjcvt%c.s32.f64\t%y1, %z0"},
1390
1391
  {ANY, ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
1392
};
1393
1394
/* Generic coprocessor instructions.  These are only matched if a more specific
1395
   SIMD or co-processor instruction does not match first.  */
1396
1397
static const struct sopcode32 generic_coprocessor_opcodes[] =
1398
{
1399
  /* Generic coprocessor instructions.  */
1400
  {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
1401
    0x0c400000, 0x0ff00000, "mcrr%c\t%{I:%8-11d%}, %{I:%4-7d%}, %12-15R, %16-19r, %{R:cr%0-3d%}"},
1402
  {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
1403
    0x0c500000, 0x0ff00000,
1404
    "mrrc%c\t%{I:%8-11d%}, %{I:%4-7d%}, %12-15Ru, %16-19Ru, %{R:cr%0-3d%}"},
1405
  {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1406
    0x0e000000, 0x0f000010,
1407
    "cdp%c\t%{I:%8-11d%}, %{I:%20-23d%}, %{R:cr%12-15d%}, %{R:cr%16-19d%}, %{R:cr%0-3d%}, {%{I:%5-7d%}}"},
1408
  {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1409
    0x0e10f010, 0x0f10f010,
1410
    "mrc%c\t%{I:%8-11d%}, %{I:%21-23d%}, %{R:APSR_nzcv%}, %{R:cr%16-19d%}, %{R:cr%0-3d%}, {%{I:%5-7d%}}"},
1411
  {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1412
    0x0e100010, 0x0f100010,
1413
    "mrc%c\t%{I:%8-11d%}, %{I:%21-23d%}, %12-15r, %{R:cr%16-19d%}, %{R:cr%0-3d%}, {%{I:%5-7d%}}"},
1414
  {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1415
    0x0e000010, 0x0f100010,
1416
    "mcr%c\t%{I:%8-11d%}, %{I:%21-23d%}, %12-15R, %{R:cr%16-19d%}, %{R:cr%0-3d%}, {%{I:%5-7d%}}"},
1417
  {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1418
    0x0c000000, 0x0e100000, "stc%22'l%c\t%{I:%8-11d%}, %{R:cr%12-15d%}, %A"},
1419
  {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1420
    0x0c100000, 0x0e100000, "ldc%22'l%c\t%{I:%8-11d%}, %{R:cr%12-15d%}, %A"},
1421
1422
  /* V6 coprocessor instructions.  */
1423
  {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1424
    0xfc500000, 0xfff00000,
1425
    "mrrc2%c\t%{I:%8-11d%}, %{I:%4-7d%}, %12-15Ru, %16-19Ru, %{R:cr%0-3d%}"},
1426
  {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1427
    0xfc400000, 0xfff00000,
1428
    "mcrr2%c\t%{I:%8-11d%}, %{I:%4-7d%}, %12-15R, %16-19R, %{R:cr%0-3d%}"},
1429
1430
  /* V5 coprocessor instructions.  */
1431
  {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1432
    0xfc100000, 0xfe100000, "ldc2%22'l%c\t%{I:%8-11d%}, %{R:cr%12-15d%}, %A"},
1433
  {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1434
    0xfc000000, 0xfe100000, "stc2%22'l%c\t%{I:%8-11d%}, %{R:cr%12-15d%}, %A"},
1435
  {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1436
    0xfe000000, 0xff000010,
1437
    "cdp2%c\t%{I:%8-11d%}, %{I:%20-23d%}, %{R:cr%12-15d%}, %{R:cr%16-19d%}, %{R:cr%0-3d%}, {%{I:%5-7d%}}"},
1438
  {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1439
    0xfe000010, 0xff100010,
1440
    "mcr2%c\t%{I:%8-11d%}, %{I:%21-23d%}, %12-15R, %{R:cr%16-19d%}, %{R:cr%0-3d%}, {%{I:%5-7d%}}"},
1441
  {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1442
    0xfe100010, 0xff100010,
1443
    "mrc2%c\t%{I:%8-11d%}, %{I:%21-23d%}, %12-15r, %{R:cr%16-19d%}, %{R:cr%0-3d%}, {%{I:%5-7d%}}"},
1444
1445
  {ANY, ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
1446
};
1447
1448
/* Neon opcode table:  This does not encode the top byte -- that is
1449
   checked by the print_insn_neon routine, as it depends on whether we are
1450
   doing thumb32 or arm32 disassembly.  */
1451
1452
/* print_insn_neon recognizes the following format control codes:
1453
1454
   %%     %
1455
1456
   %c     print condition code
1457
   %u     print condition code (unconditional in ARM mode,
1458
                          UNPREDICTABLE if not AL in Thumb)
1459
   %A     print v{st,ld}[1234] operands
1460
   %B     print v{st,ld}[1234] any one operands
1461
   %C     print v{st,ld}[1234] single->all operands
1462
   %D     print scalar
1463
   %E     print vmov, vmvn, vorr, vbic encoded constant
1464
   %F     print vtbl,vtbx register list
1465
1466
   %<bitfield>r   print as an ARM register
1467
   %<bitfield>d   print the bitfield in decimal
1468
   %<bitfield>e         print the 2^N - bitfield in decimal
1469
   %<bitfield>D   print as a NEON D register
1470
   %<bitfield>Q   print as a NEON Q register
1471
   %<bitfield>R   print as a NEON D or Q register
1472
   %<bitfield>Sn  print byte scaled width limited by n
1473
   %<bitfield>Tn  print short scaled width limited by n
1474
   %<bitfield>Un  print long scaled width limited by n
1475
1476
   %<bitfield>'c  print specified char iff bitfield is all ones
1477
   %<bitfield>`c  print specified char iff bitfield is all zeroes
1478
   %<bitfield>?ab...    select from array of values in big endian order.  */
1479
1480
static const struct opcode32 neon_opcodes[] =
1481
{
1482
  /* Extract.  */
1483
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1484
    0xf2b00840, 0xffb00850,
1485
    "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, %{I:#%8-11d%}"},
1486
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1487
    0xf2b00000, 0xffb00810,
1488
    "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, %{I:#%8-11d%}"},
1489
1490
  /* Data transfer between ARM and NEON registers.  */
1491
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1492
    0x0e800b10, 0x0ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
1493
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1494
    0x0e800b30, 0x0ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
1495
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1496
    0x0ea00b10, 0x0ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
1497
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1498
    0x0ea00b30, 0x0ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
1499
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1500
    0x0ec00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
1501
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1502
    0x0ee00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
1503
1504
  /* Move data element to all lanes.  */
1505
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1506
    0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %{R:%0-3,5D[%19d]%}"},
1507
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1508
    0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %{R:%0-3,5D[%18-19d]%}"},
1509
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1510
    0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %{R:%0-3,5D[%17-19d]%}"},
1511
1512
  /* Table lookup.  */
1513
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1514
    0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"},
1515
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1516
    0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"},
1517
1518
  /* Half-precision conversions.  */
1519
  {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1520
    0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"},
1521
  {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1522
    0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"},
1523
1524
  /* NEON fused multiply add instructions.  */
1525
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
1526
    0xf2000c10, 0xffb00f10, "vfma%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1527
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1528
    0xf2100c10, 0xffb00f10, "vfma%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1529
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
1530
    0xf2200c10, 0xffb00f10, "vfms%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1531
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1532
    0xf2300c10, 0xffb00f10, "vfms%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1533
1534
  /* BFloat16 instructions.  */
1535
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1536
    0xfc000d00, 0xffb00f10, "vdot.bf16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1537
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1538
    0xfe000d00, 0xffb00f10, "vdot.bf16\t%12-15,22R, %16-19,7R, %{R:d%0-3d[%5d]%}"},
1539
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1540
    0xfc000c40, 0xffb00f50, "vmmla.bf16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1541
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1542
    0xf3b60640, 0xffbf0fd0, "vcvt%c.bf16.f32\t%12-15,22D, %0-3,5Q"},
1543
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1544
    0xfc300810, 0xffb00f10, "vfma%6?tb.bf16\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1545
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1546
    0xfe300810, 0xffb00f10, "vfma%6?tb.bf16\t%12-15,22Q, %16-19,7Q, %{R:%0-2D[%3,5d]%}"},
1547
1548
  /* Matrix Multiply instructions.  */
1549
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
1550
    0xfc200c40, 0xffb00f50, "vsmmla.s8\t%12-15,22R, %16-19,7R, %0-3,5R"},
1551
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
1552
    0xfc200c50, 0xffb00f50, "vummla.u8\t%12-15,22R, %16-19,7R, %0-3,5R"},
1553
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
1554
    0xfca00c40, 0xffb00f50, "vusmmla.s8\t%12-15,22R, %16-19,7R, %0-3,5R"},
1555
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
1556
    0xfca00d00, 0xffb00f10, "vusdot.s8\t%12-15,22R, %16-19,7R, %0-3,5R"},
1557
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
1558
    0xfe800d00, 0xffb00f10, "vusdot.s8\t%12-15,22R, %16-19,7R, %{R:d%0-3d[%5d]%}"},
1559
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
1560
    0xfe800d10, 0xffb00f10, "vsudot.u8\t%12-15,22R, %16-19,7R, %{R:d%0-3d[%5d]%}"},
1561
1562
  /* Two registers, miscellaneous.  */
1563
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1564
    0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"},
1565
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1566
    0xf3b60400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f16\t%12-15,22R, %0-3,5R"},
1567
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1568
    0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"},
1569
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1570
    0xf3b70000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us16.f16\t%12-15,22R, %0-3,5R"},
1571
  {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1572
    0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"},
1573
  {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1574
    0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"},
1575
  {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1576
    0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"},
1577
  {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1578
    0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"},
1579
  {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1580
    0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"},
1581
  {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1582
    0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"},
1583
  {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1584
    0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"},
1585
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1586
    0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
1587
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1588
    0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
1589
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1590
    0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
1591
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1592
    0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"},
1593
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1594
    0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"},
1595
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1596
    0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"},
1597
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1598
    0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"},
1599
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1600
    0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1601
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1602
    0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1603
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1604
    0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
1605
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1606
    0xf3b20300, 0xffb30fd0,
1607
    "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, %{I:#%18-19S2%}"},
1608
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1609
    0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1610
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1611
    0xf3b70400, 0xffbf0e90, "vrecpe%c.%8?fu16\t%12-15,22R, %0-3,5R"},
1612
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1613
    0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1614
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1615
    0xf3b70480, 0xffbf0e90, "vrsqrte%c.%8?fu16\t%12-15,22R, %0-3,5R"},
1616
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1617
    0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1618
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1619
    0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1620
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1621
    0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1622
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1623
    0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1624
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1625
    0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"},
1626
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1627
    0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1628
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1629
    0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1630
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1631
    0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1632
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1633
    0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1634
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1635
    0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1636
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1637
    0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, %{I:#0%}"},
1638
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1639
    0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, %{I:#0%}"},
1640
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1641
    0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, %{I:#0%}"},
1642
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1643
    0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, %{I:#0%}"},
1644
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1645
    0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, %{I:#0%}"},
1646
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1647
    0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1648
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1649
    0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1650
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1651
    0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1652
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1653
    0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1654
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1655
    0xf3bb0600, 0xffbf0e10,
1656
    "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
1657
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1658
    0xf3b70600, 0xffbf0e10,
1659
    "vcvt%c.%7-8?usff16.%7-8?ffus16\t%12-15,22R, %0-3,5R"},
1660
1661
  /* Three registers of the same length.  */
1662
  {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1663
    0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1664
  {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1665
    0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1666
  {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1667
    0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1668
  {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1669
    0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1670
  {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1671
    0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1672
  {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1673
    0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1674
  {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1675
    0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1676
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1677
    0xf3000f10, 0xffb00f10, "vmaxnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1678
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1679
    0xf3100f10, 0xffb00f10, "vmaxnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1680
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1681
    0xf3200f10, 0xffb00f10, "vminnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1682
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1683
    0xf3300f10, 0xffb00f10, "vminnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1684
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1685
    0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1686
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1687
    0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1688
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1689
    0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1690
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1691
    0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1692
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1693
    0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1694
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1695
    0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1696
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1697
    0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1698
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1699
    0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1700
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1701
    0xf2000d00, 0xffb00f10, "vadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1702
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1703
    0xf2100d00, 0xffb00f10, "vadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1704
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1705
    0xf2000d10, 0xffb00f10, "vmla%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1706
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1707
    0xf2100d10, 0xffb00f10, "vmla%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1708
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1709
    0xf2000e00, 0xffb00f10, "vceq%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1710
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1711
    0xf2100e00, 0xffb00f10, "vceq%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1712
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1713
    0xf2000f00, 0xffb00f10, "vmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1714
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1715
    0xf2100f00, 0xffb00f10, "vmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1716
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1717
    0xf2000f10, 0xffb00f10, "vrecps%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1718
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1719
    0xf2100f10, 0xffb00f10, "vrecps%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1720
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1721
    0xf2200d00, 0xffb00f10, "vsub%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1722
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1723
    0xf2300d00, 0xffb00f10, "vsub%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1724
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1725
    0xf2200d10, 0xffb00f10, "vmls%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1726
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1727
    0xf2300d10, 0xffb00f10, "vmls%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1728
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1729
    0xf2200f00, 0xffb00f10, "vmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1730
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1731
    0xf2300f00, 0xffb00f10, "vmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1732
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1733
    0xf2200f10, 0xffb00f10, "vrsqrts%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1734
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1735
    0xf2300f10, 0xffb00f10, "vrsqrts%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1736
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1737
    0xf3000d00, 0xffb00f10, "vpadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1738
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1739
    0xf3100d00, 0xffb00f10, "vpadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1740
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1741
    0xf3000d10, 0xffb00f10, "vmul%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1742
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1743
    0xf3100d10, 0xffb00f10, "vmul%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1744
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1745
    0xf3000e00, 0xffb00f10, "vcge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1746
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1747
    0xf3100e00, 0xffb00f10, "vcge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1748
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1749
    0xf3000e10, 0xffb00f10, "vacge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1750
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1751
    0xf3100e10, 0xffb00f10, "vacge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1752
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1753
    0xf3000f00, 0xffb00f10, "vpmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1754
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1755
    0xf3100f00, 0xffb00f10, "vpmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1756
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1757
    0xf3200d00, 0xffb00f10, "vabd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1758
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1759
    0xf3300d00, 0xffb00f10, "vabd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1760
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1761
    0xf3200e00, 0xffb00f10, "vcgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1762
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1763
    0xf3300e00, 0xffb00f10, "vcgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1764
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1765
    0xf3200e10, 0xffb00f10, "vacgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1766
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1767
    0xf3300e10, 0xffb00f10, "vacgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1768
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1769
    0xf3200f00, 0xffb00f10, "vpmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1770
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1771
    0xf3300f00, 0xffb00f10, "vpmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1772
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1773
    0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1774
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1775
    0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1776
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1777
    0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1778
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1779
    0xf2000b00, 0xff800f10,
1780
    "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1781
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1782
    0xf2000b10, 0xff800f10,
1783
    "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1784
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1785
    0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1786
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1787
    0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1788
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1789
    0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1790
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1791
    0xf3000b00, 0xff800f10,
1792
    "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1793
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1794
    0xf2000000, 0xfe800f10,
1795
    "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1796
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1797
    0xf2000010, 0xfe800f10,
1798
    "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1799
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1800
    0xf2000100, 0xfe800f10,
1801
    "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1802
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1803
    0xf2000200, 0xfe800f10,
1804
    "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1805
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1806
    0xf2000210, 0xfe800f10,
1807
    "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1808
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1809
    0xf2000300, 0xfe800f10,
1810
    "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1811
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1812
    0xf2000310, 0xfe800f10,
1813
    "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1814
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1815
    0xf2000400, 0xfe800f10,
1816
    "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1817
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1818
    0xf2000410, 0xfe800f10,
1819
    "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1820
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1821
    0xf2000500, 0xfe800f10,
1822
    "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1823
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1824
    0xf2000510, 0xfe800f10,
1825
    "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1826
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1827
    0xf2000600, 0xfe800f10,
1828
    "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1829
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1830
    0xf2000610, 0xfe800f10,
1831
    "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1832
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1833
    0xf2000700, 0xfe800f10,
1834
    "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1835
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1836
    0xf2000710, 0xfe800f10,
1837
    "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1838
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1839
    0xf2000910, 0xfe800f10,
1840
    "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1841
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1842
    0xf2000a00, 0xfe800f10,
1843
    "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1844
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1845
    0xf2000a10, 0xfe800f10,
1846
    "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1847
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1848
    0xf3000b10, 0xff800f10,
1849
    "vqrdmlah%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1850
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1851
    0xf3000c10, 0xff800f10,
1852
    "vqrdmlsh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1853
1854
  /* One register and an immediate value.  */
1855
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1856
    0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"},
1857
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1858
    0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"},
1859
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1860
    0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"},
1861
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1862
    0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"},
1863
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1864
    0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"},
1865
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1866
    0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"},
1867
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1868
    0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"},
1869
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1870
    0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"},
1871
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1872
    0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"},
1873
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1874
    0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"},
1875
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1876
    0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"},
1877
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1878
    0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"},
1879
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1880
    0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"},
1881
1882
  /* Two registers and a shift amount.  */
1883
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1884
    0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, %{I:#%16-18e%}"},
1885
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1886
    0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, %{I:#%16-18e%}"},
1887
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1888
    0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, %{I:#%16-18e%}"},
1889
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1890
    0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, %{I:#%16-18e%}"},
1891
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1892
    0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, %{I:#%16-18e%}"},
1893
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1894
    0xf2880950, 0xfeb80fd0,
1895
    "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, %{I:#%16-18e%}"},
1896
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1897
    0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, %{I:#%16-18d%}"},
1898
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1899
    0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, %{I:#%16-19e%}"},
1900
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1901
    0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, %{I:#%16-19e%}"},
1902
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1903
    0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, %{I:#%16-18d%}"},
1904
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1905
    0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, %{I:#%16-18e%}"},
1906
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1907
    0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, %{I:#%16-18d%}"},
1908
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1909
    0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, %{I:#%16-18d%}"},
1910
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1911
    0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, %{I:#%16-19e%}"},
1912
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1913
    0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, %{I:#%16-19e%}"},
1914
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1915
    0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, %{I:#%16-19e%}"},
1916
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1917
    0xf2900950, 0xfeb00fd0,
1918
    "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, %{I:#%16-19e%}"},
1919
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1920
    0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, %{I:#%16-19d%}"},
1921
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1922
    0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, %{I:#%16-18e%}"},
1923
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1924
    0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, %{I:#%16-18e%}"},
1925
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1926
    0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, %{I:#%16-18e%}"},
1927
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1928
    0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, %{I:#%16-18e%}"},
1929
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1930
    0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, %{I:#%16-18d%}"},
1931
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1932
    0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, %{I:#%16-20e%}"},
1933
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1934
    0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, %{I:#%16-20e%}"},
1935
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1936
    0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, %{I:#%16-19d%}"},
1937
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1938
    0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, %{I:#%16-19e%}"},
1939
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1940
    0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, %{I:#%16-19d%}"},
1941
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1942
    0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, %{I:#%16-19d%}"},
1943
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1944
    0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, %{I:#%16-20d%}"},
1945
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1946
    0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, %{I:#%16-19e%}"},
1947
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1948
    0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, %{I:#%16-19e%}"},
1949
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1950
    0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, %{I:#%16-19e%}"},
1951
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1952
    0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, %{I:#%16-19e%}"},
1953
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1954
    0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, %{I:#%16-19d%}"},
1955
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1956
    0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, %{I:#%16-20e%}"},
1957
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1958
    0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, %{I:#%16-20e%}"},
1959
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1960
    0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, %{I:#%16-20e%}"},
1961
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1962
    0xf2a00950, 0xfea00fd0,
1963
    "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, %{I:#%16-20e%}"},
1964
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1965
    0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, %{I:#%16-20d%}"},
1966
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1967
    0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, %{I:#%16-20e%}"},
1968
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1969
    0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, %{I:#%16-20d%}"},
1970
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1971
    0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, %{I:#%16-20d%}"},
1972
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1973
    0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, %{I:#%16-20e%}"},
1974
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1975
    0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, %{I:#%16-20e%}"},
1976
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1977
    0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, %{I:#%16-20e%}"},
1978
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1979
    0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, %{I:#%16-20e%}"},
1980
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1981
    0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, %{I:#%16-20d%}"},
1982
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1983
    0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, %{I:#%16-21d%}"},
1984
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1985
    0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, %{I:#%16-21e%}"},
1986
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1987
    0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, %{I:#%16-21d%}"},
1988
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1989
    0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, %{I:#%16-21d%}"},
1990
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1991
    0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, %{I:#%16-21e%}"},
1992
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1993
    0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, %{I:#%16-21e%}"},
1994
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1995
    0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, %{I:#%16-21e%}"},
1996
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1997
    0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, %{I:#%16-21e%}"},
1998
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1999
    0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, %{I:#%16-21d%}"},
2000
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2001
    0xf2a00e10, 0xfea00e90,
2002
    "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, %{I:#%16-20e%}"},
2003
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
2004
    0xf2a00c10, 0xfea00e90,
2005
    "vcvt%c.%24,8?usff16.%24,8?ffus16\t%12-15,22R, %0-3,5R, %{I:#%16-20e%}"},
2006
2007
  /* Three registers of different lengths.  */
2008
  {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
2009
    0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2010
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2011
    0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2012
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2013
    0xf2800400, 0xff800f50,
2014
    "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
2015
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2016
    0xf2800600, 0xff800f50,
2017
    "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
2018
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2019
    0xf2800900, 0xff800f50,
2020
    "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2021
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2022
    0xf2800b00, 0xff800f50,
2023
    "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2024
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2025
    0xf2800d00, 0xff800f50,
2026
    "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2027
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2028
    0xf3800400, 0xff800f50,
2029
    "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
2030
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2031
    0xf3800600, 0xff800f50,
2032
    "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
2033
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2034
    0xf2800000, 0xfe800f50,
2035
    "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2036
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2037
    0xf2800100, 0xfe800f50,
2038
    "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
2039
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2040
    0xf2800200, 0xfe800f50,
2041
    "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2042
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2043
    0xf2800300, 0xfe800f50,
2044
    "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
2045
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2046
    0xf2800500, 0xfe800f50,
2047
    "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2048
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2049
    0xf2800700, 0xfe800f50,
2050
    "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2051
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2052
    0xf2800800, 0xfe800f50,
2053
    "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2054
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2055
    0xf2800a00, 0xfe800f50,
2056
    "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2057
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2058
    0xf2800c00, 0xfe800f50,
2059
    "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2060
2061
  /* Two registers and a scalar.  */
2062
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2063
    0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2064
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2065
    0xf2800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
2066
  {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
2067
    0xf2900140, 0xffb00f50, "vmla%c.f16\t%12-15,22D, %16-19,7D, %D"},
2068
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2069
    0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2070
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2071
    0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2072
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2073
    0xf2800540, 0xff900f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2074
  {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
2075
    0xf2900540, 0xffb00f50, "vmls%c.f16\t%12-15,22D, %16-19,7D, %D"},
2076
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2077
    0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2078
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2079
    0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2080
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2081
    0xf2800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
2082
  {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
2083
    0xf2900940, 0xffb00f50, "vmul%c.f16\t%12-15,22D, %16-19,7D, %D"},
2084
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2085
    0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2086
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2087
    0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2088
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2089
    0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2090
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2091
    0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2092
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2093
    0xf3800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
2094
  {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
2095
    0xf3900140, 0xffb00f50, "vmla%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
2096
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2097
    0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2098
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2099
    0xf3800540, 0xff900f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
2100
  {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
2101
    0xf3900540, 0xffb00f50, "vmls%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
2102
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2103
    0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2104
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2105
    0xf3800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
2106
  {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
2107
    0xf3900940, 0xffb00f50, "vmul%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
2108
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2109
    0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2110
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2111
    0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2112
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2113
    0xf2800240, 0xfe800f50,
2114
    "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2115
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2116
    0xf2800640, 0xfe800f50,
2117
    "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2118
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2119
    0xf2800a40, 0xfe800f50,
2120
    "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2121
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
2122
    0xf2800e40, 0xff800f50,
2123
   "vqrdmlah%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2124
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
2125
    0xf2800f40, 0xff800f50,
2126
   "vqrdmlsh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2127
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
2128
    0xf3800e40, 0xff800f50,
2129
   "vqrdmlah%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2130
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
2131
    0xf3800f40, 0xff800f50,
2132
   "vqrdmlsh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"
2133
  },
2134
2135
  /* Element and structure load/store.  */
2136
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2137
    0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"},
2138
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2139
    0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"},
2140
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2141
    0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"},
2142
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2143
    0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"},
2144
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2145
    0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"},
2146
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2147
    0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
2148
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2149
    0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
2150
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2151
    0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
2152
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2153
    0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
2154
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2155
    0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
2156
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2157
    0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
2158
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2159
    0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
2160
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2161
    0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
2162
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2163
    0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
2164
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2165
    0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"},
2166
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2167
    0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"},
2168
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2169
    0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"},
2170
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2171
    0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"},
2172
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2173
    0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"},
2174
2175
  {ARM_FEATURE_CORE_LOW (0), 0 ,0, 0}
2176
};
2177
2178
/* mve opcode table.  */
2179
2180
/* print_insn_mve recognizes the following format control codes:
2181
2182
   %%     %
2183
2184
   %a     print '+' or '-' or imm offset in vldr[bhwd] and
2185
      vstr[bhwd]
2186
   %c     print condition code
2187
   %d     print addr mode of MVE vldr[bhw] and vstr[bhw]
2188
   %u     print 'U' (unsigned) or 'S' for various mve instructions
2189
   %i     print MVE predicate(s) for vpt and vpst
2190
   %j     print a 5-bit immediate from hw2[14:12,7:6]
2191
   %k     print 48 if the 7th position bit is set else print 64.
2192
   %m     print rounding mode for vcvt and vrint
2193
   %n     print vector comparison code for predicated instruction
2194
   %s     print size for various vcvt instructions
2195
   %v     print vector predicate for instruction in predicated
2196
      block
2197
   %o     print offset scaled for vldr[hwd] and vstr[hwd]
2198
   %w     print writeback mode for MVE v{st,ld}[24]
2199
   %B     print v{st,ld}[24] any one operands
2200
   %E     print vmov, vmvn, vorr, vbic encoded constant
2201
   %N     print generic index for vmov
2202
   %T     print bottom ('b') or top ('t') of source register
2203
   %X     print exchange field in vmla* instructions
2204
2205
   %<bitfield>r   print as an ARM register
2206
   %<bitfield>d   print the bitfield in decimal
2207
   %<bitfield>A   print accumulate or not
2208
   %<bitfield>c   print bitfield as a condition code
2209
   %<bitfield>C   print bitfield as an inverted condition code
2210
   %<bitfield>Q   print as a MVE Q register
2211
   %<bitfield>F   print as a MVE S register
2212
   %<bitfield>Z   as %<>r but r15 is ZR instead of PC and r13 is
2213
      UNPREDICTABLE
2214
2215
   %<bitfield>S   as %<>r but r15 or r13 is UNPREDICTABLE
2216
   %<bitfield>s   print size for vector predicate & non VMOV instructions
2217
   %<bitfield>I   print carry flag or not
2218
   %<bitfield>i   print immediate for vstr/vldr reg +/- imm
2219
   %<bitfield>h   print high half of 64-bit destination reg
2220
   %<bitfield>k   print immediate for vector conversion instruction
2221
   %<bitfield>l   print low half of 64-bit destination reg
2222
   %<bitfield>o   print rotate value for vcmul
2223
   %<bitfield>u   print immediate value for vddup/vdwdup
2224
   %<bitfield>x   print the bitfield in hex.
2225
  */
2226
2227
static const struct mopcode32 mve_opcodes[] =
2228
{
2229
  /* MVE.  */
2230
2231
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2232
   MVE_VPST,
2233
   0xfe310f4d, 0xffbf1fff,
2234
   "vpst%i"
2235
  },
2236
2237
  /* Floating point VPT T1.  */
2238
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2239
   MVE_VPT_FP_T1,
2240
   0xee310f00, 0xefb10f50,
2241
   "vpt%i.f%28s\t%n, %17-19Q, %1-3,5Q"},
2242
  /* Floating point VPT T2.  */
2243
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2244
   MVE_VPT_FP_T2,
2245
   0xee310f40, 0xefb10f50,
2246
   "vpt%i.f%28s\t%n, %17-19Q, %0-3Z"},
2247
2248
  /* Vector VPT T1.  */
2249
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2250
   MVE_VPT_VEC_T1,
2251
   0xfe010f00, 0xff811f51,
2252
   "vpt%i.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
2253
  /* Vector VPT T2.  */
2254
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2255
   MVE_VPT_VEC_T2,
2256
   0xfe010f01, 0xff811f51,
2257
   "vpt%i.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
2258
  /* Vector VPT T3.  */
2259
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2260
   MVE_VPT_VEC_T3,
2261
   0xfe011f00, 0xff811f50,
2262
   "vpt%i.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
2263
  /* Vector VPT T4.  */
2264
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2265
   MVE_VPT_VEC_T4,
2266
   0xfe010f40, 0xff811f70,
2267
   "vpt%i.i%20-21s\t%n, %17-19Q, %0-3Z"},
2268
  /* Vector VPT T5.  */
2269
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2270
   MVE_VPT_VEC_T5,
2271
   0xfe010f60, 0xff811f70,
2272
   "vpt%i.u%20-21s\t%n, %17-19Q, %0-3Z"},
2273
  /* Vector VPT T6.  */
2274
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2275
   MVE_VPT_VEC_T6,
2276
   0xfe011f40, 0xff811f50,
2277
   "vpt%i.s%20-21s\t%n, %17-19Q, %0-3Z"},
2278
2279
  /* Vector VBIC immediate.  */
2280
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2281
   MVE_VBIC_IMM,
2282
   0xef800070, 0xefb81070,
2283
   "vbic%v.i%8-11s\t%13-15,22Q, %E"},
2284
2285
  /* Vector VBIC register.  */
2286
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2287
   MVE_VBIC_REG,
2288
   0xef100150, 0xffb11f51,
2289
   "vbic%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2290
2291
  /* Vector VABAV.  */
2292
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2293
   MVE_VABAV,
2294
   0xee800f01, 0xefc10f51,
2295
   "vabav%v.%u%20-21s\t%12-15r, %17-19,7Q, %1-3,5Q"},
2296
2297
  /* Vector VABD floating point.  */
2298
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2299
   MVE_VABD_FP,
2300
   0xff200d40, 0xffa11f51,
2301
   "vabd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2302
2303
  /* Vector VABD.  */
2304
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2305
   MVE_VABD_VEC,
2306
   0xef000740, 0xef811f51,
2307
   "vabd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2308
2309
  /* Vector VABS floating point.  */
2310
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2311
   MVE_VABS_FP,
2312
   0xFFB10740, 0xFFB31FD1,
2313
   "vabs%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
2314
  /* Vector VABS.  */
2315
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2316
   MVE_VABS_VEC,
2317
   0xffb10340, 0xffb31fd1,
2318
   "vabs%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2319
2320
  /* Vector VADD floating point T1.  */
2321
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2322
   MVE_VADD_FP_T1,
2323
   0xef000d40, 0xffa11f51,
2324
   "vadd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2325
  /* Vector VADD floating point T2.  */
2326
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2327
   MVE_VADD_FP_T2,
2328
   0xee300f40, 0xefb11f70,
2329
   "vadd%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2330
  /* Vector VADD T1.  */
2331
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2332
   MVE_VADD_VEC_T1,
2333
   0xef000840, 0xff811f51,
2334
   "vadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2335
  /* Vector VADD T2.  */
2336
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2337
   MVE_VADD_VEC_T2,
2338
   0xee010f40, 0xff811f70,
2339
   "vadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2340
2341
  /* Vector VADDLV.  */
2342
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2343
   MVE_VADDLV,
2344
   0xee890f00, 0xef8f1fd1,
2345
   "vaddlv%5A%v.%u32\t%13-15l, %20-22h, %1-3Q"},
2346
2347
  /* Vector VADDV.  */
2348
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2349
   MVE_VADDV,
2350
   0xeef10f00, 0xeff31fd1,
2351
   "vaddv%5A%v.%u%18-19s\t%13-15l, %1-3Q"},
2352
2353
  /* Vector VADC.  */
2354
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2355
   MVE_VADC,
2356
   0xee300f00, 0xffb10f51,
2357
   "vadc%12I%v.i32\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2358
2359
  /* Vector VAND.  */
2360
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2361
   MVE_VAND,
2362
   0xef000150, 0xffb11f51,
2363
   "vand%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2364
2365
  /* Vector VBRSR register.  */
2366
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2367
   MVE_VBRSR,
2368
   0xfe011e60, 0xff811f70,
2369
   "vbrsr%v.%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2370
2371
  /* Vector VCADD floating point.  */
2372
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2373
   MVE_VCADD_FP,
2374
   0xfc800840, 0xfea11f51,
2375
   "vcadd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, %{I:#%24o%}"},
2376
2377
  /* Vector VCADD.  */
2378
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2379
   MVE_VCADD_VEC,
2380
   0xfe000f00, 0xff810f51,
2381
   "vcadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, %{I:#%12o%}"},
2382
2383
  /* Vector VCLS.  */
2384
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2385
   MVE_VCLS,
2386
   0xffb00440, 0xffb31fd1,
2387
   "vcls%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2388
2389
  /* Vector VCLZ.  */
2390
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2391
   MVE_VCLZ,
2392
   0xffb004c0, 0xffb31fd1,
2393
   "vclz%v.i%18-19s\t%13-15,22Q, %1-3,5Q"},
2394
2395
  /* Vector VCMLA.  */
2396
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2397
   MVE_VCMLA_FP,
2398
   0xfc200840, 0xfe211f51,
2399
   "vcmla%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, %{I:#%23-24o%}"},
2400
2401
  /* Vector VCMP floating point T1.  */
2402
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2403
   MVE_VCMP_FP_T1,
2404
   0xee310f00, 0xeff1ef50,
2405
   "vcmp%v.f%28s\t%n, %17-19Q, %1-3,5Q"},
2406
2407
  /* Vector VCMP floating point T2.  */
2408
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2409
   MVE_VCMP_FP_T2,
2410
   0xee310f40, 0xeff1ef50,
2411
   "vcmp%v.f%28s\t%n, %17-19Q, %0-3Z"},
2412
2413
  /* Vector VCMP T1.  */
2414
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2415
   MVE_VCMP_VEC_T1,
2416
   0xfe010f00, 0xffc1ff51,
2417
   "vcmp%v.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
2418
  /* Vector VCMP T2.  */
2419
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2420
   MVE_VCMP_VEC_T2,
2421
   0xfe010f01, 0xffc1ff51,
2422
   "vcmp%v.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
2423
  /* Vector VCMP T3.  */
2424
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2425
   MVE_VCMP_VEC_T3,
2426
   0xfe011f00, 0xffc1ff50,
2427
   "vcmp%v.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
2428
  /* Vector VCMP T4.  */
2429
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2430
   MVE_VCMP_VEC_T4,
2431
   0xfe010f40, 0xffc1ff70,
2432
   "vcmp%v.i%20-21s\t%n, %17-19Q, %0-3Z"},
2433
  /* Vector VCMP T5.  */
2434
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2435
   MVE_VCMP_VEC_T5,
2436
   0xfe010f60, 0xffc1ff70,
2437
   "vcmp%v.u%20-21s\t%n, %17-19Q, %0-3Z"},
2438
  /* Vector VCMP T6.  */
2439
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2440
   MVE_VCMP_VEC_T6,
2441
   0xfe011f40, 0xffc1ff50,
2442
   "vcmp%v.s%20-21s\t%n, %17-19Q, %0-3Z"},
2443
2444
  /* Vector VDUP.  */
2445
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2446
   MVE_VDUP,
2447
   0xeea00b10, 0xffb10f5f,
2448
   "vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
2449
2450
  /* Vector VEOR.  */
2451
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2452
   MVE_VEOR,
2453
   0xff000150, 0xffd11f51,
2454
   "veor%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2455
2456
  /* Vector VFMA, vector * scalar.  */
2457
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2458
   MVE_VFMA_FP_SCALAR,
2459
   0xee310e40, 0xefb11f70,
2460
   "vfma%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2461
2462
  /* Vector VFMA floating point.  */
2463
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2464
   MVE_VFMA_FP,
2465
   0xef000c50, 0xffa11f51,
2466
   "vfma%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2467
2468
  /* Vector VFMS floating point.  */
2469
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2470
   MVE_VFMS_FP,
2471
   0xef200c50, 0xffa11f51,
2472
   "vfms%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2473
2474
  /* Vector VFMAS, vector * scalar.  */
2475
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2476
   MVE_VFMAS_FP_SCALAR,
2477
   0xee311e40, 0xefb11f70,
2478
   "vfmas%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2479
2480
  /* Vector VHADD T1.  */
2481
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2482
   MVE_VHADD_T1,
2483
   0xef000040, 0xef811f51,
2484
   "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2485
2486
  /* Vector VHADD T2.  */
2487
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2488
   MVE_VHADD_T2,
2489
   0xee000f40, 0xef811f70,
2490
   "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2491
2492
  /* Vector VHSUB T1.  */
2493
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2494
   MVE_VHSUB_T1,
2495
   0xef000240, 0xef811f51,
2496
   "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2497
2498
  /* Vector VHSUB T2.  */
2499
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2500
   MVE_VHSUB_T2,
2501
   0xee001f40, 0xef811f70,
2502
   "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2503
2504
  /* Vector VCMUL.  */
2505
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2506
   MVE_VCMUL_FP,
2507
   0xee300e00, 0xefb10f50,
2508
   "vcmul%v.f%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, %{I:#%0,12o%}"},
2509
2510
   /* Vector VCTP.  */
2511
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2512
   MVE_VCTP,
2513
   0xf000e801, 0xffc0ffff,
2514
   "vctp%v.%20-21s\t%16-19r"},
2515
2516
  /* Vector VDUP.  */
2517
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2518
   MVE_VDUP,
2519
   0xeea00b10, 0xffb10f5f,
2520
   "vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
2521
2522
  /* Vector VRHADD.  */
2523
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2524
   MVE_VRHADD,
2525
   0xef000140, 0xef811f51,
2526
   "vrhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2527
2528
  /* Vector VCVT.  */
2529
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2530
   MVE_VCVT_FP_FIX_VEC,
2531
   0xef800c50, 0xef801cd1,
2532
   "vcvt%v.%s\t%13-15,22Q, %1-3,5Q, %{I:#%16-21k%}"},
2533
2534
  /* Vector VCVT.  */
2535
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2536
   MVE_VCVT_BETWEEN_FP_INT,
2537
   0xffb30640, 0xffb31e51,
2538
   "vcvt%v.%s\t%13-15,22Q, %1-3,5Q"},
2539
2540
  /* Vector VCVT between single and half-precision float, bottom half.  */
2541
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2542
   MVE_VCVT_FP_HALF_FP,
2543
   0xee3f0e01, 0xefbf1fd1,
2544
   "vcvtb%v.%s\t%13-15,22Q, %1-3,5Q"},
2545
2546
  /* Vector VCVT between single and half-precision float, top half.  */
2547
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2548
   MVE_VCVT_FP_HALF_FP,
2549
   0xee3f1e01, 0xefbf1fd1,
2550
   "vcvtt%v.%s\t%13-15,22Q, %1-3,5Q"},
2551
2552
  /* Vector VCVT.  */
2553
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2554
   MVE_VCVT_FROM_FP_TO_INT,
2555
   0xffb30040, 0xffb31c51,
2556
   "vcvt%m%v.%s\t%13-15,22Q, %1-3,5Q"},
2557
2558
  /* Vector VDDUP.  */
2559
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2560
   MVE_VDDUP,
2561
   0xee011f6e, 0xff811f7e,
2562
   "vddup%v.u%20-21s\t%13-15,22Q, %17-19l, %{I:#%0,7u%}"},
2563
2564
  /* Vector VDWDUP.  */
2565
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2566
   MVE_VDWDUP,
2567
   0xee011f60, 0xff811f70,
2568
   "vdwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, %{I:#%0,7u%}"},
2569
2570
  /* Vector VHCADD.  */
2571
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2572
   MVE_VHCADD,
2573
   0xee000f00, 0xff810f51,
2574
   "vhcadd%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, %{I:#%12o%}"},
2575
2576
  /* Vector VIWDUP.  */
2577
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2578
   MVE_VIWDUP,
2579
   0xee010f60, 0xff811f70,
2580
   "viwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, %{I:#%0,7u%}"},
2581
2582
  /* Vector VIDUP.  */
2583
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2584
   MVE_VIDUP,
2585
   0xee010f6e, 0xff811f7e,
2586
   "vidup%v.u%20-21s\t%13-15,22Q, %17-19l, %{I:#%0,7u%}"},
2587
2588
  /* Vector VLD2.  */
2589
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2590
   MVE_VLD2,
2591
   0xfc901e00, 0xff901e5f,
2592
   "vld2%5d.%7-8s\t%B, [%16-19r]%w"},
2593
2594
  /* Vector VLD4.  */
2595
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2596
   MVE_VLD4,
2597
   0xfc901e01, 0xff901e1f,
2598
   "vld4%5-6d.%7-8s\t%B, [%16-19r]%w"},
2599
2600
  /* Vector VLDRB gather load.  */
2601
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2602
   MVE_VLDRB_GATHER_T1,
2603
   0xec900e00, 0xefb01e50,
2604
   "vldrb%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"},
2605
2606
  /* Vector VLDRH gather load.  */
2607
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2608
   MVE_VLDRH_GATHER_T2,
2609
   0xec900e10, 0xefb01e50,
2610
   "vldrh%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2611
2612
  /* Vector VLDRW gather load.  */
2613
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2614
   MVE_VLDRW_GATHER_T3,
2615
   0xfc900f40, 0xffb01fd0,
2616
   "vldrw%v.u32\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2617
2618
  /* Vector VLDRD gather load.  */
2619
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2620
   MVE_VLDRD_GATHER_T4,
2621
   0xec900fd0, 0xefb01fd0,
2622
   "vldrd%v.u64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2623
2624
  /* Vector VLDRW gather load.  */
2625
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2626
   MVE_VLDRW_GATHER_T5,
2627
   0xfd101e00, 0xff111f00,
2628
   "vldrw%v.u32\t%13-15,22Q, [%17-19,7Q, %{I:#%a%0-6i%}]%w"},
2629
2630
  /* Vector VLDRD gather load, variant T6.  */
2631
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2632
   MVE_VLDRD_GATHER_T6,
2633
   0xfd101f00, 0xff111f00,
2634
   "vldrd%v.u64\t%13-15,22Q, [%17-19,7Q, %{I:#%a%0-6i%}]%w"},
2635
2636
  /* Vector VLDRB.  */
2637
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2638
   MVE_VLDRB_T1,
2639
   0xec100e00, 0xee581e00,
2640
   "vldrb%v.%u%7-8s\t%13-15Q, %d"},
2641
2642
  /* Vector VLDRH.  */
2643
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2644
   MVE_VLDRH_T2,
2645
   0xec180e00, 0xee581e00,
2646
   "vldrh%v.%u%7-8s\t%13-15Q, %d"},
2647
2648
  /* Vector VLDRB unsigned, variant T5.  */
2649
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2650
   MVE_VLDRB_T5,
2651
   0xec101e00, 0xfe101f80,
2652
   "vldrb%v.u8\t%13-15,22Q, %d"},
2653
2654
  /* Vector VLDRH unsigned, variant T6.  */
2655
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2656
   MVE_VLDRH_T6,
2657
   0xec101e80, 0xfe101f80,
2658
   "vldrh%v.u16\t%13-15,22Q, %d"},
2659
2660
  /* Vector VLDRW unsigned, variant T7.  */
2661
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2662
   MVE_VLDRW_T7,
2663
   0xec101f00, 0xfe101f80,
2664
   "vldrw%v.u32\t%13-15,22Q, %d"},
2665
2666
  /* Vector VMAX.  */
2667
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2668
   MVE_VMAX,
2669
   0xef000640, 0xef811f51,
2670
   "vmax%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2671
2672
  /* Vector VMAXA.  */
2673
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2674
   MVE_VMAXA,
2675
   0xee330e81, 0xffb31fd1,
2676
   "vmaxa%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2677
2678
  /* Vector VMAXNM floating point.  */
2679
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2680
   MVE_VMAXNM_FP,
2681
   0xff000f50, 0xffa11f51,
2682
   "vmaxnm%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2683
2684
  /* Vector VMAXNMA floating point.  */
2685
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2686
   MVE_VMAXNMA_FP,
2687
   0xee3f0e81, 0xefbf1fd1,
2688
   "vmaxnma%v.f%28s\t%13-15,22Q, %1-3,5Q"},
2689
2690
  /* Vector VMAXNMV floating point.  */
2691
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2692
   MVE_VMAXNMV_FP,
2693
   0xeeee0f00, 0xefff0fd1,
2694
   "vmaxnmv%v.f%28s\t%12-15r, %1-3,5Q"},
2695
2696
  /* Vector VMAXNMAV floating point.  */
2697
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2698
   MVE_VMAXNMAV_FP,
2699
   0xeeec0f00, 0xefff0fd1,
2700
   "vmaxnmav%v.f%28s\t%12-15r, %1-3,5Q"},
2701
2702
  /* Vector VMAXV.  */
2703
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2704
   MVE_VMAXV,
2705
   0xeee20f00, 0xeff30fd1,
2706
   "vmaxv%v.%u%18-19s\t%12-15r, %1-3,5Q"},
2707
2708
  /* Vector VMAXAV.  */
2709
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2710
   MVE_VMAXAV,
2711
   0xeee00f00, 0xfff30fd1,
2712
   "vmaxav%v.s%18-19s\t%12-15r, %1-3,5Q"},
2713
2714
  /* Vector VMIN.  */
2715
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2716
   MVE_VMIN,
2717
   0xef000650, 0xef811f51,
2718
   "vmin%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2719
2720
  /* Vector VMINA.  */
2721
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2722
   MVE_VMINA,
2723
   0xee331e81, 0xffb31fd1,
2724
   "vmina%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2725
2726
  /* Vector VMINNM floating point.  */
2727
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2728
   MVE_VMINNM_FP,
2729
   0xff200f50, 0xffa11f51,
2730
   "vminnm%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2731
2732
  /* Vector VMINNMA floating point.  */
2733
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2734
   MVE_VMINNMA_FP,
2735
   0xee3f1e81, 0xefbf1fd1,
2736
   "vminnma%v.f%28s\t%13-15,22Q, %1-3,5Q"},
2737
2738
  /* Vector VMINNMV floating point.  */
2739
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2740
   MVE_VMINNMV_FP,
2741
   0xeeee0f80, 0xefff0fd1,
2742
   "vminnmv%v.f%28s\t%12-15r, %1-3,5Q"},
2743
2744
  /* Vector VMINNMAV floating point.  */
2745
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2746
   MVE_VMINNMAV_FP,
2747
   0xeeec0f80, 0xefff0fd1,
2748
   "vminnmav%v.f%28s\t%12-15r, %1-3,5Q"},
2749
2750
  /* Vector VMINV.  */
2751
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2752
   MVE_VMINV,
2753
   0xeee20f80, 0xeff30fd1,
2754
   "vminv%v.%u%18-19s\t%12-15r, %1-3,5Q"},
2755
2756
  /* Vector VMINAV.  */
2757
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2758
   MVE_VMINAV,
2759
   0xeee00f80, 0xfff30fd1,
2760
   "vminav%v.s%18-19s\t%12-15r, %1-3,5Q"},
2761
2762
  /* Vector VMLA.  */
2763
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2764
   MVE_VMLA,
2765
   0xee010e40, 0xef811f70,
2766
   "vmla%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2767
2768
  /* Vector VMLALDAV.  Note must appear before VMLADAV due to instruction
2769
     opcode aliasing.  */
2770
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2771
   MVE_VMLALDAV,
2772
   0xee801e00, 0xef801f51,
2773
   "vmlaldav%5Ax%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2774
2775
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2776
   MVE_VMLALDAV,
2777
   0xee800e00, 0xef801f51,
2778
   "vmlalv%5A%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2779
2780
  /* Vector VMLAV T1 variant, same as VMLADAV but with X == 0.  */
2781
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2782
   MVE_VMLADAV_T1,
2783
   0xeef00e00, 0xeff01f51,
2784
   "vmlav%5A%v.%u%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2785
2786
  /* Vector VMLAV T2 variant, same as VMLADAV but with X == 0.  */
2787
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2788
   MVE_VMLADAV_T2,
2789
   0xeef00f00, 0xeff11f51,
2790
   "vmlav%5A%v.%u8\t%13-15l, %17-19,7Q, %1-3Q"},
2791
2792
  /* Vector VMLADAV T1 variant.  */
2793
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2794
   MVE_VMLADAV_T1,
2795
   0xeef01e00, 0xeff01f51,
2796
   "vmladav%5Ax%v.%u%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2797
2798
  /* Vector VMLADAV T2 variant.  */
2799
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2800
   MVE_VMLADAV_T2,
2801
   0xeef01f00, 0xeff11f51,
2802
   "vmladav%5Ax%v.%u8\t%13-15l, %17-19,7Q, %1-3Q"},
2803
2804
  /* Vector VMLAS.  */
2805
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2806
   MVE_VMLAS,
2807
   0xee011e40, 0xef811f70,
2808
   "vmlas%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2809
2810
  /* Vector VRMLSLDAVH.  Note must appear before VMLSDAV due to instruction
2811
     opcode aliasing.  */
2812
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2813
   MVE_VRMLSLDAVH,
2814
   0xfe800e01, 0xff810f51,
2815
   "vrmlsldavh%5A%X%v.s32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2816
2817
  /* Vector VMLSLDAV.  Note must appear before VMLSDAV due to instruction
2818
     opcdoe aliasing.  */
2819
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2820
   MVE_VMLSLDAV,
2821
   0xee800e01, 0xff800f51,
2822
   "vmlsldav%5A%X%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2823
2824
  /* Vector VMLSDAV T1 Variant.  */
2825
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2826
   MVE_VMLSDAV_T1,
2827
   0xeef00e01, 0xfff00f51,
2828
   "vmlsdav%5A%X%v.s%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2829
2830
  /* Vector VMLSDAV T2 Variant.  */
2831
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2832
   MVE_VMLSDAV_T2,
2833
   0xfef00e01, 0xfff10f51,
2834
   "vmlsdav%5A%X%v.s8\t%13-15l, %17-19,7Q, %1-3Q"},
2835
2836
  /* Vector VMOV between gpr and half precision register, op == 0.  */
2837
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2838
   MVE_VMOV_HFP_TO_GP,
2839
   0xee000910, 0xfff00f7f,
2840
   "vmov.f16\t%7,16-19F, %12-15r"},
2841
2842
  /* Vector VMOV between gpr and half precision register, op == 1.  */
2843
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2844
   MVE_VMOV_HFP_TO_GP,
2845
   0xee100910, 0xfff00f7f,
2846
   "vmov.f16\t%12-15r, %7,16-19F"},
2847
2848
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2849
   MVE_VMOV_GP_TO_VEC_LANE,
2850
   0xee000b10, 0xff900f1f,
2851
   "vmov%c.%5-6,21-22s\t%{R:%17-19,7Q[%N]%}, %12-15r"},
2852
2853
  /* Vector VORR immediate to vector.
2854
     NOTE: MVE_VORR_IMM must appear in the table
2855
     before MVE_VMOV_IMM_TO_VEC due to opcode aliasing.  */
2856
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2857
   MVE_VORR_IMM,
2858
   0xef800050, 0xefb810f0,
2859
   "vorr%v.i%8-11s\t%13-15,22Q, %E"},
2860
2861
  /* Vector VQSHL T2 Variant.
2862
     NOTE: MVE_VQSHL_T2 must appear in the table before
2863
     before MVE_VMOV_IMM_TO_VEC due to opcode aliasing.  */
2864
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2865
   MVE_VQSHL_T2,
2866
   0xef800750, 0xef801fd1,
2867
   "vqshl%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
2868
2869
  /* Vector VQSHLU T3 Variant
2870
     NOTE: MVE_VQSHL_T2 must appear in the table before
2871
     before MVE_VMOV_IMM_TO_VEC due to opcode aliasing.  */
2872
2873
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2874
   MVE_VQSHLU_T3,
2875
   0xff800650, 0xff801fd1,
2876
   "vqshlu%v.s%19-21s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
2877
2878
  /* Vector VRSHR
2879
     NOTE: MVE_VRSHR must appear in the table before
2880
     before MVE_VMOV_IMM_TO_VEC due to opcode aliasing.  */
2881
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2882
   MVE_VRSHR,
2883
   0xef800250, 0xef801fd1,
2884
   "vrshr%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
2885
2886
  /* Vector VSHL.
2887
     NOTE: MVE_VSHL must appear in the table before
2888
     before MVE_VMOV_IMM_TO_VEC due to opcode aliasing.  */
2889
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2890
   MVE_VSHL_T1,
2891
   0xef800550, 0xff801fd1,
2892
   "vshl%v.i%19-21s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
2893
2894
  /* Vector VSHR
2895
     NOTE: MVE_VSHR must appear in the table before
2896
     before MVE_VMOV_IMM_TO_VEC due to opcode aliasing.  */
2897
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2898
   MVE_VSHR,
2899
   0xef800050, 0xef801fd1,
2900
   "vshr%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
2901
2902
  /* Vector VSLI
2903
     NOTE: MVE_VSLI must appear in the table before
2904
     before MVE_VMOV_IMM_TO_VEC due to opcode aliasing.  */
2905
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2906
   MVE_VSLI,
2907
   0xff800550, 0xff801fd1,
2908
   "vsli%v.%19-21s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
2909
2910
  /* Vector VSRI
2911
     NOTE: MVE_VSRI must appear in the table before
2912
     before MVE_VMOV_IMM_TO_VEC due to opcode aliasing.  */
2913
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2914
   MVE_VSRI,
2915
   0xff800450, 0xff801fd1,
2916
   "vsri%v.%19-21s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
2917
2918
  /* Vector VMOV immediate to vector,
2919
     undefinded for cmode == 1111 */
2920
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2921
   MVE_VMVN_IMM, 0xef800f70, 0xefb81ff0, UNDEFINED_INSTRUCTION},
2922
2923
  /* Vector VMOV immediate to vector,
2924
     cmode == 1101 */
2925
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2926
   MVE_VMOV_IMM_TO_VEC, 0xef800d50, 0xefb81fd0,
2927
   "vmov%v.%5,8-11s\t%13-15,22Q, %E"},
2928
2929
  /* Vector VMOV immediate to vector.  */
2930
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2931
   MVE_VMOV_IMM_TO_VEC,
2932
   0xef800050, 0xefb810d0,
2933
   "vmov%v.%5,8-11s\t%13-15,22Q, %E"},
2934
2935
  /* Vector VMOV two 32-bit lanes to two gprs, idx = 0.  */
2936
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2937
   MVE_VMOV2_VEC_LANE_TO_GP,
2938
   0xec000f00, 0xffb01ff0,
2939
   "vmov%c\t%0-3r, %16-19r, %{R:%13-15,22Q[2]%}, %{R:%13-15,22Q[0]%}"},
2940
2941
  /* Vector VMOV two 32-bit lanes to two gprs, idx = 1.  */
2942
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2943
   MVE_VMOV2_VEC_LANE_TO_GP,
2944
   0xec000f10, 0xffb01ff0,
2945
   "vmov%c\t%0-3r, %16-19r, %{R:%13-15,22Q[3]%}, %{R:%13-15,22Q[1]%}"},
2946
2947
  /* Vector VMOV Two gprs to two 32-bit lanes, idx = 0.  */
2948
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2949
   MVE_VMOV2_GP_TO_VEC_LANE,
2950
   0xec100f00, 0xffb01ff0,
2951
   "vmov%c\t%{R:%13-15,22Q[2]%}, %{R:%13-15,22Q[0]%}, %0-3r, %16-19r"},
2952
2953
  /* Vector VMOV Two gprs to two 32-bit lanes, idx = 1.  */
2954
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2955
   MVE_VMOV2_GP_TO_VEC_LANE,
2956
   0xec100f10, 0xffb01ff0,
2957
   "vmov%c\t%{R:%13-15,22Q[3]%}, %{R:%13-15,22Q[1]%}, %0-3r, %16-19r"},
2958
2959
  /* Vector VMOV Vector lane to gpr.  */
2960
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2961
   MVE_VMOV_VEC_LANE_TO_GP,
2962
   0xee100b10, 0xff100f1f,
2963
   "vmov%c.%u%5-6,21-22s\t%12-15r, %{R:%17-19,7Q[%N]%}"},
2964
2965
  /* Vector VSHLL T1 Variant.  Note: VSHLL T1 must appear before MVE_VMOVL due
2966
     to instruction opcode aliasing.  */
2967
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2968
   MVE_VSHLL_T1,
2969
   0xeea00f40, 0xefa00fd1,
2970
   "vshll%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
2971
2972
  /* Vector VMOVL long.  */
2973
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2974
   MVE_VMOVL,
2975
   0xeea00f40, 0xefa70fd1,
2976
   "vmovl%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q"},
2977
2978
  /* Vector VMOV and narrow.  */
2979
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2980
   MVE_VMOVN,
2981
   0xfe310e81, 0xffb30fd1,
2982
   "vmovn%T%v.i%18-19s\t%13-15,22Q, %1-3,5Q"},
2983
2984
  /* Floating point move extract.  */
2985
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2986
   MVE_VMOVX,
2987
   0xfeb00a40, 0xffbf0fd0,
2988
   "vmovx.f16\t%22,12-15F, %5,0-3F"},
2989
2990
  /* Vector VMUL floating-point T1 variant.  */
2991
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2992
   MVE_VMUL_FP_T1,
2993
   0xff000d50, 0xffa11f51,
2994
   "vmul%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2995
2996
  /* Vector VMUL floating-point T2 variant.  */
2997
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2998
   MVE_VMUL_FP_T2,
2999
   0xee310e60, 0xefb11f70,
3000
   "vmul%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3001
3002
  /* Vector VMUL T1 variant.  */
3003
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3004
   MVE_VMUL_VEC_T1,
3005
   0xef000950, 0xff811f51,
3006
   "vmul%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3007
3008
  /* Vector VMUL T2 variant.  */
3009
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3010
   MVE_VMUL_VEC_T2,
3011
   0xee011e60, 0xff811f70,
3012
   "vmul%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3013
3014
  /* Vector VMULH.  */
3015
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3016
   MVE_VMULH,
3017
   0xee010e01, 0xef811f51,
3018
   "vmulh%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3019
3020
  /* Vector VRMULH.  */
3021
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3022
   MVE_VRMULH,
3023
   0xee011e01, 0xef811f51,
3024
   "vrmulh%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3025
3026
  /* Vector VMULL integer.  */
3027
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3028
   MVE_VMULL_INT,
3029
   0xee010e00, 0xef810f51,
3030
   "vmull%T%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3031
3032
  /* Vector VMULL polynomial.  */
3033
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3034
   MVE_VMULL_POLY,
3035
   0xee310e00, 0xefb10f51,
3036
   "vmull%T%v.%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3037
3038
  /* Vector VMVN immediate to vector.  */
3039
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3040
   MVE_VMVN_IMM,
3041
   0xef800070, 0xefb810f0,
3042
   "vmvn%v.i%8-11s\t%13-15,22Q, %E"},
3043
3044
  /* Vector VMVN register.  */
3045
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3046
   MVE_VMVN_REG,
3047
   0xffb005c0, 0xffbf1fd1,
3048
   "vmvn%v\t%13-15,22Q, %1-3,5Q"},
3049
3050
  /* Vector VNEG floating point.  */
3051
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
3052
   MVE_VNEG_FP,
3053
   0xffb107c0, 0xffb31fd1,
3054
   "vneg%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
3055
3056
  /* Vector VNEG.  */
3057
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3058
   MVE_VNEG_VEC,
3059
   0xffb103c0, 0xffb31fd1,
3060
   "vneg%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
3061
3062
  /* Vector VORN, vector bitwise or not.  */
3063
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3064
   MVE_VORN,
3065
   0xef300150, 0xffb11f51,
3066
   "vorn%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3067
3068
  /* Vector VORR register.  */
3069
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3070
   MVE_VORR_REG,
3071
   0xef200150, 0xffb11f51,
3072
   "vorr%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3073
3074
  /* Vector VMOV, vector to vector move. While decoding MVE_VORR_REG if
3075
     "Qm==Qn", VORR should replaced by its alias VMOV. For that to happen
3076
     MVE_VMOV_VEC_TO_VEC need to placed after MVE_VORR_REG in this mve_opcodes
3077
     array.  */
3078
3079
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3080
   MVE_VMOV_VEC_TO_VEC,
3081
   0xef200150, 0xffb11f51,
3082
   "vmov%v\t%13-15,22Q, %17-19,7Q"},
3083
3084
  /* Vector VQDMULL T1 variant.  */
3085
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3086
   MVE_VQDMULL_T1,
3087
   0xee300f01, 0xefb10f51,
3088
   "vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3089
3090
  /* Vector VPNOT.  */
3091
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3092
   MVE_VPNOT,
3093
   0xfe310f4d, 0xffffffff,
3094
   "vpnot%v"},
3095
3096
  /* Vector VPSEL.  */
3097
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3098
   MVE_VPSEL,
3099
   0xfe310f01, 0xffb11f51,
3100
   "vpsel%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3101
3102
  /* Vector VQABS.  */
3103
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3104
   MVE_VQABS,
3105
   0xffb00740, 0xffb31fd1,
3106
   "vqabs%v.s%18-19s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3107
3108
  /* Vector VQADD T1 variant.  */
3109
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3110
   MVE_VQADD_T1,
3111
   0xef000050, 0xef811f51,
3112
   "vqadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3113
3114
  /* Vector VQADD T2 variant.  */
3115
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3116
   MVE_VQADD_T2,
3117
   0xee000f60, 0xef811f70,
3118
   "vqadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3119
3120
  /* Vector VQDMULL T2 variant.  */
3121
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3122
   MVE_VQDMULL_T2,
3123
   0xee300f60, 0xefb10f70,
3124
   "vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3125
3126
  /* Vector VQMOVN.  */
3127
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3128
   MVE_VQMOVN,
3129
   0xee330e01, 0xefb30fd1,
3130
   "vqmovn%T%v.%u%18-19s\t%13-15,22Q, %1-3,5Q"},
3131
3132
  /* Vector VQMOVUN.  */
3133
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3134
   MVE_VQMOVUN,
3135
   0xee310e81, 0xffb30fd1,
3136
   "vqmovun%T%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
3137
3138
  /* Vector VQDMLADH.  */
3139
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3140
   MVE_VQDMLADH,
3141
   0xee000e00, 0xff810f51,
3142
   "vqdmladh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3143
3144
  /* Vector VQRDMLADH.  */
3145
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3146
   MVE_VQRDMLADH,
3147
   0xee000e01, 0xff810f51,
3148
   "vqrdmladh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3149
3150
  /* Vector VQDMLAH.  */
3151
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3152
   MVE_VQDMLAH,
3153
   0xee000e60, 0xff811f70,
3154
   "vqdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3155
3156
  /* Vector VQRDMLAH.  */
3157
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3158
   MVE_VQRDMLAH,
3159
   0xee000e40, 0xff811f70,
3160
   "vqrdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3161
3162
  /* Vector VQDMLASH.  */
3163
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3164
   MVE_VQDMLASH,
3165
   0xee001e60, 0xff811f70,
3166
   "vqdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3167
3168
  /* Vector VQRDMLASH.  */
3169
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3170
   MVE_VQRDMLASH,
3171
   0xee001e40, 0xff811f70,
3172
   "vqrdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3173
3174
  /* Vector VQDMLSDH.  */
3175
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3176
   MVE_VQDMLSDH,
3177
   0xfe000e00, 0xff810f51,
3178
   "vqdmlsdh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3179
3180
  /* Vector VQRDMLSDH.  */
3181
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3182
   MVE_VQRDMLSDH,
3183
   0xfe000e01, 0xff810f51,
3184
   "vqrdmlsdh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3185
3186
  /* Vector VQDMULH T1 variant.  */
3187
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3188
   MVE_VQDMULH_T1,
3189
   0xef000b40, 0xff811f51,
3190
   "vqdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3191
3192
  /* Vector VQRDMULH T2 variant.  */
3193
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3194
   MVE_VQRDMULH_T2,
3195
   0xff000b40, 0xff811f51,
3196
   "vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3197
3198
  /* Vector VQDMULH T3 variant.  */
3199
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3200
   MVE_VQDMULH_T3,
3201
   0xee010e60, 0xff811f70,
3202
   "vqdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3203
3204
  /* Vector VQRDMULH T4 variant.  */
3205
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3206
   MVE_VQRDMULH_T4,
3207
   0xfe010e60, 0xff811f70,
3208
   "vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3209
3210
  /* Vector VQNEG.  */
3211
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3212
   MVE_VQNEG,
3213
   0xffb007c0, 0xffb31fd1,
3214
   "vqneg%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
3215
3216
  /* Vector VQRSHL T1 variant.  */
3217
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3218
   MVE_VQRSHL_T1,
3219
   0xef000550, 0xef811f51,
3220
   "vqrshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3221
3222
  /* Vector VQRSHL T2 variant.  */
3223
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3224
   MVE_VQRSHL_T2,
3225
   0xee331ee0, 0xefb31ff0,
3226
   "vqrshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3227
3228
  /* Vector VQRSHRN.  */
3229
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3230
   MVE_VQRSHRN,
3231
   0xee800f41, 0xefa00fd1,
3232
   "vqrshrn%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
3233
3234
  /* Vector VQRSHRUN.  */
3235
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3236
   MVE_VQRSHRUN,
3237
   0xfe800fc0, 0xffa00fd1,
3238
   "vqrshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
3239
3240
  /* Vector VQSHL T1 Variant.  */
3241
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3242
   MVE_VQSHL_T1,
3243
   0xee311ee0, 0xefb31ff0,
3244
   "vqshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3245
3246
  /* Vector VQSHL T4 Variant.  */
3247
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3248
   MVE_VQSHL_T4,
3249
   0xef000450, 0xef811f51,
3250
   "vqshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3251
3252
  /* Vector VQSHRN.  */
3253
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3254
   MVE_VQSHRN,
3255
   0xee800f40, 0xefa00fd1,
3256
   "vqshrn%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
3257
3258
  /* Vector VQSHRUN.  */
3259
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3260
   MVE_VQSHRUN,
3261
   0xee800fc0, 0xffa00fd1,
3262
   "vqshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
3263
3264
  /* Vector VQSUB T1 Variant.  */
3265
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3266
   MVE_VQSUB_T1,
3267
   0xef000250, 0xef811f51,
3268
   "vqsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3269
3270
  /* Vector VQSUB T2 Variant.  */
3271
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3272
   MVE_VQSUB_T2,
3273
   0xee001f60, 0xef811f70,
3274
   "vqsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3275
3276
  /* Vector VREV16.  */
3277
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3278
   MVE_VREV16,
3279
   0xffb00140, 0xffb31fd1,
3280
   "vrev16%v.8\t%13-15,22Q, %1-3,5Q"},
3281
3282
  /* Vector VREV32.  */
3283
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3284
   MVE_VREV32,
3285
   0xffb000c0, 0xffb31fd1,
3286
   "vrev32%v.%18-19s\t%13-15,22Q, %1-3,5Q"},
3287
3288
  /* Vector VREV64.  */
3289
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3290
   MVE_VREV64,
3291
   0xffb00040, 0xffb31fd1,
3292
   "vrev64%v.%18-19s\t%13-15,22Q, %1-3,5Q"},
3293
3294
  /* Vector VRINT floating point.  */
3295
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
3296
   MVE_VRINT_FP,
3297
   0xffb20440, 0xffb31c51,
3298
   "vrint%m%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
3299
3300
  /* Vector VRMLALDAVH.  */
3301
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3302
   MVE_VRMLALDAVH,
3303
   0xee800f00, 0xef811f51,
3304
   "vrmlalvh%5A%v.%u32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
3305
3306
  /* Vector VRMLALDAVH.  */
3307
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3308
   MVE_VRMLALDAVH,
3309
   0xee801f00, 0xef811f51,
3310
   "vrmlaldavh%5Ax%v.%u32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
3311
3312
  /* Vector VRSHL T1 Variant.  */
3313
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3314
   MVE_VRSHL_T1,
3315
   0xef000540, 0xef811f51,
3316
   "vrshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3317
3318
  /* Vector VRSHL T2 Variant.  */
3319
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3320
   MVE_VRSHL_T2,
3321
   0xee331e60, 0xefb31ff0,
3322
   "vrshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3323
3324
  /* Vector VRSHRN.  */
3325
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3326
   MVE_VRSHRN,
3327
   0xfe800fc1, 0xffa00fd1,
3328
   "vrshrn%T%v.i%19-20s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
3329
3330
  /* Vector VSBC.  */
3331
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3332
   MVE_VSBC,
3333
   0xfe300f00, 0xffb10f51,
3334
   "vsbc%12I%v.i32\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3335
3336
  /* Vector VSHL T2 Variant.  */
3337
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3338
   MVE_VSHL_T2,
3339
   0xee311e60, 0xefb31ff0,
3340
   "vshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3341
3342
  /* Vector VSHL T3 Variant.  */
3343
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3344
   MVE_VSHL_T3,
3345
   0xef000440, 0xef811f51,
3346
   "vshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3347
3348
  /* Vector VSHLC.  */
3349
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3350
   MVE_VSHLC,
3351
   0xeea00fc0, 0xffa01ff0,
3352
   "vshlc%v\t%13-15,22Q, %0-3r, %{I:#%16-20d%}"},
3353
3354
  /* Vector VSHLL T2 Variant.  */
3355
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3356
   MVE_VSHLL_T2,
3357
   0xee310e01, 0xefb30fd1,
3358
   "vshll%T%v.%u%18-19s\t%13-15,22Q, %1-3,5Q, %{I:#%18-19d%}"},
3359
3360
  /* Vector VSHRN.  */
3361
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3362
   MVE_VSHRN,
3363
   0xee800fc1, 0xffa00fd1,
3364
   "vshrn%T%v.i%19-20s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
3365
3366
  /* Vector VST2 no writeback.  */
3367
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3368
   MVE_VST2,
3369
   0xfc801e00, 0xffb01e5f,
3370
   "vst2%5d.%7-8s\t%B, [%16-19r]"},
3371
3372
  /* Vector VST2 writeback.  */
3373
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3374
   MVE_VST2,
3375
   0xfca01e00, 0xffb01e5f,
3376
   "vst2%5d.%7-8s\t%B, [%16-19r]!"},
3377
3378
  /* Vector VST4 no writeback.  */
3379
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3380
   MVE_VST4,
3381
   0xfc801e01, 0xffb01e1f,
3382
   "vst4%5-6d.%7-8s\t%B, [%16-19r]"},
3383
3384
  /* Vector VST4 writeback.  */
3385
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3386
   MVE_VST4,
3387
   0xfca01e01, 0xffb01e1f,
3388
   "vst4%5-6d.%7-8s\t%B, [%16-19r]!"},
3389
3390
  /* Vector VSTRB scatter store, T1 variant.  */
3391
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3392
   MVE_VSTRB_SCATTER_T1,
3393
   0xec800e00, 0xffb01e50,
3394
   "vstrb%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"},
3395
3396
  /* Vector VSTRH scatter store, T2 variant.  */
3397
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3398
   MVE_VSTRH_SCATTER_T2,
3399
   0xec800e10, 0xffb01e50,
3400
   "vstrh%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
3401
3402
  /* Vector VSTRW scatter store, T3 variant.  */
3403
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3404
   MVE_VSTRW_SCATTER_T3,
3405
   0xec800e40, 0xffb01e50,
3406
   "vstrw%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
3407
3408
  /* Vector VSTRD scatter store, T4 variant.  */
3409
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3410
   MVE_VSTRD_SCATTER_T4,
3411
   0xec800fd0, 0xffb01fd0,
3412
   "vstrd%v.64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
3413
3414
  /* Vector VSTRW scatter store, T5 variant.  */
3415
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3416
   MVE_VSTRW_SCATTER_T5,
3417
   0xfd001e00, 0xff111f00,
3418
   "vstrw%v.32\t%13-15,22Q, [%17-19,7Q, %{I:#%a%0-6i%}]%w"},
3419
3420
  /* Vector VSTRD scatter store, T6 variant.  */
3421
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3422
   MVE_VSTRD_SCATTER_T6,
3423
   0xfd001f00, 0xff111f00,
3424
   "vstrd%v.64\t%13-15,22Q, [%17-19,7Q, %{I:#%a%0-6i%}]%w"},
3425
3426
  /* Vector VSTRB.  */
3427
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3428
   MVE_VSTRB_T1,
3429
   0xec000e00, 0xfe581e00,
3430
   "vstrb%v.%7-8s\t%13-15Q, %d"},
3431
3432
  /* Vector VSTRH.  */
3433
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3434
   MVE_VSTRH_T2,
3435
   0xec080e00, 0xfe581e00,
3436
   "vstrh%v.%7-8s\t%13-15Q, %d"},
3437
3438
  /* Vector VSTRB variant T5.  */
3439
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3440
   MVE_VSTRB_T5,
3441
   0xec001e00, 0xfe101f80,
3442
   "vstrb%v.8\t%13-15,22Q, %d"},
3443
3444
  /* Vector VSTRH variant T6.  */
3445
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3446
   MVE_VSTRH_T6,
3447
   0xec001e80, 0xfe101f80,
3448
   "vstrh%v.16\t%13-15,22Q, %d"},
3449
3450
  /* Vector VSTRW variant T7.  */
3451
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3452
   MVE_VSTRW_T7,
3453
   0xec001f00, 0xfe101f80,
3454
   "vstrw%v.32\t%13-15,22Q, %d"},
3455
3456
  /* Vector VSUB floating point T1 variant.  */
3457
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
3458
   MVE_VSUB_FP_T1,
3459
   0xef200d40, 0xffa11f51,
3460
   "vsub%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3461
3462
  /* Vector VSUB floating point T2 variant.  */
3463
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
3464
   MVE_VSUB_FP_T2,
3465
   0xee301f40, 0xefb11f70,
3466
   "vsub%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3467
3468
  /* Vector VSUB T1 variant.  */
3469
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3470
   MVE_VSUB_VEC_T1,
3471
   0xff000840, 0xff811f51,
3472
   "vsub%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3473
3474
  /* Vector VSUB T2 variant.  */
3475
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3476
   MVE_VSUB_VEC_T2,
3477
   0xee011f40, 0xff811f70,
3478
   "vsub%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3479
3480
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3481
   MVE_ASRLI,
3482
   0xea50012f, 0xfff1813f,
3483
   "asrl%c\t%17-19l, %9-11h, %j"},
3484
3485
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3486
   MVE_ASRL,
3487
   0xea50012d, 0xfff101ff,
3488
   "asrl%c\t%17-19l, %9-11h, %12-15S"},
3489
3490
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3491
   MVE_LSLLI,
3492
   0xea50010f, 0xfff1813f,
3493
   "lsll%c\t%17-19l, %9-11h, %j"},
3494
3495
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3496
   MVE_LSLL,
3497
   0xea50010d, 0xfff101ff,
3498
   "lsll%c\t%17-19l, %9-11h, %12-15S"},
3499
3500
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3501
   MVE_LSRL,
3502
   0xea50011f, 0xfff1813f,
3503
   "lsrl%c\t%17-19l, %9-11h, %j"},
3504
3505
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3506
   MVE_SQRSHRL,
3507
   0xea51012d, 0xfff1017f,
3508
   "sqrshrl%c\t%17-19l, %9-11h, %k, %12-15S"},
3509
3510
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3511
   MVE_SQRSHR,
3512
   0xea500f2d, 0xfff00fff,
3513
   "sqrshr%c\t%16-19S, %12-15S"},
3514
3515
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3516
   MVE_SQSHLL,
3517
   0xea51013f, 0xfff1813f,
3518
   "sqshll%c\t%17-19l, %9-11h, %j"},
3519
3520
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3521
   MVE_SQSHL,
3522
   0xea500f3f, 0xfff08f3f,
3523
   "sqshl%c\t%16-19S, %j"},
3524
3525
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3526
   MVE_SRSHRL,
3527
   0xea51012f, 0xfff1813f,
3528
   "srshrl%c\t%17-19l, %9-11h, %j"},
3529
3530
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3531
   MVE_SRSHR,
3532
   0xea500f2f, 0xfff08f3f,
3533
   "srshr%c\t%16-19S, %j"},
3534
3535
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3536
   MVE_UQRSHLL,
3537
   0xea51010d, 0xfff1017f,
3538
   "uqrshll%c\t%17-19l, %9-11h, %k, %12-15S"},
3539
3540
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3541
   MVE_UQRSHL,
3542
   0xea500f0d, 0xfff00fff,
3543
   "uqrshl%c\t%16-19S, %12-15S"},
3544
3545
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3546
   MVE_UQSHLL,
3547
    0xea51010f, 0xfff1813f,
3548
   "uqshll%c\t%17-19l, %9-11h, %j"},
3549
3550
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3551
   MVE_UQSHL,
3552
   0xea500f0f, 0xfff08f3f,
3553
   "uqshl%c\t%16-19S, %j"},
3554
3555
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3556
   MVE_URSHRL,
3557
    0xea51011f, 0xfff1813f,
3558
   "urshrl%c\t%17-19l, %9-11h, %j"},
3559
3560
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3561
   MVE_URSHR,
3562
   0xea500f1f, 0xfff08f3f,
3563
   "urshr%c\t%16-19S, %j"},
3564
3565
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3566
   MVE_CSINC,
3567
   0xea509000, 0xfff0f000,
3568
   "csinc\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3569
3570
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3571
   MVE_CSINV,
3572
   0xea50a000, 0xfff0f000,
3573
   "csinv\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3574
3575
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3576
   MVE_CSET,
3577
   0xea5f900f, 0xfffff00f,
3578
   "cset\t%8-11S, %4-7C"},
3579
3580
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3581
   MVE_CSETM,
3582
   0xea5fa00f, 0xfffff00f,
3583
   "csetm\t%8-11S, %4-7C"},
3584
3585
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3586
   MVE_CSEL,
3587
   0xea508000, 0xfff0f000,
3588
   "csel\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3589
3590
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3591
   MVE_CSNEG,
3592
   0xea50b000, 0xfff0f000,
3593
   "csneg\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3594
3595
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3596
   MVE_CINC,
3597
   0xea509000, 0xfff0f000,
3598
   "cinc\t%8-11S, %16-19Z, %4-7C"},
3599
3600
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3601
   MVE_CINV,
3602
   0xea50a000, 0xfff0f000,
3603
   "cinv\t%8-11S, %16-19Z, %4-7C"},
3604
3605
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3606
   MVE_CNEG,
3607
   0xea50b000, 0xfff0f000,
3608
   "cneg\t%8-11S, %16-19Z, %4-7C"},
3609
3610
  {ARM_FEATURE_CORE_LOW (0),
3611
   MVE_NONE,
3612
   0x00000000, 0x00000000, 0}
3613
};
3614
3615
/* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb.  All three are partially
3616
   ordered: they must be searched linearly from the top to obtain a correct
3617
   match.  */
3618
3619
/* print_insn_arm recognizes the following format control codes:
3620
3621
   %%     %
3622
3623
   %a     print address for ldr/str instruction
3624
   %s                   print address for ldr/str halfword/signextend instruction
3625
   %S                   like %s but allow UNPREDICTABLE addressing
3626
   %b     print branch destination
3627
   %c     print condition code (always bits 28-31)
3628
   %m     print register mask for ldm/stm instruction
3629
   %o     print operand2 (immediate or register + shift)
3630
   %p     print 'p' iff bits 12-15 are 15
3631
   %t     print 't' iff bit 21 set and bit 24 clear
3632
   %B     print arm BLX(1) destination
3633
   %C     print the PSR sub type.
3634
   %U     print barrier type.
3635
   %P     print address for pli instruction.
3636
3637
   %<bitfield>r   print as an ARM register
3638
   %<bitfield>T   print as an ARM register + 1
3639
   %<bitfield>R   as %r but r15 is UNPREDICTABLE
3640
   %<bitfield>{r|R}u    as %{r|R} but if matches the other %u field then is UNPREDICTABLE
3641
   %<bitfield>{r|R}U    as %{r|R} but if matches the other %U field then is UNPREDICTABLE
3642
   %<bitfield>d   print the bitfield in decimal
3643
   %<bitfield>W         print the bitfield plus one in decimal
3644
   %<bitfield>x   print the bitfield in hex
3645
   %<bitfield>X   print the bitfield as 1 hex digit without leading "0x"
3646
3647
   %<bitfield>'c  print specified char iff bitfield is all ones
3648
   %<bitfield>`c  print specified char iff bitfield is all zeroes
3649
   %<bitfield>?ab...    select from array of values in big endian order
3650
3651
   %e                   print arm SMI operand (bits 0..7,8..19).
3652
   %E     print the LSB and WIDTH fields of a BFI or BFC instruction.
3653
   %V                   print the 16-bit immediate field of a MOVT or MOVW instruction.
3654
   %R     print the SPSR/CPSR or banked register of an MRS.  */
3655
3656
static const struct opcode32 arm_opcodes[] =
3657
{
3658
  /* ARM instructions.  */
3659
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3660
    0xe1a00000, 0xffffffff, "nop\t\t\t@ (mov r0, r0)"},
3661
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3662
    0xe7f000f0, 0xfff000f0, "udf\t%{I:#%e%}"},
3663
3664
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T | ARM_EXT_V5),
3665
    0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
3666
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
3667
    0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"},
3668
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
3669
    0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3670
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V2S),
3671
    0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"},
3672
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
3673
    0x00800090, 0x0fa000f0,
3674
    "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3675
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
3676
    0x00a00090, 0x0fa000f0,
3677
    "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3678
3679
  /* V8.2 RAS extension instructions.  */
3680
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
3681
    0xe320f010, 0xffffffff, "esb"},
3682
3683
  /* V8-R instructions.  */
3684
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8R),
3685
    0xf57ff04c, 0xffffffff, "dfb"},
3686
3687
  /* V8 instructions.  */
3688
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3689
    0x0320f005, 0x0fffffff, "sevl"},
3690
  /* Defined in V8 but is in NOP space so available to all arch.  */
3691
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3692
    0xe1000070, 0xfff000f0, "hlt\t%{I:0x%16-19X%12-15X%8-11X%0-3X%}"},
3693
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS),
3694
    0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"},
3695
  {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3696
    0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
3697
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3698
    0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"},
3699
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3700
    0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"},
3701
  {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3702
    0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"},
3703
  {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3704
    0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
3705
  {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3706
    0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"},
3707
  {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3708
    0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
3709
  {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3710
    0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"},
3711
  {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3712
    0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"},
3713
  {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3714
    0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"},
3715
  {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3716
    0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"},
3717
  {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3718
    0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"},
3719
  {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3720
    0x01f00c9f, 0x0ff00fff, "ldah%c\t%12-15r, [%16-19R]"},
3721
  /* CRC32 instructions.  */
3722
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
3723
    0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"},
3724
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
3725
    0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"},
3726
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
3727
    0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"},
3728
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
3729
    0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"},
3730
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
3731
    0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"},
3732
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
3733
    0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"},
3734
3735
  /* Privileged Access Never extension instructions.  */
3736
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),
3737
    0xf1100000, 0xfffffdff, "setpan\t%{I:#%9-9d%}"},
3738
3739
  /* Virtualization Extension instructions.  */
3740
  {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x0160006e, 0x0fffffff, "eret%c"},
3741
  {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x01400070, 0x0ff000f0, "hvc%c\t%e"},
3742
3743
  /* Integer Divide Extension instructions.  */
3744
  {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
3745
    0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"},
3746
  {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
3747
    0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"},
3748
3749
  /* MP Extension instructions.  */
3750
  {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf410f000, 0xfc70f000, "pldw\t%a"},
3751
3752
  /* Speculation Barriers.  */
3753
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xe320f014, 0xffffffff, "csdb"},
3754
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff040, 0xffffffff, "ssbb"},
3755
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff044, 0xffffffff, "pssbb"},
3756
3757
  /* V7 instructions.  */
3758
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf450f000, 0xfd70f000, "pli\t%P"},
3759
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0x0320f0f0, 0x0ffffff0, "dbg%c\t%{I:#%0-3d%}"},
3760
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff051, 0xfffffff3, "dmb\t%U"},
3761
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff041, 0xfffffff3, "dsb\t%U"},
3762
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff050, 0xfffffff0, "dmb\t%U"},
3763
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff040, 0xfffffff0, "dsb\t%U"},
3764
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff060, 0xfffffff0, "isb\t%U"},
3765
   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
3766
    0x0320f000, 0x0fffffff, "nop%c\t{%{I:%0-7d%}}"},
3767
3768
  /* ARM V6T2 instructions.  */
3769
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3770
    0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"},
3771
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3772
    0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"},
3773
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3774
    0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3775
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3776
    0x002000b0, 0x0f3000f0, "strht%c\t%12-15R, %S"},
3777
3778
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3779
    0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION },
3780
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3781
    0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"},
3782
3783
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3784
    0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"},
3785
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3786
    0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"},
3787
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3788
    0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"},
3789
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3790
    0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, %{I:#%7-11d%}, %{I:#%16-20W%}"},
3791
3792
  /* ARM Security extension instructions.  */
3793
  {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
3794
    0x01600070, 0x0ff000f0, "smc%c\t%e"},
3795
3796
  /* ARM V6K instructions.  */
3797
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3798
    0xf57ff01f, 0xffffffff, "clrex"},
3799
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3800
    0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"},
3801
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3802
    0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"},
3803
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3804
    0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"},
3805
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3806
    0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"},
3807
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3808
    0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"},
3809
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3810
    0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"},
3811
3812
  /* ARMv8.5-A instructions.  */
3813
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf57ff070, 0xffffffff, "sb"},
3814
3815
  /* ARM V6K NOP hints.  */
3816
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3817
    0x0320f001, 0x0fffffff, "yield%c"},
3818
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3819
    0x0320f002, 0x0fffffff, "wfe%c"},
3820
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3821
    0x0320f003, 0x0fffffff, "wfi%c"},
3822
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3823
    0x0320f004, 0x0fffffff, "sev%c"},
3824
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3825
    0x0320f000, 0x0fffff00, "nop%c\t{%{I:%0-7d%}}"},
3826
3827
  /* ARM V6 instructions.  */
3828
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3829
    0xf1080000, 0xfffffe3f, "cpsie\t%{B:%8'a%7'i%6'f%}"},
3830
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3831
    0xf10a0000, 0xfffffe20, "cpsie\t%{B:%8'a%7'i%6'f%}, %{I:#%0-4d%}"},
3832
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3833
    0xf10C0000, 0xfffffe3f, "cpsid\t%{B:%8'a%7'i%6'f%}"},
3834
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3835
    0xf10e0000, 0xfffffe20, "cpsid\t%{B:%8'a%7'i%6'f%}, %{I:#%0-4d%}"},
3836
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3837
    0xf1000000, 0xfff1fe20, "cps\t%{I:#%0-4d%}"},
3838
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3839
    0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"},
3840
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3841
    0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, %{B:lsl%} %{I:#%7-11d%}"},
3842
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3843
    0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, %{B:asr%} %{I:#32%}"},
3844
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3845
    0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, %{B:asr%} %{I:#%7-11d%}"},
3846
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3847
    0x01900f9f, 0x0ff00fff, "ldrex%c\t%{R:r%12-15d%}, [%16-19R]"},
3848
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3849
    0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"},
3850
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3851
    0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"},
3852
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3853
    0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"},
3854
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3855
    0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"},
3856
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3857
    0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"},
3858
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3859
    0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"},
3860
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3861
    0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"},
3862
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3863
    0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"},
3864
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3865
    0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"},
3866
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3867
    0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"},
3868
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3869
    0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"},
3870
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3871
    0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"},
3872
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3873
    0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"},
3874
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3875
    0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"},
3876
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3877
    0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"},
3878
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3879
    0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"},
3880
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3881
    0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"},
3882
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3883
    0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"},
3884
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3885
    0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"},
3886
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3887
    0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"},
3888
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3889
    0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"},
3890
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3891
    0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"},
3892
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3893
    0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"},
3894
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3895
    0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"},
3896
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3897
    0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"},
3898
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3899
    0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"},
3900
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3901
    0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"},
3902
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3903
    0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"},
3904
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3905
    0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"},
3906
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3907
    0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"},
3908
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3909
    0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"},
3910
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3911
    0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"},
3912
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3913
    0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"},
3914
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3915
    0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"},
3916
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3917
    0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"},
3918
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3919
    0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"},
3920
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3921
    0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"},
3922
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3923
    0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"},
3924
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3925
    0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"},
3926
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3927
    0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"},
3928
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3929
    0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"},
3930
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3931
    0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, %{B:ror%} %{I:#8%}"},
3932
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3933
    0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, %{B:ror%} %{I:#16%}"},
3934
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3935
    0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, %{B:ror%} %{I:#24%}"},
3936
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3937
    0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"},
3938
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3939
    0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, %{B:ror%} %{I:#8%}"},
3940
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3941
    0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, %{B:ror%} %{I:#16%}"},
3942
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3943
    0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, %{B:ror%} %{I:#24%}"},
3944
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3945
    0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"},
3946
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3947
    0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, %{B:ror%} %{I:#8%}"},
3948
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3949
    0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, %{B:ror%} %{I:#16%}"},
3950
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3951
    0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, %{B:ror%} %{I:#24%}"},
3952
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3953
    0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"},
3954
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3955
    0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, %{B:ror%} %{I:#8%}"},
3956
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3957
    0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, %{B:ror%} %{I:#16%}"},
3958
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3959
    0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, %{B:ror%} %{I:#24%}"},
3960
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3961
    0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"},
3962
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3963
    0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, %{B:ror%} %{I:#8%}"},
3964
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3965
    0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, %{B:ror%} %{I:#16%}"},
3966
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3967
    0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, %{B:ror%} %{I:#24%}"},
3968
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3969
    0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"},
3970
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3971
    0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, %{B:ror%} %{I:#8%}"},
3972
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3973
    0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, %{B:ror%} %{I:#16%}"},
3974
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3975
    0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, %{B:ror%} %{I:#24%}"},
3976
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3977
    0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"},
3978
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3979
    0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#8%}"},
3980
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3981
    0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#16%}"},
3982
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3983
    0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#24%}"},
3984
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3985
    0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"},
3986
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3987
    0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#8%}"},
3988
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3989
    0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#16%}"},
3990
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3991
    0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#24%}"},
3992
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3993
    0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"},
3994
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3995
    0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#8%}"},
3996
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3997
    0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#16%}"},
3998
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3999
    0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#24%}"},
4000
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4001
    0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"},
4002
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4003
    0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#8%}"},
4004
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4005
    0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#16%}"},
4006
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4007
    0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#24%}"},
4008
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4009
    0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"},
4010
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4011
    0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#8%}"},
4012
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4013
    0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#16%}"},
4014
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4015
    0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR %{I:#24%}"},
4016
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4017
    0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"},
4018
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4019
    0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#8%}"},
4020
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4021
    0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#16%}"},
4022
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4023
    0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#24%}"},
4024
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4025
    0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"},
4026
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4027
    0xf1010000, 0xfffffc00, "setend\t%{B:%9?ble%}"},
4028
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4029
    0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"},
4030
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4031
    0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"},
4032
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4033
    0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4034
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4035
    0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
4036
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4037
    0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4038
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4039
    0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
4040
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4041
    0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"},
4042
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4043
    0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4044
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4045
    0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4046
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4047
    0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, %{I:#%0-4d%}"},
4048
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4049
    0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, %{I:#%16-20W%}, %0-3R"},
4050
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4051
    0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, %{I:#%16-20W%}, %0-3R, %{B:lsl%} %{I:#%7-11d%}"},
4052
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4053
    0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, %{I:#%16-20W%}, %0-3R, %{B:asr%} %{I:#%7-11d%}"},
4054
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4055
    0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, %{I:#%16-19W%}, %0-3r"},
4056
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4057
    0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"},
4058
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4059
    0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"},
4060
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4061
    0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"},
4062
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4063
    0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4064
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4065
    0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, %{I:#%16-20d%}, %0-3R"},
4066
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4067
    0x06e00010, 0x0fe00070, "usat%c\t%12-15R, %{I:#%16-20d%}, %0-3R, %{B:lsl%} %{I:#%7-11d%}"},
4068
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4069
    0x06e00050, 0x0fe00070, "usat%c\t%12-15R, %{I:#%16-20d%}, %0-3R, %{B:asr%} %{I:#%7-11d%}"},
4070
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4071
    0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, %{I:#%16-19d%}, %0-3R"},
4072
4073
  /* V5J instruction.  */
4074
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5J),
4075
    0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"},
4076
4077
  /* V5 Instructions.  */
4078
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
4079
    0xe1200070, 0xfff000f0,
4080
    "bkpt\t%{I:0x%16-19X%12-15X%8-11X%0-3X%}"},
4081
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
4082
    0xfa000000, 0xfe000000, "blx\t%B"},
4083
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
4084
    0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"},
4085
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
4086
    0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"},
4087
4088
  /* V5E "El Segundo" Instructions.  */
4089
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
4090
    0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"},
4091
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
4092
    0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"},
4093
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
4094
    0xf450f000, 0xfc70f000, "pld\t%a"},
4095
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4096
    0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4097
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4098
    0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4099
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4100
    0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4101
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4102
    0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"},
4103
4104
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4105
    0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4106
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4107
    0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"},
4108
4109
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4110
    0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
4111
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4112
    0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
4113
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4114
    0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
4115
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4116
    0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
4117
4118
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4119
    0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"},
4120
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4121
    0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"},
4122
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4123
    0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"},
4124
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4125
    0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"},
4126
4127
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4128
    0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"},
4129
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4130
    0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"},
4131
4132
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4133
    0x01000050, 0x0ff00ff0,  "qadd%c\t%12-15R, %0-3R, %16-19R"},
4134
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4135
    0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"},
4136
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4137
    0x01200050, 0x0ff00ff0,  "qsub%c\t%12-15R, %0-3R, %16-19R"},
4138
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4139
    0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"},
4140
4141
  /* ARM Instructions.  */
4142
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4143
    0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t@ (str%c %12-15r, %a)"},
4144
4145
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4146
    0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"},
4147
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4148
    0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"},
4149
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4150
    0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"},
4151
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4152
    0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"},
4153
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4154
    0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"},
4155
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4156
    0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"},
4157
4158
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4159
    0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"},
4160
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4161
    0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"},
4162
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4163
    0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"},
4164
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4165
    0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"},
4166
4167
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4168
    0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION},
4169
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4170
    0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"},
4171
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4172
    0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION},
4173
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4174
    0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"},
4175
4176
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4177
    0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"},
4178
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4179
    0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"},
4180
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4181
    0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"},
4182
4183
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4184
    0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"},
4185
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4186
    0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"},
4187
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4188
    0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"},
4189
4190
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4191
    0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"},
4192
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4193
    0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"},
4194
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4195
    0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"},
4196
4197
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4198
    0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"},
4199
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4200
    0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"},
4201
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4202
    0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"},
4203
4204
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4205
    0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"},
4206
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4207
    0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"},
4208
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4209
    0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"},
4210
4211
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4212
    0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"},
4213
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4214
    0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"},
4215
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4216
    0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"},
4217
4218
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4219
    0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"},
4220
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4221
    0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"},
4222
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4223
    0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"},
4224
4225
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4226
    0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"},
4227
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4228
    0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"},
4229
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4230
    0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"},
4231
4232
  {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT),
4233
    0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"},
4234
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
4235
    0x0120f000, 0x0db0f000, "msr%c\t%C, %o"},
4236
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
4237
    0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"},
4238
4239
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4240
    0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"},
4241
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4242
    0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"},
4243
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4244
    0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"},
4245
4246
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4247
    0x03300000, 0x0ff00000, "teq%p%c\t%16-19r, %o"},
4248
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4249
    0x01300000, 0x0ff00010, "teq%p%c\t%16-19r, %o"},
4250
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4251
    0x01300010, 0x0ff00010, "teq%p%c\t%16-19R, %o"},
4252
4253
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4254
    0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"},
4255
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4256
    0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"},
4257
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4258
    0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"},
4259
4260
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4261
    0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"},
4262
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4263
    0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"},
4264
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4265
    0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"},
4266
4267
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4268
    0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"},
4269
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4270
    0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"},
4271
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4272
    0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"},
4273
4274
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4275
    0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"},
4276
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4277
    0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"},
4278
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4279
    0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"},
4280
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4281
    0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"},
4282
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4283
    0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"},
4284
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4285
    0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"},
4286
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4287
    0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"},
4288
4289
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4290
    0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"},
4291
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4292
    0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"},
4293
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4294
    0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"},
4295
4296
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4297
    0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"},
4298
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4299
    0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"},
4300
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4301
    0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"},
4302
4303
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4304
    0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION},
4305
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4306
    0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t@ (ldr%c %12-15r, %a)"},
4307
4308
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4309
    0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"},
4310
4311
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4312
    0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"},
4313
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4314
    0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"},
4315
4316
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4317
    0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4318
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4319
    0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4320
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4321
    0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4322
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4323
    0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4324
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4325
    0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4326
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4327
    0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4328
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4329
    0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4330
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4331
    0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4332
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4333
    0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4334
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4335
    0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4336
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4337
    0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4338
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4339
    0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4340
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4341
    0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4342
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4343
    0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4344
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4345
    0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4346
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4347
    0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4348
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4349
    0x092d0000, 0x0fff0000, "push%c\t%m"},
4350
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4351
    0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"},
4352
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4353
    0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
4354
4355
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4356
    0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4357
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4358
    0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4359
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4360
    0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4361
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4362
    0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4363
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4364
    0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4365
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4366
    0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4367
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4368
    0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4369
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4370
    0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4371
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4372
    0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4373
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4374
    0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4375
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4376
    0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4377
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4378
    0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4379
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4380
    0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4381
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4382
    0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4383
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4384
    0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4385
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4386
    0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4387
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4388
    0x08bd0000, 0x0fff0000, "pop%c\t%m"},
4389
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4390
    0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"},
4391
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4392
    0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
4393
4394
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4395
    0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
4396
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4397
    0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
4398
4399
  /* The rest.  */
4400
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
4401
    0x03200000, 0x0fff00ff, "nop%c\t{%{I:%0-7d%}}" UNPREDICTABLE_INSTRUCTION},
4402
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4403
    0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
4404
  {ARM_FEATURE_CORE_LOW (0),
4405
    0x00000000, 0x00000000, 0}
4406
};
4407
4408
/* print_insn_thumb16 recognizes the following format control codes:
4409
4410
   %S                   print Thumb register (bits 3..5 as high number if bit 6 set)
4411
   %D                   print Thumb register (bits 0..2 as high number if bit 7 set)
4412
   %<bitfield>I         print bitfield as a signed decimal
4413
          (top bit of range being the sign bit)
4414
   %N                   print Thumb register mask (with LR)
4415
   %O                   print Thumb register mask (with PC)
4416
   %M                   print Thumb register mask
4417
   %b     print CZB's 6-bit unsigned branch destination
4418
   %s     print Thumb right-shift immediate (6..10; 0 == 32).
4419
   %c     print the condition code
4420
   %C     print the condition code, or "s" if not conditional
4421
   %x     print warning if conditional an not at end of IT block"
4422
   %X     print "\t@ unpredictable <IT:code>" if conditional
4423
   %I     print IT instruction suffix and operands
4424
   %W     print Thumb Writeback indicator for LDMIA
4425
   %<bitfield>r   print bitfield as an ARM register
4426
   %<bitfield>d   print bitfield as a decimal
4427
   %<bitfield>H         print (bitfield * 2) as a decimal
4428
   %<bitfield>W         print (bitfield * 4) as a decimal
4429
   %<bitfield>a         print (bitfield * 4) as a pc-rel offset + decoded symbol
4430
   %<bitfield>B         print Thumb branch destination (signed displacement)
4431
   %<bitfield>c         print bitfield as a condition code
4432
   %<bitnum>'c    print specified char iff bit is one
4433
   %<bitnum>?ab   print a if bit is one else print b.  */
4434
4435
static const struct opcode16 thumb_opcodes[] =
4436
{
4437
  /* Thumb instructions.  */
4438
4439
  /* ARMv8-M Security Extensions instructions.  */
4440
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4784, 0xff87, "blxns\t%3-6r"},
4441
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4704, 0xff87, "bxns\t%3-6r"},
4442
4443
  /* ARM V8 instructions.  */
4444
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),  0xbf50, 0xffff, "sevl%c"},
4445
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),  0xba80, 0xffc0, "hlt\t%0-5x"},
4446
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),  0xb610, 0xfff7, "setpan\t%{I:#%3-3d%}"},
4447
4448
  /* ARM V6K no-argument instructions.  */
4449
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xffff, "nop%c"},
4450
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf10, 0xffff, "yield%c"},
4451
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf20, 0xffff, "wfe%c"},
4452
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf30, 0xffff, "wfi%c"},
4453
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf40, 0xffff, "sev%c"},
4454
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xff0f, "nop%c\t{%4-7d}"},
4455
4456
  /* ARM V6T2 instructions.  */
4457
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4458
    0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"},
4459
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4460
    0xb100, 0xfd00, "cbz\t%0-2r, %b%X"},
4461
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xbf00, 0xff00, "it%I%X"},
4462
4463
  /* ARM V6.  */
4464
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb660, 0xfff8, "cpsie\t%{B:%2'a%1'i%0'f%}%X"},
4465
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb670, 0xfff8, "cpsid\t%{B:%2'a%1'i%0'f%}%X"},
4466
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"},
4467
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"},
4468
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"},
4469
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"},
4470
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb650, 0xfff7, "setend\t%{B:%3?ble%}%X"},
4471
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"},
4472
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"},
4473
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"},
4474
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"},
4475
4476
  /* ARM V5 ISA extends Thumb.  */
4477
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
4478
    0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional.  */
4479
  /* This is BLX(2).  BLX(1) is a 32-bit instruction.  */
4480
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
4481
    0x4780, 0xff87, "blx%c\t%3-6r%x"},  /* note: 4 bit register number.  */
4482
  /* ARM V4T ISA (Thumb v1).  */
4483
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4484
    0x46C0, 0xFFFF, "nop%c\t\t\t@ (mov r8, r8)"},
4485
  /* Format 4.  */
4486
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
4487
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
4488
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"},
4489
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"},
4490
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"},
4491
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"},
4492
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"},
4493
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"},
4494
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"},
4495
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"},
4496
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"},
4497
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"},
4498
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"},
4499
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"},
4500
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"},
4501
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"},
4502
  /* format 13 */
4503
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB000, 0xFF80, "add%c\t%{R:sp%}, %{I:#%0-6W%}"},
4504
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB080, 0xFF80, "sub%c\t%{R:sp%}, %{I:#%0-6W%}"},
4505
  /* format 5 */
4506
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4700, 0xFF80, "bx%c\t%S%x"},
4507
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4400, 0xFF00, "add%c\t%D, %S"},
4508
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4500, 0xFF00, "cmp%c\t%D, %S"},
4509
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4600, 0xFF00, "mov%c\t%D, %S"},
4510
  /* format 14 */
4511
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB400, 0xFE00, "push%c\t%N"},
4512
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xBC00, 0xFE00, "pop%c\t%O"},
4513
  /* format 2 */
4514
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4515
    0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"},
4516
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4517
    0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"},
4518
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4519
    0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, %{I:#%6-8d%}"},
4520
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4521
    0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, %{I:#%6-8d%}"},
4522
  /* format 8 */
4523
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4524
    0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"},
4525
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4526
    0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"},
4527
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4528
    0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"},
4529
  /* format 7 */
4530
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4531
    0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
4532
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4533
    0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
4534
  /* format 1 */
4535
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"},
4536
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4537
    0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, %{I:#%6-10d%}"},
4538
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"},
4539
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"},
4540
  /* format 3 */
4541
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2000, 0xF800, "mov%C\t%8-10r, %{I:#%0-7d%}"},
4542
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2800, 0xF800, "cmp%c\t%8-10r, %{I:#%0-7d%}"},
4543
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3000, 0xF800, "add%C\t%8-10r, %{I:#%0-7d%}"},
4544
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3800, 0xF800, "sub%C\t%8-10r, %{I:#%0-7d%}"},
4545
  /* format 6 */
4546
  /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
4547
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4548
    0x4800, 0xF800,
4549
    "ldr%c\t%8-10r, [%{R:pc%}, %{I:#%0-7W%}]\t@ (%0-7a)"},
4550
  /* format 9 */
4551
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4552
    0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, %{I:#%6-10W%}]"},
4553
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4554
    0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, %{I:#%6-10W%}]"},
4555
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4556
    0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, %{I:#%6-10d%}]"},
4557
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4558
    0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, %{I:#%6-10d%}]"},
4559
  /* format 10 */
4560
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4561
    0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, %{I:#%6-10H%}]"},
4562
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4563
    0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, %{I:#%6-10H%}]"},
4564
  /* format 11 */
4565
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4566
    0x9000, 0xF800, "str%c\t%8-10r, [%{R:sp%}, %{I:#%0-7W%}]"},
4567
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4568
    0x9800, 0xF800, "ldr%c\t%8-10r, [%{R:sp%}, %{I:#%0-7W%}]"},
4569
  /* format 12 */
4570
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4571
    0xA000, 0xF800, "add%c\t%8-10r, %{R:pc%}, %{I:#%0-7W%}\t@ (adr %8-10r, %0-7a)"},
4572
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4573
    0xA800, 0xF800, "add%c\t%8-10r, %{R:sp%}, %{I:#%0-7W%}"},
4574
  /* format 15 */
4575
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
4576
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"},
4577
  /* format 17 */
4578
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDF00, 0xFF00, "svc%c\t%0-7d"},
4579
  /* format 16 */
4580
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFF00, "udf%c\t%{I:#%0-7d%}"},
4581
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION},
4582
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
4583
  /* format 18 */
4584
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xE000, 0xF800, "b%c.n\t%0-10B%x"},
4585
4586
  /* The E800 .. FFFF range is unconditionally redirected to the
4587
     32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
4588
     are processed via that table.  Thus, we can never encounter a
4589
     bare "second half of BL/BLX(1)" instruction here.  */
4590
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),  0x0000, 0x0000, UNDEFINED_INSTRUCTION},
4591
  {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
4592
};
4593
4594
/* Thumb32 opcodes use the same table structure as the ARM opcodes.
4595
   We adopt the convention that hw1 is the high 16 bits of .value and
4596
   .mask, hw2 the low 16 bits.
4597
4598
   print_insn_thumb32 recognizes the following format control codes:
4599
4600
       %%   %
4601
4602
       %I   print a 12-bit immediate from hw1[10],hw2[14:12,7:0]
4603
       %M   print a modified 12-bit immediate (same location)
4604
       %J   print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0]
4605
       %K   print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4]
4606
       %H   print a 16-bit immediate from hw2[3:0],hw1[11:0]
4607
       %S   print a possibly-shifted Rm
4608
4609
       %L   print address for a ldrd/strd instruction
4610
       %a   print the address of a plain load/store
4611
       %w   print the width and signedness of a core load/store
4612
       %m   print register mask for ldm/stm
4613
       %n   print register mask for clrm
4614
4615
       %E   print the lsb and width fields of a bfc/bfi instruction
4616
       %F   print the lsb and width fields of a sbfx/ubfx instruction
4617
       %G   print a fallback offset for Branch Future instructions
4618
       %W   print an offset for BF instruction
4619
       %Y   print an offset for BFL instruction
4620
       %Z   print an offset for BFCSEL instruction
4621
       %Q   print an offset for Low Overhead Loop instructions
4622
       %P   print an offset for Low Overhead Loop end instructions
4623
       %b   print a conditional branch offset
4624
       %B   print an unconditional branch offset
4625
       %s   print the shift field of an SSAT instruction
4626
       %R   print the rotation field of an SXT instruction
4627
       %U   print barrier type.
4628
       %P   print address for pli instruction.
4629
       %c   print the condition code
4630
       %x   print warning if conditional an not at end of IT block"
4631
       %X   print "\t@ unpredictable <IT:code>" if conditional
4632
4633
       %<bitfield>d print bitfield in decimal
4634
       %<bitfield>D     print bitfield plus one in decimal
4635
       %<bitfield>W print bitfield*4 in decimal
4636
       %<bitfield>r print bitfield as an ARM register
4637
       %<bitfield>R as %<>r but r15 is UNPREDICTABLE
4638
       %<bitfield>S as %<>r but r13 and r15 is UNPREDICTABLE
4639
       %<bitfield>c print bitfield as a condition code
4640
4641
       %<bitfield>'c  print specified char iff bitfield is all ones
4642
       %<bitfield>`c  print specified char iff bitfield is all zeroes
4643
       %<bitfield>?ab... select from array of values in big endian order
4644
4645
   With one exception at the bottom (done because BL and BLX(1) need
4646
   to come dead last), this table was machine-sorted first in
4647
   decreasing order of number of bits set in the mask, then in
4648
   increasing numeric order of mask, then in increasing numeric order
4649
   of opcode.  This order is not the clearest for a human reader, but
4650
   is guaranteed never to catch a special-case bit pattern with a more
4651
   general mask, which is important, because this instruction encoding
4652
   makes heavy use of special-case bit patterns.  */
4653
static const struct opcode32 thumb32_opcodes[] =
4654
{
4655
  /* Arm v8.1-M Mainline Pointer Authentication and Branch Target
4656
     Identification Extension.  */
4657
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4658
   0xf3af802d, 0xffffffff, "aut\t%{R:r12%}, %{R:lr%}, %{R:sp%}"},
4659
  {ARM_FEATURE_CORE_HIGH_HIGH (ARM_EXT3_PACBTI),
4660
   0xfb500f00, 0xfff00ff0, "autg%c\t%12-15r, %16-19r, %0-3r"},
4661
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4662
   0xf3af800f, 0xffffffff, "bti"},
4663
  {ARM_FEATURE_CORE_HIGH_HIGH (ARM_EXT3_PACBTI),
4664
   0xfb500f10, 0xfff00ff0, "bxaut%c\t%12-15r, %16-19r, %0-3r"},
4665
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4666
   0xf3af801d, 0xffffffff, "pac\t%{R:r12%}, %{R:lr%}, %{R:sp%}"},
4667
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4668
   0xf3af800d, 0xffffffff, "pacbti\t%{R:r12%}, %{R:lr%}, %{R:sp%}"},
4669
  {ARM_FEATURE_CORE_HIGH_HIGH (ARM_EXT3_PACBTI),
4670
   0xfb60f000, 0xfff0f0f0, "pacg%c\t%8-11r, %16-19r, %0-3r"},
4671
4672
  /* Armv8.1-M Mainline and Armv8.1-M Mainline Security Extensions
4673
     instructions.  */
4674
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4675
    0xf00fe001, 0xffffffff, "lctp%c"},
4676
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4677
    0xf02fc001, 0xfffff001, "le\t%P"},
4678
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4679
    0xf00fc001, 0xfffff001, "le\t%{R:lr%}, %P"},
4680
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4681
    0xf01fc001, 0xfffff001, "letp\t%{R:lr%}, %P"},
4682
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4683
    0xf040c001, 0xfff0f001, "wls\t%{R:lr%}, %16-19S, %Q"},
4684
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4685
    0xf000c001, 0xffc0f001, "wlstp.%20-21s\t%{R:lr%}, %16-19S, %Q"},
4686
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4687
    0xf040e001, 0xfff0ffff, "dls\t%{R:lr%}, %16-19S"},
4688
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4689
    0xf000e001, 0xffc0ffff, "dlstp.%20-21s\t%{R:lr%}, %16-19S"},
4690
4691
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4692
    0xf040e001, 0xf860f001, "bf%c\t%G, %W"},
4693
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4694
    0xf060e001, 0xf8f0f001, "bfx%c\t%G, %16-19S"},
4695
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4696
    0xf000c001, 0xf800f001, "bfl%c\t%G, %Y"},
4697
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4698
    0xf070e001, 0xf8f0f001, "bflx%c\t%G, %16-19S"},
4699
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4700
    0xf000e001, 0xf840f001, "bfcsel\t%G, %Z, %{B:%18-21c%}"},
4701
4702
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4703
    0xe89f0000, 0xffff2000, "clrm%c\t%n"},
4704
4705
  /* ARMv8-M and ARMv8-M Security Extensions instructions.  */
4706
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0xe97fe97f, 0xffffffff, "sg"},
4707
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4708
    0xe840f000, 0xfff0f0ff, "tt\t%8-11r, %16-19r"},
4709
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4710
    0xe840f040, 0xfff0f0ff, "ttt\t%8-11r, %16-19r"},
4711
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4712
    0xe840f080, 0xfff0f0ff, "tta\t%8-11r, %16-19r"},
4713
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4714
    0xe840f0c0, 0xfff0f0ff, "ttat\t%8-11r, %16-19r"},
4715
4716
  /* ARM V8.2 RAS extension instructions.  */
4717
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
4718
    0xf3af8010, 0xffffffff, "esb"},
4719
4720
  /* V8 instructions.  */
4721
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4722
    0xf3af8005, 0xffffffff, "sevl%c.w"},
4723
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4724
    0xf78f8000, 0xfffffffc, "dcps%0-1d"},
4725
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4726
    0xe8c00f8f, 0xfff00fff, "stlb%c\t%12-15r, [%16-19R]"},
4727
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4728
    0xe8c00f9f, 0xfff00fff, "stlh%c\t%12-15r, [%16-19R]"},
4729
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4730
    0xe8c00faf, 0xfff00fff, "stl%c\t%12-15r, [%16-19R]"},
4731
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4732
    0xe8c00fc0, 0xfff00ff0, "stlexb%c\t%0-3r, %12-15r, [%16-19R]"},
4733
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4734
    0xe8c00fd0, 0xfff00ff0, "stlexh%c\t%0-3r, %12-15r, [%16-19R]"},
4735
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4736
    0xe8c00fe0, 0xfff00ff0, "stlex%c\t%0-3r, %12-15r, [%16-19R]"},
4737
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4738
    0xe8c000f0, 0xfff000f0, "stlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"},
4739
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4740
    0xe8d00f8f, 0xfff00fff, "ldab%c\t%12-15r, [%16-19R]"},
4741
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4742
    0xe8d00f9f, 0xfff00fff, "ldah%c\t%12-15r, [%16-19R]"},
4743
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4744
    0xe8d00faf, 0xfff00fff, "lda%c\t%12-15r, [%16-19R]"},
4745
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4746
    0xe8d00fcf, 0xfff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
4747
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4748
    0xe8d00fdf, 0xfff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
4749
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4750
    0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
4751
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4752
    0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"},
4753
4754
  /* V8-R instructions.  */
4755
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8R),
4756
    0xf3bf8f4c, 0xffffffff, "dfb%c"},
4757
4758
  /* CRC32 instructions.  */
4759
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
4760
    0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11R, %16-19R, %0-3R"},
4761
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
4762
    0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11R, %16-19R, %0-3R"},
4763
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
4764
    0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11R, %16-19R, %0-3R"},
4765
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
4766
    0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11R, %16-19R, %0-3R"},
4767
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
4768
    0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11R, %16-19R, %0-3R"},
4769
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
4770
    0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11R, %16-19R, %0-3R"},
4771
4772
  /* Speculation Barriers.  */
4773
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8014, 0xffffffff, "csdb"},
4774
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f40, 0xffffffff, "ssbb"},
4775
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f44, 0xffffffff, "pssbb"},
4776
4777
  /* V7 instructions.  */
4778
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf910f000, 0xff70f000, "pli%c\t%a"},
4779
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3af80f0, 0xfffffff0, "dbg%c\t%{I:#%0-3d%}"},
4780
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"},
4781
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"},
4782
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"},
4783
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"},
4784
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"},
4785
  {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
4786
    0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"},
4787
  {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
4788
    0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"},
4789
4790
  /* Virtualization Extension instructions.  */
4791
  {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0xf7e08000, 0xfff0f000, "hvc%c\t%V"},
4792
  /* We skip ERET as that is SUBS pc, lr, #0.  */
4793
4794
  /* MP Extension instructions.  */
4795
  {ARM_FEATURE_CORE_LOW (ARM_EXT_MP),   0xf830f000, 0xff70f000, "pldw%c\t%a"},
4796
4797
  /* Security extension instructions.  */
4798
  {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),  0xf7f08000, 0xfff0f000, "smc%c\t%K"},
4799
4800
  /* ARMv8.5-A instructions.  */
4801
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf3bf8f70, 0xffffffff, "sb"},
4802
4803
  /* Instructions defined in the basic V6T2 set.  */
4804
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8000, 0xffffffff, "nop%c.w"},
4805
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8001, 0xffffffff, "yield%c.w"},
4806
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8002, 0xffffffff, "wfe%c.w"},
4807
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8003, 0xffffffff, "wfi%c.w"},
4808
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8004, 0xffffffff, "sev%c.w"},
4809
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4810
    0xf3af8000, 0xffffff00, "nop%c.w\t{%{I:%0-7d%}}"},
4811
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf7f0a000, 0xfff0f000, "udf%c.w\t%H"},
4812
4813
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4814
    0xf3bf8f2f, 0xffffffff, "clrex%c"},
4815
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4816
    0xf3af8400, 0xffffff1f, "cpsie.w\t%{B:%7'a%6'i%5'f%}%X"},
4817
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4818
    0xf3af8600, 0xffffff1f, "cpsid.w\t%{B:%7'a%6'i%5'f%}%X"},
4819
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4820
    0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"},
4821
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4822
    0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"},
4823
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4824
    0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"},
4825
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4826
    0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"},
4827
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4828
    0xf3af8100, 0xffffffe0, "cps\t%{I:#%0-4d%}%X"},
4829
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4830
    0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"},
4831
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4832
    0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, %{B:lsl%} %{I:#1%}]%x"},
4833
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4834
    0xf3af8500, 0xffffff00, "cpsie\t%{B:%7'a%6'i%5'f%}, %{I:#%0-4d%}%X"},
4835
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4836
    0xf3af8700, 0xffffff00, "cpsid\t%{B:%7'a%6'i%5'f%}, %{I:#%0-4d%}%X"},
4837
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4838
    0xf3de8f00, 0xffffff00, "subs%c\t%{R:pc%}, %{R:lr%}, %{I:#%0-7d%}"},
4839
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4840
    0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"},
4841
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4842
    0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"},
4843
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4844
    0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"},
4845
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4846
    0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, %{I:#%0-4d%}"},
4847
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4848
    0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, %{I:#%0-4d%}"},
4849
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4850
    0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"},
4851
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4852
    0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"},
4853
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4854
    0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"},
4855
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4856
    0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"},
4857
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4858
    0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"},
4859
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4860
    0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"},
4861
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4862
    0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"},
4863
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4864
    0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"},
4865
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4866
    0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"},
4867
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4868
    0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"},
4869
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4870
    0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"},
4871
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4872
    0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"},
4873
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4874
    0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"},
4875
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4876
    0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"},
4877
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4878
    0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"},
4879
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4880
    0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"},
4881
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4882
    0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"},
4883
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4884
    0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"},
4885
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4886
    0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"},
4887
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4888
    0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"},
4889
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4890
    0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"},
4891
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4892
    0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"},
4893
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4894
    0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"},
4895
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4896
    0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"},
4897
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4898
    0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"},
4899
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4900
    0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"},
4901
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4902
    0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"},
4903
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4904
    0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"},
4905
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4906
    0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"},
4907
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4908
    0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"},
4909
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4910
    0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"},
4911
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4912
    0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"},
4913
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4914
    0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"},
4915
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4916
    0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"},
4917
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4918
    0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"},
4919
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4920
    0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"},
4921
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4922
    0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"},
4923
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4924
    0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"},
4925
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4926
    0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"},
4927
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4928
    0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"},
4929
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4930
    0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"},
4931
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4932
    0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"},
4933
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4934
    0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"},
4935
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4936
    0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"},
4937
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4938
    0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"},
4939
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4940
    0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"},
4941
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4942
    0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"},
4943
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4944
    0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"},
4945
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4946
    0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"},
4947
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4948
    0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"},
4949
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4950
    0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"},
4951
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4952
    0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"},
4953
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4954
    0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"},
4955
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4956
    0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"},
4957
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4958
    0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"},
4959
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4960
    0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"},
4961
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4962
    0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4963
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4964
    0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4965
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4966
    0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4967
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4968
    0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"},
4969
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4970
    0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"},
4971
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4972
    0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, %{I:#%0-4D%}, %16-19r"},
4973
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4974
    0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, %{I:#%0-4d%}, %16-19r"},
4975
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4976
    0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"},
4977
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4978
    0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"},
4979
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4980
    0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"},
4981
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4982
    0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"},
4983
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4984
    0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"},
4985
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4986
    0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"},
4987
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4988
    0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
4989
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4990
    0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
4991
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4992
    0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"},
4993
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4994
    0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"},
4995
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4996
    0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"},
4997
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4998
    0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"},
4999
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5000
    0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"},
5001
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5002
    0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"},
5003
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5004
    0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"},
5005
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5006
    0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"},
5007
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5008
    0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"},
5009
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5010
    0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"},
5011
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5012
    0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"},
5013
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5014
    0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"},
5015
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5016
    0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"},
5017
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5018
    0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"},
5019
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5020
    0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"},
5021
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5022
    0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
5023
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5024
    0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
5025
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5026
    0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
5027
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5028
    0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
5029
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5030
    0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
5031
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5032
    0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
5033
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5034
    0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
5035
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5036
    0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
5037
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
5038
    0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, %{I:#%0-7W%}]"},
5039
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5040
    0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"},
5041
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5042
    0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"},
5043
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5044
    0xf810f000, 0xff70f000, "pld%c\t%a"},
5045
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5046
    0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
5047
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5048
    0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
5049
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5050
    0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
5051
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5052
    0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
5053
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5054
    0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
5055
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5056
    0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
5057
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5058
    0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
5059
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5060
    0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"},
5061
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5062
    0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"},
5063
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5064
    0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"},
5065
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5066
    0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"},
5067
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5068
    0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"},
5069
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5070
    0xfb100000, 0xfff000c0,
5071
    "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
5072
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5073
    0xfbc00080, 0xfff000c0,
5074
    "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
5075
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5076
    0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"},
5077
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5078
    0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"},
5079
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5080
    0xf3000000, 0xffd08020, "ssat%c\t%8-11r, %{I:#%0-4D%}, %16-19r%s"},
5081
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5082
    0xf3800000, 0xffd08020, "usat%c\t%8-11r, %{I:#%0-4d%}, %16-19r%s"},
5083
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5084
    0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"},
5085
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
5086
    0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"},
5087
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5088
    0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"},
5089
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
5090
    0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"},
5091
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5092
    0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"},
5093
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5094
    0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"},
5095
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5096
    0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"},
5097
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5098
    0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"},
5099
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5100
    0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"},
5101
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5102
    0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"},
5103
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5104
    0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"},
5105
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5106
    0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"},
5107
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5108
    0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"},
5109
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5110
    0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"},
5111
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
5112
    0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, %{I:#%0-7W%}]"},
5113
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5114
    0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"},
5115
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5116
    0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"},
5117
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5118
    0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"},
5119
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5120
    0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"},
5121
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5122
    0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"},
5123
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5124
    0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"},
5125
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5126
    0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"},
5127
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5128
    0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"},
5129
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5130
    0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"},
5131
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5132
    0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"},
5133
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5134
    0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"},
5135
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5136
    0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"},
5137
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5138
    0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"},
5139
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5140
    0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"},
5141
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5142
    0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"},
5143
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5144
    0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"},
5145
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5146
    0xe9400000, 0xff500000,
5147
    "strd%c\t%12-15r, %8-11r, [%16-19r, %{I:#%23`-%0-7W%}]%21'!%L"},
5148
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5149
    0xe9500000, 0xff500000,
5150
    "ldrd%c\t%12-15r, %8-11r, [%16-19r, %{I:#%23`-%0-7W%}]%21'!%L"},
5151
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5152
    0xe8600000, 0xff700000,
5153
    "strd%c\t%12-15r, %8-11r, [%16-19r], %{I:#%23`-%0-7W%}%L"},
5154
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5155
    0xe8700000, 0xff700000,
5156
    "ldrd%c\t%12-15r, %8-11r, [%16-19r], %{I:#%23`-%0-7W%}%L"},
5157
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5158
    0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"},
5159
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5160
    0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"},
5161
5162
  /* Filter out Bcc with cond=E or F, which are used for other instructions.  */
5163
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5164
    0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"},
5165
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5166
    0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"},
5167
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5168
    0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"},
5169
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5170
    0xf0009000, 0xf800d000, "b%c.w\t%B%x"},
5171
5172
  /* These have been 32-bit since the invention of Thumb.  */
5173
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
5174
     0xf000c000, 0xf800d001, "blx%c\t%B%x"},
5175
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
5176
     0xf000d000, 0xf800d000, "bl%c\t%B%x"},
5177
5178
  /* Fallback.  */
5179
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
5180
      0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
5181
  {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
5182
};
5183
5184
static const char *const arm_conditional[] =
5185
{"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
5186
 "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""};
5187
5188
static const char *const arm_fp_const[] =
5189
{"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
5190
5191
static const char *const arm_shift[] =
5192
{"lsl", "lsr", "asr", "ror"};
5193
5194
typedef struct
5195
{
5196
  const char *name;
5197
  const char *description;
5198
  const char *reg_names[16];
5199
}
5200
arm_regname;
5201
5202
static const arm_regname regnames[] =
5203
{
5204
  { "reg-names-raw", N_("Select raw register names"),
5205
    { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
5206
  { "reg-names-gcc", N_("Select register names used by GCC"),
5207
    { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl",  "fp",  "ip",  "sp",  "lr",  "pc" }},
5208
  { "reg-names-std", N_("Select register names used in ARM's ISA documentation"),
5209
    { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp",  "lr",  "pc" }},
5210
  { "force-thumb", N_("Assume all insns are Thumb insns"), {NULL} },
5211
  { "no-force-thumb", N_("Examine preceding label to determine an insn's type"), {NULL} },
5212
  { "reg-names-apcs", N_("Select register names used in the APCS"),
5213
    { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl",  "fp",  "ip",  "sp",  "lr",  "pc" }},
5214
  { "reg-names-atpcs", N_("Select register names used in the ATPCS"),
5215
    { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7",  "v8",  "IP",  "SP",  "LR",  "PC" }},
5216
  { "reg-names-special-atpcs", N_("Select special register names used in the ATPCS"),
5217
    { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL",  "FP",  "IP",  "SP",  "LR",  "PC" }},
5218
  { "coproc<N>=(cde|generic)", N_("Enable CDE extensions for coprocessor N space"), { NULL } }
5219
};
5220
5221
static const char *const iwmmxt_wwnames[] =
5222
{"b", "h", "w", "d"};
5223
5224
static const char *const iwmmxt_wwssnames[] =
5225
{"b", "bus", "bc", "bss",
5226
 "h", "hus", "hc", "hss",
5227
 "w", "wus", "wc", "wss",
5228
 "d", "dus", "dc", "dss"
5229
};
5230
5231
static const char *const iwmmxt_regnames[] =
5232
{ "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7",
5233
  "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"
5234
};
5235
5236
static const char *const iwmmxt_cregnames[] =
5237
{ "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved",
5238
  "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"
5239
};
5240
5241
static const char *const vec_condnames[] =
5242
{ "eq", "ne", "cs", "hi", "ge", "lt", "gt", "le"
5243
};
5244
5245
static const char *const mve_predicatenames[] =
5246
{ "", "ttt", "tt", "tte", "t", "tee", "te", "tet", "",
5247
  "eee", "ee", "eet", "e", "ett", "et", "ete"
5248
};
5249
5250
/* Names for 2-bit size field for mve vector isntructions.  */
5251
static const char *const mve_vec_sizename[] =
5252
  { "8", "16", "32", "64"};
5253
5254
/* Indicates whether we are processing a then predicate,
5255
   else predicate or none at all.  */
5256
enum vpt_pred_state
5257
{
5258
  PRED_NONE,
5259
  PRED_THEN,
5260
  PRED_ELSE
5261
};
5262
5263
/* Information used to process a vpt block and subsequent instructions.  */
5264
struct vpt_block
5265
{
5266
  /* Are we in a vpt block.  */
5267
  bool in_vpt_block;
5268
5269
  /* Next predicate state if in vpt block.  */
5270
  enum vpt_pred_state next_pred_state;
5271
5272
  /* Mask from vpt/vpst instruction.  */
5273
  long predicate_mask;
5274
5275
  /* Instruction number in vpt block.  */
5276
  long current_insn_num;
5277
5278
  /* Number of instructions in vpt block..   */
5279
  long num_pred_insn;
5280
};
5281
5282
static struct vpt_block vpt_block_state =
5283
{
5284
  false,
5285
  PRED_NONE,
5286
  0,
5287
  0,
5288
  0
5289
};
5290
5291
/* Default to GCC register name set.  */
5292
static unsigned int regname_selected = 1;
5293
5294
2.84k
#define NUM_ARM_OPTIONS   ARRAY_SIZE (regnames)
5295
11.0M
#define arm_regnames      regnames[regname_selected].reg_names
5296
5297
static bool force_thumb = false;
5298
static uint16_t cde_coprocs = 0;
5299
5300
/* Current IT instruction state.  This contains the same state as the IT
5301
   bits in the CPSR.  */
5302
static unsigned int ifthen_state;
5303
/* IT state for the next instruction.  */
5304
static unsigned int ifthen_next_state;
5305
/* The address of the insn for which the IT state is valid.  */
5306
static bfd_vma ifthen_address;
5307
6.07M
#define IFTHEN_COND ((ifthen_state >> 4) & 0xf)
5308
/* Indicates that the current Conditional state is unconditional or outside
5309
   an IT block.  */
5310
520M
#define COND_UNCOND 16
5311
5312

5313
/* Functions.  */
5314
/* Extract the predicate mask for a VPT or VPST instruction.
5315
   The mask is composed of bits 13-15 (Mkl) and bit 22 (Mkh).  */
5316
5317
static long
5318
mve_extract_pred_mask (long given)
5319
16.9k
{
5320
16.9k
  return ((given & 0x00400000) >> 19) | ((given & 0xe000) >> 13);
5321
16.9k
}
5322
5323
/* Return the number of instructions in a MVE predicate block.  */
5324
static long
5325
num_instructions_vpt_block (long given)
5326
3.47k
{
5327
3.47k
  long mask = mve_extract_pred_mask (given);
5328
3.47k
  if (mask == 0)
5329
0
    return 0;
5330
5331
3.47k
  if (mask == 8)
5332
606
    return 1;
5333
5334
2.86k
  if ((mask & 7) == 4)
5335
1.14k
    return 2;
5336
5337
1.72k
  if ((mask & 3) == 2)
5338
524
    return 3;
5339
5340
1.20k
  if ((mask & 1) == 1)
5341
1.20k
    return 4;
5342
5343
0
  return 0;
5344
1.20k
}
5345
5346
static void
5347
mark_outside_vpt_block (void)
5348
3.47k
{
5349
3.47k
  vpt_block_state.in_vpt_block = false;
5350
3.47k
  vpt_block_state.next_pred_state = PRED_NONE;
5351
3.47k
  vpt_block_state.predicate_mask = 0;
5352
3.47k
  vpt_block_state.current_insn_num = 0;
5353
3.47k
  vpt_block_state.num_pred_insn = 0;
5354
3.47k
}
5355
5356
static void
5357
mark_inside_vpt_block (long given)
5358
3.47k
{
5359
3.47k
  vpt_block_state.in_vpt_block = true;
5360
3.47k
  vpt_block_state.next_pred_state = PRED_THEN;
5361
3.47k
  vpt_block_state.predicate_mask = mve_extract_pred_mask (given);
5362
3.47k
  vpt_block_state.current_insn_num = 0;
5363
3.47k
  vpt_block_state.num_pred_insn = num_instructions_vpt_block (given);
5364
3.47k
  assert (vpt_block_state.num_pred_insn >= 1);
5365
3.47k
}
5366
5367
static enum vpt_pred_state
5368
invert_next_predicate_state (enum vpt_pred_state astate)
5369
3.13k
{
5370
3.13k
  if (astate == PRED_THEN)
5371
2.01k
    return PRED_ELSE;
5372
1.11k
  else if (astate == PRED_ELSE)
5373
1.11k
    return PRED_THEN;
5374
0
  else
5375
0
    return PRED_NONE;
5376
3.13k
}
5377
5378
static enum vpt_pred_state
5379
update_next_predicate_state (void)
5380
5.79k
{
5381
5.79k
  long pred_mask = vpt_block_state.predicate_mask;
5382
5.79k
  long mask_for_insn = 0;
5383
5384
5.79k
  switch (vpt_block_state.current_insn_num)
5385
5.79k
    {
5386
2.86k
    case 1:
5387
2.86k
      mask_for_insn = 8;
5388
2.86k
      break;
5389
5390
1.72k
    case 2:
5391
1.72k
      mask_for_insn = 4;
5392
1.72k
      break;
5393
5394
1.20k
    case 3:
5395
1.20k
      mask_for_insn = 2;
5396
1.20k
      break;
5397
5398
0
    case 4:
5399
0
      return PRED_NONE;
5400
5.79k
    }
5401
5402
5.79k
  if (pred_mask & mask_for_insn)
5403
3.13k
    return invert_next_predicate_state (vpt_block_state.next_pred_state);
5404
2.66k
  else
5405
2.66k
    return vpt_block_state.next_pred_state;
5406
5.79k
}
5407
5408
static void
5409
update_vpt_block_state (void)
5410
9.26k
{
5411
9.26k
  vpt_block_state.current_insn_num++;
5412
9.26k
  if (vpt_block_state.current_insn_num == vpt_block_state.num_pred_insn)
5413
3.47k
    {
5414
      /* No more instructions to process in vpt block.  */
5415
3.47k
      mark_outside_vpt_block ();
5416
3.47k
      return;
5417
3.47k
    }
5418
5419
5.79k
  vpt_block_state.next_pred_state = update_next_predicate_state ();
5420
5.79k
}
5421
5422
/* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?.
5423
   Returns pointer to following character of the format string and
5424
   fills in *VALUEP and *WIDTHP with the extracted value and number of
5425
   bits extracted.  WIDTHP can be NULL.  */
5426
5427
static const char *
5428
arm_decode_bitfield (const char *ptr,
5429
         unsigned long insn,
5430
         unsigned long *valuep,
5431
         int *widthp)
5432
10.1M
{
5433
10.1M
  unsigned long value = 0;
5434
10.1M
  int width = 0;
5435
5436
10.1M
  do
5437
10.4M
    {
5438
10.4M
      int start, end;
5439
10.4M
      int bits;
5440
5441
29.2M
      for (start = 0; *ptr >= '0' && *ptr <= '9'; ptr++)
5442
18.7M
  start = start * 10 + *ptr - '0';
5443
10.4M
      if (*ptr == '-')
5444
19.9M
  for (end = 0, ptr++; *ptr >= '0' && *ptr <= '9'; ptr++)
5445
13.0M
    end = end * 10 + *ptr - '0';
5446
3.64M
      else
5447
3.64M
  end = start;
5448
10.4M
      bits = end - start;
5449
10.4M
      if (bits < 0)
5450
0
  abort ();
5451
10.4M
      value |= ((insn >> start) & ((2ul << bits) - 1)) << width;
5452
10.4M
      width += bits + 1;
5453
10.4M
    }
5454
10.4M
  while (*ptr++ == ',');
5455
10.1M
  *valuep = value;
5456
10.1M
  if (widthp)
5457
10.1M
    *widthp = width;
5458
10.1M
  return ptr - 1;
5459
10.1M
}
5460
5461
static void
5462
arm_decode_shift (long given, fprintf_styled_ftype func, void *stream,
5463
      bool print_shift)
5464
1.20M
{
5465
1.20M
  func (stream, dis_style_register, "%s", arm_regnames[given & 0xf]);
5466
5467
1.20M
  if ((given & 0xff0) != 0)
5468
795k
    {
5469
795k
      if ((given & 0x10) == 0)
5470
625k
  {
5471
625k
    int amount = (given & 0xf80) >> 7;
5472
625k
    int shift = (given & 0x60) >> 5;
5473
5474
625k
    if (amount == 0)
5475
49.2k
      {
5476
49.2k
        if (shift == 3)
5477
11.1k
    {
5478
11.1k
      func (stream, dis_style_text, ", ");
5479
11.1k
      func (stream, dis_style_sub_mnemonic, "rrx");
5480
11.1k
      return;
5481
11.1k
    }
5482
5483
38.1k
        amount = 32;
5484
38.1k
      }
5485
5486
614k
    if (print_shift)
5487
612k
      {
5488
612k
        func (stream, dis_style_text, ", ");
5489
612k
        func (stream, dis_style_sub_mnemonic, "%s ", arm_shift[shift]);
5490
612k
        func (stream, dis_style_immediate, "#%d", amount);
5491
612k
      }
5492
2.26k
    else
5493
2.26k
      {
5494
2.26k
        func (stream, dis_style_text, ", ");
5495
2.26k
        func (stream, dis_style_immediate, "#%d", amount);
5496
2.26k
      }
5497
614k
  }
5498
169k
      else if ((given & 0x80) == 0x80)
5499
2.54k
  func (stream, dis_style_comment_start,
5500
2.54k
        "\t@ <illegal shifter operand>");
5501
167k
      else if (print_shift)
5502
166k
  {
5503
166k
    func (stream, dis_style_text, ", ");
5504
166k
    func (stream, dis_style_sub_mnemonic, "%s ",
5505
166k
    arm_shift[(given & 0x60) >> 5]);
5506
166k
    func (stream, dis_style_register, "%s",
5507
166k
    arm_regnames[(given & 0xf00) >> 8]);
5508
166k
  }
5509
685
      else
5510
685
  {
5511
685
    func (stream, dis_style_text, ", ");
5512
685
    func (stream, dis_style_register, "%s",
5513
685
    arm_regnames[(given & 0xf00) >> 8]);
5514
685
  }
5515
795k
    }
5516
1.20M
}
5517
5518
/* Return TRUE if the MATCHED_INSN can be inside an IT block.  */
5519
5520
static bool
5521
is_mve_okay_in_it (enum mve_instructions matched_insn)
5522
7.32k
{
5523
7.32k
  switch (matched_insn)
5524
7.32k
    {
5525
209
    case MVE_VMOV_GP_TO_VEC_LANE:
5526
520
    case MVE_VMOV2_VEC_LANE_TO_GP:
5527
715
    case MVE_VMOV2_GP_TO_VEC_LANE:
5528
1.12k
    case MVE_VMOV_VEC_LANE_TO_GP:
5529
1.46k
    case MVE_LSLL:
5530
1.71k
    case MVE_LSLLI:
5531
2.06k
    case MVE_LSRL:
5532
2.38k
    case MVE_ASRL:
5533
2.66k
    case MVE_ASRLI:
5534
2.93k
    case MVE_SQRSHRL:
5535
3.30k
    case MVE_SQRSHR:
5536
3.49k
    case MVE_UQRSHL:
5537
3.74k
    case MVE_UQRSHLL:
5538
3.98k
    case MVE_UQSHL:
5539
4.18k
    case MVE_UQSHLL:
5540
4.42k
    case MVE_URSHRL:
5541
4.77k
    case MVE_URSHR:
5542
4.99k
    case MVE_SRSHRL:
5543
5.18k
    case MVE_SRSHR:
5544
5.44k
    case MVE_SQSHLL:
5545
5.65k
    case MVE_SQSHL:
5546
5.65k
      return true;
5547
1.67k
    default:
5548
1.67k
      return false;
5549
7.32k
    }
5550
7.32k
}
5551
5552
static bool
5553
is_mve_architecture (struct disassemble_info *info)
5554
436k
{
5555
436k
  struct arm_private_data *private_data = info->private_data;
5556
436k
  arm_feature_set allowed_arches = private_data->features;
5557
5558
436k
  arm_feature_set arm_ext_v8_1m_main
5559
436k
    = ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN);
5560
5561
436k
  if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
5562
436k
      && !ARM_CPU_IS_ANY (allowed_arches))
5563
334k
    return true;
5564
101k
  else
5565
101k
    return false;
5566
436k
}
5567
5568
static bool
5569
is_vpt_instruction (long given)
5570
99.9k
{
5571
5572
  /* If mkh:mkl is '0000' then its not a vpt/vpst instruction.  */
5573
99.9k
  if ((given & 0x0040e000) == 0)
5574
8.45k
    return false;
5575
5576
  /* VPT floating point T1 variant.  */
5577
91.4k
  if (((given & 0xefb10f50) == 0xee310f00 && ((given & 0x1001) != 0x1))
5578
  /* VPT floating point T2 variant.  */
5579
91.4k
      || ((given & 0xefb10f50) == 0xee310f40)
5580
  /* VPT vector T1 variant.  */
5581
91.4k
      || ((given & 0xff811f51) == 0xfe010f00)
5582
  /* VPT vector T2 variant.  */
5583
91.4k
      || ((given & 0xff811f51) == 0xfe010f01
5584
90.3k
    && ((given & 0x300000) != 0x300000))
5585
  /* VPT vector T3 variant.  */
5586
91.4k
      || ((given & 0xff811f50) == 0xfe011f00)
5587
  /* VPT vector T4 variant.  */
5588
91.4k
      || ((given & 0xff811f70) == 0xfe010f40)
5589
  /* VPT vector T5 variant.  */
5590
91.4k
      || ((given & 0xff811f70) == 0xfe010f60)
5591
  /* VPT vector T6 variant.  */
5592
91.4k
      || ((given & 0xff811f50) == 0xfe011f40)
5593
  /* VPST vector T variant.  */
5594
91.4k
      || ((given & 0xffbf1fff) == 0xfe310f4d))
5595
3.47k
    return true;
5596
87.9k
  else
5597
87.9k
    return false;
5598
91.4k
}
5599
5600
/* Decode a bitfield from opcode GIVEN, with starting bitfield = START
5601
   and ending bitfield = END.  END must be greater than START.  */
5602
5603
static unsigned long
5604
arm_decode_field (unsigned long given, unsigned int start, unsigned int end)
5605
457k
{
5606
457k
  int bits = end - start;
5607
5608
457k
  if (bits < 0)
5609
0
    abort ();
5610
5611
457k
  return ((given >> start) & ((2ul << bits) - 1));
5612
457k
}
5613
5614
/* Decode a bitfield from opcode GIVEN, with multiple bitfields:
5615
   START:END and START2:END2.  END/END2 must be greater than
5616
   START/START2.  */
5617
5618
static unsigned long
5619
arm_decode_field_multiple (unsigned long given, unsigned int start,
5620
         unsigned int end, unsigned int start2,
5621
         unsigned int end2)
5622
46.3k
{
5623
46.3k
  int bits = end - start;
5624
46.3k
  int bits2 = end2 - start2;
5625
46.3k
  unsigned long value = 0;
5626
46.3k
  int width = 0;
5627
5628
46.3k
  if (bits2 < 0)
5629
0
    abort ();
5630
5631
46.3k
  value = arm_decode_field (given, start, end);
5632
46.3k
  width += bits + 1;
5633
5634
46.3k
  value |= ((given >> start2) & ((2ul << bits2) - 1)) << width;
5635
46.3k
  return value;
5636
46.3k
}
5637
5638
/* Return TRUE if the GIVEN encoding should not be decoded as MATCHED_INSN.
5639
   This helps us decode instructions that change mnemonic depending on specific
5640
   operand values/encodings.  */
5641
5642
static bool
5643
is_mve_encoding_conflict (unsigned long given,
5644
        enum mve_instructions matched_insn)
5645
148k
{
5646
148k
  switch (matched_insn)
5647
148k
    {
5648
931
    case MVE_VPST:
5649
931
      if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
5650
196
  return true;
5651
735
      else
5652
735
  return false;
5653
5654
1.94k
    case MVE_VPT_FP_T1:
5655
1.94k
      if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
5656
859
  return true;
5657
1.08k
      if ((arm_decode_field (given, 12, 12) == 0)
5658
1.08k
    && (arm_decode_field (given, 0, 0) == 1))
5659
271
  return true;
5660
816
      return false;
5661
5662
1.22k
    case MVE_VPT_FP_T2:
5663
1.22k
      if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
5664
414
  return true;
5665
812
      if (arm_decode_field (given, 0, 3) == 0xd)
5666
201
  return true;
5667
611
      return false;
5668
5669
1.06k
    case MVE_VPT_VEC_T1:
5670
2.50k
    case MVE_VPT_VEC_T2:
5671
5.26k
    case MVE_VPT_VEC_T3:
5672
7.52k
    case MVE_VPT_VEC_T4:
5673
8.68k
    case MVE_VPT_VEC_T5:
5674
10.6k
    case MVE_VPT_VEC_T6:
5675
10.6k
      if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
5676
2.55k
  return true;
5677
8.10k
      if (arm_decode_field (given, 20, 21) == 3)
5678
273
  return true;
5679
7.83k
      return false;
5680
5681
859
    case MVE_VCMP_FP_T1:
5682
859
      if ((arm_decode_field (given, 12, 12) == 0)
5683
859
    && (arm_decode_field (given, 0, 0) == 1))
5684
454
  return true;
5685
405
      else
5686
405
  return false;
5687
5688
414
    case MVE_VCMP_FP_T2:
5689
414
      if (arm_decode_field (given, 0, 3) == 0xd)
5690
196
  return true;
5691
218
      else
5692
218
  return false;
5693
5694
819
    case MVE_VQADD_T2:
5695
1.99k
    case MVE_VQSUB_T2:
5696
2.40k
    case MVE_VMUL_VEC_T2:
5697
3.62k
    case MVE_VMULH:
5698
4.32k
    case MVE_VRMULH:
5699
4.62k
    case MVE_VMLA:
5700
4.92k
    case MVE_VMAX:
5701
5.17k
    case MVE_VMIN:
5702
7.46k
    case MVE_VBRSR:
5703
7.68k
    case MVE_VADD_VEC_T2:
5704
7.91k
    case MVE_VSUB_VEC_T2:
5705
8.11k
    case MVE_VABAV:
5706
8.34k
    case MVE_VQRSHL_T1:
5707
8.58k
    case MVE_VQSHL_T4:
5708
9.03k
    case MVE_VRSHL_T1:
5709
9.40k
    case MVE_VSHL_T3:
5710
10.1k
    case MVE_VCADD_VEC:
5711
10.6k
    case MVE_VHCADD:
5712
11.4k
    case MVE_VDDUP:
5713
11.8k
    case MVE_VIDUP:
5714
12.1k
    case MVE_VQRDMLADH:
5715
12.8k
    case MVE_VQDMLAH:
5716
13.0k
    case MVE_VQRDMLAH:
5717
13.3k
    case MVE_VQDMLASH:
5718
13.5k
    case MVE_VQRDMLASH:
5719
13.9k
    case MVE_VQDMLSDH:
5720
14.2k
    case MVE_VQRDMLSDH:
5721
14.7k
    case MVE_VQDMULH_T3:
5722
15.1k
    case MVE_VQRDMULH_T4:
5723
15.5k
    case MVE_VQDMLADH:
5724
15.9k
    case MVE_VMLAS:
5725
17.5k
    case MVE_VMULL_INT:
5726
17.8k
    case MVE_VHADD_T2:
5727
18.4k
    case MVE_VHSUB_T2:
5728
18.6k
    case MVE_VCMP_VEC_T1:
5729
19.0k
    case MVE_VCMP_VEC_T2:
5730
19.3k
    case MVE_VCMP_VEC_T3:
5731
20.0k
    case MVE_VCMP_VEC_T4:
5732
20.2k
    case MVE_VCMP_VEC_T5:
5733
20.5k
    case MVE_VCMP_VEC_T6:
5734
20.5k
      if (arm_decode_field (given, 20, 21) == 3)
5735
3.93k
  return true;
5736
16.6k
      else
5737
16.6k
  return false;
5738
5739
656
    case MVE_VLD2:
5740
1.30k
    case MVE_VLD4:
5741
2.11k
    case MVE_VST2:
5742
2.55k
    case MVE_VST4:
5743
2.55k
      if (arm_decode_field (given, 7, 8) == 3)
5744
315
  return true;
5745
2.23k
      else
5746
2.23k
  return false;
5747
5748
1.63k
    case MVE_VSTRB_T1:
5749
3.76k
    case MVE_VSTRH_T2:
5750
3.76k
      if ((arm_decode_field (given, 24, 24) == 0)
5751
3.76k
    && (arm_decode_field (given, 21, 21) == 0))
5752
436
  {
5753
436
      return true;
5754
436
  }
5755
3.32k
      else if ((arm_decode_field (given, 7, 8) == 3))
5756
953
  return true;
5757
2.37k
      else
5758
2.37k
  return false;
5759
5760
770
    case MVE_VLDRB_T1:
5761
2.89k
    case MVE_VLDRH_T2:
5762
3.42k
    case MVE_VLDRW_T7:
5763
4.03k
    case MVE_VSTRB_T5:
5764
4.57k
    case MVE_VSTRH_T6:
5765
5.14k
    case MVE_VSTRW_T7:
5766
5.14k
      if ((arm_decode_field (given, 24, 24) == 0)
5767
5.14k
    && (arm_decode_field (given, 21, 21) == 0))
5768
1.93k
  {
5769
1.93k
      return true;
5770
1.93k
  }
5771
3.21k
      else
5772
3.21k
  return false;
5773
5774
4.42k
    case MVE_VCVT_FP_FIX_VEC:
5775
4.42k
      return (arm_decode_field (given, 16, 21) & 0x38) == 0;
5776
5777
5.56k
    case MVE_VBIC_IMM:
5778
8.21k
    case MVE_VORR_IMM:
5779
8.21k
      {
5780
8.21k
  unsigned long cmode = arm_decode_field (given, 8, 11);
5781
5782
8.21k
  if ((cmode & 1) == 0)
5783
4.92k
    return true;
5784
3.28k
  else if ((cmode & 0xc) == 0xc)
5785
1.45k
    return true;
5786
1.83k
  else
5787
1.83k
    return false;
5788
8.21k
      }
5789
5790
2.83k
    case MVE_VMVN_IMM:
5791
2.83k
      {
5792
2.83k
  unsigned long cmode = arm_decode_field (given, 8, 11);
5793
5794
2.83k
  if (cmode == 0xe)
5795
0
    return true;
5796
2.83k
  else if ((cmode & 0x9) == 1)
5797
0
    return true;
5798
2.83k
  else if ((cmode & 0xd) == 9)
5799
0
    return true;
5800
2.83k
  else
5801
2.83k
    return false;
5802
2.83k
      }
5803
5804
6.36k
    case MVE_VMOV_IMM_TO_VEC:
5805
6.36k
      if ((arm_decode_field (given, 5, 5) == 1)
5806
6.36k
    && (arm_decode_field (given, 8, 11) != 0xe))
5807
3.41k
  return true;
5808
2.95k
      else
5809
2.95k
  return false;
5810
5811
400
    case MVE_VMOVL:
5812
400
      {
5813
400
  unsigned long size = arm_decode_field (given, 19, 20);
5814
400
  if ((size == 0) || (size == 3))
5815
0
    return true;
5816
400
  else
5817
400
    return false;
5818
400
      }
5819
5820
420
    case MVE_VMAXA:
5821
626
    case MVE_VMINA:
5822
833
    case MVE_VMAXV:
5823
1.27k
    case MVE_VMAXAV:
5824
1.47k
    case MVE_VMINV:
5825
1.68k
    case MVE_VMINAV:
5826
1.88k
    case MVE_VQRSHL_T2:
5827
2.08k
    case MVE_VQSHL_T1:
5828
2.27k
    case MVE_VRSHL_T2:
5829
2.48k
    case MVE_VSHL_T2:
5830
2.91k
    case MVE_VSHLL_T2:
5831
3.16k
    case MVE_VADDV:
5832
3.48k
    case MVE_VMOVN:
5833
3.77k
    case MVE_VQMOVUN:
5834
3.99k
    case MVE_VQMOVN:
5835
3.99k
      if (arm_decode_field (given, 18, 19) == 3)
5836
271
  return true;
5837
3.72k
      else
5838
3.72k
  return false;
5839
5840
979
    case MVE_VMLSLDAV:
5841
1.39k
    case MVE_VRMLSLDAVH:
5842
3.02k
    case MVE_VMLALDAV:
5843
3.46k
    case MVE_VADDLV:
5844
3.46k
      if (arm_decode_field (given, 20, 22) == 7)
5845
1.02k
  return true;
5846
2.44k
      else
5847
2.44k
  return false;
5848
5849
604
    case MVE_VRMLALDAVH:
5850
604
      if ((arm_decode_field (given, 20, 22) & 6) == 6)
5851
214
  return true;
5852
390
      else
5853
390
  return false;
5854
5855
746
    case MVE_VDWDUP:
5856
1.66k
    case MVE_VIWDUP:
5857
1.66k
      if ((arm_decode_field (given, 20, 21) == 3)
5858
1.66k
    || (arm_decode_field (given, 1, 3) == 7))
5859
549
  return true;
5860
1.11k
      else
5861
1.11k
  return false;
5862
5863
5864
1.54k
    case MVE_VSHLL_T1:
5865
1.54k
      if (arm_decode_field (given, 16, 18) == 0)
5866
666
  {
5867
666
    unsigned long sz = arm_decode_field (given, 19, 20);
5868
5869
666
    if ((sz == 1) || (sz == 2))
5870
400
      return true;
5871
266
    else
5872
266
      return false;
5873
666
  }
5874
877
      else
5875
877
  return false;
5876
5877
522
    case MVE_VQSHL_T2:
5878
960
    case MVE_VQSHLU_T3:
5879
1.69k
    case MVE_VRSHR:
5880
1.90k
    case MVE_VSHL_T1:
5881
2.51k
    case MVE_VSHR:
5882
2.83k
    case MVE_VSLI:
5883
3.44k
    case MVE_VSRI:
5884
3.44k
      if (arm_decode_field (given, 19, 21) == 0)
5885
666
  return true;
5886
2.77k
      else
5887
2.77k
  return false;
5888
5889
775
    case MVE_VCTP:
5890
775
    if (arm_decode_field (given, 16, 19) == 0xf)
5891
195
      return true;
5892
580
    else
5893
580
      return false;
5894
5895
296
    case MVE_ASRLI:
5896
1.12k
    case MVE_ASRL:
5897
2.08k
    case MVE_LSLLI:
5898
2.73k
    case MVE_LSLL:
5899
3.59k
    case MVE_LSRL:
5900
4.24k
    case MVE_SQRSHRL:
5901
4.86k
    case MVE_SQSHLL:
5902
5.30k
    case MVE_SRSHRL:
5903
5.57k
    case MVE_UQRSHLL:
5904
6.16k
    case MVE_UQSHLL:
5905
6.50k
    case MVE_URSHRL:
5906
6.50k
      if (arm_decode_field (given, 9, 11) == 0x7)
5907
2.18k
  return true;
5908
4.32k
      else
5909
4.32k
  return false;
5910
5911
913
    case MVE_CSINC:
5912
1.72k
    case MVE_CSINV:
5913
1.72k
      {
5914
1.72k
  unsigned long rm, rn;
5915
1.72k
  rm = arm_decode_field (given, 0, 3);
5916
1.72k
  rn = arm_decode_field (given, 16, 19);
5917
  /* CSET/CSETM.  */
5918
1.72k
  if (rm == 0xf && rn == 0xf)
5919
337
    return true;
5920
  /* CINC/CINV.  */
5921
1.38k
  else if (rn == rm && rn != 0xf)
5922
341
    return true;
5923
1.72k
      }
5924
    /* Fall through.  */
5925
1.27k
    case MVE_CSEL:
5926
2.31k
    case MVE_CSNEG:
5927
2.31k
      if (arm_decode_field (given, 0, 3) == 0xd)
5928
301
  return true;
5929
      /* CNEG.  */
5930
2.01k
      else if (matched_insn == MVE_CSNEG)
5931
1.02k
  if (arm_decode_field (given, 0, 3) == arm_decode_field (given, 16, 19))
5932
591
    return true;
5933
1.42k
      return false;
5934
5935
52.1k
    default:
5936
52.4k
    case MVE_VADD_FP_T1:
5937
52.6k
    case MVE_VADD_FP_T2:
5938
52.8k
    case MVE_VADD_VEC_T1:
5939
52.8k
      return false;
5940
5941
148k
    }
5942
148k
}
5943
5944
static void
5945
print_mve_vld_str_addr (struct disassemble_info *info,
5946
      unsigned long given,
5947
      enum mve_instructions matched_insn)
5948
7.44k
{
5949
7.44k
  void *stream = info->stream;
5950
7.44k
  fprintf_styled_ftype func = info->fprintf_styled_func;
5951
5952
7.44k
  unsigned long p, w, gpr, imm, add, mod_imm;
5953
5954
7.44k
  imm = arm_decode_field (given, 0, 6);
5955
7.44k
  mod_imm = imm;
5956
5957
7.44k
  switch (matched_insn)
5958
7.44k
    {
5959
450
    case MVE_VLDRB_T1:
5960
1.31k
    case MVE_VSTRB_T1:
5961
1.31k
      gpr = arm_decode_field (given, 16, 18);
5962
1.31k
      break;
5963
5964
1.05k
    case MVE_VLDRH_T2:
5965
2.55k
    case MVE_VSTRH_T2:
5966
2.55k
      gpr = arm_decode_field (given, 16, 18);
5967
2.55k
      mod_imm = imm << 1;
5968
2.55k
      break;
5969
5970
1.54k
    case MVE_VLDRH_T6:
5971
1.85k
    case MVE_VSTRH_T6:
5972
1.85k
      gpr = arm_decode_field (given, 16, 19);
5973
1.85k
      mod_imm = imm << 1;
5974
1.85k
      break;
5975
5976
524
    case MVE_VLDRW_T7:
5977
1.01k
    case MVE_VSTRW_T7:
5978
1.01k
      gpr = arm_decode_field (given, 16, 19);
5979
1.01k
      mod_imm = imm << 2;
5980
1.01k
      break;
5981
5982
311
    case MVE_VLDRB_T5:
5983
688
    case MVE_VSTRB_T5:
5984
688
      gpr = arm_decode_field (given, 16, 19);
5985
688
      break;
5986
5987
0
    default:
5988
0
      return;
5989
7.44k
    }
5990
5991
7.44k
  p = arm_decode_field (given, 24, 24);
5992
7.44k
  w = arm_decode_field (given, 21, 21);
5993
5994
7.44k
  add = arm_decode_field (given, 23, 23);
5995
5996
7.44k
  char * add_sub;
5997
5998
  /* Don't print anything for '+' as it is implied.  */
5999
7.44k
  if (add == 1)
6000
4.28k
    add_sub = "";
6001
3.15k
  else
6002
3.15k
    add_sub = "-";
6003
6004
7.44k
  func (stream, dis_style_text, "[");
6005
7.44k
  func (stream, dis_style_register, "%s", arm_regnames[gpr]);
6006
7.44k
  if (p == 1)
6007
4.75k
    {
6008
4.75k
      func (stream, dis_style_text, ", ");
6009
4.75k
      func (stream, dis_style_immediate, "#%s%lu", add_sub, mod_imm);
6010
      /* Offset mode.  */
6011
4.75k
      if (w == 0)
6012
2.93k
  func (stream, dis_style_text, "]");
6013
      /* Pre-indexed mode.  */
6014
1.82k
      else
6015
1.82k
  func (stream, dis_style_text, "]!");
6016
4.75k
    }
6017
2.68k
  else if ((p == 0) && (w == 1))
6018
2.30k
    {
6019
      /* Post-index mode.  */
6020
2.30k
      func (stream, dis_style_text, "], ");
6021
2.30k
      func (stream, dis_style_immediate, "#%s%lu", add_sub, mod_imm);
6022
2.30k
    }
6023
7.44k
}
6024
6025
/* Return FALSE if GIVEN is not an undefined encoding for MATCHED_INSN.
6026
   Otherwise, return TRUE and set UNDEFINED_CODE to give a reason as to why
6027
   this encoding is undefined.  */
6028
6029
static bool
6030
is_mve_undefined (unsigned long given, enum mve_instructions matched_insn,
6031
      enum mve_undefined *undefined_code)
6032
116k
{
6033
116k
  *undefined_code = UNDEF_NONE;
6034
6035
116k
  switch (matched_insn)
6036
116k
    {
6037
1.02k
    case MVE_VDUP:
6038
1.02k
      if (arm_decode_field_multiple (given, 5, 5, 22, 22) == 3)
6039
202
  {
6040
202
    *undefined_code = UNDEF_SIZE_3;
6041
202
    return true;
6042
202
  }
6043
821
      else
6044
821
  return false;
6045
6046
565
    case MVE_VQADD_T1:
6047
847
    case MVE_VQSUB_T1:
6048
1.04k
    case MVE_VMUL_VEC_T1:
6049
1.28k
    case MVE_VABD_VEC:
6050
1.49k
    case MVE_VADD_VEC_T1:
6051
1.70k
    case MVE_VSUB_VEC_T1:
6052
1.91k
    case MVE_VQDMULH_T1:
6053
2.10k
    case MVE_VQRDMULH_T2:
6054
2.34k
    case MVE_VRHADD:
6055
2.85k
    case MVE_VHADD_T1:
6056
3.06k
    case MVE_VHSUB_T1:
6057
3.06k
      if (arm_decode_field (given, 20, 21) == 3)
6058
424
  {
6059
424
    *undefined_code = UNDEF_SIZE_3;
6060
424
    return true;
6061
424
  }
6062
2.64k
      else
6063
2.64k
  return false;
6064
6065
450
    case MVE_VLDRB_T1:
6066
450
      if (arm_decode_field (given, 7, 8) == 3)
6067
209
  {
6068
209
    *undefined_code = UNDEF_SIZE_3;
6069
209
    return true;
6070
209
  }
6071
241
      else
6072
241
  return false;
6073
6074
1.05k
    case MVE_VLDRH_T2:
6075
1.05k
      if (arm_decode_field (given, 7, 8) <= 1)
6076
642
  {
6077
642
    *undefined_code = UNDEF_SIZE_LE_1;
6078
642
    return true;
6079
642
  }
6080
411
      else
6081
411
  return false;
6082
6083
869
    case MVE_VSTRB_T1:
6084
869
      if ((arm_decode_field (given, 7, 8) == 0))
6085
415
  {
6086
415
    *undefined_code = UNDEF_SIZE_0;
6087
415
    return true;
6088
415
  }
6089
454
      else
6090
454
  return false;
6091
6092
1.50k
    case MVE_VSTRH_T2:
6093
1.50k
      if ((arm_decode_field (given, 7, 8) <= 1))
6094
352
  {
6095
352
    *undefined_code = UNDEF_SIZE_LE_1;
6096
352
    return true;
6097
352
  }
6098
1.15k
      else
6099
1.15k
  return false;
6100
6101
1.01k
    case MVE_VLDRB_GATHER_T1:
6102
1.01k
      if (arm_decode_field (given, 7, 8) == 3)
6103
219
  {
6104
219
    *undefined_code = UNDEF_SIZE_3;
6105
219
    return true;
6106
219
  }
6107
796
      else if ((arm_decode_field (given, 28, 28) == 0)
6108
796
         && (arm_decode_field (given, 7, 8) == 0))
6109
226
  {
6110
226
    *undefined_code = UNDEF_NOT_UNS_SIZE_0;
6111
226
    return true;
6112
226
  }
6113
570
      else
6114
570
  return false;
6115
6116
1.25k
    case MVE_VLDRH_GATHER_T2:
6117
1.25k
      if (arm_decode_field (given, 7, 8) == 3)
6118
229
  {
6119
229
    *undefined_code = UNDEF_SIZE_3;
6120
229
    return true;
6121
229
  }
6122
1.02k
      else if ((arm_decode_field (given, 28, 28) == 0)
6123
1.02k
         && (arm_decode_field (given, 7, 8) == 1))
6124
432
  {
6125
432
    *undefined_code = UNDEF_NOT_UNS_SIZE_1;
6126
432
    return true;
6127
432
  }
6128
591
      else if (arm_decode_field (given, 7, 8) == 0)
6129
363
  {
6130
363
    *undefined_code = UNDEF_SIZE_0;
6131
363
    return true;
6132
363
  }
6133
228
      else
6134
228
  return false;
6135
6136
418
    case MVE_VLDRW_GATHER_T3:
6137
418
      if (arm_decode_field (given, 7, 8) != 2)
6138
0
  {
6139
0
    *undefined_code = UNDEF_SIZE_NOT_2;
6140
0
    return true;
6141
0
  }
6142
418
      else if (arm_decode_field (given, 28, 28) == 0)
6143
0
  {
6144
0
    *undefined_code = UNDEF_NOT_UNSIGNED;
6145
0
    return true;
6146
0
  }
6147
418
      else
6148
418
  return false;
6149
6150
392
    case MVE_VLDRD_GATHER_T4:
6151
392
      if (arm_decode_field (given, 7, 8) != 3)
6152
0
  {
6153
0
    *undefined_code = UNDEF_SIZE_NOT_3;
6154
0
    return true;
6155
0
  }
6156
392
      else if (arm_decode_field (given, 28, 28) == 0)
6157
197
  {
6158
197
    *undefined_code = UNDEF_NOT_UNSIGNED;
6159
197
    return true;
6160
197
  }
6161
195
      else
6162
195
  return false;
6163
6164
1.09k
    case MVE_VSTRB_SCATTER_T1:
6165
1.09k
      if (arm_decode_field (given, 7, 8) == 3)
6166
624
  {
6167
624
    *undefined_code = UNDEF_SIZE_3;
6168
624
    return true;
6169
624
  }
6170
468
      else
6171
468
  return false;
6172
6173
826
    case MVE_VSTRH_SCATTER_T2:
6174
826
      {
6175
826
  unsigned long size = arm_decode_field (given, 7, 8);
6176
826
  if (size == 3)
6177
244
    {
6178
244
      *undefined_code = UNDEF_SIZE_3;
6179
244
      return true;
6180
244
    }
6181
582
  else if (size == 0)
6182
208
    {
6183
208
      *undefined_code = UNDEF_SIZE_0;
6184
208
      return true;
6185
208
    }
6186
374
  else
6187
374
    return false;
6188
826
      }
6189
6190
952
    case MVE_VSTRW_SCATTER_T3:
6191
952
      if (arm_decode_field (given, 7, 8) != 2)
6192
742
  {
6193
742
    *undefined_code = UNDEF_SIZE_NOT_2;
6194
742
    return true;
6195
742
  }
6196
210
      else
6197
210
  return false;
6198
6199
210
    case MVE_VSTRD_SCATTER_T4:
6200
210
      if (arm_decode_field (given, 7, 8) != 3)
6201
0
  {
6202
0
    *undefined_code = UNDEF_SIZE_NOT_3;
6203
0
    return true;
6204
0
  }
6205
210
      else
6206
210
  return false;
6207
6208
3.06k
    case MVE_VCVT_FP_FIX_VEC:
6209
3.06k
      {
6210
3.06k
  unsigned long imm6 = arm_decode_field (given, 16, 21);
6211
3.06k
  if ((imm6 & 0x20) == 0)
6212
381
    {
6213
381
      *undefined_code = UNDEF_VCVT_IMM6;
6214
381
      return true;
6215
381
    }
6216
6217
2.68k
  if ((arm_decode_field (given, 9, 9) == 0)
6218
2.68k
      && ((imm6 & 0x30) == 0x20))
6219
977
    {
6220
977
      *undefined_code = UNDEF_VCVT_FSI_IMM6;
6221
977
      return true;
6222
977
    }
6223
6224
1.70k
  return false;
6225
2.68k
      }
6226
6227
224
    case MVE_VNEG_FP:
6228
426
    case MVE_VABS_FP:
6229
2.56k
    case MVE_VCVT_BETWEEN_FP_INT:
6230
4.36k
    case MVE_VCVT_FROM_FP_TO_INT:
6231
4.36k
      {
6232
4.36k
  unsigned long size = arm_decode_field (given, 18, 19);
6233
4.36k
  if (size == 0)
6234
216
    {
6235
216
      *undefined_code = UNDEF_SIZE_0;
6236
216
      return true;
6237
216
    }
6238
4.14k
  else if (size == 3)
6239
1.15k
    {
6240
1.15k
      *undefined_code = UNDEF_SIZE_3;
6241
1.15k
      return true;
6242
1.15k
    }
6243
2.99k
  else
6244
2.99k
    return false;
6245
4.36k
      }
6246
6247
4.22k
    case MVE_VMOV_VEC_LANE_TO_GP:
6248
4.22k
      {
6249
4.22k
  unsigned long op1 = arm_decode_field (given, 21, 22);
6250
4.22k
  unsigned long op2 = arm_decode_field (given, 5, 6);
6251
4.22k
  unsigned long u = arm_decode_field (given, 23, 23);
6252
6253
4.22k
  if ((op2 == 0) && (u == 1))
6254
1.29k
    {
6255
1.29k
      if ((op1 == 0) || (op1 == 1))
6256
651
        {
6257
651
    *undefined_code = UNDEF_BAD_U_OP1_OP2;
6258
651
    return true;
6259
651
        }
6260
646
      else
6261
646
        return false;
6262
1.29k
    }
6263
2.92k
  else if (op2 == 2)
6264
1.02k
    {
6265
1.02k
      if ((op1 == 0) || (op1 == 1))
6266
791
        {
6267
791
    *undefined_code = UNDEF_BAD_OP1_OP2;
6268
791
    return true;
6269
791
        }
6270
238
      else
6271
238
        return false;
6272
1.02k
    }
6273
6274
1.89k
  return false;
6275
4.22k
      }
6276
6277
2.02k
    case MVE_VMOV_GP_TO_VEC_LANE:
6278
2.02k
      if (arm_decode_field (given, 5, 6) == 2)
6279
622
  {
6280
622
    unsigned long op1 = arm_decode_field (given, 21, 22);
6281
622
    if ((op1 == 0) || (op1 == 1))
6282
417
      {
6283
417
        *undefined_code = UNDEF_BAD_OP1_OP2;
6284
417
        return true;
6285
417
      }
6286
205
    else
6287
205
      return false;
6288
622
  }
6289
1.40k
      else
6290
1.40k
  return false;
6291
6292
590
    case MVE_VMOV_VEC_TO_VEC:
6293
590
      if ((arm_decode_field (given, 5, 5) == 1)
6294
590
    || (arm_decode_field (given, 22, 22) == 1))
6295
393
    return true;
6296
197
      return false;
6297
6298
2.95k
    case MVE_VMOV_IMM_TO_VEC:
6299
2.95k
      if (arm_decode_field (given, 5, 5) == 0)
6300
2.39k
      {
6301
2.39k
  unsigned long cmode = arm_decode_field (given, 8, 11);
6302
6303
2.39k
  if (((cmode & 9) == 1) || ((cmode & 5) == 1))
6304
0
    {
6305
0
      *undefined_code = UNDEF_OP_0_BAD_CMODE;
6306
0
      return true;
6307
0
    }
6308
2.39k
  else
6309
2.39k
    return false;
6310
2.39k
      }
6311
561
      else
6312
561
  return false;
6313
6314
423
    case MVE_VSHLL_T2:
6315
737
    case MVE_VMOVN:
6316
737
      if (arm_decode_field (given, 18, 19) == 2)
6317
310
  {
6318
310
    *undefined_code = UNDEF_SIZE_2;
6319
310
    return true;
6320
310
  }
6321
427
      else
6322
427
  return false;
6323
6324
390
    case MVE_VRMLALDAVH:
6325
781
    case MVE_VMLADAV_T1:
6326
1.02k
    case MVE_VMLADAV_T2:
6327
2.25k
    case MVE_VMLALDAV:
6328
2.25k
      if ((arm_decode_field (given, 28, 28) == 1)
6329
2.25k
    && (arm_decode_field (given, 12, 12) == 1))
6330
644
  {
6331
644
    *undefined_code = UNDEF_XCHG_UNS;
6332
644
    return true;
6333
644
  }
6334
1.61k
      else
6335
1.61k
  return false;
6336
6337
248
    case MVE_VQSHRN:
6338
1.02k
    case MVE_VQSHRUN:
6339
2.16k
    case MVE_VSHLL_T1:
6340
2.81k
    case MVE_VSHRN:
6341
2.81k
      {
6342
2.81k
  unsigned long sz = arm_decode_field (given, 19, 20);
6343
2.81k
  if (sz == 1)
6344
1.32k
    return false;
6345
1.48k
  else if ((sz & 2) == 2)
6346
892
    return false;
6347
595
  else
6348
595
    {
6349
595
      *undefined_code = UNDEF_SIZE;
6350
595
      return true;
6351
595
    }
6352
2.81k
      }
6353
0
      break;
6354
6355
522
    case MVE_VQSHL_T2:
6356
887
    case MVE_VQSHLU_T3:
6357
1.24k
    case MVE_VRSHR:
6358
1.45k
    case MVE_VSHL_T1:
6359
2.05k
    case MVE_VSHR:
6360
2.37k
    case MVE_VSLI:
6361
2.77k
    case MVE_VSRI:
6362
2.77k
      {
6363
2.77k
  unsigned long sz = arm_decode_field (given, 19, 21);
6364
2.77k
  if ((sz & 7) == 1)
6365
223
    return false;
6366
2.55k
  else if ((sz & 6) == 2)
6367
459
    return false;
6368
2.09k
  else if ((sz & 4) == 4)
6369
2.09k
    return false;
6370
0
  else
6371
0
    {
6372
0
      *undefined_code = UNDEF_SIZE;
6373
0
      return true;
6374
0
    }
6375
2.77k
      }
6376
6377
229
    case MVE_VQRSHRN:
6378
706
    case MVE_VQRSHRUN:
6379
706
      if (arm_decode_field (given, 19, 20) == 0)
6380
313
  {
6381
313
    *undefined_code = UNDEF_SIZE_0;
6382
313
    return true;
6383
313
  }
6384
393
      else
6385
393
  return false;
6386
6387
393
    case MVE_VABS_VEC:
6388
393
  if (arm_decode_field (given, 18, 19) == 3)
6389
194
  {
6390
194
    *undefined_code = UNDEF_SIZE_3;
6391
194
    return true;
6392
194
  }
6393
199
  else
6394
199
    return false;
6395
6396
311
    case MVE_VQNEG:
6397
507
    case MVE_VQABS:
6398
708
    case MVE_VNEG_VEC:
6399
912
    case MVE_VCLS:
6400
1.13k
    case MVE_VCLZ:
6401
1.13k
      if (arm_decode_field (given, 18, 19) == 3)
6402
201
  {
6403
201
    *undefined_code = UNDEF_SIZE_3;
6404
201
    return true;
6405
201
  }
6406
938
      else
6407
938
  return false;
6408
6409
424
    case MVE_VREV16:
6410
424
      if (arm_decode_field (given, 18, 19) == 0)
6411
225
  return false;
6412
199
      else
6413
199
  {
6414
199
    *undefined_code = UNDEF_SIZE_NOT_0;
6415
199
    return true;
6416
199
  }
6417
6418
433
    case MVE_VREV32:
6419
433
      {
6420
433
  unsigned long size = arm_decode_field (given, 18, 19);
6421
433
  if ((size & 2) == 2)
6422
237
    {
6423
237
      *undefined_code = UNDEF_SIZE_2;
6424
237
      return true;
6425
237
    }
6426
196
  else
6427
196
    return false;
6428
433
      }
6429
6430
592
    case MVE_VREV64:
6431
592
      if (arm_decode_field (given, 18, 19) != 3)
6432
285
  return false;
6433
307
      else
6434
307
  {
6435
307
    *undefined_code = UNDEF_SIZE_3;
6436
307
    return true;
6437
307
  }
6438
6439
73.3k
    default:
6440
73.3k
      return false;
6441
116k
    }
6442
116k
}
6443
6444
/* Return FALSE if GIVEN is not an unpredictable encoding for MATCHED_INSN.
6445
   Otherwise, return TRUE and set UNPREDICTABLE_CODE to give a reason as to
6446
   why this encoding is unpredictable.  */
6447
6448
static bool
6449
is_mve_unpredictable (unsigned long given, enum mve_instructions matched_insn,
6450
          enum mve_unpredictable *unpredictable_code)
6451
115k
{
6452
115k
  *unpredictable_code = UNPRED_NONE;
6453
6454
115k
  switch (matched_insn)
6455
115k
    {
6456
218
    case MVE_VCMP_FP_T2:
6457
816
    case MVE_VPT_FP_T2:
6458
816
      if ((arm_decode_field (given, 12, 12) == 0)
6459
816
    && (arm_decode_field (given, 5, 5) == 1))
6460
349
  {
6461
349
    *unpredictable_code = UNPRED_FCA_0_FCB_1;
6462
349
    return true;
6463
349
  }
6464
467
      else
6465
467
  return false;
6466
6467
1.52k
    case MVE_VPT_VEC_T4:
6468
2.40k
    case MVE_VPT_VEC_T5:
6469
4.14k
    case MVE_VPT_VEC_T6:
6470
4.68k
    case MVE_VCMP_VEC_T4:
6471
4.91k
    case MVE_VCMP_VEC_T5:
6472
5.16k
    case MVE_VCMP_VEC_T6:
6473
5.16k
      if (arm_decode_field (given, 0, 3) == 0xd)
6474
921
  {
6475
921
    *unpredictable_code = UNPRED_R13;
6476
921
    return true;
6477
921
  }
6478
4.24k
      else
6479
4.24k
  return false;
6480
6481
1.01k
    case MVE_VDUP:
6482
1.01k
      {
6483
1.01k
  unsigned long gpr = arm_decode_field (given, 12, 15);
6484
1.01k
  if (gpr == 0xd)
6485
194
    {
6486
194
      *unpredictable_code = UNPRED_R13;
6487
194
      return true;
6488
194
    }
6489
825
  else if (gpr == 0xf)
6490
195
    {
6491
195
      *unpredictable_code = UNPRED_R15;
6492
195
      return true;
6493
195
    }
6494
6495
630
  return false;
6496
1.01k
      }
6497
6498
400
    case MVE_VQADD_T2:
6499
1.56k
    case MVE_VQSUB_T2:
6500
1.94k
    case MVE_VMUL_FP_T2:
6501
2.15k
    case MVE_VMUL_VEC_T2:
6502
2.45k
    case MVE_VMLA:
6503
4.14k
    case MVE_VBRSR:
6504
4.41k
    case MVE_VADD_FP_T2:
6505
4.73k
    case MVE_VSUB_FP_T2:
6506
4.94k
    case MVE_VADD_VEC_T2:
6507
5.17k
    case MVE_VSUB_VEC_T2:
6508
5.37k
    case MVE_VQRSHL_T2:
6509
5.57k
    case MVE_VQSHL_T1:
6510
5.76k
    case MVE_VRSHL_T2:
6511
5.96k
    case MVE_VSHL_T2:
6512
6.52k
    case MVE_VSHLC:
6513
7.26k
    case MVE_VQDMLAH:
6514
7.46k
    case MVE_VQRDMLAH:
6515
7.68k
    case MVE_VQDMLASH:
6516
7.88k
    case MVE_VQRDMLASH:
6517
8.33k
    case MVE_VQDMULH_T3:
6518
8.82k
    case MVE_VQRDMULH_T4:
6519
9.17k
    case MVE_VMLAS:
6520
9.69k
    case MVE_VFMA_FP_SCALAR:
6521
10.0k
    case MVE_VFMAS_FP_SCALAR:
6522
10.3k
    case MVE_VHADD_T2:
6523
10.5k
    case MVE_VHSUB_T2:
6524
10.5k
      {
6525
10.5k
  unsigned long gpr = arm_decode_field (given, 0, 3);
6526
10.5k
  if (gpr == 0xd)
6527
2.17k
    {
6528
2.17k
      *unpredictable_code = UNPRED_R13;
6529
2.17k
      return true;
6530
2.17k
    }
6531
8.42k
  else if (gpr == 0xf)
6532
553
    {
6533
553
      *unpredictable_code = UNPRED_R15;
6534
553
      return true;
6535
553
    }
6536
6537
7.87k
  return false;
6538
10.5k
      }
6539
6540
348
    case MVE_VLD2:
6541
1.15k
    case MVE_VST2:
6542
1.15k
      {
6543
1.15k
  unsigned long rn = arm_decode_field (given, 16, 19);
6544
6545
1.15k
  if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
6546
76
    {
6547
76
      *unpredictable_code = UNPRED_R13_AND_WB;
6548
76
      return true;
6549
76
    }
6550
6551
1.08k
  if (rn == 0xf)
6552
463
    {
6553
463
      *unpredictable_code = UNPRED_R15;
6554
463
      return true;
6555
463
    }
6556
6557
617
  if (arm_decode_field_multiple (given, 13, 15, 22, 22) > 6)
6558
255
    {
6559
255
      *unpredictable_code = UNPRED_Q_GT_6;
6560
255
      return true;
6561
255
    }
6562
362
  else
6563
362
    return false;
6564
617
      }
6565
6566
643
    case MVE_VLD4:
6567
1.06k
    case MVE_VST4:
6568
1.06k
      {
6569
1.06k
  unsigned long rn = arm_decode_field (given, 16, 19);
6570
6571
1.06k
  if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
6572
198
    {
6573
198
      *unpredictable_code = UNPRED_R13_AND_WB;
6574
198
      return true;
6575
198
    }
6576
6577
868
  if (rn == 0xf)
6578
224
    {
6579
224
      *unpredictable_code = UNPRED_R15;
6580
224
      return true;
6581
224
    }
6582
6583
644
  if (arm_decode_field_multiple (given, 13, 15, 22, 22) > 4)
6584
431
    {
6585
431
      *unpredictable_code = UNPRED_Q_GT_4;
6586
431
      return true;
6587
431
    }
6588
213
  else
6589
213
    return false;
6590
644
      }
6591
6592
311
    case MVE_VLDRB_T5:
6593
1.85k
    case MVE_VLDRH_T6:
6594
2.37k
    case MVE_VLDRW_T7:
6595
2.75k
    case MVE_VSTRB_T5:
6596
3.06k
    case MVE_VSTRH_T6:
6597
3.56k
    case MVE_VSTRW_T7:
6598
3.56k
      {
6599
3.56k
  unsigned long rn = arm_decode_field (given, 16, 19);
6600
6601
3.56k
  if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
6602
275
    {
6603
275
      *unpredictable_code = UNPRED_R13_AND_WB;
6604
275
      return true;
6605
275
    }
6606
3.28k
  else if (rn == 0xf)
6607
674
    {
6608
674
      *unpredictable_code = UNPRED_R15;
6609
674
      return true;
6610
674
    }
6611
2.61k
  else
6612
2.61k
    return false;
6613
3.56k
      }
6614
6615
1.01k
    case MVE_VLDRB_GATHER_T1:
6616
1.01k
      if (arm_decode_field (given, 0, 0) == 1)
6617
220
  {
6618
220
    *unpredictable_code = UNPRED_OS;
6619
220
    return true;
6620
220
  }
6621
6622
      /*  fall through.  */
6623
      /* To handle common code with T2-T4 variants.  */
6624
2.04k
    case MVE_VLDRH_GATHER_T2:
6625
2.46k
    case MVE_VLDRW_GATHER_T3:
6626
2.85k
    case MVE_VLDRD_GATHER_T4:
6627
2.85k
      {
6628
2.85k
  unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6629
2.85k
  unsigned long qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6630
6631
2.85k
  if (qd == qm)
6632
697
    {
6633
697
      *unpredictable_code = UNPRED_Q_REGS_EQUAL;
6634
697
      return true;
6635
697
    }
6636
6637
2.15k
  if (arm_decode_field (given, 16, 19) == 0xf)
6638
1.55k
    {
6639
1.55k
      *unpredictable_code = UNPRED_R15;
6640
1.55k
      return true;
6641
1.55k
    }
6642
6643
607
  return false;
6644
2.15k
      }
6645
6646
606
    case MVE_VLDRW_GATHER_T5:
6647
856
    case MVE_VLDRD_GATHER_T6:
6648
856
      {
6649
856
  unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6650
856
  unsigned long qm = arm_decode_field_multiple (given, 17, 19, 7, 7);
6651
6652
856
  if (qd == qm)
6653
299
    {
6654
299
      *unpredictable_code = UNPRED_Q_REGS_EQUAL;
6655
299
      return true;
6656
299
    }
6657
557
  else
6658
557
    return false;
6659
856
      }
6660
6661
1.09k
    case MVE_VSTRB_SCATTER_T1:
6662
1.09k
      if (arm_decode_field (given, 16, 19) == 0xf)
6663
567
  {
6664
567
    *unpredictable_code = UNPRED_R15;
6665
567
    return true;
6666
567
  }
6667
524
      else if (arm_decode_field (given, 0, 0) == 1)
6668
303
  {
6669
303
    *unpredictable_code = UNPRED_OS;
6670
303
    return true;
6671
303
  }
6672
221
      else
6673
221
  return false;
6674
6675
826
    case MVE_VSTRH_SCATTER_T2:
6676
1.77k
    case MVE_VSTRW_SCATTER_T3:
6677
1.98k
    case MVE_VSTRD_SCATTER_T4:
6678
1.98k
      if (arm_decode_field (given, 16, 19) == 0xf)
6679
793
  {
6680
793
    *unpredictable_code = UNPRED_R15;
6681
793
    return true;
6682
793
  }
6683
1.19k
      else
6684
1.19k
  return false;
6685
6686
1.30k
    case MVE_VMOV2_VEC_LANE_TO_GP:
6687
2.36k
    case MVE_VMOV2_GP_TO_VEC_LANE:
6688
4.49k
    case MVE_VCVT_BETWEEN_FP_INT:
6689
6.29k
    case MVE_VCVT_FROM_FP_TO_INT:
6690
6.29k
      {
6691
6.29k
  unsigned long rt = arm_decode_field (given, 0, 3);
6692
6.29k
  unsigned long rt2 = arm_decode_field (given, 16, 19);
6693
6694
6.29k
  if ((rt == 0xd) || (rt2 == 0xd))
6695
791
    {
6696
791
      *unpredictable_code = UNPRED_R13;
6697
791
      return true;
6698
791
    }
6699
5.50k
  else if ((rt == 0xf) || (rt2 == 0xf))
6700
2.11k
    {
6701
2.11k
      *unpredictable_code = UNPRED_R15;
6702
2.11k
      return true;
6703
2.11k
    }
6704
3.38k
  else if (rt == rt2 && matched_insn != MVE_VMOV2_GP_TO_VEC_LANE)
6705
196
    {
6706
196
      *unpredictable_code = UNPRED_GP_REGS_EQUAL;
6707
196
      return true;
6708
196
    }
6709
6710
3.19k
  return false;
6711
6.29k
      }
6712
6713
207
    case MVE_VMAXV:
6714
650
    case MVE_VMAXAV:
6715
852
    case MVE_VMAXNMV_FP:
6716
1.07k
    case MVE_VMAXNMAV_FP:
6717
1.33k
    case MVE_VMINNMV_FP:
6718
1.52k
    case MVE_VMINNMAV_FP:
6719
1.72k
    case MVE_VMINV:
6720
1.93k
    case MVE_VMINAV:
6721
2.13k
    case MVE_VABAV:
6722
2.32k
    case MVE_VMOV_HFP_TO_GP:
6723
4.35k
    case MVE_VMOV_GP_TO_VEC_LANE:
6724
8.57k
    case MVE_VMOV_VEC_LANE_TO_GP:
6725
8.57k
      {
6726
8.57k
  unsigned long rda = arm_decode_field (given, 12, 15);
6727
8.57k
  if (rda == 0xd)
6728
197
    {
6729
197
      *unpredictable_code = UNPRED_R13;
6730
197
      return true;
6731
197
    }
6732
8.37k
  else if (rda == 0xf)
6733
1.08k
    {
6734
1.08k
      *unpredictable_code = UNPRED_R15;
6735
1.08k
      return true;
6736
1.08k
    }
6737
6738
7.29k
  return false;
6739
8.57k
      }
6740
6741
1.13k
    case MVE_VMULL_INT:
6742
1.13k
      {
6743
1.13k
  unsigned long Qd;
6744
1.13k
  unsigned long Qm;
6745
1.13k
  unsigned long Qn;
6746
6747
1.13k
  if (arm_decode_field (given, 20, 21) == 2)
6748
900
    {
6749
900
      Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6750
900
      Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6751
900
      Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6752
6753
900
      if ((Qd == Qn) || (Qd == Qm))
6754
464
        {
6755
464
    *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_2;
6756
464
    return true;
6757
464
        }
6758
436
      else
6759
436
        return false;
6760
900
    }
6761
231
  else
6762
231
    return false;
6763
1.13k
      }
6764
6765
984
    case MVE_VCMUL_FP:
6766
1.25k
    case MVE_VQDMULL_T1:
6767
1.25k
      {
6768
1.25k
  unsigned long Qd;
6769
1.25k
  unsigned long Qm;
6770
1.25k
  unsigned long Qn;
6771
6772
1.25k
  if (arm_decode_field (given, 28, 28) == 1)
6773
902
    {
6774
902
      Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6775
902
      Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6776
902
      Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6777
6778
902
      if ((Qd == Qn) || (Qd == Qm))
6779
653
        {
6780
653
    *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
6781
653
    return true;
6782
653
        }
6783
249
      else
6784
249
        return false;
6785
902
    }
6786
351
  else
6787
351
    return false;
6788
1.25k
      }
6789
6790
1.50k
    case MVE_VQDMULL_T2:
6791
1.50k
      {
6792
1.50k
  unsigned long gpr = arm_decode_field (given, 0, 3);
6793
1.50k
  if (gpr == 0xd)
6794
196
    {
6795
196
      *unpredictable_code = UNPRED_R13;
6796
196
      return true;
6797
196
    }
6798
1.31k
  else if (gpr == 0xf)
6799
194
    {
6800
194
      *unpredictable_code = UNPRED_R15;
6801
194
      return true;
6802
194
    }
6803
6804
1.11k
  if (arm_decode_field (given, 28, 28) == 1)
6805
583
    {
6806
583
      unsigned long Qd
6807
583
        = arm_decode_field_multiple (given, 13, 15, 22, 22);
6808
583
      unsigned long Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6809
6810
583
      if (Qd == Qn)
6811
199
        {
6812
199
    *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
6813
199
    return true;
6814
199
        }
6815
384
      else
6816
384
        return false;
6817
583
    }
6818
6819
533
  return false;
6820
1.11k
      }
6821
6822
763
    case MVE_VMLSLDAV:
6823
1.01k
    case MVE_VRMLSLDAVH:
6824
2.24k
    case MVE_VMLALDAV:
6825
2.44k
    case MVE_VADDLV:
6826
2.44k
      if (arm_decode_field (given, 20, 22) == 6)
6827
1.15k
  {
6828
1.15k
    *unpredictable_code = UNPRED_R13;
6829
1.15k
    return true;
6830
1.15k
  }
6831
1.28k
      else
6832
1.28k
  return false;
6833
6834
549
    case MVE_VDWDUP:
6835
1.11k
    case MVE_VIWDUP:
6836
1.11k
      if (arm_decode_field (given, 1, 3) == 6)
6837
681
  {
6838
681
    *unpredictable_code = UNPRED_R13;
6839
681
    return true;
6840
681
  }
6841
432
      else
6842
432
  return false;
6843
6844
485
    case MVE_VCADD_VEC:
6845
1.01k
    case MVE_VHCADD:
6846
1.01k
      {
6847
1.01k
  unsigned long Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6848
1.01k
  unsigned long Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6849
1.01k
  if ((Qd == Qm) && arm_decode_field (given, 20, 21) == 2)
6850
226
    {
6851
226
      *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_2;
6852
226
      return true;
6853
226
    }
6854
789
  else
6855
789
    return false;
6856
1.01k
      }
6857
6858
894
    case MVE_VCADD_FP:
6859
894
      {
6860
894
  unsigned long Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6861
894
  unsigned long Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6862
894
  if ((Qd == Qm) && arm_decode_field (given, 20, 20) == 1)
6863
195
    {
6864
195
      *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
6865
195
      return true;
6866
195
    }
6867
699
  else
6868
699
    return false;
6869
894
      }
6870
6871
892
    case MVE_VCMLA_FP:
6872
892
      {
6873
892
  unsigned long Qda;
6874
892
  unsigned long Qm;
6875
892
  unsigned long Qn;
6876
6877
892
  if (arm_decode_field (given, 20, 20) == 1)
6878
595
    {
6879
595
      Qda = arm_decode_field_multiple (given, 13, 15, 22, 22);
6880
595
      Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6881
595
      Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6882
6883
595
      if ((Qda == Qn) || (Qda == Qm))
6884
389
        {
6885
389
    *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
6886
389
    return true;
6887
389
        }
6888
206
      else
6889
206
        return false;
6890
595
    }
6891
297
  else
6892
297
    return false;
6893
6894
892
      }
6895
6896
580
    case MVE_VCTP:
6897
580
      if (arm_decode_field (given, 16, 19) == 0xd)
6898
350
  {
6899
350
    *unpredictable_code = UNPRED_R13;
6900
350
    return true;
6901
350
  }
6902
230
      else
6903
230
  return false;
6904
6905
592
    case MVE_VREV64:
6906
592
      {
6907
592
  unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6908
592
  unsigned long qm = arm_decode_field_multiple (given, 1, 3, 6, 6);
6909
6910
592
  if (qd == qm)
6911
210
    {
6912
210
      *unpredictable_code = UNPRED_Q_REGS_EQUAL;
6913
210
      return true;
6914
210
    }
6915
382
  else
6916
382
    return false;
6917
592
      }
6918
6919
451
    case MVE_LSLL:
6920
861
    case MVE_LSLLI:
6921
1.30k
    case MVE_LSRL:
6922
1.74k
    case MVE_ASRL:
6923
2.03k
    case MVE_ASRLI:
6924
2.62k
    case MVE_UQSHLL:
6925
2.87k
    case MVE_UQRSHLL:
6926
3.21k
    case MVE_URSHRL:
6927
3.44k
    case MVE_SRSHRL:
6928
4.04k
    case MVE_SQSHLL:
6929
4.32k
    case MVE_SQRSHRL:
6930
4.32k
      {
6931
4.32k
  unsigned long gpr = arm_decode_field (given, 9, 11);
6932
4.32k
  gpr = ((gpr << 1) | 1);
6933
4.32k
  if (gpr == 0xd)
6934
1.59k
    {
6935
1.59k
      *unpredictable_code = UNPRED_R13;
6936
1.59k
      return true;
6937
1.59k
    }
6938
2.73k
  else if (gpr == 0xf)
6939
0
    {
6940
0
      *unpredictable_code = UNPRED_R15;
6941
0
      return true;
6942
0
    }
6943
6944
2.73k
  return false;
6945
4.32k
      }
6946
6947
54.2k
    default:
6948
54.2k
      return false;
6949
115k
    }
6950
115k
}
6951
6952
static void
6953
print_mve_vmov_index (struct disassemble_info *info, unsigned long given)
6954
6.24k
{
6955
6.24k
  unsigned long op1 = arm_decode_field (given, 21, 22);
6956
6.24k
  unsigned long op2 = arm_decode_field (given, 5, 6);
6957
6.24k
  unsigned long h = arm_decode_field (given, 16, 16);
6958
6.24k
  unsigned long index_operand, esize, targetBeat, idx;
6959
6.24k
  void *stream = info->stream;
6960
6.24k
  fprintf_styled_ftype func = info->fprintf_styled_func;
6961
6962
6.24k
  if ((op1 & 0x2) == 0x2)
6963
2.38k
    {
6964
2.38k
      index_operand = op2;
6965
2.38k
      esize = 8;
6966
2.38k
    }
6967
3.86k
  else if (((op1 & 0x2) == 0x0) && ((op2 & 0x1) == 0x1))
6968
1.01k
    {
6969
1.01k
      index_operand = op2  >> 1;
6970
1.01k
      esize = 16;
6971
1.01k
    }
6972
2.85k
  else if (((op1 & 0x2) == 0) && ((op2 & 0x3) == 0))
6973
1.64k
    {
6974
1.64k
      index_operand = 0;
6975
1.64k
      esize = 32;
6976
1.64k
    }
6977
1.20k
  else
6978
1.20k
    {
6979
1.20k
      func (stream, dis_style_text, "<undefined index>");
6980
1.20k
      return;
6981
1.20k
    }
6982
6983
5.03k
  targetBeat =  (op1 & 0x1) | (h << 1);
6984
5.03k
  idx = index_operand + targetBeat * (32/esize);
6985
6986
5.03k
  func (stream, dis_style_immediate, "%lu", idx);
6987
5.03k
}
6988
6989
/* Print neon and mve 8-bit immediate that can be a 8, 16, 32, or 64-bits
6990
   in length and integer of floating-point type.  */
6991
static void
6992
print_simd_imm8 (struct disassemble_info *info, unsigned long given,
6993
     unsigned int ibit_loc, const struct mopcode32 *insn)
6994
7.39k
{
6995
7.39k
  int bits = 0;
6996
7.39k
  int cmode = (given >> 8) & 0xf;
6997
7.39k
  int op = (given >> 5) & 0x1;
6998
7.39k
  unsigned long value = 0, hival = 0;
6999
7.39k
  unsigned shift;
7000
7.39k
  int size = 0;
7001
7.39k
  int isfloat = 0;
7002
7.39k
  void *stream = info->stream;
7003
7.39k
  fprintf_styled_ftype func = info->fprintf_styled_func;
7004
7005
  /* On Neon the 'i' bit is at bit 24, on mve it is
7006
     at bit 28.  */
7007
7.39k
  bits |= ((given >> ibit_loc) & 1) << 7;
7008
7.39k
  bits |= ((given >> 16) & 7) << 4;
7009
7.39k
  bits |= ((given >> 0) & 15) << 0;
7010
7011
7.39k
  if (cmode < 8)
7012
3.20k
    {
7013
3.20k
      shift = (cmode >> 1) & 3;
7014
3.20k
      value = (unsigned long) bits << (8 * shift);
7015
3.20k
      size = 32;
7016
3.20k
    }
7017
4.19k
  else if (cmode < 12)
7018
1.66k
    {
7019
1.66k
      shift = (cmode >> 1) & 1;
7020
1.66k
      value = (unsigned long) bits << (8 * shift);
7021
1.66k
      size = 16;
7022
1.66k
    }
7023
2.53k
  else if (cmode < 14)
7024
1.56k
    {
7025
1.56k
      shift = (cmode & 1) + 1;
7026
1.56k
      value = (unsigned long) bits << (8 * shift);
7027
1.56k
      value |= (1ul << (8 * shift)) - 1;
7028
1.56k
      size = 32;
7029
1.56k
    }
7030
962
  else if (cmode == 14)
7031
761
    {
7032
761
      if (op)
7033
561
  {
7034
    /* Bit replication into bytes.  */
7035
561
    int ix;
7036
561
    unsigned long mask;
7037
7038
561
    value = 0;
7039
561
    hival = 0;
7040
5.04k
    for (ix = 7; ix >= 0; ix--)
7041
4.48k
      {
7042
4.48k
        mask = ((bits >> ix) & 1) ? 0xff : 0;
7043
4.48k
        if (ix <= 3)
7044
2.24k
    value = (value << 8) | mask;
7045
2.24k
        else
7046
2.24k
    hival = (hival << 8) | mask;
7047
4.48k
      }
7048
561
    size = 64;
7049
561
  }
7050
200
      else
7051
200
  {
7052
    /* Byte replication.  */
7053
200
    value = (unsigned long) bits;
7054
200
    size = 8;
7055
200
  }
7056
761
    }
7057
201
  else if (!op)
7058
201
    {
7059
      /* Floating point encoding.  */
7060
201
      int tmp;
7061
7062
201
      value = (unsigned long)  (bits & 0x7f) << 19;
7063
201
      value |= (unsigned long) (bits & 0x80) << 24;
7064
201
      tmp = bits & 0x40 ? 0x3c : 0x40;
7065
201
      value |= (unsigned long) tmp << 24;
7066
201
      size = 32;
7067
201
      isfloat = 1;
7068
201
    }
7069
0
  else
7070
0
    {
7071
0
      func (stream, dis_style_text, "<illegal constant %.8x:%x:%x>",
7072
0
      bits, cmode, op);
7073
0
      size = 32;
7074
0
      return;
7075
0
    }
7076
7077
  /* printU determines whether the immediate value should be printed as
7078
     unsigned.  */
7079
7.39k
  unsigned printU = 0;
7080
7.39k
  switch (insn->mve_op)
7081
7.39k
    {
7082
0
    default:
7083
0
      break;
7084
    /* We want this for instructions that don't have a 'signed' type.  */
7085
1.57k
    case MVE_VBIC_IMM:
7086
1.83k
    case MVE_VORR_IMM:
7087
4.44k
    case MVE_VMVN_IMM:
7088
7.39k
    case MVE_VMOV_IMM_TO_VEC:
7089
7.39k
      printU = 1;
7090
7.39k
      break;
7091
7.39k
    }
7092
7.39k
  switch (size)
7093
7.39k
    {
7094
200
    case 8:
7095
200
      func (stream, dis_style_immediate, "#%ld", value);
7096
200
      func (stream, dis_style_comment_start, "\t@ 0x%.2lx", value);
7097
200
      break;
7098
7099
1.66k
    case 16:
7100
1.66k
      func (stream, dis_style_immediate, printU ? "#%lu" : "#%ld", value);
7101
1.66k
      func (stream, dis_style_comment_start, "\t@ 0x%.4lx", value);
7102
1.66k
      break;
7103
7104
4.97k
    case 32:
7105
4.97k
      if (isfloat)
7106
201
  {
7107
201
    unsigned char valbytes[4];
7108
201
    double fvalue;
7109
7110
    /* Do this a byte at a time so we don't have to
7111
       worry about the host's endianness.  */
7112
201
    valbytes[0] = value & 0xff;
7113
201
    valbytes[1] = (value >> 8) & 0xff;
7114
201
    valbytes[2] = (value >> 16) & 0xff;
7115
201
    valbytes[3] = (value >> 24) & 0xff;
7116
7117
201
    floatformat_to_double
7118
201
      (& floatformat_ieee_single_little, valbytes,
7119
201
       & fvalue);
7120
7121
201
    func (stream, dis_style_immediate, "#%.7g", fvalue);
7122
201
    func (stream, dis_style_comment_start, "\t@ 0x%.8lx", value);
7123
201
  }
7124
4.77k
      else
7125
4.77k
  {
7126
4.77k
    func (stream, dis_style_immediate,
7127
4.77k
    printU ? "#%lu" : "#%ld",
7128
4.77k
    (long) (((value & 0x80000000L) != 0)
7129
4.77k
      && !printU
7130
4.77k
      ? value | ~0xffffffffL : value));
7131
4.77k
    func (stream, dis_style_comment_start, "\t@ 0x%.8lx", value);
7132
4.77k
  }
7133
4.97k
      break;
7134
7135
561
    case 64:
7136
561
      func (stream, dis_style_immediate, "#0x%.8lx%.8lx", hival, value);
7137
561
      break;
7138
7139
0
    default:
7140
0
      abort ();
7141
7.39k
    }
7142
7143
7.39k
}
7144
7145
static void
7146
print_mve_undefined (struct disassemble_info *info,
7147
         enum mve_undefined undefined_code)
7148
14.0k
{
7149
14.0k
  void *stream = info->stream;
7150
14.0k
  fprintf_styled_ftype func = info->fprintf_styled_func;
7151
  /* Initialize REASON to avoid compiler warning about uninitialized
7152
     usage, though such usage should be impossible.  */
7153
14.0k
  const char *reason = "??";
7154
7155
14.0k
  switch (undefined_code)
7156
14.0k
    {
7157
595
    case UNDEF_SIZE:
7158
595
      reason = "illegal size";
7159
595
      break;
7160
7161
1.82k
    case UNDEF_SIZE_0:
7162
1.82k
      reason = "size equals zero";
7163
1.82k
      break;
7164
7165
547
    case UNDEF_SIZE_2:
7166
547
      reason = "size equals two";
7167
547
      break;
7168
7169
4.01k
    case UNDEF_SIZE_3:
7170
4.01k
      reason = "size equals three";
7171
4.01k
      break;
7172
7173
994
    case UNDEF_SIZE_LE_1:
7174
994
      reason = "size <= 1";
7175
994
      break;
7176
7177
199
    case UNDEF_SIZE_NOT_0:
7178
199
      reason = "size not equal to 0";
7179
199
      break;
7180
7181
742
    case UNDEF_SIZE_NOT_2:
7182
742
      reason = "size not equal to 2";
7183
742
      break;
7184
7185
0
    case UNDEF_SIZE_NOT_3:
7186
0
      reason = "size not equal to 3";
7187
0
      break;
7188
7189
226
    case UNDEF_NOT_UNS_SIZE_0:
7190
226
      reason = "not unsigned and size = zero";
7191
226
      break;
7192
7193
432
    case UNDEF_NOT_UNS_SIZE_1:
7194
432
      reason = "not unsigned and size = one";
7195
432
      break;
7196
7197
197
    case UNDEF_NOT_UNSIGNED:
7198
197
      reason = "not unsigned";
7199
197
      break;
7200
7201
381
    case UNDEF_VCVT_IMM6:
7202
381
      reason = "invalid imm6";
7203
381
      break;
7204
7205
977
    case UNDEF_VCVT_FSI_IMM6:
7206
977
      reason = "fsi = 0 and invalid imm6";
7207
977
      break;
7208
7209
1.20k
    case UNDEF_BAD_OP1_OP2:
7210
1.20k
      reason = "bad size with op2 = 2 and op1 = 0 or 1";
7211
1.20k
      break;
7212
7213
651
    case UNDEF_BAD_U_OP1_OP2:
7214
651
      reason = "unsigned with op2 = 0 and op1 = 0 or 1";
7215
651
      break;
7216
7217
0
    case UNDEF_OP_0_BAD_CMODE:
7218
0
      reason = "op field equal 0 and bad cmode";
7219
0
      break;
7220
7221
644
    case UNDEF_XCHG_UNS:
7222
644
      reason = "exchange and unsigned together";
7223
644
      break;
7224
7225
393
    case UNDEF_NONE:
7226
393
      reason = "";
7227
393
      break;
7228
14.0k
    }
7229
7230
14.0k
  func (stream, dis_style_text, "\t\tundefined instruction: %s", reason);
7231
14.0k
}
7232
7233
static void
7234
print_mve_unpredictable (struct disassemble_info *info,
7235
       enum mve_unpredictable unpredict_code)
7236
25.5k
{
7237
25.5k
  void *stream = info->stream;
7238
25.5k
  fprintf_styled_ftype func = info->fprintf_styled_func;
7239
  /* Initialize REASON to avoid compiler warning about uninitialized
7240
     usage, though such usage should be impossible.  */
7241
25.5k
  const char *reason = "??";
7242
7243
25.5k
  switch (unpredict_code)
7244
25.5k
    {
7245
1.67k
    case UNPRED_IT_BLOCK:
7246
1.67k
      reason = "mve instruction in it block";
7247
1.67k
      break;
7248
7249
349
    case UNPRED_FCA_0_FCB_1:
7250
349
      reason = "condition bits, fca = 0 and fcb = 1";
7251
349
      break;
7252
7253
8.25k
    case UNPRED_R13:
7254
8.25k
      reason = "use of r13 (sp)";
7255
8.25k
      break;
7256
7257
8.41k
    case UNPRED_R15:
7258
8.41k
      reason = "use of r15 (pc)";
7259
8.41k
      break;
7260
7261
431
    case UNPRED_Q_GT_4:
7262
431
      reason = "start register block > r4";
7263
431
      break;
7264
7265
255
    case UNPRED_Q_GT_6:
7266
255
      reason = "start register block > r6";
7267
255
      break;
7268
7269
549
    case UNPRED_R13_AND_WB:
7270
549
      reason = "use of r13 and write back";
7271
549
      break;
7272
7273
1.20k
    case UNPRED_Q_REGS_EQUAL:
7274
1.20k
      reason = "same vector register used for destination and other operand";
7275
1.20k
      break;
7276
7277
523
    case UNPRED_OS:
7278
523
      reason = "use of offset scaled";
7279
523
      break;
7280
7281
196
    case UNPRED_GP_REGS_EQUAL:
7282
196
      reason = "same general-purpose register used for both operands";
7283
196
      break;
7284
7285
1.43k
    case UNPRED_Q_REGS_EQ_AND_SIZE_1:
7286
1.43k
      reason = "use of identical q registers and size = 1";
7287
1.43k
      break;
7288
7289
690
    case UNPRED_Q_REGS_EQ_AND_SIZE_2:
7290
690
      reason = "use of identical q registers and size = 1";
7291
690
      break;
7292
7293
1.59k
    case UNPRED_NONE:
7294
1.59k
      reason = "";
7295
1.59k
      break;
7296
25.5k
    }
7297
7298
25.5k
  func (stream, dis_style_comment_start, "%s: %s",
7299
25.5k
  UNPREDICTABLE_INSTRUCTION, reason);
7300
25.5k
}
7301
7302
/* Print register block operand for mve vld2/vld4/vst2/vld4.  */
7303
7304
static void
7305
print_mve_register_blocks (struct disassemble_info *info,
7306
         unsigned long given,
7307
         enum mve_instructions matched_insn)
7308
2.23k
{
7309
2.23k
  void *stream = info->stream;
7310
2.23k
  fprintf_styled_ftype func = info->fprintf_styled_func;
7311
7312
2.23k
  unsigned long q_reg_start = arm_decode_field_multiple (given,
7313
2.23k
               13, 15,
7314
2.23k
               22, 22);
7315
2.23k
  switch (matched_insn)
7316
2.23k
    {
7317
348
    case MVE_VLD2:
7318
1.15k
    case MVE_VST2:
7319
1.15k
      if (q_reg_start <= 6)
7320
366
  {
7321
366
    func (stream, dis_style_text, "{");
7322
366
    func (stream, dis_style_register, "q%ld", q_reg_start);
7323
366
    func (stream, dis_style_text, ", ");
7324
366
    func (stream, dis_style_register, "q%ld", q_reg_start + 1);
7325
366
    func (stream, dis_style_text, "}");
7326
366
  }
7327
791
      else
7328
791
  func (stream, dis_style_text, "<illegal reg q%ld>", q_reg_start);
7329
1.15k
      break;
7330
7331
646
    case MVE_VLD4:
7332
1.07k
    case MVE_VST4:
7333
1.07k
      if (q_reg_start <= 4)
7334
213
  {
7335
213
    func (stream, dis_style_text, "{");
7336
213
    func (stream, dis_style_register, "q%ld", q_reg_start);
7337
213
    func (stream, dis_style_text, ", ");
7338
213
    func (stream, dis_style_register, "q%ld", q_reg_start + 1);
7339
213
    func (stream, dis_style_text, ", ");
7340
213
    func (stream, dis_style_register, "q%ld", q_reg_start + 2);
7341
213
    func (stream, dis_style_text, ", ");
7342
213
    func (stream, dis_style_register, "q%ld", q_reg_start + 3);
7343
213
    func (stream, dis_style_text, "}");
7344
213
  }
7345
866
      else
7346
866
  func (stream, dis_style_text, "<illegal reg q%ld>", q_reg_start);
7347
1.07k
      break;
7348
7349
0
    default:
7350
0
      break;
7351
2.23k
    }
7352
2.23k
}
7353
7354
static void
7355
print_mve_rounding_mode (struct disassemble_info *info,
7356
       unsigned long given,
7357
       enum mve_instructions matched_insn)
7358
3.27k
{
7359
3.27k
  void *stream = info->stream;
7360
3.27k
  fprintf_styled_ftype func = info->fprintf_styled_func;
7361
7362
3.27k
  switch (matched_insn)
7363
3.27k
    {
7364
1.79k
    case MVE_VCVT_FROM_FP_TO_INT:
7365
1.79k
      {
7366
1.79k
  switch (arm_decode_field (given, 8, 9))
7367
1.79k
    {
7368
897
    case 0:
7369
897
      func (stream, dis_style_mnemonic, "a");
7370
897
      break;
7371
7372
466
    case 1:
7373
466
      func (stream, dis_style_mnemonic, "n");
7374
466
      break;
7375
7376
224
    case 2:
7377
224
      func (stream, dis_style_mnemonic, "p");
7378
224
      break;
7379
7380
210
    case 3:
7381
210
      func (stream, dis_style_mnemonic, "m");
7382
210
      break;
7383
7384
0
    default:
7385
0
      break;
7386
1.79k
    }
7387
1.79k
      }
7388
1.79k
      break;
7389
7390
1.79k
    case MVE_VRINT_FP:
7391
1.47k
      {
7392
1.47k
  switch (arm_decode_field (given, 7, 9))
7393
1.47k
    {
7394
245
    case 0:
7395
245
      func (stream, dis_style_mnemonic, "n");
7396
245
      break;
7397
7398
195
    case 1:
7399
195
      func (stream, dis_style_mnemonic, "x");
7400
195
      break;
7401
7402
219
    case 2:
7403
219
      func (stream, dis_style_mnemonic, "a");
7404
219
      break;
7405
7406
205
    case 3:
7407
205
      func (stream, dis_style_mnemonic, "z");
7408
205
      break;
7409
7410
211
    case 5:
7411
211
      func (stream, dis_style_mnemonic, "m");
7412
211
      break;
7413
7414
204
    case 7:
7415
204
      func (stream, dis_style_mnemonic, "p");
7416
7417
205
    case 4:
7418
400
    case 6:
7419
400
    default:
7420
400
      break;
7421
1.47k
    }
7422
1.47k
      }
7423
1.47k
      break;
7424
7425
1.47k
    default:
7426
0
      break;
7427
3.27k
    }
7428
3.27k
}
7429
7430
static void
7431
print_mve_vcvt_size (struct disassemble_info *info,
7432
         unsigned long given,
7433
         enum mve_instructions matched_insn)
7434
7.42k
{
7435
7.42k
  unsigned long mode = 0;
7436
7.42k
  void *stream = info->stream;
7437
7.42k
  fprintf_styled_ftype func = info->fprintf_styled_func;
7438
7439
7.42k
  switch (matched_insn)
7440
7.42k
    {
7441
3.06k
    case MVE_VCVT_FP_FIX_VEC:
7442
3.06k
      {
7443
3.06k
  mode = (((given & 0x200) >> 7)
7444
3.06k
    | ((given & 0x10000000) >> 27)
7445
3.06k
    | ((given & 0x100) >> 8));
7446
7447
3.06k
  switch (mode)
7448
3.06k
    {
7449
268
    case 0:
7450
268
      func (stream, dis_style_mnemonic, "f16.s16");
7451
268
      break;
7452
7453
797
    case 1:
7454
797
      func (stream, dis_style_mnemonic, "s16.f16");
7455
797
      break;
7456
7457
207
    case 2:
7458
207
      func (stream, dis_style_mnemonic, "f16.u16");
7459
207
      break;
7460
7461
465
    case 3:
7462
465
      func (stream, dis_style_mnemonic, "u16.f16");
7463
465
      break;
7464
7465
234
    case 4:
7466
234
      func (stream, dis_style_mnemonic, "f32.s32");
7467
234
      break;
7468
7469
612
    case 5:
7470
612
      func (stream, dis_style_mnemonic, "s32.f32");
7471
612
      break;
7472
7473
210
    case 6:
7474
210
      func (stream, dis_style_mnemonic, "f32.u32");
7475
210
      break;
7476
7477
274
    case 7:
7478
274
      func (stream, dis_style_mnemonic, "u32.f32");
7479
274
      break;
7480
7481
0
    default:
7482
0
      break;
7483
3.06k
    }
7484
3.06k
  break;
7485
3.06k
      }
7486
3.06k
    case MVE_VCVT_BETWEEN_FP_INT:
7487
2.14k
      {
7488
2.14k
  unsigned long size = arm_decode_field (given, 18, 19);
7489
2.14k
  unsigned long op = arm_decode_field (given, 7, 8);
7490
7491
2.14k
  if (size == 1)
7492
794
    {
7493
794
      switch (op)
7494
794
        {
7495
207
        case 0:
7496
207
    func (stream, dis_style_mnemonic, "f16.s16");
7497
207
    break;
7498
7499
196
        case 1:
7500
196
    func (stream, dis_style_mnemonic, "f16.u16");
7501
196
    break;
7502
7503
194
        case 2:
7504
194
    func (stream, dis_style_mnemonic, "s16.f16");
7505
194
    break;
7506
7507
197
        case 3:
7508
197
    func (stream, dis_style_mnemonic, "u16.f16");
7509
197
    break;
7510
7511
0
        default:
7512
0
    break;
7513
794
        }
7514
794
    }
7515
1.34k
  else if (size == 2)
7516
1.02k
    {
7517
1.02k
      switch (op)
7518
1.02k
        {
7519
196
        case 0:
7520
196
    func (stream, dis_style_mnemonic, "f32.s32");
7521
196
    break;
7522
7523
270
        case 1:
7524
270
    func (stream, dis_style_mnemonic, "f32.u32");
7525
270
    break;
7526
7527
353
        case 2:
7528
353
    func (stream, dis_style_mnemonic, "s32.f32");
7529
353
    break;
7530
7531
210
        case 3:
7532
210
    func (stream, dis_style_mnemonic, "u32.f32");
7533
210
    break;
7534
1.02k
        }
7535
1.02k
    }
7536
2.14k
      }
7537
2.14k
      break;
7538
7539
2.14k
    case MVE_VCVT_FP_HALF_FP:
7540
414
      {
7541
414
  unsigned long op = arm_decode_field (given, 28, 28);
7542
414
  if (op == 0)
7543
213
    func (stream, dis_style_mnemonic, "f16.f32");
7544
201
  else if (op == 1)
7545
201
    func (stream, dis_style_mnemonic, "f32.f16");
7546
414
      }
7547
414
      break;
7548
7549
1.79k
    case MVE_VCVT_FROM_FP_TO_INT:
7550
1.79k
      {
7551
1.79k
  unsigned long size = arm_decode_field_multiple (given, 7, 7, 18, 19);
7552
7553
1.79k
  switch (size)
7554
1.79k
    {
7555
216
    case 2:
7556
216
      func (stream, dis_style_mnemonic, "s16.f16");
7557
216
      break;
7558
7559
207
    case 3:
7560
207
      func (stream, dis_style_mnemonic, "u16.f16");
7561
207
      break;
7562
7563
217
    case 4:
7564
217
      func (stream, dis_style_mnemonic, "s32.f32");
7565
217
      break;
7566
7567
201
    case 5:
7568
201
      func (stream, dis_style_mnemonic, "u32.f32");
7569
201
      break;
7570
7571
956
    default:
7572
956
      break;
7573
1.79k
    }
7574
1.79k
      }
7575
1.79k
      break;
7576
7577
1.79k
    default:
7578
0
      break;
7579
7.42k
    }
7580
7.42k
}
7581
7582
static void
7583
print_mve_rotate (struct disassemble_info *info, unsigned long rot,
7584
      unsigned long rot_width)
7585
3.83k
{
7586
3.83k
  void *stream = info->stream;
7587
3.83k
  fprintf_styled_ftype func = info->fprintf_styled_func;
7588
7589
3.83k
  if (rot_width == 1)
7590
1.91k
    {
7591
1.91k
      switch (rot)
7592
1.91k
  {
7593
1.39k
  case 0:
7594
1.39k
    func (stream, dis_style_immediate, "90");
7595
1.39k
    break;
7596
528
  case 1:
7597
528
    func (stream, dis_style_immediate, "270");
7598
528
    break;
7599
0
  default:
7600
0
    break;
7601
1.91k
  }
7602
1.91k
    }
7603
1.91k
  else if (rot_width == 2)
7604
1.91k
    {
7605
1.91k
      switch (rot)
7606
1.91k
  {
7607
275
  case 0:
7608
275
    func (stream, dis_style_immediate, "0");
7609
275
    break;
7610
976
  case 1:
7611
976
    func (stream, dis_style_immediate, "90");
7612
976
    break;
7613
253
  case 2:
7614
253
    func (stream, dis_style_immediate, "180");
7615
253
    break;
7616
411
  case 3:
7617
411
    func (stream, dis_style_immediate, "270");
7618
411
    break;
7619
0
  default:
7620
0
    break;
7621
1.91k
  }
7622
1.91k
    }
7623
3.83k
}
7624
7625
static void
7626
print_instruction_predicate (struct disassemble_info *info)
7627
85.3k
{
7628
85.3k
  void *stream = info->stream;
7629
85.3k
  fprintf_styled_ftype func = info->fprintf_styled_func;
7630
7631
85.3k
  if (vpt_block_state.next_pred_state == PRED_THEN)
7632
1.84k
    func (stream, dis_style_mnemonic, "t");
7633
83.5k
  else if (vpt_block_state.next_pred_state == PRED_ELSE)
7634
702
    func (stream, dis_style_mnemonic, "e");
7635
85.3k
}
7636
7637
static void
7638
print_mve_size (struct disassemble_info *info,
7639
    unsigned long size,
7640
    enum mve_instructions matched_insn)
7641
85.3k
{
7642
85.3k
  void *stream = info->stream;
7643
85.3k
  fprintf_styled_ftype func = info->fprintf_styled_func;
7644
7645
85.3k
  switch (matched_insn)
7646
85.3k
    {
7647
196
    case MVE_VABAV:
7648
434
    case MVE_VABD_VEC:
7649
636
    case MVE_VABS_FP:
7650
1.02k
    case MVE_VABS_VEC:
7651
1.23k
    case MVE_VADD_VEC_T1:
7652
1.45k
    case MVE_VADD_VEC_T2:
7653
1.70k
    case MVE_VADDV:
7654
3.39k
    case MVE_VBRSR:
7655
3.87k
    case MVE_VCADD_VEC:
7656
4.08k
    case MVE_VCLS:
7657
4.30k
    case MVE_VCLZ:
7658
4.56k
    case MVE_VCMP_VEC_T1:
7659
4.86k
    case MVE_VCMP_VEC_T2:
7660
5.17k
    case MVE_VCMP_VEC_T3:
7661
5.71k
    case MVE_VCMP_VEC_T4:
7662
5.95k
    case MVE_VCMP_VEC_T5:
7663
6.19k
    case MVE_VCMP_VEC_T6:
7664
6.77k
    case MVE_VCTP:
7665
7.57k
    case MVE_VDDUP:
7666
8.12k
    case MVE_VDWDUP:
7667
8.63k
    case MVE_VHADD_T1:
7668
8.94k
    case MVE_VHADD_T2:
7669
9.48k
    case MVE_VHCADD:
7670
9.69k
    case MVE_VHSUB_T1:
7671
9.95k
    case MVE_VHSUB_T2:
7672
10.3k
    case MVE_VIDUP:
7673
10.8k
    case MVE_VIWDUP:
7674
11.2k
    case MVE_VLD2:
7675
11.8k
    case MVE_VLD4:
7676
12.8k
    case MVE_VLDRB_GATHER_T1:
7677
14.1k
    case MVE_VLDRH_GATHER_T2:
7678
14.1k
    case MVE_VLDRW_GATHER_T3:
7679
14.1k
    case MVE_VLDRD_GATHER_T4:
7680
14.5k
    case MVE_VLDRB_T1:
7681
15.6k
    case MVE_VLDRH_T2:
7682
15.9k
    case MVE_VMAX:
7683
16.1k
    case MVE_VMAXA:
7684
16.3k
    case MVE_VMAXV:
7685
16.7k
    case MVE_VMAXAV:
7686
17.0k
    case MVE_VMIN:
7687
17.2k
    case MVE_VMINA:
7688
17.4k
    case MVE_VMINV:
7689
17.6k
    case MVE_VMINAV:
7690
17.9k
    case MVE_VMLA:
7691
18.2k
    case MVE_VMLAS:
7692
18.4k
    case MVE_VMUL_VEC_T1:
7693
18.7k
    case MVE_VMUL_VEC_T2:
7694
19.1k
    case MVE_VMULH:
7695
19.6k
    case MVE_VRMULH:
7696
20.8k
    case MVE_VMULL_INT:
7697
21.0k
    case MVE_VNEG_FP:
7698
21.2k
    case MVE_VNEG_VEC:
7699
21.8k
    case MVE_VPT_VEC_T1:
7700
22.6k
    case MVE_VPT_VEC_T2:
7701
24.9k
    case MVE_VPT_VEC_T3:
7702
26.4k
    case MVE_VPT_VEC_T4:
7703
27.3k
    case MVE_VPT_VEC_T5:
7704
29.0k
    case MVE_VPT_VEC_T6:
7705
29.2k
    case MVE_VQABS:
7706
29.8k
    case MVE_VQADD_T1:
7707
30.2k
    case MVE_VQADD_T2:
7708
30.5k
    case MVE_VQDMLADH:
7709
30.8k
    case MVE_VQRDMLADH:
7710
31.6k
    case MVE_VQDMLAH:
7711
31.8k
    case MVE_VQRDMLAH:
7712
32.0k
    case MVE_VQDMLASH:
7713
32.2k
    case MVE_VQRDMLASH:
7714
32.6k
    case MVE_VQDMLSDH:
7715
32.9k
    case MVE_VQRDMLSDH:
7716
33.1k
    case MVE_VQDMULH_T1:
7717
33.3k
    case MVE_VQRDMULH_T2:
7718
33.8k
    case MVE_VQDMULH_T3:
7719
34.2k
    case MVE_VQRDMULH_T4:
7720
34.6k
    case MVE_VQNEG:
7721
34.8k
    case MVE_VQRSHL_T1:
7722
35.0k
    case MVE_VQRSHL_T2:
7723
35.2k
    case MVE_VQSHL_T1:
7724
35.4k
    case MVE_VQSHL_T4:
7725
35.7k
    case MVE_VQSUB_T1:
7726
36.8k
    case MVE_VQSUB_T2:
7727
37.3k
    case MVE_VREV32:
7728
37.9k
    case MVE_VREV64:
7729
38.1k
    case MVE_VRHADD:
7730
39.6k
    case MVE_VRINT_FP:
7731
39.8k
    case MVE_VRSHL_T1:
7732
40.0k
    case MVE_VRSHL_T2:
7733
40.2k
    case MVE_VSHL_T2:
7734
40.4k
    case MVE_VSHL_T3:
7735
40.8k
    case MVE_VSHLL_T2:
7736
41.7k
    case MVE_VST2:
7737
42.1k
    case MVE_VST4:
7738
43.2k
    case MVE_VSTRB_SCATTER_T1:
7739
44.0k
    case MVE_VSTRH_SCATTER_T2:
7740
45.0k
    case MVE_VSTRW_SCATTER_T3:
7741
45.8k
    case MVE_VSTRB_T1:
7742
47.3k
    case MVE_VSTRH_T2:
7743
47.5k
    case MVE_VSUB_VEC_T1:
7744
47.8k
    case MVE_VSUB_VEC_T2:
7745
47.8k
      if (size <= 3)
7746
47.8k
  func (stream, dis_style_mnemonic, "%s", mve_vec_sizename[size]);
7747
0
      else
7748
0
  func (stream, dis_style_text, "<undef size>");
7749
47.8k
      break;
7750
7751
212
    case MVE_VABD_FP:
7752
421
    case MVE_VADD_FP_T1:
7753
690
    case MVE_VADD_FP_T2:
7754
1.22k
    case MVE_VSUB_FP_T1:
7755
1.53k
    case MVE_VSUB_FP_T2:
7756
1.94k
    case MVE_VCMP_FP_T1:
7757
2.16k
    case MVE_VCMP_FP_T2:
7758
2.68k
    case MVE_VFMA_FP_SCALAR:
7759
2.95k
    case MVE_VFMA_FP:
7760
3.17k
    case MVE_VFMS_FP:
7761
3.49k
    case MVE_VFMAS_FP_SCALAR:
7762
3.74k
    case MVE_VMAXNM_FP:
7763
3.96k
    case MVE_VMAXNMA_FP:
7764
4.16k
    case MVE_VMAXNMV_FP:
7765
4.38k
    case MVE_VMAXNMAV_FP:
7766
4.60k
    case MVE_VMINNM_FP:
7767
4.81k
    case MVE_VMINNMA_FP:
7768
5.07k
    case MVE_VMINNMV_FP:
7769
5.26k
    case MVE_VMINNMAV_FP:
7770
5.58k
    case MVE_VMUL_FP_T1:
7771
5.95k
    case MVE_VMUL_FP_T2:
7772
6.77k
    case MVE_VPT_FP_T1:
7773
7.38k
    case MVE_VPT_FP_T2:
7774
7.38k
      if (size == 0)
7775
3.91k
  func (stream, dis_style_mnemonic, "32");
7776
3.46k
      else if (size == 1)
7777
3.46k
  func (stream, dis_style_mnemonic, "16");
7778
7.38k
      break;
7779
7780
894
    case MVE_VCADD_FP:
7781
1.78k
    case MVE_VCMLA_FP:
7782
2.80k
    case MVE_VCMUL_FP:
7783
3.20k
    case MVE_VMLADAV_T1:
7784
4.43k
    case MVE_VMLALDAV:
7785
4.65k
    case MVE_VMLSDAV_T1:
7786
5.41k
    case MVE_VMLSLDAV:
7787
5.72k
    case MVE_VMOVN:
7788
5.99k
    case MVE_VQDMULL_T1:
7789
7.50k
    case MVE_VQDMULL_T2:
7790
7.72k
    case MVE_VQMOVN:
7791
7.99k
    case MVE_VQMOVUN:
7792
7.99k
      if (size == 0)
7793
4.14k
  func (stream, dis_style_mnemonic, "16");
7794
3.85k
      else if (size == 1)
7795
3.27k
  func (stream, dis_style_mnemonic, "32");
7796
7.99k
      break;
7797
7798
400
    case MVE_VMOVL:
7799
400
      if (size == 1)
7800
202
  func (stream, dis_style_mnemonic, "8");
7801
198
      else if (size == 2)
7802
198
  func (stream, dis_style_mnemonic, "16");
7803
400
      break;
7804
7805
1.02k
    case MVE_VDUP:
7806
1.02k
      switch (size)
7807
1.02k
  {
7808
195
  case 0:
7809
195
    func (stream, dis_style_mnemonic, "32");
7810
195
    break;
7811
203
  case 1:
7812
203
    func (stream, dis_style_mnemonic, "16");
7813
203
    break;
7814
423
  case 2:
7815
423
    func (stream, dis_style_mnemonic, "8");
7816
423
    break;
7817
202
  default:
7818
202
    break;
7819
1.02k
  }
7820
1.02k
      break;
7821
7822
2.02k
    case MVE_VMOV_GP_TO_VEC_LANE:
7823
6.24k
    case MVE_VMOV_VEC_LANE_TO_GP:
7824
6.24k
      switch (size)
7825
6.24k
  {
7826
1.64k
  case 0: case 4:
7827
1.64k
    func (stream, dis_style_mnemonic, "32");
7828
1.64k
    break;
7829
7830
449
  case 1: case 3:
7831
1.01k
  case 5: case 7:
7832
1.01k
    func (stream, dis_style_mnemonic, "16");
7833
1.01k
    break;
7834
7835
1.32k
  case 8: case 9: case 10: case 11:
7836
2.38k
  case 12: case 13: case 14: case 15:
7837
2.38k
    func (stream, dis_style_mnemonic, "8");
7838
2.38k
    break;
7839
7840
1.20k
  default:
7841
1.20k
    break;
7842
6.24k
  }
7843
6.24k
      break;
7844
7845
6.24k
    case MVE_VMOV_IMM_TO_VEC:
7846
2.95k
      switch (size)
7847
2.95k
  {
7848
964
  case 0: case 4: case 8:
7849
1.57k
  case 12: case 24: case 26:
7850
1.57k
    func (stream, dis_style_mnemonic, "i32");
7851
1.57k
    break;
7852
420
  case 16: case 20:
7853
420
    func (stream, dis_style_mnemonic, "i16");
7854
420
    break;
7855
200
  case 28:
7856
200
    func (stream, dis_style_mnemonic, "i8");
7857
200
    break;
7858
561
  case 29:
7859
561
    func (stream, dis_style_mnemonic, "i64");
7860
561
    break;
7861
201
  case 30:
7862
201
    func (stream, dis_style_mnemonic, "f32");
7863
201
    break;
7864
0
  default:
7865
0
    break;
7866
2.95k
  }
7867
2.95k
      break;
7868
7869
2.95k
    case MVE_VMULL_POLY:
7870
474
      if (size == 0)
7871
259
  func (stream, dis_style_mnemonic, "p8");
7872
215
      else if (size == 1)
7873
215
  func (stream, dis_style_mnemonic, "p16");
7874
474
      break;
7875
7876
2.60k
    case MVE_VMVN_IMM:
7877
2.60k
      switch (size)
7878
2.60k
  {
7879
808
  case 0: case 2: case 4:
7880
2.20k
  case 6: case 12: case 13:
7881
2.20k
    func (stream, dis_style_mnemonic, "32");
7882
2.20k
    break;
7883
7884
407
  case 8: case 10:
7885
407
    func (stream, dis_style_mnemonic, "16");
7886
407
    break;
7887
7888
0
  default:
7889
0
    break;
7890
2.60k
  }
7891
2.60k
      break;
7892
7893
2.60k
    case MVE_VBIC_IMM:
7894
1.83k
    case MVE_VORR_IMM:
7895
1.83k
      switch (size)
7896
1.83k
  {
7897
522
  case 1: case 3:
7898
1.00k
  case 5: case 7:
7899
1.00k
    func (stream, dis_style_mnemonic, "32");
7900
1.00k
    break;
7901
7902
835
  case 9: case 11:
7903
835
    func (stream, dis_style_mnemonic, "16");
7904
835
    break;
7905
7906
0
  default:
7907
0
    break;
7908
1.83k
  }
7909
1.83k
      break;
7910
7911
1.83k
    case MVE_VQSHRN:
7912
1.02k
    case MVE_VQSHRUN:
7913
1.25k
    case MVE_VQRSHRN:
7914
1.73k
    case MVE_VQRSHRUN:
7915
2.03k
    case MVE_VRSHRN:
7916
2.67k
    case MVE_VSHRN:
7917
2.67k
      {
7918
2.67k
  switch (size)
7919
2.67k
  {
7920
1.34k
  case 1:
7921
1.34k
    func (stream, dis_style_mnemonic, "16");
7922
1.34k
    break;
7923
7924
678
  case 2: case 3:
7925
678
    func (stream, dis_style_mnemonic, "32");
7926
678
    break;
7927
7928
659
  default:
7929
659
    break;
7930
2.67k
  }
7931
2.67k
      }
7932
2.67k
      break;
7933
7934
2.67k
    case MVE_VQSHL_T2:
7935
887
    case MVE_VQSHLU_T3:
7936
1.24k
    case MVE_VRSHR:
7937
1.45k
    case MVE_VSHL_T1:
7938
2.59k
    case MVE_VSHLL_T1:
7939
3.19k
    case MVE_VSHR:
7940
3.51k
    case MVE_VSLI:
7941
3.91k
    case MVE_VSRI:
7942
3.91k
      {
7943
3.91k
  switch (size)
7944
3.91k
  {
7945
443
  case 1:
7946
443
    func (stream, dis_style_mnemonic, "8");
7947
443
    break;
7948
7949
1.11k
  case 2: case 3:
7950
1.11k
    func (stream, dis_style_mnemonic, "16");
7951
1.11k
    break;
7952
7953
2.09k
  case 4: case 5: case 6: case 7:
7954
2.09k
    func (stream, dis_style_mnemonic, "32");
7955
2.09k
    break;
7956
7957
270
  default:
7958
270
    break;
7959
3.91k
  }
7960
3.91k
      }
7961
3.91k
      break;
7962
7963
3.91k
    default:
7964
0
      break;
7965
85.3k
    }
7966
85.3k
}
7967
7968
static void
7969
print_mve_shift_n (struct disassemble_info *info, long given,
7970
       enum mve_instructions matched_insn)
7971
4.86k
{
7972
4.86k
  void *stream = info->stream;
7973
4.86k
  fprintf_styled_ftype func = info->fprintf_styled_func;
7974
7975
4.86k
  int startAt0
7976
4.86k
    = matched_insn == MVE_VQSHL_T2
7977
4.86k
      || matched_insn == MVE_VQSHLU_T3
7978
4.86k
      || matched_insn == MVE_VSHL_T1
7979
4.86k
      || matched_insn == MVE_VSHLL_T1
7980
4.86k
      || matched_insn == MVE_VSLI;
7981
7982
4.86k
  unsigned imm6 = (given & 0x3f0000) >> 16;
7983
7984
4.86k
  if (matched_insn == MVE_VSHLL_T1)
7985
1.14k
    imm6 &= 0x1f;
7986
7987
4.86k
  unsigned shiftAmount = 0;
7988
4.86k
  if ((imm6 & 0x20) != 0)
7989
2.09k
    shiftAmount = startAt0 ? imm6 - 32 : 64 - imm6;
7990
2.77k
  else if ((imm6 & 0x10) != 0)
7991
1.38k
    shiftAmount = startAt0 ? imm6 - 16 : 32 - imm6;
7992
1.38k
  else if ((imm6 & 0x08) != 0)
7993
1.08k
    shiftAmount = startAt0 ? imm6 - 8 : 16 - imm6;
7994
306
  else
7995
306
    print_mve_undefined (info, UNDEF_SIZE_0);
7996
7997
4.86k
  func (stream, dis_style_immediate, "%u", shiftAmount);
7998
4.86k
}
7999
8000
static void
8001
print_vec_condition (struct disassemble_info *info, long given,
8002
         enum mve_instructions matched_insn)
8003
11.7k
{
8004
11.7k
  void *stream = info->stream;
8005
11.7k
  fprintf_styled_ftype func = info->fprintf_styled_func;
8006
11.7k
  long vec_cond = 0;
8007
8008
11.7k
  switch (matched_insn)
8009
11.7k
    {
8010
816
    case MVE_VPT_FP_T1:
8011
1.22k
    case MVE_VCMP_FP_T1:
8012
1.22k
      vec_cond = (((given & 0x1000) >> 10)
8013
1.22k
      | ((given & 1) << 1)
8014
1.22k
      | ((given & 0x0080) >> 7));
8015
1.22k
      func (stream, dis_style_sub_mnemonic, "%s", vec_condnames[vec_cond]);
8016
1.22k
      break;
8017
8018
611
    case MVE_VPT_FP_T2:
8019
829
    case MVE_VCMP_FP_T2:
8020
829
      vec_cond = (((given & 0x1000) >> 10)
8021
829
      | ((given & 0x0020) >> 4)
8022
829
      | ((given & 0x0080) >> 7));
8023
829
      func (stream, dis_style_sub_mnemonic, "%s", vec_condnames[vec_cond]);
8024
829
      break;
8025
8026
599
    case MVE_VPT_VEC_T1:
8027
859
    case MVE_VCMP_VEC_T1:
8028
859
      vec_cond = (given & 0x0080) >> 7;
8029
859
      func (stream, dis_style_sub_mnemonic, "%s", vec_condnames[vec_cond]);
8030
859
      break;
8031
8032
839
    case MVE_VPT_VEC_T2:
8033
1.13k
    case MVE_VCMP_VEC_T2:
8034
1.13k
      vec_cond = 2 | ((given & 0x0080) >> 7);
8035
1.13k
      func (stream, dis_style_sub_mnemonic, "%s", vec_condnames[vec_cond]);
8036
1.13k
      break;
8037
8038
2.25k
    case MVE_VPT_VEC_T3:
8039
2.56k
    case MVE_VCMP_VEC_T3:
8040
2.56k
      vec_cond = 4 | ((given & 1) << 1) | ((given & 0x0080) >> 7);
8041
2.56k
      func (stream, dis_style_sub_mnemonic, "%s", vec_condnames[vec_cond]);
8042
2.56k
      break;
8043
8044
1.52k
    case MVE_VPT_VEC_T4:
8045
2.06k
    case MVE_VCMP_VEC_T4:
8046
2.06k
      vec_cond = (given & 0x0080) >> 7;
8047
2.06k
      func (stream, dis_style_sub_mnemonic, "%s", vec_condnames[vec_cond]);
8048
2.06k
      break;
8049
8050
887
    case MVE_VPT_VEC_T5:
8051
1.12k
    case MVE_VCMP_VEC_T5:
8052
1.12k
      vec_cond = 2 | ((given & 0x0080) >> 7);
8053
1.12k
      func (stream, dis_style_sub_mnemonic, "%s", vec_condnames[vec_cond]);
8054
1.12k
      break;
8055
8056
1.73k
    case MVE_VPT_VEC_T6:
8057
1.97k
    case MVE_VCMP_VEC_T6:
8058
1.97k
      vec_cond = 4 | ((given & 0x0020) >> 4) | ((given & 0x0080) >> 7);
8059
1.97k
      func (stream, dis_style_sub_mnemonic, "%s", vec_condnames[vec_cond]);
8060
1.97k
      break;
8061
8062
0
    case MVE_NONE:
8063
0
    case MVE_VPST:
8064
0
    default:
8065
0
      break;
8066
11.7k
    }
8067
11.7k
}
8068
8069
1.00M
#define W_BIT 21
8070
164k
#define I_BIT 22
8071
1.69M
#define U_BIT 23
8072
1.27M
#define P_BIT 24
8073
8074
1.28M
#define WRITEBACK_BIT_SET (given & (1 << W_BIT))
8075
219k
#define IMMEDIATE_BIT_SET (given & (1 << I_BIT))
8076
1.95M
#define NEGATIVE_BIT_SET  ((given & (1 << U_BIT)) == 0)
8077
1.60M
#define PRE_BIT_SET   (given & (1 << P_BIT))
8078
8079
/* The assembler string for an instruction can include %{X:...%} patterns,
8080
   where the 'X' is one of the characters understood by this function.
8081
8082
   This function takes the X character, and returns a new style.  This new
8083
   style will be used by the caller to temporarily change the current base
8084
   style.  */
8085
8086
static enum disassembler_style
8087
decode_base_style (const char x)
8088
2.32M
{
8089
2.32M
  switch (x)
8090
2.32M
    {
8091
0
    case 'A': return dis_style_address;
8092
9.67k
    case 'B': return dis_style_sub_mnemonic;
8093
0
    case 'C': return dis_style_comment_start;
8094
0
    case 'D': return dis_style_assembler_directive;
8095
1.47M
    case 'I': return dis_style_immediate;
8096
0
    case 'M': return dis_style_mnemonic;
8097
0
    case 'O': return dis_style_address_offset;
8098
842k
    case 'R': return dis_style_register;
8099
0
    case 'S': return dis_style_symbol;
8100
0
    case 'T': return dis_style_text;
8101
0
    default:
8102
0
      abort ();
8103
2.32M
    }
8104
2.32M
}
8105
8106
/* Print one coprocessor instruction on INFO->STREAM.
8107
   Return TRUE if the instuction matched, FALSE if this is not a
8108
   recognised coprocessor instruction.  */
8109
8110
static bool
8111
print_insn_coprocessor_1 (const struct sopcode32 *opcodes,
8112
        bfd_vma pc,
8113
        struct disassemble_info *info,
8114
        long given,
8115
        bool thumb)
8116
8.46M
{
8117
8.46M
  const struct sopcode32 *insn;
8118
8.46M
  void *stream = info->stream;
8119
8.46M
  fprintf_styled_ftype func = info->fprintf_styled_func;
8120
8.46M
  unsigned long mask;
8121
8.46M
  unsigned long value = 0;
8122
8.46M
  int cond;
8123
8.46M
  int cp_num;
8124
8.46M
  struct arm_private_data *private_data = info->private_data;
8125
8.46M
  arm_feature_set allowed_arches = ARM_ARCH_NONE;
8126
8.46M
  arm_feature_set arm_ext_v8_1m_main =
8127
8.46M
    ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN);
8128
8.46M
  enum disassembler_style base_style = dis_style_mnemonic;
8129
8.46M
  enum disassembler_style old_base_style = base_style;
8130
8131
8.46M
  allowed_arches = private_data->features;
8132
8133
1.48G
  for (insn = opcodes; insn->assembler; insn++)
8134
1.47G
    {
8135
1.47G
      unsigned long u_reg = 16;
8136
1.47G
      bool is_unpredictable = false;
8137
1.47G
      signed long value_in_comment = 0;
8138
1.47G
      const char *c;
8139
8140
1.47G
      if (ARM_FEATURE_ZERO (insn->arch))
8141
8.75M
  switch (insn->value)
8142
8.75M
    {
8143
4.40M
    case SENTINEL_IWMMXT_START:
8144
4.40M
      if (info->mach != bfd_mach_arm_XScale
8145
4.40M
    && info->mach != bfd_mach_arm_iWMMXt
8146
4.40M
    && info->mach != bfd_mach_arm_iWMMXt2)
8147
4.32M
        do
8148
328M
    insn++;
8149
328M
        while ((! ARM_FEATURE_ZERO (insn->arch))
8150
328M
         && insn->value != SENTINEL_IWMMXT_END);
8151
4.40M
      continue;
8152
8153
69.5k
    case SENTINEL_IWMMXT_END:
8154
69.5k
      continue;
8155
8156
4.28M
    case SENTINEL_GENERIC_START:
8157
4.28M
      allowed_arches = private_data->features;
8158
4.28M
      continue;
8159
8160
0
    default:
8161
0
      abort ();
8162
8.75M
    }
8163
8164
1.47G
      mask = insn->mask;
8165
1.47G
      value = insn->value;
8166
1.47G
      cp_num = (given >> 8) & 0xf;
8167
8168
1.47G
      if (thumb)
8169
145M
  {
8170
    /* The high 4 bits are 0xe for Arm conditional instructions, and
8171
       0xe for arm unconditional instructions.  The rest of the
8172
       encoding is the same.  */
8173
145M
    mask |= 0xf0000000;
8174
145M
    value |= 0xe0000000;
8175
145M
    if (ifthen_state)
8176
5.88M
      cond = IFTHEN_COND;
8177
139M
    else
8178
139M
      cond = COND_UNCOND;
8179
145M
  }
8180
1.32G
      else
8181
1.32G
  {
8182
    /* Only match unconditional instuctions against unconditional
8183
       patterns.  */
8184
1.32G
    if ((given & 0xf0000000) == 0xf0000000)
8185
128M
      {
8186
128M
        mask |= 0xf0000000;
8187
128M
        cond = COND_UNCOND;
8188
128M
      }
8189
1.19G
    else
8190
1.19G
      {
8191
1.19G
        cond = (given >> 28) & 0xf;
8192
1.19G
        if (cond == 0xe)
8193
71.9M
    cond = COND_UNCOND;
8194
1.19G
      }
8195
1.32G
  }
8196
8197
1.47G
      if ((insn->isa == T32 && !thumb)
8198
1.47G
    || (insn->isa == ARM && thumb))
8199
7.85M
  continue;
8200
8201
1.46G
      if ((given & mask) != value)
8202
1.46G
  continue;
8203
8204
638k
      if (! ARM_CPU_HAS_FEATURE (insn->arch, allowed_arches))
8205
48.1k
  continue;
8206
8207
590k
      if (insn->value == 0xfe000010     /* mcr2  */
8208
590k
    || insn->value == 0xfe100010  /* mrc2  */
8209
590k
    || insn->value == 0xfc100000  /* ldc2  */
8210
590k
    || insn->value == 0xfc000000) /* stc2  */
8211
52.5k
  {
8212
52.5k
    if (cp_num == 9 || cp_num == 10 || cp_num == 11)
8213
7.34k
      is_unpredictable = true;
8214
8215
    /* Armv8.1-M Mainline FP & MVE instructions.  */
8216
52.5k
    if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
8217
52.5k
        && !ARM_CPU_IS_ANY (allowed_arches)
8218
52.5k
        && (cp_num == 8 || cp_num == 14 || cp_num == 15))
8219
9.36k
      continue;
8220
8221
52.5k
  }
8222
537k
      else if (insn->value == 0x0e000000     /* cdp  */
8223
537k
         || insn->value == 0xfe000000  /* cdp2  */
8224
537k
         || insn->value == 0x0e000010  /* mcr  */
8225
537k
         || insn->value == 0x0e100010  /* mrc  */
8226
537k
         || insn->value == 0x0c100000  /* ldc  */
8227
537k
         || insn->value == 0x0c000000) /* stc  */
8228
386k
  {
8229
    /* Floating-point instructions.  */
8230
386k
    if (cp_num == 9 || cp_num == 10 || cp_num == 11)
8231
32.4k
      continue;
8232
8233
    /* Armv8.1-M Mainline FP & MVE instructions.  */
8234
354k
    if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
8235
354k
        && !ARM_CPU_IS_ANY (allowed_arches)
8236
354k
        && (cp_num == 8 || cp_num == 14 || cp_num == 15))
8237
11.5k
      continue;
8238
354k
  }
8239
150k
      else if ((insn->value == 0xec100f80      /* vldr (system register) */
8240
150k
    || insn->value == 0xec000f80)  /* vstr (system register) */
8241
150k
         && arm_decode_field (given, 24, 24) == 0
8242
150k
         && arm_decode_field (given, 21, 21) == 0)
8243
  /* If the P and W bits are both 0 then these encodings match the MVE
8244
     VLDR and VSTR instructions, these are in a different table, so we
8245
     don't let it match here.  */
8246
2.42k
  continue;
8247
8248
13.6M
      for (c = insn->assembler; *c; c++)
8249
13.1M
  {
8250
13.1M
    if (*c == '%')
8251
5.75M
      {
8252
5.75M
        const char mod = *++c;
8253
8254
5.75M
        switch (mod)
8255
5.75M
    {
8256
1.45M
    case '{':
8257
1.45M
      ++c;
8258
1.45M
      if (*c == '\0')
8259
0
        abort ();
8260
1.45M
      old_base_style = base_style;
8261
1.45M
      base_style = decode_base_style (*c);
8262
1.45M
      ++c;
8263
1.45M
      if (*c != ':')
8264
0
        abort ();
8265
1.45M
      break;
8266
8267
1.45M
    case '}':
8268
1.45M
      base_style = old_base_style;
8269
1.45M
      break;
8270
8271
0
    case '%':
8272
0
      func (stream, base_style, "%%");
8273
0
      break;
8274
8275
300k
    case 'A':
8276
304k
    case 'K':
8277
304k
      {
8278
304k
        int rn = (given >> 16) & 0xf;
8279
304k
        bfd_vma offset = given & 0xff;
8280
8281
304k
        if (mod == 'K')
8282
4.53k
          offset = given & 0x7f;
8283
8284
304k
        func (stream, dis_style_text, "[");
8285
304k
        func (stream, dis_style_register, "%s",
8286
304k
        arm_regnames [(given >> 16) & 0xf]);
8287
8288
304k
        if (PRE_BIT_SET || WRITEBACK_BIT_SET)
8289
240k
          {
8290
      /* Not unindexed.  The offset is scaled.  */
8291
240k
      if (cp_num == 9)
8292
        /* vldr.16/vstr.16 will shift the address
8293
           left by 1 bit only.  */
8294
4.08k
        offset = offset * 2;
8295
236k
      else
8296
236k
        offset = offset * 4;
8297
8298
240k
      if (NEGATIVE_BIT_SET)
8299
121k
        offset = - offset;
8300
240k
      if (rn != 15)
8301
221k
        value_in_comment = offset;
8302
240k
          }
8303
8304
304k
        if (PRE_BIT_SET)
8305
160k
          {
8306
160k
      if (offset)
8307
144k
        {
8308
144k
          func (stream, dis_style_text, ", ");
8309
144k
          func (stream, dis_style_immediate, "#%d",
8310
144k
          (int) offset);
8311
144k
          func (stream, dis_style_text, "]%s",
8312
144k
          WRITEBACK_BIT_SET ? "!" : "");
8313
144k
        }
8314
16.2k
      else if (NEGATIVE_BIT_SET)
8315
11.6k
        {
8316
11.6k
          func (stream, dis_style_text, ", ");
8317
11.6k
          func (stream, dis_style_immediate, "#-0");
8318
11.6k
          func (stream, dis_style_text, "]");
8319
11.6k
        }
8320
4.57k
      else
8321
4.57k
        func (stream, dis_style_text, "]");
8322
160k
          }
8323
143k
        else
8324
143k
          {
8325
143k
      func (stream, dis_style_text, "]");
8326
8327
143k
      if (WRITEBACK_BIT_SET)
8328
79.6k
        {
8329
79.6k
          if (offset)
8330
74.1k
            {
8331
74.1k
        func (stream, dis_style_text, ", ");
8332
74.1k
        func (stream, dis_style_immediate,
8333
74.1k
              "#%d", (int) offset);
8334
74.1k
            }
8335
5.54k
          else if (NEGATIVE_BIT_SET)
8336
1.97k
            {
8337
1.97k
        func (stream, dis_style_text, ", ");
8338
1.97k
        func (stream, dis_style_immediate, "#-0");
8339
1.97k
            }
8340
79.6k
        }
8341
64.0k
      else
8342
64.0k
        {
8343
64.0k
          func (stream, dis_style_text, ", {");
8344
64.0k
          func (stream, dis_style_immediate, "%s%d",
8345
64.0k
          (NEGATIVE_BIT_SET && !offset) ? "-" : "",
8346
64.0k
          (int) offset);
8347
64.0k
          func (stream, dis_style_text, "}");
8348
64.0k
          value_in_comment = offset;
8349
64.0k
        }
8350
143k
          }
8351
304k
        if (rn == 15 && (PRE_BIT_SET || WRITEBACK_BIT_SET))
8352
19.5k
          {
8353
19.5k
      func (stream, dis_style_comment_start, "\t@ ");
8354
      /* For unaligned PCs, apply off-by-alignment
8355
         correction.  */
8356
19.5k
      info->print_address_func (offset + pc
8357
19.5k
              + info->bytes_per_chunk * 2
8358
19.5k
              - (pc & 3),
8359
19.5k
              info);
8360
19.5k
          }
8361
304k
      }
8362
304k
      break;
8363
8364
2.93k
    case 'B':
8365
2.93k
      {
8366
2.93k
        int regno = ((given >> 12) & 0xf) | ((given >> (22 - 4)) & 0x10);
8367
2.93k
        int offset = (given >> 1) & 0x3f;
8368
8369
2.93k
        func (stream, dis_style_text, "{");
8370
2.93k
        if (offset == 1)
8371
255
          func (stream, dis_style_register, "d%d", regno);
8372
2.68k
        else if (regno + offset > 32)
8373
1.60k
          {
8374
1.60k
      func (stream, dis_style_register, "d%d", regno);
8375
1.60k
      func (stream, dis_style_text, "-<overflow reg d%d>",
8376
1.60k
            regno + offset - 1);
8377
1.60k
          }
8378
1.08k
        else
8379
1.08k
          {
8380
1.08k
      func (stream, dis_style_register, "d%d", regno);
8381
1.08k
      func (stream, dis_style_text, "-");
8382
1.08k
      func (stream, dis_style_register, "d%d",
8383
1.08k
            regno + offset - 1);
8384
1.08k
          }
8385
2.93k
        func (stream, dis_style_text, "}");
8386
2.93k
      }
8387
2.93k
      break;
8388
8389
1.37k
    case 'C':
8390
1.37k
      {
8391
1.37k
        bool single = ((given >> 8) & 1) == 0;
8392
1.37k
        char reg_prefix = single ? 's' : 'd';
8393
1.37k
        int Dreg = (given >> 22) & 0x1;
8394
1.37k
        int Vdreg = (given >> 12) & 0xf;
8395
1.37k
        int reg = single ? ((Vdreg << 1) | Dreg)
8396
1.37k
             : ((Dreg << 4) | Vdreg);
8397
1.37k
        int num = (given >> (single ? 0 : 1)) & 0x7f;
8398
1.37k
        int maxreg = single ? 31 : 15;
8399
1.37k
        int topreg = reg + num - 1;
8400
8401
1.37k
        func (stream, dis_style_text, "{");
8402
1.37k
        if (!num)
8403
197
          {
8404
      /* Nothing.  */
8405
197
          }
8406
1.17k
        else if (num == 1)
8407
375
          {
8408
375
      func (stream, dis_style_register,
8409
375
            "%c%d", reg_prefix, reg);
8410
375
      func (stream, dis_style_text, ", ");
8411
375
          }
8412
799
        else if (topreg > maxreg)
8413
596
          {
8414
596
      func (stream, dis_style_register, "%c%d",
8415
596
            reg_prefix, reg);
8416
596
      func (stream, dis_style_text, "-<overflow reg d%d, ",
8417
596
            single ? topreg >> 1 : topreg);
8418
596
          }
8419
203
        else
8420
203
          {
8421
203
      func (stream, dis_style_register,
8422
203
            "%c%d", reg_prefix, reg);
8423
203
      func (stream, dis_style_text, "-");
8424
203
      func (stream, dis_style_register, "%c%d",
8425
203
            reg_prefix, topreg);
8426
203
      func (stream, dis_style_text, ", ");
8427
203
          }
8428
1.37k
        func (stream, dis_style_register, "VPR");
8429
1.37k
        func (stream, dis_style_text, "}");
8430
1.37k
      }
8431
1.37k
      break;
8432
8433
2.17k
    case 'u':
8434
2.17k
      if (cond != COND_UNCOND)
8435
203
        is_unpredictable = true;
8436
8437
      /* Fall through.  */
8438
528k
    case 'c':
8439
528k
      if (cond != COND_UNCOND && cp_num == 9)
8440
7.43k
        is_unpredictable = true;
8441
8442
      /* Fall through.  */
8443
529k
    case 'b':
8444
529k
      func (stream, dis_style_mnemonic, "%s",
8445
529k
      arm_conditional[cond]);
8446
529k
      break;
8447
8448
1.20k
    case 'I':
8449
      /* Print a Cirrus/DSP shift immediate.  */
8450
      /* Immediates are 7bit signed ints with bits 0..3 in
8451
         bits 0..3 of opcode and bits 4..6 in bits 5..7
8452
         of opcode.  */
8453
1.20k
      {
8454
1.20k
        int imm;
8455
8456
1.20k
        imm = (given & 0xf) | ((given & 0xe0) >> 1);
8457
8458
        /* Is ``imm'' a negative number?  */
8459
1.20k
        if (imm & 0x40)
8460
338
          imm -= 0x80;
8461
8462
1.20k
        func (stream, dis_style_immediate, "%d", imm);
8463
1.20k
      }
8464
8465
1.20k
      break;
8466
8467
4.53k
    case 'J':
8468
4.53k
      {
8469
4.53k
        unsigned long regno
8470
4.53k
          = arm_decode_field_multiple (given, 13, 15, 22, 22);
8471
8472
4.53k
        switch (regno)
8473
4.53k
          {
8474
279
          case 0x1:
8475
279
      func (stream, dis_style_register, "FPSCR");
8476
279
      break;
8477
244
          case 0x2:
8478
244
      func (stream, dis_style_register, "FPSCR_nzcvqc");
8479
244
      break;
8480
728
          case 0xc:
8481
728
      func (stream, dis_style_register, "VPR");
8482
728
      break;
8483
765
          case 0xd:
8484
765
      func (stream, dis_style_register, "P0");
8485
765
      break;
8486
820
          case 0xe:
8487
820
      func (stream, dis_style_register, "FPCXTNS");
8488
820
      break;
8489
335
          case 0xf:
8490
335
      func (stream, dis_style_register, "FPCXTS");
8491
335
      break;
8492
1.36k
          default:
8493
1.36k
      func (stream, dis_style_text, "<invalid reg %lu>",
8494
1.36k
            regno);
8495
1.36k
      break;
8496
4.53k
          }
8497
4.53k
      }
8498
4.53k
      break;
8499
8500
15.5k
    case 'F':
8501
15.5k
      switch (given & 0x00408000)
8502
15.5k
        {
8503
4.96k
        case 0:
8504
4.96k
          func (stream, dis_style_immediate, "4");
8505
4.96k
          break;
8506
2.88k
        case 0x8000:
8507
2.88k
          func (stream, dis_style_immediate, "1");
8508
2.88k
          break;
8509
4.33k
        case 0x00400000:
8510
4.33k
          func (stream, dis_style_immediate, "2");
8511
4.33k
          break;
8512
3.32k
        default:
8513
3.32k
          func (stream, dis_style_immediate, "3");
8514
15.5k
        }
8515
15.5k
      break;
8516
8517
15.5k
    case 'P':
8518
7.98k
      switch (given & 0x00080080)
8519
7.98k
        {
8520
2.76k
        case 0:
8521
2.76k
          func (stream, dis_style_mnemonic, "s");
8522
2.76k
          break;
8523
1.29k
        case 0x80:
8524
1.29k
          func (stream, dis_style_mnemonic, "d");
8525
1.29k
          break;
8526
1.85k
        case 0x00080000:
8527
1.85k
          func (stream, dis_style_mnemonic, "e");
8528
1.85k
          break;
8529
2.07k
        default:
8530
2.07k
          func (stream, dis_style_text, _("<illegal precision>"));
8531
2.07k
          break;
8532
7.98k
        }
8533
7.98k
      break;
8534
8535
17.7k
    case 'Q':
8536
17.7k
      switch (given & 0x00408000)
8537
17.7k
        {
8538
5.16k
        case 0:
8539
5.16k
          func (stream, dis_style_mnemonic, "s");
8540
5.16k
          break;
8541
3.14k
        case 0x8000:
8542
3.14k
          func (stream, dis_style_mnemonic, "d");
8543
3.14k
          break;
8544
6.16k
        case 0x00400000:
8545
6.16k
          func (stream, dis_style_mnemonic, "e");
8546
6.16k
          break;
8547
3.30k
        default:
8548
3.30k
          func (stream, dis_style_mnemonic, "p");
8549
3.30k
          break;
8550
17.7k
        }
8551
17.7k
      break;
8552
8553
17.7k
    case 'R':
8554
7.98k
      switch (given & 0x60)
8555
7.98k
        {
8556
2.72k
        case 0:
8557
2.72k
          break;
8558
1.54k
        case 0x20:
8559
1.54k
          func (stream, dis_style_mnemonic, "p");
8560
1.54k
          break;
8561
1.13k
        case 0x40:
8562
1.13k
          func (stream, dis_style_mnemonic, "m");
8563
1.13k
          break;
8564
2.59k
        default:
8565
2.59k
          func (stream, dis_style_mnemonic, "z");
8566
2.59k
          break;
8567
7.98k
        }
8568
7.98k
      break;
8569
8570
1.31M
    case '0': case '1': case '2': case '3': case '4':
8571
1.88M
    case '5': case '6': case '7': case '8': case '9':
8572
1.88M
      {
8573
1.88M
        int width;
8574
8575
1.88M
        c = arm_decode_bitfield (c, given, &value, &width);
8576
8577
1.88M
        switch (*c)
8578
1.88M
          {
8579
51.4k
          case 'R':
8580
51.4k
      if (value == 15)
8581
5.14k
        is_unpredictable = true;
8582
      /* Fall through.  */
8583
107k
          case 'r':
8584
107k
      if (c[1] == 'u')
8585
10.3k
        {
8586
          /* Eat the 'u' character.  */
8587
10.3k
          ++ c;
8588
8589
10.3k
          if (u_reg == value)
8590
556
            is_unpredictable = true;
8591
10.3k
          u_reg = value;
8592
10.3k
        }
8593
107k
      func (stream, dis_style_register, "%s",
8594
107k
            arm_regnames[value]);
8595
107k
      break;
8596
7.77k
          case 'V':
8597
7.77k
      if (given & (1 << 6))
8598
5.28k
        goto Q;
8599
      /* FALLTHROUGH */
8600
12.1k
          case 'D':
8601
12.1k
      func (stream, dis_style_register, "d%ld", value);
8602
12.1k
      break;
8603
478
          case 'Q':
8604
5.76k
          Q:
8605
5.76k
      if (value & 1)
8606
1.67k
        func (stream, dis_style_text,
8607
1.67k
        "<illegal reg q%ld.5>", value >> 1);
8608
4.08k
      else
8609
4.08k
        func (stream, dis_style_register,
8610
4.08k
        "q%ld", value >> 1);
8611
5.76k
      break;
8612
1.44M
          case 'd':
8613
1.44M
      func (stream, base_style, "%ld", value);
8614
1.44M
      value_in_comment = value;
8615
1.44M
      break;
8616
1.25k
          case 'E':
8617
1.25k
                        {
8618
        /* Converts immediate 8 bit back to float value.  */
8619
1.25k
        unsigned floatVal = (value & 0x80) << 24
8620
1.25k
          | (value & 0x3F) << 19
8621
1.25k
          | ((value & 0x40) ? (0xF8 << 22) : (1 << 30));
8622
8623
        /* Quarter float have a maximum value of 31.0.
8624
           Get floating point value multiplied by 1e7.
8625
           The maximum value stays in limit of a 32-bit int.  */
8626
1.25k
        unsigned decVal =
8627
1.25k
          (78125 << (((floatVal >> 23) & 0xFF) - 124)) *
8628
1.25k
          (16 + (value & 0xF));
8629
8630
1.25k
        if (!(decVal % 1000000))
8631
509
          {
8632
509
            func (stream, dis_style_immediate, "%ld", value);
8633
509
            func (stream, dis_style_comment_start,
8634
509
            "\t@ 0x%08x %c%u.%01u",
8635
509
            floatVal, value & 0x80 ? '-' : ' ',
8636
509
            decVal / 10000000,
8637
509
            decVal % 10000000 / 1000000);
8638
509
          }
8639
741
        else if (!(decVal % 10000))
8640
263
          {
8641
263
            func (stream, dis_style_immediate, "%ld", value);
8642
263
            func (stream, dis_style_comment_start,
8643
263
            "\t@ 0x%08x %c%u.%03u",
8644
263
            floatVal, value & 0x80 ? '-' : ' ',
8645
263
            decVal / 10000000,
8646
263
            decVal % 10000000 / 10000);
8647
263
          }
8648
478
        else
8649
478
          {
8650
478
            func (stream, dis_style_immediate, "%ld", value);
8651
478
            func (stream, dis_style_comment_start,
8652
478
            "\t@ 0x%08x %c%u.%07u",
8653
478
            floatVal, value & 0x80 ? '-' : ' ',
8654
478
            decVal / 10000000, decVal % 10000000);
8655
478
          }
8656
1.25k
        break;
8657
478
      }
8658
535
          case 'k':
8659
535
      {
8660
535
        int from = (given & (1 << 7)) ? 32 : 16;
8661
535
        func (stream, dis_style_immediate, "%ld",
8662
535
        from - value);
8663
535
      }
8664
535
      break;
8665
8666
53.7k
          case 'f':
8667
53.7k
      if (value > 7)
8668
3.88k
        func (stream, dis_style_immediate, "#%s",
8669
3.88k
        arm_fp_const[value & 7]);
8670
49.9k
      else
8671
49.9k
        func (stream, dis_style_register, "f%ld", value);
8672
53.7k
      break;
8673
8674
622
          case 'w':
8675
622
      if (width == 2)
8676
397
        func (stream, dis_style_mnemonic, "%s",
8677
397
        iwmmxt_wwnames[value]);
8678
225
      else
8679
225
        func (stream, dis_style_mnemonic, "%s",
8680
225
        iwmmxt_wwssnames[value]);
8681
622
      break;
8682
8683
8.37k
          case 'g':
8684
8.37k
      func (stream, dis_style_register, "%s",
8685
8.37k
            iwmmxt_regnames[value]);
8686
8.37k
      break;
8687
369
          case 'G':
8688
369
      func (stream, dis_style_register, "%s",
8689
369
            iwmmxt_cregnames[value]);
8690
369
      break;
8691
8692
201
          case 'x':
8693
201
      func (stream, dis_style_immediate, "0x%lx",
8694
201
            (value & 0xffffffffUL));
8695
201
      break;
8696
8697
1.44k
          case 'c':
8698
1.44k
      switch (value)
8699
1.44k
        {
8700
484
        case 0:
8701
484
          func (stream, dis_style_mnemonic, "eq");
8702
484
          break;
8703
8704
253
        case 1:
8705
253
          func (stream, dis_style_mnemonic, "vs");
8706
253
          break;
8707
8708
401
        case 2:
8709
401
          func (stream, dis_style_mnemonic, "ge");
8710
401
          break;
8711
8712
302
        case 3:
8713
302
          func (stream, dis_style_mnemonic, "gt");
8714
302
          break;
8715
8716
0
        default:
8717
0
          func (stream, dis_style_text, "??");
8718
0
          break;
8719
1.44k
        }
8720
1.44k
      break;
8721
8722
1.44k
          case '`':
8723
880
      c++;
8724
880
      if (value == 0)
8725
383
        func (stream, dis_style_mnemonic, "%c", *c);
8726
880
      break;
8727
234k
          case '\'':
8728
234k
      c++;
8729
234k
      if (value == ((1ul << width) - 1))
8730
109k
        func (stream, base_style, "%c", *c);
8731
234k
      break;
8732
13.1k
          case '?':
8733
13.1k
      func (stream, base_style, "%c",
8734
13.1k
            c[(1 << width) - (int) value]);
8735
13.1k
      c += 1 << width;
8736
13.1k
      break;
8737
0
          default:
8738
0
      abort ();
8739
1.88M
          }
8740
1.88M
      }
8741
1.88M
      break;
8742
8743
1.88M
    case 'y':
8744
55.4k
    case 'z':
8745
55.4k
      {
8746
55.4k
        int single = *c++ == 'y';
8747
55.4k
        int regno;
8748
8749
55.4k
        switch (*c)
8750
55.4k
          {
8751
254
          case '4': /* Sm pair */
8752
14.0k
          case '0': /* Sm, Dm */
8753
14.0k
      regno = given & 0x0000000f;
8754
14.0k
      if (single)
8755
7.96k
        {
8756
7.96k
          regno <<= 1;
8757
7.96k
          regno += (given >> 5) & 1;
8758
7.96k
        }
8759
6.12k
      else
8760
6.12k
        regno += ((given >> 5) & 1) << 4;
8761
14.0k
      break;
8762
8763
21.4k
          case '1': /* Sd, Dd */
8764
21.4k
      regno = (given >> 12) & 0x0000000f;
8765
21.4k
      if (single)
8766
15.4k
        {
8767
15.4k
          regno <<= 1;
8768
15.4k
          regno += (given >> 22) & 1;
8769
15.4k
        }
8770
6.04k
      else
8771
6.04k
        regno += ((given >> 22) & 1) << 4;
8772
21.4k
      break;
8773
8774
11.5k
          case '2': /* Sn, Dn */
8775
11.5k
      regno = (given >> 16) & 0x0000000f;
8776
11.5k
      if (single)
8777
6.64k
        {
8778
6.64k
          regno <<= 1;
8779
6.64k
          regno += (given >> 7) & 1;
8780
6.64k
        }
8781
4.88k
      else
8782
4.88k
        regno += ((given >> 7) & 1) << 4;
8783
11.5k
      break;
8784
8785
8.35k
          case '3': /* List */
8786
8.35k
      func (stream, dis_style_text, "{");
8787
8.35k
      regno = (given >> 12) & 0x0000000f;
8788
8.35k
      if (single)
8789
5.56k
        {
8790
5.56k
          regno <<= 1;
8791
5.56k
          regno += (given >> 22) & 1;
8792
5.56k
        }
8793
2.79k
      else
8794
2.79k
        regno += ((given >> 22) & 1) << 4;
8795
8.35k
      break;
8796
8797
0
          default:
8798
0
      abort ();
8799
55.4k
          }
8800
8801
55.4k
        func (stream, dis_style_register, "%c%d",
8802
55.4k
        single ? 's' : 'd', regno);
8803
8804
55.4k
        if (*c == '3')
8805
8.35k
          {
8806
8.35k
      int count = given & 0xff;
8807
8808
8.35k
      if (single == 0)
8809
2.79k
        count >>= 1;
8810
8811
8.35k
      if (--count)
8812
8.00k
        {
8813
8.00k
          func (stream, dis_style_text, "-");
8814
8.00k
          func (stream, dis_style_register, "%c%d",
8815
8.00k
          single ? 's' : 'd',
8816
8.00k
          regno + count);
8817
8.00k
        }
8818
8819
8.35k
      func (stream, dis_style_text, "}");
8820
8.35k
          }
8821
47.0k
        else if (*c == '4')
8822
254
          {
8823
254
      func (stream, dis_style_text, ", ");
8824
254
      func (stream, dis_style_register, "%c%d",
8825
254
            single ? 's' : 'd', regno + 1);
8826
254
          }
8827
55.4k
      }
8828
0
      break;
8829
8830
2.25k
    case 'L':
8831
2.25k
      switch (given & 0x00400100)
8832
2.25k
        {
8833
330
        case 0x00000000:
8834
330
          func (stream, dis_style_mnemonic, "b");
8835
330
          break;
8836
541
        case 0x00400000:
8837
541
          func (stream, dis_style_mnemonic, "h");
8838
541
          break;
8839
617
        case 0x00000100:
8840
617
          func (stream, dis_style_mnemonic, "w");
8841
617
          break;
8842
766
        case 0x00400100:
8843
766
          func (stream, dis_style_mnemonic, "d");
8844
766
          break;
8845
0
        default:
8846
0
          break;
8847
2.25k
        }
8848
2.25k
      break;
8849
8850
2.25k
    case 'Z':
8851
202
      {
8852
        /* given (20, 23) | given (0, 3) */
8853
202
        value = ((given >> 16) & 0xf0) | (given & 0xf);
8854
202
        func (stream, dis_style_immediate, "%d", (int) value);
8855
202
      }
8856
202
      break;
8857
8858
2.25k
    case 'l':
8859
      /* This is like the 'A' operator, except that if
8860
         the width field "M" is zero, then the offset is
8861
         *not* multiplied by four.  */
8862
2.25k
      {
8863
2.25k
        int offset = given & 0xff;
8864
2.25k
        int multiplier = (given & 0x00000100) ? 4 : 1;
8865
8866
2.25k
        func (stream, dis_style_text, "[");
8867
2.25k
        func (stream, dis_style_register, "%s",
8868
2.25k
        arm_regnames [(given >> 16) & 0xf]);
8869
8870
2.25k
        if (multiplier > 1)
8871
1.38k
          {
8872
1.38k
      value_in_comment = offset * multiplier;
8873
1.38k
      if (NEGATIVE_BIT_SET)
8874
372
        value_in_comment = - value_in_comment;
8875
1.38k
          }
8876
8877
2.25k
        if (offset)
8878
1.64k
          {
8879
1.64k
      if (PRE_BIT_SET)
8880
669
        {
8881
669
          func (stream, dis_style_text, ", ");
8882
669
          func (stream, dis_style_immediate, "#%s%d",
8883
669
          NEGATIVE_BIT_SET ? "-" : "",
8884
669
          offset * multiplier);
8885
669
          func (stream, dis_style_text, "]%s",
8886
669
          WRITEBACK_BIT_SET ? "!" : "");
8887
669
        }
8888
977
      else
8889
977
        {
8890
977
          func (stream, dis_style_text, "], ");
8891
977
          func (stream, dis_style_immediate, "#%s%d",
8892
977
          NEGATIVE_BIT_SET ? "-" : "",
8893
977
          offset * multiplier);
8894
977
        }
8895
1.64k
          }
8896
608
        else
8897
608
          func (stream, dis_style_text, "]");
8898
2.25k
      }
8899
2.25k
      break;
8900
8901
2.76k
    case 'r':
8902
2.76k
      {
8903
2.76k
        int imm4 = (given >> 4) & 0xf;
8904
2.76k
        int puw_bits = ((given >> 22) & 6) | ((given >> W_BIT) & 1);
8905
2.76k
        int ubit = ! NEGATIVE_BIT_SET;
8906
2.76k
        const char *rm = arm_regnames [given & 0xf];
8907
2.76k
        const char *rn = arm_regnames [(given >> 16) & 0xf];
8908
8909
2.76k
        switch (puw_bits)
8910
2.76k
          {
8911
307
          case 1:
8912
1.00k
          case 3:
8913
1.00k
      func (stream, dis_style_text, "[");
8914
1.00k
      func (stream, dis_style_register, "%s", rn);
8915
1.00k
      func (stream, dis_style_text, "], ");
8916
1.00k
      func (stream, dis_style_text, "%c", ubit ? '+' : '-');
8917
1.00k
      func (stream, dis_style_register, "%s", rm);
8918
1.00k
      if (imm4)
8919
774
        {
8920
774
          func (stream, dis_style_text, ", ");
8921
774
          func (stream, dis_style_sub_mnemonic, "lsl ");
8922
774
          func (stream, dis_style_immediate, "#%d", imm4);
8923
774
        }
8924
1.00k
      break;
8925
8926
374
          case 4:
8927
573
          case 5:
8928
768
          case 6:
8929
1.37k
          case 7:
8930
1.37k
      func (stream, dis_style_text, "[");
8931
1.37k
      func (stream, dis_style_register, "%s", rn);
8932
1.37k
      func (stream, dis_style_text, ", ");
8933
1.37k
      func (stream, dis_style_text, "%c", ubit ? '+' : '-');
8934
1.37k
      func (stream, dis_style_register, "%s", rm);
8935
1.37k
      if (imm4 > 0)
8936
1.03k
        {
8937
1.03k
          func (stream, dis_style_text, ", ");
8938
1.03k
          func (stream, dis_style_sub_mnemonic, "lsl ");
8939
1.03k
          func (stream, dis_style_immediate, "#%d", imm4);
8940
1.03k
        }
8941
1.37k
      func (stream, dis_style_text, "]");
8942
1.37k
      if (puw_bits == 5 || puw_bits == 7)
8943
804
        func (stream, dis_style_text, "!");
8944
1.37k
      break;
8945
8946
385
          default:
8947
385
      func (stream, dis_style_text, "INVALID");
8948
2.76k
          }
8949
2.76k
      }
8950
2.76k
      break;
8951
8952
2.76k
    case 'i':
8953
389
      {
8954
389
        long imm5;
8955
389
        imm5 = ((given & 0x100) >> 4) | (given & 0xf);
8956
389
        func (stream, dis_style_immediate, "%ld",
8957
389
        (imm5 == 0) ? 32 : imm5);
8958
389
      }
8959
389
      break;
8960
8961
0
    default:
8962
0
      abort ();
8963
5.75M
    }
8964
5.75M
      }
8965
7.39M
    else
8966
7.39M
      {
8967
7.39M
        if (*c == '@')
8968
2.79k
    base_style = dis_style_comment_start;
8969
8970
7.39M
        if (*c == '\t')
8971
537k
    base_style = dis_style_text;
8972
8973
7.39M
        func (stream, base_style, "%c", *c);
8974
7.39M
      }
8975
13.1M
  }
8976
8977
534k
      if (value_in_comment > 32 || value_in_comment < -16)
8978
239k
  func (stream, dis_style_comment_start, "\t@ 0x%lx",
8979
239k
        (value_in_comment & 0xffffffffUL));
8980
8981
534k
      if (is_unpredictable)
8982
20.5k
  func (stream, dis_style_comment_start, UNPREDICTABLE_INSTRUCTION);
8983
8984
534k
      return true;
8985
534k
    }
8986
7.93M
  return false;
8987
8.46M
}
8988
8989
static bool
8990
print_insn_coprocessor (bfd_vma pc,
8991
      struct disassemble_info *info,
8992
      long given,
8993
      bool thumb)
8994
4.40M
{
8995
4.40M
  return print_insn_coprocessor_1 (coprocessor_opcodes,
8996
4.40M
           pc, info, given, thumb);
8997
4.40M
}
8998
8999
static bool
9000
print_insn_generic_coprocessor (bfd_vma pc,
9001
        struct disassemble_info *info,
9002
        long given,
9003
        bool thumb)
9004
4.06M
{
9005
4.06M
  return print_insn_coprocessor_1 (generic_coprocessor_opcodes,
9006
4.06M
           pc, info, given, thumb);
9007
4.06M
}
9008
9009
/* Decodes and prints ARM addressing modes.  Returns the offset
9010
   used in the address, if any, if it is worthwhile printing the
9011
   offset as a hexadecimal value in a comment at the end of the
9012
   line of disassembly.  */
9013
9014
static signed long
9015
print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
9016
526k
{
9017
526k
  void *stream = info->stream;
9018
526k
  fprintf_styled_ftype func = info->fprintf_styled_func;
9019
526k
  bfd_vma offset = 0;
9020
9021
526k
  if (((given & 0x000f0000) == 0x000f0000)
9022
526k
      && ((given & 0x02000000) == 0))
9023
23.0k
    {
9024
23.0k
      offset = given & 0xfff;
9025
9026
23.0k
      func (stream, dis_style_text, "[");
9027
23.0k
      func (stream, dis_style_register, "pc");
9028
9029
23.0k
      if (PRE_BIT_SET)
9030
12.3k
  {
9031
    /* Pre-indexed.  Elide offset of positive zero when
9032
       non-writeback.  */
9033
12.3k
    if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
9034
11.5k
      {
9035
11.5k
        func (stream, dis_style_text, ", ");
9036
11.5k
        func (stream, dis_style_immediate, "#%s%d",
9037
11.5k
        NEGATIVE_BIT_SET ? "-" : "", (int) offset);
9038
11.5k
      }
9039
9040
12.3k
    if (NEGATIVE_BIT_SET)
9041
4.77k
      offset = -offset;
9042
9043
12.3k
    offset += pc + 8;
9044
9045
    /* Cope with the possibility of write-back
9046
       being used.  Probably a very dangerous thing
9047
       for the programmer to do, but who are we to
9048
       argue ?  */
9049
12.3k
    func (stream, dis_style_text, "]%s", WRITEBACK_BIT_SET ? "!" : "");
9050
12.3k
  }
9051
10.7k
      else  /* Post indexed.  */
9052
10.7k
  {
9053
10.7k
    func (stream, dis_style_text, "], ");
9054
10.7k
    func (stream, dis_style_immediate, "#%s%d",
9055
10.7k
    NEGATIVE_BIT_SET ? "-" : "", (int) offset);
9056
9057
    /* Ie ignore the offset.  */
9058
10.7k
    offset = pc + 8;
9059
10.7k
  }
9060
9061
23.0k
      func (stream, dis_style_comment_start, "\t@ ");
9062
23.0k
      info->print_address_func (offset, info);
9063
23.0k
      offset = 0;
9064
23.0k
    }
9065
503k
  else
9066
503k
    {
9067
503k
      func (stream, dis_style_text, "[");
9068
503k
      func (stream, dis_style_register, "%s",
9069
503k
      arm_regnames[(given >> 16) & 0xf]);
9070
9071
503k
      if (PRE_BIT_SET)
9072
244k
  {
9073
244k
    if ((given & 0x02000000) == 0)
9074
172k
      {
9075
        /* Elide offset of positive zero when non-writeback.  */
9076
172k
        offset = given & 0xfff;
9077
172k
        if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
9078
169k
    {
9079
169k
      func (stream, dis_style_text, ", ");
9080
169k
      func (stream, dis_style_immediate, "#%s%d",
9081
169k
      NEGATIVE_BIT_SET ? "-" : "", (int) offset);
9082
169k
    }
9083
172k
      }
9084
72.0k
    else
9085
72.0k
      {
9086
72.0k
        func (stream, dis_style_text, ", %s",
9087
72.0k
        NEGATIVE_BIT_SET ? "-" : "");
9088
72.0k
        arm_decode_shift (given, func, stream, true);
9089
72.0k
      }
9090
9091
244k
    func (stream, dis_style_text, "]%s",
9092
244k
    WRITEBACK_BIT_SET ? "!" : "");
9093
244k
  }
9094
258k
      else
9095
258k
  {
9096
258k
    if ((given & 0x02000000) == 0)
9097
177k
      {
9098
        /* Always show offset.  */
9099
177k
        offset = given & 0xfff;
9100
177k
        func (stream, dis_style_text, "], ");
9101
177k
        func (stream, dis_style_immediate, "#%s%d",
9102
177k
        NEGATIVE_BIT_SET ? "-" : "", (int) offset);
9103
177k
      }
9104
80.6k
    else
9105
80.6k
      {
9106
80.6k
        func (stream, dis_style_text, "], %s",
9107
80.6k
        NEGATIVE_BIT_SET ? "-" : "");
9108
80.6k
        arm_decode_shift (given, func, stream, true);
9109
80.6k
      }
9110
258k
  }
9111
503k
      if (NEGATIVE_BIT_SET)
9112
292k
  offset = -offset;
9113
503k
    }
9114
9115
526k
  return (signed long) offset;
9116
526k
}
9117
9118
9119
/* Print one cde instruction on INFO->STREAM.
9120
   Return TRUE if the instuction matched, FALSE if this is not a
9121
   recognised cde instruction.  */
9122
static bool
9123
print_insn_cde (struct disassemble_info *info, long given, bool thumb)
9124
278k
{
9125
278k
  const struct cdeopcode32 *insn;
9126
278k
  void *stream = info->stream;
9127
278k
  fprintf_styled_ftype func = info->fprintf_styled_func;
9128
278k
  enum disassembler_style base_style = dis_style_mnemonic;
9129
278k
  enum disassembler_style old_base_style = base_style;
9130
9131
278k
  if (thumb)
9132
278k
  {
9133
    /* Manually extract the coprocessor code from a known point.
9134
       This position is the same across all CDE instructions.  */
9135
3.49M
    for (insn = cde_opcodes; insn->assembler; insn++)
9136
3.23M
    {
9137
3.23M
      uint16_t coproc = (given >> insn->coproc_shift) & insn->coproc_mask;
9138
3.23M
      uint16_t coproc_mask = 1 << coproc;
9139
3.23M
      if (! (coproc_mask & cde_coprocs))
9140
1.93M
  continue;
9141
9142
1.30M
      if ((given & insn->mask) == insn->value)
9143
18.3k
      {
9144
18.3k
  bool is_unpredictable = false;
9145
18.3k
  const char *c;
9146
9147
416k
  for (c = insn->assembler; *c; c++)
9148
397k
  {
9149
397k
    if (*c == '%')
9150
146k
    {
9151
146k
      switch (*++c)
9152
146k
      {
9153
18.3k
        case '{':
9154
18.3k
    ++c;
9155
18.3k
    if (*c == '\0')
9156
0
      abort ();
9157
18.3k
    old_base_style = base_style;
9158
18.3k
    base_style = decode_base_style (*c);
9159
18.3k
    ++c;
9160
18.3k
    if (*c != ':')
9161
0
      abort ();
9162
18.3k
    break;
9163
9164
18.3k
        case '}':
9165
18.3k
    base_style = old_base_style;
9166
18.3k
    break;
9167
9168
0
        case '%':
9169
0
    func (stream, base_style, "%%");
9170
0
    break;
9171
9172
72.9k
        case '0': case '1': case '2': case '3': case '4':
9173
72.9k
        case '5': case '6': case '7': case '8': case '9':
9174
72.9k
        {
9175
72.9k
    int width;
9176
72.9k
    unsigned long value;
9177
9178
72.9k
    c = arm_decode_bitfield (c, given, &value, &width);
9179
9180
72.9k
    switch (*c)
9181
72.9k
    {
9182
7.64k
      case 'S':
9183
7.64k
        if (value > 10)
9184
5.02k
          is_unpredictable = true;
9185
        /* Fall through.  */
9186
7.64k
      case 'R':
9187
7.64k
        if (value == 13)
9188
455
          is_unpredictable = true;
9189
        /* Fall through.  */
9190
7.64k
      case 'r':
9191
7.64k
        func (stream, dis_style_register, "%s",
9192
7.64k
        arm_regnames[value]);
9193
7.64k
        break;
9194
9195
23.1k
      case 'n':
9196
23.1k
        if (value == 15)
9197
1.38k
          func (stream, dis_style_register, "%s", "APSR_nzcv");
9198
21.7k
        else
9199
21.7k
          func (stream, dis_style_register, "%s",
9200
21.7k
          arm_regnames[value]);
9201
23.1k
        break;
9202
9203
7.64k
      case 'T':
9204
7.64k
        func (stream, dis_style_register, "%s",
9205
7.64k
        arm_regnames[(value + 1) & 15]);
9206
7.64k
        break;
9207
9208
18.3k
      case 'd':
9209
18.3k
        func (stream, dis_style_immediate, "%ld", value);
9210
18.3k
        break;
9211
9212
16.1k
      case 'V':
9213
16.1k
        if (given & (1 << 6))
9214
8.02k
          func (stream, dis_style_register, "q%ld", value >> 1);
9215
8.13k
        else if (given & (1 << 24))
9216
2.92k
          func (stream, dis_style_register, "d%ld", value);
9217
5.21k
        else
9218
5.21k
          {
9219
      /* Encoding for S register is different than for D and
9220
         Q registers.  S registers are encoded using the top
9221
         single bit in position 22 as the lowest bit of the
9222
         register number, while for Q and D it represents the
9223
         highest bit of the register number.  */
9224
5.21k
      uint8_t top_bit = (value >> 4) & 1;
9225
5.21k
      uint8_t tmp = (value << 1) & 0x1e;
9226
5.21k
      uint8_t res = tmp | top_bit;
9227
5.21k
      func (stream, dis_style_register, "s%u", res);
9228
5.21k
          }
9229
16.1k
        break;
9230
9231
0
    default:
9232
0
      abort ();
9233
72.9k
    }
9234
72.9k
        }
9235
72.9k
      break;
9236
9237
72.9k
      case 'p':
9238
18.3k
        {
9239
18.3k
    uint8_t proc_number = (given >> 8) & 0x7;
9240
18.3k
    func (stream, dis_style_register, "p%u", proc_number);
9241
18.3k
    break;
9242
72.9k
        }
9243
9244
18.3k
      case 'a':
9245
18.3k
        {
9246
18.3k
    uint8_t a_offset = 28;
9247
18.3k
    if (given & (1 << a_offset))
9248
8.11k
      func (stream, dis_style_mnemonic, "a");
9249
18.3k
    break;
9250
72.9k
        }
9251
0
    default:
9252
0
      abort ();
9253
146k
    }
9254
146k
  }
9255
251k
  else
9256
251k
    {
9257
251k
      if (*c == '@')
9258
0
        base_style = dis_style_comment_start;
9259
251k
      if (*c == '\t')
9260
18.3k
        base_style = dis_style_text;
9261
9262
251k
      func (stream, base_style, "%c", *c);
9263
251k
    }
9264
397k
      }
9265
9266
18.3k
      if (is_unpredictable)
9267
5.02k
  func (stream, dis_style_comment_start, UNPREDICTABLE_INSTRUCTION);
9268
9269
18.3k
      return true;
9270
18.3k
      }
9271
1.30M
    }
9272
259k
    return false;
9273
278k
  }
9274
0
  else
9275
0
    return false;
9276
278k
}
9277
9278
9279
/* Print one neon instruction on INFO->STREAM.
9280
   Return TRUE if the instuction matched, FALSE if this is not a
9281
   recognised neon instruction.  */
9282
9283
static bool
9284
print_insn_neon (struct disassemble_info *info, long given, bool thumb)
9285
3.94M
{
9286
3.94M
  const struct opcode32 *insn;
9287
3.94M
  void *stream = info->stream;
9288
3.94M
  fprintf_styled_ftype func = info->fprintf_styled_func;
9289
3.94M
  enum disassembler_style base_style = dis_style_mnemonic;
9290
3.94M
  enum disassembler_style old_base_style = base_style;
9291
9292
3.94M
  if (thumb)
9293
95.7k
    {
9294
95.7k
      if ((given & 0xef000000) == 0xef000000)
9295
16.7k
  {
9296
    /* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding.  */
9297
16.7k
    unsigned long bit28 = given & (1 << 28);
9298
9299
16.7k
    given &= 0x00ffffff;
9300
16.7k
    if (bit28)
9301
10.3k
            given |= 0xf3000000;
9302
6.36k
          else
9303
6.36k
      given |= 0xf2000000;
9304
16.7k
  }
9305
78.9k
      else if ((given & 0xff000000) == 0xf9000000)
9306
8.14k
  given ^= 0xf9000000 ^ 0xf4000000;
9307
      /* BFloat16 neon instructions without special top byte handling.  */
9308
70.8k
      else if ((given & 0xff000000) == 0xfe000000
9309
70.8k
         || (given & 0xff000000) == 0xfc000000)
9310
5.02k
  ;
9311
      /* vdup is also a valid neon instruction.  */
9312
65.7k
      else if ((given & 0xff900f5f) != 0xee800b10)
9313
65.5k
  return false;
9314
95.7k
    }
9315
9316
1.17G
  for (insn = neon_opcodes; insn->assembler; insn++)
9317
1.17G
    {
9318
1.17G
      unsigned long cond_mask = insn->mask;
9319
1.17G
      unsigned long cond_value = insn->value;
9320
1.17G
      int cond;
9321
9322
1.17G
      if (thumb)
9323
7.25M
        {
9324
7.25M
          if ((cond_mask & 0xf0000000) == 0) {
9325
              /* For the entries in neon_opcodes, an opcode mask/value with
9326
                 the high 4 bits equal to 0 indicates a conditional
9327
                 instruction. For thumb however, we need to include those
9328
                 bits in the instruction matching.  */
9329
180k
              cond_mask |= 0xf0000000;
9330
              /* Furthermore, the thumb encoding of a conditional instruction
9331
                 will have the high 4 bits equal to 0xe.  */
9332
180k
              cond_value |= 0xe0000000;
9333
180k
          }
9334
7.25M
          if (ifthen_state)
9335
154k
            cond = IFTHEN_COND;
9336
7.09M
          else
9337
7.09M
            cond = COND_UNCOND;
9338
7.25M
        }
9339
1.16G
      else
9340
1.16G
        {
9341
1.16G
          if ((given & 0xf0000000) == 0xf0000000)
9342
109M
            {
9343
              /* If the instruction is unconditional, update the mask to only
9344
                 match against unconditional opcode values.  */
9345
109M
              cond_mask |= 0xf0000000;
9346
109M
              cond = COND_UNCOND;
9347
109M
            }
9348
1.05G
          else
9349
1.05G
            {
9350
1.05G
              cond = (given >> 28) & 0xf;
9351
1.05G
              if (cond == 0xe)
9352
63.3M
                cond = COND_UNCOND;
9353
1.05G
            }
9354
1.16G
        }
9355
9356
1.17G
      if ((given & cond_mask) == cond_value)
9357
71.6k
  {
9358
71.6k
    signed long value_in_comment = 0;
9359
71.6k
    bool is_unpredictable = false;
9360
71.6k
    const char *c;
9361
9362
1.15M
    for (c = insn->assembler; *c; c++)
9363
1.09M
      {
9364
1.09M
        if (*c == '%')
9365
379k
    {
9366
379k
      switch (*++c)
9367
379k
        {
9368
14.7k
        case '{':
9369
14.7k
          ++c;
9370
14.7k
          if (*c == '\0')
9371
0
      abort ();
9372
14.7k
          old_base_style = base_style;
9373
14.7k
          base_style = decode_base_style (*c);
9374
14.7k
          ++c;
9375
14.7k
          if (*c != ':')
9376
0
      abort ();
9377
14.7k
          break;
9378
9379
14.7k
        case '}':
9380
14.7k
          base_style = old_base_style;
9381
14.7k
          break;
9382
9383
0
        case '%':
9384
0
          func (stream, base_style, "%%");
9385
0
          break;
9386
9387
1.77k
        case 'u':
9388
1.77k
          if (thumb && ifthen_state)
9389
202
      is_unpredictable = true;
9390
9391
          /* Fall through.  */
9392
70.6k
        case 'c':
9393
70.6k
          func (stream, dis_style_mnemonic, "%s",
9394
70.6k
          arm_conditional[cond]);
9395
70.6k
          break;
9396
9397
6.28k
        case 'A':
9398
6.28k
          {
9399
6.28k
      static const unsigned char enc[16] =
9400
6.28k
      {
9401
6.28k
        0x4, 0x14, /* st4 0,1 */
9402
6.28k
        0x4, /* st1 2 */
9403
6.28k
        0x4, /* st2 3 */
9404
6.28k
        0x3, /* st3 4 */
9405
6.28k
        0x13, /* st3 5 */
9406
6.28k
        0x3, /* st1 6 */
9407
6.28k
        0x1, /* st1 7 */
9408
6.28k
        0x2, /* st2 8 */
9409
6.28k
        0x12, /* st2 9 */
9410
6.28k
        0x2, /* st1 10 */
9411
6.28k
        0, 0, 0, 0, 0
9412
6.28k
      };
9413
6.28k
      int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
9414
6.28k
      int rn = ((given >> 16) & 0xf);
9415
6.28k
      int rm = ((given >> 0) & 0xf);
9416
6.28k
      int align = ((given >> 4) & 0x3);
9417
6.28k
      int type = ((given >> 8) & 0xf);
9418
6.28k
      int n = enc[type] & 0xf;
9419
6.28k
      int stride = (enc[type] >> 4) + 1;
9420
6.28k
      int ix;
9421
9422
6.28k
      func (stream, dis_style_text, "{");
9423
6.28k
      if (stride > 1)
9424
8.02k
        for (ix = 0; ix != n; ix++)
9425
6.03k
          {
9426
6.03k
            if (ix > 0)
9427
4.03k
        func (stream, dis_style_text, ",");
9428
6.03k
            func (stream, dis_style_register, "d%d",
9429
6.03k
            rd + ix * stride);
9430
6.03k
          }
9431
4.28k
      else if (n == 1)
9432
571
        func (stream, dis_style_register, "d%d", rd);
9433
3.71k
      else
9434
3.71k
        {
9435
3.71k
          func (stream, dis_style_register, "d%d", rd);
9436
3.71k
          func (stream, dis_style_text, "-");
9437
3.71k
          func (stream, dis_style_register, "d%d",
9438
3.71k
          rd + n - 1);
9439
3.71k
        }
9440
6.28k
      func (stream, dis_style_text, "}, [");
9441
6.28k
      func (stream, dis_style_register, "%s",
9442
6.28k
            arm_regnames[rn]);
9443
6.28k
      if (align)
9444
3.75k
        {
9445
3.75k
          func (stream, dis_style_text, " :");
9446
3.75k
          func (stream, dis_style_immediate, "%d",
9447
3.75k
          32 << align);
9448
3.75k
        }
9449
6.28k
      func (stream, dis_style_text, "]");
9450
6.28k
      if (rm == 0xd)
9451
423
        func (stream, dis_style_text, "!");
9452
5.85k
      else if (rm != 0xf)
9453
5.29k
        {
9454
5.29k
          func (stream, dis_style_text, ", ");
9455
5.29k
          func (stream, dis_style_register, "%s",
9456
5.29k
          arm_regnames[rm]);
9457
5.29k
        }
9458
6.28k
          }
9459
6.28k
          break;
9460
9461
12.8k
        case 'B':
9462
12.8k
          {
9463
12.8k
      int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
9464
12.8k
      int rn = ((given >> 16) & 0xf);
9465
12.8k
      int rm = ((given >> 0) & 0xf);
9466
12.8k
      int idx_align = ((given >> 4) & 0xf);
9467
12.8k
                        int align = 0;
9468
12.8k
      int size = ((given >> 10) & 0x3);
9469
12.8k
      int idx = idx_align >> (size + 1);
9470
12.8k
                        int length = ((given >> 8) & 3) + 1;
9471
12.8k
                        int stride = 1;
9472
12.8k
                        int i;
9473
9474
12.8k
                        if (length > 1 && size > 0)
9475
6.67k
                          stride = (idx_align & (1 << size)) ? 2 : 1;
9476
9477
12.8k
                        switch (length)
9478
12.8k
                          {
9479
4.26k
                          case 1:
9480
4.26k
                            {
9481
4.26k
                              int amask = (1 << size) - 1;
9482
4.26k
                              if ((idx_align & (1 << size)) != 0)
9483
1.96k
                                return false;
9484
2.29k
                              if (size > 0)
9485
1.28k
                                {
9486
1.28k
                                  if ((idx_align & amask) == amask)
9487
261
                                    align = 8 << size;
9488
1.02k
                                  else if ((idx_align & amask) != 0)
9489
357
                                    return false;
9490
1.28k
                                }
9491
2.29k
                              }
9492
1.93k
                            break;
9493
9494
2.52k
                          case 2:
9495
2.52k
                            if (size == 2 && (idx_align & 2) != 0)
9496
266
                              return false;
9497
2.25k
                            align = (idx_align & 1) ? 16 << size : 0;
9498
2.25k
                            break;
9499
9500
2.34k
                          case 3:
9501
2.34k
                            if ((size == 2 && (idx_align & 3) != 0)
9502
2.34k
                                || (idx_align & 1) != 0)
9503
1.07k
                              return false;
9504
1.27k
                            break;
9505
9506
3.68k
                          case 4:
9507
3.68k
                            if (size == 2)
9508
500
                              {
9509
500
                                if ((idx_align & 3) == 3)
9510
258
                                  return false;
9511
242
                                align = (idx_align & 3) * 64;
9512
242
                              }
9513
3.18k
                            else
9514
3.18k
                              align = (idx_align & 1) ? 32 << size : 0;
9515
3.43k
                            break;
9516
9517
3.43k
                          default:
9518
0
                            abort ();
9519
12.8k
                          }
9520
9521
8.90k
      func (stream, dis_style_text, "{");
9522
32.8k
                        for (i = 0; i < length; i++)
9523
23.9k
        {
9524
23.9k
          if (i > 0)
9525
15.0k
            func (stream, dis_style_text, ",");
9526
23.9k
          func (stream, dis_style_register, "d%d[%d]",
9527
23.9k
          rd + i * stride, idx);
9528
23.9k
        }
9529
8.90k
      func (stream, dis_style_text, "}, [");
9530
8.90k
      func (stream, dis_style_register, "%s",
9531
8.90k
            arm_regnames[rn]);
9532
8.90k
      if (align)
9533
3.17k
        {
9534
3.17k
          func (stream, dis_style_text, " :");
9535
3.17k
          func (stream, dis_style_immediate, "%d", align);
9536
3.17k
        }
9537
8.90k
      func (stream, dis_style_text, "]");
9538
8.90k
      if (rm == 0xd)
9539
709
        func (stream, dis_style_text, "!");
9540
8.19k
      else if (rm != 0xf)
9541
5.99k
        {
9542
5.99k
          func (stream, dis_style_text, ", ");
9543
5.99k
          func (stream, dis_style_register, "%s",
9544
5.99k
          arm_regnames[rm]);
9545
5.99k
        }
9546
8.90k
          }
9547
0
          break;
9548
9549
3.27k
        case 'C':
9550
3.27k
          {
9551
3.27k
      int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
9552
3.27k
      int rn = ((given >> 16) & 0xf);
9553
3.27k
      int rm = ((given >> 0) & 0xf);
9554
3.27k
      int align = ((given >> 4) & 0x1);
9555
3.27k
      int size = ((given >> 6) & 0x3);
9556
3.27k
      int type = ((given >> 8) & 0x3);
9557
3.27k
      int n = type + 1;
9558
3.27k
      int stride = ((given >> 5) & 0x1);
9559
3.27k
      int ix;
9560
9561
3.27k
      if (stride && (n == 1))
9562
570
        n++;
9563
2.70k
      else
9564
2.70k
        stride++;
9565
9566
3.27k
      func (stream, dis_style_text, "{");
9567
3.27k
      if (stride > 1)
9568
7.29k
        for (ix = 0; ix != n; ix++)
9569
5.73k
          {
9570
5.73k
            if (ix > 0)
9571
4.17k
        func (stream, dis_style_text, ",");
9572
5.73k
            func (stream, dis_style_register, "d%d[]",
9573
5.73k
            rd + ix * stride);
9574
5.73k
          }
9575
1.71k
      else if (n == 1)
9576
434
        func (stream, dis_style_register, "d%d[]", rd);
9577
1.28k
      else
9578
1.28k
        {
9579
1.28k
          func (stream, dis_style_register, "d%d[]", rd);
9580
1.28k
          func (stream, dis_style_text, "-");
9581
1.28k
          func (stream, dis_style_register, "d%d[]",
9582
1.28k
          rd + n - 1);
9583
1.28k
        }
9584
3.27k
      func (stream, dis_style_text, "}, [");
9585
3.27k
      func (stream, dis_style_register, "%s",
9586
3.27k
            arm_regnames[rn]);
9587
3.27k
      if (align)
9588
2.33k
        {
9589
2.33k
                            align = (8 * (type + 1)) << size;
9590
2.33k
                            if (type == 3)
9591
981
                              align = (size > 1) ? align >> 1 : align;
9592
2.33k
          if (type == 2 || (type == 0 && !size))
9593
909
            func (stream, dis_style_text,
9594
909
            " :<bad align %d>", align);
9595
1.42k
          else
9596
1.42k
            {
9597
1.42k
        func (stream, dis_style_text, " :");
9598
1.42k
        func (stream, dis_style_immediate,
9599
1.42k
              "%d", align);
9600
1.42k
            }
9601
2.33k
        }
9602
3.27k
      func (stream, dis_style_text, "]");
9603
3.27k
      if (rm == 0xd)
9604
396
        func (stream, dis_style_text, "!");
9605
2.88k
      else if (rm != 0xf)
9606
2.22k
        {
9607
2.22k
          func (stream, dis_style_text, ", ");
9608
2.22k
          func (stream, dis_style_register, "%s",
9609
2.22k
          arm_regnames[rm]);
9610
2.22k
        }
9611
3.27k
          }
9612
3.27k
          break;
9613
9614
3.28k
        case 'D':
9615
3.28k
          {
9616
3.28k
      int raw_reg = (given & 0xf) | ((given >> 1) & 0x10);
9617
3.28k
      int size = (given >> 20) & 3;
9618
3.28k
      int reg = raw_reg & ((4 << size) - 1);
9619
3.28k
      int ix = raw_reg >> size >> 2;
9620
9621
3.28k
      func (stream, dis_style_register, "d%d[%d]", reg, ix);
9622
3.28k
          }
9623
3.28k
          break;
9624
9625
3.60k
        case 'E':
9626
          /* Neon encoded constant for mov, mvn, vorr, vbic.  */
9627
3.60k
          {
9628
3.60k
      int bits = 0;
9629
3.60k
      int cmode = (given >> 8) & 0xf;
9630
3.60k
      int op = (given >> 5) & 0x1;
9631
3.60k
      unsigned long value = 0, hival = 0;
9632
3.60k
      unsigned shift;
9633
3.60k
                        int size = 0;
9634
3.60k
                        int isfloat = 0;
9635
9636
3.60k
      bits |= ((given >> 24) & 1) << 7;
9637
3.60k
      bits |= ((given >> 16) & 7) << 4;
9638
3.60k
      bits |= ((given >> 0) & 15) << 0;
9639
9640
3.60k
      if (cmode < 8)
9641
836
        {
9642
836
          shift = (cmode >> 1) & 3;
9643
836
          value = (unsigned long) bits << (8 * shift);
9644
836
                            size = 32;
9645
836
        }
9646
2.76k
      else if (cmode < 12)
9647
239
        {
9648
239
          shift = (cmode >> 1) & 1;
9649
239
          value = (unsigned long) bits << (8 * shift);
9650
239
                            size = 16;
9651
239
        }
9652
2.52k
      else if (cmode < 14)
9653
290
        {
9654
290
          shift = (cmode & 1) + 1;
9655
290
          value = (unsigned long) bits << (8 * shift);
9656
290
          value |= (1ul << (8 * shift)) - 1;
9657
290
                            size = 32;
9658
290
        }
9659
2.23k
      else if (cmode == 14)
9660
1.56k
        {
9661
1.56k
          if (op)
9662
997
            {
9663
        /* Bit replication into bytes.  */
9664
997
        int ix;
9665
997
        unsigned long mask;
9666
9667
997
        value = 0;
9668
997
                                hival = 0;
9669
8.97k
        for (ix = 7; ix >= 0; ix--)
9670
7.97k
          {
9671
7.97k
            mask = ((bits >> ix) & 1) ? 0xff : 0;
9672
7.97k
                                    if (ix <= 3)
9673
3.98k
              value = (value << 8) | mask;
9674
3.98k
                                    else
9675
3.98k
                                      hival = (hival << 8) | mask;
9676
7.97k
          }
9677
997
                                size = 64;
9678
997
            }
9679
564
                            else
9680
564
                              {
9681
                                /* Byte replication.  */
9682
564
                                value = (unsigned long) bits;
9683
564
                                size = 8;
9684
564
                              }
9685
1.56k
        }
9686
674
      else if (!op)
9687
674
        {
9688
          /* Floating point encoding.  */
9689
674
          int tmp;
9690
9691
674
          value = (unsigned long)  (bits & 0x7f) << 19;
9692
674
          value |= (unsigned long) (bits & 0x80) << 24;
9693
674
          tmp = bits & 0x40 ? 0x3c : 0x40;
9694
674
          value |= (unsigned long) tmp << 24;
9695
674
                            size = 32;
9696
674
                            isfloat = 1;
9697
674
        }
9698
0
      else
9699
0
        {
9700
0
          func (stream, dis_style_text,
9701
0
          "<illegal constant %.8x:%x:%x>",
9702
0
                                  bits, cmode, op);
9703
0
                            size = 32;
9704
0
          break;
9705
0
        }
9706
3.60k
                        switch (size)
9707
3.60k
                          {
9708
564
                          case 8:
9709
564
          func (stream, dis_style_immediate, "#%ld", value);
9710
564
          func (stream, dis_style_comment_start,
9711
564
          "\t@ 0x%.2lx", value);
9712
564
                            break;
9713
9714
239
                          case 16:
9715
239
          func (stream, dis_style_immediate, "#%ld", value);
9716
239
          func (stream, dis_style_comment_start,
9717
239
          "\t@ 0x%.4lx", value);
9718
239
                            break;
9719
9720
1.80k
                          case 32:
9721
1.80k
                            if (isfloat)
9722
674
                              {
9723
674
                                unsigned char valbytes[4];
9724
674
                                double fvalue;
9725
9726
                                /* Do this a byte at a time so we don't have to
9727
                                   worry about the host's endianness.  */
9728
674
                                valbytes[0] = value & 0xff;
9729
674
                                valbytes[1] = (value >> 8) & 0xff;
9730
674
                                valbytes[2] = (value >> 16) & 0xff;
9731
674
                                valbytes[3] = (value >> 24) & 0xff;
9732
9733
674
                                floatformat_to_double
9734
674
                                  (& floatformat_ieee_single_little, valbytes,
9735
674
                                  & fvalue);
9736
9737
674
        func (stream, dis_style_immediate,
9738
674
              "#%.7g", fvalue);
9739
674
        func (stream, dis_style_comment_start,
9740
674
              "\t@ 0x%.8lx", value);
9741
674
                              }
9742
1.12k
                            else
9743
1.12k
            {
9744
1.12k
        func (stream, dis_style_immediate, "#%ld",
9745
1.12k
              (long) (((value & 0x80000000L) != 0)
9746
1.12k
                ? value | ~0xffffffffL : value));
9747
1.12k
        func (stream, dis_style_comment_start,
9748
1.12k
              "\t@ 0x%.8lx", value);
9749
1.12k
            }
9750
1.80k
                            break;
9751
9752
997
                          case 64:
9753
997
          func (stream, dis_style_immediate,
9754
997
          "#0x%.8lx%.8lx", hival, value);
9755
997
                            break;
9756
9757
0
                          default:
9758
0
                            abort ();
9759
3.60k
                          }
9760
3.60k
          }
9761
3.60k
          break;
9762
9763
3.60k
        case 'F':
9764
1.87k
          {
9765
1.87k
      int regno = ((given >> 16) & 0xf) | ((given >> (7 - 4)) & 0x10);
9766
1.87k
      int num = (given >> 8) & 0x3;
9767
9768
1.87k
      func (stream, dis_style_text, "{");
9769
1.87k
      if (!num)
9770
419
        func (stream, dis_style_register, "d%d", regno);
9771
1.45k
      else if (num + regno >= 32)
9772
369
        {
9773
369
          func (stream, dis_style_register, "d%d", regno);
9774
369
          func (stream, dis_style_text, "-<overflow reg d%d",
9775
369
          regno + num);
9776
369
        }
9777
1.08k
      else
9778
1.08k
        {
9779
1.08k
          func (stream, dis_style_register, "d%d", regno);
9780
1.08k
          func (stream, dis_style_text, "-");
9781
1.08k
          func (stream, dis_style_register, "d%d",
9782
1.08k
          regno + num);
9783
1.08k
        }
9784
1.87k
      func (stream, dis_style_text, "}");
9785
1.87k
          }
9786
1.87k
          break;
9787
9788
9789
236k
        case '0': case '1': case '2': case '3': case '4':
9790
247k
        case '5': case '6': case '7': case '8': case '9':
9791
247k
          {
9792
247k
      int width;
9793
247k
      unsigned long value;
9794
9795
247k
      c = arm_decode_bitfield (c, given, &value, &width);
9796
9797
247k
      switch (*c)
9798
247k
        {
9799
475
        case 'r':
9800
475
          func (stream, dis_style_register, "%s",
9801
475
          arm_regnames[value]);
9802
475
          break;
9803
3.59k
        case 'd':
9804
3.59k
          func (stream, base_style, "%ld", value);
9805
3.59k
          value_in_comment = value;
9806
3.59k
          break;
9807
11.4k
        case 'e':
9808
11.4k
          func (stream, dis_style_immediate, "%ld",
9809
11.4k
          (1ul << width) - value);
9810
11.4k
          break;
9811
9812
43.2k
        case 'S':
9813
44.2k
        case 'T':
9814
44.2k
        case 'U':
9815
          /* Various width encodings.  */
9816
44.2k
          {
9817
44.2k
            int base = 8 << (*c - 'S'); /* 8,16 or 32 */
9818
44.2k
            int limit;
9819
44.2k
            unsigned low, high;
9820
9821
44.2k
            c++;
9822
44.2k
            if (*c >= '0' && *c <= '9')
9823
43.7k
        limit = *c - '0';
9824
459
            else if (*c >= 'a' && *c <= 'f')
9825
459
        limit = *c - 'a' + 10;
9826
0
            else
9827
0
        abort ();
9828
44.2k
            low = limit >> 2;
9829
44.2k
            high = limit & 3;
9830
9831
44.2k
            if (value < low || value > high)
9832
9.35k
        func (stream, dis_style_text,
9833
9.35k
              "<illegal width %d>", base << value);
9834
34.8k
            else
9835
34.8k
        func (stream, base_style, "%d",
9836
34.8k
              base << value);
9837
44.2k
          }
9838
0
          break;
9839
88.8k
        case 'R':
9840
88.8k
          if (given & (1 << 6))
9841
58.7k
            goto Q;
9842
          /* FALLTHROUGH */
9843
48.0k
        case 'D':
9844
48.0k
          func (stream, dis_style_register, "d%ld", value);
9845
48.0k
          break;
9846
13.4k
        case 'Q':
9847
72.1k
        Q:
9848
72.1k
          if (value & 1)
9849
35.1k
            func (stream, dis_style_text,
9850
35.1k
            "<illegal reg q%ld.5>", value >> 1);
9851
37.0k
          else
9852
37.0k
            func (stream, dis_style_register,
9853
37.0k
            "q%ld", value >> 1);
9854
72.1k
          break;
9855
9856
0
        case '`':
9857
0
          c++;
9858
0
          if (value == 0)
9859
0
            func (stream, dis_style_text, "%c", *c);
9860
0
          break;
9861
0
        case '\'':
9862
0
          c++;
9863
0
          if (value == ((1ul << width) - 1))
9864
0
            func (stream, dis_style_text, "%c", *c);
9865
0
          break;
9866
68.0k
        case '?':
9867
68.0k
          func (stream, dis_style_mnemonic, "%c",
9868
68.0k
          c[(1 << width) - (int) value]);
9869
68.0k
          c += 1 << width;
9870
68.0k
          break;
9871
0
        default:
9872
0
          abort ();
9873
247k
        }
9874
247k
          }
9875
247k
          break;
9876
9877
247k
        default:
9878
0
          abort ();
9879
379k
        }
9880
379k
    }
9881
711k
        else
9882
711k
    {
9883
711k
      if (*c == '@')
9884
0
        base_style = dis_style_comment_start;
9885
9886
711k
      if (*c == '\t')
9887
71.6k
        base_style = dis_style_text;
9888
9889
711k
      func (stream, base_style, "%c", *c);
9890
9891
711k
    }
9892
1.09M
      }
9893
9894
67.7k
    if (value_in_comment > 32 || value_in_comment < -16)
9895
587
      func (stream, dis_style_comment_start, "\t@ 0x%lx",
9896
587
      value_in_comment);
9897
9898
67.7k
    if (is_unpredictable)
9899
202
      func (stream, dis_style_comment_start, UNPREDICTABLE_INSTRUCTION);
9900
9901
67.7k
    return true;
9902
71.6k
  }
9903
1.17G
    }
9904
3.81M
  return false;
9905
3.88M
}
9906
9907
/* Print one mve instruction on INFO->STREAM.
9908
   Return TRUE if the instuction matched, FALSE if this is not a
9909
   recognised mve instruction.  */
9910
9911
static bool
9912
print_insn_mve (struct disassemble_info *info, long given)
9913
318k
{
9914
318k
  const struct mopcode32 *insn;
9915
318k
  void *stream = info->stream;
9916
318k
  fprintf_styled_ftype func = info->fprintf_styled_func;
9917
318k
  enum disassembler_style base_style = dis_style_mnemonic;
9918
318k
  enum disassembler_style old_base_style = base_style;
9919
9920
59.9M
  for (insn = mve_opcodes; insn->assembler; insn++)
9921
59.7M
    {
9922
59.7M
      if (((given & insn->mask) == insn->value)
9923
59.7M
    && !is_mve_encoding_conflict (given, insn->mve_op))
9924
116k
  {
9925
116k
    signed long value_in_comment = 0;
9926
116k
    bool is_unpredictable = false;
9927
116k
    bool is_undefined = false;
9928
116k
    const char *c;
9929
116k
    enum mve_unpredictable unpredictable_cond = UNPRED_NONE;
9930
116k
    enum mve_undefined undefined_cond = UNDEF_NONE;
9931
9932
    /* Most vector mve instruction are illegal in a it block.
9933
       There are a few exceptions; check for them.  */
9934
116k
    if (ifthen_state && !is_mve_okay_in_it (insn->mve_op))
9935
1.67k
      {
9936
1.67k
        is_unpredictable = true;
9937
1.67k
        unpredictable_cond = UNPRED_IT_BLOCK;
9938
1.67k
      }
9939
115k
    else if (is_mve_unpredictable (given, insn->mve_op,
9940
115k
           &unpredictable_cond))
9941
22.3k
      is_unpredictable = true;
9942
9943
116k
    if (is_mve_undefined (given, insn->mve_op, &undefined_cond))
9944
13.7k
      is_undefined = true;
9945
9946
    /* In "VORR Qd, Qm, Qn", if Qm==Qn, VORR is nothing but VMOV,
9947
       i.e "VMOV Qd, Qm".  */
9948
116k
    if ((insn->mve_op == MVE_VORR_REG)
9949
116k
        && (arm_decode_field (given, 1, 3)
9950
796
      == arm_decode_field (given, 17, 19)))
9951
590
      continue;
9952
9953
2.06M
    for (c = insn->assembler; *c; c++)
9954
1.95M
      {
9955
1.95M
        if (*c == '%')
9956
640k
    {
9957
640k
      switch (*++c)
9958
640k
        {
9959
29.4k
        case '{':
9960
29.4k
          ++c;
9961
29.4k
          if (*c == '\0')
9962
0
      abort ();
9963
29.4k
          old_base_style = base_style;
9964
29.4k
          base_style = decode_base_style (*c);
9965
29.4k
          ++c;
9966
29.4k
          if (*c != ':')
9967
0
      abort ();
9968
29.4k
          break;
9969
9970
29.4k
        case '}':
9971
29.4k
          base_style = old_base_style;
9972
29.4k
          break;
9973
9974
0
        case '%':
9975
0
          func (stream, base_style, "%%");
9976
0
          break;
9977
9978
1.78k
        case 'a':
9979
          /* Don't print anything for '+' as it is implied.  */
9980
1.78k
          if (arm_decode_field (given, 23, 23) == 0)
9981
1.11k
      func (stream, dis_style_immediate, "-");
9982
1.78k
          break;
9983
9984
15.3k
        case 'c':
9985
15.3k
          if (ifthen_state)
9986
5.65k
      func (stream, dis_style_mnemonic, "%s",
9987
5.65k
            arm_conditional[IFTHEN_COND]);
9988
15.3k
          break;
9989
9990
7.44k
        case 'd':
9991
7.44k
          print_mve_vld_str_addr (info, given, insn->mve_op);
9992
7.44k
          break;
9993
9994
9.99k
        case 'i':
9995
9.99k
          {
9996
9.99k
      long mve_mask = mve_extract_pred_mask (given);
9997
9.99k
      func (stream, dis_style_mnemonic, "%s",
9998
9.99k
            mve_predicatenames[mve_mask]);
9999
9.99k
          }
10000
9.99k
          break;
10001
10002
4.31k
        case 'j':
10003
4.31k
          {
10004
4.31k
      unsigned int imm5 = 0;
10005
4.31k
      imm5 |= arm_decode_field (given, 6, 7);
10006
4.31k
      imm5 |= (arm_decode_field (given, 12, 14) << 2);
10007
4.31k
      func (stream, dis_style_immediate, "#%u",
10008
4.31k
            (imm5 == 0) ? 32 : imm5);
10009
4.31k
          }
10010
4.31k
          break;
10011
10012
541
        case 'k':
10013
541
          func (stream, dis_style_immediate, "#%u",
10014
541
          (arm_decode_field (given, 7, 7) == 0) ? 64 : 48);
10015
541
          break;
10016
10017
11.7k
        case 'n':
10018
11.7k
          print_vec_condition (info, given, insn->mve_op);
10019
11.7k
          break;
10020
10021
4.05k
        case 'o':
10022
4.05k
          if (arm_decode_field (given, 0, 0) == 1)
10023
2.67k
      {
10024
2.67k
        unsigned long size
10025
2.67k
          = arm_decode_field (given, 4, 4)
10026
2.67k
            | (arm_decode_field (given, 6, 6) << 1);
10027
10028
2.67k
        func (stream, dis_style_text, ", ");
10029
2.67k
        func (stream, dis_style_sub_mnemonic, "uxtw ");
10030
2.67k
        func (stream, dis_style_immediate, "#%lu", size);
10031
2.67k
      }
10032
4.05k
          break;
10033
10034
3.27k
        case 'm':
10035
3.27k
          print_mve_rounding_mode (info, given, insn->mve_op);
10036
3.27k
          break;
10037
10038
7.42k
        case 's':
10039
7.42k
          print_mve_vcvt_size (info, given, insn->mve_op);
10040
7.42k
          break;
10041
10042
26.7k
        case 'u':
10043
26.7k
          {
10044
26.7k
      unsigned long op1 = arm_decode_field (given, 21, 22);
10045
10046
26.7k
      if ((insn->mve_op == MVE_VMOV_VEC_LANE_TO_GP))
10047
4.22k
        {
10048
          /* Check for signed.  */
10049
4.22k
          if (arm_decode_field (given, 23, 23) == 0)
10050
1.16k
            {
10051
        /* We don't print 's' for S32.  */
10052
1.16k
        if ((arm_decode_field (given, 5, 6) == 0)
10053
1.16k
            && ((op1 == 0) || (op1 == 1)))
10054
707
          ;
10055
456
        else
10056
456
          func (stream, dis_style_mnemonic, "s");
10057
1.16k
            }
10058
3.06k
          else
10059
3.06k
            func (stream, dis_style_mnemonic, "u");
10060
4.22k
        }
10061
22.5k
      else
10062
22.5k
        {
10063
22.5k
          if (arm_decode_field (given, 28, 28) == 0)
10064
12.2k
            func (stream, dis_style_mnemonic, "s");
10065
10.3k
          else
10066
10.3k
            func (stream, dis_style_mnemonic, "u");
10067
22.5k
        }
10068
26.7k
          }
10069
26.7k
          break;
10070
10071
85.3k
        case 'v':
10072
85.3k
          print_instruction_predicate (info);
10073
85.3k
          break;
10074
10075
2.78k
        case 'w':
10076
2.78k
          if (arm_decode_field (given, 21, 21) == 1)
10077
1.67k
      func (stream, dis_style_text, "!");
10078
2.78k
          break;
10079
10080
2.23k
        case 'B':
10081
2.23k
          print_mve_register_blocks (info, given, insn->mve_op);
10082
2.23k
          break;
10083
10084
7.39k
        case 'E':
10085
          /* SIMD encoded constant for mov, mvn, vorr, vbic.  */
10086
10087
7.39k
          print_simd_imm8 (info, given, 28, insn);
10088
7.39k
          break;
10089
10090
6.24k
        case 'N':
10091
6.24k
          print_mve_vmov_index (info, given);
10092
6.24k
          break;
10093
10094
8.83k
        case 'T':
10095
8.83k
          if (arm_decode_field (given, 12, 12) == 0)
10096
5.02k
      func (stream, dis_style_mnemonic, "b");
10097
3.81k
          else
10098
3.81k
      func (stream, dis_style_mnemonic, "t");
10099
8.83k
          break;
10100
10101
2.75k
        case 'X':
10102
2.75k
          if (arm_decode_field (given, 12, 12) == 1)
10103
853
      func (stream, dis_style_mnemonic, "x");
10104
2.75k
          break;
10105
10106
333k
        case '0': case '1': case '2': case '3': case '4':
10107
373k
        case '5': case '6': case '7': case '8': case '9':
10108
373k
          {
10109
373k
      int width;
10110
373k
      unsigned long value;
10111
10112
373k
      c = arm_decode_bitfield (c, given, &value, &width);
10113
10114
373k
      switch (*c)
10115
373k
        {
10116
10.0k
        case 'Z':
10117
10.0k
          if (value == 13)
10118
1.57k
            is_unpredictable = true;
10119
8.50k
          else if (value == 15)
10120
3.14k
            func (stream, dis_style_register, "zr");
10121
5.36k
          else
10122
5.36k
            func (stream, dis_style_register, "%s",
10123
5.36k
            arm_regnames[value]);
10124
10.0k
          break;
10125
10126
1.42k
        case 'c':
10127
1.42k
          func (stream, dis_style_sub_mnemonic, "%s",
10128
1.42k
          arm_conditional[value]);
10129
1.42k
          break;
10130
10131
1.56k
        case 'C':
10132
1.56k
          value ^= 1;
10133
1.56k
          func (stream, dis_style_sub_mnemonic, "%s",
10134
1.56k
          arm_conditional[value]);
10135
1.56k
          break;
10136
10137
7.77k
        case 'S':
10138
7.77k
          if (value == 13 || value == 15)
10139
1.68k
            is_unpredictable = true;
10140
6.09k
          else
10141
6.09k
            func (stream, dis_style_register, "%s",
10142
6.09k
            arm_regnames[value]);
10143
7.77k
          break;
10144
10145
85.3k
        case 's':
10146
85.3k
          print_mve_size (info,
10147
85.3k
              value,
10148
85.3k
              insn->mve_op);
10149
85.3k
          break;
10150
463
        case 'I':
10151
463
          if (value == 1)
10152
246
            func (stream, dis_style_mnemonic, "i");
10153
463
          break;
10154
4.10k
        case 'A':
10155
4.10k
          if (value == 1)
10156
1.17k
            func (stream, dis_style_mnemonic, "a");
10157
4.10k
          break;
10158
8.27k
        case 'h':
10159
8.27k
          {
10160
8.27k
            unsigned int odd_reg = (value << 1) | 1;
10161
8.27k
            func (stream, dis_style_register, "%s",
10162
8.27k
            arm_regnames[odd_reg]);
10163
8.27k
          }
10164
8.27k
          break;
10165
1.78k
        case 'i':
10166
1.78k
          {
10167
1.78k
            unsigned long imm
10168
1.78k
        = arm_decode_field (given, 0, 6);
10169
1.78k
            unsigned long mod_imm = imm;
10170
10171
1.78k
            switch (insn->mve_op)
10172
1.78k
        {
10173
606
        case MVE_VLDRW_GATHER_T5:
10174
962
        case MVE_VSTRW_SCATTER_T5:
10175
962
          mod_imm = mod_imm << 2;
10176
962
          break;
10177
572
        case MVE_VSTRD_SCATTER_T6:
10178
824
        case MVE_VLDRD_GATHER_T6:
10179
824
          mod_imm = mod_imm << 3;
10180
824
          break;
10181
10182
0
        default:
10183
0
          break;
10184
1.78k
        }
10185
10186
1.78k
            func (stream, dis_style_immediate, "%lu",
10187
1.78k
            mod_imm);
10188
1.78k
          }
10189
0
          break;
10190
3.06k
        case 'k':
10191
3.06k
          func (stream, dis_style_immediate, "%lu",
10192
3.06k
          64 - value);
10193
3.06k
          break;
10194
10.6k
        case 'l':
10195
10.6k
          {
10196
10.6k
            unsigned int even_reg = value << 1;
10197
10.6k
            func (stream, dis_style_register, "%s",
10198
10.6k
            arm_regnames[even_reg]);
10199
10.6k
          }
10200
10.6k
          break;
10201
2.26k
        case 'u':
10202
2.26k
          switch (value)
10203
2.26k
            {
10204
205
            case 0:
10205
205
        func (stream, dis_style_immediate, "1");
10206
205
        break;
10207
214
            case 1:
10208
214
        func (stream, dis_style_immediate, "2");
10209
214
        break;
10210
1.35k
            case 2:
10211
1.35k
        func (stream, dis_style_immediate, "4");
10212
1.35k
        break;
10213
490
            case 3:
10214
490
        func (stream, dis_style_immediate, "8");
10215
490
        break;
10216
0
            default:
10217
0
        break;
10218
2.26k
            }
10219
2.26k
          break;
10220
3.83k
        case 'o':
10221
3.83k
          print_mve_rotate (info, value, width);
10222
3.83k
          break;
10223
35.4k
        case 'r':
10224
35.4k
          func (stream, dis_style_register, "%s",
10225
35.4k
          arm_regnames[value]);
10226
35.4k
          break;
10227
9.80k
        case 'd':
10228
9.80k
          if (insn->mve_op == MVE_VQSHL_T2
10229
9.80k
        || insn->mve_op == MVE_VQSHLU_T3
10230
9.80k
        || insn->mve_op == MVE_VRSHR
10231
9.80k
        || insn->mve_op == MVE_VRSHRN
10232
9.80k
        || insn->mve_op == MVE_VSHL_T1
10233
9.80k
        || insn->mve_op == MVE_VSHLL_T1
10234
9.80k
        || insn->mve_op == MVE_VSHR
10235
9.80k
        || insn->mve_op == MVE_VSHRN
10236
9.80k
        || insn->mve_op == MVE_VSLI
10237
9.80k
        || insn->mve_op == MVE_VSRI)
10238
4.86k
            print_mve_shift_n (info, given, insn->mve_op);
10239
4.94k
          else if (insn->mve_op == MVE_VSHLL_T2)
10240
423
            {
10241
423
        switch (value)
10242
423
          {
10243
222
          case 0x00:
10244
222
            func (stream, dis_style_immediate, "8");
10245
222
            break;
10246
201
          case 0x01:
10247
201
            func (stream, dis_style_immediate, "16");
10248
201
            break;
10249
0
          case 0x10:
10250
0
            print_mve_undefined (info, UNDEF_SIZE_0);
10251
0
            break;
10252
0
          default:
10253
0
            assert (0);
10254
0
            break;
10255
423
          }
10256
423
            }
10257
4.52k
          else
10258
4.52k
            {
10259
4.52k
        if (insn->mve_op == MVE_VSHLC && value == 0)
10260
194
          value = 32;
10261
4.52k
        func (stream, base_style, "%ld", value);
10262
4.52k
        value_in_comment = value;
10263
4.52k
            }
10264
9.80k
          break;
10265
9.80k
        case 'F':
10266
196
          func (stream, dis_style_register, "s%ld", value);
10267
196
          break;
10268
186k
        case 'Q':
10269
186k
          if (value & 0x8)
10270
87.9k
            func (stream, dis_style_text,
10271
87.9k
            "<illegal reg q%ld.5>", value);
10272
98.8k
          else
10273
98.8k
            func (stream, dis_style_register, "q%ld", value);
10274
186k
          break;
10275
228
        case 'x':
10276
228
          func (stream, dis_style_immediate,
10277
228
          "0x%08lx", value);
10278
228
          break;
10279
0
        default:
10280
0
          abort ();
10281
373k
        }
10282
373k
      break;
10283
373k
          default:
10284
0
      abort ();
10285
373k
          }
10286
640k
        }
10287
640k
    }
10288
1.31M
        else
10289
1.31M
    {
10290
1.31M
      if (*c == '@')
10291
228
        base_style = dis_style_comment_start;
10292
10293
1.31M
      if (*c == '\t')
10294
115k
        base_style = dis_style_text;
10295
10296
1.31M
      func (stream, base_style, "%c", *c);
10297
1.31M
    }
10298
1.95M
      }
10299
10300
116k
    if (value_in_comment > 32 || value_in_comment < -16)
10301
0
      func (stream, dis_style_comment_start, "\t@ 0x%lx",
10302
0
      value_in_comment);
10303
10304
116k
    if (is_unpredictable)
10305
25.5k
      print_mve_unpredictable (info, unpredictable_cond);
10306
10307
116k
    if (is_undefined)
10308
13.7k
      print_mve_undefined (info, undefined_cond);
10309
10310
116k
    if (!vpt_block_state.in_vpt_block
10311
116k
        && !ifthen_state
10312
116k
        && is_vpt_instruction (given))
10313
3.47k
      mark_inside_vpt_block (given);
10314
112k
    else if (vpt_block_state.in_vpt_block)
10315
9.26k
      update_vpt_block_state ();
10316
10317
116k
    return true;
10318
116k
  }
10319
59.7M
    }
10320
201k
  return false;
10321
318k
}
10322
10323
10324
/* Return the name of a v7A special register.  */
10325
10326
static const char *
10327
banked_regname (unsigned reg)
10328
37.3k
{
10329
37.3k
  switch (reg)
10330
37.3k
    {
10331
357
      case 15: return "CPSR";
10332
459
      case 32: return "R8_usr";
10333
442
      case 33: return "R9_usr";
10334
1.19k
      case 34: return "R10_usr";
10335
453
      case 35: return "R11_usr";
10336
675
      case 36: return "R12_usr";
10337
284
      case 37: return "SP_usr";
10338
220
      case 38: return "LR_usr";
10339
220
      case 40: return "R8_fiq";
10340
409
      case 41: return "R9_fiq";
10341
282
      case 42: return "R10_fiq";
10342
267
      case 43: return "R11_fiq";
10343
238
      case 44: return "R12_fiq";
10344
231
      case 45: return "SP_fiq";
10345
303
      case 46: return "LR_fiq";
10346
402
      case 48: return "LR_irq";
10347
659
      case 49: return "SP_irq";
10348
294
      case 50: return "LR_svc";
10349
367
      case 51: return "SP_svc";
10350
442
      case 52: return "LR_abt";
10351
325
      case 53: return "SP_abt";
10352
350
      case 54: return "LR_und";
10353
278
      case 55: return "SP_und";
10354
296
      case 60: return "LR_mon";
10355
307
      case 61: return "SP_mon";
10356
429
      case 62: return "ELR_hyp";
10357
638
      case 63: return "SP_hyp";
10358
270
      case 79: return "SPSR";
10359
236
      case 110: return "SPSR_fiq";
10360
304
      case 112: return "SPSR_irq";
10361
301
      case 114: return "SPSR_svc";
10362
456
      case 116: return "SPSR_abt";
10363
590
      case 118: return "SPSR_und";
10364
427
      case 124: return "SPSR_mon";
10365
305
      case 126: return "SPSR_hyp";
10366
23.5k
      default: return NULL;
10367
37.3k
    }
10368
37.3k
}
10369
10370
/* Return the name of the DMB/DSB option.  */
10371
static const char *
10372
data_barrier_option (unsigned option)
10373
1.27k
{
10374
1.27k
  switch (option & 0xf)
10375
1.27k
    {
10376
10
    case 0xf: return "sy";
10377
309
    case 0xe: return "st";
10378
82
    case 0xd: return "ld";
10379
8
    case 0xb: return "ish";
10380
4
    case 0xa: return "ishst";
10381
54
    case 0x9: return "ishld";
10382
4
    case 0x7: return "un";
10383
43
    case 0x6: return "unst";
10384
63
    case 0x5: return "nshld";
10385
5
    case 0x3: return "osh";
10386
24
    case 0x2: return "oshst";
10387
3
    case 0x1: return "oshld";
10388
670
    default:  return NULL;
10389
1.27k
    }
10390
1.27k
}
10391
10392
/* Print one ARM instruction from PC on INFO->STREAM.  */
10393
10394
static void
10395
print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
10396
3.96M
{
10397
3.96M
  const struct opcode32 *insn;
10398
3.96M
  void *stream = info->stream;
10399
3.96M
  fprintf_styled_ftype func = info->fprintf_styled_func;
10400
3.96M
  struct arm_private_data *private_data = info->private_data;
10401
3.96M
  enum disassembler_style base_style = dis_style_mnemonic;
10402
3.96M
  enum disassembler_style old_base_style = base_style;
10403
10404
3.96M
  if (print_insn_coprocessor (pc, info, given, false))
10405
111k
    return;
10406
10407
3.85M
  if (print_insn_neon (info, given, false))
10408
48.0k
    return;
10409
10410
3.80M
  if (print_insn_generic_coprocessor (pc, info, given, false))
10411
380k
    return;
10412
10413
939M
  for (insn = arm_opcodes; insn->assembler; insn++)
10414
939M
    {
10415
939M
      if ((given & insn->mask) != insn->value)
10416
936M
  continue;
10417
10418
3.72M
      if (! ARM_CPU_HAS_FEATURE (insn->arch, private_data->features))
10419
63.7k
  continue;
10420
10421
      /* Special case: an instruction with all bits set in the condition field
10422
   (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
10423
   or by the catchall at the end of the table.  */
10424
3.66M
      if ((given & 0xF0000000) != 0xF0000000
10425
3.66M
    || (insn->mask & 0xF0000000) == 0xF0000000
10426
3.66M
    || (insn->mask == 0 && insn->value == 0))
10427
3.39M
  {
10428
3.39M
    unsigned long u_reg = 16;
10429
3.39M
    unsigned long U_reg = 16;
10430
3.39M
    bool is_unpredictable = false;
10431
3.39M
    signed long value_in_comment = 0;
10432
3.39M
    const char *c;
10433
10434
49.0M
    for (c = insn->assembler; *c; c++)
10435
45.6M
      {
10436
45.6M
        if (*c == '%')
10437
13.5M
    {
10438
13.5M
      bool allow_unpredictable = false;
10439
10440
13.5M
      switch (*++c)
10441
13.5M
        {
10442
27.4k
        case '{':
10443
27.4k
          ++c;
10444
27.4k
          if (*c == '\0')
10445
0
      abort ();
10446
27.4k
          old_base_style = base_style;
10447
27.4k
          base_style = decode_base_style (*c);
10448
27.4k
          ++c;
10449
27.4k
          if (*c != ':')
10450
0
      abort ();
10451
27.4k
          break;
10452
10453
27.4k
        case '}':
10454
27.4k
          base_style = old_base_style;
10455
27.4k
          break;
10456
10457
0
        case '%':
10458
0
          func (stream, base_style, "%%");
10459
0
          break;
10460
10461
525k
        case 'a':
10462
525k
          value_in_comment = print_arm_address (pc, info, given);
10463
525k
          break;
10464
10465
780
        case 'P':
10466
          /* Set P address bit and use normal address
10467
       printing routine.  */
10468
780
          value_in_comment = print_arm_address (pc, info, given | (1 << P_BIT));
10469
780
          break;
10470
10471
23.4k
        case 'S':
10472
23.4k
          allow_unpredictable = true;
10473
          /* Fall through.  */
10474
119k
        case 's':
10475
119k
                      if ((given & 0x004f0000) == 0x004f0000)
10476
9.49k
      {
10477
                          /* PC relative with immediate offset.  */
10478
9.49k
        bfd_vma offset = ((given & 0xf00) >> 4) | (given & 0xf);
10479
10480
9.49k
        if (PRE_BIT_SET)
10481
2.57k
          {
10482
            /* Elide positive zero offset.  */
10483
2.57k
            if (offset || NEGATIVE_BIT_SET)
10484
2.43k
        {
10485
2.43k
          func (stream, dis_style_text, "[");
10486
2.43k
          func (stream, dis_style_register, "pc");
10487
2.43k
          func (stream, dis_style_text, ", ");
10488
2.43k
          func (stream, dis_style_immediate, "#%s%d",
10489
2.43k
          (NEGATIVE_BIT_SET ? "-" : ""),
10490
2.43k
          (int) offset);
10491
2.43k
          func (stream, dis_style_text, "]");
10492
2.43k
        }
10493
136
            else
10494
136
        {
10495
136
          func (stream, dis_style_text, "[");
10496
136
          func (stream, dis_style_register, "pc");
10497
136
          func (stream, dis_style_text, "]");
10498
136
        }
10499
2.57k
            if (NEGATIVE_BIT_SET)
10500
723
        offset = -offset;
10501
2.57k
            func (stream, dis_style_comment_start, "\t@ ");
10502
2.57k
            info->print_address_func (offset + pc + 8, info);
10503
2.57k
          }
10504
6.91k
        else
10505
6.91k
          {
10506
            /* Always show the offset.  */
10507
6.91k
            func (stream, dis_style_text, "[");
10508
6.91k
            func (stream, dis_style_register, "pc");
10509
6.91k
            func (stream, dis_style_text, "], ");
10510
6.91k
            func (stream, dis_style_immediate, "#%s%d",
10511
6.91k
            NEGATIVE_BIT_SET ? "-" : "", (int) offset);
10512
6.91k
            if (! allow_unpredictable)
10513
1.11k
        is_unpredictable = true;
10514
6.91k
          }
10515
9.49k
      }
10516
109k
          else
10517
109k
      {
10518
109k
        int offset = ((given & 0xf00) >> 4) | (given & 0xf);
10519
10520
109k
        func (stream, dis_style_text, "[");
10521
109k
        func (stream, dis_style_register, "%s",
10522
109k
        arm_regnames[(given >> 16) & 0xf]);
10523
10524
109k
        if (PRE_BIT_SET)
10525
24.4k
          {
10526
24.4k
            if (IMMEDIATE_BIT_SET)
10527
15.9k
        {
10528
          /* Elide offset for non-writeback
10529
             positive zero.  */
10530
15.9k
          if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET
10531
15.9k
              || offset)
10532
15.7k
            {
10533
15.7k
              func (stream, dis_style_text, ", ");
10534
15.7k
              func (stream, dis_style_immediate,
10535
15.7k
              "#%s%d",
10536
15.7k
              (NEGATIVE_BIT_SET ? "-" : ""),
10537
15.7k
              offset);
10538
15.7k
            }
10539
10540
15.9k
          if (NEGATIVE_BIT_SET)
10541
6.58k
            offset = -offset;
10542
10543
15.9k
          value_in_comment = offset;
10544
15.9k
        }
10545
8.54k
            else
10546
8.54k
        {
10547
          /* Register Offset or Register Pre-Indexed.  */
10548
8.54k
          func (stream, dis_style_text, ", %s",
10549
8.54k
          NEGATIVE_BIT_SET ? "-" : "");
10550
8.54k
          func (stream, dis_style_register, "%s",
10551
8.54k
          arm_regnames[given & 0xf]);
10552
10553
          /* Writing back to the register that is the source/
10554
             destination of the load/store is unpredictable.  */
10555
8.54k
          if (! allow_unpredictable
10556
8.54k
              && WRITEBACK_BIT_SET
10557
8.54k
              && ((given & 0xf) == ((given >> 12) & 0xf)))
10558
689
            is_unpredictable = true;
10559
8.54k
        }
10560
10561
24.4k
            func (stream, dis_style_text, "]%s",
10562
24.4k
            WRITEBACK_BIT_SET ? "!" : "");
10563
24.4k
          }
10564
85.2k
        else
10565
85.2k
          {
10566
85.2k
            if (IMMEDIATE_BIT_SET)
10567
27.8k
        {
10568
          /* Immediate Post-indexed.  */
10569
          /* PR 10924: Offset must be printed, even if it is zero.  */
10570
27.8k
          func (stream, dis_style_text, "], ");
10571
27.8k
          func (stream, dis_style_immediate, "#%s%d",
10572
27.8k
          NEGATIVE_BIT_SET ? "-" : "", offset);
10573
27.8k
          if (NEGATIVE_BIT_SET)
10574
10.9k
            offset = -offset;
10575
27.8k
          value_in_comment = offset;
10576
27.8k
        }
10577
57.4k
            else
10578
57.4k
        {
10579
          /* Register Post-indexed.  */
10580
57.4k
          func (stream, dis_style_text, "], %s",
10581
57.4k
          NEGATIVE_BIT_SET ? "-" : "");
10582
57.4k
          func (stream, dis_style_register, "%s",
10583
57.4k
          arm_regnames[given & 0xf]);
10584
10585
          /* Writing back to the register that is the source/
10586
             destination of the load/store is unpredictable.  */
10587
57.4k
          if (! allow_unpredictable
10588
57.4k
              && (given & 0xf) == ((given >> 12) & 0xf))
10589
7.64k
            is_unpredictable = true;
10590
57.4k
        }
10591
10592
85.2k
            if (! allow_unpredictable)
10593
67.5k
        {
10594
          /* Writeback is automatically implied by post- addressing.
10595
             Setting the W bit is unnecessary and ARM specify it as
10596
             being unpredictable.  */
10597
67.5k
          if (WRITEBACK_BIT_SET
10598
              /* Specifying the PC register as the post-indexed
10599
           registers is also unpredictable.  */
10600
67.5k
              || (! IMMEDIATE_BIT_SET && ((given & 0xf) == 0xf)))
10601
31.0k
            is_unpredictable = true;
10602
67.5k
        }
10603
85.2k
          }
10604
109k
      }
10605
119k
          break;
10606
10607
276k
        case 'b':
10608
276k
          {
10609
276k
      bfd_vma disp = (((given & 0xffffff) ^ 0x800000) - 0x800000);
10610
276k
      bfd_vma target = disp * 4 + pc + 8;
10611
276k
      info->print_address_func (target, info);
10612
10613
      /* Fill in instruction information.  */
10614
276k
      info->insn_info_valid = 1;
10615
276k
      info->insn_type = dis_branch;
10616
276k
      info->target = target;
10617
276k
          }
10618
276k
          break;
10619
10620
2.91M
        case 'c':
10621
2.91M
          if (((given >> 28) & 0xf) != 0xe)
10622
2.74M
      func (stream, dis_style_mnemonic, "%s",
10623
2.74M
            arm_conditional [(given >> 28) & 0xf]);
10624
2.91M
          break;
10625
10626
366k
        case 'm':
10627
366k
          {
10628
366k
      int started = 0;
10629
366k
      int reg;
10630
10631
366k
      func (stream, dis_style_text, "{");
10632
6.23M
      for (reg = 0; reg < 16; reg++)
10633
5.86M
        if ((given & (1 << reg)) != 0)
10634
2.41M
          {
10635
2.41M
            if (started)
10636
2.07M
        func (stream, dis_style_text, ", ");
10637
2.41M
            started = 1;
10638
2.41M
            func (stream, dis_style_register, "%s",
10639
2.41M
            arm_regnames[reg]);
10640
2.41M
          }
10641
366k
      func (stream, dis_style_text, "}");
10642
366k
      if (! started)
10643
29.3k
        is_unpredictable = true;
10644
366k
          }
10645
366k
          break;
10646
10647
3.20k
        case 'q':
10648
3.20k
          arm_decode_shift (given, func, stream, false);
10649
3.20k
          break;
10650
10651
1.33M
        case 'o':
10652
1.33M
          if ((given & 0x02000000) != 0)
10653
286k
      {
10654
286k
        unsigned int rotate = (given & 0xf00) >> 7;
10655
286k
        unsigned int immed = (given & 0xff);
10656
286k
        unsigned int a, i;
10657
10658
286k
        a = (immed << ((32 - rotate) & 31)
10659
286k
             | immed >> rotate) & 0xffffffff;
10660
        /* If there is another encoding with smaller rotate,
10661
           the rotate should be specified directly.  */
10662
1.73M
        for (i = 0; i < 32; i += 2)
10663
1.73M
          if ((a << i | a >> ((32 - i) & 31)) <= 0xff)
10664
286k
            break;
10665
10666
286k
        if (i != rotate)
10667
72.6k
          {
10668
72.6k
            func (stream, dis_style_immediate, "#%d", immed);
10669
72.6k
            func (stream, dis_style_text, ", ");
10670
72.6k
            func (stream, dis_style_immediate, "%d", rotate);
10671
72.6k
          }
10672
213k
        else
10673
213k
          func (stream, dis_style_immediate, "#%d", a);
10674
286k
        value_in_comment = a;
10675
286k
      }
10676
1.04M
          else
10677
1.04M
      arm_decode_shift (given, func, stream, true);
10678
1.33M
          break;
10679
10680
132k
        case 'p':
10681
132k
          if ((given & 0x0000f000) == 0x0000f000)
10682
6.15k
      {
10683
6.15k
        arm_feature_set arm_ext_v6 =
10684
6.15k
          ARM_FEATURE_CORE_LOW (ARM_EXT_V6);
10685
10686
        /* The p-variants of tst/cmp/cmn/teq are the pre-V6
10687
           mechanism for setting PSR flag bits.  They are
10688
           obsolete in V6 onwards.  */
10689
6.15k
        if (! ARM_CPU_HAS_FEATURE (private_data->features, \
10690
6.15k
                 arm_ext_v6))
10691
442
          func (stream, dis_style_mnemonic, "p");
10692
5.71k
        else
10693
5.71k
          is_unpredictable = true;
10694
6.15k
      }
10695
132k
          break;
10696
10697
430k
        case 't':
10698
430k
          if ((given & 0x01200000) == 0x00200000)
10699
109k
      func (stream, dis_style_mnemonic, "t");
10700
430k
          break;
10701
10702
0
        case 'A':
10703
0
          {
10704
0
      int offset = given & 0xff;
10705
10706
0
      value_in_comment = offset * 4;
10707
0
      if (NEGATIVE_BIT_SET)
10708
0
        value_in_comment = - value_in_comment;
10709
10710
0
      func (stream, dis_style_text, "[%s",
10711
0
            arm_regnames [(given >> 16) & 0xf]);
10712
10713
0
      if (PRE_BIT_SET)
10714
0
        {
10715
0
          if (offset)
10716
0
            func (stream, dis_style_text, ", #%d]%s",
10717
0
            (int) value_in_comment,
10718
0
            WRITEBACK_BIT_SET ? "!" : "");
10719
0
          else
10720
0
            func (stream, dis_style_text, "]");
10721
0
        }
10722
0
      else
10723
0
        {
10724
0
          func (stream, dis_style_text, "]");
10725
10726
0
          if (WRITEBACK_BIT_SET)
10727
0
            {
10728
0
        if (offset)
10729
0
          func (stream, dis_style_text,
10730
0
          ", #%d", (int) value_in_comment);
10731
0
            }
10732
0
          else
10733
0
            {
10734
0
        func (stream, dis_style_text,
10735
0
              ", {%d}", (int) offset);
10736
0
        value_in_comment = offset;
10737
0
            }
10738
0
        }
10739
0
          }
10740
0
          break;
10741
10742
30.6k
        case 'B':
10743
          /* Print ARM V5 BLX(1) address: pc+25 bits.  */
10744
30.6k
          {
10745
30.6k
      bfd_vma address;
10746
30.6k
      bfd_vma offset = 0;
10747
10748
30.6k
      if (! NEGATIVE_BIT_SET)
10749
        /* Is signed, hi bits should be ones.  */
10750
21.5k
        offset = (-1) ^ 0x00ffffff;
10751
10752
      /* Offset is (SignExtend(offset field)<<2).  */
10753
30.6k
      offset += given & 0x00ffffff;
10754
30.6k
      offset <<= 2;
10755
30.6k
      address = offset + pc + 8;
10756
10757
30.6k
      if (given & 0x01000000)
10758
        /* H bit allows addressing to 2-byte boundaries.  */
10759
19.3k
        address += 2;
10760
10761
30.6k
            info->print_address_func (address, info);
10762
10763
      /* Fill in instruction information.  */
10764
30.6k
      info->insn_info_valid = 1;
10765
30.6k
      info->insn_type = dis_branch;
10766
30.6k
      info->target = address;
10767
30.6k
          }
10768
30.6k
          break;
10769
10770
5.14k
        case 'C':
10771
5.14k
          if ((given & 0x02000200) == 0x200)
10772
3.08k
      {
10773
3.08k
        const char * name;
10774
3.08k
        unsigned sysm = (given & 0x004f0000) >> 16;
10775
10776
3.08k
        sysm |= (given & 0x300) >> 4;
10777
3.08k
        name = banked_regname (sysm);
10778
10779
3.08k
        if (name != NULL)
10780
2.46k
          func (stream, dis_style_register, "%s", name);
10781
613
        else
10782
613
          func (stream, dis_style_text,
10783
613
          "(UNDEF: %lu)", (unsigned long) sysm);
10784
3.08k
      }
10785
2.06k
          else
10786
2.06k
      {
10787
2.06k
        func (stream, dis_style_register, "%cPSR_",
10788
2.06k
        (given & 0x00400000) ? 'S' : 'C');
10789
10790
2.06k
        if (given & 0x80000)
10791
1.33k
          func (stream, dis_style_register, "f");
10792
2.06k
        if (given & 0x40000)
10793
868
          func (stream, dis_style_register, "s");
10794
2.06k
        if (given & 0x20000)
10795
1.17k
          func (stream, dis_style_register, "x");
10796
2.06k
        if (given & 0x10000)
10797
1.10k
          func (stream, dis_style_register, "c");
10798
2.06k
      }
10799
5.14k
          break;
10800
10801
1.11k
        case 'U':
10802
1.11k
          if ((given & 0xf0) == 0x60)
10803
472
      {
10804
472
        switch (given & 0xf)
10805
472
          {
10806
208
          case 0xf:
10807
208
            func (stream, dis_style_sub_mnemonic, "sy");
10808
208
            break;
10809
264
          default:
10810
264
            func (stream, dis_style_immediate, "#%d",
10811
264
            (int) given & 0xf);
10812
264
            break;
10813
472
          }
10814
472
      }
10815
640
          else
10816
640
      {
10817
640
        const char * opt = data_barrier_option (given & 0xf);
10818
640
        if (opt != NULL)
10819
309
          func (stream, dis_style_sub_mnemonic, "%s", opt);
10820
331
        else
10821
331
          func (stream, dis_style_immediate,
10822
331
          "#%d", (int) given & 0xf);
10823
640
      }
10824
1.11k
          break;
10825
10826
7.16M
        case '0': case '1': case '2': case '3': case '4':
10827
7.28M
        case '5': case '6': case '7': case '8': case '9':
10828
7.28M
          {
10829
7.28M
      int width;
10830
7.28M
      unsigned long value;
10831
10832
7.28M
      c = arm_decode_bitfield (c, given, &value, &width);
10833
10834
7.28M
      switch (*c)
10835
7.28M
        {
10836
1.21M
        case 'R':
10837
1.21M
          if (value == 15)
10838
75.2k
            is_unpredictable = true;
10839
          /* Fall through.  */
10840
3.72M
        case 'r':
10841
3.72M
        case 'T':
10842
          /* We want register + 1 when decoding T.  */
10843
3.72M
          if (*c == 'T')
10844
444
            value = (value + 1) & 0xf;
10845
10846
3.72M
          if (c[1] == 'u')
10847
22.4k
            {
10848
        /* Eat the 'u' character.  */
10849
22.4k
        ++ c;
10850
10851
22.4k
        if (u_reg == value)
10852
1.11k
          is_unpredictable = true;
10853
22.4k
        u_reg = value;
10854
22.4k
            }
10855
3.72M
          if (c[1] == 'U')
10856
1.40k
            {
10857
        /* Eat the 'U' character.  */
10858
1.40k
        ++ c;
10859
10860
1.40k
        if (U_reg == value)
10861
543
          is_unpredictable = true;
10862
1.40k
        U_reg = value;
10863
1.40k
            }
10864
3.72M
          func (stream, dis_style_register, "%s",
10865
3.72M
          arm_regnames[value]);
10866
3.72M
          break;
10867
13.6k
        case 'd':
10868
13.6k
          func (stream, base_style, "%ld", value);
10869
13.6k
          value_in_comment = value;
10870
13.6k
          break;
10871
0
        case 'b':
10872
0
          func (stream, dis_style_immediate,
10873
0
          "%ld", value * 8);
10874
0
          value_in_comment = value * 8;
10875
0
          break;
10876
5.61k
        case 'W':
10877
5.61k
          func (stream, dis_style_immediate,
10878
5.61k
          "%ld", value + 1);
10879
5.61k
          value_in_comment = value + 1;
10880
5.61k
          break;
10881
621k
        case 'x':
10882
621k
          func (stream, dis_style_immediate,
10883
621k
          "0x%08lx", value);
10884
10885
          /* Some SWI instructions have special
10886
             meanings.  */
10887
621k
          if ((given & 0x0fffffff) == 0x0FF00000)
10888
139
            func (stream, dis_style_comment_start,
10889
139
            "\t@ IMB");
10890
621k
          else if ((given & 0x0fffffff) == 0x0FF00001)
10891
218
            func (stream, dis_style_comment_start,
10892
218
            "\t@ IMBRange");
10893
621k
          break;
10894
1.01k
        case 'X':
10895
1.01k
          func (stream, dis_style_immediate,
10896
1.01k
          "%01lx", value & 0xf);
10897
1.01k
          value_in_comment = value;
10898
1.01k
          break;
10899
0
        case '`':
10900
0
          c++;
10901
0
          if (value == 0)
10902
0
            func (stream, dis_style_text, "%c", *c);
10903
0
          break;
10904
2.26M
        case '\'':
10905
2.26M
          c++;
10906
2.26M
          if (value == ((1ul << width) - 1))
10907
797k
            func (stream, base_style, "%c", *c);
10908
2.26M
          break;
10909
657k
        case '?':
10910
657k
          func (stream, base_style, "%c",
10911
657k
          c[(1 << width) - (int) value]);
10912
657k
          c += 1 << width;
10913
657k
          break;
10914
0
        default:
10915
0
          abort ();
10916
7.28M
        }
10917
7.28M
          }
10918
7.28M
          break;
10919
10920
7.28M
        case 'e':
10921
1.94k
          {
10922
1.94k
      int imm;
10923
10924
1.94k
      imm = (given & 0xf) | ((given & 0xfff00) >> 4);
10925
1.94k
      func (stream, dis_style_immediate, "%d", imm);
10926
1.94k
      value_in_comment = imm;
10927
1.94k
          }
10928
1.94k
          break;
10929
10930
1.80k
        case 'E':
10931
          /* LSB and WIDTH fields of BFI or BFC.  The machine-
10932
       language instruction encodes LSB and MSB.  */
10933
1.80k
          {
10934
1.80k
      long msb = (given & 0x001f0000) >> 16;
10935
1.80k
      long lsb = (given & 0x00000f80) >> 7;
10936
1.80k
      long w = msb - lsb + 1;
10937
10938
1.80k
      if (w > 0)
10939
923
        {
10940
923
          func (stream, dis_style_immediate, "#%lu", lsb);
10941
923
          func (stream, dis_style_text, ", ");
10942
923
          func (stream, dis_style_immediate, "#%lu", w);
10943
923
        }
10944
883
      else
10945
883
        func (stream, dis_style_text,
10946
883
        "(invalid: %lu:%lu)", lsb, msb);
10947
1.80k
          }
10948
1.80k
          break;
10949
10950
22.9k
        case 'R':
10951
          /* Get the PSR/banked register name.  */
10952
22.9k
          {
10953
22.9k
      const char * name;
10954
22.9k
      unsigned sysm = (given & 0x004f0000) >> 16;
10955
10956
22.9k
      sysm |= (given & 0x300) >> 4;
10957
22.9k
      name = banked_regname (sysm);
10958
10959
22.9k
      if (name != NULL)
10960
2.78k
        func (stream, dis_style_register, "%s", name);
10961
20.2k
      else
10962
20.2k
        func (stream, dis_style_text,
10963
20.2k
        "(UNDEF: %lu)", (unsigned long) sysm);
10964
22.9k
          }
10965
22.9k
          break;
10966
10967
38.4k
        case 'V':
10968
          /* 16-bit unsigned immediate from a MOVT or MOVW
10969
       instruction, encoded in bits 0:11 and 15:19.  */
10970
38.4k
          {
10971
38.4k
      long hi = (given & 0x000f0000) >> 4;
10972
38.4k
      long lo = (given & 0x00000fff);
10973
38.4k
      long imm16 = hi | lo;
10974
10975
38.4k
      func (stream, dis_style_immediate, "#%lu", imm16);
10976
38.4k
      value_in_comment = imm16;
10977
38.4k
          }
10978
38.4k
          break;
10979
10980
0
        default:
10981
0
          abort ();
10982
13.5M
        }
10983
13.5M
    }
10984
32.1M
        else
10985
32.1M
    {
10986
10987
32.1M
      if (*c == '@')
10988
446k
        base_style = dis_style_comment_start;
10989
10990
32.1M
      if (*c == '\t')
10991
3.84M
        base_style = dis_style_text;
10992
10993
32.1M
      func (stream, base_style, "%c", *c);
10994
32.1M
    }
10995
45.6M
      }
10996
10997
3.39M
    if (value_in_comment > 32 || value_in_comment < -16)
10998
616k
      func (stream, dis_style_comment_start, "\t@ 0x%lx",
10999
616k
      (value_in_comment & 0xffffffffUL));
11000
11001
3.39M
    if (is_unpredictable)
11002
143k
      func (stream, dis_style_comment_start, UNPREDICTABLE_INSTRUCTION);
11003
11004
3.39M
    return;
11005
3.39M
  }
11006
3.66M
    }
11007
30.8k
  func (stream, dis_style_comment_start, UNKNOWN_INSTRUCTION_32BIT,
11008
30.8k
  (unsigned) given);
11009
30.8k
  return;
11010
3.42M
}
11011
11012
/* Print one 16-bit Thumb instruction from PC on INFO->STREAM.  */
11013
11014
static void
11015
print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
11016
1.20M
{
11017
1.20M
  const struct opcode16 *insn;
11018
1.20M
  void *stream = info->stream;
11019
1.20M
  fprintf_styled_ftype func = info->fprintf_styled_func;
11020
1.20M
  enum disassembler_style base_style = dis_style_mnemonic;
11021
1.20M
  enum disassembler_style old_base_style = base_style;
11022
11023
80.0M
  for (insn = thumb_opcodes; insn->assembler; insn++)
11024
80.0M
    if ((given & insn->mask) == insn->value)
11025
1.20M
      {
11026
1.20M
  signed long value_in_comment = 0;
11027
1.20M
  const char *c = insn->assembler;
11028
11029
17.2M
  for (; *c; c++)
11030
16.0M
    {
11031
16.0M
      int domaskpc = 0;
11032
16.0M
      int domasklr = 0;
11033
11034
16.0M
      if (*c != '%')
11035
10.3M
        {
11036
10.3M
    if (*c == '@')
11037
46.6k
      base_style = dis_style_comment_start;
11038
11039
10.3M
    if (*c == '\t')
11040
1.23M
      base_style = dis_style_text;
11041
11042
10.3M
    func (stream, base_style, "%c", *c);
11043
11044
10.3M
    continue;
11045
10.3M
        }
11046
11047
5.67M
      switch (*++c)
11048
5.67M
        {
11049
769k
    case '{':
11050
769k
      ++c;
11051
769k
      if (*c == '\0')
11052
0
        abort ();
11053
769k
      old_base_style = base_style;
11054
769k
      base_style = decode_base_style (*c);
11055
769k
      ++c;
11056
769k
      if (*c != ':')
11057
0
        abort ();
11058
769k
      break;
11059
11060
769k
    case '}':
11061
769k
      base_style = old_base_style;
11062
769k
      break;
11063
11064
0
        case '%':
11065
0
    func (stream, base_style, "%%");
11066
0
    break;
11067
11068
640k
        case 'c':
11069
640k
    if (ifthen_state)
11070
14.6k
      func (stream, dis_style_mnemonic, "%s",
11071
14.6k
      arm_conditional[IFTHEN_COND]);
11072
640k
    break;
11073
11074
478k
        case 'C':
11075
478k
    if (ifthen_state)
11076
9.04k
      func (stream, dis_style_mnemonic, "%s",
11077
9.04k
      arm_conditional[IFTHEN_COND]);
11078
469k
    else
11079
469k
      func (stream, dis_style_mnemonic, "s");
11080
478k
    break;
11081
11082
17.3k
        case 'I':
11083
17.3k
    {
11084
17.3k
      unsigned int tmp;
11085
11086
17.3k
      ifthen_next_state = given & 0xff;
11087
61.6k
      for (tmp = given << 1; tmp & 0xf; tmp <<= 1)
11088
44.3k
        func (stream, dis_style_mnemonic,
11089
44.3k
        ((given ^ tmp) & 0x10) ? "e" : "t");
11090
17.3k
      func (stream, dis_style_text, "\t");
11091
17.3k
      func (stream, dis_style_sub_mnemonic, "%s",
11092
17.3k
      arm_conditional[(given >> 4) & 0xf]);
11093
17.3k
    }
11094
17.3k
    break;
11095
11096
33.0k
        case 'x':
11097
33.0k
    if (ifthen_next_state)
11098
1.01k
      func (stream, dis_style_comment_start,
11099
1.01k
      "\t@ unpredictable branch in IT block\n");
11100
33.0k
    break;
11101
11102
78.8k
        case 'X':
11103
78.8k
    if (ifthen_state)
11104
8.61k
      func (stream, dis_style_comment_start,
11105
8.61k
      "\t@ unpredictable <IT:%s>",
11106
8.61k
      arm_conditional[IFTHEN_COND]);
11107
78.8k
    break;
11108
11109
49.1k
        case 'S':
11110
49.1k
    {
11111
49.1k
      long reg;
11112
11113
49.1k
      reg = (given >> 3) & 0x7;
11114
49.1k
      if (given & (1 << 6))
11115
38.8k
        reg += 8;
11116
11117
49.1k
      func (stream, dis_style_register, "%s", arm_regnames[reg]);
11118
49.1k
    }
11119
49.1k
    break;
11120
11121
48.2k
        case 'D':
11122
48.2k
    {
11123
48.2k
      long reg;
11124
11125
48.2k
      reg = given & 0x7;
11126
48.2k
      if (given & (1 << 7))
11127
11.8k
        reg += 8;
11128
11129
48.2k
      func (stream, dis_style_register, "%s", arm_regnames[reg]);
11130
48.2k
    }
11131
48.2k
    break;
11132
11133
7.65k
        case 'N':
11134
7.65k
    if (given & (1 << 8))
11135
5.18k
      domasklr = 1;
11136
    /* Fall through.  */
11137
26.0k
        case 'O':
11138
26.0k
    if (*c == 'O' && (given & (1 << 8)))
11139
15.5k
      domaskpc = 1;
11140
    /* Fall through.  */
11141
79.8k
        case 'M':
11142
79.8k
    {
11143
79.8k
      int started = 0;
11144
79.8k
      int reg;
11145
11146
79.8k
      func (stream, dis_style_text, "{");
11147
11148
      /* It would be nice if we could spot
11149
         ranges, and generate the rS-rE format: */
11150
718k
      for (reg = 0; (reg < 8); reg++)
11151
638k
        if ((given & (1 << reg)) != 0)
11152
364k
          {
11153
364k
      if (started)
11154
287k
        func (stream, dis_style_text, ", ");
11155
364k
      started = 1;
11156
364k
      func (stream, dis_style_register, "%s",
11157
364k
            arm_regnames[reg]);
11158
364k
          }
11159
11160
79.8k
      if (domasklr)
11161
5.18k
        {
11162
5.18k
          if (started)
11163
4.90k
      func (stream, dis_style_text, ", ");
11164
5.18k
          started = 1;
11165
5.18k
          func (stream, dis_style_register, "%s",
11166
5.18k
          arm_regnames[14] /* "lr" */);
11167
5.18k
        }
11168
11169
79.8k
      if (domaskpc)
11170
15.5k
        {
11171
15.5k
          if (started)
11172
15.0k
      func (stream, dis_style_text, ", ");
11173
15.5k
          func (stream, dis_style_register, "%s",
11174
15.5k
          arm_regnames[15] /* "pc" */);
11175
15.5k
        }
11176
11177
79.8k
      func (stream, dis_style_text, "}");
11178
79.8k
    }
11179
79.8k
    break;
11180
11181
26.2k
        case 'W':
11182
    /* Print writeback indicator for a LDMIA.  We are doing a
11183
       writeback if the base register is not in the register
11184
       mask.  */
11185
26.2k
    if ((given & (1 << ((given & 0x0700) >> 8))) == 0)
11186
11.0k
      func (stream, dis_style_text, "!");
11187
26.2k
    break;
11188
11189
4.57k
        case 'b':
11190
    /* Print ARM V6T2 CZB address: pc+4+6 bits.  */
11191
4.57k
    {
11192
4.57k
      bfd_vma address = (pc + 4
11193
4.57k
             + ((given & 0x00f8) >> 2)
11194
4.57k
             + ((given & 0x0200) >> 3));
11195
4.57k
      info->print_address_func (address, info);
11196
11197
      /* Fill in instruction information.  */
11198
4.57k
      info->insn_info_valid = 1;
11199
4.57k
      info->insn_type = dis_branch;
11200
4.57k
      info->target = address;
11201
4.57k
    }
11202
4.57k
    break;
11203
11204
52.8k
        case 's':
11205
    /* Right shift immediate -- bits 6..10; 1-31 print
11206
       as themselves, 0 prints as 32.  */
11207
52.8k
    {
11208
52.8k
      long imm = (given & 0x07c0) >> 6;
11209
52.8k
      if (imm == 0)
11210
2.90k
        imm = 32;
11211
52.8k
      func (stream, dis_style_immediate, "#%ld", imm);
11212
52.8k
    }
11213
52.8k
    break;
11214
11215
1.80M
        case '0': case '1': case '2': case '3': case '4':
11216
2.62M
        case '5': case '6': case '7': case '8': case '9':
11217
2.62M
    {
11218
2.62M
      int bitstart = *c++ - '0';
11219
2.62M
      int bitend = 0;
11220
11221
2.66M
      while (*c >= '0' && *c <= '9')
11222
37.3k
        bitstart = (bitstart * 10) + *c++ - '0';
11223
11224
2.62M
      switch (*c)
11225
2.62M
        {
11226
2.58M
        case '-':
11227
2.58M
          {
11228
2.58M
      bfd_vma reg;
11229
11230
2.58M
      c++;
11231
5.95M
      while (*c >= '0' && *c <= '9')
11232
3.36M
        bitend = (bitend * 10) + *c++ - '0';
11233
2.58M
      if (!bitend)
11234
0
        abort ();
11235
2.58M
      reg = given >> bitstart;
11236
2.58M
      reg &= ((bfd_vma) 2 << (bitend - bitstart)) - 1;
11237
11238
2.58M
      switch (*c)
11239
2.58M
        {
11240
1.73M
        case 'r':
11241
1.73M
          func (stream, dis_style_register, "%s",
11242
1.73M
          arm_regnames[reg]);
11243
1.73M
          break;
11244
11245
378k
        case 'd':
11246
378k
          func (stream, dis_style_immediate, "%ld",
11247
378k
          (long) reg);
11248
378k
          value_in_comment = reg;
11249
378k
          break;
11250
11251
61.1k
        case 'H':
11252
61.1k
          func (stream, dis_style_immediate, "%ld",
11253
61.1k
          (long) (reg << 1));
11254
61.1k
          value_in_comment = reg << 1;
11255
61.1k
          break;
11256
11257
217k
        case 'W':
11258
217k
          func (stream, dis_style_immediate, "%ld",
11259
217k
          (long) (reg << 2));
11260
217k
          value_in_comment = reg << 2;
11261
217k
          break;
11262
11263
42.5k
        case 'a':
11264
          /* PC-relative address -- the bottom two
11265
             bits of the address are dropped
11266
             before the calculation.  */
11267
42.5k
          info->print_address_func
11268
42.5k
            (((pc + 4) & ~3) + (reg << 2), info);
11269
42.5k
          value_in_comment = 0;
11270
42.5k
          break;
11271
11272
7.88k
        case 'x':
11273
7.88k
          func (stream, dis_style_immediate, "0x%04lx",
11274
7.88k
          (long) reg);
11275
7.88k
          break;
11276
11277
88.2k
        case 'B':
11278
88.2k
          reg = ((reg ^ (1 << bitend)) - (1 << bitend));
11279
88.2k
          bfd_vma target = reg * 2 + pc + 4;
11280
88.2k
          info->print_address_func (target, info);
11281
88.2k
          value_in_comment = 0;
11282
11283
          /* Fill in instruction information.  */
11284
88.2k
          info->insn_info_valid = 1;
11285
88.2k
          info->insn_type = dis_branch;
11286
88.2k
          info->target = target;
11287
88.2k
          break;
11288
11289
56.7k
        case 'c':
11290
56.7k
          func (stream, dis_style_mnemonic, "%s",
11291
56.7k
          arm_conditional [reg]);
11292
56.7k
          break;
11293
11294
0
        default:
11295
0
          abort ();
11296
2.58M
        }
11297
2.58M
          }
11298
2.58M
          break;
11299
11300
2.58M
        case '\'':
11301
23.3k
          c++;
11302
23.3k
          if ((given & (1 << bitstart)) != 0)
11303
11.4k
      func (stream, base_style, "%c", *c);
11304
23.3k
          break;
11305
11306
14.6k
        case '?':
11307
14.6k
          ++c;
11308
14.6k
          if ((given & (1 << bitstart)) != 0)
11309
6.53k
      func (stream, base_style, "%c", *c++);
11310
8.11k
          else
11311
8.11k
      func (stream, base_style, "%c", *++c);
11312
14.6k
          break;
11313
11314
0
        default:
11315
0
          abort ();
11316
2.62M
        }
11317
2.62M
    }
11318
2.62M
    break;
11319
11320
2.62M
        default:
11321
0
    abort ();
11322
5.67M
        }
11323
5.67M
    }
11324
11325
1.20M
  if (value_in_comment > 32 || value_in_comment < -16)
11326
240k
    func (stream, dis_style_comment_start,
11327
240k
    "\t@ 0x%lx", value_in_comment);
11328
1.20M
  return;
11329
1.20M
      }
11330
11331
  /* No match.  */
11332
0
  func (stream, dis_style_comment_start, UNKNOWN_INSTRUCTION_16BIT,
11333
0
  (unsigned) given);
11334
0
  return;
11335
1.20M
}
11336
11337
/* Return the name of an V7M special register.  */
11338
11339
static const char *
11340
psr_name (int regno)
11341
7.26k
{
11342
7.26k
  switch (regno)
11343
7.26k
    {
11344
0
    case 0x0: return "APSR";
11345
201
    case 0x1: return "IAPSR";
11346
203
    case 0x2: return "EAPSR";
11347
224
    case 0x3: return "PSR";
11348
198
    case 0x5: return "IPSR";
11349
202
    case 0x6: return "EPSR";
11350
197
    case 0x7: return "IEPSR";
11351
341
    case 0x8: return "MSP";
11352
203
    case 0x9: return "PSP";
11353
208
    case 0xa: return "MSPLIM";
11354
201
    case 0xb: return "PSPLIM";
11355
227
    case 0x10: return "PRIMASK";
11356
221
    case 0x11: return "BASEPRI";
11357
230
    case 0x12: return "BASEPRI_MAX";
11358
196
    case 0x13: return "FAULTMASK";
11359
210
    case 0x14: return "CONTROL";
11360
292
    case 0x88: return "MSP_NS";
11361
319
    case 0x89: return "PSP_NS";
11362
229
    case 0x8a: return "MSPLIM_NS";
11363
578
    case 0x8b: return "PSPLIM_NS";
11364
198
    case 0x90: return "PRIMASK_NS";
11365
200
    case 0x91: return "BASEPRI_NS";
11366
210
    case 0x93: return "FAULTMASK_NS";
11367
225
    case 0x94: return "CONTROL_NS";
11368
238
    case 0x98: return "SP_NS";
11369
1.50k
    default: return "<unknown>";
11370
7.26k
    }
11371
7.26k
}
11372
11373
/* Print one 32-bit Thumb instruction from PC on INFO->STREAM.  */
11374
11375
static void
11376
print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
11377
436k
{
11378
436k
  const struct opcode32 *insn;
11379
436k
  void *stream = info->stream;
11380
436k
  fprintf_styled_ftype func = info->fprintf_styled_func;
11381
436k
  bool is_mve = is_mve_architecture (info);
11382
436k
  enum disassembler_style base_style = dis_style_mnemonic;
11383
436k
  enum disassembler_style old_base_style = base_style;
11384
11385
436k
  if (print_insn_coprocessor (pc, info, given, true))
11386
22.2k
    return;
11387
11388
414k
  if (!is_mve && print_insn_neon (info, given, true))
11389
19.6k
    return;
11390
11391
394k
  if (is_mve && print_insn_mve (info, given))
11392
116k
    return;
11393
11394
278k
  if (print_insn_cde (info, given, true))
11395
18.3k
    return;
11396
11397
259k
  if (print_insn_generic_coprocessor (pc, info, given, true))
11398
20.0k
    return;
11399
11400
54.2M
  for (insn = thumb32_opcodes; insn->assembler; insn++)
11401
54.2M
    if ((given & insn->mask) == insn->value)
11402
239k
      {
11403
239k
  bool is_clrm = false;
11404
239k
  bool is_unpredictable = false;
11405
239k
  signed long value_in_comment = 0;
11406
239k
  const char *c = insn->assembler;
11407
11408
5.35M
  for (; *c; c++)
11409
5.11M
    {
11410
5.11M
      if (*c != '%')
11411
4.59M
        {
11412
4.59M
    if (*c == '@')
11413
134k
      base_style = dis_style_comment_start;
11414
4.59M
    if (*c == '\t')
11415
371k
      base_style = dis_style_text;
11416
4.59M
    func (stream, base_style, "%c", *c);
11417
4.59M
    continue;
11418
4.59M
        }
11419
11420
519k
      switch (*++c)
11421
519k
        {
11422
10.4k
        case '{':
11423
10.4k
    ++c;
11424
10.4k
    if (*c == '\0')
11425
0
      abort ();
11426
10.4k
    old_base_style = base_style;
11427
10.4k
    base_style = decode_base_style (*c);
11428
10.4k
    ++c;
11429
10.4k
    if (*c != ':')
11430
0
      abort ();
11431
10.4k
    break;
11432
11433
10.4k
        case '}':
11434
10.4k
    base_style = old_base_style;
11435
10.4k
    break;
11436
11437
0
        case '%':
11438
0
    func (stream, base_style, "%%");
11439
0
    break;
11440
11441
94.1k
        case 'c':
11442
94.1k
    if (ifthen_state)
11443
3.29k
      func (stream, dis_style_mnemonic, "%s",
11444
3.29k
      arm_conditional[IFTHEN_COND]);
11445
94.1k
    break;
11446
11447
36.8k
        case 'x':
11448
36.8k
    if (ifthen_next_state)
11449
497
      func (stream, dis_style_comment_start,
11450
497
      "\t@ unpredictable branch in IT block\n");
11451
36.8k
    break;
11452
11453
5.95k
        case 'X':
11454
5.95k
    if (ifthen_state)
11455
641
      func (stream, dis_style_comment_start,
11456
641
      "\t@ unpredictable <IT:%s>",
11457
641
      arm_conditional[IFTHEN_COND]);
11458
5.95k
    break;
11459
11460
665
        case 'I':
11461
665
    {
11462
665
      unsigned int imm12 = 0;
11463
11464
665
      imm12 |= (given & 0x000000ffu);
11465
665
      imm12 |= (given & 0x00007000u) >> 4;
11466
665
      imm12 |= (given & 0x04000000u) >> 15;
11467
665
      func (stream, dis_style_immediate, "#%u", imm12);
11468
665
      value_in_comment = imm12;
11469
665
    }
11470
665
    break;
11471
11472
2.49k
        case 'M':
11473
2.49k
    {
11474
2.49k
      unsigned int bits = 0, imm, imm8, mod;
11475
11476
2.49k
      bits |= (given & 0x000000ffu);
11477
2.49k
      bits |= (given & 0x00007000u) >> 4;
11478
2.49k
      bits |= (given & 0x04000000u) >> 15;
11479
2.49k
      imm8 = (bits & 0x0ff);
11480
2.49k
      mod = (bits & 0xf00) >> 8;
11481
2.49k
      switch (mod)
11482
2.49k
        {
11483
720
        case 0: imm = imm8; break;
11484
227
        case 1: imm = ((imm8 << 16) | imm8); break;
11485
358
        case 2: imm = ((imm8 << 24) | (imm8 << 8)); break;
11486
210
        case 3: imm = ((imm8 << 24) | (imm8 << 16) | (imm8 << 8) | imm8); break;
11487
982
        default:
11488
982
          mod  = (bits & 0xf80) >> 7;
11489
982
          imm8 = (bits & 0x07f) | 0x80;
11490
982
          imm  = (((imm8 << (32 - mod)) | (imm8 >> mod)) & 0xffffffff);
11491
2.49k
        }
11492
2.49k
      func (stream, dis_style_immediate, "#%u", imm);
11493
2.49k
      value_in_comment = imm;
11494
2.49k
    }
11495
0
    break;
11496
11497
3.30k
        case 'J':
11498
3.30k
    {
11499
3.30k
      unsigned int imm = 0;
11500
11501
3.30k
      imm |= (given & 0x000000ffu);
11502
3.30k
      imm |= (given & 0x00007000u) >> 4;
11503
3.30k
      imm |= (given & 0x04000000u) >> 15;
11504
3.30k
      imm |= (given & 0x000f0000u) >> 4;
11505
3.30k
      func (stream, dis_style_immediate, "#%u", imm);
11506
3.30k
      value_in_comment = imm;
11507
3.30k
    }
11508
3.30k
    break;
11509
11510
224
        case 'K':
11511
224
    {
11512
224
      unsigned int imm = 0;
11513
11514
224
      imm |= (given & 0x000f0000u) >> 16;
11515
224
      imm |= (given & 0x00000ff0u) >> 0;
11516
224
      imm |= (given & 0x0000000fu) << 12;
11517
224
      func (stream, dis_style_immediate, "#%u", imm);
11518
224
      value_in_comment = imm;
11519
224
    }
11520
224
    break;
11521
11522
196
        case 'H':
11523
196
    {
11524
196
      unsigned int imm = 0;
11525
11526
196
      imm |= (given & 0x000f0000u) >> 4;
11527
196
      imm |= (given & 0x00000fffu) >> 0;
11528
196
      func (stream, dis_style_immediate, "#%u", imm);
11529
196
      value_in_comment = imm;
11530
196
    }
11531
196
    break;
11532
11533
198
        case 'V':
11534
198
    {
11535
198
      unsigned int imm = 0;
11536
11537
198
      imm |= (given & 0x00000fffu);
11538
198
      imm |= (given & 0x000f0000u) >> 4;
11539
198
      func (stream, dis_style_immediate, "#%u", imm);
11540
198
      value_in_comment = imm;
11541
198
    }
11542
198
    break;
11543
11544
4.26k
        case 'S':
11545
4.26k
    {
11546
4.26k
      unsigned int reg = (given & 0x0000000fu);
11547
4.26k
      unsigned int stp = (given & 0x00000030u) >> 4;
11548
4.26k
      unsigned int imm = 0;
11549
4.26k
      imm |= (given & 0x000000c0u) >> 6;
11550
4.26k
      imm |= (given & 0x00007000u) >> 10;
11551
11552
4.26k
      func (stream, dis_style_register, "%s", arm_regnames[reg]);
11553
4.26k
      switch (stp)
11554
4.26k
        {
11555
1.28k
        case 0:
11556
1.28k
          if (imm > 0)
11557
493
      {
11558
493
        func (stream, dis_style_text, ", ");
11559
493
        func (stream, dis_style_sub_mnemonic, "lsl ");
11560
493
        func (stream, dis_style_immediate, "#%u", imm);
11561
493
      }
11562
1.28k
          break;
11563
11564
822
        case 1:
11565
822
          if (imm == 0)
11566
205
      imm = 32;
11567
822
          func (stream, dis_style_text, ", ");
11568
822
          func (stream, dis_style_sub_mnemonic, "lsr ");
11569
822
          func (stream, dis_style_immediate, "#%u", imm);
11570
822
          break;
11571
11572
1.15k
        case 2:
11573
1.15k
          if (imm == 0)
11574
219
      imm = 32;
11575
1.15k
          func (stream, dis_style_text, ", ");
11576
1.15k
          func (stream, dis_style_sub_mnemonic, "asr ");
11577
1.15k
          func (stream, dis_style_immediate, "#%u", imm);
11578
1.15k
          break;
11579
11580
994
        case 3:
11581
994
          if (imm == 0)
11582
227
      {
11583
227
        func (stream, dis_style_text, ", ");
11584
227
        func (stream, dis_style_sub_mnemonic, "rrx");
11585
227
      }
11586
767
          else
11587
767
      {
11588
767
        func (stream, dis_style_text, ", ");
11589
767
        func (stream, dis_style_sub_mnemonic, "ror ");
11590
767
        func (stream, dis_style_immediate, "#%u", imm);
11591
767
      }
11592
4.26k
        }
11593
4.26k
    }
11594
4.26k
    break;
11595
11596
11.8k
        case 'a':
11597
11.8k
    {
11598
11.8k
      unsigned int Rn  = (given & 0x000f0000) >> 16;
11599
11.8k
      unsigned int U   = ! NEGATIVE_BIT_SET;
11600
11.8k
      unsigned int op  = (given & 0x00000f00) >> 8;
11601
11.8k
      unsigned int i12 = (given & 0x00000fff);
11602
11.8k
      unsigned int i8  = (given & 0x000000ff);
11603
11.8k
      bool writeback = false, postind = false;
11604
11.8k
      bfd_vma offset = 0;
11605
11606
11.8k
      func (stream, dis_style_text, "[");
11607
11.8k
      func (stream, dis_style_register, "%s", arm_regnames[Rn]);
11608
11.8k
      if (U) /* 12-bit positive immediate offset.  */
11609
6.15k
        {
11610
6.15k
          offset = i12;
11611
6.15k
          if (Rn != 15)
11612
3.62k
      value_in_comment = offset;
11613
6.15k
        }
11614
5.73k
      else if (Rn == 15) /* 12-bit negative immediate offset.  */
11615
398
        offset = - (int) i12;
11616
5.34k
      else if (op == 0x0) /* Shifted register offset.  */
11617
1.35k
        {
11618
1.35k
          unsigned int Rm = (i8 & 0x0f);
11619
1.35k
          unsigned int sh = (i8 & 0x30) >> 4;
11620
11621
1.35k
          func (stream, dis_style_text, ", ");
11622
1.35k
          func (stream, dis_style_register, "%s",
11623
1.35k
          arm_regnames[Rm]);
11624
1.35k
          if (sh)
11625
630
      {
11626
630
        func (stream, dis_style_text, ", ");
11627
630
        func (stream, dis_style_sub_mnemonic, "lsl ");
11628
630
        func (stream, dis_style_immediate, "#%u", sh);
11629
630
      }
11630
1.35k
          func (stream, dis_style_text, "]");
11631
1.35k
          break;
11632
1.35k
        }
11633
3.98k
      else switch (op)
11634
3.98k
        {
11635
546
        case 0xE:  /* 8-bit positive immediate offset.  */
11636
546
          offset = i8;
11637
546
          break;
11638
11639
790
        case 0xC:  /* 8-bit negative immediate offset.  */
11640
790
          offset = -i8;
11641
790
          break;
11642
11643
500
        case 0xF:  /* 8-bit + preindex with wb.  */
11644
500
          offset = i8;
11645
500
          writeback = true;
11646
500
          break;
11647
11648
313
        case 0xD:  /* 8-bit - preindex with wb.  */
11649
313
          offset = -i8;
11650
313
          writeback = true;
11651
313
          break;
11652
11653
443
        case 0xB:  /* 8-bit + postindex.  */
11654
443
          offset = i8;
11655
443
          postind = true;
11656
443
          break;
11657
11658
422
        case 0x9:  /* 8-bit - postindex.  */
11659
422
          offset = -i8;
11660
422
          postind = true;
11661
422
          break;
11662
11663
967
        default:
11664
967
          func (stream, dis_style_text, ", <undefined>]");
11665
967
          goto skip;
11666
3.98k
        }
11667
11668
9.57k
      if (postind)
11669
865
        {
11670
865
          func (stream, dis_style_text, "], ");
11671
865
          func (stream, dis_style_immediate, "#%d", (int) offset);
11672
865
        }
11673
8.70k
      else
11674
8.70k
        {
11675
8.70k
          if (offset)
11676
7.84k
      {
11677
7.84k
        func (stream, dis_style_text, ", ");
11678
7.84k
        func (stream, dis_style_immediate, "#%d",
11679
7.84k
        (int) offset);
11680
7.84k
      }
11681
8.70k
          func (stream, dis_style_text, writeback ? "]!" : "]");
11682
8.70k
        }
11683
11684
9.57k
      if (Rn == 15)
11685
2.93k
        {
11686
2.93k
          func (stream, dis_style_comment_start, "\t@ ");
11687
2.93k
          info->print_address_func (((pc + 4) & ~3) + offset, info);
11688
2.93k
        }
11689
9.57k
    }
11690
10.5k
        skip:
11691
10.5k
    break;
11692
11693
0
        case 'A':
11694
0
    {
11695
0
      unsigned int U   = ! NEGATIVE_BIT_SET;
11696
0
      unsigned int W   = WRITEBACK_BIT_SET;
11697
0
      unsigned int Rn  = (given & 0x000f0000) >> 16;
11698
0
      unsigned int off = (given & 0x000000ff);
11699
11700
0
      func (stream, dis_style_text, "[");
11701
0
      func (stream, dis_style_register, "%s", arm_regnames[Rn]);
11702
11703
0
      if (PRE_BIT_SET)
11704
0
        {
11705
0
          if (off || !U)
11706
0
      {
11707
0
        func (stream, dis_style_text, ", ");
11708
0
        func (stream, dis_style_immediate, "#%c%u",
11709
0
        U ? '+' : '-', off * 4);
11710
0
        value_in_comment = off * 4 * (U ? 1 : -1);
11711
0
      }
11712
0
          func (stream, dis_style_text, "]");
11713
0
          if (W)
11714
0
      func (stream, dis_style_text, "!");
11715
0
        }
11716
0
      else
11717
0
        {
11718
0
          func (stream, dis_style_text, "], ");
11719
0
          if (W)
11720
0
      {
11721
0
        func (stream, dis_style_immediate, "#%c%u",
11722
0
        U ? '+' : '-', off * 4);
11723
0
        value_in_comment = off * 4 * (U ? 1 : -1);
11724
0
      }
11725
0
          else
11726
0
      {
11727
0
        func (stream, dis_style_text, "{");
11728
0
        func (stream, dis_style_immediate, "%u", off);
11729
0
        func (stream, dis_style_text, "}");
11730
0
        value_in_comment = off;
11731
0
      }
11732
0
        }
11733
0
    }
11734
0
    break;
11735
11736
11.8k
        case 'w':
11737
11.8k
    {
11738
11.8k
      unsigned int Sbit = (given & 0x01000000) >> 24;
11739
11.8k
      unsigned int type = (given & 0x00600000) >> 21;
11740
11741
11.8k
      switch (type)
11742
11.8k
        {
11743
2.06k
        case 0:
11744
2.06k
          func (stream, dis_style_mnemonic, Sbit ? "sb" : "b");
11745
2.06k
          break;
11746
1.88k
        case 1:
11747
1.88k
          func (stream, dis_style_mnemonic, Sbit ? "sh" : "h");
11748
1.88k
          break;
11749
1.96k
        case 2:
11750
1.96k
          if (Sbit)
11751
819
      func (stream, dis_style_text, "??");
11752
1.96k
          break;
11753
5.88k
        case 3:
11754
5.88k
          func (stream, dis_style_text, "??");
11755
5.88k
          break;
11756
11.8k
        }
11757
11.8k
    }
11758
11.8k
    break;
11759
11760
11.8k
        case 'n':
11761
472
    is_clrm = true;
11762
    /* Fall through.  */
11763
2.79k
        case 'm':
11764
2.79k
    {
11765
2.79k
      int started = 0;
11766
2.79k
      int reg;
11767
11768
2.79k
      func (stream, dis_style_text, "{");
11769
47.4k
      for (reg = 0; reg < 16; reg++)
11770
44.6k
        if ((given & (1 << reg)) != 0)
11771
27.5k
          {
11772
27.5k
      if (started)
11773
24.8k
        func (stream, dis_style_text, ", ");
11774
27.5k
      started = 1;
11775
27.5k
      if (is_clrm && reg == 13)
11776
0
        func (stream, dis_style_text, "(invalid: %s)",
11777
0
        arm_regnames[reg]);
11778
27.5k
      else if (is_clrm && reg == 15)
11779
362
        func (stream, dis_style_register, "%s", "APSR");
11780
27.2k
      else
11781
27.2k
        func (stream, dis_style_register, "%s",
11782
27.2k
        arm_regnames[reg]);
11783
27.5k
          }
11784
2.79k
      func (stream, dis_style_text, "}");
11785
2.79k
    }
11786
2.79k
    break;
11787
11788
204
        case 'E':
11789
204
    {
11790
204
      unsigned int msb = (given & 0x0000001f);
11791
204
      unsigned int lsb = 0;
11792
11793
204
      lsb |= (given & 0x000000c0u) >> 6;
11794
204
      lsb |= (given & 0x00007000u) >> 10;
11795
204
      func (stream, dis_style_immediate, "#%u", lsb);
11796
204
      func (stream, dis_style_text, ", ");
11797
204
      func (stream, dis_style_immediate, "#%u", msb - lsb + 1);
11798
204
    }
11799
204
    break;
11800
11801
259
        case 'F':
11802
259
    {
11803
259
      unsigned int width = (given & 0x0000001f) + 1;
11804
259
      unsigned int lsb = 0;
11805
11806
259
      lsb |= (given & 0x000000c0u) >> 6;
11807
259
      lsb |= (given & 0x00007000u) >> 10;
11808
259
      func (stream, dis_style_immediate, "#%u", lsb);
11809
259
      func (stream, dis_style_text, ", ");
11810
259
      func (stream, dis_style_immediate, "#%u", width);
11811
259
    }
11812
259
    break;
11813
11814
3.21k
        case 'G':
11815
3.21k
    {
11816
3.21k
      unsigned int boff = (((given & 0x07800000) >> 23) << 1);
11817
3.21k
      func (stream, dis_style_immediate, "%x", boff);
11818
3.21k
    }
11819
3.21k
    break;
11820
11821
557
        case 'W':
11822
557
    {
11823
557
      unsigned int immA = (given & 0x001f0000u) >> 16;
11824
557
      unsigned int immB = (given & 0x000007feu) >> 1;
11825
557
      unsigned int immC = (given & 0x00000800u) >> 11;
11826
557
      bfd_vma offset = 0;
11827
11828
557
      offset |= immA << 12;
11829
557
      offset |= immB << 2;
11830
557
      offset |= immC << 1;
11831
      /* Sign extend.  */
11832
557
      offset = (offset & 0x10000) ? offset - (1 << 17) : offset;
11833
11834
557
      info->print_address_func (pc + 4 + offset, info);
11835
557
    }
11836
557
    break;
11837
11838
1.56k
        case 'Y':
11839
1.56k
    {
11840
1.56k
      unsigned int immA = (given & 0x007f0000u) >> 16;
11841
1.56k
      unsigned int immB = (given & 0x000007feu) >> 1;
11842
1.56k
      unsigned int immC = (given & 0x00000800u) >> 11;
11843
1.56k
      bfd_vma offset = 0;
11844
11845
1.56k
      offset |= immA << 12;
11846
1.56k
      offset |= immB << 2;
11847
1.56k
      offset |= immC << 1;
11848
      /* Sign extend.  */
11849
1.56k
      offset = (offset & 0x40000) ? offset - (1 << 19) : offset;
11850
11851
1.56k
      info->print_address_func (pc + 4 + offset, info);
11852
1.56k
    }
11853
1.56k
    break;
11854
11855
1.07k
        case 'Z':
11856
1.07k
    {
11857
1.07k
      unsigned int immA = (given & 0x00010000u) >> 16;
11858
1.07k
      unsigned int immB = (given & 0x000007feu) >> 1;
11859
1.07k
      unsigned int immC = (given & 0x00000800u) >> 11;
11860
1.07k
      bfd_vma offset = 0;
11861
11862
1.07k
      offset |= immA << 12;
11863
1.07k
      offset |= immB << 2;
11864
1.07k
      offset |= immC << 1;
11865
      /* Sign extend.  */
11866
1.07k
      offset = (offset & 0x1000) ? offset - (1 << 13) : offset;
11867
11868
1.07k
      info->print_address_func (pc + 4 + offset, info);
11869
11870
1.07k
      unsigned int T    = (given & 0x00020000u) >> 17;
11871
1.07k
      unsigned int endoffset = (((given & 0x07800000) >> 23) << 1);
11872
1.07k
      unsigned int boffset   = (T == 1) ? 4 : 2;
11873
1.07k
      func (stream, dis_style_text, ", ");
11874
1.07k
      func (stream, dis_style_immediate, "%x",
11875
1.07k
      endoffset + boffset);
11876
1.07k
    }
11877
1.07k
    break;
11878
11879
915
        case 'Q':
11880
915
    {
11881
915
      unsigned int immh = (given & 0x000007feu) >> 1;
11882
915
      unsigned int imml = (given & 0x00000800u) >> 11;
11883
915
      bfd_vma imm32 = 0;
11884
11885
915
      imm32 |= immh << 2;
11886
915
      imm32 |= imml << 1;
11887
11888
915
      info->print_address_func (pc + 4 + imm32, info);
11889
915
    }
11890
915
    break;
11891
11892
195
        case 'P':
11893
195
    {
11894
195
      unsigned int immh = (given & 0x000007feu) >> 1;
11895
195
      unsigned int imml = (given & 0x00000800u) >> 11;
11896
195
      bfd_vma imm32 = 0;
11897
11898
195
      imm32 |= immh << 2;
11899
195
      imm32 |= imml << 1;
11900
11901
195
      info->print_address_func (pc + 4 - imm32, info);
11902
195
    }
11903
195
    break;
11904
11905
5.05k
        case 'b':
11906
5.05k
    {
11907
5.05k
      unsigned int S = (given & 0x04000000u) >> 26;
11908
5.05k
      unsigned int J1 = (given & 0x00002000u) >> 13;
11909
5.05k
      unsigned int J2 = (given & 0x00000800u) >> 11;
11910
5.05k
      bfd_vma offset = 0;
11911
11912
5.05k
      offset |= !S << 20;
11913
5.05k
      offset |= J2 << 19;
11914
5.05k
      offset |= J1 << 18;
11915
5.05k
      offset |= (given & 0x003f0000) >> 4;
11916
5.05k
      offset |= (given & 0x000007ff) << 1;
11917
5.05k
      offset -= (1 << 20);
11918
11919
5.05k
      bfd_vma target = pc + 4 + offset;
11920
5.05k
      info->print_address_func (target, info);
11921
11922
      /* Fill in instruction information.  */
11923
5.05k
      info->insn_info_valid = 1;
11924
5.05k
      info->insn_type = dis_branch;
11925
5.05k
      info->target = target;
11926
5.05k
    }
11927
5.05k
    break;
11928
11929
36.8k
        case 'B':
11930
36.8k
    {
11931
36.8k
      unsigned int S = (given & 0x04000000u) >> 26;
11932
36.8k
      unsigned int I1 = (given & 0x00002000u) >> 13;
11933
36.8k
      unsigned int I2 = (given & 0x00000800u) >> 11;
11934
36.8k
      bfd_vma offset = 0;
11935
11936
36.8k
      offset |= !S << 24;
11937
36.8k
      offset |= !(I1 ^ S) << 23;
11938
36.8k
      offset |= !(I2 ^ S) << 22;
11939
36.8k
      offset |= (given & 0x03ff0000u) >> 4;
11940
36.8k
      offset |= (given & 0x000007ffu) << 1;
11941
36.8k
      offset -= (1 << 24);
11942
36.8k
      offset += pc + 4;
11943
11944
      /* BLX target addresses are always word aligned.  */
11945
36.8k
      if ((given & 0x00001000u) == 0)
11946
12.1k
          offset &= ~2u;
11947
11948
36.8k
      info->print_address_func (offset, info);
11949
11950
      /* Fill in instruction information.  */
11951
36.8k
      info->insn_info_valid = 1;
11952
36.8k
      info->insn_type = dis_branch;
11953
36.8k
      info->target = offset;
11954
36.8k
    }
11955
36.8k
    break;
11956
11957
1.87k
        case 's':
11958
1.87k
    {
11959
1.87k
      unsigned int shift = 0;
11960
11961
1.87k
      shift |= (given & 0x000000c0u) >> 6;
11962
1.87k
      shift |= (given & 0x00007000u) >> 10;
11963
1.87k
      if (WRITEBACK_BIT_SET)
11964
269
        {
11965
269
          func (stream, dis_style_text, ", ");
11966
269
          func (stream, dis_style_sub_mnemonic, "asr ");
11967
269
          func (stream, dis_style_immediate, "#%u", shift);
11968
269
        }
11969
1.60k
      else if (shift)
11970
711
        {
11971
711
          func (stream, dis_style_text, ", ");
11972
711
          func (stream, dis_style_sub_mnemonic, "lsl ");
11973
711
          func (stream, dis_style_immediate, "#%u", shift);
11974
711
        }
11975
      /* else print nothing - lsl #0 */
11976
1.87k
    }
11977
1.87k
    break;
11978
11979
412
        case 'R':
11980
412
    {
11981
412
      unsigned int rot = (given & 0x00000030) >> 4;
11982
11983
412
      if (rot)
11984
211
        {
11985
211
          func (stream, dis_style_text, ", ");
11986
211
          func (stream, dis_style_sub_mnemonic, "ror ");
11987
211
          func (stream, dis_style_immediate, "#%u", rot * 8);
11988
211
        }
11989
412
    }
11990
412
    break;
11991
11992
1.08k
        case 'U':
11993
1.08k
    if ((given & 0xf0) == 0x60)
11994
446
      {
11995
446
        switch (given & 0xf)
11996
446
          {
11997
240
          case 0xf:
11998
240
      func (stream, dis_style_sub_mnemonic, "sy");
11999
240
      break;
12000
206
          default:
12001
206
      func (stream, dis_style_immediate, "#%d",
12002
206
            (int) given & 0xf);
12003
206
      break;
12004
446
          }
12005
446
      }
12006
639
    else
12007
639
      {
12008
639
        const char * opt = data_barrier_option (given & 0xf);
12009
639
        if (opt != NULL)
12010
300
          func (stream, dis_style_sub_mnemonic, "%s", opt);
12011
339
        else
12012
339
          func (stream, dis_style_immediate, "#%d",
12013
339
          (int) given & 0xf);
12014
639
       }
12015
1.08k
    break;
12016
12017
9.36k
        case 'C':
12018
9.36k
    if ((given & 0xff) == 0)
12019
617
      {
12020
617
        func (stream, dis_style_register, "%cPSR_",
12021
617
        (given & 0x100000) ? 'S' : 'C');
12022
12023
617
        if (given & 0x800)
12024
248
          func (stream, dis_style_register, "f");
12025
617
        if (given & 0x400)
12026
228
          func (stream, dis_style_register, "s");
12027
617
        if (given & 0x200)
12028
358
          func (stream, dis_style_register, "x");
12029
617
        if (given & 0x100)
12030
267
          func (stream, dis_style_register, "c");
12031
617
      }
12032
8.74k
    else if ((given & 0x20) == 0x20)
12033
6.21k
      {
12034
6.21k
        char const* name;
12035
6.21k
        unsigned sysm = (given & 0xf00) >> 8;
12036
12037
6.21k
        sysm |= (given & 0x30);
12038
6.21k
        sysm |= (given & 0x00100000) >> 14;
12039
6.21k
        name = banked_regname (sysm);
12040
12041
6.21k
        if (name != NULL)
12042
5.40k
          func (stream, dis_style_register, "%s", name);
12043
811
        else
12044
811
          func (stream, dis_style_text,
12045
811
          "(UNDEF: %lu)", (unsigned long) sysm);
12046
6.21k
      }
12047
2.53k
    else
12048
2.53k
      {
12049
2.53k
        func (stream, dis_style_register, "%s",
12050
2.53k
        psr_name (given & 0xff));
12051
2.53k
      }
12052
9.36k
    break;
12053
12054
9.75k
        case 'D':
12055
9.75k
    if (((given & 0xff) == 0)
12056
9.75k
        || ((given & 0x20) == 0x20))
12057
5.02k
      {
12058
5.02k
        char const* name;
12059
5.02k
        unsigned sm = (given & 0xf0000) >> 16;
12060
12061
5.02k
        sm |= (given & 0x30);
12062
5.02k
        sm |= (given & 0x00100000) >> 14;
12063
5.02k
        name = banked_regname (sm);
12064
12065
5.02k
        if (name != NULL)
12066
3.06k
          func (stream, dis_style_register, "%s", name);
12067
1.96k
        else
12068
1.96k
          func (stream, dis_style_text,
12069
1.96k
          "(UNDEF: %lu)", (unsigned long) sm);
12070
5.02k
      }
12071
4.72k
    else
12072
4.72k
      func (stream, dis_style_register, "%s",
12073
4.72k
      psr_name (given & 0xff));
12074
9.75k
    break;
12075
12076
214k
        case '0': case '1': case '2': case '3': case '4':
12077
246k
        case '5': case '6': case '7': case '8': case '9':
12078
246k
    {
12079
246k
      int width;
12080
246k
      unsigned long val;
12081
12082
246k
      c = arm_decode_bitfield (c, given, &val, &width);
12083
12084
246k
      switch (*c)
12085
246k
        {
12086
914
        case 's':
12087
914
          if (val <= 3)
12088
914
      func (stream, dis_style_mnemonic, "%s",
12089
914
            mve_vec_sizename[val]);
12090
0
          else
12091
0
      func (stream, dis_style_text, "<undef size>");
12092
914
          break;
12093
12094
1.20k
        case 'd':
12095
1.20k
          func (stream, base_style, "%lu", val);
12096
1.20k
          value_in_comment = val;
12097
1.20k
          break;
12098
12099
1.03k
        case 'D':
12100
1.03k
          func (stream, dis_style_immediate, "%lu", val + 1);
12101
1.03k
          value_in_comment = val + 1;
12102
1.03k
          break;
12103
12104
4.71k
        case 'W':
12105
4.71k
          func (stream, dis_style_immediate, "%lu", val * 4);
12106
4.71k
          value_in_comment = val * 4;
12107
4.71k
          break;
12108
12109
926
        case 'S':
12110
926
          if (val == 13)
12111
550
      is_unpredictable = true;
12112
          /* Fall through.  */
12113
3.87k
        case 'R':
12114
3.87k
          if (val == 15)
12115
677
      is_unpredictable = true;
12116
          /* Fall through.  */
12117
77.4k
        case 'r':
12118
77.4k
          func (stream, dis_style_register, "%s",
12119
77.4k
          arm_regnames[val]);
12120
77.4k
          break;
12121
12122
6.12k
        case 'c':
12123
6.12k
          func (stream, base_style, "%s", arm_conditional[val]);
12124
6.12k
          break;
12125
12126
15.8k
        case '\'':
12127
15.8k
          c++;
12128
15.8k
          if (val == ((1ul << width) - 1))
12129
6.47k
      func (stream, base_style, "%c", *c);
12130
15.8k
          break;
12131
12132
4.69k
        case '`':
12133
4.69k
          c++;
12134
4.69k
          if (val == 0)
12135
1.32k
      func (stream, dis_style_immediate, "%c", *c);
12136
4.69k
          break;
12137
12138
604
        case '?':
12139
604
          func (stream, dis_style_mnemonic, "%c",
12140
604
          c[(1 << width) - (int) val]);
12141
604
          c += 1 << width;
12142
604
          break;
12143
12144
134k
        case 'x':
12145
134k
          func (stream, dis_style_immediate, "0x%lx",
12146
134k
          val & 0xffffffffUL);
12147
134k
          break;
12148
12149
0
        default:
12150
0
          abort ();
12151
246k
        }
12152
246k
    }
12153
246k
    break;
12154
12155
246k
        case 'L':
12156
    /* PR binutils/12534
12157
       If we have a PC relative offset in an LDRD or STRD
12158
       instructions then display the decoded address.  */
12159
4.69k
    if (((given >> 16) & 0xf) == 0xf)
12160
746
      {
12161
746
        bfd_vma offset = (given & 0xff) * 4;
12162
12163
746
        if ((given & (1 << 23)) == 0)
12164
382
          offset = - offset;
12165
746
        func (stream, dis_style_comment_start, "\t@ ");
12166
746
        info->print_address_func ((pc & ~3) + 4 + offset, info);
12167
746
      }
12168
4.69k
    break;
12169
12170
0
        default:
12171
0
    abort ();
12172
519k
        }
12173
519k
    }
12174
12175
239k
  if (value_in_comment > 32 || value_in_comment < -16)
12176
12.0k
    func (stream, dis_style_comment_start, "\t@ 0x%lx",
12177
12.0k
    value_in_comment);
12178
12179
239k
  if (is_unpredictable)
12180
930
    func (stream, dis_style_comment_start, UNPREDICTABLE_INSTRUCTION);
12181
12182
239k
  return;
12183
239k
      }
12184
12185
  /* No match.  */
12186
0
  func (stream, dis_style_comment_start, UNKNOWN_INSTRUCTION_32BIT,
12187
0
  (unsigned) given);
12188
0
  return;
12189
239k
}
12190
12191
/* Print data bytes on INFO->STREAM.  */
12192
12193
static void
12194
print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED,
12195
     struct disassemble_info *info,
12196
     long given)
12197
0
{
12198
0
  fprintf_styled_ftype func = info->fprintf_styled_func;
12199
12200
0
  switch (info->bytes_per_chunk)
12201
0
    {
12202
0
    case 1:
12203
0
      func (info->stream, dis_style_assembler_directive, ".byte");
12204
0
      func (info->stream, dis_style_text, "\t");
12205
0
      func (info->stream, dis_style_immediate, "0x%02lx", given);
12206
0
      break;
12207
0
    case 2:
12208
0
      func (info->stream, dis_style_assembler_directive, ".short");
12209
0
      func (info->stream, dis_style_text, "\t");
12210
0
      func (info->stream, dis_style_immediate, "0x%04lx", given);
12211
0
      break;
12212
0
    case 4:
12213
0
      func (info->stream, dis_style_assembler_directive, ".word");
12214
0
      func (info->stream, dis_style_text, "\t");
12215
0
      func (info->stream, dis_style_immediate, "0x%08lx", given);
12216
0
      break;
12217
0
    default:
12218
0
      abort ();
12219
0
    }
12220
0
}
12221
12222
/* Disallow mapping symbols ($a, $b, $d, $t etc) from
12223
   being displayed in symbol relative addresses.
12224
12225
   Also disallow private symbol, with __tagsym$$ prefix,
12226
   from ARM RVCT toolchain being displayed.  */
12227
12228
bool
12229
arm_symbol_is_valid (asymbol * sym,
12230
         struct disassemble_info * info ATTRIBUTE_UNUSED)
12231
107k
{
12232
107k
  const char * name;
12233
12234
107k
  if (sym == NULL)
12235
0
    return false;
12236
12237
107k
  name = bfd_asymbol_name (sym);
12238
12239
107k
  return (name && *name != '$' && strncmp (name, "__tagsym$$", 10));
12240
107k
}
12241
12242
/* Parse the string of disassembler options.  */
12243
12244
static void
12245
parse_arm_disassembler_options (const char *options)
12246
17.7k
{
12247
17.7k
  const char *opt;
12248
12249
17.7k
  force_thumb = false;
12250
17.7k
  FOR_EACH_DISASSEMBLER_OPTION (opt, options)
12251
26.4k
    {
12252
26.4k
      if (startswith (opt, "reg-names-"))
12253
314
  {
12254
314
    unsigned int i;
12255
2.53k
    for (i = 0; i < NUM_ARM_OPTIONS; i++)
12256
2.29k
      if (disassembler_options_cmp (opt, regnames[i].name) == 0)
12257
76
        {
12258
76
    regname_selected = i;
12259
76
    break;
12260
76
        }
12261
12262
314
    if (i >= NUM_ARM_OPTIONS)
12263
      /* xgettext: c-format */
12264
238
      opcodes_error_handler (_("unrecognised register name set: %s"),
12265
238
           opt);
12266
314
  }
12267
26.1k
      else if (startswith (opt, "force-thumb"))
12268
12.8k
  force_thumb = 1;
12269
13.3k
      else if (startswith (opt, "no-force-thumb"))
12270
58
  force_thumb = 0;
12271
13.2k
      else if (startswith (opt, "coproc"))
12272
582
  {
12273
582
    const char *procptr = opt + sizeof ("coproc") - 1;
12274
582
    char *endptr;
12275
582
    uint8_t coproc_number = strtol (procptr, &endptr, 10);
12276
582
    if (endptr != procptr + 1 || coproc_number > 7)
12277
116
      {
12278
116
        opcodes_error_handler (_("cde coprocessor not between 0-7: %s"),
12279
116
             opt);
12280
116
        continue;
12281
116
      }
12282
466
    if (*endptr != '=')
12283
76
      {
12284
76
        opcodes_error_handler (_("coproc must have an argument: %s"),
12285
76
             opt);
12286
76
        continue;
12287
76
      }
12288
390
    endptr += 1;
12289
390
    if (startswith (endptr, "generic"))
12290
12
      cde_coprocs &= ~(1 << coproc_number);
12291
378
    else if (startswith (endptr, "cde")
12292
378
       || startswith (endptr, "CDE"))
12293
122
      cde_coprocs |= (1 << coproc_number);
12294
256
    else
12295
256
      {
12296
256
        opcodes_error_handler (
12297
256
      _("coprocN argument takes options \"generic\","
12298
256
        " \"cde\", or \"CDE\": %s"), opt);
12299
256
      }
12300
390
  }
12301
12.6k
      else
12302
  /* xgettext: c-format */
12303
12.6k
  opcodes_error_handler (_("unrecognised disassembler option: %s"), opt);
12304
26.4k
    }
12305
12306
17.7k
  return;
12307
17.7k
}
12308
12309
static bool
12310
mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
12311
       enum map_type *map_symbol);
12312
12313
/* Search back through the insn stream to determine if this instruction is
12314
   conditionally executed.  */
12315
12316
static void
12317
find_ifthen_state (bfd_vma pc,
12318
       struct disassemble_info *info,
12319
       bool little)
12320
12.9k
{
12321
12.9k
  unsigned char b[2];
12322
12.9k
  unsigned int insn;
12323
12.9k
  int status;
12324
  /* COUNT is twice the number of instructions seen.  It will be odd if we
12325
     just crossed an instruction boundary.  */
12326
12.9k
  int count;
12327
12.9k
  int it_count;
12328
12.9k
  unsigned int seen_it;
12329
12.9k
  bfd_vma addr;
12330
12331
12.9k
  ifthen_address = pc;
12332
12.9k
  ifthen_state = 0;
12333
12334
12.9k
  addr = pc;
12335
12.9k
  count = 1;
12336
12.9k
  it_count = 0;
12337
12.9k
  seen_it = 0;
12338
  /* Scan backwards looking for IT instructions, keeping track of where
12339
     instruction boundaries are.  We don't know if something is actually an
12340
     IT instruction until we find a definite instruction boundary.  */
12341
12.9k
  for (;;)
12342
12.9k
    {
12343
12.9k
      if (addr == 0 || info->symbol_at_address_func (addr, info))
12344
229
  {
12345
    /* A symbol must be on an instruction boundary, and will not
12346
       be within an IT block.  */
12347
229
    if (seen_it && (count & 1))
12348
0
      break;
12349
12350
229
    return;
12351
229
  }
12352
12.7k
      addr -= 2;
12353
12.7k
      status = info->read_memory_func (addr, (bfd_byte *) b, 2, info);
12354
12.7k
      if (status)
12355
12.7k
  return;
12356
12357
16
      if (little)
12358
16
  insn = (b[0]) | (b[1] << 8);
12359
0
      else
12360
0
  insn = (b[1]) | (b[0] << 8);
12361
16
      if (seen_it)
12362
0
  {
12363
0
    if ((insn & 0xf800) < 0xe800)
12364
0
      {
12365
        /* Addr + 2 is an instruction boundary.  See if this matches
12366
           the expected boundary based on the position of the last
12367
     IT candidate.  */
12368
0
        if (count & 1)
12369
0
    break;
12370
0
        seen_it = 0;
12371
0
      }
12372
0
  }
12373
16
      if ((insn & 0xff00) == 0xbf00 && (insn & 0xf) != 0)
12374
0
  {
12375
0
    enum map_type type = MAP_ARM;
12376
0
    bool found = mapping_symbol_for_insn (addr, info, &type);
12377
12378
0
    if (!found || (found && type == MAP_THUMB))
12379
0
      {
12380
        /* This could be an IT instruction.  */
12381
0
        seen_it = insn;
12382
0
        it_count = count >> 1;
12383
0
      }
12384
0
  }
12385
16
      if ((insn & 0xf800) >= 0xe800)
12386
0
  count++;
12387
16
      else
12388
16
  count = (count + 2) | 1;
12389
      /* IT blocks contain at most 4 instructions.  */
12390
16
      if (count >= 8 && !seen_it)
12391
4
  return;
12392
16
    }
12393
  /* We found an IT instruction.  */
12394
0
  ifthen_state = (seen_it & 0xe0) | ((seen_it << it_count) & 0x1f);
12395
0
  if ((ifthen_state & 0xf) == 0)
12396
0
    ifthen_state = 0;
12397
0
}
12398
12399
/* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a
12400
   mapping symbol.  */
12401
12402
static int
12403
is_mapping_symbol (struct disassemble_info *info,
12404
       int n,
12405
       enum map_type *map_type)
12406
18.6k
{
12407
18.6k
  const char *name = bfd_asymbol_name (info->symtab[n]);
12408
12409
18.6k
  if (name[0] == '$'
12410
18.6k
      && (name[1] == 'a' || name[1] == 't' || name[1] == 'd')
12411
18.6k
      && (name[2] == 0 || name[2] == '.'))
12412
0
    {
12413
0
      *map_type = ((name[1] == 'a') ? MAP_ARM
12414
0
       : (name[1] == 't') ? MAP_THUMB
12415
0
       : MAP_DATA);
12416
0
      return true;
12417
0
    }
12418
12419
18.6k
  return false;
12420
18.6k
}
12421
12422
/* Try to infer the code type (ARM or Thumb) from a mapping symbol.
12423
   Returns nonzero if *MAP_TYPE was set.  */
12424
12425
static int
12426
get_map_sym_type (struct disassemble_info *info,
12427
      int n,
12428
      enum map_type *map_type)
12429
2.29M
{
12430
  /* If the symbol is in a different section, ignore it.  */
12431
2.29M
  if (info->section != NULL && info->section != info->symtab[n]->section)
12432
2.27M
    return false;
12433
12434
18.6k
  return is_mapping_symbol (info, n, map_type);
12435
2.29M
}
12436
12437
/* Try to infer the code type (ARM or Thumb) from a non-mapping symbol.
12438
   Returns nonzero if *MAP_TYPE was set.  */
12439
12440
static int
12441
get_sym_code_type (struct disassemble_info *info,
12442
       int n,
12443
       enum map_type *map_type)
12444
338
{
12445
338
  elf_symbol_type *es;
12446
338
  unsigned int type;
12447
338
  asymbol * sym;
12448
12449
  /* If the symbol is in a different section, ignore it.  */
12450
338
  if (info->section != NULL && info->section != info->symtab[n]->section)
12451
0
    return false;
12452
12453
  /* PR 30230: Reject non-ELF symbols, eg synthetic ones.  */
12454
338
  sym = info->symtab[n];
12455
338
  if (bfd_asymbol_flavour (sym) != bfd_target_elf_flavour)
12456
333
    return false;
12457
12458
5
  es = (elf_symbol_type *) sym;
12459
5
  type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
12460
12461
  /* If the symbol has function type then use that.  */
12462
5
  if (type == STT_FUNC || type == STT_GNU_IFUNC)
12463
5
    {
12464
5
      if (ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
12465
5
    == ST_BRANCH_TO_THUMB)
12466
0
  *map_type = MAP_THUMB;
12467
5
      else
12468
5
  *map_type = MAP_ARM;
12469
5
      return true;
12470
5
    }
12471
12472
0
  return false;
12473
5
}
12474
12475
/* Search the mapping symbol state for instruction at pc.  This is only
12476
   applicable for elf target.
12477
12478
   There is an assumption Here, info->private_data contains the correct AND
12479
   up-to-date information about current scan process.  The information will be
12480
   used to speed this search process.
12481
12482
   Return TRUE if the mapping state can be determined, and map_symbol
12483
   will be updated accordingly.  Otherwise, return FALSE.  */
12484
12485
static bool
12486
mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
12487
       enum map_type *map_symbol)
12488
22.1k
{
12489
22.1k
  bfd_vma addr, section_vma = 0;
12490
22.1k
  int n, last_sym = -1;
12491
22.1k
  bool found = false;
12492
22.1k
  bool can_use_search_opt_p = false;
12493
12494
  /* Sanity check.  */
12495
22.1k
  if (info == NULL)
12496
0
    return false;
12497
12498
  /* Default to DATA.  A text section is required by the ABI to contain an
12499
     INSN mapping symbol at the start.  A data section has no such
12500
     requirement, hence if no mapping symbol is found the section must
12501
     contain only data.  This however isn't very useful if the user has
12502
     fully stripped the binaries.  If this is the case use the section
12503
     attributes to determine the default.  If we have no section default to
12504
     INSN as well, as we may be disassembling some raw bytes on a baremetal
12505
     HEX file or similar.  */
12506
22.1k
  enum map_type type = MAP_DATA;
12507
22.1k
  if ((info->section && info->section->flags & SEC_CODE) || !info->section)
12508
17.1k
    type = MAP_ARM;
12509
22.1k
  struct arm_private_data *private_data;
12510
12511
22.1k
  if (info->private_data == NULL || info->symtab == NULL
12512
22.1k
      || info->symtab_size == 0
12513
22.1k
      || bfd_asymbol_flavour (*info->symtab) != bfd_target_elf_flavour)
12514
0
    return false;
12515
12516
22.1k
  private_data = info->private_data;
12517
12518
  /* First, look for mapping symbols.  */
12519
22.1k
  if (pc <= private_data->last_mapping_addr)
12520
2
    private_data->last_mapping_sym = -1;
12521
12522
  /* Start scanning at the start of the function, or wherever
12523
     we finished last time.  */
12524
22.1k
  n = info->symtab_pos + 1;
12525
12526
  /* If the last stop offset is different from the current one it means we
12527
     are disassembling a different glob of bytes.  As such the optimization
12528
     would not be safe and we should start over.  */
12529
22.1k
  can_use_search_opt_p
12530
22.1k
    = (private_data->last_mapping_sym >= 0
12531
22.1k
       && info->stop_offset == private_data->last_stop_offset);
12532
12533
22.1k
  if (n >= private_data->last_mapping_sym && can_use_search_opt_p)
12534
3
    n = private_data->last_mapping_sym;
12535
12536
  /* Look down while we haven't passed the location being disassembled.
12537
     The reason for this is that there's no defined order between a symbol
12538
     and an mapping symbol that may be at the same address.  We may have to
12539
     look at least one position ahead.  */
12540
2.29M
  for (; n < info->symtab_size; n++)
12541
2.29M
    {
12542
2.29M
      addr = bfd_asymbol_value (info->symtab[n]);
12543
2.29M
      if (addr > pc)
12544
22.1k
  break;
12545
2.27M
      if (get_map_sym_type (info, n, &type))
12546
0
  {
12547
0
    last_sym = n;
12548
0
    found = true;
12549
0
  }
12550
2.27M
    }
12551
12552
22.1k
  if (!found)
12553
22.1k
    {
12554
22.1k
      n = info->symtab_pos;
12555
22.1k
      if (n >= private_data->last_mapping_sym && can_use_search_opt_p)
12556
3
  n = private_data->last_mapping_sym;
12557
12558
      /* No mapping symbol found at this address.  Look backwards
12559
   for a preceeding one, but don't go pass the section start
12560
   otherwise a data section with no mapping symbol can pick up
12561
   a text mapping symbol of a preceeding section.  The documentation
12562
   says section can be NULL, in which case we will seek up all the
12563
   way to the top.  */
12564
22.1k
      if (info->section)
12565
22.1k
  section_vma = info->section->vma;
12566
12567
40.7k
      for (; n >= 0; n--)
12568
18.9k
  {
12569
18.9k
    addr = bfd_asymbol_value (info->symtab[n]);
12570
18.9k
    if (addr < section_vma)
12571
335
      break;
12572
12573
18.6k
    if (get_map_sym_type (info, n, &type))
12574
0
      {
12575
0
        last_sym = n;
12576
0
        found = true;
12577
0
        break;
12578
0
      }
12579
18.6k
  }
12580
22.1k
    }
12581
12582
  /* If no mapping symbol was found, try looking up without a mapping
12583
     symbol.  This is done by walking up from the current PC to the nearest
12584
     symbol.  We don't actually have to loop here since symtab_pos will
12585
     contain the nearest symbol already.  */
12586
22.1k
  if (!found)
12587
22.1k
    {
12588
22.1k
      n = info->symtab_pos;
12589
22.1k
      if (n >= 0 && get_sym_code_type (info, n, &type))
12590
5
  {
12591
5
    last_sym = n;
12592
5
    found = true;
12593
5
  }
12594
22.1k
    }
12595
12596
22.1k
  private_data->last_mapping_sym = last_sym;
12597
22.1k
  private_data->last_type = type;
12598
22.1k
  private_data->last_stop_offset = info->stop_offset;
12599
12600
22.1k
  *map_symbol = type;
12601
22.1k
  return found;
12602
22.1k
}
12603
12604
/* Given a bfd_mach_arm_XXX value, this function fills in the fields
12605
   of the supplied arm_feature_set structure with bitmasks indicating
12606
   the supported base architectures and coprocessor extensions.
12607
12608
   FIXME: This could more efficiently implemented as a constant array,
12609
   although it would also be less robust.  */
12610
12611
static void
12612
select_arm_features (unsigned long mach,
12613
         arm_feature_set * features)
12614
1.18k
{
12615
1.18k
  arm_feature_set arch_fset;
12616
1.18k
  const arm_feature_set fpu_any = FPU_ANY;
12617
12618
1.18k
#undef ARM_SET_FEATURES
12619
1.18k
#define ARM_SET_FEATURES(FSET) \
12620
1.18k
  {             \
12621
1.18k
    const arm_feature_set fset = FSET;      \
12622
1.18k
    arch_fset = fset;         \
12623
1.18k
  }
12624
12625
  /* When several architecture versions share the same bfd_mach_arm_XXX value
12626
     the most featureful is chosen.  */
12627
1.18k
  switch (mach)
12628
1.18k
    {
12629
0
    case bfd_mach_arm_2:  ARM_SET_FEATURES (ARM_ARCH_V2); break;
12630
0
    case bfd_mach_arm_2a:  ARM_SET_FEATURES (ARM_ARCH_V2S); break;
12631
0
    case bfd_mach_arm_3:  ARM_SET_FEATURES (ARM_ARCH_V3); break;
12632
0
    case bfd_mach_arm_3M:  ARM_SET_FEATURES (ARM_ARCH_V3M); break;
12633
0
    case bfd_mach_arm_4:  ARM_SET_FEATURES (ARM_ARCH_V4); break;
12634
0
    case bfd_mach_arm_4T:  ARM_SET_FEATURES (ARM_ARCH_V4T); break;
12635
0
    case bfd_mach_arm_5:  ARM_SET_FEATURES (ARM_ARCH_V5); break;
12636
0
    case bfd_mach_arm_5T:  ARM_SET_FEATURES (ARM_ARCH_V5T); break;
12637
0
    case bfd_mach_arm_5TE:  ARM_SET_FEATURES (ARM_ARCH_V5TE); break;
12638
0
    case bfd_mach_arm_XScale:  ARM_SET_FEATURES (ARM_ARCH_XSCALE); break;
12639
0
    case bfd_mach_arm_ep9312:
12640
0
  ARM_SET_FEATURES (ARM_FEATURE_LOW (ARM_AEXT_V4T,
12641
0
             ARM_CEXT_MAVERICK | FPU_MAVERICK));
12642
0
       break;
12643
0
    case bfd_mach_arm_iWMMXt:  ARM_SET_FEATURES (ARM_ARCH_IWMMXT); break;
12644
0
    case bfd_mach_arm_iWMMXt2:  ARM_SET_FEATURES (ARM_ARCH_IWMMXT2); break;
12645
0
    case bfd_mach_arm_5TEJ:  ARM_SET_FEATURES (ARM_ARCH_V5TEJ); break;
12646
0
    case bfd_mach_arm_6:  ARM_SET_FEATURES (ARM_ARCH_V6); break;
12647
0
    case bfd_mach_arm_6KZ:  ARM_SET_FEATURES (ARM_ARCH_V6KZ); break;
12648
0
    case bfd_mach_arm_6T2:  ARM_SET_FEATURES (ARM_ARCH_V6KZT2); break;
12649
0
    case bfd_mach_arm_6K:  ARM_SET_FEATURES (ARM_ARCH_V6K); break;
12650
0
    case bfd_mach_arm_7:  ARM_SET_FEATURES (ARM_ARCH_V7VE); break;
12651
0
    case bfd_mach_arm_6M:  ARM_SET_FEATURES (ARM_ARCH_V6M); break;
12652
0
    case bfd_mach_arm_6SM:  ARM_SET_FEATURES (ARM_ARCH_V6SM); break;
12653
0
    case bfd_mach_arm_7EM:  ARM_SET_FEATURES (ARM_ARCH_V7EM); break;
12654
0
    case bfd_mach_arm_8:
12655
0
  {
12656
    /* Add bits for extensions that Armv8.6-A recognizes.  */
12657
0
    arm_feature_set armv8_6_ext_fset
12658
0
      = ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST);
12659
0
    ARM_SET_FEATURES (ARM_ARCH_V8_6A);
12660
0
    ARM_MERGE_FEATURE_SETS (arch_fset, arch_fset, armv8_6_ext_fset);
12661
0
    break;
12662
0
  }
12663
0
    case bfd_mach_arm_8R:  ARM_SET_FEATURES (ARM_ARCH_V8R); break;
12664
0
    case bfd_mach_arm_8M_BASE:  ARM_SET_FEATURES (ARM_ARCH_V8M_BASE); break;
12665
0
    case bfd_mach_arm_8M_MAIN:  ARM_SET_FEATURES (ARM_ARCH_V8M_MAIN); break;
12666
0
    case bfd_mach_arm_8_1M_MAIN:
12667
0
      ARM_SET_FEATURES (ARM_ARCH_V8_1M_MAIN);
12668
0
      arm_feature_set mve_all
12669
0
  = ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE | ARM_EXT2_MVE_FP);
12670
0
      ARM_MERGE_FEATURE_SETS (arch_fset, arch_fset, mve_all);
12671
0
      force_thumb = 1;
12672
0
      break;
12673
0
    case bfd_mach_arm_9:         ARM_SET_FEATURES (ARM_ARCH_V9A); break;
12674
      /* If the machine type is unknown allow all architecture types and all
12675
   extensions, with the exception of MVE as that clashes with NEON.  */
12676
1.18k
    case bfd_mach_arm_unknown:
12677
1.18k
      ARM_SET_FEATURES (ARM_ARCH_UNKNOWN);
12678
1.18k
      break;
12679
0
    default:
12680
0
      abort ();
12681
1.18k
    }
12682
1.18k
#undef ARM_SET_FEATURES
12683
12684
  /* None of the feature bits related to -mfpu have an impact on Tag_CPU_arch
12685
     and thus on bfd_mach_arm_XXX value.  Therefore for a given
12686
     bfd_mach_arm_XXX value all coprocessor feature bits should be allowed.  */
12687
1.18k
  ARM_MERGE_FEATURE_SETS (*features, arch_fset, fpu_any);
12688
1.18k
}
12689
12690
12691
/* NOTE: There are no checks in these routines that
12692
   the relevant number of data bytes exist.  */
12693
12694
static int
12695
print_insn (bfd_vma pc, struct disassemble_info *info, bool little)
12696
5.61M
{
12697
5.61M
  unsigned char b[4];
12698
5.61M
  unsigned long given;
12699
5.61M
  int status;
12700
5.61M
  int is_thumb = false;
12701
5.61M
  int is_data = false;
12702
5.61M
  int little_code;
12703
5.61M
  unsigned int  size = 4;
12704
5.61M
  void (*printer) (bfd_vma, struct disassemble_info *, long);
12705
5.61M
  bool found = false;
12706
5.61M
  struct arm_private_data *private_data;
12707
12708
  /* Clear instruction information field.  */
12709
5.61M
  info->insn_info_valid = 0;
12710
5.61M
  info->branch_delay_insns = 0;
12711
5.61M
  info->data_size = 0;
12712
5.61M
  info->insn_type = dis_noninsn;
12713
5.61M
  info->target = 0;
12714
5.61M
  info->target2 = 0;
12715
12716
5.61M
  if (info->disassembler_options)
12717
17.7k
    {
12718
17.7k
      parse_arm_disassembler_options (info->disassembler_options);
12719
12720
      /* To avoid repeated parsing of these options, we remove them here.  */
12721
17.7k
      info->disassembler_options = NULL;
12722
17.7k
    }
12723
12724
  /* PR 10288: Control which instructions will be disassembled.  */
12725
5.61M
  if (info->private_data == NULL)
12726
1.18k
    {
12727
1.18k
      static struct arm_private_data private;
12728
12729
1.18k
      if ((info->flags & USER_SPECIFIED_MACHINE_TYPE) == 0)
12730
  /* If the user did not use the -m command line switch then default to
12731
     disassembling all types of ARM instruction.
12732
12733
     The info->mach value has to be ignored as this will be based on
12734
     the default archictecture for the target and/or hints in the notes
12735
     section, but it will never be greater than the current largest arm
12736
     machine value (iWMMXt2), which is only equivalent to the V5TE
12737
     architecture.  ARM architectures have advanced beyond the machine
12738
     value encoding, and these newer architectures would be ignored if
12739
     the machine value was used.
12740
12741
     Ie the -m switch is used to restrict which instructions will be
12742
     disassembled.  If it is necessary to use the -m switch to tell
12743
     objdump that an ARM binary is being disassembled, eg because the
12744
     input is a raw binary file, but it is also desired to disassemble
12745
     all ARM instructions then use "-marm".  This will select the
12746
     "unknown" arm architecture which is compatible with any ARM
12747
     instruction.  */
12748
1.18k
    info->mach = bfd_mach_arm_unknown;
12749
12750
      /* Compute the architecture bitmask from the machine number.
12751
   Note: This assumes that the machine number will not change
12752
   during disassembly....  */
12753
1.18k
      select_arm_features (info->mach, & private.features);
12754
12755
1.18k
      private.last_mapping_sym = -1;
12756
1.18k
      private.last_mapping_addr = 0;
12757
1.18k
      private.last_stop_offset = 0;
12758
12759
1.18k
      info->private_data = & private;
12760
1.18k
    }
12761
12762
5.61M
  private_data = info->private_data;
12763
12764
  /* Decide if our code is going to be little-endian, despite what the
12765
     function argument might say.  */
12766
5.61M
  little_code = ((info->endian_code == BFD_ENDIAN_LITTLE) || little);
12767
12768
  /* For ELF, consult the symbol table to determine what kind of code
12769
     or data we have.  */
12770
5.61M
  if (info->symtab_size != 0
12771
5.61M
      && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour)
12772
22.1k
    {
12773
22.1k
      bfd_vma addr;
12774
22.1k
      int n;
12775
22.1k
      int last_sym = -1;
12776
22.1k
      enum map_type type = MAP_ARM;
12777
12778
22.1k
      found = mapping_symbol_for_insn (pc, info, &type);
12779
22.1k
      last_sym = private_data->last_mapping_sym;
12780
12781
22.1k
      is_thumb = (private_data->last_type == MAP_THUMB);
12782
22.1k
      is_data = (private_data->last_type == MAP_DATA);
12783
12784
      /* Look a little bit ahead to see if we should print out
12785
   two or four bytes of data.  If there's a symbol,
12786
   mapping or otherwise, after two bytes then don't
12787
   print more.  */
12788
22.1k
      if (is_data)
12789
5.00k
  {
12790
5.00k
    size = 4 - (pc & 3);
12791
650k
    for (n = last_sym + 1; n < info->symtab_size; n++)
12792
645k
      {
12793
645k
        addr = bfd_asymbol_value (info->symtab[n]);
12794
645k
        if (addr > pc
12795
645k
      && (info->section == NULL
12796
252k
          || info->section == info->symtab[n]->section))
12797
53
    {
12798
53
      if (addr - pc < size)
12799
0
        size = addr - pc;
12800
53
      break;
12801
53
    }
12802
645k
      }
12803
    /* If the next symbol is after three bytes, we need to
12804
       print only part of the data, so that we can use either
12805
       .byte or .short.  */
12806
5.00k
    if (size == 3)
12807
0
      size = (pc & 1) ? 1 : 2;
12808
5.00k
  }
12809
22.1k
    }
12810
12811
5.61M
  if (info->symbols != NULL)
12812
363k
    {
12813
363k
      if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour)
12814
0
  {
12815
0
    coff_symbol_type * cs;
12816
12817
0
    cs = coffsymbol (*info->symbols);
12818
0
    is_thumb = (   cs->native->u.syment.n_sclass == C_THUMBEXT
12819
0
          || cs->native->u.syment.n_sclass == C_THUMBSTAT
12820
0
          || cs->native->u.syment.n_sclass == C_THUMBLABEL
12821
0
          || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC
12822
0
          || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC);
12823
0
  }
12824
363k
      else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour
12825
363k
         && !found)
12826
0
  {
12827
    /* If no mapping symbol has been found then fall back to the type
12828
       of the function symbol.  */
12829
0
    elf_symbol_type *  es;
12830
0
    unsigned int       type;
12831
12832
0
    es = *(elf_symbol_type **)(info->symbols);
12833
0
    type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
12834
12835
0
    is_thumb =
12836
0
      ((ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
12837
0
        == ST_BRANCH_TO_THUMB) || type == STT_ARM_16BIT);
12838
0
  }
12839
363k
      else if (bfd_asymbol_flavour (*info->symbols)
12840
363k
         == bfd_target_mach_o_flavour)
12841
362k
  {
12842
362k
    bfd_mach_o_asymbol *asym = (bfd_mach_o_asymbol *)*info->symbols;
12843
12844
362k
    is_thumb = (asym->n_desc & BFD_MACH_O_N_ARM_THUMB_DEF);
12845
362k
  }
12846
363k
    }
12847
12848
5.61M
  if (force_thumb)
12849
1.29M
    is_thumb = true;
12850
12851
5.61M
  if (is_data)
12852
5.00k
    info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
12853
5.61M
  else
12854
5.61M
    info->display_endian = little_code ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
12855
12856
5.61M
  info->bytes_per_line = 4;
12857
12858
  /* PR 10263: Disassemble data if requested to do so by the user.  */
12859
5.61M
  if (is_data && ((info->flags & DISASSEMBLE_DATA) == 0))
12860
0
    {
12861
0
      int i;
12862
12863
      /* Size was already set above.  */
12864
0
      info->bytes_per_chunk = size;
12865
0
      printer = print_insn_data;
12866
12867
0
      status = info->read_memory_func (pc, (bfd_byte *) b, size, info);
12868
0
      given = 0;
12869
0
      if (little)
12870
0
  for (i = size - 1; i >= 0; i--)
12871
0
    given = b[i] | (given << 8);
12872
0
      else
12873
0
  for (i = 0; i < (int) size; i++)
12874
0
    given = b[i] | (given << 8);
12875
0
    }
12876
5.61M
  else if (!is_thumb)
12877
3.96M
    {
12878
      /* In ARM mode endianness is a straightforward issue: the instruction
12879
   is four bytes long and is either ordered 0123 or 3210.  */
12880
3.96M
      printer = print_insn_arm;
12881
3.96M
      info->bytes_per_chunk = 4;
12882
3.96M
      size = 4;
12883
12884
3.96M
      status = info->read_memory_func (pc, (bfd_byte *) b, 4, info);
12885
3.96M
      if (little_code)
12886
1.48M
  given = (b[0]) | (b[1] << 8) | (b[2] << 16) | ((unsigned) b[3] << 24);
12887
2.48M
      else
12888
2.48M
  given = (b[3]) | (b[2] << 8) | (b[1] << 16) | ((unsigned) b[0] << 24);
12889
3.96M
    }
12890
1.64M
  else
12891
1.64M
    {
12892
      /* In Thumb mode we have the additional wrinkle of two
12893
   instruction lengths.  Fortunately, the bits that determine
12894
   the length of the current instruction are always to be found
12895
   in the first two bytes.  */
12896
1.64M
      printer = print_insn_thumb16;
12897
1.64M
      info->bytes_per_chunk = 2;
12898
1.64M
      size = 2;
12899
12900
1.64M
      status = info->read_memory_func (pc, (bfd_byte *) b, 2, info);
12901
1.64M
      if (little_code)
12902
1.00M
  given = (b[0]) | (b[1] << 8);
12903
644k
      else
12904
644k
  given = (b[1]) | (b[0] << 8);
12905
12906
1.64M
      if (!status)
12907
1.64M
  {
12908
    /* These bit patterns signal a four-byte Thumb
12909
       instruction.  */
12910
1.64M
    if ((given & 0xF800) == 0xF800
12911
1.64M
        || (given & 0xF800) == 0xF000
12912
1.64M
        || (given & 0xF800) == 0xE800)
12913
436k
      {
12914
436k
        status = info->read_memory_func (pc + 2, (bfd_byte *) b, 2, info);
12915
436k
        if (little_code)
12916
230k
    given = (b[0]) | (b[1] << 8) | (given << 16);
12917
206k
        else
12918
206k
    given = (b[1]) | (b[0] << 8) | (given << 16);
12919
12920
436k
        printer = print_insn_thumb32;
12921
436k
        size = 4;
12922
436k
      }
12923
1.64M
  }
12924
12925
1.64M
      if (ifthen_address != pc)
12926
12.9k
  find_ifthen_state (pc, info, little_code);
12927
12928
1.64M
      if (ifthen_state)
12929
49.9k
  {
12930
49.9k
    if ((ifthen_state & 0xf) == 0x8)
12931
11.4k
      ifthen_next_state = 0;
12932
38.4k
    else
12933
38.4k
      ifthen_next_state = (ifthen_state & 0xe0)
12934
38.4k
        | ((ifthen_state & 0xf) << 1);
12935
49.9k
  }
12936
1.64M
    }
12937
12938
5.61M
  if (status)
12939
10.7k
    {
12940
10.7k
      info->memory_error_func (status, pc, info);
12941
10.7k
      return -1;
12942
10.7k
    }
12943
5.60M
  if (info->flags & INSN_HAS_RELOC)
12944
    /* If the instruction has a reloc associated with it, then
12945
       the offset field in the instruction will actually be the
12946
       addend for the reloc.  (We are using REL type relocs).
12947
       In such cases, we can ignore the pc when computing
12948
       addresses, since the addend is not currently pc-relative.  */
12949
0
    pc = 0;
12950
12951
5.60M
  printer (pc, info, given);
12952
12953
5.60M
  if (is_thumb)
12954
1.64M
    {
12955
1.64M
      ifthen_state = ifthen_next_state;
12956
1.64M
      ifthen_address += size;
12957
1.64M
    }
12958
5.60M
  return size;
12959
5.61M
}
12960
12961
int
12962
print_insn_big_arm (bfd_vma pc, struct disassemble_info *info)
12963
3.20M
{
12964
  /* Detect BE8-ness and record it in the disassembler info.  */
12965
3.20M
  if (info->flavour == bfd_target_elf_flavour
12966
3.20M
      && info->section != NULL
12967
3.20M
      && (elf_elfheader (info->section->owner)->e_flags & EF_ARM_BE8))
12968
69.0k
    info->endian_code = BFD_ENDIAN_LITTLE;
12969
12970
3.20M
  return print_insn (pc, info, false);
12971
3.20M
}
12972
12973
int
12974
print_insn_little_arm (bfd_vma pc, struct disassemble_info *info)
12975
2.41M
{
12976
2.41M
  return print_insn (pc, info, true);
12977
2.41M
}
12978
12979
const disasm_options_and_args_t *
12980
disassembler_options_arm (void)
12981
0
{
12982
0
  static disasm_options_and_args_t *opts_and_args;
12983
12984
0
  if (opts_and_args == NULL)
12985
0
    {
12986
0
      disasm_options_t *opts;
12987
0
      unsigned int i;
12988
12989
0
      opts_and_args = XNEW (disasm_options_and_args_t);
12990
0
      opts_and_args->args = NULL;
12991
12992
0
      opts = &opts_and_args->options;
12993
0
      opts->name = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
12994
0
      opts->description = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
12995
0
      opts->arg = NULL;
12996
0
      for (i = 0; i < NUM_ARM_OPTIONS; i++)
12997
0
  {
12998
0
    opts->name[i] = regnames[i].name;
12999
0
    if (regnames[i].description != NULL)
13000
0
      opts->description[i] = _(regnames[i].description);
13001
0
    else
13002
0
      opts->description[i] = NULL;
13003
0
  }
13004
      /* The array we return must be NULL terminated.  */
13005
0
      opts->name[i] = NULL;
13006
0
      opts->description[i] = NULL;
13007
0
    }
13008
13009
0
  return opts_and_args;
13010
0
}
13011
13012
void
13013
print_arm_disassembler_options (FILE *stream)
13014
0
{
13015
0
  unsigned int i, max_len = 0;
13016
0
  fprintf (stream, _("\n\
13017
0
The following ARM specific disassembler options are supported for use with\n\
13018
0
the -M switch:\n"));
13019
13020
0
  for (i = 0; i < NUM_ARM_OPTIONS; i++)
13021
0
    {
13022
0
      unsigned int len = strlen (regnames[i].name);
13023
0
      if (max_len < len)
13024
0
  max_len = len;
13025
0
    }
13026
13027
0
  for (i = 0, max_len++; i < NUM_ARM_OPTIONS; i++)
13028
0
    fprintf (stream, "  %s%*c %s\n",
13029
0
       regnames[i].name,
13030
0
       (int)(max_len - strlen (regnames[i].name)), ' ',
13031
0
       _(regnames[i].description));
13032
0
}