Coverage Report

Created: 2023-08-28 06:31

/src/binutils-gdb/opcodes/iq2000-desc.c
Line
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Source (jump to first uncovered line)
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/* DO NOT EDIT!  -*- buffer-read-only: t -*- vi:set ro:  */
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/* CPU data for iq2000.
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THIS FILE IS MACHINE GENERATED WITH CGEN.
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Copyright (C) 1996-2023 Free Software Foundation, Inc.
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This file is part of the GNU Binutils and/or GDB, the GNU debugger.
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   This file is free software; you can redistribute it and/or modify
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   it under the terms of the GNU General Public License as published by
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   the Free Software Foundation; either version 3, or (at your option)
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   any later version.
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   It is distributed in the hope that it will be useful, but WITHOUT
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   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
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   License for more details.
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   You should have received a copy of the GNU General Public License along
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   with this program; if not, write to the Free Software Foundation, Inc.,
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   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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#include "sysdep.h"
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#include <stdio.h>
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#include <stdarg.h>
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#include <stdlib.h>
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#include "ansidecl.h"
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#include "bfd.h"
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#include "symcat.h"
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#include "iq2000-desc.h"
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#include "iq2000-opc.h"
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#include "opintl.h"
36
#include "libiberty.h"
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#include "xregex.h"
38
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/* Attributes.  */
40
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static const CGEN_ATTR_ENTRY bool_attr[] =
42
{
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  { "#f", 0 },
44
  { "#t", 1 },
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  { 0, 0 }
46
};
47
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static const CGEN_ATTR_ENTRY MACH_attr[] ATTRIBUTE_UNUSED =
49
{
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  { "base", MACH_BASE },
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  { "iq2000", MACH_IQ2000 },
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  { "iq10", MACH_IQ10 },
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  { "max", MACH_MAX },
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  { 0, 0 }
55
};
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static const CGEN_ATTR_ENTRY ISA_attr[] ATTRIBUTE_UNUSED =
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{
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  { "iq2000", ISA_IQ2000 },
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  { "max", ISA_MAX },
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  { 0, 0 }
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};
63
64
const CGEN_ATTR_TABLE iq2000_cgen_ifield_attr_table[] =
65
{
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  { "MACH", & MACH_attr[0], & MACH_attr[0] },
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  { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
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  { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
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  { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
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  { "RESERVED", &bool_attr[0], &bool_attr[0] },
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  { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
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  { "SIGNED", &bool_attr[0], &bool_attr[0] },
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  { 0, 0, 0 }
74
};
75
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const CGEN_ATTR_TABLE iq2000_cgen_hardware_attr_table[] =
77
{
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  { "MACH", & MACH_attr[0], & MACH_attr[0] },
79
  { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
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  { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
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  { "PC", &bool_attr[0], &bool_attr[0] },
82
  { "PROFILE", &bool_attr[0], &bool_attr[0] },
83
  { 0, 0, 0 }
84
};
85
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const CGEN_ATTR_TABLE iq2000_cgen_operand_attr_table[] =
87
{
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  { "MACH", & MACH_attr[0], & MACH_attr[0] },
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  { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
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  { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
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  { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
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  { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
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  { "SIGNED", &bool_attr[0], &bool_attr[0] },
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  { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
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  { "RELAX", &bool_attr[0], &bool_attr[0] },
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  { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
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  { 0, 0, 0 }
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};
99
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const CGEN_ATTR_TABLE iq2000_cgen_insn_attr_table[] =
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{
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  { "MACH", & MACH_attr[0], & MACH_attr[0] },
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  { "ALIAS", &bool_attr[0], &bool_attr[0] },
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  { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
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  { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
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  { "COND-CTI", &bool_attr[0], &bool_attr[0] },
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  { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
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  { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
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  { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
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  { "RELAXED", &bool_attr[0], &bool_attr[0] },
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  { "NO-DIS", &bool_attr[0], &bool_attr[0] },
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  { "PBB", &bool_attr[0], &bool_attr[0] },
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  { "YIELD-INSN", &bool_attr[0], &bool_attr[0] },
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  { "LOAD-DELAY", &bool_attr[0], &bool_attr[0] },
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  { "EVEN-REG-NUM", &bool_attr[0], &bool_attr[0] },
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  { "UNSUPPORTED", &bool_attr[0], &bool_attr[0] },
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  { "USES-RD", &bool_attr[0], &bool_attr[0] },
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  { "USES-RS", &bool_attr[0], &bool_attr[0] },
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  { "USES-RT", &bool_attr[0], &bool_attr[0] },
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  { "USES-R31", &bool_attr[0], &bool_attr[0] },
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  { 0, 0, 0 }
122
};
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/* Instruction set variants.  */
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static const CGEN_ISA iq2000_cgen_isa_table[] = {
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  { "iq2000", 32, 32, 32, 32 },
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  { 0, 0, 0, 0, 0 }
129
};
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/* Machine variants.  */
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static const CGEN_MACH iq2000_cgen_mach_table[] = {
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  { "iq2000", "iq2000", MACH_IQ2000, 0 },
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  { "iq10", "iq10", MACH_IQ10, 0 },
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  { 0, 0, 0, 0 }
137
};
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static CGEN_KEYWORD_ENTRY iq2000_cgen_opval_gr_names_entries[] =
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{
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  { "r0", 0, {0, {{{0, 0}}}}, 0, 0 },
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  { "%0", 0, {0, {{{0, 0}}}}, 0, 0 },
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  { "r1", 1, {0, {{{0, 0}}}}, 0, 0 },
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  { "%1", 1, {0, {{{0, 0}}}}, 0, 0 },
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  { "r2", 2, {0, {{{0, 0}}}}, 0, 0 },
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  { "%2", 2, {0, {{{0, 0}}}}, 0, 0 },
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  { "r3", 3, {0, {{{0, 0}}}}, 0, 0 },
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  { "%3", 3, {0, {{{0, 0}}}}, 0, 0 },
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  { "r4", 4, {0, {{{0, 0}}}}, 0, 0 },
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  { "%4", 4, {0, {{{0, 0}}}}, 0, 0 },
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  { "r5", 5, {0, {{{0, 0}}}}, 0, 0 },
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  { "%5", 5, {0, {{{0, 0}}}}, 0, 0 },
153
  { "r6", 6, {0, {{{0, 0}}}}, 0, 0 },
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  { "%6", 6, {0, {{{0, 0}}}}, 0, 0 },
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  { "r7", 7, {0, {{{0, 0}}}}, 0, 0 },
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  { "%7", 7, {0, {{{0, 0}}}}, 0, 0 },
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  { "r8", 8, {0, {{{0, 0}}}}, 0, 0 },
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  { "%8", 8, {0, {{{0, 0}}}}, 0, 0 },
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  { "r9", 9, {0, {{{0, 0}}}}, 0, 0 },
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  { "%9", 9, {0, {{{0, 0}}}}, 0, 0 },
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  { "r10", 10, {0, {{{0, 0}}}}, 0, 0 },
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  { "%10", 10, {0, {{{0, 0}}}}, 0, 0 },
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  { "r11", 11, {0, {{{0, 0}}}}, 0, 0 },
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  { "%11", 11, {0, {{{0, 0}}}}, 0, 0 },
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  { "r12", 12, {0, {{{0, 0}}}}, 0, 0 },
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  { "%12", 12, {0, {{{0, 0}}}}, 0, 0 },
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  { "r13", 13, {0, {{{0, 0}}}}, 0, 0 },
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  { "%13", 13, {0, {{{0, 0}}}}, 0, 0 },
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  { "r14", 14, {0, {{{0, 0}}}}, 0, 0 },
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  { "%14", 14, {0, {{{0, 0}}}}, 0, 0 },
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  { "r15", 15, {0, {{{0, 0}}}}, 0, 0 },
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  { "%15", 15, {0, {{{0, 0}}}}, 0, 0 },
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  { "r16", 16, {0, {{{0, 0}}}}, 0, 0 },
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  { "%16", 16, {0, {{{0, 0}}}}, 0, 0 },
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  { "r17", 17, {0, {{{0, 0}}}}, 0, 0 },
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  { "%17", 17, {0, {{{0, 0}}}}, 0, 0 },
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  { "r18", 18, {0, {{{0, 0}}}}, 0, 0 },
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  { "%18", 18, {0, {{{0, 0}}}}, 0, 0 },
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  { "r19", 19, {0, {{{0, 0}}}}, 0, 0 },
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  { "%19", 19, {0, {{{0, 0}}}}, 0, 0 },
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  { "r20", 20, {0, {{{0, 0}}}}, 0, 0 },
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  { "%20", 20, {0, {{{0, 0}}}}, 0, 0 },
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  { "r21", 21, {0, {{{0, 0}}}}, 0, 0 },
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  { "%21", 21, {0, {{{0, 0}}}}, 0, 0 },
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  { "r22", 22, {0, {{{0, 0}}}}, 0, 0 },
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  { "%22", 22, {0, {{{0, 0}}}}, 0, 0 },
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  { "r23", 23, {0, {{{0, 0}}}}, 0, 0 },
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  { "%23", 23, {0, {{{0, 0}}}}, 0, 0 },
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  { "r24", 24, {0, {{{0, 0}}}}, 0, 0 },
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  { "%24", 24, {0, {{{0, 0}}}}, 0, 0 },
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  { "r25", 25, {0, {{{0, 0}}}}, 0, 0 },
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  { "%25", 25, {0, {{{0, 0}}}}, 0, 0 },
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  { "r26", 26, {0, {{{0, 0}}}}, 0, 0 },
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  { "%26", 26, {0, {{{0, 0}}}}, 0, 0 },
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  { "r27", 27, {0, {{{0, 0}}}}, 0, 0 },
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  { "%27", 27, {0, {{{0, 0}}}}, 0, 0 },
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  { "r28", 28, {0, {{{0, 0}}}}, 0, 0 },
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  { "%28", 28, {0, {{{0, 0}}}}, 0, 0 },
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  { "r29", 29, {0, {{{0, 0}}}}, 0, 0 },
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  { "%29", 29, {0, {{{0, 0}}}}, 0, 0 },
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  { "r30", 30, {0, {{{0, 0}}}}, 0, 0 },
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  { "%30", 30, {0, {{{0, 0}}}}, 0, 0 },
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  { "r31", 31, {0, {{{0, 0}}}}, 0, 0 },
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  { "%31", 31, {0, {{{0, 0}}}}, 0, 0 }
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};
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CGEN_KEYWORD iq2000_cgen_opval_gr_names =
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{
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  & iq2000_cgen_opval_gr_names_entries[0],
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  64,
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  0, 0, 0, 0, ""
212
};
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/* The hardware table.  */
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#define A(a) (1 << CGEN_HW_##a)
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const CGEN_HW_ENTRY iq2000_cgen_hw_table[] =
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{
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  { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
222
  { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
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  { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
224
  { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
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  { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
226
  { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { { { (1<<MACH_BASE), 0 } } } } },
227
  { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, & iq2000_cgen_opval_gr_names, { 0, { { { (1<<MACH_BASE), 0 } } } } },
228
  { 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
229
};
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#undef A
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/* The instruction field table.  */
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#define A(a) (1 << CGEN_IFLD_##a)
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const CGEN_IFLD iq2000_cgen_ifld_table[] =
239
{
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  { IQ2000_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
241
  { IQ2000_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
242
  { IQ2000_F_OPCODE, "f-opcode", 0, 32, 31, 6, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
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  { IQ2000_F_RS, "f-rs", 0, 32, 25, 5, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
244
  { IQ2000_F_RT, "f-rt", 0, 32, 20, 5, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
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  { IQ2000_F_RD, "f-rd", 0, 32, 15, 5, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
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  { IQ2000_F_SHAMT, "f-shamt", 0, 32, 10, 5, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
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  { IQ2000_F_CP_OP, "f-cp-op", 0, 32, 10, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
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  { IQ2000_F_CP_OP_10, "f-cp-op-10", 0, 32, 10, 5, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
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  { IQ2000_F_CP_GRP, "f-cp-grp", 0, 32, 7, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
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  { IQ2000_F_FUNC, "f-func", 0, 32, 5, 6, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
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  { IQ2000_F_IMM, "f-imm", 0, 32, 15, 16, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
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  { IQ2000_F_RD_RS, "f-rd-rs", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
253
  { IQ2000_F_RD_RT, "f-rd-rt", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
254
  { IQ2000_F_RT_RS, "f-rt-rs", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
255
  { IQ2000_F_JTARG, "f-jtarg", 0, 32, 15, 16, { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
256
  { IQ2000_F_JTARGQ10, "f-jtargq10", 0, 32, 20, 21, { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
257
  { IQ2000_F_OFFSET, "f-offset", 0, 32, 15, 16, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
258
  { IQ2000_F_COUNT, "f-count", 0, 32, 15, 7, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
259
  { IQ2000_F_BYTECOUNT, "f-bytecount", 0, 32, 7, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
260
  { IQ2000_F_INDEX, "f-index", 0, 32, 8, 9, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
261
  { IQ2000_F_MASK, "f-mask", 0, 32, 9, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
262
  { IQ2000_F_MASKQ10, "f-maskq10", 0, 32, 10, 5, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
263
  { IQ2000_F_MASKL, "f-maskl", 0, 32, 4, 5, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
264
  { IQ2000_F_EXCODE, "f-excode", 0, 32, 25, 20, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
265
  { IQ2000_F_RSRVD, "f-rsrvd", 0, 32, 25, 10, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
266
  { IQ2000_F_10_11, "f-10-11", 0, 32, 10, 11, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
267
  { IQ2000_F_24_19, "f-24-19", 0, 32, 24, 19, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
268
  { IQ2000_F_5, "f-5", 0, 32, 5, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
269
  { IQ2000_F_10, "f-10", 0, 32, 10, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
270
  { IQ2000_F_25, "f-25", 0, 32, 25, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
271
  { IQ2000_F_CAM_Z, "f-cam-z", 0, 32, 5, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
272
  { IQ2000_F_CAM_Y, "f-cam-y", 0, 32, 2, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
273
  { IQ2000_F_CM_3FUNC, "f-cm-3func", 0, 32, 5, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
274
  { IQ2000_F_CM_4FUNC, "f-cm-4func", 0, 32, 5, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
275
  { IQ2000_F_CM_3Z, "f-cm-3z", 0, 32, 1, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
276
  { IQ2000_F_CM_4Z, "f-cm-4z", 0, 32, 2, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
277
  { 0, 0, 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
278
};
279
280
#undef A
281
282
283
284
/* multi ifield declarations */
285
286
const CGEN_MAYBE_MULTI_IFLD IQ2000_F_RD_RS_MULTI_IFIELD [];
287
const CGEN_MAYBE_MULTI_IFLD IQ2000_F_RD_RT_MULTI_IFIELD [];
288
const CGEN_MAYBE_MULTI_IFLD IQ2000_F_RT_RS_MULTI_IFIELD [];
289
290
291
/* multi ifield definitions */
292
293
const CGEN_MAYBE_MULTI_IFLD IQ2000_F_RD_RS_MULTI_IFIELD [] =
294
{
295
    { 0, { &iq2000_cgen_ifld_table[IQ2000_F_RD] } },
296
    { 0, { &iq2000_cgen_ifld_table[IQ2000_F_RS] } },
297
    { 0, { 0 } }
298
};
299
const CGEN_MAYBE_MULTI_IFLD IQ2000_F_RD_RT_MULTI_IFIELD [] =
300
{
301
    { 0, { &iq2000_cgen_ifld_table[IQ2000_F_RD] } },
302
    { 0, { &iq2000_cgen_ifld_table[IQ2000_F_RT] } },
303
    { 0, { 0 } }
304
};
305
const CGEN_MAYBE_MULTI_IFLD IQ2000_F_RT_RS_MULTI_IFIELD [] =
306
{
307
    { 0, { &iq2000_cgen_ifld_table[IQ2000_F_RT] } },
308
    { 0, { &iq2000_cgen_ifld_table[IQ2000_F_RS] } },
309
    { 0, { 0 } }
310
};
311
312
/* The operand table.  */
313
314
#define A(a) (1 << CGEN_OPERAND_##a)
315
#define OPERAND(op) IQ2000_OPERAND_##op
316
317
const CGEN_OPERAND iq2000_cgen_operand_table[] =
318
{
319
/* pc: program counter */
320
  { "pc", IQ2000_OPERAND_PC, HW_H_PC, 0, 0,
321
    { 0, { &iq2000_cgen_ifld_table[IQ2000_F_NIL] } },
322
    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
323
/* rs: register Rs */
324
  { "rs", IQ2000_OPERAND_RS, HW_H_GR, 25, 5,
325
    { 0, { &iq2000_cgen_ifld_table[IQ2000_F_RS] } },
326
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
327
/* rt: register Rt */
328
  { "rt", IQ2000_OPERAND_RT, HW_H_GR, 20, 5,
329
    { 0, { &iq2000_cgen_ifld_table[IQ2000_F_RT] } },
330
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
331
/* rd: register Rd */
332
  { "rd", IQ2000_OPERAND_RD, HW_H_GR, 15, 5,
333
    { 0, { &iq2000_cgen_ifld_table[IQ2000_F_RD] } },
334
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
335
/* rd-rs: register Rd from Rs */
336
  { "rd-rs", IQ2000_OPERAND_RD_RS, HW_H_GR, 15, 10,
337
    { 2, { &IQ2000_F_RD_RS_MULTI_IFIELD[0] } },
338
    { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
339
/* rd-rt: register Rd from Rt */
340
  { "rd-rt", IQ2000_OPERAND_RD_RT, HW_H_GR, 15, 10,
341
    { 2, { &IQ2000_F_RD_RT_MULTI_IFIELD[0] } },
342
    { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
343
/* rt-rs: register Rt from Rs */
344
  { "rt-rs", IQ2000_OPERAND_RT_RS, HW_H_GR, 20, 10,
345
    { 2, { &IQ2000_F_RT_RS_MULTI_IFIELD[0] } },
346
    { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
347
/* shamt: shift amount */
348
  { "shamt", IQ2000_OPERAND_SHAMT, HW_H_UINT, 10, 5,
349
    { 0, { &iq2000_cgen_ifld_table[IQ2000_F_SHAMT] } },
350
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
351
/* imm: immediate */
352
  { "imm", IQ2000_OPERAND_IMM, HW_H_UINT, 15, 16,
353
    { 0, { &iq2000_cgen_ifld_table[IQ2000_F_IMM] } },
354
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
355
/* offset: pc-relative offset */
356
  { "offset", IQ2000_OPERAND_OFFSET, HW_H_IADDR, 15, 16,
357
    { 0, { &iq2000_cgen_ifld_table[IQ2000_F_OFFSET] } },
358
    { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
359
/* baseoff: base register offset */
360
  { "baseoff", IQ2000_OPERAND_BASEOFF, HW_H_IADDR, 15, 16,
361
    { 0, { &iq2000_cgen_ifld_table[IQ2000_F_IMM] } },
362
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
363
/* jmptarg: jump target */
364
  { "jmptarg", IQ2000_OPERAND_JMPTARG, HW_H_IADDR, 15, 16,
365
    { 0, { &iq2000_cgen_ifld_table[IQ2000_F_JTARG] } },
366
    { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
367
/* mask: mask */
368
  { "mask", IQ2000_OPERAND_MASK, HW_H_UINT, 9, 4,
369
    { 0, { &iq2000_cgen_ifld_table[IQ2000_F_MASK] } },
370
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
371
/* maskq10: iq10 mask */
372
  { "maskq10", IQ2000_OPERAND_MASKQ10, HW_H_UINT, 10, 5,
373
    { 0, { &iq2000_cgen_ifld_table[IQ2000_F_MASKQ10] } },
374
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
375
/* maskl: mask left */
376
  { "maskl", IQ2000_OPERAND_MASKL, HW_H_UINT, 4, 5,
377
    { 0, { &iq2000_cgen_ifld_table[IQ2000_F_MASKL] } },
378
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
379
/* count: count */
380
  { "count", IQ2000_OPERAND_COUNT, HW_H_UINT, 15, 7,
381
    { 0, { &iq2000_cgen_ifld_table[IQ2000_F_COUNT] } },
382
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
383
/* _index: index */
384
  { "_index", IQ2000_OPERAND__INDEX, HW_H_UINT, 8, 9,
385
    { 0, { &iq2000_cgen_ifld_table[IQ2000_F_INDEX] } },
386
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
387
/* execode: execcode */
388
  { "execode", IQ2000_OPERAND_EXECODE, HW_H_UINT, 25, 20,
389
    { 0, { &iq2000_cgen_ifld_table[IQ2000_F_EXCODE] } },
390
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
391
/* bytecount: byte count */
392
  { "bytecount", IQ2000_OPERAND_BYTECOUNT, HW_H_UINT, 7, 8,
393
    { 0, { &iq2000_cgen_ifld_table[IQ2000_F_BYTECOUNT] } },
394
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
395
/* cam-y: cam global opn y */
396
  { "cam-y", IQ2000_OPERAND_CAM_Y, HW_H_UINT, 2, 3,
397
    { 0, { &iq2000_cgen_ifld_table[IQ2000_F_CAM_Y] } },
398
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
399
/* cam-z: cam global mask z */
400
  { "cam-z", IQ2000_OPERAND_CAM_Z, HW_H_UINT, 5, 3,
401
    { 0, { &iq2000_cgen_ifld_table[IQ2000_F_CAM_Z] } },
402
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
403
/* cm-3func: CM 3 bit fn field */
404
  { "cm-3func", IQ2000_OPERAND_CM_3FUNC, HW_H_UINT, 5, 3,
405
    { 0, { &iq2000_cgen_ifld_table[IQ2000_F_CM_3FUNC] } },
406
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
407
/* cm-4func: CM 4 bit fn field */
408
  { "cm-4func", IQ2000_OPERAND_CM_4FUNC, HW_H_UINT, 5, 4,
409
    { 0, { &iq2000_cgen_ifld_table[IQ2000_F_CM_4FUNC] } },
410
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
411
/* cm-3z: CM 3 bit Z field */
412
  { "cm-3z", IQ2000_OPERAND_CM_3Z, HW_H_UINT, 1, 2,
413
    { 0, { &iq2000_cgen_ifld_table[IQ2000_F_CM_3Z] } },
414
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
415
/* cm-4z: CM 4 bit Z field */
416
  { "cm-4z", IQ2000_OPERAND_CM_4Z, HW_H_UINT, 2, 3,
417
    { 0, { &iq2000_cgen_ifld_table[IQ2000_F_CM_4Z] } },
418
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
419
/* base: base register */
420
  { "base", IQ2000_OPERAND_BASE, HW_H_GR, 25, 5,
421
    { 0, { &iq2000_cgen_ifld_table[IQ2000_F_RS] } },
422
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
423
/* maskr: mask right */
424
  { "maskr", IQ2000_OPERAND_MASKR, HW_H_UINT, 25, 5,
425
    { 0, { &iq2000_cgen_ifld_table[IQ2000_F_RS] } },
426
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
427
/* bitnum: bit number */
428
  { "bitnum", IQ2000_OPERAND_BITNUM, HW_H_UINT, 20, 5,
429
    { 0, { &iq2000_cgen_ifld_table[IQ2000_F_RT] } },
430
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
431
/* hi16: high 16 bit immediate */
432
  { "hi16", IQ2000_OPERAND_HI16, HW_H_UINT, 15, 16,
433
    { 0, { &iq2000_cgen_ifld_table[IQ2000_F_IMM] } },
434
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
435
/* lo16: 16 bit signed immediate, for low */
436
  { "lo16", IQ2000_OPERAND_LO16, HW_H_UINT, 15, 16,
437
    { 0, { &iq2000_cgen_ifld_table[IQ2000_F_IMM] } },
438
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
439
/* mlo16: negated 16 bit signed immediate */
440
  { "mlo16", IQ2000_OPERAND_MLO16, HW_H_UINT, 15, 16,
441
    { 0, { &iq2000_cgen_ifld_table[IQ2000_F_IMM] } },
442
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
443
/* jmptargq10: iq10 21-bit jump offset */
444
  { "jmptargq10", IQ2000_OPERAND_JMPTARGQ10, HW_H_IADDR, 20, 21,
445
    { 0, { &iq2000_cgen_ifld_table[IQ2000_F_JTARGQ10] } },
446
    { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
447
/* sentinel */
448
  { 0, 0, 0, 0, 0,
449
    { 0, { 0 } },
450
    { 0, { { { (1<<MACH_BASE), 0 } } } } }
451
};
452
453
#undef A
454
455
456
/* The instruction table.  */
457
458
#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
459
#define A(a) (1 << CGEN_INSN_##a)
460
461
static const CGEN_IBASE iq2000_cgen_insn_table[MAX_INSNS] =
462
{
463
  /* Special null first entry.
464
     A `num' value of zero is thus invalid.
465
     Also, the special `invalid' insn resides here.  */
466
  { 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
467
/* add ${rd-rs},$rt */
468
  {
469
    -1, "add2", "add", 32,
470
    { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
471
  },
472
/* add $rd,$rs,$rt */
473
  {
474
    IQ2000_INSN_ADD, "add", "add", 32,
475
    { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } }
476
  },
477
/* addi ${rt-rs},$lo16 */
478
  {
479
    -1, "addi2", "addi", 32,
480
    { 0|A(USES_RT)|A(USES_RS)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
481
  },
482
/* addi $rt,$rs,$lo16 */
483
  {
484
    IQ2000_INSN_ADDI, "addi", "addi", 32,
485
    { 0|A(USES_RT)|A(USES_RS), { { { (1<<MACH_BASE), 0 } } } }
486
  },
487
/* addiu ${rt-rs},$lo16 */
488
  {
489
    -1, "addiu2", "addiu", 32,
490
    { 0|A(USES_RT)|A(USES_RS)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
491
  },
492
/* addiu $rt,$rs,$lo16 */
493
  {
494
    IQ2000_INSN_ADDIU, "addiu", "addiu", 32,
495
    { 0|A(USES_RT)|A(USES_RS), { { { (1<<MACH_BASE), 0 } } } }
496
  },
497
/* addu ${rd-rs},$rt */
498
  {
499
    -1, "addu2", "addu", 32,
500
    { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
501
  },
502
/* addu $rd,$rs,$rt */
503
  {
504
    IQ2000_INSN_ADDU, "addu", "addu", 32,
505
    { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } }
506
  },
507
/* ado16 ${rd-rs},$rt */
508
  {
509
    -1, "ado162", "ado16", 32,
510
    { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
511
  },
512
/* ado16 $rd,$rs,$rt */
513
  {
514
    IQ2000_INSN_ADO16, "ado16", "ado16", 32,
515
    { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } }
516
  },
517
/* and ${rd-rs},$rt */
518
  {
519
    -1, "and2", "and", 32,
520
    { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
521
  },
522
/* and $rd,$rs,$rt */
523
  {
524
    IQ2000_INSN_AND, "and", "and", 32,
525
    { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } }
526
  },
527
/* andi ${rt-rs},$lo16 */
528
  {
529
    -1, "andi2", "andi", 32,
530
    { 0|A(USES_RT)|A(USES_RS)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
531
  },
532
/* andi $rt,$rs,$lo16 */
533
  {
534
    IQ2000_INSN_ANDI, "andi", "andi", 32,
535
    { 0|A(USES_RT)|A(USES_RS), { { { (1<<MACH_BASE), 0 } } } }
536
  },
537
/* andoi ${rt-rs},$lo16 */
538
  {
539
    -1, "andoi2", "andoi", 32,
540
    { 0|A(USES_RT)|A(USES_RS)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
541
  },
542
/* andoi $rt,$rs,$lo16 */
543
  {
544
    IQ2000_INSN_ANDOI, "andoi", "andoi", 32,
545
    { 0|A(USES_RT)|A(USES_RS), { { { (1<<MACH_BASE), 0 } } } }
546
  },
547
/* nor ${rd-rs},$rt */
548
  {
549
    -1, "nor2", "nor", 32,
550
    { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
551
  },
552
/* nor $rd,$rs,$rt */
553
  {
554
    IQ2000_INSN_NOR, "nor", "nor", 32,
555
    { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } }
556
  },
557
/* or ${rd-rs},$rt */
558
  {
559
    -1, "or2", "or", 32,
560
    { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
561
  },
562
/* or $rd,$rs,$rt */
563
  {
564
    IQ2000_INSN_OR, "or", "or", 32,
565
    { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } }
566
  },
567
/* ori ${rt-rs},$lo16 */
568
  {
569
    -1, "ori2", "ori", 32,
570
    { 0|A(USES_RT)|A(USES_RS)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
571
  },
572
/* ori $rt,$rs,$lo16 */
573
  {
574
    IQ2000_INSN_ORI, "ori", "ori", 32,
575
    { 0|A(USES_RT)|A(USES_RS), { { { (1<<MACH_BASE), 0 } } } }
576
  },
577
/* ram $rd,$rt,$shamt,$maskl,$maskr */
578
  {
579
    IQ2000_INSN_RAM, "ram", "ram", 32,
580
    { 0|A(USES_RT)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } }
581
  },
582
/* sll $rd,$rt,$shamt */
583
  {
584
    IQ2000_INSN_SLL, "sll", "sll", 32,
585
    { 0|A(USES_RT)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } }
586
  },
587
/* sllv ${rd-rt},$rs */
588
  {
589
    -1, "sllv2", "sllv", 32,
590
    { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
591
  },
592
/* sllv $rd,$rt,$rs */
593
  {
594
    IQ2000_INSN_SLLV, "sllv", "sllv", 32,
595
    { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } }
596
  },
597
/* slmv ${rd-rt},$rs,$shamt */
598
  {
599
    -1, "slmv2", "slmv", 32,
600
    { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
601
  },
602
/* slmv $rd,$rt,$rs,$shamt */
603
  {
604
    IQ2000_INSN_SLMV, "slmv", "slmv", 32,
605
    { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } }
606
  },
607
/* slt ${rd-rs},$rt */
608
  {
609
    -1, "slt2", "slt", 32,
610
    { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
611
  },
612
/* slt $rd,$rs,$rt */
613
  {
614
    IQ2000_INSN_SLT, "slt", "slt", 32,
615
    { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } }
616
  },
617
/* slti ${rt-rs},$imm */
618
  {
619
    -1, "slti2", "slti", 32,
620
    { 0|A(USES_RT)|A(USES_RS)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
621
  },
622
/* slti $rt,$rs,$imm */
623
  {
624
    IQ2000_INSN_SLTI, "slti", "slti", 32,
625
    { 0|A(USES_RT)|A(USES_RS), { { { (1<<MACH_BASE), 0 } } } }
626
  },
627
/* sltiu ${rt-rs},$imm */
628
  {
629
    -1, "sltiu2", "sltiu", 32,
630
    { 0|A(USES_RT)|A(USES_RS)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
631
  },
632
/* sltiu $rt,$rs,$imm */
633
  {
634
    IQ2000_INSN_SLTIU, "sltiu", "sltiu", 32,
635
    { 0|A(USES_RT)|A(USES_RS), { { { (1<<MACH_BASE), 0 } } } }
636
  },
637
/* sltu ${rd-rs},$rt */
638
  {
639
    -1, "sltu2", "sltu", 32,
640
    { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
641
  },
642
/* sltu $rd,$rs,$rt */
643
  {
644
    IQ2000_INSN_SLTU, "sltu", "sltu", 32,
645
    { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } }
646
  },
647
/* sra ${rd-rt},$shamt */
648
  {
649
    -1, "sra2", "sra", 32,
650
    { 0|A(USES_RT)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
651
  },
652
/* sra $rd,$rt,$shamt */
653
  {
654
    IQ2000_INSN_SRA, "sra", "sra", 32,
655
    { 0|A(USES_RT)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } }
656
  },
657
/* srav ${rd-rt},$rs */
658
  {
659
    -1, "srav2", "srav", 32,
660
    { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
661
  },
662
/* srav $rd,$rt,$rs */
663
  {
664
    IQ2000_INSN_SRAV, "srav", "srav", 32,
665
    { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } }
666
  },
667
/* srl $rd,$rt,$shamt */
668
  {
669
    IQ2000_INSN_SRL, "srl", "srl", 32,
670
    { 0|A(USES_RT)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } }
671
  },
672
/* srlv ${rd-rt},$rs */
673
  {
674
    -1, "srlv2", "srlv", 32,
675
    { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
676
  },
677
/* srlv $rd,$rt,$rs */
678
  {
679
    IQ2000_INSN_SRLV, "srlv", "srlv", 32,
680
    { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } }
681
  },
682
/* srmv ${rd-rt},$rs,$shamt */
683
  {
684
    -1, "srmv2", "srmv", 32,
685
    { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
686
  },
687
/* srmv $rd,$rt,$rs,$shamt */
688
  {
689
    IQ2000_INSN_SRMV, "srmv", "srmv", 32,
690
    { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } }
691
  },
692
/* sub ${rd-rs},$rt */
693
  {
694
    -1, "sub2", "sub", 32,
695
    { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
696
  },
697
/* sub $rd,$rs,$rt */
698
  {
699
    IQ2000_INSN_SUB, "sub", "sub", 32,
700
    { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } }
701
  },
702
/* subu ${rd-rs},$rt */
703
  {
704
    -1, "subu2", "subu", 32,
705
    { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
706
  },
707
/* subu $rd,$rs,$rt */
708
  {
709
    IQ2000_INSN_SUBU, "subu", "subu", 32,
710
    { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } }
711
  },
712
/* xor ${rd-rs},$rt */
713
  {
714
    -1, "xor2", "xor", 32,
715
    { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
716
  },
717
/* xor $rd,$rs,$rt */
718
  {
719
    IQ2000_INSN_XOR, "xor", "xor", 32,
720
    { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } }
721
  },
722
/* xori ${rt-rs},$lo16 */
723
  {
724
    -1, "xori2", "xori", 32,
725
    { 0|A(USES_RT)|A(USES_RS)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
726
  },
727
/* xori $rt,$rs,$lo16 */
728
  {
729
    IQ2000_INSN_XORI, "xori", "xori", 32,
730
    { 0|A(USES_RT)|A(USES_RS), { { { (1<<MACH_BASE), 0 } } } }
731
  },
732
/* bbi $rs($bitnum),$offset */
733
  {
734
    IQ2000_INSN_BBI, "bbi", "bbi", 32,
735
    { 0|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
736
  },
737
/* bbin $rs($bitnum),$offset */
738
  {
739
    IQ2000_INSN_BBIN, "bbin", "bbin", 32,
740
    { 0|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
741
  },
742
/* bbv $rs,$rt,$offset */
743
  {
744
    IQ2000_INSN_BBV, "bbv", "bbv", 32,
745
    { 0|A(USES_RT)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
746
  },
747
/* bbvn $rs,$rt,$offset */
748
  {
749
    IQ2000_INSN_BBVN, "bbvn", "bbvn", 32,
750
    { 0|A(USES_RT)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
751
  },
752
/* beq $rs,$rt,$offset */
753
  {
754
    IQ2000_INSN_BEQ, "beq", "beq", 32,
755
    { 0|A(USES_RT)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
756
  },
757
/* beql $rs,$rt,$offset */
758
  {
759
    IQ2000_INSN_BEQL, "beql", "beql", 32,
760
    { 0|A(USES_RT)|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
761
  },
762
/* bgez $rs,$offset */
763
  {
764
    IQ2000_INSN_BGEZ, "bgez", "bgez", 32,
765
    { 0|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
766
  },
767
/* bgezal $rs,$offset */
768
  {
769
    IQ2000_INSN_BGEZAL, "bgezal", "bgezal", 32,
770
    { 0|A(USES_R31)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
771
  },
772
/* bgezall $rs,$offset */
773
  {
774
    IQ2000_INSN_BGEZALL, "bgezall", "bgezall", 32,
775
    { 0|A(USES_R31)|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
776
  },
777
/* bgezl $rs,$offset */
778
  {
779
    IQ2000_INSN_BGEZL, "bgezl", "bgezl", 32,
780
    { 0|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
781
  },
782
/* bltz $rs,$offset */
783
  {
784
    IQ2000_INSN_BLTZ, "bltz", "bltz", 32,
785
    { 0|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
786
  },
787
/* bltzl $rs,$offset */
788
  {
789
    IQ2000_INSN_BLTZL, "bltzl", "bltzl", 32,
790
    { 0|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
791
  },
792
/* bltzal $rs,$offset */
793
  {
794
    IQ2000_INSN_BLTZAL, "bltzal", "bltzal", 32,
795
    { 0|A(USES_R31)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
796
  },
797
/* bltzall $rs,$offset */
798
  {
799
    IQ2000_INSN_BLTZALL, "bltzall", "bltzall", 32,
800
    { 0|A(USES_R31)|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
801
  },
802
/* bmb0 $rs,$rt,$offset */
803
  {
804
    IQ2000_INSN_BMB0, "bmb0", "bmb0", 32,
805
    { 0|A(USES_RT)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
806
  },
807
/* bmb1 $rs,$rt,$offset */
808
  {
809
    IQ2000_INSN_BMB1, "bmb1", "bmb1", 32,
810
    { 0|A(USES_RT)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
811
  },
812
/* bmb2 $rs,$rt,$offset */
813
  {
814
    IQ2000_INSN_BMB2, "bmb2", "bmb2", 32,
815
    { 0|A(USES_RT)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
816
  },
817
/* bmb3 $rs,$rt,$offset */
818
  {
819
    IQ2000_INSN_BMB3, "bmb3", "bmb3", 32,
820
    { 0|A(USES_RT)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
821
  },
822
/* bne $rs,$rt,$offset */
823
  {
824
    IQ2000_INSN_BNE, "bne", "bne", 32,
825
    { 0|A(USES_RT)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
826
  },
827
/* bnel $rs,$rt,$offset */
828
  {
829
    IQ2000_INSN_BNEL, "bnel", "bnel", 32,
830
    { 0|A(USES_RT)|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
831
  },
832
/* jalr $rd,$rs */
833
  {
834
    IQ2000_INSN_JALR, "jalr", "jalr", 32,
835
    { 0|A(USES_RS)|A(USES_RD)|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
836
  },
837
/* jr $rs */
838
  {
839
    IQ2000_INSN_JR, "jr", "jr", 32,
840
    { 0|A(USES_RS)|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
841
  },
842
/* lb $rt,$lo16($base) */
843
  {
844
    IQ2000_INSN_LB, "lb", "lb", 32,
845
    { 0|A(USES_RT)|A(USES_RS)|A(LOAD_DELAY), { { { (1<<MACH_BASE), 0 } } } }
846
  },
847
/* lbu $rt,$lo16($base) */
848
  {
849
    IQ2000_INSN_LBU, "lbu", "lbu", 32,
850
    { 0|A(USES_RT)|A(USES_RS)|A(LOAD_DELAY), { { { (1<<MACH_BASE), 0 } } } }
851
  },
852
/* lh $rt,$lo16($base) */
853
  {
854
    IQ2000_INSN_LH, "lh", "lh", 32,
855
    { 0|A(USES_RT)|A(USES_RS)|A(LOAD_DELAY), { { { (1<<MACH_BASE), 0 } } } }
856
  },
857
/* lhu $rt,$lo16($base) */
858
  {
859
    IQ2000_INSN_LHU, "lhu", "lhu", 32,
860
    { 0|A(USES_RT)|A(USES_RS)|A(LOAD_DELAY), { { { (1<<MACH_BASE), 0 } } } }
861
  },
862
/* lui $rt,$hi16 */
863
  {
864
    IQ2000_INSN_LUI, "lui", "lui", 32,
865
    { 0|A(USES_RT), { { { (1<<MACH_BASE), 0 } } } }
866
  },
867
/* lw $rt,$lo16($base) */
868
  {
869
    IQ2000_INSN_LW, "lw", "lw", 32,
870
    { 0|A(USES_RT)|A(USES_RS)|A(LOAD_DELAY), { { { (1<<MACH_BASE), 0 } } } }
871
  },
872
/* sb $rt,$lo16($base) */
873
  {
874
    IQ2000_INSN_SB, "sb", "sb", 32,
875
    { 0|A(USES_RT)|A(USES_RS), { { { (1<<MACH_BASE), 0 } } } }
876
  },
877
/* sh $rt,$lo16($base) */
878
  {
879
    IQ2000_INSN_SH, "sh", "sh", 32,
880
    { 0|A(USES_RT)|A(USES_RS), { { { (1<<MACH_BASE), 0 } } } }
881
  },
882
/* sw $rt,$lo16($base) */
883
  {
884
    IQ2000_INSN_SW, "sw", "sw", 32,
885
    { 0|A(USES_RT)|A(USES_RS), { { { (1<<MACH_BASE), 0 } } } }
886
  },
887
/* break */
888
  {
889
    IQ2000_INSN_BREAK, "break", "break", 32,
890
    { 0, { { { (1<<MACH_BASE), 0 } } } }
891
  },
892
/* syscall */
893
  {
894
    IQ2000_INSN_SYSCALL, "syscall", "syscall", 32,
895
    { 0|A(YIELD_INSN), { { { (1<<MACH_BASE), 0 } } } }
896
  },
897
/* andoui $rt,$rs,$hi16 */
898
  {
899
    IQ2000_INSN_ANDOUI, "andoui", "andoui", 32,
900
    { 0|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ2000), 0 } } } }
901
  },
902
/* andoui ${rt-rs},$hi16 */
903
  {
904
    -1, "andoui2", "andoui", 32,
905
    { 0|A(USES_RT)|A(USES_RS)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_IQ2000), 0 } } } }
906
  },
907
/* orui ${rt-rs},$hi16 */
908
  {
909
    -1, "orui2", "orui", 32,
910
    { 0|A(USES_RT)|A(USES_RS)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_IQ2000), 0 } } } }
911
  },
912
/* orui $rt,$rs,$hi16 */
913
  {
914
    IQ2000_INSN_ORUI, "orui", "orui", 32,
915
    { 0|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ2000), 0 } } } }
916
  },
917
/* bgtz $rs,$offset */
918
  {
919
    IQ2000_INSN_BGTZ, "bgtz", "bgtz", 32,
920
    { 0|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ2000), 0 } } } }
921
  },
922
/* bgtzl $rs,$offset */
923
  {
924
    IQ2000_INSN_BGTZL, "bgtzl", "bgtzl", 32,
925
    { 0|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ2000), 0 } } } }
926
  },
927
/* blez $rs,$offset */
928
  {
929
    IQ2000_INSN_BLEZ, "blez", "blez", 32,
930
    { 0|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ2000), 0 } } } }
931
  },
932
/* blezl $rs,$offset */
933
  {
934
    IQ2000_INSN_BLEZL, "blezl", "blezl", 32,
935
    { 0|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ2000), 0 } } } }
936
  },
937
/* mrgb $rd,$rs,$rt,$mask */
938
  {
939
    IQ2000_INSN_MRGB, "mrgb", "mrgb", 32,
940
    { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } }
941
  },
942
/* mrgb ${rd-rs},$rt,$mask */
943
  {
944
    -1, "mrgb2", "mrgb", 32,
945
    { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_IQ2000), 0 } } } }
946
  },
947
/* bctxt $rs,$offset */
948
  {
949
    IQ2000_INSN_BCTXT, "bctxt", "bctxt", 32,
950
    { 0|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ2000), 0 } } } }
951
  },
952
/* bc0f $offset */
953
  {
954
    IQ2000_INSN_BC0F, "bc0f", "bc0f", 32,
955
    { 0|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ2000), 0 } } } }
956
  },
957
/* bc0fl $offset */
958
  {
959
    IQ2000_INSN_BC0FL, "bc0fl", "bc0fl", 32,
960
    { 0|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ2000), 0 } } } }
961
  },
962
/* bc3f $offset */
963
  {
964
    IQ2000_INSN_BC3F, "bc3f", "bc3f", 32,
965
    { 0|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ2000), 0 } } } }
966
  },
967
/* bc3fl $offset */
968
  {
969
    IQ2000_INSN_BC3FL, "bc3fl", "bc3fl", 32,
970
    { 0|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ2000), 0 } } } }
971
  },
972
/* bc0t $offset */
973
  {
974
    IQ2000_INSN_BC0T, "bc0t", "bc0t", 32,
975
    { 0|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ2000), 0 } } } }
976
  },
977
/* bc0tl $offset */
978
  {
979
    IQ2000_INSN_BC0TL, "bc0tl", "bc0tl", 32,
980
    { 0|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ2000), 0 } } } }
981
  },
982
/* bc3t $offset */
983
  {
984
    IQ2000_INSN_BC3T, "bc3t", "bc3t", 32,
985
    { 0|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ2000), 0 } } } }
986
  },
987
/* bc3tl $offset */
988
  {
989
    IQ2000_INSN_BC3TL, "bc3tl", "bc3tl", 32,
990
    { 0|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ2000), 0 } } } }
991
  },
992
/* cfc0 $rt,$rd */
993
  {
994
    IQ2000_INSN_CFC0, "cfc0", "cfc0", 32,
995
    { 0|A(USES_RT)|A(LOAD_DELAY), { { { (1<<MACH_IQ2000), 0 } } } }
996
  },
997
/* cfc1 $rt,$rd */
998
  {
999
    IQ2000_INSN_CFC1, "cfc1", "cfc1", 32,
1000
    { 0|A(USES_RT)|A(LOAD_DELAY), { { { (1<<MACH_IQ2000), 0 } } } }
1001
  },
1002
/* cfc2 $rt,$rd */
1003
  {
1004
    IQ2000_INSN_CFC2, "cfc2", "cfc2", 32,
1005
    { 0|A(YIELD_INSN)|A(USES_RT)|A(LOAD_DELAY), { { { (1<<MACH_IQ2000), 0 } } } }
1006
  },
1007
/* cfc3 $rt,$rd */
1008
  {
1009
    IQ2000_INSN_CFC3, "cfc3", "cfc3", 32,
1010
    { 0|A(YIELD_INSN)|A(USES_RT)|A(LOAD_DELAY), { { { (1<<MACH_IQ2000), 0 } } } }
1011
  },
1012
/* chkhdr $rd,$rt */
1013
  {
1014
    IQ2000_INSN_CHKHDR, "chkhdr", "chkhdr", 32,
1015
    { 0|A(YIELD_INSN)|A(USES_RD)|A(LOAD_DELAY), { { { (1<<MACH_IQ2000), 0 } } } }
1016
  },
1017
/* ctc0 $rt,$rd */
1018
  {
1019
    IQ2000_INSN_CTC0, "ctc0", "ctc0", 32,
1020
    { 0|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
1021
  },
1022
/* ctc1 $rt,$rd */
1023
  {
1024
    IQ2000_INSN_CTC1, "ctc1", "ctc1", 32,
1025
    { 0|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
1026
  },
1027
/* ctc2 $rt,$rd */
1028
  {
1029
    IQ2000_INSN_CTC2, "ctc2", "ctc2", 32,
1030
    { 0|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
1031
  },
1032
/* ctc3 $rt,$rd */
1033
  {
1034
    IQ2000_INSN_CTC3, "ctc3", "ctc3", 32,
1035
    { 0|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
1036
  },
1037
/* jcr $rs */
1038
  {
1039
    IQ2000_INSN_JCR, "jcr", "jcr", 32,
1040
    { 0|A(USES_RS)|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ2000), 0 } } } }
1041
  },
1042
/* luc32 $rt,$rd */
1043
  {
1044
    IQ2000_INSN_LUC32, "luc32", "luc32", 32,
1045
    { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } }
1046
  },
1047
/* luc32l $rt,$rd */
1048
  {
1049
    IQ2000_INSN_LUC32L, "luc32l", "luc32l", 32,
1050
    { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } }
1051
  },
1052
/* luc64 $rt,$rd */
1053
  {
1054
    IQ2000_INSN_LUC64, "luc64", "luc64", 32,
1055
    { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } }
1056
  },
1057
/* luc64l $rt,$rd */
1058
  {
1059
    IQ2000_INSN_LUC64L, "luc64l", "luc64l", 32,
1060
    { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } }
1061
  },
1062
/* luk $rt,$rd */
1063
  {
1064
    IQ2000_INSN_LUK, "luk", "luk", 32,
1065
    { 0|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } }
1066
  },
1067
/* lulck $rt */
1068
  {
1069
    IQ2000_INSN_LULCK, "lulck", "lulck", 32,
1070
    { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
1071
  },
1072
/* lum32 $rt,$rd */
1073
  {
1074
    IQ2000_INSN_LUM32, "lum32", "lum32", 32,
1075
    { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } }
1076
  },
1077
/* lum32l $rt,$rd */
1078
  {
1079
    IQ2000_INSN_LUM32L, "lum32l", "lum32l", 32,
1080
    { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } }
1081
  },
1082
/* lum64 $rt,$rd */
1083
  {
1084
    IQ2000_INSN_LUM64, "lum64", "lum64", 32,
1085
    { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } }
1086
  },
1087
/* lum64l $rt,$rd */
1088
  {
1089
    IQ2000_INSN_LUM64L, "lum64l", "lum64l", 32,
1090
    { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } }
1091
  },
1092
/* lur $rt,$rd */
1093
  {
1094
    IQ2000_INSN_LUR, "lur", "lur", 32,
1095
    { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } }
1096
  },
1097
/* lurl $rt,$rd */
1098
  {
1099
    IQ2000_INSN_LURL, "lurl", "lurl", 32,
1100
    { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } }
1101
  },
1102
/* luulck $rt */
1103
  {
1104
    IQ2000_INSN_LUULCK, "luulck", "luulck", 32,
1105
    { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
1106
  },
1107
/* mfc0 $rt,$rd */
1108
  {
1109
    IQ2000_INSN_MFC0, "mfc0", "mfc0", 32,
1110
    { 0|A(USES_RT)|A(LOAD_DELAY), { { { (1<<MACH_IQ2000), 0 } } } }
1111
  },
1112
/* mfc1 $rt,$rd */
1113
  {
1114
    IQ2000_INSN_MFC1, "mfc1", "mfc1", 32,
1115
    { 0|A(USES_RT)|A(LOAD_DELAY), { { { (1<<MACH_IQ2000), 0 } } } }
1116
  },
1117
/* mfc2 $rt,$rd */
1118
  {
1119
    IQ2000_INSN_MFC2, "mfc2", "mfc2", 32,
1120
    { 0|A(YIELD_INSN)|A(USES_RT)|A(LOAD_DELAY), { { { (1<<MACH_IQ2000), 0 } } } }
1121
  },
1122
/* mfc3 $rt,$rd */
1123
  {
1124
    IQ2000_INSN_MFC3, "mfc3", "mfc3", 32,
1125
    { 0|A(YIELD_INSN)|A(USES_RT)|A(LOAD_DELAY), { { { (1<<MACH_IQ2000), 0 } } } }
1126
  },
1127
/* mtc0 $rt,$rd */
1128
  {
1129
    IQ2000_INSN_MTC0, "mtc0", "mtc0", 32,
1130
    { 0|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
1131
  },
1132
/* mtc1 $rt,$rd */
1133
  {
1134
    IQ2000_INSN_MTC1, "mtc1", "mtc1", 32,
1135
    { 0|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
1136
  },
1137
/* mtc2 $rt,$rd */
1138
  {
1139
    IQ2000_INSN_MTC2, "mtc2", "mtc2", 32,
1140
    { 0|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
1141
  },
1142
/* mtc3 $rt,$rd */
1143
  {
1144
    IQ2000_INSN_MTC3, "mtc3", "mtc3", 32,
1145
    { 0|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
1146
  },
1147
/* pkrl $rd,$rt */
1148
  {
1149
    IQ2000_INSN_PKRL, "pkrl", "pkrl", 32,
1150
    { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } }
1151
  },
1152
/* pkrlr1 $rt,$_index,$count */
1153
  {
1154
    IQ2000_INSN_PKRLR1, "pkrlr1", "pkrlr1", 32,
1155
    { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
1156
  },
1157
/* pkrlr30 $rt,$_index,$count */
1158
  {
1159
    IQ2000_INSN_PKRLR30, "pkrlr30", "pkrlr30", 32,
1160
    { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
1161
  },
1162
/* rb $rd,$rt */
1163
  {
1164
    IQ2000_INSN_RB, "rb", "rb", 32,
1165
    { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } }
1166
  },
1167
/* rbr1 $rt,$_index,$count */
1168
  {
1169
    IQ2000_INSN_RBR1, "rbr1", "rbr1", 32,
1170
    { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
1171
  },
1172
/* rbr30 $rt,$_index,$count */
1173
  {
1174
    IQ2000_INSN_RBR30, "rbr30", "rbr30", 32,
1175
    { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
1176
  },
1177
/* rfe */
1178
  {
1179
    IQ2000_INSN_RFE, "rfe", "rfe", 32,
1180
    { 0, { { { (1<<MACH_IQ2000), 0 } } } }
1181
  },
1182
/* rx $rd,$rt */
1183
  {
1184
    IQ2000_INSN_RX, "rx", "rx", 32,
1185
    { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } }
1186
  },
1187
/* rxr1 $rt,$_index,$count */
1188
  {
1189
    IQ2000_INSN_RXR1, "rxr1", "rxr1", 32,
1190
    { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
1191
  },
1192
/* rxr30 $rt,$_index,$count */
1193
  {
1194
    IQ2000_INSN_RXR30, "rxr30", "rxr30", 32,
1195
    { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
1196
  },
1197
/* sleep */
1198
  {
1199
    IQ2000_INSN_SLEEP, "sleep", "sleep", 32,
1200
    { 0|A(YIELD_INSN), { { { (1<<MACH_IQ2000), 0 } } } }
1201
  },
1202
/* srrd $rt */
1203
  {
1204
    IQ2000_INSN_SRRD, "srrd", "srrd", 32,
1205
    { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
1206
  },
1207
/* srrdl $rt */
1208
  {
1209
    IQ2000_INSN_SRRDL, "srrdl", "srrdl", 32,
1210
    { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
1211
  },
1212
/* srulck $rt */
1213
  {
1214
    IQ2000_INSN_SRULCK, "srulck", "srulck", 32,
1215
    { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
1216
  },
1217
/* srwr $rt,$rd */
1218
  {
1219
    IQ2000_INSN_SRWR, "srwr", "srwr", 32,
1220
    { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } }
1221
  },
1222
/* srwru $rt,$rd */
1223
  {
1224
    IQ2000_INSN_SRWRU, "srwru", "srwru", 32,
1225
    { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } }
1226
  },
1227
/* trapqfl */
1228
  {
1229
    IQ2000_INSN_TRAPQFL, "trapqfl", "trapqfl", 32,
1230
    { 0|A(YIELD_INSN), { { { (1<<MACH_IQ2000), 0 } } } }
1231
  },
1232
/* trapqne */
1233
  {
1234
    IQ2000_INSN_TRAPQNE, "trapqne", "trapqne", 32,
1235
    { 0|A(YIELD_INSN), { { { (1<<MACH_IQ2000), 0 } } } }
1236
  },
1237
/* traprel $rt */
1238
  {
1239
    IQ2000_INSN_TRAPREL, "traprel", "traprel", 32,
1240
    { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
1241
  },
1242
/* wb $rd,$rt */
1243
  {
1244
    IQ2000_INSN_WB, "wb", "wb", 32,
1245
    { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } }
1246
  },
1247
/* wbu $rd,$rt */
1248
  {
1249
    IQ2000_INSN_WBU, "wbu", "wbu", 32,
1250
    { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } }
1251
  },
1252
/* wbr1 $rt,$_index,$count */
1253
  {
1254
    IQ2000_INSN_WBR1, "wbr1", "wbr1", 32,
1255
    { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
1256
  },
1257
/* wbr1u $rt,$_index,$count */
1258
  {
1259
    IQ2000_INSN_WBR1U, "wbr1u", "wbr1u", 32,
1260
    { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
1261
  },
1262
/* wbr30 $rt,$_index,$count */
1263
  {
1264
    IQ2000_INSN_WBR30, "wbr30", "wbr30", 32,
1265
    { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
1266
  },
1267
/* wbr30u $rt,$_index,$count */
1268
  {
1269
    IQ2000_INSN_WBR30U, "wbr30u", "wbr30u", 32,
1270
    { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
1271
  },
1272
/* wx $rd,$rt */
1273
  {
1274
    IQ2000_INSN_WX, "wx", "wx", 32,
1275
    { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } }
1276
  },
1277
/* wxu $rd,$rt */
1278
  {
1279
    IQ2000_INSN_WXU, "wxu", "wxu", 32,
1280
    { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } }
1281
  },
1282
/* wxr1 $rt,$_index,$count */
1283
  {
1284
    IQ2000_INSN_WXR1, "wxr1", "wxr1", 32,
1285
    { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
1286
  },
1287
/* wxr1u $rt,$_index,$count */
1288
  {
1289
    IQ2000_INSN_WXR1U, "wxr1u", "wxr1u", 32,
1290
    { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
1291
  },
1292
/* wxr30 $rt,$_index,$count */
1293
  {
1294
    IQ2000_INSN_WXR30, "wxr30", "wxr30", 32,
1295
    { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
1296
  },
1297
/* wxr30u $rt,$_index,$count */
1298
  {
1299
    IQ2000_INSN_WXR30U, "wxr30u", "wxr30u", 32,
1300
    { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
1301
  },
1302
/* ldw $rt,$lo16($base) */
1303
  {
1304
    IQ2000_INSN_LDW, "ldw", "ldw", 32,
1305
    { 0|A(USES_RT)|A(LOAD_DELAY)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ2000), 0 } } } }
1306
  },
1307
/* sdw $rt,$lo16($base) */
1308
  {
1309
    IQ2000_INSN_SDW, "sdw", "sdw", 32,
1310
    { 0|A(USES_RT)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ2000), 0 } } } }
1311
  },
1312
/* j $jmptarg */
1313
  {
1314
    IQ2000_INSN_J, "j", "j", 32,
1315
    { 0|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ2000), 0 } } } }
1316
  },
1317
/* jal $jmptarg */
1318
  {
1319
    IQ2000_INSN_JAL, "jal", "jal", 32,
1320
    { 0|A(USES_R31)|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ2000), 0 } } } }
1321
  },
1322
/* bmb $rs,$rt,$offset */
1323
  {
1324
    IQ2000_INSN_BMB, "bmb", "bmb", 32,
1325
    { 0|A(USES_RT)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ2000), 0 } } } }
1326
  },
1327
/* andoui $rt,$rs,$hi16 */
1328
  {
1329
    IQ2000_INSN_ANDOUI_Q10, "andoui-q10", "andoui", 32,
1330
    { 0|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
1331
  },
1332
/* andoui ${rt-rs},$hi16 */
1333
  {
1334
    -1, "andoui2-q10", "andoui", 32,
1335
    { 0|A(USES_RT)|A(USES_RS)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
1336
  },
1337
/* orui $rt,$rs,$hi16 */
1338
  {
1339
    IQ2000_INSN_ORUI_Q10, "orui-q10", "orui", 32,
1340
    { 0|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
1341
  },
1342
/* orui ${rt-rs},$hi16 */
1343
  {
1344
    -1, "orui2-q10", "orui", 32,
1345
    { 0|A(USES_RT)|A(USES_RS)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
1346
  },
1347
/* mrgb $rd,$rs,$rt,$maskq10 */
1348
  {
1349
    IQ2000_INSN_MRGBQ10, "mrgbq10", "mrgb", 32,
1350
    { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } }
1351
  },
1352
/* mrgb ${rd-rs},$rt,$maskq10 */
1353
  {
1354
    -1, "mrgbq102", "mrgb", 32,
1355
    { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
1356
  },
1357
/* j $jmptarg */
1358
  {
1359
    IQ2000_INSN_JQ10, "jq10", "j", 32,
1360
    { 0|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } }
1361
  },
1362
/* jal $rt,$jmptarg */
1363
  {
1364
    IQ2000_INSN_JALQ10, "jalq10", "jal", 32,
1365
    { 0|A(USES_RT)|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } }
1366
  },
1367
/* jal $jmptarg */
1368
  {
1369
    IQ2000_INSN_JALQ10_2, "jalq10-2", "jal", 32,
1370
    { 0|A(USES_RT)|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } }
1371
  },
1372
/* bbil $rs($bitnum),$offset */
1373
  {
1374
    IQ2000_INSN_BBIL, "bbil", "bbil", 32,
1375
    { 0|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } }
1376
  },
1377
/* bbinl $rs($bitnum),$offset */
1378
  {
1379
    IQ2000_INSN_BBINL, "bbinl", "bbinl", 32,
1380
    { 0|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } }
1381
  },
1382
/* bbvl $rs,$rt,$offset */
1383
  {
1384
    IQ2000_INSN_BBVL, "bbvl", "bbvl", 32,
1385
    { 0|A(USES_RT)|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } }
1386
  },
1387
/* bbvnl $rs,$rt,$offset */
1388
  {
1389
    IQ2000_INSN_BBVNL, "bbvnl", "bbvnl", 32,
1390
    { 0|A(USES_RT)|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } }
1391
  },
1392
/* bgtzal $rs,$offset */
1393
  {
1394
    IQ2000_INSN_BGTZAL, "bgtzal", "bgtzal", 32,
1395
    { 0|A(USES_R31)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } }
1396
  },
1397
/* bgtzall $rs,$offset */
1398
  {
1399
    IQ2000_INSN_BGTZALL, "bgtzall", "bgtzall", 32,
1400
    { 0|A(USES_R31)|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } }
1401
  },
1402
/* blezal $rs,$offset */
1403
  {
1404
    IQ2000_INSN_BLEZAL, "blezal", "blezal", 32,
1405
    { 0|A(USES_R31)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } }
1406
  },
1407
/* blezall $rs,$offset */
1408
  {
1409
    IQ2000_INSN_BLEZALL, "blezall", "blezall", 32,
1410
    { 0|A(USES_R31)|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } }
1411
  },
1412
/* bgtz $rs,$offset */
1413
  {
1414
    IQ2000_INSN_BGTZ_Q10, "bgtz-q10", "bgtz", 32,
1415
    { 0|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } }
1416
  },
1417
/* bgtzl $rs,$offset */
1418
  {
1419
    IQ2000_INSN_BGTZL_Q10, "bgtzl-q10", "bgtzl", 32,
1420
    { 0|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } }
1421
  },
1422
/* blez $rs,$offset */
1423
  {
1424
    IQ2000_INSN_BLEZ_Q10, "blez-q10", "blez", 32,
1425
    { 0|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } }
1426
  },
1427
/* blezl $rs,$offset */
1428
  {
1429
    IQ2000_INSN_BLEZL_Q10, "blezl-q10", "blezl", 32,
1430
    { 0|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } }
1431
  },
1432
/* bmb $rs,$rt,$offset */
1433
  {
1434
    IQ2000_INSN_BMB_Q10, "bmb-q10", "bmb", 32,
1435
    { 0|A(USES_RT)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } }
1436
  },
1437
/* bmbl $rs,$rt,$offset */
1438
  {
1439
    IQ2000_INSN_BMBL, "bmbl", "bmbl", 32,
1440
    { 0|A(USES_RT)|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } }
1441
  },
1442
/* bri $rs,$offset */
1443
  {
1444
    IQ2000_INSN_BRI, "bri", "bri", 32,
1445
    { 0|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } }
1446
  },
1447
/* brv $rs,$offset */
1448
  {
1449
    IQ2000_INSN_BRV, "brv", "brv", 32,
1450
    { 0|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } }
1451
  },
1452
/* bctx $rs,$offset */
1453
  {
1454
    IQ2000_INSN_BCTX, "bctx", "bctx", 32,
1455
    { 0|A(USES_RS)|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } }
1456
  },
1457
/* yield */
1458
  {
1459
    IQ2000_INSN_YIELD, "yield", "yield", 32,
1460
    { 0, { { { (1<<MACH_IQ10), 0 } } } }
1461
  },
1462
/* crc32 $rd,$rs,$rt */
1463
  {
1464
    IQ2000_INSN_CRC32, "crc32", "crc32", 32,
1465
    { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } }
1466
  },
1467
/* crc32b $rd,$rs,$rt */
1468
  {
1469
    IQ2000_INSN_CRC32B, "crc32b", "crc32b", 32,
1470
    { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } }
1471
  },
1472
/* cnt1s $rd,$rs */
1473
  {
1474
    IQ2000_INSN_CNT1S, "cnt1s", "cnt1s", 32,
1475
    { 0|A(USES_RS)|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } }
1476
  },
1477
/* avail $rd */
1478
  {
1479
    IQ2000_INSN_AVAIL, "avail", "avail", 32,
1480
    { 0|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } }
1481
  },
1482
/* free $rd,$rs */
1483
  {
1484
    IQ2000_INSN_FREE, "free", "free", 32,
1485
    { 0|A(USES_RD)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
1486
  },
1487
/* tstod $rd,$rs */
1488
  {
1489
    IQ2000_INSN_TSTOD, "tstod", "tstod", 32,
1490
    { 0|A(USES_RD)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
1491
  },
1492
/* cmphdr $rd */
1493
  {
1494
    IQ2000_INSN_CMPHDR, "cmphdr", "cmphdr", 32,
1495
    { 0|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } }
1496
  },
1497
/* mcid $rd,$rt */
1498
  {
1499
    IQ2000_INSN_MCID, "mcid", "mcid", 32,
1500
    { 0|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } }
1501
  },
1502
/* dba $rd */
1503
  {
1504
    IQ2000_INSN_DBA, "dba", "dba", 32,
1505
    { 0|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } }
1506
  },
1507
/* dbd $rd,$rs,$rt */
1508
  {
1509
    IQ2000_INSN_DBD, "dbd", "dbd", 32,
1510
    { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
1511
  },
1512
/* dpwt $rd,$rs */
1513
  {
1514
    IQ2000_INSN_DPWT, "dpwt", "dpwt", 32,
1515
    { 0|A(USES_RD)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
1516
  },
1517
/* chkhdr $rd,$rs */
1518
  {
1519
    IQ2000_INSN_CHKHDRQ10, "chkhdrq10", "chkhdr", 32,
1520
    { 0|A(USES_RD)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
1521
  },
1522
/* rba $rd,$rs,$rt */
1523
  {
1524
    IQ2000_INSN_RBA, "rba", "rba", 32,
1525
    { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
1526
  },
1527
/* rbal $rd,$rs,$rt */
1528
  {
1529
    IQ2000_INSN_RBAL, "rbal", "rbal", 32,
1530
    { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
1531
  },
1532
/* rbar $rd,$rs,$rt */
1533
  {
1534
    IQ2000_INSN_RBAR, "rbar", "rbar", 32,
1535
    { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
1536
  },
1537
/* wba $rd,$rs,$rt */
1538
  {
1539
    IQ2000_INSN_WBA, "wba", "wba", 32,
1540
    { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
1541
  },
1542
/* wbau $rd,$rs,$rt */
1543
  {
1544
    IQ2000_INSN_WBAU, "wbau", "wbau", 32,
1545
    { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
1546
  },
1547
/* wbac $rd,$rs,$rt */
1548
  {
1549
    IQ2000_INSN_WBAC, "wbac", "wbac", 32,
1550
    { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
1551
  },
1552
/* rbi $rd,$rs,$rt,$bytecount */
1553
  {
1554
    IQ2000_INSN_RBI, "rbi", "rbi", 32,
1555
    { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } }
1556
  },
1557
/* rbil $rd,$rs,$rt,$bytecount */
1558
  {
1559
    IQ2000_INSN_RBIL, "rbil", "rbil", 32,
1560
    { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } }
1561
  },
1562
/* rbir $rd,$rs,$rt,$bytecount */
1563
  {
1564
    IQ2000_INSN_RBIR, "rbir", "rbir", 32,
1565
    { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } }
1566
  },
1567
/* wbi $rd,$rs,$rt,$bytecount */
1568
  {
1569
    IQ2000_INSN_WBI, "wbi", "wbi", 32,
1570
    { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } }
1571
  },
1572
/* wbic $rd,$rs,$rt,$bytecount */
1573
  {
1574
    IQ2000_INSN_WBIC, "wbic", "wbic", 32,
1575
    { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } }
1576
  },
1577
/* wbiu $rd,$rs,$rt,$bytecount */
1578
  {
1579
    IQ2000_INSN_WBIU, "wbiu", "wbiu", 32,
1580
    { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } }
1581
  },
1582
/* pkrli $rd,$rs,$rt,$bytecount */
1583
  {
1584
    IQ2000_INSN_PKRLI, "pkrli", "pkrli", 32,
1585
    { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } }
1586
  },
1587
/* pkrlih $rd,$rs,$rt,$bytecount */
1588
  {
1589
    IQ2000_INSN_PKRLIH, "pkrlih", "pkrlih", 32,
1590
    { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } }
1591
  },
1592
/* pkrliu $rd,$rs,$rt,$bytecount */
1593
  {
1594
    IQ2000_INSN_PKRLIU, "pkrliu", "pkrliu", 32,
1595
    { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } }
1596
  },
1597
/* pkrlic $rd,$rs,$rt,$bytecount */
1598
  {
1599
    IQ2000_INSN_PKRLIC, "pkrlic", "pkrlic", 32,
1600
    { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } }
1601
  },
1602
/* pkrla $rd,$rs,$rt */
1603
  {
1604
    IQ2000_INSN_PKRLA, "pkrla", "pkrla", 32,
1605
    { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
1606
  },
1607
/* pkrlau $rd,$rs,$rt */
1608
  {
1609
    IQ2000_INSN_PKRLAU, "pkrlau", "pkrlau", 32,
1610
    { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
1611
  },
1612
/* pkrlah $rd,$rs,$rt */
1613
  {
1614
    IQ2000_INSN_PKRLAH, "pkrlah", "pkrlah", 32,
1615
    { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
1616
  },
1617
/* pkrlac $rd,$rs,$rt */
1618
  {
1619
    IQ2000_INSN_PKRLAC, "pkrlac", "pkrlac", 32,
1620
    { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
1621
  },
1622
/* lock $rd,$rt */
1623
  {
1624
    IQ2000_INSN_LOCK, "lock", "lock", 32,
1625
    { 0|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } }
1626
  },
1627
/* unlk $rd,$rt */
1628
  {
1629
    IQ2000_INSN_UNLK, "unlk", "unlk", 32,
1630
    { 0|A(USES_RD)|A(USES_RT), { { { (1<<MACH_IQ10), 0 } } } }
1631
  },
1632
/* swrd $rd,$rt */
1633
  {
1634
    IQ2000_INSN_SWRD, "swrd", "swrd", 32,
1635
    { 0|A(USES_RD)|A(USES_RT), { { { (1<<MACH_IQ10), 0 } } } }
1636
  },
1637
/* swrdl $rd,$rt */
1638
  {
1639
    IQ2000_INSN_SWRDL, "swrdl", "swrdl", 32,
1640
    { 0|A(USES_RD)|A(USES_RT), { { { (1<<MACH_IQ10), 0 } } } }
1641
  },
1642
/* swwr $rd,$rs,$rt */
1643
  {
1644
    IQ2000_INSN_SWWR, "swwr", "swwr", 32,
1645
    { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
1646
  },
1647
/* swwru $rd,$rs,$rt */
1648
  {
1649
    IQ2000_INSN_SWWRU, "swwru", "swwru", 32,
1650
    { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
1651
  },
1652
/* dwrd $rd,$rt */
1653
  {
1654
    IQ2000_INSN_DWRD, "dwrd", "dwrd", 32,
1655
    { 0|A(USES_RD)|A(USES_RT)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ10), 0 } } } }
1656
  },
1657
/* dwrdl $rd,$rt */
1658
  {
1659
    IQ2000_INSN_DWRDL, "dwrdl", "dwrdl", 32,
1660
    { 0|A(USES_RD)|A(USES_RT)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ10), 0 } } } }
1661
  },
1662
/* cam36 $rd,$rt,${cam-z},${cam-y} */
1663
  {
1664
    IQ2000_INSN_CAM36, "cam36", "cam36", 32,
1665
    { 0|A(USES_RD)|A(USES_RT), { { { (1<<MACH_IQ10), 0 } } } }
1666
  },
1667
/* cam72 $rd,$rt,${cam-y},${cam-z} */
1668
  {
1669
    IQ2000_INSN_CAM72, "cam72", "cam72", 32,
1670
    { 0|A(USES_RD)|A(USES_RT), { { { (1<<MACH_IQ10), 0 } } } }
1671
  },
1672
/* cam144 $rd,$rt,${cam-y},${cam-z} */
1673
  {
1674
    IQ2000_INSN_CAM144, "cam144", "cam144", 32,
1675
    { 0|A(USES_RD)|A(USES_RT), { { { (1<<MACH_IQ10), 0 } } } }
1676
  },
1677
/* cam288 $rd,$rt,${cam-y},${cam-z} */
1678
  {
1679
    IQ2000_INSN_CAM288, "cam288", "cam288", 32,
1680
    { 0|A(USES_RD)|A(USES_RT), { { { (1<<MACH_IQ10), 0 } } } }
1681
  },
1682
/* cm32and $rd,$rs,$rt */
1683
  {
1684
    IQ2000_INSN_CM32AND, "cm32and", "cm32and", 32,
1685
    { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
1686
  },
1687
/* cm32andn $rd,$rs,$rt */
1688
  {
1689
    IQ2000_INSN_CM32ANDN, "cm32andn", "cm32andn", 32,
1690
    { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
1691
  },
1692
/* cm32or $rd,$rs,$rt */
1693
  {
1694
    IQ2000_INSN_CM32OR, "cm32or", "cm32or", 32,
1695
    { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
1696
  },
1697
/* cm32ra $rd,$rs,$rt */
1698
  {
1699
    IQ2000_INSN_CM32RA, "cm32ra", "cm32ra", 32,
1700
    { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
1701
  },
1702
/* cm32rd $rd,$rt */
1703
  {
1704
    IQ2000_INSN_CM32RD, "cm32rd", "cm32rd", 32,
1705
    { 0|A(USES_RD)|A(USES_RT), { { { (1<<MACH_IQ10), 0 } } } }
1706
  },
1707
/* cm32ri $rd,$rt */
1708
  {
1709
    IQ2000_INSN_CM32RI, "cm32ri", "cm32ri", 32,
1710
    { 0|A(USES_RD)|A(USES_RT), { { { (1<<MACH_IQ10), 0 } } } }
1711
  },
1712
/* cm32rs $rd,$rs,$rt */
1713
  {
1714
    IQ2000_INSN_CM32RS, "cm32rs", "cm32rs", 32,
1715
    { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
1716
  },
1717
/* cm32sa $rd,$rs,$rt */
1718
  {
1719
    IQ2000_INSN_CM32SA, "cm32sa", "cm32sa", 32,
1720
    { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
1721
  },
1722
/* cm32sd $rd,$rt */
1723
  {
1724
    IQ2000_INSN_CM32SD, "cm32sd", "cm32sd", 32,
1725
    { 0|A(USES_RD)|A(USES_RT), { { { (1<<MACH_IQ10), 0 } } } }
1726
  },
1727
/* cm32si $rd,$rt */
1728
  {
1729
    IQ2000_INSN_CM32SI, "cm32si", "cm32si", 32,
1730
    { 0|A(USES_RD)|A(USES_RT), { { { (1<<MACH_IQ10), 0 } } } }
1731
  },
1732
/* cm32ss $rd,$rs,$rt */
1733
  {
1734
    IQ2000_INSN_CM32SS, "cm32ss", "cm32ss", 32,
1735
    { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
1736
  },
1737
/* cm32xor $rd,$rs,$rt */
1738
  {
1739
    IQ2000_INSN_CM32XOR, "cm32xor", "cm32xor", 32,
1740
    { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
1741
  },
1742
/* cm64clr $rd,$rt */
1743
  {
1744
    IQ2000_INSN_CM64CLR, "cm64clr", "cm64clr", 32,
1745
    { 0|A(USES_RD)|A(USES_RT)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ10), 0 } } } }
1746
  },
1747
/* cm64ra $rd,$rs,$rt */
1748
  {
1749
    IQ2000_INSN_CM64RA, "cm64ra", "cm64ra", 32,
1750
    { 0|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ10), 0 } } } }
1751
  },
1752
/* cm64rd $rd,$rt */
1753
  {
1754
    IQ2000_INSN_CM64RD, "cm64rd", "cm64rd", 32,
1755
    { 0|A(USES_RD)|A(USES_RT)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ10), 0 } } } }
1756
  },
1757
/* cm64ri $rd,$rt */
1758
  {
1759
    IQ2000_INSN_CM64RI, "cm64ri", "cm64ri", 32,
1760
    { 0|A(USES_RD)|A(USES_RT)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ10), 0 } } } }
1761
  },
1762
/* cm64ria2 $rd,$rs,$rt */
1763
  {
1764
    IQ2000_INSN_CM64RIA2, "cm64ria2", "cm64ria2", 32,
1765
    { 0|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ10), 0 } } } }
1766
  },
1767
/* cm64rs $rd,$rs,$rt */
1768
  {
1769
    IQ2000_INSN_CM64RS, "cm64rs", "cm64rs", 32,
1770
    { 0|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ10), 0 } } } }
1771
  },
1772
/* cm64sa $rd,$rs,$rt */
1773
  {
1774
    IQ2000_INSN_CM64SA, "cm64sa", "cm64sa", 32,
1775
    { 0|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ10), 0 } } } }
1776
  },
1777
/* cm64sd $rd,$rt */
1778
  {
1779
    IQ2000_INSN_CM64SD, "cm64sd", "cm64sd", 32,
1780
    { 0|A(USES_RD)|A(USES_RT)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ10), 0 } } } }
1781
  },
1782
/* cm64si $rd,$rt */
1783
  {
1784
    IQ2000_INSN_CM64SI, "cm64si", "cm64si", 32,
1785
    { 0|A(USES_RD)|A(USES_RT)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ10), 0 } } } }
1786
  },
1787
/* cm64sia2 $rd,$rs,$rt */
1788
  {
1789
    IQ2000_INSN_CM64SIA2, "cm64sia2", "cm64sia2", 32,
1790
    { 0|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ10), 0 } } } }
1791
  },
1792
/* cm64ss $rd,$rs,$rt */
1793
  {
1794
    IQ2000_INSN_CM64SS, "cm64ss", "cm64ss", 32,
1795
    { 0|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ10), 0 } } } }
1796
  },
1797
/* cm128ria2 $rd,$rs,$rt */
1798
  {
1799
    IQ2000_INSN_CM128RIA2, "cm128ria2", "cm128ria2", 32,
1800
    { 0|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ10), 0 } } } }
1801
  },
1802
/* cm128ria3 $rd,$rs,$rt,${cm-3z} */
1803
  {
1804
    IQ2000_INSN_CM128RIA3, "cm128ria3", "cm128ria3", 32,
1805
    { 0|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ10), 0 } } } }
1806
  },
1807
/* cm128ria4 $rd,$rs,$rt,${cm-4z} */
1808
  {
1809
    IQ2000_INSN_CM128RIA4, "cm128ria4", "cm128ria4", 32,
1810
    { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
1811
  },
1812
/* cm128sia2 $rd,$rs,$rt */
1813
  {
1814
    IQ2000_INSN_CM128SIA2, "cm128sia2", "cm128sia2", 32,
1815
    { 0|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ10), 0 } } } }
1816
  },
1817
/* cm128sia3 $rd,$rs,$rt,${cm-3z} */
1818
  {
1819
    IQ2000_INSN_CM128SIA3, "cm128sia3", "cm128sia3", 32,
1820
    { 0|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ10), 0 } } } }
1821
  },
1822
/* cm128sia4 $rd,$rs,$rt,${cm-4z} */
1823
  {
1824
    IQ2000_INSN_CM128SIA4, "cm128sia4", "cm128sia4", 32,
1825
    { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
1826
  },
1827
/* cm128vsa $rd,$rs,$rt */
1828
  {
1829
    IQ2000_INSN_CM128VSA, "cm128vsa", "cm128vsa", 32,
1830
    { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
1831
  },
1832
/* cfc $rd,$rt */
1833
  {
1834
    IQ2000_INSN_CFC, "cfc", "cfc", 32,
1835
    { 0|A(YIELD_INSN)|A(USES_RD)|A(LOAD_DELAY), { { { (1<<MACH_IQ10), 0 } } } }
1836
  },
1837
/* ctc $rs,$rt */
1838
  {
1839
    IQ2000_INSN_CTC, "ctc", "ctc", 32,
1840
    { 0|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
1841
  },
1842
};
1843
1844
#undef OP
1845
#undef A
1846
1847
/* Initialize anything needed to be done once, before any cpu_open call.  */
1848
1849
static void
1850
init_tables (void)
1851
1
{
1852
1
}
1853
1854
#ifndef opcodes_error_handler
1855
#define opcodes_error_handler(...) \
1856
  fprintf (stderr, __VA_ARGS__); fputc ('\n', stderr)
1857
#endif
1858
1859
static const CGEN_MACH * lookup_mach_via_bfd_name (const CGEN_MACH *, const char *);
1860
static void build_hw_table      (CGEN_CPU_TABLE *);
1861
static void build_ifield_table  (CGEN_CPU_TABLE *);
1862
static void build_operand_table (CGEN_CPU_TABLE *);
1863
static void build_insn_table    (CGEN_CPU_TABLE *);
1864
static void iq2000_cgen_rebuild_tables (CGEN_CPU_TABLE *);
1865
1866
/* Subroutine of iq2000_cgen_cpu_open to look up a mach via its bfd name.  */
1867
1868
static const CGEN_MACH *
1869
lookup_mach_via_bfd_name (const CGEN_MACH *table, const char *name)
1870
3
{
1871
4
  while (table->name)
1872
4
    {
1873
4
      if (strcmp (name, table->bfd_name) == 0)
1874
3
  return table;
1875
1
      ++table;
1876
1
    }
1877
0
  return NULL;
1878
3
}
1879
1880
/* Subroutine of iq2000_cgen_cpu_open to build the hardware table.  */
1881
1882
static void
1883
build_hw_table (CGEN_CPU_TABLE *cd)
1884
3
{
1885
3
  int i;
1886
3
  int machs = cd->machs;
1887
3
  const CGEN_HW_ENTRY *init = & iq2000_cgen_hw_table[0];
1888
  /* MAX_HW is only an upper bound on the number of selected entries.
1889
     However each entry is indexed by it's enum so there can be holes in
1890
     the table.  */
1891
3
  const CGEN_HW_ENTRY **selected =
1892
3
    (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *));
1893
1894
3
  cd->hw_table.init_entries = init;
1895
3
  cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY);
1896
3
  memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *));
1897
  /* ??? For now we just use machs to determine which ones we want.  */
1898
24
  for (i = 0; init[i].name != NULL; ++i)
1899
21
    if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH)
1900
21
  & machs)
1901
21
      selected[init[i].type] = &init[i];
1902
3
  cd->hw_table.entries = selected;
1903
3
  cd->hw_table.num_entries = MAX_HW;
1904
3
}
1905
1906
/* Subroutine of iq2000_cgen_cpu_open to build the hardware table.  */
1907
1908
static void
1909
build_ifield_table (CGEN_CPU_TABLE *cd)
1910
3
{
1911
3
  cd->ifld_table = & iq2000_cgen_ifld_table[0];
1912
3
}
1913
1914
/* Subroutine of iq2000_cgen_cpu_open to build the hardware table.  */
1915
1916
static void
1917
build_operand_table (CGEN_CPU_TABLE *cd)
1918
3
{
1919
3
  int i;
1920
3
  int machs = cd->machs;
1921
3
  const CGEN_OPERAND *init = & iq2000_cgen_operand_table[0];
1922
  /* MAX_OPERANDS is only an upper bound on the number of selected entries.
1923
     However each entry is indexed by it's enum so there can be holes in
1924
     the table.  */
1925
3
  const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected));
1926
1927
3
  cd->operand_table.init_entries = init;
1928
3
  cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
1929
3
  memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *));
1930
  /* ??? For now we just use mach to determine which ones we want.  */
1931
99
  for (i = 0; init[i].name != NULL; ++i)
1932
96
    if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH)
1933
96
  & machs)
1934
96
      selected[init[i].type] = &init[i];
1935
3
  cd->operand_table.entries = selected;
1936
3
  cd->operand_table.num_entries = MAX_OPERANDS;
1937
3
}
1938
1939
/* Subroutine of iq2000_cgen_cpu_open to build the hardware table.
1940
   ??? This could leave out insns not supported by the specified mach/isa,
1941
   but that would cause errors like "foo only supported by bar" to become
1942
   "unknown insn", so for now we include all insns and require the app to
1943
   do the checking later.
1944
   ??? On the other hand, parsing of such insns may require their hardware or
1945
   operand elements to be in the table [which they mightn't be].  */
1946
1947
static void
1948
build_insn_table (CGEN_CPU_TABLE *cd)
1949
3
{
1950
3
  int i;
1951
3
  const CGEN_IBASE *ib = & iq2000_cgen_insn_table[0];
1952
3
  CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
1953
1954
3
  memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
1955
831
  for (i = 0; i < MAX_INSNS; ++i)
1956
828
    insns[i].base = &ib[i];
1957
3
  cd->insn_table.init_entries = insns;
1958
3
  cd->insn_table.entry_size = sizeof (CGEN_IBASE);
1959
3
  cd->insn_table.num_init_entries = MAX_INSNS;
1960
3
}
1961
1962
/* Subroutine of iq2000_cgen_cpu_open to rebuild the tables.  */
1963
1964
static void
1965
iq2000_cgen_rebuild_tables (CGEN_CPU_TABLE *cd)
1966
3
{
1967
3
  int i;
1968
3
  CGEN_BITSET *isas = cd->isas;
1969
3
  unsigned int machs = cd->machs;
1970
1971
3
  cd->int_insn_p = CGEN_INT_INSN_P;
1972
1973
  /* Data derived from the isa spec.  */
1974
12
#define UNSET (CGEN_SIZE_UNKNOWN + 1)
1975
3
  cd->default_insn_bitsize = UNSET;
1976
3
  cd->base_insn_bitsize = UNSET;
1977
3
  cd->min_insn_bitsize = 65535; /* Some ridiculously big number.  */
1978
3
  cd->max_insn_bitsize = 0;
1979
6
  for (i = 0; i < MAX_ISAS; ++i)
1980
3
    if (cgen_bitset_contains (isas, i))
1981
3
      {
1982
3
  const CGEN_ISA *isa = & iq2000_cgen_isa_table[i];
1983
1984
  /* Default insn sizes of all selected isas must be
1985
     equal or we set the result to 0, meaning "unknown".  */
1986
3
  if (cd->default_insn_bitsize == UNSET)
1987
3
    cd->default_insn_bitsize = isa->default_insn_bitsize;
1988
0
  else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
1989
0
    ; /* This is ok.  */
1990
0
  else
1991
0
    cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
1992
1993
  /* Base insn sizes of all selected isas must be equal
1994
     or we set the result to 0, meaning "unknown".  */
1995
3
  if (cd->base_insn_bitsize == UNSET)
1996
3
    cd->base_insn_bitsize = isa->base_insn_bitsize;
1997
0
  else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
1998
0
    ; /* This is ok.  */
1999
0
  else
2000
0
    cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
2001
2002
  /* Set min,max insn sizes.  */
2003
3
  if (isa->min_insn_bitsize < cd->min_insn_bitsize)
2004
3
    cd->min_insn_bitsize = isa->min_insn_bitsize;
2005
3
  if (isa->max_insn_bitsize > cd->max_insn_bitsize)
2006
3
    cd->max_insn_bitsize = isa->max_insn_bitsize;
2007
3
      }
2008
2009
  /* Data derived from the mach spec.  */
2010
12
  for (i = 0; i < MAX_MACHS; ++i)
2011
9
    if (((1 << i) & machs) != 0)
2012
6
      {
2013
6
  const CGEN_MACH *mach = & iq2000_cgen_mach_table[i];
2014
2015
6
  if (mach->insn_chunk_bitsize != 0)
2016
0
  {
2017
0
    if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize)
2018
0
      {
2019
0
        opcodes_error_handler
2020
0
    (/* xgettext:c-format */
2021
0
     _("internal error: iq2000_cgen_rebuild_tables: "
2022
0
       "conflicting insn-chunk-bitsize values: `%d' vs. `%d'"),
2023
0
     cd->insn_chunk_bitsize, mach->insn_chunk_bitsize);
2024
0
        abort ();
2025
0
      }
2026
2027
0
    cd->insn_chunk_bitsize = mach->insn_chunk_bitsize;
2028
0
  }
2029
6
      }
2030
2031
  /* Determine which hw elements are used by MACH.  */
2032
3
  build_hw_table (cd);
2033
2034
  /* Build the ifield table.  */
2035
3
  build_ifield_table (cd);
2036
2037
  /* Determine which operands are used by MACH/ISA.  */
2038
3
  build_operand_table (cd);
2039
2040
  /* Build the instruction table.  */
2041
3
  build_insn_table (cd);
2042
3
}
2043
2044
/* Initialize a cpu table and return a descriptor.
2045
   It's much like opening a file, and must be the first function called.
2046
   The arguments are a set of (type/value) pairs, terminated with
2047
   CGEN_CPU_OPEN_END.
2048
2049
   Currently supported values:
2050
   CGEN_CPU_OPEN_ISAS:    bitmap of values in enum isa_attr
2051
   CGEN_CPU_OPEN_MACHS:   bitmap of values in enum mach_attr
2052
   CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name
2053
   CGEN_CPU_OPEN_ENDIAN:  specify endian choice
2054
   CGEN_CPU_OPEN_INSN_ENDIAN: specify instruction endian choice
2055
   CGEN_CPU_OPEN_END:     terminates arguments
2056
2057
   ??? Simultaneous multiple isas might not make sense, but it's not (yet)
2058
   precluded.  */
2059
2060
CGEN_CPU_DESC
2061
iq2000_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
2062
3
{
2063
3
  CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
2064
3
  static int init_p;
2065
3
  CGEN_BITSET *isas = 0;  /* 0 = "unspecified" */
2066
3
  unsigned int machs = 0; /* 0 = "unspecified" */
2067
3
  enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
2068
3
  enum cgen_endian insn_endian = CGEN_ENDIAN_UNKNOWN;
2069
3
  va_list ap;
2070
2071
3
  if (! init_p)
2072
1
    {
2073
1
      init_tables ();
2074
1
      init_p = 1;
2075
1
    }
2076
2077
3
  memset (cd, 0, sizeof (*cd));
2078
2079
3
  va_start (ap, arg_type);
2080
15
  while (arg_type != CGEN_CPU_OPEN_END)
2081
12
    {
2082
12
      switch (arg_type)
2083
12
  {
2084
3
  case CGEN_CPU_OPEN_ISAS :
2085
3
    isas = va_arg (ap, CGEN_BITSET *);
2086
3
    break;
2087
0
  case CGEN_CPU_OPEN_MACHS :
2088
0
    machs = va_arg (ap, unsigned int);
2089
0
    break;
2090
3
  case CGEN_CPU_OPEN_BFDMACH :
2091
3
    {
2092
3
      const char *name = va_arg (ap, const char *);
2093
3
      const CGEN_MACH *mach =
2094
3
        lookup_mach_via_bfd_name (iq2000_cgen_mach_table, name);
2095
2096
3
      if (mach != NULL)
2097
3
        machs |= 1 << mach->num;
2098
3
      break;
2099
0
    }
2100
3
  case CGEN_CPU_OPEN_ENDIAN :
2101
3
    endian = va_arg (ap, enum cgen_endian);
2102
3
    break;
2103
3
  case CGEN_CPU_OPEN_INSN_ENDIAN :
2104
3
    insn_endian = va_arg (ap, enum cgen_endian);
2105
3
    break;
2106
0
  default :
2107
0
    opcodes_error_handler
2108
0
      (/* xgettext:c-format */
2109
0
       _("internal error: iq2000_cgen_cpu_open: "
2110
0
         "unsupported argument `%d'"),
2111
0
       arg_type);
2112
0
    abort (); /* ??? return NULL? */
2113
12
  }
2114
12
      arg_type = va_arg (ap, enum cgen_cpu_open_arg);
2115
12
    }
2116
3
  va_end (ap);
2117
2118
  /* Mach unspecified means "all".  */
2119
3
  if (machs == 0)
2120
0
    machs = (1 << MAX_MACHS) - 1;
2121
  /* Base mach is always selected.  */
2122
3
  machs |= 1;
2123
3
  if (endian == CGEN_ENDIAN_UNKNOWN)
2124
0
    {
2125
      /* ??? If target has only one, could have a default.  */
2126
0
      opcodes_error_handler
2127
0
  (/* xgettext:c-format */
2128
0
   _("internal error: iq2000_cgen_cpu_open: no endianness specified"));
2129
0
      abort ();
2130
0
    }
2131
2132
3
  cd->isas = cgen_bitset_copy (isas);
2133
3
  cd->machs = machs;
2134
3
  cd->endian = endian;
2135
3
  cd->insn_endian
2136
3
    = (insn_endian == CGEN_ENDIAN_UNKNOWN ? endian : insn_endian);
2137
2138
  /* Table (re)builder.  */
2139
3
  cd->rebuild_tables = iq2000_cgen_rebuild_tables;
2140
3
  iq2000_cgen_rebuild_tables (cd);
2141
2142
  /* Default to not allowing signed overflow.  */
2143
3
  cd->signed_overflow_ok_p = 0;
2144
2145
3
  return (CGEN_CPU_DESC) cd;
2146
3
}
2147
2148
/* Cover fn to iq2000_cgen_cpu_open to handle the simple case of 1 isa, 1 mach.
2149
   MACH_NAME is the bfd name of the mach.  */
2150
2151
CGEN_CPU_DESC
2152
iq2000_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian)
2153
0
{
2154
0
  return iq2000_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
2155
0
             CGEN_CPU_OPEN_ENDIAN, endian,
2156
0
             CGEN_CPU_OPEN_END);
2157
0
}
2158
2159
/* Close a cpu table.
2160
   ??? This can live in a machine independent file, but there's currently
2161
   no place to put this file (there's no libcgen).  libopcodes is the wrong
2162
   place as some simulator ports use this but they don't use libopcodes.  */
2163
2164
void
2165
iq2000_cgen_cpu_close (CGEN_CPU_DESC cd)
2166
0
{
2167
0
  unsigned int i;
2168
0
  const CGEN_INSN *insns;
2169
2170
0
  if (cd->macro_insn_table.init_entries)
2171
0
    {
2172
0
      insns = cd->macro_insn_table.init_entries;
2173
0
      for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
2174
0
  if (CGEN_INSN_RX ((insns)))
2175
0
    regfree (CGEN_INSN_RX (insns));
2176
0
    }
2177
2178
0
  if (cd->insn_table.init_entries)
2179
0
    {
2180
0
      insns = cd->insn_table.init_entries;
2181
0
      for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
2182
0
  if (CGEN_INSN_RX (insns))
2183
0
    regfree (CGEN_INSN_RX (insns));
2184
0
    }
2185
2186
0
  free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
2187
0
  free ((CGEN_INSN *) cd->insn_table.init_entries);
2188
0
  free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
2189
0
  free ((CGEN_HW_ENTRY *) cd->operand_table.entries);
2190
0
  free (cd);
2191
0
}
2192