Coverage Report

Created: 2024-05-21 06:29

/src/binutils-gdb/gas/config/tc-i386.c
Line
Count
Source (jump to first uncovered line)
1
/* tc-i386.c -- Assemble code for the Intel 80386
2
   Copyright (C) 1989-2024 Free Software Foundation, Inc.
3
4
   This file is part of GAS, the GNU Assembler.
5
6
   GAS is free software; you can redistribute it and/or modify
7
   it under the terms of the GNU General Public License as published by
8
   the Free Software Foundation; either version 3, or (at your option)
9
   any later version.
10
11
   GAS is distributed in the hope that it will be useful,
12
   but WITHOUT ANY WARRANTY; without even the implied warranty of
13
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14
   GNU General Public License for more details.
15
16
   You should have received a copy of the GNU General Public License
17
   along with GAS; see the file COPYING.  If not, write to the Free
18
   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
19
   02110-1301, USA.  */
20
21
/* Intel 80386 machine specific gas.
22
   Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23
   x86_64 support by Jan Hubicka (jh@suse.cz)
24
   VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25
   Bugs & suggestions are completely welcome.  This is free software.
26
   Please help us make it better.  */
27
28
#include "as.h"
29
#include "safe-ctype.h"
30
#include "subsegs.h"
31
#include "dwarf2dbg.h"
32
#include "dw2gencfi.h"
33
#include "scfi.h"
34
#include "gen-sframe.h"
35
#include "sframe.h"
36
#include "elf/x86-64.h"
37
#include "opcodes/i386-init.h"
38
#include "opcodes/i386-mnem.h"
39
#include <limits.h>
40
41
#ifndef INFER_ADDR_PREFIX
42
#define INFER_ADDR_PREFIX 1
43
#endif
44
45
#ifndef DEFAULT_ARCH
46
#define DEFAULT_ARCH "i386"
47
#endif
48
49
#ifndef INLINE
50
#if __GNUC__ >= 2
51
#define INLINE __inline__
52
#else
53
#define INLINE
54
#endif
55
#endif
56
57
/* Prefixes will be emitted in the order defined below.
58
   WAIT_PREFIX must be the first prefix since FWAIT is really is an
59
   instruction, and so must come before any prefixes.
60
   The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
61
   REP_PREFIX/HLE_PREFIX, LOCK_PREFIX.  */
62
36
#define WAIT_PREFIX 0
63
23.6k
#define SEG_PREFIX  1
64
163k
#define ADDR_PREFIX 2
65
685k
#define DATA_PREFIX 3
66
1.32k
#define REP_PREFIX  4
67
0
#define HLE_PREFIX  REP_PREFIX
68
1.28k
#define BND_PREFIX  REP_PREFIX
69
662k
#define LOCK_PREFIX 5
70
1.34M
#define REX_PREFIX  6       /* must come last.  */
71
#define MAX_PREFIXES  7 /* max prefixes per opcode */
72
73
/* we define the syntax here (modulo base,index,scale syntax) */
74
1.39M
#define REGISTER_PREFIX '%'
75
96.7k
#define IMMEDIATE_PREFIX '$'
76
193k
#define ABSOLUTE_PREFIX '*'
77
78
/* these are the instruction mnemonic suffixes in AT&T syntax or
79
   memory operand size in Intel syntax.  */
80
695k
#define WORD_MNEM_SUFFIX  'w'
81
728k
#define BYTE_MNEM_SUFFIX  'b'
82
822k
#define SHORT_MNEM_SUFFIX 's'
83
2.22M
#define LONG_MNEM_SUFFIX  'l'
84
2.44M
#define QWORD_MNEM_SUFFIX  'q'
85
86
8.90M
#define END_OF_INSN '\0'
87
88
651k
#define OPERAND_TYPE_NONE { .bitfield = { .class = ClassNone } }
89
90
/* This matches the C -> StaticRounding alias in the opcode table.  */
91
2
#define commutative staticrounding
92
93
/*
94
  'templates' is for grouping together 'template' structures for opcodes
95
  of the same name.  This is only used for storing the insns in the grand
96
  ole hash table of insns.
97
  The templates themselves start at START and range up to (but not including)
98
  END.
99
  */
100
typedef struct
101
{
102
  const insn_template *start;
103
  const insn_template *end;
104
}
105
templates;
106
107
/* 386 operand encoding bytes:  see 386 book for details of this.  */
108
typedef struct
109
{
110
  unsigned int regmem;  /* codes register or memory operand */
111
  unsigned int reg; /* codes register operand (or extended opcode) */
112
  unsigned int mode;  /* how to interpret regmem & reg */
113
}
114
modrm_byte;
115
116
/* x86-64 extension prefix.  */
117
typedef int rex_byte;
118
119
/* 386 opcode byte to code indirect addressing.  */
120
typedef struct
121
{
122
  unsigned base;
123
  unsigned index;
124
  unsigned scale;
125
}
126
sib_byte;
127
128
/* x86 arch names, types and features */
129
typedef struct
130
{
131
  const char *name;   /* arch name */
132
  unsigned int len:8;   /* arch string length */
133
  bool skip:1;      /* show_arch should skip this. */
134
  enum processor_type type; /* arch type */
135
  enum { vsz_none, vsz_set, vsz_reset } vsz; /* vector size control */
136
  i386_cpu_flags enable;    /* cpu feature enable flags */
137
  i386_cpu_flags disable; /* cpu feature disable flags */
138
}
139
arch_entry;
140
141
static void update_code_flag (int, int);
142
static void s_insn (int);
143
static void s_noopt (int);
144
static void set_code_flag (int);
145
static void set_16bit_gcc_code_flag (int);
146
static void set_intel_syntax (int);
147
static void set_intel_mnemonic (int);
148
static void set_allow_index_reg (int);
149
static void set_check (int);
150
static void set_cpu_arch (int);
151
#ifdef TE_PE
152
static void pe_directive_secrel (int);
153
static void pe_directive_secidx (int);
154
#endif
155
static void signed_cons (int);
156
static char *output_invalid (int c);
157
static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
158
            const char *);
159
static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
160
               const char *);
161
static int i386_att_operand (char *);
162
static int i386_intel_operand (char *, int);
163
static int i386_intel_simplify (expressionS *);
164
static int i386_intel_parse_name (const char *, expressionS *);
165
static const reg_entry *parse_register (const char *, char **);
166
static const char *parse_insn (const char *, char *, bool);
167
static char *parse_operands (char *, const char *);
168
static void swap_operands (void);
169
static void swap_2_operands (unsigned int, unsigned int);
170
static enum i386_flag_code i386_addressing_mode (void);
171
static void optimize_imm (void);
172
static bool optimize_disp (const insn_template *t);
173
static const insn_template *match_template (char);
174
static int check_string (void);
175
static int process_suffix (void);
176
static int check_byte_reg (void);
177
static int check_long_reg (void);
178
static int check_qword_reg (void);
179
static int check_word_reg (void);
180
static int finalize_imm (void);
181
static int process_operands (void);
182
static const reg_entry *build_modrm_byte (void);
183
static void output_insn (const struct last_insn *);
184
static void output_imm (fragS *, offsetT);
185
static void output_disp (fragS *, offsetT);
186
#ifdef OBJ_AOUT
187
static void s_bss (int);
188
#endif
189
#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
190
static void handle_large_common (int small ATTRIBUTE_UNUSED);
191
192
/* GNU_PROPERTY_X86_ISA_1_USED.  */
193
static unsigned int x86_isa_1_used;
194
/* GNU_PROPERTY_X86_FEATURE_2_USED.  */
195
static unsigned int x86_feature_2_used;
196
/* Generate x86 used ISA and feature properties.  */
197
static unsigned int x86_used_note = DEFAULT_X86_USED_NOTE;
198
#endif
199
200
static const char *default_arch = DEFAULT_ARCH;
201
202
/* parse_register() returns this when a register alias cannot be used.  */
203
static const reg_entry bad_reg = { "<bad>", OPERAND_TYPE_NONE, 0, 0,
204
           { Dw2Inval, Dw2Inval } };
205
206
static const reg_entry *reg_eax;
207
static const reg_entry *reg_ds;
208
static const reg_entry *reg_es;
209
static const reg_entry *reg_ss;
210
static const reg_entry *reg_st0;
211
static const reg_entry *reg_k0;
212
213
/* VEX prefix.  */
214
typedef struct
215
{
216
  /* VEX prefix is either 2 byte or 3 byte.  EVEX is 4 byte.  */
217
  unsigned char bytes[4];
218
  unsigned int length;
219
  /* Destination or source register specifier.  */
220
  const reg_entry *register_specifier;
221
} vex_prefix;
222
223
/* 'md_assemble ()' gathers together information and puts it into a
224
   i386_insn.  */
225
226
union i386_op
227
  {
228
    expressionS *disps;
229
    expressionS *imms;
230
    const reg_entry *regs;
231
  };
232
233
enum i386_error
234
  {
235
    no_error, /* Must be first.  */
236
    operand_size_mismatch,
237
    operand_type_mismatch,
238
    register_type_mismatch,
239
    number_of_operands_mismatch,
240
    invalid_instruction_suffix,
241
    bad_imm4,
242
    unsupported_with_intel_mnemonic,
243
    unsupported_syntax,
244
    unsupported_EGPR_for_addressing,
245
    unsupported_nf,
246
    unsupported,
247
    unsupported_on_arch,
248
    unsupported_64bit,
249
    no_vex_encoding,
250
    no_evex_encoding,
251
    invalid_sib_address,
252
    invalid_vsib_address,
253
    invalid_vector_register_set,
254
    invalid_tmm_register_set,
255
    invalid_dest_and_src_register_set,
256
    invalid_dest_register_set,
257
    invalid_pseudo_prefix,
258
    unsupported_vector_index_register,
259
    unsupported_broadcast,
260
    broadcast_needed,
261
    unsupported_masking,
262
    mask_not_on_destination,
263
    no_default_mask,
264
    unsupported_rc_sae,
265
    unsupported_vector_size,
266
    unsupported_rsp_register,
267
    internal_error,
268
  };
269
270
struct _i386_insn
271
  {
272
    /* TM holds the template for the insn were currently assembling.  */
273
    insn_template tm;
274
275
    /* SUFFIX holds the instruction size suffix for byte, word, dword
276
       or qword, if given.  */
277
    char suffix;
278
279
    /* OPCODE_LENGTH holds the number of base opcode bytes.  */
280
    unsigned char opcode_length;
281
282
    /* OPERANDS gives the number of given operands.  */
283
    unsigned int operands;
284
285
    /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
286
       of given register, displacement, memory operands and immediate
287
       operands.  */
288
    unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
289
290
    /* TYPES [i] is the type (see above #defines) which tells us how to
291
       use OP[i] for the corresponding operand.  */
292
    i386_operand_type types[MAX_OPERANDS];
293
294
    /* Displacement expression, immediate expression, or register for each
295
       operand.  */
296
    union i386_op op[MAX_OPERANDS];
297
298
    /* Flags for operands.  */
299
    unsigned int flags[MAX_OPERANDS];
300
3.35k
#define Operand_PCrel 1
301
155k
#define Operand_Mem   2
302
0
#define Operand_Signed 4 /* .insn only */
303
304
    /* Relocation type for operand */
305
    enum bfd_reloc_code_real reloc[MAX_OPERANDS];
306
307
    /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
308
       the base index byte below.  */
309
    const reg_entry *base_reg;
310
    const reg_entry *index_reg;
311
    unsigned int log2_scale_factor;
312
313
    /* SEG gives the seg_entries of this insn.  They are zero unless
314
       explicit segment overrides are given.  */
315
    const reg_entry *seg[2];
316
317
    /* PREFIX holds all the given prefix opcodes (usually null).
318
       PREFIXES is the number of prefix opcodes.  */
319
    unsigned int prefixes;
320
    unsigned char prefix[MAX_PREFIXES];
321
322
    /* .insn allows for reserved opcode spaces.  */
323
    unsigned char insn_opcode_space;
324
325
    /* .insn also allows (requires) specifying immediate size.  */
326
    unsigned char imm_bits[MAX_OPERANDS];
327
328
    /* Register is in low 3 bits of opcode.  */
329
    bool short_form;
330
331
    /* The operand to a branch insn indicates an absolute branch.  */
332
    bool jumpabsolute;
333
334
    /* The operand to a branch insn indicates a far branch.  */
335
    bool far_branch;
336
337
    /* There is a memory operand of (%dx) which should be only used
338
       with input/output instructions.  */
339
    bool input_output_operand;
340
341
    /* Extended states.  */
342
    enum
343
      {
344
  /* Use MMX state.  */
345
  xstate_mmx = 1 << 0,
346
  /* Use XMM state.  */
347
  xstate_xmm = 1 << 1,
348
  /* Use YMM state.  */
349
  xstate_ymm = 1 << 2 | xstate_xmm,
350
  /* Use ZMM state.  */
351
  xstate_zmm = 1 << 3 | xstate_ymm,
352
  /* Use TMM state.  */
353
  xstate_tmm = 1 << 4,
354
  /* Use MASK state.  */
355
  xstate_mask = 1 << 5
356
      } xstate;
357
358
    /* Has GOTPC or TLS relocation.  */
359
    bool has_gotpc_tls_reloc;
360
361
    /* RM and SIB are the modrm byte and the sib byte where the
362
       addressing modes of this insn are encoded.  */
363
    modrm_byte rm;
364
    rex_byte rex;
365
    rex_byte vrex;
366
    rex_byte rex2;
367
    sib_byte sib;
368
    vex_prefix vex;
369
370
    /* Masking attributes.
371
372
       The struct describes masking, applied to OPERAND in the instruction.
373
       REG is a pointer to the corresponding mask register.  ZEROING tells
374
       whether merging or zeroing mask is used.  */
375
    struct Mask_Operation
376
    {
377
      const reg_entry *reg;
378
      unsigned int zeroing;
379
      /* The operand where this operation is associated.  */
380
      unsigned int operand;
381
    } mask;
382
383
    /* Rounding control and SAE attributes.  */
384
    struct RC_Operation
385
    {
386
      enum rc_type
387
  {
388
    rc_none = -1,
389
    rne,
390
    rd,
391
    ru,
392
    rz,
393
    saeonly
394
  } type;
395
      /* In Intel syntax the operand modifier form is supposed to be used, but
396
   we continue to accept the immediate forms as well.  */
397
      bool modifier;
398
    } rounding;
399
400
    /* Broadcasting attributes.
401
402
       The struct describes broadcasting, applied to OPERAND.  TYPE is
403
       expresses the broadcast factor.  */
404
    struct Broadcast_Operation
405
    {
406
      /* Type of broadcast: {1to2}, {1to4}, {1to8}, {1to16} or {1to32}.  */
407
      unsigned int type;
408
409
      /* Index of broadcasted operand.  */
410
      unsigned int operand;
411
412
      /* Number of bytes to broadcast.  */
413
      unsigned int bytes;
414
    } broadcast;
415
416
    /* Compressed disp8*N attribute.  */
417
    unsigned int memshift;
418
419
    /* Prefer load or store in encoding.  */
420
    enum
421
      {
422
  dir_encoding_default = 0,
423
  dir_encoding_load,
424
  dir_encoding_store,
425
  dir_encoding_swap
426
      } dir_encoding;
427
428
    /* Prefer 8bit, 16bit, 32bit displacement in encoding.  */
429
    enum
430
      {
431
  disp_encoding_default = 0,
432
  disp_encoding_8bit,
433
  disp_encoding_16bit,
434
  disp_encoding_32bit
435
      } disp_encoding;
436
437
    /* Prefer the REX byte in encoding.  */
438
    bool rex_encoding;
439
440
    /* Prefer the REX2 prefix in encoding.  */
441
    bool rex2_encoding;
442
443
    /* No CSPAZO flags update.  */
444
    bool has_nf;
445
446
    /* Disable instruction size optimization.  */
447
    bool no_optimize;
448
449
    /* How to encode instructions.  */
450
    enum
451
      {
452
  encoding_default = 0,
453
  encoding_vex,
454
  encoding_vex3,
455
  encoding_egpr, /* REX2 or EVEX.  */
456
  encoding_evex,
457
  encoding_evex512,
458
  encoding_error
459
      } encoding;
460
461
    /* REP prefix.  */
462
    const char *rep_prefix;
463
464
    /* HLE prefix.  */
465
    const char *hle_prefix;
466
467
    /* Have BND prefix.  */
468
    const char *bnd_prefix;
469
470
    /* Have NOTRACK prefix.  */
471
    const char *notrack_prefix;
472
473
    /* Error message.  */
474
    enum i386_error error;
475
  };
476
477
typedef struct _i386_insn i386_insn;
478
479
/* Link RC type with corresponding string, that'll be looked for in
480
   asm.  */
481
struct RC_name
482
{
483
  enum rc_type type;
484
  const char *name;
485
  unsigned int len;
486
};
487
488
static const struct RC_name RC_NamesTable[] =
489
{
490
  {  rne, STRING_COMMA_LEN ("rn-sae") },
491
  {  rd,  STRING_COMMA_LEN ("rd-sae") },
492
  {  ru,  STRING_COMMA_LEN ("ru-sae") },
493
  {  rz,  STRING_COMMA_LEN ("rz-sae") },
494
  {  saeonly,  STRING_COMMA_LEN ("sae") },
495
};
496
497
/* To be indexed by segment register number.  */
498
static const unsigned char i386_seg_prefixes[] = {
499
  ES_PREFIX_OPCODE,
500
  CS_PREFIX_OPCODE,
501
  SS_PREFIX_OPCODE,
502
  DS_PREFIX_OPCODE,
503
  FS_PREFIX_OPCODE,
504
  GS_PREFIX_OPCODE
505
};
506
507
/* List of chars besides those in app.c:symbol_chars that can start an
508
   operand.  Used to prevent the scrubber eating vital white-space.  */
509
const char extra_symbol_chars[] = "*%-([{}"
510
#ifdef LEX_AT
511
  "@"
512
#endif
513
#ifdef LEX_QM
514
  "?"
515
#endif
516
  ;
517
518
#if ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
519
     && !defined (TE_GNU)       \
520
     && !defined (TE_LINUX)       \
521
     && !defined (TE_Haiku)       \
522
     && !defined (TE_FreeBSD)       \
523
     && !defined (TE_DragonFly)       \
524
     && !defined (TE_NetBSD))
525
/* This array holds the chars that always start a comment.  If the
526
   pre-processor is disabled, these aren't very useful.  The option
527
   --divide will remove '/' from this list.  */
528
const char *i386_comment_chars = "#/";
529
#define SVR4_COMMENT_CHARS 1
530
#define PREFIX_SEPARATOR '\\'
531
532
#else
533
const char *i386_comment_chars = "#";
534
1.49M
#define PREFIX_SEPARATOR '/'
535
#endif
536
537
/* This array holds the chars that only start a comment at the beginning of
538
   a line.  If the line seems to have the form '# 123 filename'
539
   .line and .file directives will appear in the pre-processed output.
540
   Note that input_file.c hand checks for '#' at the beginning of the
541
   first line of the input file.  This is because the compiler outputs
542
   #NO_APP at the beginning of its output.
543
   Also note that comments started like this one will always work if
544
   '/' isn't otherwise defined.  */
545
const char line_comment_chars[] = "#/";
546
547
const char line_separator_chars[] = ";";
548
549
/* Chars that can be used to separate mant from exp in floating point
550
   nums.  */
551
const char EXP_CHARS[] = "eE";
552
553
/* Chars that mean this number is a floating point constant
554
   As in 0f12.456
555
   or    0d1.2345e12.  */
556
const char FLT_CHARS[] = "fFdDxXhHbB";
557
558
/* Tables for lexical analysis.  */
559
static char mnemonic_chars[256];
560
static char register_chars[256];
561
static char operand_chars[256];
562
563
/* Lexical macros.  */
564
3.55M
#define is_operand_char(x) (operand_chars[(unsigned char) x])
565
#define is_register_char(x) (register_chars[(unsigned char) x])
566
4.67M
#define is_space_char(x) ((x) == ' ')
567
568
/* All non-digit non-letter characters that may occur in an operand and
569
   which aren't already in extra_symbol_chars[].  */
570
static const char operand_special_chars[] = "$+,)._~/<>|&^!=:@]";
571
572
/* md_assemble() always leaves the strings it's passed unaltered.  To
573
   effect this we maintain a stack of saved characters that we've smashed
574
   with '\0's (indicating end of strings for various sub-fields of the
575
   assembler instruction).  */
576
static char save_stack[32];
577
static char *save_stack_p;
578
#define END_STRING_AND_SAVE(s) \
579
131k
  do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
580
#define RESTORE_END_STRING(s) \
581
129k
  do { *(s) = *--save_stack_p; } while (0)
582
583
/* The instruction we're assembling.  */
584
static i386_insn i;
585
586
/* Possible templates for current insn.  */
587
static templates current_templates;
588
589
/* Per instruction expressionS buffers: max displacements & immediates.  */
590
static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
591
static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
592
593
/* Current operand we are working on.  */
594
static int this_operand = -1;
595
596
/* Are we processing a .insn directive?  */
597
126k
#define dot_insn() (i.tm.mnem_off == MN__insn)
598
599
enum i386_flag_code i386_flag_code;
600
4.13M
#define flag_code i386_flag_code /* Permit to continue using original name.  */
601
static unsigned int object_64bit;
602
static unsigned int disallow_64bit_reloc;
603
static int use_rela_relocations = 0;
604
/* __tls_get_addr/___tls_get_addr symbol for TLS.  */
605
static const char *tls_get_addr;
606
607
#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
608
609
/* The ELF ABI to use.  */
610
enum x86_elf_abi
611
{
612
  I386_ABI,
613
  X86_64_ABI,
614
  X86_64_X32_ABI
615
};
616
617
static enum x86_elf_abi x86_elf_abi = I386_ABI;
618
#endif
619
620
#if defined (TE_PE) || defined (TE_PEP)
621
/* Use big object file format.  */
622
static int use_big_obj = 0;
623
#endif
624
625
#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
626
/* 1 if generating code for a shared library.  */
627
static int shared = 0;
628
629
unsigned int x86_sframe_cfa_sp_reg;
630
/* The other CFA base register for SFrame stack trace info.  */
631
unsigned int x86_sframe_cfa_fp_reg;
632
unsigned int x86_sframe_cfa_ra_reg;
633
634
#endif
635
636
/* 1 for intel syntax,
637
   0 if att syntax.  */
638
static int intel_syntax = 0;
639
640
static enum x86_64_isa
641
{
642
  amd64 = 1,  /* AMD64 ISA.  */
643
  intel64 /* Intel64 ISA.  */
644
} isa64;
645
646
/* 1 for intel mnemonic,
647
   0 if att mnemonic.  */
648
static int intel_mnemonic = !SYSV386_COMPAT;
649
650
/* 1 if pseudo registers are permitted.  */
651
static int allow_pseudo_reg = 0;
652
653
/* 1 if register prefix % not required.  */
654
static int allow_naked_reg = 0;
655
656
/* 1 if the assembler should add BND prefix for all control-transferring
657
   instructions supporting it, even if this prefix wasn't specified
658
   explicitly.  */
659
static int add_bnd_prefix = 0;
660
661
/* 1 if pseudo index register, eiz/riz, is allowed .  */
662
static int allow_index_reg = 0;
663
664
/* 1 if the assembler should ignore LOCK prefix, even if it was
665
   specified explicitly.  */
666
static int omit_lock_prefix = 0;
667
668
/* 1 if the assembler should encode lfence, mfence, and sfence as
669
   "lock addl $0, (%{re}sp)".  */
670
static int avoid_fence = 0;
671
672
/* 1 if lfence should be inserted after every load.  */
673
static int lfence_after_load = 0;
674
675
/* Non-zero if lfence should be inserted before indirect branch.  */
676
static enum lfence_before_indirect_branch_kind
677
  {
678
    lfence_branch_none = 0,
679
    lfence_branch_register,
680
    lfence_branch_memory,
681
    lfence_branch_all
682
  }
683
lfence_before_indirect_branch;
684
685
/* Non-zero if lfence should be inserted before ret.  */
686
static enum lfence_before_ret_kind
687
  {
688
    lfence_before_ret_none = 0,
689
    lfence_before_ret_not,
690
    lfence_before_ret_or,
691
    lfence_before_ret_shl
692
  }
693
lfence_before_ret;
694
695
/* 1 if the assembler should generate relax relocations.  */
696
697
static int generate_relax_relocations
698
  = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS;
699
700
static enum check_kind
701
  {
702
    check_none = 0,
703
    check_warning,
704
    check_error
705
  }
706
sse_check, operand_check = check_warning;
707
708
/* Non-zero if branches should be aligned within power of 2 boundary.  */
709
static int align_branch_power = 0;
710
711
/* Types of branches to align.  */
712
enum align_branch_kind
713
  {
714
    align_branch_none = 0,
715
    align_branch_jcc = 1,
716
    align_branch_fused = 2,
717
    align_branch_jmp = 3,
718
    align_branch_call = 4,
719
    align_branch_indirect = 5,
720
    align_branch_ret = 6
721
  };
722
723
/* Type bits of branches to align.  */
724
enum align_branch_bit
725
  {
726
    align_branch_jcc_bit = 1 << align_branch_jcc,
727
    align_branch_fused_bit = 1 << align_branch_fused,
728
    align_branch_jmp_bit = 1 << align_branch_jmp,
729
    align_branch_call_bit = 1 << align_branch_call,
730
    align_branch_indirect_bit = 1 << align_branch_indirect,
731
    align_branch_ret_bit = 1 << align_branch_ret
732
  };
733
734
static unsigned int align_branch = (align_branch_jcc_bit
735
            | align_branch_fused_bit
736
            | align_branch_jmp_bit);
737
738
/* Types of condition jump used by macro-fusion.  */
739
enum mf_jcc_kind
740
  {
741
    mf_jcc_jo = 0,  /* base opcode 0x70  */
742
    mf_jcc_jc,      /* base opcode 0x72  */
743
    mf_jcc_je,      /* base opcode 0x74  */
744
    mf_jcc_jna,     /* base opcode 0x76  */
745
    mf_jcc_js,      /* base opcode 0x78  */
746
    mf_jcc_jp,      /* base opcode 0x7a  */
747
    mf_jcc_jl,      /* base opcode 0x7c  */
748
    mf_jcc_jle,     /* base opcode 0x7e  */
749
  };
750
751
/* Types of compare flag-modifying insntructions used by macro-fusion.  */
752
enum mf_cmp_kind
753
  {
754
    mf_cmp_test_and,  /* test/cmp */
755
    mf_cmp_alu_cmp,  /* add/sub/cmp */
756
    mf_cmp_incdec  /* inc/dec */
757
  };
758
759
/* The maximum padding size for fused jcc.  CMP like instruction can
760
   be 9 bytes and jcc can be 6 bytes.  Leave room just in case for
761
   prefixes.   */
762
736
#define MAX_FUSED_JCC_PADDING_SIZE 20
763
764
/* The maximum number of prefixes added for an instruction.  */
765
static unsigned int align_branch_prefix_size = 5;
766
767
/* Optimization:
768
   1. Clear the REX_W bit with register operand if possible.
769
   2. Above plus use 128bit vector instruction to clear the full vector
770
      register.
771
 */
772
static int optimize = 0;
773
774
/* Optimization:
775
   1. Clear the REX_W bit with register operand if possible.
776
   2. Above plus use 128bit vector instruction to clear the full vector
777
      register.
778
   3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
779
      "testb $imm7,%r8".
780
 */
781
static int optimize_for_space = 0;
782
783
/* Register prefix used for error message.  */
784
static const char *register_prefix = "%";
785
786
/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
787
   leave, push, and pop instructions so that gcc has the same stack
788
   frame as in 32 bit mode.  */
789
static char stackop_size = '\0';
790
791
/* Non-zero to optimize code alignment.  */
792
int optimize_align_code = 1;
793
794
/* Non-zero to quieten some warnings.  */
795
static int quiet_warnings = 0;
796
797
/* Guard to avoid repeated warnings about non-16-bit code on 16-bit CPUs.  */
798
static bool pre_386_16bit_warned;
799
800
/* CPU name.  */
801
static const char *cpu_arch_name = NULL;
802
static char *cpu_sub_arch_name = NULL;
803
804
/* CPU feature flags.  */
805
i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
806
807
/* ISA extensions available in 64-bit mode only.  */
808
static const i386_cpu_flags cpu_64_flags = CPU_ANY_64_FLAGS;
809
810
/* If we have selected a cpu we are generating instructions for.  */
811
static int cpu_arch_tune_set = 0;
812
813
/* Cpu we are generating instructions for.  */
814
enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
815
816
/* CPU instruction set architecture used.  */
817
enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
818
819
/* CPU feature flags of instruction set architecture used.  */
820
i386_cpu_flags cpu_arch_isa_flags;
821
822
/* If set, conditional jumps are not automatically promoted to handle
823
   larger than a byte offset.  */
824
static bool no_cond_jump_promotion = false;
825
826
/* This will be set from an expression parser hook if there's any
827
   applicable operator involved in an expression.  */
828
static enum {
829
  expr_operator_none,
830
  expr_operator_present,
831
  expr_large_value,
832
} expr_mode;
833
834
/* Encode SSE instructions with VEX prefix.  */
835
static unsigned int sse2avx;
836
837
/* Encode aligned vector move as unaligned vector move.  */
838
static unsigned int use_unaligned_vector_move;
839
840
/* Maximum permitted vector size. */
841
0
#define VSZ128 0
842
1.32M
#define VSZ256 1
843
1.32M
#define VSZ512 2
844
116
#define VSZ_DEFAULT VSZ512
845
static unsigned int vector_size = VSZ_DEFAULT;
846
847
/* Encode scalar AVX instructions with specific vector length.  */
848
static enum
849
  {
850
    vex128 = 0,
851
    vex256
852
  } avxscalar;
853
854
/* Encode VEX WIG instructions with specific vex.w.  */
855
static enum
856
  {
857
    vexw0 = 0,
858
    vexw1
859
  } vexwig;
860
861
/* Encode scalar EVEX LIG instructions with specific vector length.  */
862
static enum
863
  {
864
    evexl128 = 0,
865
    evexl256,
866
    evexl512
867
  } evexlig;
868
869
/* Encode EVEX WIG instructions with specific evex.w.  */
870
static enum
871
  {
872
    evexw0 = 0,
873
    evexw1
874
  } evexwig;
875
876
/* Value to encode in EVEX RC bits, for SAE-only instructions.  */
877
static enum rc_type evexrcig = rne;
878
879
/* Pre-defined "_GLOBAL_OFFSET_TABLE_".  */
880
static symbolS *GOT_symbol;
881
882
/* The dwarf2 return column, adjusted for 32 or 64 bit.  */
883
unsigned int x86_dwarf2_return_column;
884
885
/* The dwarf2 data alignment, adjusted for 32 or 64 bit.  */
886
int x86_cie_data_alignment;
887
888
/* Interface to relax_segment.
889
   There are 3 major relax states for 386 jump insns because the
890
   different types of jumps add different sizes to frags when we're
891
   figuring out what sort of jump to choose to reach a given label.
892
893
   BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING are used to align
894
   branches which are handled by md_estimate_size_before_relax() and
895
   i386_generic_table_relax_frag().  */
896
897
/* Types.  */
898
0
#define UNCOND_JUMP 0
899
0
#define COND_JUMP 1
900
0
#define COND_JUMP86 2
901
0
#define BRANCH_PADDING 3
902
0
#define BRANCH_PREFIX 4
903
0
#define FUSED_JCC_PADDING 5
904
905
/* Sizes.  */
906
42
#define CODE16  1
907
1.26k
#define SMALL 0
908
#define SMALL16 (SMALL | CODE16)
909
0
#define BIG 2
910
0
#define BIG16 (BIG | CODE16)
911
912
#ifndef INLINE
913
#ifdef __GNUC__
914
#define INLINE __inline__
915
#else
916
#define INLINE
917
#endif
918
#endif
919
920
#define ENCODE_RELAX_STATE(type, size) \
921
631
  ((relax_substateT) (((type) << 2) | (size)))
922
#define TYPE_FROM_RELAX_STATE(s) \
923
0
  ((s) >> 2)
924
#define DISP_SIZE_FROM_RELAX_STATE(s) \
925
0
    ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
926
927
/* This table is used by relax_frag to promote short jumps to long
928
   ones where necessary.  SMALL (short) jumps may be promoted to BIG
929
   (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long).  We
930
   don't allow a short jump in a 32 bit code segment to be promoted to
931
   a 16 bit offset jump because it's slower (requires data size
932
   prefix), and doesn't work, unless the destination is in the bottom
933
   64k of the code segment (The top 16 bits of eip are zeroed).  */
934
935
const relax_typeS md_relax_table[] =
936
{
937
  /* The fields are:
938
     1) most positive reach of this state,
939
     2) most negative reach of this state,
940
     3) how many bytes this mode will have in the variable part of the frag
941
     4) which index into the table to try if we can't fit into this one.  */
942
943
  /* UNCOND_JUMP states.  */
944
  {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
945
  {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
946
  /* dword jmp adds 4 bytes to frag:
947
     0 extra opcode bytes, 4 displacement bytes.  */
948
  {0, 0, 4, 0},
949
  /* word jmp adds 2 byte2 to frag:
950
     0 extra opcode bytes, 2 displacement bytes.  */
951
  {0, 0, 2, 0},
952
953
  /* COND_JUMP states.  */
954
  {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
955
  {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
956
  /* dword conditionals adds 5 bytes to frag:
957
     1 extra opcode byte, 4 displacement bytes.  */
958
  {0, 0, 5, 0},
959
  /* word conditionals add 3 bytes to frag:
960
     1 extra opcode byte, 2 displacement bytes.  */
961
  {0, 0, 3, 0},
962
963
  /* COND_JUMP86 states.  */
964
  {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
965
  {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
966
  /* dword conditionals adds 5 bytes to frag:
967
     1 extra opcode byte, 4 displacement bytes.  */
968
  {0, 0, 5, 0},
969
  /* word conditionals add 4 bytes to frag:
970
     1 displacement byte and a 3 byte long branch insn.  */
971
  {0, 0, 4, 0}
972
};
973
974
#define ARCH(n, t, f, s) \
975
  { STRING_COMMA_LEN (#n), s, PROCESSOR_ ## t, vsz_none, CPU_ ## f ## _FLAGS, \
976
    CPU_NONE_FLAGS }
977
#define SUBARCH(n, e, d, s) \
978
  { STRING_COMMA_LEN (#n), s, PROCESSOR_NONE, vsz_none, CPU_ ## e ## _FLAGS, \
979
    CPU_ ## d ## _FLAGS }
980
#define VECARCH(n, e, d, v) \
981
  { STRING_COMMA_LEN (#n), false, PROCESSOR_NONE, vsz_ ## v, \
982
    CPU_ ## e ## _FLAGS, CPU_ ## d ## _FLAGS }
983
984
static const arch_entry cpu_arch[] =
985
{
986
  /* Do not replace the first two entries - i386_target_format() and
987
     set_cpu_arch() rely on them being there in this order.  */
988
  ARCH (generic32, GENERIC32, GENERIC32, false),
989
  ARCH (generic64, GENERIC64, GENERIC64, false),
990
  ARCH (i8086, UNKNOWN, NONE, false),
991
  ARCH (i186, UNKNOWN, 186, false),
992
  ARCH (i286, UNKNOWN, 286, false),
993
  ARCH (i386, I386, 386, false),
994
  ARCH (i486, I486, 486, false),
995
  ARCH (i586, PENTIUM, 586, false),
996
  ARCH (pentium, PENTIUM, 586, false),
997
  ARCH (i686, I686, 686, false),
998
  ARCH (pentiumpro, PENTIUMPRO, PENTIUMPRO, false),
999
  ARCH (pentiumii, PENTIUMPRO, P2, false),
1000
  ARCH (pentiumiii, PENTIUMPRO, P3, false),
1001
  ARCH (pentium4, PENTIUM4, P4, false),
1002
  ARCH (prescott, NOCONA, CORE, false),
1003
  ARCH (nocona, NOCONA, NOCONA, false),
1004
  ARCH (yonah, CORE, CORE, true),
1005
  ARCH (core, CORE, CORE, false),
1006
  ARCH (merom, CORE2, CORE2, true),
1007
  ARCH (core2, CORE2, CORE2, false),
1008
  ARCH (corei7, COREI7, COREI7, false),
1009
  ARCH (iamcu, IAMCU, IAMCU, false),
1010
  ARCH (k6, K6, K6, false),
1011
  ARCH (k6_2, K6, K6_2, false),
1012
  ARCH (athlon, ATHLON, ATHLON, false),
1013
  ARCH (sledgehammer, K8, K8, true),
1014
  ARCH (opteron, K8, K8, false),
1015
  ARCH (k8, K8, K8, false),
1016
  ARCH (amdfam10, AMDFAM10, AMDFAM10, false),
1017
  ARCH (bdver1, BD, BDVER1, false),
1018
  ARCH (bdver2, BD, BDVER2, false),
1019
  ARCH (bdver3, BD, BDVER3, false),
1020
  ARCH (bdver4, BD, BDVER4, false),
1021
  ARCH (znver1, ZNVER, ZNVER1, false),
1022
  ARCH (znver2, ZNVER, ZNVER2, false),
1023
  ARCH (znver3, ZNVER, ZNVER3, false),
1024
  ARCH (znver4, ZNVER, ZNVER4, false),
1025
  ARCH (znver5, ZNVER, ZNVER5, false),
1026
  ARCH (btver1, BT, BTVER1, false),
1027
  ARCH (btver2, BT, BTVER2, false),
1028
1029
  SUBARCH (8087, 8087, ANY_8087, false),
1030
  SUBARCH (87, NONE, ANY_8087, false), /* Disable only!  */
1031
  SUBARCH (287, 287, ANY_287, false),
1032
  SUBARCH (387, 387, ANY_387, false),
1033
  SUBARCH (687, 687, ANY_687, false),
1034
  SUBARCH (cmov, CMOV, CMOV, false),
1035
  SUBARCH (fxsr, FXSR, ANY_FXSR, false),
1036
  SUBARCH (mmx, MMX, ANY_MMX, false),
1037
  SUBARCH (sse, SSE, ANY_SSE, false),
1038
  SUBARCH (sse2, SSE2, ANY_SSE2, false),
1039
  SUBARCH (sse3, SSE3, ANY_SSE3, false),
1040
  SUBARCH (sse4a, SSE4A, ANY_SSE4A, false),
1041
  SUBARCH (ssse3, SSSE3, ANY_SSSE3, false),
1042
  SUBARCH (sse4.1, SSE4_1, ANY_SSE4_1, false),
1043
  SUBARCH (sse4.2, SSE4_2, ANY_SSE4_2, false),
1044
  SUBARCH (sse4, SSE4_2, ANY_SSE4_1, false),
1045
  VECARCH (avx, AVX, ANY_AVX, reset),
1046
  VECARCH (avx2, AVX2, ANY_AVX2, reset),
1047
  VECARCH (avx512f, AVX512F, ANY_AVX512F, reset),
1048
  VECARCH (avx512cd, AVX512CD, ANY_AVX512CD, reset),
1049
  VECARCH (avx512er, AVX512ER, ANY_AVX512ER, reset),
1050
  VECARCH (avx512pf, AVX512PF, ANY_AVX512PF, reset),
1051
  VECARCH (avx512dq, AVX512DQ, ANY_AVX512DQ, reset),
1052
  VECARCH (avx512bw, AVX512BW, ANY_AVX512BW, reset),
1053
  VECARCH (avx512vl, AVX512VL, ANY_AVX512VL, reset),
1054
  SUBARCH (monitor, MONITOR, MONITOR, false),
1055
  SUBARCH (vmx, VMX, ANY_VMX, false),
1056
  SUBARCH (vmfunc, VMFUNC, ANY_VMFUNC, false),
1057
  SUBARCH (smx, SMX, SMX, false),
1058
  SUBARCH (xsave, XSAVE, ANY_XSAVE, false),
1059
  SUBARCH (xsaveopt, XSAVEOPT, ANY_XSAVEOPT, false),
1060
  SUBARCH (xsavec, XSAVEC, ANY_XSAVEC, false),
1061
  SUBARCH (xsaves, XSAVES, ANY_XSAVES, false),
1062
  SUBARCH (aes, AES, ANY_AES, false),
1063
  SUBARCH (pclmul, PCLMULQDQ, ANY_PCLMULQDQ, false),
1064
  SUBARCH (clmul, PCLMULQDQ, ANY_PCLMULQDQ, true),
1065
  SUBARCH (fsgsbase, FSGSBASE, FSGSBASE, false),
1066
  SUBARCH (rdrnd, RDRND, RDRND, false),
1067
  SUBARCH (f16c, F16C, ANY_F16C, false),
1068
  SUBARCH (bmi2, BMI2, BMI2, false),
1069
  SUBARCH (fma, FMA, ANY_FMA, false),
1070
  SUBARCH (fma4, FMA4, ANY_FMA4, false),
1071
  SUBARCH (xop, XOP, ANY_XOP, false),
1072
  SUBARCH (lwp, LWP, ANY_LWP, false),
1073
  SUBARCH (movbe, MOVBE, MOVBE, false),
1074
  SUBARCH (cx16, CX16, CX16, false),
1075
  SUBARCH (lahf_sahf, LAHF_SAHF, LAHF_SAHF, false),
1076
  SUBARCH (ept, EPT, ANY_EPT, false),
1077
  SUBARCH (lzcnt, LZCNT, LZCNT, false),
1078
  SUBARCH (popcnt, POPCNT, POPCNT, false),
1079
  SUBARCH (hle, HLE, HLE, false),
1080
  SUBARCH (rtm, RTM, ANY_RTM, false),
1081
  SUBARCH (tsx, TSX, TSX, false),
1082
  SUBARCH (invpcid, INVPCID, INVPCID, false),
1083
  SUBARCH (clflush, CLFLUSH, CLFLUSH, false),
1084
  SUBARCH (nop, NOP, NOP, false),
1085
  SUBARCH (syscall, SYSCALL, SYSCALL, false),
1086
  SUBARCH (rdtscp, RDTSCP, RDTSCP, false),
1087
  SUBARCH (3dnow, 3DNOW, ANY_3DNOW, false),
1088
  SUBARCH (3dnowa, 3DNOWA, ANY_3DNOWA, false),
1089
  SUBARCH (padlock, PADLOCK, PADLOCK, false),
1090
  SUBARCH (pacifica, SVME, ANY_SVME, true),
1091
  SUBARCH (svme, SVME, ANY_SVME, false),
1092
  SUBARCH (abm, ABM, ABM, false),
1093
  SUBARCH (bmi, BMI, BMI, false),
1094
  SUBARCH (tbm, TBM, TBM, false),
1095
  SUBARCH (adx, ADX, ADX, false),
1096
  SUBARCH (rdseed, RDSEED, RDSEED, false),
1097
  SUBARCH (prfchw, PRFCHW, PRFCHW, false),
1098
  SUBARCH (smap, SMAP, SMAP, false),
1099
  SUBARCH (mpx, MPX, ANY_MPX, false),
1100
  SUBARCH (sha, SHA, ANY_SHA, false),
1101
  SUBARCH (clflushopt, CLFLUSHOPT, CLFLUSHOPT, false),
1102
  SUBARCH (prefetchwt1, PREFETCHWT1, PREFETCHWT1, false),
1103
  SUBARCH (se1, SE1, SE1, false),
1104
  SUBARCH (clwb, CLWB, CLWB, false),
1105
  VECARCH (avx512ifma, AVX512IFMA, ANY_AVX512IFMA, reset),
1106
  VECARCH (avx512vbmi, AVX512VBMI, ANY_AVX512VBMI, reset),
1107
  VECARCH (avx512_4fmaps, AVX512_4FMAPS, ANY_AVX512_4FMAPS, reset),
1108
  VECARCH (avx512_4vnniw, AVX512_4VNNIW, ANY_AVX512_4VNNIW, reset),
1109
  VECARCH (avx512_vpopcntdq, AVX512_VPOPCNTDQ, ANY_AVX512_VPOPCNTDQ, reset),
1110
  VECARCH (avx512_vbmi2, AVX512_VBMI2, ANY_AVX512_VBMI2, reset),
1111
  VECARCH (avx512_vnni, AVX512_VNNI, ANY_AVX512_VNNI, reset),
1112
  VECARCH (avx512_bitalg, AVX512_BITALG, ANY_AVX512_BITALG, reset),
1113
  VECARCH (avx_vnni, AVX_VNNI, ANY_AVX_VNNI, reset),
1114
  SUBARCH (clzero, CLZERO, CLZERO, false),
1115
  SUBARCH (mwaitx, MWAITX, MWAITX, false),
1116
  SUBARCH (ospke, OSPKE, ANY_OSPKE, false),
1117
  SUBARCH (rdpid, RDPID, RDPID, false),
1118
  SUBARCH (ptwrite, PTWRITE, PTWRITE, false),
1119
  SUBARCH (ibt, IBT, IBT, false),
1120
  SUBARCH (shstk, SHSTK, SHSTK, false),
1121
  SUBARCH (gfni, GFNI, ANY_GFNI, false),
1122
  VECARCH (vaes, VAES, ANY_VAES, reset),
1123
  VECARCH (vpclmulqdq, VPCLMULQDQ, ANY_VPCLMULQDQ, reset),
1124
  SUBARCH (wbnoinvd, WBNOINVD, WBNOINVD, false),
1125
  SUBARCH (pconfig, PCONFIG, PCONFIG, false),
1126
  SUBARCH (waitpkg, WAITPKG, WAITPKG, false),
1127
  SUBARCH (cldemote, CLDEMOTE, CLDEMOTE, false),
1128
  SUBARCH (amx_int8, AMX_INT8, ANY_AMX_INT8, false),
1129
  SUBARCH (amx_bf16, AMX_BF16, ANY_AMX_BF16, false),
1130
  SUBARCH (amx_fp16, AMX_FP16, ANY_AMX_FP16, false),
1131
  SUBARCH (amx_complex, AMX_COMPLEX, ANY_AMX_COMPLEX, false),
1132
  SUBARCH (amx_tile, AMX_TILE, ANY_AMX_TILE, false),
1133
  SUBARCH (movdiri, MOVDIRI, MOVDIRI, false),
1134
  SUBARCH (movdir64b, MOVDIR64B, MOVDIR64B, false),
1135
  VECARCH (avx512_bf16, AVX512_BF16, ANY_AVX512_BF16, reset),
1136
  VECARCH (avx512_vp2intersect, AVX512_VP2INTERSECT,
1137
     ANY_AVX512_VP2INTERSECT, reset),
1138
  SUBARCH (tdx, TDX, TDX, false),
1139
  SUBARCH (enqcmd, ENQCMD, ENQCMD, false),
1140
  SUBARCH (serialize, SERIALIZE, SERIALIZE, false),
1141
  SUBARCH (rdpru, RDPRU, RDPRU, false),
1142
  SUBARCH (mcommit, MCOMMIT, MCOMMIT, false),
1143
  SUBARCH (sev_es, SEV_ES, ANY_SEV_ES, false),
1144
  SUBARCH (tsxldtrk, TSXLDTRK, ANY_TSXLDTRK, false),
1145
  SUBARCH (kl, KL, ANY_KL, false),
1146
  SUBARCH (widekl, WIDEKL, ANY_WIDEKL, false),
1147
  SUBARCH (uintr, UINTR, UINTR, false),
1148
  SUBARCH (hreset, HRESET, HRESET, false),
1149
  VECARCH (avx512_fp16, AVX512_FP16, ANY_AVX512_FP16, reset),
1150
  SUBARCH (prefetchi, PREFETCHI, PREFETCHI, false),
1151
  VECARCH (avx_ifma, AVX_IFMA, ANY_AVX_IFMA, reset),
1152
  VECARCH (avx_vnni_int8, AVX_VNNI_INT8, ANY_AVX_VNNI_INT8, reset),
1153
  SUBARCH (cmpccxadd, CMPCCXADD, CMPCCXADD, false),
1154
  SUBARCH (wrmsrns, WRMSRNS, WRMSRNS, false),
1155
  SUBARCH (msrlist, MSRLIST, MSRLIST, false),
1156
  VECARCH (avx_ne_convert, AVX_NE_CONVERT, ANY_AVX_NE_CONVERT, reset),
1157
  SUBARCH (rao_int, RAO_INT, RAO_INT, false),
1158
  SUBARCH (rmpquery, RMPQUERY, ANY_RMPQUERY, false),
1159
  SUBARCH (fred, FRED, ANY_FRED, false),
1160
  SUBARCH (lkgs, LKGS, ANY_LKGS, false),
1161
  VECARCH (avx_vnni_int16, AVX_VNNI_INT16, ANY_AVX_VNNI_INT16, reset),
1162
  VECARCH (sha512, SHA512, ANY_SHA512, reset),
1163
  VECARCH (sm3, SM3, ANY_SM3, reset),
1164
  VECARCH (sm4, SM4, ANY_SM4, reset),
1165
  SUBARCH (pbndkb, PBNDKB, PBNDKB, false),
1166
  VECARCH (avx10.1, AVX10_1, ANY_AVX512F, set),
1167
  SUBARCH (user_msr, USER_MSR, USER_MSR, false),
1168
  SUBARCH (apx_f, APX_F, APX_F, false),
1169
};
1170
1171
#undef SUBARCH
1172
#undef ARCH
1173
1174
#ifdef I386COFF
1175
/* Like s_lcomm_internal in gas/read.c but the alignment string
1176
   is allowed to be optional.  */
1177
1178
static symbolS *
1179
pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
1180
{
1181
  addressT align = 0;
1182
1183
  SKIP_WHITESPACE ();
1184
1185
  if (needs_align
1186
      && *input_line_pointer == ',')
1187
    {
1188
      align = parse_align (needs_align - 1);
1189
1190
      if (align == (addressT) -1)
1191
  return NULL;
1192
    }
1193
  else
1194
    {
1195
      if (size >= 8)
1196
  align = 3;
1197
      else if (size >= 4)
1198
  align = 2;
1199
      else if (size >= 2)
1200
  align = 1;
1201
      else
1202
  align = 0;
1203
    }
1204
1205
  bss_alloc (symbolP, size, align);
1206
  return symbolP;
1207
}
1208
1209
static void
1210
pe_lcomm (int needs_align)
1211
{
1212
  s_comm_internal (needs_align * 2, pe_lcomm_internal);
1213
}
1214
#endif
1215
1216
const pseudo_typeS md_pseudo_table[] =
1217
{
1218
#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1219
  {"align", s_align_bytes, 0},
1220
#else
1221
  {"align", s_align_ptwo, 0},
1222
#endif
1223
  {"arch", set_cpu_arch, 0},
1224
#ifdef OBJ_AOUT
1225
  {"bss", s_bss, 0},
1226
#endif
1227
#ifdef I386COFF
1228
  {"lcomm", pe_lcomm, 1},
1229
#endif
1230
  {"ffloat", float_cons, 'f'},
1231
  {"dfloat", float_cons, 'd'},
1232
  {"tfloat", float_cons, 'x'},
1233
  {"hfloat", float_cons, 'h'},
1234
  {"bfloat16", float_cons, 'b'},
1235
  {"value", cons, 2},
1236
  {"slong", signed_cons, 4},
1237
  {"insn", s_insn, 0},
1238
  {"noopt", s_noopt, 0},
1239
  {"optim", s_ignore, 0},
1240
  {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
1241
  {"code16", set_code_flag, CODE_16BIT},
1242
  {"code32", set_code_flag, CODE_32BIT},
1243
#ifdef BFD64
1244
  {"code64", set_code_flag, CODE_64BIT},
1245
#endif
1246
  {"intel_syntax", set_intel_syntax, 1},
1247
  {"att_syntax", set_intel_syntax, 0},
1248
  {"intel_mnemonic", set_intel_mnemonic, 1},
1249
  {"att_mnemonic", set_intel_mnemonic, 0},
1250
  {"allow_index_reg", set_allow_index_reg, 1},
1251
  {"disallow_index_reg", set_allow_index_reg, 0},
1252
  {"sse_check", set_check, 0},
1253
  {"operand_check", set_check, 1},
1254
#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1255
  {"largecomm", handle_large_common, 0},
1256
#else
1257
  {"file", dwarf2_directive_file, 0},
1258
  {"loc", dwarf2_directive_loc, 0},
1259
  {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
1260
#endif
1261
#ifdef TE_PE
1262
  {"secrel32", pe_directive_secrel, 0},
1263
  {"secidx", pe_directive_secidx, 0},
1264
#endif
1265
  {0, 0, 0}
1266
};
1267
1268
/* For interface with expression ().  */
1269
extern char *input_line_pointer;
1270
1271
/* Hash table for instruction mnemonic lookup.  */
1272
static htab_t op_hash;
1273
1274
/* Hash table for register lookup.  */
1275
static htab_t reg_hash;
1276

1277
  /* Various efficient no-op patterns for aligning code labels.
1278
     Note: Don't try to assemble the instructions in the comments.
1279
     0L and 0w are not legal.  */
1280
static const unsigned char f32_1[] =
1281
  {0x90};       /* nop      */
1282
static const unsigned char f32_2[] =
1283
  {0x66,0x90};        /* xchg %ax,%ax   */
1284
static const unsigned char f32_3[] =
1285
  {0x8d,0x76,0x00};     /* leal 0(%esi),%esi  */
1286
#define f32_4 (f32_5 + 1) /* leal 0(%esi,%eiz),%esi */
1287
static const unsigned char f32_5[] =
1288
  {0x2e,0x8d,0x74,0x26,0x00};   /* leal %cs:0(%esi,%eiz),%esi */
1289
static const unsigned char f32_6[] =
1290
  {0x8d,0xb6,0x00,0x00,0x00,0x00};  /* leal 0L(%esi),%esi */
1291
#define f32_7 (f32_8 + 1) /* leal 0L(%esi,%eiz),%esi */
1292
static const unsigned char f32_8[] =
1293
  {0x2e,0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal %cs:0L(%esi,%eiz),%esi */
1294
static const unsigned char f64_3[] =
1295
  {0x48,0x89,0xf6};     /* mov %rsi,%rsi  */
1296
static const unsigned char f64_4[] =
1297
  {0x48,0x8d,0x76,0x00};    /* lea 0(%rsi),%rsi */
1298
#define f64_5 (f64_6 + 1)   /* lea 0(%rsi,%riz),%rsi  */
1299
static const unsigned char f64_6[] =
1300
  {0x2e,0x48,0x8d,0x74,0x26,0x00};  /* lea %cs:0(%rsi,%riz),%rsi  */
1301
static const unsigned char f64_7[] =
1302
  {0x48,0x8d,0xb6,0x00,0x00,0x00,0x00}; /* lea 0L(%rsi),%rsi  */
1303
#define f64_8 (f64_9 + 1)   /* lea 0L(%rsi,%riz),%rsi */
1304
static const unsigned char f64_9[] =
1305
  {0x2e,0x48,0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* lea %cs:0L(%rsi,%riz),%rsi */
1306
#define f16_2 (f64_3 + 1)   /* mov %si,%si  */
1307
static const unsigned char f16_3[] =
1308
  {0x8d,0x74,0x00};     /* lea 0(%si),%si */
1309
#define f16_4 (f16_5 + 1)   /* lea 0W(%si),%si */
1310
static const unsigned char f16_5[] =
1311
  {0x2e,0x8d,0xb4,0x00,0x00};   /* lea %cs:0W(%si),%si  */
1312
static const unsigned char jump_disp8[] =
1313
  {0xeb};       /* jmp disp8         */
1314
static const unsigned char jump32_disp32[] =
1315
  {0xe9};       /* jmp disp32        */
1316
static const unsigned char jump16_disp32[] =
1317
  {0x66,0xe9};        /* jmp disp32        */
1318
/* 32-bit NOPs patterns.  */
1319
static const unsigned char *const f32_patt[] = {
1320
  f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8
1321
};
1322
/* 64-bit NOPs patterns.  */
1323
static const unsigned char *const f64_patt[] = {
1324
  f32_1, f32_2, f64_3, f64_4, f64_5, f64_6, f64_7, f64_8, f64_9
1325
};
1326
/* 16-bit NOPs patterns.  */
1327
static const unsigned char *const f16_patt[] = {
1328
  f32_1, f16_2, f16_3, f16_4, f16_5
1329
};
1330
/* nopl (%[re]ax) */
1331
static const unsigned char alt_3[] =
1332
  {0x0f,0x1f,0x00};
1333
/* nopl 0(%[re]ax) */
1334
static const unsigned char alt_4[] =
1335
  {0x0f,0x1f,0x40,0x00};
1336
/* nopl 0(%[re]ax,%[re]ax,1) */
1337
#define alt_5 (alt_6 + 1)
1338
/* nopw 0(%[re]ax,%[re]ax,1) */
1339
static const unsigned char alt_6[] =
1340
  {0x66,0x0f,0x1f,0x44,0x00,0x00};
1341
/* nopl 0L(%[re]ax) */
1342
static const unsigned char alt_7[] =
1343
  {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1344
/* nopl 0L(%[re]ax,%[re]ax,1) */
1345
#define alt_8 (alt_9 + 1)
1346
/* nopw 0L(%[re]ax,%[re]ax,1) */
1347
static const unsigned char alt_9[] =
1348
  {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1349
/* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1350
#define alt_10 (alt_11 + 1)
1351
/* data16 nopw %cs:0L(%eax,%eax,1) */
1352
static const unsigned char alt_11[] =
1353
  {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1354
/* 32-bit and 64-bit NOPs patterns.  */
1355
static const unsigned char *const alt_patt[] = {
1356
  f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1357
  alt_9, alt_10, alt_11
1358
};
1359
#define alt64_9 (alt64_15 + 6)    /* nopq 0L(%rax,%rax,1)  */
1360
#define alt64_10 (alt64_15 + 5)   /* cs nopq 0L(%rax,%rax,1)  */
1361
/* data16 cs nopq 0L(%rax,%rax,1)  */
1362
#define alt64_11 (alt64_15 + 4)
1363
/* data16 data16 cs nopq 0L(%rax,%rax,1)  */
1364
#define alt64_12 (alt64_15 + 3)
1365
/* data16 data16 data16 cs nopq 0L(%rax,%rax,1)  */
1366
#define alt64_13 (alt64_15 + 2)
1367
/* data16 data16 data16 data16 cs nopq 0L(%rax,%rax,1)  */
1368
#define alt64_14 (alt64_15 + 1)
1369
/* data16 data16 data16 data16 data16 cs nopq 0L(%rax,%rax,1)  */
1370
static const unsigned char alt64_15[] =
1371
  {0x66,0x66,0x66,0x66,0x66,0x2e,0x48,
1372
   0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1373
/* Long 64-bit NOPs patterns.  */
1374
static const unsigned char *const alt64_patt[] = {
1375
  f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1376
  alt64_9, alt64_10, alt64_11,alt64_12, alt64_13, alt64_14, alt64_15
1377
};
1378
1379
/* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1380
   size of a single NOP instruction MAX_SINGLE_NOP_SIZE.  */
1381
1382
static void
1383
i386_output_nops (char *where, const unsigned char *const *patt,
1384
      int count, int max_single_nop_size)
1385
1386
0
{
1387
  /* Place the longer NOP first.  */
1388
0
  int last;
1389
0
  int offset;
1390
0
  const unsigned char *nops;
1391
1392
0
  if (max_single_nop_size < 1)
1393
0
    {
1394
0
      as_fatal (_("i386_output_nops called to generate nops of at most %d bytes!"),
1395
0
    max_single_nop_size);
1396
0
      return;
1397
0
    }
1398
1399
0
  nops = patt[max_single_nop_size - 1];
1400
0
  last = count % max_single_nop_size;
1401
1402
0
  count -= last;
1403
0
  for (offset = 0; offset < count; offset += max_single_nop_size)
1404
0
    memcpy (where + offset, nops, max_single_nop_size);
1405
1406
0
  if (last)
1407
0
    {
1408
0
      nops = patt[last - 1];
1409
0
      memcpy (where + offset, nops, last);
1410
0
    }
1411
0
}
1412
1413
static INLINE int
1414
fits_in_imm7 (offsetT num)
1415
0
{
1416
0
  return (num & 0x7f) == num;
1417
0
}
1418
1419
static INLINE int
1420
fits_in_imm31 (offsetT num)
1421
0
{
1422
0
  return (num & 0x7fffffff) == num;
1423
0
}
1424
1425
/* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1426
   single NOP instruction LIMIT.  */
1427
1428
void
1429
i386_generate_nops (fragS *fragP, char *where, offsetT count, int limit)
1430
0
{
1431
0
  const unsigned char *const *patt = NULL;
1432
0
  int max_single_nop_size;
1433
  /* Maximum number of NOPs before switching to jump over NOPs.  */
1434
0
  int max_number_of_nops;
1435
1436
0
  switch (fragP->fr_type)
1437
0
    {
1438
0
    case rs_fill_nop:
1439
0
    case rs_align_code:
1440
0
      break;
1441
0
    case rs_machine_dependent:
1442
      /* Allow NOP padding for jumps and calls.  */
1443
0
      if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PADDING
1444
0
    || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == FUSED_JCC_PADDING)
1445
0
  break;
1446
      /* Fall through.  */
1447
0
    default:
1448
0
      return;
1449
0
    }
1450
1451
  /* We need to decide which NOP sequence to use for 32bit and
1452
     64bit. When -mtune= is used:
1453
1454
     1. For PROCESSOR_I?86, PROCESSOR_PENTIUM, PROCESSOR_IAMCU, and
1455
     PROCESSOR_GENERIC32, f32_patt will be used.
1456
     2. For the rest, alt_patt will be used.
1457
1458
     When -mtune= isn't used, alt_patt will be used if
1459
     cpu_arch_isa_flags has CpuNop.  Otherwise, f32_patt/f64_patt will
1460
     be used.
1461
1462
     When -march= or .arch is used, we can't use anything beyond
1463
     cpu_arch_isa_flags.   */
1464
1465
0
  if (fragP->tc_frag_data.code == CODE_16BIT)
1466
0
    {
1467
0
      patt = f16_patt;
1468
0
      max_single_nop_size = sizeof (f16_patt) / sizeof (f16_patt[0]);
1469
      /* Limit number of NOPs to 2 in 16-bit mode.  */
1470
0
      max_number_of_nops = 2;
1471
0
    }
1472
0
  else
1473
0
    {
1474
0
      patt = fragP->tc_frag_data.code == CODE_64BIT ? f64_patt : f32_patt;
1475
0
      if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
1476
0
  {
1477
    /* PROCESSOR_UNKNOWN means that all ISAs may be used, unless
1478
       explicitly disabled.  */
1479
0
    switch (fragP->tc_frag_data.tune)
1480
0
      {
1481
0
      case PROCESSOR_UNKNOWN:
1482
        /* We use cpu_arch_isa_flags to check if we SHOULD
1483
     optimize with nops.  */
1484
0
        if (fragP->tc_frag_data.isanop)
1485
0
    patt = alt_patt;
1486
0
        break;
1487
1488
0
      case PROCESSOR_CORE:
1489
0
      case PROCESSOR_CORE2:
1490
0
      case PROCESSOR_COREI7:
1491
0
        if (fragP->tc_frag_data.cpunop)
1492
0
    {
1493
0
      if (fragP->tc_frag_data.code == CODE_64BIT)
1494
0
        patt = alt64_patt;
1495
0
      else
1496
0
        patt = alt_patt;
1497
0
    }
1498
0
        break;
1499
1500
0
      case PROCESSOR_PENTIUMPRO:
1501
0
      case PROCESSOR_PENTIUM4:
1502
0
      case PROCESSOR_NOCONA:
1503
0
      case PROCESSOR_GENERIC64:
1504
0
      case PROCESSOR_K6:
1505
0
      case PROCESSOR_ATHLON:
1506
0
      case PROCESSOR_K8:
1507
0
      case PROCESSOR_AMDFAM10:
1508
0
      case PROCESSOR_BD:
1509
0
      case PROCESSOR_ZNVER:
1510
0
      case PROCESSOR_BT:
1511
0
        if (fragP->tc_frag_data.cpunop)
1512
0
    patt = alt_patt;
1513
0
        break;
1514
1515
0
      case PROCESSOR_I386:
1516
0
      case PROCESSOR_I486:
1517
0
      case PROCESSOR_PENTIUM:
1518
0
      case PROCESSOR_I686:
1519
0
      case PROCESSOR_IAMCU:
1520
0
      case PROCESSOR_GENERIC32:
1521
0
        break;
1522
0
      case PROCESSOR_NONE:
1523
0
        abort ();
1524
0
      }
1525
0
  }
1526
0
      else
1527
0
  {
1528
0
    switch (fragP->tc_frag_data.tune)
1529
0
      {
1530
0
      case PROCESSOR_UNKNOWN:
1531
        /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1532
     PROCESSOR_UNKNOWN.  */
1533
0
        abort ();
1534
0
        break;
1535
1536
0
      default:
1537
        /* We use cpu_arch_isa_flags to check if we CAN optimize
1538
     with nops.  */
1539
0
        if (fragP->tc_frag_data.isanop)
1540
0
    patt = alt_patt;
1541
0
        break;
1542
1543
0
      case PROCESSOR_NONE:
1544
0
        abort ();
1545
0
      }
1546
0
  }
1547
1548
0
      if (patt != alt_patt && patt != alt64_patt)
1549
0
  {
1550
0
    max_single_nop_size = patt == f32_patt ? ARRAY_SIZE (f32_patt)
1551
0
             : ARRAY_SIZE (f64_patt);
1552
    /* Limit number of NOPs to 2 for older processors.  */
1553
0
    max_number_of_nops = 2;
1554
0
  }
1555
0
      else
1556
0
  {
1557
0
    max_single_nop_size = patt == alt_patt
1558
0
        ? ARRAY_SIZE (alt_patt)
1559
0
        : ARRAY_SIZE (alt64_patt);
1560
    /* Limit number of NOPs to 7 for newer processors.  */
1561
0
    max_number_of_nops = 7;
1562
0
  }
1563
0
    }
1564
1565
0
  if (limit == 0)
1566
0
    limit = max_single_nop_size;
1567
1568
0
  if (fragP->fr_type == rs_fill_nop)
1569
0
    {
1570
      /* Output NOPs for .nop directive.  */
1571
0
      if (limit > max_single_nop_size)
1572
0
  {
1573
0
    as_bad_where (fragP->fr_file, fragP->fr_line,
1574
0
      _("invalid single nop size: %d "
1575
0
        "(expect within [0, %d])"),
1576
0
      limit, max_single_nop_size);
1577
0
    return;
1578
0
  }
1579
0
    }
1580
0
  else if (fragP->fr_type != rs_machine_dependent)
1581
0
    fragP->fr_var = count;
1582
1583
  /* Emit a plain NOP first when the last thing we saw may not have been
1584
     a proper instruction (e.g. a stand-alone prefix or .byte).  */
1585
0
  if (!fragP->tc_frag_data.last_insn_normal)
1586
0
    {
1587
0
      *where++ = 0x90;
1588
0
      --count;
1589
0
    }
1590
1591
0
  if ((count / max_single_nop_size) > max_number_of_nops)
1592
0
    {
1593
      /* Generate jump over NOPs.  */
1594
0
      offsetT disp = count - 2;
1595
0
      if (fits_in_imm7 (disp))
1596
0
  {
1597
    /* Use "jmp disp8" if possible.  */
1598
0
    count = disp;
1599
0
    where[0] = jump_disp8[0];
1600
0
    where[1] = count;
1601
0
    where += 2;
1602
0
  }
1603
0
      else
1604
0
  {
1605
0
    unsigned int size_of_jump;
1606
1607
0
    if (flag_code == CODE_16BIT)
1608
0
      {
1609
0
        where[0] = jump16_disp32[0];
1610
0
        where[1] = jump16_disp32[1];
1611
0
        size_of_jump = 2;
1612
0
      }
1613
0
    else
1614
0
      {
1615
0
        where[0] = jump32_disp32[0];
1616
0
        size_of_jump = 1;
1617
0
      }
1618
1619
0
    count -= size_of_jump + 4;
1620
0
    if (!fits_in_imm31 (count))
1621
0
      {
1622
0
        as_bad_where (fragP->fr_file, fragP->fr_line,
1623
0
          _("jump over nop padding out of range"));
1624
0
        return;
1625
0
      }
1626
1627
0
    md_number_to_chars (where + size_of_jump, count, 4);
1628
0
    where += size_of_jump + 4;
1629
0
  }
1630
0
    }
1631
1632
  /* Generate multiple NOPs.  */
1633
0
  i386_output_nops (where, patt, count, limit);
1634
0
}
1635
1636
static INLINE int
1637
operand_type_all_zero (const union i386_operand_type *x)
1638
74.0k
{
1639
74.0k
  switch (ARRAY_SIZE(x->array))
1640
74.0k
    {
1641
0
    case 3:
1642
0
      if (x->array[2])
1643
0
  return 0;
1644
      /* Fall through.  */
1645
0
    case 2:
1646
0
      if (x->array[1])
1647
0
  return 0;
1648
      /* Fall through.  */
1649
74.0k
    case 1:
1650
74.0k
      return !x->array[0];
1651
0
    default:
1652
0
      abort ();
1653
74.0k
    }
1654
74.0k
}
1655
1656
static INLINE void
1657
operand_type_set (union i386_operand_type *x, unsigned int v)
1658
128k
{
1659
128k
  switch (ARRAY_SIZE(x->array))
1660
128k
    {
1661
0
    case 3:
1662
0
      x->array[2] = v;
1663
      /* Fall through.  */
1664
0
    case 2:
1665
0
      x->array[1] = v;
1666
      /* Fall through.  */
1667
128k
    case 1:
1668
128k
      x->array[0] = v;
1669
      /* Fall through.  */
1670
128k
      break;
1671
0
    default:
1672
0
      abort ();
1673
128k
    }
1674
1675
128k
  x->bitfield.class = ClassNone;
1676
128k
  x->bitfield.instance = InstanceNone;
1677
128k
}
1678
1679
static INLINE int
1680
operand_type_equal (const union i386_operand_type *x,
1681
        const union i386_operand_type *y)
1682
0
{
1683
0
  switch (ARRAY_SIZE(x->array))
1684
0
    {
1685
0
    case 3:
1686
0
      if (x->array[2] != y->array[2])
1687
0
  return 0;
1688
      /* Fall through.  */
1689
0
    case 2:
1690
0
      if (x->array[1] != y->array[1])
1691
0
  return 0;
1692
      /* Fall through.  */
1693
0
    case 1:
1694
0
      return x->array[0] == y->array[0];
1695
0
      break;
1696
0
    default:
1697
0
      abort ();
1698
0
    }
1699
0
}
1700
1701
static INLINE bool
1702
_is_cpu (const i386_cpu_attr *a, enum i386_cpu cpu)
1703
19.4M
{
1704
19.4M
  switch (cpu)
1705
19.4M
    {
1706
619k
    case Cpu287:      return a->bitfield.cpu287;
1707
619k
    case Cpu387:      return a->bitfield.cpu387;
1708
0
    case Cpu3dnow:    return a->bitfield.cpu3dnow;
1709
0
    case Cpu3dnowA:   return a->bitfield.cpu3dnowa;
1710
639k
    case CpuAVX:      return a->bitfield.cpuavx;
1711
47
    case CpuHLE:      return a->bitfield.cpuhle;
1712
619k
    case CpuAVX512F:  return a->bitfield.cpuavx512f;
1713
619k
    case CpuAVX512VL: return a->bitfield.cpuavx512vl;
1714
17.5k
    case CpuAPX_F:    return a->bitfield.cpuapx_f;
1715
0
    case Cpu64:       return a->bitfield.cpu64;
1716
0
    case CpuNo64:     return a->bitfield.cpuno64;
1717
16.3M
    default:
1718
16.3M
      gas_assert (cpu < CpuAttrEnums);
1719
19.4M
    }
1720
16.3M
  return a->bitfield.isa == cpu + 1u;
1721
19.4M
}
1722
1723
static INLINE bool
1724
is_cpu (const insn_template *t, enum i386_cpu cpu)
1725
19.4M
{
1726
19.4M
  return _is_cpu(&t->cpu, cpu);
1727
19.4M
}
1728
1729
static INLINE bool
1730
maybe_cpu (const insn_template *t, enum i386_cpu cpu)
1731
19.4k
{
1732
19.4k
  return _is_cpu(&t->cpu_any, cpu);
1733
19.4k
}
1734
1735
static i386_cpu_flags cpu_flags_from_attr (i386_cpu_attr a)
1736
3.16M
{
1737
3.16M
  const unsigned int bps = sizeof (a.array[0]) * CHAR_BIT;
1738
3.16M
  i386_cpu_flags f = { .array[0] = 0 };
1739
1740
3.16M
  switch (ARRAY_SIZE (a.array))
1741
3.16M
    {
1742
3.16M
    case 1:
1743
3.16M
      f.array[CpuAttrEnums / bps]
1744
3.16M
#ifndef WORDS_BIGENDIAN
1745
3.16M
  |= (a.array[0] >> CpuIsaBits) << (CpuAttrEnums % bps);
1746
#else
1747
  |= (a.array[0] << CpuIsaBits) >> (CpuAttrEnums % bps);
1748
#endif
1749
3.16M
      if (CpuMax / bps > CpuAttrEnums / bps)
1750
0
  f.array[CpuAttrEnums / bps + 1]
1751
0
#ifndef WORDS_BIGENDIAN
1752
0
    = (a.array[0] >> CpuIsaBits) >> (bps - CpuAttrEnums % bps);
1753
#else
1754
    = (a.array[0] << CpuIsaBits) << (bps - CpuAttrEnums % bps);
1755
#endif
1756
3.16M
      break;
1757
1758
0
    default:
1759
0
      abort ();
1760
3.16M
    }
1761
1762
3.16M
  if (a.bitfield.isa)
1763
656k
#ifndef WORDS_BIGENDIAN
1764
656k
    f.array[(a.bitfield.isa - 1) / bps] |= 1u << ((a.bitfield.isa - 1) % bps);
1765
#else
1766
    f.array[(a.bitfield.isa - 1) / bps] |= 1u << (~(a.bitfield.isa - 1) % bps);
1767
#endif
1768
1769
3.16M
  return f;
1770
3.16M
}
1771
1772
static INLINE int
1773
cpu_flags_all_zero (const union i386_cpu_flags *x)
1774
3.08M
{
1775
3.08M
  switch (ARRAY_SIZE(x->array))
1776
3.08M
    {
1777
3.08M
    case 5:
1778
3.08M
      if (x->array[4])
1779
99.6k
  return 0;
1780
      /* Fall through.  */
1781
2.98M
    case 4:
1782
2.98M
      if (x->array[3])
1783
177
  return 0;
1784
      /* Fall through.  */
1785
2.98M
    case 3:
1786
2.98M
      if (x->array[2])
1787
1.12k
  return 0;
1788
      /* Fall through.  */
1789
2.98M
    case 2:
1790
2.98M
      if (x->array[1])
1791
4.31k
  return 0;
1792
      /* Fall through.  */
1793
2.97M
    case 1:
1794
2.97M
      return !x->array[0];
1795
0
    default:
1796
0
      abort ();
1797
3.08M
    }
1798
3.08M
}
1799
1800
static INLINE int
1801
cpu_flags_equal (const union i386_cpu_flags *x,
1802
     const union i386_cpu_flags *y)
1803
746k
{
1804
746k
  switch (ARRAY_SIZE(x->array))
1805
746k
    {
1806
746k
    case 5:
1807
746k
      if (x->array[4] != y->array[4])
1808
83.4k
  return 0;
1809
      /* Fall through.  */
1810
663k
    case 4:
1811
663k
      if (x->array[3] != y->array[3])
1812
151
  return 0;
1813
      /* Fall through.  */
1814
663k
    case 3:
1815
663k
      if (x->array[2] != y->array[2])
1816
234
  return 0;
1817
      /* Fall through.  */
1818
663k
    case 2:
1819
663k
      if (x->array[1] != y->array[1])
1820
4.03k
  return 0;
1821
      /* Fall through.  */
1822
658k
    case 1:
1823
658k
      return x->array[0] == y->array[0];
1824
0
      break;
1825
0
    default:
1826
0
      abort ();
1827
746k
    }
1828
746k
}
1829
1830
static INLINE int
1831
cpu_flags_check_cpu64 (const insn_template *t)
1832
1.57M
{
1833
1.57M
  return flag_code == CODE_64BIT
1834
1.57M
   ? !t->cpu.bitfield.cpuno64
1835
1.57M
   : !t->cpu.bitfield.cpu64;
1836
1.57M
}
1837
1838
static INLINE i386_cpu_flags
1839
cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
1840
1.42M
{
1841
1.42M
  switch (ARRAY_SIZE (x.array))
1842
1.42M
    {
1843
1.42M
    case 5:
1844
1.42M
      x.array [4] &= y.array [4];
1845
      /* Fall through.  */
1846
1.42M
    case 4:
1847
1.42M
      x.array [3] &= y.array [3];
1848
      /* Fall through.  */
1849
1.42M
    case 3:
1850
1.42M
      x.array [2] &= y.array [2];
1851
      /* Fall through.  */
1852
1.42M
    case 2:
1853
1.42M
      x.array [1] &= y.array [1];
1854
      /* Fall through.  */
1855
1.42M
    case 1:
1856
1.42M
      x.array [0] &= y.array [0];
1857
1.42M
      break;
1858
0
    default:
1859
0
      abort ();
1860
1.42M
    }
1861
1.42M
  return x;
1862
1.42M
}
1863
1864
static INLINE i386_cpu_flags
1865
cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
1866
60
{
1867
60
  switch (ARRAY_SIZE (x.array))
1868
60
    {
1869
60
    case 5:
1870
60
      x.array [4] |= y.array [4];
1871
      /* Fall through.  */
1872
60
    case 4:
1873
60
      x.array [3] |= y.array [3];
1874
      /* Fall through.  */
1875
60
    case 3:
1876
60
      x.array [2] |= y.array [2];
1877
      /* Fall through.  */
1878
60
    case 2:
1879
60
      x.array [1] |= y.array [1];
1880
      /* Fall through.  */
1881
60
    case 1:
1882
60
      x.array [0] |= y.array [0];
1883
60
      break;
1884
0
    default:
1885
0
      abort ();
1886
60
    }
1887
60
  return x;
1888
60
}
1889
1890
static INLINE i386_cpu_flags
1891
cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1892
646k
{
1893
646k
  switch (ARRAY_SIZE (x.array))
1894
646k
    {
1895
646k
    case 5:
1896
646k
      x.array [4] &= ~y.array [4];
1897
      /* Fall through.  */
1898
646k
    case 4:
1899
646k
      x.array [3] &= ~y.array [3];
1900
      /* Fall through.  */
1901
646k
    case 3:
1902
646k
      x.array [2] &= ~y.array [2];
1903
      /* Fall through.  */
1904
646k
    case 2:
1905
646k
      x.array [1] &= ~y.array [1];
1906
      /* Fall through.  */
1907
646k
    case 1:
1908
646k
      x.array [0] &= ~y.array [0];
1909
646k
      break;
1910
0
    default:
1911
0
      abort ();
1912
646k
    }
1913
646k
  return x;
1914
646k
}
1915
1916
static const i386_cpu_flags avx512 = CPU_ANY_AVX512F_FLAGS;
1917
1918
static INLINE bool need_evex_encoding (const insn_template *t)
1919
3.45k
{
1920
3.45k
  return i.encoding == encoding_evex
1921
3.45k
  || i.encoding == encoding_evex512
1922
3.45k
  || (t->opcode_modifier.vex && i.encoding == encoding_egpr)
1923
3.45k
  || i.mask.reg;
1924
3.45k
}
1925
1926
3.05M
#define CPU_FLAGS_ARCH_MATCH    0x1
1927
3.09M
#define CPU_FLAGS_64BIT_MATCH   0x2
1928
1929
#define CPU_FLAGS_PERFECT_MATCH \
1930
1.57M
  (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1931
1932
/* Return CPU flags match bits. */
1933
1934
static int
1935
cpu_flags_match (const insn_template *t)
1936
1.57M
{
1937
1.57M
  i386_cpu_flags cpu, active, all = cpu_flags_from_attr (t->cpu);
1938
1.57M
  i386_cpu_flags any = cpu_flags_from_attr (t->cpu_any);
1939
1.57M
  int match = cpu_flags_check_cpu64 (t) ? CPU_FLAGS_64BIT_MATCH : 0;
1940
1941
1.57M
  all.bitfield.cpu64 = 0;
1942
1.57M
  all.bitfield.cpuno64 = 0;
1943
1.57M
  gas_assert (!any.bitfield.cpu64);
1944
1.57M
  gas_assert (!any.bitfield.cpuno64);
1945
1946
1.57M
  if (cpu_flags_all_zero (&all) && cpu_flags_all_zero (&any))
1947
825k
    {
1948
      /* This instruction is available on all archs.  */
1949
825k
      return match | CPU_FLAGS_ARCH_MATCH;
1950
825k
    }
1951
1952
  /* This instruction is available only on some archs.  */
1953
1954
  /* Dual VEX/EVEX templates may need stripping of one of the flags.  */
1955
746k
  if (t->opcode_modifier.vex && t->opcode_modifier.evex)
1956
3.45k
    {
1957
      /* Dual AVX/AVX512 templates need to retain AVX512* only if we already
1958
   know that EVEX encoding will be needed.  */
1959
3.45k
      if ((any.bitfield.cpuavx || any.bitfield.cpuavx2 || any.bitfield.cpufma)
1960
3.45k
    && (any.bitfield.cpuavx512f || any.bitfield.cpuavx512vl))
1961
3.44k
  {
1962
3.44k
    if (need_evex_encoding (t))
1963
0
      {
1964
0
        any.bitfield.cpuavx = 0;
1965
0
        any.bitfield.cpuavx2 = 0;
1966
0
        any.bitfield.cpufma = 0;
1967
0
      }
1968
    /* need_evex_encoding(t) isn't reliable before operands were
1969
       parsed.  */
1970
3.44k
    else if (i.operands)
1971
0
      {
1972
0
        any.bitfield.cpuavx512f = 0;
1973
0
        any.bitfield.cpuavx512vl = 0;
1974
0
      }
1975
3.44k
  }
1976
1977
      /* Dual non-APX/APX templates need massaging from what APX_F() in the
1978
         opcode table has produced.  While the direct transformation of the
1979
         incoming cpuid&(cpuid|APX_F) would be to cpuid&(cpuid) / cpuid&(APX_F)
1980
         respectively, it's cheaper to move to just cpuid / cpuid&APX_F
1981
         instead.  */
1982
3.45k
      if (any.bitfield.cpuapx_f
1983
3.45k
    && (any.bitfield.cpubmi || any.bitfield.cpubmi2
1984
2
        || any.bitfield.cpuavx512f || any.bitfield.cpuavx512bw
1985
2
        || any.bitfield.cpuavx512dq || any.bitfield.cpuamx_tile
1986
2
        || any.bitfield.cpucmpccxadd || any.bitfield.cpuuser_msr))
1987
2
  {
1988
    /* These checks (verifying that APX_F() was properly used in the
1989
       opcode table entry) make sure there's no need for an "else" to
1990
       the "if()" below.  */
1991
2
    gas_assert (!cpu_flags_all_zero (&all));
1992
2
    cpu = cpu_flags_and (all, any);
1993
2
    gas_assert (cpu_flags_equal (&cpu, &all));
1994
1995
2
    if (need_evex_encoding (t))
1996
0
      all = any;
1997
1998
2
    memset (&any, 0, sizeof (any));
1999
2
  }
2000
3.45k
    }
2001
2002
746k
  if (flag_code != CODE_64BIT)
2003
646k
    active = cpu_flags_and_not (cpu_arch_flags, cpu_64_flags);
2004
100k
  else
2005
100k
    active = cpu_arch_flags;
2006
746k
  cpu = cpu_flags_and (all, active);
2007
746k
  if (cpu_flags_equal (&cpu, &all))
2008
658k
    {
2009
      /* AVX and AVX2 present at the same time express an operand size
2010
   dependency - strip AVX2 for the purposes here.  The operand size
2011
   dependent check occurs in check_vecOperands().  */
2012
658k
      if (any.bitfield.cpuavx && any.bitfield.cpuavx2)
2013
225
  any.bitfield.cpuavx2 = 0;
2014
2015
658k
      cpu = cpu_flags_and (any, active);
2016
658k
      if (cpu_flags_all_zero (&any) || !cpu_flags_all_zero (&cpu))
2017
658k
  match |= CPU_FLAGS_ARCH_MATCH;
2018
658k
    }
2019
746k
  return match;
2020
746k
}
2021
2022
static INLINE i386_operand_type
2023
operand_type_and (i386_operand_type x, i386_operand_type y)
2024
285k
{
2025
285k
  if (x.bitfield.class != y.bitfield.class)
2026
119k
    x.bitfield.class = ClassNone;
2027
285k
  if (x.bitfield.instance != y.bitfield.instance)
2028
3.47k
    x.bitfield.instance = InstanceNone;
2029
2030
285k
  switch (ARRAY_SIZE (x.array))
2031
285k
    {
2032
0
    case 3:
2033
0
      x.array [2] &= y.array [2];
2034
      /* Fall through.  */
2035
0
    case 2:
2036
0
      x.array [1] &= y.array [1];
2037
      /* Fall through.  */
2038
285k
    case 1:
2039
285k
      x.array [0] &= y.array [0];
2040
285k
      break;
2041
0
    default:
2042
0
      abort ();
2043
285k
    }
2044
285k
  return x;
2045
285k
}
2046
2047
static INLINE i386_operand_type
2048
operand_type_and_not (i386_operand_type x, i386_operand_type y)
2049
51.0k
{
2050
51.0k
  gas_assert (y.bitfield.class == ClassNone);
2051
51.0k
  gas_assert (y.bitfield.instance == InstanceNone);
2052
2053
51.0k
  switch (ARRAY_SIZE (x.array))
2054
51.0k
    {
2055
0
    case 3:
2056
0
      x.array [2] &= ~y.array [2];
2057
      /* Fall through.  */
2058
0
    case 2:
2059
0
      x.array [1] &= ~y.array [1];
2060
      /* Fall through.  */
2061
51.0k
    case 1:
2062
51.0k
      x.array [0] &= ~y.array [0];
2063
51.0k
      break;
2064
0
    default:
2065
0
      abort ();
2066
51.0k
    }
2067
51.0k
  return x;
2068
51.0k
}
2069
2070
static INLINE i386_operand_type
2071
operand_type_or (i386_operand_type x, i386_operand_type y)
2072
156k
{
2073
156k
  gas_assert (x.bitfield.class == ClassNone ||
2074
156k
              y.bitfield.class == ClassNone ||
2075
156k
              x.bitfield.class == y.bitfield.class);
2076
156k
  gas_assert (x.bitfield.instance == InstanceNone ||
2077
156k
              y.bitfield.instance == InstanceNone ||
2078
156k
              x.bitfield.instance == y.bitfield.instance);
2079
2080
156k
  switch (ARRAY_SIZE (x.array))
2081
156k
    {
2082
0
    case 3:
2083
0
      x.array [2] |= y.array [2];
2084
      /* Fall through.  */
2085
0
    case 2:
2086
0
      x.array [1] |= y.array [1];
2087
      /* Fall through.  */
2088
156k
    case 1:
2089
156k
      x.array [0] |= y.array [0];
2090
156k
      break;
2091
0
    default:
2092
0
      abort ();
2093
156k
    }
2094
156k
  return x;
2095
156k
}
2096
2097
static INLINE i386_operand_type
2098
operand_type_xor (i386_operand_type x, i386_operand_type y)
2099
0
{
2100
0
  gas_assert (y.bitfield.class == ClassNone);
2101
0
  gas_assert (y.bitfield.instance == InstanceNone);
2102
2103
0
  switch (ARRAY_SIZE (x.array))
2104
0
    {
2105
0
    case 3:
2106
0
      x.array [2] ^= y.array [2];
2107
      /* Fall through.  */
2108
0
    case 2:
2109
0
      x.array [1] ^= y.array [1];
2110
      /* Fall through.  */
2111
0
    case 1:
2112
0
      x.array [0] ^= y.array [0];
2113
0
      break;
2114
0
    default:
2115
0
      abort ();
2116
0
    }
2117
0
  return x;
2118
0
}
2119
2120
static const i386_operand_type anydisp = {
2121
  .bitfield = { .disp8 = 1, .disp16 = 1, .disp32 = 1, .disp64 = 1 }
2122
};
2123
2124
enum operand_type
2125
{
2126
  reg,
2127
  imm,
2128
  disp,
2129
  anymem
2130
};
2131
2132
static INLINE int
2133
operand_type_check (i386_operand_type t, enum operand_type c)
2134
297k
{
2135
297k
  switch (c)
2136
297k
    {
2137
0
    case reg:
2138
0
      return t.bitfield.class == Reg;
2139
2140
98.7k
    case imm:
2141
98.7k
      return (t.bitfield.imm8
2142
98.7k
        || t.bitfield.imm8s
2143
98.7k
        || t.bitfield.imm16
2144
98.7k
        || t.bitfield.imm32
2145
98.7k
        || t.bitfield.imm32s
2146
98.7k
        || t.bitfield.imm64);
2147
2148
198k
    case disp:
2149
198k
      return (t.bitfield.disp8
2150
198k
        || t.bitfield.disp16
2151
198k
        || t.bitfield.disp32
2152
198k
        || t.bitfield.disp64);
2153
2154
0
    case anymem:
2155
0
      return (t.bitfield.disp8
2156
0
        || t.bitfield.disp16
2157
0
        || t.bitfield.disp32
2158
0
        || t.bitfield.disp64
2159
0
        || t.bitfield.baseindex);
2160
2161
0
    default:
2162
0
      abort ();
2163
297k
    }
2164
2165
0
  return 0;
2166
297k
}
2167
2168
/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size
2169
   between operand GIVEN and opeand WANTED for instruction template T.  */
2170
2171
static INLINE int
2172
match_operand_size (const insn_template *t, unsigned int wanted,
2173
        unsigned int given)
2174
156k
{
2175
156k
  return !((i.types[given].bitfield.byte
2176
156k
      && !t->operand_types[wanted].bitfield.byte)
2177
156k
     || (i.types[given].bitfield.word
2178
156k
         && !t->operand_types[wanted].bitfield.word)
2179
156k
     || (i.types[given].bitfield.dword
2180
156k
         && !t->operand_types[wanted].bitfield.dword)
2181
156k
     || (i.types[given].bitfield.qword
2182
156k
         && (!t->operand_types[wanted].bitfield.qword
2183
       /* Don't allow 64-bit (memory) operands outside of 64-bit
2184
          mode, when they're used where a 64-bit GPR could also
2185
          be used.  Checking is needed for Intel Syntax only.  */
2186
0
       || (intel_syntax
2187
0
           && flag_code != CODE_64BIT
2188
0
           && (t->operand_types[wanted].bitfield.class == Reg
2189
0
         || t->operand_types[wanted].bitfield.class == Accum
2190
0
         || t->opcode_modifier.isstring))))
2191
156k
     || (i.types[given].bitfield.tbyte
2192
156k
         && !t->operand_types[wanted].bitfield.tbyte));
2193
156k
}
2194
2195
/* Return 1 if there is no conflict in SIMD register between operand
2196
   GIVEN and opeand WANTED for instruction template T.  */
2197
2198
static INLINE int
2199
match_simd_size (const insn_template *t, unsigned int wanted,
2200
     unsigned int given)
2201
49.8k
{
2202
49.8k
  return !((i.types[given].bitfield.xmmword
2203
49.8k
      && !t->operand_types[wanted].bitfield.xmmword)
2204
49.8k
     || (i.types[given].bitfield.ymmword
2205
49.8k
         && !t->operand_types[wanted].bitfield.ymmword)
2206
49.8k
     || (i.types[given].bitfield.zmmword
2207
49.8k
         && !t->operand_types[wanted].bitfield.zmmword)
2208
49.8k
     || (i.types[given].bitfield.tmmword
2209
49.8k
         && !t->operand_types[wanted].bitfield.tmmword));
2210
49.8k
}
2211
2212
/* Return 1 if there is no conflict in any size between operand GIVEN
2213
   and opeand WANTED for instruction template T.  */
2214
2215
static INLINE int
2216
match_mem_size (const insn_template *t, unsigned int wanted,
2217
    unsigned int given)
2218
72.6k
{
2219
72.6k
  return (match_operand_size (t, wanted, given)
2220
72.6k
    && !((i.types[given].bitfield.unspecified
2221
72.6k
    && !i.broadcast.type
2222
72.6k
    && !i.broadcast.bytes
2223
72.6k
    && !t->operand_types[wanted].bitfield.unspecified)
2224
72.6k
         || (i.types[given].bitfield.fword
2225
41.9k
       && !t->operand_types[wanted].bitfield.fword)
2226
         /* For scalar opcode templates to allow register and memory
2227
      operands at the same time, some special casing is needed
2228
      here.  Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
2229
      down-conversion vpmov*.  */
2230
72.6k
         || ((t->operand_types[wanted].bitfield.class == RegSIMD
2231
41.9k
        && t->operand_types[wanted].bitfield.byte
2232
0
           + t->operand_types[wanted].bitfield.word
2233
0
           + t->operand_types[wanted].bitfield.dword
2234
0
           + t->operand_types[wanted].bitfield.qword
2235
0
           > !!t->opcode_modifier.broadcast)
2236
41.9k
       ? (i.types[given].bitfield.xmmword
2237
0
          || i.types[given].bitfield.ymmword
2238
0
          || i.types[given].bitfield.zmmword)
2239
41.9k
       : !match_simd_size(t, wanted, given))));
2240
72.6k
}
2241
2242
/* Return value has MATCH_STRAIGHT set if there is no size conflict on any
2243
   operands for instruction template T, and it has MATCH_REVERSE set if there
2244
   is no size conflict on any operands for the template with operands reversed
2245
   (and the template allows for reversing in the first place).  */
2246
2247
745k
#define MATCH_STRAIGHT 1
2248
16.3k
#define MATCH_REVERSE  2
2249
2250
static INLINE unsigned int
2251
operand_size_match (const insn_template *t)
2252
706k
{
2253
706k
  unsigned int j, match = MATCH_STRAIGHT;
2254
2255
  /* Don't check non-absolute jump instructions.  */
2256
706k
  if (t->opcode_modifier.jump
2257
706k
      && t->opcode_modifier.jump != JUMP_ABSOLUTE)
2258
1.30k
    return match;
2259
2260
  /* Check memory and accumulator operand size.  */
2261
799k
  for (j = 0; j < i.operands; j++)
2262
108k
    {
2263
108k
      if (i.types[j].bitfield.class != Reg
2264
108k
    && i.types[j].bitfield.class != RegSIMD
2265
108k
    && t->opcode_modifier.operandconstraint == ANY_SIZE)
2266
410
  continue;
2267
2268
108k
      if (t->operand_types[j].bitfield.class == Reg
2269
108k
    && !match_operand_size (t, j, j))
2270
120
  {
2271
120
    match = 0;
2272
120
    break;
2273
120
  }
2274
2275
108k
      if (t->operand_types[j].bitfield.class == RegSIMD
2276
108k
    && !match_simd_size (t, j, j))
2277
0
  {
2278
0
    match = 0;
2279
0
    break;
2280
0
  }
2281
2282
108k
      if (t->operand_types[j].bitfield.instance == Accum
2283
108k
    && (!match_operand_size (t, j, j) || !match_simd_size (t, j, j)))
2284
0
  {
2285
0
    match = 0;
2286
0
    break;
2287
0
  }
2288
2289
108k
      if ((i.flags[j] & Operand_Mem) && !match_mem_size (t, j, j))
2290
13.3k
  {
2291
13.3k
    match = 0;
2292
13.3k
    break;
2293
13.3k
  }
2294
108k
    }
2295
2296
704k
  if (!t->opcode_modifier.d)
2297
687k
    return match;
2298
2299
  /* Check reverse.  */
2300
17.3k
  gas_assert (i.operands >= 2);
2301
2302
17.5k
  for (j = 0; j < i.operands; j++)
2303
17.4k
    {
2304
17.4k
      unsigned int given = i.operands - j - 1;
2305
2306
      /* For FMA4 and XOP insns VEX.W controls just the first two
2307
   register operands. And APX_F insns just swap the two source operands,
2308
   with the 3rd one being the destination.  */
2309
17.4k
      if (is_cpu (t, CpuFMA4) || is_cpu (t, CpuXOP)
2310
17.4k
    || is_cpu (t, CpuAPX_F))
2311
1.30k
  given = j < 2 ? 1 - j : j;
2312
2313
17.4k
      if (t->operand_types[j].bitfield.class == Reg
2314
17.4k
    && !match_operand_size (t, j, given))
2315
0
  return match;
2316
2317
17.4k
      if (t->operand_types[j].bitfield.class == RegSIMD
2318
17.4k
    && !match_simd_size (t, j, given))
2319
0
  return match;
2320
2321
17.4k
      if (t->operand_types[j].bitfield.instance == Accum
2322
17.4k
    && (!match_operand_size (t, j, given)
2323
45
        || !match_simd_size (t, j, given)))
2324
0
  return match;
2325
2326
17.4k
      if ((i.flags[given] & Operand_Mem) && !match_mem_size (t, j, given))
2327
17.3k
  return match;
2328
17.4k
    }
2329
2330
71
  return match | MATCH_REVERSE;
2331
17.3k
}
2332
2333
static INLINE int
2334
operand_type_match (i386_operand_type overlap,
2335
        i386_operand_type given)
2336
64.2k
{
2337
64.2k
  i386_operand_type temp = overlap;
2338
2339
64.2k
  temp.bitfield.unspecified = 0;
2340
64.2k
  temp.bitfield.byte = 0;
2341
64.2k
  temp.bitfield.word = 0;
2342
64.2k
  temp.bitfield.dword = 0;
2343
64.2k
  temp.bitfield.fword = 0;
2344
64.2k
  temp.bitfield.qword = 0;
2345
64.2k
  temp.bitfield.tbyte = 0;
2346
64.2k
  temp.bitfield.xmmword = 0;
2347
64.2k
  temp.bitfield.ymmword = 0;
2348
64.2k
  temp.bitfield.zmmword = 0;
2349
64.2k
  temp.bitfield.tmmword = 0;
2350
64.2k
  if (operand_type_all_zero (&temp))
2351
29.5k
    goto mismatch;
2352
2353
34.6k
  if (given.bitfield.baseindex == overlap.bitfield.baseindex)
2354
34.6k
    return 1;
2355
2356
29.5k
 mismatch:
2357
29.5k
  i.error = operand_type_mismatch;
2358
29.5k
  return 0;
2359
34.6k
}
2360
2361
/* If given types g0 and g1 are registers they must be of the same type
2362
   unless the expected operand type register overlap is null.
2363
   Intel syntax sized memory operands are also checked here.  */
2364
2365
static INLINE int
2366
operand_type_register_match (i386_operand_type g0,
2367
           i386_operand_type t0,
2368
           i386_operand_type g1,
2369
           i386_operand_type t1)
2370
0
{
2371
0
  if (g0.bitfield.class != Reg
2372
0
      && g0.bitfield.class != RegSIMD
2373
0
      && (g0.bitfield.unspecified
2374
0
    || !operand_type_check (g0, anymem)))
2375
0
    return 1;
2376
2377
0
  if (g1.bitfield.class != Reg
2378
0
      && g1.bitfield.class != RegSIMD
2379
0
      && (g1.bitfield.unspecified
2380
0
    || !operand_type_check (g1, anymem)))
2381
0
    return 1;
2382
2383
0
  if (g0.bitfield.byte == g1.bitfield.byte
2384
0
      && g0.bitfield.word == g1.bitfield.word
2385
0
      && g0.bitfield.dword == g1.bitfield.dword
2386
0
      && g0.bitfield.qword == g1.bitfield.qword
2387
0
      && g0.bitfield.xmmword == g1.bitfield.xmmword
2388
0
      && g0.bitfield.ymmword == g1.bitfield.ymmword
2389
0
      && g0.bitfield.zmmword == g1.bitfield.zmmword)
2390
0
    return 1;
2391
2392
  /* If expectations overlap in no more than a single size, all is fine. */
2393
0
  g0 = operand_type_and (t0, t1);
2394
0
  if (g0.bitfield.byte
2395
0
      + g0.bitfield.word
2396
0
      + g0.bitfield.dword
2397
0
      + g0.bitfield.qword
2398
0
      + g0.bitfield.xmmword
2399
0
      + g0.bitfield.ymmword
2400
0
      + g0.bitfield.zmmword <= 1)
2401
0
    return 1;
2402
2403
0
  i.error = register_type_mismatch;
2404
2405
0
  return 0;
2406
0
}
2407
2408
static INLINE unsigned int
2409
register_number (const reg_entry *r)
2410
0
{
2411
0
  unsigned int nr = r->reg_num;
2412
2413
0
  if (r->reg_flags & RegRex)
2414
0
    nr += 8;
2415
2416
0
  if (r->reg_flags & (RegVRex | RegRex2))
2417
0
    nr += 16;
2418
2419
0
  return nr;
2420
0
}
2421
2422
static INLINE unsigned int
2423
mode_from_disp_size (i386_operand_type t)
2424
0
{
2425
0
  if (t.bitfield.disp8)
2426
0
    return 1;
2427
0
  else if (t.bitfield.disp16
2428
0
     || t.bitfield.disp32)
2429
0
    return 2;
2430
0
  else
2431
0
    return 0;
2432
0
}
2433
2434
static INLINE int
2435
fits_in_signed_byte (addressT num)
2436
42.6k
{
2437
42.6k
  return num + 0x80 <= 0xff;
2438
42.6k
}
2439
2440
static INLINE int
2441
fits_in_unsigned_byte (addressT num)
2442
23.2k
{
2443
23.2k
  return num <= 0xff;
2444
23.2k
}
2445
2446
static INLINE int
2447
fits_in_unsigned_word (addressT num)
2448
19.5k
{
2449
19.5k
  return num <= 0xffff;
2450
19.5k
}
2451
2452
static INLINE int
2453
fits_in_signed_word (addressT num)
2454
7.37k
{
2455
7.37k
  return num + 0x8000 <= 0xffff;
2456
7.37k
}
2457
2458
static INLINE int
2459
fits_in_signed_long (addressT num ATTRIBUTE_UNUSED)
2460
14.4k
{
2461
#ifndef BFD64
2462
  return 1;
2463
#else
2464
14.4k
  return num + 0x80000000 <= 0xffffffff;
2465
14.4k
#endif
2466
14.4k
}        /* fits_in_signed_long() */
2467
2468
static INLINE int
2469
fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED)
2470
557k
{
2471
#ifndef BFD64
2472
  return 1;
2473
#else
2474
557k
  return num <= 0xffffffff;
2475
557k
#endif
2476
557k
}        /* fits_in_unsigned_long() */
2477
2478
static INLINE valueT extend_to_32bit_address (addressT num)
2479
0
{
2480
0
#ifdef BFD64
2481
0
  if (fits_in_unsigned_long(num))
2482
0
    return (num ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
2483
2484
0
  if (!fits_in_signed_long (num))
2485
0
    return num & 0xffffffff;
2486
0
#endif
2487
2488
0
  return num;
2489
0
}
2490
2491
static INLINE int
2492
fits_in_disp8 (offsetT num)
2493
19.3k
{
2494
19.3k
  int shift = i.memshift;
2495
19.3k
  unsigned int mask;
2496
2497
19.3k
  if (shift == -1)
2498
0
    abort ();
2499
2500
19.3k
  mask = (1 << shift) - 1;
2501
2502
  /* Return 0 if NUM isn't properly aligned.  */
2503
19.3k
  if ((num & mask))
2504
0
    return 0;
2505
2506
  /* Check if NUM will fit in 8bit after shift.  */
2507
19.3k
  return fits_in_signed_byte (num >> shift);
2508
19.3k
}
2509
2510
static INLINE int
2511
fits_in_imm4 (offsetT num)
2512
0
{
2513
  /* Despite the name, check for imm3 if we're dealing with EVEX.  */
2514
0
  return (num & (i.encoding != encoding_evex
2515
0
     && i.encoding != encoding_egpr ? 0xf : 7)) == num;
2516
0
}
2517
2518
static i386_operand_type
2519
smallest_imm_type (offsetT num)
2520
23.5k
{
2521
23.5k
  i386_operand_type t;
2522
2523
23.5k
  operand_type_set (&t, 0);
2524
23.5k
  t.bitfield.imm64 = 1;
2525
2526
23.5k
  if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
2527
300
    {
2528
      /* This code is disabled on the 486 because all the Imm1 forms
2529
   in the opcode table are slower on the i486.  They're the
2530
   versions with the implicitly specified single-position
2531
   displacement, which has another syntax if you really want to
2532
   use that form.  */
2533
300
      t.bitfield.imm1 = 1;
2534
300
      t.bitfield.imm8 = 1;
2535
300
      t.bitfield.imm8s = 1;
2536
300
      t.bitfield.imm16 = 1;
2537
300
      t.bitfield.imm32 = 1;
2538
300
      t.bitfield.imm32s = 1;
2539
300
    }
2540
23.2k
  else if (fits_in_signed_byte (num))
2541
15.7k
    {
2542
15.7k
      if (fits_in_unsigned_byte (num))
2543
13.7k
  t.bitfield.imm8 = 1;
2544
15.7k
      t.bitfield.imm8s = 1;
2545
15.7k
      t.bitfield.imm16 = 1;
2546
15.7k
      if (flag_code != CODE_64BIT || fits_in_unsigned_long (num))
2547
15.6k
  t.bitfield.imm32 = 1;
2548
15.7k
      t.bitfield.imm32s = 1;
2549
15.7k
    }
2550
7.45k
  else if (fits_in_unsigned_byte (num))
2551
81
    {
2552
81
      t.bitfield.imm8 = 1;
2553
81
      t.bitfield.imm16 = 1;
2554
81
      t.bitfield.imm32 = 1;
2555
81
      t.bitfield.imm32s = 1;
2556
81
    }
2557
7.37k
  else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
2558
3.59k
    {
2559
3.59k
      t.bitfield.imm16 = 1;
2560
3.59k
      if (flag_code != CODE_64BIT || fits_in_unsigned_long (num))
2561
3.52k
  t.bitfield.imm32 = 1;
2562
3.59k
      t.bitfield.imm32s = 1;
2563
3.59k
    }
2564
3.77k
  else if (fits_in_signed_long (num))
2565
2.17k
    {
2566
2.17k
      if (flag_code != CODE_64BIT || fits_in_unsigned_long (num))
2567
2.10k
  t.bitfield.imm32 = 1;
2568
2.17k
      t.bitfield.imm32s = 1;
2569
2.17k
    }
2570
1.60k
  else if (fits_in_unsigned_long (num))
2571
0
    t.bitfield.imm32 = 1;
2572
2573
23.5k
  return t;
2574
23.5k
}
2575
2576
static offsetT
2577
offset_in_range (offsetT val, int size)
2578
21.4k
{
2579
21.4k
  addressT mask;
2580
2581
21.4k
  switch (size)
2582
21.4k
    {
2583
8.89k
    case 1: mask = ((addressT) 1 <<  8) - 1; break;
2584
6.56k
    case 2: mask = ((addressT) 1 << 16) - 1; break;
2585
0
#ifdef BFD64
2586
5.99k
    case 4: mask = ((addressT) 1 << 32) - 1; break;
2587
0
#endif
2588
0
    case sizeof (val): return val;
2589
0
    default: abort ();
2590
21.4k
    }
2591
2592
21.4k
  if ((val & ~mask) != 0 && (-val & ~mask) != 0)
2593
1.30k
    as_warn (_("0x%" PRIx64 " shortened to 0x%" PRIx64),
2594
1.30k
       (uint64_t) val, (uint64_t) (val & mask));
2595
2596
21.4k
  return val & mask;
2597
21.4k
}
2598
2599
static INLINE const char *insn_name (const insn_template *t)
2600
1.79M
{
2601
1.79M
  return &i386_mnemonics[t->mnem_off];
2602
1.79M
}
2603
2604
enum PREFIX_GROUP
2605
{
2606
  PREFIX_EXIST = 0,
2607
  PREFIX_LOCK,
2608
  PREFIX_REP,
2609
  PREFIX_DS,
2610
  PREFIX_OTHER
2611
};
2612
2613
/* Returns
2614
   a. PREFIX_EXIST if attempting to add a prefix where one from the
2615
   same class already exists.
2616
   b. PREFIX_LOCK if lock prefix is added.
2617
   c. PREFIX_REP if rep/repne prefix is added.
2618
   d. PREFIX_DS if ds prefix is added.
2619
   e. PREFIX_OTHER if other prefix is added.
2620
 */
2621
2622
static enum PREFIX_GROUP
2623
add_prefix (unsigned int prefix)
2624
5.33k
{
2625
5.33k
  enum PREFIX_GROUP ret = PREFIX_OTHER;
2626
5.33k
  unsigned int q;
2627
2628
5.33k
  if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
2629
5.33k
      && flag_code == CODE_64BIT)
2630
3.02k
    {
2631
3.02k
      if ((i.prefix[REX_PREFIX] & prefix & REX_W)
2632
3.02k
    || (i.prefix[REX_PREFIX] & prefix & REX_R)
2633
3.02k
    || (i.prefix[REX_PREFIX] & prefix & REX_X)
2634
3.02k
    || (i.prefix[REX_PREFIX] & prefix & REX_B))
2635
0
  ret = PREFIX_EXIST;
2636
3.02k
      q = REX_PREFIX;
2637
3.02k
    }
2638
2.31k
  else
2639
2.31k
    {
2640
2.31k
      switch (prefix)
2641
2.31k
  {
2642
0
  default:
2643
0
    abort ();
2644
2645
55
  case DS_PREFIX_OPCODE:
2646
55
    ret = PREFIX_DS;
2647
    /* Fall through.  */
2648
266
  case CS_PREFIX_OPCODE:
2649
272
  case ES_PREFIX_OPCODE:
2650
1.00k
  case FS_PREFIX_OPCODE:
2651
1.00k
  case GS_PREFIX_OPCODE:
2652
1.74k
  case SS_PREFIX_OPCODE:
2653
1.74k
    q = SEG_PREFIX;
2654
1.74k
    break;
2655
2656
13
  case REPNE_PREFIX_OPCODE:
2657
47
  case REPE_PREFIX_OPCODE:
2658
47
    q = REP_PREFIX;
2659
47
    ret = PREFIX_REP;
2660
47
    break;
2661
2662
0
  case LOCK_PREFIX_OPCODE:
2663
0
    q = LOCK_PREFIX;
2664
0
    ret = PREFIX_LOCK;
2665
0
    break;
2666
2667
36
  case FWAIT_OPCODE:
2668
36
    q = WAIT_PREFIX;
2669
36
    break;
2670
2671
29
  case ADDR_PREFIX_OPCODE:
2672
29
    q = ADDR_PREFIX;
2673
29
    break;
2674
2675
458
  case DATA_PREFIX_OPCODE:
2676
458
    q = DATA_PREFIX;
2677
458
    break;
2678
2.31k
  }
2679
2.31k
      if (i.prefix[q] != 0)
2680
324
  ret = PREFIX_EXIST;
2681
2.31k
    }
2682
2683
5.33k
  if (ret)
2684
5.01k
    {
2685
5.01k
      if (!i.prefix[q])
2686
5.01k
  ++i.prefixes;
2687
5.01k
      i.prefix[q] |= prefix;
2688
5.01k
    }
2689
324
  else
2690
324
    as_bad (_("same type of prefix used twice"));
2691
2692
5.33k
  return ret;
2693
5.33k
}
2694
2695
static void
2696
update_code_flag (int value, int check)
2697
4.72k
{
2698
4.72k
  PRINTF_LIKE ((*as_error)) = check ? as_fatal : as_bad;
2699
2700
4.72k
  if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpu64 )
2701
0
    {
2702
0
      as_error (_("64bit mode not supported on `%s'."),
2703
0
    cpu_arch_name ? cpu_arch_name : default_arch);
2704
0
      return;
2705
0
    }
2706
2707
4.72k
  if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
2708
0
    {
2709
0
      as_error (_("32bit mode not supported on `%s'."),
2710
0
    cpu_arch_name ? cpu_arch_name : default_arch);
2711
0
      return;
2712
0
    }
2713
2714
4.72k
  flag_code = (enum flag_code) value;
2715
2716
4.72k
  stackop_size = '\0';
2717
4.72k
}
2718
2719
static void
2720
set_code_flag (int value)
2721
3.98k
{
2722
3.98k
  update_code_flag (value, 0);
2723
3.98k
}
2724
2725
static void
2726
set_16bit_gcc_code_flag (int new_code_flag)
2727
0
{
2728
0
  flag_code = (enum flag_code) new_code_flag;
2729
0
  if (flag_code != CODE_16BIT)
2730
0
    abort ();
2731
0
  stackop_size = LONG_MNEM_SUFFIX;
2732
0
}
2733
2734
static void
2735
_set_intel_syntax (int syntax_flag)
2736
0
{
2737
0
  intel_syntax = syntax_flag;
2738
2739
0
  expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
2740
2741
0
  register_prefix = allow_naked_reg ? "" : "%";
2742
0
}
2743
2744
static void
2745
set_intel_syntax (int syntax_flag)
2746
0
{
2747
  /* Find out if register prefixing is specified.  */
2748
0
  int ask_naked_reg = 0;
2749
2750
0
  SKIP_WHITESPACE ();
2751
0
  if (!is_end_of_line[(unsigned char) *input_line_pointer])
2752
0
    {
2753
0
      char *string;
2754
0
      int e = get_symbol_name (&string);
2755
2756
0
      if (strcmp (string, "prefix") == 0)
2757
0
  ask_naked_reg = 1;
2758
0
      else if (strcmp (string, "noprefix") == 0)
2759
0
  ask_naked_reg = -1;
2760
0
      else
2761
0
  as_bad (_("bad argument to syntax directive."));
2762
0
      (void) restore_line_pointer (e);
2763
0
    }
2764
0
  demand_empty_rest_of_line ();
2765
2766
0
  if (ask_naked_reg == 0)
2767
0
    allow_naked_reg = (syntax_flag
2768
0
           && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
2769
0
  else
2770
0
    allow_naked_reg = (ask_naked_reg < 0);
2771
2772
0
  _set_intel_syntax (syntax_flag);
2773
0
}
2774
2775
static void
2776
set_intel_mnemonic (int mnemonic_flag)
2777
0
{
2778
0
  intel_mnemonic = mnemonic_flag;
2779
0
}
2780
2781
static void
2782
set_allow_index_reg (int flag)
2783
0
{
2784
0
  allow_index_reg = flag;
2785
0
}
2786
2787
static void
2788
set_check (int what)
2789
0
{
2790
0
  enum check_kind *kind;
2791
0
  const char *str;
2792
2793
0
  if (what)
2794
0
    {
2795
0
      kind = &operand_check;
2796
0
      str = "operand";
2797
0
    }
2798
0
  else
2799
0
    {
2800
0
      kind = &sse_check;
2801
0
      str = "sse";
2802
0
    }
2803
2804
0
  SKIP_WHITESPACE ();
2805
2806
0
  if (!is_end_of_line[(unsigned char) *input_line_pointer])
2807
0
    {
2808
0
      char *string;
2809
0
      int e = get_symbol_name (&string);
2810
2811
0
      if (strcmp (string, "none") == 0)
2812
0
  *kind = check_none;
2813
0
      else if (strcmp (string, "warning") == 0)
2814
0
  *kind = check_warning;
2815
0
      else if (strcmp (string, "error") == 0)
2816
0
  *kind = check_error;
2817
0
      else
2818
0
  as_bad (_("bad argument to %s_check directive."), str);
2819
0
      (void) restore_line_pointer (e);
2820
0
    }
2821
0
  else
2822
0
    as_bad (_("missing argument for %s_check directive"), str);
2823
2824
0
  demand_empty_rest_of_line ();
2825
0
}
2826
2827
static void
2828
check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
2829
         i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
2830
110
{
2831
110
#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2832
110
  static const char *arch;
2833
2834
  /* Intel MCU is only supported on ELF.  */
2835
110
  if (!IS_ELF)
2836
0
    return;
2837
2838
110
  if (!arch)
2839
1
    {
2840
      /* Use cpu_arch_name if it is set in md_parse_option.  Otherwise
2841
   use default_arch.  */
2842
1
      arch = cpu_arch_name;
2843
1
      if (!arch)
2844
1
  arch = default_arch;
2845
1
    }
2846
2847
  /* If we are targeting Intel MCU, we must enable it.  */
2848
110
  if ((get_elf_backend_data (stdoutput)->elf_machine_code == EM_IAMCU)
2849
110
      == new_flag.bitfield.cpuiamcu)
2850
110
    return;
2851
2852
0
  as_bad (_("`%s' is not supported on `%s'"), name, arch);
2853
0
#endif
2854
0
}
2855
2856
static void
2857
extend_cpu_sub_arch_name (const char *pfx, const char *name)
2858
8
{
2859
8
  if (cpu_sub_arch_name)
2860
0
    cpu_sub_arch_name = reconcat (cpu_sub_arch_name, cpu_sub_arch_name,
2861
0
          pfx, name, (const char *) NULL);
2862
8
  else
2863
8
    cpu_sub_arch_name = concat (pfx, name, (const char *) NULL);
2864
8
}
2865
2866
static void isa_enable (unsigned int idx)
2867
30
{
2868
30
  i386_cpu_flags flags = cpu_flags_or (cpu_arch_flags, cpu_arch[idx].enable);
2869
2870
30
  if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2871
0
    {
2872
0
      extend_cpu_sub_arch_name (".", cpu_arch[idx].name);
2873
0
      cpu_arch_flags = flags;
2874
0
    }
2875
2876
30
  cpu_arch_isa_flags = cpu_flags_or (cpu_arch_isa_flags, cpu_arch[idx].enable);
2877
30
}
2878
2879
static void isa_disable (unsigned int idx)
2880
31
{
2881
31
  i386_cpu_flags flags
2882
31
    = cpu_flags_and_not (cpu_arch_flags, cpu_arch[idx].disable);
2883
2884
31
  if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2885
8
    {
2886
8
      extend_cpu_sub_arch_name (".no", cpu_arch[idx].name);
2887
8
      cpu_arch_flags = flags;
2888
8
    }
2889
2890
31
  cpu_arch_isa_flags
2891
31
    = cpu_flags_and_not (cpu_arch_isa_flags, cpu_arch[idx].disable);
2892
31
}
2893
2894
static void
2895
set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
2896
491
{
2897
491
  typedef struct arch_stack_entry
2898
491
  {
2899
491
    const struct arch_stack_entry *prev;
2900
491
    const char *name;
2901
491
    char *sub_name;
2902
491
    i386_cpu_flags flags;
2903
491
    i386_cpu_flags isa_flags;
2904
491
    enum processor_type isa;
2905
491
    enum flag_code flag_code;
2906
491
    unsigned int vector_size;
2907
491
    char stackop_size;
2908
491
    bool no_cond_jump_promotion;
2909
491
  } arch_stack_entry;
2910
491
  static const arch_stack_entry *arch_stack_top;
2911
491
  char *s;
2912
491
  int e;
2913
491
  const char *string;
2914
491
  unsigned int j = 0;
2915
2916
491
  SKIP_WHITESPACE ();
2917
2918
491
  if (is_end_of_line[(unsigned char) *input_line_pointer])
2919
31
    {
2920
31
      as_bad (_("missing cpu architecture"));
2921
31
      input_line_pointer++;
2922
31
      return;
2923
31
    }
2924
2925
460
  e = get_symbol_name (&s);
2926
460
  string = s;
2927
2928
460
  if (strcmp (string, "push") == 0)
2929
0
    {
2930
0
      arch_stack_entry *top = XNEW (arch_stack_entry);
2931
2932
0
      top->name = cpu_arch_name;
2933
0
      if (cpu_sub_arch_name)
2934
0
  top->sub_name = xstrdup (cpu_sub_arch_name);
2935
0
      else
2936
0
  top->sub_name = NULL;
2937
0
      top->flags = cpu_arch_flags;
2938
0
      top->isa = cpu_arch_isa;
2939
0
      top->isa_flags = cpu_arch_isa_flags;
2940
0
      top->flag_code = flag_code;
2941
0
      top->vector_size = vector_size;
2942
0
      top->stackop_size = stackop_size;
2943
0
      top->no_cond_jump_promotion = no_cond_jump_promotion;
2944
2945
0
      top->prev = arch_stack_top;
2946
0
      arch_stack_top = top;
2947
2948
0
      (void) restore_line_pointer (e);
2949
0
      demand_empty_rest_of_line ();
2950
0
      return;
2951
0
    }
2952
2953
460
  if (strcmp (string, "pop") == 0)
2954
0
    {
2955
0
      const arch_stack_entry *top = arch_stack_top;
2956
2957
0
      if (!top)
2958
0
  as_bad (_(".arch stack is empty"));
2959
0
      else if (top->flag_code != flag_code
2960
0
         || top->stackop_size != stackop_size)
2961
0
  {
2962
0
    static const unsigned int bits[] = {
2963
0
      [CODE_16BIT] = 16,
2964
0
      [CODE_32BIT] = 32,
2965
0
      [CODE_64BIT] = 64,
2966
0
    };
2967
2968
0
    as_bad (_("this `.arch pop' requires `.code%u%s' to be in effect"),
2969
0
      bits[top->flag_code],
2970
0
      top->stackop_size == LONG_MNEM_SUFFIX ? "gcc" : "");
2971
0
  }
2972
0
      else
2973
0
  {
2974
0
    arch_stack_top = top->prev;
2975
2976
0
    cpu_arch_name = top->name;
2977
0
    free (cpu_sub_arch_name);
2978
0
    cpu_sub_arch_name = top->sub_name;
2979
0
    cpu_arch_flags = top->flags;
2980
0
    cpu_arch_isa = top->isa;
2981
0
    cpu_arch_isa_flags = top->isa_flags;
2982
0
    vector_size = top->vector_size;
2983
0
    no_cond_jump_promotion = top->no_cond_jump_promotion;
2984
2985
0
    XDELETE (top);
2986
0
  }
2987
2988
0
      (void) restore_line_pointer (e);
2989
0
      demand_empty_rest_of_line ();
2990
0
      return;
2991
0
    }
2992
2993
460
  if (strcmp (string, "default") == 0)
2994
0
    {
2995
0
      if (strcmp (default_arch, "iamcu") == 0)
2996
0
  string = default_arch;
2997
0
      else
2998
0
  {
2999
0
    static const i386_cpu_flags cpu_unknown_flags = CPU_UNKNOWN_FLAGS;
3000
3001
0
    cpu_arch_name = NULL;
3002
0
    free (cpu_sub_arch_name);
3003
0
    cpu_sub_arch_name = NULL;
3004
0
    cpu_arch_flags = cpu_unknown_flags;
3005
0
    cpu_arch_isa = PROCESSOR_UNKNOWN;
3006
0
    cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].enable;
3007
0
    if (!cpu_arch_tune_set)
3008
0
      cpu_arch_tune = PROCESSOR_UNKNOWN;
3009
3010
0
    vector_size = VSZ_DEFAULT;
3011
3012
0
    j = ARRAY_SIZE (cpu_arch) + 1;
3013
0
  }
3014
0
    }
3015
3016
65.1k
  for (; j < ARRAY_SIZE (cpu_arch); j++)
3017
64.7k
    {
3018
64.7k
      if (strcmp (string + (*string == '.'), cpu_arch[j].name) == 0
3019
64.7k
    && (*string == '.') == (cpu_arch[j].type == PROCESSOR_NONE))
3020
140
  {
3021
140
    if (*string != '.')
3022
110
      {
3023
110
        check_cpu_arch_compatible (string, cpu_arch[j].enable);
3024
3025
110
        if (flag_code == CODE_64BIT && !cpu_arch[j].enable.bitfield.cpu64 )
3026
0
    {
3027
0
      as_bad (_("64bit mode not supported on `%s'."),
3028
0
        cpu_arch[j].name);
3029
0
      (void) restore_line_pointer (e);
3030
0
      ignore_rest_of_line ();
3031
0
      return;
3032
0
    }
3033
3034
110
        if (flag_code == CODE_32BIT && !cpu_arch[j].enable.bitfield.cpui386)
3035
0
    {
3036
0
      as_bad (_("32bit mode not supported on `%s'."),
3037
0
        cpu_arch[j].name);
3038
0
      (void) restore_line_pointer (e);
3039
0
      ignore_rest_of_line ();
3040
0
      return;
3041
0
    }
3042
3043
110
        cpu_arch_name = cpu_arch[j].name;
3044
110
        free (cpu_sub_arch_name);
3045
110
        cpu_sub_arch_name = NULL;
3046
110
        cpu_arch_flags = cpu_arch[j].enable;
3047
110
        cpu_arch_isa = cpu_arch[j].type;
3048
110
        cpu_arch_isa_flags = cpu_arch[j].enable;
3049
110
        if (!cpu_arch_tune_set)
3050
110
    cpu_arch_tune = cpu_arch_isa;
3051
3052
110
        vector_size = VSZ_DEFAULT;
3053
3054
110
        pre_386_16bit_warned = false;
3055
110
        break;
3056
110
      }
3057
3058
30
    if (cpu_flags_all_zero (&cpu_arch[j].enable))
3059
0
      continue;
3060
3061
30
    isa_enable (j);
3062
3063
30
    (void) restore_line_pointer (e);
3064
3065
30
    switch (cpu_arch[j].vsz)
3066
30
      {
3067
24
      default:
3068
24
        break;
3069
3070
24
      case vsz_set:
3071
#ifdef SVR4_COMMENT_CHARS
3072
        if (*input_line_pointer == ':' || *input_line_pointer == '/')
3073
#else
3074
0
        if (*input_line_pointer == '/')
3075
0
#endif
3076
0
    {
3077
0
      ++input_line_pointer;
3078
0
      switch (get_absolute_expression ())
3079
0
        {
3080
0
        case 512: vector_size = VSZ512; break;
3081
0
        case 256: vector_size = VSZ256; break;
3082
0
        case 128: vector_size = VSZ128; break;
3083
0
        default:
3084
0
          as_bad (_("Unrecognized vector size specifier"));
3085
0
          ignore_rest_of_line ();
3086
0
          return;
3087
0
        }
3088
0
      break;
3089
0
    }
3090
    /* Fall through.  */
3091
6
      case vsz_reset:
3092
6
        vector_size = VSZ_DEFAULT;
3093
6
        break;
3094
30
      }
3095
3096
30
    demand_empty_rest_of_line ();
3097
30
    return;
3098
30
  }
3099
64.7k
    }
3100
3101
430
  if (startswith (string, ".no") && j >= ARRAY_SIZE (cpu_arch))
3102
48
    {
3103
      /* Disable an ISA extension.  */
3104
5.75k
      for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
3105
5.74k
  if (cpu_arch[j].type == PROCESSOR_NONE
3106
5.74k
      && strcmp (string + 3, cpu_arch[j].name) == 0)
3107
31
    {
3108
31
      isa_disable (j);
3109
3110
31
      if (cpu_arch[j].vsz == vsz_set)
3111
0
        vector_size = VSZ_DEFAULT;
3112
3113
31
      (void) restore_line_pointer (e);
3114
31
      demand_empty_rest_of_line ();
3115
31
      return;
3116
31
    }
3117
48
    }
3118
3119
399
  if (j == ARRAY_SIZE (cpu_arch))
3120
289
    as_bad (_("no such architecture: `%s'"), string);
3121
3122
399
  *input_line_pointer = e;
3123
3124
399
  no_cond_jump_promotion = 0;
3125
399
  if (*input_line_pointer == ','
3126
399
      && !is_end_of_line[(unsigned char) input_line_pointer[1]])
3127
0
    {
3128
0
      ++input_line_pointer;
3129
0
      e = get_symbol_name (&s);
3130
0
      string = s;
3131
3132
0
      if (strcmp (string, "nojumps") == 0)
3133
0
  no_cond_jump_promotion = 1;
3134
0
      else if (strcmp (string, "jumps") == 0)
3135
0
  ;
3136
0
      else
3137
0
  as_bad (_("no such architecture modifier: `%s'"), string);
3138
3139
0
      (void) restore_line_pointer (e);
3140
0
    }
3141
3142
399
  demand_empty_rest_of_line ();
3143
399
}
3144
3145
enum bfd_architecture
3146
i386_arch (void)
3147
736
{
3148
736
  if (cpu_arch_isa == PROCESSOR_IAMCU)
3149
0
    {
3150
0
      if (!IS_ELF || flag_code == CODE_64BIT)
3151
0
  as_fatal (_("Intel MCU is 32bit ELF only"));
3152
0
      return bfd_arch_iamcu;
3153
0
    }
3154
736
  else
3155
736
    return bfd_arch_i386;
3156
736
}
3157
3158
unsigned long
3159
i386_mach (void)
3160
736
{
3161
736
  if (startswith (default_arch, "x86_64"))
3162
736
    {
3163
736
      if (default_arch[6] == '\0')
3164
736
  return bfd_mach_x86_64;
3165
0
      else
3166
0
  return bfd_mach_x64_32;
3167
736
    }
3168
0
  else if (!strcmp (default_arch, "i386")
3169
0
     || !strcmp (default_arch, "iamcu"))
3170
0
    {
3171
0
      if (cpu_arch_isa == PROCESSOR_IAMCU)
3172
0
  {
3173
0
    if (!IS_ELF)
3174
0
      as_fatal (_("Intel MCU is 32bit ELF only"));
3175
0
    return bfd_mach_i386_iamcu;
3176
0
  }
3177
0
      else
3178
0
  return bfd_mach_i386_i386;
3179
0
    }
3180
0
  else
3181
0
    as_fatal (_("unknown architecture"));
3182
736
}
3183

3184
#include "opcodes/i386-tbl.h"
3185
3186
static void
3187
op_lookup (const char *mnemonic)
3188
1.35M
{
3189
1.35M
   i386_op_off_t *pos = str_hash_find (op_hash, mnemonic);
3190
3191
1.35M
   if (pos != NULL)
3192
778k
     {
3193
778k
       current_templates.start = &i386_optab[pos[0]];
3194
778k
       current_templates.end = &i386_optab[pos[1]];
3195
778k
     }
3196
573k
   else
3197
573k
     current_templates.end = current_templates.start = NULL;
3198
1.35M
}
3199
3200
void
3201
md_begin (void)
3202
736
{
3203
  /* Support pseudo prefixes like {disp32}.  */
3204
736
  lex_type ['{'] = LEX_BEGIN_NAME;
3205
3206
  /* Initialize op_hash hash table.  */
3207
736
  op_hash = str_htab_create ();
3208
3209
736
  {
3210
736
    const i386_op_off_t *cur = i386_op_sets;
3211
736
    const i386_op_off_t *end = cur + ARRAY_SIZE (i386_op_sets) - 1;
3212
3213
1.72M
    for (; cur < end; ++cur)
3214
1.72M
      if (str_hash_insert (op_hash, insn_name (&i386_optab[*cur]), cur, 0))
3215
0
  as_fatal (_("duplicate %s"), insn_name (&i386_optab[*cur]));
3216
736
  }
3217
3218
  /* Initialize reg_hash hash table.  */
3219
736
  reg_hash = str_htab_create ();
3220
736
  {
3221
736
    const reg_entry *regtab;
3222
736
    unsigned int regtab_size = i386_regtab_size;
3223
3224
259k
    for (regtab = i386_regtab; regtab_size--; regtab++)
3225
259k
      {
3226
259k
  switch (regtab->reg_type.bitfield.class)
3227
259k
    {
3228
105k
    case Reg:
3229
105k
      if (regtab->reg_type.bitfield.dword)
3230
23.5k
        {
3231
23.5k
    if (regtab->reg_type.bitfield.instance == Accum)
3232
736
      reg_eax = regtab;
3233
23.5k
        }
3234
82.4k
      else if (regtab->reg_type.bitfield.tbyte)
3235
5.88k
        {
3236
    /* There's no point inserting st(<N>) in the hash table, as
3237
       parentheses aren't included in register_chars[] anyway.  */
3238
5.88k
    if (regtab->reg_type.bitfield.instance != Accum)
3239
5.15k
      continue;
3240
736
    reg_st0 = regtab;
3241
736
        }
3242
100k
      break;
3243
3244
100k
    case SReg:
3245
5.15k
      switch (regtab->reg_num)
3246
5.15k
        {
3247
736
        case 0: reg_es = regtab; break;
3248
736
        case 2: reg_ss = regtab; break;
3249
736
        case 3: reg_ds = regtab; break;
3250
5.15k
        }
3251
5.15k
      break;
3252
3253
5.88k
    case RegMask:
3254
5.88k
      if (!regtab->reg_num)
3255
736
        reg_k0 = regtab;
3256
5.88k
      break;
3257
259k
    }
3258
3259
253k
  if (str_hash_insert (reg_hash, regtab->reg_name, regtab, 0) != NULL)
3260
0
    as_fatal (_("duplicate %s"), regtab->reg_name);
3261
253k
      }
3262
736
  }
3263
3264
  /* Fill in lexical tables:  mnemonic_chars, operand_chars.  */
3265
736
  {
3266
736
    int c;
3267
736
    const char *p;
3268
3269
189k
    for (c = 0; c < 256; c++)
3270
188k
      {
3271
188k
  if (ISDIGIT (c) || ISLOWER (c))
3272
26.4k
    {
3273
26.4k
      mnemonic_chars[c] = c;
3274
26.4k
      register_chars[c] = c;
3275
26.4k
      operand_chars[c] = c;
3276
26.4k
    }
3277
161k
  else if (ISUPPER (c))
3278
19.1k
    {
3279
19.1k
      mnemonic_chars[c] = TOLOWER (c);
3280
19.1k
      register_chars[c] = mnemonic_chars[c];
3281
19.1k
      operand_chars[c] = c;
3282
19.1k
    }
3283
#ifdef SVR4_COMMENT_CHARS
3284
  else if (c == '\\' && strchr (i386_comment_chars, '/'))
3285
    operand_chars[c] = c;
3286
#endif
3287
3288
188k
  if (c >= 128)
3289
94.2k
    operand_chars[c] = c;
3290
188k
      }
3291
3292
736
    mnemonic_chars['_'] = '_';
3293
736
    mnemonic_chars['-'] = '-';
3294
736
    mnemonic_chars['.'] = '.';
3295
3296
5.88k
    for (p = extra_symbol_chars; *p != '\0'; p++)
3297
5.15k
      operand_chars[(unsigned char) *p] = *p;
3298
13.9k
    for (p = operand_special_chars; *p != '\0'; p++)
3299
13.2k
      operand_chars[(unsigned char) *p] = *p;
3300
736
  }
3301
3302
736
  if (object_64bit)
3303
736
    {
3304
#if defined (OBJ_COFF) && defined (TE_PE)
3305
      x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
3306
          ? 32 : 16);
3307
#else
3308
736
      x86_dwarf2_return_column = 16;
3309
736
#endif
3310
736
      x86_cie_data_alignment = -8;
3311
736
#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3312
736
      x86_sframe_cfa_sp_reg = REG_SP;
3313
736
      x86_sframe_cfa_fp_reg = REG_FP;
3314
736
#endif
3315
736
    }
3316
0
  else
3317
0
    {
3318
0
      x86_dwarf2_return_column = 8;
3319
0
      x86_cie_data_alignment = -4;
3320
0
    }
3321
3322
  /* NB: FUSED_JCC_PADDING frag must have sufficient room so that it
3323
     can be turned into BRANCH_PREFIX frag.  */
3324
736
  if (align_branch_prefix_size > MAX_FUSED_JCC_PADDING_SIZE)
3325
0
    abort ();
3326
736
}
3327
3328
void
3329
i386_print_statistics (FILE *file)
3330
0
{
3331
0
  htab_print_statistics (file, "i386 opcode", op_hash);
3332
0
  htab_print_statistics (file, "i386 register", reg_hash);
3333
0
}
3334
3335
void
3336
i386_md_end (void)
3337
736
{
3338
736
  htab_delete (op_hash);
3339
736
  htab_delete (reg_hash);
3340
736
}
3341

3342
#ifdef DEBUG386
3343
3344
/* Debugging routines for md_assemble.  */
3345
static void pte (insn_template *);
3346
static void pt (i386_operand_type);
3347
static void pe (expressionS *);
3348
static void ps (symbolS *);
3349
3350
static void
3351
pi (const char *line, i386_insn *x)
3352
{
3353
  unsigned int j;
3354
3355
  fprintf (stdout, "%s: template ", line);
3356
  pte (&x->tm);
3357
  fprintf (stdout, "  address: base %s  index %s  scale %x\n",
3358
     x->base_reg ? x->base_reg->reg_name : "none",
3359
     x->index_reg ? x->index_reg->reg_name : "none",
3360
     x->log2_scale_factor);
3361
  fprintf (stdout, "  modrm:  mode %x  reg %x  reg/mem %x\n",
3362
     x->rm.mode, x->rm.reg, x->rm.regmem);
3363
  fprintf (stdout, "  sib:  base %x  index %x  scale %x\n",
3364
     x->sib.base, x->sib.index, x->sib.scale);
3365
  fprintf (stdout, "  rex: 64bit %x  extX %x  extY %x  extZ %x\n",
3366
     (x->rex & REX_W) != 0,
3367
     (x->rex & REX_R) != 0,
3368
     (x->rex & REX_X) != 0,
3369
     (x->rex & REX_B) != 0);
3370
  for (j = 0; j < x->operands; j++)
3371
    {
3372
      fprintf (stdout, "    #%d:  ", j + 1);
3373
      pt (x->types[j]);
3374
      fprintf (stdout, "\n");
3375
      if (x->types[j].bitfield.class == Reg
3376
    || x->types[j].bitfield.class == RegMMX
3377
    || x->types[j].bitfield.class == RegSIMD
3378
    || x->types[j].bitfield.class == RegMask
3379
    || x->types[j].bitfield.class == SReg
3380
    || x->types[j].bitfield.class == RegCR
3381
    || x->types[j].bitfield.class == RegDR
3382
    || x->types[j].bitfield.class == RegTR
3383
    || x->types[j].bitfield.class == RegBND)
3384
  fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
3385
      if (operand_type_check (x->types[j], imm))
3386
  pe (x->op[j].imms);
3387
      if (operand_type_check (x->types[j], disp))
3388
  pe (x->op[j].disps);
3389
    }
3390
}
3391
3392
static void
3393
pte (insn_template *t)
3394
{
3395
  static const unsigned char opc_pfx[] = { 0, 0x66, 0xf3, 0xf2 };
3396
  static const char *const opc_spc[] = {
3397
    NULL, "0f", "0f38", "0f3a", NULL, "evexmap5", "evexmap6", NULL,
3398
    "XOP08", "XOP09", "XOP0A",
3399
  };
3400
  unsigned int j;
3401
3402
  fprintf (stdout, " %d operands ", t->operands);
3403
  if (opc_pfx[t->opcode_modifier.opcodeprefix])
3404
    fprintf (stdout, "pfx %x ", opc_pfx[t->opcode_modifier.opcodeprefix]);
3405
  if (opc_spc[t->opcode_space])
3406
    fprintf (stdout, "space %s ", opc_spc[t->opcode_space]);
3407
  fprintf (stdout, "opcode %x ", t->base_opcode);
3408
  if (t->extension_opcode != None)
3409
    fprintf (stdout, "ext %x ", t->extension_opcode);
3410
  if (t->opcode_modifier.d)
3411
    fprintf (stdout, "D");
3412
  if (t->opcode_modifier.w)
3413
    fprintf (stdout, "W");
3414
  fprintf (stdout, "\n");
3415
  for (j = 0; j < t->operands; j++)
3416
    {
3417
      fprintf (stdout, "    #%d type ", j + 1);
3418
      pt (t->operand_types[j]);
3419
      fprintf (stdout, "\n");
3420
    }
3421
}
3422
3423
static void
3424
pe (expressionS *e)
3425
{
3426
  fprintf (stdout, "    operation     %d\n", e->X_op);
3427
  fprintf (stdout, "    add_number    %" PRId64 " (%" PRIx64 ")\n",
3428
     (int64_t) e->X_add_number, (uint64_t) (valueT) e->X_add_number);
3429
  if (e->X_add_symbol)
3430
    {
3431
      fprintf (stdout, "    add_symbol    ");
3432
      ps (e->X_add_symbol);
3433
      fprintf (stdout, "\n");
3434
    }
3435
  if (e->X_op_symbol)
3436
    {
3437
      fprintf (stdout, "    op_symbol    ");
3438
      ps (e->X_op_symbol);
3439
      fprintf (stdout, "\n");
3440
    }
3441
}
3442
3443
static void
3444
ps (symbolS *s)
3445
{
3446
  fprintf (stdout, "%s type %s%s",
3447
     S_GET_NAME (s),
3448
     S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
3449
     segment_name (S_GET_SEGMENT (s)));
3450
}
3451
3452
static struct type_name
3453
  {
3454
    i386_operand_type mask;
3455
    const char *name;
3456
  }
3457
const type_names[] =
3458
{
3459
  { { .bitfield = { .class = Reg, .byte = 1 } }, "r8" },
3460
  { { .bitfield = { .class = Reg, .word = 1 } }, "r16" },
3461
  { { .bitfield = { .class = Reg, .dword = 1 } }, "r32" },
3462
  { { .bitfield = { .class = Reg, .qword = 1 } }, "r64" },
3463
  { { .bitfield = { .instance = Accum, .byte = 1 } }, "acc8" },
3464
  { { .bitfield = { .instance = Accum, .word = 1 } }, "acc16" },
3465
  { { .bitfield = { .instance = Accum, .dword = 1 } }, "acc32" },
3466
  { { .bitfield = { .instance = Accum, .qword = 1 } }, "acc64" },
3467
  { { .bitfield = { .imm8 = 1 } }, "i8" },
3468
  { { .bitfield = { .imm8s = 1 } }, "i8s" },
3469
  { { .bitfield = { .imm16 = 1 } }, "i16" },
3470
  { { .bitfield = { .imm32 = 1 } }, "i32" },
3471
  { { .bitfield = { .imm32s = 1 } }, "i32s" },
3472
  { { .bitfield = { .imm64 = 1 } }, "i64" },
3473
  { { .bitfield = { .imm1 = 1 } }, "i1" },
3474
  { { .bitfield = { .baseindex = 1 } }, "BaseIndex" },
3475
  { { .bitfield = { .disp8 = 1 } }, "d8" },
3476
  { { .bitfield = { .disp16 = 1 } }, "d16" },
3477
  { { .bitfield = { .disp32 = 1 } }, "d32" },
3478
  { { .bitfield = { .disp64 = 1 } }, "d64" },
3479
  { { .bitfield = { .instance = RegD, .word = 1 } }, "InOutPortReg" },
3480
  { { .bitfield = { .instance = RegC, .byte = 1 } }, "ShiftCount" },
3481
  { { .bitfield = { .class = RegCR } }, "control reg" },
3482
  { { .bitfield = { .class = RegTR } }, "test reg" },
3483
  { { .bitfield = { .class = RegDR } }, "debug reg" },
3484
  { { .bitfield = { .class = Reg, .tbyte = 1 } }, "FReg" },
3485
  { { .bitfield = { .instance = Accum, .tbyte = 1 } }, "FAcc" },
3486
  { { .bitfield = { .class = SReg } }, "SReg" },
3487
  { { .bitfield = { .class = RegMMX } }, "rMMX" },
3488
  { { .bitfield = { .class = RegSIMD, .xmmword = 1 } }, "rXMM" },
3489
  { { .bitfield = { .class = RegSIMD, .ymmword = 1 } }, "rYMM" },
3490
  { { .bitfield = { .class = RegSIMD, .zmmword = 1 } }, "rZMM" },
3491
  { { .bitfield = { .class = RegSIMD, .tmmword = 1 } }, "rTMM" },
3492
  { { .bitfield = { .class = RegMask } }, "Mask reg" },
3493
};
3494
3495
static void
3496
pt (i386_operand_type t)
3497
{
3498
  unsigned int j;
3499
  i386_operand_type a;
3500
3501
  for (j = 0; j < ARRAY_SIZE (type_names); j++)
3502
    {
3503
      a = operand_type_and (t, type_names[j].mask);
3504
      if (operand_type_equal (&a, &type_names[j].mask))
3505
  fprintf (stdout, "%s, ",  type_names[j].name);
3506
    }
3507
  fflush (stdout);
3508
}
3509
3510
#endif /* DEBUG386 */
3511

3512
static bfd_reloc_code_real_type
3513
reloc (unsigned int size,
3514
       int pcrel,
3515
       int sign,
3516
       bfd_reloc_code_real_type other)
3517
154k
{
3518
154k
  if (other != NO_RELOC)
3519
1.89k
    {
3520
1.89k
      reloc_howto_type *rel;
3521
3522
1.89k
      if (size == 8)
3523
0
  switch (other)
3524
0
    {
3525
0
    case BFD_RELOC_X86_64_GOT32:
3526
0
      return BFD_RELOC_X86_64_GOT64;
3527
0
      break;
3528
0
    case BFD_RELOC_X86_64_GOTPLT64:
3529
0
      return BFD_RELOC_X86_64_GOTPLT64;
3530
0
      break;
3531
0
    case BFD_RELOC_X86_64_PLTOFF64:
3532
0
      return BFD_RELOC_X86_64_PLTOFF64;
3533
0
      break;
3534
0
    case BFD_RELOC_X86_64_GOTPC32:
3535
0
      other = BFD_RELOC_X86_64_GOTPC64;
3536
0
      break;
3537
0
    case BFD_RELOC_X86_64_GOTPCREL:
3538
0
      other = BFD_RELOC_X86_64_GOTPCREL64;
3539
0
      break;
3540
0
    case BFD_RELOC_X86_64_TPOFF32:
3541
0
      other = BFD_RELOC_X86_64_TPOFF64;
3542
0
      break;
3543
0
    case BFD_RELOC_X86_64_DTPOFF32:
3544
0
      other = BFD_RELOC_X86_64_DTPOFF64;
3545
0
      break;
3546
0
    default:
3547
0
      break;
3548
0
    }
3549
3550
1.89k
#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3551
1.89k
      if (other == BFD_RELOC_SIZE32)
3552
155
  {
3553
155
    if (size == 8)
3554
0
      other = BFD_RELOC_SIZE64;
3555
155
    if (pcrel)
3556
0
      {
3557
0
        as_bad (_("there are no pc-relative size relocations"));
3558
0
        return NO_RELOC;
3559
0
      }
3560
155
  }
3561
1.89k
#endif
3562
3563
      /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless.  */
3564
1.89k
      if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
3565
1.50k
  sign = -1;
3566
3567
1.89k
      rel = bfd_reloc_type_lookup (stdoutput, other);
3568
1.89k
      if (!rel)
3569
0
  as_bad (_("unknown relocation (%u)"), other);
3570
1.89k
      else if (size != bfd_get_reloc_size (rel))
3571
468
  as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3572
468
    bfd_get_reloc_size (rel),
3573
468
    size);
3574
1.42k
      else if (pcrel && !rel->pc_relative)
3575
0
  as_bad (_("non-pc-relative relocation for pc-relative field"));
3576
1.42k
      else if ((rel->complain_on_overflow == complain_overflow_signed
3577
1.42k
    && !sign)
3578
1.42k
         || (rel->complain_on_overflow == complain_overflow_unsigned
3579
1.39k
       && sign > 0))
3580
37
  as_bad (_("relocated field and relocation type differ in signedness"));
3581
1.39k
      else
3582
1.39k
  return other;
3583
505
      return NO_RELOC;
3584
1.89k
    }
3585
3586
152k
  if (pcrel)
3587
19
    {
3588
19
      if (!sign)
3589
0
  as_bad (_("there are no unsigned pc-relative relocations"));
3590
19
      switch (size)
3591
19
  {
3592
0
  case 1: return BFD_RELOC_8_PCREL;
3593
0
  case 2: return BFD_RELOC_16_PCREL;
3594
19
  case 4: return BFD_RELOC_32_PCREL;
3595
0
  case 8: return BFD_RELOC_64_PCREL;
3596
19
  }
3597
0
      as_bad (_("cannot do %u byte pc-relative relocation"), size);
3598
0
    }
3599
152k
  else
3600
152k
    {
3601
152k
      if (sign > 0)
3602
2.11k
  switch (size)
3603
2.11k
    {
3604
2.11k
    case 4: return BFD_RELOC_X86_64_32S;
3605
2.11k
    }
3606
150k
      else
3607
150k
  switch (size)
3608
150k
    {
3609
414
    case 1: return BFD_RELOC_8;
3610
2.69k
    case 2: return BFD_RELOC_16;
3611
146k
    case 4: return BFD_RELOC_32;
3612
400
    case 8: return BFD_RELOC_64;
3613
150k
    }
3614
1
      as_bad (_("cannot do %s %u byte relocation"),
3615
1
        sign > 0 ? "signed" : "unsigned", size);
3616
1
    }
3617
3618
1
  return NO_RELOC;
3619
152k
}
3620
3621
#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3622
/* Here we decide which fixups can be adjusted to make them relative to
3623
   the beginning of the section instead of the symbol.  Basically we need
3624
   to make sure that the dynamic relocations are done correctly, so in
3625
   some cases we force the original symbol to be used.  */
3626
3627
int
3628
tc_i386_fix_adjustable (fixS *fixP)
3629
0
{
3630
0
  if (!IS_ELF)
3631
0
    return 1;
3632
3633
  /* Don't adjust pc-relative references to merge sections in 64-bit
3634
     mode.  */
3635
0
  if (use_rela_relocations
3636
0
      && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
3637
0
      && fixP->fx_pcrel)
3638
0
    return 0;
3639
3640
  /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3641
     and changed later by validate_fix.  */
3642
0
  if (GOT_symbol && fixP->fx_subsy == GOT_symbol
3643
0
      && fixP->fx_r_type == BFD_RELOC_32_PCREL)
3644
0
    return 0;
3645
3646
  /* Adjust_reloc_syms doesn't know about the GOT.  Need to keep symbol
3647
     for size relocations.  */
3648
0
  if (fixP->fx_r_type == BFD_RELOC_SIZE32
3649
0
      || fixP->fx_r_type == BFD_RELOC_SIZE64
3650
0
      || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
3651
0
      || fixP->fx_r_type == BFD_RELOC_386_GOT32
3652
0
      || fixP->fx_r_type == BFD_RELOC_386_GOT32X
3653
0
      || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
3654
0
      || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
3655
0
      || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
3656
0
      || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
3657
0
      || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
3658
0
      || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
3659
0
      || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
3660
0
      || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
3661
0
      || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
3662
0
      || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3663
0
      || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
3664
0
      || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
3665
0
      || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX
3666
0
      || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX
3667
0
      || fixP->fx_r_type == BFD_RELOC_X86_64_CODE_4_GOTPCRELX
3668
0
      || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
3669
0
      || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
3670
0
      || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
3671
0
      || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
3672
0
      || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
3673
0
      || fixP->fx_r_type == BFD_RELOC_X86_64_CODE_4_GOTTPOFF
3674
0
      || fixP->fx_r_type == BFD_RELOC_X86_64_CODE_6_GOTTPOFF
3675
0
      || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
3676
0
      || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
3677
0
      || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
3678
0
      || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
3679
0
      || fixP->fx_r_type == BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC
3680
0
      || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
3681
0
      || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3682
0
      || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3683
0
    return 0;
3684
0
  return 1;
3685
0
}
3686
#endif
3687
3688
static INLINE bool
3689
want_disp32 (const insn_template *t)
3690
32.4k
{
3691
32.4k
  return flag_code != CODE_64BIT
3692
32.4k
   || i.prefix[ADDR_PREFIX]
3693
32.4k
   || (t->mnem_off == MN_lea
3694
16.4k
       && (!i.types[1].bitfield.qword
3695
0
    || t->opcode_modifier.size == SIZE32));
3696
32.4k
}
3697
3698
static int
3699
intel_float_operand (const char *mnemonic)
3700
0
{
3701
  /* Note that the value returned is meaningful only for opcodes with (memory)
3702
     operands, hence the code here is free to improperly handle opcodes that
3703
     have no operands (for better performance and smaller code). */
3704
3705
0
  if (mnemonic[0] != 'f')
3706
0
    return 0; /* non-math */
3707
3708
0
  switch (mnemonic[1])
3709
0
    {
3710
    /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3711
       the fs segment override prefix not currently handled because no
3712
       call path can make opcodes without operands get here */
3713
0
    case 'i':
3714
0
      return 2 /* integer op */;
3715
0
    case 'l':
3716
0
      if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
3717
0
  return 3; /* fldcw/fldenv */
3718
0
      break;
3719
0
    case 'n':
3720
0
      if (mnemonic[2] != 'o' /* fnop */)
3721
0
  return 3; /* non-waiting control op */
3722
0
      break;
3723
0
    case 'r':
3724
0
      if (mnemonic[2] == 's')
3725
0
  return 3; /* frstor/frstpm */
3726
0
      break;
3727
0
    case 's':
3728
0
      if (mnemonic[2] == 'a')
3729
0
  return 3; /* fsave */
3730
0
      if (mnemonic[2] == 't')
3731
0
  {
3732
0
    switch (mnemonic[3])
3733
0
      {
3734
0
      case 'c': /* fstcw */
3735
0
      case 'd': /* fstdw */
3736
0
      case 'e': /* fstenv */
3737
0
      case 's': /* fsts[gw] */
3738
0
        return 3;
3739
0
      }
3740
0
  }
3741
0
      break;
3742
0
    case 'x':
3743
0
      if (mnemonic[2] == 'r' || mnemonic[2] == 's')
3744
0
  return 0; /* fxsave/fxrstor are not really math ops */
3745
0
      break;
3746
0
    }
3747
3748
0
  return 1;
3749
0
}
3750
3751
static INLINE void
3752
install_template (const insn_template *t)
3753
662k
{
3754
662k
  unsigned int l;
3755
3756
662k
  i.tm = *t;
3757
3758
  /* Dual VEX/EVEX templates need stripping one of the possible variants.  */
3759
662k
  if (t->opcode_modifier.vex && t->opcode_modifier.evex)
3760
0
    {
3761
0
      if ((maybe_cpu (t, CpuAVX) || maybe_cpu (t, CpuAVX2)
3762
0
     || maybe_cpu (t, CpuFMA))
3763
0
    && (maybe_cpu (t, CpuAVX512F) || maybe_cpu (t, CpuAVX512VL)))
3764
0
  {
3765
0
    if (need_evex_encoding (t))
3766
0
      {
3767
0
        i.tm.opcode_modifier.vex = 0;
3768
0
        i.tm.cpu.bitfield.cpuavx512f = i.tm.cpu_any.bitfield.cpuavx512f;
3769
0
        i.tm.cpu.bitfield.cpuavx512vl = i.tm.cpu_any.bitfield.cpuavx512vl;
3770
0
      }
3771
0
    else
3772
0
      {
3773
0
        i.tm.opcode_modifier.evex = 0;
3774
0
        if (i.tm.cpu_any.bitfield.cpuavx)
3775
0
    i.tm.cpu.bitfield.cpuavx = 1;
3776
0
        else if (!i.tm.cpu.bitfield.isa)
3777
0
    i.tm.cpu.bitfield.isa = i.tm.cpu_any.bitfield.isa;
3778
0
        else
3779
0
    gas_assert (i.tm.cpu.bitfield.isa == i.tm.cpu_any.bitfield.isa);
3780
0
      }
3781
0
  }
3782
3783
0
      if ((maybe_cpu (t, CpuCMPCCXADD) || maybe_cpu (t, CpuAMX_TILE)
3784
0
     || maybe_cpu (t, CpuAVX512F) || maybe_cpu (t, CpuAVX512DQ)
3785
0
     || maybe_cpu (t, CpuAVX512BW) || maybe_cpu (t, CpuBMI)
3786
0
     || maybe_cpu (t, CpuBMI2) || maybe_cpu (t, CpuUSER_MSR))
3787
0
    && maybe_cpu (t, CpuAPX_F))
3788
0
  {
3789
0
    if (need_evex_encoding (t))
3790
0
      i.tm.opcode_modifier.vex = 0;
3791
0
    else
3792
0
      i.tm.opcode_modifier.evex = 0;
3793
0
  }
3794
0
    }
3795
3796
  /* Note that for pseudo prefixes this produces a length of 1. But for them
3797
     the length isn't interesting at all.  */
3798
662k
  for (l = 1; l < 4; ++l)
3799
662k
    if (!(t->base_opcode >> (8 * l)))
3800
662k
      break;
3801
3802
662k
  i.opcode_length = l;
3803
662k
}
3804
3805
/* Build the VEX prefix.  */
3806
3807
static void
3808
build_vex_prefix (const insn_template *t)
3809
2
{
3810
2
  unsigned int register_specifier;
3811
2
  unsigned int vector_length;
3812
2
  unsigned int w;
3813
3814
  /* Check register specifier.  */
3815
2
  if (i.vex.register_specifier)
3816
0
    {
3817
0
      register_specifier =
3818
0
  ~register_number (i.vex.register_specifier) & 0xf;
3819
0
      gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0);
3820
0
    }
3821
2
  else
3822
2
    register_specifier = 0xf;
3823
3824
  /* Use 2-byte VEX prefix by swapping destination and source operand
3825
     if there are more than 1 register operand.  */
3826
2
  if (i.reg_operands > 1
3827
2
      && i.encoding != encoding_vex3
3828
2
      && i.dir_encoding == dir_encoding_default
3829
2
      && i.operands == i.reg_operands
3830
2
      && operand_type_equal (&i.types[0], &i.types[i.operands - 1])
3831
2
      && i.tm.opcode_space == SPACE_0F
3832
2
      && (i.tm.opcode_modifier.load || i.tm.opcode_modifier.d)
3833
2
      && i.rex == REX_B)
3834
0
    {
3835
0
      unsigned int xchg;
3836
3837
0
      swap_2_operands (0, i.operands - 1);
3838
3839
0
      gas_assert (i.rm.mode == 3);
3840
3841
0
      i.rex = REX_R;
3842
0
      xchg = i.rm.regmem;
3843
0
      i.rm.regmem = i.rm.reg;
3844
0
      i.rm.reg = xchg;
3845
3846
0
      if (i.tm.opcode_modifier.d)
3847
0
  i.tm.base_opcode ^= (i.tm.base_opcode & 0xee) != 0x6e
3848
0
          ? Opcode_ExtD : Opcode_SIMD_IntD;
3849
0
      else /* Use the next insn.  */
3850
0
  install_template (&t[1]);
3851
0
    }
3852
3853
  /* Use 2-byte VEX prefix by swapping commutative source operands if there
3854
     are no memory operands and at least 3 register ones.  */
3855
2
  if (i.reg_operands >= 3
3856
2
      && i.encoding != encoding_vex3
3857
2
      && i.reg_operands == i.operands - i.imm_operands
3858
2
      && i.tm.opcode_modifier.vex
3859
2
      && i.tm.opcode_modifier.commutative
3860
      /* .commutative aliases .staticrounding; disambiguate.  */
3861
2
      && !i.tm.opcode_modifier.sae
3862
2
      && (i.tm.opcode_modifier.sse2avx
3863
0
    || (optimize > 1 && !i.no_optimize))
3864
2
      && i.rex == REX_B
3865
2
      && i.vex.register_specifier
3866
2
      && !(i.vex.register_specifier->reg_flags & RegRex))
3867
0
    {
3868
0
      unsigned int xchg = i.operands - i.reg_operands;
3869
3870
0
      gas_assert (i.tm.opcode_space == SPACE_0F);
3871
0
      gas_assert (!i.tm.opcode_modifier.sae);
3872
0
      gas_assert (operand_type_equal (&i.types[i.operands - 2],
3873
0
                                      &i.types[i.operands - 3]));
3874
0
      gas_assert (i.rm.mode == 3);
3875
3876
0
      swap_2_operands (xchg, xchg + 1);
3877
3878
0
      i.rex = 0;
3879
0
      xchg = i.rm.regmem | 8;
3880
0
      i.rm.regmem = ~register_specifier & 0xf;
3881
0
      gas_assert (!(i.rm.regmem & 8));
3882
0
      i.vex.register_specifier += xchg - i.rm.regmem;
3883
0
      register_specifier = ~xchg & 0xf;
3884
0
    }
3885
3886
2
  if (i.tm.opcode_modifier.vex == VEXScalar)
3887
0
    vector_length = avxscalar;
3888
2
  else if (i.tm.opcode_modifier.vex == VEX256)
3889
2
    vector_length = 1;
3890
0
  else if (dot_insn () && i.tm.opcode_modifier.vex == VEX128)
3891
0
    vector_length = 0;
3892
0
  else
3893
0
    {
3894
0
      unsigned int op;
3895
3896
      /* Determine vector length from the last multi-length vector
3897
   operand.  */
3898
0
      vector_length = 0;
3899
0
      for (op = t->operands; op--;)
3900
0
  if (t->operand_types[op].bitfield.xmmword
3901
0
      && t->operand_types[op].bitfield.ymmword
3902
0
      && i.types[op].bitfield.ymmword)
3903
0
    {
3904
0
      vector_length = 1;
3905
0
      break;
3906
0
    }
3907
0
    }
3908
3909
  /* Check the REX.W bit and VEXW.  */
3910
2
  if (i.tm.opcode_modifier.vexw == VEXWIG)
3911
2
    w = (vexwig == vexw1 || (i.rex & REX_W)) ? 1 : 0;
3912
0
  else if (i.tm.opcode_modifier.vexw && !(i.rex & REX_W))
3913
0
    w = i.tm.opcode_modifier.vexw == VEXW1 ? 1 : 0;
3914
0
  else
3915
0
    w = (flag_code == CODE_64BIT ? i.rex & REX_W : vexwig == vexw1) ? 1 : 0;
3916
3917
  /* Use 2-byte VEX prefix if possible.  */
3918
2
  if (w == 0
3919
2
      && i.encoding != encoding_vex3
3920
2
      && i.tm.opcode_space == SPACE_0F
3921
2
      && (i.rex & (REX_W | REX_X | REX_B)) == 0)
3922
2
    {
3923
      /* 2-byte VEX prefix.  */
3924
2
      unsigned int r;
3925
3926
2
      i.vex.length = 2;
3927
2
      i.vex.bytes[0] = 0xc5;
3928
3929
      /* Check the REX.R bit.  */
3930
2
      r = (i.rex & REX_R) ? 0 : 1;
3931
2
      i.vex.bytes[1] = (r << 7
3932
2
      | register_specifier << 3
3933
2
      | vector_length << 2
3934
2
      | i.tm.opcode_modifier.opcodeprefix);
3935
2
    }
3936
0
  else
3937
0
    {
3938
      /* 3-byte VEX prefix.  */
3939
0
      i.vex.length = 3;
3940
3941
0
      switch (i.tm.opcode_space)
3942
0
  {
3943
0
  case SPACE_0F:
3944
0
  case SPACE_0F38:
3945
0
  case SPACE_0F3A:
3946
0
  case SPACE_VEXMAP7:
3947
0
    i.vex.bytes[0] = 0xc4;
3948
0
    break;
3949
0
  case SPACE_XOP08:
3950
0
  case SPACE_XOP09:
3951
0
  case SPACE_XOP0A:
3952
0
    i.vex.bytes[0] = 0x8f;
3953
0
    break;
3954
0
  default:
3955
0
    abort ();
3956
0
  }
3957
3958
      /* The high 3 bits of the second VEX byte are 1's compliment
3959
   of RXB bits from REX.  */
3960
0
      i.vex.bytes[1] = ((~i.rex & 7) << 5)
3961
0
           | (!dot_insn () ? i.tm.opcode_space
3962
0
               : i.insn_opcode_space);
3963
3964
0
      i.vex.bytes[2] = (w << 7
3965
0
      | register_specifier << 3
3966
0
      | vector_length << 2
3967
0
      | i.tm.opcode_modifier.opcodeprefix);
3968
0
    }
3969
2
}
3970
3971
static INLINE bool
3972
is_any_vex_encoding (const insn_template *t)
3973
2.00M
{
3974
2.00M
  return t->opcode_modifier.vex || t->opcode_modifier.evex;
3975
2.00M
}
3976
3977
/* We can use this function only when the current encoding is evex.  */
3978
static INLINE bool
3979
is_apx_evex_encoding (void)
3980
2
{
3981
2
  return i.rex2 || i.tm.opcode_space == SPACE_EVEXMAP4 || i.has_nf
3982
2
    || (i.vex.register_specifier
3983
2
  && (i.vex.register_specifier->reg_flags & RegRex2));
3984
2
}
3985
3986
static INLINE bool
3987
is_apx_rex2_encoding (void)
3988
1.32M
{
3989
1.32M
  return i.rex2 || i.rex2_encoding
3990
1.32M
  || i.tm.opcode_modifier.rex2;
3991
1.32M
}
3992
3993
static unsigned int
3994
get_broadcast_bytes (const insn_template *t, bool diag)
3995
0
{
3996
0
  unsigned int op, bytes;
3997
0
  const i386_operand_type *types;
3998
3999
0
  if (i.broadcast.type)
4000
0
    return (1 << (t->opcode_modifier.broadcast - 1)) * i.broadcast.type;
4001
4002
0
  gas_assert (intel_syntax);
4003
4004
0
  for (op = 0; op < t->operands; ++op)
4005
0
    if (t->operand_types[op].bitfield.baseindex)
4006
0
      break;
4007
4008
0
  gas_assert (op < t->operands);
4009
4010
0
  if (t->opcode_modifier.evex != EVEXDYN)
4011
0
    switch (i.broadcast.bytes)
4012
0
      {
4013
0
      case 1:
4014
0
  if (t->operand_types[op].bitfield.word)
4015
0
    return 2;
4016
      /* Fall through.  */
4017
0
      case 2:
4018
0
  if (t->operand_types[op].bitfield.dword)
4019
0
    return 4;
4020
      /* Fall through.  */
4021
0
      case 4:
4022
0
  if (t->operand_types[op].bitfield.qword)
4023
0
    return 8;
4024
      /* Fall through.  */
4025
0
      case 8:
4026
0
  if (t->operand_types[op].bitfield.xmmword)
4027
0
    return 16;
4028
0
  if (t->operand_types[op].bitfield.ymmword)
4029
0
    return 32;
4030
0
  if (t->operand_types[op].bitfield.zmmword)
4031
0
    return 64;
4032
      /* Fall through.  */
4033
0
      default:
4034
0
        abort ();
4035
0
      }
4036
4037
0
  gas_assert (op + 1 < t->operands);
4038
4039
0
  if (t->operand_types[op + 1].bitfield.xmmword
4040
0
      + t->operand_types[op + 1].bitfield.ymmword
4041
0
      + t->operand_types[op + 1].bitfield.zmmword > 1)
4042
0
    {
4043
0
      types = &i.types[op + 1];
4044
0
      diag = false;
4045
0
    }
4046
0
  else /* Ambiguous - guess with a preference to non-AVX512VL forms.  */
4047
0
    types = &t->operand_types[op];
4048
4049
0
  if (types->bitfield.zmmword)
4050
0
    bytes = 64;
4051
0
  else if (types->bitfield.ymmword)
4052
0
    bytes = 32;
4053
0
  else
4054
0
    bytes = 16;
4055
4056
0
  if (diag)
4057
0
    as_warn (_("ambiguous broadcast for `%s', using %u-bit form"),
4058
0
       insn_name (t), bytes * 8);
4059
4060
0
  return bytes;
4061
0
}
4062
4063
/* Build the EVEX prefix.  */
4064
4065
static void
4066
build_evex_prefix (void)
4067
0
{
4068
0
  unsigned int register_specifier, w;
4069
0
  rex_byte vrex_used = 0;
4070
4071
  /* Check register specifier.  */
4072
0
  if (i.vex.register_specifier)
4073
0
    {
4074
0
      gas_assert ((i.vrex & REX_X) == 0);
4075
4076
0
      register_specifier = i.vex.register_specifier->reg_num;
4077
0
      if ((i.vex.register_specifier->reg_flags & RegRex))
4078
0
  register_specifier += 8;
4079
      /* The upper 16 registers are encoded in the fourth byte of the
4080
   EVEX prefix.  */
4081
0
      if (!(i.vex.register_specifier->reg_flags & RegVRex))
4082
0
  i.vex.bytes[3] = 0x8;
4083
0
      register_specifier = ~register_specifier & 0xf;
4084
0
    }
4085
0
  else
4086
0
    {
4087
0
      register_specifier = 0xf;
4088
4089
      /* Encode upper 16 vector index register in the fourth byte of
4090
   the EVEX prefix.  */
4091
0
      if (!(i.vrex & REX_X))
4092
0
  i.vex.bytes[3] = 0x8;
4093
0
      else
4094
0
  vrex_used |= REX_X;
4095
0
    }
4096
4097
  /* 4 byte EVEX prefix.  */
4098
0
  i.vex.length = 4;
4099
0
  i.vex.bytes[0] = 0x62;
4100
4101
  /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
4102
     bits from REX.  */
4103
0
  gas_assert (i.tm.opcode_space >= SPACE_0F);
4104
0
  gas_assert (i.tm.opcode_space <= SPACE_VEXMAP7);
4105
0
  i.vex.bytes[1] = ((~i.rex & 7) << 5)
4106
0
       | (!dot_insn () ? i.tm.opcode_space
4107
0
           : i.insn_opcode_space);
4108
4109
  /* The fifth bit of the second EVEX byte is 1's compliment of the
4110
     REX_R bit in VREX.  */
4111
0
  if (!(i.vrex & REX_R))
4112
0
    i.vex.bytes[1] |= 0x10;
4113
0
  else
4114
0
    vrex_used |= REX_R;
4115
4116
0
  if ((i.reg_operands + i.imm_operands) == i.operands)
4117
0
    {
4118
      /* When all operands are registers, the REX_X bit in REX is not
4119
   used.  We reuse it to encode the upper 16 registers, which is
4120
   indicated by the REX_B bit in VREX.  The REX_X bit is encoded
4121
   as 1's compliment.  */
4122
0
      if ((i.vrex & REX_B))
4123
0
  {
4124
0
    vrex_used |= REX_B;
4125
0
    i.vex.bytes[1] &= ~0x40;
4126
0
  }
4127
0
    }
4128
4129
  /* EVEX instructions shouldn't need the REX prefix.  */
4130
0
  i.vrex &= ~vrex_used;
4131
0
  gas_assert (i.vrex == 0);
4132
4133
  /* Check the REX.W bit and VEXW.  */
4134
0
  if (i.tm.opcode_modifier.vexw == VEXWIG)
4135
0
    w = (evexwig == evexw1 || (i.rex & REX_W)) ? 1 : 0;
4136
0
  else if (i.tm.opcode_modifier.vexw && !(i.rex & REX_W))
4137
0
    w = i.tm.opcode_modifier.vexw == VEXW1 ? 1 : 0;
4138
0
  else
4139
0
    w = (flag_code == CODE_64BIT ? i.rex & REX_W : evexwig == evexw1) ? 1 : 0;
4140
4141
  /* The third byte of the EVEX prefix.  */
4142
0
  i.vex.bytes[2] = ((w << 7)
4143
0
        | (register_specifier << 3)
4144
0
        | 4 /* Encode the U bit.  */
4145
0
        | i.tm.opcode_modifier.opcodeprefix);
4146
4147
  /* The fourth byte of the EVEX prefix.  */
4148
  /* The zeroing-masking bit.  */
4149
0
  if (i.mask.reg && i.mask.zeroing)
4150
0
    i.vex.bytes[3] |= 0x80;
4151
4152
  /* Don't always set the broadcast bit if there is no RC.  */
4153
0
  if (i.rounding.type == rc_none)
4154
0
    {
4155
      /* Encode the vector length.  */
4156
0
      unsigned int vec_length;
4157
4158
0
      if (i.tm.opcode_modifier.evex == EVEXDYN)
4159
0
  {
4160
0
    unsigned int op;
4161
4162
    /* Determine vector length from the last multi-length vector
4163
       operand.  */
4164
0
    for (op = i.operands; op--;)
4165
0
      if (i.tm.operand_types[op].bitfield.xmmword
4166
0
    + i.tm.operand_types[op].bitfield.ymmword
4167
0
    + i.tm.operand_types[op].bitfield.zmmword > 1)
4168
0
        {
4169
0
    if (i.types[op].bitfield.zmmword)
4170
0
      {
4171
0
        i.tm.opcode_modifier.evex = EVEX512;
4172
0
        break;
4173
0
      }
4174
0
    else if (i.types[op].bitfield.ymmword)
4175
0
      {
4176
0
        i.tm.opcode_modifier.evex = EVEX256;
4177
0
        break;
4178
0
      }
4179
0
    else if (i.types[op].bitfield.xmmword)
4180
0
      {
4181
0
        i.tm.opcode_modifier.evex = EVEX128;
4182
0
        break;
4183
0
      }
4184
0
    else if ((i.broadcast.type || i.broadcast.bytes)
4185
0
       && op == i.broadcast.operand)
4186
0
      {
4187
0
        switch (get_broadcast_bytes (&i.tm, true))
4188
0
          {
4189
0
      case 64:
4190
0
        i.tm.opcode_modifier.evex = EVEX512;
4191
0
        break;
4192
0
      case 32:
4193
0
        i.tm.opcode_modifier.evex = EVEX256;
4194
0
        break;
4195
0
      case 16:
4196
0
        i.tm.opcode_modifier.evex = EVEX128;
4197
0
        break;
4198
0
      default:
4199
0
        abort ();
4200
0
          }
4201
0
        break;
4202
0
      }
4203
0
        }
4204
4205
0
    if (op >= MAX_OPERANDS)
4206
0
      abort ();
4207
0
  }
4208
4209
0
      switch (i.tm.opcode_modifier.evex)
4210
0
  {
4211
0
  case EVEXLIG: /* LL' is ignored */
4212
0
    vec_length = evexlig << 5;
4213
0
    break;
4214
0
  case EVEX128:
4215
0
    vec_length = 0 << 5;
4216
0
    break;
4217
0
  case EVEX256:
4218
0
    vec_length = 1 << 5;
4219
0
    break;
4220
0
  case EVEX512:
4221
0
    vec_length = 2 << 5;
4222
0
    break;
4223
0
  case EVEX_L3:
4224
0
    if (dot_insn ())
4225
0
      {
4226
0
        vec_length = 3 << 5;
4227
0
        break;
4228
0
      }
4229
    /* Fall through.  */
4230
0
  default:
4231
0
    abort ();
4232
0
    break;
4233
0
  }
4234
0
      i.vex.bytes[3] |= vec_length;
4235
      /* Encode the broadcast bit.  */
4236
0
      if (i.broadcast.type || i.broadcast.bytes)
4237
0
  i.vex.bytes[3] |= 0x10;
4238
0
    }
4239
0
  else if (i.rounding.type != saeonly)
4240
0
    i.vex.bytes[3] |= 0x10 | (i.rounding.type << 5);
4241
0
  else
4242
0
    i.vex.bytes[3] |= 0x10 | (evexrcig << 5);
4243
4244
0
  if (i.mask.reg)
4245
0
    i.vex.bytes[3] |= i.mask.reg->reg_num;
4246
0
}
4247
4248
/* Build (2 bytes) rex2 prefix.
4249
   | D5h |
4250
   | m | R4 X4 B4 | W R X B |
4251
4252
   Rex2 reuses i.vex as they both encode i.tm.opcode_space in their prefixes.
4253
 */
4254
static void
4255
build_rex2_prefix (void)
4256
0
{
4257
0
  i.vex.length = 2;
4258
0
  i.vex.bytes[0] = 0xd5;
4259
  /* For the W R X B bits, the variables of rex prefix will be reused.  */
4260
0
  i.vex.bytes[1] = ((i.tm.opcode_space << 7)
4261
0
        | (i.rex2 << 4) | i.rex);
4262
0
}
4263
4264
/* Build the EVEX prefix (4-byte) for evex insn
4265
   | 62h |
4266
   | `R`X`B`R' | B'mmm |
4267
   | W | v`v`v`v | `x' | pp |
4268
   | z| L'L | b | `v | aaa |
4269
*/
4270
static void
4271
build_apx_evex_prefix (void)
4272
0
{
4273
0
  build_evex_prefix ();
4274
0
  if (i.rex2 & REX_R)
4275
0
    i.vex.bytes[1] &= ~0x10;
4276
0
  if (i.rex2 & REX_B)
4277
0
    i.vex.bytes[1] |= 0x08;
4278
0
  if (i.rex2 & REX_X)
4279
0
    {
4280
0
      gas_assert (i.rm.mode != 3);
4281
0
      i.vex.bytes[2] &= ~0x04;
4282
0
    }
4283
0
  if (i.vex.register_specifier
4284
0
      && i.vex.register_specifier->reg_flags & RegRex2)
4285
0
    i.vex.bytes[3] &= ~0x08;
4286
4287
  /* Encode the NDD bit of the instruction promoted from the legacy
4288
     space.  */
4289
0
  if (i.vex.register_specifier && i.tm.opcode_space == SPACE_EVEXMAP4)
4290
0
    i.vex.bytes[3] |= 0x10;
4291
4292
  /* Encode the NF bit.  */
4293
0
  if (i.has_nf)
4294
0
    i.vex.bytes[3] |= 0x04;
4295
0
}
4296
4297
static void establish_rex (void)
4298
662k
{
4299
  /* Note that legacy encodings have at most 2 non-immediate operands.  */
4300
662k
  unsigned int first = i.imm_operands;
4301
662k
  unsigned int last = i.operands > first ? i.operands - first - 1 : first;
4302
4303
  /* Respect a user-specified REX prefix.  */
4304
662k
  i.rex |= i.prefix[REX_PREFIX] & REX_OPCODE;
4305
4306
  /* For 8 bit registers we need an empty rex prefix.  Also if the
4307
     instruction already has a prefix, we need to convert old
4308
     registers to new ones.  */
4309
4310
662k
  if ((i.types[first].bitfield.class == Reg && i.types[first].bitfield.byte
4311
662k
       && ((i.op[first].regs->reg_flags & RegRex64) != 0 || i.rex != 0
4312
0
     || i.rex2 != 0))
4313
662k
      || (i.types[last].bitfield.class == Reg && i.types[last].bitfield.byte
4314
662k
    && ((i.op[last].regs->reg_flags & RegRex64) != 0 || i.rex != 0
4315
0
        || i.rex2 != 0)))
4316
0
    {
4317
0
      unsigned int x;
4318
4319
0
      if (!is_apx_rex2_encoding () && !is_any_vex_encoding(&i.tm))
4320
0
  i.rex |= REX_OPCODE;
4321
0
      for (x = first; x <= last; x++)
4322
0
  {
4323
    /* Look for 8 bit operand that uses old registers.  */
4324
0
    if (i.types[x].bitfield.class == Reg && i.types[x].bitfield.byte
4325
0
        && (i.op[x].regs->reg_flags & RegRex64) == 0)
4326
0
      {
4327
0
        gas_assert (!(i.op[x].regs->reg_flags & RegRex));
4328
        /* In case it is "hi" register, give up.  */
4329
0
        if (i.op[x].regs->reg_num > 3)
4330
0
    as_bad (_("can't encode register '%s%s' in an "
4331
0
        "instruction requiring REX/REX2 prefix"),
4332
0
      register_prefix, i.op[x].regs->reg_name);
4333
4334
        /* Otherwise it is equivalent to the extended register.
4335
     Since the encoding doesn't change this is merely
4336
     cosmetic cleanup for debug output.  */
4337
0
        i.op[x].regs += 8;
4338
0
      }
4339
0
  }
4340
0
    }
4341
4342
662k
  if (i.rex == 0 && i.rex2 == 0 && (i.rex_encoding || i.rex2_encoding))
4343
0
    {
4344
      /* Check if we can add a REX_OPCODE byte.  Look for 8 bit operand
4345
   that uses legacy register.  If it is "hi" register, don't add
4346
   rex and rex2 prefix.  */
4347
0
      unsigned int x;
4348
4349
0
      for (x = first; x <= last; x++)
4350
0
  if (i.types[x].bitfield.class == Reg
4351
0
      && i.types[x].bitfield.byte
4352
0
      && (i.op[x].regs->reg_flags & RegRex64) == 0
4353
0
      && i.op[x].regs->reg_num > 3)
4354
0
    {
4355
0
      gas_assert (!(i.op[x].regs->reg_flags & RegRex));
4356
0
      i.rex_encoding = false;
4357
0
      i.rex2_encoding = false;
4358
0
      break;
4359
0
    }
4360
4361
0
      if (i.rex_encoding)
4362
0
  i.rex = REX_OPCODE;
4363
0
    }
4364
4365
662k
  if (is_apx_rex2_encoding ())
4366
0
    {
4367
0
      build_rex2_prefix ();
4368
      /* The individual REX.RXBW bits got consumed.  */
4369
0
      i.rex &= REX_OPCODE;
4370
0
    }
4371
662k
  else if (i.rex != 0)
4372
3.02k
    add_prefix (REX_OPCODE | i.rex);
4373
662k
}
4374
4375
static void
4376
process_immext (void)
4377
0
{
4378
0
  expressionS *exp;
4379
4380
  /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
4381
     which is coded in the same place as an 8-bit immediate field
4382
     would be.  Here we fake an 8-bit immediate operand from the
4383
     opcode suffix stored in tm.extension_opcode.
4384
4385
     AVX instructions also use this encoding, for some of
4386
     3 argument instructions.  */
4387
4388
0
  gas_assert (i.imm_operands <= 1
4389
0
        && (i.operands <= 2
4390
0
      || (is_any_vex_encoding (&i.tm)
4391
0
          && i.operands <= 4)));
4392
4393
0
  exp = &im_expressions[i.imm_operands++];
4394
0
  i.op[i.operands].imms = exp;
4395
0
  i.types[i.operands].bitfield.imm8 = 1;
4396
0
  i.operands++;
4397
0
  exp->X_op = O_constant;
4398
0
  exp->X_add_number = i.tm.extension_opcode;
4399
0
  i.tm.extension_opcode = None;
4400
0
}
4401
4402
4403
static int
4404
check_hle (void)
4405
0
{
4406
0
  switch (i.tm.opcode_modifier.prefixok)
4407
0
    {
4408
0
    default:
4409
0
      abort ();
4410
0
    case PrefixLock:
4411
0
    case PrefixNone:
4412
0
    case PrefixNoTrack:
4413
0
    case PrefixRep:
4414
0
      as_bad (_("invalid instruction `%s' after `%s'"),
4415
0
        insn_name (&i.tm), i.hle_prefix);
4416
0
      return 0;
4417
0
    case PrefixHLELock:
4418
0
      if (i.prefix[LOCK_PREFIX])
4419
0
  return 1;
4420
0
      as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
4421
0
      return 0;
4422
0
    case PrefixHLEAny:
4423
0
      return 1;
4424
0
    case PrefixHLERelease:
4425
0
      if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
4426
0
  {
4427
0
    as_bad (_("instruction `%s' after `xacquire' not allowed"),
4428
0
      insn_name (&i.tm));
4429
0
    return 0;
4430
0
  }
4431
0
      if (i.mem_operands == 0 || !(i.flags[i.operands - 1] & Operand_Mem))
4432
0
  {
4433
0
    as_bad (_("memory destination needed for instruction `%s'"
4434
0
        " after `xrelease'"), insn_name (&i.tm));
4435
0
    return 0;
4436
0
  }
4437
0
      return 1;
4438
0
    }
4439
0
}
4440
4441
/* Encode aligned vector move as unaligned vector move.  */
4442
4443
static void
4444
encode_with_unaligned_vector_move (void)
4445
0
{
4446
0
  switch (i.tm.base_opcode)
4447
0
    {
4448
0
    case 0x28:  /* Load instructions.  */
4449
0
    case 0x29:  /* Store instructions.  */
4450
      /* movaps/movapd/vmovaps/vmovapd.  */
4451
0
      if (i.tm.opcode_space == SPACE_0F
4452
0
    && i.tm.opcode_modifier.opcodeprefix <= PREFIX_0X66)
4453
0
  i.tm.base_opcode = 0x10 | (i.tm.base_opcode & 1);
4454
0
      break;
4455
0
    case 0x6f:  /* Load instructions.  */
4456
0
    case 0x7f:  /* Store instructions.  */
4457
      /* movdqa/vmovdqa/vmovdqa64/vmovdqa32. */
4458
0
      if (i.tm.opcode_space == SPACE_0F
4459
0
    && i.tm.opcode_modifier.opcodeprefix == PREFIX_0X66)
4460
0
  i.tm.opcode_modifier.opcodeprefix = PREFIX_0XF3;
4461
0
      break;
4462
0
    default:
4463
0
      break;
4464
0
    }
4465
0
}
4466
4467
/* Try the shortest encoding by shortening operand size.  */
4468
4469
static void
4470
optimize_encoding (void)
4471
0
{
4472
0
  unsigned int j;
4473
4474
0
  if (i.tm.mnem_off == MN_lea)
4475
0
    {
4476
      /* Optimize: -O:
4477
     lea symbol, %rN    -> mov $symbol, %rN
4478
     lea (%rM), %rN     -> mov %rM, %rN
4479
     lea (,%rM,1), %rN  -> mov %rM, %rN
4480
4481
     and in 32-bit mode for 16-bit addressing
4482
4483
     lea (%rM), %rN     -> movzx %rM, %rN
4484
4485
     and in 64-bit mode zap 32-bit addressing in favor of using a
4486
     32-bit (or less) destination.
4487
       */
4488
0
      if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX])
4489
0
  {
4490
0
    if (!i.op[1].regs->reg_type.bitfield.word)
4491
0
      i.tm.opcode_modifier.size = SIZE32;
4492
0
    i.prefix[ADDR_PREFIX] = 0;
4493
0
  }
4494
4495
0
      if (!i.index_reg && !i.base_reg)
4496
0
  {
4497
    /* Handle:
4498
         lea symbol, %rN    -> mov $symbol, %rN
4499
     */
4500
0
    if (flag_code == CODE_64BIT)
4501
0
      {
4502
        /* Don't transform a relocation to a 16-bit one.  */
4503
0
        if (i.op[0].disps
4504
0
      && i.op[0].disps->X_op != O_constant
4505
0
      && i.op[1].regs->reg_type.bitfield.word)
4506
0
    return;
4507
4508
0
        if (!i.op[1].regs->reg_type.bitfield.qword
4509
0
      || i.tm.opcode_modifier.size == SIZE32)
4510
0
    {
4511
0
      i.tm.base_opcode = 0xb8;
4512
0
      i.tm.opcode_modifier.modrm = 0;
4513
0
      if (!i.op[1].regs->reg_type.bitfield.word)
4514
0
        i.types[0].bitfield.imm32 = 1;
4515
0
      else
4516
0
        {
4517
0
          i.tm.opcode_modifier.size = SIZE16;
4518
0
          i.types[0].bitfield.imm16 = 1;
4519
0
        }
4520
0
    }
4521
0
        else
4522
0
    {
4523
      /* Subject to further optimization below.  */
4524
0
      i.tm.base_opcode = 0xc7;
4525
0
      i.tm.extension_opcode = 0;
4526
0
      i.types[0].bitfield.imm32s = 1;
4527
0
      i.types[0].bitfield.baseindex = 0;
4528
0
    }
4529
0
      }
4530
    /* Outside of 64-bit mode address and operand sizes have to match if
4531
       a relocation is involved, as otherwise we wouldn't (currently) or
4532
       even couldn't express the relocation correctly.  */
4533
0
    else if (i.op[0].disps
4534
0
       && i.op[0].disps->X_op != O_constant
4535
0
       && ((!i.prefix[ADDR_PREFIX])
4536
0
           != (flag_code == CODE_32BIT
4537
0
         ? i.op[1].regs->reg_type.bitfield.dword
4538
0
         : i.op[1].regs->reg_type.bitfield.word)))
4539
0
      return;
4540
    /* In 16-bit mode converting LEA with 16-bit addressing and a 32-bit
4541
       destination is going to grow encoding size.  */
4542
0
    else if (flag_code == CODE_16BIT
4543
0
       && (optimize <= 1 || optimize_for_space)
4544
0
       && !i.prefix[ADDR_PREFIX]
4545
0
       && i.op[1].regs->reg_type.bitfield.dword)
4546
0
      return;
4547
0
    else
4548
0
      {
4549
0
        i.tm.base_opcode = 0xb8;
4550
0
        i.tm.opcode_modifier.modrm = 0;
4551
0
        if (i.op[1].regs->reg_type.bitfield.dword)
4552
0
    i.types[0].bitfield.imm32 = 1;
4553
0
        else
4554
0
    i.types[0].bitfield.imm16 = 1;
4555
4556
0
        if (i.op[0].disps
4557
0
      && i.op[0].disps->X_op == O_constant
4558
0
      && i.op[1].regs->reg_type.bitfield.dword
4559
      /* NB: Add () to !i.prefix[ADDR_PREFIX] to silence
4560
         GCC 5. */
4561
0
      && (!i.prefix[ADDR_PREFIX]) != (flag_code == CODE_32BIT))
4562
0
    i.op[0].disps->X_add_number &= 0xffff;
4563
0
      }
4564
4565
0
    i.tm.operand_types[0] = i.types[0];
4566
0
    i.imm_operands = 1;
4567
0
    if (!i.op[0].imms)
4568
0
      {
4569
0
        i.op[0].imms = &im_expressions[0];
4570
0
        i.op[0].imms->X_op = O_absent;
4571
0
      }
4572
0
  }
4573
0
      else if (i.op[0].disps
4574
0
      && (i.op[0].disps->X_op != O_constant
4575
0
          || i.op[0].disps->X_add_number))
4576
0
  return;
4577
0
      else
4578
0
  {
4579
    /* Handle:
4580
         lea (%rM), %rN     -> mov %rM, %rN
4581
         lea (,%rM,1), %rN  -> mov %rM, %rN
4582
         lea (%rM), %rN     -> movzx %rM, %rN
4583
     */
4584
0
    const reg_entry *addr_reg;
4585
4586
0
    if (!i.index_reg && i.base_reg->reg_num != RegIP)
4587
0
      addr_reg = i.base_reg;
4588
0
    else if (!i.base_reg
4589
0
       && i.index_reg->reg_num != RegIZ
4590
0
       && !i.log2_scale_factor)
4591
0
      addr_reg = i.index_reg;
4592
0
    else
4593
0
      return;
4594
4595
0
    if (addr_reg->reg_type.bitfield.word
4596
0
        && i.op[1].regs->reg_type.bitfield.dword)
4597
0
      {
4598
0
        if (flag_code != CODE_32BIT)
4599
0
    return;
4600
0
        i.tm.opcode_space = SPACE_0F;
4601
0
        i.tm.base_opcode = 0xb7;
4602
0
      }
4603
0
    else
4604
0
      i.tm.base_opcode = 0x8b;
4605
4606
0
    if (addr_reg->reg_type.bitfield.dword
4607
0
        && i.op[1].regs->reg_type.bitfield.qword)
4608
0
      i.tm.opcode_modifier.size = SIZE32;
4609
4610
0
    i.op[0].regs = addr_reg;
4611
0
    i.reg_operands = 2;
4612
0
  }
4613
4614
0
      i.mem_operands = 0;
4615
0
      i.disp_operands = 0;
4616
0
      i.prefix[ADDR_PREFIX] = 0;
4617
0
      i.prefix[SEG_PREFIX] = 0;
4618
0
      i.seg[0] = NULL;
4619
0
    }
4620
4621
0
  if (optimize_for_space
4622
0
      && i.tm.mnem_off == MN_test
4623
0
      && i.reg_operands == 1
4624
0
      && i.imm_operands == 1
4625
0
      && !i.types[1].bitfield.byte
4626
0
      && i.op[0].imms->X_op == O_constant
4627
0
      && fits_in_imm7 (i.op[0].imms->X_add_number))
4628
0
    {
4629
      /* Optimize: -Os:
4630
     test $imm7, %r64/%r32/%r16  -> test $imm7, %r8
4631
       */
4632
0
      unsigned int base_regnum = i.op[1].regs->reg_num;
4633
0
      if (flag_code == CODE_64BIT || base_regnum < 4)
4634
0
  {
4635
0
    i.types[1].bitfield.byte = 1;
4636
    /* Ignore the suffix.  */
4637
0
    i.suffix = 0;
4638
    /* Convert to byte registers. 8-bit registers are special,
4639
       RegRex64 and non-RegRex64 each have 8 registers.  */
4640
0
    if (i.types[1].bitfield.word)
4641
      /* 32 (or 40) 8-bit registers.  */
4642
0
      j = 32;
4643
0
    else if (i.types[1].bitfield.dword)
4644
      /* 32 (or 40) 8-bit registers + 32 16-bit registers.  */
4645
0
      j = 64;
4646
0
    else
4647
      /* 32 (or 40) 8-bit registers + 32 16-bit registers
4648
         + 32 32-bit registers.  */
4649
0
      j = 96;
4650
4651
    /* In 64-bit mode, the following byte registers cannot be accessed
4652
       if using the Rex and Rex2 prefix: AH, BH, CH, DH */
4653
0
    if (!(i.op[1].regs->reg_flags & (RegRex | RegRex2)) && base_regnum < 4)
4654
0
      j += 8;
4655
0
    i.op[1].regs -= j;
4656
0
  }
4657
0
    }
4658
0
  else if (flag_code == CODE_64BIT
4659
0
     && i.tm.opcode_space == SPACE_BASE
4660
0
     && ((i.types[1].bitfield.qword
4661
0
    && i.reg_operands == 1
4662
0
    && i.imm_operands == 1
4663
0
    && i.op[0].imms->X_op == O_constant
4664
0
    && ((i.tm.base_opcode == 0xb8
4665
0
         && i.tm.extension_opcode == None
4666
0
         && fits_in_unsigned_long (i.op[0].imms->X_add_number))
4667
0
        || (fits_in_imm31 (i.op[0].imms->X_add_number)
4668
0
      && (i.tm.base_opcode == 0x24
4669
0
          || (i.tm.base_opcode == 0x80
4670
0
        && i.tm.extension_opcode == 0x4)
4671
0
          || i.tm.mnem_off == MN_test
4672
0
          || ((i.tm.base_opcode | 1) == 0xc7
4673
0
        && i.tm.extension_opcode == 0x0)))
4674
0
        || (fits_in_imm7 (i.op[0].imms->X_add_number)
4675
0
      && i.tm.base_opcode == 0x83
4676
0
      && i.tm.extension_opcode == 0x4)))
4677
0
         || (i.types[0].bitfield.qword
4678
0
       && ((i.reg_operands == 2
4679
0
      && i.op[0].regs == i.op[1].regs
4680
0
      && (i.tm.mnem_off == MN_xor
4681
0
          || i.tm.mnem_off == MN_sub))
4682
0
           || i.tm.mnem_off == MN_clr))))
4683
0
    {
4684
      /* Optimize: -O:
4685
     andq $imm31, %r64   -> andl $imm31, %r32
4686
     andq $imm7, %r64    -> andl $imm7, %r32
4687
     testq $imm31, %r64  -> testl $imm31, %r32
4688
     xorq %r64, %r64     -> xorl %r32, %r32
4689
     subq %r64, %r64     -> subl %r32, %r32
4690
     movq $imm31, %r64   -> movl $imm31, %r32
4691
     movq $imm32, %r64   -> movl $imm32, %r32
4692
        */
4693
0
      i.tm.opcode_modifier.size = SIZE32;
4694
0
      if (i.imm_operands)
4695
0
  {
4696
0
    i.types[0].bitfield.imm32 = 1;
4697
0
    i.types[0].bitfield.imm32s = 0;
4698
0
    i.types[0].bitfield.imm64 = 0;
4699
0
  }
4700
0
      else
4701
0
  {
4702
0
    i.types[0].bitfield.dword = 1;
4703
0
    i.types[0].bitfield.qword = 0;
4704
0
  }
4705
0
      i.types[1].bitfield.dword = 1;
4706
0
      i.types[1].bitfield.qword = 0;
4707
0
      if (i.tm.mnem_off == MN_mov || i.tm.mnem_off == MN_lea)
4708
0
  {
4709
    /* Handle
4710
         movq $imm31, %r64   -> movl $imm31, %r32
4711
         movq $imm32, %r64   -> movl $imm32, %r32
4712
     */
4713
0
    i.tm.operand_types[0].bitfield.imm32 = 1;
4714
0
    i.tm.operand_types[0].bitfield.imm32s = 0;
4715
0
    i.tm.operand_types[0].bitfield.imm64 = 0;
4716
0
    if ((i.tm.base_opcode | 1) == 0xc7)
4717
0
      {
4718
        /* Handle
4719
       movq $imm31, %r64   -> movl $imm31, %r32
4720
         */
4721
0
        i.tm.base_opcode = 0xb8;
4722
0
        i.tm.extension_opcode = None;
4723
0
        i.tm.opcode_modifier.w = 0;
4724
0
        i.tm.opcode_modifier.modrm = 0;
4725
0
      }
4726
0
  }
4727
0
    }
4728
0
  else if (i.reg_operands == 3
4729
0
     && i.op[0].regs == i.op[1].regs
4730
0
     && i.encoding != encoding_evex
4731
0
     && (i.tm.mnem_off == MN_xor
4732
0
         || i.tm.mnem_off == MN_sub))
4733
0
    {
4734
      /* Optimize: -O:
4735
     xorb %rNb, %rNb, %rMb  -> xorl %rMd, %rMd
4736
     xorw %rNw, %rNw, %rMw  -> xorl %rMd, %rMd
4737
     xorl %rNd, %rNd, %rMd  -> xorl %rMd, %rMd
4738
     xorq %rN,  %rN,  %rM   -> xorl %rMd, %rMd
4739
     subb %rNb, %rNb, %rMb  -> subl %rMd, %rMd
4740
     subw %rNw, %rNw, %rMw  -> subl %rMd, %rMd
4741
     subl %rNd, %rNd, %rMd  -> subl %rMd, %rMd
4742
     subq %rN,  %rN,  %rM   -> subl %rMd, %rMd
4743
        */
4744
0
      i.tm.opcode_space = SPACE_BASE;
4745
0
      i.tm.opcode_modifier.evex = 0;
4746
0
      i.tm.opcode_modifier.size = SIZE32;
4747
0
      i.types[0].bitfield.byte = 0;
4748
0
      i.types[0].bitfield.word = 0;
4749
0
      i.types[0].bitfield.dword = 1;
4750
0
      i.types[0].bitfield.qword = 0;
4751
0
      i.op[0].regs = i.op[2].regs;
4752
0
      i.types[1] = i.types[0];
4753
0
      i.op[1].regs = i.op[2].regs;
4754
0
      i.reg_operands = 2;
4755
0
    }
4756
0
  else if (optimize > 1
4757
0
     && !optimize_for_space
4758
0
     && i.reg_operands == 2
4759
0
     && i.op[0].regs == i.op[1].regs
4760
0
     && (i.tm.mnem_off == MN_and || i.tm.mnem_off == MN_or)
4761
0
     && (flag_code != CODE_64BIT || !i.types[0].bitfield.dword))
4762
0
    {
4763
      /* Optimize: -O2:
4764
     andb %rN, %rN  -> testb %rN, %rN
4765
     andw %rN, %rN  -> testw %rN, %rN
4766
     andq %rN, %rN  -> testq %rN, %rN
4767
     orb %rN, %rN   -> testb %rN, %rN
4768
     orw %rN, %rN   -> testw %rN, %rN
4769
     orq %rN, %rN   -> testq %rN, %rN
4770
4771
     and outside of 64-bit mode
4772
4773
     andl %rN, %rN  -> testl %rN, %rN
4774
     orl %rN, %rN   -> testl %rN, %rN
4775
       */
4776
0
      i.tm.base_opcode = 0x84 | (i.tm.base_opcode & 1);
4777
0
    }
4778
0
  else if (i.tm.base_opcode == 0xba
4779
0
     && i.tm.opcode_space == SPACE_0F
4780
0
     && i.reg_operands == 1
4781
0
     && i.op[0].imms->X_op == O_constant
4782
0
     && i.op[0].imms->X_add_number >= 0)
4783
0
    {
4784
      /* Optimize: -O:
4785
     btw $n, %rN -> btl $n, %rN (outside of 16-bit mode, n < 16)
4786
     btq $n, %rN -> btl $n, %rN (in 64-bit mode, n < 32, N < 8)
4787
     btl $n, %rN -> btw $n, %rN (in 16-bit mode, n < 16)
4788
4789
     With <BT> one of bts, btr, and bts also:
4790
     <BT>w $n, %rN -> btl $n, %rN (in 32-bit mode, n < 16)
4791
     <BT>l $n, %rN -> btw $n, %rN (in 16-bit mode, n < 16)
4792
       */
4793
0
      switch (flag_code)
4794
0
  {
4795
0
  case CODE_64BIT:
4796
0
    if (i.tm.extension_opcode != 4)
4797
0
      break;
4798
0
    if (i.types[1].bitfield.qword
4799
0
        && i.op[0].imms->X_add_number < 32
4800
0
        && !(i.op[1].regs->reg_flags & RegRex))
4801
0
      i.tm.opcode_modifier.size = SIZE32;
4802
    /* Fall through.  */
4803
0
  case CODE_32BIT:
4804
0
    if (i.types[1].bitfield.word
4805
0
        && i.op[0].imms->X_add_number < 16)
4806
0
      i.tm.opcode_modifier.size = SIZE32;
4807
0
    break;
4808
0
  case CODE_16BIT:
4809
0
    if (i.op[0].imms->X_add_number < 16)
4810
0
      i.tm.opcode_modifier.size = SIZE16;
4811
0
    break;
4812
0
  }
4813
0
    }
4814
0
  else if (i.reg_operands == 3
4815
0
     && i.op[0].regs == i.op[1].regs
4816
0
     && !i.types[2].bitfield.xmmword
4817
0
     && (i.tm.opcode_modifier.vex
4818
0
         || ((!i.mask.reg || i.mask.zeroing)
4819
0
       && i.tm.opcode_modifier.evex
4820
0
       && (i.encoding != encoding_evex
4821
0
           || cpu_arch_isa_flags.bitfield.cpuavx512vl
4822
0
           || is_cpu (&i.tm, CpuAVX512VL)
4823
0
           || (i.tm.operand_types[2].bitfield.zmmword
4824
0
         && i.types[2].bitfield.ymmword))))
4825
0
     && i.tm.opcode_space == SPACE_0F
4826
0
     && ((i.tm.base_opcode | 2) == 0x57
4827
0
         || i.tm.base_opcode == 0xdf
4828
0
         || i.tm.base_opcode == 0xef
4829
0
         || (i.tm.base_opcode | 3) == 0xfb
4830
0
         || i.tm.base_opcode == 0x42
4831
0
         || i.tm.base_opcode == 0x47))
4832
0
    {
4833
      /* Optimize: -O1:
4834
     VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
4835
     vpsubq and vpsubw:
4836
       EVEX VOP %zmmM, %zmmM, %zmmN
4837
         -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4838
         -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4839
       EVEX VOP %ymmM, %ymmM, %ymmN
4840
         -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4841
         -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4842
       VEX VOP %ymmM, %ymmM, %ymmN
4843
         -> VEX VOP %xmmM, %xmmM, %xmmN
4844
     VOP, one of vpandn and vpxor:
4845
       VEX VOP %ymmM, %ymmM, %ymmN
4846
         -> VEX VOP %xmmM, %xmmM, %xmmN
4847
     VOP, one of vpandnd and vpandnq:
4848
       EVEX VOP %zmmM, %zmmM, %zmmN
4849
         -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4850
         -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4851
       EVEX VOP %ymmM, %ymmM, %ymmN
4852
         -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4853
         -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4854
     VOP, one of vpxord and vpxorq:
4855
       EVEX VOP %zmmM, %zmmM, %zmmN
4856
         -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4857
         -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4858
       EVEX VOP %ymmM, %ymmM, %ymmN
4859
         -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4860
         -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4861
     VOP, one of kxord and kxorq:
4862
       VEX VOP %kM, %kM, %kN
4863
         -> VEX kxorw %kM, %kM, %kN
4864
     VOP, one of kandnd and kandnq:
4865
       VEX VOP %kM, %kM, %kN
4866
         -> VEX kandnw %kM, %kM, %kN
4867
       */
4868
0
      if (i.tm.opcode_modifier.evex)
4869
0
  {
4870
0
    if (i.encoding != encoding_evex)
4871
0
      {
4872
0
        i.tm.opcode_modifier.vex = VEX128;
4873
0
        i.tm.opcode_modifier.vexw = VEXW0;
4874
0
        i.tm.opcode_modifier.evex = 0;
4875
0
        i.encoding = encoding_vex;
4876
0
        i.mask.reg = NULL;
4877
0
      }
4878
0
    else if (optimize > 1)
4879
0
      i.tm.opcode_modifier.evex = EVEX128;
4880
0
    else
4881
0
      return;
4882
0
  }
4883
0
      else if (i.tm.operand_types[0].bitfield.class == RegMask)
4884
0
  {
4885
0
    i.tm.opcode_modifier.opcodeprefix = PREFIX_NONE;
4886
0
    i.tm.opcode_modifier.vexw = VEXW0;
4887
0
  }
4888
0
      else
4889
0
  i.tm.opcode_modifier.vex = VEX128;
4890
4891
0
      if (i.tm.opcode_modifier.vex)
4892
0
  for (j = 0; j < 3; j++)
4893
0
    {
4894
0
      i.types[j].bitfield.xmmword = 1;
4895
0
      i.types[j].bitfield.ymmword = 0;
4896
0
    }
4897
0
    }
4898
0
  else if (i.encoding != encoding_evex
4899
0
     && i.encoding != encoding_egpr
4900
0
     && !i.types[0].bitfield.zmmword
4901
0
     && !i.types[1].bitfield.zmmword
4902
0
     && !i.mask.reg
4903
0
     && !i.broadcast.type
4904
0
     && !i.broadcast.bytes
4905
0
     && i.tm.opcode_modifier.evex
4906
0
     && ((i.tm.base_opcode & ~Opcode_SIMD_IntD) == 0x6f
4907
0
         || (i.tm.base_opcode & ~4) == 0xdb
4908
0
         || (i.tm.base_opcode & ~4) == 0xeb)
4909
0
     && i.tm.extension_opcode == None)
4910
0
    {
4911
      /* Optimize: -O1:
4912
     VOP, one of vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16,
4913
     vmovdqu32 and vmovdqu64:
4914
       EVEX VOP %xmmM, %xmmN
4915
         -> VEX vmovdqa|vmovdqu %xmmM, %xmmN (M and N < 16)
4916
       EVEX VOP %ymmM, %ymmN
4917
         -> VEX vmovdqa|vmovdqu %ymmM, %ymmN (M and N < 16)
4918
       EVEX VOP %xmmM, mem
4919
         -> VEX vmovdqa|vmovdqu %xmmM, mem (M < 16)
4920
       EVEX VOP %ymmM, mem
4921
         -> VEX vmovdqa|vmovdqu %ymmM, mem (M < 16)
4922
       EVEX VOP mem, %xmmN
4923
         -> VEX mvmovdqa|vmovdquem, %xmmN (N < 16)
4924
       EVEX VOP mem, %ymmN
4925
         -> VEX vmovdqa|vmovdqu mem, %ymmN (N < 16)
4926
     VOP, one of vpand, vpandn, vpor, vpxor:
4927
       EVEX VOP{d,q} %xmmL, %xmmM, %xmmN
4928
         -> VEX VOP %xmmL, %xmmM, %xmmN (L, M, and N < 16)
4929
       EVEX VOP{d,q} %ymmL, %ymmM, %ymmN
4930
         -> VEX VOP %ymmL, %ymmM, %ymmN (L, M, and N < 16)
4931
       EVEX VOP{d,q} mem, %xmmM, %xmmN
4932
         -> VEX VOP mem, %xmmM, %xmmN (M and N < 16)
4933
       EVEX VOP{d,q} mem, %ymmM, %ymmN
4934
         -> VEX VOP mem, %ymmM, %ymmN (M and N < 16)
4935
       */
4936
0
      for (j = 0; j < i.operands; j++)
4937
0
  if (operand_type_check (i.types[j], disp)
4938
0
      && i.op[j].disps->X_op == O_constant)
4939
0
    {
4940
      /* Since the VEX prefix has 2 or 3 bytes, the EVEX prefix
4941
         has 4 bytes, EVEX Disp8 has 1 byte and VEX Disp32 has 4
4942
         bytes, we choose EVEX Disp8 over VEX Disp32.  */
4943
0
      int evex_disp8, vex_disp8;
4944
0
      unsigned int memshift = i.memshift;
4945
0
      offsetT n = i.op[j].disps->X_add_number;
4946
4947
0
      evex_disp8 = fits_in_disp8 (n);
4948
0
      i.memshift = 0;
4949
0
      vex_disp8 = fits_in_disp8 (n);
4950
0
      if (evex_disp8 != vex_disp8)
4951
0
        {
4952
0
    i.memshift = memshift;
4953
0
    return;
4954
0
        }
4955
4956
0
      i.types[j].bitfield.disp8 = vex_disp8;
4957
0
      break;
4958
0
    }
4959
0
      if ((i.tm.base_opcode & ~Opcode_SIMD_IntD) == 0x6f
4960
0
    && i.tm.opcode_modifier.opcodeprefix == PREFIX_0XF2)
4961
0
  i.tm.opcode_modifier.opcodeprefix = PREFIX_0XF3;
4962
0
      i.tm.opcode_modifier.vex
4963
0
  = i.types[0].bitfield.ymmword ? VEX256 : VEX128;
4964
0
      i.tm.opcode_modifier.vexw = VEXW0;
4965
      /* VPAND, VPOR, and VPXOR are commutative.  */
4966
0
      if (i.reg_operands == 3 && i.tm.base_opcode != 0xdf)
4967
0
  i.tm.opcode_modifier.commutative = 1;
4968
0
      i.tm.opcode_modifier.evex = 0;
4969
0
      i.tm.opcode_modifier.masking = 0;
4970
0
      i.tm.opcode_modifier.broadcast = 0;
4971
0
      i.tm.opcode_modifier.disp8memshift = 0;
4972
0
      i.memshift = 0;
4973
0
      if (j < i.operands)
4974
0
  i.types[j].bitfield.disp8
4975
0
    = fits_in_disp8 (i.op[j].disps->X_add_number);
4976
0
    }
4977
0
  else if (optimize_for_space
4978
0
     && i.tm.base_opcode == 0x29
4979
0
     && i.tm.opcode_space == SPACE_0F38
4980
0
     && i.operands == i.reg_operands
4981
0
     && i.op[0].regs == i.op[1].regs
4982
0
     && (!i.tm.opcode_modifier.vex
4983
0
         || !(i.op[0].regs->reg_flags & RegRex))
4984
0
     && !i.tm.opcode_modifier.evex)
4985
0
    {
4986
      /* Optimize: -Os:
4987
         pcmpeqq %xmmN, %xmmN          -> pcmpeqd %xmmN, %xmmN
4988
         vpcmpeqq %xmmN, %xmmN, %xmmM  -> vpcmpeqd %xmmN, %xmmN, %xmmM (N < 8)
4989
         vpcmpeqq %ymmN, %ymmN, %ymmM  -> vpcmpeqd %ymmN, %ymmN, %ymmM (N < 8)
4990
       */
4991
0
      i.tm.opcode_space = SPACE_0F;
4992
0
      i.tm.base_opcode = 0x76;
4993
0
    }
4994
0
  else if (((i.tm.base_opcode >= 0x64
4995
0
       && i.tm.base_opcode <= 0x66
4996
0
       && i.tm.opcode_space == SPACE_0F)
4997
0
      || (i.tm.base_opcode == 0x37
4998
0
    && i.tm.opcode_space == SPACE_0F38))
4999
0
     && i.operands == i.reg_operands
5000
0
     && i.op[0].regs == i.op[1].regs
5001
0
     && !i.tm.opcode_modifier.evex)
5002
0
    {
5003
      /* Optimize: -O:
5004
         pcmpgt[bwd] %mmN, %mmN             -> pxor %mmN, %mmN
5005
         pcmpgt[bwdq] %xmmN, %xmmN          -> pxor %xmmN, %xmmN
5006
         vpcmpgt[bwdq] %xmmN, %xmmN, %xmmM  -> vpxor %xmmN, %xmmN, %xmmM (N < 8)
5007
         vpcmpgt[bwdq] %xmmN, %xmmN, %xmmM  -> vpxor %xmm0, %xmm0, %xmmM (N > 7)
5008
         vpcmpgt[bwdq] %ymmN, %ymmN, %ymmM  -> vpxor %ymmN, %ymmN, %ymmM (N < 8)
5009
         vpcmpgt[bwdq] %ymmN, %ymmN, %ymmM  -> vpxor %ymm0, %ymm0, %ymmM (N > 7)
5010
       */
5011
0
      i.tm.opcode_space = SPACE_0F;
5012
0
      i.tm.base_opcode = 0xef;
5013
0
      if (i.tm.opcode_modifier.vex && (i.op[0].regs->reg_flags & RegRex))
5014
0
  {
5015
0
    if (i.operands == 2)
5016
0
      {
5017
0
        gas_assert (i.tm.opcode_modifier.sse2avx);
5018
5019
0
        i.operands = 3;
5020
0
        i.reg_operands = 3;
5021
0
        i.tm.operands = 3;
5022
5023
0
        i.op[2].regs = i.op[0].regs;
5024
0
        i.types[2] = i.types[0];
5025
0
        i.flags[2] = i.flags[0];
5026
0
        i.tm.operand_types[2] = i.tm.operand_types[0];
5027
5028
0
        i.tm.opcode_modifier.sse2avx = 0;
5029
0
      }
5030
0
    i.op[0].regs -= i.op[0].regs->reg_num + 8;
5031
0
    i.op[1].regs = i.op[0].regs;
5032
0
  }
5033
0
    }
5034
0
  else if (optimize_for_space
5035
0
     && i.tm.base_opcode == 0x59
5036
0
     && i.tm.opcode_space == SPACE_0F38
5037
0
     && i.operands == i.reg_operands
5038
0
     && i.tm.opcode_modifier.vex
5039
0
     && !(i.op[0].regs->reg_flags & RegRex)
5040
0
     && i.op[0].regs->reg_type.bitfield.xmmword
5041
0
     && i.encoding != encoding_vex3)
5042
0
    {
5043
      /* Optimize: -Os:
5044
         vpbroadcastq %xmmN, %xmmM  -> vpunpcklqdq %xmmN, %xmmN, %xmmM (N < 8)
5045
       */
5046
0
      i.tm.opcode_space = SPACE_0F;
5047
0
      i.tm.base_opcode = 0x6c;
5048
0
      i.tm.opcode_modifier.vexvvvv = VexVVVV_SRC1;
5049
5050
0
      ++i.operands;
5051
0
      ++i.reg_operands;
5052
0
      ++i.tm.operands;
5053
5054
0
      i.op[2].regs = i.op[0].regs;
5055
0
      i.types[2] = i.types[0];
5056
0
      i.flags[2] = i.flags[0];
5057
0
      i.tm.operand_types[2] = i.tm.operand_types[0];
5058
5059
0
      swap_2_operands (1, 2);
5060
0
    }
5061
0
}
5062
5063
static void
5064
s_noopt (int dummy ATTRIBUTE_UNUSED)
5065
0
{
5066
0
  if (!is_it_end_of_statement ())
5067
0
    as_warn (_("`.noopt' arguments ignored"));
5068
5069
0
  optimize = 0;
5070
0
  optimize_for_space = 0;
5071
5072
0
  ignore_rest_of_line ();
5073
0
}
5074
5075
/* Return non-zero for load instruction.  */
5076
5077
static int
5078
load_insn_p (void)
5079
0
{
5080
0
  unsigned int dest;
5081
0
  int any_vex_p = is_any_vex_encoding (&i.tm);
5082
0
  unsigned int base_opcode = i.tm.base_opcode | 1;
5083
5084
0
  if (!any_vex_p)
5085
0
    {
5086
      /* Anysize insns: lea, invlpg, clflush, prefetch*, bndmk, bndcl, bndcu,
5087
   bndcn, bndstx, bndldx, clflushopt, clwb, cldemote.  */
5088
0
      if (i.tm.opcode_modifier.operandconstraint == ANY_SIZE)
5089
0
  return 0;
5090
5091
      /* pop.   */
5092
0
      if (i.tm.mnem_off == MN_pop)
5093
0
  return 1;
5094
0
    }
5095
5096
0
  if (i.tm.opcode_space == SPACE_BASE)
5097
0
    {
5098
      /* popf, popa.   */
5099
0
      if (i.tm.base_opcode == 0x9d
5100
0
    || i.tm.base_opcode == 0x61)
5101
0
  return 1;
5102
5103
      /* movs, cmps, lods, scas.  */
5104
0
      if ((i.tm.base_opcode | 0xb) == 0xaf)
5105
0
  return 1;
5106
5107
      /* outs, xlatb.  */
5108
0
      if (base_opcode == 0x6f
5109
0
    || i.tm.base_opcode == 0xd7)
5110
0
  return 1;
5111
      /* NB: For AMD-specific insns with implicit memory operands,
5112
   they're intentionally not covered.  */
5113
0
    }
5114
5115
  /* No memory operand.  */
5116
0
  if (!i.mem_operands)
5117
0
    return 0;
5118
5119
0
  if (any_vex_p)
5120
0
    {
5121
0
      if (i.tm.mnem_off == MN_vldmxcsr)
5122
0
  return 1;
5123
0
    }
5124
0
  else if (i.tm.opcode_space == SPACE_BASE)
5125
0
    {
5126
      /* test, not, neg, mul, imul, div, idiv.  */
5127
0
      if (base_opcode == 0xf7 && i.tm.extension_opcode != 1)
5128
0
  return 1;
5129
5130
      /* inc, dec.  */
5131
0
      if (base_opcode == 0xff && i.tm.extension_opcode <= 1)
5132
0
  return 1;
5133
5134
      /* add, or, adc, sbb, and, sub, xor, cmp.  */
5135
0
      if (i.tm.base_opcode >= 0x80 && i.tm.base_opcode <= 0x83)
5136
0
  return 1;
5137
5138
      /* rol, ror, rcl, rcr, shl/sal, shr, sar. */
5139
0
      if ((base_opcode == 0xc1 || (base_opcode | 2) == 0xd3)
5140
0
    && i.tm.extension_opcode != 6)
5141
0
  return 1;
5142
5143
      /* Check for x87 instructions.  */
5144
0
      if ((base_opcode | 6) == 0xdf)
5145
0
  {
5146
    /* Skip fst, fstp, fstenv, fstcw.  */
5147
0
    if (i.tm.base_opcode == 0xd9
5148
0
        && (i.tm.extension_opcode == 2
5149
0
      || i.tm.extension_opcode == 3
5150
0
      || i.tm.extension_opcode == 6
5151
0
      || i.tm.extension_opcode == 7))
5152
0
      return 0;
5153
5154
    /* Skip fisttp, fist, fistp, fstp.  */
5155
0
    if (i.tm.base_opcode == 0xdb
5156
0
        && (i.tm.extension_opcode == 1
5157
0
      || i.tm.extension_opcode == 2
5158
0
      || i.tm.extension_opcode == 3
5159
0
      || i.tm.extension_opcode == 7))
5160
0
      return 0;
5161
5162
    /* Skip fisttp, fst, fstp, fsave, fstsw.  */
5163
0
    if (i.tm.base_opcode == 0xdd
5164
0
        && (i.tm.extension_opcode == 1
5165
0
      || i.tm.extension_opcode == 2
5166
0
      || i.tm.extension_opcode == 3
5167
0
      || i.tm.extension_opcode == 6
5168
0
      || i.tm.extension_opcode == 7))
5169
0
      return 0;
5170
5171
    /* Skip fisttp, fist, fistp, fbstp, fistp.  */
5172
0
    if (i.tm.base_opcode == 0xdf
5173
0
        && (i.tm.extension_opcode == 1
5174
0
      || i.tm.extension_opcode == 2
5175
0
      || i.tm.extension_opcode == 3
5176
0
      || i.tm.extension_opcode == 6
5177
0
      || i.tm.extension_opcode == 7))
5178
0
      return 0;
5179
5180
0
    return 1;
5181
0
  }
5182
0
    }
5183
0
  else if (i.tm.opcode_space == SPACE_0F)
5184
0
    {
5185
      /* bt, bts, btr, btc.  */
5186
0
      if (i.tm.base_opcode == 0xba
5187
0
    && (i.tm.extension_opcode | 3) == 7)
5188
0
  return 1;
5189
5190
      /* cmpxchg8b, cmpxchg16b, xrstors, vmptrld.  */
5191
0
      if (i.tm.base_opcode == 0xc7
5192
0
    && i.tm.opcode_modifier.opcodeprefix == PREFIX_NONE
5193
0
    && (i.tm.extension_opcode == 1 || i.tm.extension_opcode == 3
5194
0
        || i.tm.extension_opcode == 6))
5195
0
  return 1;
5196
5197
      /* fxrstor, ldmxcsr, xrstor.  */
5198
0
      if (i.tm.base_opcode == 0xae
5199
0
    && (i.tm.extension_opcode == 1
5200
0
        || i.tm.extension_opcode == 2
5201
0
        || i.tm.extension_opcode == 5))
5202
0
  return 1;
5203
5204
      /* lgdt, lidt, lmsw.  */
5205
0
      if (i.tm.base_opcode == 0x01
5206
0
    && (i.tm.extension_opcode == 2
5207
0
        || i.tm.extension_opcode == 3
5208
0
        || i.tm.extension_opcode == 6))
5209
0
  return 1;
5210
0
    }
5211
5212
0
  dest = i.operands - 1;
5213
5214
  /* Check fake imm8 operand and 3 source operands.  */
5215
0
  if ((i.tm.opcode_modifier.immext
5216
0
       || i.reg_operands + i.mem_operands == 4)
5217
0
      && i.types[dest].bitfield.imm8)
5218
0
    dest--;
5219
5220
  /* add, or, adc, sbb, and, sub, xor, cmp, test, xchg.  */
5221
0
  if (i.tm.opcode_space == SPACE_BASE
5222
0
      && ((base_opcode | 0x38) == 0x39
5223
0
    || (base_opcode | 2) == 0x87))
5224
0
    return 1;
5225
5226
0
  if (i.tm.mnem_off == MN_xadd)
5227
0
    return 1;
5228
5229
  /* Check for load instruction.  */
5230
0
  return (i.types[dest].bitfield.class != ClassNone
5231
0
    || i.types[dest].bitfield.instance == Accum);
5232
0
}
5233
5234
/* Output lfence, 0xfaee8, after instruction.  */
5235
5236
static void
5237
insert_lfence_after (void)
5238
662k
{
5239
662k
  if (lfence_after_load && load_insn_p ())
5240
0
    {
5241
      /* There are also two REP string instructions that require
5242
   special treatment. Specifically, the compare string (CMPS)
5243
   and scan string (SCAS) instructions set EFLAGS in a manner
5244
   that depends on the data being compared/scanned. When used
5245
   with a REP prefix, the number of iterations may therefore
5246
   vary depending on this data. If the data is a program secret
5247
   chosen by the adversary using an LVI method,
5248
   then this data-dependent behavior may leak some aspect
5249
   of the secret.  */
5250
0
      if (((i.tm.base_opcode | 0x9) == 0xaf)
5251
0
    && i.prefix[REP_PREFIX])
5252
0
  {
5253
0
      as_warn (_("`%s` changes flags which would affect control flow behavior"),
5254
0
         insn_name (&i.tm));
5255
0
  }
5256
0
      char *p = frag_more (3);
5257
0
      *p++ = 0xf;
5258
0
      *p++ = 0xae;
5259
0
      *p = 0xe8;
5260
0
    }
5261
662k
}
5262
5263
/* Output lfence, 0xfaee8, before instruction.  */
5264
5265
static void
5266
insert_lfence_before (const struct last_insn *last_insn)
5267
662k
{
5268
662k
  char *p;
5269
5270
662k
  if (i.tm.opcode_space != SPACE_BASE)
5271
1.34k
    return;
5272
5273
661k
  if (i.tm.base_opcode == 0xff
5274
661k
      && (i.tm.extension_opcode == 2 || i.tm.extension_opcode == 4))
5275
0
    {
5276
      /* Insert lfence before indirect branch if needed.  */
5277
5278
0
      if (lfence_before_indirect_branch == lfence_branch_none)
5279
0
  return;
5280
5281
0
      if (i.operands != 1)
5282
0
  abort ();
5283
5284
0
      if (i.reg_operands == 1)
5285
0
  {
5286
    /* Indirect branch via register.  Don't insert lfence with
5287
       -mlfence-after-load=yes.  */
5288
0
    if (lfence_after_load
5289
0
        || lfence_before_indirect_branch == lfence_branch_memory)
5290
0
      return;
5291
0
  }
5292
0
      else if (i.mem_operands == 1
5293
0
         && lfence_before_indirect_branch != lfence_branch_register)
5294
0
  {
5295
0
    as_warn (_("indirect `%s` with memory operand should be avoided"),
5296
0
       insn_name (&i.tm));
5297
0
    return;
5298
0
  }
5299
0
      else
5300
0
  return;
5301
5302
0
      if (last_insn->kind != last_insn_other)
5303
0
  {
5304
0
    as_warn_where (last_insn->file, last_insn->line,
5305
0
       _("`%s` skips -mlfence-before-indirect-branch on `%s`"),
5306
0
       last_insn->name, insn_name (&i.tm));
5307
0
    return;
5308
0
  }
5309
5310
0
      p = frag_more (3);
5311
0
      *p++ = 0xf;
5312
0
      *p++ = 0xae;
5313
0
      *p = 0xe8;
5314
0
      return;
5315
0
    }
5316
5317
  /* Output or/not/shl and lfence before near ret.  */
5318
661k
  if (lfence_before_ret != lfence_before_ret_none
5319
661k
      && (i.tm.base_opcode | 1) == 0xc3)
5320
0
    {
5321
0
      if (last_insn->kind != last_insn_other)
5322
0
  {
5323
0
    as_warn_where (last_insn->file, last_insn->line,
5324
0
       _("`%s` skips -mlfence-before-ret on `%s`"),
5325
0
       last_insn->name, insn_name (&i.tm));
5326
0
    return;
5327
0
  }
5328
5329
      /* Near ret ingore operand size override under CPU64.  */
5330
0
      char prefix = flag_code == CODE_64BIT
5331
0
        ? 0x48
5332
0
        : i.prefix[DATA_PREFIX] ? 0x66 : 0x0;
5333
5334
0
      if (lfence_before_ret == lfence_before_ret_not)
5335
0
  {
5336
    /* not: 0xf71424, may add prefix
5337
       for operand size override or 64-bit code.  */
5338
0
    p = frag_more ((prefix ? 2 : 0) + 6 + 3);
5339
0
    if (prefix)
5340
0
      *p++ = prefix;
5341
0
    *p++ = 0xf7;
5342
0
    *p++ = 0x14;
5343
0
    *p++ = 0x24;
5344
0
    if (prefix)
5345
0
      *p++ = prefix;
5346
0
    *p++ = 0xf7;
5347
0
    *p++ = 0x14;
5348
0
    *p++ = 0x24;
5349
0
  }
5350
0
      else
5351
0
  {
5352
0
    p = frag_more ((prefix ? 1 : 0) + 4 + 3);
5353
0
    if (prefix)
5354
0
      *p++ = prefix;
5355
0
    if (lfence_before_ret == lfence_before_ret_or)
5356
0
      {
5357
        /* or: 0x830c2400, may add prefix
5358
     for operand size override or 64-bit code.  */
5359
0
        *p++ = 0x83;
5360
0
        *p++ = 0x0c;
5361
0
      }
5362
0
    else
5363
0
      {
5364
        /* shl: 0xc1242400, may add prefix
5365
     for operand size override or 64-bit code.  */
5366
0
        *p++ = 0xc1;
5367
0
        *p++ = 0x24;
5368
0
      }
5369
5370
0
    *p++ = 0x24;
5371
0
    *p++ = 0x0;
5372
0
  }
5373
5374
0
      *p++ = 0xf;
5375
0
      *p++ = 0xae;
5376
0
      *p = 0xe8;
5377
0
    }
5378
661k
}
5379
5380
/* Shared helper for md_assemble() and s_insn().  */
5381
static void init_globals (void)
5382
1.90M
{
5383
1.90M
  unsigned int j;
5384
5385
1.90M
  memset (&i, '\0', sizeof (i));
5386
1.90M
  i.rounding.type = rc_none;
5387
11.4M
  for (j = 0; j < MAX_OPERANDS; j++)
5388
9.53M
    i.reloc[j] = NO_RELOC;
5389
1.90M
  memset (disp_expressions, '\0', sizeof (disp_expressions));
5390
1.90M
  memset (im_expressions, '\0', sizeof (im_expressions));
5391
1.90M
  save_stack_p = save_stack;
5392
1.90M
}
5393
5394
/* Helper for md_assemble() to decide whether to prepare for a possible 2nd
5395
   parsing pass. Instead of introducing a rarely use new insn attribute this
5396
   utilizes a common pattern between affected templates. It is deemed
5397
   acceptable that this will lead to unnecessary pass 2 preparations in a
5398
   limited set of cases.  */
5399
static INLINE bool may_need_pass2 (const insn_template *t)
5400
762k
{
5401
762k
  return t->opcode_modifier.sse2avx
5402
   /* Note that all SSE2AVX templates have at least one operand.  */
5403
762k
   ? t->operand_types[t->operands - 1].bitfield.class == RegSIMD
5404
762k
   : (t->opcode_space == SPACE_0F
5405
759k
      && (t->base_opcode | 1) == 0xbf)
5406
759k
     || (t->opcode_space == SPACE_BASE
5407
757k
         && t->base_opcode == 0x63);
5408
762k
}
5409
5410
#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
5411
5412
/* DWARF register number for EFLAGS.  Used for pushf/popf insns.  */
5413
0
#define GINSN_DW2_REGNUM_EFLAGS     49
5414
/* DWARF register number for RSI.  Used as dummy value when RegIP/RegIZ.  */
5415
0
#define GINSN_DW2_REGNUM_RSI_DUMMY  4
5416
5417
/* Identify the callee-saved registers in System V AMD64 ABI.  */
5418
5419
bool
5420
x86_scfi_callee_saved_p (unsigned int dw2reg_num)
5421
0
{
5422
0
  if (dw2reg_num == 3 /* rbx.  */
5423
      || dw2reg_num == REG_FP /* rbp.  */
5424
      || dw2reg_num == REG_SP /* rsp.  */
5425
0
      || (dw2reg_num >= 12 && dw2reg_num <= 15) /* r12 - r15.  */)
5426
0
    return true;
5427
5428
0
  return false;
5429
0
}
5430
5431
/* Check whether an instruction prefix which affects operation size
5432
   accompanies.  For insns in the legacy space, setting REX.W takes precedence
5433
   over the operand-size prefix (66H) when both are used.
5434
5435
   The current users of this API are in the handlers for PUSH, POP or other
5436
   instructions which affect the stack pointer implicitly:  the operation size
5437
   (16, 32, or 64 bits) determines the amount by which the stack pointer is
5438
   incremented / decremented (2, 4 or 8).  */
5439
5440
static bool
5441
ginsn_opsize_prefix_p (void)
5442
0
{
5443
0
  return (!(i.prefix[REX_PREFIX] & REX_W) && i.prefix[DATA_PREFIX]);
5444
0
}
5445
5446
/* Get the DWARF register number for the given register entry.
5447
   For specific byte/word/dword register accesses like al, cl, ah, ch, r8d,
5448
   r20w etc., we need to identify the DWARF register number for the
5449
   corresponding 8-byte GPR.
5450
5451
   This function is a hack - it relies on relative ordering of reg entries in
5452
   the i386_regtab.  FIXME - it will be good to allow a more direct way to get
5453
   this information.  */
5454
5455
static unsigned int
5456
ginsn_dw2_regnum (const reg_entry *ireg)
5457
0
{
5458
0
  const reg_entry *temp = ireg;
5459
0
  unsigned int dwarf_reg = Dw2Inval, idx = 0;
5460
5461
  /* ginsn creation is available for AMD64 abi only ATM.  Other flag_code
5462
     are not expected.  */
5463
0
  gas_assert (ireg && flag_code == CODE_64BIT);
5464
5465
  /* Watch out for RegIP, RegIZ.  These are expected to appear only with
5466
     base/index addressing modes.  Although creating inaccurate data
5467
     dependencies, using a dummy value (lets say volatile register rsi) will
5468
     not hurt SCFI.  TBD_GINSN_GEN_NOT_SCFI.  */
5469
0
  if (ireg->reg_num == RegIP || ireg->reg_num == RegIZ)
5470
0
    return GINSN_DW2_REGNUM_RSI_DUMMY;
5471
5472
0
  dwarf_reg = ireg->dw2_regnum[object_64bit];
5473
5474
0
  if (dwarf_reg == Dw2Inval)
5475
0
    {
5476
0
      if (ireg <= &i386_regtab[3])
5477
  /* For al, cl, dl, bl, bump over to axl, cxl, dxl, bxl respectively by
5478
     adding 8.  */
5479
0
  temp = ireg + 8;
5480
0
      else if (ireg <= &i386_regtab[7])
5481
  /* For ah, ch, dh, bh, bump over to axl, cxl, dxl, bxl respectively by
5482
     adding 4.  */
5483
0
  temp = ireg + 4;
5484
0
      else
5485
0
  {
5486
    /* The code relies on the relative ordering of the reg entries in
5487
       i386_regtab.  There are 32 register entries between axl-r31b,
5488
       ax-r31w etc.  The assertions here ensures the code does not
5489
       recurse indefinitely.  */
5490
0
    gas_assert ((temp - &i386_regtab[0]) >= 0);
5491
0
    idx = temp - &i386_regtab[0];
5492
0
    gas_assert (idx + 32 < i386_regtab_size - 1);
5493
5494
0
    temp = temp + 32;
5495
0
  }
5496
5497
0
      dwarf_reg = ginsn_dw2_regnum (temp);
5498
0
    }
5499
5500
  /* Sanity check - failure may indicate state corruption, bad ginsn or
5501
     perhaps the i386-reg table and the current function got out of sync.  */
5502
0
  gas_assert (dwarf_reg < Dw2Inval);
5503
5504
0
  return dwarf_reg;
5505
0
}
5506
5507
static ginsnS *
5508
x86_ginsn_addsub_reg_mem (const symbolS *insn_end_sym)
5509
0
{
5510
0
  unsigned int dw2_regnum;
5511
0
  unsigned int src1_dw2_regnum;
5512
0
  ginsnS *ginsn = NULL;
5513
0
  ginsnS * (*ginsn_func) (const symbolS *, bool,
5514
0
        enum ginsn_src_type, unsigned int, offsetT,
5515
0
        enum ginsn_src_type, unsigned int, offsetT,
5516
0
        enum ginsn_dst_type, unsigned int, offsetT);
5517
0
  uint16_t opcode = i.tm.base_opcode;
5518
5519
0
  gas_assert (i.tm.opcode_space == SPACE_BASE
5520
0
        && (opcode == 0x1 || opcode == 0x29));
5521
0
  ginsn_func = (opcode == 0x1) ? ginsn_new_add : ginsn_new_sub;
5522
5523
  /* op %reg, symbol or even other cases where destination involves indirect
5524
     access are unnecessary for SCFI correctness.  TBD_GINSN_GEN_NOT_SCFI.  */
5525
0
  if (i.mem_operands)
5526
0
    return ginsn;
5527
5528
  /* Skip detection of 8/16/32-bit op size; 'add/sub reg, reg/mem' ops always
5529
     make the dest reg untraceable for SCFI.  */
5530
5531
  /* op reg, reg/mem.  */
5532
0
  src1_dw2_regnum = ginsn_dw2_regnum (i.op[0].regs);
5533
  /* Of interest only when second opnd is not memory.  */
5534
0
  if (i.reg_operands == 2)
5535
0
    {
5536
0
      dw2_regnum = ginsn_dw2_regnum (i.op[1].regs);
5537
0
      ginsn = ginsn_func (insn_end_sym, true,
5538
0
        GINSN_SRC_REG, src1_dw2_regnum, 0,
5539
0
        GINSN_SRC_REG, dw2_regnum, 0,
5540
0
        GINSN_DST_REG, dw2_regnum, 0);
5541
0
      ginsn_set_where (ginsn);
5542
0
    }
5543
5544
0
  return ginsn;
5545
0
}
5546
5547
static ginsnS *
5548
x86_ginsn_addsub_mem_reg (const symbolS *insn_end_sym)
5549
0
{
5550
0
  unsigned int dw2_regnum;
5551
0
  unsigned int src1_dw2_regnum;
5552
0
  const reg_entry *mem_reg;
5553
0
  int32_t gdisp = 0;
5554
0
  ginsnS *ginsn = NULL;
5555
0
  ginsnS * (*ginsn_func) (const symbolS *, bool,
5556
0
        enum ginsn_src_type, unsigned int, offsetT,
5557
0
        enum ginsn_src_type, unsigned int, offsetT,
5558
0
        enum ginsn_dst_type, unsigned int, offsetT);
5559
0
  uint16_t opcode = i.tm.base_opcode;
5560
5561
0
  gas_assert (i.tm.opcode_space == SPACE_BASE
5562
0
        && (opcode == 0x3 || opcode == 0x2b));
5563
0
  ginsn_func = (opcode == 0x3) ? ginsn_new_add : ginsn_new_sub;
5564
5565
  /* op symbol, %reg.  */
5566
0
  if (i.mem_operands && !i.base_reg && !i.index_reg)
5567
0
    return ginsn;
5568
5569
  /* Skip detection of 8/16/32-bit op size; 'add/sub reg/mem, reg' ops always
5570
     make the dest reg untraceable for SCFI.  */
5571
5572
  /* op reg/mem, %reg.  */
5573
0
  dw2_regnum = ginsn_dw2_regnum (i.op[1].regs);
5574
5575
0
  if (i.reg_operands == 2)
5576
0
    {
5577
0
      src1_dw2_regnum = ginsn_dw2_regnum (i.op[0].regs);
5578
0
      ginsn = ginsn_func (insn_end_sym, true,
5579
0
        GINSN_SRC_REG, src1_dw2_regnum, 0,
5580
0
        GINSN_SRC_REG, dw2_regnum, 0,
5581
0
        GINSN_DST_REG, dw2_regnum, 0);
5582
0
      ginsn_set_where (ginsn);
5583
0
    }
5584
0
  else if (i.mem_operands)
5585
0
    {
5586
0
      mem_reg = (i.base_reg) ? i.base_reg : i.index_reg;
5587
0
      src1_dw2_regnum = ginsn_dw2_regnum (mem_reg);
5588
0
      if (i.disp_operands == 1)
5589
0
  gdisp = i.op[0].disps->X_add_number;
5590
0
      ginsn = ginsn_func (insn_end_sym, true,
5591
0
        GINSN_SRC_INDIRECT, src1_dw2_regnum, gdisp,
5592
0
        GINSN_SRC_REG, dw2_regnum, 0,
5593
0
        GINSN_DST_REG, dw2_regnum, 0);
5594
0
      ginsn_set_where (ginsn);
5595
0
    }
5596
5597
0
  return ginsn;
5598
0
}
5599
5600
static ginsnS *
5601
x86_ginsn_alu_imm (const symbolS *insn_end_sym)
5602
0
{
5603
0
  offsetT src_imm;
5604
0
  unsigned int dw2_regnum;
5605
0
  ginsnS *ginsn = NULL;
5606
0
  enum ginsn_src_type src_type = GINSN_SRC_REG;
5607
0
  enum ginsn_dst_type dst_type = GINSN_DST_REG;
5608
5609
0
  ginsnS * (*ginsn_func) (const symbolS *, bool,
5610
0
        enum ginsn_src_type, unsigned int, offsetT,
5611
0
        enum ginsn_src_type, unsigned int, offsetT,
5612
0
        enum ginsn_dst_type, unsigned int, offsetT);
5613
5614
  /* FIXME - create ginsn where dest is REG_SP / REG_FP only ? */
5615
  /* Map for insn.tm.extension_opcode
5616
     000 ADD    100 AND
5617
     001 OR     101 SUB
5618
     010 ADC    110 XOR
5619
     011 SBB    111 CMP  */
5620
5621
  /* add/sub/and imm, %reg only at this time for SCFI.
5622
     Although all three ('and', 'or' , 'xor') make the destination reg
5623
     untraceable, 'and' op is handled but not 'or' / 'xor' because we will look
5624
     into supporting the DRAP pattern at some point.  Other opcodes ('adc',
5625
     'sbb' and 'cmp') are not generated here either.  The ginsn representation
5626
     does not have support for the latter three opcodes;  GINSN_TYPE_OTHER may
5627
     be added for these after x86_ginsn_unhandled () invocation if the
5628
     destination register is REG_SP or REG_FP.  */
5629
0
  if (i.tm.extension_opcode == 5)
5630
0
    ginsn_func = ginsn_new_sub;
5631
0
  else if (i.tm.extension_opcode == 4)
5632
0
    ginsn_func = ginsn_new_and;
5633
0
  else if (i.tm.extension_opcode == 0)
5634
0
    ginsn_func = ginsn_new_add;
5635
0
  else
5636
0
    return ginsn;
5637
5638
  /* TBD_GINSN_REPRESENTATION_LIMIT: There is no representation for when a
5639
     symbol is used as an operand, like so:
5640
    addq    $simd_cmp_op+8, %rdx
5641
     Skip generating any ginsn for this.  */
5642
0
  if (i.imm_operands == 1
5643
0
      && i.op[0].imms->X_op != O_constant)
5644
0
    return ginsn;
5645
5646
  /* addq    $1, symbol
5647
     addq    $1, -16(%rbp)
5648
     These are not of interest for SCFI.  Also, TBD_GINSN_GEN_NOT_SCFI.  */
5649
0
  if (i.mem_operands == 1)
5650
0
    return ginsn;
5651
5652
  /* 8/16/32-bit op size makes the destination reg untraceable for SCFI.
5653
     Deal with this via the x86_ginsn_unhandled () code path.  */
5654
0
  if (i.suffix != QWORD_MNEM_SUFFIX)
5655
0
    return ginsn;
5656
5657
0
  gas_assert (i.imm_operands == 1);
5658
0
  src_imm = i.op[0].imms->X_add_number;
5659
  /* The second operand may be a register or indirect access.  For SCFI, only
5660
     the case when the second opnd is a register is interesting.  Revisit this
5661
     if generating ginsns for a different gen mode TBD_GINSN_GEN_NOT_SCFI.  */
5662
0
  if (i.reg_operands == 1)
5663
0
    {
5664
0
      dw2_regnum = ginsn_dw2_regnum (i.op[1].regs);
5665
      /* For ginsn, keep the imm as second src operand.  */
5666
0
      ginsn = ginsn_func (insn_end_sym, true,
5667
0
        src_type, dw2_regnum, 0,
5668
0
        GINSN_SRC_IMM, 0, src_imm,
5669
0
        dst_type, dw2_regnum, 0);
5670
5671
0
      ginsn_set_where (ginsn);
5672
0
    }
5673
5674
0
  return ginsn;
5675
0
}
5676
5677
/* Create ginsn(s) for MOV operations.
5678
5679
   The generated ginsns corresponding to mov with indirect access to memory
5680
   (src or dest) suffer with loss of information: when both index and base
5681
   registers are at play, only base register gets conveyed in ginsn.  Note
5682
   this TBD_GINSN_GEN_NOT_SCFI.  */
5683
5684
static ginsnS *
5685
x86_ginsn_move (const symbolS *insn_end_sym)
5686
0
{
5687
0
  ginsnS *ginsn = NULL;
5688
0
  unsigned int dst_reg;
5689
0
  unsigned int src_reg;
5690
0
  offsetT src_disp = 0;
5691
0
  offsetT dst_disp = 0;
5692
0
  const reg_entry *dst = NULL;
5693
0
  const reg_entry *src = NULL;
5694
0
  uint16_t opcode = i.tm.base_opcode;
5695
0
  enum ginsn_src_type src_type = GINSN_SRC_REG;
5696
0
  enum ginsn_dst_type dst_type = GINSN_DST_REG;
5697
5698
  /* mov %reg, symbol or mov symbol, %reg.
5699
     Not of interest for SCFI.  Also, TBD_GINSN_GEN_NOT_SCFI.  */
5700
0
  if (i.mem_operands == 1 && !i.base_reg && !i.index_reg)
5701
0
    return ginsn;
5702
5703
  /* 8/16/32-bit op size makes the destination reg untraceable for SCFI.
5704
     Handle mov reg, reg only.  mov to or from a memory operand will make
5705
     dest reg, when present, untraceable, irrespective of the op size.  */
5706
0
  if (i.reg_operands == 2 && i.suffix != QWORD_MNEM_SUFFIX)
5707
0
    return ginsn;
5708
5709
0
  gas_assert (i.tm.opcode_space == SPACE_BASE);
5710
0
  if (opcode == 0x8b || opcode == 0x8a)
5711
0
    {
5712
      /* mov  disp(%reg), %reg.  */
5713
0
      if (i.mem_operands)
5714
0
  {
5715
0
    src = (i.base_reg) ? i.base_reg : i.index_reg;
5716
0
    if (i.disp_operands == 1)
5717
0
      src_disp = i.op[0].disps->X_add_number;
5718
0
    src_type = GINSN_SRC_INDIRECT;
5719
0
  }
5720
0
      else
5721
0
  src = i.op[0].regs;
5722
5723
0
      dst = i.op[1].regs;
5724
0
    }
5725
0
  else if (opcode == 0x89 || opcode == 0x88)
5726
0
    {
5727
      /* mov %reg, disp(%reg).  */
5728
0
      src = i.op[0].regs;
5729
0
      if (i.mem_operands)
5730
0
  {
5731
0
    dst = (i.base_reg) ? i.base_reg : i.index_reg;
5732
0
    if (i.disp_operands == 1)
5733
0
      dst_disp = i.op[1].disps->X_add_number;
5734
0
    dst_type = GINSN_DST_INDIRECT;
5735
0
  }
5736
0
      else
5737
0
  dst = i.op[1].regs;
5738
0
    }
5739
5740
0
  src_reg = ginsn_dw2_regnum (src);
5741
0
  dst_reg = ginsn_dw2_regnum (dst);
5742
5743
0
  ginsn = ginsn_new_mov (insn_end_sym, true,
5744
0
       src_type, src_reg, src_disp,
5745
0
       dst_type, dst_reg, dst_disp);
5746
0
  ginsn_set_where (ginsn);
5747
5748
0
  return ginsn;
5749
0
}
5750
5751
/* Generate appropriate ginsn for lea.
5752
5753
   Unhandled sub-cases (marked with TBD_GINSN_GEN_NOT_SCFI) also suffer with
5754
   some loss of information in the final ginsn chosen eventually (type
5755
   GINSN_TYPE_OTHER).  But this is fine for now for GINSN_GEN_SCFI generation
5756
   mode.  */
5757
5758
static ginsnS *
5759
x86_ginsn_lea (const symbolS *insn_end_sym)
5760
0
{
5761
0
  offsetT src_disp = 0;
5762
0
  ginsnS *ginsn = NULL;
5763
0
  unsigned int src1_reg;
5764
0
  const reg_entry *src1;
5765
0
  offsetT index_scale;
5766
0
  unsigned int dst_reg;
5767
0
  bool index_regiz_p;
5768
5769
0
  if ((!i.base_reg) != (!i.index_reg || i.index_reg->reg_num == RegIZ))
5770
0
    {
5771
      /* lea disp(%base), %dst    or    lea disp(,%index,imm), %dst.
5772
   Either index_reg or base_reg exists, but not both.  Further, as per
5773
   above, the case when just %index exists but is equal to RegIZ is
5774
   excluded.  If not excluded, a GINSN_TYPE_MOV of %rsi
5775
   (GINSN_DW2_REGNUM_RSI_DUMMY) to %dst will be generated by this block.
5776
   Such a mov ginsn is imprecise; so, exclude now and generate
5777
   GINSN_TYPE_OTHER instead later via the x86_ginsn_unhandled ().
5778
   Excluding other cases is required due to
5779
   TBD_GINSN_REPRESENTATION_LIMIT.  */
5780
5781
0
      index_scale = i.log2_scale_factor;
5782
0
      index_regiz_p = i.index_reg && i.index_reg->reg_num == RegIZ;
5783
0
      src1 = i.base_reg ? i.base_reg : i.index_reg;
5784
0
      src1_reg = ginsn_dw2_regnum (src1);
5785
0
      dst_reg = ginsn_dw2_regnum (i.op[1].regs);
5786
      /* It makes sense to represent a scale factor of 1 precisely here
5787
   (i.e., not using GINSN_TYPE_OTHER, but rather similar to the
5788
   base-without-index case).  A non-zero scale factor is still OK if
5789
   the index reg is zero reg.
5790
   However, skip from here the case when disp has a symbol instead.
5791
   TBD_GINSN_REPRESENTATION_LIMIT.  */
5792
0
      if ((!index_scale || index_regiz_p)
5793
0
    && (!i.disp_operands || i.op[0].disps->X_op == O_constant))
5794
0
  {
5795
0
    if (i.disp_operands)
5796
0
      src_disp = i.op[0].disps->X_add_number;
5797
5798
0
    if (src_disp)
5799
      /* Generate an ADD ginsn.  */
5800
0
      ginsn = ginsn_new_add (insn_end_sym, true,
5801
0
           GINSN_SRC_REG, src1_reg, 0,
5802
0
           GINSN_SRC_IMM, 0, src_disp,
5803
0
           GINSN_DST_REG, dst_reg, 0);
5804
0
    else
5805
      /* Generate a MOV ginsn.  */
5806
0
      ginsn = ginsn_new_mov (insn_end_sym, true,
5807
0
           GINSN_SRC_REG, src1_reg, 0,
5808
0
           GINSN_DST_REG, dst_reg, 0);
5809
5810
0
    ginsn_set_where (ginsn);
5811
0
  }
5812
0
    }
5813
  /* Skip handling other cases here,
5814
     - when (i.index_reg && i.base_reg) is true,
5815
       e.g., lea disp(%base,%index,imm), %dst
5816
       We do not have a ginsn representation for multiply.
5817
     - or, when (!i.index_reg && !i.base_reg) is true,
5818
       e.g., lea symbol, %dst
5819
       Not a frequent pattern.  If %dst is a register of interest, the user is
5820
       likely to use a MOV op anyway.
5821
     Deal with these via the x86_ginsn_unhandled () code path to generate
5822
     GINSN_TYPE_OTHER when necessary.  TBD_GINSN_GEN_NOT_SCFI.  */
5823
5824
0
  return ginsn;
5825
0
}
5826
5827
static ginsnS *
5828
x86_ginsn_jump (const symbolS *insn_end_sym, bool cond_p)
5829
0
{
5830
0
  ginsnS *ginsn = NULL;
5831
0
  const symbolS *src_symbol;
5832
0
  ginsnS * (*ginsn_func) (const symbolS *sym, bool real_p,
5833
0
        enum ginsn_src_type src_type, unsigned int src_reg,
5834
0
        const symbolS *src_ginsn_sym);
5835
5836
0
  gas_assert (i.disp_operands == 1);
5837
5838
0
  ginsn_func = cond_p ? ginsn_new_jump_cond : ginsn_new_jump;
5839
0
  if (i.op[0].disps->X_op == O_symbol && !i.op[0].disps->X_add_number)
5840
0
    {
5841
0
      src_symbol = i.op[0].disps->X_add_symbol;
5842
0
      ginsn = ginsn_func (insn_end_sym, true,
5843
0
        GINSN_SRC_SYMBOL, 0, src_symbol);
5844
5845
0
      ginsn_set_where (ginsn);
5846
0
    }
5847
0
  else
5848
0
    {
5849
      /* A non-zero addend in jump/JCC target makes control-flow tracking
5850
   difficult.  Skip SCFI for now.  */
5851
0
      as_bad (_("SCFI: `%s' insn with non-zero addend to sym not supported"),
5852
0
        cond_p ? "JCC" : "jmp");
5853
0
      return ginsn;
5854
0
    }
5855
5856
0
  return ginsn;
5857
0
}
5858
5859
static ginsnS *
5860
x86_ginsn_enter (const symbolS *insn_end_sym)
5861
0
{
5862
0
  ginsnS *ginsn = NULL;
5863
0
  ginsnS *ginsn_next = NULL;
5864
0
  ginsnS *ginsn_last = NULL;
5865
  /* In 64-bit mode, the default stack update size is 8 bytes.  */
5866
0
  int stack_opnd_size = 8;
5867
5868
0
  gas_assert (i.imm_operands == 2);
5869
5870
  /* For non-zero size operands, bail out as untraceable for SCFI.  */
5871
0
  if (i.op[0].imms->X_op != O_constant || i.op[0].imms->X_add_symbol != 0
5872
0
      || i.op[1].imms->X_op != O_constant || i.op[1].imms->X_add_symbol != 0)
5873
0
    {
5874
0
      as_bad ("SCFI: enter insn with non-zero operand not supported");
5875
0
      return ginsn;
5876
0
    }
5877
5878
  /* Check if this is a 16-bit op.  */
5879
0
  if (ginsn_opsize_prefix_p ())
5880
0
    stack_opnd_size = 2;
5881
5882
  /* If the nesting level is 0, the processor pushes the frame pointer from
5883
     the BP/EBP/RBP register onto the stack, copies the current stack
5884
     pointer from the SP/ESP/RSP register into the BP/EBP/RBP register, and
5885
     loads the SP/ESP/RSP register with the current stack-pointer value
5886
     minus the value in the size operand.  */
5887
0
  ginsn = ginsn_new_sub (insn_end_sym, false,
5888
0
       GINSN_SRC_REG, REG_SP, 0,
5889
0
       GINSN_SRC_IMM, 0, stack_opnd_size,
5890
0
       GINSN_DST_REG, REG_SP, 0);
5891
0
  ginsn_set_where (ginsn);
5892
0
  ginsn_next = ginsn_new_store (insn_end_sym, false,
5893
0
        GINSN_SRC_REG, REG_FP,
5894
0
        GINSN_DST_INDIRECT, REG_SP, 0);
5895
0
  ginsn_set_where (ginsn_next);
5896
0
  gas_assert (!ginsn_link_next (ginsn, ginsn_next));
5897
0
  ginsn_last = ginsn_new_mov (insn_end_sym, false,
5898
0
            GINSN_SRC_REG, REG_SP, 0,
5899
0
            GINSN_DST_REG, REG_FP, 0);
5900
0
  ginsn_set_where (ginsn_last);
5901
0
  gas_assert (!ginsn_link_next (ginsn_next, ginsn_last));
5902
5903
0
  return ginsn;
5904
0
}
5905
5906
static ginsnS *
5907
x86_ginsn_leave (const symbolS *insn_end_sym)
5908
0
{
5909
0
  ginsnS *ginsn = NULL;
5910
0
  ginsnS *ginsn_next = NULL;
5911
0
  ginsnS *ginsn_last = NULL;
5912
  /* In 64-bit mode, the default stack update size is 8 bytes.  */
5913
0
  int stack_opnd_size = 8;
5914
5915
  /* Check if this is a 16-bit op.  */
5916
0
  if (ginsn_opsize_prefix_p ())
5917
0
    stack_opnd_size = 2;
5918
5919
  /* The 'leave' instruction copies the contents of the RBP register
5920
     into the RSP register to release all stack space allocated to the
5921
     procedure.  */
5922
0
  ginsn = ginsn_new_mov (insn_end_sym, false,
5923
0
       GINSN_SRC_REG, REG_FP, 0,
5924
0
       GINSN_DST_REG, REG_SP, 0);
5925
0
  ginsn_set_where (ginsn);
5926
  /* Then it restores the old value of the RBP register from the stack.  */
5927
0
  ginsn_next = ginsn_new_load (insn_end_sym, false,
5928
0
             GINSN_SRC_INDIRECT, REG_SP, 0,
5929
0
             GINSN_DST_REG, REG_FP);
5930
0
  ginsn_set_where (ginsn_next);
5931
0
  gas_assert (!ginsn_link_next (ginsn, ginsn_next));
5932
0
  ginsn_last = ginsn_new_add (insn_end_sym, false,
5933
0
            GINSN_SRC_REG, REG_SP, 0,
5934
0
            GINSN_SRC_IMM, 0, stack_opnd_size,
5935
0
            GINSN_DST_REG, REG_SP, 0);
5936
0
  ginsn_set_where (ginsn_next);
5937
0
  gas_assert (!ginsn_link_next (ginsn_next, ginsn_last));
5938
5939
0
  return ginsn;
5940
0
}
5941
5942
/* Check if an instruction is whitelisted.
5943
5944
   Some instructions may appear with REG_SP or REG_FP as destination, because
5945
   which they are deemed 'interesting' for SCFI.  Whitelist them here if they
5946
   do not affect SCFI correctness.  */
5947
5948
static bool
5949
x86_ginsn_safe_to_skip_p (void)
5950
0
{
5951
0
  bool skip_p = false;
5952
0
  uint16_t opcode = i.tm.base_opcode;
5953
5954
0
  switch (opcode)
5955
0
    {
5956
0
    case 0x80:
5957
0
    case 0x81:
5958
0
    case 0x83:
5959
0
      if (i.tm.opcode_space != SPACE_BASE)
5960
0
  break;
5961
      /* cmp imm, reg/rem.  */
5962
0
      if (i.tm.extension_opcode == 7)
5963
0
  skip_p = true;
5964
0
      break;
5965
5966
0
    case 0x38:
5967
0
    case 0x39:
5968
0
    case 0x3a:
5969
0
    case 0x3b:
5970
0
      if (i.tm.opcode_space != SPACE_BASE)
5971
0
  break;
5972
      /* cmp imm/reg/mem, reg/rem.  */
5973
0
      skip_p = true;
5974
0
      break;
5975
5976
0
    case 0xf6:
5977
0
    case 0xf7:
5978
0
    case 0x84:
5979
0
    case 0x85:
5980
      /* test imm/reg/mem, reg/mem.  */
5981
0
      if (i.tm.opcode_space != SPACE_BASE)
5982
0
  break;
5983
0
      skip_p = true;
5984
0
      break;
5985
5986
0
    default:
5987
0
      break;
5988
0
    }
5989
5990
0
  return skip_p;
5991
0
}
5992
5993
0
#define X86_GINSN_UNHANDLED_NONE        0
5994
0
#define X86_GINSN_UNHANDLED_DEST_REG    1
5995
0
#define X86_GINSN_UNHANDLED_CFG         2
5996
0
#define X86_GINSN_UNHANDLED_STACKOP     3
5997
0
#define X86_GINSN_UNHANDLED_UNEXPECTED  4
5998
5999
/* Check the input insn for its impact on the correctness of the synthesized
6000
   CFI.  Returns an error code to the caller.  */
6001
6002
static int
6003
x86_ginsn_unhandled (void)
6004
0
{
6005
0
  int err = X86_GINSN_UNHANDLED_NONE;
6006
0
  const reg_entry *reg_op;
6007
0
  unsigned int dw2_regnum;
6008
6009
  /* Keep an eye out for instructions affecting control flow.  */
6010
0
  if (i.tm.opcode_modifier.jump)
6011
0
    err = X86_GINSN_UNHANDLED_CFG;
6012
  /* Also, for any instructions involving an implicit update to the stack
6013
     pointer.  */
6014
0
  else if (i.tm.opcode_modifier.operandconstraint == IMPLICIT_STACK_OP)
6015
0
    err = X86_GINSN_UNHANDLED_STACKOP;
6016
  /* Finally, also check if the missed instructions are affecting REG_SP or
6017
     REG_FP.  The destination operand is the last at all stages of assembly
6018
     (due to following AT&T syntax layout in the internal representation).  In
6019
     case of Intel syntax input, this still remains true as swap_operands ()
6020
     is done by now.
6021
     PS: These checks do not involve index / base reg, as indirect memory
6022
     accesses via REG_SP or REG_FP do not affect SCFI correctness.
6023
     (Also note these instructions are candidates for other ginsn generation
6024
     modes in future.  TBD_GINSN_GEN_NOT_SCFI.)  */
6025
0
  else if (i.operands && i.reg_operands
6026
0
     && !(i.flags[i.operands - 1] & Operand_Mem))
6027
0
    {
6028
0
      reg_op = i.op[i.operands - 1].regs;
6029
0
      if (reg_op)
6030
0
  {
6031
0
    dw2_regnum = ginsn_dw2_regnum (reg_op);
6032
0
    if (dw2_regnum == REG_SP || dw2_regnum == REG_FP)
6033
0
      err = X86_GINSN_UNHANDLED_DEST_REG;
6034
0
  }
6035
0
      else
6036
  /* Something unexpected.  Indicate to caller.  */
6037
0
  err = X86_GINSN_UNHANDLED_UNEXPECTED;
6038
0
    }
6039
6040
0
  return err;
6041
0
}
6042
6043
/* Generate one or more generic GAS instructions, a.k.a, ginsns for the current
6044
   machine instruction.
6045
6046
   Returns the head of linked list of ginsn(s) added, if success; Returns NULL
6047
   if failure.
6048
6049
   The input ginsn_gen_mode GMODE determines the set of minimal necessary
6050
   ginsns necessary for correctness of any passes applicable for that mode.
6051
   For supporting the GINSN_GEN_SCFI generation mode, following is the list of
6052
   machine instructions that must be translated into the corresponding ginsns
6053
   to ensure correctness of SCFI:
6054
     - All instructions affecting the two registers that could potentially
6055
       be used as the base register for CFA tracking.  For SCFI, the base
6056
       register for CFA tracking is limited to REG_SP and REG_FP only for
6057
       now.
6058
     - All change of flow instructions: conditional and unconditional branches,
6059
       call and return from functions.
6060
     - All instructions that can potentially be a register save / restore
6061
       operation.
6062
     - All instructions that perform stack manipulation implicitly: the CALL,
6063
       RET, PUSH, POP, ENTER, and LEAVE instructions.
6064
6065
   The function currently supports GINSN_GEN_SCFI ginsn generation mode only.
6066
   To support other generation modes will require work on this target-specific
6067
   process of creation of ginsns:
6068
     - Some of such places are tagged with TBD_GINSN_GEN_NOT_SCFI to serve as
6069
       possible starting points.
6070
     - Also note that ginsn representation may need enhancements.  Specifically,
6071
       note some TBD_GINSN_INFO_LOSS and TBD_GINSN_REPRESENTATION_LIMIT markers.
6072
   */
6073
6074
static ginsnS *
6075
x86_ginsn_new (const symbolS *insn_end_sym, enum ginsn_gen_mode gmode)
6076
0
{
6077
0
  int err = 0;
6078
0
  uint16_t opcode;
6079
0
  unsigned int dw2_regnum;
6080
0
  const reg_entry *mem_reg;
6081
0
  ginsnS *ginsn = NULL;
6082
0
  ginsnS *ginsn_next = NULL;
6083
  /* In 64-bit mode, the default stack update size is 8 bytes.  */
6084
0
  int stack_opnd_size = 8;
6085
6086
  /* Currently supports generation of selected ginsns, sufficient for
6087
     the use-case of SCFI only.  */
6088
0
  if (gmode != GINSN_GEN_SCFI)
6089
0
    return ginsn;
6090
6091
0
  opcode = i.tm.base_opcode;
6092
6093
  /* Until it is clear how to handle APX NDD and other new opcodes, disallow
6094
     them from SCFI.  */
6095
0
  if (is_apx_rex2_encoding ()
6096
0
      || (i.tm.opcode_modifier.evex && is_apx_evex_encoding ()))
6097
0
    {
6098
0
      as_bad (_("SCFI: unsupported APX op %#x may cause incorrect CFI"),
6099
0
        opcode);
6100
0
      return ginsn;
6101
0
    }
6102
6103
0
  switch (opcode)
6104
0
    {
6105
6106
    /* Add opcodes 0x0/0x2 and sub opcodes 0x28/0x2a (with opcode_space
6107
       SPACE_BASE) are 8-bit ops.  While they are relevant for SCFI
6108
       correctness,  skip handling them here and use the x86_ginsn_unhandled
6109
       code path to generate GINSN_TYPE_OTHER when necessary.  */
6110
6111
0
    case 0x1:  /* add reg, reg/mem.  */
6112
0
    case 0x29: /* sub reg, reg/mem.  */
6113
0
      if (i.tm.opcode_space != SPACE_BASE)
6114
0
  break;
6115
0
      ginsn = x86_ginsn_addsub_reg_mem (insn_end_sym);
6116
0
      break;
6117
6118
0
    case 0x3:  /* add reg/mem, reg.  */
6119
0
    case 0x2b: /* sub reg/mem, reg.  */
6120
0
      if (i.tm.opcode_space != SPACE_BASE)
6121
0
  break;
6122
0
      ginsn = x86_ginsn_addsub_mem_reg (insn_end_sym);
6123
0
      break;
6124
6125
0
    case 0xa0: /* push fs.  */
6126
0
    case 0xa8: /* push gs.  */
6127
      /* push fs / push gs have opcode_space == SPACE_0F.  */
6128
0
      if (i.tm.opcode_space != SPACE_0F)
6129
0
  break;
6130
0
      dw2_regnum = ginsn_dw2_regnum (i.op[0].regs);
6131
      /* Check if operation size is 16-bit.  */
6132
0
      if (ginsn_opsize_prefix_p ())
6133
0
  stack_opnd_size = 2;
6134
0
      ginsn = ginsn_new_sub (insn_end_sym, false,
6135
0
           GINSN_SRC_REG, REG_SP, 0,
6136
0
           GINSN_SRC_IMM, 0, stack_opnd_size,
6137
0
           GINSN_DST_REG, REG_SP, 0);
6138
0
      ginsn_set_where (ginsn);
6139
0
      ginsn_next = ginsn_new_store (insn_end_sym, false,
6140
0
            GINSN_SRC_REG, dw2_regnum,
6141
0
            GINSN_DST_INDIRECT, REG_SP, 0);
6142
0
      ginsn_set_where (ginsn_next);
6143
0
      gas_assert (!ginsn_link_next (ginsn, ginsn_next));
6144
0
      break;
6145
6146
0
    case 0xa1: /* pop fs.  */
6147
0
    case 0xa9: /* pop gs.  */
6148
      /* pop fs / pop gs have opcode_space == SPACE_0F.  */
6149
0
      if (i.tm.opcode_space != SPACE_0F)
6150
0
  break;
6151
0
      dw2_regnum = ginsn_dw2_regnum (i.op[0].regs);
6152
      /* Check if operation size is 16-bit.  */
6153
0
      if (ginsn_opsize_prefix_p ())
6154
0
  stack_opnd_size = 2;
6155
0
      ginsn = ginsn_new_load (insn_end_sym, false,
6156
0
            GINSN_SRC_INDIRECT, REG_SP, 0,
6157
0
            GINSN_DST_REG, dw2_regnum);
6158
0
      ginsn_set_where (ginsn);
6159
0
      ginsn_next = ginsn_new_add (insn_end_sym, false,
6160
0
          GINSN_SRC_REG, REG_SP, 0,
6161
0
          GINSN_SRC_IMM, 0, stack_opnd_size,
6162
0
          GINSN_DST_REG, REG_SP, 0);
6163
0
      ginsn_set_where (ginsn_next);
6164
0
      gas_assert (!ginsn_link_next (ginsn, ginsn_next));
6165
0
      break;
6166
6167
0
    case 0x50 ... 0x57:
6168
0
      if (i.tm.opcode_space != SPACE_BASE)
6169
0
  break;
6170
      /* push reg.  */
6171
0
      dw2_regnum = ginsn_dw2_regnum (i.op[0].regs);
6172
      /* Check if operation size is 16-bit.  */
6173
0
      if (ginsn_opsize_prefix_p ())
6174
0
  stack_opnd_size = 2;
6175
0
      ginsn = ginsn_new_sub (insn_end_sym, false,
6176
0
           GINSN_SRC_REG, REG_SP, 0,
6177
0
           GINSN_SRC_IMM, 0, stack_opnd_size,
6178
0
           GINSN_DST_REG, REG_SP, 0);
6179
0
      ginsn_set_where (ginsn);
6180
0
      ginsn_next = ginsn_new_store (insn_end_sym, false,
6181
0
            GINSN_SRC_REG, dw2_regnum,
6182
0
            GINSN_DST_INDIRECT, REG_SP, 0);
6183
0
      ginsn_set_where (ginsn_next);
6184
0
      gas_assert (!ginsn_link_next (ginsn, ginsn_next));
6185
0
      break;
6186
6187
0
    case 0x58 ... 0x5f:
6188
0
      if (i.tm.opcode_space != SPACE_BASE)
6189
0
  break;
6190
      /* pop reg.  */
6191
0
      dw2_regnum = ginsn_dw2_regnum (i.op[0].regs);
6192
0
      ginsn = ginsn_new_load (insn_end_sym, false,
6193
0
            GINSN_SRC_INDIRECT, REG_SP, 0,
6194
0
            GINSN_DST_REG, dw2_regnum);
6195
0
      ginsn_set_where (ginsn);
6196
      /* Check if operation size is 16-bit.  */
6197
0
      if (ginsn_opsize_prefix_p ())
6198
0
  stack_opnd_size = 2;
6199
0
      ginsn_next = ginsn_new_add (insn_end_sym, false,
6200
0
          GINSN_SRC_REG, REG_SP, 0,
6201
0
          GINSN_SRC_IMM, 0, stack_opnd_size,
6202
0
          GINSN_DST_REG, REG_SP, 0);
6203
0
      ginsn_set_where (ginsn_next);
6204
0
      gas_assert (!ginsn_link_next (ginsn, ginsn_next));
6205
0
      break;
6206
6207
0
    case 0x6a: /* push imm8.  */
6208
0
    case 0x68: /* push imm16/imm32.  */
6209
0
      if (i.tm.opcode_space != SPACE_BASE)
6210
0
  break;
6211
      /* Check if operation size is 16-bit.  */
6212
0
      if (ginsn_opsize_prefix_p ())
6213
0
  stack_opnd_size = 2;
6214
      /* Skip getting the value of imm from machine instruction
6215
   because this is not important for SCFI.  */
6216
0
      ginsn = ginsn_new_sub (insn_end_sym, false,
6217
0
           GINSN_SRC_REG, REG_SP, 0,
6218
0
           GINSN_SRC_IMM, 0, stack_opnd_size,
6219
0
           GINSN_DST_REG, REG_SP, 0);
6220
0
      ginsn_set_where (ginsn);
6221
0
      ginsn_next = ginsn_new_store (insn_end_sym, false,
6222
0
            GINSN_SRC_IMM, 0,
6223
0
            GINSN_DST_INDIRECT, REG_SP, 0);
6224
0
      ginsn_set_where (ginsn_next);
6225
0
      gas_assert (!ginsn_link_next (ginsn, ginsn_next));
6226
0
      break;
6227
6228
    /* PS: Opcodes 0x80 ... 0x8f with opcode_space SPACE_0F are present
6229
       only after relaxation.  They do not need to be handled for ginsn
6230
       creation.  */
6231
0
    case 0x70 ... 0x7f:
6232
0
      if (i.tm.opcode_space != SPACE_BASE)
6233
0
  break;
6234
0
      ginsn = x86_ginsn_jump (insn_end_sym, true);
6235
0
      break;
6236
6237
0
    case 0x80:
6238
0
    case 0x81:
6239
0
    case 0x83:
6240
0
      if (i.tm.opcode_space != SPACE_BASE)
6241
0
  break;
6242
0
      ginsn = x86_ginsn_alu_imm (insn_end_sym);
6243
0
      break;
6244
6245
0
    case 0x8a: /* mov r/m8, r8.  */
6246
0
    case 0x8b: /* mov r/m(16/32/64), r(16/32/64).  */
6247
0
    case 0x88: /* mov r8, r/m8.  */
6248
0
    case 0x89: /* mov r(16/32/64), r/m(16/32/64).  */
6249
0
      if (i.tm.opcode_space != SPACE_BASE)
6250
0
  break;
6251
0
      ginsn = x86_ginsn_move (insn_end_sym);
6252
0
      break;
6253
6254
0
    case 0x8d:
6255
0
      if (i.tm.opcode_space != SPACE_BASE)
6256
0
  break;
6257
      /* lea disp(%base,%index,imm), %dst.  */
6258
0
      ginsn = x86_ginsn_lea (insn_end_sym);
6259
0
      break;
6260
6261
0
    case 0x8f:
6262
0
      if (i.tm.opcode_space != SPACE_BASE)
6263
0
  break;
6264
      /* pop to reg/mem.  */
6265
0
      if (i.mem_operands)
6266
0
  {
6267
0
    mem_reg = (i.base_reg) ? i.base_reg : i.index_reg;
6268
    /* Use dummy register if no base or index.  Unlike other opcodes,
6269
       ginsns must be generated as this affect stack pointer.  */
6270
0
    dw2_regnum = (mem_reg
6271
0
      ? ginsn_dw2_regnum (mem_reg)
6272
0
      : GINSN_DW2_REGNUM_RSI_DUMMY);
6273
0
  }
6274
0
      else
6275
0
  dw2_regnum = ginsn_dw2_regnum (i.op[0].regs);
6276
0
      ginsn = ginsn_new_load (insn_end_sym, false,
6277
0
            GINSN_SRC_INDIRECT, REG_SP, 0,
6278
0
            GINSN_DST_INDIRECT, dw2_regnum);
6279
0
      ginsn_set_where (ginsn);
6280
      /* Check if operation size is 16-bit.  */
6281
0
      if (ginsn_opsize_prefix_p ())
6282
0
  stack_opnd_size = 2;
6283
0
      ginsn_next = ginsn_new_add (insn_end_sym, false,
6284
0
          GINSN_SRC_REG, REG_SP, 0,
6285
0
          GINSN_SRC_IMM, 0, stack_opnd_size,
6286
0
          GINSN_DST_REG, REG_SP, 0);
6287
0
      ginsn_set_where (ginsn_next);
6288
0
      gas_assert (!ginsn_link_next (ginsn, ginsn_next));
6289
0
      break;
6290
6291
0
    case 0x9c:
6292
0
      if (i.tm.opcode_space != SPACE_BASE)
6293
0
  break;
6294
      /* pushf / pushfq.  */
6295
      /* Check if operation size is 16-bit.  */
6296
0
      if (ginsn_opsize_prefix_p ())
6297
0
  stack_opnd_size = 2;
6298
0
      ginsn = ginsn_new_sub (insn_end_sym, false,
6299
0
           GINSN_SRC_REG, REG_SP, 0,
6300
0
           GINSN_SRC_IMM, 0, stack_opnd_size,
6301
0
           GINSN_DST_REG, REG_SP, 0);
6302
0
      ginsn_set_where (ginsn);
6303
      /* FIXME - hardcode the actual DWARF reg number value.  As for SCFI
6304
   correctness, although this behaves simply a placeholder value; its
6305
   just clearer if the value is correct.  */
6306
0
      dw2_regnum = GINSN_DW2_REGNUM_EFLAGS;
6307
0
      ginsn_next = ginsn_new_store (insn_end_sym, false,
6308
0
            GINSN_SRC_REG, dw2_regnum,
6309
0
            GINSN_DST_INDIRECT, REG_SP, 0);
6310
0
      ginsn_set_where (ginsn_next);
6311
0
      gas_assert (!ginsn_link_next (ginsn, ginsn_next));
6312
0
      break;
6313
6314
0
    case 0x9d:
6315
0
      if (i.tm.opcode_space != SPACE_BASE)
6316
0
  break;
6317
      /* popf / popfq.  */
6318
      /* Check if operation size is 16-bit.  */
6319
0
      if (ginsn_opsize_prefix_p ())
6320
0
  stack_opnd_size = 2;
6321
      /* FIXME - hardcode the actual DWARF reg number value.  As for SCFI
6322
   correctness, although this behaves simply a placeholder value; its
6323
   just clearer if the value is correct.  */
6324
0
      dw2_regnum = GINSN_DW2_REGNUM_EFLAGS;
6325
0
      ginsn = ginsn_new_load (insn_end_sym, false,
6326
0
            GINSN_SRC_INDIRECT, REG_SP, 0,
6327
0
            GINSN_DST_REG, dw2_regnum);
6328
0
      ginsn_set_where (ginsn);
6329
0
      ginsn_next = ginsn_new_add (insn_end_sym, false,
6330
0
          GINSN_SRC_REG, REG_SP, 0,
6331
0
          GINSN_SRC_IMM, 0, stack_opnd_size,
6332
0
          GINSN_DST_REG, REG_SP, 0);
6333
0
      ginsn_set_where (ginsn_next);
6334
0
      gas_assert (!ginsn_link_next (ginsn, ginsn_next));
6335
0
      break;
6336
6337
0
    case 0xff:
6338
0
      if (i.tm.opcode_space != SPACE_BASE)
6339
0
  break;
6340
      /* push from reg/mem.  */
6341
0
      if (i.tm.extension_opcode == 6)
6342
0
  {
6343
    /* Check if operation size is 16-bit.  */
6344
0
    if (ginsn_opsize_prefix_p ())
6345
0
      stack_opnd_size = 2;
6346
0
    ginsn = ginsn_new_sub (insn_end_sym, false,
6347
0
         GINSN_SRC_REG, REG_SP, 0,
6348
0
         GINSN_SRC_IMM, 0, stack_opnd_size,
6349
0
         GINSN_DST_REG, REG_SP, 0);
6350
0
    ginsn_set_where (ginsn);
6351
0
    if (i.mem_operands)
6352
0
      {
6353
0
        mem_reg = (i.base_reg) ? i.base_reg : i.index_reg;
6354
        /* Use dummy register if no base or index.  Unlike other opcodes,
6355
     ginsns must be generated as this affect stack pointer.  */
6356
0
        dw2_regnum = (mem_reg
6357
0
          ? ginsn_dw2_regnum (mem_reg)
6358
0
          : GINSN_DW2_REGNUM_RSI_DUMMY);
6359
0
      }
6360
0
    else
6361
0
      dw2_regnum = ginsn_dw2_regnum (i.op[0].regs);
6362
0
    ginsn_next = ginsn_new_store (insn_end_sym, false,
6363
0
          GINSN_SRC_INDIRECT, dw2_regnum,
6364
0
          GINSN_DST_INDIRECT, REG_SP, 0);
6365
0
    ginsn_set_where (ginsn_next);
6366
0
    gas_assert (!ginsn_link_next (ginsn, ginsn_next));
6367
0
  }
6368
0
      else if (i.tm.extension_opcode == 4)
6369
0
  {
6370
    /* jmp r/m.  E.g., notrack jmp *%rax.  */
6371
0
    if (i.reg_operands)
6372
0
      {
6373
0
        dw2_regnum = ginsn_dw2_regnum (i.op[0].regs);
6374
0
        ginsn = ginsn_new_jump (insn_end_sym, true,
6375
0
              GINSN_SRC_REG, dw2_regnum, NULL);
6376
0
        ginsn_set_where (ginsn);
6377
0
      }
6378
0
    else if (i.mem_operands && i.index_reg)
6379
0
      {
6380
        /* jmp    *0x0(,%rax,8).  */
6381
0
        dw2_regnum = ginsn_dw2_regnum (i.index_reg);
6382
0
        ginsn = ginsn_new_jump (insn_end_sym, true,
6383
0
              GINSN_SRC_REG, dw2_regnum, NULL);
6384
0
        ginsn_set_where (ginsn);
6385
0
      }
6386
0
    else if (i.mem_operands && i.base_reg)
6387
0
      {
6388
0
        dw2_regnum = ginsn_dw2_regnum (i.base_reg);
6389
0
        ginsn = ginsn_new_jump (insn_end_sym, true,
6390
0
              GINSN_SRC_REG, dw2_regnum, NULL);
6391
0
        ginsn_set_where (ginsn);
6392
0
      }
6393
0
  }
6394
0
      else if (i.tm.extension_opcode == 2)
6395
0
  {
6396
    /* 0xFF /2 (call).  */
6397
0
    if (i.reg_operands)
6398
0
      {
6399
0
        dw2_regnum = ginsn_dw2_regnum (i.op[0].regs);
6400
0
        ginsn = ginsn_new_call (insn_end_sym, true,
6401
0
              GINSN_SRC_REG, dw2_regnum, NULL);
6402
0
        ginsn_set_where (ginsn);
6403
0
      }
6404
0
    else if (i.mem_operands && i.base_reg)
6405
0
      {
6406
0
        dw2_regnum = ginsn_dw2_regnum (i.base_reg);
6407
0
        ginsn = ginsn_new_call (insn_end_sym, true,
6408
0
              GINSN_SRC_REG, dw2_regnum, NULL);
6409
0
        ginsn_set_where (ginsn);
6410
0
      }
6411
0
  }
6412
0
      break;
6413
6414
0
    case 0xc2: /* ret imm16.  */
6415
0
    case 0xc3: /* ret.  */
6416
0
      if (i.tm.opcode_space != SPACE_BASE)
6417
0
  break;
6418
      /* Near ret.  */
6419
0
      ginsn = ginsn_new_return (insn_end_sym, true);
6420
0
      ginsn_set_where (ginsn);
6421
0
      break;
6422
6423
0
    case 0xc8:
6424
0
      if (i.tm.opcode_space != SPACE_BASE)
6425
0
  break;
6426
      /* enter.  */
6427
0
      ginsn = x86_ginsn_enter (insn_end_sym);
6428
0
      break;
6429
6430
0
    case 0xc9:
6431
0
      if (i.tm.opcode_space != SPACE_BASE)
6432
0
  break;
6433
      /* leave.  */
6434
0
      ginsn = x86_ginsn_leave (insn_end_sym);
6435
0
      break;
6436
6437
0
    case 0xe0 ... 0xe2: /* loop / loope / loopne.  */
6438
0
    case 0xe3:          /* jecxz / jrcxz.  */
6439
0
      if (i.tm.opcode_space != SPACE_BASE)
6440
0
  break;
6441
0
      ginsn = x86_ginsn_jump (insn_end_sym, true);
6442
0
      ginsn_set_where (ginsn);
6443
0
      break;
6444
6445
0
    case 0xe8:
6446
0
      if (i.tm.opcode_space != SPACE_BASE)
6447
0
  break;
6448
      /* PS: SCFI machinery does not care about which func is being
6449
   called.  OK to skip that info.  */
6450
0
      ginsn = ginsn_new_call (insn_end_sym, true,
6451
0
            GINSN_SRC_SYMBOL, 0, NULL);
6452
0
      ginsn_set_where (ginsn);
6453
0
      break;
6454
6455
    /* PS: opcode 0xe9 appears only after relaxation.  Skip here.  */
6456
0
    case 0xeb:
6457
      /* If opcode_space != SPACE_BASE, this is not a jmp insn.  Skip it
6458
   for GINSN_GEN_SCFI.  */
6459
0
      if (i.tm.opcode_space != SPACE_BASE)
6460
0
  break;
6461
      /* Unconditional jmp.  */
6462
0
      ginsn = x86_ginsn_jump (insn_end_sym, false);
6463
0
      ginsn_set_where (ginsn);
6464
0
      break;
6465
6466
0
    default:
6467
      /* TBD_GINSN_GEN_NOT_SCFI: Skip all other opcodes uninteresting for
6468
   GINSN_GEN_SCFI mode.  */
6469
0
      break;
6470
0
    }
6471
6472
0
  if (!ginsn && !x86_ginsn_safe_to_skip_p ())
6473
0
    {
6474
      /* For all unhandled insns that are not whitelisted, check that they do
6475
   not impact SCFI correctness.  */
6476
0
      err = x86_ginsn_unhandled ();
6477
0
      switch (err)
6478
0
  {
6479
0
  case X86_GINSN_UNHANDLED_NONE:
6480
0
    break;
6481
0
  case X86_GINSN_UNHANDLED_DEST_REG:
6482
    /* Not all writes to REG_FP are harmful in context of SCFI.  Simply
6483
       generate a GINSN_TYPE_OTHER with destination set to the
6484
       appropriate register.  The SCFI machinery will bail out if this
6485
       ginsn affects SCFI correctness.  */
6486
0
    dw2_regnum = ginsn_dw2_regnum (i.op[i.operands - 1].regs);
6487
0
    ginsn = ginsn_new_other (insn_end_sym, true,
6488
0
           GINSN_SRC_IMM, 0,
6489
0
           GINSN_SRC_IMM, 0,
6490
0
           GINSN_DST_REG, dw2_regnum);
6491
0
    ginsn_set_where (ginsn);
6492
0
    break;
6493
0
  case X86_GINSN_UNHANDLED_CFG:
6494
0
  case X86_GINSN_UNHANDLED_STACKOP:
6495
0
    as_bad (_("SCFI: unhandled op %#x may cause incorrect CFI"), opcode);
6496
0
    break;
6497
0
  case X86_GINSN_UNHANDLED_UNEXPECTED:
6498
0
    as_bad (_("SCFI: unexpected op %#x may cause incorrect CFI"),
6499
0
      opcode);
6500
0
    break;
6501
0
  default:
6502
0
    abort ();
6503
0
    break;
6504
0
  }
6505
0
    }
6506
6507
0
  return ginsn;
6508
0
}
6509
6510
#endif
6511
6512
/* This is the guts of the machine-dependent assembler.  LINE points to a
6513
   machine dependent instruction.  This function is supposed to emit
6514
   the frags/bytes it assembles to.  */
6515
6516
void
6517
md_assemble (char *line)
6518
1.90M
{
6519
1.90M
  unsigned int j;
6520
1.90M
  char mnemonic[MAX_MNEM_SIZE], mnem_suffix = 0, *copy = NULL;
6521
1.90M
  char *xstrdup_copy = NULL;
6522
1.90M
  const char *end, *pass1_mnem = NULL;
6523
1.90M
  enum i386_error pass1_err = 0;
6524
1.90M
  const insn_template *t;
6525
1.90M
  struct last_insn *last_insn
6526
1.90M
    = &seg_info(now_seg)->tc_segment_info_data.last_insn;
6527
6528
  /* Initialize globals.  */
6529
1.90M
  current_templates.end = current_templates.start = NULL;
6530
1.90M
 retry:
6531
1.90M
  init_globals ();
6532
6533
  /* Suppress optimization when the last thing we saw may not have been
6534
     a proper instruction (e.g. a stand-alone prefix or .byte).  */
6535
1.90M
  if (last_insn->kind != last_insn_other)
6536
291k
    i.no_optimize = true;
6537
6538
  /* First parse an instruction mnemonic & call i386_operand for the operands.
6539
     We assume that the scrubber has arranged it so that line[0] is the valid
6540
     start of a (possibly prefixed) mnemonic.  */
6541
6542
1.90M
  end = parse_insn (line, mnemonic, false);
6543
1.90M
  if (end == NULL)
6544
1.15M
    {
6545
1.15M
      if (pass1_mnem != NULL)
6546
582
  goto match_error;
6547
1.15M
      if (i.error != no_error)
6548
15.2k
  {
6549
15.2k
    gas_assert (current_templates.start != NULL);
6550
15.2k
    if (may_need_pass2 (current_templates.start) && !i.suffix)
6551
2
      goto no_match;
6552
    /* No point in trying a 2nd pass - it'll only find the same suffix
6553
       again.  */
6554
15.2k
    mnem_suffix = i.suffix;
6555
15.2k
    goto match_error;
6556
15.2k
  }
6557
1.14M
      return;
6558
1.15M
    }
6559
747k
  t = current_templates.start;
6560
  /* NB: LINE may be change to be the same as XSTRDUP_COPY.  */
6561
747k
  if (xstrdup_copy != line && may_need_pass2 (t))
6562
4.14k
    {
6563
      /* Make a copy of the full line in case we need to retry.  */
6564
4.14k
      xstrdup_copy = xstrdup (line);
6565
4.14k
      copy = xstrdup_copy;
6566
4.14k
    }
6567
747k
  line += end - line;
6568
747k
  mnem_suffix = i.suffix;
6569
6570
747k
  line = parse_operands (line, mnemonic);
6571
747k
  this_operand = -1;
6572
747k
  if (line == NULL)
6573
50.6k
    {
6574
50.6k
      free (xstrdup_copy);
6575
50.6k
      return;
6576
50.6k
    }
6577
6578
  /* Now we've parsed the mnemonic into a set of templates, and have the
6579
     operands at hand.  */
6580
6581
  /* All Intel opcodes have reversed operands except for "bound", "enter",
6582
     "invlpg*", "monitor*", "mwait*", "tpause", "umwait", "pvalidate",
6583
     "rmpadjust", "rmpupdate", and "rmpquery".  We also don't reverse
6584
     intersegment "jmp" and "call" instructions with 2 immediate operands so
6585
     that the immediate segment precedes the offset consistently in Intel and
6586
     AT&T modes.  */
6587
696k
  if (intel_syntax
6588
696k
      && i.operands > 1
6589
696k
      && (t->mnem_off != MN_bound)
6590
696k
      && !startswith (mnemonic, "invlpg")
6591
696k
      && !startswith (mnemonic, "monitor")
6592
696k
      && !startswith (mnemonic, "mwait")
6593
696k
      && (t->mnem_off != MN_pvalidate)
6594
696k
      && !startswith (mnemonic, "rmp")
6595
696k
      && (t->mnem_off != MN_tpause)
6596
696k
      && (t->mnem_off != MN_umwait)
6597
696k
      && !(i.operands == 2
6598
0
     && operand_type_check (i.types[0], imm)
6599
0
     && operand_type_check (i.types[1], imm)))
6600
0
    swap_operands ();
6601
6602
  /* The order of the immediates should be reversed for 2-immediates EXTRQ
6603
     and INSERTQ instructions.  Also UWRMSR wants its immediate to be in the
6604
     "canonical" place (first), despite it appearing last (in AT&T syntax, or
6605
     because of the swapping above) in the incoming set of operands.  */
6606
696k
  if ((i.imm_operands == 2
6607
696k
       && (t->mnem_off == MN_extrq || t->mnem_off == MN_insertq))
6608
696k
      || (t->mnem_off == MN_uwrmsr && i.imm_operands
6609
696k
    && i.operands > i.imm_operands))
6610
0
      swap_2_operands (0, 1);
6611
6612
696k
  if (i.imm_operands)
6613
31.3k
    {
6614
      /* For USER_MSR instructions, imm32 stands for the name of an model specific
6615
   register (MSR). That's an unsigned quantity, whereas all other insns with
6616
   32-bit immediate and 64-bit operand size use sign-extended
6617
   immediates (imm32s). Therefore these insns are special-cased, bypassing
6618
   the normal handling of immediates here.  */
6619
31.3k
      if (is_cpu(current_templates.start, CpuUSER_MSR))
6620
0
  {
6621
0
    for (j = 0; j < i.operands; j++)
6622
0
      {
6623
0
        if (operand_type_check(i.types[j], imm))
6624
0
    i.types[j] = smallest_imm_type (i.op[j].imms->X_add_number);
6625
0
      }
6626
0
  }
6627
31.3k
      else
6628
31.3k
  optimize_imm ();
6629
31.3k
    }
6630
6631
696k
  if (i.disp_operands && !optimize_disp (t))
6632
0
    return;
6633
6634
  /* Next, we find a template that matches the given insn,
6635
     making sure the overlap of the given operands types is consistent
6636
     with the template operand types.  */
6637
6638
696k
  if (!(t = match_template (mnem_suffix)))
6639
34.1k
    {
6640
34.1k
      const char *err_msg;
6641
6642
34.1k
      if (copy && !mnem_suffix)
6643
594
  {
6644
594
    line = copy;
6645
594
    copy = NULL;
6646
596
  no_match:
6647
596
    pass1_err = i.error;
6648
596
    pass1_mnem = insn_name (current_templates.start);
6649
596
    goto retry;
6650
594
  }
6651
6652
      /* If a non-/only-64bit template (group) was found in pass 1, and if
6653
   _some_ template (group) was found in pass 2, squash pass 1's
6654
   error.  */
6655
33.5k
      if (pass1_err == unsupported_64bit)
6656
0
  pass1_mnem = NULL;
6657
6658
49.3k
  match_error:
6659
49.3k
      free (xstrdup_copy);
6660
6661
49.3k
      switch (pass1_mnem ? pass1_err : i.error)
6662
49.3k
  {
6663
0
  default:
6664
0
    abort ();
6665
3.03k
  case operand_size_mismatch:
6666
3.03k
    err_msg = _("operand size mismatch");
6667
3.03k
    break;
6668
493
  case operand_type_mismatch:
6669
493
    err_msg = _("operand type mismatch");
6670
493
    break;
6671
0
  case register_type_mismatch:
6672
0
    err_msg = _("register type mismatch");
6673
0
    break;
6674
14.4k
  case number_of_operands_mismatch:
6675
14.4k
    err_msg = _("number of operands mismatch");
6676
14.4k
    break;
6677
15.9k
  case invalid_instruction_suffix:
6678
15.9k
    err_msg = _("invalid instruction suffix");
6679
15.9k
    break;
6680
0
  case bad_imm4:
6681
0
    err_msg = _("constant doesn't fit in 4 bits");
6682
0
    break;
6683
0
  case unsupported_with_intel_mnemonic:
6684
0
    err_msg = _("unsupported with Intel mnemonic");
6685
0
    break;
6686
0
  case unsupported_syntax:
6687
0
    err_msg = _("unsupported syntax");
6688
0
    break;
6689
0
  case unsupported_EGPR_for_addressing:
6690
0
    err_msg = _("extended GPR cannot be used as base/index");
6691
0
    break;
6692
0
  case unsupported_nf:
6693
0
    err_msg = _("{nf} unsupported");
6694
0
    break;
6695
179
  case unsupported:
6696
179
    as_bad (_("unsupported instruction `%s'"),
6697
179
      pass1_mnem ? pass1_mnem : insn_name (current_templates.start));
6698
179
    return;
6699
3.79k
  case unsupported_on_arch:
6700
3.79k
    as_bad (_("`%s' is not supported on `%s%s'"),
6701
3.79k
      pass1_mnem ? pass1_mnem : insn_name (current_templates.start),
6702
3.79k
      cpu_arch_name ? cpu_arch_name : default_arch,
6703
3.79k
      cpu_sub_arch_name ? cpu_sub_arch_name : "");
6704
3.79k
    return;
6705
11.4k
  case unsupported_64bit:
6706
11.4k
    if (ISLOWER (mnem_suffix))
6707
1.35k
      {
6708
1.35k
        if (flag_code == CODE_64BIT)
6709
78
    as_bad (_("`%s%c' is not supported in 64-bit mode"),
6710
78
      pass1_mnem ? pass1_mnem : insn_name (current_templates.start),
6711
78
      mnem_suffix);
6712
1.27k
        else
6713
1.27k
    as_bad (_("`%s%c' is only supported in 64-bit mode"),
6714
1.27k
      pass1_mnem ? pass1_mnem : insn_name (current_templates.start),
6715
1.27k
      mnem_suffix);
6716
1.35k
      }
6717
10.0k
    else
6718
10.0k
      {
6719
10.0k
        if (flag_code == CODE_64BIT)
6720
843
    as_bad (_("`%s' is not supported in 64-bit mode"),
6721
843
      pass1_mnem ? pass1_mnem : insn_name (current_templates.start));
6722
9.24k
        else
6723
9.24k
    as_bad (_("`%s' is only supported in 64-bit mode"),
6724
9.24k
      pass1_mnem ? pass1_mnem : insn_name (current_templates.start));
6725
10.0k
      }
6726
11.4k
    return;
6727
0
  case no_vex_encoding:
6728
0
    err_msg = _("no VEX/XOP encoding");
6729
0
    break;
6730
0
  case no_evex_encoding:
6731
0
    err_msg = _("no EVEX encoding");
6732
0
    break;
6733
0
  case invalid_sib_address:
6734
0
    err_msg = _("invalid SIB address");
6735
0
    break;
6736
0
  case invalid_vsib_address:
6737
0
    err_msg = _("invalid VSIB address");
6738
0
    break;
6739
0
  case invalid_vector_register_set:
6740
0
    err_msg = _("mask, index, and destination registers must be distinct");
6741
0
    break;
6742
0
  case invalid_tmm_register_set:
6743
0
    err_msg = _("all tmm registers must be distinct");
6744
0
    break;
6745
0
  case invalid_dest_and_src_register_set:
6746
0
    err_msg = _("destination and source registers must be distinct");
6747
0
    break;
6748
0
  case invalid_dest_register_set:
6749
0
    err_msg = _("two dest registers must be distinct");
6750
0
    break;
6751
0
  case invalid_pseudo_prefix:
6752
0
    err_msg = _("rex2 pseudo prefix cannot be used");
6753
0
    break;
6754
0
  case unsupported_vector_index_register:
6755
0
    err_msg = _("unsupported vector index register");
6756
0
    break;
6757
0
  case unsupported_broadcast:
6758
0
    err_msg = _("unsupported broadcast");
6759
0
    break;
6760
0
  case broadcast_needed:
6761
0
    err_msg = _("broadcast is needed for operand of such type");
6762
0
    break;
6763
0
  case unsupported_masking:
6764
0
    err_msg = _("unsupported masking");
6765
0
    break;
6766
0
  case mask_not_on_destination:
6767
0
    err_msg = _("mask not on destination operand");
6768
0
    break;
6769
0
  case no_default_mask:
6770
0
    err_msg = _("default mask isn't allowed");
6771
0
    break;
6772
1
  case unsupported_rc_sae:
6773
1
    err_msg = _("unsupported static rounding/sae");
6774
1
    break;
6775
0
  case unsupported_vector_size:
6776
0
    as_bad (_("vector size above %u required for `%s'"), 128u << vector_size,
6777
0
      pass1_mnem ? pass1_mnem : insn_name (current_templates.start));
6778
0
    return;
6779
0
  case unsupported_rsp_register:
6780
0
    err_msg = _("'rsp' register cannot be used");
6781
0
    break;
6782
0
  case internal_error:
6783
0
    err_msg = _("internal error");
6784
0
    break;
6785
49.3k
  }
6786
33.9k
      as_bad (_("%s for `%s'"), err_msg,
6787
33.9k
        pass1_mnem ? pass1_mnem : insn_name (current_templates.start));
6788
33.9k
      return;
6789
49.3k
    }
6790
6791
662k
  free (xstrdup_copy);
6792
6793
662k
  if (sse_check != check_none
6794
      /* The opcode space check isn't strictly needed; it's there only to
6795
   bypass the logic below when easily possible.  */
6796
662k
      && t->opcode_space >= SPACE_0F
6797
662k
      && t->opcode_space <= SPACE_0F3A
6798
662k
      && !is_cpu (&i.tm, CpuSSE4a)
6799
662k
      && !is_any_vex_encoding (t))
6800
0
    {
6801
      /* Some KL and all WideKL insns have only implicit %xmm operands.  */
6802
0
      bool simd = is_cpu (t, CpuKL) || is_cpu (t, CpuWideKL);
6803
6804
0
      for (j = 0; j < t->operands; ++j)
6805
0
  {
6806
0
    if (t->operand_types[j].bitfield.class == RegMMX)
6807
0
      break;
6808
0
    if (t->operand_types[j].bitfield.class == RegSIMD)
6809
0
      simd = true;
6810
0
  }
6811
6812
0
      if (j >= t->operands && simd)
6813
0
  (sse_check == check_warning
6814
0
   ? as_warn
6815
0
   : as_bad) (_("SSE instruction `%s' is used"), insn_name (&i.tm));
6816
0
    }
6817
6818
662k
  if (i.tm.opcode_modifier.fwait)
6819
36
    if (!add_prefix (FWAIT_OPCODE))
6820
0
      return;
6821
6822
  /* Check if REP prefix is OK.  */
6823
662k
  if (i.rep_prefix && i.tm.opcode_modifier.prefixok != PrefixRep)
6824
0
    {
6825
0
      as_bad (_("invalid instruction `%s' after `%s'"),
6826
0
    insn_name (&i.tm), i.rep_prefix);
6827
0
      return;
6828
0
    }
6829
6830
  /* Check for lock without a lockable instruction.  Destination operand
6831
     must be memory unless it is xchg (0x86).  */
6832
662k
  if (i.prefix[LOCK_PREFIX])
6833
0
    {
6834
0
      if (i.tm.opcode_modifier.prefixok < PrefixLock
6835
0
    || i.mem_operands == 0
6836
0
    || (i.tm.base_opcode != 0x86
6837
0
        && !(i.flags[i.operands - 1] & Operand_Mem)))
6838
0
  {
6839
0
    as_bad (_("expecting lockable instruction after `lock'"));
6840
0
    return;
6841
0
  }
6842
6843
      /* Zap the redundant prefix from XCHG when optimizing.  */
6844
0
      if (i.tm.base_opcode == 0x86 && optimize && !i.no_optimize)
6845
0
  i.prefix[LOCK_PREFIX] = 0;
6846
0
    }
6847
6848
662k
  if (is_any_vex_encoding (&i.tm)
6849
662k
      || i.tm.operand_types[i.imm_operands].bitfield.class >= RegMMX
6850
662k
      || i.tm.operand_types[i.imm_operands + 1].bitfield.class >= RegMMX)
6851
2
    {
6852
      /* Check for data size prefix on VEX/XOP/EVEX encoded and SIMD insns.  */
6853
2
      if (i.prefix[DATA_PREFIX])
6854
0
  {
6855
0
    as_bad (_("data size prefix invalid with `%s'"), insn_name (&i.tm));
6856
0
    return;
6857
0
  }
6858
6859
      /* Don't allow e.g. KMOV in TLS code sequences.  */
6860
2
      for (j = i.imm_operands; j < i.operands; ++j)
6861
0
  switch (i.reloc[j])
6862
0
    {
6863
0
    case BFD_RELOC_X86_64_GOTTPOFF:
6864
0
      if (i.tm.mnem_off == MN_add
6865
0
    && i.tm.opcode_space == SPACE_EVEXMAP4
6866
0
    && i.mem_operands == 1
6867
0
    && i.base_reg
6868
0
    && i.base_reg->reg_num == RegIP
6869
0
    && i.tm.operand_types[0].bitfield.class == Reg
6870
0
    && i.tm.operand_types[2].bitfield.class == Reg)
6871
        /* Allow APX: add %reg1, foo@gottpoff(%rip), %reg2.  */
6872
0
        break;
6873
      /* Fall through.  */
6874
0
    case BFD_RELOC_386_TLS_GOTIE:
6875
0
    case BFD_RELOC_386_TLS_LE_32:
6876
0
    case BFD_RELOC_X86_64_TLSLD:
6877
0
      as_bad (_("TLS relocation cannot be used with `%s'"), insn_name (&i.tm));
6878
0
      return;
6879
0
    default:
6880
0
      break;
6881
0
    }
6882
2
    }
6883
6884
  /* Check if HLE prefix is OK.  */
6885
662k
  if (i.hle_prefix && !check_hle ())
6886
0
    return;
6887
6888
  /* Check BND prefix.  */
6889
662k
  if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
6890
0
    as_bad (_("expecting valid branch instruction after `bnd'"));
6891
6892
  /* Check NOTRACK prefix.  */
6893
662k
  if (i.notrack_prefix && i.tm.opcode_modifier.prefixok != PrefixNoTrack)
6894
0
    as_bad (_("expecting indirect branch instruction after `notrack'"));
6895
6896
662k
  if (is_cpu (&i.tm, CpuMPX))
6897
73
    {
6898
73
      if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX])
6899
0
  as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
6900
73
      else if (flag_code != CODE_16BIT
6901
73
         ? i.prefix[ADDR_PREFIX]
6902
73
         : i.mem_operands && !i.prefix[ADDR_PREFIX])
6903
0
  as_bad (_("16-bit address isn't allowed in MPX instructions"));
6904
73
    }
6905
6906
  /* Insert BND prefix.  */
6907
662k
  if (add_bnd_prefix && i.tm.opcode_modifier.bndprefixok)
6908
0
    {
6909
0
      if (!i.prefix[BND_PREFIX])
6910
0
  add_prefix (BND_PREFIX_OPCODE);
6911
0
      else if (i.prefix[BND_PREFIX] != BND_PREFIX_OPCODE)
6912
0
  {
6913
0
    as_warn (_("replacing `rep'/`repe' prefix by `bnd'"));
6914
0
    i.prefix[BND_PREFIX] = BND_PREFIX_OPCODE;
6915
0
  }
6916
0
    }
6917
6918
  /* Check string instruction segment overrides.  */
6919
662k
  if (i.tm.opcode_modifier.isstring >= IS_STRING_ES_OP0)
6920
0
    {
6921
0
      gas_assert (i.mem_operands);
6922
0
      if (!check_string ())
6923
0
  return;
6924
0
      i.disp_operands = 0;
6925
0
    }
6926
6927
  /* The memory operand of (%dx) should be only used with input/output
6928
     instructions (base opcodes: 0x6c, 0x6e, 0xec, 0xee).  */
6929
662k
  if (i.input_output_operand
6930
662k
      && ((i.tm.base_opcode | 0x82) != 0xee
6931
0
    || i.tm.opcode_space != SPACE_BASE))
6932
0
    {
6933
0
      as_bad (_("input/output port address isn't allowed with `%s'"),
6934
0
        insn_name (&i.tm));
6935
0
      return;
6936
0
    }
6937
6938
662k
  if (optimize && !i.no_optimize && i.tm.opcode_modifier.optimize)
6939
0
    optimize_encoding ();
6940
6941
  /* Past optimization there's no need to distinguish encoding_evex,
6942
     encoding_evex512, and encoding_egpr anymore.  */
6943
662k
  if (i.encoding == encoding_evex512)
6944
0
    i.encoding = encoding_evex;
6945
662k
  else if (i.encoding == encoding_egpr)
6946
0
    i.encoding = is_any_vex_encoding (&i.tm) ? encoding_evex
6947
0
               : encoding_default;
6948
6949
662k
  if (use_unaligned_vector_move)
6950
0
    encode_with_unaligned_vector_move ();
6951
6952
662k
  if (!process_suffix ())
6953
0
    return;
6954
6955
  /* Check if IP-relative addressing requirements can be satisfied.  */
6956
662k
  if (is_cpu (&i.tm, CpuPREFETCHI)
6957
662k
      && !(i.base_reg && i.base_reg->reg_num == RegIP))
6958
0
    as_warn (_("'%s' only supports RIP-relative address"), insn_name (&i.tm));
6959
6960
  /* Update operand types and check extended states.  */
6961
697k
  for (j = 0; j < i.operands; j++)
6962
34.5k
    {
6963
34.5k
      i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
6964
34.5k
      switch (i.tm.operand_types[j].bitfield.class)
6965
34.5k
  {
6966
34.5k
  default:
6967
34.5k
    break;
6968
34.5k
  case RegMMX:
6969
0
    i.xstate |= xstate_mmx;
6970
0
    break;
6971
0
  case RegMask:
6972
0
    i.xstate |= xstate_mask;
6973
0
    break;
6974
0
  case RegSIMD:
6975
0
    if (i.tm.operand_types[j].bitfield.tmmword)
6976
0
      i.xstate |= xstate_tmm;
6977
0
    else if (i.tm.operand_types[j].bitfield.zmmword
6978
0
       && !i.tm.opcode_modifier.vex
6979
0
       && vector_size >= VSZ512)
6980
0
      i.xstate |= xstate_zmm;
6981
0
    else if (i.tm.operand_types[j].bitfield.ymmword
6982
0
       && vector_size >= VSZ256)
6983
0
      i.xstate |= xstate_ymm;
6984
0
    else if (i.tm.operand_types[j].bitfield.xmmword)
6985
0
      i.xstate |= xstate_xmm;
6986
0
    break;
6987
34.5k
  }
6988
34.5k
    }
6989
6990
  /* Make still unresolved immediate matches conform to size of immediate
6991
     given in i.suffix.  */
6992
662k
  if (!finalize_imm ())
6993
0
    return;
6994
6995
662k
  if (i.types[0].bitfield.imm1)
6996
0
    i.imm_operands = 0; /* kludge for shift insns.  */
6997
6998
  /* For insns with operands there are more diddles to do to the opcode.  */
6999
662k
  if (i.operands)
7000
19.4k
    {
7001
19.4k
      if (!process_operands ())
7002
0
  return;
7003
19.4k
    }
7004
643k
  else if (!quiet_warnings && i.tm.opcode_modifier.operandconstraint == UGH)
7005
0
    {
7006
      /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc.  */
7007
0
      as_warn (_("translating to `%sp'"), insn_name (&i.tm));
7008
0
    }
7009
7010
662k
  if (is_any_vex_encoding (&i.tm))
7011
2
    {
7012
2
      if (!cpu_arch_flags.bitfield.cpui286)
7013
0
  {
7014
0
    as_bad (_("instruction `%s' isn't supported outside of protected mode."),
7015
0
      insn_name (&i.tm));
7016
0
    return;
7017
0
  }
7018
7019
      /* Check for explicit REX prefix.  */
7020
2
      if (i.prefix[REX_PREFIX] || i.rex_encoding)
7021
0
  {
7022
0
    as_bad (_("REX prefix invalid with `%s'"), insn_name (&i.tm));
7023
0
    return;
7024
0
  }
7025
7026
      /* Check for explicit REX2 prefix.  */
7027
2
      if (i.rex2_encoding)
7028
0
  {
7029
0
    as_bad (_("{rex2} prefix invalid with `%s'"), insn_name (&i.tm));
7030
0
    return;
7031
0
  }
7032
7033
2
      if (is_apx_evex_encoding ())
7034
0
  build_apx_evex_prefix ();
7035
2
      else if (i.tm.opcode_modifier.vex)
7036
2
  build_vex_prefix (t);
7037
0
      else
7038
0
  build_evex_prefix ();
7039
7040
      /* The individual REX.RXBW bits got consumed.  */
7041
2
      i.rex &= REX_OPCODE;
7042
7043
      /* The rex2 bits got consumed.  */
7044
2
      i.rex2 = 0;
7045
2
    }
7046
7047
  /* Handle conversion of 'int $3' --> special int3 insn.  */
7048
662k
  if (i.tm.mnem_off == MN_int
7049
662k
      && i.op[0].imms->X_add_number == 3)
7050
0
    {
7051
0
      i.tm.base_opcode = INT3_OPCODE;
7052
0
      i.imm_operands = 0;
7053
0
    }
7054
7055
662k
  if ((i.tm.opcode_modifier.jump == JUMP
7056
662k
       || i.tm.opcode_modifier.jump == JUMP_BYTE
7057
662k
       || i.tm.opcode_modifier.jump == JUMP_DWORD)
7058
662k
      && i.op[0].disps->X_op == O_constant)
7059
100
    {
7060
      /* Convert "jmp constant" (and "call constant") to a jump (call) to
7061
   the absolute address given by the constant.  Since ix86 jumps and
7062
   calls are pc relative, we need to generate a reloc.  */
7063
100
      i.op[0].disps->X_add_symbol = &abs_symbol;
7064
100
      i.op[0].disps->X_op = O_symbol;
7065
100
    }
7066
7067
662k
  establish_rex ();
7068
7069
662k
  insert_lfence_before (last_insn);
7070
7071
  /* We are ready to output the insn.  */
7072
662k
  output_insn (last_insn);
7073
7074
662k
#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7075
  /* PS: SCFI is enabled only for System V AMD64 ABI.  The ABI check has been
7076
     performed in i386_target_format.  */
7077
662k
  if (IS_ELF && flag_synth_cfi)
7078
0
    {
7079
0
      ginsnS *ginsn;
7080
0
      ginsn = x86_ginsn_new (symbol_temp_new_now (), frch_ginsn_gen_mode ());
7081
0
      frch_ginsn_data_append (ginsn);
7082
0
    }
7083
662k
#endif
7084
7085
662k
  insert_lfence_after ();
7086
7087
662k
  if (i.tm.opcode_modifier.isprefix)
7088
3.72k
    {
7089
3.72k
      last_insn->kind = last_insn_prefix;
7090
3.72k
      last_insn->name = insn_name (&i.tm);
7091
3.72k
      last_insn->file = as_where (&last_insn->line);
7092
3.72k
    }
7093
659k
  else
7094
659k
    last_insn->kind = last_insn_other;
7095
662k
}
7096
7097
/* The Q suffix is generally valid only in 64-bit mode, with very few
7098
   exceptions: fild, fistp, fisttp, and cmpxchg8b.  Note that for fild
7099
   and fisttp only one of their two templates is matched below: That's
7100
   sufficient since other relevant attributes are the same between both
7101
   respective templates.  */
7102
static INLINE bool q_suffix_allowed(const insn_template *t)
7103
2.12k
{
7104
2.12k
  return flag_code == CODE_64BIT
7105
2.12k
   || (t->opcode_space == SPACE_BASE
7106
1.42k
       && t->base_opcode == 0xdf
7107
1.42k
       && (t->extension_opcode & 1)) /* fild / fistp / fisttp */
7108
2.12k
   || t->mnem_off == MN_cmpxchg8b;
7109
2.12k
}
7110
7111
static const char *
7112
parse_insn (const char *line, char *mnemonic, bool prefix_only)
7113
1.90M
{
7114
1.90M
  const char *l = line, *token_start = l;
7115
1.90M
  char *mnem_p;
7116
1.90M
  bool pass1 = !current_templates.start;
7117
1.90M
  int supported;
7118
1.90M
  const insn_template *t;
7119
1.90M
  char *dot_p = NULL;
7120
7121
1.90M
  while (1)
7122
1.90M
    {
7123
1.90M
      mnem_p = mnemonic;
7124
      /* Pseudo-prefixes start with an opening figure brace.  */
7125
1.90M
      if ((*mnem_p = *l) == '{')
7126
6.19k
  {
7127
6.19k
    ++mnem_p;
7128
6.19k
    ++l;
7129
6.19k
  }
7130
6.71M
      while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
7131
4.83M
  {
7132
4.83M
    if (*mnem_p == '.')
7133
46.0k
      dot_p = mnem_p;
7134
4.83M
    mnem_p++;
7135
4.83M
    if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
7136
24.9k
      {
7137
24.9k
      too_long:
7138
24.9k
        as_bad (_("no such instruction: `%s'"), token_start);
7139
24.9k
        return NULL;
7140
24.9k
      }
7141
4.80M
    l++;
7142
4.80M
  }
7143
      /* Pseudo-prefixes end with a closing figure brace.  */
7144
1.88M
      if (*mnemonic == '{' && *l == '}')
7145
165
  {
7146
165
    *mnem_p++ = *l++;
7147
165
    if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
7148
13
      goto too_long;
7149
152
    *mnem_p = '\0';
7150
7151
    /* Point l at the closing brace if there's no other separator.  */
7152
152
    if (*l != END_OF_INSN && !is_space_char (*l)
7153
152
        && *l != PREFIX_SEPARATOR)
7154
77
      --l;
7155
152
  }
7156
1.88M
      else if (!is_space_char (*l)
7157
1.88M
         && *l != END_OF_INSN
7158
1.88M
         && (intel_syntax
7159
746k
       || (*l != PREFIX_SEPARATOR && *l != ',')))
7160
715k
  {
7161
715k
    if (prefix_only)
7162
66
      break;
7163
715k
    as_bad (_("invalid character %s in mnemonic"),
7164
715k
      output_invalid (*l));
7165
715k
    return NULL;
7166
715k
  }
7167
1.16M
      if (token_start == l)
7168
2.34k
  {
7169
2.34k
    if (!intel_syntax && *l == PREFIX_SEPARATOR)
7170
1.48k
      as_bad (_("expecting prefix; got nothing"));
7171
858
    else
7172
858
      as_bad (_("expecting mnemonic; got nothing"));
7173
2.34k
    return NULL;
7174
2.34k
  }
7175
7176
      /* Look up instruction (or prefix) via hash table.  */
7177
1.16M
      op_lookup (mnemonic);
7178
7179
1.16M
      if (*l != END_OF_INSN
7180
1.16M
    && (!is_space_char (*l) || l[1] != END_OF_INSN)
7181
1.16M
    && current_templates.start
7182
1.16M
    && current_templates.start->opcode_modifier.isprefix)
7183
2.29k
  {
7184
2.29k
    supported = cpu_flags_match (current_templates.start);
7185
2.29k
    if (!(supported & CPU_FLAGS_64BIT_MATCH))
7186
108
      {
7187
108
        as_bad ((flag_code != CODE_64BIT
7188
108
           ? _("`%s' is only supported in 64-bit mode")
7189
108
           : _("`%s' is not supported in 64-bit mode")),
7190
108
          insn_name (current_templates.start));
7191
108
        return NULL;
7192
108
      }
7193
2.18k
    if (supported != CPU_FLAGS_PERFECT_MATCH)
7194
485
      {
7195
485
        as_bad (_("`%s' is not supported on `%s%s'"),
7196
485
          insn_name (current_templates.start),
7197
485
          cpu_arch_name ? cpu_arch_name : default_arch,
7198
485
          cpu_sub_arch_name ? cpu_sub_arch_name : "");
7199
485
        return NULL;
7200
485
      }
7201
    /* If we are in 16-bit mode, do not allow addr16 or data16.
7202
       Similarly, in 32-bit mode, do not allow addr32 or data32.  */
7203
1.70k
    if ((current_templates.start->opcode_modifier.size == SIZE16
7204
1.70k
         || current_templates.start->opcode_modifier.size == SIZE32)
7205
1.70k
        && flag_code != CODE_64BIT
7206
1.70k
        && ((current_templates.start->opcode_modifier.size == SIZE32)
7207
26
      ^ (flag_code == CODE_16BIT)))
7208
25
      {
7209
25
        as_bad (_("redundant %s prefix"),
7210
25
          insn_name (current_templates.start));
7211
25
        return NULL;
7212
25
      }
7213
7214
1.67k
    if (current_templates.start->base_opcode == PSEUDO_PREFIX)
7215
3
      {
7216
        /* Handle pseudo prefixes.  */
7217
3
        switch (current_templates.start->extension_opcode)
7218
3
    {
7219
0
    case Prefix_Disp8:
7220
      /* {disp8} */
7221
0
      i.disp_encoding = disp_encoding_8bit;
7222
0
      break;
7223
0
    case Prefix_Disp16:
7224
      /* {disp16} */
7225
0
      i.disp_encoding = disp_encoding_16bit;
7226
0
      break;
7227
0
    case Prefix_Disp32:
7228
      /* {disp32} */
7229
0
      i.disp_encoding = disp_encoding_32bit;
7230
0
      break;
7231
0
    case Prefix_Load:
7232
      /* {load} */
7233
0
      i.dir_encoding = dir_encoding_load;
7234
0
      break;
7235
0
    case Prefix_Store:
7236
      /* {store} */
7237
0
      i.dir_encoding = dir_encoding_store;
7238
0
      break;
7239
0
    case Prefix_VEX:
7240
      /* {vex} */
7241
0
      i.encoding = encoding_vex;
7242
0
      break;
7243
0
    case Prefix_VEX3:
7244
      /* {vex3} */
7245
0
      i.encoding = encoding_vex3;
7246
0
      break;
7247
0
    case Prefix_EVEX:
7248
      /* {evex} */
7249
0
      i.encoding = encoding_evex;
7250
0
      break;
7251
0
    case Prefix_REX:
7252
      /* {rex} */
7253
0
      i.rex_encoding = true;
7254
0
      break;
7255
0
    case Prefix_REX2:
7256
      /* {rex2} */
7257
0
      i.rex2_encoding = true;
7258
0
      break;
7259
0
    case Prefix_NF:
7260
      /* {nf} */
7261
0
      i.has_nf = true;
7262
0
      if (i.encoding == encoding_default)
7263
0
        i.encoding = encoding_evex;
7264
0
      break;
7265
3
    case Prefix_NoOptimize:
7266
      /* {nooptimize} */
7267
3
      i.no_optimize = true;
7268
3
      break;
7269
0
    default:
7270
0
      abort ();
7271
3
    }
7272
3
        if (i.has_nf && i.encoding != encoding_evex)
7273
0
    {
7274
0
      as_bad (_("{nf} cannot be combined with {vex}/{vex3}"));
7275
0
      return NULL;
7276
0
    }
7277
3
      }
7278
1.67k
    else
7279
1.67k
      {
7280
        /* Add prefix, checking for repeated prefixes.  */
7281
1.67k
        switch (add_prefix (current_templates.start->base_opcode))
7282
1.67k
    {
7283
324
    case PREFIX_EXIST:
7284
324
      return NULL;
7285
55
    case PREFIX_DS:
7286
55
      if (is_cpu (current_templates.start, CpuIBT))
7287
0
        i.notrack_prefix = insn_name (current_templates.start);
7288
55
      break;
7289
47
    case PREFIX_REP:
7290
47
      if (is_cpu (current_templates.start, CpuHLE))
7291
0
        i.hle_prefix = insn_name (current_templates.start);
7292
47
      else if (is_cpu (current_templates.start, CpuMPX))
7293
13
        i.bnd_prefix = insn_name (current_templates.start);
7294
34
      else
7295
34
        i.rep_prefix = insn_name (current_templates.start);
7296
47
      break;
7297
1.24k
    default:
7298
1.24k
      break;
7299
1.67k
    }
7300
1.67k
      }
7301
    /* Skip past PREFIX_SEPARATOR and reset token_start.  */
7302
1.35k
    token_start = ++l;
7303
1.35k
  }
7304
1.16M
      else
7305
1.16M
  break;
7306
1.16M
    }
7307
7308
1.16M
  if (prefix_only)
7309
66
    return token_start;
7310
7311
1.16M
  if (!current_templates.start)
7312
416k
    {
7313
      /* Deprecated functionality (new code should use pseudo-prefixes instead):
7314
   Check if we should swap operand or force 32bit displacement in
7315
   encoding.  */
7316
416k
      if (mnem_p - 2 == dot_p && dot_p[1] == 's')
7317
16
  {
7318
16
    if (i.dir_encoding == dir_encoding_default)
7319
16
      i.dir_encoding = dir_encoding_swap;
7320
0
    else
7321
0
      as_warn (_("ignoring `.s' suffix due to earlier `{%s}'"),
7322
0
         i.dir_encoding == dir_encoding_load ? "load" : "store");
7323
16
  }
7324
416k
      else if (mnem_p - 3 == dot_p
7325
416k
         && dot_p[1] == 'd'
7326
416k
         && dot_p[2] == '8')
7327
9
  {
7328
9
    if (i.disp_encoding == disp_encoding_default)
7329
9
      i.disp_encoding = disp_encoding_8bit;
7330
0
    else if (i.disp_encoding != disp_encoding_8bit)
7331
0
      as_warn (_("ignoring `.d8' suffix due to earlier `{disp<N>}'"));
7332
9
  }
7333
416k
      else if (mnem_p - 4 == dot_p
7334
416k
         && dot_p[1] == 'd'
7335
416k
         && dot_p[2] == '3'
7336
416k
         && dot_p[3] == '2')
7337
0
  {
7338
0
    if (i.disp_encoding == disp_encoding_default)
7339
0
      i.disp_encoding = disp_encoding_32bit;
7340
0
    else if (i.disp_encoding != disp_encoding_32bit)
7341
0
      as_warn (_("ignoring `.d32' suffix due to earlier `{disp<N>}'"));
7342
0
  }
7343
416k
      else
7344
416k
  goto check_suffix;
7345
25
      mnem_p = dot_p;
7346
25
      *dot_p = '\0';
7347
25
      op_lookup (mnemonic);
7348
25
    }
7349
7350
746k
  if (!current_templates.start || !pass1)
7351
612
    {
7352
612
      current_templates.start = NULL;
7353
7354
416k
    check_suffix:
7355
416k
      if (mnem_p > mnemonic)
7356
416k
  {
7357
    /* See if we can get a match by trimming off a suffix.  */
7358
416k
    switch (mnem_p[-1])
7359
416k
      {
7360
3.77k
      case WORD_MNEM_SUFFIX:
7361
3.77k
        if (intel_syntax && (intel_float_operand (mnemonic) & 2))
7362
0
    i.suffix = SHORT_MNEM_SUFFIX;
7363
3.77k
        else
7364
    /* Fall through.  */
7365
45.4k
        case BYTE_MNEM_SUFFIX:
7366
51.2k
        case QWORD_MNEM_SUFFIX:
7367
51.2k
    i.suffix = mnem_p[-1];
7368
51.2k
        mnem_p[-1] = '\0';
7369
51.2k
        op_lookup (mnemonic);
7370
51.2k
        break;
7371
98.1k
      case SHORT_MNEM_SUFFIX:
7372
114k
      case LONG_MNEM_SUFFIX:
7373
114k
        if (!intel_syntax)
7374
114k
    {
7375
114k
      i.suffix = mnem_p[-1];
7376
114k
      mnem_p[-1] = '\0';
7377
114k
      op_lookup (mnemonic);
7378
114k
    }
7379
114k
        break;
7380
7381
        /* Intel Syntax.  */
7382
23.0k
      case 'd':
7383
23.0k
        if (intel_syntax)
7384
0
    {
7385
0
      if (intel_float_operand (mnemonic) == 1)
7386
0
        i.suffix = SHORT_MNEM_SUFFIX;
7387
0
      else
7388
0
        i.suffix = LONG_MNEM_SUFFIX;
7389
0
      mnem_p[-1] = '\0';
7390
0
      op_lookup (mnemonic);
7391
0
    }
7392
        /* For compatibility reasons accept MOVSD and CMPSD without
7393
           operands even in AT&T mode.  */
7394
23.0k
        else if (*l == END_OF_INSN
7395
23.0k
           || (is_space_char (*l) && l[1] == END_OF_INSN))
7396
21.3k
    {
7397
21.3k
      mnem_p[-1] = '\0';
7398
21.3k
      op_lookup (mnemonic);
7399
21.3k
      if (current_templates.start != NULL
7400
          /* MOVS or CMPS */
7401
21.3k
          && (current_templates.start->base_opcode | 2) == 0xa6
7402
21.3k
          && current_templates.start->opcode_space
7403
0
       == SPACE_BASE
7404
21.3k
          && mnem_p[-2] == 's')
7405
0
        {
7406
0
          as_warn (_("found `%sd'; assuming `%sl' was meant"),
7407
0
             mnemonic, mnemonic);
7408
0
          i.suffix = LONG_MNEM_SUFFIX;
7409
0
        }
7410
21.3k
      else
7411
21.3k
        {
7412
21.3k
          current_templates.start = NULL;
7413
21.3k
          mnem_p[-1] = 'd';
7414
21.3k
        }
7415
21.3k
    }
7416
23.0k
        break;
7417
416k
      }
7418
416k
  }
7419
7420
416k
      if (!current_templates.start)
7421
389k
  {
7422
389k
    if (pass1)
7423
389k
      as_bad (_("no such instruction: `%s'"), token_start);
7424
389k
    return NULL;
7425
389k
  }
7426
416k
    }
7427
7428
772k
  if (current_templates.start->opcode_modifier.jump == JUMP
7429
772k
      || current_templates.start->opcode_modifier.jump == JUMP_BYTE)
7430
8.50k
    {
7431
      /* Check for a branch hint.  We allow ",pt" and ",pn" for
7432
   predict taken and predict not taken respectively.
7433
   I'm not sure that branch hints actually do anything on loop
7434
   and jcxz insns (JumpByte) for current Pentium4 chips.  They
7435
   may work in the future and it doesn't hurt to accept them
7436
   now.  */
7437
8.50k
      if (l[0] == ',' && l[1] == 'p')
7438
183
  {
7439
183
    if (l[2] == 't')
7440
0
      {
7441
0
        if (!add_prefix (DS_PREFIX_OPCODE))
7442
0
    return NULL;
7443
0
        l += 3;
7444
0
      }
7445
183
    else if (l[2] == 'n')
7446
183
      {
7447
183
        if (!add_prefix (CS_PREFIX_OPCODE))
7448
0
    return NULL;
7449
183
        l += 3;
7450
183
      }
7451
183
  }
7452
8.50k
    }
7453
  /* Any other comma loses.  */
7454
772k
  if (*l == ',')
7455
10.0k
    {
7456
10.0k
      as_bad (_("invalid character %s in mnemonic"),
7457
10.0k
        output_invalid (*l));
7458
10.0k
      return NULL;
7459
10.0k
    }
7460
7461
  /* Check if instruction is supported on specified architecture.  */
7462
762k
  supported = 0;
7463
848k
  for (t = current_templates.start; t < current_templates.end; ++t)
7464
833k
    {
7465
833k
      supported |= cpu_flags_match (t);
7466
7467
833k
      if (i.suffix == QWORD_MNEM_SUFFIX && !q_suffix_allowed (t))
7468
1.42k
  supported &= ~CPU_FLAGS_64BIT_MATCH;
7469
7470
833k
      if (supported == CPU_FLAGS_PERFECT_MATCH)
7471
747k
  return l;
7472
833k
    }
7473
7474
15.2k
  if (pass1)
7475
15.2k
    {
7476
15.2k
      if (supported & CPU_FLAGS_64BIT_MATCH)
7477
3.79k
        i.error = unsupported_on_arch;
7478
11.4k
      else
7479
11.4k
        i.error = unsupported_64bit;
7480
15.2k
    }
7481
7482
15.2k
  return NULL;
7483
762k
}
7484
7485
static char *
7486
parse_operands (char *l, const char *mnemonic)
7487
747k
{
7488
747k
  char *token_start;
7489
7490
  /* 1 if operand is pending after ','.  */
7491
747k
  unsigned int expecting_operand = 0;
7492
7493
829k
  while (*l != END_OF_INSN)
7494
132k
    {
7495
      /* Non-zero if operand parens not balanced.  */
7496
132k
      unsigned int paren_not_balanced = 0;
7497
      /* True if inside double quotes.  */
7498
132k
      bool in_quotes = false;
7499
7500
      /* Skip optional white space before operand.  */
7501
132k
      if (is_space_char (*l))
7502
90.4k
  ++l;
7503
132k
      if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"')
7504
1.03k
  {
7505
1.03k
    as_bad (_("invalid character %s before operand %d"),
7506
1.03k
      output_invalid (*l),
7507
1.03k
      i.operands + 1);
7508
1.03k
    return NULL;
7509
1.03k
  }
7510
131k
      token_start = l;  /* After white space.  */
7511
1.79M
      while (in_quotes || paren_not_balanced || *l != ',')
7512
1.74M
  {
7513
1.74M
    if (*l == END_OF_INSN)
7514
71.0k
      {
7515
71.0k
        if (in_quotes)
7516
668
    {
7517
668
      as_bad (_("unbalanced double quotes in operand %d."),
7518
668
        i.operands + 1);
7519
668
      return NULL;
7520
668
    }
7521
70.3k
        if (paren_not_balanced)
7522
15.8k
    {
7523
15.8k
      know (!intel_syntax);
7524
15.8k
      as_bad (_("unbalanced parenthesis in operand %d."),
7525
15.8k
        i.operands + 1);
7526
15.8k
      return NULL;
7527
15.8k
    }
7528
54.5k
        else
7529
54.5k
    break; /* we are done */
7530
70.3k
      }
7531
1.67M
    else if (*l == '\\' && l[1] == '"')
7532
639
      ++l;
7533
1.67M
    else if (*l == '"')
7534
3.75k
      in_quotes = !in_quotes;
7535
1.67M
    else if (!in_quotes && !is_operand_char (*l) && !is_space_char (*l))
7536
14.8k
      {
7537
14.8k
        as_bad (_("invalid character %s in operand %d"),
7538
14.8k
          output_invalid (*l),
7539
14.8k
          i.operands + 1);
7540
14.8k
        return NULL;
7541
14.8k
      }
7542
1.66M
    if (!intel_syntax && !in_quotes)
7543
1.60M
      {
7544
1.60M
        if (*l == '(')
7545
2.82k
    ++paren_not_balanced;
7546
1.60M
        if (*l == ')')
7547
18.7k
    --paren_not_balanced;
7548
1.60M
      }
7549
1.66M
    l++;
7550
1.66M
  }
7551
100k
      if (l != token_start)
7552
98.3k
  {     /* Yes, we've read in another operand.  */
7553
98.3k
    unsigned int operand_ok;
7554
98.3k
    this_operand = i.operands++;
7555
98.3k
    if (i.operands > MAX_OPERANDS)
7556
0
      {
7557
0
        as_bad (_("spurious operands; (%d operands/instruction max)"),
7558
0
          MAX_OPERANDS);
7559
0
        return NULL;
7560
0
      }
7561
98.3k
    i.types[this_operand].bitfield.unspecified = 1;
7562
    /* Now parse operand adding info to 'i' as we go along.  */
7563
98.3k
    END_STRING_AND_SAVE (l);
7564
7565
98.3k
    if (i.mem_operands > 1)
7566
1.49k
      {
7567
1.49k
        as_bad (_("too many memory references for `%s'"),
7568
1.49k
          mnemonic);
7569
1.49k
        return 0;
7570
1.49k
      }
7571
7572
96.8k
    if (intel_syntax)
7573
0
      operand_ok =
7574
0
        i386_intel_operand (token_start,
7575
0
          intel_float_operand (mnemonic));
7576
96.8k
    else
7577
96.8k
      operand_ok = i386_att_operand (token_start);
7578
7579
96.8k
    RESTORE_END_STRING (l);
7580
96.8k
    if (!operand_ok)
7581
15.8k
      return NULL;
7582
96.8k
  }
7583
1.83k
      else
7584
1.83k
  {
7585
1.83k
    if (expecting_operand)
7586
639
      {
7587
802
      expecting_operand_after_comma:
7588
802
        as_bad (_("expecting operand after ','; got nothing"));
7589
802
        return NULL;
7590
639
      }
7591
1.19k
    if (*l == ',')
7592
5
      {
7593
5
        as_bad (_("expecting operand before ','; got nothing"));
7594
5
        return NULL;
7595
5
      }
7596
1.19k
  }
7597
7598
      /* Now *l must be either ',' or END_OF_INSN.  */
7599
82.1k
      if (*l == ',')
7600
42.0k
  {
7601
42.0k
    if (*++l == END_OF_INSN)
7602
163
      {
7603
        /* Just skip it, if it's \n complain.  */
7604
163
        goto expecting_operand_after_comma;
7605
163
      }
7606
41.9k
    expecting_operand = 1;
7607
41.9k
  }
7608
82.1k
    }
7609
696k
  return l;
7610
747k
}
7611
7612
static void
7613
swap_2_operands (unsigned int xchg1, unsigned int xchg2)
7614
0
{
7615
0
  union i386_op temp_op;
7616
0
  i386_operand_type temp_type;
7617
0
  unsigned int temp_flags;
7618
0
  enum bfd_reloc_code_real temp_reloc;
7619
7620
0
  temp_type = i.types[xchg2];
7621
0
  i.types[xchg2] = i.types[xchg1];
7622
0
  i.types[xchg1] = temp_type;
7623
7624
0
  temp_flags = i.flags[xchg2];
7625
0
  i.flags[xchg2] = i.flags[xchg1];
7626
0
  i.flags[xchg1] = temp_flags;
7627
7628
0
  temp_op = i.op[xchg2];
7629
0
  i.op[xchg2] = i.op[xchg1];
7630
0
  i.op[xchg1] = temp_op;
7631
7632
0
  temp_reloc = i.reloc[xchg2];
7633
0
  i.reloc[xchg2] = i.reloc[xchg1];
7634
0
  i.reloc[xchg1] = temp_reloc;
7635
7636
0
  temp_flags = i.imm_bits[xchg2];
7637
0
  i.imm_bits[xchg2] = i.imm_bits[xchg1];
7638
0
  i.imm_bits[xchg1] = temp_flags;
7639
7640
0
  if (i.mask.reg)
7641
0
    {
7642
0
      if (i.mask.operand == xchg1)
7643
0
  i.mask.operand = xchg2;
7644
0
      else if (i.mask.operand == xchg2)
7645
0
  i.mask.operand = xchg1;
7646
0
    }
7647
0
  if (i.broadcast.type || i.broadcast.bytes)
7648
0
    {
7649
0
      if (i.broadcast.operand == xchg1)
7650
0
  i.broadcast.operand = xchg2;
7651
0
      else if (i.broadcast.operand == xchg2)
7652
0
  i.broadcast.operand = xchg1;
7653
0
    }
7654
0
}
7655
7656
static void
7657
swap_operands (void)
7658
0
{
7659
0
  switch (i.operands)
7660
0
    {
7661
0
    case 5:
7662
0
    case 4:
7663
0
      swap_2_operands (1, i.operands - 2);
7664
      /* Fall through.  */
7665
0
    case 3:
7666
0
    case 2:
7667
0
      swap_2_operands (0, i.operands - 1);
7668
0
      break;
7669
0
    default:
7670
0
      abort ();
7671
0
    }
7672
7673
0
  if (i.mem_operands == 2)
7674
0
    {
7675
0
      const reg_entry *temp_seg;
7676
0
      temp_seg = i.seg[0];
7677
0
      i.seg[0] = i.seg[1];
7678
0
      i.seg[1] = temp_seg;
7679
0
    }
7680
0
}
7681
7682
/* Try to ensure constant immediates are represented in the smallest
7683
   opcode possible.  */
7684
static void
7685
optimize_imm (void)
7686
31.3k
{
7687
31.3k
  char guess_suffix = 0;
7688
31.3k
  int op;
7689
7690
31.3k
  if (i.suffix)
7691
5.15k
    guess_suffix = i.suffix;
7692
26.1k
  else if (i.reg_operands)
7693
60
    {
7694
      /* Figure out a suffix from the last register operand specified.
7695
   We can't do this properly yet, i.e. excluding special register
7696
   instances, but the following works for instructions with
7697
   immediates.  In any case, we can't set i.suffix yet.  */
7698
60
      for (op = i.operands; --op >= 0;)
7699
60
  if (i.types[op].bitfield.class != Reg)
7700
0
    continue;
7701
60
  else if (i.types[op].bitfield.byte)
7702
60
    {
7703
60
      guess_suffix = BYTE_MNEM_SUFFIX;
7704
60
      break;
7705
60
    }
7706
0
  else if (i.types[op].bitfield.word)
7707
0
    {
7708
0
      guess_suffix = WORD_MNEM_SUFFIX;
7709
0
      break;
7710
0
    }
7711
0
  else if (i.types[op].bitfield.dword)
7712
0
    {
7713
0
      guess_suffix = LONG_MNEM_SUFFIX;
7714
0
      break;
7715
0
    }
7716
0
  else if (i.types[op].bitfield.qword)
7717
0
    {
7718
0
      guess_suffix = QWORD_MNEM_SUFFIX;
7719
0
      break;
7720
0
    }
7721
60
    }
7722
26.0k
  else if ((flag_code == CODE_16BIT)
7723
26.0k
      ^ (i.prefix[DATA_PREFIX] != 0 && !(i.prefix[REX_PREFIX] & REX_W)))
7724
9.29k
    guess_suffix = WORD_MNEM_SUFFIX;
7725
16.7k
  else if (flag_code != CODE_64BIT
7726
16.7k
     || (!(i.prefix[REX_PREFIX] & REX_W)
7727
         /* A more generic (but also more involved) way of dealing
7728
      with the special case(s) would be to go look for
7729
      DefaultSize attributes on any of the templates.  */
7730
7.54k
         && current_templates.start->mnem_off != MN_push))
7731
16.7k
    guess_suffix = LONG_MNEM_SUFFIX;
7732
7733
80.0k
  for (op = i.operands; --op >= 0;)
7734
48.7k
    if (operand_type_check (i.types[op], imm))
7735
31.3k
      {
7736
31.3k
  switch (i.op[op].imms->X_op)
7737
31.3k
    {
7738
23.5k
    case O_constant:
7739
      /* If a suffix is given, this operand may be shortened.  */
7740
23.5k
      switch (guess_suffix)
7741
23.5k
        {
7742
16.8k
        case LONG_MNEM_SUFFIX:
7743
16.8k
    i.types[op].bitfield.imm32 = 1;
7744
16.8k
    i.types[op].bitfield.imm64 = 1;
7745
16.8k
    break;
7746
6.48k
        case WORD_MNEM_SUFFIX:
7747
6.48k
    i.types[op].bitfield.imm16 = 1;
7748
6.48k
    i.types[op].bitfield.imm32 = 1;
7749
6.48k
    i.types[op].bitfield.imm32s = 1;
7750
6.48k
    i.types[op].bitfield.imm64 = 1;
7751
6.48k
    break;
7752
241
        case BYTE_MNEM_SUFFIX:
7753
241
    i.types[op].bitfield.imm8 = 1;
7754
241
    i.types[op].bitfield.imm8s = 1;
7755
241
    i.types[op].bitfield.imm16 = 1;
7756
241
    i.types[op].bitfield.imm32 = 1;
7757
241
    i.types[op].bitfield.imm32s = 1;
7758
241
    i.types[op].bitfield.imm64 = 1;
7759
241
    break;
7760
23.5k
        }
7761
7762
      /* If this operand is at most 16 bits, convert it
7763
         to a signed 16 bit number before trying to see
7764
         whether it will fit in an even smaller size.
7765
         This allows a 16-bit operand such as $0xffe0 to
7766
         be recognised as within Imm8S range.  */
7767
23.5k
      if ((i.types[op].bitfield.imm16)
7768
23.5k
    && fits_in_unsigned_word (i.op[op].imms->X_add_number))
7769
6.52k
        {
7770
6.52k
    i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
7771
6.52k
            ^ 0x8000) - 0x8000);
7772
6.52k
        }
7773
23.5k
#ifdef BFD64
7774
      /* Store 32-bit immediate in 64-bit for 64-bit BFD.  */
7775
23.5k
      if ((i.types[op].bitfield.imm32)
7776
23.5k
    && fits_in_unsigned_long (i.op[op].imms->X_add_number))
7777
17.5k
        {
7778
17.5k
    i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
7779
17.5k
            ^ ((offsetT) 1 << 31))
7780
17.5k
                 - ((offsetT) 1 << 31));
7781
17.5k
        }
7782
23.5k
#endif
7783
23.5k
      i.types[op]
7784
23.5k
        = operand_type_or (i.types[op],
7785
23.5k
         smallest_imm_type (i.op[op].imms->X_add_number));
7786
7787
      /* We must avoid matching of Imm32 templates when 64bit
7788
         only immediate is available.  */
7789
23.5k
      if (guess_suffix == QWORD_MNEM_SUFFIX)
7790
0
        i.types[op].bitfield.imm32 = 0;
7791
23.5k
      break;
7792
7793
0
    case O_absent:
7794
0
    case O_register:
7795
0
      abort ();
7796
7797
      /* Symbols and expressions.  */
7798
7.76k
    default:
7799
      /* Convert symbolic operand to proper sizes for matching, but don't
7800
         prevent matching a set of insns that only supports sizes other
7801
         than those matching the insn suffix.  */
7802
7.76k
      {
7803
7.76k
        i386_operand_type mask, allowed;
7804
7.76k
        const insn_template *t = current_templates.start;
7805
7806
7.76k
        operand_type_set (&mask, 0);
7807
7.76k
        switch (guess_suffix)
7808
7.76k
    {
7809
3
    case QWORD_MNEM_SUFFIX:
7810
3
      mask.bitfield.imm64 = 1;
7811
3
      mask.bitfield.imm32s = 1;
7812
3
      break;
7813
4.78k
    case LONG_MNEM_SUFFIX:
7814
4.78k
      mask.bitfield.imm32 = 1;
7815
4.78k
      break;
7816
2.80k
    case WORD_MNEM_SUFFIX:
7817
2.80k
      mask.bitfield.imm16 = 1;
7818
2.80k
      break;
7819
167
    case BYTE_MNEM_SUFFIX:
7820
167
      mask.bitfield.imm8 = 1;
7821
167
      break;
7822
0
    default:
7823
0
      break;
7824
7.76k
    }
7825
7826
7.76k
        allowed = operand_type_and (t->operand_types[op], mask);
7827
74.7k
        while (++t < current_templates.end)
7828
67.0k
    {
7829
67.0k
      allowed = operand_type_or (allowed, t->operand_types[op]);
7830
67.0k
      allowed = operand_type_and (allowed, mask);
7831
67.0k
    }
7832
7833
7.76k
        if (!operand_type_all_zero (&allowed))
7834
7.38k
    i.types[op] = operand_type_and (i.types[op], mask);
7835
7.76k
      }
7836
0
      break;
7837
31.3k
    }
7838
31.3k
      }
7839
31.3k
}
7840
7841
/* Try to use the smallest displacement type too.  */
7842
static bool
7843
optimize_disp (const insn_template *t)
7844
24.8k
{
7845
24.8k
  unsigned int op;
7846
7847
24.8k
  if (!want_disp32 (t)
7848
24.8k
      && (!t->opcode_modifier.jump
7849
8.80k
    || i.jumpabsolute || i.types[0].bitfield.baseindex))
7850
7.93k
    {
7851
20.6k
      for (op = 0; op < i.operands; ++op)
7852
12.7k
  {
7853
12.7k
    const expressionS *exp = i.op[op].disps;
7854
7855
12.7k
    if (!operand_type_check (i.types[op], disp))
7856
4.44k
      continue;
7857
7858
8.26k
    if (exp->X_op != O_constant)
7859
3.07k
      continue;
7860
7861
    /* Since displacement is signed extended to 64bit, don't allow
7862
       disp32 if it is out of range.  */
7863
5.19k
    if (fits_in_signed_long (exp->X_add_number))
7864
4.98k
      continue;
7865
7866
212
    i.types[op].bitfield.disp32 = 0;
7867
212
    if (i.types[op].bitfield.baseindex)
7868
0
      {
7869
0
        as_bad (_("0x%" PRIx64 " out of range of signed 32bit displacement"),
7870
0
          (uint64_t) exp->X_add_number);
7871
0
        return false;
7872
0
      }
7873
212
  }
7874
7.93k
    }
7875
7876
  /* Don't optimize displacement for movabs since it only takes 64bit
7877
     displacement.  */
7878
24.8k
  if (i.disp_encoding > disp_encoding_8bit
7879
24.8k
      || (flag_code == CODE_64BIT && t->mnem_off == MN_movabs))
7880
6
    return true;
7881
7882
67.7k
  for (op = i.operands; op-- > 0;)
7883
42.9k
    if (operand_type_check (i.types[op], disp))
7884
25.7k
      {
7885
25.7k
  if (i.op[op].disps->X_op == O_constant)
7886
19.5k
    {
7887
19.5k
      offsetT op_disp = i.op[op].disps->X_add_number;
7888
7889
19.5k
      if (!op_disp && i.types[op].bitfield.baseindex)
7890
0
        {
7891
0
    i.types[op] = operand_type_and_not (i.types[op], anydisp);
7892
0
    i.op[op].disps = NULL;
7893
0
    i.disp_operands--;
7894
0
    continue;
7895
0
        }
7896
7897
19.5k
      if (i.types[op].bitfield.disp16
7898
19.5k
    && fits_in_unsigned_word (op_disp))
7899
3.58k
        {
7900
    /* If this operand is at most 16 bits, convert
7901
       to a signed 16 bit number and don't use 64bit
7902
       displacement.  */
7903
3.58k
    op_disp = ((op_disp ^ 0x8000) - 0x8000);
7904
3.58k
    i.types[op].bitfield.disp64 = 0;
7905
3.58k
        }
7906
7907
19.5k
#ifdef BFD64
7908
      /* Optimize 64-bit displacement to 32-bit for 64-bit BFD.  */
7909
19.5k
      if ((flag_code != CODE_64BIT
7910
19.5k
     ? i.types[op].bitfield.disp32
7911
19.5k
     : want_disp32 (t)
7912
5.51k
       && (!t->opcode_modifier.jump
7913
0
           || i.jumpabsolute || i.types[op].bitfield.baseindex))
7914
19.5k
    && fits_in_unsigned_long (op_disp))
7915
1.92k
        {
7916
    /* If this operand is at most 32 bits, convert
7917
       to a signed 32 bit number and don't use 64bit
7918
       displacement.  */
7919
1.92k
    op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
7920
1.92k
    i.types[op].bitfield.disp64 = 0;
7921
1.92k
    i.types[op].bitfield.disp32 = 1;
7922
1.92k
        }
7923
7924
19.5k
      if (flag_code == CODE_64BIT && fits_in_signed_long (op_disp))
7925
5.26k
        {
7926
5.26k
    i.types[op].bitfield.disp64 = 0;
7927
5.26k
    i.types[op].bitfield.disp32 = 1;
7928
5.26k
        }
7929
19.5k
#endif
7930
19.5k
      if ((i.types[op].bitfield.disp32
7931
19.5k
     || i.types[op].bitfield.disp16)
7932
19.5k
    && fits_in_disp8 (op_disp))
7933
13.3k
        i.types[op].bitfield.disp8 = 1;
7934
7935
19.5k
      i.op[op].disps->X_add_number = op_disp;
7936
19.5k
    }
7937
6.13k
  else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
7938
6.13k
     || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
7939
0
    {
7940
0
      fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
7941
0
       i.op[op].disps, 0, i.reloc[op]);
7942
0
      i.types[op] = operand_type_and_not (i.types[op], anydisp);
7943
0
    }
7944
6.13k
  else
7945
    /* We only support 64bit displacement on constants.  */
7946
6.13k
    i.types[op].bitfield.disp64 = 0;
7947
25.7k
      }
7948
7949
24.8k
  return true;
7950
24.8k
}
7951
7952
/* Return 1 if there is a match in broadcast bytes between operand
7953
   GIVEN and instruction template T.   */
7954
7955
static INLINE int
7956
match_broadcast_size (const insn_template *t, unsigned int given)
7957
0
{
7958
0
  return ((t->opcode_modifier.broadcast == BYTE_BROADCAST
7959
0
     && i.types[given].bitfield.byte)
7960
0
    || (t->opcode_modifier.broadcast == WORD_BROADCAST
7961
0
        && i.types[given].bitfield.word)
7962
0
    || (t->opcode_modifier.broadcast == DWORD_BROADCAST
7963
0
        && i.types[given].bitfield.dword)
7964
0
    || (t->opcode_modifier.broadcast == QWORD_BROADCAST
7965
0
        && i.types[given].bitfield.qword));
7966
0
}
7967
7968
/* Check if operands are valid for the instruction.  */
7969
7970
static int
7971
check_VecOperands (const insn_template *t)
7972
19.4k
{
7973
19.4k
  unsigned int op;
7974
19.4k
  i386_cpu_flags cpu;
7975
7976
  /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
7977
     any one operand are implicity requiring AVX512VL support if the actual
7978
     operand size is YMMword or XMMword.  Since this function runs after
7979
     template matching, there's no need to check for YMMword/XMMword in
7980
     the template.  */
7981
19.4k
  cpu = cpu_flags_and (cpu_flags_from_attr (t->cpu), avx512);
7982
19.4k
  if (!cpu_flags_all_zero (&cpu)
7983
19.4k
      && !is_cpu (t, CpuAVX512VL)
7984
19.4k
      && !cpu_arch_flags.bitfield.cpuavx512vl
7985
19.4k
      && (!t->opcode_modifier.vex || need_evex_encoding (t)))
7986
0
    {
7987
0
      for (op = 0; op < t->operands; ++op)
7988
0
  {
7989
0
    if (t->operand_types[op].bitfield.zmmword
7990
0
        && (i.types[op].bitfield.ymmword
7991
0
      || i.types[op].bitfield.xmmword))
7992
0
      {
7993
0
        i.error = operand_size_mismatch;
7994
0
        return 1;
7995
0
      }
7996
0
  }
7997
0
    }
7998
7999
  /* Somewhat similarly, templates specifying both AVX and AVX2 are
8000
     requiring AVX2 support if the actual operand size is YMMword.  */
8001
19.4k
  if (maybe_cpu (t, CpuAVX) && maybe_cpu (t, CpuAVX2)
8002
19.4k
      && !cpu_arch_flags.bitfield.cpuavx2)
8003
0
    {
8004
0
      for (op = 0; op < t->operands; ++op)
8005
0
  {
8006
0
    if (t->operand_types[op].bitfield.xmmword
8007
0
        && i.types[op].bitfield.ymmword)
8008
0
      {
8009
0
        i.error = operand_size_mismatch;
8010
0
        return 1;
8011
0
      }
8012
0
  }
8013
0
    }
8014
8015
  /* Without VSIB byte, we can't have a vector register for index.  */
8016
19.4k
  if (!t->opcode_modifier.sib
8017
19.4k
      && i.index_reg
8018
19.4k
      && (i.index_reg->reg_type.bitfield.xmmword
8019
0
    || i.index_reg->reg_type.bitfield.ymmword
8020
0
    || i.index_reg->reg_type.bitfield.zmmword))
8021
0
    {
8022
0
      i.error = unsupported_vector_index_register;
8023
0
      return 1;
8024
0
    }
8025
8026
  /* Check if default mask is allowed.  */
8027
19.4k
  if (t->opcode_modifier.operandconstraint == NO_DEFAULT_MASK
8028
19.4k
      && (!i.mask.reg || i.mask.reg->reg_num == 0))
8029
0
    {
8030
0
      i.error = no_default_mask;
8031
0
      return 1;
8032
0
    }
8033
8034
  /* For VSIB byte, we need a vector register for index, and all vector
8035
     registers must be distinct.  */
8036
19.4k
  if (t->opcode_modifier.sib && t->opcode_modifier.sib != SIBMEM)
8037
0
    {
8038
0
      if (!i.index_reg
8039
0
    || !((t->opcode_modifier.sib == VECSIB128
8040
0
    && i.index_reg->reg_type.bitfield.xmmword)
8041
0
         || (t->opcode_modifier.sib == VECSIB256
8042
0
       && i.index_reg->reg_type.bitfield.ymmword)
8043
0
         || (t->opcode_modifier.sib == VECSIB512
8044
0
       && i.index_reg->reg_type.bitfield.zmmword)))
8045
0
      {
8046
0
  i.error = invalid_vsib_address;
8047
0
  return 1;
8048
0
      }
8049
8050
0
      gas_assert (i.reg_operands == 2 || i.mask.reg);
8051
0
      if (i.reg_operands == 2 && !i.mask.reg)
8052
0
  {
8053
0
    gas_assert (i.types[0].bitfield.class == RegSIMD);
8054
0
    gas_assert (i.types[0].bitfield.xmmword
8055
0
          || i.types[0].bitfield.ymmword);
8056
0
    gas_assert (i.types[2].bitfield.class == RegSIMD);
8057
0
    gas_assert (i.types[2].bitfield.xmmword
8058
0
          || i.types[2].bitfield.ymmword);
8059
0
    if (operand_check == check_none)
8060
0
      return 0;
8061
0
    if (register_number (i.op[0].regs)
8062
0
        != register_number (i.index_reg)
8063
0
        && register_number (i.op[2].regs)
8064
0
     != register_number (i.index_reg)
8065
0
        && register_number (i.op[0].regs)
8066
0
     != register_number (i.op[2].regs))
8067
0
      return 0;
8068
0
    if (operand_check == check_error)
8069
0
      {
8070
0
        i.error = invalid_vector_register_set;
8071
0
        return 1;
8072
0
      }
8073
0
    as_warn (_("mask, index, and destination registers should be distinct"));
8074
0
  }
8075
0
      else if (i.reg_operands == 1 && i.mask.reg)
8076
0
  {
8077
0
    if (i.types[1].bitfield.class == RegSIMD
8078
0
        && (i.types[1].bitfield.xmmword
8079
0
            || i.types[1].bitfield.ymmword
8080
0
            || i.types[1].bitfield.zmmword)
8081
0
        && (register_number (i.op[1].regs)
8082
0
      == register_number (i.index_reg)))
8083
0
      {
8084
0
        if (operand_check == check_error)
8085
0
    {
8086
0
      i.error = invalid_vector_register_set;
8087
0
      return 1;
8088
0
    }
8089
0
        if (operand_check != check_none)
8090
0
    as_warn (_("index and destination registers should be distinct"));
8091
0
      }
8092
0
  }
8093
0
    }
8094
8095
  /* For AMX instructions with 3 TMM register operands, all operands
8096
      must be distinct.  */
8097
19.4k
  if (i.reg_operands == 3
8098
19.4k
      && t->operand_types[0].bitfield.tmmword
8099
19.4k
      && (i.op[0].regs == i.op[1].regs
8100
0
          || i.op[0].regs == i.op[2].regs
8101
0
          || i.op[1].regs == i.op[2].regs))
8102
0
    {
8103
0
      i.error = invalid_tmm_register_set;
8104
0
      return 1;
8105
0
    }
8106
8107
  /* For some special instructions require that destination must be distinct
8108
     from source registers.  */
8109
19.4k
  if (t->opcode_modifier.operandconstraint == DISTINCT_DEST)
8110
0
    {
8111
0
      unsigned int dest_reg = i.operands - 1;
8112
8113
0
      know (i.operands >= 3);
8114
8115
      /* #UD if dest_reg == src1_reg or dest_reg == src2_reg.  */
8116
0
      if (i.op[dest_reg - 1].regs == i.op[dest_reg].regs
8117
0
    || (i.reg_operands > 2
8118
0
        && i.op[dest_reg - 2].regs == i.op[dest_reg].regs))
8119
0
  {
8120
0
    i.error = invalid_dest_and_src_register_set;
8121
0
    return 1;
8122
0
  }
8123
0
    }
8124
8125
  /* Check if broadcast is supported by the instruction and is applied
8126
     to the memory operand.  */
8127
19.4k
  if (i.broadcast.type || i.broadcast.bytes)
8128
0
    {
8129
0
      i386_operand_type type, overlap;
8130
8131
      /* Check if specified broadcast is supported in this instruction,
8132
   and its broadcast bytes match the memory operand.  */
8133
0
      op = i.broadcast.operand;
8134
0
      if (!t->opcode_modifier.broadcast
8135
0
    || !(i.flags[op] & Operand_Mem)
8136
0
    || (!i.types[op].bitfield.unspecified
8137
0
        && !match_broadcast_size (t, op)))
8138
0
  {
8139
0
  bad_broadcast:
8140
0
    i.error = unsupported_broadcast;
8141
0
    return 1;
8142
0
  }
8143
8144
0
      operand_type_set (&type, 0);
8145
0
      switch (get_broadcast_bytes (t, false))
8146
0
  {
8147
0
  case 2:
8148
0
    type.bitfield.word = 1;
8149
0
    break;
8150
0
  case 4:
8151
0
    type.bitfield.dword = 1;
8152
0
    break;
8153
0
  case 8:
8154
0
    type.bitfield.qword = 1;
8155
0
    break;
8156
0
  case 16:
8157
0
    type.bitfield.xmmword = 1;
8158
0
    break;
8159
0
  case 32:
8160
0
    if (vector_size < VSZ256)
8161
0
      goto bad_broadcast;
8162
0
    type.bitfield.ymmword = 1;
8163
0
    break;
8164
0
  case 64:
8165
0
    if (vector_size < VSZ512)
8166
0
      goto bad_broadcast;
8167
0
    type.bitfield.zmmword = 1;
8168
0
    break;
8169
0
  default:
8170
0
    goto bad_broadcast;
8171
0
  }
8172
8173
0
      overlap = operand_type_and (type, t->operand_types[op]);
8174
0
      if (t->operand_types[op].bitfield.class == RegSIMD
8175
0
    && t->operand_types[op].bitfield.byte
8176
0
       + t->operand_types[op].bitfield.word
8177
0
       + t->operand_types[op].bitfield.dword
8178
0
       + t->operand_types[op].bitfield.qword > 1)
8179
0
  {
8180
0
    overlap.bitfield.xmmword = 0;
8181
0
    overlap.bitfield.ymmword = 0;
8182
0
    overlap.bitfield.zmmword = 0;
8183
0
  }
8184
0
      if (operand_type_all_zero (&overlap))
8185
0
    goto bad_broadcast;
8186
8187
0
      if (t->opcode_modifier.checkoperandsize)
8188
0
  {
8189
0
    unsigned int j;
8190
8191
0
    type.bitfield.baseindex = 1;
8192
0
    for (j = 0; j < i.operands; ++j)
8193
0
      {
8194
0
        if (j != op
8195
0
      && !operand_type_register_match(i.types[j],
8196
0
              t->operand_types[j],
8197
0
              type,
8198
0
              t->operand_types[op]))
8199
0
    goto bad_broadcast;
8200
0
      }
8201
0
  }
8202
0
    }
8203
  /* If broadcast is supported in this instruction, we need to check if
8204
     operand of one-element size isn't specified without broadcast.  */
8205
19.4k
  else if (t->opcode_modifier.broadcast && i.mem_operands)
8206
0
    {
8207
      /* Find memory operand.  */
8208
0
      for (op = 0; op < i.operands; op++)
8209
0
  if (i.flags[op] & Operand_Mem)
8210
0
    break;
8211
0
      gas_assert (op < i.operands);
8212
      /* Check size of the memory operand.  */
8213
0
      if (match_broadcast_size (t, op))
8214
0
  {
8215
0
    i.error = broadcast_needed;
8216
0
    return 1;
8217
0
  }
8218
0
    }
8219
19.4k
  else
8220
19.4k
    op = MAX_OPERANDS - 1; /* Avoid uninitialized variable warning.  */
8221
8222
  /* Check if requested masking is supported.  */
8223
19.4k
  if (i.mask.reg)
8224
0
    {
8225
0
      if (!t->opcode_modifier.masking)
8226
0
  {
8227
0
    i.error = unsupported_masking;
8228
0
    return 1;
8229
0
  }
8230
8231
      /* Common rules for masking:
8232
   - mask register destinations permit only zeroing-masking, without
8233
     that actually being expressed by a {z} operand suffix or EVEX.z,
8234
   - memory destinations allow only merging-masking,
8235
   - scatter/gather insns (i.e. ones using vSIB) only allow merging-
8236
     masking.  */
8237
0
      if (i.mask.zeroing
8238
0
    && (t->operand_types[t->operands - 1].bitfield.class == RegMask
8239
0
        || (i.flags[t->operands - 1] & Operand_Mem)
8240
0
        || t->opcode_modifier.sib))
8241
0
  {
8242
0
    i.error = unsupported_masking;
8243
0
    return 1;
8244
0
  }
8245
0
    }
8246
8247
  /* Check if masking is applied to dest operand.  */
8248
19.4k
  if (i.mask.reg && (i.mask.operand != i.operands - 1))
8249
0
    {
8250
0
      i.error = mask_not_on_destination;
8251
0
      return 1;
8252
0
    }
8253
8254
  /* Check RC/SAE.  */
8255
19.4k
  if (i.rounding.type != rc_none)
8256
1
    {
8257
1
      if (!t->opcode_modifier.sae
8258
1
    || ((i.rounding.type != saeonly) != t->opcode_modifier.staticrounding)
8259
1
    || i.mem_operands)
8260
1
  {
8261
1
    i.error = unsupported_rc_sae;
8262
1
    return 1;
8263
1
  }
8264
8265
      /* Non-EVEX.LIG forms need to have a ZMM register as at least one
8266
   operand.  */
8267
0
      if (t->opcode_modifier.evex != EVEXLIG)
8268
0
  {
8269
0
    for (op = 0; op < t->operands; ++op)
8270
0
      if (i.types[op].bitfield.zmmword)
8271
0
        break;
8272
0
    if (op >= t->operands)
8273
0
      {
8274
0
        i.error = operand_size_mismatch;
8275
0
        return 1;
8276
0
      }
8277
0
  }
8278
0
    }
8279
8280
  /* Check the special Imm4 cases; must be the first operand.  */
8281
19.4k
  if ((is_cpu (t, CpuXOP) && t->operands == 5)
8282
19.4k
      || (t->opcode_space == SPACE_0F3A
8283
19.4k
    && (t->base_opcode | 3) == 0x0b
8284
19.4k
    && (is_cpu (t, CpuAPX_F)
8285
0
     || (t->opcode_modifier.sse2avx && t->opcode_modifier.evex
8286
0
         && (!t->opcode_modifier.vex
8287
0
       || (i.encoding != encoding_default
8288
0
           && i.encoding != encoding_vex
8289
0
           && i.encoding != encoding_vex3))))))
8290
0
    {
8291
0
      if (i.op[0].imms->X_op != O_constant
8292
0
    || !fits_in_imm4 (i.op[0].imms->X_add_number))
8293
0
  {
8294
0
    i.error = bad_imm4;
8295
0
    return 1;
8296
0
  }
8297
8298
      /* Turn off Imm<N> so that update_imm won't complain.  */
8299
0
      if (t->operands == 5)
8300
0
  operand_type_set (&i.types[0], 0);
8301
0
    }
8302
8303
  /* Check vector Disp8 operand.  */
8304
19.4k
  if (t->opcode_modifier.disp8memshift
8305
19.4k
      && (!t->opcode_modifier.vex
8306
0
    || need_evex_encoding (t))
8307
19.4k
      && i.disp_encoding <= disp_encoding_8bit)
8308
0
    {
8309
0
      if (i.broadcast.type || i.broadcast.bytes)
8310
0
  i.memshift = t->opcode_modifier.broadcast - 1;
8311
0
      else if (t->opcode_modifier.disp8memshift != DISP8_SHIFT_VL)
8312
0
  i.memshift = t->opcode_modifier.disp8memshift;
8313
0
      else
8314
0
  {
8315
0
    const i386_operand_type *type = NULL, *fallback = NULL;
8316
8317
0
    i.memshift = 0;
8318
0
    for (op = 0; op < i.operands; op++)
8319
0
      if (i.flags[op] & Operand_Mem)
8320
0
        {
8321
0
    if (t->opcode_modifier.evex == EVEXLIG)
8322
0
      i.memshift = 2 + (i.suffix == QWORD_MNEM_SUFFIX);
8323
0
    else if (t->operand_types[op].bitfield.xmmword
8324
0
       + t->operand_types[op].bitfield.ymmword
8325
0
       + t->operand_types[op].bitfield.zmmword <= 1)
8326
0
      type = &t->operand_types[op];
8327
0
    else if (!i.types[op].bitfield.unspecified)
8328
0
      type = &i.types[op];
8329
0
    else /* Ambiguities get resolved elsewhere.  */
8330
0
      fallback = &t->operand_types[op];
8331
0
        }
8332
0
      else if (i.types[op].bitfield.class == RegSIMD
8333
0
         && t->opcode_modifier.evex != EVEXLIG)
8334
0
        {
8335
0
    if (i.types[op].bitfield.zmmword)
8336
0
      i.memshift = 6;
8337
0
    else if (i.types[op].bitfield.ymmword && i.memshift < 5)
8338
0
      i.memshift = 5;
8339
0
    else if (i.types[op].bitfield.xmmword && i.memshift < 4)
8340
0
      i.memshift = 4;
8341
0
        }
8342
8343
0
    if (!type && !i.memshift)
8344
0
      type = fallback;
8345
0
    if (type)
8346
0
      {
8347
0
        if (type->bitfield.zmmword)
8348
0
    i.memshift = 6;
8349
0
        else if (type->bitfield.ymmword)
8350
0
    i.memshift = 5;
8351
0
        else if (type->bitfield.xmmword)
8352
0
    i.memshift = 4;
8353
0
      }
8354
8355
    /* For the check in fits_in_disp8().  */
8356
0
    if (i.memshift == 0)
8357
0
      i.memshift = -1;
8358
0
  }
8359
8360
0
      for (op = 0; op < i.operands; op++)
8361
0
  if (operand_type_check (i.types[op], disp)
8362
0
      && i.op[op].disps->X_op == O_constant)
8363
0
    {
8364
0
      if (fits_in_disp8 (i.op[op].disps->X_add_number))
8365
0
        {
8366
0
    i.types[op].bitfield.disp8 = 1;
8367
0
    return 0;
8368
0
        }
8369
0
      i.types[op].bitfield.disp8 = 0;
8370
0
    }
8371
0
    }
8372
8373
19.4k
  i.memshift = 0;
8374
8375
19.4k
  return 0;
8376
19.4k
}
8377
8378
/* Check if encoding requirements are met by the instruction.  */
8379
8380
static int
8381
VEX_check_encoding (const insn_template *t)
8382
662k
{
8383
662k
  if (i.encoding == encoding_error)
8384
0
    {
8385
0
      i.error = unsupported;
8386
0
      return 1;
8387
0
    }
8388
8389
  /* Vector size restrictions.  */
8390
662k
  if ((vector_size < VSZ512
8391
662k
       && t->opcode_modifier.evex == EVEX512)
8392
662k
      || (vector_size < VSZ256
8393
662k
    && (t->opcode_modifier.evex == EVEX256
8394
0
        || t->opcode_modifier.vex == VEX256)))
8395
0
    {
8396
0
      i.error = unsupported_vector_size;
8397
0
      return 1;
8398
0
    }
8399
8400
662k
  switch (i.encoding)
8401
662k
    {
8402
662k
    case encoding_default:
8403
662k
      break;
8404
8405
0
    case encoding_vex:
8406
0
    case encoding_vex3:
8407
      /* This instruction must be encoded with VEX prefix.  */
8408
0
      if (!t->opcode_modifier.vex)
8409
0
  {
8410
0
    i.error = no_vex_encoding;
8411
0
    return 1;
8412
0
  }
8413
0
      break;
8414
8415
0
    case encoding_evex:
8416
3
    case encoding_evex512:
8417
      /* This instruction must be encoded with EVEX prefix.  */
8418
3
      if (!t->opcode_modifier.evex)
8419
2
  {
8420
2
    i.error = no_evex_encoding;
8421
2
    return 1;
8422
2
  }
8423
1
      break;
8424
8425
1
    case encoding_egpr:
8426
      /* This instruction must be encoded with REX2 or EVEX prefix.  */
8427
0
      if (t->opcode_modifier.vex && !t->opcode_modifier.evex)
8428
0
  {
8429
0
    i.error = no_evex_encoding;
8430
0
    return 1;
8431
0
  }
8432
0
      break;
8433
8434
0
    default:
8435
0
      abort ();
8436
662k
    }
8437
8438
662k
  return 0;
8439
662k
}
8440
8441
/* Check if Egprs operands are valid for the instruction.  */
8442
8443
static bool
8444
check_EgprOperands (const insn_template *t)
8445
19.4k
{
8446
19.4k
  if (!t->opcode_modifier.noegpr)
8447
18.2k
    return false;
8448
8449
2.37k
  for (unsigned int op = 0; op < i.operands; op++)
8450
1.18k
    {
8451
1.18k
      if (i.types[op].bitfield.class != Reg)
8452
1.18k
  continue;
8453
8454
0
      if (i.op[op].regs->reg_flags & RegRex2)
8455
0
  {
8456
0
    i.error = register_type_mismatch;
8457
0
    return true;
8458
0
  }
8459
0
    }
8460
8461
1.18k
  if ((i.index_reg && (i.index_reg->reg_flags & RegRex2))
8462
1.18k
      || (i.base_reg && (i.base_reg->reg_flags & RegRex2)))
8463
0
    {
8464
0
      i.error = unsupported_EGPR_for_addressing;
8465
0
      return true;
8466
0
    }
8467
8468
  /* Check if pseudo prefix {rex2} is valid.  */
8469
1.18k
  if (i.rex2_encoding && !t->opcode_modifier.sse2avx)
8470
0
    {
8471
0
      i.error = invalid_pseudo_prefix;
8472
0
      return true;
8473
0
    }
8474
8475
1.18k
  return false;
8476
1.18k
}
8477
8478
/* Check if APX operands are valid for the instruction.  */
8479
static bool
8480
check_APX_operands (const insn_template *t)
8481
19.4k
{
8482
  /* Push2* and Pop2* cannot use RSP and Pop2* cannot pop two same registers.
8483
   */
8484
19.4k
  switch (t->mnem_off)
8485
19.4k
    {
8486
0
    case MN_pop2:
8487
0
    case MN_pop2p:
8488
0
      if (register_number (i.op[0].regs) == register_number (i.op[1].regs))
8489
0
  {
8490
0
    i.error = invalid_dest_register_set;
8491
0
    return 1;
8492
0
  }
8493
    /* fall through */
8494
0
    case MN_push2:
8495
0
    case MN_push2p:
8496
0
      if (register_number (i.op[0].regs) == 4
8497
0
    || register_number (i.op[1].regs) == 4)
8498
0
  {
8499
0
    i.error = unsupported_rsp_register;
8500
0
    return 1;
8501
0
  }
8502
0
      break;
8503
19.4k
    }
8504
19.4k
  return 0;
8505
19.4k
}
8506
8507
/* Check if the instruction use the REX registers or REX prefix.  */
8508
static bool
8509
check_Rex_required (void)
8510
0
{
8511
0
  for (unsigned int op = 0; op < i.operands; op++)
8512
0
    {
8513
0
      if (i.types[op].bitfield.class != Reg)
8514
0
  continue;
8515
8516
0
      if (i.op[op].regs->reg_flags & (RegRex | RegRex64))
8517
0
  return true;
8518
0
    }
8519
8520
0
  if ((i.index_reg && (i.index_reg->reg_flags & (RegRex | RegRex64)))
8521
0
      || (i.base_reg && (i.base_reg->reg_flags & (RegRex | RegRex64))))
8522
0
    return true;
8523
8524
  /* Check pseudo prefix {rex} are valid.  */
8525
0
  return i.rex_encoding;
8526
0
}
8527
8528
/* Optimize APX NDD insns to legacy insns.  */
8529
static unsigned int
8530
can_convert_NDD_to_legacy (const insn_template *t)
8531
0
{
8532
0
  unsigned int match_dest_op = ~0;
8533
8534
0
  if (!i.has_nf && i.reg_operands >= 2)
8535
0
    {
8536
0
      unsigned int dest = i.operands - 1;
8537
0
      unsigned int src1 = i.operands - 2;
8538
0
      unsigned int src2 = (i.operands > 3) ? i.operands - 3 : 0;
8539
8540
0
      if (i.types[src1].bitfield.class == Reg
8541
0
    && i.op[src1].regs == i.op[dest].regs)
8542
0
  match_dest_op = src1;
8543
      /* If the first operand is the same as the third operand,
8544
   these instructions need to support the ability to commutative
8545
   the first two operands and still not change the semantics in order
8546
   to be optimized.  */
8547
0
      else if (optimize > 1
8548
0
         && t->opcode_modifier.commutative
8549
0
         && i.types[src2].bitfield.class == Reg
8550
0
         && i.op[src2].regs == i.op[dest].regs)
8551
0
  match_dest_op = src2;
8552
0
    }
8553
0
  return match_dest_op;
8554
0
}
8555
8556
/* Helper function for the progress() macro in match_template().  */
8557
static INLINE enum i386_error progress (enum i386_error new,
8558
          enum i386_error last,
8559
          unsigned int line, unsigned int *line_p)
8560
5.73M
{
8561
5.73M
  if (line <= *line_p)
8562
302k
    return last;
8563
5.42M
  *line_p = line;
8564
5.42M
  return new;
8565
5.73M
}
8566
8567
static const insn_template *
8568
match_template (char mnem_suffix)
8569
696k
{
8570
  /* Points to template once we've found it.  */
8571
696k
  const insn_template *t;
8572
696k
  i386_operand_type overlap0, overlap1, overlap2, overlap3;
8573
696k
  i386_operand_type overlap4;
8574
696k
  unsigned int found_reverse_match;
8575
696k
  i386_operand_type operand_types [MAX_OPERANDS];
8576
696k
  int addr_prefix_disp;
8577
696k
  unsigned int j, size_match, check_register, errline = __LINE__;
8578
696k
  enum i386_error specific_error = number_of_operands_mismatch;
8579
5.73M
#define progress(err) progress (err, specific_error, __LINE__, &errline)
8580
8581
#if MAX_OPERANDS != 5
8582
# error "MAX_OPERANDS must be 5."
8583
#endif
8584
8585
696k
  found_reverse_match = 0;
8586
696k
  addr_prefix_disp = -1;
8587
8588
1.59M
  for (t = current_templates.start; t < current_templates.end; t++)
8589
1.55M
    {
8590
1.55M
      addr_prefix_disp = -1;
8591
1.55M
      found_reverse_match = 0;
8592
8593
      /* Must have right number of operands.  */
8594
1.55M
      if (i.operands != t->operands)
8595
822k
  continue;
8596
8597
      /* Skip SSE2AVX templates when inapplicable.  */
8598
736k
      if (t->opcode_modifier.sse2avx
8599
736k
    && (!sse2avx || i.prefix[DATA_PREFIX]))
8600
0
  {
8601
    /* Another non-SSE2AVX template has to follow.  */
8602
0
    gas_assert (t + 1 < current_templates.end);
8603
0
    continue;
8604
0
  }
8605
8606
      /* Check processor support.  */
8607
736k
      specific_error = progress (unsupported);
8608
736k
      if (cpu_flags_match (t) != CPU_FLAGS_PERFECT_MATCH)
8609
17.2k
  continue;
8610
8611
      /* Check AT&T mnemonic.   */
8612
719k
      specific_error = progress (unsupported_with_intel_mnemonic);
8613
719k
      if (!intel_syntax && intel_mnemonic
8614
719k
    && t->opcode_modifier.dialect == ATT_MNEMONIC)
8615
0
  continue;
8616
8617
      /* Check AT&T/Intel syntax.  */
8618
719k
      specific_error = progress (unsupported_syntax);
8619
719k
      if (intel_syntax
8620
719k
     ? t->opcode_modifier.dialect >= ATT_SYNTAX
8621
719k
     : t->opcode_modifier.dialect == INTEL_SYNTAX)
8622
0
  continue;
8623
8624
      /* Check NF support.  */
8625
719k
      specific_error = progress (unsupported_nf);
8626
719k
      if (i.has_nf && !t->opcode_modifier.nf)
8627
0
  continue;
8628
8629
      /* Check Intel64/AMD64 ISA.   */
8630
719k
      switch (isa64)
8631
719k
  {
8632
719k
  default:
8633
    /* Default: Don't accept Intel64.  */
8634
719k
    if (t->opcode_modifier.isa64 == INTEL64)
8635
4
      continue;
8636
719k
    break;
8637
719k
  case amd64:
8638
    /* -mamd64: Don't accept Intel64 and Intel64 only.  */
8639
0
    if (t->opcode_modifier.isa64 >= INTEL64)
8640
0
      continue;
8641
0
    break;
8642
0
  case intel64:
8643
    /* -mintel64: Don't accept AMD64.  */
8644
0
    if (t->opcode_modifier.isa64 == AMD64 && flag_code == CODE_64BIT)
8645
0
      continue;
8646
0
    break;
8647
719k
  }
8648
8649
      /* Check the suffix.  */
8650
719k
      specific_error = progress (invalid_instruction_suffix);
8651
719k
      if ((t->opcode_modifier.no_bsuf && mnem_suffix == BYTE_MNEM_SUFFIX)
8652
719k
    || (t->opcode_modifier.no_wsuf && mnem_suffix == WORD_MNEM_SUFFIX)
8653
719k
    || (t->opcode_modifier.no_lsuf && mnem_suffix == LONG_MNEM_SUFFIX)
8654
719k
    || (t->opcode_modifier.no_ssuf && mnem_suffix == SHORT_MNEM_SUFFIX)
8655
719k
    || (t->opcode_modifier.no_qsuf && mnem_suffix == QWORD_MNEM_SUFFIX))
8656
13.4k
  continue;
8657
8658
706k
      specific_error = progress (operand_size_mismatch);
8659
706k
      size_match = operand_size_match (t);
8660
706k
      if (!size_match)
8661
13.4k
  continue;
8662
8663
      /* This is intentionally not
8664
8665
   if (i.jumpabsolute != (t->opcode_modifier.jump == JUMP_ABSOLUTE))
8666
8667
   as the case of a missing * on the operand is accepted (perhaps with
8668
   a warning, issued further down).  */
8669
692k
      specific_error = progress (operand_type_mismatch);
8670
692k
      if (i.jumpabsolute && t->opcode_modifier.jump != JUMP_ABSOLUTE)
8671
403
  continue;
8672
8673
      /* In Intel syntax, normally we can check for memory operand size when
8674
   there is no mnemonic suffix.  But jmp and call have 2 different
8675
   encodings with Dword memory operand size.  Skip the "near" one
8676
   (permitting a register operand) when "far" was requested.  */
8677
692k
      if (i.far_branch
8678
692k
    && t->opcode_modifier.jump == JUMP_ABSOLUTE
8679
692k
    && t->operand_types[0].bitfield.class == Reg)
8680
0
  continue;
8681
8682
4.15M
      for (j = 0; j < MAX_OPERANDS; j++)
8683
3.46M
  operand_types[j] = t->operand_types[j];
8684
8685
      /* In general, don't allow 32-bit operands on pre-386.  */
8686
692k
      specific_error = progress (mnem_suffix ? invalid_instruction_suffix
8687
692k
               : operand_size_mismatch);
8688
692k
      j = i.imm_operands + (t->operands > i.imm_operands + 1);
8689
692k
      if (i.suffix == LONG_MNEM_SUFFIX
8690
692k
    && !cpu_arch_flags.bitfield.cpui386
8691
692k
    && (intel_syntax
8692
0
        ? (t->opcode_modifier.mnemonicsize != IGNORESIZE
8693
0
     && !intel_float_operand (insn_name (t)))
8694
0
        : intel_float_operand (insn_name (t)) != 2)
8695
692k
    && (t->operands == i.imm_operands
8696
0
        || (operand_types[i.imm_operands].bitfield.class != RegMMX
8697
0
         && operand_types[i.imm_operands].bitfield.class != RegSIMD
8698
0
         && operand_types[i.imm_operands].bitfield.class != RegMask)
8699
0
        || (operand_types[j].bitfield.class != RegMMX
8700
0
      && operand_types[j].bitfield.class != RegSIMD
8701
0
      && operand_types[j].bitfield.class != RegMask))
8702
692k
    && !t->opcode_modifier.sib)
8703
0
  continue;
8704
8705
      /* Do not verify operands when there are none.  */
8706
692k
      if (!t->operands)
8707
643k
  {
8708
643k
    if (VEX_check_encoding (t))
8709
0
      {
8710
0
        specific_error = progress (i.error);
8711
0
        continue;
8712
0
      }
8713
8714
    /* Check if pseudo prefix {rex2} is valid.  */
8715
643k
    if (t->opcode_modifier.noegpr && i.rex2_encoding)
8716
0
      {
8717
0
        specific_error = progress (invalid_pseudo_prefix);
8718
0
        continue;
8719
0
      }
8720
8721
    /* We've found a match; break out of loop.  */
8722
643k
    break;
8723
643k
  }
8724
8725
48.9k
      if (!t->opcode_modifier.jump
8726
48.9k
    || t->opcode_modifier.jump == JUMP_ABSOLUTE)
8727
48.0k
  {
8728
    /* There should be only one Disp operand.  */
8729
115k
    for (j = 0; j < MAX_OPERANDS; j++)
8730
109k
      if (operand_type_check (operand_types[j], disp))
8731
42.3k
        break;
8732
48.0k
    if (j < MAX_OPERANDS)
8733
42.3k
      {
8734
42.3k
        bool override = (i.prefix[ADDR_PREFIX] != 0);
8735
8736
42.3k
        addr_prefix_disp = j;
8737
8738
        /* Address size prefix will turn Disp64 operand into Disp32 and
8739
     Disp32/Disp16 one into Disp16/Disp32 respectively.  */
8740
42.3k
        switch (flag_code)
8741
42.3k
    {
8742
19.1k
    case CODE_16BIT:
8743
19.1k
      override = !override;
8744
      /* Fall through.  */
8745
28.6k
    case CODE_32BIT:
8746
28.6k
      if (operand_types[j].bitfield.disp32
8747
28.6k
          && operand_types[j].bitfield.disp16)
8748
28.6k
        {
8749
28.6k
          operand_types[j].bitfield.disp16 = override;
8750
28.6k
          operand_types[j].bitfield.disp32 = !override;
8751
28.6k
        }
8752
28.6k
      gas_assert (!operand_types[j].bitfield.disp64);
8753
28.6k
      break;
8754
8755
28.6k
    case CODE_64BIT:
8756
13.6k
      if (operand_types[j].bitfield.disp64)
8757
5
        {
8758
5
          gas_assert (!operand_types[j].bitfield.disp32);
8759
5
          operand_types[j].bitfield.disp32 = override;
8760
5
          operand_types[j].bitfield.disp64 = !override;
8761
5
        }
8762
13.6k
      operand_types[j].bitfield.disp16 = 0;
8763
13.6k
      break;
8764
42.3k
    }
8765
42.3k
      }
8766
48.0k
  }
8767
8768
      /* We check register size if needed.  */
8769
48.9k
      if (t->opcode_modifier.checkoperandsize)
8770
16.2k
  {
8771
16.2k
    check_register = (1 << t->operands) - 1;
8772
16.2k
    if (i.broadcast.type || i.broadcast.bytes)
8773
0
      check_register &= ~(1 << i.broadcast.operand);
8774
16.2k
  }
8775
32.6k
      else
8776
32.6k
  check_register = 0;
8777
8778
48.9k
      overlap0 = operand_type_and (i.types[0], operand_types[0]);
8779
48.9k
      switch (t->operands)
8780
48.9k
  {
8781
9.77k
  case 1:
8782
9.77k
    if (!operand_type_match (overlap0, i.types[0]))
8783
5.41k
      continue;
8784
8785
    /* Allow the ModR/M encoding to be requested by using the {load} or
8786
       {store} pseudo prefix on an applicable insn.  */
8787
4.35k
    if (!t->opcode_modifier.modrm
8788
4.35k
        && i.reg_operands == 1
8789
4.35k
        && ((i.dir_encoding == dir_encoding_load
8790
0
       && t->mnem_off != MN_pop)
8791
0
      || (i.dir_encoding == dir_encoding_store
8792
0
          && t->mnem_off != MN_push))
8793
        /* Avoid BSWAP.  */
8794
4.35k
        && t->mnem_off != MN_bswap)
8795
0
      continue;
8796
4.35k
    break;
8797
8798
39.1k
  case 2:
8799
    /* xchg %eax, %eax is a special case. It is an alias for nop
8800
       only in 32bit mode and we can use opcode 0x90.  In 64bit
8801
       mode, we can't use 0x90 for xchg %eax, %eax since it should
8802
       zero-extend %eax to %rax.  */
8803
39.1k
    if (t->base_opcode == 0x90
8804
39.1k
        && t->opcode_space == SPACE_BASE)
8805
0
      {
8806
0
        if (flag_code == CODE_64BIT
8807
0
      && i.types[0].bitfield.instance == Accum
8808
0
      && i.types[0].bitfield.dword
8809
0
      && i.types[1].bitfield.instance == Accum)
8810
0
    continue;
8811
8812
        /* Allow the ModR/M encoding to be requested by using the
8813
     {load} or {store} pseudo prefix.  */
8814
0
        if (i.dir_encoding == dir_encoding_load
8815
0
      || i.dir_encoding == dir_encoding_store)
8816
0
    continue;
8817
0
      }
8818
8819
39.1k
    if (t->base_opcode == MOV_AX_DISP32
8820
39.1k
        && t->opcode_space == SPACE_BASE
8821
39.1k
        && t->mnem_off != MN_movabs)
8822
6
      {
8823
        /* Force 0x8b encoding for "mov foo@GOT, %eax".  */
8824
6
        if (i.reloc[0] == BFD_RELOC_386_GOT32)
8825
0
    continue;
8826
8827
        /* xrelease mov %eax, <disp> is another special case. It must not
8828
     match the accumulator-only encoding of mov.  */
8829
6
        if (i.hle_prefix)
8830
0
    continue;
8831
8832
        /* Allow the ModR/M encoding to be requested by using a suitable
8833
     {load} or {store} pseudo prefix.  */
8834
6
        if (i.dir_encoding == (i.types[0].bitfield.instance == Accum
8835
6
             ? dir_encoding_store
8836
6
             : dir_encoding_load)
8837
6
      && !i.types[0].bitfield.disp64
8838
6
      && !i.types[1].bitfield.disp64)
8839
0
    continue;
8840
6
      }
8841
8842
    /* Allow the ModR/M encoding to be requested by using the {load} or
8843
       {store} pseudo prefix on an applicable insn.  */
8844
39.1k
    if (!t->opcode_modifier.modrm
8845
39.1k
        && i.reg_operands == 1
8846
39.1k
        && i.imm_operands == 1
8847
39.1k
        && (i.dir_encoding == dir_encoding_load
8848
60
      || i.dir_encoding == dir_encoding_store)
8849
39.1k
        && t->opcode_space == SPACE_BASE)
8850
0
      {
8851
0
        if (t->base_opcode == 0xb0 /* mov $imm, %reg */
8852
0
      && i.dir_encoding == dir_encoding_store)
8853
0
    continue;
8854
8855
0
        if ((t->base_opcode | 0x38) == 0x3c /* <alu> $imm, %acc */
8856
0
      && (t->base_opcode != 0x3c /* cmp $imm, %acc */
8857
0
          || i.dir_encoding == dir_encoding_load))
8858
0
    continue;
8859
8860
0
        if (t->base_opcode == 0xa8 /* test $imm, %acc */
8861
0
      && i.dir_encoding == dir_encoding_load)
8862
0
    continue;
8863
0
      }
8864
    /* Fall through.  */
8865
8866
39.1k
  case 3:
8867
39.1k
    if (!(size_match & MATCH_STRAIGHT))
8868
11
      goto check_reverse;
8869
    /* Reverse direction of operands if swapping is possible in the first
8870
       place (operands need to be symmetric) and
8871
       - the load form is requested, and the template is a store form,
8872
       - the store form is requested, and the template is a load form,
8873
       - the non-default (swapped) form is requested.  */
8874
39.1k
    overlap1 = operand_type_and (operand_types[0], operand_types[1]);
8875
8876
39.1k
    j = i.operands - 1 - (t->opcode_space == SPACE_EVEXMAP4
8877
39.1k
        && t->opcode_modifier.vexvvvv);
8878
8879
39.1k
    if (t->opcode_modifier.d && i.reg_operands == i.operands
8880
39.1k
        && !operand_type_all_zero (&overlap1))
8881
0
      switch (i.dir_encoding)
8882
0
        {
8883
0
        case dir_encoding_load:
8884
0
    if (operand_type_check (operand_types[j], anymem)
8885
0
        || t->opcode_modifier.regmem)
8886
0
      goto check_reverse;
8887
0
    break;
8888
8889
0
        case dir_encoding_store:
8890
0
    if (!operand_type_check (operand_types[j], anymem)
8891
0
        && !t->opcode_modifier.regmem)
8892
0
      goto check_reverse;
8893
0
    break;
8894
8895
0
        case dir_encoding_swap:
8896
0
    goto check_reverse;
8897
8898
0
        case dir_encoding_default:
8899
0
    break;
8900
0
        }
8901
8902
    /* If we want store form, we skip the current load.  */
8903
39.1k
    if ((i.dir_encoding == dir_encoding_store
8904
39.1k
         || i.dir_encoding == dir_encoding_swap)
8905
39.1k
        && i.mem_operands == 0
8906
39.1k
        && t->opcode_modifier.load)
8907
0
      continue;
8908
    /* Fall through.  */
8909
39.1k
  case 4:
8910
39.1k
  case 5:
8911
39.1k
    overlap1 = operand_type_and (i.types[1], operand_types[1]);
8912
39.1k
    if (!operand_type_match (overlap0, i.types[0])
8913
39.1k
        || !operand_type_match (overlap1, i.types[1])
8914
39.1k
        || ((check_register & 3) == 3
8915
15.1k
      && !operand_type_register_match (i.types[0],
8916
0
               operand_types[0],
8917
0
               i.types[1],
8918
0
               operand_types[1])))
8919
24.0k
      {
8920
24.0k
        specific_error = progress (i.error);
8921
8922
        /* Check if other direction is valid ...  */
8923
24.0k
        if (!t->opcode_modifier.d)
8924
7.80k
    continue;
8925
8926
16.2k
      check_reverse:
8927
16.2k
        if (!(size_match & MATCH_REVERSE))
8928
16.1k
    continue;
8929
        /* Try reversing direction of operands.  */
8930
71
        j = is_cpu (t, CpuFMA4)
8931
71
      || is_cpu (t, CpuXOP)
8932
71
      || is_cpu (t, CpuAPX_F) ? 1 : i.operands - 1;
8933
71
        overlap0 = operand_type_and (i.types[0], operand_types[j]);
8934
71
        overlap1 = operand_type_and (i.types[j], operand_types[0]);
8935
71
        overlap2 = operand_type_and (i.types[1], operand_types[1]);
8936
71
        gas_assert (t->operands != 3 || !check_register
8937
71
        || is_cpu (t, CpuAPX_F));
8938
71
        if (!operand_type_match (overlap0, i.types[0])
8939
71
      || !operand_type_match (overlap1, i.types[j])
8940
71
      || (t->operands == 3
8941
0
          && !operand_type_match (overlap2, i.types[1]))
8942
71
      || (check_register
8943
0
          && !operand_type_register_match (i.types[0],
8944
0
                   operand_types[j],
8945
0
                   i.types[j],
8946
0
                   operand_types[0])))
8947
71
    {
8948
      /* Does not match either direction.  */
8949
71
      specific_error = progress (i.error);
8950
71
      continue;
8951
71
    }
8952
        /* found_reverse_match holds which variant of D
8953
     we've found.  */
8954
0
        if (!t->opcode_modifier.d)
8955
0
    found_reverse_match = 0;
8956
0
        else if (operand_types[0].bitfield.tbyte)
8957
0
    {
8958
0
      if (t->opcode_modifier.operandconstraint != UGH)
8959
0
        found_reverse_match = Opcode_FloatD;
8960
0
      else
8961
0
        found_reverse_match = ~0;
8962
      /* FSUB{,R} and FDIV{,R} may need a 2nd bit flipped.  */
8963
0
      if ((t->extension_opcode & 4)
8964
0
          && (intel_syntax || intel_mnemonic))
8965
0
        found_reverse_match |= Opcode_FloatR;
8966
0
    }
8967
0
        else if (is_cpu (t, CpuFMA4) || is_cpu (t, CpuXOP))
8968
0
    {
8969
0
      found_reverse_match = Opcode_VexW;
8970
0
      goto check_operands_345;
8971
0
    }
8972
0
        else if (t->opcode_space == SPACE_EVEXMAP4
8973
0
           && t->opcode_modifier.w)
8974
0
    {
8975
0
      found_reverse_match = Opcode_D;
8976
0
      goto check_operands_345;
8977
0
    }
8978
0
        else if (t->opcode_space != SPACE_BASE
8979
0
           && (t->opcode_space != SPACE_0F
8980
         /* MOV to/from CR/DR/TR, as an exception, follow
8981
            the base opcode space encoding model.  */
8982
0
         || (t->base_opcode | 7) != 0x27))
8983
0
    found_reverse_match = (t->base_opcode & 0xee) != 0x6e
8984
0
              ? Opcode_ExtD : Opcode_SIMD_IntD;
8985
0
        else if (!t->opcode_modifier.commutative)
8986
0
    found_reverse_match = Opcode_D;
8987
0
        else
8988
0
    found_reverse_match = ~0;
8989
0
      }
8990
15.1k
    else
8991
15.1k
      {
8992
        /* Found a forward 2 operand match here.  */
8993
15.1k
      check_operands_345:
8994
15.1k
        switch (t->operands)
8995
15.1k
    {
8996
0
    case 5:
8997
0
      overlap4 = operand_type_and (i.types[4], operand_types[4]);
8998
0
      if (!operand_type_match (overlap4, i.types[4])
8999
0
          || !operand_type_register_match (i.types[3],
9000
0
                   operand_types[3],
9001
0
                   i.types[4],
9002
0
                   operand_types[4]))
9003
0
        {
9004
0
          specific_error = progress (i.error);
9005
0
          continue;
9006
0
        }
9007
      /* Fall through.  */
9008
0
    case 4:
9009
0
      overlap3 = operand_type_and (i.types[3], operand_types[3]);
9010
0
      if (!operand_type_match (overlap3, i.types[3])
9011
0
          || ((check_register & 0xa) == 0xa
9012
0
        && !operand_type_register_match (i.types[1],
9013
0
                  operand_types[1],
9014
0
                  i.types[3],
9015
0
                  operand_types[3]))
9016
0
          || ((check_register & 0xc) == 0xc
9017
0
        && !operand_type_register_match (i.types[2],
9018
0
                  operand_types[2],
9019
0
                  i.types[3],
9020
0
                  operand_types[3])))
9021
0
        {
9022
0
          specific_error = progress (i.error);
9023
0
          continue;
9024
0
        }
9025
      /* Fall through.  */
9026
0
    case 3:
9027
0
      overlap2 = operand_type_and (i.types[2], operand_types[2]);
9028
0
      if (!operand_type_match (overlap2, i.types[2])
9029
0
          || ((check_register & 5) == 5
9030
0
        && !operand_type_register_match (i.types[0],
9031
0
                  operand_types[0],
9032
0
                  i.types[2],
9033
0
                  operand_types[2]))
9034
0
          || ((check_register & 6) == 6
9035
0
        && !operand_type_register_match (i.types[1],
9036
0
                  operand_types[1],
9037
0
                  i.types[2],
9038
0
                  operand_types[2])))
9039
0
        {
9040
0
          specific_error = progress (i.error);
9041
0
          continue;
9042
0
        }
9043
0
      break;
9044
15.1k
    }
9045
15.1k
      }
9046
    /* Found either forward/reverse 2, 3 or 4 operand match here:
9047
       slip through to break.  */
9048
48.9k
  }
9049
9050
      /* Check if VEX/EVEX encoding requirements can be satisfied.  */
9051
19.4k
      if (VEX_check_encoding (t))
9052
2
  {
9053
2
    specific_error = progress (i.error);
9054
2
    continue;
9055
2
  }
9056
9057
      /* Check if EGPR operands(r16-r31) are valid.  */
9058
19.4k
      if (check_EgprOperands (t))
9059
0
  {
9060
0
    specific_error = progress (i.error);
9061
0
    continue;
9062
0
  }
9063
9064
      /* Check if vector operands are valid.  */
9065
19.4k
      if (check_VecOperands (t))
9066
1
  {
9067
1
    specific_error = progress (i.error);
9068
1
    continue;
9069
1
  }
9070
9071
      /* Check if APX operands are valid.  */
9072
19.4k
      if (check_APX_operands (t))
9073
0
  {
9074
0
    specific_error = progress (i.error);
9075
0
    continue;
9076
0
  }
9077
9078
      /* Check whether to use the shorter VEX encoding for certain insns where
9079
   the EVEX encoding comes first in the table.  This requires the respective
9080
   AVX-* feature to be explicitly enabled.
9081
9082
   Most of the respective insns have just a single EVEX and a single VEX
9083
   template.  The one that's presently different is generated using the
9084
   Vxy / Exy constructs: There are 3 suffix-less EVEX forms, the latter
9085
   two of which may fall back to their two corresponding VEX forms.  */
9086
19.4k
      j = t->mnem_off != MN_vcvtneps2bf16 ? 1 : 2;
9087
19.4k
      if ((t == current_templates.start || j > 1)
9088
19.4k
    && t->opcode_modifier.disp8memshift
9089
19.4k
    && !t->opcode_modifier.vex
9090
19.4k
    && !need_evex_encoding (t)
9091
19.4k
    && t + j < current_templates.end
9092
19.4k
    && t[j].opcode_modifier.vex)
9093
0
  {
9094
0
    i386_cpu_flags cpu;
9095
0
    unsigned int memshift = i.memshift;
9096
9097
0
    i.memshift = 0;
9098
0
    cpu = cpu_flags_and (cpu_flags_from_attr (t[j].cpu),
9099
0
             cpu_arch_isa_flags);
9100
0
    if (!cpu_flags_all_zero (&cpu)
9101
0
        && (!i.types[0].bitfield.disp8
9102
0
      || !operand_type_check (i.types[0], disp)
9103
0
      || i.op[0].disps->X_op != O_constant
9104
0
      || fits_in_disp8 (i.op[0].disps->X_add_number)))
9105
0
      {
9106
0
        specific_error = progress (internal_error);
9107
0
        t += j - 1;
9108
0
        continue;
9109
0
      }
9110
0
    i.memshift = memshift;
9111
0
  }
9112
9113
      /* If we can optimize a NDD insn to legacy insn, like
9114
   add %r16, %r8, %r8 -> add %r16, %r8,
9115
   add  %r8, %r16, %r8 -> add %r16, %r8, then rematch template.
9116
   Note that the semantics have not been changed.  */
9117
19.4k
      if (optimize
9118
19.4k
    && !i.no_optimize
9119
19.4k
    && i.encoding != encoding_evex
9120
19.4k
    && ((t + 1 < current_templates.end
9121
0
         && !t[1].opcode_modifier.evex
9122
0
         && t[1].opcode_space <= SPACE_0F38
9123
0
         && t->opcode_modifier.vexvvvv == VexVVVV_DST)
9124
0
        || t->mnem_off == MN_movbe)
9125
19.4k
    && (i.types[i.operands - 1].bitfield.dword
9126
0
        || i.types[i.operands - 1].bitfield.qword))
9127
0
  {
9128
0
    unsigned int match_dest_op = can_convert_NDD_to_legacy (t);
9129
9130
0
    if (match_dest_op != (unsigned int) ~0)
9131
0
      {
9132
0
        size_match = true;
9133
        /* We ensure that the next template has the same input
9134
     operands as the original matching template by the first
9135
     opernd (ATT). To avoid someone support new NDD insns and
9136
     put it in the wrong position.  */
9137
0
        overlap0 = operand_type_and (i.types[0],
9138
0
             t[1].operand_types[0]);
9139
0
        if (t->opcode_modifier.d)
9140
0
    overlap1 = operand_type_and (i.types[0],
9141
0
               t[1].operand_types[1]);
9142
0
        if (!operand_type_match (overlap0, i.types[0])
9143
0
      && (!t->opcode_modifier.d
9144
0
          || !operand_type_match (overlap1, i.types[0])))
9145
0
    size_match = false;
9146
9147
0
        if (size_match
9148
0
      && (t[1].opcode_space <= SPACE_0F
9149
          /* Some non-legacy-map0/1 insns can be shorter when
9150
       legacy-encoded and when no REX prefix is required.  */
9151
0
          || (!check_EgprOperands (t + 1)
9152
0
        && !check_Rex_required ()
9153
0
        && !i.op[i.operands - 1].regs->reg_type.bitfield.qword)))
9154
0
    {
9155
0
      if (i.operands > 2 && match_dest_op == i.operands - 3)
9156
0
        swap_2_operands (match_dest_op, i.operands - 2);
9157
9158
0
      --i.operands;
9159
0
      --i.reg_operands;
9160
9161
0
      if (t->mnem_off == MN_movbe)
9162
0
        {
9163
0
          gas_assert (t[1].mnem_off == MN_bswap);
9164
0
          ++current_templates.end;
9165
0
        }
9166
9167
0
      specific_error = progress (internal_error);
9168
0
      continue;
9169
0
    }
9170
9171
0
      }
9172
0
  }
9173
9174
      /* We've found a match; break out of loop.  */
9175
19.4k
      break;
9176
19.4k
    }
9177
9178
696k
#undef progress
9179
9180
696k
  if (t == current_templates.end)
9181
34.1k
    {
9182
      /* We found no match.  */
9183
34.1k
      i.error = specific_error;
9184
34.1k
      return NULL;
9185
34.1k
    }
9186
9187
662k
  if (!quiet_warnings)
9188
662k
    {
9189
662k
      if (!intel_syntax
9190
662k
    && (i.jumpabsolute != (t->opcode_modifier.jump == JUMP_ABSOLUTE)))
9191
0
  as_warn (_("indirect %s without `*'"), insn_name (t));
9192
9193
662k
      if (t->opcode_modifier.isprefix
9194
662k
    && t->opcode_modifier.mnemonicsize == IGNORESIZE)
9195
1
  {
9196
    /* Warn them that a data or address size prefix doesn't
9197
       affect assembly of the next line of code.  */
9198
1
    as_warn (_("stand-alone `%s' prefix"), insn_name (t));
9199
1
  }
9200
662k
    }
9201
9202
  /* Copy the template we found.  */
9203
662k
  install_template (t);
9204
9205
662k
  if (addr_prefix_disp != -1)
9206
18.2k
    i.tm.operand_types[addr_prefix_disp]
9207
18.2k
      = operand_types[addr_prefix_disp];
9208
9209
  /* APX insns acting on byte operands are WIG, yet that can't be expressed
9210
     in the templates (they're also covering word/dword/qword operands).  */
9211
662k
  if (t->opcode_space == SPACE_EVEXMAP4 && !t->opcode_modifier.vexw &&
9212
662k
      i.types[i.operands - 1].bitfield.byte)
9213
0
    {
9214
0
      gas_assert (t->opcode_modifier.w);
9215
0
      i.tm.opcode_modifier.vexw = VEXWIG;
9216
0
    }
9217
9218
662k
  switch (found_reverse_match)
9219
662k
    {
9220
662k
    case 0:
9221
662k
      break;
9222
9223
0
    case Opcode_FloatR:
9224
0
    case Opcode_FloatR | Opcode_FloatD:
9225
0
      i.tm.extension_opcode ^= Opcode_FloatR >> 3;
9226
0
      found_reverse_match &= Opcode_FloatD;
9227
9228
      /* Fall through.  */
9229
0
    default:
9230
      /* If we found a reverse match we must alter the opcode direction
9231
   bit and clear/flip the regmem modifier one.  found_reverse_match
9232
   holds bits to change (different for int & float insns).  */
9233
9234
0
      i.tm.base_opcode ^= found_reverse_match;
9235
9236
0
      if (i.tm.opcode_space == SPACE_EVEXMAP4)
9237
0
  goto swap_first_2;
9238
9239
      /* Certain SIMD insns have their load forms specified in the opcode
9240
   table, and hence we need to _set_ RegMem instead of clearing it.
9241
   We need to avoid setting the bit though on insns like KMOVW.  */
9242
0
      i.tm.opcode_modifier.regmem
9243
0
  = i.tm.opcode_modifier.modrm && i.tm.opcode_modifier.d
9244
0
    && i.tm.operands > 2U - i.tm.opcode_modifier.sse2avx
9245
0
    && !i.tm.opcode_modifier.regmem;
9246
9247
      /* Fall through.  */
9248
0
    case ~0:
9249
0
      i.tm.operand_types[0] = operand_types[i.operands - 1];
9250
0
      i.tm.operand_types[i.operands - 1] = operand_types[0];
9251
0
      break;
9252
9253
0
    case Opcode_VexW:
9254
      /* Only the first two register operands need reversing, alongside
9255
   flipping VEX.W.  */
9256
0
      i.tm.opcode_modifier.vexw ^= VEXW0 ^ VEXW1;
9257
9258
0
    swap_first_2:
9259
0
      j = i.tm.operand_types[0].bitfield.imm8;
9260
0
      i.tm.operand_types[j] = operand_types[j + 1];
9261
0
      i.tm.operand_types[j + 1] = operand_types[j];
9262
0
      break;
9263
662k
    }
9264
9265
662k
  return t;
9266
662k
}
9267
9268
static int
9269
check_string (void)
9270
0
{
9271
0
  unsigned int es_op = i.tm.opcode_modifier.isstring - IS_STRING_ES_OP0;
9272
0
  unsigned int op = i.tm.operand_types[0].bitfield.baseindex ? es_op : 0;
9273
9274
0
  if (i.seg[op] != NULL && i.seg[op] != reg_es)
9275
0
    {
9276
0
      as_bad (_("`%s' operand %u must use `%ses' segment"),
9277
0
        insn_name (&i.tm),
9278
0
        intel_syntax ? i.tm.operands - es_op : es_op + 1,
9279
0
        register_prefix);
9280
0
      return 0;
9281
0
    }
9282
9283
  /* There's only ever one segment override allowed per instruction.
9284
     This instruction possibly has a legal segment override on the
9285
     second operand, so copy the segment to where non-string
9286
     instructions store it, allowing common code.  */
9287
0
  i.seg[op] = i.seg[1];
9288
9289
0
  return 1;
9290
0
}
9291
9292
static int
9293
process_suffix (void)
9294
662k
{
9295
662k
  bool is_movx = false;
9296
9297
  /* If matched instruction specifies an explicit instruction mnemonic
9298
     suffix, use it.  */
9299
662k
  if (i.tm.opcode_modifier.size == SIZE16)
9300
1
    i.suffix = WORD_MNEM_SUFFIX;
9301
662k
  else if (i.tm.opcode_modifier.size == SIZE32)
9302
918
    i.suffix = LONG_MNEM_SUFFIX;
9303
661k
  else if (i.tm.opcode_modifier.size == SIZE64)
9304
3.02k
    i.suffix = QWORD_MNEM_SUFFIX;
9305
658k
  else if (i.reg_operands
9306
658k
     && (i.operands > 1 || i.types[0].bitfield.class == Reg)
9307
658k
     && i.tm.opcode_modifier.operandconstraint != ADDR_PREFIX_OP_REG)
9308
60
    {
9309
60
      unsigned int numop = i.operands;
9310
9311
      /* MOVSX/MOVZX */
9312
60
      is_movx = (i.tm.opcode_space == SPACE_0F
9313
60
     && (i.tm.base_opcode | 8) == 0xbe)
9314
60
    || (i.tm.opcode_space == SPACE_BASE
9315
60
        && i.tm.base_opcode == 0x63
9316
60
        && is_cpu (&i.tm, Cpu64));
9317
9318
      /* movsx/movzx want only their source operand considered here, for the
9319
   ambiguity checking below.  The suffix will be replaced afterwards
9320
   to represent the destination (register).  */
9321
60
      if (is_movx && (i.tm.opcode_modifier.w || i.tm.base_opcode == 0x63))
9322
0
  --i.operands;
9323
9324
      /* crc32 needs REX.W set regardless of suffix / source operand size.  */
9325
60
      if (i.tm.mnem_off == MN_crc32 && i.tm.operand_types[1].bitfield.qword)
9326
0
        i.rex |= REX_W;
9327
9328
      /* If there's no instruction mnemonic suffix we try to invent one
9329
   based on GPR operands.  */
9330
60
      if (!i.suffix)
9331
60
  {
9332
    /* We take i.suffix from the last register operand specified,
9333
       Destination register type is more significant than source
9334
       register type.  crc32 in SSE4.2 prefers source register
9335
       type. */
9336
60
    unsigned int op = i.tm.mnem_off == MN_crc32 ? 1 : i.operands;
9337
9338
60
    while (op--)
9339
60
      if (i.tm.operand_types[op].bitfield.instance == InstanceNone
9340
60
    || i.tm.operand_types[op].bitfield.instance == Accum)
9341
60
        {
9342
60
    if (i.types[op].bitfield.class != Reg)
9343
0
      continue;
9344
60
    if (i.types[op].bitfield.byte)
9345
60
      i.suffix = BYTE_MNEM_SUFFIX;
9346
0
    else if (i.types[op].bitfield.word)
9347
0
      i.suffix = WORD_MNEM_SUFFIX;
9348
0
    else if (i.types[op].bitfield.dword)
9349
0
      i.suffix = LONG_MNEM_SUFFIX;
9350
0
    else if (i.types[op].bitfield.qword)
9351
0
      i.suffix = QWORD_MNEM_SUFFIX;
9352
0
    else
9353
0
      continue;
9354
60
    break;
9355
60
        }
9356
9357
    /* As an exception, movsx/movzx silently default to a byte source
9358
       in AT&T mode.  */
9359
60
    if (is_movx && i.tm.opcode_modifier.w && !i.suffix && !intel_syntax)
9360
0
      i.suffix = BYTE_MNEM_SUFFIX;
9361
60
  }
9362
0
      else if (i.suffix == BYTE_MNEM_SUFFIX)
9363
0
  {
9364
0
    if (!check_byte_reg ())
9365
0
      return 0;
9366
0
  }
9367
0
      else if (i.suffix == LONG_MNEM_SUFFIX)
9368
0
  {
9369
0
    if (!check_long_reg ())
9370
0
      return 0;
9371
0
  }
9372
0
      else if (i.suffix == QWORD_MNEM_SUFFIX)
9373
0
  {
9374
0
    if (!check_qword_reg ())
9375
0
      return 0;
9376
0
  }
9377
0
      else if (i.suffix == WORD_MNEM_SUFFIX)
9378
0
  {
9379
0
    if (!check_word_reg ())
9380
0
      return 0;
9381
0
  }
9382
0
      else if (intel_syntax
9383
0
         && i.tm.opcode_modifier.mnemonicsize == IGNORESIZE)
9384
  /* Do nothing if the instruction is going to ignore the prefix.  */
9385
0
  ;
9386
0
      else
9387
0
  abort ();
9388
9389
      /* Undo the movsx/movzx change done above.  */
9390
60
      i.operands = numop;
9391
60
    }
9392
658k
  else if (i.tm.opcode_modifier.mnemonicsize == DEFAULTSIZE
9393
658k
     && !i.suffix)
9394
408
    {
9395
408
      i.suffix = stackop_size;
9396
408
      if (stackop_size == LONG_MNEM_SUFFIX)
9397
0
  {
9398
    /* stackop_size is set to LONG_MNEM_SUFFIX for the
9399
       .code16gcc directive to support 16-bit mode with
9400
       32-bit address.  For IRET without a suffix, generate
9401
       16-bit IRET (opcode 0xcf) to return from an interrupt
9402
       handler.  */
9403
0
    if (i.tm.base_opcode == 0xcf)
9404
0
      {
9405
0
        i.suffix = WORD_MNEM_SUFFIX;
9406
0
        as_warn (_("generating 16-bit `iret' for .code16gcc directive"));
9407
0
      }
9408
    /* Warn about changed behavior for segment register push/pop.  */
9409
0
    else if ((i.tm.base_opcode | 1) == 0x07)
9410
0
      as_warn (_("generating 32-bit `%s', unlike earlier gas versions"),
9411
0
         insn_name (&i.tm));
9412
0
  }
9413
408
    }
9414
658k
  else if (!i.suffix
9415
658k
     && (i.tm.opcode_modifier.jump == JUMP_ABSOLUTE
9416
658k
         || i.tm.opcode_modifier.jump == JUMP_BYTE
9417
658k
         || i.tm.opcode_modifier.jump == JUMP_INTERSEGMENT
9418
658k
         || (i.tm.opcode_space == SPACE_0F
9419
658k
       && i.tm.base_opcode == 0x01 /* [ls][gi]dt */
9420
658k
       && i.tm.extension_opcode <= 3)))
9421
877
    {
9422
877
      switch (flag_code)
9423
877
  {
9424
423
  case CODE_64BIT:
9425
423
    if (!i.tm.opcode_modifier.no_qsuf)
9426
423
      {
9427
423
        if (i.tm.opcode_modifier.jump == JUMP_BYTE
9428
423
      || i.tm.opcode_modifier.no_lsuf)
9429
423
    i.suffix = QWORD_MNEM_SUFFIX;
9430
423
        break;
9431
423
      }
9432
    /* Fall through.  */
9433
339
  case CODE_32BIT:
9434
339
    if (!i.tm.opcode_modifier.no_lsuf)
9435
339
      i.suffix = LONG_MNEM_SUFFIX;
9436
339
    break;
9437
115
  case CODE_16BIT:
9438
115
    if (!i.tm.opcode_modifier.no_wsuf)
9439
115
      i.suffix = WORD_MNEM_SUFFIX;
9440
115
    break;
9441
877
  }
9442
877
    }
9443
9444
662k
  if (!i.suffix
9445
662k
      && (i.tm.opcode_modifier.mnemonicsize != DEFAULTSIZE
9446
    /* Also cover lret/retf/iret in 64-bit mode.  */
9447
657k
    || (flag_code == CODE_64BIT
9448
408
        && !i.tm.opcode_modifier.no_lsuf
9449
408
        && !i.tm.opcode_modifier.no_qsuf))
9450
662k
      && i.tm.opcode_modifier.mnemonicsize != IGNORESIZE
9451
      /* Explicit sizing prefixes are assumed to disambiguate insns.  */
9452
662k
      && !i.prefix[DATA_PREFIX] && !(i.prefix[REX_PREFIX] & REX_W)
9453
      /* Accept FLDENV et al without suffix.  */
9454
662k
      && (i.tm.opcode_modifier.no_ssuf || i.tm.opcode_modifier.floatmf))
9455
656k
    {
9456
656k
      unsigned int suffixes, evex = 0;
9457
9458
656k
      suffixes = !i.tm.opcode_modifier.no_bsuf;
9459
656k
      if (!i.tm.opcode_modifier.no_wsuf)
9460
16.4k
  suffixes |= 1 << 1;
9461
656k
      if (!i.tm.opcode_modifier.no_lsuf)
9462
16.4k
  suffixes |= 1 << 2;
9463
656k
      if (!i.tm.opcode_modifier.no_ssuf)
9464
22
  suffixes |= 1 << 4;
9465
656k
      if (flag_code == CODE_64BIT && !i.tm.opcode_modifier.no_qsuf)
9466
5.23k
  suffixes |= 1 << 5;
9467
9468
      /* For [XYZ]MMWORD operands inspect operand sizes.  While generally
9469
   also suitable for AT&T syntax mode, it was requested that this be
9470
   restricted to just Intel syntax.  */
9471
656k
      if (intel_syntax && is_any_vex_encoding (&i.tm)
9472
656k
    && !i.broadcast.type && !i.broadcast.bytes)
9473
0
  {
9474
0
    unsigned int op;
9475
9476
0
    for (op = 0; op < i.tm.operands; ++op)
9477
0
      {
9478
0
        if (vector_size < VSZ512)
9479
0
    {
9480
0
      i.tm.operand_types[op].bitfield.zmmword = 0;
9481
0
      if (vector_size < VSZ256)
9482
0
        {
9483
0
          i.tm.operand_types[op].bitfield.ymmword = 0;
9484
0
          if (i.tm.operand_types[op].bitfield.xmmword
9485
0
        && i.tm.opcode_modifier.evex == EVEXDYN)
9486
0
      i.tm.opcode_modifier.evex = EVEX128;
9487
0
        }
9488
0
      else if (i.tm.operand_types[op].bitfield.ymmword
9489
0
         && !i.tm.operand_types[op].bitfield.xmmword
9490
0
         && i.tm.opcode_modifier.evex == EVEXDYN)
9491
0
        i.tm.opcode_modifier.evex = EVEX256;
9492
0
    }
9493
0
        else if (i.tm.opcode_modifier.evex
9494
0
           && !cpu_arch_flags.bitfield.cpuavx512vl)
9495
0
    {
9496
0
      if (i.tm.operand_types[op].bitfield.ymmword)
9497
0
        i.tm.operand_types[op].bitfield.xmmword = 0;
9498
0
      if (i.tm.operand_types[op].bitfield.zmmword)
9499
0
        i.tm.operand_types[op].bitfield.ymmword = 0;
9500
0
      if (i.tm.opcode_modifier.evex == EVEXDYN)
9501
0
        i.tm.opcode_modifier.evex = EVEX512;
9502
0
    }
9503
9504
0
        if (i.tm.operand_types[op].bitfield.xmmword
9505
0
      + i.tm.operand_types[op].bitfield.ymmword
9506
0
      + i.tm.operand_types[op].bitfield.zmmword < 2)
9507
0
    continue;
9508
9509
        /* Any properly sized operand disambiguates the insn.  */
9510
0
        if (i.types[op].bitfield.xmmword
9511
0
      || i.types[op].bitfield.ymmword
9512
0
      || i.types[op].bitfield.zmmword)
9513
0
    {
9514
0
      suffixes &= ~(7 << 6);
9515
0
      evex = 0;
9516
0
      break;
9517
0
    }
9518
9519
0
        if ((i.flags[op] & Operand_Mem)
9520
0
      && i.tm.operand_types[op].bitfield.unspecified)
9521
0
    {
9522
0
      if (i.tm.operand_types[op].bitfield.xmmword)
9523
0
        suffixes |= 1 << 6;
9524
0
      if (i.tm.operand_types[op].bitfield.ymmword)
9525
0
        suffixes |= 1 << 7;
9526
0
      if (i.tm.operand_types[op].bitfield.zmmword)
9527
0
        suffixes |= 1 << 8;
9528
0
      if (i.tm.opcode_modifier.evex)
9529
0
        evex = EVEX512;
9530
0
    }
9531
0
      }
9532
0
  }
9533
9534
      /* Are multiple suffixes / operand sizes allowed?  */
9535
656k
      if (suffixes & (suffixes - 1))
9536
16.4k
  {
9537
16.4k
    if (intel_syntax
9538
16.4k
        && (i.tm.opcode_modifier.mnemonicsize != DEFAULTSIZE
9539
0
      || operand_check == check_error))
9540
0
      {
9541
0
        as_bad (_("ambiguous operand size for `%s'"), insn_name (&i.tm));
9542
0
        return 0;
9543
0
      }
9544
16.4k
    if (operand_check == check_error)
9545
0
      {
9546
0
        as_bad (_("no instruction mnemonic suffix given and "
9547
0
      "no register operands; can't size `%s'"), insn_name (&i.tm));
9548
0
        return 0;
9549
0
      }
9550
16.4k
    if (operand_check == check_warning)
9551
16.4k
      as_warn (_("%s; using default for `%s'"),
9552
16.4k
           intel_syntax
9553
16.4k
           ? _("ambiguous operand size")
9554
16.4k
           : _("no instruction mnemonic suffix given and "
9555
16.4k
         "no register operands"),
9556
16.4k
           insn_name (&i.tm));
9557
9558
16.4k
    if (i.tm.opcode_modifier.floatmf)
9559
22
      i.suffix = SHORT_MNEM_SUFFIX;
9560
16.4k
    else if (is_movx)
9561
0
      /* handled below */;
9562
16.4k
    else if (evex)
9563
0
      i.tm.opcode_modifier.evex = evex;
9564
16.4k
    else if (flag_code == CODE_16BIT)
9565
6.94k
      i.suffix = WORD_MNEM_SUFFIX;
9566
9.52k
    else if (!i.tm.opcode_modifier.no_lsuf)
9567
9.52k
      i.suffix = LONG_MNEM_SUFFIX;
9568
0
    else
9569
0
      i.suffix = QWORD_MNEM_SUFFIX;
9570
16.4k
  }
9571
656k
    }
9572
9573
662k
  if (is_movx)
9574
0
    {
9575
      /* In Intel syntax, movsx/movzx must have a "suffix" (checked above).
9576
   In AT&T syntax, if there is no suffix (warned about above), the default
9577
   will be byte extension.  */
9578
0
      if (i.tm.opcode_modifier.w && i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
9579
0
  i.tm.base_opcode |= 1;
9580
9581
      /* For further processing, the suffix should represent the destination
9582
   (register).  This is already the case when one was used with
9583
   mov[sz][bw]*, but we need to replace it for mov[sz]x, or if there was
9584
   no suffix to begin with.  */
9585
0
      if (i.tm.opcode_modifier.w || i.tm.base_opcode == 0x63 || !i.suffix)
9586
0
  {
9587
0
    if (i.types[1].bitfield.word)
9588
0
      i.suffix = WORD_MNEM_SUFFIX;
9589
0
    else if (i.types[1].bitfield.qword)
9590
0
      i.suffix = QWORD_MNEM_SUFFIX;
9591
0
    else
9592
0
      i.suffix = LONG_MNEM_SUFFIX;
9593
9594
0
    i.tm.opcode_modifier.w = 0;
9595
0
  }
9596
0
    }
9597
9598
662k
  if (!i.tm.opcode_modifier.modrm && i.reg_operands && i.tm.operands < 3)
9599
60
    i.short_form = (i.tm.operand_types[0].bitfield.class == Reg)
9600
60
       != (i.tm.operand_types[1].bitfield.class == Reg);
9601
9602
  /* Change the opcode based on the operand size given by i.suffix.  */
9603
662k
  switch (i.suffix)
9604
662k
    {
9605
    /* Size floating point instruction.  */
9606
11.0k
    case LONG_MNEM_SUFFIX:
9607
11.0k
      if (i.tm.opcode_modifier.floatmf)
9608
0
  {
9609
0
    i.tm.base_opcode ^= 4;
9610
0
    break;
9611
0
  }
9612
    /* fall through */
9613
18.0k
    case WORD_MNEM_SUFFIX:
9614
21.5k
    case QWORD_MNEM_SUFFIX:
9615
      /* It's not a byte, select word/dword operation.  */
9616
21.5k
      if (i.tm.opcode_modifier.w)
9617
5.52k
  {
9618
5.52k
    if (i.short_form)
9619
0
      i.tm.base_opcode |= 8;
9620
5.52k
    else
9621
5.52k
      i.tm.base_opcode |= 1;
9622
5.52k
  }
9623
9624
      /* Set mode64 for an operand.  */
9625
21.5k
      if (i.suffix == QWORD_MNEM_SUFFIX)
9626
3.45k
  {
9627
3.45k
    if (flag_code == CODE_64BIT
9628
3.45k
        && !i.tm.opcode_modifier.norex64
9629
3.45k
        && !i.tm.opcode_modifier.vexw
9630
        /* Special case for xchg %rax,%rax.  It is NOP and doesn't
9631
     need rex64. */
9632
3.45k
        && ! (i.operands == 2
9633
3.02k
        && i.tm.base_opcode == 0x90
9634
3.02k
        && i.tm.opcode_space == SPACE_BASE
9635
3.02k
        && i.types[0].bitfield.instance == Accum
9636
3.02k
        && i.types[1].bitfield.instance == Accum))
9637
3.02k
      i.rex |= REX_W;
9638
9639
3.45k
    break;
9640
3.45k
  }
9641
9642
    /* fall through */
9643
18.1k
    case SHORT_MNEM_SUFFIX:
9644
      /* Now select between word & dword operations via the operand
9645
   size prefix, except for instructions that will ignore this
9646
   prefix anyway.  */
9647
18.1k
      if (i.tm.opcode_modifier.mnemonicsize != IGNORESIZE
9648
18.1k
    && !i.tm.opcode_modifier.floatmf
9649
18.1k
    && (!is_any_vex_encoding (&i.tm)
9650
18.0k
        || i.tm.opcode_space == SPACE_EVEXMAP4)
9651
18.1k
    && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
9652
18.0k
        || (flag_code == CODE_64BIT
9653
18.0k
      && i.tm.opcode_modifier.jump == JUMP_BYTE)))
9654
6
  {
9655
6
    unsigned int prefix = DATA_PREFIX_OPCODE;
9656
9657
6
    if (i.tm.opcode_modifier.jump == JUMP_BYTE) /* jcxz, loop */
9658
0
      prefix = ADDR_PREFIX_OPCODE;
9659
9660
    /* The DATA PREFIX of EVEX promoted from legacy APX instructions
9661
       needs to be adjusted.  */
9662
6
    if (i.tm.opcode_space == SPACE_EVEXMAP4)
9663
0
      {
9664
0
        gas_assert (!i.tm.opcode_modifier.opcodeprefix);
9665
0
        i.tm.opcode_modifier.opcodeprefix = PREFIX_0X66;
9666
0
      }
9667
6
    else if (!add_prefix (prefix))
9668
0
      return 0;
9669
6
  }
9670
9671
18.1k
      break;
9672
9673
641k
    case 0:
9674
      /* Select word/dword/qword operation with explicit data sizing prefix
9675
   when there are no suitable register operands.  */
9676
641k
      if (i.tm.opcode_modifier.w
9677
641k
    && (i.prefix[DATA_PREFIX] || (i.prefix[REX_PREFIX] & REX_W))
9678
641k
    && (!i.reg_operands
9679
0
        || (i.reg_operands == 1
9680
          /* ShiftCount */
9681
0
      && (i.tm.operand_types[0].bitfield.instance == RegC
9682
          /* InOutPortReg */
9683
0
          || i.tm.operand_types[0].bitfield.instance == RegD
9684
0
          || i.tm.operand_types[1].bitfield.instance == RegD
9685
0
          || i.tm.mnem_off == MN_crc32))))
9686
0
  i.tm.base_opcode |= 1;
9687
641k
      break;
9688
662k
    }
9689
9690
662k
  if (i.tm.opcode_modifier.operandconstraint == ADDR_PREFIX_OP_REG)
9691
0
    {
9692
0
      gas_assert (!i.suffix);
9693
0
      gas_assert (i.reg_operands);
9694
9695
0
      if (i.tm.operand_types[0].bitfield.instance == Accum
9696
0
    || i.operands == 1)
9697
0
  {
9698
    /* The address size override prefix changes the size of the
9699
       first operand.  */
9700
0
    if (flag_code == CODE_64BIT
9701
0
        && i.op[0].regs->reg_type.bitfield.word)
9702
0
      {
9703
0
        as_bad (_("16-bit addressing unavailable for `%s'"),
9704
0
          insn_name (&i.tm));
9705
0
        return 0;
9706
0
      }
9707
9708
0
    if ((flag_code == CODE_32BIT
9709
0
         ? i.op[0].regs->reg_type.bitfield.word
9710
0
         : i.op[0].regs->reg_type.bitfield.dword)
9711
0
        && !add_prefix (ADDR_PREFIX_OPCODE))
9712
0
      return 0;
9713
0
  }
9714
0
      else
9715
0
  {
9716
    /* Check invalid register operand when the address size override
9717
       prefix changes the size of register operands.  */
9718
0
    unsigned int op;
9719
0
    enum { need_word, need_dword, need_qword } need;
9720
9721
    /* Check the register operand for the address size prefix if
9722
       the memory operand has no real registers, like symbol, DISP
9723
       or bogus (x32-only) symbol(%rip) when symbol(%eip) is meant.  */
9724
0
    if (i.mem_operands == 1
9725
0
        && i.reg_operands == 1
9726
0
        && i.operands == 2
9727
0
        && i.types[1].bitfield.class == Reg
9728
0
        && (flag_code == CODE_32BIT
9729
0
      ? i.op[1].regs->reg_type.bitfield.word
9730
0
      : i.op[1].regs->reg_type.bitfield.dword)
9731
0
        && ((i.base_reg == NULL && i.index_reg == NULL)
9732
0
#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
9733
0
      || (x86_elf_abi == X86_64_X32_ABI
9734
0
          && i.base_reg
9735
0
          && i.base_reg->reg_num == RegIP
9736
0
          && i.base_reg->reg_type.bitfield.qword))
9737
#else
9738
      || 0)
9739
#endif
9740
0
        && !add_prefix (ADDR_PREFIX_OPCODE))
9741
0
      return 0;
9742
9743
0
    if (flag_code == CODE_32BIT)
9744
0
      need = i.prefix[ADDR_PREFIX] ? need_word : need_dword;
9745
0
    else if (i.prefix[ADDR_PREFIX])
9746
0
      need = need_dword;
9747
0
    else
9748
0
      need = flag_code == CODE_64BIT ? need_qword : need_word;
9749
9750
0
    for (op = 0; op < i.operands; op++)
9751
0
      {
9752
0
        if (i.types[op].bitfield.class != Reg)
9753
0
    continue;
9754
9755
0
        switch (need)
9756
0
    {
9757
0
    case need_word:
9758
0
      if (i.op[op].regs->reg_type.bitfield.word)
9759
0
        continue;
9760
0
      break;
9761
0
    case need_dword:
9762
0
      if (i.op[op].regs->reg_type.bitfield.dword)
9763
0
        continue;
9764
0
      break;
9765
0
    case need_qword:
9766
0
      if (i.op[op].regs->reg_type.bitfield.qword)
9767
0
        continue;
9768
0
      break;
9769
0
    }
9770
9771
0
        as_bad (_("invalid register operand size for `%s'"),
9772
0
          insn_name (&i.tm));
9773
0
        return 0;
9774
0
      }
9775
0
  }
9776
0
    }
9777
9778
662k
  return 1;
9779
662k
}
9780
9781
static int
9782
check_byte_reg (void)
9783
0
{
9784
0
  int op;
9785
9786
0
  for (op = i.operands; --op >= 0;)
9787
0
    {
9788
      /* Skip non-register operands. */
9789
0
      if (i.types[op].bitfield.class != Reg)
9790
0
  continue;
9791
9792
      /* If this is an eight bit register, it's OK.  If it's the 16 or
9793
   32 bit version of an eight bit register, we will just use the
9794
   low portion, and that's OK too.  */
9795
0
      if (i.types[op].bitfield.byte)
9796
0
  continue;
9797
9798
      /* I/O port address operands are OK too.  */
9799
0
      if (i.tm.operand_types[op].bitfield.instance == RegD
9800
0
    && i.tm.operand_types[op].bitfield.word)
9801
0
  continue;
9802
9803
      /* crc32 only wants its source operand checked here.  */
9804
0
      if (i.tm.mnem_off == MN_crc32 && op != 0)
9805
0
  continue;
9806
9807
      /* Any other register is bad.  */
9808
0
      as_bad (_("`%s%s' not allowed with `%s%c'"),
9809
0
        register_prefix, i.op[op].regs->reg_name,
9810
0
        insn_name (&i.tm), i.suffix);
9811
0
      return 0;
9812
0
    }
9813
0
  return 1;
9814
0
}
9815
9816
static int
9817
check_long_reg (void)
9818
0
{
9819
0
  int op;
9820
9821
0
  for (op = i.operands; --op >= 0;)
9822
    /* Skip non-register operands. */
9823
0
    if (i.types[op].bitfield.class != Reg)
9824
0
      continue;
9825
    /* Reject eight bit registers, except where the template requires
9826
       them. (eg. movzb)  */
9827
0
    else if (i.types[op].bitfield.byte
9828
0
       && (i.tm.operand_types[op].bitfield.class == Reg
9829
0
     || i.tm.operand_types[op].bitfield.instance == Accum)
9830
0
       && (i.tm.operand_types[op].bitfield.word
9831
0
     || i.tm.operand_types[op].bitfield.dword))
9832
0
      {
9833
0
  as_bad (_("`%s%s' not allowed with `%s%c'"),
9834
0
    register_prefix,
9835
0
    i.op[op].regs->reg_name,
9836
0
    insn_name (&i.tm),
9837
0
    i.suffix);
9838
0
  return 0;
9839
0
      }
9840
    /* Error if the e prefix on a general reg is missing, or if the r
9841
       prefix on a general reg is present.  */
9842
0
    else if ((i.types[op].bitfield.word
9843
0
        || i.types[op].bitfield.qword)
9844
0
       && (i.tm.operand_types[op].bitfield.class == Reg
9845
0
     || i.tm.operand_types[op].bitfield.instance == Accum)
9846
0
       && i.tm.operand_types[op].bitfield.dword)
9847
0
      {
9848
0
  as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
9849
0
    register_prefix, i.op[op].regs->reg_name,
9850
0
    i.suffix);
9851
0
  return 0;
9852
0
      }
9853
0
  return 1;
9854
0
}
9855
9856
static int
9857
check_qword_reg (void)
9858
0
{
9859
0
  int op;
9860
9861
0
  for (op = i.operands; --op >= 0; )
9862
    /* Skip non-register operands. */
9863
0
    if (i.types[op].bitfield.class != Reg)
9864
0
      continue;
9865
    /* Reject eight bit registers, except where the template requires
9866
       them. (eg. movzb)  */
9867
0
    else if (i.types[op].bitfield.byte
9868
0
       && (i.tm.operand_types[op].bitfield.class == Reg
9869
0
     || i.tm.operand_types[op].bitfield.instance == Accum)
9870
0
       && (i.tm.operand_types[op].bitfield.word
9871
0
     || i.tm.operand_types[op].bitfield.dword
9872
0
     || i.tm.operand_types[op].bitfield.qword))
9873
0
      {
9874
0
  as_bad (_("`%s%s' not allowed with `%s%c'"),
9875
0
    register_prefix,
9876
0
    i.op[op].regs->reg_name,
9877
0
    insn_name (&i.tm),
9878
0
    i.suffix);
9879
0
  return 0;
9880
0
      }
9881
    /* Error if the r prefix on a general reg is missing.  */
9882
0
    else if ((i.types[op].bitfield.word
9883
0
        || i.types[op].bitfield.dword)
9884
0
       && (i.tm.operand_types[op].bitfield.class == Reg
9885
0
     || i.tm.operand_types[op].bitfield.instance == Accum)
9886
0
       && i.tm.operand_types[op].bitfield.qword)
9887
0
      {
9888
  /* Prohibit these changes in the 64bit mode, since the
9889
     lowering is more complicated.  */
9890
0
  as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
9891
0
    register_prefix, i.op[op].regs->reg_name, i.suffix);
9892
0
  return 0;
9893
0
      }
9894
0
  return 1;
9895
0
}
9896
9897
static int
9898
check_word_reg (void)
9899
0
{
9900
0
  int op;
9901
0
  for (op = i.operands; --op >= 0;)
9902
    /* Skip non-register operands. */
9903
0
    if (i.types[op].bitfield.class != Reg)
9904
0
      continue;
9905
    /* Reject eight bit registers, except where the template requires
9906
       them. (eg. movzb)  */
9907
0
    else if (i.types[op].bitfield.byte
9908
0
       && (i.tm.operand_types[op].bitfield.class == Reg
9909
0
     || i.tm.operand_types[op].bitfield.instance == Accum)
9910
0
       && (i.tm.operand_types[op].bitfield.word
9911
0
     || i.tm.operand_types[op].bitfield.dword))
9912
0
      {
9913
0
  as_bad (_("`%s%s' not allowed with `%s%c'"),
9914
0
    register_prefix,
9915
0
    i.op[op].regs->reg_name,
9916
0
    insn_name (&i.tm),
9917
0
    i.suffix);
9918
0
  return 0;
9919
0
      }
9920
    /* Error if the e or r prefix on a general reg is present.  */
9921
0
    else if ((i.types[op].bitfield.dword
9922
0
     || i.types[op].bitfield.qword)
9923
0
       && (i.tm.operand_types[op].bitfield.class == Reg
9924
0
     || i.tm.operand_types[op].bitfield.instance == Accum)
9925
0
       && i.tm.operand_types[op].bitfield.word)
9926
0
      {
9927
0
  as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
9928
0
    register_prefix, i.op[op].regs->reg_name,
9929
0
    i.suffix);
9930
0
  return 0;
9931
0
      }
9932
0
  return 1;
9933
0
}
9934
9935
static int
9936
update_imm (unsigned int j)
9937
34.5k
{
9938
34.5k
  i386_operand_type overlap = i.types[j];
9939
9940
34.5k
  if (i.tm.operand_types[j].bitfield.imm8
9941
34.5k
      && i.tm.operand_types[j].bitfield.imm8s
9942
34.5k
      && overlap.bitfield.imm8 && overlap.bitfield.imm8s)
9943
0
    {
9944
      /* This combination is used on 8-bit immediates where e.g. $~0 is
9945
   desirable to permit.  We're past operand type matching, so simply
9946
   put things back in the shape they were before introducing the
9947
   distinction between Imm8, Imm8S, and Imm8|Imm8S.  */
9948
0
      overlap.bitfield.imm8s = 0;
9949
0
    }
9950
9951
34.5k
  if (overlap.bitfield.imm8
9952
34.5k
      + overlap.bitfield.imm8s
9953
34.5k
      + overlap.bitfield.imm16
9954
34.5k
      + overlap.bitfield.imm32
9955
34.5k
      + overlap.bitfield.imm32s
9956
34.5k
      + overlap.bitfield.imm64 > 1)
9957
1.04k
    {
9958
1.04k
      static const i386_operand_type imm16 = { .bitfield = { .imm16 = 1 } };
9959
1.04k
      static const i386_operand_type imm32 = { .bitfield = { .imm32 = 1 } };
9960
1.04k
      static const i386_operand_type imm32s = { .bitfield = { .imm32s = 1 } };
9961
1.04k
      static const i386_operand_type imm16_32 = { .bitfield =
9962
1.04k
  { .imm16 = 1, .imm32 = 1 }
9963
1.04k
      };
9964
1.04k
      static const i386_operand_type imm16_32s =  { .bitfield =
9965
1.04k
  { .imm16 = 1, .imm32s = 1 }
9966
1.04k
      };
9967
1.04k
      static const i386_operand_type imm16_32_32s = { .bitfield =
9968
1.04k
  { .imm16 = 1, .imm32 = 1, .imm32s = 1 }
9969
1.04k
      };
9970
9971
1.04k
      if (i.suffix)
9972
1.04k
  {
9973
1.04k
    i386_operand_type temp;
9974
9975
1.04k
    operand_type_set (&temp, 0);
9976
1.04k
    if (i.suffix == BYTE_MNEM_SUFFIX)
9977
141
      {
9978
141
        temp.bitfield.imm8 = overlap.bitfield.imm8;
9979
141
        temp.bitfield.imm8s = overlap.bitfield.imm8s;
9980
141
      }
9981
902
    else if (i.suffix == WORD_MNEM_SUFFIX)
9982
108
      temp.bitfield.imm16 = overlap.bitfield.imm16;
9983
794
    else if (i.suffix == QWORD_MNEM_SUFFIX)
9984
0
      {
9985
0
        temp.bitfield.imm64 = overlap.bitfield.imm64;
9986
0
        temp.bitfield.imm32s = overlap.bitfield.imm32s;
9987
0
      }
9988
794
    else
9989
794
      temp.bitfield.imm32 = overlap.bitfield.imm32;
9990
1.04k
    overlap = temp;
9991
1.04k
  }
9992
0
      else if (operand_type_equal (&overlap, &imm16_32_32s)
9993
0
         || operand_type_equal (&overlap, &imm16_32)
9994
0
         || operand_type_equal (&overlap, &imm16_32s))
9995
0
  {
9996
0
    if ((flag_code == CODE_16BIT)
9997
0
        ^ (i.prefix[DATA_PREFIX] != 0 && !(i.prefix[REX_PREFIX] & REX_W)))
9998
0
      overlap = imm16;
9999
0
    else
10000
0
      overlap = imm32s;
10001
0
  }
10002
0
      else if (i.prefix[REX_PREFIX] & REX_W)
10003
0
  overlap = operand_type_and (overlap, imm32s);
10004
0
      else if (i.prefix[DATA_PREFIX])
10005
0
  overlap = operand_type_and (overlap,
10006
0
            flag_code != CODE_16BIT ? imm16 : imm32);
10007
1.04k
      if (overlap.bitfield.imm8
10008
1.04k
    + overlap.bitfield.imm8s
10009
1.04k
    + overlap.bitfield.imm16
10010
1.04k
    + overlap.bitfield.imm32
10011
1.04k
    + overlap.bitfield.imm32s
10012
1.04k
    + overlap.bitfield.imm64 != 1)
10013
0
  {
10014
0
    as_bad (_("no instruction mnemonic suffix given; "
10015
0
        "can't determine immediate size"));
10016
0
    return 0;
10017
0
  }
10018
1.04k
    }
10019
34.5k
  i.types[j] = overlap;
10020
10021
34.5k
  return 1;
10022
34.5k
}
10023
10024
static int
10025
finalize_imm (void)
10026
662k
{
10027
662k
  unsigned int j, n;
10028
10029
  /* Update the first 2 immediate operands.  */
10030
662k
  n = i.operands > 2 ? 2 : i.operands;
10031
662k
  if (n)
10032
19.4k
    {
10033
54.0k
      for (j = 0; j < n; j++)
10034
34.5k
  if (update_imm (j) == 0)
10035
0
    return 0;
10036
10037
      /* The 3rd operand can't be immediate operand.  */
10038
19.4k
      gas_assert (operand_type_check (i.types[2], imm) == 0);
10039
19.4k
    }
10040
10041
662k
  return 1;
10042
662k
}
10043
10044
static INLINE void set_rex_vrex (const reg_entry *r, unsigned int rex_bit,
10045
         bool do_sse2avx)
10046
0
{
10047
0
  if (r->reg_flags & RegRex)
10048
0
    {
10049
0
      if (i.rex & rex_bit)
10050
0
  as_bad (_("same type of prefix used twice"));
10051
0
      i.rex |= rex_bit;
10052
0
    }
10053
0
  else if (do_sse2avx && (i.rex & rex_bit) && i.vex.register_specifier)
10054
0
    {
10055
0
      gas_assert (i.vex.register_specifier == r);
10056
0
      i.vex.register_specifier += 8;
10057
0
    }
10058
10059
0
  if (r->reg_flags & RegVRex)
10060
0
    i.vrex |= rex_bit;
10061
10062
0
  if (r->reg_flags & RegRex2)
10063
0
    i.rex2 |= rex_bit;
10064
0
}
10065
10066
static INLINE void
10067
set_rex_rex2 (const reg_entry *r, unsigned int rex_bit)
10068
0
{
10069
0
  if ((r->reg_flags & RegRex) != 0)
10070
0
    i.rex |= rex_bit;
10071
0
  if ((r->reg_flags & RegRex2) != 0)
10072
0
    i.rex2 |= rex_bit;
10073
0
}
10074
10075
static int
10076
process_operands (void)
10077
19.4k
{
10078
  /* Default segment register this instruction will use for memory
10079
     accesses.  0 means unknown.  This is only for optimizing out
10080
     unnecessary segment overrides.  */
10081
19.4k
  const reg_entry *default_seg = NULL;
10082
10083
54.0k
  for (unsigned int j = 0; j < i.operands; j++)
10084
34.5k
    if (i.types[j].bitfield.instance != InstanceNone)
10085
60
      i.reg_operands--;
10086
10087
19.4k
  if (i.tm.opcode_modifier.sse2avx)
10088
0
    {
10089
      /* Legacy encoded insns allow explicit REX prefixes, so these prefixes
10090
   need converting.  */
10091
0
      i.rex |= i.prefix[REX_PREFIX] & (REX_W | REX_R | REX_X | REX_B);
10092
0
      i.prefix[REX_PREFIX] = 0;
10093
0
      i.rex_encoding = 0;
10094
0
      i.rex2_encoding = 0;
10095
0
    }
10096
  /* ImmExt should be processed after SSE2AVX.  */
10097
19.4k
  else if (i.tm.opcode_modifier.immext)
10098
0
    process_immext ();
10099
10100
  /* TILEZERO is unusual in that it has a single operand encoded in ModR/M.reg,
10101
     not ModR/M.rm.  To avoid special casing this in build_modrm_byte(), fake a
10102
     new destination operand here, while converting the source one to register
10103
     number 0.  */
10104
19.4k
  if (i.tm.mnem_off == MN_tilezero)
10105
0
    {
10106
0
      i.op[1].regs = i.op[0].regs;
10107
0
      i.op[0].regs -= i.op[0].regs->reg_num;
10108
0
      i.types[1] = i.types[0];
10109
0
      i.tm.operand_types[1] = i.tm.operand_types[0];
10110
0
      i.flags[1] = i.flags[0];
10111
0
      i.operands++;
10112
0
      i.reg_operands++;
10113
0
      i.tm.operands++;
10114
0
    }
10115
10116
19.4k
  if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
10117
0
    {
10118
0
      static const i386_operand_type regxmm = {
10119
0
        .bitfield = { .class = RegSIMD, .xmmword = 1 }
10120
0
      };
10121
0
      unsigned int dupl = i.operands;
10122
0
      unsigned int dest = dupl - 1;
10123
0
      unsigned int j;
10124
10125
      /* The destination must be an xmm register.  */
10126
0
      gas_assert (i.reg_operands
10127
0
      && MAX_OPERANDS > dupl
10128
0
      && operand_type_equal (&i.types[dest], &regxmm));
10129
10130
0
      if (i.tm.operand_types[0].bitfield.instance == Accum
10131
0
    && i.tm.operand_types[0].bitfield.xmmword)
10132
0
  {
10133
    /* Keep xmm0 for instructions with VEX prefix and 3
10134
       sources.  */
10135
0
    i.tm.operand_types[0].bitfield.instance = InstanceNone;
10136
0
    i.tm.operand_types[0].bitfield.class = RegSIMD;
10137
0
    i.reg_operands++;
10138
0
    goto duplicate;
10139
0
  }
10140
10141
0
      if (i.tm.opcode_modifier.operandconstraint == IMPLICIT_1ST_XMM0)
10142
0
  {
10143
0
    gas_assert ((MAX_OPERANDS - 1) > dupl);
10144
10145
    /* Add the implicit xmm0 for instructions with VEX prefix
10146
       and 3 sources.  */
10147
0
    for (j = i.operands; j > 0; j--)
10148
0
      {
10149
0
        i.op[j] = i.op[j - 1];
10150
0
        i.types[j] = i.types[j - 1];
10151
0
        i.tm.operand_types[j] = i.tm.operand_types[j - 1];
10152
0
        i.flags[j] = i.flags[j - 1];
10153
0
      }
10154
0
    i.op[0].regs
10155
0
      = (const reg_entry *) str_hash_find (reg_hash, "xmm0");
10156
0
    i.types[0] = regxmm;
10157
0
    i.tm.operand_types[0] = regxmm;
10158
10159
0
    i.operands += 2;
10160
0
    i.reg_operands += 2;
10161
0
    i.tm.operands += 2;
10162
10163
0
    dupl++;
10164
0
    dest++;
10165
0
    i.op[dupl] = i.op[dest];
10166
0
    i.types[dupl] = i.types[dest];
10167
0
    i.tm.operand_types[dupl] = i.tm.operand_types[dest];
10168
0
    i.flags[dupl] = i.flags[dest];
10169
0
  }
10170
0
      else
10171
0
  {
10172
0
  duplicate:
10173
0
    i.operands++;
10174
0
    i.reg_operands++;
10175
0
    i.tm.operands++;
10176
10177
0
    i.op[dupl] = i.op[dest];
10178
0
    i.types[dupl] = i.types[dest];
10179
0
    i.tm.operand_types[dupl] = i.tm.operand_types[dest];
10180
0
    i.flags[dupl] = i.flags[dest];
10181
0
  }
10182
10183
0
       if (i.tm.opcode_modifier.immext)
10184
0
   process_immext ();
10185
0
    }
10186
19.4k
  else if (i.tm.operand_types[0].bitfield.instance == Accum
10187
19.4k
     && i.tm.opcode_modifier.modrm)
10188
0
    {
10189
0
      unsigned int j;
10190
10191
0
      for (j = 1; j < i.operands; j++)
10192
0
  {
10193
0
    i.op[j - 1] = i.op[j];
10194
0
    i.types[j - 1] = i.types[j];
10195
10196
    /* We need to adjust fields in i.tm since they are used by
10197
       build_modrm_byte.  */
10198
0
    i.tm.operand_types [j - 1] = i.tm.operand_types [j];
10199
10200
0
    i.flags[j - 1] = i.flags[j];
10201
0
  }
10202
10203
      /* No adjustment to i.reg_operands: This was already done at the top
10204
   of the function.  */
10205
0
      i.operands--;
10206
0
      i.tm.operands--;
10207
0
    }
10208
19.4k
  else if (i.tm.opcode_modifier.operandconstraint == IMPLICIT_QUAD_GROUP)
10209
0
    {
10210
0
      unsigned int regnum, first_reg_in_group, last_reg_in_group;
10211
10212
      /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
10213
0
      gas_assert (i.operands >= 2 && i.types[1].bitfield.class == RegSIMD);
10214
0
      regnum = register_number (i.op[1].regs);
10215
0
      first_reg_in_group = regnum & ~3;
10216
0
      last_reg_in_group = first_reg_in_group + 3;
10217
0
      if (regnum != first_reg_in_group)
10218
0
  as_warn (_("source register `%s%s' implicitly denotes"
10219
0
       " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
10220
0
     register_prefix, i.op[1].regs->reg_name,
10221
0
     register_prefix, i.op[1].regs->reg_name, first_reg_in_group,
10222
0
     register_prefix, i.op[1].regs->reg_name, last_reg_in_group,
10223
0
     insn_name (&i.tm));
10224
0
    }
10225
19.4k
  else if (i.tm.opcode_modifier.operandconstraint == REG_KLUDGE)
10226
0
    {
10227
      /* The imul $imm, %reg instruction is converted into
10228
   imul $imm, %reg, %reg, and the clr %reg instruction
10229
   is converted into xor %reg, %reg.  */
10230
10231
0
      unsigned int first_reg_op;
10232
10233
0
      if (operand_type_check (i.types[0], reg))
10234
0
  first_reg_op = 0;
10235
0
      else
10236
0
  first_reg_op = 1;
10237
      /* Pretend we saw the extra register operand.  */
10238
0
      gas_assert (i.reg_operands == 1
10239
0
      && i.op[first_reg_op + 1].regs == 0);
10240
0
      i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
10241
0
      i.types[first_reg_op + 1] = i.types[first_reg_op];
10242
0
      i.operands++;
10243
0
      i.reg_operands++;
10244
0
    }
10245
10246
19.4k
  if (i.tm.opcode_modifier.modrm)
10247
18.2k
    {
10248
      /* The opcode is completed (modulo i.tm.extension_opcode which
10249
   must be put into the modrm byte).  Now, we make the modrm and
10250
   index base bytes based on all the info we've collected.  */
10251
10252
18.2k
      default_seg = build_modrm_byte ();
10253
10254
18.2k
      if (!quiet_warnings && i.tm.opcode_modifier.operandconstraint == UGH)
10255
0
  {
10256
    /* Warn about some common errors, but press on regardless.  */
10257
0
    if (i.operands == 2)
10258
0
      {
10259
        /* Reversed arguments on faddp or fmulp.  */
10260
0
        as_warn (_("translating to `%s %s%s,%s%s'"), insn_name (&i.tm),
10261
0
           register_prefix, i.op[!intel_syntax].regs->reg_name,
10262
0
           register_prefix, i.op[intel_syntax].regs->reg_name);
10263
0
      }
10264
0
    else if (i.tm.opcode_modifier.mnemonicsize == IGNORESIZE)
10265
0
      {
10266
        /* Extraneous `l' suffix on fp insn.  */
10267
0
        as_warn (_("translating to `%s %s%s'"), insn_name (&i.tm),
10268
0
           register_prefix, i.op[0].regs->reg_name);
10269
0
      }
10270
0
  }
10271
18.2k
    }
10272
1.25k
  else if (i.types[0].bitfield.class == SReg && !dot_insn ())
10273
0
    {
10274
0
      if (flag_code != CODE_64BIT
10275
0
    ? i.tm.base_opcode == POP_SEG_SHORT
10276
0
      && i.op[0].regs->reg_num == 1
10277
0
    : (i.tm.base_opcode | 1) == (POP_SEG386_SHORT & 0xff)
10278
0
      && i.op[0].regs->reg_num < 4)
10279
0
  {
10280
0
    as_bad (_("you can't `%s %s%s'"),
10281
0
      insn_name (&i.tm), register_prefix, i.op[0].regs->reg_name);
10282
0
    return 0;
10283
0
  }
10284
0
      if (i.op[0].regs->reg_num > 3
10285
0
    && i.tm.opcode_space == SPACE_BASE )
10286
0
  {
10287
0
    i.tm.base_opcode ^= (POP_SEG_SHORT ^ POP_SEG386_SHORT) & 0xff;
10288
0
    i.tm.opcode_space = SPACE_0F;
10289
0
  }
10290
0
      i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
10291
0
    }
10292
1.25k
  else if (i.tm.opcode_space == SPACE_BASE
10293
1.25k
     && (i.tm.base_opcode & ~3) == MOV_AX_DISP32)
10294
0
    {
10295
0
      default_seg = reg_ds;
10296
0
    }
10297
1.25k
  else if (i.tm.opcode_modifier.isstring)
10298
0
    {
10299
      /* For the string instructions that allow a segment override
10300
   on one of their operands, the default segment is ds.  */
10301
0
      default_seg = reg_ds;
10302
0
    }
10303
1.25k
  else if (i.short_form)
10304
0
    {
10305
      /* The register operand is in the 1st or 2nd non-immediate operand.  */
10306
0
      const reg_entry *r = i.op[i.imm_operands].regs;
10307
10308
0
      if (!dot_insn ()
10309
0
    && r->reg_type.bitfield.instance == Accum
10310
0
    && i.op[i.imm_operands + 1].regs)
10311
0
  r = i.op[i.imm_operands + 1].regs;
10312
      /* Register goes in low 3 bits of opcode.  */
10313
0
      i.tm.base_opcode |= r->reg_num;
10314
0
      set_rex_vrex (r, REX_B, false);
10315
10316
0
      if (dot_insn () && i.reg_operands == 2)
10317
0
  {
10318
0
    gas_assert (is_any_vex_encoding (&i.tm)
10319
0
          || i.encoding != encoding_default);
10320
0
    i.vex.register_specifier = i.op[i.operands - 1].regs;
10321
0
  }
10322
0
    }
10323
1.25k
  else if (i.reg_operands == 1
10324
1.25k
     && !i.flags[i.operands - 1]
10325
1.25k
     && i.tm.operand_types[i.operands - 1].bitfield.instance
10326
0
        == InstanceNone)
10327
0
    {
10328
0
      gas_assert (is_any_vex_encoding (&i.tm)
10329
0
      || i.encoding != encoding_default);
10330
0
      i.vex.register_specifier = i.op[i.operands - 1].regs;
10331
0
    }
10332
10333
19.4k
  if ((i.seg[0] || i.prefix[SEG_PREFIX])
10334
19.4k
      && i.tm.mnem_off == MN_lea)
10335
0
    {
10336
0
      if (!quiet_warnings)
10337
0
  as_warn (_("segment override on `%s' is ineffectual"), insn_name (&i.tm));
10338
0
      if (optimize && !i.no_optimize)
10339
0
  {
10340
0
    i.seg[0] = NULL;
10341
0
    i.prefix[SEG_PREFIX] = 0;
10342
0
  }
10343
0
    }
10344
10345
  /* If a segment was explicitly specified, and the specified segment
10346
     is neither the default nor the one already recorded from a prefix,
10347
     use an opcode prefix to select it.  If we never figured out what
10348
     the default segment is, then default_seg will be zero at this
10349
     point, and the specified segment prefix will always be used.  */
10350
19.4k
  if (i.seg[0]
10351
19.4k
      && i.seg[0] != default_seg
10352
19.4k
      && i386_seg_prefixes[i.seg[0]->reg_num] != i.prefix[SEG_PREFIX])
10353
0
    {
10354
0
      if (!add_prefix (i386_seg_prefixes[i.seg[0]->reg_num]))
10355
0
  return 0;
10356
0
    }
10357
19.4k
  return 1;
10358
19.4k
}
10359
10360
static const reg_entry *
10361
build_modrm_byte (void)
10362
18.2k
{
10363
18.2k
  const reg_entry *default_seg = NULL;
10364
18.2k
  unsigned int source = i.imm_operands - i.tm.opcode_modifier.immext
10365
      /* Compensate for kludge in md_assemble().  */
10366
18.2k
      + i.tm.operand_types[0].bitfield.imm1;
10367
18.2k
  unsigned int dest = i.operands - 1 - i.tm.opcode_modifier.immext;
10368
18.2k
  unsigned int v, op, reg_slot;
10369
10370
  /* Accumulator (in particular %st), shift count (%cl), and alike need
10371
     to be skipped just like immediate operands do.  */
10372
18.2k
  if (i.tm.operand_types[source].bitfield.instance)
10373
0
    ++source;
10374
18.2k
  while (i.tm.operand_types[dest].bitfield.instance)
10375
0
    --dest;
10376
10377
18.2k
  for (op = source; op < i.operands; ++op)
10378
18.2k
    if (i.tm.operand_types[op].bitfield.baseindex)
10379
18.2k
      break;
10380
10381
18.2k
  if (i.reg_operands + i.mem_operands + (i.tm.extension_opcode != None) == 4)
10382
0
    {
10383
0
      expressionS *exp;
10384
10385
      /* There are 2 kinds of instructions:
10386
   1. 5 operands: 4 register operands or 3 register operands
10387
   plus 1 memory operand plus one Imm4 operand, VexXDS, and
10388
   VexW0 or VexW1.  The destination must be either XMM, YMM or
10389
   ZMM register.
10390
   2. 4 operands: 4 register operands or 3 register operands
10391
   plus 1 memory operand, with VexXDS.
10392
   3. Other equivalent combinations when coming from s_insn().  */
10393
0
      gas_assert (i.tm.opcode_modifier.vexvvvv
10394
0
      && i.tm.opcode_modifier.vexw);
10395
0
      gas_assert (dot_insn ()
10396
0
      || i.tm.operand_types[dest].bitfield.class == RegSIMD);
10397
10398
      /* Of the first two non-immediate operands the one with the template
10399
   not allowing for a memory one is encoded in the immediate operand.  */
10400
0
      if (source == op)
10401
0
  reg_slot = source + 1;
10402
0
      else
10403
0
  reg_slot = source++;
10404
10405
0
      if (!dot_insn ())
10406
0
  {
10407
0
    gas_assert (i.tm.operand_types[reg_slot].bitfield.class == RegSIMD);
10408
0
    gas_assert (!(i.op[reg_slot].regs->reg_flags & RegVRex));
10409
0
  }
10410
0
      else
10411
0
  gas_assert (i.tm.operand_types[reg_slot].bitfield.class != ClassNone);
10412
10413
0
      if (i.imm_operands == 0)
10414
0
  {
10415
    /* When there is no immediate operand, generate an 8bit
10416
       immediate operand to encode the first operand.  */
10417
0
    exp = &im_expressions[i.imm_operands++];
10418
0
    i.op[i.operands].imms = exp;
10419
0
    i.types[i.operands].bitfield.imm8 = 1;
10420
0
    i.operands++;
10421
10422
0
    exp->X_op = O_constant;
10423
0
  }
10424
0
      else
10425
0
  {
10426
0
    gas_assert (i.imm_operands == 1);
10427
0
    gas_assert (fits_in_imm4 (i.op[0].imms->X_add_number));
10428
0
    gas_assert (!i.tm.opcode_modifier.immext);
10429
10430
    /* Turn on Imm8 again so that output_imm will generate it.  */
10431
0
    i.types[0].bitfield.imm8 = 1;
10432
10433
0
    exp = i.op[0].imms;
10434
0
  }
10435
0
      exp->X_add_number |= register_number (i.op[reg_slot].regs)
10436
0
         << (3 + !(i.tm.opcode_modifier.evex
10437
0
             || i.encoding == encoding_evex));
10438
0
    }
10439
10440
18.2k
  switch (i.tm.opcode_modifier.vexvvvv)
10441
18.2k
    {
10442
    /* VEX.vvvv encodes the last source register operand.  */
10443
0
    case VexVVVV_SRC2:
10444
0
      if (source != op)
10445
0
  {
10446
0
    v = source++;
10447
0
    break;
10448
0
  }
10449
      /* For vprot*, vpshl*, and vpsha*, XOP.W controls the swapping of src1
10450
   and src2, and it requires fall through when the operands are swapped.
10451
       */
10452
      /* Fall through.  */
10453
    /* VEX.vvvv encodes the first source register operand.  */
10454
0
    case VexVVVV_SRC1:
10455
0
      v =  dest - 1;
10456
0
      break;
10457
    /* VEX.vvvv encodes the destination register operand.  */
10458
0
    case VexVVVV_DST:
10459
0
      v = dest--;
10460
0
      break;
10461
18.2k
    default:
10462
18.2k
      v = ~0;
10463
18.2k
      break;
10464
18.2k
     }
10465
10466
18.2k
  if (dest == source)
10467
18.2k
    dest = ~0;
10468
10469
18.2k
  gas_assert (source < dest);
10470
10471
18.2k
  if (v < MAX_OPERANDS)
10472
0
    {
10473
0
      gas_assert (i.tm.opcode_modifier.vexvvvv);
10474
0
      i.vex.register_specifier = i.op[v].regs;
10475
0
    }
10476
10477
18.2k
  if (op < i.operands)
10478
18.2k
    {
10479
18.2k
      if (i.mem_operands)
10480
18.2k
  {
10481
18.2k
    unsigned int fake_zero_displacement = 0;
10482
10483
18.2k
    gas_assert (i.flags[op] & Operand_Mem);
10484
10485
18.2k
    if (i.tm.opcode_modifier.sib)
10486
0
      {
10487
        /* The index register of VSIB shouldn't be RegIZ.  */
10488
0
        if (i.tm.opcode_modifier.sib != SIBMEM
10489
0
      && i.index_reg->reg_num == RegIZ)
10490
0
    abort ();
10491
10492
0
        i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
10493
0
        if (!i.base_reg)
10494
0
    {
10495
0
      i.sib.base = NO_BASE_REGISTER;
10496
0
      i.sib.scale = i.log2_scale_factor;
10497
0
      i.types[op] = operand_type_and_not (i.types[op], anydisp);
10498
0
      i.types[op].bitfield.disp32 = 1;
10499
0
    }
10500
10501
        /* Since the mandatory SIB always has index register, so
10502
     the code logic remains unchanged. The non-mandatory SIB
10503
     without index register is allowed and will be handled
10504
     later.  */
10505
0
        if (i.index_reg)
10506
0
    {
10507
0
      if (i.index_reg->reg_num == RegIZ)
10508
0
        i.sib.index = NO_INDEX_REGISTER;
10509
0
      else
10510
0
        i.sib.index = i.index_reg->reg_num;
10511
0
      set_rex_vrex (i.index_reg, REX_X, false);
10512
0
    }
10513
0
      }
10514
10515
18.2k
    default_seg = reg_ds;
10516
10517
18.2k
    if (i.base_reg == 0)
10518
18.2k
      {
10519
18.2k
        i.rm.mode = 0;
10520
18.2k
        if (!i.disp_operands)
10521
0
    fake_zero_displacement = 1;
10522
18.2k
        if (i.index_reg == 0)
10523
18.2k
    {
10524
      /* Both check for VSIB and mandatory non-vector SIB. */
10525
18.2k
      gas_assert (!i.tm.opcode_modifier.sib
10526
18.2k
            || i.tm.opcode_modifier.sib == SIBMEM);
10527
      /* Operand is just <disp>  */
10528
18.2k
      i.types[op] = operand_type_and_not (i.types[op], anydisp);
10529
18.2k
      if (flag_code == CODE_64BIT)
10530
6.32k
        {
10531
          /* 64bit mode overwrites the 32bit absolute
10532
       addressing by RIP relative addressing and
10533
       absolute addressing is encoded by one of the
10534
       redundant SIB forms.  */
10535
6.32k
          i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
10536
6.32k
          i.sib.base = NO_BASE_REGISTER;
10537
6.32k
          i.sib.index = NO_INDEX_REGISTER;
10538
6.32k
          i.types[op].bitfield.disp32 = 1;
10539
6.32k
        }
10540
11.8k
      else if ((flag_code == CODE_16BIT)
10541
11.8k
         ^ (i.prefix[ADDR_PREFIX] != 0))
10542
7.30k
        {
10543
7.30k
          i.rm.regmem = NO_BASE_REGISTER_16;
10544
7.30k
          i.types[op].bitfield.disp16 = 1;
10545
7.30k
        }
10546
4.59k
      else
10547
4.59k
        {
10548
4.59k
          i.rm.regmem = NO_BASE_REGISTER;
10549
4.59k
          i.types[op].bitfield.disp32 = 1;
10550
4.59k
        }
10551
18.2k
    }
10552
0
        else if (!i.tm.opcode_modifier.sib)
10553
0
    {
10554
      /* !i.base_reg && i.index_reg  */
10555
0
      if (i.index_reg->reg_num == RegIZ)
10556
0
        i.sib.index = NO_INDEX_REGISTER;
10557
0
      else
10558
0
        i.sib.index = i.index_reg->reg_num;
10559
0
      i.sib.base = NO_BASE_REGISTER;
10560
0
      i.sib.scale = i.log2_scale_factor;
10561
0
      i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
10562
0
      i.types[op] = operand_type_and_not (i.types[op], anydisp);
10563
0
      i.types[op].bitfield.disp32 = 1;
10564
0
      set_rex_rex2 (i.index_reg, REX_X);
10565
0
    }
10566
18.2k
      }
10567
    /* RIP addressing for 64bit mode.  */
10568
0
    else if (i.base_reg->reg_num == RegIP)
10569
0
      {
10570
0
        gas_assert (!i.tm.opcode_modifier.sib);
10571
0
        i.rm.regmem = NO_BASE_REGISTER;
10572
0
        i.types[op].bitfield.disp8 = 0;
10573
0
        i.types[op].bitfield.disp16 = 0;
10574
0
        i.types[op].bitfield.disp32 = 1;
10575
0
        i.types[op].bitfield.disp64 = 0;
10576
0
        i.flags[op] |= Operand_PCrel;
10577
0
        if (! i.disp_operands)
10578
0
    fake_zero_displacement = 1;
10579
0
      }
10580
0
    else if (i.base_reg->reg_type.bitfield.word)
10581
0
      {
10582
0
        gas_assert (!i.tm.opcode_modifier.sib);
10583
0
        switch (i.base_reg->reg_num)
10584
0
    {
10585
0
    case 3: /* (%bx)  */
10586
0
      if (i.index_reg == 0)
10587
0
        i.rm.regmem = 7;
10588
0
      else /* (%bx,%si) -> 0, or (%bx,%di) -> 1  */
10589
0
        i.rm.regmem = i.index_reg->reg_num - 6;
10590
0
      break;
10591
0
    case 5: /* (%bp)  */
10592
0
      default_seg = reg_ss;
10593
0
      if (i.index_reg == 0)
10594
0
        {
10595
0
          i.rm.regmem = 6;
10596
0
          if (operand_type_check (i.types[op], disp) == 0)
10597
0
      {
10598
        /* fake (%bp) into 0(%bp)  */
10599
0
        if (i.disp_encoding == disp_encoding_16bit)
10600
0
          i.types[op].bitfield.disp16 = 1;
10601
0
        else
10602
0
          i.types[op].bitfield.disp8 = 1;
10603
0
        fake_zero_displacement = 1;
10604
0
      }
10605
0
        }
10606
0
      else /* (%bp,%si) -> 2, or (%bp,%di) -> 3  */
10607
0
        i.rm.regmem = i.index_reg->reg_num - 6 + 2;
10608
0
      break;
10609
0
    default: /* (%si) -> 4 or (%di) -> 5  */
10610
0
      i.rm.regmem = i.base_reg->reg_num - 6 + 4;
10611
0
    }
10612
0
        if (!fake_zero_displacement
10613
0
      && !i.disp_operands
10614
0
      && i.disp_encoding)
10615
0
    {
10616
0
      fake_zero_displacement = 1;
10617
0
      if (i.disp_encoding == disp_encoding_8bit)
10618
0
        i.types[op].bitfield.disp8 = 1;
10619
0
      else
10620
0
        i.types[op].bitfield.disp16 = 1;
10621
0
    }
10622
0
        i.rm.mode = mode_from_disp_size (i.types[op]);
10623
0
      }
10624
0
    else /* i.base_reg and 32/64 bit mode  */
10625
0
      {
10626
0
        if (operand_type_check (i.types[op], disp))
10627
0
    {
10628
0
      i.types[op].bitfield.disp16 = 0;
10629
0
      i.types[op].bitfield.disp64 = 0;
10630
0
      i.types[op].bitfield.disp32 = 1;
10631
0
    }
10632
10633
0
        if (!i.tm.opcode_modifier.sib)
10634
0
    i.rm.regmem = i.base_reg->reg_num;
10635
0
        set_rex_rex2 (i.base_reg, REX_B);
10636
0
        i.sib.base = i.base_reg->reg_num;
10637
        /* x86-64 ignores REX prefix bit here to avoid decoder
10638
     complications.  */
10639
0
        if (!(i.base_reg->reg_flags & RegRex)
10640
0
      && (i.base_reg->reg_num == EBP_REG_NUM
10641
0
       || i.base_reg->reg_num == ESP_REG_NUM))
10642
0
      default_seg = reg_ss;
10643
0
        if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
10644
0
    {
10645
0
      fake_zero_displacement = 1;
10646
0
      if (i.disp_encoding == disp_encoding_32bit)
10647
0
        i.types[op].bitfield.disp32 = 1;
10648
0
      else
10649
0
        i.types[op].bitfield.disp8 = 1;
10650
0
    }
10651
0
        i.sib.scale = i.log2_scale_factor;
10652
0
        if (i.index_reg == 0)
10653
0
    {
10654
      /* Only check for VSIB. */
10655
0
      gas_assert (i.tm.opcode_modifier.sib != VECSIB128
10656
0
            && i.tm.opcode_modifier.sib != VECSIB256
10657
0
            && i.tm.opcode_modifier.sib != VECSIB512);
10658
10659
      /* <disp>(%esp) becomes two byte modrm with no index
10660
         register.  We've already stored the code for esp
10661
         in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
10662
         Any base register besides %esp will not use the
10663
         extra modrm byte.  */
10664
0
      i.sib.index = NO_INDEX_REGISTER;
10665
0
    }
10666
0
        else if (!i.tm.opcode_modifier.sib)
10667
0
    {
10668
0
      if (i.index_reg->reg_num == RegIZ)
10669
0
        i.sib.index = NO_INDEX_REGISTER;
10670
0
      else
10671
0
        i.sib.index = i.index_reg->reg_num;
10672
0
      i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
10673
0
      set_rex_rex2 (i.index_reg, REX_X);
10674
0
    }
10675
10676
0
        if (i.disp_operands
10677
0
      && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
10678
0
          || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
10679
0
    i.rm.mode = 0;
10680
0
        else
10681
0
    {
10682
0
      if (!fake_zero_displacement
10683
0
          && !i.disp_operands
10684
0
          && i.disp_encoding)
10685
0
        {
10686
0
          fake_zero_displacement = 1;
10687
0
          if (i.disp_encoding == disp_encoding_8bit)
10688
0
      i.types[op].bitfield.disp8 = 1;
10689
0
          else
10690
0
      i.types[op].bitfield.disp32 = 1;
10691
0
        }
10692
0
      i.rm.mode = mode_from_disp_size (i.types[op]);
10693
0
    }
10694
0
      }
10695
10696
18.2k
    if (fake_zero_displacement)
10697
0
      {
10698
        /* Fakes a zero displacement assuming that i.types[op]
10699
     holds the correct displacement size.  */
10700
0
        expressionS *exp;
10701
10702
0
        gas_assert (i.op[op].disps == 0);
10703
0
        exp = &disp_expressions[i.disp_operands++];
10704
0
        i.op[op].disps = exp;
10705
0
        exp->X_op = O_constant;
10706
0
        exp->X_add_number = 0;
10707
0
        exp->X_add_symbol = (symbolS *) 0;
10708
0
        exp->X_op_symbol = (symbolS *) 0;
10709
0
      }
10710
18.2k
  }
10711
0
    else
10712
0
  {
10713
0
      i.rm.mode = 3;
10714
0
      i.rm.regmem = i.op[op].regs->reg_num;
10715
0
      set_rex_vrex (i.op[op].regs, REX_B, false);
10716
0
  }
10717
10718
18.2k
      if (op == dest)
10719
0
  dest = ~0;
10720
18.2k
      if (op == source)
10721
18.2k
  source = ~0;
10722
18.2k
    }
10723
0
  else
10724
0
    {
10725
0
      i.rm.mode = 3;
10726
0
      if (!i.tm.opcode_modifier.regmem)
10727
0
  {
10728
0
    gas_assert (source < MAX_OPERANDS);
10729
0
    i.rm.regmem = i.op[source].regs->reg_num;
10730
0
    set_rex_vrex (i.op[source].regs, REX_B,
10731
0
      dest >= MAX_OPERANDS && i.tm.opcode_modifier.sse2avx);
10732
0
    source = ~0;
10733
0
  }
10734
0
      else
10735
0
  {
10736
0
    gas_assert (dest < MAX_OPERANDS);
10737
0
    i.rm.regmem = i.op[dest].regs->reg_num;
10738
0
    set_rex_vrex (i.op[dest].regs, REX_B, i.tm.opcode_modifier.sse2avx);
10739
0
    dest = ~0;
10740
0
  }
10741
0
    }
10742
10743
  /* Fill in i.rm.reg field with extension opcode (if any) or the
10744
     appropriate register.  */
10745
18.2k
  if (i.tm.extension_opcode != None)
10746
18.2k
    i.rm.reg = i.tm.extension_opcode;
10747
0
  else if (!i.tm.opcode_modifier.regmem && dest < MAX_OPERANDS)
10748
0
    {
10749
0
      i.rm.reg = i.op[dest].regs->reg_num;
10750
0
      set_rex_vrex (i.op[dest].regs, REX_R, i.tm.opcode_modifier.sse2avx);
10751
0
    }
10752
0
  else
10753
0
    {
10754
0
      gas_assert (source < MAX_OPERANDS);
10755
0
      i.rm.reg = i.op[source].regs->reg_num;
10756
0
      set_rex_vrex (i.op[source].regs, REX_R, false);
10757
0
    }
10758
10759
18.2k
  if (flag_code != CODE_64BIT && (i.rex & REX_R))
10760
0
    {
10761
0
      gas_assert (i.types[!i.tm.opcode_modifier.regmem].bitfield.class == RegCR);
10762
0
      i.rex &= ~REX_R;
10763
0
      add_prefix (LOCK_PREFIX_OPCODE);
10764
0
    }
10765
10766
18.2k
  return default_seg;
10767
18.2k
}
10768
10769
static INLINE void
10770
frag_opcode_byte (unsigned char byte)
10771
28.0k
{
10772
28.0k
  if (now_seg != absolute_section)
10773
23.7k
    FRAG_APPEND_1_CHAR (byte);
10774
4.26k
  else
10775
4.26k
    ++abs_section_offset;
10776
28.0k
}
10777
10778
static unsigned int
10779
flip_code16 (unsigned int code16)
10780
0
{
10781
0
  gas_assert (i.tm.operands == 1);
10782
10783
0
  return !(i.prefix[REX_PREFIX] & REX_W)
10784
0
   && (code16 ? i.tm.operand_types[0].bitfield.disp32
10785
0
        : i.tm.operand_types[0].bitfield.disp16)
10786
0
   ? CODE16 : 0;
10787
0
}
10788
10789
static void
10790
output_branch (void)
10791
881
{
10792
881
  char *p;
10793
881
  int size;
10794
881
  int code16;
10795
881
  int prefix;
10796
881
  relax_substateT subtype;
10797
881
  symbolS *sym;
10798
881
  offsetT off;
10799
10800
881
  if (now_seg == absolute_section)
10801
250
    {
10802
250
      as_bad (_("relaxable branches not supported in absolute section"));
10803
250
      return;
10804
250
    }
10805
10806
631
  code16 = flag_code == CODE_16BIT ? CODE16 : 0;
10807
631
  size = i.disp_encoding > disp_encoding_8bit ? BIG : SMALL;
10808
10809
631
  prefix = 0;
10810
631
  if (i.prefix[DATA_PREFIX] != 0)
10811
0
    {
10812
0
      prefix = 1;
10813
0
      i.prefixes -= 1;
10814
0
      code16 ^= flip_code16(code16);
10815
0
    }
10816
  /* Pentium4 branch hints.  */
10817
  if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
10818
631
      || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
10819
108
    {
10820
108
      prefix++;
10821
108
      i.prefixes--;
10822
108
    }
10823
631
  if (i.prefix[REX_PREFIX] != 0)
10824
0
    {
10825
0
      prefix++;
10826
0
      i.prefixes--;
10827
0
    }
10828
10829
  /* BND prefixed jump.  */
10830
631
  if (i.prefix[BND_PREFIX] != 0)
10831
0
    {
10832
0
      prefix++;
10833
0
      i.prefixes--;
10834
0
    }
10835
10836
631
  if (i.prefixes != 0)
10837
0
    as_warn (_("skipping prefixes on `%s'"), insn_name (&i.tm));
10838
10839
  /* It's always a symbol;  End frag & setup for relax.
10840
     Make sure there is enough room in this frag for the largest
10841
     instruction we may generate in md_convert_frag.  This is 2
10842
     bytes for the opcode and room for the prefix and largest
10843
     displacement.  */
10844
631
  frag_grow (prefix + 2 + 4);
10845
  /* Prefix and 1 opcode byte go in fr_fix.  */
10846
631
  p = frag_more (prefix + 1);
10847
631
  if (i.prefix[DATA_PREFIX] != 0)
10848
0
    *p++ = DATA_PREFIX_OPCODE;
10849
631
  if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
10850
631
      || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
10851
108
    *p++ = i.prefix[SEG_PREFIX];
10852
631
  if (i.prefix[BND_PREFIX] != 0)
10853
0
    *p++ = BND_PREFIX_OPCODE;
10854
631
  if (i.prefix[REX_PREFIX] != 0)
10855
0
    *p++ = i.prefix[REX_PREFIX];
10856
631
  *p = i.tm.base_opcode;
10857
10858
631
  if ((unsigned char) *p == JUMP_PC_RELATIVE)
10859
0
    subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
10860
631
  else if (cpu_arch_flags.bitfield.cpui386)
10861
631
    subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
10862
0
  else
10863
0
    subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
10864
631
  subtype |= code16;
10865
10866
631
  sym = i.op[0].disps->X_add_symbol;
10867
631
  off = i.op[0].disps->X_add_number;
10868
10869
631
  if (i.op[0].disps->X_op != O_constant
10870
631
      && i.op[0].disps->X_op != O_symbol)
10871
66
    {
10872
      /* Handle complex expressions.  */
10873
66
      sym = make_expr_symbol (i.op[0].disps);
10874
66
      off = 0;
10875
66
    }
10876
10877
  /* 1 possible extra opcode + 4 byte displacement go in var part.
10878
     Pass reloc in fr_var.  */
10879
631
  frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
10880
631
}
10881
10882
#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10883
/* Return TRUE iff PLT32 relocation should be used for branching to
10884
   symbol S.  */
10885
10886
static bool
10887
need_plt32_p (symbolS *s)
10888
6
{
10889
  /* PLT32 relocation is ELF only.  */
10890
6
  if (!IS_ELF)
10891
0
    return false;
10892
10893
#ifdef TE_SOLARIS
10894
  /* Don't emit PLT32 relocation on Solaris: neither native linker nor
10895
     krtld support it.  */
10896
  return false;
10897
#endif
10898
10899
  /* Since there is no need to prepare for PLT branch on x86-64, we
10900
     can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
10901
     be used as a marker for 32-bit PC-relative branches.  */
10902
6
  if (!object_64bit)
10903
0
    return false;
10904
10905
6
  if (s == NULL)
10906
0
    return false;
10907
10908
  /* Weak or undefined symbol need PLT32 relocation.  */
10909
6
  if (S_IS_WEAK (s) || !S_IS_DEFINED (s))
10910
1
    return true;
10911
10912
  /* Non-global symbol doesn't need PLT32 relocation.  */
10913
5
  if (! S_IS_EXTERNAL (s))
10914
5
    return false;
10915
10916
  /* Other global symbols need PLT32 relocation.  NB: Symbol with
10917
     non-default visibilities are treated as normal global symbol
10918
     so that PLT32 relocation can be used as a marker for 32-bit
10919
     PC-relative branches.  It is useful for linker relaxation.  */
10920
0
  return true;
10921
5
}
10922
#endif
10923
10924
static void
10925
output_jump (void)
10926
20
{
10927
20
  char *p;
10928
20
  int size;
10929
20
  fixS *fixP;
10930
20
  bfd_reloc_code_real_type jump_reloc = i.reloc[0];
10931
10932
20
  if (i.tm.opcode_modifier.jump == JUMP_BYTE)
10933
0
    {
10934
      /* This is a loop or jecxz type instruction.  */
10935
0
      size = 1;
10936
0
      if (i.prefix[ADDR_PREFIX] != 0)
10937
0
  {
10938
0
    frag_opcode_byte (ADDR_PREFIX_OPCODE);
10939
0
    i.prefixes -= 1;
10940
0
  }
10941
      /* Pentium4 branch hints.  */
10942
      if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
10943
0
    || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
10944
0
  {
10945
0
    frag_opcode_byte (i.prefix[SEG_PREFIX]);
10946
0
    i.prefixes--;
10947
0
  }
10948
0
    }
10949
20
  else
10950
20
    {
10951
20
      int code16;
10952
10953
20
      code16 = 0;
10954
20
      if (flag_code == CODE_16BIT)
10955
0
  code16 = CODE16;
10956
10957
20
      if (i.prefix[DATA_PREFIX] != 0)
10958
0
  {
10959
0
    frag_opcode_byte (DATA_PREFIX_OPCODE);
10960
0
    i.prefixes -= 1;
10961
0
    code16 ^= flip_code16(code16);
10962
0
  }
10963
10964
20
      size = 4;
10965
20
      if (code16)
10966
0
  size = 2;
10967
20
    }
10968
10969
  /* BND prefixed jump.  */
10970
20
  if (i.prefix[BND_PREFIX] != 0)
10971
0
    {
10972
0
      frag_opcode_byte (i.prefix[BND_PREFIX]);
10973
0
      i.prefixes -= 1;
10974
0
    }
10975
10976
20
  if (i.prefix[REX_PREFIX] != 0)
10977
0
    {
10978
0
      frag_opcode_byte (i.prefix[REX_PREFIX]);
10979
0
      i.prefixes -= 1;
10980
0
    }
10981
10982
20
  if (i.prefixes != 0)
10983
0
    as_warn (_("skipping prefixes on `%s'"), insn_name (&i.tm));
10984
10985
20
  if (now_seg == absolute_section)
10986
0
    {
10987
0
      abs_section_offset += i.opcode_length + size;
10988
0
      return;
10989
0
    }
10990
10991
20
  p = frag_more (i.opcode_length + size);
10992
20
  switch (i.opcode_length)
10993
20
    {
10994
0
    case 2:
10995
0
      *p++ = i.tm.base_opcode >> 8;
10996
      /* Fall through.  */
10997
20
    case 1:
10998
20
      *p++ = i.tm.base_opcode;
10999
20
      break;
11000
0
    default:
11001
0
      abort ();
11002
20
    }
11003
11004
20
#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11005
20
  if (flag_code == CODE_64BIT && size == 4
11006
20
      && jump_reloc == NO_RELOC && i.op[0].disps->X_add_number == 0
11007
20
      && need_plt32_p (i.op[0].disps->X_add_symbol))
11008
1
    jump_reloc = BFD_RELOC_X86_64_PLT32;
11009
20
#endif
11010
11011
20
  jump_reloc = reloc (size, 1, 1, jump_reloc);
11012
11013
20
  fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
11014
20
          i.op[0].disps, 1, jump_reloc);
11015
11016
  /* All jumps handled here are signed, but don't unconditionally use a
11017
     signed limit check for 32 and 16 bit jumps as we want to allow wrap
11018
     around at 4G (outside of 64-bit mode) and 64k (except for XBEGIN)
11019
     respectively.  */
11020
20
  switch (size)
11021
20
    {
11022
0
    case 1:
11023
0
      fixP->fx_signed = 1;
11024
0
      break;
11025
11026
0
    case 2:
11027
0
      if (i.tm.mnem_off == MN_xbegin)
11028
0
  fixP->fx_signed = 1;
11029
0
      break;
11030
11031
20
    case 4:
11032
20
      if (flag_code == CODE_64BIT)
11033
20
  fixP->fx_signed = 1;
11034
20
      break;
11035
20
    }
11036
20
}
11037
11038
static void
11039
output_interseg_jump (void)
11040
0
{
11041
0
  char *p;
11042
0
  int size;
11043
0
  int prefix;
11044
0
  int code16;
11045
11046
0
  code16 = 0;
11047
0
  if (flag_code == CODE_16BIT)
11048
0
    code16 = CODE16;
11049
11050
0
  prefix = 0;
11051
0
  if (i.prefix[DATA_PREFIX] != 0)
11052
0
    {
11053
0
      prefix = 1;
11054
0
      i.prefixes -= 1;
11055
0
      code16 ^= CODE16;
11056
0
    }
11057
11058
0
  gas_assert (!i.prefix[REX_PREFIX]);
11059
11060
0
  size = 4;
11061
0
  if (code16)
11062
0
    size = 2;
11063
11064
0
  if (i.prefixes != 0)
11065
0
    as_warn (_("skipping prefixes on `%s'"), insn_name (&i.tm));
11066
11067
0
  if (now_seg == absolute_section)
11068
0
    {
11069
0
      abs_section_offset += prefix + 1 + 2 + size;
11070
0
      return;
11071
0
    }
11072
11073
  /* 1 opcode; 2 segment; offset  */
11074
0
  p = frag_more (prefix + 1 + 2 + size);
11075
11076
0
  if (i.prefix[DATA_PREFIX] != 0)
11077
0
    *p++ = DATA_PREFIX_OPCODE;
11078
11079
0
  if (i.prefix[REX_PREFIX] != 0)
11080
0
    *p++ = i.prefix[REX_PREFIX];
11081
11082
0
  *p++ = i.tm.base_opcode;
11083
0
  if (i.op[1].imms->X_op == O_constant)
11084
0
    {
11085
0
      offsetT n = i.op[1].imms->X_add_number;
11086
11087
0
      if (size == 2
11088
0
    && !fits_in_unsigned_word (n)
11089
0
    && !fits_in_signed_word (n))
11090
0
  {
11091
0
    as_bad (_("16-bit jump out of range"));
11092
0
    return;
11093
0
  }
11094
0
      md_number_to_chars (p, n, size);
11095
0
    }
11096
0
  else
11097
0
    fix_new_exp (frag_now, p - frag_now->fr_literal, size,
11098
0
     i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
11099
11100
0
  p += size;
11101
0
  if (i.op[0].imms->X_op == O_constant)
11102
0
    md_number_to_chars (p, (valueT) i.op[0].imms->X_add_number, 2);
11103
0
  else
11104
0
    fix_new_exp (frag_now, p - frag_now->fr_literal, 2,
11105
0
     i.op[0].imms, 0, reloc (2, 0, 0, i.reloc[0]));
11106
0
}
11107
11108
#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11109
void
11110
x86_cleanup (void)
11111
736
{
11112
736
  char *p;
11113
736
  asection *seg = now_seg;
11114
736
  subsegT subseg = now_subseg;
11115
736
  asection *sec;
11116
736
  unsigned int alignment, align_size_1;
11117
736
  unsigned int isa_1_descsz, feature_2_descsz, descsz;
11118
736
  unsigned int isa_1_descsz_raw, feature_2_descsz_raw;
11119
736
  unsigned int padding;
11120
11121
736
  if (!IS_ELF || !x86_used_note)
11122
0
    return;
11123
11124
736
  x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_X86;
11125
11126
  /* The .note.gnu.property section layout:
11127
11128
     Field  Length    Contents
11129
     ---- ----    ----
11130
     n_namsz  4   4
11131
     n_descsz 4   The note descriptor size
11132
     n_type 4   NT_GNU_PROPERTY_TYPE_0
11133
     n_name 4   "GNU"
11134
     n_desc n_descsz  The program property array
11135
     .... ....    ....
11136
   */
11137
11138
  /* Create the .note.gnu.property section.  */
11139
736
  sec = subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME, 0);
11140
736
  bfd_set_section_flags (sec,
11141
736
       (SEC_ALLOC
11142
736
        | SEC_LOAD
11143
736
        | SEC_DATA
11144
736
        | SEC_HAS_CONTENTS
11145
736
        | SEC_READONLY));
11146
11147
736
  if (get_elf_backend_data (stdoutput)->s->elfclass == ELFCLASS64)
11148
736
    {
11149
736
      align_size_1 = 7;
11150
736
      alignment = 3;
11151
736
    }
11152
0
  else
11153
0
    {
11154
0
      align_size_1 = 3;
11155
0
      alignment = 2;
11156
0
    }
11157
11158
736
  bfd_set_section_alignment (sec, alignment);
11159
736
  elf_section_type (sec) = SHT_NOTE;
11160
11161
  /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size
11162
          + 4-byte data  */
11163
736
  isa_1_descsz_raw = 4 + 4 + 4;
11164
  /* Align GNU_PROPERTY_X86_ISA_1_USED.  */
11165
736
  isa_1_descsz = (isa_1_descsz_raw + align_size_1) & ~align_size_1;
11166
11167
736
  feature_2_descsz_raw = isa_1_descsz;
11168
  /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size
11169
              + 4-byte data  */
11170
736
  feature_2_descsz_raw += 4 + 4 + 4;
11171
  /* Align GNU_PROPERTY_X86_FEATURE_2_USED.  */
11172
736
  feature_2_descsz = ((feature_2_descsz_raw + align_size_1)
11173
736
          & ~align_size_1);
11174
11175
736
  descsz = feature_2_descsz;
11176
  /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz.  */
11177
736
  p = frag_more (4 + 4 + 4 + 4 + descsz);
11178
11179
  /* Write n_namsz.  */
11180
736
  md_number_to_chars (p, (valueT) 4, 4);
11181
11182
  /* Write n_descsz.  */
11183
736
  md_number_to_chars (p + 4, (valueT) descsz, 4);
11184
11185
  /* Write n_type.  */
11186
736
  md_number_to_chars (p + 4 * 2, (valueT) NT_GNU_PROPERTY_TYPE_0, 4);
11187
11188
  /* Write n_name.  */
11189
736
  memcpy (p + 4 * 3, "GNU", 4);
11190
11191
  /* Write 4-byte type.  */
11192
736
  md_number_to_chars (p + 4 * 4,
11193
736
          (valueT) GNU_PROPERTY_X86_ISA_1_USED, 4);
11194
11195
  /* Write 4-byte data size.  */
11196
736
  md_number_to_chars (p + 4 * 5, (valueT) 4, 4);
11197
11198
  /* Write 4-byte data.  */
11199
736
  md_number_to_chars (p + 4 * 6, (valueT) x86_isa_1_used, 4);
11200
11201
  /* Zero out paddings.  */
11202
736
  padding = isa_1_descsz - isa_1_descsz_raw;
11203
736
  if (padding)
11204
736
    memset (p + 4 * 7, 0, padding);
11205
11206
  /* Write 4-byte type.  */
11207
736
  md_number_to_chars (p + isa_1_descsz + 4 * 4,
11208
736
          (valueT) GNU_PROPERTY_X86_FEATURE_2_USED, 4);
11209
11210
  /* Write 4-byte data size.  */
11211
736
  md_number_to_chars (p + isa_1_descsz + 4 * 5, (valueT) 4, 4);
11212
11213
  /* Write 4-byte data.  */
11214
736
  md_number_to_chars (p + isa_1_descsz + 4 * 6,
11215
736
          (valueT) x86_feature_2_used, 4);
11216
11217
  /* Zero out paddings.  */
11218
736
  padding = feature_2_descsz - feature_2_descsz_raw;
11219
736
  if (padding)
11220
736
    memset (p + isa_1_descsz + 4 * 7, 0, padding);
11221
11222
  /* We probably can't restore the current segment, for there likely
11223
     isn't one yet...  */
11224
736
  if (seg && subseg)
11225
11
    subseg_set (seg, subseg);
11226
736
}
11227
11228
bool
11229
x86_support_sframe_p (void)
11230
0
{
11231
  /* At this time, SFrame stack trace is supported for AMD64 ABI only.  */
11232
0
  return (x86_elf_abi == X86_64_ABI);
11233
0
}
11234
11235
bool
11236
x86_sframe_ra_tracking_p (void)
11237
0
{
11238
  /* In AMD64, return address is always stored on the stack at a fixed offset
11239
     from the CFA (provided via x86_sframe_cfa_ra_offset ()).
11240
     Do not track explicitly via an SFrame Frame Row Entry.  */
11241
0
  return false;
11242
0
}
11243
11244
offsetT
11245
x86_sframe_cfa_ra_offset (void)
11246
0
{
11247
0
  gas_assert (x86_elf_abi == X86_64_ABI);
11248
0
  return (offsetT) -8;
11249
0
}
11250
11251
unsigned char
11252
x86_sframe_get_abi_arch (void)
11253
0
{
11254
0
  unsigned char sframe_abi_arch = 0;
11255
11256
0
  if (x86_support_sframe_p ())
11257
0
    {
11258
0
      gas_assert (!target_big_endian);
11259
0
      sframe_abi_arch = SFRAME_ABI_AMD64_ENDIAN_LITTLE;
11260
0
    }
11261
11262
0
  return sframe_abi_arch;
11263
0
}
11264
11265
#endif
11266
11267
static unsigned int
11268
encoding_length (const fragS *start_frag, offsetT start_off,
11269
     const char *frag_now_ptr)
11270
618k
{
11271
618k
  unsigned int len = 0;
11272
11273
618k
  if (start_frag != frag_now)
11274
158
    {
11275
158
      const fragS *fr = start_frag;
11276
11277
158
      do {
11278
158
  len += fr->fr_fix;
11279
158
  fr = fr->fr_next;
11280
158
      } while (fr && fr != frag_now);
11281
158
    }
11282
11283
618k
  return len - start_off + (frag_now_ptr - frag_now->fr_literal);
11284
618k
}
11285
11286
/* Return 1 for test, and, cmp, add, sub, inc and dec which may
11287
   be macro-fused with conditional jumps.
11288
   NB: If TEST/AND/CMP/ADD/SUB/INC/DEC is of RIP relative address,
11289
   or is one of the following format:
11290
11291
    cmp m, imm
11292
    add m, imm
11293
    sub m, imm
11294
   test m, imm
11295
    and m, imm
11296
    inc m
11297
    dec m
11298
11299
   it is unfusible.  */
11300
11301
static int
11302
maybe_fused_with_jcc_p (enum mf_cmp_kind* mf_cmp_p)
11303
0
{
11304
  /* No RIP address.  */
11305
0
  if (i.base_reg && i.base_reg->reg_num == RegIP)
11306
0
    return 0;
11307
11308
  /* No opcodes outside of base encoding space.  */
11309
0
  if (i.tm.opcode_space != SPACE_BASE)
11310
0
    return 0;
11311
11312
  /* add, sub without add/sub m, imm.  */
11313
0
  if (i.tm.base_opcode <= 5
11314
0
      || (i.tm.base_opcode >= 0x28 && i.tm.base_opcode <= 0x2d)
11315
0
      || ((i.tm.base_opcode | 3) == 0x83
11316
0
    && (i.tm.extension_opcode == 0x5
11317
0
        || i.tm.extension_opcode == 0x0)))
11318
0
    {
11319
0
      *mf_cmp_p = mf_cmp_alu_cmp;
11320
0
      return !(i.mem_operands && i.imm_operands);
11321
0
    }
11322
11323
  /* and without and m, imm.  */
11324
0
  if ((i.tm.base_opcode >= 0x20 && i.tm.base_opcode <= 0x25)
11325
0
      || ((i.tm.base_opcode | 3) == 0x83
11326
0
    && i.tm.extension_opcode == 0x4))
11327
0
    {
11328
0
      *mf_cmp_p = mf_cmp_test_and;
11329
0
      return !(i.mem_operands && i.imm_operands);
11330
0
    }
11331
11332
  /* test without test m imm.  */
11333
0
  if ((i.tm.base_opcode | 1) == 0x85
11334
0
      || (i.tm.base_opcode | 1) == 0xa9
11335
0
      || ((i.tm.base_opcode | 1) == 0xf7
11336
0
    && i.tm.extension_opcode == 0))
11337
0
    {
11338
0
      *mf_cmp_p = mf_cmp_test_and;
11339
0
      return !(i.mem_operands && i.imm_operands);
11340
0
    }
11341
11342
  /* cmp without cmp m, imm.  */
11343
0
  if ((i.tm.base_opcode >= 0x38 && i.tm.base_opcode <= 0x3d)
11344
0
      || ((i.tm.base_opcode | 3) == 0x83
11345
0
    && (i.tm.extension_opcode == 0x7)))
11346
0
    {
11347
0
      *mf_cmp_p = mf_cmp_alu_cmp;
11348
0
      return !(i.mem_operands && i.imm_operands);
11349
0
    }
11350
11351
  /* inc, dec without inc/dec m.   */
11352
0
  if ((is_cpu (&i.tm, CpuNo64)
11353
0
       && (i.tm.base_opcode | 0xf) == 0x4f)
11354
0
      || ((i.tm.base_opcode | 1) == 0xff
11355
0
    && i.tm.extension_opcode <= 0x1))
11356
0
    {
11357
0
      *mf_cmp_p = mf_cmp_incdec;
11358
0
      return !i.mem_operands;
11359
0
    }
11360
11361
0
  return 0;
11362
0
}
11363
11364
/* Return 1 if a FUSED_JCC_PADDING frag should be generated.  */
11365
11366
static int
11367
add_fused_jcc_padding_frag_p (enum mf_cmp_kind *mf_cmp_p,
11368
            const struct last_insn *last_insn)
11369
661k
{
11370
  /* NB: Don't work with COND_JUMP86 without i386.  */
11371
661k
  if (!align_branch_power
11372
661k
      || now_seg == absolute_section
11373
661k
      || !cpu_arch_flags.bitfield.cpui386
11374
661k
      || !(align_branch & align_branch_fused_bit))
11375
661k
    return 0;
11376
11377
0
  if (maybe_fused_with_jcc_p (mf_cmp_p))
11378
0
    {
11379
0
      if (last_insn->kind == last_insn_other)
11380
0
  return 1;
11381
0
      if (flag_debug)
11382
0
  as_warn_where (last_insn->file, last_insn->line,
11383
0
           _("`%s` skips -malign-branch-boundary on `%s`"),
11384
0
           last_insn->name, insn_name (&i.tm));
11385
0
    }
11386
11387
0
  return 0;
11388
0
}
11389
11390
/* Return 1 if a BRANCH_PREFIX frag should be generated.  */
11391
11392
static int
11393
add_branch_prefix_frag_p (const struct last_insn *last_insn)
11394
661k
{
11395
  /* NB: Don't work with COND_JUMP86 without i386.  Don't add prefix
11396
     to PadLock instructions since they include prefixes in opcode.  */
11397
661k
  if (!align_branch_power
11398
661k
      || !align_branch_prefix_size
11399
661k
      || now_seg == absolute_section
11400
661k
      || is_cpu (&i.tm, CpuPadLock)
11401
661k
      || !cpu_arch_flags.bitfield.cpui386)
11402
661k
    return 0;
11403
11404
  /* Don't add prefix if it is a prefix or there is no operand in case
11405
     that segment prefix is special.  */
11406
0
  if (!i.operands || i.tm.opcode_modifier.isprefix)
11407
0
    return 0;
11408
11409
0
  if (last_insn->kind == last_insn_other)
11410
0
    return 1;
11411
11412
0
  if (flag_debug)
11413
0
    as_warn_where (last_insn->file, last_insn->line,
11414
0
       _("`%s` skips -malign-branch-boundary on `%s`"),
11415
0
       last_insn->name, insn_name (&i.tm));
11416
11417
0
  return 0;
11418
0
}
11419
11420
/* Return 1 if a BRANCH_PADDING frag should be generated.  */
11421
11422
static int
11423
add_branch_padding_frag_p (enum align_branch_kind *branch_p,
11424
         enum mf_jcc_kind *mf_jcc_p,
11425
         const struct last_insn *last_insn)
11426
662k
{
11427
662k
  int add_padding;
11428
11429
  /* NB: Don't work with COND_JUMP86 without i386.  */
11430
662k
  if (!align_branch_power
11431
662k
      || now_seg == absolute_section
11432
662k
      || !cpu_arch_flags.bitfield.cpui386
11433
662k
      || i.tm.opcode_space != SPACE_BASE)
11434
662k
    return 0;
11435
11436
0
  add_padding = 0;
11437
11438
  /* Check for jcc and direct jmp.  */
11439
0
  if (i.tm.opcode_modifier.jump == JUMP)
11440
0
    {
11441
0
      if (i.tm.base_opcode == JUMP_PC_RELATIVE)
11442
0
  {
11443
0
    *branch_p = align_branch_jmp;
11444
0
    add_padding = align_branch & align_branch_jmp_bit;
11445
0
  }
11446
0
      else
11447
0
  {
11448
    /* Because J<cc> and JN<cc> share same group in macro-fusible table,
11449
       igore the lowest bit.  */
11450
0
    *mf_jcc_p = (i.tm.base_opcode & 0x0e) >> 1;
11451
0
    *branch_p = align_branch_jcc;
11452
0
    if ((align_branch & align_branch_jcc_bit))
11453
0
      add_padding = 1;
11454
0
  }
11455
0
    }
11456
0
  else if ((i.tm.base_opcode | 1) == 0xc3)
11457
0
    {
11458
      /* Near ret.  */
11459
0
      *branch_p = align_branch_ret;
11460
0
      if ((align_branch & align_branch_ret_bit))
11461
0
  add_padding = 1;
11462
0
    }
11463
0
  else
11464
0
    {
11465
      /* Check for indirect jmp, direct and indirect calls.  */
11466
0
      if (i.tm.base_opcode == 0xe8)
11467
0
  {
11468
    /* Direct call.  */
11469
0
    *branch_p = align_branch_call;
11470
0
    if ((align_branch & align_branch_call_bit))
11471
0
      add_padding = 1;
11472
0
  }
11473
0
      else if (i.tm.base_opcode == 0xff
11474
0
         && (i.tm.extension_opcode == 2
11475
0
       || i.tm.extension_opcode == 4))
11476
0
  {
11477
    /* Indirect call and jmp.  */
11478
0
    *branch_p = align_branch_indirect;
11479
0
    if ((align_branch & align_branch_indirect_bit))
11480
0
      add_padding = 1;
11481
0
  }
11482
11483
0
      if (add_padding
11484
0
    && i.disp_operands
11485
0
    && tls_get_addr
11486
0
    && (i.op[0].disps->X_op == O_symbol
11487
0
        || (i.op[0].disps->X_op == O_subtract
11488
0
      && i.op[0].disps->X_op_symbol == GOT_symbol)))
11489
0
  {
11490
0
    symbolS *s = i.op[0].disps->X_add_symbol;
11491
    /* No padding to call to global or undefined tls_get_addr.  */
11492
0
    if ((S_IS_EXTERNAL (s) || !S_IS_DEFINED (s))
11493
0
        && strcmp (S_GET_NAME (s), tls_get_addr) == 0)
11494
0
      return 0;
11495
0
  }
11496
0
    }
11497
11498
0
  if (add_padding
11499
0
      && last_insn->kind != last_insn_other)
11500
0
    {
11501
0
      if (flag_debug)
11502
0
  as_warn_where (last_insn->file, last_insn->line,
11503
0
           _("`%s` skips -malign-branch-boundary on `%s`"),
11504
0
           last_insn->name, insn_name (&i.tm));
11505
0
      return 0;
11506
0
    }
11507
11508
0
  return add_padding;
11509
0
}
11510
11511
static void
11512
output_insn (const struct last_insn *last_insn)
11513
662k
{
11514
662k
  fragS *insn_start_frag;
11515
662k
  offsetT insn_start_off;
11516
662k
  fragS *fragP = NULL;
11517
662k
  enum align_branch_kind branch = align_branch_none;
11518
  /* The initializer is arbitrary just to avoid uninitialized error.
11519
     it's actually either assigned in add_branch_padding_frag_p
11520
     or never be used.  */
11521
662k
  enum mf_jcc_kind mf_jcc = mf_jcc_jo;
11522
11523
662k
#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11524
662k
  if (IS_ELF && x86_used_note && now_seg != absolute_section)
11525
619k
    {
11526
619k
      if ((i.xstate & xstate_tmm) == xstate_tmm
11527
619k
    || is_cpu (&i.tm, CpuAMX_TILE))
11528
0
  x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_TMM;
11529
11530
619k
      if (is_cpu (&i.tm, Cpu8087)
11531
619k
    || is_cpu (&i.tm, Cpu287)
11532
619k
    || is_cpu (&i.tm, Cpu387)
11533
619k
    || is_cpu (&i.tm, Cpu687)
11534
619k
    || is_cpu (&i.tm, CpuFISTTP))
11535
9
  x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_X87;
11536
11537
619k
      if ((i.xstate & xstate_mmx)
11538
619k
    || i.tm.mnem_off == MN_emms
11539
619k
    || i.tm.mnem_off == MN_femms)
11540
0
  x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_MMX;
11541
11542
619k
      if (i.index_reg)
11543
0
  {
11544
0
    if (i.index_reg->reg_type.bitfield.zmmword)
11545
0
      i.xstate |= xstate_zmm;
11546
0
    else if (i.index_reg->reg_type.bitfield.ymmword)
11547
0
      i.xstate |= xstate_ymm;
11548
0
    else if (i.index_reg->reg_type.bitfield.xmmword)
11549
0
      i.xstate |= xstate_xmm;
11550
0
  }
11551
11552
      /* vzeroall / vzeroupper */
11553
619k
      if (i.tm.base_opcode == 0x77 && is_cpu (&i.tm, CpuAVX))
11554
2
  i.xstate |= xstate_ymm;
11555
11556
619k
      if ((i.xstate & xstate_xmm)
11557
    /* ldmxcsr / stmxcsr / vldmxcsr / vstmxcsr */
11558
619k
    || (i.tm.base_opcode == 0xae
11559
619k
        && (is_cpu (&i.tm, CpuSSE)
11560
410
      || is_cpu (&i.tm, CpuAVX)))
11561
619k
    || is_cpu (&i.tm, CpuWideKL)
11562
619k
    || is_cpu (&i.tm, CpuKL))
11563
2
  x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XMM;
11564
11565
619k
      if ((i.xstate & xstate_ymm) == xstate_ymm)
11566
2
  x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_YMM;
11567
619k
      if ((i.xstate & xstate_zmm) == xstate_zmm)
11568
0
  x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_ZMM;
11569
619k
      if (i.mask.reg || (i.xstate & xstate_mask) == xstate_mask)
11570
0
  x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_MASK;
11571
619k
      if (is_cpu (&i.tm, CpuFXSR))
11572
0
  x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_FXSR;
11573
619k
      if (is_cpu (&i.tm, CpuXsave))
11574
0
  x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XSAVE;
11575
619k
      if (is_cpu (&i.tm, CpuXsaveopt))
11576
0
  x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT;
11577
619k
      if (is_cpu (&i.tm, CpuXSAVEC))
11578
0
  x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XSAVEC;
11579
11580
619k
      if (x86_feature_2_used
11581
619k
    || is_cpu (&i.tm, CpuCMOV)
11582
619k
    || is_cpu (&i.tm, CpuSYSCALL)
11583
619k
    || i.tm.mnem_off == MN_cmpxchg8b)
11584
619k
  x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_BASELINE;
11585
619k
      if (is_cpu (&i.tm, CpuSSE3)
11586
619k
    || is_cpu (&i.tm, CpuSSSE3)
11587
619k
    || is_cpu (&i.tm, CpuSSE4_1)
11588
619k
    || is_cpu (&i.tm, CpuSSE4_2)
11589
619k
    || is_cpu (&i.tm, CpuCX16)
11590
619k
    || is_cpu (&i.tm, CpuPOPCNT)
11591
    /* LAHF-SAHF insns in 64-bit mode.  */
11592
619k
    || (flag_code == CODE_64BIT
11593
619k
        && (i.tm.base_opcode | 1) == 0x9f
11594
619k
        && i.tm.opcode_space == SPACE_BASE))
11595
0
  x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_V2;
11596
619k
      if (is_cpu (&i.tm, CpuAVX)
11597
619k
    || is_cpu (&i.tm, CpuAVX2)
11598
    /* Any VEX encoded insns execpt for AVX512F, AVX512BW, AVX512DQ,
11599
       XOP, FMA4, LPW, TBM, and AMX.  */
11600
619k
    || (i.tm.opcode_modifier.vex
11601
619k
        && !is_cpu (&i.tm, CpuAVX512F)
11602
619k
        && !is_cpu (&i.tm, CpuAVX512BW)
11603
619k
        && !is_cpu (&i.tm, CpuAVX512DQ)
11604
619k
        && !is_cpu (&i.tm, CpuXOP)
11605
619k
        && !is_cpu (&i.tm, CpuFMA4)
11606
619k
        && !is_cpu (&i.tm, CpuLWP)
11607
619k
        && !is_cpu (&i.tm, CpuTBM)
11608
619k
        && !(x86_feature_2_used & GNU_PROPERTY_X86_FEATURE_2_TMM))
11609
619k
    || is_cpu (&i.tm, CpuF16C)
11610
619k
    || is_cpu (&i.tm, CpuFMA)
11611
619k
    || is_cpu (&i.tm, CpuLZCNT)
11612
619k
    || is_cpu (&i.tm, CpuMovbe)
11613
619k
    || is_cpu (&i.tm, CpuXSAVES)
11614
619k
    || (x86_feature_2_used
11615
619k
        & (GNU_PROPERTY_X86_FEATURE_2_XSAVE
11616
619k
     | GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
11617
619k
     | GNU_PROPERTY_X86_FEATURE_2_XSAVEC)) != 0)
11618
2
  x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_V3;
11619
619k
      if (is_cpu (&i.tm, CpuAVX512F)
11620
619k
    || is_cpu (&i.tm, CpuAVX512BW)
11621
619k
    || is_cpu (&i.tm, CpuAVX512DQ)
11622
619k
    || is_cpu (&i.tm, CpuAVX512VL)
11623
    /* Any EVEX encoded insns except for AVX512ER, AVX512PF,
11624
       AVX512-4FMAPS, and AVX512-4VNNIW.  */
11625
619k
    || (i.tm.opcode_modifier.evex
11626
619k
        && !is_cpu (&i.tm, CpuAVX512ER)
11627
619k
        && !is_cpu (&i.tm, CpuAVX512PF)
11628
619k
        && !is_cpu (&i.tm, CpuAVX512_4FMAPS)
11629
619k
        && !is_cpu (&i.tm, CpuAVX512_4VNNIW)))
11630
0
  x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_V4;
11631
619k
    }
11632
662k
#endif
11633
11634
  /* Tie dwarf2 debug info to the address at the start of the insn.
11635
     We can't do this after the insn has been output as the current
11636
     frag may have been closed off.  eg. by frag_var.  */
11637
662k
  dwarf2_emit_insn (0);
11638
11639
662k
  insn_start_frag = frag_now;
11640
662k
  insn_start_off = frag_now_fix ();
11641
11642
662k
  if (add_branch_padding_frag_p (&branch, &mf_jcc, last_insn))
11643
0
    {
11644
0
      char *p;
11645
      /* Branch can be 8 bytes.  Leave some room for prefixes.  */
11646
0
      unsigned int max_branch_padding_size = 14;
11647
11648
      /* Align section to boundary.  */
11649
0
      record_alignment (now_seg, align_branch_power);
11650
11651
      /* Make room for padding.  */
11652
0
      frag_grow (max_branch_padding_size);
11653
11654
      /* Start of the padding.  */
11655
0
      p = frag_more (0);
11656
11657
0
      fragP = frag_now;
11658
11659
0
      frag_var (rs_machine_dependent, max_branch_padding_size, 0,
11660
0
    ENCODE_RELAX_STATE (BRANCH_PADDING, 0),
11661
0
    NULL, 0, p);
11662
11663
0
      fragP->tc_frag_data.mf_type = mf_jcc;
11664
0
      fragP->tc_frag_data.branch_type = branch;
11665
0
      fragP->tc_frag_data.max_bytes = max_branch_padding_size;
11666
0
    }
11667
11668
662k
  if (!cpu_arch_flags.bitfield.cpui386 && (flag_code != CODE_16BIT)
11669
662k
      && !pre_386_16bit_warned)
11670
0
    {
11671
0
      as_warn (_("use .code16 to ensure correct addressing mode"));
11672
0
      pre_386_16bit_warned = true;
11673
0
    }
11674
11675
  /* Output jumps.  */
11676
662k
  if (i.tm.opcode_modifier.jump == JUMP)
11677
881
    output_branch ();
11678
661k
  else if (i.tm.opcode_modifier.jump == JUMP_BYTE
11679
661k
     || i.tm.opcode_modifier.jump == JUMP_DWORD)
11680
20
    output_jump ();
11681
661k
  else if (i.tm.opcode_modifier.jump == JUMP_INTERSEGMENT)
11682
0
    output_interseg_jump ();
11683
661k
  else
11684
661k
    {
11685
      /* Output normal instructions here.  */
11686
661k
      char *p;
11687
661k
      unsigned char *q;
11688
661k
      unsigned int j;
11689
661k
      enum mf_cmp_kind mf_cmp;
11690
11691
661k
      if (avoid_fence
11692
661k
    && (i.tm.base_opcode == 0xaee8
11693
0
        || i.tm.base_opcode == 0xaef0
11694
0
        || i.tm.base_opcode == 0xaef8))
11695
0
  {
11696
    /* Encode lfence, mfence, and sfence as
11697
       f0 83 04 24 00   lock addl $0x0, (%{re}sp).  */
11698
0
    if (flag_code == CODE_16BIT)
11699
0
      as_bad (_("Cannot convert `%s' in 16-bit mode"), insn_name (&i.tm));
11700
0
    else if (omit_lock_prefix)
11701
0
      as_bad (_("Cannot convert `%s' with `-momit-lock-prefix=yes' in effect"),
11702
0
        insn_name (&i.tm));
11703
0
    else if (now_seg != absolute_section)
11704
0
      {
11705
0
        offsetT val = 0x240483f0ULL;
11706
11707
0
        p = frag_more (5);
11708
0
        md_number_to_chars (p, val, 5);
11709
0
      }
11710
0
    else
11711
0
      abs_section_offset += 5;
11712
0
    return;
11713
0
  }
11714
11715
      /* Some processors fail on LOCK prefix. This options makes
11716
   assembler ignore LOCK prefix and serves as a workaround.  */
11717
661k
      if (omit_lock_prefix)
11718
0
  {
11719
0
    if (i.tm.base_opcode == LOCK_PREFIX_OPCODE
11720
0
        && i.tm.opcode_modifier.isprefix)
11721
0
      return;
11722
0
    i.prefix[LOCK_PREFIX] = 0;
11723
0
  }
11724
11725
661k
      if (branch)
11726
  /* Skip if this is a branch.  */
11727
0
  ;
11728
661k
      else if (add_fused_jcc_padding_frag_p (&mf_cmp, last_insn))
11729
0
  {
11730
    /* Make room for padding.  */
11731
0
    frag_grow (MAX_FUSED_JCC_PADDING_SIZE);
11732
0
    p = frag_more (0);
11733
11734
0
    fragP = frag_now;
11735
11736
0
    frag_var (rs_machine_dependent, MAX_FUSED_JCC_PADDING_SIZE, 0,
11737
0
        ENCODE_RELAX_STATE (FUSED_JCC_PADDING, 0),
11738
0
        NULL, 0, p);
11739
11740
0
    fragP->tc_frag_data.mf_type = mf_cmp;
11741
0
    fragP->tc_frag_data.branch_type = align_branch_fused;
11742
0
    fragP->tc_frag_data.max_bytes = MAX_FUSED_JCC_PADDING_SIZE;
11743
0
  }
11744
661k
      else if (add_branch_prefix_frag_p (last_insn))
11745
0
  {
11746
0
    unsigned int max_prefix_size = align_branch_prefix_size;
11747
11748
    /* Make room for padding.  */
11749
0
    frag_grow (max_prefix_size);
11750
0
    p = frag_more (0);
11751
11752
0
    fragP = frag_now;
11753
11754
0
    frag_var (rs_machine_dependent, max_prefix_size, 0,
11755
0
        ENCODE_RELAX_STATE (BRANCH_PREFIX, 0),
11756
0
        NULL, 0, p);
11757
11758
0
    fragP->tc_frag_data.max_bytes = max_prefix_size;
11759
0
  }
11760
11761
      /* Since the VEX/EVEX prefix contains the implicit prefix, we
11762
   don't need the explicit prefix.  */
11763
661k
      if (!is_any_vex_encoding (&i.tm))
11764
661k
  {
11765
661k
    switch (i.tm.opcode_modifier.opcodeprefix)
11766
661k
      {
11767
410
      case PREFIX_0X66:
11768
410
        add_prefix (0x66);
11769
410
        break;
11770
0
      case PREFIX_0XF2:
11771
0
        add_prefix (0xf2);
11772
0
        break;
11773
0
      case PREFIX_0XF3:
11774
0
        if (!is_cpu (&i.tm, CpuPadLock)
11775
0
      || (i.prefix[REP_PREFIX] != 0xf3))
11776
0
    add_prefix (0xf3);
11777
0
        break;
11778
661k
      case PREFIX_NONE:
11779
661k
        switch (i.opcode_length)
11780
661k
    {
11781
15
    case 2:
11782
15
      break;
11783
661k
    case 1:
11784
      /* Check for pseudo prefixes.  */
11785
661k
      if (!i.tm.opcode_modifier.isprefix || i.tm.base_opcode)
11786
661k
        break;
11787
0
      as_bad_where (insn_start_frag->fr_file,
11788
0
        insn_start_frag->fr_line,
11789
0
        _("pseudo prefix without instruction"));
11790
0
      return;
11791
0
    default:
11792
0
      abort ();
11793
661k
    }
11794
661k
        break;
11795
661k
      default:
11796
0
        abort ();
11797
661k
      }
11798
11799
661k
#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11800
    /* For x32, add a dummy REX_OPCODE prefix for mov/add with
11801
       R_X86_64_GOTTPOFF relocation so that linker can safely
11802
       perform IE->LE optimization.  A dummy REX_OPCODE prefix
11803
       is also needed for lea with R_X86_64_GOTPC32_TLSDESC
11804
       relocation for GDesc -> IE/LE optimization.  */
11805
661k
    if (x86_elf_abi == X86_64_X32_ABI
11806
661k
        && !is_apx_rex2_encoding ()
11807
661k
        && i.operands == 2
11808
661k
        && (i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF
11809
0
      || i.reloc[0] == BFD_RELOC_X86_64_GOTPC32_TLSDESC)
11810
661k
        && i.prefix[REX_PREFIX] == 0)
11811
0
      add_prefix (REX_OPCODE);
11812
661k
#endif
11813
11814
    /* The prefix bytes.  */
11815
5.29M
    for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
11816
4.63M
      if (*q)
11817
3.49k
        frag_opcode_byte (*q);
11818
11819
661k
    if (is_apx_rex2_encoding ())
11820
0
      {
11821
0
        frag_opcode_byte (i.vex.bytes[0]);
11822
0
        frag_opcode_byte (i.vex.bytes[1]);
11823
0
      }
11824
661k
  }
11825
2
      else
11826
2
  {
11827
16
    for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
11828
14
      if (*q)
11829
0
        switch (j)
11830
0
    {
11831
0
    case SEG_PREFIX:
11832
0
    case ADDR_PREFIX:
11833
0
      frag_opcode_byte (*q);
11834
0
      break;
11835
0
    default:
11836
      /* There should be no other prefixes for instructions
11837
         with VEX prefix.  */
11838
0
      abort ();
11839
0
    }
11840
11841
    /* For EVEX instructions i.vrex should become 0 after
11842
       build_evex_prefix.  For VEX instructions upper 16 registers
11843
       aren't available, so VREX should be 0.  */
11844
2
    if (i.vrex)
11845
0
      abort ();
11846
    /* Now the VEX prefix.  */
11847
2
    if (now_seg != absolute_section)
11848
2
      {
11849
2
        p = frag_more (i.vex.length);
11850
6
        for (j = 0; j < i.vex.length; j++)
11851
4
    p[j] = i.vex.bytes[j];
11852
2
      }
11853
0
    else
11854
0
      abs_section_offset += i.vex.length;
11855
2
  }
11856
11857
      /* Now the opcode; be careful about word order here!  */
11858
661k
      j = i.opcode_length;
11859
661k
      if (!i.vex.length)
11860
661k
  switch (i.tm.opcode_space)
11861
661k
    {
11862
660k
    case SPACE_BASE:
11863
660k
      break;
11864
1.34k
    case SPACE_0F:
11865
1.34k
      ++j;
11866
1.34k
      break;
11867
0
    case SPACE_0F38:
11868
0
    case SPACE_0F3A:
11869
0
      j += 2;
11870
0
      break;
11871
0
    default:
11872
0
      abort ();
11873
661k
    }
11874
11875
661k
      if (now_seg == absolute_section)
11876
43.0k
  abs_section_offset += j;
11877
618k
      else if (j == 1)
11878
617k
  {
11879
617k
    FRAG_APPEND_1_CHAR (i.tm.base_opcode);
11880
617k
  }
11881
1.32k
      else
11882
1.32k
  {
11883
1.32k
    p = frag_more (j);
11884
1.32k
    if (!i.vex.length
11885
1.32k
        && i.tm.opcode_space != SPACE_BASE)
11886
1.31k
      {
11887
1.31k
        *p++ = 0x0f;
11888
1.31k
        if (i.tm.opcode_space != SPACE_0F)
11889
0
    *p++ = i.tm.opcode_space == SPACE_0F38
11890
0
           ? 0x38 : 0x3a;
11891
1.31k
      }
11892
11893
1.32k
    switch (i.opcode_length)
11894
1.32k
      {
11895
15
      case 2:
11896
        /* Put out high byte first: can't use md_number_to_chars!  */
11897
15
        *p++ = (i.tm.base_opcode >> 8) & 0xff;
11898
        /* Fall through.  */
11899
1.32k
      case 1:
11900
1.32k
        *p = i.tm.base_opcode & 0xff;
11901
1.32k
        break;
11902
0
      default:
11903
0
        abort ();
11904
0
        break;
11905
1.32k
      }
11906
11907
1.32k
  }
11908
11909
      /* Now the modrm byte and sib byte (if present).  */
11910
661k
      if (i.tm.opcode_modifier.modrm)
11911
18.2k
  {
11912
18.2k
    frag_opcode_byte ((i.rm.regmem << 0)
11913
18.2k
           | (i.rm.reg << 3)
11914
18.2k
           | (i.rm.mode << 6));
11915
    /* If i.rm.regmem == ESP (4)
11916
       && i.rm.mode != (Register mode)
11917
       && not 16 bit
11918
       ==> need second modrm byte.  */
11919
18.2k
    if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
11920
18.2k
        && i.rm.mode != 3
11921
18.2k
        && !(i.base_reg && i.base_reg->reg_type.bitfield.word))
11922
6.32k
      frag_opcode_byte ((i.sib.base << 0)
11923
6.32k
            | (i.sib.index << 3)
11924
6.32k
            | (i.sib.scale << 6));
11925
18.2k
  }
11926
11927
661k
      if (i.disp_operands)
11928
18.2k
  output_disp (insn_start_frag, insn_start_off);
11929
11930
661k
      if (i.imm_operands)
11931
15.3k
  output_imm (insn_start_frag, insn_start_off);
11932
11933
      /*
11934
       * frag_now_fix () returning plain abs_section_offset when we're in the
11935
       * absolute section, and abs_section_offset not getting updated as data
11936
       * gets added to the frag breaks the logic below.
11937
       */
11938
661k
      if (now_seg != absolute_section)
11939
618k
  {
11940
618k
    j = encoding_length (insn_start_frag, insn_start_off, frag_more (0));
11941
618k
    if (j > 15)
11942
0
      {
11943
0
        if (dot_insn ())
11944
0
    as_warn (_("instruction length of %u bytes exceeds the limit of 15"),
11945
0
      j);
11946
0
        else
11947
0
    as_bad (_("instruction length of %u bytes exceeds the limit of 15"),
11948
0
      j);
11949
0
      }
11950
618k
    else if (fragP)
11951
0
      {
11952
        /* NB: Don't add prefix with GOTPC relocation since
11953
     output_disp() above depends on the fixed encoding
11954
     length.  Can't add prefix with TLS relocation since
11955
     it breaks TLS linker optimization.  */
11956
0
        unsigned int max = i.has_gotpc_tls_reloc ? 0 : 15 - j;
11957
        /* Prefix count on the current instruction.  */
11958
0
        unsigned int count = i.vex.length;
11959
0
        unsigned int k;
11960
0
        for (k = 0; k < ARRAY_SIZE (i.prefix); k++)
11961
    /* REX byte is encoded in VEX/EVEX prefix.  */
11962
0
    if (i.prefix[k] && (k != REX_PREFIX || !i.vex.length))
11963
0
      count++;
11964
11965
        /* Count prefixes for extended opcode maps.  */
11966
0
        if (!i.vex.length)
11967
0
    switch (i.tm.opcode_space)
11968
0
      {
11969
0
      case SPACE_BASE:
11970
0
        break;
11971
0
      case SPACE_0F:
11972
0
        count++;
11973
0
        break;
11974
0
      case SPACE_0F38:
11975
0
      case SPACE_0F3A:
11976
0
        count += 2;
11977
0
        break;
11978
0
      default:
11979
0
        abort ();
11980
0
      }
11981
11982
0
        if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype)
11983
0
      == BRANCH_PREFIX)
11984
0
    {
11985
      /* Set the maximum prefix size in BRANCH_PREFIX
11986
         frag.  */
11987
0
      if (fragP->tc_frag_data.max_bytes > max)
11988
0
        fragP->tc_frag_data.max_bytes = max;
11989
0
      if (fragP->tc_frag_data.max_bytes > count)
11990
0
        fragP->tc_frag_data.max_bytes -= count;
11991
0
      else
11992
0
        fragP->tc_frag_data.max_bytes = 0;
11993
0
    }
11994
0
        else
11995
0
    {
11996
      /* Remember the maximum prefix size in FUSED_JCC_PADDING
11997
         frag.  */
11998
0
      unsigned int max_prefix_size;
11999
0
      if (align_branch_prefix_size > max)
12000
0
        max_prefix_size = max;
12001
0
      else
12002
0
        max_prefix_size = align_branch_prefix_size;
12003
0
      if (max_prefix_size > count)
12004
0
        fragP->tc_frag_data.max_prefix_length
12005
0
          = max_prefix_size - count;
12006
0
    }
12007
12008
        /* Use existing segment prefix if possible.  Use CS
12009
     segment prefix in 64-bit mode.  In 32-bit mode, use SS
12010
     segment prefix with ESP/EBP base register and use DS
12011
     segment prefix without ESP/EBP base register.  */
12012
0
        if (i.prefix[SEG_PREFIX])
12013
0
    fragP->tc_frag_data.default_prefix = i.prefix[SEG_PREFIX];
12014
0
        else if (flag_code == CODE_64BIT)
12015
0
    fragP->tc_frag_data.default_prefix = CS_PREFIX_OPCODE;
12016
0
        else if (i.base_reg
12017
0
           && (i.base_reg->reg_num == 4
12018
0
         || i.base_reg->reg_num == 5))
12019
0
    fragP->tc_frag_data.default_prefix = SS_PREFIX_OPCODE;
12020
0
        else
12021
0
    fragP->tc_frag_data.default_prefix = DS_PREFIX_OPCODE;
12022
0
      }
12023
618k
  }
12024
661k
    }
12025
12026
  /* NB: Don't work with COND_JUMP86 without i386.  */
12027
662k
  if (align_branch_power
12028
662k
      && now_seg != absolute_section
12029
662k
      && cpu_arch_flags.bitfield.cpui386)
12030
0
    {
12031
      /* Terminate each frag so that we can add prefix and check for
12032
         fused jcc.  */
12033
0
      frag_wane (frag_now);
12034
0
      frag_new (0);
12035
0
    }
12036
12037
#ifdef DEBUG386
12038
  if (flag_debug)
12039
    {
12040
      pi ("" /*line*/, &i);
12041
    }
12042
#endif /* DEBUG386  */
12043
662k
}
12044
12045
/* Return the size of the displacement operand N.  */
12046
12047
static int
12048
disp_size (unsigned int n)
12049
18.2k
{
12050
18.2k
  int size = 4;
12051
12052
18.2k
  if (i.types[n].bitfield.disp64)
12053
0
    size = 8;
12054
18.2k
  else if (i.types[n].bitfield.disp8)
12055
0
    size = 1;
12056
18.2k
  else if (i.types[n].bitfield.disp16)
12057
7.30k
    size = 2;
12058
18.2k
  return size;
12059
18.2k
}
12060
12061
/* Return the size of the immediate operand N.  */
12062
12063
static int
12064
imm_size (unsigned int n)
12065
15.3k
{
12066
15.3k
  int size = 4;
12067
15.3k
  if (i.types[n].bitfield.imm64)
12068
0
    size = 8;
12069
15.3k
  else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
12070
11.6k
    size = 1;
12071
3.77k
  else if (i.types[n].bitfield.imm16)
12072
2.41k
    size = 2;
12073
15.3k
  return size;
12074
15.3k
}
12075
12076
static void
12077
output_disp (fragS *insn_start_frag, offsetT insn_start_off)
12078
18.2k
{
12079
18.2k
  char *p;
12080
18.2k
  unsigned int n;
12081
12082
51.4k
  for (n = 0; n < i.operands; n++)
12083
33.2k
    {
12084
33.2k
      if (operand_type_check (i.types[n], disp))
12085
18.2k
  {
12086
18.2k
    int size = disp_size (n);
12087
12088
18.2k
    if (now_seg == absolute_section)
12089
3.16k
      abs_section_offset += size;
12090
15.0k
    else if (i.op[n].disps->X_op == O_constant)
12091
11.6k
      {
12092
11.6k
        offsetT val = i.op[n].disps->X_add_number;
12093
12094
11.6k
        val = offset_in_range (val >> (size == 1 ? i.memshift : 0),
12095
11.6k
             size);
12096
11.6k
        p = frag_more (size);
12097
11.6k
        md_number_to_chars (p, val, size);
12098
11.6k
      }
12099
3.35k
    else
12100
3.35k
      {
12101
3.35k
        enum bfd_reloc_code_real reloc_type;
12102
3.35k
        bool pcrel = (i.flags[n] & Operand_PCrel) != 0;
12103
3.35k
        bool sign = (flag_code == CODE_64BIT && size == 4
12104
3.35k
         && (!want_disp32 (&i.tm)
12105
2.12k
             || (i.tm.opcode_modifier.jump && !i.jumpabsolute
12106
0
           && !i.types[n].bitfield.baseindex)))
12107
3.35k
        || pcrel;
12108
3.35k
        fixS *fixP;
12109
12110
        /* We can't have 8 bit displacement here.  */
12111
3.35k
        gas_assert (!i.types[n].bitfield.disp8);
12112
12113
        /* The PC relative address is computed relative
12114
     to the instruction boundary, so in case immediate
12115
     fields follows, we need to adjust the value.  */
12116
3.35k
        if (pcrel && i.imm_operands)
12117
0
    {
12118
0
      unsigned int n1;
12119
0
      int sz = 0;
12120
12121
0
      for (n1 = 0; n1 < i.operands; n1++)
12122
0
        if (operand_type_check (i.types[n1], imm))
12123
0
          {
12124
      /* Only one immediate is allowed for PC
12125
         relative address, except with .insn.  */
12126
0
      gas_assert (sz == 0 || dot_insn ());
12127
0
      sz += imm_size (n1);
12128
0
          }
12129
      /* We should find at least one immediate.  */
12130
0
      gas_assert (sz != 0);
12131
0
      i.op[n].disps->X_add_number -= sz;
12132
0
    }
12133
12134
3.35k
        p = frag_more (size);
12135
3.35k
        reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
12136
3.35k
        if (GOT_symbol
12137
3.35k
      && GOT_symbol == i.op[n].disps->X_add_symbol
12138
3.35k
      && (((reloc_type == BFD_RELOC_32
12139
0
      || reloc_type == BFD_RELOC_X86_64_32S
12140
0
      || (reloc_type == BFD_RELOC_64
12141
0
          && object_64bit))
12142
0
           && (i.op[n].disps->X_op == O_symbol
12143
0
         || (i.op[n].disps->X_op == O_add
12144
0
             && ((symbol_get_value_expression
12145
0
            (i.op[n].disps->X_op_symbol)->X_op)
12146
0
           == O_subtract))))
12147
0
          || reloc_type == BFD_RELOC_32_PCREL))
12148
0
    {
12149
0
      if (!object_64bit)
12150
0
        {
12151
0
          reloc_type = BFD_RELOC_386_GOTPC;
12152
0
          i.has_gotpc_tls_reloc = true;
12153
0
          i.op[n].disps->X_add_number +=
12154
0
      encoding_length (insn_start_frag, insn_start_off, p);
12155
0
        }
12156
0
      else if (reloc_type == BFD_RELOC_64)
12157
0
        reloc_type = BFD_RELOC_X86_64_GOTPC64;
12158
0
      else
12159
        /* Don't do the adjustment for x86-64, as there
12160
           the pcrel addressing is relative to the _next_
12161
           insn, and that is taken care of in other code.  */
12162
0
        reloc_type = BFD_RELOC_X86_64_GOTPC32;
12163
0
    }
12164
3.35k
        else if (align_branch_power)
12165
0
    {
12166
0
      switch (reloc_type)
12167
0
        {
12168
0
        case BFD_RELOC_386_TLS_GD:
12169
0
        case BFD_RELOC_386_TLS_LDM:
12170
0
        case BFD_RELOC_386_TLS_IE:
12171
0
        case BFD_RELOC_386_TLS_IE_32:
12172
0
        case BFD_RELOC_386_TLS_GOTIE:
12173
0
        case BFD_RELOC_386_TLS_GOTDESC:
12174
0
        case BFD_RELOC_386_TLS_DESC_CALL:
12175
0
        case BFD_RELOC_X86_64_TLSGD:
12176
0
        case BFD_RELOC_X86_64_TLSLD:
12177
0
        case BFD_RELOC_X86_64_GOTTPOFF:
12178
0
        case BFD_RELOC_X86_64_CODE_4_GOTTPOFF:
12179
0
        case BFD_RELOC_X86_64_CODE_6_GOTTPOFF:
12180
0
        case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
12181
0
        case BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC:
12182
0
        case BFD_RELOC_X86_64_TLSDESC_CALL:
12183
0
          i.has_gotpc_tls_reloc = true;
12184
0
        default:
12185
0
          break;
12186
0
        }
12187
0
    }
12188
3.35k
        fixP = fix_new_exp (frag_now, p - frag_now->fr_literal,
12189
3.35k
          size, i.op[n].disps, pcrel,
12190
3.35k
          reloc_type);
12191
12192
3.35k
        if (flag_code == CODE_64BIT && size == 4 && pcrel
12193
3.35k
      && !i.prefix[ADDR_PREFIX])
12194
0
    fixP->fx_signed = 1;
12195
12196
3.35k
        if (reloc_type == BFD_RELOC_X86_64_GOTTPOFF
12197
3.35k
      && i.tm.opcode_space == SPACE_EVEXMAP4)
12198
0
    {
12199
      /* Only "add %reg1, foo@gottpoff(%rip), %reg2" is
12200
         allowed in md_assemble.  Set fx_tcbit2 for EVEX
12201
         prefix.  */
12202
0
      fixP->fx_tcbit2 = 1;
12203
0
      continue;
12204
0
    }
12205
12206
3.35k
        if (i.base_reg && i.base_reg->reg_num == RegIP)
12207
0
    {
12208
0
      if (reloc_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC)
12209
0
        {
12210
          /* Set fx_tcbit for REX2 prefix.  */
12211
0
          if (is_apx_rex2_encoding ())
12212
0
      fixP->fx_tcbit = 1;
12213
0
          continue;
12214
0
        }
12215
0
    }
12216
        /* In 64-bit, i386_validate_fix updates only (%rip)
12217
     relocations.  */
12218
3.35k
        else if (object_64bit)
12219
3.35k
    continue;
12220
12221
        /* Check for "call/jmp *mem", "mov mem, %reg",
12222
     "test %reg, mem" and "binop mem, %reg" where binop
12223
     is one of adc, add, and, cmp, or, sbb, sub, xor
12224
     instructions without data prefix.  Always generate
12225
     R_386_GOT32X for "sym*GOT" operand in 32-bit mode.  */
12226
0
        if (i.prefix[DATA_PREFIX] == 0
12227
0
      && (i.rm.mode == 2
12228
0
          || (i.rm.mode == 0 && i.rm.regmem == 5))
12229
0
      && i.tm.opcode_space == SPACE_BASE
12230
0
      && ((i.operands == 1
12231
0
           && i.tm.base_opcode == 0xff
12232
0
           && (i.rm.reg == 2 || i.rm.reg == 4))
12233
0
          || (i.operands == 2
12234
0
        && (i.tm.base_opcode == 0x8b
12235
0
            || i.tm.base_opcode == 0x85
12236
0
            || (i.tm.base_opcode & ~0x38) == 0x03))))
12237
0
    {
12238
0
      if (object_64bit)
12239
0
        {
12240
0
          if (reloc_type == BFD_RELOC_X86_64_GOTTPOFF)
12241
0
      {
12242
        /* Set fx_tcbit for REX2 prefix.  */
12243
0
        if (is_apx_rex2_encoding ())
12244
0
          fixP->fx_tcbit = 1;
12245
0
      }
12246
0
          else if (generate_relax_relocations)
12247
0
      {
12248
        /* Set fx_tcbit3 for REX2 prefix.  */
12249
0
        if (is_apx_rex2_encoding ())
12250
0
          fixP->fx_tcbit3 = 1;
12251
0
        else if (i.rex)
12252
0
          fixP->fx_tcbit2 = 1;
12253
0
        else
12254
0
          fixP->fx_tcbit = 1;
12255
0
      }
12256
0
        }
12257
0
      else if (generate_relax_relocations
12258
0
         || (i.rm.mode == 0 && i.rm.regmem == 5))
12259
0
        fixP->fx_tcbit2 = 1;
12260
0
    }
12261
0
      }
12262
18.2k
  }
12263
33.2k
    }
12264
18.2k
}
12265
12266
static void
12267
output_imm (fragS *insn_start_frag, offsetT insn_start_off)
12268
15.3k
{
12269
15.3k
  char *p;
12270
15.3k
  unsigned int n;
12271
12272
45.8k
  for (n = 0; n < i.operands; n++)
12273
30.5k
    {
12274
30.5k
      if (operand_type_check (i.types[n], imm))
12275
15.3k
  {
12276
15.3k
    int size = imm_size (n);
12277
12278
15.3k
    if (now_seg == absolute_section)
12279
2.71k
      abs_section_offset += size;
12280
12.6k
    else if (i.op[n].imms->X_op == O_constant)
12281
9.75k
      {
12282
9.75k
        offsetT val;
12283
12284
9.75k
        val = offset_in_range (i.op[n].imms->X_add_number,
12285
9.75k
             size);
12286
9.75k
        p = frag_more (size);
12287
9.75k
        md_number_to_chars (p, val, size);
12288
9.75k
      }
12289
2.92k
    else
12290
2.92k
      {
12291
        /* Not absolute_section.
12292
     Need a 32-bit fixup (don't support 8bit
12293
     non-absolute imms).  Try to support other
12294
     sizes ...  */
12295
2.92k
        enum bfd_reloc_code_real reloc_type;
12296
2.92k
        int sign;
12297
12298
2.92k
        if (i.types[n].bitfield.imm32s
12299
2.92k
      && (i.suffix == QWORD_MNEM_SUFFIX
12300
0
          || (!i.suffix && i.tm.opcode_modifier.no_lsuf)
12301
0
          || (i.prefix[REX_PREFIX] & REX_W)
12302
0
          || dot_insn ()))
12303
0
    sign = 1;
12304
2.92k
        else
12305
2.92k
    sign = 0;
12306
12307
2.92k
        p = frag_more (size);
12308
2.92k
        reloc_type = reloc (size, 0, sign, i.reloc[n]);
12309
12310
        /*   This is tough to explain.  We end up with this one if we
12311
         * have operands that look like
12312
         * "_GLOBAL_OFFSET_TABLE_+[.-.L284]".  The goal here is to
12313
         * obtain the absolute address of the GOT, and it is strongly
12314
         * preferable from a performance point of view to avoid using
12315
         * a runtime relocation for this.  The actual sequence of
12316
         * instructions often look something like:
12317
         *
12318
         *  call  .L66
12319
         * .L66:
12320
         *  popl  %ebx
12321
         *  addl  $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
12322
         *
12323
         *   The call and pop essentially return the absolute address
12324
         * of the label .L66 and store it in %ebx.  The linker itself
12325
         * will ultimately change the first operand of the addl so
12326
         * that %ebx points to the GOT, but to keep things simple, the
12327
         * .o file must have this operand set so that it generates not
12328
         * the absolute address of .L66, but the absolute address of
12329
         * itself.  This allows the linker itself simply treat a GOTPC
12330
         * relocation as asking for a pcrel offset to the GOT to be
12331
         * added in, and the addend of the relocation is stored in the
12332
         * operand field for the instruction itself.
12333
         *
12334
         *   Our job here is to fix the operand so that it would add
12335
         * the correct offset so that %ebx would point to itself.  The
12336
         * thing that is tricky is that .-.L66 will point to the
12337
         * beginning of the instruction, so we need to further modify
12338
         * the operand so that it will point to itself.  There are
12339
         * other cases where you have something like:
12340
         *
12341
         *  .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
12342
         *
12343
         * and here no correction would be required.  Internally in
12344
         * the assembler we treat operands of this form as not being
12345
         * pcrel since the '.' is explicitly mentioned, and I wonder
12346
         * whether it would simplify matters to do it this way.  Who
12347
         * knows.  In earlier versions of the PIC patches, the
12348
         * pcrel_adjust field was used to store the correction, but
12349
         * since the expression is not pcrel, I felt it would be
12350
         * confusing to do it this way.  */
12351
12352
2.92k
        if ((reloc_type == BFD_RELOC_32
12353
2.92k
       || reloc_type == BFD_RELOC_X86_64_32S
12354
2.92k
       || reloc_type == BFD_RELOC_64)
12355
2.92k
      && GOT_symbol
12356
2.92k
      && GOT_symbol == i.op[n].imms->X_add_symbol
12357
2.92k
      && (i.op[n].imms->X_op == O_symbol
12358
0
          || (i.op[n].imms->X_op == O_add
12359
0
        && ((symbol_get_value_expression
12360
0
             (i.op[n].imms->X_op_symbol)->X_op)
12361
0
            == O_subtract))))
12362
0
    {
12363
0
      if (!object_64bit)
12364
0
        reloc_type = BFD_RELOC_386_GOTPC;
12365
0
      else if (size == 4)
12366
0
        reloc_type = BFD_RELOC_X86_64_GOTPC32;
12367
0
      else if (size == 8)
12368
0
        reloc_type = BFD_RELOC_X86_64_GOTPC64;
12369
0
      i.has_gotpc_tls_reloc = true;
12370
0
      i.op[n].imms->X_add_number +=
12371
0
        encoding_length (insn_start_frag, insn_start_off, p);
12372
0
    }
12373
2.92k
        fix_new_exp (frag_now, p - frag_now->fr_literal, size,
12374
2.92k
         i.op[n].imms, 0, reloc_type);
12375
2.92k
      }
12376
15.3k
  }
12377
30.5k
    }
12378
15.3k
}
12379

12380
/* x86_cons_fix_new is called via the expression parsing code when a
12381
   reloc is needed.  We use this hook to get the correct .got reloc.  */
12382
static int cons_sign = -1;
12383
12384
void
12385
x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
12386
      expressionS *exp, bfd_reloc_code_real_type r)
12387
147k
{
12388
147k
  r = reloc (len, 0, cons_sign, r);
12389
12390
#ifdef TE_PE
12391
  if (exp->X_op == O_secrel)
12392
    {
12393
      exp->X_op = O_symbol;
12394
      r = BFD_RELOC_32_SECREL;
12395
    }
12396
  else if (exp->X_op == O_secidx)
12397
    r = BFD_RELOC_16_SECIDX;
12398
#endif
12399
12400
147k
  fix_new_exp (frag, off, len, exp, 0, r);
12401
147k
}
12402
12403
/* Export the ABI address size for use by TC_ADDRESS_BYTES for the
12404
   purpose of the `.dc.a' internal pseudo-op.  */
12405
12406
int
12407
x86_address_bytes (void)
12408
0
{
12409
0
  if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
12410
0
    return 4;
12411
0
  return stdoutput->arch_info->bits_per_address / 8;
12412
0
}
12413
12414
#if (!(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
12415
     || defined (LEX_AT)) && !defined (TE_PE)
12416
# define lex_got(reloc, adjust, types) NULL
12417
#else
12418
/* Parse operands of the form
12419
   <symbol>@GOTOFF+<nnn>
12420
   and similar .plt or .got references.
12421
12422
   If we find one, set up the correct relocation in RELOC and copy the
12423
   input string, minus the `@GOTOFF' into a malloc'd buffer for
12424
   parsing by the calling routine.  Return this buffer, and if ADJUST
12425
   is non-null set it to the length of the string we removed from the
12426
   input line.  Otherwise return NULL.  */
12427
static char *
12428
lex_got (enum bfd_reloc_code_real *rel,
12429
   int *adjust,
12430
   i386_operand_type *types)
12431
162k
{
12432
  /* Some of the relocations depend on the size of what field is to
12433
     be relocated.  But in our callers i386_immediate and i386_displacement
12434
     we don't yet know the operand size (this will be set by insn
12435
     matching).  Hence we record the word32 relocation here,
12436
     and adjust the reloc according to the real size in reloc().  */
12437
162k
  static const struct
12438
162k
  {
12439
162k
    const char *str;
12440
162k
    int len;
12441
162k
    const enum bfd_reloc_code_real rel[2];
12442
162k
    const i386_operand_type types64;
12443
162k
    bool need_GOT_symbol;
12444
162k
  }
12445
162k
    gotrel[] =
12446
162k
  {
12447
12448
1.14M
#define OPERAND_TYPE_IMM32_32S_DISP32 { .bitfield = \
12449
1.14M
  { .imm32 = 1, .imm32s = 1, .disp32 = 1 } }
12450
162k
#define OPERAND_TYPE_IMM32_32S_64_DISP32 { .bitfield = \
12451
162k
  { .imm32 = 1, .imm32s = 1, .imm64 = 1, .disp32 = 1 } }
12452
325k
#define OPERAND_TYPE_IMM32_32S_64_DISP32_64 { .bitfield = \
12453
325k
  { .imm32 = 1, .imm32s = 1, .imm64 = 1, .disp32 = 1, .disp64 = 1 } }
12454
325k
#define OPERAND_TYPE_IMM64_DISP64 { .bitfield = \
12455
325k
  { .imm64 = 1, .disp64 = 1 } }
12456
12457
162k
#ifndef TE_PE
12458
162k
#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12459
162k
    { STRING_COMMA_LEN ("SIZE"),      { BFD_RELOC_SIZE32,
12460
162k
          BFD_RELOC_SIZE32 },
12461
162k
      { .bitfield = { .imm32 = 1, .imm64 = 1 } }, false },
12462
162k
#endif
12463
162k
    { STRING_COMMA_LEN ("PLTOFF"),   { _dummy_first_bfd_reloc_code_real,
12464
162k
               BFD_RELOC_X86_64_PLTOFF64 },
12465
162k
      { .bitfield = { .imm64 = 1 } }, true },
12466
162k
    { STRING_COMMA_LEN ("PLT"),      { BFD_RELOC_386_PLT32,
12467
162k
               BFD_RELOC_X86_64_PLT32    },
12468
162k
      OPERAND_TYPE_IMM32_32S_DISP32, false },
12469
162k
    { STRING_COMMA_LEN ("GOTPLT"),   { _dummy_first_bfd_reloc_code_real,
12470
162k
               BFD_RELOC_X86_64_GOTPLT64 },
12471
162k
      OPERAND_TYPE_IMM64_DISP64, true },
12472
162k
    { STRING_COMMA_LEN ("GOTOFF"),   { BFD_RELOC_386_GOTOFF,
12473
162k
               BFD_RELOC_X86_64_GOTOFF64 },
12474
162k
      OPERAND_TYPE_IMM64_DISP64, true },
12475
162k
    { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
12476
162k
               BFD_RELOC_X86_64_GOTPCREL },
12477
162k
      OPERAND_TYPE_IMM32_32S_DISP32, true },
12478
162k
    { STRING_COMMA_LEN ("TLSGD"),    { BFD_RELOC_386_TLS_GD,
12479
162k
               BFD_RELOC_X86_64_TLSGD    },
12480
162k
      OPERAND_TYPE_IMM32_32S_DISP32, true },
12481
162k
    { STRING_COMMA_LEN ("TLSLDM"),   { BFD_RELOC_386_TLS_LDM,
12482
162k
               _dummy_first_bfd_reloc_code_real },
12483
162k
      OPERAND_TYPE_NONE, true },
12484
162k
    { STRING_COMMA_LEN ("TLSLD"),    { _dummy_first_bfd_reloc_code_real,
12485
162k
               BFD_RELOC_X86_64_TLSLD    },
12486
162k
      OPERAND_TYPE_IMM32_32S_DISP32, true },
12487
162k
    { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
12488
162k
               BFD_RELOC_X86_64_GOTTPOFF },
12489
162k
      OPERAND_TYPE_IMM32_32S_DISP32, true },
12490
162k
    { STRING_COMMA_LEN ("TPOFF"),    { BFD_RELOC_386_TLS_LE_32,
12491
162k
               BFD_RELOC_X86_64_TPOFF32  },
12492
162k
      OPERAND_TYPE_IMM32_32S_64_DISP32_64, true },
12493
162k
    { STRING_COMMA_LEN ("NTPOFF"),   { BFD_RELOC_386_TLS_LE,
12494
162k
               _dummy_first_bfd_reloc_code_real },
12495
162k
      OPERAND_TYPE_NONE, true },
12496
162k
    { STRING_COMMA_LEN ("DTPOFF"),   { BFD_RELOC_386_TLS_LDO_32,
12497
162k
               BFD_RELOC_X86_64_DTPOFF32 },
12498
162k
      OPERAND_TYPE_IMM32_32S_64_DISP32_64, true },
12499
162k
    { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
12500
162k
               _dummy_first_bfd_reloc_code_real },
12501
162k
      OPERAND_TYPE_NONE, true },
12502
162k
    { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
12503
162k
               _dummy_first_bfd_reloc_code_real },
12504
162k
      OPERAND_TYPE_NONE, true },
12505
162k
    { STRING_COMMA_LEN ("GOT"),      { BFD_RELOC_386_GOT32,
12506
162k
               BFD_RELOC_X86_64_GOT32    },
12507
162k
      OPERAND_TYPE_IMM32_32S_64_DISP32, true },
12508
162k
    { STRING_COMMA_LEN ("TLSDESC"),  { BFD_RELOC_386_TLS_GOTDESC,
12509
162k
               BFD_RELOC_X86_64_GOTPC32_TLSDESC },
12510
162k
      OPERAND_TYPE_IMM32_32S_DISP32, true },
12511
162k
    { STRING_COMMA_LEN ("TLSCALL"),  { BFD_RELOC_386_TLS_DESC_CALL,
12512
162k
               BFD_RELOC_X86_64_TLSDESC_CALL },
12513
162k
      OPERAND_TYPE_IMM32_32S_DISP32, true },
12514
#else /* TE_PE */
12515
    { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
12516
               BFD_RELOC_32_SECREL },
12517
      OPERAND_TYPE_IMM32_32S_64_DISP32_64, false },
12518
#endif
12519
12520
162k
#undef OPERAND_TYPE_IMM32_32S_DISP32
12521
162k
#undef OPERAND_TYPE_IMM32_32S_64_DISP32
12522
162k
#undef OPERAND_TYPE_IMM32_32S_64_DISP32_64
12523
162k
#undef OPERAND_TYPE_IMM64_DISP64
12524
12525
162k
  };
12526
162k
  char *cp;
12527
162k
  unsigned int j;
12528
12529
#if defined (OBJ_MAYBE_ELF) && !defined (TE_PE)
12530
  if (!IS_ELF)
12531
    return NULL;
12532
#endif
12533
12534
2.77M
  for (cp = input_line_pointer; *cp != '@'; cp++)
12535
2.76M
    if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
12536
144k
      return NULL;
12537
12538
178k
  for (j = 0; j < ARRAY_SIZE (gotrel); j++)
12539
173k
    {
12540
173k
      int len = gotrel[j].len;
12541
173k
      if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
12542
12.7k
  {
12543
12.7k
    if (gotrel[j].rel[object_64bit] != 0)
12544
12.7k
      {
12545
12.7k
        int first, second;
12546
12.7k
        char *tmpbuf, *past_reloc;
12547
12548
12.7k
        *rel = gotrel[j].rel[object_64bit];
12549
12550
12.7k
        if (types)
12551
9.65k
    {
12552
9.65k
      if (flag_code != CODE_64BIT)
12553
8.29k
        {
12554
8.29k
          types->bitfield.imm32 = 1;
12555
8.29k
          types->bitfield.disp32 = 1;
12556
8.29k
        }
12557
1.35k
      else
12558
1.35k
        *types = gotrel[j].types64;
12559
9.65k
    }
12560
12561
12.7k
        if (gotrel[j].need_GOT_symbol && GOT_symbol == NULL)
12562
1
    GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
12563
12564
        /* The length of the first part of our input line.  */
12565
12.7k
        first = cp - input_line_pointer;
12566
12567
        /* The second part goes from after the reloc token until
12568
     (and including) an end_of_line char or comma.  */
12569
12.7k
        past_reloc = cp + 1 + len;
12570
12.7k
        cp = past_reloc;
12571
120k
        while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
12572
108k
    ++cp;
12573
12.7k
        second = cp + 1 - past_reloc;
12574
12575
        /* Allocate and copy string.  The trailing NUL shouldn't
12576
     be necessary, but be safe.  */
12577
12.7k
        tmpbuf = XNEWVEC (char, first + second + 2);
12578
12.7k
        memcpy (tmpbuf, input_line_pointer, first);
12579
12.7k
        if (second != 0 && *past_reloc != ' ')
12580
    /* Replace the relocation token with ' ', so that
12581
       errors like foo@GOTOFF1 will be detected.  */
12582
12.7k
    tmpbuf[first++] = ' ';
12583
1
        else
12584
    /* Increment length by 1 if the relocation token is
12585
       removed.  */
12586
1
    len++;
12587
12.7k
        if (adjust)
12588
3.12k
    *adjust = len;
12589
12.7k
        memcpy (tmpbuf + first, past_reloc, second);
12590
12.7k
        tmpbuf[first + second] = '\0';
12591
12.7k
        return tmpbuf;
12592
12.7k
      }
12593
12594
14
    as_bad (_("@%s reloc is not supported with %d-bit output format"),
12595
14
      gotrel[j].str, 1 << (5 + object_64bit));
12596
14
    return NULL;
12597
12.7k
  }
12598
173k
    }
12599
12600
  /* Might be a symbol version string.  Don't as_bad here.  */
12601
5.28k
  return NULL;
12602
18.0k
}
12603
#endif
12604
12605
bfd_reloc_code_real_type
12606
x86_cons (expressionS *exp, int size)
12607
66.7k
{
12608
66.7k
  bfd_reloc_code_real_type got_reloc = NO_RELOC;
12609
12610
66.7k
  intel_syntax = -intel_syntax;
12611
66.7k
  exp->X_md = 0;
12612
66.7k
  expr_mode = expr_operator_none;
12613
12614
66.7k
#if ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
12615
66.7k
      && !defined (LEX_AT)) \
12616
66.7k
    || defined (TE_PE)
12617
66.7k
  if (size == 4 || (object_64bit && size == 8))
12618
66.5k
    {
12619
      /* Handle @GOTOFF and the like in an expression.  */
12620
66.5k
      char *save;
12621
66.5k
      char *gotfree_input_line;
12622
66.5k
      int adjust = 0;
12623
12624
66.5k
      save = input_line_pointer;
12625
66.5k
      gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
12626
66.5k
      if (gotfree_input_line)
12627
3.12k
  input_line_pointer = gotfree_input_line;
12628
12629
66.5k
      expression (exp);
12630
12631
66.5k
      if (gotfree_input_line)
12632
3.12k
  {
12633
    /* expression () has merrily parsed up to the end of line,
12634
       or a comma - in the wrong buffer.  Transfer how far
12635
       input_line_pointer has moved to the right buffer.  */
12636
3.12k
    input_line_pointer = (save
12637
3.12k
        + (input_line_pointer - gotfree_input_line)
12638
3.12k
        + adjust);
12639
3.12k
    free (gotfree_input_line);
12640
3.12k
    if (exp->X_op == O_constant
12641
3.12k
        || exp->X_op == O_absent
12642
3.12k
        || exp->X_op == O_illegal
12643
3.12k
        || exp->X_op == O_register
12644
3.12k
        || exp->X_op == O_big)
12645
1.25k
      {
12646
1.25k
        char c = *input_line_pointer;
12647
1.25k
        *input_line_pointer = 0;
12648
1.25k
        as_bad (_("missing or invalid expression `%s'"), save);
12649
1.25k
        *input_line_pointer = c;
12650
1.25k
      }
12651
1.87k
    else if ((got_reloc == BFD_RELOC_386_PLT32
12652
1.87k
        || got_reloc == BFD_RELOC_X86_64_PLT32)
12653
1.87k
       && exp->X_op != O_symbol)
12654
0
      {
12655
0
        char c = *input_line_pointer;
12656
0
        *input_line_pointer = 0;
12657
0
        as_bad (_("invalid PLT expression `%s'"), save);
12658
0
        *input_line_pointer = c;
12659
0
      }
12660
3.12k
  }
12661
66.5k
    }
12662
197
  else
12663
197
#endif
12664
197
    expression (exp);
12665
12666
66.7k
  intel_syntax = -intel_syntax;
12667
12668
66.7k
  if (intel_syntax)
12669
0
    i386_intel_simplify (exp);
12670
12671
  /* If not 64bit, massage value, to account for wraparound when !BFD64.  */
12672
66.7k
  if (size <= 4 && expr_mode == expr_operator_present
12673
66.7k
      && exp->X_op == O_constant && !object_64bit)
12674
0
    exp->X_add_number = extend_to_32bit_address (exp->X_add_number);
12675
12676
66.7k
  return got_reloc;
12677
66.7k
}
12678
12679
static void
12680
signed_cons (int size)
12681
8
{
12682
8
  if (object_64bit)
12683
8
    cons_sign = 1;
12684
8
  cons (size);
12685
8
  cons_sign = -1;
12686
8
}
12687
12688
static void
12689
s_insn (int dummy ATTRIBUTE_UNUSED)
12690
66
{
12691
66
  char mnemonic[MAX_MNEM_SIZE], *line = input_line_pointer, *ptr;
12692
66
  char *saved_ilp = find_end_of_line (line, false), saved_char;
12693
66
  const char *end;
12694
66
  unsigned int j;
12695
66
  valueT val;
12696
66
  bool vex = false, xop = false, evex = false;
12697
66
  struct last_insn *last_insn;
12698
12699
66
  init_globals ();
12700
12701
66
  saved_char = *saved_ilp;
12702
66
  *saved_ilp = 0;
12703
12704
66
  end = parse_insn (line, mnemonic, true);
12705
66
  if (end == NULL)
12706
0
    {
12707
0
  bad:
12708
0
      *saved_ilp = saved_char;
12709
0
      ignore_rest_of_line ();
12710
0
      i.tm.mnem_off = 0;
12711
0
      return;
12712
0
    }
12713
66
  line += end - line;
12714
12715
66
  current_templates.start = &i.tm;
12716
66
  current_templates.end = &i.tm + 1;
12717
66
  i.tm.mnem_off = MN__insn;
12718
66
  i.tm.extension_opcode = None;
12719
12720
66
  if (startswith (line, "VEX")
12721
66
      && (line[3] == '.' || is_space_char (line[3])))
12722
0
    {
12723
0
      vex = true;
12724
0
      line += 3;
12725
0
    }
12726
66
  else if (startswith (line, "XOP") && ISDIGIT (line[3]))
12727
0
    {
12728
0
      char *e;
12729
0
      unsigned long n = strtoul (line + 3, &e, 16);
12730
12731
0
      if (e == line + 5 && n >= 0x08 && n <= 0x1f
12732
0
    && (*e == '.' || is_space_char (*e)))
12733
0
  {
12734
0
    xop = true;
12735
    /* Arrange for build_vex_prefix() to emit 0x8f.  */
12736
0
    i.tm.opcode_space = SPACE_XOP08;
12737
0
    i.insn_opcode_space = n;
12738
0
    line = e;
12739
0
  }
12740
0
    }
12741
66
  else if (startswith (line, "EVEX")
12742
66
     && (line[4] == '.' || is_space_char (line[4])))
12743
0
    {
12744
0
      evex = true;
12745
0
      line += 4;
12746
0
    }
12747
12748
66
  if (vex || xop
12749
66
      ? i.encoding == encoding_evex
12750
66
      : evex
12751
66
  ? i.encoding == encoding_vex
12752
0
    || i.encoding == encoding_vex3
12753
66
  : i.encoding != encoding_default)
12754
0
    {
12755
0
      as_bad (_("pseudo-prefix conflicts with encoding specifier"));
12756
0
      goto bad;
12757
0
    }
12758
12759
66
  if (line > end && i.encoding == encoding_default)
12760
0
    i.encoding = evex ? encoding_evex : encoding_vex;
12761
12762
66
  if (i.encoding != encoding_default)
12763
0
    {
12764
      /* Only address size and segment override prefixes are permitted with
12765
         VEX/XOP/EVEX encodings.  */
12766
0
      const unsigned char *p = i.prefix;
12767
12768
0
      for (j = 0; j < ARRAY_SIZE (i.prefix); ++j, ++p)
12769
0
  {
12770
0
    if (!*p)
12771
0
      continue;
12772
12773
0
    switch (j)
12774
0
      {
12775
0
      case SEG_PREFIX:
12776
0
      case ADDR_PREFIX:
12777
0
        break;
12778
0
      default:
12779
0
      as_bad (_("illegal prefix used with VEX/XOP/EVEX"));
12780
0
      goto bad;
12781
0
      }
12782
0
  }
12783
0
    }
12784
12785
66
  if (line > end && *line == '.')
12786
0
    {
12787
      /* Length specifier (VEX.L, XOP.L, EVEX.L'L).  */
12788
0
      switch (line[1])
12789
0
  {
12790
0
  case 'L':
12791
0
    switch (line[2])
12792
0
      {
12793
0
      case '0':
12794
0
        if (evex)
12795
0
    i.tm.opcode_modifier.evex = EVEX128;
12796
0
        else
12797
0
    i.tm.opcode_modifier.vex = VEX128;
12798
0
        break;
12799
12800
0
      case '1':
12801
0
        if (evex)
12802
0
    i.tm.opcode_modifier.evex = EVEX256;
12803
0
        else
12804
0
    i.tm.opcode_modifier.vex = VEX256;
12805
0
        break;
12806
12807
0
      case '2':
12808
0
        if (evex)
12809
0
    i.tm.opcode_modifier.evex = EVEX512;
12810
0
        break;
12811
12812
0
      case '3':
12813
0
        if (evex)
12814
0
    i.tm.opcode_modifier.evex = EVEX_L3;
12815
0
        break;
12816
12817
0
      case 'I':
12818
0
        if (line[3] == 'G')
12819
0
    {
12820
0
      if (evex)
12821
0
        i.tm.opcode_modifier.evex = EVEXLIG;
12822
0
      else
12823
0
        i.tm.opcode_modifier.vex = VEXScalar; /* LIG */
12824
0
      ++line;
12825
0
    }
12826
0
        break;
12827
0
      }
12828
12829
0
    if (i.tm.opcode_modifier.vex || i.tm.opcode_modifier.evex)
12830
0
      line += 3;
12831
0
    break;
12832
12833
0
  case '1':
12834
0
    if (line[2] == '2' && line[3] == '8')
12835
0
      {
12836
0
        if (evex)
12837
0
    i.tm.opcode_modifier.evex = EVEX128;
12838
0
        else
12839
0
    i.tm.opcode_modifier.vex = VEX128;
12840
0
        line += 4;
12841
0
      }
12842
0
    break;
12843
12844
0
  case '2':
12845
0
    if (line[2] == '5' && line[3] == '6')
12846
0
      {
12847
0
        if (evex)
12848
0
    i.tm.opcode_modifier.evex = EVEX256;
12849
0
        else
12850
0
    i.tm.opcode_modifier.vex = VEX256;
12851
0
        line += 4;
12852
0
      }
12853
0
    break;
12854
12855
0
  case '5':
12856
0
    if (evex && line[2] == '1' && line[3] == '2')
12857
0
      {
12858
0
        i.tm.opcode_modifier.evex = EVEX512;
12859
0
        line += 4;
12860
0
      }
12861
0
    break;
12862
0
  }
12863
0
    }
12864
12865
66
  if (line > end && *line == '.')
12866
0
    {
12867
      /* embedded prefix (VEX.pp, XOP.pp, EVEX.pp).  */
12868
0
      switch (line[1])
12869
0
  {
12870
0
  case 'N':
12871
0
    if (line[2] == 'P')
12872
0
      line += 3;
12873
0
    break;
12874
12875
0
  case '6':
12876
0
    if (line[2] == '6')
12877
0
      {
12878
0
        i.tm.opcode_modifier.opcodeprefix = PREFIX_0X66;
12879
0
        line += 3;
12880
0
      }
12881
0
    break;
12882
12883
0
  case 'F': case 'f':
12884
0
    if (line[2] == '3')
12885
0
      {
12886
0
        i.tm.opcode_modifier.opcodeprefix = PREFIX_0XF3;
12887
0
        line += 3;
12888
0
      }
12889
0
    else if (line[2] == '2')
12890
0
      {
12891
0
        i.tm.opcode_modifier.opcodeprefix = PREFIX_0XF2;
12892
0
        line += 3;
12893
0
      }
12894
0
    break;
12895
0
  }
12896
0
    }
12897
12898
66
  if (line > end && !xop && *line == '.')
12899
0
    {
12900
      /* Encoding space (VEX.mmmmm, EVEX.mmmm).  */
12901
0
      switch (line[1])
12902
0
  {
12903
0
  case '0':
12904
0
    if (TOUPPER (line[2]) != 'F')
12905
0
      break;
12906
0
    if (line[3] == '.' || is_space_char (line[3]))
12907
0
      {
12908
0
        i.insn_opcode_space = SPACE_0F;
12909
0
        line += 3;
12910
0
      }
12911
0
    else if (line[3] == '3'
12912
0
       && (line[4] == '8' || TOUPPER (line[4]) == 'A')
12913
0
       && (line[5] == '.' || is_space_char (line[5])))
12914
0
      {
12915
0
        i.insn_opcode_space = line[4] == '8' ? SPACE_0F38 : SPACE_0F3A;
12916
0
        line += 5;
12917
0
      }
12918
0
    break;
12919
12920
0
  case 'M':
12921
0
    if (ISDIGIT (line[2]) && line[2] != '0')
12922
0
      {
12923
0
        char *e;
12924
0
        unsigned long n = strtoul (line + 2, &e, 10);
12925
12926
0
        if (n <= (evex ? 15 : 31)
12927
0
      && (*e == '.' || is_space_char (*e)))
12928
0
    {
12929
0
      i.insn_opcode_space = n;
12930
0
      line = e;
12931
0
    }
12932
0
      }
12933
0
    break;
12934
0
  }
12935
0
    }
12936
12937
66
  if (line > end && *line == '.' && line[1] == 'W')
12938
0
    {
12939
      /* VEX.W, XOP.W, EVEX.W  */
12940
0
      switch (line[2])
12941
0
  {
12942
0
  case '0':
12943
0
    i.tm.opcode_modifier.vexw = VEXW0;
12944
0
    break;
12945
12946
0
  case '1':
12947
0
    i.tm.opcode_modifier.vexw = VEXW1;
12948
0
    break;
12949
12950
0
  case 'I':
12951
0
    if (line[3] == 'G')
12952
0
      {
12953
0
        i.tm.opcode_modifier.vexw = VEXWIG;
12954
0
        ++line;
12955
0
      }
12956
0
    break;
12957
0
  }
12958
12959
0
      if (i.tm.opcode_modifier.vexw)
12960
0
  line += 3;
12961
0
    }
12962
12963
66
  if (line > end && *line && !is_space_char (*line))
12964
0
    {
12965
      /* Improve diagnostic a little.  */
12966
0
      if (*line == '.' && line[1] && !is_space_char (line[1]))
12967
0
  ++line;
12968
0
      goto done;
12969
0
    }
12970
12971
  /* Before processing the opcode expression, find trailing "+r" or
12972
     "/<digit>" specifiers.  */
12973
66
  for (ptr = line; ; ++ptr)
12974
119
    {
12975
119
      unsigned long n;
12976
119
      char *e;
12977
12978
119
      ptr = strpbrk (ptr, "+/,");
12979
119
      if (ptr == NULL || *ptr == ',')
12980
66
  break;
12981
12982
53
      if (*ptr == '+' && ptr[1] == 'r'
12983
53
    && (ptr[2] == ',' || (is_space_char (ptr[2]) && ptr[3] == ',')))
12984
0
  {
12985
0
    *ptr = ' ';
12986
0
    ptr[1] = ' ';
12987
0
    i.short_form = true;
12988
0
    break;
12989
0
  }
12990
12991
53
      if (*ptr == '/' && ISDIGIT (ptr[1])
12992
53
    && (n = strtoul (ptr + 1, &e, 8)) < 8
12993
53
    && e == ptr + 2
12994
53
    && (ptr[2] == ',' || (is_space_char (ptr[2]) && ptr[3] == ',')))
12995
0
  {
12996
0
    *ptr = ' ';
12997
0
    ptr[1] = ' ';
12998
0
    i.tm.extension_opcode = n;
12999
0
    i.tm.opcode_modifier.modrm = 1;
13000
0
    break;
13001
0
  }
13002
53
    }
13003
13004
66
  input_line_pointer = line;
13005
66
  val = get_absolute_expression ();
13006
66
  line = input_line_pointer;
13007
13008
66
  if (i.short_form && (val & 7))
13009
0
    as_warn ("`+r' assumes low three opcode bits to be clear");
13010
13011
66
  for (j = 1; j < sizeof(val); ++j)
13012
66
    if (!(val >> (j * 8)))
13013
66
      break;
13014
13015
  /* Trim off a prefix if present.  */
13016
66
  if (j > 1 && !vex && !xop && !evex)
13017
0
    {
13018
0
      uint8_t byte = val >> ((j - 1) * 8);
13019
13020
0
      switch (byte)
13021
0
  {
13022
0
  case DATA_PREFIX_OPCODE:
13023
0
  case REPE_PREFIX_OPCODE:
13024
0
  case REPNE_PREFIX_OPCODE:
13025
0
    if (!add_prefix (byte))
13026
0
      goto bad;
13027
0
    val &= ((uint64_t)1 << (--j * 8)) - 1;
13028
0
    break;
13029
0
  }
13030
0
    }
13031
13032
  /* Parse operands, if any, before evaluating encoding space.  */
13033
66
  if (*line == ',')
13034
1
    {
13035
1
      i.memshift = -1;
13036
13037
1
      ptr = parse_operands (line + 1, &i386_mnemonics[MN__insn]);
13038
1
      this_operand = -1;
13039
1
      if (!ptr)
13040
0
  goto bad;
13041
1
      line = ptr;
13042
13043
1
      if (!i.operands)
13044
0
  {
13045
0
    as_bad (_("expecting operand after ','; got nothing"));
13046
0
    goto done;
13047
0
  }
13048
13049
1
      if (i.mem_operands > 1)
13050
0
  {
13051
0
    as_bad (_("too many memory references for `%s'"),
13052
0
      &i386_mnemonics[MN__insn]);
13053
0
    goto done;
13054
0
  }
13055
13056
      /* No need to distinguish encoding_evex and encoding_evex512.  */
13057
1
      if (i.encoding == encoding_evex512)
13058
0
  i.encoding = encoding_evex;
13059
1
    }
13060
13061
  /* Trim off encoding space.  */
13062
66
  if (j > 1 && !i.insn_opcode_space && (val >> ((j - 1) * 8)) == 0x0f)
13063
0
    {
13064
0
      uint8_t byte = val >> ((--j - 1) * 8);
13065
13066
0
      i.insn_opcode_space = SPACE_0F;
13067
0
      switch (byte & -(j > 1 && !i.rex2_encoding
13068
0
           && (i.encoding != encoding_egpr || evex)))
13069
0
  {
13070
0
  case 0x38:
13071
0
    i.insn_opcode_space = SPACE_0F38;
13072
0
    --j;
13073
0
    break;
13074
0
  case 0x3a:
13075
0
    i.insn_opcode_space = SPACE_0F3A;
13076
0
    --j;
13077
0
    break;
13078
0
  }
13079
0
      i.tm.opcode_space = i.insn_opcode_space;
13080
0
      val &= ((uint64_t)1 << (j * 8)) - 1;
13081
0
    }
13082
66
  if (!i.tm.opcode_space && (vex || evex))
13083
    /* Arrange for build_vex_prefix() to properly emit 0xC4/0xC5.
13084
       Also avoid hitting abort() there or in build_evex_prefix().  */
13085
0
    i.tm.opcode_space = i.insn_opcode_space == SPACE_0F ? SPACE_0F
13086
0
               : SPACE_0F38;
13087
13088
66
  if (j > 2)
13089
0
    {
13090
0
      as_bad (_("opcode residual (%#"PRIx64") too wide"), (uint64_t) val);
13091
0
      goto done;
13092
0
    }
13093
66
  i.opcode_length = j;
13094
13095
  /* Handle operands, if any.  */
13096
66
  if (i.operands)
13097
1
    {
13098
1
      i386_operand_type combined;
13099
1
      expressionS *disp_exp = NULL;
13100
1
      bool changed;
13101
13102
1
      if (i.encoding == encoding_egpr)
13103
0
  {
13104
0
    if (vex || xop)
13105
0
      {
13106
0
        as_bad (_("eGPR use conflicts with encoding specifier"));
13107
0
        goto done;
13108
0
      }
13109
0
    if (evex)
13110
0
      i.encoding = encoding_evex;
13111
0
    else
13112
0
      i.encoding = encoding_default;
13113
0
  }
13114
13115
      /* Are we to emit ModR/M encoding?  */
13116
1
      if (!i.short_form
13117
1
    && (i.mem_operands
13118
1
        || i.reg_operands > (i.encoding != encoding_default)
13119
1
        || i.tm.extension_opcode != None))
13120
1
  i.tm.opcode_modifier.modrm = 1;
13121
13122
1
      if (!i.tm.opcode_modifier.modrm
13123
1
    && (i.reg_operands
13124
0
        > i.short_form + 0U + (i.encoding != encoding_default)
13125
0
        || i.mem_operands))
13126
0
  {
13127
0
    as_bad (_("too many register/memory operands"));
13128
0
    goto done;
13129
0
  }
13130
13131
      /* Enforce certain constraints on operands.  */
13132
1
      switch (i.reg_operands + i.mem_operands
13133
1
        + (i.tm.extension_opcode != None))
13134
1
  {
13135
0
  case 0:
13136
0
    if (i.short_form)
13137
0
      {
13138
0
        as_bad (_("too few register/memory operands"));
13139
0
        goto done;
13140
0
      }
13141
    /* Fall through.  */
13142
1
  case 1:
13143
1
    if (i.tm.opcode_modifier.modrm)
13144
1
      {
13145
1
        as_bad (_("too few register/memory operands"));
13146
1
        goto done;
13147
1
      }
13148
0
    break;
13149
13150
0
  case 2:
13151
0
    break;
13152
13153
0
  case 4:
13154
0
    if (i.imm_operands
13155
0
        && (i.op[0].imms->X_op != O_constant
13156
0
      || !fits_in_imm4 (i.op[0].imms->X_add_number)))
13157
0
      {
13158
0
        as_bad (_("constant doesn't fit in %d bits"), evex ? 3 : 4);
13159
0
        goto done;
13160
0
      }
13161
    /* Fall through.  */
13162
0
  case 3:
13163
0
    if (i.encoding != encoding_default)
13164
0
      {
13165
0
        i.tm.opcode_modifier.vexvvvv = VexVVVV_SRC1;
13166
0
        break;
13167
0
      }
13168
    /* Fall through.  */
13169
0
  default:
13170
0
    as_bad (_("too many register/memory operands"));
13171
0
    goto done;
13172
1
  }
13173
13174
      /* Bring operands into canonical order (imm, mem, reg).  */
13175
0
      do
13176
0
  {
13177
0
    changed = false;
13178
13179
0
    for (j = 1; j < i.operands; ++j)
13180
0
      {
13181
0
        if ((!operand_type_check (i.types[j - 1], imm)
13182
0
       && operand_type_check (i.types[j], imm))
13183
0
      || (i.types[j - 1].bitfield.class != ClassNone
13184
0
          && i.types[j].bitfield.class == ClassNone))
13185
0
    {
13186
0
      swap_2_operands (j - 1, j);
13187
0
      changed = true;
13188
0
    }
13189
0
      }
13190
0
  }
13191
0
      while (changed);
13192
13193
      /* For Intel syntax swap the order of register operands.  */
13194
0
      if (intel_syntax)
13195
0
  switch (i.reg_operands)
13196
0
    {
13197
0
    case 0:
13198
0
    case 1:
13199
0
      break;
13200
13201
0
    case 4:
13202
0
      swap_2_operands (i.imm_operands + i.mem_operands + 1, i.operands - 2);
13203
      /* Fall through.  */
13204
0
    case 3:
13205
0
    case 2:
13206
0
      swap_2_operands (i.imm_operands + i.mem_operands, i.operands - 1);
13207
0
      break;
13208
13209
0
    default:
13210
0
      abort ();
13211
0
    }
13212
13213
      /* Enforce constraints when using VSIB.  */
13214
0
      if (i.index_reg
13215
0
    && (i.index_reg->reg_type.bitfield.xmmword
13216
0
        || i.index_reg->reg_type.bitfield.ymmword
13217
0
        || i.index_reg->reg_type.bitfield.zmmword))
13218
0
  {
13219
0
    if (i.encoding == encoding_default)
13220
0
      {
13221
0
        as_bad (_("VSIB unavailable with legacy encoding"));
13222
0
        goto done;
13223
0
      }
13224
13225
0
    if (i.encoding == encoding_evex
13226
0
        && i.reg_operands > 1)
13227
0
      {
13228
        /* We could allow two register operands, encoding the 2nd one in
13229
     an 8-bit immediate like for 4-register-operand insns, but that
13230
     would require ugly fiddling with process_operands() and/or
13231
     build_modrm_byte().  */
13232
0
        as_bad (_("too many register operands with VSIB"));
13233
0
        goto done;
13234
0
      }
13235
13236
0
    i.tm.opcode_modifier.sib = 1;
13237
0
  }
13238
13239
      /* Establish operand size encoding.  */
13240
0
      operand_type_set (&combined, 0);
13241
13242
0
      for (j = i.imm_operands; j < i.operands; ++j)
13243
0
  {
13244
    /* Look for 8-bit operands that use old registers.  */
13245
0
    if (i.encoding != encoding_default
13246
0
        && flag_code == CODE_64BIT
13247
0
        && i.types[j].bitfield.class == Reg
13248
0
        && i.types[j].bitfield.byte
13249
0
        && !(i.op[j].regs->reg_flags & RegRex64)
13250
0
        && i.op[j].regs->reg_num > 3)
13251
0
      as_bad (_("can't encode register '%s%s' with VEX/XOP/EVEX"),
13252
0
        register_prefix, i.op[j].regs->reg_name);
13253
13254
0
    i.types[j].bitfield.instance = InstanceNone;
13255
13256
0
    if (operand_type_check (i.types[j], disp))
13257
0
      {
13258
0
        i.types[j].bitfield.baseindex = 1;
13259
0
        disp_exp = i.op[j].disps;
13260
0
      }
13261
13262
0
    if (evex && i.types[j].bitfield.baseindex)
13263
0
      {
13264
0
        unsigned int n = i.memshift;
13265
13266
0
        if (i.types[j].bitfield.byte)
13267
0
    n = 0;
13268
0
        else if (i.types[j].bitfield.word)
13269
0
    n = 1;
13270
0
        else if (i.types[j].bitfield.dword)
13271
0
    n = 2;
13272
0
        else if (i.types[j].bitfield.qword)
13273
0
    n = 3;
13274
0
        else if (i.types[j].bitfield.xmmword)
13275
0
    n = 4;
13276
0
        else if (i.types[j].bitfield.ymmword)
13277
0
    n = 5;
13278
0
        else if (i.types[j].bitfield.zmmword)
13279
0
    n = 6;
13280
13281
0
        if (i.memshift < 32 && n != i.memshift)
13282
0
    as_warn ("conflicting memory operand size specifiers");
13283
0
        i.memshift = n;
13284
0
      }
13285
13286
0
    if ((i.broadcast.type || i.broadcast.bytes)
13287
0
        && j == i.broadcast.operand)
13288
0
      continue;
13289
13290
0
    combined = operand_type_or (combined, i.types[j]);
13291
0
    combined.bitfield.class = ClassNone;
13292
0
  }
13293
13294
0
      switch ((i.broadcast.type ? i.broadcast.type : 1)
13295
0
        << (i.memshift < 32 ? i.memshift : 0))
13296
0
  {
13297
0
  case 64: combined.bitfield.zmmword = 1; break;
13298
0
  case 32: combined.bitfield.ymmword = 1; break;
13299
0
  case 16: combined.bitfield.xmmword = 1; break;
13300
0
  case  8: combined.bitfield.qword = 1; break;
13301
0
  case  4: combined.bitfield.dword = 1; break;
13302
0
  }
13303
13304
0
      if (i.encoding == encoding_default)
13305
0
  {
13306
0
    if (flag_code == CODE_64BIT && combined.bitfield.qword)
13307
0
      i.rex |= REX_W;
13308
0
    else if ((flag_code == CODE_16BIT ? combined.bitfield.dword
13309
0
              : combined.bitfield.word)
13310
0
             && !add_prefix (DATA_PREFIX_OPCODE))
13311
0
      goto done;
13312
0
  }
13313
0
      else if (!i.tm.opcode_modifier.vexw)
13314
0
  {
13315
0
    if (flag_code == CODE_64BIT)
13316
0
      {
13317
0
        if (combined.bitfield.qword)
13318
0
          i.tm.opcode_modifier.vexw = VEXW1;
13319
0
        else if (combined.bitfield.dword)
13320
0
          i.tm.opcode_modifier.vexw = VEXW0;
13321
0
      }
13322
13323
0
    if (!i.tm.opcode_modifier.vexw)
13324
0
      i.tm.opcode_modifier.vexw = VEXWIG;
13325
0
  }
13326
13327
0
      if (vex || xop)
13328
0
  {
13329
0
    if (!i.tm.opcode_modifier.vex)
13330
0
      {
13331
0
        if (combined.bitfield.ymmword)
13332
0
          i.tm.opcode_modifier.vex = VEX256;
13333
0
        else if (combined.bitfield.xmmword)
13334
0
          i.tm.opcode_modifier.vex = VEX128;
13335
0
      }
13336
0
  }
13337
0
      else if (evex)
13338
0
  {
13339
0
    if (!i.tm.opcode_modifier.evex)
13340
0
      {
13341
        /* Do _not_ consider AVX512VL here.  */
13342
0
        if (i.rounding.type != rc_none || combined.bitfield.zmmword)
13343
0
          i.tm.opcode_modifier.evex = EVEX512;
13344
0
        else if (combined.bitfield.ymmword)
13345
0
          i.tm.opcode_modifier.evex = EVEX256;
13346
0
        else if (combined.bitfield.xmmword)
13347
0
          i.tm.opcode_modifier.evex = EVEX128;
13348
0
      }
13349
13350
0
    if (i.memshift >= 32)
13351
0
      {
13352
0
        unsigned int n = 0;
13353
13354
0
        switch (i.tm.opcode_modifier.evex)
13355
0
    {
13356
0
    case EVEX512: n = 64; break;
13357
0
    case EVEX256: n = 32; break;
13358
0
    case EVEX128: n = 16; break;
13359
0
    }
13360
13361
0
        if (i.broadcast.type)
13362
0
    n /= i.broadcast.type;
13363
13364
0
        if (n > 0)
13365
0
    for (i.memshift = 0; !(n & 1); n >>= 1)
13366
0
      ++i.memshift;
13367
0
        else if (disp_exp != NULL && disp_exp->X_op == O_constant
13368
0
           && disp_exp->X_add_number != 0
13369
0
           && i.disp_encoding != disp_encoding_32bit)
13370
0
    {
13371
0
      if (!quiet_warnings)
13372
0
        as_warn ("cannot determine memory operand size");
13373
0
      i.disp_encoding = disp_encoding_32bit;
13374
0
    }
13375
0
      }
13376
0
  }
13377
13378
0
      if (i.memshift >= 32)
13379
0
  i.memshift = 0;
13380
0
      else if (!evex)
13381
0
  i.encoding = encoding_error;
13382
13383
0
      if (i.disp_operands && !optimize_disp (&i.tm))
13384
0
  goto done;
13385
13386
      /* Establish size for immediate operands.  */
13387
0
      for (j = 0; j < i.imm_operands; ++j)
13388
0
  {
13389
0
    expressionS *expP = i.op[j].imms;
13390
13391
0
    gas_assert (operand_type_check (i.types[j], imm));
13392
0
    operand_type_set (&i.types[j], 0);
13393
13394
0
    if (i.imm_bits[j] > 32)
13395
0
      i.types[j].bitfield.imm64 = 1;
13396
0
    else if (i.imm_bits[j] > 16)
13397
0
      {
13398
0
        if (flag_code == CODE_64BIT && (i.flags[j] & Operand_Signed))
13399
0
    i.types[j].bitfield.imm32s = 1;
13400
0
        else
13401
0
    i.types[j].bitfield.imm32 = 1;
13402
0
      }
13403
0
    else if (i.imm_bits[j] > 8)
13404
0
      i.types[j].bitfield.imm16 = 1;
13405
0
    else if (i.imm_bits[j] > 0)
13406
0
      {
13407
0
        if (i.flags[j] & Operand_Signed)
13408
0
    i.types[j].bitfield.imm8s = 1;
13409
0
        else
13410
0
    i.types[j].bitfield.imm8 = 1;
13411
0
      }
13412
0
    else if (expP->X_op == O_constant)
13413
0
      {
13414
0
        i.types[j] = smallest_imm_type (expP->X_add_number);
13415
0
        i.types[j].bitfield.imm1 = 0;
13416
        /* Oddly enough imm_size() checks imm64 first, so the bit needs
13417
     zapping since smallest_imm_type() sets it unconditionally.  */
13418
0
        if (flag_code != CODE_64BIT)
13419
0
    {
13420
0
      i.types[j].bitfield.imm64 = 0;
13421
0
      i.types[j].bitfield.imm32s = 0;
13422
0
      i.types[j].bitfield.imm32 = 1;
13423
0
    }
13424
0
        else if (i.types[j].bitfield.imm32 || i.types[j].bitfield.imm32s)
13425
0
    i.types[j].bitfield.imm64 = 0;
13426
0
      }
13427
0
    else
13428
      /* Non-constant expressions are sized heuristically.  */
13429
0
      switch (flag_code)
13430
0
        {
13431
0
        case CODE_64BIT: i.types[j].bitfield.imm32s = 1; break;
13432
0
        case CODE_32BIT: i.types[j].bitfield.imm32 = 1; break;
13433
0
        case CODE_16BIT: i.types[j].bitfield.imm16 = 1; break;
13434
0
        }
13435
0
  }
13436
13437
0
      for (j = 0; j < i.operands; ++j)
13438
0
  i.tm.operand_types[j] = i.types[j];
13439
13440
0
      process_operands ();
13441
0
    }
13442
13443
  /* Don't set opcode until after processing operands, to avoid any
13444
     potential special casing there.  */
13445
65
  i.tm.base_opcode |= val;
13446
13447
65
  if (i.encoding == encoding_error
13448
65
      || (i.encoding != encoding_evex
13449
65
    ? i.broadcast.type || i.broadcast.bytes
13450
65
      || i.rounding.type != rc_none
13451
65
      || i.mask.reg
13452
65
    : (i.mem_operands && i.rounding.type != rc_none)
13453
0
      || ((i.broadcast.type || i.broadcast.bytes)
13454
0
    && !(i.flags[i.broadcast.operand] & Operand_Mem))))
13455
0
    {
13456
0
      as_bad (_("conflicting .insn operands"));
13457
0
      goto done;
13458
0
    }
13459
13460
65
  if (vex || xop)
13461
0
    {
13462
0
      if (!i.tm.opcode_modifier.vex)
13463
0
  i.tm.opcode_modifier.vex = VEXScalar; /* LIG */
13464
13465
0
      build_vex_prefix (NULL);
13466
0
      i.rex &= REX_OPCODE;
13467
0
    }
13468
65
  else if (evex)
13469
0
    {
13470
0
      if (!i.tm.opcode_modifier.evex)
13471
0
  i.tm.opcode_modifier.evex = EVEXLIG;
13472
13473
0
      build_evex_prefix ();
13474
0
      i.rex &= REX_OPCODE;
13475
0
    }
13476
65
  else
13477
65
    establish_rex ();
13478
13479
65
  last_insn = &seg_info(now_seg)->tc_segment_info_data.last_insn;
13480
65
  output_insn (last_insn);
13481
65
  last_insn->kind = last_insn_directive;
13482
65
  last_insn->name = ".insn directive";
13483
65
  last_insn->file = as_where (&last_insn->line);
13484
13485
65
#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
13486
  /* PS: SCFI is enabled only for System V AMD64 ABI.  The ABI check has been
13487
     performed in i386_target_format.  */
13488
65
  if (IS_ELF && flag_synth_cfi)
13489
0
    as_bad (_("SCFI: hand-crafting instructions not supported"));
13490
65
#endif
13491
13492
66
 done:
13493
66
  *saved_ilp = saved_char;
13494
66
  input_line_pointer = line;
13495
13496
66
  demand_empty_rest_of_line ();
13497
13498
  /* Make sure dot_insn() won't yield "true" anymore.  */
13499
66
  i.tm.mnem_off = 0;
13500
66
}
13501
13502
#ifdef TE_PE
13503
static void
13504
pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
13505
{
13506
  expressionS exp;
13507
13508
  do
13509
    {
13510
      expression (&exp);
13511
      if (exp.X_op == O_symbol)
13512
  exp.X_op = O_secrel;
13513
13514
      emit_expr (&exp, 4);
13515
    }
13516
  while (*input_line_pointer++ == ',');
13517
13518
  input_line_pointer--;
13519
  demand_empty_rest_of_line ();
13520
}
13521
13522
static void
13523
pe_directive_secidx (int dummy ATTRIBUTE_UNUSED)
13524
{
13525
  expressionS exp;
13526
13527
  do
13528
    {
13529
      expression (&exp);
13530
      if (exp.X_op == O_symbol)
13531
  exp.X_op = O_secidx;
13532
13533
      emit_expr (&exp, 2);
13534
    }
13535
  while (*input_line_pointer++ == ',');
13536
13537
  input_line_pointer--;
13538
  demand_empty_rest_of_line ();
13539
}
13540
#endif
13541
13542
/* Handle Rounding Control / SAE specifiers.  */
13543
13544
static char *
13545
RC_SAE_specifier (const char *pstr)
13546
25
{
13547
25
  unsigned int j;
13548
13549
145
  for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++)
13550
121
    {
13551
121
      if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len))
13552
1
  {
13553
1
    if (i.rounding.type != rc_none)
13554
0
      {
13555
0
        as_bad (_("duplicated `{%s}'"), RC_NamesTable[j].name);
13556
0
        return NULL;
13557
0
      }
13558
13559
1
    switch (i.encoding)
13560
1
      {
13561
1
      case encoding_default:
13562
1
      case encoding_egpr:
13563
1
        i.encoding = encoding_evex512;
13564
1
        break;
13565
0
      case encoding_evex:
13566
0
      case encoding_evex512:
13567
0
        break;
13568
0
      default:
13569
0
        return NULL;
13570
1
      }
13571
13572
1
    i.rounding.type = RC_NamesTable[j].type;
13573
13574
1
    return (char *)(pstr + RC_NamesTable[j].len);
13575
1
  }
13576
121
    }
13577
13578
24
  return NULL;
13579
25
}
13580
13581
/* Handle Vector operations.  */
13582
13583
static char *
13584
check_VecOperations (char *op_string)
13585
2
{
13586
2
  const reg_entry *mask;
13587
2
  const char *saved;
13588
2
  char *end_op;
13589
13590
2
  while (*op_string)
13591
2
    {
13592
2
      saved = op_string;
13593
2
      if (*op_string == '{')
13594
2
  {
13595
2
    op_string++;
13596
13597
    /* Check broadcasts.  */
13598
2
    if (startswith (op_string, "1to"))
13599
0
      {
13600
0
        unsigned int bcst_type;
13601
13602
0
        if (i.broadcast.type)
13603
0
    goto duplicated_vec_op;
13604
13605
0
        op_string += 3;
13606
0
        if (*op_string == '8')
13607
0
    bcst_type = 8;
13608
0
        else if (*op_string == '4')
13609
0
    bcst_type = 4;
13610
0
        else if (*op_string == '2')
13611
0
    bcst_type = 2;
13612
0
        else if (*op_string == '1'
13613
0
           && *(op_string+1) == '6')
13614
0
    {
13615
0
      bcst_type = 16;
13616
0
      op_string++;
13617
0
    }
13618
0
        else if (*op_string == '3'
13619
0
           && *(op_string+1) == '2')
13620
0
    {
13621
0
      bcst_type = 32;
13622
0
      op_string++;
13623
0
    }
13624
0
        else
13625
0
    {
13626
0
      as_bad (_("Unsupported broadcast: `%s'"), saved);
13627
0
      return NULL;
13628
0
    }
13629
0
        op_string++;
13630
13631
0
        switch (i.encoding)
13632
0
    {
13633
0
    case encoding_default:
13634
0
    case encoding_egpr:
13635
0
      i.encoding = encoding_evex;
13636
0
      break;
13637
0
    case encoding_evex:
13638
0
    case encoding_evex512:
13639
0
      break;
13640
0
    default:
13641
0
      goto unknown_vec_op;
13642
0
    }
13643
13644
0
        i.broadcast.type = bcst_type;
13645
0
        i.broadcast.operand = this_operand;
13646
13647
        /* For .insn a data size specifier may be appended.  */
13648
0
        if (dot_insn () && *op_string == ':')
13649
0
    goto dot_insn_modifier;
13650
0
      }
13651
    /* Check .insn special cases.  */
13652
2
    else if (dot_insn () && *op_string == ':')
13653
0
      {
13654
0
      dot_insn_modifier:
13655
0
        switch (op_string[1])
13656
0
    {
13657
0
      unsigned long n;
13658
13659
0
    case 'd':
13660
0
      if (i.memshift < 32)
13661
0
        goto duplicated_vec_op;
13662
13663
0
      n = strtoul (op_string + 2, &end_op, 0);
13664
0
      if (n)
13665
0
        for (i.memshift = 0; !(n & 1); n >>= 1)
13666
0
          ++i.memshift;
13667
0
      if (i.memshift < 32 && n == 1)
13668
0
        op_string = end_op;
13669
0
      break;
13670
13671
0
    case 's': case 'u':
13672
      /* This isn't really a "vector" operation, but a sign/size
13673
         specifier for immediate operands of .insn.  Note that AT&T
13674
         syntax handles the same in i386_immediate().  */
13675
0
      if (!intel_syntax)
13676
0
        break;
13677
13678
0
      if (i.imm_bits[this_operand])
13679
0
        goto duplicated_vec_op;
13680
13681
0
      n = strtoul (op_string + 2, &end_op, 0);
13682
0
      if (n && n <= (flag_code == CODE_64BIT ? 64 : 32))
13683
0
        {
13684
0
          i.imm_bits[this_operand] = n;
13685
0
          if (op_string[1] == 's')
13686
0
      i.flags[this_operand] |= Operand_Signed;
13687
0
          op_string = end_op;
13688
0
        }
13689
0
      break;
13690
0
    }
13691
0
      }
13692
    /* Check masking operation.  */
13693
2
    else if ((mask = parse_register (op_string, &end_op)) != NULL)
13694
0
      {
13695
0
        if (mask == &bad_reg)
13696
0
    return NULL;
13697
13698
        /* k0 can't be used for write mask.  */
13699
0
        if (mask->reg_type.bitfield.class != RegMask || !mask->reg_num)
13700
0
    {
13701
0
      as_bad (_("`%s%s' can't be used for write mask"),
13702
0
        register_prefix, mask->reg_name);
13703
0
      return NULL;
13704
0
    }
13705
13706
0
        if (!i.mask.reg)
13707
0
    {
13708
0
      i.mask.reg = mask;
13709
0
      i.mask.operand = this_operand;
13710
0
    }
13711
0
        else if (i.mask.reg->reg_num)
13712
0
    goto duplicated_vec_op;
13713
0
        else
13714
0
    {
13715
0
      i.mask.reg = mask;
13716
13717
      /* Only "{z}" is allowed here.  No need to check
13718
         zeroing mask explicitly.  */
13719
0
      if (i.mask.operand != (unsigned int) this_operand)
13720
0
        {
13721
0
          as_bad (_("invalid write mask `%s'"), saved);
13722
0
          return NULL;
13723
0
        }
13724
0
    }
13725
13726
0
        op_string = end_op;
13727
0
      }
13728
    /* Check zeroing-flag for masking operation.  */
13729
2
    else if (*op_string == 'z')
13730
0
      {
13731
0
        if (!i.mask.reg)
13732
0
    {
13733
0
      i.mask.reg = reg_k0;
13734
0
      i.mask.zeroing = 1;
13735
0
      i.mask.operand = this_operand;
13736
0
    }
13737
0
        else
13738
0
    {
13739
0
      if (i.mask.zeroing)
13740
0
        {
13741
0
        duplicated_vec_op:
13742
0
          as_bad (_("duplicated `%s'"), saved);
13743
0
          return NULL;
13744
0
        }
13745
13746
0
      i.mask.zeroing = 1;
13747
13748
      /* Only "{%k}" is allowed here.  No need to check mask
13749
         register explicitly.  */
13750
0
      if (i.mask.operand != (unsigned int) this_operand)
13751
0
        {
13752
0
          as_bad (_("invalid zeroing-masking `%s'"),
13753
0
            saved);
13754
0
          return NULL;
13755
0
        }
13756
0
    }
13757
13758
0
        op_string++;
13759
0
      }
13760
2
    else if (intel_syntax
13761
2
       && (op_string = RC_SAE_specifier (op_string)) != NULL)
13762
0
      i.rounding.modifier = true;
13763
2
    else
13764
2
      goto unknown_vec_op;
13765
13766
0
    if (*op_string != '}')
13767
0
      {
13768
0
        as_bad (_("missing `}' in `%s'"), saved);
13769
0
        return NULL;
13770
0
      }
13771
0
    op_string++;
13772
13773
    /* Strip whitespace since the addition of pseudo prefixes
13774
       changed how the scrubber treats '{'.  */
13775
0
    if (is_space_char (*op_string))
13776
0
      ++op_string;
13777
13778
0
    continue;
13779
0
  }
13780
2
    unknown_vec_op:
13781
      /* We don't know this one.  */
13782
2
      as_bad (_("unknown vector operation: `%s'"), saved);
13783
2
      return NULL;
13784
2
    }
13785
13786
0
  if (i.mask.reg && i.mask.zeroing && !i.mask.reg->reg_num)
13787
0
    {
13788
0
      as_bad (_("zeroing-masking only allowed with write mask"));
13789
0
      return NULL;
13790
0
    }
13791
13792
0
  return op_string;
13793
0
}
13794
13795
static int
13796
i386_immediate (char *imm_start)
13797
63.6k
{
13798
63.6k
  char *save_input_line_pointer;
13799
63.6k
  char *gotfree_input_line;
13800
63.6k
  segT exp_seg = 0;
13801
63.6k
  expressionS *exp;
13802
63.6k
  i386_operand_type types;
13803
13804
63.6k
  operand_type_set (&types, ~0);
13805
13806
63.6k
  if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
13807
177
    {
13808
177
      as_bad (_("at most %d immediate operands are allowed"),
13809
177
        MAX_IMMEDIATE_OPERANDS);
13810
177
      return 0;
13811
177
    }
13812
13813
63.4k
  exp = &im_expressions[i.imm_operands++];
13814
63.4k
  i.op[this_operand].imms = exp;
13815
13816
63.4k
  if (is_space_char (*imm_start))
13817
17
    ++imm_start;
13818
13819
63.4k
  save_input_line_pointer = input_line_pointer;
13820
63.4k
  input_line_pointer = imm_start;
13821
13822
63.4k
  gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
13823
63.4k
  if (gotfree_input_line)
13824
8.83k
    input_line_pointer = gotfree_input_line;
13825
13826
63.4k
  expr_mode = expr_operator_none;
13827
63.4k
  exp_seg = expression (exp);
13828
13829
  /* For .insn immediates there may be a size specifier.  */
13830
63.4k
  if (dot_insn () && *input_line_pointer == '{' && input_line_pointer[1] == ':'
13831
63.4k
      && (input_line_pointer[2] == 's' || input_line_pointer[2] == 'u'))
13832
0
    {
13833
0
      char *e;
13834
0
      unsigned long n = strtoul (input_line_pointer + 3, &e, 0);
13835
13836
0
      if (*e == '}' && n && n <= (flag_code == CODE_64BIT ? 64 : 32))
13837
0
  {
13838
0
    i.imm_bits[this_operand] = n;
13839
0
    if (input_line_pointer[2] == 's')
13840
0
      i.flags[this_operand] |= Operand_Signed;
13841
0
    input_line_pointer = e + 1;
13842
0
  }
13843
0
    }
13844
13845
63.4k
  SKIP_WHITESPACE ();
13846
63.4k
  if (*input_line_pointer)
13847
25.1k
    as_bad (_("junk `%s' after expression"), input_line_pointer);
13848
13849
63.4k
  input_line_pointer = save_input_line_pointer;
13850
63.4k
  if (gotfree_input_line)
13851
8.83k
    {
13852
8.83k
      free (gotfree_input_line);
13853
13854
8.83k
      if (exp->X_op == O_constant)
13855
8.72k
  exp->X_op = O_illegal;
13856
8.83k
    }
13857
13858
63.4k
  if (exp_seg == reg_section)
13859
139
    {
13860
139
      as_bad (_("illegal immediate register operand %s"), imm_start);
13861
139
      return 0;
13862
139
    }
13863
13864
63.2k
  return i386_finalize_immediate (exp_seg, exp, types, imm_start);
13865
63.4k
}
13866
13867
static int
13868
i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
13869
       i386_operand_type types, const char *imm_start)
13870
63.2k
{
13871
63.2k
  if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
13872
12.5k
    {
13873
12.5k
      if (imm_start)
13874
12.5k
  as_bad (_("missing or invalid immediate expression `%s'"),
13875
12.5k
    imm_start);
13876
12.5k
      return 0;
13877
12.5k
    }
13878
50.7k
  else if (exp->X_op == O_constant)
13879
42.2k
    {
13880
      /* Size it properly later.  */
13881
42.2k
      i.types[this_operand].bitfield.imm64 = 1;
13882
13883
      /* If not 64bit, sign/zero extend val, to account for wraparound
13884
   when !BFD64.  */
13885
42.2k
      if (expr_mode == expr_operator_present
13886
42.2k
    && flag_code != CODE_64BIT && !object_64bit)
13887
0
  exp->X_add_number = extend_to_32bit_address (exp->X_add_number);
13888
42.2k
    }
13889
#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
13890
  else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
13891
     && exp_seg != absolute_section
13892
     && exp_seg != text_section
13893
     && exp_seg != data_section
13894
     && exp_seg != bss_section
13895
     && exp_seg != undefined_section
13896
     && !bfd_is_com_section (exp_seg))
13897
    {
13898
      as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
13899
      return 0;
13900
    }
13901
#endif
13902
8.47k
  else
13903
8.47k
    {
13904
      /* This is an address.  The size of the address will be
13905
   determined later, depending on destination register,
13906
   suffix, or the default for the section.  */
13907
8.47k
      i.types[this_operand].bitfield.imm8 = 1;
13908
8.47k
      i.types[this_operand].bitfield.imm16 = 1;
13909
8.47k
      i.types[this_operand].bitfield.imm32 = 1;
13910
8.47k
      i.types[this_operand].bitfield.imm32s = 1;
13911
8.47k
      i.types[this_operand].bitfield.imm64 = 1;
13912
8.47k
      i.types[this_operand] = operand_type_and (i.types[this_operand],
13913
8.47k
            types);
13914
8.47k
    }
13915
13916
50.7k
  return 1;
13917
63.2k
}
13918
13919
static char *
13920
i386_scale (char *scale)
13921
47
{
13922
47
  offsetT val;
13923
47
  char *save = input_line_pointer;
13924
13925
47
  input_line_pointer = scale;
13926
47
  val = get_absolute_expression ();
13927
13928
47
  switch (val)
13929
47
    {
13930
33
    case 1:
13931
33
      i.log2_scale_factor = 0;
13932
33
      break;
13933
9
    case 2:
13934
9
      i.log2_scale_factor = 1;
13935
9
      break;
13936
0
    case 4:
13937
0
      i.log2_scale_factor = 2;
13938
0
      break;
13939
0
    case 8:
13940
0
      i.log2_scale_factor = 3;
13941
0
      break;
13942
5
    default:
13943
5
      {
13944
5
  char sep = *input_line_pointer;
13945
13946
5
  *input_line_pointer = '\0';
13947
5
  as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
13948
5
    scale);
13949
5
  *input_line_pointer = sep;
13950
5
  input_line_pointer = save;
13951
5
  return NULL;
13952
0
      }
13953
47
    }
13954
42
  if (i.log2_scale_factor != 0 && i.index_reg == 0)
13955
9
    {
13956
9
      as_warn (_("scale factor of %d without an index register"),
13957
9
         1 << i.log2_scale_factor);
13958
9
      i.log2_scale_factor = 0;
13959
9
    }
13960
42
  scale = input_line_pointer;
13961
42
  input_line_pointer = save;
13962
42
  return scale;
13963
47
}
13964
13965
static int
13966
i386_displacement (char *disp_start, char *disp_end)
13967
32.8k
{
13968
32.8k
  expressionS *exp;
13969
32.8k
  segT exp_seg = 0;
13970
32.8k
  char *save_input_line_pointer;
13971
32.8k
  char *gotfree_input_line;
13972
32.8k
  int override;
13973
32.8k
  i386_operand_type bigdisp, types = anydisp;
13974
32.8k
  int ret;
13975
13976
32.8k
  if (i.disp_operands == MAX_MEMORY_OPERANDS)
13977
0
    {
13978
0
      as_bad (_("at most %d displacement operands are allowed"),
13979
0
        MAX_MEMORY_OPERANDS);
13980
0
      return 0;
13981
0
    }
13982
13983
32.8k
  operand_type_set (&bigdisp, 0);
13984
32.8k
  if (i.jumpabsolute
13985
32.8k
      || i.types[this_operand].bitfield.baseindex
13986
32.8k
      || (current_templates.start->opcode_modifier.jump != JUMP
13987
32.4k
    && current_templates.start->opcode_modifier.jump != JUMP_DWORD))
13988
31.5k
    {
13989
31.5k
      i386_addressing_mode ();
13990
31.5k
      override = (i.prefix[ADDR_PREFIX] != 0);
13991
31.5k
      if (flag_code == CODE_64BIT)
13992
9.53k
  {
13993
9.53k
    bigdisp.bitfield.disp32 = 1;
13994
9.53k
    if (!override)
13995
9.53k
      bigdisp.bitfield.disp64 = 1;
13996
9.53k
  }
13997
21.9k
      else if ((flag_code == CODE_16BIT) ^ override)
13998
14.2k
    bigdisp.bitfield.disp16 = 1;
13999
7.72k
      else
14000
7.72k
    bigdisp.bitfield.disp32 = 1;
14001
31.5k
    }
14002
1.33k
  else
14003
1.33k
    {
14004
      /* For PC-relative branches, the width of the displacement may be
14005
   dependent upon data size, but is never dependent upon address size.
14006
   Also make sure to not unintentionally match against a non-PC-relative
14007
   branch template.  */
14008
1.33k
      const insn_template *t = current_templates.start;
14009
1.33k
      bool has_intel64 = false;
14010
14011
1.37k
      while (++t < current_templates.end)
14012
60
  {
14013
60
    if (t->opcode_modifier.jump
14014
60
        != current_templates.start->opcode_modifier.jump)
14015
20
      break;
14016
40
    if ((t->opcode_modifier.isa64 >= INTEL64))
14017
20
      has_intel64 = true;
14018
40
  }
14019
1.33k
      current_templates.end = t;
14020
14021
1.33k
      override = (i.prefix[DATA_PREFIX] != 0);
14022
1.33k
      if (flag_code == CODE_64BIT)
14023
893
  {
14024
893
    if ((override || i.suffix == WORD_MNEM_SUFFIX)
14025
893
        && (!intel64 || !has_intel64))
14026
262
      bigdisp.bitfield.disp16 = 1;
14027
631
    else
14028
631
      bigdisp.bitfield.disp32 = 1;
14029
893
  }
14030
439
      else
14031
439
  {
14032
439
    if (!override)
14033
439
      override = (i.suffix == (flag_code != CODE_16BIT
14034
439
             ? WORD_MNEM_SUFFIX
14035
439
             : LONG_MNEM_SUFFIX));
14036
439
    bigdisp.bitfield.disp32 = 1;
14037
439
    if ((flag_code == CODE_16BIT) ^ override)
14038
136
      {
14039
136
        bigdisp.bitfield.disp32 = 0;
14040
136
        bigdisp.bitfield.disp16 = 1;
14041
136
      }
14042
439
  }
14043
1.33k
    }
14044
32.8k
  i.types[this_operand] = operand_type_or (i.types[this_operand],
14045
32.8k
             bigdisp);
14046
14047
32.8k
  exp = &disp_expressions[i.disp_operands];
14048
32.8k
  i.op[this_operand].disps = exp;
14049
32.8k
  i.disp_operands++;
14050
32.8k
  save_input_line_pointer = input_line_pointer;
14051
32.8k
  input_line_pointer = disp_start;
14052
32.8k
  END_STRING_AND_SAVE (disp_end);
14053
14054
32.8k
#ifndef GCC_ASM_O_HACK
14055
32.8k
#define GCC_ASM_O_HACK 0
14056
32.8k
#endif
14057
#if GCC_ASM_O_HACK
14058
  END_STRING_AND_SAVE (disp_end + 1);
14059
  if (i.types[this_operand].bitfield.baseIndex
14060
      && displacement_string_end[-1] == '+')
14061
    {
14062
      /* This hack is to avoid a warning when using the "o"
14063
   constraint within gcc asm statements.
14064
   For instance:
14065
14066
   #define _set_tssldt_desc(n,addr,limit,type) \
14067
   __asm__ __volatile__ ( \
14068
   "movw %w2,%0\n\t" \
14069
   "movw %w1,2+%0\n\t" \
14070
   "rorl $16,%1\n\t" \
14071
   "movb %b1,4+%0\n\t" \
14072
   "movb %4,5+%0\n\t" \
14073
   "movb $0,6+%0\n\t" \
14074
   "movb %h1,7+%0\n\t" \
14075
   "rorl $16,%1" \
14076
   : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
14077
14078
   This works great except that the output assembler ends
14079
   up looking a bit weird if it turns out that there is
14080
   no offset.  You end up producing code that looks like:
14081
14082
   #APP
14083
   movw $235,(%eax)
14084
   movw %dx,2+(%eax)
14085
   rorl $16,%edx
14086
   movb %dl,4+(%eax)
14087
   movb $137,5+(%eax)
14088
   movb $0,6+(%eax)
14089
   movb %dh,7+(%eax)
14090
   rorl $16,%edx
14091
   #NO_APP
14092
14093
   So here we provide the missing zero.  */
14094
14095
      *displacement_string_end = '0';
14096
    }
14097
#endif
14098
32.8k
  gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
14099
32.8k
  if (gotfree_input_line)
14100
820
    input_line_pointer = gotfree_input_line;
14101
14102
32.8k
  expr_mode = expr_operator_none;
14103
32.8k
  exp_seg = expression (exp);
14104
14105
32.8k
  SKIP_WHITESPACE ();
14106
32.8k
  if (*input_line_pointer)
14107
13.6k
    as_bad (_("junk `%s' after expression"), input_line_pointer);
14108
#if GCC_ASM_O_HACK
14109
  RESTORE_END_STRING (disp_end + 1);
14110
#endif
14111
32.8k
  input_line_pointer = save_input_line_pointer;
14112
32.8k
  if (gotfree_input_line)
14113
820
    {
14114
820
      free (gotfree_input_line);
14115
14116
820
      if (exp->X_op == O_constant || exp->X_op == O_register)
14117
488
  exp->X_op = O_illegal;
14118
820
    }
14119
14120
32.8k
  ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
14121
14122
32.8k
  RESTORE_END_STRING (disp_end);
14123
14124
32.8k
  return ret;
14125
32.8k
}
14126
14127
static int
14128
i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
14129
          i386_operand_type types, const char *disp_start)
14130
32.8k
{
14131
32.8k
  int ret = 1;
14132
14133
  /* We do this to make sure that the section symbol is in
14134
     the symbol table.  We will ultimately change the relocation
14135
     to be relative to the beginning of the section.  */
14136
32.8k
  if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
14137
32.8k
      || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
14138
32.8k
      || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
14139
403
    {
14140
403
      if (exp->X_op != O_symbol)
14141
316
  goto inv_disp;
14142
14143
87
      if (S_IS_LOCAL (exp->X_add_symbol)
14144
87
    && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
14145
87
    && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
14146
0
  section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
14147
87
      exp->X_op = O_subtract;
14148
87
      exp->X_op_symbol = GOT_symbol;
14149
87
      if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
14150
30
  i.reloc[this_operand] = BFD_RELOC_32_PCREL;
14151
57
      else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
14152
57
  i.reloc[this_operand] = BFD_RELOC_64;
14153
0
      else
14154
0
  i.reloc[this_operand] = BFD_RELOC_32;
14155
87
    }
14156
14157
32.4k
  else if (exp->X_op == O_absent
14158
32.4k
     || exp->X_op == O_illegal
14159
32.4k
     || exp->X_op == O_big)
14160
2.38k
    {
14161
2.69k
    inv_disp:
14162
2.69k
      as_bad (_("missing or invalid displacement expression `%s'"),
14163
2.69k
        disp_start);
14164
2.69k
      ret = 0;
14165
2.69k
    }
14166
14167
30.0k
  else if (exp->X_op == O_constant)
14168
19.9k
    {
14169
      /* Sizing gets taken care of by optimize_disp().
14170
14171
   If not 64bit, sign/zero extend val, to account for wraparound
14172
   when !BFD64.  */
14173
19.9k
      if (expr_mode == expr_operator_present
14174
19.9k
    && flag_code != CODE_64BIT && !object_64bit)
14175
0
  exp->X_add_number = extend_to_32bit_address (exp->X_add_number);
14176
19.9k
    }
14177
14178
#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
14179
  else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
14180
     && exp_seg != absolute_section
14181
     && exp_seg != text_section
14182
     && exp_seg != data_section
14183
     && exp_seg != bss_section
14184
     && exp_seg != undefined_section
14185
     && !bfd_is_com_section (exp_seg))
14186
    {
14187
      as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
14188
      ret = 0;
14189
    }
14190
#endif
14191
14192
10.1k
  else if (current_templates.start->opcode_modifier.jump == JUMP_BYTE)
14193
0
    i.types[this_operand].bitfield.disp8 = 1;
14194
14195
  /* Check if this is a displacement only operand.  */
14196
32.8k
  if (!i.types[this_operand].bitfield.baseindex)
14197
32.8k
    i.types[this_operand] =
14198
32.8k
      operand_type_or (operand_type_and_not (i.types[this_operand], anydisp),
14199
32.8k
           operand_type_and (i.types[this_operand], types));
14200
14201
32.8k
  return ret;
14202
32.8k
}
14203
14204
/* Return the active addressing mode, taking address override and
14205
   registers forming the address into consideration.  Update the
14206
   address override prefix if necessary.  */
14207
14208
static enum flag_code
14209
i386_addressing_mode (void)
14210
61.6k
{
14211
61.6k
  enum flag_code addr_mode;
14212
14213
61.6k
  if (i.prefix[ADDR_PREFIX])
14214
0
    addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
14215
61.6k
  else if (flag_code == CODE_16BIT
14216
61.6k
     && is_cpu (current_templates.start, CpuMPX)
14217
     /* Avoid replacing the "16-bit addressing not allowed" diagnostic
14218
        from md_assemble() by "is not a valid base/index expression"
14219
        when there is a base and/or index.  */
14220
61.6k
     && !i.types[this_operand].bitfield.baseindex)
14221
0
    {
14222
      /* MPX insn memory operands with neither base nor index must be forced
14223
   to use 32-bit addressing in 16-bit mode.  */
14224
0
      addr_mode = CODE_32BIT;
14225
0
      i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
14226
0
      ++i.prefixes;
14227
0
      gas_assert (!i.types[this_operand].bitfield.disp16);
14228
0
      gas_assert (!i.types[this_operand].bitfield.disp32);
14229
0
    }
14230
61.6k
  else
14231
61.6k
    {
14232
61.6k
      addr_mode = flag_code;
14233
14234
61.6k
#if INFER_ADDR_PREFIX
14235
61.6k
      if (i.mem_operands == 0)
14236
56.5k
  {
14237
    /* Infer address prefix from the first memory operand.  */
14238
56.5k
    const reg_entry *addr_reg = i.base_reg;
14239
14240
56.5k
    if (addr_reg == NULL)
14241
56.5k
      addr_reg = i.index_reg;
14242
14243
56.5k
    if (addr_reg)
14244
0
      {
14245
0
        if (addr_reg->reg_type.bitfield.dword)
14246
0
    addr_mode = CODE_32BIT;
14247
0
        else if (flag_code != CODE_64BIT
14248
0
           && addr_reg->reg_type.bitfield.word)
14249
0
    addr_mode = CODE_16BIT;
14250
14251
0
        if (addr_mode != flag_code)
14252
0
    {
14253
0
      i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
14254
0
      i.prefixes += 1;
14255
      /* Change the size of any displacement too.  At most one
14256
         of Disp16 or Disp32 is set.
14257
         FIXME.  There doesn't seem to be any real need for
14258
         separate Disp16 and Disp32 flags.  The same goes for
14259
         Imm16 and Imm32.  Removing them would probably clean
14260
         up the code quite a lot.  */
14261
0
      if (flag_code != CODE_64BIT
14262
0
          && (i.types[this_operand].bitfield.disp16
14263
0
        || i.types[this_operand].bitfield.disp32))
14264
0
        {
14265
0
          static const i386_operand_type disp16_32 = {
14266
0
      .bitfield = { .disp16 = 1, .disp32 = 1 }
14267
0
          };
14268
14269
0
          i.types[this_operand]
14270
0
      = operand_type_xor (i.types[this_operand], disp16_32);
14271
0
        }
14272
0
    }
14273
0
      }
14274
56.5k
  }
14275
61.6k
#endif
14276
61.6k
    }
14277
14278
61.6k
  return addr_mode;
14279
61.6k
}
14280
14281
/* Make sure the memory operand we've been dealt is valid.
14282
   Return 1 on success, 0 on a failure.  */
14283
14284
static int
14285
i386_index_check (const char *operand_string)
14286
30.1k
{
14287
30.1k
  const char *kind = "base/index";
14288
30.1k
  enum flag_code addr_mode = i386_addressing_mode ();
14289
30.1k
  const insn_template *t = current_templates.end - 1;
14290
14291
30.1k
  if (t->opcode_modifier.isstring)
14292
67
    {
14293
      /* Memory operands of string insns are special in that they only allow
14294
   a single register (rDI, rSI, or rBX) as their memory address.  */
14295
67
      const reg_entry *expected_reg;
14296
67
      static const char di_si[][2][4] =
14297
67
  {
14298
67
    { "esi", "edi" },
14299
67
    { "si", "di" },
14300
67
    { "rsi", "rdi" }
14301
67
  };
14302
67
      static const char bx[][4] = { "ebx", "bx", "rbx" };
14303
14304
67
      kind = "string address";
14305
14306
67
      if (t->opcode_modifier.prefixok == PrefixRep)
14307
55
  {
14308
55
    int es_op = t->opcode_modifier.isstring - IS_STRING_ES_OP0;
14309
55
    int op = 0;
14310
14311
55
    if (!t->operand_types[0].bitfield.baseindex
14312
55
        || ((!i.mem_operands != !intel_syntax)
14313
11
      && t->operand_types[1].bitfield.baseindex))
14314
44
      op = 1;
14315
55
    expected_reg
14316
55
      = (const reg_entry *) str_hash_find (reg_hash,
14317
55
             di_si[addr_mode][op == es_op]);
14318
55
  }
14319
12
      else
14320
12
  expected_reg
14321
12
    = (const reg_entry *)str_hash_find (reg_hash, bx[addr_mode]);
14322
14323
67
      if (i.base_reg != expected_reg
14324
67
    || i.index_reg
14325
67
    || operand_type_check (i.types[this_operand], disp))
14326
67
  {
14327
    /* The second memory operand must have the same size as
14328
       the first one.  */
14329
67
    if (i.mem_operands
14330
67
        && i.base_reg
14331
67
        && !((addr_mode == CODE_64BIT
14332
0
        && i.base_reg->reg_type.bitfield.qword)
14333
0
       || (addr_mode == CODE_32BIT
14334
0
           ? i.base_reg->reg_type.bitfield.dword
14335
0
           : i.base_reg->reg_type.bitfield.word)))
14336
0
      goto bad_address;
14337
14338
67
    as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
14339
67
       operand_string,
14340
67
       intel_syntax ? '[' : '(',
14341
67
       register_prefix,
14342
67
       expected_reg->reg_name,
14343
67
       intel_syntax ? ']' : ')');
14344
67
    return 1;
14345
67
  }
14346
0
      else
14347
0
  return 1;
14348
14349
0
    bad_address:
14350
0
      as_bad (_("`%s' is not a valid %s expression"),
14351
0
        operand_string, kind);
14352
0
      return 0;
14353
67
    }
14354
30.0k
  else
14355
30.0k
    {
14356
30.0k
      t = current_templates.start;
14357
14358
30.0k
      if (addr_mode != CODE_16BIT)
14359
17.5k
  {
14360
    /* 32-bit/64-bit checks.  */
14361
17.5k
    if (i.disp_encoding == disp_encoding_16bit)
14362
0
      {
14363
0
      bad_disp:
14364
0
        as_bad (_("invalid `%s' prefix"),
14365
0
          addr_mode == CODE_16BIT ? "{disp32}" : "{disp16}");
14366
0
        return 0;
14367
0
      }
14368
14369
17.5k
    if ((i.base_reg
14370
17.5k
         && ((addr_mode == CODE_64BIT
14371
0
        ? !i.base_reg->reg_type.bitfield.qword
14372
0
        : !i.base_reg->reg_type.bitfield.dword)
14373
0
       || (i.index_reg && i.base_reg->reg_num == RegIP)
14374
0
       || i.base_reg->reg_num == RegIZ))
14375
17.5k
        || (i.index_reg
14376
17.5k
      && !i.index_reg->reg_type.bitfield.xmmword
14377
17.5k
      && !i.index_reg->reg_type.bitfield.ymmword
14378
17.5k
      && !i.index_reg->reg_type.bitfield.zmmword
14379
17.5k
      && ((addr_mode == CODE_64BIT
14380
0
           ? !i.index_reg->reg_type.bitfield.qword
14381
0
           : !i.index_reg->reg_type.bitfield.dword)
14382
0
          || !i.index_reg->reg_type.bitfield.baseindex)))
14383
0
      goto bad_address;
14384
14385
    /* bndmk, bndldx, bndstx and mandatory non-vector SIB have special restrictions. */
14386
17.5k
    if (t->mnem_off == MN_bndmk
14387
17.5k
        || t->mnem_off == MN_bndldx
14388
17.5k
        || t->mnem_off == MN_bndstx
14389
17.5k
        || t->opcode_modifier.sib == SIBMEM)
14390
0
      {
14391
        /* They cannot use RIP-relative addressing. */
14392
0
        if (i.base_reg && i.base_reg->reg_num == RegIP)
14393
0
    {
14394
0
      as_bad (_("`%s' cannot be used here"), operand_string);
14395
0
      return 0;
14396
0
    }
14397
14398
        /* bndldx and bndstx ignore their scale factor. */
14399
0
        if ((t->mnem_off == MN_bndldx || t->mnem_off == MN_bndstx)
14400
0
      && i.log2_scale_factor)
14401
0
    as_warn (_("register scaling is being ignored here"));
14402
0
      }
14403
17.5k
  }
14404
12.5k
      else
14405
12.5k
  {
14406
    /* 16-bit checks.  */
14407
12.5k
    if (i.disp_encoding == disp_encoding_32bit)
14408
0
      goto bad_disp;
14409
14410
12.5k
    if ((i.base_reg
14411
12.5k
         && (!i.base_reg->reg_type.bitfield.word
14412
0
       || !i.base_reg->reg_type.bitfield.baseindex))
14413
12.5k
        || (i.index_reg
14414
12.5k
      && (!i.index_reg->reg_type.bitfield.word
14415
0
          || !i.index_reg->reg_type.bitfield.baseindex
14416
0
          || !(i.base_reg
14417
0
         && i.base_reg->reg_num < 6
14418
0
         && i.index_reg->reg_num >= 6
14419
0
         && i.log2_scale_factor == 0))))
14420
0
      goto bad_address;
14421
12.5k
  }
14422
30.0k
    }
14423
30.0k
  return 1;
14424
30.1k
}
14425
14426
/* Handle vector immediates.  */
14427
14428
static int
14429
RC_SAE_immediate (const char *imm_start)
14430
33.1k
{
14431
33.1k
  const char *pstr = imm_start;
14432
14433
33.1k
  if (*pstr != '{')
14434
33.0k
    return 0;
14435
14436
25
  pstr = RC_SAE_specifier (pstr + 1);
14437
25
  if (pstr == NULL)
14438
24
    return 0;
14439
14440
1
  if (*pstr++ != '}')
14441
1
    {
14442
1
      as_bad (_("Missing '}': '%s'"), imm_start);
14443
1
      return 0;
14444
1
    }
14445
0
  /* RC/SAE immediate string should contain nothing more.  */;
14446
0
  if (*pstr != 0)
14447
0
    {
14448
0
      as_bad (_("Junk after '}': '%s'"), imm_start);
14449
0
      return 0;
14450
0
    }
14451
14452
  /* Internally this doesn't count as an operand.  */
14453
0
  --i.operands;
14454
14455
0
  return 1;
14456
0
}
14457
14458
static INLINE bool starts_memory_operand (char c)
14459
33.1k
{
14460
33.1k
  return ISDIGIT (c)
14461
33.1k
   || is_name_beginner (c)
14462
33.1k
   || strchr ("([\"+-!~", c);
14463
33.1k
}
14464
14465
/* Parse OPERAND_STRING into the i386_insn structure I.  Returns zero
14466
   on error.  */
14467
14468
static int
14469
i386_att_operand (char *operand_string)
14470
96.8k
{
14471
96.8k
  const reg_entry *r;
14472
96.8k
  char *end_op;
14473
96.8k
  char *op_string = operand_string;
14474
14475
96.8k
  if (is_space_char (*op_string))
14476
0
    ++op_string;
14477
14478
  /* We check for an absolute prefix (differentiating,
14479
     for example, 'jmp pc_relative_label' from 'jmp *absolute_label'.  */
14480
96.8k
  if (*op_string == ABSOLUTE_PREFIX
14481
96.8k
      && current_templates.start->opcode_modifier.jump)
14482
404
    {
14483
404
      ++op_string;
14484
404
      if (is_space_char (*op_string))
14485
0
  ++op_string;
14486
404
      i.jumpabsolute = true;
14487
404
    }
14488
14489
  /* Check if operand is a register.  */
14490
96.8k
  if ((r = parse_register (op_string, &end_op)) != NULL)
14491
65
    {
14492
65
      i386_operand_type temp;
14493
14494
65
      if (r == &bad_reg)
14495
0
  return 0;
14496
14497
      /* Check for a segment override by searching for ':' after a
14498
   segment register.  */
14499
65
      op_string = end_op;
14500
65
      if (is_space_char (*op_string))
14501
0
  ++op_string;
14502
65
      if (*op_string == ':' && r->reg_type.bitfield.class == SReg)
14503
0
  {
14504
0
    i.seg[i.mem_operands] = r;
14505
14506
    /* Skip the ':' and whitespace.  */
14507
0
    ++op_string;
14508
0
    if (is_space_char (*op_string))
14509
0
      ++op_string;
14510
14511
    /* Handle case of %es:*foo.  */
14512
0
    if (!i.jumpabsolute && *op_string == ABSOLUTE_PREFIX
14513
0
        && current_templates.start->opcode_modifier.jump)
14514
0
      {
14515
0
        ++op_string;
14516
0
        if (is_space_char (*op_string))
14517
0
    ++op_string;
14518
0
        i.jumpabsolute = true;
14519
0
      }
14520
14521
0
    if (!starts_memory_operand (*op_string))
14522
0
      {
14523
0
        as_bad (_("bad memory operand `%s'"), op_string);
14524
0
        return 0;
14525
0
      }
14526
0
    goto do_memory_reference;
14527
0
  }
14528
14529
      /* Handle vector operations.  */
14530
65
      if (*op_string == '{')
14531
0
  {
14532
0
    op_string = check_VecOperations (op_string);
14533
0
    if (op_string == NULL)
14534
0
      return 0;
14535
0
  }
14536
14537
65
      if (*op_string)
14538
5
  {
14539
5
    as_bad (_("junk `%s' after register"), op_string);
14540
5
    return 0;
14541
5
  }
14542
14543
       /* Reject pseudo registers for .insn.  */
14544
60
      if (dot_insn () && r->reg_type.bitfield.class == ClassNone)
14545
0
  {
14546
0
    as_bad (_("`%s%s' cannot be used here"),
14547
0
      register_prefix, r->reg_name);
14548
0
    return 0;
14549
0
  }
14550
14551
60
      temp = r->reg_type;
14552
60
      temp.bitfield.baseindex = 0;
14553
60
      i.types[this_operand] = operand_type_or (i.types[this_operand],
14554
60
                 temp);
14555
60
      i.types[this_operand].bitfield.unspecified = 0;
14556
60
      i.op[this_operand].regs = r;
14557
60
      i.reg_operands++;
14558
14559
      /* A GPR may follow an RC or SAE immediate only if a (vector) register
14560
         operand was also present earlier on.  */
14561
60
      if (i.rounding.type != rc_none && temp.bitfield.class == Reg
14562
60
          && i.reg_operands == 1)
14563
0
  {
14564
0
    unsigned int j;
14565
14566
0
    for (j = 0; j < ARRAY_SIZE (RC_NamesTable); ++j)
14567
0
      if (i.rounding.type == RC_NamesTable[j].type)
14568
0
        break;
14569
0
    as_bad (_("`%s': misplaced `{%s}'"),
14570
0
      insn_name (current_templates.start), RC_NamesTable[j].name);
14571
0
    return 0;
14572
0
  }
14573
60
    }
14574
96.7k
  else if (*op_string == REGISTER_PREFIX)
14575
47
    {
14576
47
      as_bad (_("bad register name `%s'"), op_string);
14577
47
      return 0;
14578
47
    }
14579
96.7k
  else if (*op_string == IMMEDIATE_PREFIX)
14580
63.6k
    {
14581
63.6k
      ++op_string;
14582
63.6k
      if (i.jumpabsolute)
14583
0
  {
14584
0
    as_bad (_("immediate operand illegal with absolute jump"));
14585
0
    return 0;
14586
0
  }
14587
63.6k
      if (!i386_immediate (op_string))
14588
12.8k
  return 0;
14589
50.7k
      if (i.rounding.type != rc_none)
14590
0
  {
14591
0
    as_bad (_("`%s': RC/SAE operand must follow immediate operands"),
14592
0
      insn_name (current_templates.start));
14593
0
    return 0;
14594
0
  }
14595
50.7k
    }
14596
33.1k
  else if (RC_SAE_immediate (operand_string))
14597
0
    {
14598
      /* If it is a RC or SAE immediate, do the necessary placement check:
14599
   Only another immediate or a GPR may precede it.  */
14600
0
      if (i.mem_operands || i.reg_operands + i.imm_operands > 1
14601
0
    || (i.reg_operands == 1
14602
0
        && i.op[0].regs->reg_type.bitfield.class != Reg))
14603
0
  {
14604
0
    as_bad (_("`%s': misplaced `%s'"),
14605
0
      insn_name (current_templates.start), operand_string);
14606
0
    return 0;
14607
0
  }
14608
0
    }
14609
33.1k
  else if (starts_memory_operand (*op_string))
14610
32.9k
    {
14611
      /* This is a memory reference of some sort.  */
14612
32.9k
      char *base_string;
14613
14614
      /* Start and end of displacement string expression (if found).  */
14615
32.9k
      char *displacement_string_start;
14616
32.9k
      char *displacement_string_end;
14617
14618
32.9k
    do_memory_reference:
14619
      /* Check for base index form.  We detect the base index form by
14620
   looking for an ')' at the end of the operand, searching
14621
   for the '(' matching it, and finding a REGISTER_PREFIX or ','
14622
   after the '('.  */
14623
32.9k
      base_string = op_string + strlen (op_string);
14624
14625
      /* Handle vector operations.  */
14626
32.9k
      --base_string;
14627
32.9k
      if (is_space_char (*base_string))
14628
152
  --base_string;
14629
14630
32.9k
      if (*base_string == '}')
14631
5
  {
14632
5
    char *vop_start = NULL;
14633
14634
101
    while (base_string-- > op_string)
14635
98
      {
14636
98
        if (*base_string == '"')
14637
0
    break;
14638
98
        if (*base_string != '{')
14639
95
    continue;
14640
14641
3
        vop_start = base_string;
14642
14643
3
        --base_string;
14644
3
        if (is_space_char (*base_string))
14645
3
    --base_string;
14646
14647
3
        if (*base_string != '}')
14648
2
    break;
14649
14650
1
        vop_start = NULL;
14651
1
      }
14652
14653
5
    if (!vop_start)
14654
3
      {
14655
3
        as_bad (_("unbalanced figure braces"));
14656
3
        return 0;
14657
3
      }
14658
14659
2
    if (check_VecOperations (vop_start) == NULL)
14660
2
      return 0;
14661
2
  }
14662
14663
      /* If we only have a displacement, set-up for it to be parsed later.  */
14664
32.9k
      displacement_string_start = op_string;
14665
32.9k
      displacement_string_end = base_string + 1;
14666
14667
32.9k
      if (*base_string == ')')
14668
340
  {
14669
340
    char *temp_string;
14670
340
    unsigned int parens_not_balanced = 0;
14671
340
    bool in_quotes = false;
14672
14673
    /* We've already checked that the number of left & right ()'s are
14674
       equal, and that there's a matching set of double quotes.  */
14675
340
    end_op = base_string;
14676
3.42k
    for (temp_string = op_string; temp_string < end_op; temp_string++)
14677
3.08k
      {
14678
3.08k
        if (*temp_string == '\\' && temp_string[1] == '"')
14679
0
    ++temp_string;
14680
3.08k
        else if (*temp_string == '"')
14681
36
    in_quotes = !in_quotes;
14682
3.04k
        else if (!in_quotes)
14683
3.02k
    {
14684
3.02k
      if (*temp_string == '(' && !parens_not_balanced++)
14685
341
        base_string = temp_string;
14686
3.02k
      if (*temp_string == ')')
14687
2
        --parens_not_balanced;
14688
3.02k
    }
14689
3.08k
      }
14690
14691
340
    temp_string = base_string;
14692
14693
    /* Skip past '(' and whitespace.  */
14694
340
    gas_assert (*base_string == '(');
14695
340
    ++base_string;
14696
340
    if (is_space_char (*base_string))
14697
54
      ++base_string;
14698
14699
340
    if (*base_string == ','
14700
340
        || ((i.base_reg = parse_register (base_string, &end_op))
14701
293
      != NULL))
14702
47
      {
14703
47
        displacement_string_end = temp_string;
14704
14705
47
        i.types[this_operand].bitfield.baseindex = 1;
14706
14707
47
        if (i.base_reg)
14708
0
    {
14709
0
      if (i.base_reg == &bad_reg)
14710
0
        return 0;
14711
0
      base_string = end_op;
14712
0
      if (is_space_char (*base_string))
14713
0
        ++base_string;
14714
0
    }
14715
14716
        /* There may be an index reg or scale factor here.  */
14717
47
        if (*base_string == ',')
14718
47
    {
14719
47
      ++base_string;
14720
47
      if (is_space_char (*base_string))
14721
0
        ++base_string;
14722
14723
47
      if ((i.index_reg = parse_register (base_string, &end_op))
14724
47
          != NULL)
14725
0
        {
14726
0
          if (i.index_reg == &bad_reg)
14727
0
      return 0;
14728
0
          base_string = end_op;
14729
0
          if (is_space_char (*base_string))
14730
0
      ++base_string;
14731
0
          if (*base_string == ',')
14732
0
      {
14733
0
        ++base_string;
14734
0
        if (is_space_char (*base_string))
14735
0
          ++base_string;
14736
0
      }
14737
0
          else if (*base_string != ')')
14738
0
      {
14739
0
        as_bad (_("expecting `,' or `)' "
14740
0
            "after index register in `%s'"),
14741
0
          operand_string);
14742
0
        return 0;
14743
0
      }
14744
0
        }
14745
47
      else if (*base_string == REGISTER_PREFIX)
14746
0
        {
14747
0
          end_op = strchr (base_string, ',');
14748
0
          if (end_op)
14749
0
      *end_op = '\0';
14750
0
          as_bad (_("bad register name `%s'"), base_string);
14751
0
          return 0;
14752
0
        }
14753
14754
      /* Check for scale factor.  */
14755
47
      if (*base_string != ')')
14756
47
        {
14757
47
          char *end_scale = i386_scale (base_string);
14758
14759
47
          if (!end_scale)
14760
5
      return 0;
14761
14762
42
          base_string = end_scale;
14763
42
          if (is_space_char (*base_string))
14764
0
      ++base_string;
14765
42
          if (*base_string != ')')
14766
42
      {
14767
42
        as_bad (_("expecting `)' "
14768
42
            "after scale factor in `%s'"),
14769
42
          operand_string);
14770
42
        return 0;
14771
42
      }
14772
42
        }
14773
0
      else if (!i.index_reg)
14774
0
        {
14775
0
          as_bad (_("expecting index register or scale factor "
14776
0
        "after `,'; got '%c'"),
14777
0
            *base_string);
14778
0
          return 0;
14779
0
        }
14780
47
    }
14781
0
        else if (*base_string != ')')
14782
0
    {
14783
0
      as_bad (_("expecting `,' or `)' "
14784
0
          "after base register in `%s'"),
14785
0
        operand_string);
14786
0
      return 0;
14787
0
    }
14788
47
      }
14789
293
    else if (*base_string == REGISTER_PREFIX)
14790
0
      {
14791
0
        end_op = strchr (base_string, ',');
14792
0
        if (end_op)
14793
0
    *end_op = '\0';
14794
0
        as_bad (_("bad register name `%s'"), base_string);
14795
0
        return 0;
14796
0
      }
14797
340
  }
14798
14799
      /* If there's an expression beginning the operand, parse it,
14800
   assuming displacement_string_start and
14801
   displacement_string_end are meaningful.  */
14802
32.8k
      if (displacement_string_start != displacement_string_end)
14803
32.8k
  {
14804
32.8k
    if (!i386_displacement (displacement_string_start,
14805
32.8k
          displacement_string_end))
14806
2.69k
      return 0;
14807
32.8k
  }
14808
14809
      /* Special case for (%dx) while doing input/output op.  */
14810
30.1k
      if (i.base_reg
14811
30.1k
    && i.base_reg->reg_type.bitfield.instance == RegD
14812
30.1k
    && i.base_reg->reg_type.bitfield.word
14813
30.1k
    && i.index_reg == 0
14814
30.1k
    && i.log2_scale_factor == 0
14815
30.1k
    && i.seg[i.mem_operands] == 0
14816
30.1k
    && !operand_type_check (i.types[this_operand], disp))
14817
0
  {
14818
0
    i.types[this_operand] = i.base_reg->reg_type;
14819
0
    i.op[this_operand].regs = i.base_reg;
14820
0
    i.base_reg = NULL;
14821
0
    i.input_output_operand = true;
14822
0
    return 1;
14823
0
  }
14824
14825
30.1k
      if (i386_index_check (operand_string) == 0)
14826
0
  return 0;
14827
30.1k
      i.flags[this_operand] |= Operand_Mem;
14828
30.1k
      i.mem_operands++;
14829
30.1k
    }
14830
204
  else
14831
204
    {
14832
      /* It's not a memory operand; argh!  */
14833
204
      as_bad (_("invalid char %s beginning operand %d `%s'"),
14834
204
        output_invalid (*op_string),
14835
204
        this_operand + 1,
14836
204
        op_string);
14837
204
      return 0;
14838
204
    }
14839
80.9k
  return 1;     /* Normal return.  */
14840
96.8k
}
14841

14842
/* Calculate the maximum variable size (i.e., excluding fr_fix)
14843
   that an rs_machine_dependent frag may reach.  */
14844
14845
unsigned int
14846
i386_frag_max_var (fragS *frag)
14847
0
{
14848
  /* The only relaxable frags are for jumps.
14849
     Unconditional jumps can grow by 4 bytes and others by 5 bytes.  */
14850
0
  gas_assert (frag->fr_type == rs_machine_dependent);
14851
0
  return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
14852
0
}
14853
14854
#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14855
static int
14856
elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var)
14857
0
{
14858
  /* STT_GNU_IFUNC symbol must go through PLT.  */
14859
0
  if ((symbol_get_bfdsym (fr_symbol)->flags
14860
0
       & BSF_GNU_INDIRECT_FUNCTION) != 0)
14861
0
    return 0;
14862
14863
0
  if (!S_IS_EXTERNAL (fr_symbol))
14864
    /* Symbol may be weak or local.  */
14865
0
    return !S_IS_WEAK (fr_symbol);
14866
14867
  /* Global symbols with non-default visibility can't be preempted. */
14868
0
  if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT)
14869
0
    return 1;
14870
14871
0
  if (fr_var != NO_RELOC)
14872
0
    switch ((enum bfd_reloc_code_real) fr_var)
14873
0
      {
14874
0
      case BFD_RELOC_386_PLT32:
14875
0
      case BFD_RELOC_X86_64_PLT32:
14876
  /* Symbol with PLT relocation may be preempted. */
14877
0
  return 0;
14878
0
      default:
14879
0
  abort ();
14880
0
      }
14881
14882
  /* Global symbols with default visibility in a shared library may be
14883
     preempted by another definition.  */
14884
0
  return !shared;
14885
0
}
14886
#endif
14887
14888
/* Table 3-2. Macro-Fusible Instructions in Haswell Microarchitecture
14889
   Note also work for Skylake and Cascadelake.
14890
---------------------------------------------------------------------
14891
|   JCC   | ADD/SUB/CMP | INC/DEC | TEST/AND |
14892
| ------  | ----------- | ------- | -------- |
14893
|   Jo    |      N      |    N    |     Y    |
14894
|   Jno   |      N      |    N    |     Y    |
14895
|  Jc/Jb  |      Y      |    N    |     Y    |
14896
| Jae/Jnb |      Y      |    N    |     Y    |
14897
|  Je/Jz  |      Y      |    Y    |     Y    |
14898
| Jne/Jnz |      Y      |    Y    |     Y    |
14899
| Jna/Jbe |      Y      |    N    |     Y    |
14900
| Ja/Jnbe |      Y      |    N    |     Y    |
14901
|   Js    |      N      |    N    |     Y    |
14902
|   Jns   |      N      |    N    |     Y    |
14903
|  Jp/Jpe |      N      |    N    |     Y    |
14904
| Jnp/Jpo |      N      |    N    |     Y    |
14905
| Jl/Jnge |      Y      |    Y    |     Y    |
14906
| Jge/Jnl |      Y      |    Y    |     Y    |
14907
| Jle/Jng |      Y      |    Y    |     Y    |
14908
| Jg/Jnle |      Y      |    Y    |     Y    |
14909
---------------------------------------------------------------------  */
14910
static int
14911
i386_macro_fusible_p (enum mf_cmp_kind mf_cmp, enum mf_jcc_kind mf_jcc)
14912
0
{
14913
0
  if (mf_cmp == mf_cmp_alu_cmp)
14914
0
    return ((mf_jcc >= mf_jcc_jc && mf_jcc <= mf_jcc_jna)
14915
0
      || mf_jcc == mf_jcc_jl || mf_jcc == mf_jcc_jle);
14916
0
  if (mf_cmp == mf_cmp_incdec)
14917
0
    return (mf_jcc == mf_jcc_je || mf_jcc == mf_jcc_jl
14918
0
      || mf_jcc == mf_jcc_jle);
14919
0
  if (mf_cmp == mf_cmp_test_and)
14920
0
    return 1;
14921
0
  return 0;
14922
0
}
14923
14924
/* Return the next non-empty frag.  */
14925
14926
static fragS *
14927
i386_next_non_empty_frag (fragS *fragP)
14928
0
{
14929
  /* There may be a frag with a ".fill 0" when there is no room in
14930
     the current frag for frag_grow in output_insn.  */
14931
0
  for (fragP = fragP->fr_next;
14932
0
       (fragP != NULL
14933
0
  && fragP->fr_type == rs_fill
14934
0
  && fragP->fr_fix == 0);
14935
0
       fragP = fragP->fr_next)
14936
0
    ;
14937
0
  return fragP;
14938
0
}
14939
14940
/* Return the next jcc frag after BRANCH_PADDING.  */
14941
14942
static fragS *
14943
i386_next_fusible_jcc_frag (fragS *maybe_cmp_fragP, fragS *pad_fragP)
14944
0
{
14945
0
  fragS *branch_fragP;
14946
0
  if (!pad_fragP)
14947
0
    return NULL;
14948
14949
0
  if (pad_fragP->fr_type == rs_machine_dependent
14950
0
      && (TYPE_FROM_RELAX_STATE (pad_fragP->fr_subtype)
14951
0
    == BRANCH_PADDING))
14952
0
    {
14953
0
      branch_fragP = i386_next_non_empty_frag (pad_fragP);
14954
0
      if (branch_fragP->fr_type != rs_machine_dependent)
14955
0
  return NULL;
14956
0
      if (TYPE_FROM_RELAX_STATE (branch_fragP->fr_subtype) == COND_JUMP
14957
0
    && i386_macro_fusible_p (maybe_cmp_fragP->tc_frag_data.mf_type,
14958
0
           pad_fragP->tc_frag_data.mf_type))
14959
0
  return branch_fragP;
14960
0
    }
14961
14962
0
  return NULL;
14963
0
}
14964
14965
/* Classify BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags.  */
14966
14967
static void
14968
i386_classify_machine_dependent_frag (fragS *fragP)
14969
0
{
14970
0
  fragS *cmp_fragP;
14971
0
  fragS *pad_fragP;
14972
0
  fragS *branch_fragP;
14973
0
  fragS *next_fragP;
14974
0
  unsigned int max_prefix_length;
14975
14976
0
  if (fragP->tc_frag_data.classified)
14977
0
    return;
14978
14979
  /* First scan for BRANCH_PADDING and FUSED_JCC_PADDING.  Convert
14980
     FUSED_JCC_PADDING and merge BRANCH_PADDING.  */
14981
0
  for (next_fragP = fragP;
14982
0
       next_fragP != NULL;
14983
0
       next_fragP = next_fragP->fr_next)
14984
0
    {
14985
0
      next_fragP->tc_frag_data.classified = 1;
14986
0
      if (next_fragP->fr_type == rs_machine_dependent)
14987
0
  switch (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype))
14988
0
    {
14989
0
    case BRANCH_PADDING:
14990
      /* The BRANCH_PADDING frag must be followed by a branch
14991
         frag.  */
14992
0
      branch_fragP = i386_next_non_empty_frag (next_fragP);
14993
0
      next_fragP->tc_frag_data.u.branch_fragP = branch_fragP;
14994
0
      break;
14995
0
    case FUSED_JCC_PADDING:
14996
      /* Check if this is a fused jcc:
14997
         FUSED_JCC_PADDING
14998
         CMP like instruction
14999
         BRANCH_PADDING
15000
         COND_JUMP
15001
         */
15002
0
      cmp_fragP = i386_next_non_empty_frag (next_fragP);
15003
0
      pad_fragP = i386_next_non_empty_frag (cmp_fragP);
15004
0
      branch_fragP = i386_next_fusible_jcc_frag (next_fragP, pad_fragP);
15005
0
      if (branch_fragP)
15006
0
        {
15007
    /* The BRANCH_PADDING frag is merged with the
15008
       FUSED_JCC_PADDING frag.  */
15009
0
    next_fragP->tc_frag_data.u.branch_fragP = branch_fragP;
15010
    /* CMP like instruction size.  */
15011
0
    next_fragP->tc_frag_data.cmp_size = cmp_fragP->fr_fix;
15012
0
    frag_wane (pad_fragP);
15013
    /* Skip to branch_fragP.  */
15014
0
    next_fragP = branch_fragP;
15015
0
        }
15016
0
      else if (next_fragP->tc_frag_data.max_prefix_length)
15017
0
        {
15018
    /* Turn FUSED_JCC_PADDING into BRANCH_PREFIX if it isn't
15019
       a fused jcc.  */
15020
0
    next_fragP->fr_subtype
15021
0
      = ENCODE_RELAX_STATE (BRANCH_PREFIX, 0);
15022
0
    next_fragP->tc_frag_data.max_bytes
15023
0
      = next_fragP->tc_frag_data.max_prefix_length;
15024
    /* This will be updated in the BRANCH_PREFIX scan.  */
15025
0
    next_fragP->tc_frag_data.max_prefix_length = 0;
15026
0
        }
15027
0
      else
15028
0
        frag_wane (next_fragP);
15029
0
      break;
15030
0
    }
15031
0
    }
15032
15033
  /* Stop if there is no BRANCH_PREFIX.  */
15034
0
  if (!align_branch_prefix_size)
15035
0
    return;
15036
15037
  /* Scan for BRANCH_PREFIX.  */
15038
0
  for (; fragP != NULL; fragP = fragP->fr_next)
15039
0
    {
15040
0
      if (fragP->fr_type != rs_machine_dependent
15041
0
    || (TYPE_FROM_RELAX_STATE (fragP->fr_subtype)
15042
0
        != BRANCH_PREFIX))
15043
0
  continue;
15044
15045
      /* Count all BRANCH_PREFIX frags before BRANCH_PADDING and
15046
   COND_JUMP_PREFIX.  */
15047
0
      max_prefix_length = 0;
15048
0
      for (next_fragP = fragP;
15049
0
     next_fragP != NULL;
15050
0
     next_fragP = next_fragP->fr_next)
15051
0
  {
15052
0
    if (next_fragP->fr_type == rs_fill)
15053
      /* Skip rs_fill frags.  */
15054
0
      continue;
15055
0
    else if (next_fragP->fr_type != rs_machine_dependent)
15056
      /* Stop for all other frags.  */
15057
0
      break;
15058
15059
    /* rs_machine_dependent frags.  */
15060
0
    if (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype)
15061
0
        == BRANCH_PREFIX)
15062
0
      {
15063
        /* Count BRANCH_PREFIX frags.  */
15064
0
        if (max_prefix_length >= MAX_FUSED_JCC_PADDING_SIZE)
15065
0
    {
15066
0
      max_prefix_length = MAX_FUSED_JCC_PADDING_SIZE;
15067
0
      frag_wane (next_fragP);
15068
0
    }
15069
0
        else
15070
0
    max_prefix_length
15071
0
      += next_fragP->tc_frag_data.max_bytes;
15072
0
      }
15073
0
    else if ((TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype)
15074
0
        == BRANCH_PADDING)
15075
0
       || (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype)
15076
0
           == FUSED_JCC_PADDING))
15077
0
      {
15078
        /* Stop at BRANCH_PADDING and FUSED_JCC_PADDING.  */
15079
0
        fragP->tc_frag_data.u.padding_fragP = next_fragP;
15080
0
        break;
15081
0
      }
15082
0
    else
15083
      /* Stop for other rs_machine_dependent frags.  */
15084
0
      break;
15085
0
  }
15086
15087
0
      fragP->tc_frag_data.max_prefix_length = max_prefix_length;
15088
15089
      /* Skip to the next frag.  */
15090
0
      fragP = next_fragP;
15091
0
    }
15092
0
}
15093
15094
/* Compute padding size for
15095
15096
  FUSED_JCC_PADDING
15097
  CMP like instruction
15098
  BRANCH_PADDING
15099
  COND_JUMP/UNCOND_JUMP
15100
15101
   or
15102
15103
  BRANCH_PADDING
15104
  COND_JUMP/UNCOND_JUMP
15105
 */
15106
15107
static int
15108
i386_branch_padding_size (fragS *fragP, offsetT address)
15109
0
{
15110
0
  unsigned int offset, size, padding_size;
15111
0
  fragS *branch_fragP = fragP->tc_frag_data.u.branch_fragP;
15112
15113
  /* The start address of the BRANCH_PADDING or FUSED_JCC_PADDING frag.  */
15114
0
  if (!address)
15115
0
    address = fragP->fr_address;
15116
0
  address += fragP->fr_fix;
15117
15118
  /* CMP like instrunction size.  */
15119
0
  size = fragP->tc_frag_data.cmp_size;
15120
15121
  /* The base size of the branch frag.  */
15122
0
  size += branch_fragP->fr_fix;
15123
15124
  /* Add opcode and displacement bytes for the rs_machine_dependent
15125
     branch frag.  */
15126
0
  if (branch_fragP->fr_type == rs_machine_dependent)
15127
0
    size += md_relax_table[branch_fragP->fr_subtype].rlx_length;
15128
15129
  /* Check if branch is within boundary and doesn't end at the last
15130
     byte.  */
15131
0
  offset = address & ((1U << align_branch_power) - 1);
15132
0
  if ((offset + size) >= (1U << align_branch_power))
15133
    /* Padding needed to avoid crossing boundary.  */
15134
0
    padding_size = (1U << align_branch_power) - offset;
15135
0
  else
15136
    /* No padding needed.  */
15137
0
    padding_size = 0;
15138
15139
  /* The return value may be saved in tc_frag_data.length which is
15140
     unsigned byte.  */
15141
0
  if (!fits_in_unsigned_byte (padding_size))
15142
0
    abort ();
15143
15144
0
  return padding_size;
15145
0
}
15146
15147
/* i386_generic_table_relax_frag()
15148
15149
   Handle BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags to
15150
   grow/shrink padding to align branch frags.  Hand others to
15151
   relax_frag().  */
15152
15153
long
15154
i386_generic_table_relax_frag (segT segment, fragS *fragP, long stretch)
15155
0
{
15156
0
  if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PADDING
15157
0
      || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == FUSED_JCC_PADDING)
15158
0
    {
15159
0
      long padding_size = i386_branch_padding_size (fragP, 0);
15160
0
      long grow = padding_size - fragP->tc_frag_data.length;
15161
15162
      /* When the BRANCH_PREFIX frag is used, the computed address
15163
         must match the actual address and there should be no padding.  */
15164
0
      if (fragP->tc_frag_data.padding_address
15165
0
    && (fragP->tc_frag_data.padding_address != fragP->fr_address
15166
0
        || padding_size))
15167
0
  abort ();
15168
15169
      /* Update the padding size.  */
15170
0
      if (grow)
15171
0
  fragP->tc_frag_data.length = padding_size;
15172
15173
0
      return grow;
15174
0
    }
15175
0
  else if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PREFIX)
15176
0
    {
15177
0
      fragS *padding_fragP, *next_fragP;
15178
0
      long padding_size, left_size, last_size;
15179
15180
0
      padding_fragP = fragP->tc_frag_data.u.padding_fragP;
15181
0
      if (!padding_fragP)
15182
  /* Use the padding set by the leading BRANCH_PREFIX frag.  */
15183
0
  return (fragP->tc_frag_data.length
15184
0
    - fragP->tc_frag_data.last_length);
15185
15186
      /* Compute the relative address of the padding frag in the very
15187
        first time where the BRANCH_PREFIX frag sizes are zero.  */
15188
0
      if (!fragP->tc_frag_data.padding_address)
15189
0
  fragP->tc_frag_data.padding_address
15190
0
    = padding_fragP->fr_address - (fragP->fr_address - stretch);
15191
15192
      /* First update the last length from the previous interation.  */
15193
0
      left_size = fragP->tc_frag_data.prefix_length;
15194
0
      for (next_fragP = fragP;
15195
0
     next_fragP != padding_fragP;
15196
0
     next_fragP = next_fragP->fr_next)
15197
0
  if (next_fragP->fr_type == rs_machine_dependent
15198
0
      && (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype)
15199
0
    == BRANCH_PREFIX))
15200
0
    {
15201
0
      if (left_size)
15202
0
        {
15203
0
    int max = next_fragP->tc_frag_data.max_bytes;
15204
0
    if (max)
15205
0
      {
15206
0
        int size;
15207
0
        if (max > left_size)
15208
0
          size = left_size;
15209
0
        else
15210
0
          size = max;
15211
0
        left_size -= size;
15212
0
        next_fragP->tc_frag_data.last_length = size;
15213
0
      }
15214
0
        }
15215
0
      else
15216
0
        next_fragP->tc_frag_data.last_length = 0;
15217
0
    }
15218
15219
      /* Check the padding size for the padding frag.  */
15220
0
      padding_size = i386_branch_padding_size
15221
0
  (padding_fragP, (fragP->fr_address
15222
0
       + fragP->tc_frag_data.padding_address));
15223
15224
0
      last_size = fragP->tc_frag_data.prefix_length;
15225
      /* Check if there is change from the last interation.  */
15226
0
      if (padding_size == last_size)
15227
0
  {
15228
    /* Update the expected address of the padding frag.  */
15229
0
    padding_fragP->tc_frag_data.padding_address
15230
0
      = (fragP->fr_address + padding_size
15231
0
         + fragP->tc_frag_data.padding_address);
15232
0
    return 0;
15233
0
  }
15234
15235
0
      if (padding_size > fragP->tc_frag_data.max_prefix_length)
15236
0
  {
15237
    /* No padding if there is no sufficient room.  Clear the
15238
       expected address of the padding frag.  */
15239
0
    padding_fragP->tc_frag_data.padding_address = 0;
15240
0
    padding_size = 0;
15241
0
  }
15242
0
      else
15243
  /* Store the expected address of the padding frag.  */
15244
0
  padding_fragP->tc_frag_data.padding_address
15245
0
    = (fragP->fr_address + padding_size
15246
0
       + fragP->tc_frag_data.padding_address);
15247
15248
0
      fragP->tc_frag_data.prefix_length = padding_size;
15249
15250
      /* Update the length for the current interation.  */
15251
0
      left_size = padding_size;
15252
0
      for (next_fragP = fragP;
15253
0
     next_fragP != padding_fragP;
15254
0
     next_fragP = next_fragP->fr_next)
15255
0
  if (next_fragP->fr_type == rs_machine_dependent
15256
0
      && (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype)
15257
0
    == BRANCH_PREFIX))
15258
0
    {
15259
0
      if (left_size)
15260
0
        {
15261
0
    int max = next_fragP->tc_frag_data.max_bytes;
15262
0
    if (max)
15263
0
      {
15264
0
        int size;
15265
0
        if (max > left_size)
15266
0
          size = left_size;
15267
0
        else
15268
0
          size = max;
15269
0
        left_size -= size;
15270
0
        next_fragP->tc_frag_data.length = size;
15271
0
      }
15272
0
        }
15273
0
      else
15274
0
        next_fragP->tc_frag_data.length = 0;
15275
0
    }
15276
15277
0
      return (fragP->tc_frag_data.length
15278
0
        - fragP->tc_frag_data.last_length);
15279
0
    }
15280
0
  return relax_frag (segment, fragP, stretch);
15281
0
}
15282
15283
/* md_estimate_size_before_relax()
15284
15285
   Called just before relax() for rs_machine_dependent frags.  The x86
15286
   assembler uses these frags to handle variable size jump
15287
   instructions.
15288
15289
   Any symbol that is now undefined will not become defined.
15290
   Return the correct fr_subtype in the frag.
15291
   Return the initial "guess for variable size of frag" to caller.
15292
   The guess is actually the growth beyond the fixed part.  Whatever
15293
   we do to grow the fixed or variable part contributes to our
15294
   returned value.  */
15295
15296
int
15297
md_estimate_size_before_relax (fragS *fragP, segT segment)
15298
0
{
15299
0
  if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PADDING
15300
0
      || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PREFIX
15301
0
      || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == FUSED_JCC_PADDING)
15302
0
    {
15303
0
      i386_classify_machine_dependent_frag (fragP);
15304
0
      return fragP->tc_frag_data.length;
15305
0
    }
15306
15307
  /* We've already got fragP->fr_subtype right;  all we have to do is
15308
     check for un-relaxable symbols.  On an ELF system, we can't relax
15309
     an externally visible symbol, because it may be overridden by a
15310
     shared library.  */
15311
0
  if (S_GET_SEGMENT (fragP->fr_symbol) != segment
15312
0
#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15313
0
      || (IS_ELF
15314
0
    && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol,
15315
0
            fragP->fr_var))
15316
0
#endif
15317
#if defined (OBJ_COFF) && defined (TE_PE)
15318
      || (OUTPUT_FLAVOR == bfd_target_coff_flavour
15319
    && S_IS_WEAK (fragP->fr_symbol))
15320
#endif
15321
0
      )
15322
0
    {
15323
      /* Symbol is undefined in this segment, or we need to keep a
15324
   reloc so that weak symbols can be overridden.  */
15325
0
      int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
15326
0
      enum bfd_reloc_code_real reloc_type;
15327
0
      unsigned char *opcode;
15328
0
      int old_fr_fix;
15329
0
      fixS *fixP = NULL;
15330
15331
0
      if (fragP->fr_var != NO_RELOC)
15332
0
  reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
15333
0
      else if (size == 2)
15334
0
  reloc_type = BFD_RELOC_16_PCREL;
15335
0
#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15336
0
      else if (fragP->tc_frag_data.code == CODE_64BIT
15337
0
         && fragP->fr_offset == 0
15338
0
         && need_plt32_p (fragP->fr_symbol))
15339
0
  reloc_type = BFD_RELOC_X86_64_PLT32;
15340
0
#endif
15341
0
      else
15342
0
  reloc_type = BFD_RELOC_32_PCREL;
15343
15344
0
      old_fr_fix = fragP->fr_fix;
15345
0
      opcode = (unsigned char *) fragP->fr_opcode;
15346
15347
0
      switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
15348
0
  {
15349
0
  case UNCOND_JUMP:
15350
    /* Make jmp (0xeb) a (d)word displacement jump.  */
15351
0
    opcode[0] = 0xe9;
15352
0
    fragP->fr_fix += size;
15353
0
    fixP = fix_new (fragP, old_fr_fix, size,
15354
0
        fragP->fr_symbol,
15355
0
        fragP->fr_offset, 1,
15356
0
        reloc_type);
15357
0
    break;
15358
15359
0
  case COND_JUMP86:
15360
0
    if (size == 2
15361
0
        && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
15362
0
      {
15363
        /* Negate the condition, and branch past an
15364
     unconditional jump.  */
15365
0
        opcode[0] ^= 1;
15366
0
        opcode[1] = 3;
15367
        /* Insert an unconditional jump.  */
15368
0
        opcode[2] = 0xe9;
15369
        /* We added two extra opcode bytes, and have a two byte
15370
     offset.  */
15371
0
        fragP->fr_fix += 2 + 2;
15372
0
        fix_new (fragP, old_fr_fix + 2, 2,
15373
0
           fragP->fr_symbol,
15374
0
           fragP->fr_offset, 1,
15375
0
           reloc_type);
15376
0
        break;
15377
0
      }
15378
    /* Fall through.  */
15379
15380
0
  case COND_JUMP:
15381
0
    if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
15382
0
      {
15383
0
        fragP->fr_fix += 1;
15384
0
        fixP = fix_new (fragP, old_fr_fix, 1,
15385
0
            fragP->fr_symbol,
15386
0
            fragP->fr_offset, 1,
15387
0
            BFD_RELOC_8_PCREL);
15388
0
        fixP->fx_signed = 1;
15389
0
        break;
15390
0
      }
15391
15392
    /* This changes the byte-displacement jump 0x7N
15393
       to the (d)word-displacement jump 0x0f,0x8N.  */
15394
0
    opcode[1] = opcode[0] + 0x10;
15395
0
    opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
15396
    /* We've added an opcode byte.  */
15397
0
    fragP->fr_fix += 1 + size;
15398
0
    fixP = fix_new (fragP, old_fr_fix + 1, size,
15399
0
        fragP->fr_symbol,
15400
0
        fragP->fr_offset, 1,
15401
0
        reloc_type);
15402
0
    break;
15403
15404
0
  default:
15405
0
    BAD_CASE (fragP->fr_subtype);
15406
0
    break;
15407
0
  }
15408
15409
      /* All jumps handled here are signed, but don't unconditionally use a
15410
   signed limit check for 32 and 16 bit jumps as we want to allow wrap
15411
   around at 4G (outside of 64-bit mode) and 64k.  */
15412
0
      if (size == 4 && flag_code == CODE_64BIT)
15413
0
  fixP->fx_signed = 1;
15414
15415
0
      frag_wane (fragP);
15416
0
      return fragP->fr_fix - old_fr_fix;
15417
0
    }
15418
15419
  /* Guess size depending on current relax state.  Initially the relax
15420
     state will correspond to a short jump and we return 1, because
15421
     the variable part of the frag (the branch offset) is one byte
15422
     long.  However, we can relax a section more than once and in that
15423
     case we must either set fr_subtype back to the unrelaxed state,
15424
     or return the value for the appropriate branch.  */
15425
0
  return md_relax_table[fragP->fr_subtype].rlx_length;
15426
0
}
15427
15428
/* Called after relax() is finished.
15429
15430
   In:  Address of frag.
15431
  fr_type == rs_machine_dependent.
15432
  fr_subtype is what the address relaxed to.
15433
15434
   Out: Any fixSs and constants are set up.
15435
  Caller will turn frag into a ".space 0".  */
15436
15437
void
15438
md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
15439
                 fragS *fragP)
15440
0
{
15441
0
  unsigned char *opcode;
15442
0
  unsigned char *where_to_put_displacement = NULL;
15443
0
  offsetT target_address;
15444
0
  offsetT opcode_address;
15445
0
  unsigned int extension = 0;
15446
0
  offsetT displacement_from_opcode_start;
15447
15448
0
  if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PADDING
15449
0
      || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == FUSED_JCC_PADDING
15450
0
      || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PREFIX)
15451
0
    {
15452
      /* Generate nop padding.  */
15453
0
      unsigned int size = fragP->tc_frag_data.length;
15454
0
      if (size)
15455
0
  {
15456
0
    if (size > fragP->tc_frag_data.max_bytes)
15457
0
      abort ();
15458
15459
0
    if (flag_debug)
15460
0
      {
15461
0
        const char *msg;
15462
0
        const char *branch = "branch";
15463
0
        const char *prefix = "";
15464
0
        fragS *padding_fragP;
15465
0
        if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype)
15466
0
      == BRANCH_PREFIX)
15467
0
    {
15468
0
      padding_fragP = fragP->tc_frag_data.u.padding_fragP;
15469
0
      switch (fragP->tc_frag_data.default_prefix)
15470
0
        {
15471
0
        default:
15472
0
          abort ();
15473
0
          break;
15474
0
        case CS_PREFIX_OPCODE:
15475
0
          prefix = " cs";
15476
0
          break;
15477
0
        case DS_PREFIX_OPCODE:
15478
0
          prefix = " ds";
15479
0
          break;
15480
0
        case ES_PREFIX_OPCODE:
15481
0
          prefix = " es";
15482
0
          break;
15483
0
        case FS_PREFIX_OPCODE:
15484
0
          prefix = " fs";
15485
0
          break;
15486
0
        case GS_PREFIX_OPCODE:
15487
0
          prefix = " gs";
15488
0
          break;
15489
0
        case SS_PREFIX_OPCODE:
15490
0
          prefix = " ss";
15491
0
          break;
15492
0
        }
15493
0
      if (padding_fragP)
15494
0
        msg = _("%s:%u: add %d%s at 0x%llx to align "
15495
0
          "%s within %d-byte boundary\n");
15496
0
      else
15497
0
        msg = _("%s:%u: add additional %d%s at 0x%llx to "
15498
0
          "align %s within %d-byte boundary\n");
15499
0
    }
15500
0
        else
15501
0
    {
15502
0
      padding_fragP = fragP;
15503
0
      msg = _("%s:%u: add %d%s-byte nop at 0x%llx to align "
15504
0
        "%s within %d-byte boundary\n");
15505
0
    }
15506
15507
0
        if (padding_fragP)
15508
0
    switch (padding_fragP->tc_frag_data.branch_type)
15509
0
      {
15510
0
      case align_branch_jcc:
15511
0
        branch = "jcc";
15512
0
        break;
15513
0
      case align_branch_fused:
15514
0
        branch = "fused jcc";
15515
0
        break;
15516
0
      case align_branch_jmp:
15517
0
        branch = "jmp";
15518
0
        break;
15519
0
      case align_branch_call:
15520
0
        branch = "call";
15521
0
        break;
15522
0
      case align_branch_indirect:
15523
0
        branch = "indiret branch";
15524
0
        break;
15525
0
      case align_branch_ret:
15526
0
        branch = "ret";
15527
0
        break;
15528
0
      default:
15529
0
        break;
15530
0
      }
15531
15532
0
        fprintf (stdout, msg,
15533
0
           fragP->fr_file, fragP->fr_line, size, prefix,
15534
0
           (long long) fragP->fr_address, branch,
15535
0
           1 << align_branch_power);
15536
0
      }
15537
0
    if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PREFIX)
15538
0
      memset (fragP->fr_opcode,
15539
0
        fragP->tc_frag_data.default_prefix, size);
15540
0
    else
15541
0
      i386_generate_nops (fragP, (char *) fragP->fr_opcode,
15542
0
        size, 0);
15543
0
    fragP->fr_fix += size;
15544
0
  }
15545
0
      return;
15546
0
    }
15547
15548
0
  opcode = (unsigned char *) fragP->fr_opcode;
15549
15550
  /* Address we want to reach in file space.  */
15551
0
  target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
15552
15553
  /* Address opcode resides at in file space.  */
15554
0
  opcode_address = fragP->fr_address + fragP->fr_fix;
15555
15556
  /* Displacement from opcode start to fill into instruction.  */
15557
0
  displacement_from_opcode_start = target_address - opcode_address;
15558
15559
0
  if ((fragP->fr_subtype & BIG) == 0)
15560
0
    {
15561
      /* Don't have to change opcode.  */
15562
0
      extension = 1;    /* 1 opcode + 1 displacement  */
15563
0
      where_to_put_displacement = &opcode[1];
15564
0
    }
15565
0
  else
15566
0
    {
15567
0
      if (no_cond_jump_promotion
15568
0
    && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
15569
0
  as_warn_where (fragP->fr_file, fragP->fr_line,
15570
0
           _("long jump required"));
15571
15572
0
      switch (fragP->fr_subtype)
15573
0
  {
15574
0
  case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
15575
0
    extension = 4;    /* 1 opcode + 4 displacement  */
15576
0
    opcode[0] = 0xe9;
15577
0
    where_to_put_displacement = &opcode[1];
15578
0
    break;
15579
15580
0
  case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
15581
0
    extension = 2;    /* 1 opcode + 2 displacement  */
15582
0
    opcode[0] = 0xe9;
15583
0
    where_to_put_displacement = &opcode[1];
15584
0
    break;
15585
15586
0
  case ENCODE_RELAX_STATE (COND_JUMP, BIG):
15587
0
  case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
15588
0
    extension = 5;    /* 2 opcode + 4 displacement  */
15589
0
    opcode[1] = opcode[0] + 0x10;
15590
0
    opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
15591
0
    where_to_put_displacement = &opcode[2];
15592
0
    break;
15593
15594
0
  case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
15595
0
    extension = 3;    /* 2 opcode + 2 displacement  */
15596
0
    opcode[1] = opcode[0] + 0x10;
15597
0
    opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
15598
0
    where_to_put_displacement = &opcode[2];
15599
0
    break;
15600
15601
0
  case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
15602
0
    extension = 4;
15603
0
    opcode[0] ^= 1;
15604
0
    opcode[1] = 3;
15605
0
    opcode[2] = 0xe9;
15606
0
    where_to_put_displacement = &opcode[3];
15607
0
    break;
15608
15609
0
  default:
15610
0
    BAD_CASE (fragP->fr_subtype);
15611
0
    break;
15612
0
  }
15613
0
    }
15614
15615
  /* If size if less then four we are sure that the operand fits,
15616
     but if it's 4, then it could be that the displacement is larger
15617
     then -/+ 2GB.  */
15618
0
  if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
15619
0
      && object_64bit
15620
0
      && ((addressT) (displacement_from_opcode_start - extension
15621
0
          + ((addressT) 1 << 31))
15622
0
    > (((addressT) 2 << 31) - 1)))
15623
0
    {
15624
0
      as_bad_where (fragP->fr_file, fragP->fr_line,
15625
0
        _("jump target out of range"));
15626
      /* Make us emit 0.  */
15627
0
      displacement_from_opcode_start = extension;
15628
0
    }
15629
  /* Now put displacement after opcode.  */
15630
0
  md_number_to_chars ((char *) where_to_put_displacement,
15631
0
          (valueT) (displacement_from_opcode_start - extension),
15632
0
          DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
15633
0
  fragP->fr_fix += extension;
15634
0
}
15635

15636
/* Apply a fixup (fixP) to segment data, once it has been determined
15637
   by our caller that we have all the info we need to fix it up.
15638
15639
   Parameter valP is the pointer to the value of the bits.
15640
15641
   On the 386, immediates, displacements, and data pointers are all in
15642
   the same (little-endian) format, so we don't need to care about which
15643
   we are handling.  */
15644
15645
void
15646
md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
15647
0
{
15648
0
  char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
15649
0
  valueT value = *valP;
15650
15651
0
#if !defined (TE_Mach)
15652
0
  if (fixP->fx_pcrel)
15653
0
    {
15654
0
      switch (fixP->fx_r_type)
15655
0
  {
15656
0
  default:
15657
0
    break;
15658
15659
0
  case BFD_RELOC_64:
15660
0
    fixP->fx_r_type = BFD_RELOC_64_PCREL;
15661
0
    break;
15662
0
  case BFD_RELOC_32:
15663
0
  case BFD_RELOC_X86_64_32S:
15664
0
    fixP->fx_r_type = BFD_RELOC_32_PCREL;
15665
0
    break;
15666
0
  case BFD_RELOC_16:
15667
0
    fixP->fx_r_type = BFD_RELOC_16_PCREL;
15668
0
    break;
15669
0
  case BFD_RELOC_8:
15670
0
    fixP->fx_r_type = BFD_RELOC_8_PCREL;
15671
0
    break;
15672
0
  }
15673
0
    }
15674
15675
0
  if (fixP->fx_addsy != NULL
15676
0
      && (fixP->fx_r_type == BFD_RELOC_32_PCREL
15677
0
    || fixP->fx_r_type == BFD_RELOC_64_PCREL
15678
0
    || fixP->fx_r_type == BFD_RELOC_16_PCREL
15679
0
    || fixP->fx_r_type == BFD_RELOC_8_PCREL)
15680
0
      && !use_rela_relocations)
15681
0
    {
15682
      /* This is a hack.  There should be a better way to handle this.
15683
   This covers for the fact that bfd_install_relocation will
15684
   subtract the current location (for partial_inplace, PC relative
15685
   relocations); see more below.  */
15686
0
#ifndef OBJ_AOUT
15687
0
      if (IS_ELF
15688
#ifdef TE_PE
15689
    || OUTPUT_FLAVOR == bfd_target_coff_flavour
15690
#endif
15691
0
    )
15692
0
  value += fixP->fx_where + fixP->fx_frag->fr_address;
15693
0
#endif
15694
0
#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15695
0
      if (IS_ELF)
15696
0
  {
15697
0
    segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
15698
15699
0
    if ((sym_seg == seg
15700
0
         || (symbol_section_p (fixP->fx_addsy)
15701
0
       && sym_seg != absolute_section))
15702
0
        && !generic_force_reloc (fixP))
15703
0
      {
15704
        /* Yes, we add the values in twice.  This is because
15705
     bfd_install_relocation subtracts them out again.  I think
15706
     bfd_install_relocation is broken, but I don't dare change
15707
     it.  FIXME.  */
15708
0
        value += fixP->fx_where + fixP->fx_frag->fr_address;
15709
0
      }
15710
0
  }
15711
0
#endif
15712
#if defined (OBJ_COFF) && defined (TE_PE)
15713
      /* For some reason, the PE format does not store a
15714
   section address offset for a PC relative symbol.  */
15715
      if (S_GET_SEGMENT (fixP->fx_addsy) != seg
15716
    || S_IS_WEAK (fixP->fx_addsy))
15717
  value += md_pcrel_from (fixP);
15718
#endif
15719
0
    }
15720
#if defined (OBJ_COFF) && defined (TE_PE)
15721
  if (fixP->fx_addsy != NULL
15722
      && S_IS_WEAK (fixP->fx_addsy)
15723
      /* PR 16858: Do not modify weak function references.  */
15724
      && ! fixP->fx_pcrel)
15725
    {
15726
#if !defined (TE_PEP)
15727
      /* For x86 PE weak function symbols are neither PC-relative
15728
   nor do they set S_IS_FUNCTION.  So the only reliable way
15729
   to detect them is to check the flags of their containing
15730
   section.  */
15731
      if (S_GET_SEGMENT (fixP->fx_addsy) != NULL
15732
    && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE)
15733
  ;
15734
      else
15735
#endif
15736
      value -= S_GET_VALUE (fixP->fx_addsy);
15737
    }
15738
#endif
15739
15740
  /* Fix a few things - the dynamic linker expects certain values here,
15741
     and we must not disappoint it.  */
15742
0
#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15743
0
  if (IS_ELF && fixP->fx_addsy)
15744
0
    switch (fixP->fx_r_type)
15745
0
      {
15746
0
      case BFD_RELOC_386_PLT32:
15747
0
      case BFD_RELOC_X86_64_PLT32:
15748
  /* Make the jump instruction point to the address of the operand.
15749
     At runtime we merely add the offset to the actual PLT entry.
15750
     NB: Subtract the offset size only for jump instructions.  */
15751
0
  if (fixP->fx_pcrel)
15752
0
    value = -4;
15753
0
  break;
15754
15755
0
      case BFD_RELOC_386_TLS_GD:
15756
0
      case BFD_RELOC_386_TLS_LDM:
15757
0
      case BFD_RELOC_386_TLS_IE_32:
15758
0
      case BFD_RELOC_386_TLS_IE:
15759
0
      case BFD_RELOC_386_TLS_GOTIE:
15760
0
      case BFD_RELOC_386_TLS_GOTDESC:
15761
0
      case BFD_RELOC_X86_64_TLSGD:
15762
0
      case BFD_RELOC_X86_64_TLSLD:
15763
0
      case BFD_RELOC_X86_64_GOTTPOFF:
15764
0
      case BFD_RELOC_X86_64_CODE_4_GOTTPOFF:
15765
0
      case BFD_RELOC_X86_64_CODE_6_GOTTPOFF:
15766
0
      case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
15767
0
      case BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC:
15768
0
  value = 0; /* Fully resolved at runtime.  No addend.  */
15769
  /* Fallthrough */
15770
0
      case BFD_RELOC_386_TLS_LE:
15771
0
      case BFD_RELOC_386_TLS_LDO_32:
15772
0
      case BFD_RELOC_386_TLS_LE_32:
15773
0
      case BFD_RELOC_X86_64_DTPOFF32:
15774
0
      case BFD_RELOC_X86_64_DTPOFF64:
15775
0
      case BFD_RELOC_X86_64_TPOFF32:
15776
0
      case BFD_RELOC_X86_64_TPOFF64:
15777
0
  S_SET_THREAD_LOCAL (fixP->fx_addsy);
15778
0
  break;
15779
15780
0
      case BFD_RELOC_386_TLS_DESC_CALL:
15781
0
      case BFD_RELOC_X86_64_TLSDESC_CALL:
15782
0
  value = 0; /* Fully resolved at runtime.  No addend.  */
15783
0
  S_SET_THREAD_LOCAL (fixP->fx_addsy);
15784
0
  fixP->fx_done = 0;
15785
0
  return;
15786
15787
0
      case BFD_RELOC_VTABLE_INHERIT:
15788
0
      case BFD_RELOC_VTABLE_ENTRY:
15789
0
  fixP->fx_done = 0;
15790
0
  return;
15791
15792
0
      default:
15793
0
  break;
15794
0
      }
15795
0
#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)  */
15796
15797
  /* If not 64bit, massage value, to account for wraparound when !BFD64.  */
15798
0
  if (!object_64bit)
15799
0
    value = extend_to_32bit_address (value);
15800
15801
0
  *valP = value;
15802
0
#endif /* !defined (TE_Mach)  */
15803
15804
  /* Are we finished with this relocation now?  */
15805
0
  if (fixP->fx_addsy == NULL)
15806
0
    {
15807
0
      fixP->fx_done = 1;
15808
0
      switch (fixP->fx_r_type)
15809
0
  {
15810
0
  case BFD_RELOC_X86_64_32S:
15811
0
    fixP->fx_signed = 1;
15812
0
    break;
15813
15814
0
  default:
15815
0
    break;
15816
0
  }
15817
0
    }
15818
#if defined (OBJ_COFF) && defined (TE_PE)
15819
  else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
15820
    {
15821
      fixP->fx_done = 0;
15822
      /* Remember value for tc_gen_reloc.  */
15823
      fixP->fx_addnumber = value;
15824
      /* Clear out the frag for now.  */
15825
      value = 0;
15826
    }
15827
#endif
15828
0
  else if (use_rela_relocations)
15829
0
    {
15830
0
      if (!disallow_64bit_reloc || fixP->fx_r_type == NO_RELOC)
15831
0
  fixP->fx_no_overflow = 1;
15832
      /* Remember value for tc_gen_reloc.  */
15833
0
      fixP->fx_addnumber = value;
15834
0
      value = 0;
15835
0
    }
15836
15837
0
  md_number_to_chars (p, value, fixP->fx_size);
15838
0
}
15839

15840
const char *
15841
md_atof (int type, char *litP, int *sizeP)
15842
10.9k
{
15843
  /* This outputs the LITTLENUMs in REVERSE order;
15844
     in accord with the bigendian 386.  */
15845
10.9k
  return ieee_md_atof (type, litP, sizeP, false);
15846
10.9k
}
15847

15848
static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
15849
15850
static char *
15851
output_invalid (int c)
15852
742k
{
15853
742k
  if (ISPRINT (c))
15854
111k
    snprintf (output_invalid_buf, sizeof (output_invalid_buf),
15855
111k
        "'%c'", c);
15856
630k
  else
15857
630k
    snprintf (output_invalid_buf, sizeof (output_invalid_buf),
15858
630k
        "(0x%x)", (unsigned char) c);
15859
742k
  return output_invalid_buf;
15860
742k
}
15861
15862
/* Verify that @r can be used in the current context.  */
15863
15864
static bool check_register (const reg_entry *r)
15865
2.09k
{
15866
2.09k
  if (allow_pseudo_reg)
15867
0
    return true;
15868
15869
2.09k
  if (operand_type_all_zero (&r->reg_type))
15870
51
    return false;
15871
15872
2.04k
  if ((r->reg_type.bitfield.dword
15873
2.04k
       || (r->reg_type.bitfield.class == SReg && r->reg_num > 3)
15874
2.04k
       || r->reg_type.bitfield.class == RegCR
15875
2.04k
       || r->reg_type.bitfield.class == RegDR)
15876
2.04k
      && !cpu_arch_flags.bitfield.cpui386)
15877
0
    return false;
15878
15879
2.04k
  if (r->reg_type.bitfield.class == RegTR
15880
2.04k
      && (flag_code == CODE_64BIT
15881
17
    || !cpu_arch_flags.bitfield.cpui386
15882
17
    || cpu_arch_isa_flags.bitfield.cpui586
15883
17
    || cpu_arch_isa_flags.bitfield.cpui686))
15884
17
    return false;
15885
15886
2.02k
  if (r->reg_type.bitfield.class == RegMMX && !cpu_arch_flags.bitfield.cpummx)
15887
0
    return false;
15888
15889
2.02k
  if (!cpu_arch_flags.bitfield.cpuavx512f)
15890
1.91k
    {
15891
1.91k
      if (r->reg_type.bitfield.zmmword
15892
1.91k
    || r->reg_type.bitfield.class == RegMask)
15893
0
  return false;
15894
15895
1.91k
      if (!cpu_arch_flags.bitfield.cpuavx)
15896
0
  {
15897
0
    if (r->reg_type.bitfield.ymmword)
15898
0
      return false;
15899
15900
0
    if (!cpu_arch_flags.bitfield.cpusse && r->reg_type.bitfield.xmmword)
15901
0
      return false;
15902
0
  }
15903
1.91k
    }
15904
15905
2.02k
  if (r->reg_type.bitfield.zmmword)
15906
46
    {
15907
46
      if (vector_size < VSZ512)
15908
0
  return false;
15909
15910
46
      switch (i.encoding)
15911
46
  {
15912
44
  case encoding_default:
15913
44
  case encoding_egpr:
15914
44
    i.encoding = encoding_evex512;
15915
44
    break;
15916
0
  case encoding_evex:
15917
2
  case encoding_evex512:
15918
2
    break;
15919
0
  default:
15920
0
    i.encoding = encoding_error;
15921
0
    break;
15922
46
  }
15923
46
    }
15924
15925
2.02k
  if (vector_size < VSZ256 && r->reg_type.bitfield.ymmword)
15926
0
    return false;
15927
15928
2.02k
  if (r->reg_type.bitfield.tmmword
15929
2.02k
      && (!cpu_arch_flags.bitfield.cpuamx_tile
15930
0
          || flag_code != CODE_64BIT))
15931
0
    return false;
15932
15933
2.02k
  if (r->reg_type.bitfield.class == RegBND && !cpu_arch_flags.bitfield.cpumpx)
15934
0
    return false;
15935
15936
  /* Don't allow fake index register unless allow_index_reg isn't 0. */
15937
2.02k
  if (!allow_index_reg && r->reg_num == RegIZ)
15938
0
    return false;
15939
15940
  /* Upper 16 vector registers are only available with VREX in 64bit
15941
     mode, and require EVEX encoding.  */
15942
2.02k
  if (r->reg_flags & RegVRex)
15943
0
    {
15944
0
      if (!cpu_arch_flags.bitfield.cpuavx512f
15945
0
    || flag_code != CODE_64BIT)
15946
0
  return false;
15947
15948
0
      switch (i.encoding)
15949
0
  {
15950
0
    case encoding_default:
15951
0
    case encoding_egpr:
15952
0
    case encoding_evex512:
15953
0
      i.encoding = encoding_evex;
15954
0
      break;
15955
0
    case encoding_evex:
15956
0
      break;
15957
0
    default:
15958
0
      i.encoding = encoding_error;
15959
0
      break;
15960
0
  }
15961
0
    }
15962
15963
2.02k
  if (r->reg_flags & RegRex2)
15964
0
    {
15965
0
      if (!cpu_arch_flags.bitfield.cpuapx_f
15966
0
    || flag_code != CODE_64BIT)
15967
0
  return false;
15968
15969
0
      switch (i.encoding)
15970
0
  {
15971
0
  case encoding_default:
15972
0
    i.encoding = encoding_egpr;
15973
0
    break;
15974
0
  case encoding_egpr:
15975
0
  case encoding_evex:
15976
0
  case encoding_evex512:
15977
0
    break;
15978
0
  default:
15979
0
    i.encoding = encoding_error;
15980
0
    break;
15981
0
  }
15982
0
    }
15983
15984
2.02k
  if (((r->reg_flags & (RegRex64 | RegRex)) || r->reg_type.bitfield.qword)
15985
2.02k
      && (!cpu_arch_flags.bitfield.cpu64
15986
6
    || r->reg_type.bitfield.class != RegCR
15987
6
    || dot_insn ())
15988
2.02k
      && flag_code != CODE_64BIT)
15989
6
    return false;
15990
15991
2.02k
  if (r->reg_type.bitfield.class == SReg && r->reg_num == RegFlat
15992
2.02k
      && !intel_syntax)
15993
0
    return false;
15994
15995
2.02k
  return true;
15996
2.02k
}
15997
15998
/* REG_STRING starts *before* REGISTER_PREFIX.  */
15999
16000
static const reg_entry *
16001
parse_real_register (const char *reg_string, char **end_op)
16002
112k
{
16003
112k
  const char *s = reg_string;
16004
112k
  char *p;
16005
112k
  char reg_name_given[MAX_REG_NAME_SIZE + 1];
16006
112k
  const reg_entry *r;
16007
16008
  /* Skip possible REGISTER_PREFIX and possible whitespace.  */
16009
112k
  if (*s == REGISTER_PREFIX)
16010
112k
    ++s;
16011
16012
112k
  if (is_space_char (*s))
16013
1.47k
    ++s;
16014
16015
112k
  p = reg_name_given;
16016
132k
  while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
16017
21.4k
    {
16018
21.4k
      if (p >= reg_name_given + MAX_REG_NAME_SIZE)
16019
2.01k
  return (const reg_entry *) NULL;
16020
19.4k
      s++;
16021
19.4k
    }
16022
16023
110k
  if (is_part_of_name (*s))
16024
59.6k
    return (const reg_entry *) NULL;
16025
16026
50.9k
  *end_op = (char *) s;
16027
16028
50.9k
  r = (const reg_entry *) str_hash_find (reg_hash, reg_name_given);
16029
16030
  /* Handle floating point regs, allowing spaces in the (i) part.  */
16031
50.9k
  if (r == reg_st0)
16032
30
    {
16033
30
      if (!cpu_arch_flags.bitfield.cpu8087
16034
30
    && !cpu_arch_flags.bitfield.cpu287
16035
30
    && !cpu_arch_flags.bitfield.cpu387
16036
30
    && !allow_pseudo_reg)
16037
0
  return (const reg_entry *) NULL;
16038
16039
30
      if (is_space_char (*s))
16040
0
  ++s;
16041
30
      if (*s == '(')
16042
0
  {
16043
0
    ++s;
16044
0
    if (is_space_char (*s))
16045
0
      ++s;
16046
0
    if (*s >= '0' && *s <= '7')
16047
0
      {
16048
0
        int fpr = *s - '0';
16049
0
        ++s;
16050
0
        if (is_space_char (*s))
16051
0
    ++s;
16052
0
        if (*s == ')')
16053
0
    {
16054
0
      *end_op = (char *) s + 1;
16055
0
      know (r[fpr].reg_num == fpr);
16056
0
      return r + fpr;
16057
0
    }
16058
0
      }
16059
    /* We have "%st(" then garbage.  */
16060
0
    return (const reg_entry *) NULL;
16061
0
  }
16062
30
    }
16063
16064
50.9k
  return r && check_register (r) ? r : NULL;
16065
50.9k
}
16066
16067
/* REG_STRING starts *before* REGISTER_PREFIX.  */
16068
16069
static const reg_entry *
16070
parse_register (const char *reg_string, char **end_op)
16071
97.1k
{
16072
97.1k
  const reg_entry *r;
16073
16074
97.1k
  if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
16075
52
    r = parse_real_register (reg_string, end_op);
16076
97.1k
  else
16077
97.1k
    r = NULL;
16078
97.1k
  if (!r)
16079
97.1k
    {
16080
97.1k
      char *save = input_line_pointer;
16081
97.1k
      char *buf = xstrdup (reg_string), *name;
16082
97.1k
      symbolS *symbolP;
16083
16084
97.1k
      input_line_pointer = buf;
16085
97.1k
      get_symbol_name (&name);
16086
97.1k
      symbolP = symbol_find (name);
16087
97.3k
      while (symbolP && symbol_equated_p (symbolP))
16088
163
  {
16089
163
    const expressionS *e = symbol_get_value_expression(symbolP);
16090
16091
163
    if (e->X_add_number)
16092
0
      break;
16093
163
    symbolP = e->X_add_symbol;
16094
163
  }
16095
97.1k
      if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
16096
133
  {
16097
133
    const expressionS *e = symbol_get_value_expression (symbolP);
16098
16099
133
    if (e->X_op == O_register)
16100
60
      {
16101
60
        know (e->X_add_number >= 0
16102
60
        && (valueT) e->X_add_number < i386_regtab_size);
16103
60
        r = i386_regtab + e->X_add_number;
16104
60
        *end_op = (char *) reg_string + (input_line_pointer - buf);
16105
60
      }
16106
133
    if (r && !check_register (r))
16107
0
      {
16108
0
        as_bad (_("register '%s%s' cannot be used here"),
16109
0
          register_prefix, r->reg_name);
16110
0
        r = &bad_reg;
16111
0
      }
16112
133
  }
16113
97.1k
      input_line_pointer = save;
16114
97.1k
      free (buf);
16115
97.1k
    }
16116
97.1k
  return r;
16117
97.1k
}
16118
16119
int
16120
i386_parse_name (char *name, expressionS *e, char *nextcharP)
16121
445k
{
16122
445k
  const reg_entry *r = NULL;
16123
445k
  char *end = input_line_pointer;
16124
16125
  /* We only know the terminating character here.  It being double quote could
16126
     be the closing one of a quoted symbol name, or an opening one from a
16127
     following string (or another quoted symbol name).  Since the latter can't
16128
     be valid syntax for anything, bailing in either case is good enough.  */
16129
445k
  if (*nextcharP == '"')
16130
8.02k
    return 0;
16131
16132
437k
  *end = *nextcharP;
16133
437k
  if (*name == REGISTER_PREFIX || allow_naked_reg)
16134
217
    r = parse_real_register (name, &input_line_pointer);
16135
437k
  if (r && end <= input_line_pointer)
16136
0
    {
16137
0
      *nextcharP = *input_line_pointer;
16138
0
      *input_line_pointer = 0;
16139
0
      e->X_op = O_register;
16140
0
      e->X_add_number = r - i386_regtab;
16141
0
      return 1;
16142
0
    }
16143
437k
  input_line_pointer = end;
16144
437k
  *end = 0;
16145
437k
  return intel_syntax ? i386_intel_parse_name (name, e) : 0;
16146
437k
}
16147
16148
void
16149
md_operand (expressionS *e)
16150
200k
{
16151
200k
  char *end;
16152
200k
  const reg_entry *r;
16153
16154
200k
  switch (*input_line_pointer)
16155
200k
    {
16156
112k
    case REGISTER_PREFIX:
16157
112k
      r = parse_real_register (input_line_pointer, &end);
16158
112k
      if (r)
16159
1.95k
  {
16160
1.95k
    e->X_op = O_register;
16161
1.95k
    e->X_add_number = r - i386_regtab;
16162
1.95k
    input_line_pointer = end;
16163
1.95k
  }
16164
112k
      break;
16165
16166
0
    case '[':
16167
0
      gas_assert (intel_syntax);
16168
0
      end = input_line_pointer++;
16169
0
      expression (e);
16170
0
      if (*input_line_pointer == ']')
16171
0
  {
16172
0
    ++input_line_pointer;
16173
0
    e->X_op_symbol = make_expr_symbol (e);
16174
0
    e->X_add_symbol = NULL;
16175
0
    e->X_add_number = 0;
16176
0
    e->X_op = O_index;
16177
0
  }
16178
0
      else
16179
0
  {
16180
0
    e->X_op = O_absent;
16181
0
    input_line_pointer = end;
16182
0
  }
16183
0
      break;
16184
200k
    }
16185
200k
}
16186
16187
#ifdef BFD64
16188
/* To maintain consistency with !BFD64 builds of gas record, whether any
16189
   (binary) operator was involved in an expression.  As expressions are
16190
   evaluated in only 32 bits when !BFD64, we use this to decide whether to
16191
   truncate results.  */
16192
bool i386_record_operator (operatorT op,
16193
         const expressionS *left,
16194
         const expressionS *right)
16195
792k
{
16196
792k
  if (op == O_absent)
16197
52.5k
    return false;
16198
16199
739k
  if (!left)
16200
223k
    {
16201
      /* Since the expression parser applies unary operators fine to bignum
16202
   operands, we don't need to be concerned of respective operands not
16203
   fitting in 32 bits.  */
16204
223k
      if (right->X_op == O_constant && right->X_unsigned
16205
223k
    && !fits_in_unsigned_long (right->X_add_number))
16206
2.69k
  return false;
16207
223k
    }
16208
  /* This isn't entirely right: The pattern can also result when constant
16209
     expressions are folded (e.g. 0xffffffff + 1).  */
16210
516k
  else if ((left->X_op == O_constant && left->X_unsigned
16211
516k
      && !fits_in_unsigned_long (left->X_add_number))
16212
516k
     || (right->X_op == O_constant && right->X_unsigned
16213
510k
         && !fits_in_unsigned_long (right->X_add_number)))
16214
25.7k
    expr_mode = expr_large_value;
16215
16216
737k
  if (expr_mode != expr_large_value)
16217
589k
    expr_mode = expr_operator_present;
16218
16219
737k
  return false;
16220
739k
}
16221
#endif
16222

16223
#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
16224
const char *md_shortopts = "kVQ:sqnO::";
16225
#else
16226
const char *md_shortopts = "qnO::";
16227
#endif
16228
16229
0
#define OPTION_32 (OPTION_MD_BASE + 0)
16230
0
#define OPTION_64 (OPTION_MD_BASE + 1)
16231
0
#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
16232
0
#define OPTION_MARCH (OPTION_MD_BASE + 3)
16233
0
#define OPTION_MTUNE (OPTION_MD_BASE + 4)
16234
0
#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
16235
0
#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
16236
0
#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
16237
0
#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
16238
0
#define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
16239
0
#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
16240
0
#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
16241
0
#define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
16242
0
#define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
16243
0
#define OPTION_X32 (OPTION_MD_BASE + 14)
16244
0
#define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
16245
0
#define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
16246
0
#define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
16247
#define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
16248
0
#define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
16249
0
#define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
16250
0
#define OPTION_MSHARED (OPTION_MD_BASE + 21)
16251
0
#define OPTION_MAMD64 (OPTION_MD_BASE + 22)
16252
0
#define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
16253
0
#define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
16254
0
#define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25)
16255
0
#define OPTION_MVEXWIG (OPTION_MD_BASE + 26)
16256
0
#define OPTION_MALIGN_BRANCH_BOUNDARY (OPTION_MD_BASE + 27)
16257
0
#define OPTION_MALIGN_BRANCH_PREFIX_SIZE (OPTION_MD_BASE + 28)
16258
0
#define OPTION_MALIGN_BRANCH (OPTION_MD_BASE + 29)
16259
0
#define OPTION_MBRANCHES_WITH_32B_BOUNDARIES (OPTION_MD_BASE + 30)
16260
0
#define OPTION_MLFENCE_AFTER_LOAD (OPTION_MD_BASE + 31)
16261
0
#define OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH (OPTION_MD_BASE + 32)
16262
0
#define OPTION_MLFENCE_BEFORE_RET (OPTION_MD_BASE + 33)
16263
0
#define OPTION_MUSE_UNALIGNED_VECTOR_MOVE (OPTION_MD_BASE + 34)
16264
16265
struct option md_longopts[] =
16266
{
16267
  {"32", no_argument, NULL, OPTION_32},
16268
#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
16269
     || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
16270
  {"64", no_argument, NULL, OPTION_64},
16271
#endif
16272
#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
16273
  {"x32", no_argument, NULL, OPTION_X32},
16274
  {"mshared", no_argument, NULL, OPTION_MSHARED},
16275
  {"mx86-used-note", required_argument, NULL, OPTION_X86_USED_NOTE},
16276
#endif
16277
  {"divide", no_argument, NULL, OPTION_DIVIDE},
16278
  {"march", required_argument, NULL, OPTION_MARCH},
16279
  {"mtune", required_argument, NULL, OPTION_MTUNE},
16280
  {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
16281
  {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
16282
  {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
16283
  {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
16284
  {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
16285
  {"muse-unaligned-vector-move", no_argument, NULL, OPTION_MUSE_UNALIGNED_VECTOR_MOVE},
16286
  {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
16287
  {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
16288
  {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
16289
  {"mvexwig", required_argument, NULL, OPTION_MVEXWIG},
16290
  {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
16291
  {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG},
16292
  {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG},
16293
# if defined (TE_PE) || defined (TE_PEP)
16294
  {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ},
16295
#endif
16296
  {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX},
16297
  {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD},
16298
  {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS},
16299
  {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG},
16300
  {"malign-branch-boundary", required_argument, NULL, OPTION_MALIGN_BRANCH_BOUNDARY},
16301
  {"malign-branch-prefix-size", required_argument, NULL, OPTION_MALIGN_BRANCH_PREFIX_SIZE},
16302
  {"malign-branch", required_argument, NULL, OPTION_MALIGN_BRANCH},
16303
  {"mbranches-within-32B-boundaries", no_argument, NULL, OPTION_MBRANCHES_WITH_32B_BOUNDARIES},
16304
  {"mlfence-after-load", required_argument, NULL, OPTION_MLFENCE_AFTER_LOAD},
16305
  {"mlfence-before-indirect-branch", required_argument, NULL,
16306
   OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH},
16307
  {"mlfence-before-ret", required_argument, NULL, OPTION_MLFENCE_BEFORE_RET},
16308
  {"mamd64", no_argument, NULL, OPTION_MAMD64},
16309
  {"mintel64", no_argument, NULL, OPTION_MINTEL64},
16310
  {NULL, no_argument, NULL, 0}
16311
};
16312
size_t md_longopts_size = sizeof (md_longopts);
16313
16314
int
16315
md_parse_option (int c, const char *arg)
16316
0
{
16317
0
  unsigned int j;
16318
0
  char *arch, *next, *saved, *type;
16319
16320
0
  switch (c)
16321
0
    {
16322
0
    case 'n':
16323
0
      optimize_align_code = 0;
16324
0
      break;
16325
16326
0
    case 'q':
16327
0
      quiet_warnings = 1;
16328
0
      break;
16329
16330
0
#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
16331
      /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
16332
   should be emitted or not.  FIXME: Not implemented.  */
16333
0
    case 'Q':
16334
0
      if ((arg[0] != 'y' && arg[0] != 'n') || arg[1])
16335
0
  return 0;
16336
0
      break;
16337
16338
      /* -V: SVR4 argument to print version ID.  */
16339
0
    case 'V':
16340
0
      print_version_id ();
16341
0
      break;
16342
16343
      /* -k: Ignore for FreeBSD compatibility.  */
16344
0
    case 'k':
16345
0
      break;
16346
16347
0
    case 's':
16348
      /* -s: On i386 Solaris, this tells the native assembler to use
16349
   .stab instead of .stab.excl.  We always use .stab anyhow.  */
16350
0
      break;
16351
16352
0
    case OPTION_MSHARED:
16353
0
      shared = 1;
16354
0
      break;
16355
16356
0
    case OPTION_X86_USED_NOTE:
16357
0
      if (strcasecmp (arg, "yes") == 0)
16358
0
        x86_used_note = 1;
16359
0
      else if (strcasecmp (arg, "no") == 0)
16360
0
        x86_used_note = 0;
16361
0
      else
16362
0
        as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg);
16363
0
      break;
16364
16365
16366
0
#endif
16367
0
#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
16368
0
     || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
16369
0
    case OPTION_64:
16370
0
      {
16371
0
  const char **list, **l;
16372
16373
0
  list = bfd_target_list ();
16374
0
  for (l = list; *l != NULL; l++)
16375
0
    if (startswith (*l, "elf64-x86-64")
16376
0
        || strcmp (*l, "coff-x86-64") == 0
16377
0
        || strcmp (*l, "pe-x86-64") == 0
16378
0
        || strcmp (*l, "pei-x86-64") == 0
16379
0
        || strcmp (*l, "mach-o-x86-64") == 0)
16380
0
      {
16381
0
        default_arch = "x86_64";
16382
0
        break;
16383
0
      }
16384
0
  if (*l == NULL)
16385
0
    as_fatal (_("no compiled in support for x86_64"));
16386
0
  free (list);
16387
0
      }
16388
0
      break;
16389
0
#endif
16390
16391
0
#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
16392
0
    case OPTION_X32:
16393
0
      if (IS_ELF)
16394
0
  {
16395
0
    const char **list, **l;
16396
16397
0
    list = bfd_target_list ();
16398
0
    for (l = list; *l != NULL; l++)
16399
0
      if (startswith (*l, "elf32-x86-64"))
16400
0
        {
16401
0
    default_arch = "x86_64:32";
16402
0
    break;
16403
0
        }
16404
0
    if (*l == NULL)
16405
0
      as_fatal (_("no compiled in support for 32bit x86_64"));
16406
0
    free (list);
16407
0
  }
16408
0
      else
16409
0
  as_fatal (_("32bit x86_64 is only supported for ELF"));
16410
0
      break;
16411
0
#endif
16412
16413
0
    case OPTION_32:
16414
0
      {
16415
0
  const char **list, **l;
16416
16417
0
  list = bfd_target_list ();
16418
0
  for (l = list; *l != NULL; l++)
16419
0
    if (strstr (*l, "-i386")
16420
0
        || strstr (*l, "-go32"))
16421
0
      {
16422
0
        default_arch = "i386";
16423
0
        break;
16424
0
      }
16425
0
  if (*l == NULL)
16426
0
    as_fatal (_("no compiled in support for ix86"));
16427
0
  free (list);
16428
0
      }
16429
0
      break;
16430
16431
0
    case OPTION_DIVIDE:
16432
#ifdef SVR4_COMMENT_CHARS
16433
      {
16434
  char *n, *t;
16435
  const char *s;
16436
16437
  n = XNEWVEC (char, strlen (i386_comment_chars) + 1);
16438
  t = n;
16439
  for (s = i386_comment_chars; *s != '\0'; s++)
16440
    if (*s != '/')
16441
      *t++ = *s;
16442
  *t = '\0';
16443
  i386_comment_chars = n;
16444
      }
16445
#endif
16446
0
      break;
16447
16448
0
    case OPTION_MARCH:
16449
0
      saved = xstrdup (arg);
16450
0
      arch = saved;
16451
      /* Allow -march=+nosse.  */
16452
0
      if (*arch == '+')
16453
0
  arch++;
16454
0
      do
16455
0
  {
16456
0
    char *vsz;
16457
16458
0
    if (*arch == '.')
16459
0
      as_fatal (_("invalid -march= option: `%s'"), arg);
16460
0
    next = strchr (arch, '+');
16461
0
    if (next)
16462
0
      *next++ = '\0';
16463
0
    vsz = strchr (arch, '/');
16464
0
    if (vsz)
16465
0
      *vsz++ = '\0';
16466
0
    for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
16467
0
      {
16468
0
        if (vsz && cpu_arch[j].vsz != vsz_set)
16469
0
    continue;
16470
16471
0
        if (arch == saved && cpu_arch[j].type != PROCESSOR_NONE
16472
0
            && strcmp (arch, cpu_arch[j].name) == 0)
16473
0
    {
16474
      /* Processor.  */
16475
0
      if (! cpu_arch[j].enable.bitfield.cpui386)
16476
0
        continue;
16477
16478
0
      cpu_arch_name = cpu_arch[j].name;
16479
0
      free (cpu_sub_arch_name);
16480
0
      cpu_sub_arch_name = NULL;
16481
0
      cpu_arch_flags = cpu_arch[j].enable;
16482
0
      cpu_arch_isa = cpu_arch[j].type;
16483
0
      cpu_arch_isa_flags = cpu_arch[j].enable;
16484
0
      if (!cpu_arch_tune_set)
16485
0
        cpu_arch_tune = cpu_arch_isa;
16486
0
      vector_size = VSZ_DEFAULT;
16487
0
      break;
16488
0
    }
16489
0
        else if (cpu_arch[j].type == PROCESSOR_NONE
16490
0
           && strcmp (arch, cpu_arch[j].name) == 0
16491
0
           && !cpu_flags_all_zero (&cpu_arch[j].enable))
16492
0
    {
16493
      /* ISA extension.  */
16494
0
      isa_enable (j);
16495
16496
0
      switch (cpu_arch[j].vsz)
16497
0
        {
16498
0
        default:
16499
0
          break;
16500
16501
0
        case vsz_set:
16502
0
          if (vsz)
16503
0
      {
16504
0
        char *end;
16505
0
        unsigned long val = strtoul (vsz, &end, 0);
16506
16507
0
        if (*end)
16508
0
          val = 0;
16509
0
        switch (val)
16510
0
          {
16511
0
          case 512: vector_size = VSZ512; break;
16512
0
          case 256: vector_size = VSZ256; break;
16513
0
          case 128: vector_size = VSZ128; break;
16514
0
          default:
16515
0
            as_warn (_("Unrecognized vector size specifier ignored"));
16516
0
            break;
16517
0
          }
16518
0
        break;
16519
0
      }
16520
      /* Fall through.  */
16521
0
        case vsz_reset:
16522
0
          vector_size = VSZ_DEFAULT;
16523
0
          break;
16524
0
        }
16525
16526
0
      break;
16527
0
    }
16528
0
      }
16529
16530
0
    if (j >= ARRAY_SIZE (cpu_arch) && startswith (arch, "no"))
16531
0
      {
16532
        /* Disable an ISA extension.  */
16533
0
        for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
16534
0
    if (cpu_arch[j].type == PROCESSOR_NONE
16535
0
        && strcmp (arch + 2, cpu_arch[j].name) == 0)
16536
0
      {
16537
0
        isa_disable (j);
16538
0
        if (cpu_arch[j].vsz == vsz_set)
16539
0
          vector_size = VSZ_DEFAULT;
16540
0
        break;
16541
0
      }
16542
0
      }
16543
16544
0
    if (j >= ARRAY_SIZE (cpu_arch))
16545
0
      as_fatal (_("invalid -march= option: `%s'"), arg);
16546
16547
0
    arch = next;
16548
0
  }
16549
0
      while (next != NULL);
16550
0
      free (saved);
16551
0
      break;
16552
16553
0
    case OPTION_MTUNE:
16554
0
      if (*arg == '.')
16555
0
  as_fatal (_("invalid -mtune= option: `%s'"), arg);
16556
0
      for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
16557
0
  {
16558
0
    if (cpu_arch[j].type != PROCESSOR_NONE
16559
0
        && strcmp (arg, cpu_arch[j].name) == 0)
16560
0
      {
16561
0
        cpu_arch_tune_set = 1;
16562
0
        cpu_arch_tune = cpu_arch [j].type;
16563
0
        break;
16564
0
      }
16565
0
  }
16566
0
      if (j >= ARRAY_SIZE (cpu_arch))
16567
0
  as_fatal (_("invalid -mtune= option: `%s'"), arg);
16568
0
      break;
16569
16570
0
    case OPTION_MMNEMONIC:
16571
0
      if (strcasecmp (arg, "att") == 0)
16572
0
  intel_mnemonic = 0;
16573
0
      else if (strcasecmp (arg, "intel") == 0)
16574
0
  intel_mnemonic = 1;
16575
0
      else
16576
0
  as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
16577
0
      break;
16578
16579
0
    case OPTION_MSYNTAX:
16580
0
      if (strcasecmp (arg, "att") == 0)
16581
0
  _set_intel_syntax (0);
16582
0
      else if (strcasecmp (arg, "intel") == 0)
16583
0
  _set_intel_syntax (1);
16584
0
      else
16585
0
  as_fatal (_("invalid -msyntax= option: `%s'"), arg);
16586
0
      break;
16587
16588
0
    case OPTION_MINDEX_REG:
16589
0
      allow_index_reg = 1;
16590
0
      break;
16591
16592
0
    case OPTION_MNAKED_REG:
16593
0
      allow_naked_reg = 1;
16594
0
      register_prefix = "";
16595
0
      break;
16596
16597
0
    case OPTION_MSSE2AVX:
16598
0
      sse2avx = 1;
16599
0
      break;
16600
16601
0
    case OPTION_MUSE_UNALIGNED_VECTOR_MOVE:
16602
0
      use_unaligned_vector_move = 1;
16603
0
      break;
16604
16605
0
    case OPTION_MSSE_CHECK:
16606
0
      if (strcasecmp (arg, "error") == 0)
16607
0
  sse_check = check_error;
16608
0
      else if (strcasecmp (arg, "warning") == 0)
16609
0
  sse_check = check_warning;
16610
0
      else if (strcasecmp (arg, "none") == 0)
16611
0
  sse_check = check_none;
16612
0
      else
16613
0
  as_fatal (_("invalid -msse-check= option: `%s'"), arg);
16614
0
      break;
16615
16616
0
    case OPTION_MOPERAND_CHECK:
16617
0
      if (strcasecmp (arg, "error") == 0)
16618
0
  operand_check = check_error;
16619
0
      else if (strcasecmp (arg, "warning") == 0)
16620
0
  operand_check = check_warning;
16621
0
      else if (strcasecmp (arg, "none") == 0)
16622
0
  operand_check = check_none;
16623
0
      else
16624
0
  as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
16625
0
      break;
16626
16627
0
    case OPTION_MAVXSCALAR:
16628
0
      if (strcasecmp (arg, "128") == 0)
16629
0
  avxscalar = vex128;
16630
0
      else if (strcasecmp (arg, "256") == 0)
16631
0
  avxscalar = vex256;
16632
0
      else
16633
0
  as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
16634
0
      break;
16635
16636
0
    case OPTION_MVEXWIG:
16637
0
      if (strcmp (arg, "0") == 0)
16638
0
  vexwig = vexw0;
16639
0
      else if (strcmp (arg, "1") == 0)
16640
0
  vexwig = vexw1;
16641
0
      else
16642
0
  as_fatal (_("invalid -mvexwig= option: `%s'"), arg);
16643
0
      break;
16644
16645
0
    case OPTION_MADD_BND_PREFIX:
16646
0
      add_bnd_prefix = 1;
16647
0
      break;
16648
16649
0
    case OPTION_MEVEXLIG:
16650
0
      if (strcmp (arg, "128") == 0)
16651
0
  evexlig = evexl128;
16652
0
      else if (strcmp (arg, "256") == 0)
16653
0
  evexlig = evexl256;
16654
0
      else  if (strcmp (arg, "512") == 0)
16655
0
  evexlig = evexl512;
16656
0
      else
16657
0
  as_fatal (_("invalid -mevexlig= option: `%s'"), arg);
16658
0
      break;
16659
16660
0
    case OPTION_MEVEXRCIG:
16661
0
      if (strcmp (arg, "rne") == 0)
16662
0
  evexrcig = rne;
16663
0
      else if (strcmp (arg, "rd") == 0)
16664
0
  evexrcig = rd;
16665
0
      else if (strcmp (arg, "ru") == 0)
16666
0
  evexrcig = ru;
16667
0
      else if (strcmp (arg, "rz") == 0)
16668
0
  evexrcig = rz;
16669
0
      else
16670
0
  as_fatal (_("invalid -mevexrcig= option: `%s'"), arg);
16671
0
      break;
16672
16673
0
    case OPTION_MEVEXWIG:
16674
0
      if (strcmp (arg, "0") == 0)
16675
0
  evexwig = evexw0;
16676
0
      else if (strcmp (arg, "1") == 0)
16677
0
  evexwig = evexw1;
16678
0
      else
16679
0
  as_fatal (_("invalid -mevexwig= option: `%s'"), arg);
16680
0
      break;
16681
16682
# if defined (TE_PE) || defined (TE_PEP)
16683
    case OPTION_MBIG_OBJ:
16684
      use_big_obj = 1;
16685
      break;
16686
#endif
16687
16688
0
    case OPTION_MOMIT_LOCK_PREFIX:
16689
0
      if (strcasecmp (arg, "yes") == 0)
16690
0
        omit_lock_prefix = 1;
16691
0
      else if (strcasecmp (arg, "no") == 0)
16692
0
        omit_lock_prefix = 0;
16693
0
      else
16694
0
        as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg);
16695
0
      break;
16696
16697
0
    case OPTION_MFENCE_AS_LOCK_ADD:
16698
0
      if (strcasecmp (arg, "yes") == 0)
16699
0
        avoid_fence = 1;
16700
0
      else if (strcasecmp (arg, "no") == 0)
16701
0
        avoid_fence = 0;
16702
0
      else
16703
0
        as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg);
16704
0
      break;
16705
16706
0
    case OPTION_MLFENCE_AFTER_LOAD:
16707
0
      if (strcasecmp (arg, "yes") == 0)
16708
0
  lfence_after_load = 1;
16709
0
      else if (strcasecmp (arg, "no") == 0)
16710
0
  lfence_after_load = 0;
16711
0
      else
16712
0
        as_fatal (_("invalid -mlfence-after-load= option: `%s'"), arg);
16713
0
      break;
16714
16715
0
    case OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH:
16716
0
      if (strcasecmp (arg, "all") == 0)
16717
0
  {
16718
0
    lfence_before_indirect_branch = lfence_branch_all;
16719
0
    if (lfence_before_ret == lfence_before_ret_none)
16720
0
      lfence_before_ret = lfence_before_ret_shl;
16721
0
  }
16722
0
      else if (strcasecmp (arg, "memory") == 0)
16723
0
  lfence_before_indirect_branch = lfence_branch_memory;
16724
0
      else if (strcasecmp (arg, "register") == 0)
16725
0
  lfence_before_indirect_branch = lfence_branch_register;
16726
0
      else if (strcasecmp (arg, "none") == 0)
16727
0
  lfence_before_indirect_branch = lfence_branch_none;
16728
0
      else
16729
0
        as_fatal (_("invalid -mlfence-before-indirect-branch= option: `%s'"),
16730
0
      arg);
16731
0
      break;
16732
16733
0
    case OPTION_MLFENCE_BEFORE_RET:
16734
0
      if (strcasecmp (arg, "or") == 0)
16735
0
  lfence_before_ret = lfence_before_ret_or;
16736
0
      else if (strcasecmp (arg, "not") == 0)
16737
0
  lfence_before_ret = lfence_before_ret_not;
16738
0
      else if (strcasecmp (arg, "shl") == 0 || strcasecmp (arg, "yes") == 0)
16739
0
  lfence_before_ret = lfence_before_ret_shl;
16740
0
      else if (strcasecmp (arg, "none") == 0)
16741
0
  lfence_before_ret = lfence_before_ret_none;
16742
0
      else
16743
0
        as_fatal (_("invalid -mlfence-before-ret= option: `%s'"),
16744
0
      arg);
16745
0
      break;
16746
16747
0
    case OPTION_MRELAX_RELOCATIONS:
16748
0
      if (strcasecmp (arg, "yes") == 0)
16749
0
        generate_relax_relocations = 1;
16750
0
      else if (strcasecmp (arg, "no") == 0)
16751
0
        generate_relax_relocations = 0;
16752
0
      else
16753
0
        as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg);
16754
0
      break;
16755
16756
0
    case OPTION_MALIGN_BRANCH_BOUNDARY:
16757
0
      {
16758
0
  char *end;
16759
0
  long int align = strtoul (arg, &end, 0);
16760
0
  if (*end == '\0')
16761
0
    {
16762
0
      if (align == 0)
16763
0
        {
16764
0
    align_branch_power = 0;
16765
0
    break;
16766
0
        }
16767
0
      else if (align >= 16)
16768
0
        {
16769
0
    int align_power;
16770
0
    for (align_power = 0;
16771
0
         (align & 1) == 0;
16772
0
         align >>= 1, align_power++)
16773
0
      continue;
16774
    /* Limit alignment power to 31.  */
16775
0
    if (align == 1 && align_power < 32)
16776
0
      {
16777
0
        align_branch_power = align_power;
16778
0
        break;
16779
0
      }
16780
0
        }
16781
0
    }
16782
0
  as_fatal (_("invalid -malign-branch-boundary= value: %s"), arg);
16783
0
      }
16784
0
      break;
16785
16786
0
    case OPTION_MALIGN_BRANCH_PREFIX_SIZE:
16787
0
      {
16788
0
  char *end;
16789
0
  int align = strtoul (arg, &end, 0);
16790
  /* Some processors only support 5 prefixes.  */
16791
0
  if (*end == '\0' && align >= 0 && align < 6)
16792
0
    {
16793
0
      align_branch_prefix_size = align;
16794
0
      break;
16795
0
    }
16796
0
  as_fatal (_("invalid -malign-branch-prefix-size= value: %s"),
16797
0
      arg);
16798
0
      }
16799
0
      break;
16800
16801
0
    case OPTION_MALIGN_BRANCH:
16802
0
      align_branch = 0;
16803
0
      saved = xstrdup (arg);
16804
0
      type = saved;
16805
0
      do
16806
0
  {
16807
0
    next = strchr (type, '+');
16808
0
    if (next)
16809
0
      *next++ = '\0';
16810
0
    if (strcasecmp (type, "jcc") == 0)
16811
0
      align_branch |= align_branch_jcc_bit;
16812
0
    else if (strcasecmp (type, "fused") == 0)
16813
0
      align_branch |= align_branch_fused_bit;
16814
0
    else if (strcasecmp (type, "jmp") == 0)
16815
0
      align_branch |= align_branch_jmp_bit;
16816
0
    else if (strcasecmp (type, "call") == 0)
16817
0
      align_branch |= align_branch_call_bit;
16818
0
    else if (strcasecmp (type, "ret") == 0)
16819
0
      align_branch |= align_branch_ret_bit;
16820
0
    else if (strcasecmp (type, "indirect") == 0)
16821
0
      align_branch |= align_branch_indirect_bit;
16822
0
    else
16823
0
      as_fatal (_("invalid -malign-branch= option: `%s'"), arg);
16824
0
    type = next;
16825
0
  }
16826
0
      while (next != NULL);
16827
0
      free (saved);
16828
0
      break;
16829
16830
0
    case OPTION_MBRANCHES_WITH_32B_BOUNDARIES:
16831
0
      align_branch_power = 5;
16832
0
      align_branch_prefix_size = 5;
16833
0
      align_branch = (align_branch_jcc_bit
16834
0
          | align_branch_fused_bit
16835
0
          | align_branch_jmp_bit);
16836
0
      break;
16837
16838
0
    case OPTION_MAMD64:
16839
0
      isa64 = amd64;
16840
0
      break;
16841
16842
0
    case OPTION_MINTEL64:
16843
0
      isa64 = intel64;
16844
0
      break;
16845
16846
0
    case 'O':
16847
0
      if (arg == NULL)
16848
0
  {
16849
0
    optimize = 1;
16850
    /* Turn off -Os.  */
16851
0
    optimize_for_space = 0;
16852
0
  }
16853
0
      else if (*arg == 's')
16854
0
  {
16855
0
    optimize_for_space = 1;
16856
    /* Turn on all encoding optimizations.  */
16857
0
    optimize = INT_MAX;
16858
0
  }
16859
0
      else
16860
0
  {
16861
0
    optimize = atoi (arg);
16862
    /* Turn off -Os.  */
16863
0
    optimize_for_space = 0;
16864
0
  }
16865
0
      break;
16866
16867
0
    default:
16868
0
      return 0;
16869
0
    }
16870
0
  return 1;
16871
0
}
16872
16873
0
#define MESSAGE_TEMPLATE \
16874
0
"                                                                                "
16875
16876
static char *
16877
output_message (FILE *stream, char *p, char *message, char *start,
16878
    int *left_p, const char *name, int len)
16879
0
{
16880
0
  int size = sizeof (MESSAGE_TEMPLATE);
16881
0
  int left = *left_p;
16882
16883
  /* Reserve 2 spaces for ", " or ",\0" */
16884
0
  left -= len + 2;
16885
16886
  /* Check if there is any room.  */
16887
0
  if (left >= 0)
16888
0
    {
16889
0
      if (p != start)
16890
0
  {
16891
0
    *p++ = ',';
16892
0
    *p++ = ' ';
16893
0
  }
16894
0
      p = mempcpy (p, name, len);
16895
0
    }
16896
0
  else
16897
0
    {
16898
      /* Output the current message now and start a new one.  */
16899
0
      *p++ = ',';
16900
0
      *p = '\0';
16901
0
      fprintf (stream, "%s\n", message);
16902
0
      p = start;
16903
0
      left = size - (start - message) - len - 2;
16904
16905
0
      gas_assert (left >= 0);
16906
16907
0
      p = mempcpy (p, name, len);
16908
0
    }
16909
16910
0
  *left_p = left;
16911
0
  return p;
16912
0
}
16913
16914
static void
16915
show_arch (FILE *stream, int ext, int check)
16916
0
{
16917
0
  static char message[] = MESSAGE_TEMPLATE;
16918
0
  char *start = message + 27;
16919
0
  char *p;
16920
0
  int size = sizeof (MESSAGE_TEMPLATE);
16921
0
  int left;
16922
0
  const char *name;
16923
0
  int len;
16924
0
  unsigned int j;
16925
16926
0
  p = start;
16927
0
  left = size - (start - message);
16928
16929
0
  if (!ext && check)
16930
0
    {
16931
0
      p = output_message (stream, p, message, start, &left,
16932
0
        STRING_COMMA_LEN ("default"));
16933
0
      p = output_message (stream, p, message, start, &left,
16934
0
        STRING_COMMA_LEN ("push"));
16935
0
      p = output_message (stream, p, message, start, &left,
16936
0
        STRING_COMMA_LEN ("pop"));
16937
0
    }
16938
16939
0
  for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
16940
0
    {
16941
      /* Should it be skipped?  */
16942
0
      if (cpu_arch [j].skip)
16943
0
  continue;
16944
16945
0
      name = cpu_arch [j].name;
16946
0
      len = cpu_arch [j].len;
16947
0
      if (cpu_arch[j].type == PROCESSOR_NONE)
16948
0
  {
16949
    /* It is an extension.  Skip if we aren't asked to show it.  */
16950
0
    if (!ext || cpu_flags_all_zero (&cpu_arch[j].enable))
16951
0
      continue;
16952
0
  }
16953
0
      else if (ext)
16954
0
  {
16955
    /* It is an processor.  Skip if we show only extension.  */
16956
0
    continue;
16957
0
  }
16958
0
      else if (check && ! cpu_arch[j].enable.bitfield.cpui386)
16959
0
  {
16960
    /* It is an impossible processor - skip.  */
16961
0
    continue;
16962
0
  }
16963
16964
0
      p = output_message (stream, p, message, start, &left, name, len);
16965
0
    }
16966
16967
  /* Display disabled extensions.  */
16968
0
  if (ext)
16969
0
    for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
16970
0
      {
16971
0
  char *str;
16972
16973
0
  if (cpu_arch[j].type != PROCESSOR_NONE
16974
0
      || !cpu_flags_all_zero (&cpu_arch[j].enable))
16975
0
    continue;
16976
0
  str = xasprintf ("no%s", cpu_arch[j].name);
16977
0
  p = output_message (stream, p, message, start, &left, str,
16978
0
          strlen (str));
16979
0
  free (str);
16980
0
      }
16981
16982
0
  *p = '\0';
16983
0
  fprintf (stream, "%s\n", message);
16984
0
}
16985
16986
void
16987
md_show_usage (FILE *stream)
16988
0
{
16989
0
#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
16990
0
  fprintf (stream, _("\
16991
0
  -Qy, -Qn                ignored\n\
16992
0
  -V                      print assembler version number\n\
16993
0
  -k                      ignored\n"));
16994
0
#endif
16995
0
  fprintf (stream, _("\
16996
0
  -n                      do not optimize code alignment\n\
16997
0
  -O{012s}                attempt some code optimizations\n\
16998
0
  -q                      quieten some warnings\n"));
16999
0
#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
17000
0
  fprintf (stream, _("\
17001
0
  -s                      ignored\n"));
17002
0
#endif
17003
0
#ifdef BFD64
17004
0
# if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
17005
0
  fprintf (stream, _("\
17006
0
  --32/--64/--x32         generate 32bit/64bit/x32 object\n"));
17007
# elif defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)
17008
  fprintf (stream, _("\
17009
  --32/--64               generate 32bit/64bit object\n"));
17010
# endif
17011
0
#endif
17012
#ifdef SVR4_COMMENT_CHARS
17013
  fprintf (stream, _("\
17014
  --divide                do not treat `/' as a comment character\n"));
17015
#else
17016
0
  fprintf (stream, _("\
17017
0
  --divide                ignored\n"));
17018
0
#endif
17019
0
  fprintf (stream, _("\
17020
0
  -march=CPU[,+EXTENSION...]\n\
17021
0
                          generate code for CPU and EXTENSION, CPU is one of:\n"));
17022
0
  show_arch (stream, 0, 1);
17023
0
  fprintf (stream, _("\
17024
0
                          EXTENSION is combination of (possibly \"no\"-prefixed):\n"));
17025
0
  show_arch (stream, 1, 0);
17026
0
  fprintf (stream, _("\
17027
0
  -mtune=CPU              optimize for CPU, CPU is one of:\n"));
17028
0
  show_arch (stream, 0, 0);
17029
0
  fprintf (stream, _("\
17030
0
  -msse2avx               encode SSE instructions with VEX prefix\n"));
17031
0
  fprintf (stream, _("\
17032
0
  -muse-unaligned-vector-move\n\
17033
0
                          encode aligned vector move as unaligned vector move\n"));
17034
0
  fprintf (stream, _("\
17035
0
  -msse-check=[none|error|warning] (default: none)\n\
17036
0
                          check SSE instructions\n"));
17037
0
  fprintf (stream, _("\
17038
0
  -moperand-check=[none|error|warning] (default: warning)\n\
17039
0
                          check operand combinations for validity\n"));
17040
0
  fprintf (stream, _("\
17041
0
  -mavxscalar=[128|256] (default: 128)\n\
17042
0
                          encode scalar AVX instructions with specific vector\n\
17043
0
                           length\n"));
17044
0
  fprintf (stream, _("\
17045
0
  -mvexwig=[0|1] (default: 0)\n\
17046
0
                          encode VEX instructions with specific VEX.W value\n\
17047
0
                           for VEX.W bit ignored instructions\n"));
17048
0
  fprintf (stream, _("\
17049
0
  -mevexlig=[128|256|512] (default: 128)\n\
17050
0
                          encode scalar EVEX instructions with specific vector\n\
17051
0
                           length\n"));
17052
0
  fprintf (stream, _("\
17053
0
  -mevexwig=[0|1] (default: 0)\n\
17054
0
                          encode EVEX instructions with specific EVEX.W value\n\
17055
0
                           for EVEX.W bit ignored instructions\n"));
17056
0
  fprintf (stream, _("\
17057
0
  -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\
17058
0
                          encode EVEX instructions with specific EVEX.RC value\n\
17059
0
                           for SAE-only ignored instructions\n"));
17060
0
  fprintf (stream, _("\
17061
0
  -mmnemonic=[att|intel] "));
17062
0
  if (SYSV386_COMPAT)
17063
0
    fprintf (stream, _("(default: att)\n"));
17064
0
  else
17065
0
    fprintf (stream, _("(default: intel)\n"));
17066
0
  fprintf (stream, _("\
17067
0
                          use AT&T/Intel mnemonic (AT&T syntax only)\n"));
17068
0
  fprintf (stream, _("\
17069
0
  -msyntax=[att|intel] (default: att)\n\
17070
0
                          use AT&T/Intel syntax\n"));
17071
0
  fprintf (stream, _("\
17072
0
  -mindex-reg             support pseudo index registers\n"));
17073
0
  fprintf (stream, _("\
17074
0
  -mnaked-reg             don't require `%%' prefix for registers\n"));
17075
0
  fprintf (stream, _("\
17076
0
  -madd-bnd-prefix        add BND prefix for all valid branches\n"));
17077
0
#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
17078
0
  fprintf (stream, _("\
17079
0
  -mshared                disable branch optimization for shared code\n"));
17080
0
  fprintf (stream, _("\
17081
0
  -mx86-used-note=[no|yes] "));
17082
0
  if (DEFAULT_X86_USED_NOTE)
17083
0
    fprintf (stream, _("(default: yes)\n"));
17084
0
  else
17085
0
    fprintf (stream, _("(default: no)\n"));
17086
0
  fprintf (stream, _("\
17087
0
                          generate x86 used ISA and feature properties\n"));
17088
0
#endif
17089
#if defined (TE_PE) || defined (TE_PEP)
17090
  fprintf (stream, _("\
17091
  -mbig-obj               generate big object files\n"));
17092
#endif
17093
0
  fprintf (stream, _("\
17094
0
  -momit-lock-prefix=[no|yes] (default: no)\n\
17095
0
                          strip all lock prefixes\n"));
17096
0
  fprintf (stream, _("\
17097
0
  -mfence-as-lock-add=[no|yes] (default: no)\n\
17098
0
                          encode lfence, mfence and sfence as\n\
17099
0
                           lock addl $0x0, (%%{re}sp)\n"));
17100
0
  fprintf (stream, _("\
17101
0
  -mrelax-relocations=[no|yes] "));
17102
0
  if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS)
17103
0
    fprintf (stream, _("(default: yes)\n"));
17104
0
  else
17105
0
    fprintf (stream, _("(default: no)\n"));
17106
0
  fprintf (stream, _("\
17107
0
                          generate relax relocations\n"));
17108
0
  fprintf (stream, _("\
17109
0
  -malign-branch-boundary=NUM (default: 0)\n\
17110
0
                          align branches within NUM byte boundary\n"));
17111
0
  fprintf (stream, _("\
17112
0
  -malign-branch=TYPE[+TYPE...] (default: jcc+fused+jmp)\n\
17113
0
                          TYPE is combination of jcc, fused, jmp, call, ret,\n\
17114
0
                           indirect\n\
17115
0
                          specify types of branches to align\n"));
17116
0
  fprintf (stream, _("\
17117
0
  -malign-branch-prefix-size=NUM (default: 5)\n\
17118
0
                          align branches with NUM prefixes per instruction\n"));
17119
0
  fprintf (stream, _("\
17120
0
  -mbranches-within-32B-boundaries\n\
17121
0
                          align branches within 32 byte boundary\n"));
17122
0
  fprintf (stream, _("\
17123
0
  -mlfence-after-load=[no|yes] (default: no)\n\
17124
0
                          generate lfence after load\n"));
17125
0
  fprintf (stream, _("\
17126
0
  -mlfence-before-indirect-branch=[none|all|register|memory] (default: none)\n\
17127
0
                          generate lfence before indirect near branch\n"));
17128
0
  fprintf (stream, _("\
17129
0
  -mlfence-before-ret=[none|or|not|shl|yes] (default: none)\n\
17130
0
                          generate lfence before ret\n"));
17131
0
  fprintf (stream, _("\
17132
0
  -mamd64                 accept only AMD64 ISA [default]\n"));
17133
0
  fprintf (stream, _("\
17134
0
  -mintel64               accept only Intel64 ISA\n"));
17135
0
}
17136
17137
#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
17138
     || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
17139
     || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
17140
17141
/* Pick the target format to use.  */
17142
17143
const char *
17144
i386_target_format (void)
17145
736
{
17146
736
  if (startswith (default_arch, "x86_64"))
17147
736
    {
17148
736
      update_code_flag (CODE_64BIT, 1);
17149
736
#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
17150
736
      if (default_arch[6] == '\0')
17151
736
  x86_elf_abi = X86_64_ABI;
17152
0
      else
17153
0
  x86_elf_abi = X86_64_X32_ABI;
17154
736
#endif
17155
736
    }
17156
0
  else if (!strcmp (default_arch, "i386"))
17157
0
    update_code_flag (CODE_32BIT, 1);
17158
0
  else if (!strcmp (default_arch, "iamcu"))
17159
0
    {
17160
0
      update_code_flag (CODE_32BIT, 1);
17161
0
      if (cpu_arch_isa == PROCESSOR_UNKNOWN)
17162
0
  {
17163
0
    static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS;
17164
0
    cpu_arch_name = "iamcu";
17165
0
    free (cpu_sub_arch_name);
17166
0
    cpu_sub_arch_name = NULL;
17167
0
    cpu_arch_flags = iamcu_flags;
17168
0
    cpu_arch_isa = PROCESSOR_IAMCU;
17169
0
    cpu_arch_isa_flags = iamcu_flags;
17170
0
    if (!cpu_arch_tune_set)
17171
0
      cpu_arch_tune = PROCESSOR_IAMCU;
17172
0
  }
17173
0
      else if (cpu_arch_isa != PROCESSOR_IAMCU)
17174
0
  as_fatal (_("Intel MCU doesn't support `%s' architecture"),
17175
0
      cpu_arch_name);
17176
0
    }
17177
0
  else
17178
0
    as_fatal (_("unknown architecture"));
17179
17180
736
#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
17181
736
  if (IS_ELF && flag_synth_cfi && x86_elf_abi != X86_64_ABI)
17182
0
    as_fatal (_("SCFI is not supported for this ABI"));
17183
736
#endif
17184
17185
736
  if (cpu_flags_all_zero (&cpu_arch_isa_flags))
17186
1
    cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].enable;
17187
17188
736
  switch (OUTPUT_FLAVOR)
17189
736
    {
17190
#if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
17191
    case bfd_target_aout_flavour:
17192
      return AOUT_TARGET_FORMAT;
17193
#endif
17194
#if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
17195
# if defined (TE_PE) || defined (TE_PEP)
17196
    case bfd_target_coff_flavour:
17197
      if (flag_code == CODE_64BIT)
17198
  {
17199
    object_64bit = 1;
17200
    return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64";
17201
  }
17202
      return use_big_obj ? "pe-bigobj-i386" : "pe-i386";
17203
# elif defined (TE_GO32)
17204
    case bfd_target_coff_flavour:
17205
      return "coff-go32";
17206
# else
17207
    case bfd_target_coff_flavour:
17208
      return "coff-i386";
17209
# endif
17210
#endif
17211
0
#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
17212
736
    case bfd_target_elf_flavour:
17213
736
      {
17214
736
  const char *format;
17215
17216
736
  switch (x86_elf_abi)
17217
736
    {
17218
0
    default:
17219
0
      format = ELF_TARGET_FORMAT;
17220
0
#ifndef TE_SOLARIS
17221
0
      tls_get_addr = "___tls_get_addr";
17222
0
#endif
17223
0
      break;
17224
736
    case X86_64_ABI:
17225
736
      use_rela_relocations = 1;
17226
736
      object_64bit = 1;
17227
736
#ifndef TE_SOLARIS
17228
736
      tls_get_addr = "__tls_get_addr";
17229
736
#endif
17230
736
      format = ELF_TARGET_FORMAT64;
17231
736
      break;
17232
0
    case X86_64_X32_ABI:
17233
0
      use_rela_relocations = 1;
17234
0
      object_64bit = 1;
17235
0
#ifndef TE_SOLARIS
17236
0
      tls_get_addr = "__tls_get_addr";
17237
0
#endif
17238
0
      disallow_64bit_reloc = 1;
17239
0
      format = ELF_TARGET_FORMAT32;
17240
0
      break;
17241
736
    }
17242
736
  if (cpu_arch_isa == PROCESSOR_IAMCU)
17243
0
    {
17244
0
      if (x86_elf_abi != I386_ABI)
17245
0
        as_fatal (_("Intel MCU is 32bit only"));
17246
0
      return ELF_TARGET_IAMCU_FORMAT;
17247
0
    }
17248
736
  else
17249
736
    return format;
17250
736
      }
17251
0
#endif
17252
#if defined (OBJ_MACH_O)
17253
    case bfd_target_mach_o_flavour:
17254
      if (flag_code == CODE_64BIT)
17255
  {
17256
    use_rela_relocations = 1;
17257
    object_64bit = 1;
17258
    return "mach-o-x86-64";
17259
  }
17260
      else
17261
  return "mach-o-i386";
17262
#endif
17263
0
    default:
17264
0
      abort ();
17265
0
      return NULL;
17266
736
    }
17267
736
}
17268
17269
#endif /* OBJ_MAYBE_ more than one  */
17270

17271
symbolS *
17272
md_undefined_symbol (char *name)
17273
88.7k
{
17274
88.7k
  if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
17275
88.7k
      && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
17276
88.7k
      && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
17277
88.7k
      && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
17278
1
    {
17279
1
      if (!GOT_symbol)
17280
1
  {
17281
1
    if (symbol_find (name))
17282
0
      as_bad (_("GOT already in symbol table"));
17283
1
    GOT_symbol = symbol_new (name, undefined_section,
17284
1
           &zero_address_frag, 0);
17285
1
  };
17286
1
      return GOT_symbol;
17287
1
    }
17288
88.7k
  return 0;
17289
88.7k
}
17290
17291
#if defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)
17292
/* Round up a section size to the appropriate boundary.  */
17293
17294
valueT
17295
md_section_align (segT segment, valueT size)
17296
{
17297
  if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
17298
    {
17299
      /* For a.out, force the section size to be aligned.  If we don't do
17300
   this, BFD will align it for us, but it will not write out the
17301
   final bytes of the section.  This may be a bug in BFD, but it is
17302
   easier to fix it here since that is how the other a.out targets
17303
   work.  */
17304
      int align;
17305
17306
      align = bfd_section_alignment (segment);
17307
      size = ((size + (1 << align) - 1) & (-((valueT) 1 << align)));
17308
    }
17309
17310
  return size;
17311
}
17312
#endif
17313
17314
/* On the i386, PC-relative offsets are relative to the start of the
17315
   next instruction.  That is, the address of the offset, plus its
17316
   size, since the offset is always the last part of the insn.  */
17317
17318
long
17319
md_pcrel_from (fixS *fixP)
17320
0
{
17321
0
  return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
17322
0
}
17323
17324
#ifdef OBJ_AOUT
17325
17326
static void
17327
s_bss (int ignore ATTRIBUTE_UNUSED)
17328
{
17329
  int temp;
17330
17331
  temp = get_absolute_expression ();
17332
  subseg_set (bss_section, (subsegT) temp);
17333
  demand_empty_rest_of_line ();
17334
}
17335
17336
#endif
17337
17338
/* Remember constant directive.  */
17339
17340
void
17341
i386_cons_align (int ignore ATTRIBUTE_UNUSED)
17342
48.8k
{
17343
48.8k
  struct last_insn *last_insn
17344
48.8k
    = &seg_info(now_seg)->tc_segment_info_data.last_insn;
17345
17346
48.8k
  if (bfd_section_flags (now_seg) & SEC_CODE)
17347
24.2k
    {
17348
24.2k
      last_insn->kind = last_insn_directive;
17349
24.2k
      last_insn->name = "constant directive";
17350
24.2k
      last_insn->file = as_where (&last_insn->line);
17351
24.2k
    }
17352
48.8k
}
17353
17354
int
17355
i386_validate_fix (fixS *fixp)
17356
0
{
17357
0
  if (fixp->fx_addsy && S_GET_SEGMENT(fixp->fx_addsy) == reg_section)
17358
0
    {
17359
0
      reloc_howto_type *howto;
17360
17361
0
      howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
17362
0
      as_bad_where (fixp->fx_file, fixp->fx_line,
17363
0
        _("invalid %s relocation against register"),
17364
0
        howto ? howto->name : "<unknown>");
17365
0
      return 0;
17366
0
    }
17367
17368
0
#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
17369
0
  if (fixp->fx_r_type == BFD_RELOC_SIZE32
17370
0
      || fixp->fx_r_type == BFD_RELOC_SIZE64)
17371
0
    return IS_ELF && fixp->fx_addsy
17372
0
     && (!S_IS_DEFINED (fixp->fx_addsy)
17373
0
         || S_IS_EXTERNAL (fixp->fx_addsy));
17374
17375
  /* BFD_RELOC_X86_64_GOTTPOFF:
17376
      1. fx_tcbit -> BFD_RELOC_X86_64_CODE_4_GOTTPOFF
17377
      2. fx_tcbit2 -> BFD_RELOC_X86_64_CODE_6_GOTTPOFF
17378
    BFD_RELOC_X86_64_GOTPC32_TLSDESC:
17379
      1. fx_tcbit -> BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC
17380
    BFD_RELOC_32_PCREL:
17381
      1. fx_tcbit -> BFD_RELOC_X86_64_GOTPCRELX
17382
      2. fx_tcbit2 -> BFD_RELOC_X86_64_REX_GOTPCRELX
17383
      3. fx_tcbit3 -> BFD_RELOC_X86_64_CODE_4_GOTPCRELX
17384
      4. else -> BFD_RELOC_X86_64_GOTPCREL
17385
   */
17386
0
  if (fixp->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF)
17387
0
    {
17388
0
      if (fixp->fx_tcbit)
17389
0
  fixp->fx_r_type = BFD_RELOC_X86_64_CODE_4_GOTTPOFF;
17390
0
      else if (fixp->fx_tcbit2)
17391
0
  fixp->fx_r_type = BFD_RELOC_X86_64_CODE_6_GOTTPOFF;
17392
0
    }
17393
0
  else if (fixp->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
17394
0
     && fixp->fx_tcbit)
17395
0
    fixp->fx_r_type = BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC;
17396
0
#endif
17397
17398
0
  if (fixp->fx_subsy)
17399
0
    {
17400
0
      if (fixp->fx_subsy == GOT_symbol)
17401
0
  {
17402
0
    if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
17403
0
      {
17404
0
        if (!object_64bit)
17405
0
    abort ();
17406
0
#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
17407
0
        if (fixp->fx_tcbit)
17408
0
    fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCRELX;
17409
0
        else if (fixp->fx_tcbit2)
17410
0
    fixp->fx_r_type = BFD_RELOC_X86_64_REX_GOTPCRELX;
17411
0
        else if (fixp->fx_tcbit3)
17412
0
    fixp->fx_r_type = BFD_RELOC_X86_64_CODE_4_GOTPCRELX;
17413
0
        else
17414
0
#endif
17415
0
    fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
17416
0
      }
17417
0
    else
17418
0
      {
17419
0
        if (!object_64bit)
17420
0
    fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
17421
0
        else
17422
0
    fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
17423
0
      }
17424
0
    fixp->fx_subsy = 0;
17425
0
  }
17426
0
    }
17427
0
#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
17428
0
  else
17429
0
    {
17430
      /* NB: Commit 292676c1 resolved PLT32 reloc aganst local symbol
17431
   to section.  Since PLT32 relocation must be against symbols,
17432
   turn such PLT32 relocation into PC32 relocation.  */
17433
0
      if (fixp->fx_addsy
17434
0
    && (fixp->fx_r_type == BFD_RELOC_386_PLT32
17435
0
        || fixp->fx_r_type == BFD_RELOC_X86_64_PLT32)
17436
0
    && symbol_section_p (fixp->fx_addsy))
17437
0
  fixp->fx_r_type = BFD_RELOC_32_PCREL;
17438
0
      if (!object_64bit)
17439
0
  {
17440
0
    if (fixp->fx_r_type == BFD_RELOC_386_GOT32
17441
0
        && fixp->fx_tcbit2)
17442
0
      fixp->fx_r_type = BFD_RELOC_386_GOT32X;
17443
0
  }
17444
0
    }
17445
0
#endif
17446
17447
0
  return 1;
17448
0
}
17449
17450
arelent *
17451
tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
17452
0
{
17453
0
  arelent *rel;
17454
0
  bfd_reloc_code_real_type code;
17455
17456
0
  switch (fixp->fx_r_type)
17457
0
    {
17458
0
#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
17459
0
      symbolS *sym;
17460
17461
0
    case BFD_RELOC_SIZE32:
17462
0
    case BFD_RELOC_SIZE64:
17463
0
      if (fixp->fx_addsy
17464
0
    && !bfd_is_abs_section (S_GET_SEGMENT (fixp->fx_addsy))
17465
0
    && (!fixp->fx_subsy
17466
0
        || bfd_is_abs_section (S_GET_SEGMENT (fixp->fx_subsy))))
17467
0
  sym = fixp->fx_addsy;
17468
0
      else if (fixp->fx_subsy
17469
0
         && !bfd_is_abs_section (S_GET_SEGMENT (fixp->fx_subsy))
17470
0
         && (!fixp->fx_addsy
17471
0
       || bfd_is_abs_section (S_GET_SEGMENT (fixp->fx_addsy))))
17472
0
  sym = fixp->fx_subsy;
17473
0
      else
17474
0
  sym = NULL;
17475
0
      if (IS_ELF && sym && S_IS_DEFINED (sym) && !S_IS_EXTERNAL (sym))
17476
0
  {
17477
    /* Resolve size relocation against local symbol to size of
17478
       the symbol plus addend.  */
17479
0
    valueT value = S_GET_SIZE (sym);
17480
17481
0
    if (symbol_get_bfdsym (sym)->flags & BSF_SECTION_SYM)
17482
0
      value = bfd_section_size (S_GET_SEGMENT (sym));
17483
0
    if (sym == fixp->fx_subsy)
17484
0
      {
17485
0
        value = -value;
17486
0
        if (fixp->fx_addsy)
17487
0
          value += S_GET_VALUE (fixp->fx_addsy);
17488
0
      }
17489
0
    else if (fixp->fx_subsy)
17490
0
      value -= S_GET_VALUE (fixp->fx_subsy);
17491
0
    value += fixp->fx_offset;
17492
0
    if (fixp->fx_r_type == BFD_RELOC_SIZE32
17493
0
        && object_64bit
17494
0
        && !fits_in_unsigned_long (value))
17495
0
      as_bad_where (fixp->fx_file, fixp->fx_line,
17496
0
        _("symbol size computation overflow"));
17497
0
    fixp->fx_addsy = NULL;
17498
0
    fixp->fx_subsy = NULL;
17499
0
    md_apply_fix (fixp, (valueT *) &value, NULL);
17500
0
    return NULL;
17501
0
  }
17502
0
      if (!fixp->fx_addsy || fixp->fx_subsy)
17503
0
  {
17504
0
    as_bad_where (fixp->fx_file, fixp->fx_line,
17505
0
      "unsupported expression involving @size");
17506
0
    return NULL;
17507
0
  }
17508
0
#endif
17509
      /* Fall through.  */
17510
17511
0
    case BFD_RELOC_X86_64_PLT32:
17512
0
    case BFD_RELOC_X86_64_GOT32:
17513
0
    case BFD_RELOC_X86_64_GOTPCREL:
17514
0
    case BFD_RELOC_X86_64_GOTPCRELX:
17515
0
    case BFD_RELOC_X86_64_REX_GOTPCRELX:
17516
0
    case BFD_RELOC_X86_64_CODE_4_GOTPCRELX:
17517
0
    case BFD_RELOC_386_PLT32:
17518
0
    case BFD_RELOC_386_GOT32:
17519
0
    case BFD_RELOC_386_GOT32X:
17520
0
    case BFD_RELOC_386_GOTOFF:
17521
0
    case BFD_RELOC_386_GOTPC:
17522
0
    case BFD_RELOC_386_TLS_GD:
17523
0
    case BFD_RELOC_386_TLS_LDM:
17524
0
    case BFD_RELOC_386_TLS_LDO_32:
17525
0
    case BFD_RELOC_386_TLS_IE_32:
17526
0
    case BFD_RELOC_386_TLS_IE:
17527
0
    case BFD_RELOC_386_TLS_GOTIE:
17528
0
    case BFD_RELOC_386_TLS_LE_32:
17529
0
    case BFD_RELOC_386_TLS_LE:
17530
0
    case BFD_RELOC_386_TLS_GOTDESC:
17531
0
    case BFD_RELOC_386_TLS_DESC_CALL:
17532
0
    case BFD_RELOC_X86_64_TLSGD:
17533
0
    case BFD_RELOC_X86_64_TLSLD:
17534
0
    case BFD_RELOC_X86_64_DTPOFF32:
17535
0
    case BFD_RELOC_X86_64_DTPOFF64:
17536
0
    case BFD_RELOC_X86_64_GOTTPOFF:
17537
0
    case BFD_RELOC_X86_64_CODE_4_GOTTPOFF:
17538
0
    case BFD_RELOC_X86_64_CODE_6_GOTTPOFF:
17539
0
    case BFD_RELOC_X86_64_TPOFF32:
17540
0
    case BFD_RELOC_X86_64_TPOFF64:
17541
0
    case BFD_RELOC_X86_64_GOTOFF64:
17542
0
    case BFD_RELOC_X86_64_GOTPC32:
17543
0
    case BFD_RELOC_X86_64_GOT64:
17544
0
    case BFD_RELOC_X86_64_GOTPCREL64:
17545
0
    case BFD_RELOC_X86_64_GOTPC64:
17546
0
    case BFD_RELOC_X86_64_GOTPLT64:
17547
0
    case BFD_RELOC_X86_64_PLTOFF64:
17548
0
    case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
17549
0
    case BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC:
17550
0
    case BFD_RELOC_X86_64_TLSDESC_CALL:
17551
0
    case BFD_RELOC_RVA:
17552
0
    case BFD_RELOC_VTABLE_ENTRY:
17553
0
    case BFD_RELOC_VTABLE_INHERIT:
17554
#ifdef TE_PE
17555
    case BFD_RELOC_32_SECREL:
17556
    case BFD_RELOC_16_SECIDX:
17557
#endif
17558
0
      code = fixp->fx_r_type;
17559
0
      break;
17560
0
    case BFD_RELOC_X86_64_32S:
17561
0
      if (!fixp->fx_pcrel)
17562
0
  {
17563
    /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32.  */
17564
0
    code = fixp->fx_r_type;
17565
0
    break;
17566
0
  }
17567
      /* Fall through.  */
17568
0
    default:
17569
0
      if (fixp->fx_pcrel)
17570
0
  {
17571
0
    switch (fixp->fx_size)
17572
0
      {
17573
0
      default:
17574
0
        as_bad_where (fixp->fx_file, fixp->fx_line,
17575
0
          _("can not do %d byte pc-relative relocation"),
17576
0
          fixp->fx_size);
17577
0
        code = BFD_RELOC_32_PCREL;
17578
0
        break;
17579
0
      case 1: code = BFD_RELOC_8_PCREL;  break;
17580
0
      case 2: code = BFD_RELOC_16_PCREL; break;
17581
0
      case 4: code = BFD_RELOC_32_PCREL; break;
17582
0
#ifdef BFD64
17583
0
      case 8: code = BFD_RELOC_64_PCREL; break;
17584
0
#endif
17585
0
      }
17586
0
  }
17587
0
      else
17588
0
  {
17589
0
    switch (fixp->fx_size)
17590
0
      {
17591
0
      default:
17592
0
        as_bad_where (fixp->fx_file, fixp->fx_line,
17593
0
          _("can not do %d byte relocation"),
17594
0
          fixp->fx_size);
17595
0
        code = BFD_RELOC_32;
17596
0
        break;
17597
0
      case 1: code = BFD_RELOC_8;  break;
17598
0
      case 2: code = BFD_RELOC_16; break;
17599
0
      case 4: code = BFD_RELOC_32; break;
17600
0
#ifdef BFD64
17601
0
      case 8: code = BFD_RELOC_64; break;
17602
0
#endif
17603
0
      }
17604
0
  }
17605
0
      break;
17606
0
    }
17607
17608
0
  if ((code == BFD_RELOC_32
17609
0
       || code == BFD_RELOC_32_PCREL
17610
0
       || code == BFD_RELOC_X86_64_32S)
17611
0
      && GOT_symbol
17612
0
      && fixp->fx_addsy == GOT_symbol)
17613
0
    {
17614
0
      if (!object_64bit)
17615
0
  code = BFD_RELOC_386_GOTPC;
17616
0
      else
17617
0
  code = BFD_RELOC_X86_64_GOTPC32;
17618
0
    }
17619
0
  if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
17620
0
      && GOT_symbol
17621
0
      && fixp->fx_addsy == GOT_symbol)
17622
0
    {
17623
0
      code = BFD_RELOC_X86_64_GOTPC64;
17624
0
    }
17625
17626
0
  rel = XNEW (arelent);
17627
0
  rel->sym_ptr_ptr = XNEW (asymbol *);
17628
0
  *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
17629
17630
0
  rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
17631
17632
0
  if (!use_rela_relocations)
17633
0
    {
17634
      /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
17635
   vtable entry to be used in the relocation's section offset.  */
17636
0
      if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
17637
0
  rel->address = fixp->fx_offset;
17638
#if defined (OBJ_COFF) && defined (TE_PE)
17639
      else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
17640
  rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
17641
      else
17642
#endif
17643
0
      rel->addend = 0;
17644
0
    }
17645
  /* Use the rela in 64bit mode.  */
17646
0
  else
17647
0
    {
17648
0
      if (disallow_64bit_reloc)
17649
0
  switch (code)
17650
0
    {
17651
0
    case BFD_RELOC_X86_64_DTPOFF64:
17652
0
    case BFD_RELOC_X86_64_TPOFF64:
17653
0
    case BFD_RELOC_64_PCREL:
17654
0
    case BFD_RELOC_X86_64_GOTOFF64:
17655
0
    case BFD_RELOC_X86_64_GOT64:
17656
0
    case BFD_RELOC_X86_64_GOTPCREL64:
17657
0
    case BFD_RELOC_X86_64_GOTPC64:
17658
0
    case BFD_RELOC_X86_64_GOTPLT64:
17659
0
    case BFD_RELOC_X86_64_PLTOFF64:
17660
0
      as_bad_where (fixp->fx_file, fixp->fx_line,
17661
0
        _("cannot represent relocation type %s in x32 mode"),
17662
0
        bfd_get_reloc_code_name (code));
17663
0
      break;
17664
0
    default:
17665
0
      break;
17666
0
    }
17667
17668
0
      if (!fixp->fx_pcrel)
17669
0
  rel->addend = fixp->fx_offset;
17670
0
      else
17671
0
  switch (code)
17672
0
    {
17673
0
    case BFD_RELOC_X86_64_PLT32:
17674
0
    case BFD_RELOC_X86_64_GOT32:
17675
0
    case BFD_RELOC_X86_64_GOTPCREL:
17676
0
    case BFD_RELOC_X86_64_GOTPCRELX:
17677
0
    case BFD_RELOC_X86_64_REX_GOTPCRELX:
17678
0
    case BFD_RELOC_X86_64_CODE_4_GOTPCRELX:
17679
0
    case BFD_RELOC_X86_64_TLSGD:
17680
0
    case BFD_RELOC_X86_64_TLSLD:
17681
0
    case BFD_RELOC_X86_64_GOTTPOFF:
17682
0
    case BFD_RELOC_X86_64_CODE_4_GOTTPOFF:
17683
0
    case BFD_RELOC_X86_64_CODE_6_GOTTPOFF:
17684
0
    case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
17685
0
    case BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC:
17686
0
    case BFD_RELOC_X86_64_TLSDESC_CALL:
17687
0
      rel->addend = fixp->fx_offset - fixp->fx_size;
17688
0
      break;
17689
0
    default:
17690
0
      rel->addend = (section->vma
17691
0
         - fixp->fx_size
17692
0
         + fixp->fx_addnumber
17693
0
         + md_pcrel_from (fixp));
17694
0
      break;
17695
0
    }
17696
0
    }
17697
17698
0
  rel->howto = bfd_reloc_type_lookup (stdoutput, code);
17699
0
  if (rel->howto == NULL)
17700
0
    {
17701
0
      as_bad_where (fixp->fx_file, fixp->fx_line,
17702
0
        _("cannot represent relocation type %s"),
17703
0
        bfd_get_reloc_code_name (code));
17704
      /* Set howto to a garbage value so that we can keep going.  */
17705
0
      rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
17706
0
      gas_assert (rel->howto != NULL);
17707
0
    }
17708
17709
0
  return rel;
17710
0
}
17711
17712
#include "tc-i386-intel.c"
17713
17714
void
17715
tc_x86_parse_to_dw2regnum (expressionS *exp)
17716
0
{
17717
0
  int saved_naked_reg;
17718
0
  char saved_register_dot;
17719
17720
0
  saved_naked_reg = allow_naked_reg;
17721
0
  allow_naked_reg = 1;
17722
0
  saved_register_dot = register_chars['.'];
17723
0
  register_chars['.'] = '.';
17724
0
  allow_pseudo_reg = 1;
17725
0
  expression_and_evaluate (exp);
17726
0
  allow_pseudo_reg = 0;
17727
0
  register_chars['.'] = saved_register_dot;
17728
0
  allow_naked_reg = saved_naked_reg;
17729
17730
0
  if (exp->X_op == O_register && exp->X_add_number >= 0)
17731
0
    {
17732
0
      exp->X_op = O_illegal;
17733
0
      if ((addressT) exp->X_add_number < i386_regtab_size)
17734
0
  {
17735
0
    exp->X_add_number = i386_regtab[exp->X_add_number]
17736
0
            .dw2_regnum[object_64bit];
17737
0
    if (exp->X_add_number != Dw2Inval)
17738
0
      exp->X_op = O_constant;
17739
0
  }
17740
0
    }
17741
0
}
17742
17743
void
17744
tc_x86_frame_initial_instructions (void)
17745
62
{
17746
62
  cfi_add_CFA_def_cfa (object_64bit ? REG_SP : 4, -x86_cie_data_alignment);
17747
62
  cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
17748
62
}
17749
17750
int
17751
x86_dwarf2_addr_size (void)
17752
100
{
17753
100
#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
17754
100
  if (x86_elf_abi == X86_64_X32_ABI)
17755
0
    return 4;
17756
100
#endif
17757
100
  return bfd_arch_bits_per_address (stdoutput) / 8;
17758
100
}
17759
17760
#ifdef TE_PE
17761
void
17762
tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
17763
{
17764
  expressionS exp;
17765
17766
  exp.X_op = O_secrel;
17767
  exp.X_add_symbol = symbol;
17768
  exp.X_add_number = 0;
17769
  emit_expr (&exp, size);
17770
}
17771
#endif
17772
17773
#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
17774
int
17775
i386_elf_section_type (const char *str, size_t len)
17776
0
{
17777
0
  if (flag_code == CODE_64BIT
17778
0
      && len == sizeof ("unwind") - 1
17779
0
      && startswith (str, "unwind"))
17780
0
    return SHT_X86_64_UNWIND;
17781
17782
0
  return -1;
17783
0
}
17784
17785
void
17786
i386_elf_section_change_hook (void)
17787
12.7k
{
17788
12.7k
  struct i386_segment_info *info = &seg_info(now_seg)->tc_segment_info_data;
17789
12.7k
  struct i386_segment_info *curr, *prev;
17790
17791
12.7k
  if (info->subseg == now_subseg)
17792
11.0k
    return;
17793
17794
  /* Find the (or make a) list entry to save state into.  */
17795
2.69k
  for (prev = info; (curr = prev->next) != NULL; prev = curr)
17796
2.61k
    if (curr->subseg == info->subseg)
17797
1.68k
      break;
17798
1.76k
  if (!curr)
17799
76
    {
17800
76
      curr = notes_alloc (sizeof (*curr));
17801
76
      curr->subseg = info->subseg;
17802
76
      curr->next = NULL;
17803
76
      prev->next = curr;
17804
76
    }
17805
1.76k
  curr->last_insn = info->last_insn;
17806
17807
  /* Find the list entry to load state from.  */
17808
2.71k
  for (curr = info->next; curr; curr = curr->next)
17809
2.66k
    if (curr->subseg == now_subseg)
17810
1.71k
      break;
17811
1.76k
  if (curr)
17812
1.71k
    info->last_insn = curr->last_insn;
17813
54
  else
17814
54
    memset (&info->last_insn, 0, sizeof (info->last_insn));
17815
1.76k
  info->subseg = now_subseg;
17816
1.76k
}
17817
17818
#ifdef TE_SOLARIS
17819
void
17820
i386_solaris_fix_up_eh_frame (segT sec)
17821
{
17822
  if (flag_code == CODE_64BIT)
17823
    elf_section_type (sec) = SHT_X86_64_UNWIND;
17824
}
17825
#endif
17826
17827
/* For ELF on x86-64, add support for SHF_X86_64_LARGE.  */
17828
17829
bfd_vma
17830
x86_64_section_letter (int letter, const char **ptr_msg)
17831
0
{
17832
0
  if (flag_code == CODE_64BIT)
17833
0
    {
17834
0
      if (letter == 'l')
17835
0
  return SHF_X86_64_LARGE;
17836
17837
0
      *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
17838
0
    }
17839
0
  else
17840
0
    *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
17841
0
  return -1;
17842
0
}
17843
17844
static void
17845
handle_large_common (int small ATTRIBUTE_UNUSED)
17846
0
{
17847
0
  if (flag_code != CODE_64BIT)
17848
0
    {
17849
0
      s_comm_internal (0, elf_common_parse);
17850
0
      as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
17851
0
    }
17852
0
  else
17853
0
    {
17854
0
      static segT lbss_section;
17855
0
      asection *saved_com_section_ptr = elf_com_section_ptr;
17856
0
      asection *saved_bss_section = bss_section;
17857
17858
0
      if (lbss_section == NULL)
17859
0
  {
17860
0
    flagword applicable;
17861
0
    segT seg = now_seg;
17862
0
    subsegT subseg = now_subseg;
17863
17864
    /* The .lbss section is for local .largecomm symbols.  */
17865
0
    lbss_section = subseg_new (".lbss", 0);
17866
0
    applicable = bfd_applicable_section_flags (stdoutput);
17867
0
    bfd_set_section_flags (lbss_section, applicable & SEC_ALLOC);
17868
0
    seg_info (lbss_section)->bss = 1;
17869
17870
0
    subseg_set (seg, subseg);
17871
0
  }
17872
17873
0
      elf_com_section_ptr = &_bfd_elf_large_com_section;
17874
0
      bss_section = lbss_section;
17875
17876
0
      s_comm_internal (0, elf_common_parse);
17877
17878
0
      elf_com_section_ptr = saved_com_section_ptr;
17879
0
      bss_section = saved_bss_section;
17880
0
    }
17881
0
}
17882
#endif /* OBJ_ELF || OBJ_MAYBE_ELF */