/src/binutils-gdb/include/opcode/riscv.h
Line | Count | Source (jump to first uncovered line) |
1 | | /* riscv.h. RISC-V opcode list for GDB, the GNU debugger. |
2 | | Copyright (C) 2011-2024 Free Software Foundation, Inc. |
3 | | Contributed by Andrew Waterman |
4 | | |
5 | | This file is part of GDB, GAS, and the GNU binutils. |
6 | | |
7 | | GDB, GAS, and the GNU binutils are free software; you can redistribute |
8 | | them and/or modify them under the terms of the GNU General Public |
9 | | License as published by the Free Software Foundation; either version |
10 | | 3, or (at your option) any later version. |
11 | | |
12 | | GDB, GAS, and the GNU binutils are distributed in the hope that they |
13 | | will be useful, but WITHOUT ANY WARRANTY; without even the implied |
14 | | warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See |
15 | | the GNU General Public License for more details. |
16 | | |
17 | | You should have received a copy of the GNU General Public License |
18 | | along with this program; see the file COPYING3. If not, |
19 | | see <http://www.gnu.org/licenses/>. */ |
20 | | |
21 | | #ifndef _RISCV_H_ |
22 | | #define _RISCV_H_ |
23 | | |
24 | | #include "riscv-opc.h" |
25 | | #include <stdlib.h> |
26 | | #include <stdint.h> |
27 | | |
28 | | typedef uint64_t insn_t; |
29 | | |
30 | | static inline unsigned int riscv_insn_length (insn_t insn) |
31 | 1.94M | { |
32 | 1.94M | if ((insn & 0x3) != 0x3) /* RVC instructions. */ |
33 | 1.47M | return 2; |
34 | 464k | if ((insn & 0x1f) != 0x1f) /* 32-bit instructions. */ |
35 | 265k | return 4; |
36 | 199k | if ((insn & 0x3f) == 0x1f) /* 48-bit instructions. */ |
37 | 15.2k | return 6; |
38 | 183k | if ((insn & 0x7f) == 0x3f) /* 64-bit instructions. */ |
39 | 6.64k | return 8; |
40 | | /* 80- ... 176-bit instructions. */ |
41 | 177k | if ((insn & 0x7f) == 0x7f && (insn & 0x7000) != 0x7000) |
42 | 38.7k | return 10 + ((insn >> 11) & 0xe); |
43 | | /* Maximum value returned by this function. */ |
44 | 138k | #define RISCV_MAX_INSN_LEN 22 |
45 | | /* Longer instructions not supported at the moment. */ |
46 | 138k | return 2; |
47 | 177k | } Unexecuted instantiation: elf32-riscv.c:riscv_insn_length Unexecuted instantiation: elf64-riscv.c:riscv_insn_length Unexecuted instantiation: elfxx-riscv.c:riscv_insn_length riscv-dis.c:riscv_insn_length Line | Count | Source | 31 | 1.94M | { | 32 | 1.94M | if ((insn & 0x3) != 0x3) /* RVC instructions. */ | 33 | 1.47M | return 2; | 34 | 464k | if ((insn & 0x1f) != 0x1f) /* 32-bit instructions. */ | 35 | 265k | return 4; | 36 | 199k | if ((insn & 0x3f) == 0x1f) /* 48-bit instructions. */ | 37 | 15.2k | return 6; | 38 | 183k | if ((insn & 0x7f) == 0x3f) /* 64-bit instructions. */ | 39 | 6.64k | return 8; | 40 | | /* 80- ... 176-bit instructions. */ | 41 | 177k | if ((insn & 0x7f) == 0x7f && (insn & 0x7000) != 0x7000) | 42 | 38.7k | return 10 + ((insn >> 11) & 0xe); | 43 | | /* Maximum value returned by this function. */ | 44 | 138k | #define RISCV_MAX_INSN_LEN 22 | 45 | | /* Longer instructions not supported at the moment. */ | 46 | 138k | return 2; | 47 | 177k | } |
Unexecuted instantiation: riscv-opc.c:riscv_insn_length |
48 | | |
49 | | #define RVC_JUMP_BITS 11 |
50 | | #define RVC_JUMP_REACH ((1ULL << RVC_JUMP_BITS) * RISCV_JUMP_ALIGN) |
51 | | |
52 | | #define RVC_BRANCH_BITS 8 |
53 | | #define RVC_BRANCH_REACH ((1ULL << RVC_BRANCH_BITS) * RISCV_BRANCH_ALIGN) |
54 | | |
55 | 1.52M | #define RV_X(x, s, n) (((x) >> (s)) & ((1 << (n)) - 1)) |
56 | 40.6k | #define RV_IMM_SIGN(x) (-(((x) >> 31) & 1)) |
57 | 0 | #define RV_X_SIGNED(x, s, n) (RV_X(x, s, n) | ((-(RV_X(x, (s + n - 1), 1))) << (n))) |
58 | | |
59 | | #define EXTRACT_ITYPE_IMM(x) \ |
60 | 16.4k | (RV_X(x, 20, 12) | (RV_IMM_SIGN(x) << 12)) |
61 | | #define EXTRACT_STYPE_IMM(x) \ |
62 | 7.79k | (RV_X(x, 7, 5) | (RV_X(x, 25, 7) << 5) | (RV_IMM_SIGN(x) << 12)) |
63 | | #define EXTRACT_BTYPE_IMM(x) \ |
64 | 2.19k | ((RV_X(x, 8, 4) << 1) | (RV_X(x, 25, 6) << 5) | (RV_X(x, 7, 1) << 11) | (RV_IMM_SIGN(x) << 12)) |
65 | | #define EXTRACT_UTYPE_IMM(x) \ |
66 | 10.4k | ((RV_X(x, 12, 20) << 12) | (RV_IMM_SIGN(x) << 32)) |
67 | | #define EXTRACT_JTYPE_IMM(x) \ |
68 | 3.66k | ((RV_X(x, 21, 10) << 1) | (RV_X(x, 20, 1) << 11) | (RV_X(x, 12, 8) << 12) | (RV_IMM_SIGN(x) << 20)) |
69 | | #define EXTRACT_CITYPE_IMM(x) \ |
70 | 188k | (RV_X(x, 2, 5) | (-RV_X(x, 12, 1) << 5)) |
71 | | #define EXTRACT_CITYPE_LUI_IMM(x) \ |
72 | 27.4k | (EXTRACT_CITYPE_IMM (x) << RISCV_IMM_BITS) |
73 | | #define EXTRACT_CITYPE_ADDI16SP_IMM(x) \ |
74 | 3.31k | ((RV_X(x, 6, 1) << 4) | (RV_X(x, 2, 1) << 5) | (RV_X(x, 5, 1) << 6) | (RV_X(x, 3, 2) << 7) | (-RV_X(x, 12, 1) << 9)) |
75 | | #define EXTRACT_CITYPE_LWSP_IMM(x) \ |
76 | 11.8k | ((RV_X(x, 4, 3) << 2) | (RV_X(x, 12, 1) << 5) | (RV_X(x, 2, 2) << 6)) |
77 | | #define EXTRACT_CITYPE_LDSP_IMM(x) \ |
78 | 27.8k | ((RV_X(x, 5, 2) << 3) | (RV_X(x, 12, 1) << 5) | (RV_X(x, 2, 3) << 6)) |
79 | | #define EXTRACT_CSSTYPE_IMM(x) \ |
80 | | (RV_X(x, 7, 6) << 0) |
81 | | #define EXTRACT_CSSTYPE_SWSP_IMM(x) \ |
82 | 16.8k | ((RV_X(x, 9, 4) << 2) | (RV_X(x, 7, 2) << 6)) |
83 | | #define EXTRACT_CSSTYPE_SDSP_IMM(x) \ |
84 | 22.2k | ((RV_X(x, 10, 3) << 3) | (RV_X(x, 7, 3) << 6)) |
85 | | #define EXTRACT_CIWTYPE_IMM(x) \ |
86 | | (RV_X(x, 5, 8)) |
87 | | #define EXTRACT_CIWTYPE_ADDI4SPN_IMM(x) \ |
88 | 97.0k | ((RV_X(x, 6, 1) << 2) | (RV_X(x, 5, 1) << 3) | (RV_X(x, 11, 2) << 4) | (RV_X(x, 7, 4) << 6)) |
89 | | #define EXTRACT_CLTYPE_IMM(x) \ |
90 | | ((RV_X(x, 5, 2) << 0) | (RV_X(x, 10, 3) << 2)) |
91 | | #define EXTRACT_CLTYPE_LW_IMM(x) \ |
92 | 36.1k | ((RV_X(x, 6, 1) << 2) | (RV_X(x, 10, 3) << 3) | (RV_X(x, 5, 1) << 6)) |
93 | | #define EXTRACT_CLTYPE_LD_IMM(x) \ |
94 | 77.7k | ((RV_X(x, 10, 3) << 3) | (RV_X(x, 5, 2) << 6)) |
95 | | #define EXTRACT_CBTYPE_IMM(x) \ |
96 | 22.5k | ((RV_X(x, 3, 2) << 1) | (RV_X(x, 10, 2) << 3) | (RV_X(x, 2, 1) << 5) | (RV_X(x, 5, 2) << 6) | (-RV_X(x, 12, 1) << 8)) |
97 | | #define EXTRACT_CJTYPE_IMM(x) \ |
98 | 13.8k | ((RV_X(x, 3, 3) << 1) | (RV_X(x, 11, 1) << 4) | (RV_X(x, 2, 1) << 5) | (RV_X(x, 7, 1) << 6) | (RV_X(x, 6, 1) << 7) | (RV_X(x, 9, 2) << 8) | (RV_X(x, 8, 1) << 10) | (-RV_X(x, 12, 1) << 11)) |
99 | | #define EXTRACT_RVV_VI_IMM(x) \ |
100 | 0 | (RV_X(x, 15, 5) | (-RV_X(x, 19, 1) << 5)) |
101 | | #define EXTRACT_RVV_VI_UIMM(x) \ |
102 | 0 | (RV_X(x, 15, 5)) |
103 | | #define EXTRACT_RVV_VI_UIMM6(x) \ |
104 | 0 | (RV_X(x, 15, 5) | (RV_X(x, 26, 1) << 5)) |
105 | | #define EXTRACT_RVV_OFFSET(x) \ |
106 | 0 | (RV_X(x, 29, 3)) |
107 | | #define EXTRACT_RVV_VB_IMM(x) \ |
108 | 0 | (RV_X(x, 20, 10)) |
109 | | #define EXTRACT_RVV_VC_IMM(x) \ |
110 | 0 | (RV_X(x, 20, 11)) |
111 | | #define EXTRACT_ZCB_BYTE_UIMM(x) \ |
112 | 0 | (RV_X(x, 6, 1) | (RV_X(x, 5, 1) << 1)) |
113 | | #define EXTRACT_ZCB_HALFWORD_UIMM(x) \ |
114 | 0 | (RV_X(x, 5, 1) << 1) |
115 | | #define EXTRACT_ZCMP_SPIMM(x) \ |
116 | 0 | (RV_X(x, 2, 2) << 4) |
117 | | /* Vendor-specific (CORE-V) extract macros. */ |
118 | | #define EXTRACT_CV_IS2_UIMM5(x) \ |
119 | 0 | (RV_X(x, 20, 5)) |
120 | | #define EXTRACT_CV_IS3_UIMM5(x) \ |
121 | 0 | (RV_X(x, 25, 5)) |
122 | | |
123 | | #define ENCODE_ITYPE_IMM(x) \ |
124 | 0 | (RV_X(x, 0, 12) << 20) |
125 | | #define ENCODE_STYPE_IMM(x) \ |
126 | 0 | ((RV_X(x, 0, 5) << 7) | (RV_X(x, 5, 7) << 25)) |
127 | | #define ENCODE_BTYPE_IMM(x) \ |
128 | 0 | ((RV_X(x, 1, 4) << 8) | (RV_X(x, 5, 6) << 25) | (RV_X(x, 11, 1) << 7) | (RV_X(x, 12, 1) << 31)) |
129 | | #define ENCODE_UTYPE_IMM(x) \ |
130 | 0 | (RV_X(x, 12, 20) << 12) |
131 | | #define ENCODE_JTYPE_IMM(x) \ |
132 | 0 | ((RV_X(x, 1, 10) << 21) | (RV_X(x, 11, 1) << 20) | (RV_X(x, 12, 8) << 12) | (RV_X(x, 20, 1) << 31)) |
133 | | #define ENCODE_CITYPE_IMM(x) \ |
134 | 0 | ((RV_X(x, 0, 5) << 2) | (RV_X(x, 5, 1) << 12)) |
135 | | #define ENCODE_CITYPE_LUI_IMM(x) \ |
136 | 0 | ENCODE_CITYPE_IMM ((x) >> RISCV_IMM_BITS) |
137 | | #define ENCODE_CITYPE_ADDI16SP_IMM(x) \ |
138 | | ((RV_X(x, 4, 1) << 6) | (RV_X(x, 5, 1) << 2) | (RV_X(x, 6, 1) << 5) | (RV_X(x, 7, 2) << 3) | (RV_X(x, 9, 1) << 12)) |
139 | | #define ENCODE_CITYPE_LWSP_IMM(x) \ |
140 | | ((RV_X(x, 2, 3) << 4) | (RV_X(x, 5, 1) << 12) | (RV_X(x, 6, 2) << 2)) |
141 | | #define ENCODE_CITYPE_LDSP_IMM(x) \ |
142 | | ((RV_X(x, 3, 2) << 5) | (RV_X(x, 5, 1) << 12) | (RV_X(x, 6, 3) << 2)) |
143 | | #define ENCODE_CSSTYPE_IMM(x) \ |
144 | | (RV_X(x, 0, 6) << 7) |
145 | | #define ENCODE_CSSTYPE_SWSP_IMM(x) \ |
146 | | ((RV_X(x, 2, 4) << 9) | (RV_X(x, 6, 2) << 7)) |
147 | | #define ENCODE_CSSTYPE_SDSP_IMM(x) \ |
148 | | ((RV_X(x, 3, 3) << 10) | (RV_X(x, 6, 3) << 7)) |
149 | | #define ENCODE_CIWTYPE_IMM(x) \ |
150 | | (RV_X(x, 0, 8) << 5) |
151 | | #define ENCODE_CIWTYPE_ADDI4SPN_IMM(x) \ |
152 | | ((RV_X(x, 2, 1) << 6) | (RV_X(x, 3, 1) << 5) | (RV_X(x, 4, 2) << 11) | (RV_X(x, 6, 4) << 7)) |
153 | | #define ENCODE_CLTYPE_IMM(x) \ |
154 | | ((RV_X(x, 0, 2) << 5) | (RV_X(x, 2, 3) << 10)) |
155 | | #define ENCODE_CLTYPE_LW_IMM(x) \ |
156 | | ((RV_X(x, 2, 1) << 6) | (RV_X(x, 3, 3) << 10) | (RV_X(x, 6, 1) << 5)) |
157 | | #define ENCODE_CLTYPE_LD_IMM(x) \ |
158 | | ((RV_X(x, 3, 3) << 10) | (RV_X(x, 6, 2) << 5)) |
159 | | #define ENCODE_CBTYPE_IMM(x) \ |
160 | 0 | ((RV_X(x, 1, 2) << 3) | (RV_X(x, 3, 2) << 10) | (RV_X(x, 5, 1) << 2) | (RV_X(x, 6, 2) << 5) | (RV_X(x, 8, 1) << 12)) |
161 | | #define ENCODE_CJTYPE_IMM(x) \ |
162 | 0 | ((RV_X(x, 1, 3) << 3) | (RV_X(x, 4, 1) << 11) | (RV_X(x, 5, 1) << 2) | (RV_X(x, 6, 1) << 7) | (RV_X(x, 7, 1) << 6) | (RV_X(x, 8, 2) << 9) | (RV_X(x, 10, 1) << 8) | (RV_X(x, 11, 1) << 12)) |
163 | | #define ENCODE_RVV_VB_IMM(x) \ |
164 | | (RV_X(x, 0, 10) << 20) |
165 | | #define ENCODE_RVV_VC_IMM(x) \ |
166 | | (RV_X(x, 0, 11) << 20) |
167 | | #define ENCODE_RVV_VI_UIMM6(x) \ |
168 | | (RV_X(x, 0, 5) << 15 | RV_X(x, 5, 1) << 26) |
169 | | #define ENCODE_ZCB_BYTE_UIMM(x) \ |
170 | | ((RV_X(x, 0, 1) << 6) | (RV_X(x, 1, 1) << 5)) |
171 | | #define ENCODE_ZCB_HALFWORD_UIMM(x) \ |
172 | | (RV_X(x, 1, 1) << 5) |
173 | | #define ENCODE_ZCMP_SPIMM(x) \ |
174 | | (RV_X(x, 4, 2) << 2) |
175 | | /* Vendor-specific (CORE-V) encode macros. */ |
176 | | #define ENCODE_CV_IS2_UIMM5(x) \ |
177 | | (RV_X(x, 0, 5) << 20) |
178 | | #define ENCODE_CV_IS3_UIMM5(x) \ |
179 | | (RV_X(x, 0, 5) << 25) |
180 | | |
181 | 0 | #define VALID_ITYPE_IMM(x) (EXTRACT_ITYPE_IMM(ENCODE_ITYPE_IMM(x)) == (x)) |
182 | | #define VALID_STYPE_IMM(x) (EXTRACT_STYPE_IMM(ENCODE_STYPE_IMM(x)) == (x)) |
183 | 0 | #define VALID_BTYPE_IMM(x) (EXTRACT_BTYPE_IMM(ENCODE_BTYPE_IMM(x)) == (x)) |
184 | 0 | #define VALID_UTYPE_IMM(x) (EXTRACT_UTYPE_IMM(ENCODE_UTYPE_IMM(x)) == (x)) |
185 | 0 | #define VALID_JTYPE_IMM(x) (EXTRACT_JTYPE_IMM(ENCODE_JTYPE_IMM(x)) == (x)) |
186 | | #define VALID_CITYPE_IMM(x) (EXTRACT_CITYPE_IMM(ENCODE_CITYPE_IMM(x)) == (x)) |
187 | 0 | #define VALID_CITYPE_LUI_IMM(x) (ENCODE_CITYPE_LUI_IMM(x) != 0 \ |
188 | 0 | && EXTRACT_CITYPE_LUI_IMM(ENCODE_CITYPE_LUI_IMM(x)) == (x)) |
189 | | #define VALID_CITYPE_ADDI16SP_IMM(x) (ENCODE_CITYPE_ADDI16SP_IMM(x) != 0 \ |
190 | | && EXTRACT_CITYPE_ADDI16SP_IMM(ENCODE_CITYPE_ADDI16SP_IMM(x)) == (x)) |
191 | | #define VALID_CITYPE_LWSP_IMM(x) (EXTRACT_CITYPE_LWSP_IMM(ENCODE_CITYPE_LWSP_IMM(x)) == (x)) |
192 | | #define VALID_CITYPE_LDSP_IMM(x) (EXTRACT_CITYPE_LDSP_IMM(ENCODE_CITYPE_LDSP_IMM(x)) == (x)) |
193 | | #define VALID_CSSTYPE_IMM(x) (EXTRACT_CSSTYPE_IMM(ENCODE_CSSTYPE_IMM(x)) == (x)) |
194 | | #define VALID_CSSTYPE_SWSP_IMM(x) (EXTRACT_CSSTYPE_SWSP_IMM(ENCODE_CSSTYPE_SWSP_IMM(x)) == (x)) |
195 | | #define VALID_CSSTYPE_SDSP_IMM(x) (EXTRACT_CSSTYPE_SDSP_IMM(ENCODE_CSSTYPE_SDSP_IMM(x)) == (x)) |
196 | | #define VALID_CIWTYPE_IMM(x) (EXTRACT_CIWTYPE_IMM(ENCODE_CIWTYPE_IMM(x)) == (x)) |
197 | | #define VALID_CIWTYPE_ADDI4SPN_IMM(x) (EXTRACT_CIWTYPE_ADDI4SPN_IMM(ENCODE_CIWTYPE_ADDI4SPN_IMM(x)) == (x)) |
198 | | #define VALID_CLTYPE_IMM(x) (EXTRACT_CLTYPE_IMM(ENCODE_CLTYPE_IMM(x)) == (x)) |
199 | | #define VALID_CLTYPE_LW_IMM(x) (EXTRACT_CLTYPE_LW_IMM(ENCODE_CLTYPE_LW_IMM(x)) == (x)) |
200 | | #define VALID_CLTYPE_LD_IMM(x) (EXTRACT_CLTYPE_LD_IMM(ENCODE_CLTYPE_LD_IMM(x)) == (x)) |
201 | 0 | #define VALID_CBTYPE_IMM(x) (EXTRACT_CBTYPE_IMM(ENCODE_CBTYPE_IMM(x)) == (x)) |
202 | 0 | #define VALID_CJTYPE_IMM(x) (EXTRACT_CJTYPE_IMM(ENCODE_CJTYPE_IMM(x)) == (x)) |
203 | | #define VALID_RVV_VB_IMM(x) (EXTRACT_RVV_VB_IMM(ENCODE_RVV_VB_IMM(x)) == (x)) |
204 | | #define VALID_RVV_VC_IMM(x) (EXTRACT_RVV_VC_IMM(ENCODE_RVV_VC_IMM(x)) == (x)) |
205 | | #define VALID_ZCB_BYTE_UIMM(x) (EXTRACT_ZCB_BYTE_UIMM(ENCODE_ZCB_BYTE_UIMM(x)) == (x)) |
206 | | #define VALID_ZCB_HALFWORD_UIMM(x) (EXTRACT_ZCB_HALFWORD_UIMM(ENCODE_ZCB_HALFWORD_UIMM(x)) == (x)) |
207 | | #define VALID_ZCMP_SPIMM(x) (EXTRACT_ZCMP_SPIMM(ENCODE_ZCMP_SPIMM(x)) == (x)) |
208 | | |
209 | | #define RISCV_RTYPE(insn, rd, rs1, rs2) \ |
210 | 0 | ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ((rs1) << OP_SH_RS1) | ((rs2) << OP_SH_RS2)) |
211 | | #define RISCV_ITYPE(insn, rd, rs1, imm) \ |
212 | 0 | ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ((rs1) << OP_SH_RS1) | ENCODE_ITYPE_IMM(imm)) |
213 | | #define RISCV_STYPE(insn, rs1, rs2, imm) \ |
214 | | ((MATCH_ ## insn) | ((rs1) << OP_SH_RS1) | ((rs2) << OP_SH_RS2) | ENCODE_STYPE_IMM(imm)) |
215 | | #define RISCV_BTYPE(insn, rs1, rs2, target) \ |
216 | | ((MATCH_ ## insn) | ((rs1) << OP_SH_RS1) | ((rs2) << OP_SH_RS2) | ENCODE_BTYPE_IMM(target)) |
217 | | #define RISCV_UTYPE(insn, rd, bigimm) \ |
218 | 0 | ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ENCODE_UTYPE_IMM(bigimm)) |
219 | | #define RISCV_JTYPE(insn, rd, target) \ |
220 | | ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ENCODE_JTYPE_IMM(target)) |
221 | | |
222 | 0 | #define RISCV_NOP RISCV_ITYPE(ADDI, 0, 0, 0) |
223 | 0 | #define RVC_NOP MATCH_C_ADDI |
224 | | |
225 | | #define RISCV_CONST_HIGH_PART(VALUE) \ |
226 | 0 | (((VALUE) + (RISCV_IMM_REACH/2)) & ~(RISCV_IMM_REACH-1)) |
227 | 0 | #define RISCV_CONST_LOW_PART(VALUE) ((VALUE) - RISCV_CONST_HIGH_PART (VALUE)) |
228 | 0 | #define RISCV_PCREL_HIGH_PART(VALUE, PC) RISCV_CONST_HIGH_PART((VALUE) - (PC)) |
229 | 0 | #define RISCV_PCREL_LOW_PART(VALUE, PC) RISCV_CONST_LOW_PART((VALUE) - (PC)) |
230 | | |
231 | | #define RISCV_JUMP_BITS RISCV_BIGIMM_BITS |
232 | | #define RISCV_JUMP_ALIGN_BITS 1 |
233 | | #define RISCV_JUMP_ALIGN (1 << RISCV_JUMP_ALIGN_BITS) |
234 | | #define RISCV_JUMP_REACH ((1ULL << RISCV_JUMP_BITS) * RISCV_JUMP_ALIGN) |
235 | | |
236 | 46.0k | #define RISCV_IMM_BITS 12 |
237 | 13.3k | #define RISCV_BIGIMM_BITS (32 - RISCV_IMM_BITS) |
238 | 0 | #define RISCV_IMM_REACH (1LL << RISCV_IMM_BITS) |
239 | 13.3k | #define RISCV_BIGIMM_REACH (1LL << RISCV_BIGIMM_BITS) |
240 | | #define RISCV_RVC_IMM_REACH (1LL << 6) |
241 | | #define RISCV_BRANCH_BITS RISCV_IMM_BITS |
242 | | #define RISCV_BRANCH_ALIGN_BITS RISCV_JUMP_ALIGN_BITS |
243 | | #define RISCV_BRANCH_ALIGN (1 << RISCV_BRANCH_ALIGN_BITS) |
244 | | #define RISCV_BRANCH_REACH (RISCV_IMM_REACH * RISCV_BRANCH_ALIGN) |
245 | | |
246 | | /* RV fields. */ |
247 | | |
248 | 111k | #define OP_MASK_OP 0x7f |
249 | | #define OP_SH_OP 0 |
250 | 2.27M | #define OP_MASK_RS2 0x1f |
251 | 4.55M | #define OP_SH_RS2 20 |
252 | 4.39M | #define OP_MASK_RS1 0x1f |
253 | 8.29M | #define OP_SH_RS1 15 |
254 | | #define OP_MASK_RS3 0x1fU |
255 | | #define OP_SH_RS3 27 |
256 | 2.64M | #define OP_MASK_RD 0x1f |
257 | 4.62M | #define OP_SH_RD 7 |
258 | | #define OP_MASK_SHAMT 0x3f |
259 | | #define OP_SH_SHAMT 20 |
260 | | #define OP_MASK_SHAMTW 0x1f |
261 | | #define OP_SH_SHAMTW 20 |
262 | | #define OP_MASK_RM 0x7 |
263 | | #define OP_SH_RM 12 |
264 | | #define OP_MASK_PRED 0xf |
265 | | #define OP_SH_PRED 24 |
266 | | #define OP_MASK_SUCC 0xf |
267 | | #define OP_SH_SUCC 20 |
268 | | #define OP_MASK_AQ 0x1 |
269 | | #define OP_SH_AQ 26 |
270 | | #define OP_MASK_RL 0x1 |
271 | | #define OP_SH_RL 25 |
272 | | |
273 | | #define OP_MASK_CSR 0xfffU |
274 | | #define OP_SH_CSR 20 |
275 | | |
276 | | #define OP_MASK_FUNCT3 0x7 |
277 | | #define OP_SH_FUNCT3 12 |
278 | | #define OP_MASK_FUNCT7 0x7fU |
279 | | #define OP_SH_FUNCT7 25 |
280 | | #define OP_MASK_FUNCT2 0x3 |
281 | | #define OP_SH_FUNCT2 25 |
282 | | |
283 | | /* RVC fields. */ |
284 | | |
285 | | #define OP_MASK_OP2 0x3 |
286 | | #define OP_SH_OP2 0 |
287 | | |
288 | 7.72k | #define OP_MASK_CRS2 0x1f |
289 | 7.72k | #define OP_SH_CRS2 2 |
290 | | #define OP_MASK_CRS1S 0x7 |
291 | | #define OP_SH_CRS1S 7 |
292 | | #define OP_MASK_CRS2S 0x7 |
293 | | #define OP_SH_CRS2S 2 |
294 | | |
295 | | #define OP_MASK_CFUNCT6 0x3f |
296 | | #define OP_SH_CFUNCT6 10 |
297 | | #define OP_MASK_CFUNCT4 0xf |
298 | | #define OP_SH_CFUNCT4 12 |
299 | | #define OP_MASK_CFUNCT3 0x7 |
300 | | #define OP_SH_CFUNCT3 13 |
301 | | #define OP_MASK_CFUNCT2 0x3 |
302 | | #define OP_SH_CFUNCT2 5 |
303 | | |
304 | | /* Scalar crypto fields. */ |
305 | | |
306 | | #define OP_SH_BS 30 |
307 | | #define OP_MASK_BS 3 |
308 | | #define OP_SH_RNUM 20 |
309 | | #define OP_MASK_RNUM 0xf |
310 | | |
311 | | /* RVV fields. */ |
312 | | |
313 | 445k | #define OP_MASK_VD 0x1f |
314 | 891k | #define OP_SH_VD 7 |
315 | 1.77M | #define OP_MASK_VS1 0x1f |
316 | 3.55M | #define OP_SH_VS1 15 |
317 | 1.77M | #define OP_MASK_VS2 0x1f |
318 | 3.55M | #define OP_SH_VS2 20 |
319 | | #define OP_MASK_VIMM 0x1f |
320 | | #define OP_SH_VIMM 15 |
321 | | #define OP_MASK_VMASK 0x1 |
322 | | #define OP_SH_VMASK 25 |
323 | | #define OP_MASK_VFUNCT6 0x3f |
324 | | #define OP_SH_VFUNCT6 26 |
325 | | #define OP_MASK_VLMUL 0x7 |
326 | | #define OP_SH_VLMUL 0 |
327 | | #define OP_MASK_VSEW 0x7 |
328 | | #define OP_SH_VSEW 3 |
329 | | #define OP_MASK_VTA 0x1 |
330 | | #define OP_SH_VTA 6 |
331 | | #define OP_MASK_VMA 0x1 |
332 | | #define OP_SH_VMA 7 |
333 | | #define OP_MASK_VWD 0x1 |
334 | | #define OP_SH_VWD 26 |
335 | | |
336 | | #define OP_MASK_XTHEADVLMUL 0x3 |
337 | | #define OP_SH_XTHEADVLMUL 0 |
338 | | #define OP_MASK_XTHEADVSEW 0x7 |
339 | | #define OP_SH_XTHEADVSEW 2 |
340 | | #define OP_MASK_XTHEADVEDIV 0x3 |
341 | | #define OP_SH_XTHEADVEDIV 5 |
342 | | #define OP_MASK_XTHEADVTYPE_RES 0xf |
343 | | #define OP_SH_XTHEADVTYPE_RES 7 |
344 | | |
345 | | /* Zc fields. */ |
346 | | #define OP_MASK_REG_LIST 0xf |
347 | | #define OP_SH_REG_LIST 4 |
348 | 0 | #define ZCMP_SP_ALIGNMENT 16 |
349 | | |
350 | | #define NVECR 32 |
351 | | #define NVECM 1 |
352 | | |
353 | | /* SiFive fields. */ |
354 | | #define OP_MASK_XSO2 0x3 |
355 | | #define OP_SH_XSO2 26 |
356 | | #define OP_MASK_XSO1 0x1 |
357 | | #define OP_SH_XSO1 26 |
358 | | |
359 | | /* ABI names for selected x-registers. */ |
360 | | |
361 | 0 | #define X_RA 1 |
362 | 126k | #define X_SP 2 |
363 | 65.8k | #define X_GP 3 |
364 | 65.8k | #define X_TP 4 |
365 | | #define X_T0 5 |
366 | | #define X_T1 6 |
367 | | #define X_T2 7 |
368 | 0 | #define X_S0 8 |
369 | 0 | #define X_S1 9 |
370 | 0 | #define X_S2 18 |
371 | | #define X_S10 26 |
372 | 0 | #define X_S11 27 |
373 | | #define X_T3 28 |
374 | | |
375 | | #define NGPR 32 |
376 | | #define NFPR 32 |
377 | | |
378 | | /* These fake label defines are use by both the assembler, and |
379 | | libopcodes. The assembler uses this when it needs to generate a fake |
380 | | label, and libopcodes uses it to hide the fake labels in its output. */ |
381 | 222 | #define RISCV_FAKE_LABEL_NAME ".L0 " |
382 | | #define RISCV_FAKE_LABEL_CHAR ' ' |
383 | | |
384 | | /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in |
385 | | VALUE << SHIFT. VALUE is evaluated exactly once. */ |
386 | | #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \ |
387 | | (STRUCT) = (((STRUCT) & ~((insn_t)(MASK) << (SHIFT))) \ |
388 | | | ((insn_t)((VALUE) & (MASK)) << (SHIFT))) |
389 | | |
390 | | /* Extract bits MASK << SHIFT from STRUCT and shift them right |
391 | | SHIFT places. */ |
392 | | #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \ |
393 | 380k | (((STRUCT) >> (SHIFT)) & (MASK)) |
394 | | |
395 | | /* Extract the operand given by FIELD from integer INSN. */ |
396 | | #define EXTRACT_OPERAND(FIELD, INSN) \ |
397 | 380k | ((unsigned int) EXTRACT_BITS ((INSN), OP_MASK_##FIELD, OP_SH_##FIELD)) |
398 | | |
399 | | /* Extract an unsigned immediate operand on position s with n bits. */ |
400 | | #define EXTRACT_U_IMM(n, s, l) \ |
401 | 0 | RV_X (l, s, n) |
402 | | |
403 | | /* Extract an signed immediate operand on position s with n bits. */ |
404 | | #define EXTRACT_S_IMM(n, s, l) \ |
405 | 0 | RV_X_SIGNED (l, s, n) |
406 | | |
407 | | /* Validate that unsigned n-bit immediate is within bounds. */ |
408 | | #define VALIDATE_U_IMM(v, n) \ |
409 | | ((unsigned long) v < (1UL << n)) |
410 | | |
411 | | /* Validate that signed n-bit immediate is within bounds. */ |
412 | | #define VALIDATE_S_IMM(v, n) \ |
413 | | (v < (long) (1UL << (n-1)) && v >= -(offsetT) (1UL << (n-1))) |
414 | | |
415 | | /* The maximal number of subset can be required. */ |
416 | | #define MAX_SUBSET_NUM 4 |
417 | | |
418 | | /* All RISC-V instructions belong to at least one of these classes. */ |
419 | | enum riscv_insn_class |
420 | | { |
421 | | INSN_CLASS_NONE, |
422 | | |
423 | | INSN_CLASS_I, |
424 | | INSN_CLASS_C, |
425 | | INSN_CLASS_M, |
426 | | INSN_CLASS_F, |
427 | | INSN_CLASS_D, |
428 | | INSN_CLASS_Q, |
429 | | INSN_CLASS_F_AND_C, |
430 | | INSN_CLASS_D_AND_C, |
431 | | INSN_CLASS_ZICOND, |
432 | | INSN_CLASS_ZICSR, |
433 | | INSN_CLASS_ZIFENCEI, |
434 | | INSN_CLASS_ZIHINTNTL, |
435 | | INSN_CLASS_ZIHINTNTL_AND_C, |
436 | | INSN_CLASS_ZIHINTPAUSE, |
437 | | INSN_CLASS_ZMMUL, |
438 | | INSN_CLASS_ZAAMO, |
439 | | INSN_CLASS_ZALRSC, |
440 | | INSN_CLASS_ZAWRS, |
441 | | INSN_CLASS_F_INX, |
442 | | INSN_CLASS_D_INX, |
443 | | INSN_CLASS_Q_INX, |
444 | | INSN_CLASS_ZFH_INX, |
445 | | INSN_CLASS_ZFHMIN, |
446 | | INSN_CLASS_ZFHMIN_INX, |
447 | | INSN_CLASS_ZFHMIN_AND_D_INX, |
448 | | INSN_CLASS_ZFHMIN_AND_Q_INX, |
449 | | INSN_CLASS_ZFA, |
450 | | INSN_CLASS_D_AND_ZFA, |
451 | | INSN_CLASS_Q_AND_ZFA, |
452 | | INSN_CLASS_ZFH_AND_ZFA, |
453 | | INSN_CLASS_ZFH_OR_ZVFH_AND_ZFA, |
454 | | INSN_CLASS_ZBA, |
455 | | INSN_CLASS_ZBB, |
456 | | INSN_CLASS_ZBC, |
457 | | INSN_CLASS_ZBS, |
458 | | INSN_CLASS_ZBKB, |
459 | | INSN_CLASS_ZBKC, |
460 | | INSN_CLASS_ZBKX, |
461 | | INSN_CLASS_ZKND, |
462 | | INSN_CLASS_ZKNE, |
463 | | INSN_CLASS_ZKNH, |
464 | | INSN_CLASS_ZKSED, |
465 | | INSN_CLASS_ZKSH, |
466 | | INSN_CLASS_ZBB_OR_ZBKB, |
467 | | INSN_CLASS_ZBC_OR_ZBKC, |
468 | | INSN_CLASS_ZKND_OR_ZKNE, |
469 | | INSN_CLASS_V, |
470 | | INSN_CLASS_ZVEF, |
471 | | INSN_CLASS_ZVBB, |
472 | | INSN_CLASS_ZVBC, |
473 | | INSN_CLASS_ZVKB, |
474 | | INSN_CLASS_ZVKG, |
475 | | INSN_CLASS_ZVKNED, |
476 | | INSN_CLASS_ZVKNHA_OR_ZVKNHB, |
477 | | INSN_CLASS_ZVKSED, |
478 | | INSN_CLASS_ZVKSH, |
479 | | INSN_CLASS_ZCB, |
480 | | INSN_CLASS_ZCB_AND_ZBA, |
481 | | INSN_CLASS_ZCB_AND_ZBB, |
482 | | INSN_CLASS_ZCB_AND_ZMMUL, |
483 | | INSN_CLASS_ZCMP, |
484 | | INSN_CLASS_SVINVAL, |
485 | | INSN_CLASS_ZICBOM, |
486 | | INSN_CLASS_ZICBOP, |
487 | | INSN_CLASS_ZICBOZ, |
488 | | INSN_CLASS_ZABHA, |
489 | | INSN_CLASS_H, |
490 | | INSN_CLASS_XCVMAC, |
491 | | INSN_CLASS_XCVALU, |
492 | | INSN_CLASS_XTHEADBA, |
493 | | INSN_CLASS_XTHEADBB, |
494 | | INSN_CLASS_XTHEADBS, |
495 | | INSN_CLASS_XTHEADCMO, |
496 | | INSN_CLASS_XTHEADCONDMOV, |
497 | | INSN_CLASS_XTHEADFMEMIDX, |
498 | | INSN_CLASS_XTHEADFMV, |
499 | | INSN_CLASS_XTHEADINT, |
500 | | INSN_CLASS_XTHEADMAC, |
501 | | INSN_CLASS_XTHEADMEMIDX, |
502 | | INSN_CLASS_XTHEADMEMPAIR, |
503 | | INSN_CLASS_XTHEADSYNC, |
504 | | INSN_CLASS_XTHEADVECTOR, |
505 | | INSN_CLASS_XTHEADZVAMO, |
506 | | INSN_CLASS_XVENTANACONDOPS, |
507 | | INSN_CLASS_XSFVCP, |
508 | | }; |
509 | | |
510 | | /* This structure holds information for a particular instruction. */ |
511 | | struct riscv_opcode |
512 | | { |
513 | | /* The name of the instruction. */ |
514 | | const char *name; |
515 | | |
516 | | /* The requirement of xlen for the instruction, 0 if no requirement. */ |
517 | | unsigned xlen_requirement; |
518 | | |
519 | | /* Class to which this instruction belongs. Used to decide whether or |
520 | | not this instruction is legal in the current -march context. */ |
521 | | enum riscv_insn_class insn_class; |
522 | | |
523 | | /* A string describing the arguments for this instruction. */ |
524 | | const char *args; |
525 | | |
526 | | /* The basic opcode for the instruction. When assembling, this |
527 | | opcode is modified by the arguments to produce the actual opcode |
528 | | that is used. If pinfo is INSN_MACRO, then this is 0. */ |
529 | | insn_t match; |
530 | | |
531 | | /* If pinfo is not INSN_MACRO, then this is a bit mask for the |
532 | | relevant portions of the opcode when disassembling. If the |
533 | | actual opcode anded with the match field equals the opcode field, |
534 | | then we have found the correct instruction. If pinfo is |
535 | | INSN_MACRO, then this field is the macro identifier. */ |
536 | | insn_t mask; |
537 | | |
538 | | /* A function to determine if a word corresponds to this instruction. |
539 | | Usually, this computes ((word & mask) == match). */ |
540 | | int (*match_func) (const struct riscv_opcode *op, insn_t word); |
541 | | |
542 | | /* For a macro, this is INSN_MACRO. Otherwise, it is a collection |
543 | | of bits describing the instruction, notably any relevant hazard |
544 | | information. */ |
545 | | unsigned long pinfo; |
546 | | }; |
547 | | |
548 | | /* Instruction is a simple alias (e.g. "mv" for "addi"). */ |
549 | 0 | #define INSN_ALIAS 0x00000001 |
550 | | |
551 | | /* These are for setting insn_info fields. |
552 | | |
553 | | Nonbranch is the default. Noninsn is used only if there is no match. |
554 | | There are no condjsr or dref2 instructions. So that leaves condbranch, |
555 | | branch, jsr, and dref that we need to handle here, encoded in 3 bits. */ |
556 | 506k | #define INSN_TYPE 0x0000000e |
557 | | |
558 | | /* Instruction is an unconditional branch. */ |
559 | 13.5k | #define INSN_BRANCH 0x00000002 |
560 | | /* Instruction is a conditional branch. */ |
561 | 24.7k | #define INSN_CONDBRANCH 0x00000004 |
562 | | /* Instruction is a jump to subroutine. */ |
563 | 5.87k | #define INSN_JSR 0x00000006 |
564 | | /* Instruction is a data reference. */ |
565 | 202k | #define INSN_DREF 0x00000008 |
566 | | /* Instruction is allowed when eew >= 64. */ |
567 | | #define INSN_V_EEW64 0x10000000 |
568 | | |
569 | | /* We have 5 data reference sizes, which we can encode in 3 bits. */ |
570 | 708k | #define INSN_DATA_SIZE 0x00000070 |
571 | 202k | #define INSN_DATA_SIZE_SHIFT 4 |
572 | | #define INSN_1_BYTE 0x00000010 |
573 | | #define INSN_2_BYTE 0x00000020 |
574 | | #define INSN_4_BYTE 0x00000030 |
575 | | #define INSN_8_BYTE 0x00000040 |
576 | | #define INSN_16_BYTE 0x00000050 |
577 | | |
578 | | /* Instruction is actually a macro. It should be ignored by the |
579 | | disassembler, and requires special treatment by the assembler. */ |
580 | 356M | #define INSN_MACRO 0xffffffff |
581 | | |
582 | | /* This is a list of macro expanded instructions. */ |
583 | | enum |
584 | | { |
585 | | M_LA, |
586 | | M_LLA, |
587 | | M_LGA, |
588 | | M_LA_TLS_GD, |
589 | | M_LA_TLS_IE, |
590 | | M_Lx, |
591 | | M_FLx, |
592 | | M_Sx_FSx, |
593 | | M_CALL, |
594 | | M_J, |
595 | | M_LI, |
596 | | M_EXTH, |
597 | | M_ZEXTW, |
598 | | M_SEXTB, |
599 | | M_VMSGE, |
600 | | M_NUM_MACROS |
601 | | }; |
602 | | |
603 | | /* The mapping symbol states. */ |
604 | | enum riscv_seg_mstate |
605 | | { |
606 | | MAP_NONE = 0, /* Must be zero, for seginfo in new sections. */ |
607 | | MAP_DATA, /* Data. */ |
608 | | MAP_INSN, /* Instructions. */ |
609 | | }; |
610 | | |
611 | | #define NRC (4 + 1) /* Max characters in register names, incl nul. */ |
612 | | |
613 | | extern const char riscv_gpr_names_numeric[NGPR][NRC]; |
614 | | extern const char riscv_gpr_names_abi[NGPR][NRC]; |
615 | | extern const char riscv_fpr_names_numeric[NFPR][NRC]; |
616 | | extern const char riscv_fpr_names_abi[NFPR][NRC]; |
617 | | extern const char * const riscv_rm[8]; |
618 | | extern const char * const riscv_pred_succ[16]; |
619 | | extern const char riscv_vecr_names_numeric[NVECR][NRC]; |
620 | | extern const char riscv_vecm_names_numeric[NVECM][NRC]; |
621 | | extern const char * const riscv_vsew[8]; |
622 | | extern const char * const riscv_vlmul[8]; |
623 | | extern const char * const riscv_vta[2]; |
624 | | extern const char * const riscv_vma[2]; |
625 | | extern const char * const riscv_th_vlen[4]; |
626 | | extern const char * const riscv_th_vediv[4]; |
627 | | extern const char * const riscv_fli_symval[32]; |
628 | | extern const float riscv_fli_numval[32]; |
629 | | |
630 | | extern const struct riscv_opcode riscv_opcodes[]; |
631 | | extern const struct riscv_opcode riscv_insn_types[]; |
632 | | |
633 | | extern unsigned int riscv_get_sp_base (insn_t, unsigned int); |
634 | | |
635 | | #endif /* _RISCV_H_ */ |