Coverage Report

Created: 2024-05-21 06:29

/src/binutils-gdb/opcodes/aarch64-dis.c
Line
Count
Source (jump to first uncovered line)
1
/* aarch64-dis.c -- AArch64 disassembler.
2
   Copyright (C) 2009-2024 Free Software Foundation, Inc.
3
   Contributed by ARM Ltd.
4
5
   This file is part of the GNU opcodes library.
6
7
   This library is free software; you can redistribute it and/or modify
8
   it under the terms of the GNU General Public License as published by
9
   the Free Software Foundation; either version 3, or (at your option)
10
   any later version.
11
12
   It is distributed in the hope that it will be useful, but WITHOUT
13
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
15
   License for more details.
16
17
   You should have received a copy of the GNU General Public License
18
   along with this program; see the file COPYING3. If not,
19
   see <http://www.gnu.org/licenses/>.  */
20
21
#include "sysdep.h"
22
#include <stdint.h>
23
#include "disassemble.h"
24
#include "libiberty.h"
25
#include "opintl.h"
26
#include "aarch64-dis.h"
27
#include "elf-bfd.h"
28
#include "safe-ctype.h"
29
#include "obstack.h"
30
31
#define obstack_chunk_alloc xmalloc
32
#define obstack_chunk_free free
33
34
12.0M
#define INSNLEN 4
35
36
/* This character is used to encode style information within the output
37
   buffers.  See get_style_text and print_operands for more details.  */
38
166M
#define STYLE_MARKER_CHAR '\002'
39
40
/* Cached mapping symbol state.  */
41
enum map_type
42
{
43
  MAP_INSN,
44
  MAP_DATA
45
};
46
47
static aarch64_feature_set arch_variant; /* See select_aarch64_variant.  */
48
static enum map_type last_type;
49
static int last_mapping_sym = -1;
50
static bfd_vma last_stop_offset = 0;
51
static bfd_vma last_mapping_addr = 0;
52
53
/* Other options */
54
static int no_aliases = 0;  /* If set disassemble as most general inst.  */
55
static int no_notes = 1; /* If set do not print disassemble notes in the
56
          output as comments.  */
57
58
/* Currently active instruction sequence.  */
59
static aarch64_instr_sequence insn_sequence;
60
61
static void
62
set_default_aarch64_dis_options (struct disassemble_info *info ATTRIBUTE_UNUSED)
63
0
{
64
0
}
65
66
static void
67
parse_aarch64_dis_option (const char *option, unsigned int len ATTRIBUTE_UNUSED)
68
0
{
69
  /* Try to match options that are simple flags */
70
0
  if (startswith (option, "no-aliases"))
71
0
    {
72
0
      no_aliases = 1;
73
0
      return;
74
0
    }
75
76
0
  if (startswith (option, "aliases"))
77
0
    {
78
0
      no_aliases = 0;
79
0
      return;
80
0
    }
81
82
0
  if (startswith (option, "no-notes"))
83
0
    {
84
0
      no_notes = 1;
85
0
      return;
86
0
    }
87
88
0
  if (startswith (option, "notes"))
89
0
    {
90
0
      no_notes = 0;
91
0
      return;
92
0
    }
93
94
#ifdef DEBUG_AARCH64
95
  if (startswith (option, "debug_dump"))
96
    {
97
      debug_dump = 1;
98
      return;
99
    }
100
#endif /* DEBUG_AARCH64 */
101
102
  /* Invalid option.  */
103
0
  opcodes_error_handler (_("unrecognised disassembler option: %s"), option);
104
0
}
105
106
static void
107
parse_aarch64_dis_options (const char *options)
108
0
{
109
0
  const char *option_end;
110
111
0
  if (options == NULL)
112
0
    return;
113
114
0
  while (*options != '\0')
115
0
    {
116
      /* Skip empty options.  */
117
0
      if (*options == ',')
118
0
  {
119
0
    options++;
120
0
    continue;
121
0
  }
122
123
      /* We know that *options is neither NUL or a comma.  */
124
0
      option_end = options + 1;
125
0
      while (*option_end != ',' && *option_end != '\0')
126
0
  option_end++;
127
128
0
      parse_aarch64_dis_option (options, option_end - options);
129
130
      /* Go on to the next one.  If option_end points to a comma, it
131
   will be skipped above.  */
132
0
      options = option_end;
133
0
    }
134
0
}
135

136
/* Functions doing the instruction disassembling.  */
137
138
/* The unnamed arguments consist of the number of fields and information about
139
   these fields where the VALUE will be extracted from CODE and returned.
140
   MASK can be zero or the base mask of the opcode.
141
142
   N.B. the fields are required to be in such an order than the most signficant
143
   field for VALUE comes the first, e.g. the <index> in
144
    SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>]
145
   is encoded in H:L:M in some cases, the fields H:L:M should be passed in
146
   the order of H, L, M.  */
147
148
aarch64_insn
149
extract_fields (aarch64_insn code, aarch64_insn mask, ...)
150
1.13M
{
151
1.13M
  uint32_t num;
152
1.13M
  const aarch64_field *field;
153
1.13M
  enum aarch64_field_kind kind;
154
1.13M
  va_list va;
155
156
1.13M
  va_start (va, mask);
157
1.13M
  num = va_arg (va, uint32_t);
158
1.13M
  assert (num <= 5);
159
1.13M
  aarch64_insn value = 0x0;
160
3.75M
  while (num--)
161
2.62M
    {
162
2.62M
      kind = va_arg (va, enum aarch64_field_kind);
163
2.62M
      field = &fields[kind];
164
2.62M
      value <<= field->width;
165
2.62M
      value |= extract_field (kind, code, mask);
166
2.62M
    }
167
1.13M
  va_end (va);
168
1.13M
  return value;
169
1.13M
}
170
171
/* Extract the value of all fields in SELF->fields after START from
172
   instruction CODE.  The least significant bit comes from the final field.  */
173
174
static aarch64_insn
175
extract_all_fields_after (const aarch64_operand *self, unsigned int start,
176
        aarch64_insn code)
177
3.03M
{
178
3.03M
  aarch64_insn value;
179
3.03M
  unsigned int i;
180
3.03M
  enum aarch64_field_kind kind;
181
182
3.03M
  value = 0;
183
3.03M
  for (i = start;
184
6.62M
       i < ARRAY_SIZE (self->fields) && self->fields[i] != FLD_NIL; ++i)
185
3.58M
    {
186
3.58M
      kind = self->fields[i];
187
3.58M
      value <<= fields[kind].width;
188
3.58M
      value |= extract_field (kind, code, 0);
189
3.58M
    }
190
3.03M
  return value;
191
3.03M
}
192
193
/* Extract the value of all fields in SELF->fields from instruction CODE.
194
   The least significant bit comes from the final field.  */
195
196
static aarch64_insn
197
extract_all_fields (const aarch64_operand *self, aarch64_insn code)
198
3.02M
{
199
3.02M
  return extract_all_fields_after (self, 0, code);
200
3.02M
}
201
202
/* Sign-extend bit I of VALUE.  */
203
static inline uint64_t
204
sign_extend (aarch64_insn value, unsigned i)
205
1.60M
{
206
1.60M
  uint64_t ret, sign;
207
208
1.60M
  assert (i < 32);
209
1.60M
  ret = value;
210
1.60M
  sign = (uint64_t) 1 << i;
211
1.60M
  return ((ret & (sign + sign - 1)) ^ sign) - sign;
212
1.60M
}
213
214
/* N.B. the following inline helpfer functions create a dependency on the
215
   order of operand qualifier enumerators.  */
216
217
/* Given VALUE, return qualifier for a general purpose register.  */
218
static inline enum aarch64_opnd_qualifier
219
get_greg_qualifier_from_value (aarch64_insn value)
220
2.08M
{
221
2.08M
  enum aarch64_opnd_qualifier qualifier = AARCH64_OPND_QLF_W + value;
222
2.08M
  if (value <= 0x1
223
2.08M
      && aarch64_get_qualifier_standard_value (qualifier) == value)
224
2.08M
    return qualifier;
225
0
  return AARCH64_OPND_QLF_ERR;
226
2.08M
}
227
228
/* Given VALUE, return qualifier for a vector register.  This does not support
229
   decoding instructions that accept the 2H vector type.  */
230
231
static inline enum aarch64_opnd_qualifier
232
get_vreg_qualifier_from_value (aarch64_insn value)
233
155k
{
234
155k
  enum aarch64_opnd_qualifier qualifier = AARCH64_OPND_QLF_V_8B + value;
235
236
  /* Instructions using vector type 2H should not call this function.  Skip over
237
     the 2H qualifier.  */
238
155k
  if (qualifier >= AARCH64_OPND_QLF_V_2H)
239
107k
    qualifier += 1;
240
241
155k
  if (value <= 0x8
242
155k
      && aarch64_get_qualifier_standard_value (qualifier) == value)
243
155k
    return qualifier;
244
0
  return AARCH64_OPND_QLF_ERR;
245
155k
}
246
247
/* Given VALUE, return qualifier for an FP or AdvSIMD scalar register.  */
248
static inline enum aarch64_opnd_qualifier
249
get_sreg_qualifier_from_value (aarch64_insn value)
250
154k
{
251
154k
  enum aarch64_opnd_qualifier qualifier = AARCH64_OPND_QLF_S_B + value;
252
253
154k
  if (value <= 0x4
254
154k
      && aarch64_get_qualifier_standard_value (qualifier) == value)
255
151k
    return qualifier;
256
3.24k
  return AARCH64_OPND_QLF_ERR;
257
154k
}
258
259
/* Given the instruction in *INST which is probably half way through the
260
   decoding and our caller wants to know the expected qualifier for operand
261
   I.  Return such a qualifier if we can establish it; otherwise return
262
   AARCH64_OPND_QLF_NIL.  */
263
264
static aarch64_opnd_qualifier_t
265
get_expected_qualifier (const aarch64_inst *inst, int i)
266
818k
{
267
818k
  aarch64_opnd_qualifier_seq_t qualifiers;
268
  /* Should not be called if the qualifier is known.  */
269
818k
  if (inst->operands[i].qualifier == AARCH64_OPND_QLF_NIL)
270
818k
    {
271
818k
      int invalid_count;
272
818k
      if (aarch64_find_best_match (inst, inst->opcode->qualifiers_list,
273
818k
           i, qualifiers, &invalid_count))
274
797k
  return qualifiers[i];
275
21.3k
      else
276
21.3k
  return AARCH64_OPND_QLF_NIL;
277
818k
    }
278
0
  else
279
0
    return AARCH64_OPND_QLF_ERR;
280
818k
}
281
282
/* Operand extractors.  */
283
284
bool
285
aarch64_ext_none (const aarch64_operand *self ATTRIBUTE_UNUSED,
286
      aarch64_opnd_info *info ATTRIBUTE_UNUSED,
287
      const aarch64_insn code ATTRIBUTE_UNUSED,
288
      const aarch64_inst *inst ATTRIBUTE_UNUSED,
289
      aarch64_operand_error *errors ATTRIBUTE_UNUSED)
290
437
{
291
437
  return true;
292
437
}
293
294
bool
295
aarch64_ext_regno (const aarch64_operand *self, aarch64_opnd_info *info,
296
       const aarch64_insn code,
297
       const aarch64_inst *inst ATTRIBUTE_UNUSED,
298
       aarch64_operand_error *errors ATTRIBUTE_UNUSED)
299
7.11M
{
300
7.11M
  info->reg.regno = (extract_field (self->fields[0], code, 0)
301
7.11M
         + get_operand_specific_data (self));
302
7.11M
  return true;
303
7.11M
}
304
305
bool
306
aarch64_ext_regno_pair (const aarch64_operand *self ATTRIBUTE_UNUSED, aarch64_opnd_info *info,
307
       const aarch64_insn code ATTRIBUTE_UNUSED,
308
       const aarch64_inst *inst ATTRIBUTE_UNUSED,
309
       aarch64_operand_error *errors ATTRIBUTE_UNUSED)
310
5.05k
{
311
5.05k
  assert (info->idx == 1
312
5.05k
    || info->idx == 2
313
5.05k
    || info->idx == 3
314
5.05k
    || info->idx == 5);
315
316
5.05k
  unsigned prev_regno = inst->operands[info->idx - 1].reg.regno;
317
5.05k
  info->reg.regno = (prev_regno == 0x1f) ? 0x1f
318
5.05k
           : prev_regno + 1;
319
5.05k
  return true;
320
5.05k
}
321
322
/* e.g. IC <ic_op>{, <Xt>}.  */
323
bool
324
aarch64_ext_regrt_sysins (const aarch64_operand *self, aarch64_opnd_info *info,
325
        const aarch64_insn code,
326
        const aarch64_inst *inst ATTRIBUTE_UNUSED,
327
        aarch64_operand_error *errors ATTRIBUTE_UNUSED)
328
208
{
329
208
  info->reg.regno = extract_field (self->fields[0], code, 0);
330
208
  assert (info->idx == 1
331
208
    && (aarch64_get_operand_class (inst->operands[0].type)
332
208
        == AARCH64_OPND_CLASS_SYSTEM));
333
  /* This will make the constraint checking happy and more importantly will
334
     help the disassembler determine whether this operand is optional or
335
     not.  */
336
208
  info->present = aarch64_sys_ins_reg_has_xt (inst->operands[0].sysins_op);
337
338
208
  return true;
339
208
}
340
341
/* e.g. SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>].  */
342
bool
343
aarch64_ext_reglane (const aarch64_operand *self, aarch64_opnd_info *info,
344
         const aarch64_insn code,
345
         const aarch64_inst *inst ATTRIBUTE_UNUSED,
346
         aarch64_operand_error *errors ATTRIBUTE_UNUSED)
347
73.9k
{
348
  /* regno */
349
73.9k
  info->reglane.regno = extract_field (self->fields[0], code,
350
73.9k
               inst->opcode->mask);
351
352
  /* Index and/or type.  */
353
73.9k
  if (inst->opcode->iclass == asisdone
354
73.9k
    || inst->opcode->iclass == asimdins)
355
8.76k
    {
356
8.76k
      if (info->type == AARCH64_OPND_En
357
8.76k
    && inst->opcode->operands[0] == AARCH64_OPND_Ed)
358
2.20k
  {
359
2.20k
    unsigned shift;
360
    /* index2 for e.g. INS <Vd>.<Ts>[<index1>], <Vn>.<Ts>[<index2>].  */
361
2.20k
    assert (info->idx == 1);  /* Vn */
362
2.20k
    aarch64_insn value = extract_field (FLD_imm4_11, code, 0);
363
    /* Depend on AARCH64_OPND_Ed to determine the qualifier.  */
364
2.20k
    info->qualifier = get_expected_qualifier (inst, info->idx);
365
2.20k
    if (info->qualifier == AARCH64_OPND_QLF_ERR)
366
0
      return 0;
367
2.20k
    shift = get_logsz (aarch64_get_qualifier_esize (info->qualifier));
368
2.20k
    info->reglane.index = value >> shift;
369
2.20k
  }
370
6.55k
      else
371
6.55k
  {
372
    /* index and type for e.g. DUP <V><d>, <Vn>.<T>[<index>].
373
       imm5<3:0>  <V>
374
       0000 RESERVED
375
       xxx1 B
376
       xx10 H
377
       x100 S
378
       1000 D  */
379
6.55k
    int pos = -1;
380
6.55k
    aarch64_insn value = extract_field (FLD_imm5, code, 0);
381
13.8k
    while (++pos <= 3 && (value & 0x1) == 0)
382
7.27k
      value >>= 1;
383
6.55k
    if (pos > 3)
384
478
      return false;
385
6.07k
    info->qualifier = get_sreg_qualifier_from_value (pos);
386
6.07k
    if (info->qualifier == AARCH64_OPND_QLF_ERR)
387
0
      return 0;
388
6.07k
    info->reglane.index = (unsigned) (value >> 1);
389
6.07k
  }
390
8.76k
    }
391
65.1k
  else if (inst->opcode->iclass == dotproduct)
392
4.53k
    {
393
      /* Need information in other operand(s) to help decoding.  */
394
4.53k
      info->qualifier = get_expected_qualifier (inst, info->idx);
395
4.53k
      if (info->qualifier == AARCH64_OPND_QLF_ERR)
396
0
  return 0;
397
4.53k
      switch (info->qualifier)
398
4.53k
  {
399
2.02k
  case AARCH64_OPND_QLF_S_4B:
400
2.74k
  case AARCH64_OPND_QLF_S_2H:
401
    /* L:H */
402
2.74k
    info->reglane.index = extract_fields (code, 0, 2, FLD_H, FLD_L);
403
2.74k
    info->reglane.regno &= 0x1f;
404
2.74k
    break;
405
1.79k
  default:
406
1.79k
    return false;
407
4.53k
  }
408
4.53k
    }
409
60.6k
  else if (inst->opcode->iclass == cryptosm3)
410
561
    {
411
      /* index for e.g. SM3TT2A <Vd>.4S, <Vn>.4S, <Vm>S[<imm2>].  */
412
561
      info->reglane.index = extract_field (FLD_SM3_imm2, code, 0);
413
561
    }
414
60.0k
  else
415
60.0k
    {
416
      /* Index only for e.g. SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>]
417
         or SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>].  */
418
419
      /* Need information in other operand(s) to help decoding.  */
420
60.0k
      info->qualifier = get_expected_qualifier (inst, info->idx);
421
60.0k
      if (info->qualifier == AARCH64_OPND_QLF_ERR)
422
0
  return 0;
423
60.0k
      switch (info->qualifier)
424
60.0k
  {
425
30.7k
  case AARCH64_OPND_QLF_S_H:
426
30.7k
    if (info->type == AARCH64_OPND_Em16)
427
25.3k
      {
428
        /* h:l:m */
429
25.3k
        info->reglane.index = extract_fields (code, 0, 3, FLD_H, FLD_L,
430
25.3k
                FLD_M);
431
25.3k
        info->reglane.regno &= 0xf;
432
25.3k
      }
433
5.42k
    else
434
5.42k
      {
435
        /* h:l */
436
5.42k
        info->reglane.index = extract_fields (code, 0, 2, FLD_H, FLD_L);
437
5.42k
      }
438
30.7k
    break;
439
8.77k
  case AARCH64_OPND_QLF_S_S:
440
    /* h:l */
441
8.77k
    info->reglane.index = extract_fields (code, 0, 2, FLD_H, FLD_L);
442
8.77k
    break;
443
990
  case AARCH64_OPND_QLF_S_D:
444
    /* H */
445
990
    info->reglane.index = extract_field (FLD_H, code, 0);
446
990
    break;
447
19.5k
  default:
448
19.5k
    return false;
449
60.0k
  }
450
451
40.5k
      if (inst->opcode->op == OP_FCMLA_ELEM
452
40.5k
    && info->qualifier != AARCH64_OPND_QLF_S_H)
453
978
  {
454
    /* Complex operand takes two elements.  */
455
978
    if (info->reglane.index & 1)
456
424
      return false;
457
554
    info->reglane.index /= 2;
458
554
  }
459
40.5k
    }
460
461
51.6k
  return true;
462
73.9k
}
463
464
bool
465
aarch64_ext_reglist (const aarch64_operand *self, aarch64_opnd_info *info,
466
         const aarch64_insn code,
467
         const aarch64_inst *inst ATTRIBUTE_UNUSED,
468
         aarch64_operand_error *errors ATTRIBUTE_UNUSED)
469
13.0k
{
470
  /* R */
471
13.0k
  info->reglist.first_regno = extract_field (self->fields[0], code, 0);
472
  /* len */
473
13.0k
  info->reglist.num_regs = extract_field (FLD_len, code, 0) + 1;
474
13.0k
  info->reglist.stride = 1;
475
13.0k
  return true;
476
13.0k
}
477
478
/* Decode Rt and opcode fields of Vt in AdvSIMD load/store instructions.  */
479
bool
480
aarch64_ext_ldst_reglist (const aarch64_operand *self ATTRIBUTE_UNUSED,
481
        aarch64_opnd_info *info, const aarch64_insn code,
482
        const aarch64_inst *inst,
483
        aarch64_operand_error *errors ATTRIBUTE_UNUSED)
484
49.3k
{
485
49.3k
  aarch64_insn value;
486
  /* Number of elements in each structure to be loaded/stored.  */
487
49.3k
  unsigned expected_num = get_opcode_dependent_value (inst->opcode);
488
489
49.3k
  struct
490
49.3k
    {
491
49.3k
      unsigned is_reserved;
492
49.3k
      unsigned num_regs;
493
49.3k
      unsigned num_elements;
494
49.3k
    } data [] =
495
49.3k
  {   {0, 4, 4},
496
49.3k
      {1, 4, 4},
497
49.3k
      {0, 4, 1},
498
49.3k
      {0, 4, 2},
499
49.3k
      {0, 3, 3},
500
49.3k
      {1, 3, 3},
501
49.3k
      {0, 3, 1},
502
49.3k
      {0, 1, 1},
503
49.3k
      {0, 2, 2},
504
49.3k
      {1, 2, 2},
505
49.3k
      {0, 2, 1},
506
49.3k
  };
507
508
  /* Rt */
509
49.3k
  info->reglist.first_regno = extract_field (FLD_Rt, code, 0);
510
  /* opcode */
511
49.3k
  value = extract_field (FLD_opcode, code, 0);
512
  /* PR 21595: Check for a bogus value.  */
513
49.3k
  if (value >= ARRAY_SIZE (data))
514
15.9k
    return false;
515
33.4k
  if (expected_num != data[value].num_elements || data[value].is_reserved)
516
19.0k
    return false;
517
14.3k
  info->reglist.num_regs = data[value].num_regs;
518
14.3k
  info->reglist.stride = 1;
519
520
14.3k
  return true;
521
33.4k
}
522
523
/* Decode Rt and S fields of Vt in AdvSIMD load single structure to all
524
   lanes instructions.  */
525
bool
526
aarch64_ext_ldst_reglist_r (const aarch64_operand *self ATTRIBUTE_UNUSED,
527
          aarch64_opnd_info *info, const aarch64_insn code,
528
          const aarch64_inst *inst,
529
          aarch64_operand_error *errors ATTRIBUTE_UNUSED)
530
1.43k
{
531
1.43k
  aarch64_insn value;
532
533
  /* Rt */
534
1.43k
  info->reglist.first_regno = extract_field (FLD_Rt, code, 0);
535
  /* S */
536
1.43k
  value = extract_field (FLD_S, code, 0);
537
538
  /* Number of registers is equal to the number of elements in
539
     each structure to be loaded/stored.  */
540
1.43k
  info->reglist.num_regs = get_opcode_dependent_value (inst->opcode);
541
1.43k
  assert (info->reglist.num_regs >= 1 && info->reglist.num_regs <= 4);
542
543
  /* Except when it is LD1R.  */
544
1.43k
  if (info->reglist.num_regs == 1 && value == (aarch64_insn) 1)
545
0
    info->reglist.num_regs = 2;
546
547
1.43k
  info->reglist.stride = 1;
548
1.43k
  return true;
549
1.43k
}
550
551
/* Decode Q, opcode<2:1>, S, size and Rt fields of Vt in AdvSIMD
552
   load/store single element instructions.  */
553
bool
554
aarch64_ext_ldst_elemlist (const aarch64_operand *self ATTRIBUTE_UNUSED,
555
         aarch64_opnd_info *info, const aarch64_insn code,
556
         const aarch64_inst *inst ATTRIBUTE_UNUSED,
557
         aarch64_operand_error *errors ATTRIBUTE_UNUSED)
558
32.1k
{
559
32.1k
  aarch64_field field = {0, 0};
560
32.1k
  aarch64_insn QSsize;    /* fields Q:S:size.  */
561
32.1k
  aarch64_insn opcodeh2;  /* opcode<2:1> */
562
563
  /* Rt */
564
32.1k
  info->reglist.first_regno = extract_field (FLD_Rt, code, 0);
565
566
  /* Decode the index, opcode<2:1> and size.  */
567
32.1k
  gen_sub_field (FLD_asisdlso_opcode, 1, 2, &field);
568
32.1k
  opcodeh2 = extract_field_2 (&field, code, 0);
569
32.1k
  QSsize = extract_fields (code, 0, 3, FLD_Q, FLD_S, FLD_vldst_size);
570
32.1k
  switch (opcodeh2)
571
32.1k
    {
572
15.1k
    case 0x0:
573
15.1k
      info->qualifier = AARCH64_OPND_QLF_S_B;
574
      /* Index encoded in "Q:S:size".  */
575
15.1k
      info->reglist.index = QSsize;
576
15.1k
      break;
577
6.41k
    case 0x1:
578
6.41k
      if (QSsize & 0x1)
579
  /* UND.  */
580
2.48k
  return false;
581
3.92k
      info->qualifier = AARCH64_OPND_QLF_S_H;
582
      /* Index encoded in "Q:S:size<1>".  */
583
3.92k
      info->reglist.index = QSsize >> 1;
584
3.92k
      break;
585
4.73k
    case 0x2:
586
4.73k
      if ((QSsize >> 1) & 0x1)
587
  /* UND.  */
588
2.07k
  return false;
589
2.65k
      if ((QSsize & 0x1) == 0)
590
1.52k
  {
591
1.52k
    info->qualifier = AARCH64_OPND_QLF_S_S;
592
    /* Index encoded in "Q:S".  */
593
1.52k
    info->reglist.index = QSsize >> 2;
594
1.52k
  }
595
1.13k
      else
596
1.13k
  {
597
1.13k
    if (extract_field (FLD_S, code, 0))
598
      /* UND */
599
455
      return false;
600
679
    info->qualifier = AARCH64_OPND_QLF_S_D;
601
    /* Index encoded in "Q".  */
602
679
    info->reglist.index = QSsize >> 3;
603
679
  }
604
2.20k
      break;
605
5.92k
    default:
606
5.92k
      return false;
607
32.1k
    }
608
609
21.2k
  info->reglist.has_index = 1;
610
21.2k
  info->reglist.num_regs = 0;
611
21.2k
  info->reglist.stride = 1;
612
  /* Number of registers is equal to the number of elements in
613
     each structure to be loaded/stored.  */
614
21.2k
  info->reglist.num_regs = get_opcode_dependent_value (inst->opcode);
615
21.2k
  assert (info->reglist.num_regs >= 1 && info->reglist.num_regs <= 4);
616
617
21.2k
  return true;
618
21.2k
}
619
620
/* Decode fields immh:immb and/or Q for e.g.
621
   SSHR <Vd>.<T>, <Vn>.<T>, #<shift>
622
   or SSHR <V><d>, <V><n>, #<shift>.  */
623
624
bool
625
aarch64_ext_advsimd_imm_shift (const aarch64_operand *self ATTRIBUTE_UNUSED,
626
             aarch64_opnd_info *info, const aarch64_insn code,
627
             const aarch64_inst *inst,
628
             aarch64_operand_error *errors ATTRIBUTE_UNUSED)
629
26.7k
{
630
26.7k
  int pos;
631
26.7k
  aarch64_insn Q, imm, immh;
632
26.7k
  enum aarch64_insn_class iclass = inst->opcode->iclass;
633
634
26.7k
  immh = extract_field (FLD_immh, code, 0);
635
26.7k
  if (immh == 0)
636
2.80k
    return false;
637
23.9k
  imm = extract_fields (code, 0, 2, FLD_immh, FLD_immb);
638
23.9k
  pos = 4;
639
  /* Get highest set bit in immh.  */
640
38.6k
  while (--pos >= 0 && (immh & 0x8) == 0)
641
14.7k
    immh <<= 1;
642
643
23.9k
  assert ((iclass == asimdshf || iclass == asisdshf)
644
23.9k
    && (info->type == AARCH64_OPND_IMM_VLSR
645
23.9k
        || info->type == AARCH64_OPND_IMM_VLSL));
646
647
23.9k
  if (iclass == asimdshf)
648
17.1k
    {
649
17.1k
      Q = extract_field (FLD_Q, code, 0);
650
      /* immh Q <T>
651
   0000 x SEE AdvSIMD modified immediate
652
   0001 0 8B
653
   0001 1 16B
654
   001x 0 4H
655
   001x 1 8H
656
   01xx 0 2S
657
   01xx 1 4S
658
   1xxx 0 RESERVED
659
   1xxx 1 2D  */
660
17.1k
      info->qualifier =
661
17.1k
  get_vreg_qualifier_from_value ((pos << 1) | (int) Q);
662
17.1k
      if (info->qualifier == AARCH64_OPND_QLF_ERR)
663
0
  return false;
664
17.1k
    }
665
6.81k
  else
666
6.81k
    {
667
6.81k
      info->qualifier = get_sreg_qualifier_from_value (pos);
668
6.81k
      if (info->qualifier == AARCH64_OPND_QLF_ERR)
669
0
  return 0;
670
6.81k
    }
671
672
23.9k
  if (info->type == AARCH64_OPND_IMM_VLSR)
673
    /* immh <shift>
674
       0000 SEE AdvSIMD modified immediate
675
       0001 (16-UInt(immh:immb))
676
       001x (32-UInt(immh:immb))
677
       01xx (64-UInt(immh:immb))
678
       1xxx (128-UInt(immh:immb))  */
679
16.2k
    info->imm.value = (16 << pos) - imm;
680
7.68k
  else
681
    /* immh:immb
682
       immh <shift>
683
       0000 SEE AdvSIMD modified immediate
684
       0001 (UInt(immh:immb)-8)
685
       001x (UInt(immh:immb)-16)
686
       01xx (UInt(immh:immb)-32)
687
       1xxx (UInt(immh:immb)-64)  */
688
7.68k
    info->imm.value = imm - (8 << pos);
689
690
23.9k
  return true;
691
23.9k
}
692
693
/* Decode shift immediate for e.g. sshr (imm).  */
694
bool
695
aarch64_ext_shll_imm (const aarch64_operand *self ATTRIBUTE_UNUSED,
696
          aarch64_opnd_info *info, const aarch64_insn code,
697
          const aarch64_inst *inst ATTRIBUTE_UNUSED,
698
          aarch64_operand_error *errors ATTRIBUTE_UNUSED)
699
22
{
700
22
  int64_t imm;
701
22
  aarch64_insn val;
702
22
  val = extract_field (FLD_size, code, 0);
703
22
  switch (val)
704
22
    {
705
4
    case 0: imm = 8; break;
706
14
    case 1: imm = 16; break;
707
4
    case 2: imm = 32; break;
708
0
    default: return false;
709
22
    }
710
22
  info->imm.value = imm;
711
22
  return true;
712
22
}
713
714
/* Decode imm for e.g. BFM <Wd>, <Wn>, #<immr>, #<imms>.
715
   value in the field(s) will be extracted as unsigned immediate value.  */
716
bool
717
aarch64_ext_imm (const aarch64_operand *self, aarch64_opnd_info *info,
718
     const aarch64_insn code,
719
     const aarch64_inst *inst,
720
     aarch64_operand_error *errors ATTRIBUTE_UNUSED)
721
3.01M
{
722
3.01M
  uint64_t imm;
723
724
3.01M
  imm = extract_all_fields (self, code);
725
726
3.01M
  if (operand_need_sign_extension (self))
727
1.09M
    imm = sign_extend (imm, get_operand_fields_width (self) - 1);
728
729
3.01M
  if (operand_need_shift_by_two (self))
730
719k
    imm <<= 2;
731
2.29M
  else if (operand_need_shift_by_three (self))
732
0
    imm <<= 3;
733
2.29M
  else if (operand_need_shift_by_four (self))
734
2.28k
    imm <<= 4;
735
736
3.01M
  if (info->type == AARCH64_OPND_ADDR_ADRP)
737
150k
    imm <<= 12;
738
739
3.01M
  if (inst->operands[0].type == AARCH64_OPND_PSTATEFIELD
740
3.01M
      && inst->operands[0].sysreg.flags & F_IMM_IN_CRM)
741
0
    imm &= PSTATE_DECODE_CRM_IMM (inst->operands[0].sysreg.flags);
742
743
3.01M
  info->imm.value = imm;
744
3.01M
  return true;
745
3.01M
}
746
747
/* Decode imm and its shifter for e.g. MOVZ <Wd>, #<imm16>{, LSL #<shift>}.  */
748
bool
749
aarch64_ext_imm_half (const aarch64_operand *self, aarch64_opnd_info *info,
750
          const aarch64_insn code,
751
          const aarch64_inst *inst ATTRIBUTE_UNUSED,
752
          aarch64_operand_error *errors)
753
102k
{
754
102k
  aarch64_ext_imm (self, info, code, inst, errors);
755
102k
  info->shifter.kind = AARCH64_MOD_LSL;
756
102k
  info->shifter.amount = extract_field (FLD_hw, code, 0) << 4;
757
102k
  return true;
758
102k
}
759
760
/* Decode cmode and "a:b:c:d:e:f:g:h" for e.g.
761
     MOVI <Vd>.<T>, #<imm8> {, LSL #<amount>}.  */
762
bool
763
aarch64_ext_advsimd_imm_modified (const aarch64_operand *self ATTRIBUTE_UNUSED,
764
          aarch64_opnd_info *info,
765
          const aarch64_insn code,
766
          const aarch64_inst *inst ATTRIBUTE_UNUSED,
767
          aarch64_operand_error *errors ATTRIBUTE_UNUSED)
768
2.75k
{
769
2.75k
  uint64_t imm;
770
2.75k
  enum aarch64_opnd_qualifier opnd0_qualifier = inst->operands[0].qualifier;
771
2.75k
  aarch64_field field = {0, 0};
772
773
2.75k
  assert (info->idx == 1);
774
775
2.75k
  if (info->type == AARCH64_OPND_SIMD_FPIMM)
776
599
    info->imm.is_fp = 1;
777
778
  /* a:b:c:d:e:f:g:h */
779
2.75k
  imm = extract_fields (code, 0, 2, FLD_abc, FLD_defgh);
780
2.75k
  if (!info->imm.is_fp && aarch64_get_qualifier_esize (opnd0_qualifier) == 8)
781
108
    {
782
      /* Either MOVI <Dd>, #<imm>
783
   or     MOVI <Vd>.2D, #<imm>.
784
   <imm> is a 64-bit immediate
785
   'aaaaaaaabbbbbbbbccccccccddddddddeeeeeeeeffffffffgggggggghhhhhhhh',
786
   encoded in "a:b:c:d:e:f:g:h".  */
787
108
      int i;
788
108
      unsigned abcdefgh = imm;
789
972
      for (imm = 0ull, i = 0; i < 8; i++)
790
864
  if (((abcdefgh >> i) & 0x1) != 0)
791
389
    imm |= 0xffull << (8 * i);
792
108
    }
793
2.75k
  info->imm.value = imm;
794
795
  /* cmode */
796
2.75k
  info->qualifier = get_expected_qualifier (inst, info->idx);
797
2.75k
  if (info->qualifier == AARCH64_OPND_QLF_ERR)
798
0
    return 0;
799
2.75k
  switch (info->qualifier)
800
2.75k
    {
801
707
    case AARCH64_OPND_QLF_NIL:
802
      /* no shift */
803
707
      info->shifter.kind = AARCH64_MOD_NONE;
804
707
      return 1;
805
1.77k
    case AARCH64_OPND_QLF_LSL:
806
      /* shift zeros */
807
1.77k
      info->shifter.kind = AARCH64_MOD_LSL;
808
1.77k
      switch (aarch64_get_qualifier_esize (opnd0_qualifier))
809
1.77k
  {
810
1.12k
  case 4: gen_sub_field (FLD_cmode, 1, 2, &field); break; /* per word */
811
438
  case 2: gen_sub_field (FLD_cmode, 1, 1, &field); break; /* per half */
812
212
  case 1: gen_sub_field (FLD_cmode, 1, 0, &field); break; /* per byte */
813
0
  default: return false;
814
1.77k
  }
815
      /* 00: 0; 01: 8; 10:16; 11:24.  */
816
1.77k
      info->shifter.amount = extract_field_2 (&field, code, 0) << 3;
817
1.77k
      break;
818
273
    case AARCH64_OPND_QLF_MSL:
819
      /* shift ones */
820
273
      info->shifter.kind = AARCH64_MOD_MSL;
821
273
      gen_sub_field (FLD_cmode, 0, 1, &field);    /* per word */
822
273
      info->shifter.amount = extract_field_2 (&field, code, 0) ? 16 : 8;
823
273
      break;
824
0
    default:
825
0
      return false;
826
2.75k
    }
827
828
2.04k
  return true;
829
2.75k
}
830
831
/* Decode an 8-bit floating-point immediate.  */
832
bool
833
aarch64_ext_fpimm (const aarch64_operand *self, aarch64_opnd_info *info,
834
       const aarch64_insn code,
835
       const aarch64_inst *inst ATTRIBUTE_UNUSED,
836
       aarch64_operand_error *errors ATTRIBUTE_UNUSED)
837
1.31k
{
838
1.31k
  info->imm.value = extract_all_fields (self, code);
839
1.31k
  info->imm.is_fp = 1;
840
1.31k
  return true;
841
1.31k
}
842
843
/* Decode a 1-bit rotate immediate (#90 or #270).  */
844
bool
845
aarch64_ext_imm_rotate1 (const aarch64_operand *self, aarch64_opnd_info *info,
846
       const aarch64_insn code,
847
       const aarch64_inst *inst ATTRIBUTE_UNUSED,
848
       aarch64_operand_error *errors ATTRIBUTE_UNUSED)
849
796
{
850
796
  uint64_t rot = extract_field (self->fields[0], code, 0);
851
796
  assert (rot < 2U);
852
796
  info->imm.value = rot * 180 + 90;
853
796
  return true;
854
796
}
855
856
/* Decode a 2-bit rotate immediate (#0, #90, #180 or #270).  */
857
bool
858
aarch64_ext_imm_rotate2 (const aarch64_operand *self, aarch64_opnd_info *info,
859
       const aarch64_insn code,
860
       const aarch64_inst *inst ATTRIBUTE_UNUSED,
861
       aarch64_operand_error *errors ATTRIBUTE_UNUSED)
862
17.2k
{
863
17.2k
  uint64_t rot = extract_field (self->fields[0], code, 0);
864
17.2k
  assert (rot < 4U);
865
17.2k
  info->imm.value = rot * 90;
866
17.2k
  return true;
867
17.2k
}
868
869
/* Decode scale for e.g. SCVTF <Dd>, <Wn>, #<fbits>.  */
870
bool
871
aarch64_ext_fbits (const aarch64_operand *self ATTRIBUTE_UNUSED,
872
       aarch64_opnd_info *info, const aarch64_insn code,
873
       const aarch64_inst *inst ATTRIBUTE_UNUSED,
874
       aarch64_operand_error *errors ATTRIBUTE_UNUSED)
875
3.08k
{
876
3.08k
  info->imm.value = 64- extract_field (FLD_scale, code, 0);
877
3.08k
  return true;
878
3.08k
}
879
880
/* Decode arithmetic immediate for e.g.
881
     SUBS <Wd>, <Wn|WSP>, #<imm> {, <shift>}.  */
882
bool
883
aarch64_ext_aimm (const aarch64_operand *self ATTRIBUTE_UNUSED,
884
      aarch64_opnd_info *info, const aarch64_insn code,
885
      const aarch64_inst *inst ATTRIBUTE_UNUSED,
886
      aarch64_operand_error *errors ATTRIBUTE_UNUSED)
887
451k
{
888
451k
  aarch64_insn value;
889
890
451k
  info->shifter.kind = AARCH64_MOD_LSL;
891
  /* shift */
892
451k
  value = extract_field (FLD_shift, code, 0);
893
451k
  if (value >= 2)
894
100k
    return false;
895
350k
  info->shifter.amount = value ? 12 : 0;
896
  /* imm12 (unsigned) */
897
350k
  info->imm.value = extract_field (FLD_imm12, code, 0);
898
899
350k
  return true;
900
451k
}
901
902
/* Return true if VALUE is a valid logical immediate encoding, storing the
903
   decoded value in *RESULT if so.  ESIZE is the number of bytes in the
904
   decoded immediate.  */
905
static bool
906
decode_limm (uint32_t esize, aarch64_insn value, int64_t *result)
907
295k
{
908
295k
  uint64_t imm, mask;
909
295k
  uint32_t N, R, S;
910
295k
  unsigned simd_size;
911
912
  /* value is N:immr:imms.  */
913
295k
  S = value & 0x3f;
914
295k
  R = (value >> 6) & 0x3f;
915
295k
  N = (value >> 12) & 0x1;
916
917
  /* The immediate value is S+1 bits to 1, left rotated by SIMDsize - R
918
     (in other words, right rotated by R), then replicated.  */
919
295k
  if (N != 0)
920
101k
    {
921
101k
      simd_size = 64;
922
101k
      mask = 0xffffffffffffffffull;
923
101k
    }
924
193k
  else
925
193k
    {
926
193k
      switch (S)
927
193k
  {
928
148k
  case 0x00 ... 0x1f: /* 0xxxxx */ simd_size = 32;           break;
929
20.7k
  case 0x20 ... 0x2f: /* 10xxxx */ simd_size = 16; S &= 0xf; break;
930
11.3k
  case 0x30 ... 0x37: /* 110xxx */ simd_size =  8; S &= 0x7; break;
931
6.54k
  case 0x38 ... 0x3b: /* 1110xx */ simd_size =  4; S &= 0x3; break;
932
3.31k
  case 0x3c ... 0x3d: /* 11110x */ simd_size =  2; S &= 0x1; break;
933
3.34k
  default: return false;
934
193k
  }
935
190k
      mask = (1ull << simd_size) - 1;
936
      /* Top bits are IGNORED.  */
937
190k
      R &= simd_size - 1;
938
190k
    }
939
940
292k
  if (simd_size > esize * 8)
941
61.2k
    return false;
942
943
  /* NOTE: if S = simd_size - 1 we get 0xf..f which is rejected.  */
944
231k
  if (S == simd_size - 1)
945
5.35k
    return false;
946
  /* S+1 consecutive bits to 1.  */
947
  /* NOTE: S can't be 63 due to detection above.  */
948
225k
  imm = (1ull << (S + 1)) - 1;
949
  /* Rotate to the left by simd_size - R.  */
950
225k
  if (R != 0)
951
174k
    imm = ((imm << (simd_size - R)) & mask) | (imm >> R);
952
  /* Replicate the value according to SIMD size.  */
953
225k
  switch (simd_size)
954
225k
    {
955
2.26k
    case  2: imm = (imm <<  2) | imm;
956
      /* Fall through.  */
957
7.42k
    case  4: imm = (imm <<  4) | imm;
958
      /* Fall through.  */
959
17.8k
    case  8: imm = (imm <<  8) | imm;
960
      /* Fall through.  */
961
37.9k
    case 16: imm = (imm << 16) | imm;
962
      /* Fall through.  */
963
185k
    case 32: imm = (imm << 32) | imm;
964
      /* Fall through.  */
965
225k
    case 64: break;
966
0
    default: return 0;
967
225k
    }
968
969
225k
  *result = imm & ~((uint64_t) -1 << (esize * 4) << (esize * 4));
970
971
225k
  return true;
972
225k
}
973
974
/* Decode a logical immediate for e.g. ORR <Wd|WSP>, <Wn>, #<imm>.  */
975
bool
976
aarch64_ext_limm (const aarch64_operand *self,
977
      aarch64_opnd_info *info, const aarch64_insn code,
978
      const aarch64_inst *inst,
979
      aarch64_operand_error *errors ATTRIBUTE_UNUSED)
980
295k
{
981
295k
  uint32_t esize;
982
295k
  aarch64_insn value;
983
984
295k
  value = extract_fields (code, 0, 3, self->fields[0], self->fields[1],
985
295k
        self->fields[2]);
986
295k
  esize = aarch64_get_qualifier_esize (inst->operands[0].qualifier);
987
295k
  return decode_limm (esize, value, &info->imm.value);
988
295k
}
989
990
/* Decode a logical immediate for the BIC alias of AND (etc.).  */
991
bool
992
aarch64_ext_inv_limm (const aarch64_operand *self,
993
          aarch64_opnd_info *info, const aarch64_insn code,
994
          const aarch64_inst *inst,
995
          aarch64_operand_error *errors)
996
0
{
997
0
  if (!aarch64_ext_limm (self, info, code, inst, errors))
998
0
    return false;
999
0
  info->imm.value = ~info->imm.value;
1000
0
  return true;
1001
0
}
1002
1003
/* Decode Ft for e.g. STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]
1004
   or LDP <Qt1>, <Qt2>, [<Xn|SP>], #<imm>.  */
1005
bool
1006
aarch64_ext_ft (const aarch64_operand *self ATTRIBUTE_UNUSED,
1007
    aarch64_opnd_info *info,
1008
    const aarch64_insn code, const aarch64_inst *inst,
1009
    aarch64_operand_error *errors ATTRIBUTE_UNUSED)
1010
539k
{
1011
539k
  aarch64_insn value;
1012
1013
  /* Rt */
1014
539k
  info->reg.regno = extract_field (FLD_Rt, code, 0);
1015
1016
  /* size */
1017
539k
  value = extract_field (FLD_ldst_size, code, 0);
1018
539k
  if (inst->opcode->iclass == ldstpair_indexed
1019
539k
      || inst->opcode->iclass == ldstnapair_offs
1020
539k
      || inst->opcode->iclass == ldstpair_off
1021
539k
      || inst->opcode->iclass == loadlit)
1022
341k
    {
1023
341k
      enum aarch64_opnd_qualifier qualifier;
1024
341k
      switch (value)
1025
341k
  {
1026
91.0k
  case 0: qualifier = AARCH64_OPND_QLF_S_S; break;
1027
108k
  case 1: qualifier = AARCH64_OPND_QLF_S_D; break;
1028
69.5k
  case 2: qualifier = AARCH64_OPND_QLF_S_Q; break;
1029
71.4k
  default: return false;
1030
341k
  }
1031
269k
      info->qualifier = qualifier;
1032
269k
    }
1033
198k
  else
1034
198k
    {
1035
      /* opc1:size */
1036
198k
      value = extract_fields (code, 0, 2, FLD_opc1, FLD_ldst_size);
1037
198k
      if (value > 0x4)
1038
76.4k
  return false;
1039
121k
      info->qualifier = get_sreg_qualifier_from_value (value);
1040
121k
      if (info->qualifier == AARCH64_OPND_QLF_ERR)
1041
0
  return false;
1042
121k
    }
1043
1044
391k
  return true;
1045
539k
}
1046
1047
/* Decode the address operand for e.g. STXRB <Ws>, <Wt>, [<Xn|SP>{,#0}].  */
1048
bool
1049
aarch64_ext_addr_simple (const aarch64_operand *self ATTRIBUTE_UNUSED,
1050
       aarch64_opnd_info *info,
1051
       aarch64_insn code,
1052
       const aarch64_inst *inst ATTRIBUTE_UNUSED,
1053
       aarch64_operand_error *errors ATTRIBUTE_UNUSED)
1054
168k
{
1055
  /* Rn */
1056
168k
  info->addr.base_regno = extract_field (FLD_Rn, code, 0);
1057
168k
  return true;
1058
168k
}
1059
1060
/* Decode the address operand for rcpc3 instructions with optional load/store
1061
   datasize offset, e.g. STILPP <Xs>, <Xt>, [<Xn|SP>{,#-16}]! and
1062
   LIDAP <Xs>, <Xt>, [<Xn|SP>]{,#-16}.  */
1063
bool
1064
aarch64_ext_rcpc3_addr_opt_offset (const aarch64_operand *self ATTRIBUTE_UNUSED,
1065
           aarch64_opnd_info *info,
1066
           aarch64_insn code,
1067
           const aarch64_inst *inst ATTRIBUTE_UNUSED,
1068
           aarch64_operand_error *err ATTRIBUTE_UNUSED)
1069
5.20k
{
1070
5.20k
  info->addr.base_regno = extract_field (FLD_Rn, code, 0);
1071
5.20k
  if (!extract_field (FLD_opc2, code, 0))
1072
341
    {
1073
341
      info->addr.writeback = 1;
1074
1075
341
      enum aarch64_opnd type;
1076
341
      for (int i = 0; i < AARCH64_MAX_OPND_NUM; i++)
1077
341
  {
1078
341
    aarch64_opnd_info opnd = info[i];
1079
341
    type = opnd.type;
1080
341
    if (aarch64_operands[type].op_class == AARCH64_OPND_CLASS_ADDRESS)
1081
341
      break;
1082
341
  }
1083
1084
341
      assert (aarch64_operands[type].op_class == AARCH64_OPND_CLASS_ADDRESS);
1085
341
      int offset = calc_ldst_datasize (inst->operands);
1086
1087
341
      switch (type)
1088
341
  {
1089
132
  case AARCH64_OPND_RCPC3_ADDR_OPT_PREIND_WB:
1090
133
  case AARCH64_OPND_RCPC3_ADDR_PREIND_WB:
1091
133
    info->addr.offset.imm = -offset;
1092
133
    info->addr.preind = 1;
1093
133
    break;
1094
208
  case AARCH64_OPND_RCPC3_ADDR_OPT_POSTIND:
1095
208
  case AARCH64_OPND_RCPC3_ADDR_POSTIND:
1096
208
    info->addr.offset.imm = offset;
1097
208
    info->addr.postind = 1;
1098
208
    break;
1099
0
  default:
1100
0
    return false;
1101
341
  }
1102
341
    }
1103
5.20k
  return true;
1104
5.20k
}
1105
1106
bool
1107
aarch64_ext_rcpc3_addr_offset (const aarch64_operand *self ATTRIBUTE_UNUSED,
1108
             aarch64_opnd_info *info,
1109
             aarch64_insn code,
1110
             const aarch64_inst *inst ATTRIBUTE_UNUSED,
1111
             aarch64_operand_error *errors ATTRIBUTE_UNUSED)
1112
6.73k
{
1113
6.73k
  info->qualifier = get_expected_qualifier (inst, info->idx);
1114
6.73k
  if (info->qualifier == AARCH64_OPND_QLF_ERR)
1115
0
    return 0;
1116
1117
  /* Rn */
1118
6.73k
  info->addr.base_regno = extract_field (self->fields[0], code, 0);
1119
1120
  /* simm9 */
1121
6.73k
  aarch64_insn imm = extract_fields (code, 0, 1, self->fields[1]);
1122
6.73k
  info->addr.offset.imm = sign_extend (imm, 8);
1123
6.73k
  return true;
1124
6.73k
}
1125
1126
/* Decode the address operand for e.g.
1127
     stlur <Xt>, [<Xn|SP>{, <amount>}].  */
1128
bool
1129
aarch64_ext_addr_offset (const aarch64_operand *self ATTRIBUTE_UNUSED,
1130
       aarch64_opnd_info *info,
1131
       aarch64_insn code, const aarch64_inst *inst,
1132
       aarch64_operand_error *errors ATTRIBUTE_UNUSED)
1133
13.0k
{
1134
13.0k
  info->qualifier = get_expected_qualifier (inst, info->idx);
1135
13.0k
  if (info->qualifier == AARCH64_OPND_QLF_ERR)
1136
0
    return 0;
1137
1138
  /* Rn */
1139
13.0k
  info->addr.base_regno = extract_field (self->fields[0], code, 0);
1140
1141
  /* simm9 */
1142
13.0k
  aarch64_insn imm = extract_fields (code, 0, 1, self->fields[1]);
1143
13.0k
  info->addr.offset.imm = sign_extend (imm, 8);
1144
13.0k
  if (extract_field (self->fields[2], code, 0) == 1) {
1145
0
    info->addr.writeback = 1;
1146
0
    info->addr.preind = 1;
1147
0
  }
1148
13.0k
  return true;
1149
13.0k
}
1150
1151
/* Decode the address operand for e.g.
1152
     STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}].  */
1153
bool
1154
aarch64_ext_addr_regoff (const aarch64_operand *self ATTRIBUTE_UNUSED,
1155
       aarch64_opnd_info *info,
1156
       aarch64_insn code, const aarch64_inst *inst,
1157
       aarch64_operand_error *errors ATTRIBUTE_UNUSED)
1158
36.6k
{
1159
36.6k
  aarch64_insn S, value;
1160
1161
  /* Rn */
1162
36.6k
  info->addr.base_regno = extract_field (FLD_Rn, code, 0);
1163
  /* Rm */
1164
36.6k
  info->addr.offset.regno = extract_field (FLD_Rm, code, 0);
1165
  /* option */
1166
36.6k
  value = extract_field (FLD_option, code, 0);
1167
36.6k
  info->shifter.kind =
1168
36.6k
    aarch64_get_operand_modifier_from_value (value, true /* extend_p */);
1169
  /* Fix-up the shifter kind; although the table-driven approach is
1170
     efficient, it is slightly inflexible, thus needing this fix-up.  */
1171
36.6k
  if (info->shifter.kind == AARCH64_MOD_UXTX)
1172
8.81k
    info->shifter.kind = AARCH64_MOD_LSL;
1173
  /* S */
1174
36.6k
  S = extract_field (FLD_S, code, 0);
1175
36.6k
  if (S == 0)
1176
10.3k
    {
1177
10.3k
      info->shifter.amount = 0;
1178
10.3k
      info->shifter.amount_present = 0;
1179
10.3k
    }
1180
26.3k
  else
1181
26.3k
    {
1182
26.3k
      int size;
1183
      /* Need information in other operand(s) to help achieve the decoding
1184
   from 'S' field.  */
1185
26.3k
      info->qualifier = get_expected_qualifier (inst, info->idx);
1186
26.3k
      if (info->qualifier == AARCH64_OPND_QLF_ERR)
1187
0
  return 0;
1188
      /* Get the size of the data element that is accessed, which may be
1189
   different from that of the source register size, e.g. in strb/ldrb.  */
1190
26.3k
      size = aarch64_get_qualifier_esize (info->qualifier);
1191
26.3k
      info->shifter.amount = get_logsz (size);
1192
26.3k
      info->shifter.amount_present = 1;
1193
26.3k
    }
1194
1195
36.6k
  return true;
1196
36.6k
}
1197
1198
/* Decode the address operand for e.g. LDRSW <Xt>, [<Xn|SP>], #<simm>.  */
1199
bool
1200
aarch64_ext_addr_simm (const aarch64_operand *self, aarch64_opnd_info *info,
1201
           aarch64_insn code, const aarch64_inst *inst,
1202
           aarch64_operand_error *errors ATTRIBUTE_UNUSED)
1203
480k
{
1204
480k
  aarch64_insn imm;
1205
480k
  info->qualifier = get_expected_qualifier (inst, info->idx);
1206
480k
  if (info->qualifier == AARCH64_OPND_QLF_ERR)
1207
0
    return 0;
1208
1209
  /* Rn */
1210
480k
  info->addr.base_regno = extract_field (FLD_Rn, code, 0);
1211
  /* simm (imm9 or imm7)  */
1212
480k
  imm = extract_field (self->fields[0], code, 0);
1213
480k
  info->addr.offset.imm = sign_extend (imm, fields[self->fields[0]].width - 1);
1214
480k
  if (self->fields[0] == FLD_imm7
1215
480k
      || info->qualifier == AARCH64_OPND_QLF_imm_tag)
1216
    /* scaled immediate in ld/st pair instructions.  */
1217
386k
    info->addr.offset.imm *= aarch64_get_qualifier_esize (info->qualifier);
1218
  /* qualifier */
1219
480k
  if (inst->opcode->iclass == ldst_unscaled
1220
480k
      || inst->opcode->iclass == ldstnapair_offs
1221
480k
      || inst->opcode->iclass == ldstpair_off
1222
480k
      || inst->opcode->iclass == ldst_unpriv)
1223
294k
    info->addr.writeback = 0;
1224
186k
  else
1225
186k
    {
1226
      /* pre/post- index */
1227
186k
      info->addr.writeback = 1;
1228
186k
      if (extract_field (self->fields[1], code, 0) == 1)
1229
91.0k
  info->addr.preind = 1;
1230
94.9k
      else
1231
94.9k
  info->addr.postind = 1;
1232
186k
    }
1233
1234
480k
  return true;
1235
480k
}
1236
1237
/* Decode the address operand for e.g. LDRSW <Xt>, [<Xn|SP>{, #<simm>}].  */
1238
bool
1239
aarch64_ext_addr_uimm12 (const aarch64_operand *self, aarch64_opnd_info *info,
1240
       aarch64_insn code,
1241
       const aarch64_inst *inst ATTRIBUTE_UNUSED,
1242
       aarch64_operand_error *errors ATTRIBUTE_UNUSED)
1243
214k
{
1244
214k
  int shift;
1245
214k
  info->qualifier = get_expected_qualifier (inst, info->idx);
1246
214k
  if (info->qualifier == AARCH64_OPND_QLF_ERR)
1247
0
    return 0;
1248
214k
  shift = get_logsz (aarch64_get_qualifier_esize (info->qualifier));
1249
  /* Rn */
1250
214k
  info->addr.base_regno = extract_field (self->fields[0], code, 0);
1251
  /* uimm12 */
1252
214k
  info->addr.offset.imm = extract_field (self->fields[1], code, 0) << shift;
1253
214k
  return true;
1254
214k
}
1255
1256
/* Decode the address operand for e.g. LDRAA <Xt>, [<Xn|SP>{, #<simm>}].  */
1257
bool
1258
aarch64_ext_addr_simm10 (const aarch64_operand *self, aarch64_opnd_info *info,
1259
       aarch64_insn code,
1260
       const aarch64_inst *inst ATTRIBUTE_UNUSED,
1261
       aarch64_operand_error *errors ATTRIBUTE_UNUSED)
1262
8.69k
{
1263
8.69k
  aarch64_insn imm;
1264
1265
8.69k
  info->qualifier = get_expected_qualifier (inst, info->idx);
1266
8.69k
  if (info->qualifier == AARCH64_OPND_QLF_ERR)
1267
0
    return 0;
1268
  /* Rn */
1269
8.69k
  info->addr.base_regno = extract_field (self->fields[0], code, 0);
1270
  /* simm10 */
1271
8.69k
  imm = extract_fields (code, 0, 2, self->fields[1], self->fields[2]);
1272
8.69k
  info->addr.offset.imm = sign_extend (imm, 9) << 3;
1273
8.69k
  if (extract_field (self->fields[3], code, 0) == 1) {
1274
5.02k
    info->addr.writeback = 1;
1275
5.02k
    info->addr.preind = 1;
1276
5.02k
  }
1277
8.69k
  return true;
1278
8.69k
}
1279
1280
/* Decode the address operand for e.g.
1281
     LD1 {<Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>}, [<Xn|SP>], <Xm|#<amount>>.  */
1282
bool
1283
aarch64_ext_simd_addr_post (const aarch64_operand *self ATTRIBUTE_UNUSED,
1284
          aarch64_opnd_info *info,
1285
          aarch64_insn code, const aarch64_inst *inst,
1286
          aarch64_operand_error *errors ATTRIBUTE_UNUSED)
1287
24.8k
{
1288
  /* The opcode dependent area stores the number of elements in
1289
     each structure to be loaded/stored.  */
1290
24.8k
  int is_ld1r = get_opcode_dependent_value (inst->opcode) == 1;
1291
1292
  /* Rn */
1293
24.8k
  info->addr.base_regno = extract_field (FLD_Rn, code, 0);
1294
  /* Rm | #<amount>  */
1295
24.8k
  info->addr.offset.regno = extract_field (FLD_Rm, code, 0);
1296
24.8k
  if (info->addr.offset.regno == 31)
1297
1.63k
    {
1298
1.63k
      if (inst->opcode->operands[0] == AARCH64_OPND_LVt_AL)
1299
  /* Special handling of loading single structure to all lane.  */
1300
163
  info->addr.offset.imm = (is_ld1r ? 1
1301
163
         : inst->operands[0].reglist.num_regs)
1302
163
    * aarch64_get_qualifier_esize (inst->operands[0].qualifier);
1303
1.46k
      else
1304
1.46k
  info->addr.offset.imm = inst->operands[0].reglist.num_regs
1305
1.46k
    * aarch64_get_qualifier_esize (inst->operands[0].qualifier)
1306
1.46k
    * aarch64_get_qualifier_nelem (inst->operands[0].qualifier);
1307
1.63k
    }
1308
23.1k
  else
1309
23.1k
    info->addr.offset.is_reg = 1;
1310
24.8k
  info->addr.writeback = 1;
1311
1312
24.8k
  return true;
1313
24.8k
}
1314
1315
/* Decode the condition operand for e.g. CSEL <Xd>, <Xn>, <Xm>, <cond>.  */
1316
bool
1317
aarch64_ext_cond (const aarch64_operand *self ATTRIBUTE_UNUSED,
1318
      aarch64_opnd_info *info,
1319
      aarch64_insn code, const aarch64_inst *inst ATTRIBUTE_UNUSED,
1320
      aarch64_operand_error *errors ATTRIBUTE_UNUSED)
1321
21.8k
{
1322
21.8k
  aarch64_insn value;
1323
  /* cond */
1324
21.8k
  value = extract_field (FLD_cond, code, 0);
1325
21.8k
  info->cond = get_cond_from_value (value);
1326
21.8k
  return true;
1327
21.8k
}
1328
1329
/* Decode the system register operand for e.g. MRS <Xt>, <systemreg>.  */
1330
bool
1331
aarch64_ext_sysreg (const aarch64_operand *self ATTRIBUTE_UNUSED,
1332
        aarch64_opnd_info *info,
1333
        aarch64_insn code,
1334
        const aarch64_inst *inst ATTRIBUTE_UNUSED,
1335
        aarch64_operand_error *errors ATTRIBUTE_UNUSED)
1336
7.19k
{
1337
  /* op0:op1:CRn:CRm:op2 */
1338
7.19k
  info->sysreg.value = extract_fields (code, 0, 5, FLD_op0, FLD_op1, FLD_CRn,
1339
7.19k
               FLD_CRm, FLD_op2);
1340
7.19k
  info->sysreg.flags = 0;
1341
1342
  /* If a system instruction, check which restrictions should be on the register
1343
     value during decoding, these will be enforced then.  */
1344
7.19k
  if (inst->opcode->iclass == ic_system)
1345
7.19k
    {
1346
      /* Check to see if it's read-only, else check if it's write only.
1347
   if it's both or unspecified don't care.  */
1348
7.19k
      if ((inst->opcode->flags & (F_SYS_READ | F_SYS_WRITE)) == F_SYS_READ)
1349
2.53k
  info->sysreg.flags = F_REG_READ;
1350
4.65k
      else if ((inst->opcode->flags & (F_SYS_READ | F_SYS_WRITE))
1351
4.65k
         == F_SYS_WRITE)
1352
4.65k
  info->sysreg.flags = F_REG_WRITE;
1353
7.19k
    }
1354
1355
7.19k
  return true;
1356
7.19k
}
1357
1358
/* Decode the PSTATE field operand for e.g. MSR <pstatefield>, #<imm>.  */
1359
bool
1360
aarch64_ext_pstatefield (const aarch64_operand *self ATTRIBUTE_UNUSED,
1361
       aarch64_opnd_info *info, aarch64_insn code,
1362
       const aarch64_inst *inst ATTRIBUTE_UNUSED,
1363
       aarch64_operand_error *errors ATTRIBUTE_UNUSED)
1364
229
{
1365
229
  int i;
1366
229
  aarch64_insn fld_crm = extract_field (FLD_CRm, code, 0);
1367
  /* op1:op2 */
1368
229
  info->pstatefield = extract_fields (code, 0, 2, FLD_op1, FLD_op2);
1369
1.12k
  for (i = 0; aarch64_pstatefields[i].name != NULL; ++i)
1370
1.06k
    if (aarch64_pstatefields[i].value == (aarch64_insn)info->pstatefield)
1371
338
      {
1372
        /* PSTATEFIELD name can be encoded partially in CRm[3:1].  */
1373
338
        uint32_t flags = aarch64_pstatefields[i].flags;
1374
338
        if ((flags & F_REG_IN_CRM)
1375
338
            && ((fld_crm & 0xe) != PSTATE_DECODE_CRM (flags)))
1376
165
          continue;
1377
173
        info->sysreg.flags = flags;
1378
173
        return true;
1379
338
      }
1380
  /* Reserved value in <pstatefield>.  */
1381
56
  return false;
1382
229
}
1383
1384
/* Decode the system instruction op operand for e.g. AT <at_op>, <Xt>.  */
1385
bool
1386
aarch64_ext_sysins_op (const aarch64_operand *self ATTRIBUTE_UNUSED,
1387
           aarch64_opnd_info *info,
1388
           aarch64_insn code,
1389
           const aarch64_inst *inst ATTRIBUTE_UNUSED,
1390
           aarch64_operand_error *errors ATTRIBUTE_UNUSED)
1391
4.15k
{
1392
4.15k
  int i;
1393
4.15k
  aarch64_insn value;
1394
4.15k
  const aarch64_sys_ins_reg *sysins_ops;
1395
  /* op0:op1:CRn:CRm:op2 */
1396
4.15k
  value = extract_fields (code, 0, 5,
1397
4.15k
        FLD_op0, FLD_op1, FLD_CRn,
1398
4.15k
        FLD_CRm, FLD_op2);
1399
1400
4.15k
  switch (info->type)
1401
4.15k
    {
1402
878
    case AARCH64_OPND_SYSREG_AT: sysins_ops = aarch64_sys_regs_at; break;
1403
918
    case AARCH64_OPND_SYSREG_DC: sysins_ops = aarch64_sys_regs_dc; break;
1404
1.02k
    case AARCH64_OPND_SYSREG_IC: sysins_ops = aarch64_sys_regs_ic; break;
1405
1.12k
    case AARCH64_OPND_SYSREG_TLBI: sysins_ops = aarch64_sys_regs_tlbi; break;
1406
214
    case AARCH64_OPND_SYSREG_TLBIP: sysins_ops = aarch64_sys_regs_tlbi; break;
1407
0
    case AARCH64_OPND_SYSREG_SR:
1408
0
  sysins_ops = aarch64_sys_regs_sr;
1409
   /* Let's remove op2 for rctx.  Refer to comments in the definition of
1410
      aarch64_sys_regs_sr[].  */
1411
0
  value = value & ~(0x7);
1412
0
  break;
1413
0
    default: return false;
1414
4.15k
    }
1415
1416
257k
  for (i = 0; sysins_ops[i].name != NULL; ++i)
1417
253k
    if (sysins_ops[i].value == value)
1418
252
      {
1419
252
  info->sysins_op = sysins_ops + i;
1420
252
  DEBUG_TRACE ("%s found value: %x, has_xt: %d, i: %d.",
1421
252
         info->sysins_op->name,
1422
252
         (unsigned)info->sysins_op->value,
1423
252
         aarch64_sys_ins_reg_has_xt (info->sysins_op), i);
1424
252
  return true;
1425
252
      }
1426
1427
3.90k
  return false;
1428
4.15k
}
1429
1430
/* Decode the memory barrier option operand for e.g. DMB <option>|#<imm>.  */
1431
1432
bool
1433
aarch64_ext_barrier (const aarch64_operand *self ATTRIBUTE_UNUSED,
1434
         aarch64_opnd_info *info,
1435
         aarch64_insn code,
1436
         const aarch64_inst *inst ATTRIBUTE_UNUSED,
1437
         aarch64_operand_error *errors ATTRIBUTE_UNUSED)
1438
330
{
1439
  /* CRm */
1440
330
  info->barrier = aarch64_barrier_options + extract_field (FLD_CRm, code, 0);
1441
330
  return true;
1442
330
}
1443
1444
/* Decode the memory barrier option operand for DSB <option>nXS|#<imm>.  */
1445
1446
bool
1447
aarch64_ext_barrier_dsb_nxs (const aarch64_operand *self ATTRIBUTE_UNUSED,
1448
         aarch64_opnd_info *info,
1449
         aarch64_insn code,
1450
         const aarch64_inst *inst ATTRIBUTE_UNUSED,
1451
         aarch64_operand_error *errors ATTRIBUTE_UNUSED)
1452
228
{
1453
  /* For the DSB nXS barrier variant immediate is encoded in 2-bit field.  */
1454
228
  aarch64_insn field = extract_field (FLD_CRm_dsb_nxs, code, 0);
1455
228
  info->barrier = aarch64_barrier_dsb_nxs_options + field;
1456
228
  return true;
1457
228
}
1458
1459
/* Decode the prefetch operation option operand for e.g.
1460
     PRFM <prfop>, [<Xn|SP>{, #<pimm>}].  */
1461
1462
bool
1463
aarch64_ext_prfop (const aarch64_operand *self ATTRIBUTE_UNUSED,
1464
       aarch64_opnd_info *info,
1465
       aarch64_insn code, const aarch64_inst *inst ATTRIBUTE_UNUSED,
1466
       aarch64_operand_error *errors ATTRIBUTE_UNUSED)
1467
33.9k
{
1468
  /* prfop in Rt */
1469
33.9k
  info->prfop = aarch64_prfops + extract_field (FLD_Rt, code, 0);
1470
33.9k
  return true;
1471
33.9k
}
1472
1473
/* Decode the hint number for an alias taking an operand.  Set info->hint_option
1474
   to the matching name/value pair in aarch64_hint_options.  */
1475
1476
bool
1477
aarch64_ext_hint (const aarch64_operand *self ATTRIBUTE_UNUSED,
1478
      aarch64_opnd_info *info,
1479
      aarch64_insn code,
1480
      const aarch64_inst *inst ATTRIBUTE_UNUSED,
1481
      aarch64_operand_error *errors ATTRIBUTE_UNUSED)
1482
240
{
1483
  /* CRm:op2.  */
1484
240
  unsigned hint_number;
1485
240
  int i;
1486
1487
240
  hint_number = extract_fields (code, 0, 2, FLD_CRm, FLD_op2);
1488
1489
1.41k
  for (i = 0; aarch64_hint_options[i].name != NULL; i++)
1490
1.41k
    {
1491
1.41k
      if (hint_number == HINT_VAL (aarch64_hint_options[i].value))
1492
240
  {
1493
240
    info->hint_option = &(aarch64_hint_options[i]);
1494
240
    return true;
1495
240
  }
1496
1.41k
    }
1497
1498
0
  return false;
1499
240
}
1500
1501
/* Decode the extended register operand for e.g.
1502
     STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}].  */
1503
bool
1504
aarch64_ext_reg_extended (const aarch64_operand *self ATTRIBUTE_UNUSED,
1505
        aarch64_opnd_info *info,
1506
        aarch64_insn code,
1507
        const aarch64_inst *inst ATTRIBUTE_UNUSED,
1508
        aarch64_operand_error *errors ATTRIBUTE_UNUSED)
1509
41.9k
{
1510
41.9k
  aarch64_insn value;
1511
1512
  /* Rm */
1513
41.9k
  info->reg.regno = extract_field (FLD_Rm, code, 0);
1514
  /* option */
1515
41.9k
  value = extract_field (FLD_option, code, 0);
1516
41.9k
  info->shifter.kind =
1517
41.9k
    aarch64_get_operand_modifier_from_value (value, true /* extend_p */);
1518
  /* imm3 */
1519
41.9k
  info->shifter.amount = extract_field (FLD_imm3_10, code,  0);
1520
1521
  /* This makes the constraint checking happy.  */
1522
41.9k
  info->shifter.operator_present = 1;
1523
1524
  /* Assume inst->operands[0].qualifier has been resolved.  */
1525
41.9k
  assert (inst->operands[0].qualifier != AARCH64_OPND_QLF_NIL);
1526
41.9k
  info->qualifier = AARCH64_OPND_QLF_W;
1527
41.9k
  if (inst->operands[0].qualifier == AARCH64_OPND_QLF_X
1528
41.9k
      && (info->shifter.kind == AARCH64_MOD_UXTX
1529
13.8k
    || info->shifter.kind == AARCH64_MOD_SXTX))
1530
4.08k
    info->qualifier = AARCH64_OPND_QLF_X;
1531
1532
41.9k
  return true;
1533
41.9k
}
1534
1535
/* Decode the shifted register operand for e.g.
1536
     SUBS <Xd>, <Xn>, <Xm> {, <shift> #<amount>}.  */
1537
bool
1538
aarch64_ext_reg_shifted (const aarch64_operand *self ATTRIBUTE_UNUSED,
1539
       aarch64_opnd_info *info,
1540
       aarch64_insn code,
1541
       const aarch64_inst *inst ATTRIBUTE_UNUSED,
1542
       aarch64_operand_error *errors ATTRIBUTE_UNUSED)
1543
488k
{
1544
488k
  aarch64_insn value;
1545
1546
  /* Rm */
1547
488k
  info->reg.regno = extract_field (FLD_Rm, code, 0);
1548
  /* shift */
1549
488k
  value = extract_field (FLD_shift, code, 0);
1550
488k
  info->shifter.kind =
1551
488k
    aarch64_get_operand_modifier_from_value (value, false /* extend_p */);
1552
488k
  if (info->shifter.kind == AARCH64_MOD_ROR
1553
488k
      && inst->opcode->iclass != log_shift)
1554
    /* ROR is not available for the shifted register operand in arithmetic
1555
       instructions.  */
1556
21.0k
    return false;
1557
  /* imm6 */
1558
467k
  info->shifter.amount = extract_field (FLD_imm6_10, code,  0);
1559
1560
  /* This makes the constraint checking happy.  */
1561
467k
  info->shifter.operator_present = 1;
1562
1563
467k
  return true;
1564
488k
}
1565
1566
/* Decode the LSL-shifted register operand for e.g.
1567
     ADDPT <Xd|SP>, <Xn|SP>, <Xm>{, LSL #<amount>}.  */
1568
bool
1569
aarch64_ext_reg_lsl_shifted (const aarch64_operand *self ATTRIBUTE_UNUSED,
1570
           aarch64_opnd_info *info,
1571
           aarch64_insn code,
1572
           const aarch64_inst *inst ATTRIBUTE_UNUSED,
1573
           aarch64_operand_error *errors ATTRIBUTE_UNUSED)
1574
881
{
1575
  /* Rm */
1576
881
  info->reg.regno = extract_field (FLD_Rm, code, 0);
1577
  /* imm3 */
1578
881
  info->shifter.kind = AARCH64_MOD_LSL;
1579
881
  info->shifter.amount = extract_field (FLD_imm3_10, code,  0);
1580
881
  return true;
1581
881
}
1582
1583
/* Decode an SVE address [<base>, #<offset>*<factor>, MUL VL],
1584
   where <offset> is given by the OFFSET parameter and where <factor> is
1585
   1 plus SELF's operand-dependent value.  fields[0] specifies the field
1586
   that holds <base>.  */
1587
static bool
1588
aarch64_ext_sve_addr_reg_mul_vl (const aarch64_operand *self,
1589
         aarch64_opnd_info *info, aarch64_insn code,
1590
         int64_t offset)
1591
59.5k
{
1592
59.5k
  info->addr.base_regno = extract_field (self->fields[0], code, 0);
1593
59.5k
  info->addr.offset.imm = offset * (1 + get_operand_specific_data (self));
1594
59.5k
  info->addr.offset.is_reg = false;
1595
59.5k
  info->addr.writeback = false;
1596
59.5k
  info->addr.preind = true;
1597
59.5k
  if (offset != 0)
1598
56.4k
    info->shifter.kind = AARCH64_MOD_MUL_VL;
1599
59.5k
  info->shifter.amount = 1;
1600
59.5k
  info->shifter.operator_present = (info->addr.offset.imm != 0);
1601
59.5k
  info->shifter.amount_present = false;
1602
59.5k
  return true;
1603
59.5k
}
1604
1605
/* Decode an SVE address [<base>, #<simm4>*<factor>, MUL VL],
1606
   where <simm4> is a 4-bit signed value and where <factor> is 1 plus
1607
   SELF's operand-dependent value.  fields[0] specifies the field that
1608
   holds <base>.  <simm4> is encoded in the SVE_imm4 field.  */
1609
bool
1610
aarch64_ext_sve_addr_ri_s4xvl (const aarch64_operand *self,
1611
             aarch64_opnd_info *info, aarch64_insn code,
1612
             const aarch64_inst *inst ATTRIBUTE_UNUSED,
1613
             aarch64_operand_error *errors ATTRIBUTE_UNUSED)
1614
54.1k
{
1615
54.1k
  int offset;
1616
1617
54.1k
  offset = extract_field (FLD_SVE_imm4, code, 0);
1618
54.1k
  offset = ((offset + 8) & 15) - 8;
1619
54.1k
  return aarch64_ext_sve_addr_reg_mul_vl (self, info, code, offset);
1620
54.1k
}
1621
1622
/* Decode an SVE address [<base>, #<simm6>*<factor>, MUL VL],
1623
   where <simm6> is a 6-bit signed value and where <factor> is 1 plus
1624
   SELF's operand-dependent value.  fields[0] specifies the field that
1625
   holds <base>.  <simm6> is encoded in the SVE_imm6 field.  */
1626
bool
1627
aarch64_ext_sve_addr_ri_s6xvl (const aarch64_operand *self,
1628
             aarch64_opnd_info *info, aarch64_insn code,
1629
             const aarch64_inst *inst ATTRIBUTE_UNUSED,
1630
             aarch64_operand_error *errors ATTRIBUTE_UNUSED)
1631
1.66k
{
1632
1.66k
  int offset;
1633
1634
1.66k
  offset = extract_field (FLD_SVE_imm6, code, 0);
1635
1.66k
  offset = (((offset + 32) & 63) - 32);
1636
1.66k
  return aarch64_ext_sve_addr_reg_mul_vl (self, info, code, offset);
1637
1.66k
}
1638
1639
/* Decode an SVE address [<base>, #<simm9>*<factor>, MUL VL],
1640
   where <simm9> is a 9-bit signed value and where <factor> is 1 plus
1641
   SELF's operand-dependent value.  fields[0] specifies the field that
1642
   holds <base>.  <simm9> is encoded in the concatenation of the SVE_imm6
1643
   and imm3 fields, with imm3 being the less-significant part.  */
1644
bool
1645
aarch64_ext_sve_addr_ri_s9xvl (const aarch64_operand *self,
1646
             aarch64_opnd_info *info,
1647
             aarch64_insn code,
1648
             const aarch64_inst *inst ATTRIBUTE_UNUSED,
1649
             aarch64_operand_error *errors ATTRIBUTE_UNUSED)
1650
3.74k
{
1651
3.74k
  int offset;
1652
1653
3.74k
  offset = extract_fields (code, 0, 2, FLD_SVE_imm6, FLD_imm3_10);
1654
3.74k
  offset = (((offset + 256) & 511) - 256);
1655
3.74k
  return aarch64_ext_sve_addr_reg_mul_vl (self, info, code, offset);
1656
3.74k
}
1657
1658
/* Decode an SVE address [<base>, #<offset> << <shift>], where <offset>
1659
   is given by the OFFSET parameter and where <shift> is SELF's operand-
1660
   dependent value.  fields[0] specifies the base register field <base>.  */
1661
static bool
1662
aarch64_ext_sve_addr_reg_imm (const aarch64_operand *self,
1663
            aarch64_opnd_info *info, aarch64_insn code,
1664
            int64_t offset)
1665
24.1k
{
1666
24.1k
  info->addr.base_regno = extract_field (self->fields[0], code, 0);
1667
24.1k
  info->addr.offset.imm = offset * (1 << get_operand_specific_data (self));
1668
24.1k
  info->addr.offset.is_reg = false;
1669
24.1k
  info->addr.writeback = false;
1670
24.1k
  info->addr.preind = true;
1671
24.1k
  info->shifter.operator_present = false;
1672
24.1k
  info->shifter.amount_present = false;
1673
24.1k
  return true;
1674
24.1k
}
1675
1676
/* Decode an SVE address [X<n>, #<SVE_imm4> << <shift>], where <SVE_imm4>
1677
   is a 4-bit signed number and where <shift> is SELF's operand-dependent
1678
   value.  fields[0] specifies the base register field.  */
1679
bool
1680
aarch64_ext_sve_addr_ri_s4 (const aarch64_operand *self,
1681
          aarch64_opnd_info *info, aarch64_insn code,
1682
          const aarch64_inst *inst ATTRIBUTE_UNUSED,
1683
          aarch64_operand_error *errors ATTRIBUTE_UNUSED)
1684
1.32k
{
1685
1.32k
  int offset = sign_extend (extract_field (FLD_SVE_imm4, code, 0), 3);
1686
1.32k
  return aarch64_ext_sve_addr_reg_imm (self, info, code, offset);
1687
1.32k
}
1688
1689
/* Decode an SVE address [X<n>, #<SVE_imm6> << <shift>], where <SVE_imm6>
1690
   is a 6-bit unsigned number and where <shift> is SELF's operand-dependent
1691
   value.  fields[0] specifies the base register field.  */
1692
bool
1693
aarch64_ext_sve_addr_ri_u6 (const aarch64_operand *self,
1694
          aarch64_opnd_info *info, aarch64_insn code,
1695
          const aarch64_inst *inst ATTRIBUTE_UNUSED,
1696
          aarch64_operand_error *errors ATTRIBUTE_UNUSED)
1697
11.1k
{
1698
11.1k
  int offset = extract_field (FLD_SVE_imm6, code, 0);
1699
11.1k
  return aarch64_ext_sve_addr_reg_imm (self, info, code, offset);
1700
11.1k
}
1701
1702
/* Decode an SVE address [X<n>, X<m>{, LSL #<shift>}], where <shift>
1703
   is SELF's operand-dependent value.  fields[0] specifies the base
1704
   register field and fields[1] specifies the offset register field.  */
1705
bool
1706
aarch64_ext_sve_addr_rr_lsl (const aarch64_operand *self,
1707
           aarch64_opnd_info *info, aarch64_insn code,
1708
           const aarch64_inst *inst ATTRIBUTE_UNUSED,
1709
           aarch64_operand_error *errors ATTRIBUTE_UNUSED)
1710
113k
{
1711
113k
  int index_regno;
1712
1713
113k
  index_regno = extract_field (self->fields[1], code, 0);
1714
113k
  if (index_regno == 31 && (self->flags & OPD_F_NO_ZR) != 0)
1715
786
    return false;
1716
1717
112k
  info->addr.base_regno = extract_field (self->fields[0], code, 0);
1718
112k
  info->addr.offset.regno = index_regno;
1719
112k
  info->addr.offset.is_reg = true;
1720
112k
  info->addr.writeback = false;
1721
112k
  info->addr.preind = true;
1722
112k
  info->shifter.kind = AARCH64_MOD_LSL;
1723
112k
  info->shifter.amount = get_operand_specific_data (self);
1724
112k
  info->shifter.operator_present = (info->shifter.amount != 0);
1725
112k
  info->shifter.amount_present = (info->shifter.amount != 0);
1726
112k
  return true;
1727
113k
}
1728
1729
/* Decode an SVE address [X<n>, Z<m>.<T>, (S|U)XTW {#<shift>}], where
1730
   <shift> is SELF's operand-dependent value.  fields[0] specifies the
1731
   base register field, fields[1] specifies the offset register field and
1732
   fields[2] is a single-bit field that selects SXTW over UXTW.  */
1733
bool
1734
aarch64_ext_sve_addr_rz_xtw (const aarch64_operand *self,
1735
           aarch64_opnd_info *info, aarch64_insn code,
1736
           const aarch64_inst *inst ATTRIBUTE_UNUSED,
1737
           aarch64_operand_error *errors ATTRIBUTE_UNUSED)
1738
53.7k
{
1739
53.7k
  info->addr.base_regno = extract_field (self->fields[0], code, 0);
1740
53.7k
  info->addr.offset.regno = extract_field (self->fields[1], code, 0);
1741
53.7k
  info->addr.offset.is_reg = true;
1742
53.7k
  info->addr.writeback = false;
1743
53.7k
  info->addr.preind = true;
1744
53.7k
  if (extract_field (self->fields[2], code, 0))
1745
24.5k
    info->shifter.kind = AARCH64_MOD_SXTW;
1746
29.2k
  else
1747
29.2k
    info->shifter.kind = AARCH64_MOD_UXTW;
1748
53.7k
  info->shifter.amount = get_operand_specific_data (self);
1749
53.7k
  info->shifter.operator_present = true;
1750
53.7k
  info->shifter.amount_present = (info->shifter.amount != 0);
1751
53.7k
  return true;
1752
53.7k
}
1753
1754
/* Decode an SVE address [Z<n>.<T>, #<imm5> << <shift>], where <imm5> is a
1755
   5-bit unsigned number and where <shift> is SELF's operand-dependent value.
1756
   fields[0] specifies the base register field.  */
1757
bool
1758
aarch64_ext_sve_addr_zi_u5 (const aarch64_operand *self,
1759
          aarch64_opnd_info *info, aarch64_insn code,
1760
          const aarch64_inst *inst ATTRIBUTE_UNUSED,
1761
          aarch64_operand_error *errors ATTRIBUTE_UNUSED)
1762
11.7k
{
1763
11.7k
  int offset = extract_field (FLD_imm5, code, 0);
1764
11.7k
  return aarch64_ext_sve_addr_reg_imm (self, info, code, offset);
1765
11.7k
}
1766
1767
/* Decode an SVE address [Z<n>.<T>, Z<m>.<T>{, <modifier> {#<msz>}}],
1768
   where <modifier> is given by KIND and where <msz> is a 2-bit unsigned
1769
   number.  fields[0] specifies the base register field and fields[1]
1770
   specifies the offset register field.  */
1771
static bool
1772
aarch64_ext_sve_addr_zz (const aarch64_operand *self, aarch64_opnd_info *info,
1773
       aarch64_insn code, enum aarch64_modifier_kind kind)
1774
1.05k
{
1775
1.05k
  info->addr.base_regno = extract_field (self->fields[0], code, 0);
1776
1.05k
  info->addr.offset.regno = extract_field (self->fields[1], code, 0);
1777
1.05k
  info->addr.offset.is_reg = true;
1778
1.05k
  info->addr.writeback = false;
1779
1.05k
  info->addr.preind = true;
1780
1.05k
  info->shifter.kind = kind;
1781
1.05k
  info->shifter.amount = extract_field (FLD_SVE_msz, code, 0);
1782
1.05k
  info->shifter.operator_present = (kind != AARCH64_MOD_LSL
1783
1.05k
            || info->shifter.amount != 0);
1784
1.05k
  info->shifter.amount_present = (info->shifter.amount != 0);
1785
1.05k
  return true;
1786
1.05k
}
1787
1788
/* Decode an SVE address [Z<n>.<T>, Z<m>.<T>{, LSL #<msz>}], where
1789
   <msz> is a 2-bit unsigned number.  fields[0] specifies the base register
1790
   field and fields[1] specifies the offset register field.  */
1791
bool
1792
aarch64_ext_sve_addr_zz_lsl (const aarch64_operand *self,
1793
           aarch64_opnd_info *info, aarch64_insn code,
1794
           const aarch64_inst *inst ATTRIBUTE_UNUSED,
1795
           aarch64_operand_error *errors ATTRIBUTE_UNUSED)
1796
375
{
1797
375
  return aarch64_ext_sve_addr_zz (self, info, code, AARCH64_MOD_LSL);
1798
375
}
1799
1800
/* Decode an SVE address [Z<n>.<T>, Z<m>.<T>, SXTW {#<msz>}], where
1801
   <msz> is a 2-bit unsigned number.  fields[0] specifies the base register
1802
   field and fields[1] specifies the offset register field.  */
1803
bool
1804
aarch64_ext_sve_addr_zz_sxtw (const aarch64_operand *self,
1805
            aarch64_opnd_info *info, aarch64_insn code,
1806
            const aarch64_inst *inst ATTRIBUTE_UNUSED,
1807
            aarch64_operand_error *errors ATTRIBUTE_UNUSED)
1808
157
{
1809
157
  return aarch64_ext_sve_addr_zz (self, info, code, AARCH64_MOD_SXTW);
1810
157
}
1811
1812
/* Decode an SVE address [Z<n>.<T>, Z<m>.<T>, UXTW {#<msz>}], where
1813
   <msz> is a 2-bit unsigned number.  fields[0] specifies the base register
1814
   field and fields[1] specifies the offset register field.  */
1815
bool
1816
aarch64_ext_sve_addr_zz_uxtw (const aarch64_operand *self,
1817
            aarch64_opnd_info *info, aarch64_insn code,
1818
            const aarch64_inst *inst ATTRIBUTE_UNUSED,
1819
            aarch64_operand_error *errors ATTRIBUTE_UNUSED)
1820
524
{
1821
524
  return aarch64_ext_sve_addr_zz (self, info, code, AARCH64_MOD_UXTW);
1822
524
}
1823
1824
/* Finish decoding an SVE arithmetic immediate, given that INFO already
1825
   has the raw field value and that the low 8 bits decode to VALUE.  */
1826
static bool
1827
decode_sve_aimm (aarch64_opnd_info *info, int64_t value)
1828
16.5k
{
1829
16.5k
  info->shifter.kind = AARCH64_MOD_LSL;
1830
16.5k
  info->shifter.amount = 0;
1831
16.5k
  if (info->imm.value & 0x100)
1832
2.92k
    {
1833
2.92k
      if (value == 0)
1834
  /* Decode 0x100 as #0, LSL #8.  */
1835
76
  info->shifter.amount = 8;
1836
2.85k
      else
1837
2.85k
  value *= 256;
1838
2.92k
    }
1839
16.5k
  info->shifter.operator_present = (info->shifter.amount != 0);
1840
16.5k
  info->shifter.amount_present = (info->shifter.amount != 0);
1841
16.5k
  info->imm.value = value;
1842
16.5k
  return true;
1843
16.5k
}
1844
1845
/* Decode an SVE ADD/SUB immediate.  */
1846
bool
1847
aarch64_ext_sve_aimm (const aarch64_operand *self,
1848
          aarch64_opnd_info *info, const aarch64_insn code,
1849
          const aarch64_inst *inst,
1850
          aarch64_operand_error *errors)
1851
1.05k
{
1852
1.05k
  return (aarch64_ext_imm (self, info, code, inst, errors)
1853
1.05k
    && decode_sve_aimm (info, (uint8_t) info->imm.value));
1854
1.05k
}
1855
1856
bool
1857
aarch64_ext_sve_aligned_reglist (const aarch64_operand *self,
1858
         aarch64_opnd_info *info, aarch64_insn code,
1859
         const aarch64_inst *inst ATTRIBUTE_UNUSED,
1860
         aarch64_operand_error *errors ATTRIBUTE_UNUSED)
1861
19.1k
{
1862
19.1k
  unsigned int num_regs = get_operand_specific_data (self);
1863
19.1k
  unsigned int val = extract_field (self->fields[0], code, 0);
1864
19.1k
  info->reglist.first_regno = val * num_regs;
1865
19.1k
  info->reglist.num_regs = num_regs;
1866
19.1k
  info->reglist.stride = 1;
1867
19.1k
  return true;
1868
19.1k
}
1869
1870
/* Decode an SVE CPY/DUP immediate.  */
1871
bool
1872
aarch64_ext_sve_asimm (const aarch64_operand *self,
1873
           aarch64_opnd_info *info, const aarch64_insn code,
1874
           const aarch64_inst *inst,
1875
           aarch64_operand_error *errors)
1876
15.4k
{
1877
15.4k
  return (aarch64_ext_imm (self, info, code, inst, errors)
1878
15.4k
    && decode_sve_aimm (info, (int8_t) info->imm.value));
1879
15.4k
}
1880
1881
/* Decode a single-bit immediate that selects between #0.5 and #1.0.
1882
   The fields array specifies which field to use.  */
1883
bool
1884
aarch64_ext_sve_float_half_one (const aarch64_operand *self,
1885
        aarch64_opnd_info *info, aarch64_insn code,
1886
        const aarch64_inst *inst ATTRIBUTE_UNUSED,
1887
        aarch64_operand_error *errors ATTRIBUTE_UNUSED)
1888
12
{
1889
12
  if (extract_field (self->fields[0], code, 0))
1890
8
    info->imm.value = 0x3f800000;
1891
4
  else
1892
4
    info->imm.value = 0x3f000000;
1893
12
  info->imm.is_fp = true;
1894
12
  return true;
1895
12
}
1896
1897
/* Decode a single-bit immediate that selects between #0.5 and #2.0.
1898
   The fields array specifies which field to use.  */
1899
bool
1900
aarch64_ext_sve_float_half_two (const aarch64_operand *self,
1901
        aarch64_opnd_info *info, aarch64_insn code,
1902
        const aarch64_inst *inst ATTRIBUTE_UNUSED,
1903
        aarch64_operand_error *errors ATTRIBUTE_UNUSED)
1904
3
{
1905
3
  if (extract_field (self->fields[0], code, 0))
1906
0
    info->imm.value = 0x40000000;
1907
3
  else
1908
3
    info->imm.value = 0x3f000000;
1909
3
  info->imm.is_fp = true;
1910
3
  return true;
1911
3
}
1912
1913
/* Decode a single-bit immediate that selects between #0.0 and #1.0.
1914
   The fields array specifies which field to use.  */
1915
bool
1916
aarch64_ext_sve_float_zero_one (const aarch64_operand *self,
1917
        aarch64_opnd_info *info, aarch64_insn code,
1918
        const aarch64_inst *inst ATTRIBUTE_UNUSED,
1919
        aarch64_operand_error *errors ATTRIBUTE_UNUSED)
1920
75
{
1921
75
  if (extract_field (self->fields[0], code, 0))
1922
24
    info->imm.value = 0x3f800000;
1923
51
  else
1924
51
    info->imm.value = 0x0;
1925
75
  info->imm.is_fp = true;
1926
75
  return true;
1927
75
}
1928
1929
/* Decode ZA tile vector, vector indicator, vector selector, qualifier and
1930
   immediate on numerous SME instruction fields such as MOVA.  */
1931
bool
1932
aarch64_ext_sme_za_hv_tiles (const aarch64_operand *self,
1933
                             aarch64_opnd_info *info, aarch64_insn code,
1934
                             const aarch64_inst *inst ATTRIBUTE_UNUSED,
1935
                             aarch64_operand_error *errors ATTRIBUTE_UNUSED)
1936
41.6k
{
1937
41.6k
  int fld_size = extract_field (self->fields[0], code, 0);
1938
41.6k
  int fld_q = extract_field (self->fields[1], code, 0);
1939
41.6k
  int fld_v = extract_field (self->fields[2], code, 0);
1940
41.6k
  int fld_rv = extract_field (self->fields[3], code, 0);
1941
41.6k
  int fld_zan_imm = extract_field (self->fields[4], code, 0);
1942
1943
  /* Deduce qualifier encoded in size and Q fields.  */
1944
41.6k
  if (fld_size == 0)
1945
9.30k
    {
1946
9.30k
      info->indexed_za.regno = 0;
1947
9.30k
      info->indexed_za.index.imm = fld_zan_imm;
1948
9.30k
    }
1949
32.3k
  else if (fld_size == 1)
1950
3.34k
    {
1951
3.34k
      info->indexed_za.regno = fld_zan_imm >> 3;
1952
3.34k
      info->indexed_za.index.imm = fld_zan_imm & 0x07;
1953
3.34k
    }
1954
28.9k
  else if (fld_size == 2)
1955
2.56k
    {
1956
2.56k
      info->indexed_za.regno = fld_zan_imm >> 2;
1957
2.56k
      info->indexed_za.index.imm = fld_zan_imm & 0x03;
1958
2.56k
    }
1959
26.4k
  else if (fld_size == 3 && fld_q == 0)
1960
18.4k
    {
1961
18.4k
      info->indexed_za.regno = fld_zan_imm >> 1;
1962
18.4k
      info->indexed_za.index.imm = fld_zan_imm & 0x01;
1963
18.4k
    }
1964
7.96k
  else if (fld_size == 3 && fld_q == 1)
1965
7.96k
    {
1966
7.96k
      info->indexed_za.regno = fld_zan_imm;
1967
7.96k
      info->indexed_za.index.imm = 0;
1968
7.96k
    }
1969
0
  else
1970
0
    return false;
1971
1972
41.6k
  info->indexed_za.index.regno = fld_rv + 12;
1973
41.6k
  info->indexed_za.v = fld_v;
1974
1975
41.6k
  return true;
1976
41.6k
}
1977
1978
bool
1979
aarch64_ext_sme_za_hv_tiles_range (const aarch64_operand *self,
1980
           aarch64_opnd_info *info, aarch64_insn code,
1981
           const aarch64_inst *inst ATTRIBUTE_UNUSED,
1982
           aarch64_operand_error *errors
1983
             ATTRIBUTE_UNUSED)
1984
267
{
1985
267
  int ebytes = aarch64_get_qualifier_esize (info->qualifier);
1986
267
  int range_size = get_opcode_dependent_value (inst->opcode);
1987
267
  int fld_v = extract_field (self->fields[0], code, 0);
1988
267
  int fld_rv = extract_field (self->fields[1], code, 0);
1989
267
  int fld_zan_imm = extract_field (self->fields[2], code, 0);
1990
267
  int max_value = 16 / range_size / ebytes;
1991
1992
267
  if (max_value == 0)
1993
54
    max_value = 1;
1994
1995
267
  int regno = fld_zan_imm / max_value;
1996
267
  if (regno >= ebytes)
1997
2
    return false;
1998
1999
265
  info->indexed_za.regno = regno;
2000
265
  info->indexed_za.index.imm = (fld_zan_imm % max_value) * range_size;
2001
265
  info->indexed_za.index.countm1 = range_size - 1;
2002
265
  info->indexed_za.index.regno = fld_rv + 12;
2003
265
  info->indexed_za.v = fld_v;
2004
2005
265
  return true;
2006
267
}
2007
2008
/* Decode in SME instruction ZERO list of up to eight 64-bit element tile names
2009
   separated by commas, encoded in the "imm8" field.
2010
2011
   For programmer convenience an assembler must also accept the names of
2012
   32-bit, 16-bit and 8-bit element tiles which are converted into the
2013
   corresponding set of 64-bit element tiles.
2014
*/
2015
bool
2016
aarch64_ext_sme_za_list (const aarch64_operand *self,
2017
                         aarch64_opnd_info *info, aarch64_insn code,
2018
                         const aarch64_inst *inst ATTRIBUTE_UNUSED,
2019
                         aarch64_operand_error *errors ATTRIBUTE_UNUSED)
2020
0
{
2021
0
  int mask = extract_field (self->fields[0], code, 0);
2022
0
  info->imm.value = mask;
2023
0
  return true;
2024
0
}
2025
2026
/* Decode ZA array vector select register (Rv field), optional vector and
2027
   memory offset (imm4_11 field).
2028
*/
2029
bool
2030
aarch64_ext_sme_za_array (const aarch64_operand *self,
2031
                          aarch64_opnd_info *info, aarch64_insn code,
2032
                          const aarch64_inst *inst,
2033
                          aarch64_operand_error *errors ATTRIBUTE_UNUSED)
2034
12.0k
{
2035
12.0k
  int regno = extract_field (self->fields[0], code, 0);
2036
12.0k
  if (info->type == AARCH64_OPND_SME_ZA_array_off4)
2037
908
    regno += 12;
2038
11.1k
  else
2039
11.1k
    regno += 8;
2040
12.0k
  int imm = extract_field (self->fields[1], code, 0);
2041
12.0k
  int num_offsets = get_operand_specific_data (self);
2042
12.0k
  if (num_offsets == 0)
2043
3.04k
    num_offsets = 1;
2044
12.0k
  info->indexed_za.index.regno = regno;
2045
12.0k
  info->indexed_za.index.imm = imm * num_offsets;
2046
12.0k
  info->indexed_za.index.countm1 = num_offsets - 1;
2047
12.0k
  info->indexed_za.group_size = get_opcode_dependent_value (inst->opcode);
2048
12.0k
  return true;
2049
12.0k
}
2050
2051
/* Decode two ZA tile slice (V, Rv, off3| ZAn ,off2 | ZAn, ol| ZAn) feilds.  */
2052
bool
2053
aarch64_ext_sme_za_vrs1 (const aarch64_operand *self,
2054
        aarch64_opnd_info *info, aarch64_insn code,
2055
        const aarch64_inst *inst,
2056
        aarch64_operand_error *errors ATTRIBUTE_UNUSED)
2057
0
{
2058
0
  int v = extract_field (self->fields[0], code, 0);
2059
0
  int regno = 12 + extract_field (self->fields[1], code, 0);
2060
0
  int imm, za_reg, num_offset = 2;
2061
2062
0
  switch (info->qualifier)
2063
0
    {
2064
0
    case AARCH64_OPND_QLF_S_B:
2065
0
      imm = extract_field (self->fields[2], code, 0);
2066
0
      info->indexed_za.index.imm = imm * num_offset;
2067
0
      break;
2068
0
    case AARCH64_OPND_QLF_S_H:
2069
0
    case AARCH64_OPND_QLF_S_S:
2070
0
      za_reg = extract_field (self->fields[2], code, 0);
2071
0
      imm = extract_field (self->fields[3], code, 0);
2072
0
      info->indexed_za.index.imm = imm * num_offset;
2073
0
      info->indexed_za.regno = za_reg;
2074
0
      break;
2075
0
    case AARCH64_OPND_QLF_S_D:
2076
0
      za_reg = extract_field (self->fields[2], code, 0);
2077
0
      info->indexed_za.regno = za_reg;
2078
0
      break;
2079
0
    default:
2080
0
      return false;
2081
0
    }
2082
2083
0
  info->indexed_za.index.regno = regno;
2084
0
  info->indexed_za.index.countm1 = num_offset - 1;
2085
0
  info->indexed_za.v = v;
2086
0
  info->indexed_za.group_size = get_opcode_dependent_value (inst->opcode);
2087
0
  return true;
2088
0
}
2089
2090
/* Decode four ZA tile slice (V, Rv, off3| ZAn ,off2 | ZAn, ol| ZAn) feilds.  */
2091
bool
2092
aarch64_ext_sme_za_vrs2 (const aarch64_operand *self,
2093
        aarch64_opnd_info *info, aarch64_insn code,
2094
        const aarch64_inst *inst,
2095
        aarch64_operand_error *errors ATTRIBUTE_UNUSED)
2096
3
{
2097
3
  int v = extract_field (self->fields[0], code, 0);
2098
3
  int regno = 12 + extract_field (self->fields[1], code, 0);
2099
3
  int imm, za_reg, num_offset =4;
2100
2101
3
  switch (info->qualifier)
2102
3
    {
2103
2
    case AARCH64_OPND_QLF_S_B:
2104
2
      imm = extract_field (self->fields[2], code, 0);
2105
2
      info->indexed_za.index.imm = imm * num_offset;
2106
2
      break;
2107
0
    case AARCH64_OPND_QLF_S_H:
2108
0
      za_reg = extract_field (self->fields[2], code, 0);
2109
0
      imm = extract_field (self->fields[3], code, 0);
2110
0
      info->indexed_za.index.imm = imm * num_offset;
2111
0
      info->indexed_za.regno = za_reg;
2112
0
      break;
2113
0
    case AARCH64_OPND_QLF_S_S:
2114
1
    case AARCH64_OPND_QLF_S_D:
2115
1
      za_reg = extract_field (self->fields[2], code, 0);
2116
1
      info->indexed_za.regno = za_reg;
2117
1
      break;
2118
0
    default:
2119
0
      return false;
2120
3
    }
2121
2122
3
  info->indexed_za.index.regno = regno;
2123
3
  info->indexed_za.index.countm1 = num_offset - 1;
2124
3
  info->indexed_za.v = v;
2125
3
  info->indexed_za.group_size = get_opcode_dependent_value (inst->opcode);
2126
3
  return true;
2127
3
}
2128
2129
bool
2130
aarch64_ext_sme_addr_ri_u4xvl (const aarch64_operand *self,
2131
                               aarch64_opnd_info *info, aarch64_insn code,
2132
                               const aarch64_inst *inst ATTRIBUTE_UNUSED,
2133
                               aarch64_operand_error *errors ATTRIBUTE_UNUSED)
2134
908
{
2135
908
  int regno = extract_field (self->fields[0], code, 0);
2136
908
  int imm = extract_field (self->fields[1], code, 0);
2137
908
  info->addr.base_regno = regno;
2138
908
  info->addr.offset.imm = imm;
2139
  /* MUL VL operator is always present for this operand.  */
2140
908
  info->shifter.kind = AARCH64_MOD_MUL_VL;
2141
908
  info->shifter.operator_present = (imm != 0);
2142
908
  return true;
2143
908
}
2144
2145
/* Decode {SM|ZA} filed for SMSTART and SMSTOP instructions.  */
2146
bool
2147
aarch64_ext_sme_sm_za (const aarch64_operand *self,
2148
                       aarch64_opnd_info *info, aarch64_insn code,
2149
                       const aarch64_inst *inst ATTRIBUTE_UNUSED,
2150
                       aarch64_operand_error *errors ATTRIBUTE_UNUSED)
2151
59
{
2152
59
  info->pstatefield = 0x1b;
2153
59
  aarch64_insn fld_crm = extract_field (self->fields[0], code, 0);
2154
59
  fld_crm >>= 1;    /* CRm[3:1].  */
2155
2156
59
  if (fld_crm == 0x1)
2157
4
    info->reg.regno = 's';
2158
55
  else if (fld_crm == 0x2)
2159
0
    info->reg.regno = 'z';
2160
55
  else
2161
55
    return false;
2162
2163
4
  return true;
2164
59
}
2165
2166
bool
2167
aarch64_ext_sme_pred_reg_with_index (const aarch64_operand *self,
2168
             aarch64_opnd_info *info, aarch64_insn code,
2169
             const aarch64_inst *inst ATTRIBUTE_UNUSED,
2170
             aarch64_operand_error *errors ATTRIBUTE_UNUSED)
2171
1.02k
{
2172
1.02k
  aarch64_insn fld_rm = extract_field (self->fields[0], code, 0);
2173
1.02k
  aarch64_insn fld_pn = extract_field (self->fields[1], code, 0);
2174
1.02k
  aarch64_insn fld_i1 = extract_field (self->fields[2], code, 0);
2175
1.02k
  aarch64_insn fld_tszh = extract_field (self->fields[3], code, 0);
2176
1.02k
  aarch64_insn fld_tszl = extract_field (self->fields[4], code, 0);
2177
1.02k
  int imm;
2178
2179
1.02k
  info->indexed_za.regno = fld_pn;
2180
1.02k
  info->indexed_za.index.regno = fld_rm + 12;
2181
2182
1.02k
  if (fld_tszl & 0x1)
2183
504
    imm = (fld_i1 << 3) | (fld_tszh << 2) | (fld_tszl >> 1);
2184
525
  else if (fld_tszl & 0x2)
2185
361
    imm = (fld_i1 << 2) | (fld_tszh << 1) | (fld_tszl >> 2);
2186
164
  else if (fld_tszl & 0x4)
2187
94
    imm = (fld_i1 << 1) | fld_tszh;
2188
70
  else if (fld_tszh)
2189
70
    imm = fld_i1;
2190
0
  else
2191
0
    return false;
2192
2193
1.02k
  info->indexed_za.index.imm = imm;
2194
1.02k
  return true;
2195
1.02k
}
2196
2197
/* Decode Zn[MM], where MM has a 7-bit triangular encoding.  The fields
2198
   array specifies which field to use for Zn.  MM is encoded in the
2199
   concatenation of imm5 and SVE_tszh, with imm5 being the less
2200
   significant part.  */
2201
bool
2202
aarch64_ext_sve_index (const aarch64_operand *self,
2203
           aarch64_opnd_info *info, aarch64_insn code,
2204
           const aarch64_inst *inst ATTRIBUTE_UNUSED,
2205
           aarch64_operand_error *errors ATTRIBUTE_UNUSED)
2206
817
{
2207
817
  int val;
2208
2209
817
  info->reglane.regno = extract_field (self->fields[0], code, 0);
2210
817
  val = extract_fields (code, 0, 2, FLD_SVE_tszh, FLD_imm5);
2211
817
  if ((val & 31) == 0)
2212
0
    return 0;
2213
1.11k
  while ((val & 1) == 0)
2214
293
    val /= 2;
2215
817
  info->reglane.index = val / 2;
2216
817
  return true;
2217
817
}
2218
2219
/* Decode Zn.<T>[<imm>], where <imm> is an immediate with range of 0 to one less
2220
   than the number of elements in 128 bit, which can encode il:tsz.  */
2221
bool
2222
aarch64_ext_sve_index_imm (const aarch64_operand *self,
2223
         aarch64_opnd_info *info, aarch64_insn code,
2224
         const aarch64_inst *inst ATTRIBUTE_UNUSED,
2225
         aarch64_operand_error *errors ATTRIBUTE_UNUSED)
2226
71
{
2227
71
  int val;
2228
2229
71
  info->reglane.regno = extract_field (self->fields[0], code, 0);
2230
71
  val = extract_fields (code, 0, 2, self->fields[2], self->fields[1]);
2231
71
  if ((val & 15) == 0)
2232
0
    return 0;
2233
100
  while ((val & 1) == 0)
2234
29
    val /= 2;
2235
71
  info->reglane.index = val / 2;
2236
71
  return true;
2237
71
}
2238
2239
/* Decode a logical immediate for the MOV alias of SVE DUPM.  */
2240
bool
2241
aarch64_ext_sve_limm_mov (const aarch64_operand *self,
2242
        aarch64_opnd_info *info, const aarch64_insn code,
2243
        const aarch64_inst *inst,
2244
        aarch64_operand_error *errors)
2245
2.36k
{
2246
2.36k
  int esize = aarch64_get_qualifier_esize (inst->operands[0].qualifier);
2247
2.36k
  return (aarch64_ext_limm (self, info, code, inst, errors)
2248
2.36k
    && aarch64_sve_dupm_mov_immediate_p (info->imm.value, esize));
2249
2.36k
}
2250
2251
/* Decode Zn[MM], where Zn occupies the least-significant part of the field
2252
   and where MM occupies the most-significant part.  The operand-dependent
2253
   value specifies the number of bits in Zn.  */
2254
bool
2255
aarch64_ext_sve_quad_index (const aarch64_operand *self,
2256
          aarch64_opnd_info *info, aarch64_insn code,
2257
          const aarch64_inst *inst ATTRIBUTE_UNUSED,
2258
          aarch64_operand_error *errors ATTRIBUTE_UNUSED)
2259
15.4k
{
2260
15.4k
  unsigned int reg_bits = get_operand_specific_data (self);
2261
15.4k
  unsigned int val = extract_all_fields (self, code);
2262
15.4k
  info->reglane.regno = val & ((1 << reg_bits) - 1);
2263
15.4k
  info->reglane.index = val >> reg_bits;
2264
15.4k
  return true;
2265
15.4k
}
2266
2267
/* Decode {Zn.<T> - Zm.<T>}.  The fields array specifies which field
2268
   to use for Zn.  The opcode-dependent value specifies the number
2269
   of registers in the list.  */
2270
bool
2271
aarch64_ext_sve_reglist (const aarch64_operand *self,
2272
       aarch64_opnd_info *info, aarch64_insn code,
2273
       const aarch64_inst *inst ATTRIBUTE_UNUSED,
2274
       aarch64_operand_error *errors ATTRIBUTE_UNUSED)
2275
184k
{
2276
184k
  info->reglist.first_regno = extract_field (self->fields[0], code, 0);
2277
184k
  info->reglist.num_regs = get_opcode_dependent_value (inst->opcode);
2278
184k
  info->reglist.stride = 1;
2279
184k
  return true;
2280
184k
}
2281
2282
/* Decode {Zn.<T> , Zm.<T>}.  The fields array specifies which field
2283
   to use for Zn.  The opcode-dependent value specifies the number
2284
   of registers in the list.  */
2285
bool
2286
aarch64_ext_sve_reglist_zt (const aarch64_operand *self,
2287
          aarch64_opnd_info *info, aarch64_insn code,
2288
          const aarch64_inst *inst ATTRIBUTE_UNUSED,
2289
          aarch64_operand_error *errors ATTRIBUTE_UNUSED)
2290
3.52k
{
2291
3.52k
  info->reglist.first_regno = extract_field (self->fields[0], code, 0);
2292
3.52k
  info->reglist.num_regs = get_operand_specific_data (self);
2293
3.52k
  info->reglist.stride = 1;
2294
3.52k
  return true;
2295
3.52k
}
2296
2297
/* Decode a strided register list.  The first field holds the top bit
2298
   (0 or 16) and the second field holds the lower bits.  The stride is
2299
   16 divided by the list length.  */
2300
bool
2301
aarch64_ext_sve_strided_reglist (const aarch64_operand *self,
2302
         aarch64_opnd_info *info, aarch64_insn code,
2303
         const aarch64_inst *inst ATTRIBUTE_UNUSED,
2304
         aarch64_operand_error *errors
2305
           ATTRIBUTE_UNUSED)
2306
6.52k
{
2307
6.52k
  unsigned int upper = extract_field (self->fields[0], code, 0);
2308
6.52k
  unsigned int lower = extract_field (self->fields[1], code, 0);
2309
6.52k
  info->reglist.first_regno = upper * 16 + lower;
2310
6.52k
  info->reglist.num_regs = get_operand_specific_data (self);
2311
6.52k
  info->reglist.stride = 16 / info->reglist.num_regs;
2312
6.52k
  return true;
2313
6.52k
}
2314
2315
/* Decode <pattern>{, MUL #<amount>}.  The fields array specifies which
2316
   fields to use for <pattern>.  <amount> - 1 is encoded in the SVE_imm4
2317
   field.  */
2318
bool
2319
aarch64_ext_sve_scale (const aarch64_operand *self,
2320
           aarch64_opnd_info *info, aarch64_insn code,
2321
           const aarch64_inst *inst, aarch64_operand_error *errors)
2322
3.92k
{
2323
3.92k
  int val;
2324
2325
3.92k
  if (!aarch64_ext_imm (self, info, code, inst, errors))
2326
0
    return false;
2327
3.92k
  val = extract_field (FLD_SVE_imm4, code, 0);
2328
3.92k
  info->shifter.kind = AARCH64_MOD_MUL;
2329
3.92k
  info->shifter.amount = val + 1;
2330
3.92k
  info->shifter.operator_present = (val != 0);
2331
3.92k
  info->shifter.amount_present = (val != 0);
2332
3.92k
  return true;
2333
3.92k
}
2334
2335
/* Return the top set bit in VALUE, which is expected to be relatively
2336
   small.  */
2337
static uint64_t
2338
get_top_bit (uint64_t value)
2339
6.79k
{
2340
24.6k
  while ((value & -value) != value)
2341
17.8k
    value -= value & -value;
2342
6.79k
  return value;
2343
6.79k
}
2344
2345
/* Decode an SVE shift-left immediate.  */
2346
bool
2347
aarch64_ext_sve_shlimm (const aarch64_operand *self,
2348
      aarch64_opnd_info *info, const aarch64_insn code,
2349
      const aarch64_inst *inst, aarch64_operand_error *errors)
2350
1.29k
{
2351
1.29k
  if (!aarch64_ext_imm (self, info, code, inst, errors)
2352
1.29k
      || info->imm.value == 0)
2353
0
    return false;
2354
2355
1.29k
  info->imm.value -= get_top_bit (info->imm.value);
2356
1.29k
  return true;
2357
1.29k
}
2358
2359
/* Decode an SVE shift-right immediate.  */
2360
bool
2361
aarch64_ext_sve_shrimm (const aarch64_operand *self,
2362
      aarch64_opnd_info *info, const aarch64_insn code,
2363
      const aarch64_inst *inst, aarch64_operand_error *errors)
2364
5.49k
{
2365
5.49k
  if (!aarch64_ext_imm (self, info, code, inst, errors)
2366
5.49k
      || info->imm.value == 0)
2367
0
    return false;
2368
2369
5.49k
  info->imm.value = get_top_bit (info->imm.value) * 2 - info->imm.value;
2370
5.49k
  return true;
2371
5.49k
}
2372
2373
/* Decode X0-X30.  Register 31 is unallocated.  */
2374
bool
2375
aarch64_ext_x0_to_x30 (const aarch64_operand *self, aarch64_opnd_info *info,
2376
           const aarch64_insn code,
2377
           const aarch64_inst *inst ATTRIBUTE_UNUSED,
2378
           aarch64_operand_error *errors ATTRIBUTE_UNUSED)
2379
18.1k
{
2380
18.1k
  info->reg.regno = extract_field (self->fields[0], code, 0);
2381
18.1k
  return info->reg.regno <= 30;
2382
18.1k
}
2383
2384
/* Decode an indexed register, with the first field being the register
2385
   number and the remaining fields being the index.  */
2386
bool
2387
aarch64_ext_simple_index (const aarch64_operand *self, aarch64_opnd_info *info,
2388
        const aarch64_insn code,
2389
        const aarch64_inst *inst ATTRIBUTE_UNUSED,
2390
        aarch64_operand_error *errors ATTRIBUTE_UNUSED)
2391
8.74k
{
2392
8.74k
  int bias = get_operand_specific_data (self);
2393
8.74k
  info->reglane.regno = extract_field (self->fields[0], code, 0) + bias;
2394
8.74k
  info->reglane.index = extract_all_fields_after (self, 1, code);
2395
8.74k
  return true;
2396
8.74k
}
2397
2398
/* Decode a plain shift-right immediate, when there is only a single
2399
   element size.  */
2400
bool
2401
aarch64_ext_plain_shrimm (const aarch64_operand *self, aarch64_opnd_info *info,
2402
        const aarch64_insn code,
2403
        const aarch64_inst *inst ATTRIBUTE_UNUSED,
2404
        aarch64_operand_error *errors ATTRIBUTE_UNUSED)
2405
78
{
2406
78
  unsigned int base = 1 << get_operand_field_width (self, 0);
2407
78
  info->imm.value = base - extract_field (self->fields[0], code, 0);
2408
78
  return true;
2409
78
}
2410

2411
/* Bitfields that are commonly used to encode certain operands' information
2412
   may be partially used as part of the base opcode in some instructions.
2413
   For example, the bit 1 of the field 'size' in
2414
     FCVTXN <Vb><d>, <Va><n>
2415
   is actually part of the base opcode, while only size<0> is available
2416
   for encoding the register type.  Another example is the AdvSIMD
2417
   instruction ORR (register), in which the field 'size' is also used for
2418
   the base opcode, leaving only the field 'Q' available to encode the
2419
   vector register arrangement specifier '8B' or '16B'.
2420
2421
   This function tries to deduce the qualifier from the value of partially
2422
   constrained field(s).  Given the VALUE of such a field or fields, the
2423
   qualifiers CANDIDATES and the MASK (indicating which bits are valid for
2424
   operand encoding), the function returns the matching qualifier or
2425
   AARCH64_OPND_QLF_NIL if nothing matches.
2426
2427
   N.B. CANDIDATES is a group of possible qualifiers that are valid for
2428
   one operand; it has a maximum of AARCH64_MAX_QLF_SEQ_NUM qualifiers and
2429
   may end with AARCH64_OPND_QLF_NIL.  */
2430
2431
static enum aarch64_opnd_qualifier
2432
get_qualifier_from_partial_encoding (aarch64_insn value,
2433
             const enum aarch64_opnd_qualifier* \
2434
             candidates,
2435
             aarch64_insn mask)
2436
96.0k
{
2437
96.0k
  int i;
2438
96.0k
  DEBUG_TRACE ("enter with value: %d, mask: %d", (int)value, (int)mask);
2439
180k
  for (i = 0; i < AARCH64_MAX_QLF_SEQ_NUM; ++i)
2440
180k
    {
2441
180k
      aarch64_insn standard_value;
2442
180k
      if (candidates[i] == AARCH64_OPND_QLF_NIL)
2443
18.6k
  break;
2444
161k
      standard_value = aarch64_get_qualifier_standard_value (candidates[i]);
2445
161k
      if ((standard_value & mask) == (value & mask))
2446
77.4k
  return candidates[i];
2447
161k
    }
2448
18.6k
  return AARCH64_OPND_QLF_NIL;
2449
96.0k
}
2450
2451
/* Given a list of qualifier sequences, return all possible valid qualifiers
2452
   for operand IDX in QUALIFIERS.
2453
   Assume QUALIFIERS is an array whose length is large enough.  */
2454
2455
static void
2456
get_operand_possible_qualifiers (int idx,
2457
         const aarch64_opnd_qualifier_seq_t *list,
2458
         enum aarch64_opnd_qualifier *qualifiers)
2459
96.0k
{
2460
96.0k
  int i;
2461
319k
  for (i = 0; i < AARCH64_MAX_QLF_SEQ_NUM; ++i)
2462
319k
    if ((qualifiers[i] = list[i][idx]) == AARCH64_OPND_QLF_NIL)
2463
96.0k
      break;
2464
96.0k
}
2465
2466
/* Decode the size Q field for e.g. SHADD.
2467
   We tag one operand with the qualifer according to the code;
2468
   whether the qualifier is valid for this opcode or not, it is the
2469
   duty of the semantic checking.  */
2470
2471
static int
2472
decode_sizeq (aarch64_inst *inst)
2473
224k
{
2474
224k
  int idx;
2475
224k
  enum aarch64_opnd_qualifier qualifier;
2476
224k
  aarch64_insn code;
2477
224k
  aarch64_insn value, mask;
2478
224k
  enum aarch64_field_kind fld_sz;
2479
224k
  enum aarch64_opnd_qualifier candidates[AARCH64_MAX_QLF_SEQ_NUM];
2480
2481
224k
  if (inst->opcode->iclass == asisdlse
2482
224k
     || inst->opcode->iclass == asisdlsep
2483
224k
     || inst->opcode->iclass == asisdlso
2484
224k
     || inst->opcode->iclass == asisdlsop)
2485
50.8k
    fld_sz = FLD_vldst_size;
2486
173k
  else
2487
173k
    fld_sz = FLD_size;
2488
2489
224k
  code = inst->value;
2490
224k
  value = extract_fields (code, inst->opcode->mask, 2, fld_sz, FLD_Q);
2491
  /* Obtain the info that which bits of fields Q and size are actually
2492
     available for operand encoding.  Opcodes like FMAXNM and FMLA have
2493
     size[1] unavailable.  */
2494
224k
  mask = extract_fields (~inst->opcode->mask, 0, 2, fld_sz, FLD_Q);
2495
2496
  /* The index of the operand we are going to tag a qualifier and the qualifer
2497
     itself are reasoned from the value of the size and Q fields and the
2498
     possible valid qualifier lists.  */
2499
224k
  idx = aarch64_select_operand_for_sizeq_field_coding (inst->opcode);
2500
224k
  DEBUG_TRACE ("key idx: %d", idx);
2501
2502
  /* For most related instruciton, size:Q are fully available for operand
2503
     encoding.  */
2504
224k
  if (mask == 0x7)
2505
131k
    {
2506
131k
      inst->operands[idx].qualifier = get_vreg_qualifier_from_value (value);
2507
131k
      if (inst->operands[idx].qualifier == AARCH64_OPND_QLF_ERR)
2508
0
  return 0;
2509
131k
      return 1;
2510
131k
    }
2511
2512
92.2k
  get_operand_possible_qualifiers (idx, inst->opcode->qualifiers_list,
2513
92.2k
           candidates);
2514
#ifdef DEBUG_AARCH64
2515
  if (debug_dump)
2516
    {
2517
      int i;
2518
      for (i = 0; candidates[i] != AARCH64_OPND_QLF_NIL
2519
     && i < AARCH64_MAX_QLF_SEQ_NUM; ++i)
2520
  DEBUG_TRACE ("qualifier %d: %s", i,
2521
         aarch64_get_qualifier_name(candidates[i]));
2522
      DEBUG_TRACE ("%d, %d", (int)value, (int)mask);
2523
    }
2524
#endif /* DEBUG_AARCH64 */
2525
2526
92.2k
  qualifier = get_qualifier_from_partial_encoding (value, candidates, mask);
2527
2528
92.2k
  if (qualifier == AARCH64_OPND_QLF_NIL)
2529
18.6k
    return 0;
2530
2531
73.5k
  inst->operands[idx].qualifier = qualifier;
2532
73.5k
  return 1;
2533
92.2k
}
2534
2535
/* Decode size[0]:Q, i.e. bit 22 and bit 30, for
2536
     e.g. FCVTN<Q> <Vd>.<Tb>, <Vn>.<Ta>.  */
2537
2538
static int
2539
decode_asimd_fcvt (aarch64_inst *inst)
2540
215
{
2541
215
  aarch64_field field = {0, 0};
2542
215
  aarch64_insn value;
2543
215
  enum aarch64_opnd_qualifier qualifier;
2544
2545
215
  gen_sub_field (FLD_size, 0, 1, &field);
2546
215
  value = extract_field_2 (&field, inst->value, 0);
2547
215
  qualifier = value == 0 ? AARCH64_OPND_QLF_V_4S
2548
215
    : AARCH64_OPND_QLF_V_2D;
2549
215
  switch (inst->opcode->op)
2550
215
    {
2551
201
    case OP_FCVTN:
2552
209
    case OP_FCVTN2:
2553
      /* FCVTN<Q> <Vd>.<Tb>, <Vn>.<Ta>.  */
2554
209
      inst->operands[1].qualifier = qualifier;
2555
209
      break;
2556
5
    case OP_FCVTL:
2557
6
    case OP_FCVTL2:
2558
      /* FCVTL<Q> <Vd>.<Ta>, <Vn>.<Tb>.  */
2559
6
      inst->operands[0].qualifier = qualifier;
2560
6
      break;
2561
0
    default:
2562
0
      return 0;
2563
215
    }
2564
2565
215
  return 1;
2566
215
}
2567
2568
/* Decode size[0], i.e. bit 22, for
2569
     e.g. FCVTXN <Vb><d>, <Va><n>.  */
2570
2571
static int
2572
decode_asisd_fcvtxn (aarch64_inst *inst)
2573
31
{
2574
31
  aarch64_field field = {0, 0};
2575
31
  gen_sub_field (FLD_size, 0, 1, &field);
2576
31
  if (!extract_field_2 (&field, inst->value, 0))
2577
29
    return 0;
2578
2
  inst->operands[0].qualifier = AARCH64_OPND_QLF_S_S;
2579
2
  return 1;
2580
31
}
2581
2582
/* Decode the 'opc' field for e.g. FCVT <Dd>, <Sn>.  */
2583
static int
2584
decode_fcvt (aarch64_inst *inst)
2585
22
{
2586
22
  enum aarch64_opnd_qualifier qualifier;
2587
22
  aarch64_insn value;
2588
22
  const aarch64_field field = {15, 2};
2589
2590
  /* opc dstsize */
2591
22
  value = extract_field_2 (&field, inst->value, 0);
2592
22
  switch (value)
2593
22
    {
2594
5
    case 0: qualifier = AARCH64_OPND_QLF_S_S; break;
2595
12
    case 1: qualifier = AARCH64_OPND_QLF_S_D; break;
2596
0
    case 3: qualifier = AARCH64_OPND_QLF_S_H; break;
2597
5
    default: return 0;
2598
22
    }
2599
17
  inst->operands[0].qualifier = qualifier;
2600
2601
17
  return 1;
2602
22
}
2603
2604
/* Do miscellaneous decodings that are not common enough to be driven by
2605
   flags.  */
2606
2607
static int
2608
do_misc_decoding (aarch64_inst *inst)
2609
8.08k
{
2610
8.08k
  unsigned int value;
2611
8.08k
  switch (inst->opcode->op)
2612
8.08k
    {
2613
22
    case OP_FCVT:
2614
22
      return decode_fcvt (inst);
2615
2616
201
    case OP_FCVTN:
2617
209
    case OP_FCVTN2:
2618
214
    case OP_FCVTL:
2619
215
    case OP_FCVTL2:
2620
215
      return decode_asimd_fcvt (inst);
2621
2622
31
    case OP_FCVTXN_S:
2623
31
      return decode_asisd_fcvtxn (inst);
2624
2625
211
    case OP_MOV_P_P:
2626
401
    case OP_MOVS_P_P:
2627
401
      value = extract_field (FLD_SVE_Pn, inst->value, 0);
2628
401
      return (value == extract_field (FLD_SVE_Pm, inst->value, 0)
2629
401
        && value == extract_field (FLD_SVE_Pg4_10, inst->value, 0));
2630
2631
5.84k
    case OP_MOV_Z_P_Z:
2632
5.84k
      return (extract_field (FLD_SVE_Zd, inst->value, 0)
2633
5.84k
        == extract_field (FLD_SVE_Zm_16, inst->value, 0));
2634
2635
17
    case OP_MOV_Z_V:
2636
      /* Index must be zero.  */
2637
17
      value = extract_fields (inst->value, 0, 2, FLD_SVE_tszh, FLD_imm5);
2638
17
      return value > 0 && value <= 16 && value == (value & -value);
2639
2640
134
    case OP_MOV_Z_Z:
2641
134
      return (extract_field (FLD_SVE_Zn, inst->value, 0)
2642
134
        == extract_field (FLD_SVE_Zm_16, inst->value, 0));
2643
2644
417
    case OP_MOV_Z_Zi:
2645
      /* Index must be nonzero.  */
2646
417
      value = extract_fields (inst->value, 0, 2, FLD_SVE_tszh, FLD_imm5);
2647
417
      return value > 0 && value != (value & -value);
2648
2649
66
    case OP_MOVM_P_P_P:
2650
66
      return (extract_field (FLD_SVE_Pd, inst->value, 0)
2651
66
        == extract_field (FLD_SVE_Pm, inst->value, 0));
2652
2653
154
    case OP_MOVZS_P_P_P:
2654
415
    case OP_MOVZ_P_P_P:
2655
415
      return (extract_field (FLD_SVE_Pn, inst->value, 0)
2656
415
        == extract_field (FLD_SVE_Pm, inst->value, 0));
2657
2658
98
    case OP_NOTS_P_P_P_Z:
2659
316
    case OP_NOT_P_P_P_Z:
2660
316
      return (extract_field (FLD_SVE_Pm, inst->value, 0)
2661
316
        == extract_field (FLD_SVE_Pg4_10, inst->value, 0));
2662
2663
211
    default:
2664
211
      return 0;
2665
8.08k
    }
2666
8.08k
}
2667
2668
/* Opcodes that have fields shared by multiple operands are usually flagged
2669
   with flags.  In this function, we detect such flags, decode the related
2670
   field(s) and store the information in one of the related operands.  The
2671
   'one' operand is not any operand but one of the operands that can
2672
   accommadate all the information that has been decoded.  */
2673
2674
static int
2675
do_special_decoding (aarch64_inst *inst)
2676
2.45M
{
2677
2.45M
  int idx;
2678
2.45M
  aarch64_insn value;
2679
  /* Condition for truly conditional executed instructions, e.g. b.cond.  */
2680
2.45M
  if (inst->opcode->flags & F_COND)
2681
38.4k
    {
2682
38.4k
      value = extract_field (FLD_cond2, inst->value, 0);
2683
38.4k
      inst->cond = get_cond_from_value (value);
2684
38.4k
    }
2685
  /* 'sf' field.  */
2686
2.45M
  if (inst->opcode->flags & F_SF)
2687
1.86M
    {
2688
1.86M
      idx = select_operand_for_sf_field_coding (inst->opcode);
2689
1.86M
      value = extract_field (FLD_sf, inst->value, 0);
2690
1.86M
      inst->operands[idx].qualifier = get_greg_qualifier_from_value (value);
2691
1.86M
      if (inst->operands[idx].qualifier == AARCH64_OPND_QLF_ERR)
2692
0
  return 0;
2693
1.86M
      if ((inst->opcode->flags & F_N)
2694
1.86M
    && extract_field (FLD_N, inst->value, 0) != value)
2695
60.0k
  return 0;
2696
1.86M
    }
2697
  /* 'sf' field.  */
2698
2.39M
  if (inst->opcode->flags & F_LSE_SZ)
2699
13.1k
    {
2700
13.1k
      idx = select_operand_for_sf_field_coding (inst->opcode);
2701
13.1k
      value = extract_field (FLD_lse_sz, inst->value, 0);
2702
13.1k
      inst->operands[idx].qualifier = get_greg_qualifier_from_value (value);
2703
13.1k
      if (inst->operands[idx].qualifier == AARCH64_OPND_QLF_ERR)
2704
0
  return 0;
2705
13.1k
    }
2706
  /* rcpc3 'size' field.  */
2707
2.39M
  if (inst->opcode->flags & F_RCPC3_SIZE)
2708
15.1k
    {
2709
15.1k
      value = extract_field (FLD_rcpc3_size, inst->value, 0);
2710
15.1k
      for (int i = 0;
2711
32.3k
     aarch64_operands[inst->operands[i].type].op_class != AARCH64_OPND_CLASS_ADDRESS;
2712
17.1k
     i++)
2713
20.3k
  {
2714
20.3k
    if (aarch64_operands[inst->operands[i].type].op_class
2715
20.3k
        == AARCH64_OPND_CLASS_INT_REG)
2716
10.4k
      {
2717
10.4k
        inst->operands[i].qualifier = get_greg_qualifier_from_value (value & 1);
2718
10.4k
        if (inst->operands[i].qualifier == AARCH64_OPND_QLF_ERR)
2719
0
    return 0;
2720
10.4k
      }
2721
9.97k
    else if (aarch64_operands[inst->operands[i].type].op_class
2722
9.97k
        == AARCH64_OPND_CLASS_FP_REG)
2723
9.97k
      {
2724
9.97k
        value += (extract_field (FLD_opc1, inst->value, 0) << 2);
2725
9.97k
        inst->operands[i].qualifier = get_sreg_qualifier_from_value (value);
2726
9.97k
        if (inst->operands[i].qualifier == AARCH64_OPND_QLF_ERR)
2727
3.24k
    return 0;
2728
9.97k
      }
2729
20.3k
  }
2730
15.1k
    }
2731
2732
  /* size:Q fields.  */
2733
2.39M
  if (inst->opcode->flags & F_SIZEQ)
2734
224k
    return decode_sizeq (inst);
2735
2736
2.16M
  if (inst->opcode->flags & F_FPTYPE)
2737
53.7k
    {
2738
53.7k
      idx = select_operand_for_fptype_field_coding (inst->opcode);
2739
53.7k
      value = extract_field (FLD_type, inst->value, 0);
2740
53.7k
      switch (value)
2741
53.7k
  {
2742
15.2k
  case 0: inst->operands[idx].qualifier = AARCH64_OPND_QLF_S_S; break;
2743
7.12k
  case 1: inst->operands[idx].qualifier = AARCH64_OPND_QLF_S_D; break;
2744
18.4k
  case 3: inst->operands[idx].qualifier = AARCH64_OPND_QLF_S_H; break;
2745
12.9k
  default: return 0;
2746
53.7k
  }
2747
53.7k
    }
2748
2749
2.15M
  if (inst->opcode->flags & F_SSIZE)
2750
13.6k
    {
2751
      /* N.B. some opcodes like FCMGT <V><d>, <V><n>, #0 have the size[1] as part
2752
   of the base opcode.  */
2753
13.6k
      aarch64_insn mask;
2754
13.6k
      enum aarch64_opnd_qualifier candidates[AARCH64_MAX_QLF_SEQ_NUM];
2755
13.6k
      idx = select_operand_for_scalar_size_field_coding (inst->opcode);
2756
13.6k
      value = extract_field (FLD_size, inst->value, inst->opcode->mask);
2757
13.6k
      mask = extract_field (FLD_size, ~inst->opcode->mask, 0);
2758
      /* For most related instruciton, the 'size' field is fully available for
2759
   operand encoding.  */
2760
13.6k
      if (mask == 0x3)
2761
9.73k
  {
2762
9.73k
    inst->operands[idx].qualifier = get_sreg_qualifier_from_value (value);
2763
9.73k
    if (inst->operands[idx].qualifier == AARCH64_OPND_QLF_ERR)
2764
0
      return 0;
2765
9.73k
  }
2766
3.86k
      else
2767
3.86k
  {
2768
3.86k
    get_operand_possible_qualifiers (idx, inst->opcode->qualifiers_list,
2769
3.86k
             candidates);
2770
3.86k
    inst->operands[idx].qualifier
2771
3.86k
      = get_qualifier_from_partial_encoding (value, candidates, mask);
2772
3.86k
  }
2773
13.6k
    }
2774
2775
2.15M
  if (inst->opcode->flags & F_T)
2776
7.21k
    {
2777
      /* Num of consecutive '0's on the right side of imm5<3:0>.  */
2778
7.21k
      int num = 0;
2779
7.21k
      unsigned val, Q;
2780
7.21k
      assert (aarch64_get_operand_class (inst->opcode->operands[0])
2781
7.21k
        == AARCH64_OPND_CLASS_SIMD_REG);
2782
      /* imm5<3:0>  q <t>
2783
   0000   x reserved
2784
   xxx1   0 8b
2785
   xxx1   1 16b
2786
   xx10   0 4h
2787
   xx10   1 8h
2788
   x100   0 2s
2789
   x100   1 4s
2790
   1000   0 reserved
2791
   1000   1 2d  */
2792
7.21k
      val = extract_field (FLD_imm5, inst->value, 0);
2793
16.8k
      while ((val & 0x1) == 0 && ++num <= 3)
2794
9.63k
  val >>= 1;
2795
7.21k
      if (num > 3)
2796
1.36k
  return 0;
2797
5.85k
      Q = (unsigned) extract_field (FLD_Q, inst->value, inst->opcode->mask);
2798
5.85k
      inst->operands[0].qualifier =
2799
5.85k
  get_vreg_qualifier_from_value ((num << 1) | Q);
2800
5.85k
      if (inst->operands[0].qualifier == AARCH64_OPND_QLF_ERR)
2801
0
  return 0;
2802
2803
5.85k
    }
2804
2805
2.15M
  if ((inst->opcode->flags & F_OPD_SIZE) && inst->opcode->iclass == sve2_urqvs)
2806
628
    {
2807
628
      unsigned size;
2808
628
      size = (unsigned) extract_field (FLD_size, inst->value,
2809
628
               inst->opcode->mask);
2810
628
      inst->operands[0].qualifier
2811
628
  = get_vreg_qualifier_from_value (1 + (size << 1));
2812
628
      if (inst->operands[0].qualifier == AARCH64_OPND_QLF_ERR)
2813
0
  return 0;
2814
628
      inst->operands[2].qualifier = get_sreg_qualifier_from_value (size);
2815
628
      if (inst->operands[2].qualifier == AARCH64_OPND_QLF_ERR)
2816
0
  return 0;
2817
628
    }
2818
2819
2.15M
  if (inst->opcode->flags & F_GPRSIZE_IN_Q)
2820
196k
    {
2821
      /* Use Rt to encode in the case of e.g.
2822
   STXP <Ws>, <Xt1>, <Xt2>, [<Xn|SP>{,#0}].  */
2823
196k
      idx = aarch64_operand_index (inst->opcode->operands, AARCH64_OPND_Rt);
2824
196k
      if (idx == -1)
2825
2.78k
  {
2826
    /* Otherwise use the result operand, which has to be a integer
2827
       register.  */
2828
2.78k
    assert (aarch64_get_operand_class (inst->opcode->operands[0])
2829
2.78k
      == AARCH64_OPND_CLASS_INT_REG);
2830
2.78k
    idx = 0;
2831
2.78k
  }
2832
196k
      assert (idx == 0 || idx == 1);
2833
196k
      value = extract_field (FLD_Q, inst->value, 0);
2834
196k
      inst->operands[idx].qualifier = get_greg_qualifier_from_value (value);
2835
196k
      if (inst->operands[idx].qualifier == AARCH64_OPND_QLF_ERR)
2836
0
  return 0;
2837
196k
    }
2838
2839
2.15M
  if (inst->opcode->flags & F_LDS_SIZE)
2840
28.8k
    {
2841
28.8k
      aarch64_field field = {0, 0};
2842
28.8k
      assert (aarch64_get_operand_class (inst->opcode->operands[0])
2843
28.8k
        == AARCH64_OPND_CLASS_INT_REG);
2844
28.8k
      gen_sub_field (FLD_opc, 0, 1, &field);
2845
28.8k
      value = extract_field_2 (&field, inst->value, 0);
2846
28.8k
      inst->operands[0].qualifier
2847
28.8k
  = value ? AARCH64_OPND_QLF_W : AARCH64_OPND_QLF_X;
2848
28.8k
    }
2849
2850
  /* Miscellaneous decoding; done as the last step.  */
2851
2.15M
  if (inst->opcode->flags & F_MISC)
2852
8.08k
    return do_misc_decoding (inst);
2853
2854
2.14M
  return 1;
2855
2.15M
}
2856
2857
/* Converters converting a real opcode instruction to its alias form.  */
2858
2859
/* ROR <Wd>, <Ws>, #<shift>
2860
     is equivalent to:
2861
   EXTR <Wd>, <Ws>, <Ws>, #<shift>.  */
2862
static int
2863
convert_extr_to_ror (aarch64_inst *inst)
2864
3.72k
{
2865
3.72k
  if (inst->operands[1].reg.regno == inst->operands[2].reg.regno)
2866
87
    {
2867
87
      copy_operand_info (inst, 2, 3);
2868
87
      inst->operands[3].type = AARCH64_OPND_NIL;
2869
87
      return 1;
2870
87
    }
2871
3.63k
  return 0;
2872
3.72k
}
2873
2874
/* UXTL<Q> <Vd>.<Ta>, <Vn>.<Tb>
2875
     is equivalent to:
2876
   USHLL<Q> <Vd>.<Ta>, <Vn>.<Tb>, #0.  */
2877
static int
2878
convert_shll_to_xtl (aarch64_inst *inst)
2879
454
{
2880
454
  if (inst->operands[2].imm.value == 0)
2881
260
    {
2882
260
      inst->operands[2].type = AARCH64_OPND_NIL;
2883
260
      return 1;
2884
260
    }
2885
194
  return 0;
2886
454
}
2887
2888
/* Convert
2889
     UBFM <Xd>, <Xn>, #<shift>, #63.
2890
   to
2891
     LSR <Xd>, <Xn>, #<shift>.  */
2892
static int
2893
convert_bfm_to_sr (aarch64_inst *inst)
2894
24.5k
{
2895
24.5k
  int64_t imms, val;
2896
2897
24.5k
  imms = inst->operands[3].imm.value;
2898
24.5k
  val = inst->operands[2].qualifier == AARCH64_OPND_QLF_imm_0_31 ? 31 : 63;
2899
24.5k
  if (imms == val)
2900
654
    {
2901
654
      inst->operands[3].type = AARCH64_OPND_NIL;
2902
654
      return 1;
2903
654
    }
2904
2905
23.8k
  return 0;
2906
24.5k
}
2907
2908
/* Convert MOV to ORR.  */
2909
static int
2910
convert_orr_to_mov (aarch64_inst *inst)
2911
224
{
2912
  /* MOV <Vd>.<T>, <Vn>.<T>
2913
     is equivalent to:
2914
     ORR <Vd>.<T>, <Vn>.<T>, <Vn>.<T>.  */
2915
224
  if (inst->operands[1].reg.regno == inst->operands[2].reg.regno)
2916
47
    {
2917
47
      inst->operands[2].type = AARCH64_OPND_NIL;
2918
47
      return 1;
2919
47
    }
2920
177
  return 0;
2921
224
}
2922
2923
/* When <imms> >= <immr>, the instruction written:
2924
     SBFX <Xd>, <Xn>, #<lsb>, #<width>
2925
   is equivalent to:
2926
     SBFM <Xd>, <Xn>, #<lsb>, #(<lsb>+<width>-1).  */
2927
2928
static int
2929
convert_bfm_to_bfx (aarch64_inst *inst)
2930
31.3k
{
2931
31.3k
  int64_t immr, imms;
2932
2933
31.3k
  immr = inst->operands[2].imm.value;
2934
31.3k
  imms = inst->operands[3].imm.value;
2935
31.3k
  if (imms >= immr)
2936
14.8k
    {
2937
14.8k
      int64_t lsb = immr;
2938
14.8k
      inst->operands[2].imm.value = lsb;
2939
14.8k
      inst->operands[3].imm.value = imms + 1 - lsb;
2940
      /* The two opcodes have different qualifiers for
2941
   the immediate operands; reset to help the checking.  */
2942
14.8k
      reset_operand_qualifier (inst, 2);
2943
14.8k
      reset_operand_qualifier (inst, 3);
2944
14.8k
      return 1;
2945
14.8k
    }
2946
2947
16.4k
  return 0;
2948
31.3k
}
2949
2950
/* When <imms> < <immr>, the instruction written:
2951
     SBFIZ <Xd>, <Xn>, #<lsb>, #<width>
2952
   is equivalent to:
2953
     SBFM <Xd>, <Xn>, #((64-<lsb>)&0x3f), #(<width>-1).  */
2954
2955
static int
2956
convert_bfm_to_bfi (aarch64_inst *inst)
2957
16.4k
{
2958
16.4k
  int64_t immr, imms, val;
2959
2960
16.4k
  immr = inst->operands[2].imm.value;
2961
16.4k
  imms = inst->operands[3].imm.value;
2962
16.4k
  val = inst->operands[2].qualifier == AARCH64_OPND_QLF_imm_0_31 ? 32 : 64;
2963
16.4k
  if (imms < immr)
2964
16.4k
    {
2965
16.4k
      inst->operands[2].imm.value = (val - immr) & (val - 1);
2966
16.4k
      inst->operands[3].imm.value = imms + 1;
2967
      /* The two opcodes have different qualifiers for
2968
   the immediate operands; reset to help the checking.  */
2969
16.4k
      reset_operand_qualifier (inst, 2);
2970
16.4k
      reset_operand_qualifier (inst, 3);
2971
16.4k
      return 1;
2972
16.4k
    }
2973
2974
0
  return 0;
2975
16.4k
}
2976
2977
/* The instruction written:
2978
     BFC <Xd>, #<lsb>, #<width>
2979
   is equivalent to:
2980
     BFM <Xd>, XZR, #((64-<lsb>)&0x3f), #(<width>-1).  */
2981
2982
static int
2983
convert_bfm_to_bfc (aarch64_inst *inst)
2984
378
{
2985
378
  int64_t immr, imms, val;
2986
2987
  /* Should have been assured by the base opcode value.  */
2988
378
  assert (inst->operands[1].reg.regno == 0x1f);
2989
2990
378
  immr = inst->operands[2].imm.value;
2991
378
  imms = inst->operands[3].imm.value;
2992
378
  val = inst->operands[2].qualifier == AARCH64_OPND_QLF_imm_0_31 ? 32 : 64;
2993
378
  if (imms < immr)
2994
123
    {
2995
      /* Drop XZR from the second operand.  */
2996
123
      copy_operand_info (inst, 1, 2);
2997
123
      copy_operand_info (inst, 2, 3);
2998
123
      inst->operands[3].type = AARCH64_OPND_NIL;
2999
3000
      /* Recalculate the immediates.  */
3001
123
      inst->operands[1].imm.value = (val - immr) & (val - 1);
3002
123
      inst->operands[2].imm.value = imms + 1;
3003
3004
      /* The two opcodes have different qualifiers for the operands; reset to
3005
   help the checking.  */
3006
123
      reset_operand_qualifier (inst, 1);
3007
123
      reset_operand_qualifier (inst, 2);
3008
123
      reset_operand_qualifier (inst, 3);
3009
3010
123
      return 1;
3011
123
    }
3012
3013
255
  return 0;
3014
378
}
3015
3016
/* The instruction written:
3017
     LSL <Xd>, <Xn>, #<shift>
3018
   is equivalent to:
3019
     UBFM <Xd>, <Xn>, #((64-<shift>)&0x3f), #(63-<shift>).  */
3020
3021
static int
3022
convert_ubfm_to_lsl (aarch64_inst *inst)
3023
8.18k
{
3024
8.18k
  int64_t immr = inst->operands[2].imm.value;
3025
8.18k
  int64_t imms = inst->operands[3].imm.value;
3026
8.18k
  int64_t val
3027
8.18k
    = inst->operands[2].qualifier == AARCH64_OPND_QLF_imm_0_31 ? 31 : 63;
3028
3029
8.18k
  if ((immr == 0 && imms == val) || immr == imms + 1)
3030
437
    {
3031
437
      inst->operands[3].type = AARCH64_OPND_NIL;
3032
437
      inst->operands[2].imm.value = val - imms;
3033
437
      return 1;
3034
437
    }
3035
3036
7.74k
  return 0;
3037
8.18k
}
3038
3039
/* CINC <Wd>, <Wn>, <cond>
3040
     is equivalent to:
3041
   CSINC <Wd>, <Wn>, <Wn>, invert(<cond>)
3042
     where <cond> is not AL or NV.  */
3043
3044
static int
3045
convert_from_csel (aarch64_inst *inst)
3046
3.92k
{
3047
3.92k
  if (inst->operands[1].reg.regno == inst->operands[2].reg.regno
3048
3.92k
      && (inst->operands[3].cond->value & 0xe) != 0xe)
3049
123
    {
3050
123
      copy_operand_info (inst, 2, 3);
3051
123
      inst->operands[2].cond = get_inverted_cond (inst->operands[3].cond);
3052
123
      inst->operands[3].type = AARCH64_OPND_NIL;
3053
123
      return 1;
3054
123
    }
3055
3.79k
  return 0;
3056
3.92k
}
3057
3058
/* CSET <Wd>, <cond>
3059
     is equivalent to:
3060
   CSINC <Wd>, WZR, WZR, invert(<cond>)
3061
     where <cond> is not AL or NV.  */
3062
3063
static int
3064
convert_csinc_to_cset (aarch64_inst *inst)
3065
752
{
3066
752
  if (inst->operands[1].reg.regno == 0x1f
3067
752
      && inst->operands[2].reg.regno == 0x1f
3068
752
      && (inst->operands[3].cond->value & 0xe) != 0xe)
3069
679
    {
3070
679
      copy_operand_info (inst, 1, 3);
3071
679
      inst->operands[1].cond = get_inverted_cond (inst->operands[3].cond);
3072
679
      inst->operands[3].type = AARCH64_OPND_NIL;
3073
679
      inst->operands[2].type = AARCH64_OPND_NIL;
3074
679
      return 1;
3075
679
    }
3076
73
  return 0;
3077
752
}
3078
3079
/* MOV <Wd>, #<imm>
3080
     is equivalent to:
3081
   MOVZ <Wd>, #<imm16_5>, LSL #<shift>.
3082
3083
   A disassembler may output ORR, MOVZ and MOVN as a MOV mnemonic, except when
3084
   ORR has an immediate that could be generated by a MOVZ or MOVN instruction,
3085
   or where a MOVN has an immediate that could be encoded by MOVZ, or where
3086
   MOVZ/MOVN #0 have a shift amount other than LSL #0, in which case the
3087
   machine-instruction mnemonic must be used.  */
3088
3089
static int
3090
convert_movewide_to_mov (aarch64_inst *inst)
3091
53.6k
{
3092
53.6k
  uint64_t value = inst->operands[1].imm.value;
3093
  /* MOVZ/MOVN #0 have a shift amount other than LSL #0.  */
3094
53.6k
  if (value == 0 && inst->operands[1].shifter.amount != 0)
3095
25
    return 0;
3096
53.5k
  inst->operands[1].type = AARCH64_OPND_IMM_MOV;
3097
53.5k
  inst->operands[1].shifter.kind = AARCH64_MOD_NONE;
3098
53.5k
  value <<= inst->operands[1].shifter.amount;
3099
  /* As an alias convertor, it has to be clear that the INST->OPCODE
3100
     is the opcode of the real instruction.  */
3101
53.5k
  if (inst->opcode->op == OP_MOVN)
3102
23.5k
    {
3103
23.5k
      int is32 = inst->operands[0].qualifier == AARCH64_OPND_QLF_W;
3104
23.5k
      value = ~value;
3105
      /* A MOVN has an immediate that could be encoded by MOVZ.  */
3106
23.5k
      if (aarch64_wide_constant_p (value, is32, NULL))
3107
27
  return 0;
3108
23.5k
    }
3109
53.5k
  inst->operands[1].imm.value = value;
3110
53.5k
  inst->operands[1].shifter.amount = 0;
3111
53.5k
  return 1;
3112
53.5k
}
3113
3114
/* MOV <Wd>, #<imm>
3115
     is equivalent to:
3116
   ORR <Wd>, WZR, #<imm>.
3117
3118
   A disassembler may output ORR, MOVZ and MOVN as a MOV mnemonic, except when
3119
   ORR has an immediate that could be generated by a MOVZ or MOVN instruction,
3120
   or where a MOVN has an immediate that could be encoded by MOVZ, or where
3121
   MOVZ/MOVN #0 have a shift amount other than LSL #0, in which case the
3122
   machine-instruction mnemonic must be used.  */
3123
3124
static int
3125
convert_movebitmask_to_mov (aarch64_inst *inst)
3126
568
{
3127
568
  int is32;
3128
568
  uint64_t value;
3129
3130
  /* Should have been assured by the base opcode value.  */
3131
568
  assert (inst->operands[1].reg.regno == 0x1f);
3132
568
  copy_operand_info (inst, 1, 2);
3133
568
  is32 = inst->operands[0].qualifier == AARCH64_OPND_QLF_W;
3134
568
  inst->operands[1].type = AARCH64_OPND_IMM_MOV;
3135
568
  value = inst->operands[1].imm.value;
3136
  /* ORR has an immediate that could be generated by a MOVZ or MOVN
3137
     instruction.  */
3138
568
  if (inst->operands[0].reg.regno != 0x1f
3139
568
      && (aarch64_wide_constant_p (value, is32, NULL)
3140
505
    || aarch64_wide_constant_p (~value, is32, NULL)))
3141
231
    return 0;
3142
3143
337
  inst->operands[2].type = AARCH64_OPND_NIL;
3144
337
  return 1;
3145
568
}
3146
3147
/* Some alias opcodes are disassembled by being converted from their real-form.
3148
   N.B. INST->OPCODE is the real opcode rather than the alias.  */
3149
3150
static int
3151
convert_to_alias (aarch64_inst *inst, const aarch64_opcode *alias)
3152
144k
{
3153
144k
  switch (alias->op)
3154
144k
    {
3155
16.0k
    case OP_ASR_IMM:
3156
24.5k
    case OP_LSR_IMM:
3157
24.5k
      return convert_bfm_to_sr (inst);
3158
8.18k
    case OP_LSL_IMM:
3159
8.18k
      return convert_ubfm_to_lsl (inst);
3160
1.53k
    case OP_CINC:
3161
2.97k
    case OP_CINV:
3162
3.92k
    case OP_CNEG:
3163
3.92k
      return convert_from_csel (inst);
3164
609
    case OP_CSET:
3165
752
    case OP_CSETM:
3166
752
      return convert_csinc_to_cset (inst);
3167
7.74k
    case OP_UBFX:
3168
15.6k
    case OP_BFXIL:
3169
31.3k
    case OP_SBFX:
3170
31.3k
      return convert_bfm_to_bfx (inst);
3171
10.4k
    case OP_SBFIZ:
3172
13.4k
    case OP_BFI:
3173
16.4k
    case OP_UBFIZ:
3174
16.4k
      return convert_bfm_to_bfi (inst);
3175
378
    case OP_BFC:
3176
378
      return convert_bfm_to_bfc (inst);
3177
224
    case OP_MOV_V:
3178
224
      return convert_orr_to_mov (inst);
3179
30.0k
    case OP_MOV_IMM_WIDE:
3180
53.6k
    case OP_MOV_IMM_WIDEN:
3181
53.6k
      return convert_movewide_to_mov (inst);
3182
568
    case OP_MOV_IMM_LOG:
3183
568
      return convert_movebitmask_to_mov (inst);
3184
3.72k
    case OP_ROR_IMM:
3185
3.72k
      return convert_extr_to_ror (inst);
3186
42
    case OP_SXTL:
3187
68
    case OP_SXTL2:
3188
281
    case OP_UXTL:
3189
454
    case OP_UXTL2:
3190
454
      return convert_shll_to_xtl (inst);
3191
0
    default:
3192
0
      return 0;
3193
144k
    }
3194
144k
}
3195
3196
static bool
3197
aarch64_opcode_decode (const aarch64_opcode *, const aarch64_insn,
3198
           aarch64_inst *, int, aarch64_operand_error *errors);
3199
3200
/* Given the instruction information in *INST, check if the instruction has
3201
   any alias form that can be used to represent *INST.  If the answer is yes,
3202
   update *INST to be in the form of the determined alias.  */
3203
3204
/* In the opcode description table, the following flags are used in opcode
3205
   entries to help establish the relations between the real and alias opcodes:
3206
3207
  F_ALIAS:  opcode is an alias
3208
  F_HAS_ALIAS:  opcode has alias(es)
3209
  F_P1
3210
  F_P2
3211
  F_P3:   Disassembly preference priority 1-3 (the larger the
3212
      higher).  If nothing is specified, it is the priority
3213
      0 by default, i.e. the lowest priority.
3214
3215
   Although the relation between the machine and the alias instructions are not
3216
   explicitly described, it can be easily determined from the base opcode
3217
   values, masks and the flags F_ALIAS and F_HAS_ALIAS in their opcode
3218
   description entries:
3219
3220
   The mask of an alias opcode must be equal to or a super-set (i.e. more
3221
   constrained) of that of the aliased opcode; so is the base opcode value.
3222
3223
   if (opcode_has_alias (real) && alias_opcode_p (opcode)
3224
       && (opcode->mask & real->mask) == real->mask
3225
       && (real->mask & opcode->opcode) == (real->mask & real->opcode))
3226
   then OPCODE is an alias of, and only of, the REAL instruction
3227
3228
   The alias relationship is forced flat-structured to keep related algorithm
3229
   simple; an opcode entry cannot be flagged with both F_ALIAS and F_HAS_ALIAS.
3230
3231
   During the disassembling, the decoding decision tree (in
3232
   opcodes/aarch64-dis-2.c) always returns an machine instruction opcode entry;
3233
   if the decoding of such a machine instruction succeeds (and -Mno-aliases is
3234
   not specified), the disassembler will check whether there is any alias
3235
   instruction exists for this real instruction.  If there is, the disassembler
3236
   will try to disassemble the 32-bit binary again using the alias's rule, or
3237
   try to convert the IR to the form of the alias.  In the case of the multiple
3238
   aliases, the aliases are tried one by one from the highest priority
3239
   (currently the flag F_P3) to the lowest priority (no priority flag), and the
3240
   first succeeds first adopted.
3241
3242
   You may ask why there is a need for the conversion of IR from one form to
3243
   another in handling certain aliases.  This is because on one hand it avoids
3244
   adding more operand code to handle unusual encoding/decoding; on other
3245
   hand, during the disassembling, the conversion is an effective approach to
3246
   check the condition of an alias (as an alias may be adopted only if certain
3247
   conditions are met).
3248
3249
   In order to speed up the alias opcode lookup, aarch64-gen has preprocessed
3250
   aarch64_opcode_table and generated aarch64_find_alias_opcode and
3251
   aarch64_find_next_alias_opcode (in opcodes/aarch64-dis-2.c) to help.  */
3252
3253
static void
3254
determine_disassembling_preference (struct aarch64_inst *inst,
3255
            aarch64_operand_error *errors)
3256
4.90M
{
3257
4.90M
  const aarch64_opcode *opcode;
3258
4.90M
  const aarch64_opcode *alias;
3259
3260
4.90M
  opcode = inst->opcode;
3261
3262
  /* This opcode does not have an alias, so use itself.  */
3263
4.90M
  if (!opcode_has_alias (opcode))
3264
4.33M
    return;
3265
3266
577k
  alias = aarch64_find_alias_opcode (opcode);
3267
577k
  assert (alias);
3268
3269
#ifdef DEBUG_AARCH64
3270
  if (debug_dump)
3271
    {
3272
      const aarch64_opcode *tmp = alias;
3273
      printf ("####   LIST    orderd: ");
3274
      while (tmp)
3275
  {
3276
    printf ("%s, ", tmp->name);
3277
    tmp = aarch64_find_next_alias_opcode (tmp);
3278
  }
3279
      printf ("\n");
3280
    }
3281
#endif /* DEBUG_AARCH64 */
3282
3283
1.20M
  for (; alias; alias = aarch64_find_next_alias_opcode (alias))
3284
1.20M
    {
3285
1.20M
      DEBUG_TRACE ("try %s", alias->name);
3286
1.20M
      assert (alias_opcode_p (alias) || opcode_has_alias (opcode));
3287
3288
      /* An alias can be a pseudo opcode which will never be used in the
3289
   disassembly, e.g. BIC logical immediate is such a pseudo opcode
3290
   aliasing AND.  */
3291
1.20M
      if (pseudo_opcode_p (alias))
3292
99.6k
  {
3293
99.6k
    DEBUG_TRACE ("skip pseudo %s", alias->name);
3294
99.6k
    continue;
3295
99.6k
  }
3296
3297
1.11M
      if ((inst->value & alias->mask) != alias->opcode)
3298
460k
  {
3299
460k
    DEBUG_TRACE ("skip %s as base opcode not match", alias->name);
3300
460k
    continue;
3301
460k
  }
3302
3303
649k
      if (!AARCH64_CPU_HAS_ALL_FEATURES (arch_variant, *alias->avariant))
3304
42
  {
3305
42
    DEBUG_TRACE ("skip %s: we're missing features", alias->name);
3306
42
    continue;
3307
42
  }
3308
3309
      /* No need to do any complicated transformation on operands, if the alias
3310
   opcode does not have any operand.  */
3311
649k
      if (aarch64_num_of_operands (alias) == 0 && alias->opcode == inst->value)
3312
115
  {
3313
115
    DEBUG_TRACE ("succeed with 0-operand opcode %s", alias->name);
3314
115
    aarch64_replace_opcode (inst, alias);
3315
115
    return;
3316
115
  }
3317
649k
      if (alias->flags & F_CONV)
3318
144k
  {
3319
144k
    aarch64_inst copy;
3320
144k
    memcpy (&copy, inst, sizeof (aarch64_inst));
3321
    /* ALIAS is the preference as long as the instruction can be
3322
       successfully converted to the form of ALIAS.  */
3323
144k
    if (convert_to_alias (&copy, alias) == 1)
3324
87.6k
      {
3325
87.6k
        aarch64_replace_opcode (&copy, alias);
3326
87.6k
        if (aarch64_match_operands_constraint (&copy, NULL) != 1)
3327
0
    {
3328
0
      DEBUG_TRACE ("FAILED with alias %s ", alias->name);
3329
0
    }
3330
87.6k
        else
3331
87.6k
    {
3332
87.6k
      DEBUG_TRACE ("succeed with %s via conversion", alias->name);
3333
87.6k
      memcpy (inst, &copy, sizeof (aarch64_inst));
3334
87.6k
    }
3335
87.6k
        return;
3336
87.6k
      }
3337
144k
  }
3338
505k
      else
3339
505k
  {
3340
    /* Directly decode the alias opcode.  */
3341
505k
    aarch64_inst temp;
3342
505k
    memset (&temp, '\0', sizeof (aarch64_inst));
3343
505k
    if (aarch64_opcode_decode (alias, inst->value, &temp, 1, errors) == 1)
3344
489k
      {
3345
489k
        DEBUG_TRACE ("succeed with %s via direct decoding", alias->name);
3346
489k
        memcpy (inst, &temp, sizeof (aarch64_inst));
3347
489k
        return;
3348
489k
      }
3349
505k
  }
3350
649k
    }
3351
577k
}
3352
3353
/* Some instructions (including all SVE ones) use the instruction class
3354
   to describe how a qualifiers_list index is represented in the instruction
3355
   encoding.  If INST is such an instruction, decode the appropriate fields
3356
   and fill in the operand qualifiers accordingly.  Return true if no
3357
   problems are found.  */
3358
3359
static bool
3360
aarch64_decode_variant_using_iclass (aarch64_inst *inst)
3361
6.07M
{
3362
6.07M
  int i, variant;
3363
3364
6.07M
  variant = 0;
3365
6.07M
  switch (inst->opcode->iclass)
3366
6.07M
    {
3367
13.0k
    case sme_mov:
3368
13.0k
      variant = extract_fields (inst->value, 0, 2, FLD_SME_Q, FLD_SME_size_22);
3369
13.0k
      if (variant >= 4 && variant < 7)
3370
2.63k
  return false;
3371
10.4k
      if (variant == 7)
3372
426
  variant = 4;
3373
10.4k
      break;
3374
3375
1.19k
    case sme_psel:
3376
1.19k
      i = extract_fields (inst->value, 0, 2, FLD_SME_tszh, FLD_SME_tszl);
3377
1.19k
      if (i == 0)
3378
166
  return false;
3379
1.78k
      while ((i & 1) == 0)
3380
759
  {
3381
759
    i >>= 1;
3382
759
    variant += 1;
3383
759
  }
3384
1.02k
      break;
3385
3386
257
    case sme_shift:
3387
257
      i = extract_field (FLD_SVE_tszh, inst->value, 0);
3388
257
      goto sve_shift;
3389
3390
279
    case sme_size_12_bhs:
3391
279
      variant = extract_field (FLD_SME_size_12, inst->value, 0);
3392
279
      if (variant >= 3)
3393
9
  return false;
3394
270
      break;
3395
3396
270
    case sme_size_12_hs:
3397
45
      variant = extract_field (FLD_SME_size_12, inst->value, 0);
3398
45
      if (variant != 1 && variant != 2)
3399
29
  return false;
3400
16
      variant -= 1;
3401
16
      break;
3402
3403
2.20k
    case sme_size_22:
3404
2.20k
      variant = extract_field (FLD_SME_size_22, inst->value, 0);
3405
2.20k
      break;
3406
3407
635
    case sme_size_22_hsd:
3408
635
      variant = extract_field (FLD_SME_size_22, inst->value, 0);
3409
635
      if (variant < 1)
3410
157
  return false;
3411
478
      variant -= 1;
3412
478
      break;
3413
3414
55
    case sme_sz_23:
3415
55
      variant = extract_field (FLD_SME_sz_23, inst->value, 0);
3416
55
      break;
3417
3418
15.2k
    case sve_cpy:
3419
15.2k
      variant = extract_fields (inst->value, 0, 2, FLD_size, FLD_SVE_M_14);
3420
15.2k
      break;
3421
3422
875
    case sve_index:
3423
875
      i = extract_fields (inst->value, 0, 2, FLD_SVE_tszh, FLD_imm5);
3424
875
      if ((i & 31) == 0)
3425
41
  return false;
3426
1.16k
      while ((i & 1) == 0)
3427
326
  {
3428
326
    i >>= 1;
3429
326
    variant += 1;
3430
326
  }
3431
834
      break;
3432
3433
72
    case sve_index1:
3434
72
      i = extract_fields (inst->value, 0, 2, FLD_SVE_tsz, FLD_SVE_i2h);
3435
72
      if ((i & 15) == 0)
3436
1
  return false;
3437
100
      while ((i & 1) == 0)
3438
29
  {
3439
29
    i >>= 1;
3440
29
    variant += 1;
3441
29
  }
3442
71
      break;
3443
3444
34.8k
    case sve_limm:
3445
      /* Pick the smallest applicable element size.  */
3446
34.8k
      if ((inst->value & 0x20600) == 0x600)
3447
5.42k
  variant = 0;
3448
29.3k
      else if ((inst->value & 0x20400) == 0x400)
3449
2.99k
  variant = 1;
3450
26.3k
      else if ((inst->value & 0x20000) == 0)
3451
23.4k
  variant = 2;
3452
2.96k
      else
3453
2.96k
  variant = 3;
3454
34.8k
      break;
3455
3456
1
    case sme2_mov:
3457
      /* .D is preferred over the other sizes in disassembly.  */
3458
1
      variant = 3;
3459
1
      break;
3460
3461
3
    case sme2_movaz:
3462
50.6k
    case sme_misc:
3463
339k
    case sve_misc:
3464
      /* These instructions have only a single variant.  */
3465
339k
      break;
3466
3467
462
    case sve_movprfx:
3468
462
      variant = extract_fields (inst->value, 0, 2, FLD_size, FLD_SVE_M_16);
3469
462
      break;
3470
3471
55
    case sve_pred_zm:
3472
55
      variant = extract_field (FLD_SVE_M_4, inst->value, 0);
3473
55
      break;
3474
3475
1.68k
    case sve_shift_pred:
3476
1.68k
      i = extract_fields (inst->value, 0, 2, FLD_SVE_tszh, FLD_SVE_tszl_8);
3477
2.64k
    sve_shift:
3478
2.64k
      if (i == 0)
3479
549
  return false;
3480
5.65k
      while (i != 1)
3481
3.55k
  {
3482
3.55k
    i >>= 1;
3483
3.55k
    variant += 1;
3484
3.55k
  }
3485
2.09k
      break;
3486
3487
697
    case sve_shift_unpred:
3488
697
      i = extract_fields (inst->value, 0, 2, FLD_SVE_tszh, FLD_SVE_tszl_19);
3489
697
      goto sve_shift;
3490
3491
10.2k
    case sve_size_bhs:
3492
10.2k
      variant = extract_field (FLD_size, inst->value, 0);
3493
10.2k
      if (variant >= 3)
3494
2.14k
  return false;
3495
8.10k
      break;
3496
3497
117k
    case sve_size_bhsd:
3498
117k
      variant = extract_field (FLD_size, inst->value, 0);
3499
117k
      break;
3500
3501
100k
    case sve_size_hsd:
3502
100k
      i = extract_field (FLD_size, inst->value, 0);
3503
100k
      if (i < 1)
3504
26.3k
  return false;
3505
73.6k
      variant = i - 1;
3506
73.6k
      break;
3507
3508
132
    case sme_fp_sd:
3509
1.44k
    case sme_int_sd:
3510
2.27k
    case sve_size_bh:
3511
6.87k
    case sve_size_sd:
3512
6.87k
      variant = extract_field (FLD_SVE_sz, inst->value, 0);
3513
6.87k
      break;
3514
3515
4.20k
    case sve_size_sd2:
3516
4.20k
      variant = extract_field (FLD_SVE_sz2, inst->value, 0);
3517
4.20k
      break;
3518
3519
179
    case sve_size_hsd2:
3520
179
      i = extract_field (FLD_SVE_size, inst->value, 0);
3521
179
      if (i < 1)
3522
106
  return false;
3523
73
      variant = i - 1;
3524
73
      break;
3525
3526
645
    case sve_size_13:
3527
      /* Ignore low bit of this field since that is set in the opcode for
3528
   instructions of this iclass.  */
3529
645
      i = (extract_field (FLD_size, inst->value, 0) & 2);
3530
645
      variant = (i >> 1);
3531
645
      break;
3532
3533
1.75k
    case sve_shift_tsz_bhsd:
3534
1.75k
      i = extract_fields (inst->value, 0, 2, FLD_SVE_tszh, FLD_SVE_tszl_19);
3535
1.75k
      if (i == 0)
3536
462
  return false;
3537
4.20k
      while (i != 1)
3538
2.91k
  {
3539
2.91k
    i >>= 1;
3540
2.91k
    variant += 1;
3541
2.91k
  }
3542
1.29k
      break;
3543
3544
159
    case sve_size_tsz_bhs:
3545
159
      i = extract_fields (inst->value, 0, 2, FLD_SVE_sz, FLD_SVE_tszl_19);
3546
159
      if (i == 0)
3547
24
  return false;
3548
214
      while (i != 1)
3549
168
  {
3550
168
    if (i & 1)
3551
89
      return false;
3552
79
    i >>= 1;
3553
79
    variant += 1;
3554
79
  }
3555
46
      break;
3556
3557
3.85k
    case sve_shift_tsz_hsd:
3558
3.85k
      i = extract_fields (inst->value, 0, 2, FLD_SVE_sz, FLD_SVE_tszl_19);
3559
3.85k
      if (i == 0)
3560
453
  return false;
3561
8.64k
      while (i != 1)
3562
5.24k
  {
3563
5.24k
    i >>= 1;
3564
5.24k
    variant += 1;
3565
5.24k
  }
3566
3.40k
      break;
3567
3568
5.41M
    default:
3569
      /* No mapping between instruction class and qualifiers.  */
3570
5.41M
      return true;
3571
6.07M
    }
3572
3573
4.98M
  for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
3574
4.35M
    inst->operands[i].qualifier = inst->opcode->qualifiers_list[variant][i];
3575
622k
  return true;
3576
6.07M
}
3577
/* Decode the CODE according to OPCODE; fill INST.  Return 0 if the decoding
3578
   fails, which meanes that CODE is not an instruction of OPCODE; otherwise
3579
   return 1.
3580
3581
   If OPCODE has alias(es) and NOALIASES_P is 0, an alias opcode may be
3582
   determined and used to disassemble CODE; this is done just before the
3583
   return.  */
3584
3585
static bool
3586
aarch64_opcode_decode (const aarch64_opcode *opcode, const aarch64_insn code,
3587
           aarch64_inst *inst, int noaliases_p,
3588
           aarch64_operand_error *errors)
3589
14.4M
{
3590
14.4M
  int i;
3591
3592
14.4M
  DEBUG_TRACE ("enter with %s", opcode->name);
3593
3594
14.4M
  assert (opcode && inst);
3595
3596
  /* Clear inst.  */
3597
14.4M
  memset (inst, '\0', sizeof (aarch64_inst));
3598
3599
  /* Check the base opcode.  */
3600
14.4M
  if ((code & opcode->mask) != (opcode->opcode & opcode->mask))
3601
8.25M
    {
3602
8.25M
      DEBUG_TRACE ("base opcode match FAIL");
3603
8.25M
      goto decode_fail;
3604
8.25M
    }
3605
3606
6.17M
  inst->opcode = opcode;
3607
6.17M
  inst->value = code;
3608
3609
  /* Assign operand codes and indexes.  */
3610
20.6M
  for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
3611
20.6M
    {
3612
20.6M
      if (opcode->operands[i] == AARCH64_OPND_NIL)
3613
6.17M
  break;
3614
14.5M
      inst->operands[i].type = opcode->operands[i];
3615
14.5M
      inst->operands[i].idx = i;
3616
14.5M
    }
3617
3618
  /* Call the opcode decoder indicated by flags.  */
3619
6.17M
  if (opcode_has_special_coder (opcode) && do_special_decoding (inst) == 0)
3620
102k
    {
3621
102k
      DEBUG_TRACE ("opcode flag-based decoder FAIL");
3622
102k
      goto decode_fail;
3623
102k
    }
3624
3625
  /* Possibly use the instruction class to determine the correct
3626
     qualifier.  */
3627
6.07M
  if (!aarch64_decode_variant_using_iclass (inst))
3628
33.2k
    {
3629
33.2k
      DEBUG_TRACE ("iclass-based decoder FAIL");
3630
33.2k
      goto decode_fail;
3631
33.2k
    }
3632
3633
  /* Call operand decoders.  */
3634
19.3M
  for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
3635
19.3M
    {
3636
19.3M
      const aarch64_operand *opnd;
3637
19.3M
      enum aarch64_opnd type;
3638
3639
19.3M
      type = opcode->operands[i];
3640
19.3M
      if (type == AARCH64_OPND_NIL)
3641
5.62M
  break;
3642
13.7M
      opnd = &aarch64_operands[type];
3643
13.7M
      if (operand_has_extractor (opnd)
3644
13.7M
    && (! aarch64_extract_operand (opnd, &inst->operands[i], code, inst,
3645
13.7M
           errors)))
3646
416k
  {
3647
416k
    DEBUG_TRACE ("operand decoder FAIL at operand %d", i);
3648
416k
    goto decode_fail;
3649
416k
  }
3650
13.7M
    }
3651
3652
  /* If the opcode has a verifier, then check it now.  */
3653
5.62M
  if (opcode->verifier
3654
5.62M
      && opcode->verifier (inst, code, 0, false, errors, NULL) != ERR_OK)
3655
4.99k
    {
3656
4.99k
      DEBUG_TRACE ("operand verifier FAIL");
3657
4.99k
      goto decode_fail;
3658
4.99k
    }
3659
3660
  /* Match the qualifiers.  */
3661
5.62M
  if (aarch64_match_operands_constraint (inst, NULL) == 1)
3662
5.39M
    {
3663
      /* Arriving here, the CODE has been determined as a valid instruction
3664
   of OPCODE and *INST has been filled with information of this OPCODE
3665
   instruction.  Before the return, check if the instruction has any
3666
   alias and should be disassembled in the form of its alias instead.
3667
   If the answer is yes, *INST will be updated.  */
3668
5.39M
      if (!noaliases_p)
3669
4.90M
  determine_disassembling_preference (inst, errors);
3670
5.39M
      DEBUG_TRACE ("SUCCESS");
3671
5.39M
      return true;
3672
5.39M
    }
3673
222k
  else
3674
222k
    {
3675
222k
      DEBUG_TRACE ("constraint matching FAIL");
3676
222k
    }
3677
3678
9.03M
 decode_fail:
3679
9.03M
  return false;
3680
5.62M
}
3681

3682
/* This does some user-friendly fix-up to *INST.  It is currently focus on
3683
   the adjustment of qualifiers to help the printed instruction
3684
   recognized/understood more easily.  */
3685
3686
static void
3687
user_friendly_fixup (aarch64_inst *inst)
3688
4.90M
{
3689
4.90M
  switch (inst->opcode->iclass)
3690
4.90M
    {
3691
148k
    case testbranch:
3692
      /* TBNZ Xn|Wn, #uimm6, label
3693
   Test and Branch Not Zero: conditionally jumps to label if bit number
3694
   uimm6 in register Xn is not zero.  The bit number implies the width of
3695
   the register, which may be written and should be disassembled as Wn if
3696
   uimm is less than 32. Limited to a branch offset range of +/- 32KiB.
3697
   */
3698
148k
      if (inst->operands[1].imm.value < 32)
3699
102k
  inst->operands[0].qualifier = AARCH64_OPND_QLF_W;
3700
148k
      break;
3701
4.75M
    default: break;
3702
4.90M
    }
3703
4.90M
}
3704
3705
/* Decode INSN and fill in *INST the instruction information.  An alias
3706
   opcode may be filled in *INSN if NOALIASES_P is FALSE.  Return zero on
3707
   success.  */
3708
3709
enum err_type
3710
aarch64_decode_insn (aarch64_insn insn, aarch64_inst *inst,
3711
         bool noaliases_p,
3712
         aarch64_operand_error *errors)
3713
12.0M
{
3714
12.0M
  const aarch64_opcode *opcode = aarch64_opcode_lookup (insn);
3715
3716
#ifdef DEBUG_AARCH64
3717
  if (debug_dump)
3718
    {
3719
      const aarch64_opcode *tmp = opcode;
3720
      printf ("\n");
3721
      DEBUG_TRACE ("opcode lookup:");
3722
      while (tmp != NULL)
3723
  {
3724
    aarch64_verbose ("  %s", tmp->name);
3725
    tmp = aarch64_find_next_opcode (tmp);
3726
  }
3727
    }
3728
#endif /* DEBUG_AARCH64 */
3729
3730
  /* A list of opcodes may have been found, as aarch64_opcode_lookup cannot
3731
     distinguish some opcodes, e.g. SSHR and MOVI, which almost share the same
3732
     opcode field and value, apart from the difference that one of them has an
3733
     extra field as part of the opcode, but such a field is used for operand
3734
     encoding in other opcode(s) ('immh' in the case of the example).  */
3735
21.0M
  while (opcode != NULL)
3736
13.9M
    {
3737
      /* But only one opcode can be decoded successfully for, as the
3738
   decoding routine will check the constraint carefully.  */
3739
13.9M
      if (aarch64_opcode_decode (opcode, insn, inst, noaliases_p, errors) == 1)
3740
4.90M
  return ERR_OK;
3741
9.01M
      opcode = aarch64_find_next_opcode (opcode);
3742
9.01M
    }
3743
3744
7.09M
  return ERR_UND;
3745
12.0M
}
3746
3747
/* Return a short string to indicate a switch to STYLE.  These strings
3748
   will be embedded into the disassembled operand text (as produced by
3749
   aarch64_print_operand), and then spotted in the print_operands function
3750
   so that the disassembler output can be split by style.  */
3751
3752
static const char *
3753
get_style_text (enum disassembler_style style)
3754
25.6M
{
3755
25.6M
  static bool init = false;
3756
25.6M
  static char formats[16][4];
3757
25.6M
  unsigned num;
3758
3759
  /* First time through we build a string for every possible format.  This
3760
     code relies on there being no more than 16 different styles (there's
3761
     an assert below for this).  */
3762
25.6M
  if (!init)
3763
2
    {
3764
2
      int i;
3765
3766
34
      for (i = 0; i <= 0xf; ++i)
3767
32
  {
3768
32
    int res ATTRIBUTE_UNUSED
3769
32
      = snprintf (&formats[i][0], sizeof (formats[i]), "%c%x%c",
3770
32
      STYLE_MARKER_CHAR, i, STYLE_MARKER_CHAR);
3771
32
    assert (res == 3);
3772
32
  }
3773
3774
2
      init = true;
3775
2
    }
3776
3777
  /* Return the string that marks switching to STYLE.  */
3778
25.6M
  num = (unsigned) style;
3779
25.6M
  assert (style <= 0xf);
3780
25.6M
  return formats[num];
3781
25.6M
}
3782
3783
/* Callback used by aarch64_print_operand to apply STYLE to the
3784
   disassembler output created from FMT and ARGS.  The STYLER object holds
3785
   any required state.  Must return a pointer to a string (created from FMT
3786
   and ARGS) that will continue to be valid until the complete disassembled
3787
   instruction has been printed.
3788
3789
   We return a string that includes two embedded style markers, the first,
3790
   places at the start of the string, indicates a switch to STYLE, and the
3791
   second, placed at the end of the string, indicates a switch back to the
3792
   default text style.
3793
3794
   Later, when we print the operand text we take care to collapse any
3795
   adjacent style markers, and to ignore any style markers that appear at
3796
   the very end of a complete operand string.  */
3797
3798
static const char *aarch64_apply_style (struct aarch64_styler *styler,
3799
          enum disassembler_style style,
3800
          const char *fmt,
3801
          va_list args)
3802
12.8M
{
3803
12.8M
  int res;
3804
12.8M
  char *ptr, *tmp;
3805
12.8M
  struct obstack *stack = (struct obstack *) styler->state;
3806
12.8M
  va_list ap;
3807
3808
  /* These are the two strings for switching styles.  */
3809
12.8M
  const char *style_on = get_style_text (style);
3810
12.8M
  const char *style_off = get_style_text (dis_style_text);
3811
3812
  /* Calculate space needed once FMT and ARGS are expanded.  */
3813
12.8M
  va_copy (ap, args);
3814
12.8M
  res = vsnprintf (NULL, 0, fmt, ap);
3815
12.8M
  va_end (ap);
3816
12.8M
  assert (res >= 0);
3817
3818
  /* Allocate space on the obstack for the expanded FMT and ARGS, as well
3819
     as the two strings for switching styles, then write all of these
3820
     strings onto the obstack.  */
3821
12.8M
  ptr = (char *) obstack_alloc (stack, res + strlen (style_on)
3822
12.8M
        + strlen (style_off) + 1);
3823
12.8M
  tmp = stpcpy (ptr, style_on);
3824
12.8M
  res = vsnprintf (tmp, (res + 1), fmt, args);
3825
12.8M
  assert (res >= 0);
3826
12.8M
  tmp += res;
3827
12.8M
  strcpy (tmp, style_off);
3828
3829
12.8M
  return ptr;
3830
12.8M
}
3831
3832
/* Print operands.  */
3833
3834
static void
3835
print_operands (bfd_vma pc, const aarch64_opcode *opcode,
3836
    const aarch64_opnd_info *opnds, struct disassemble_info *info,
3837
    bool *has_notes)
3838
4.90M
{
3839
4.90M
  char *notes = NULL;
3840
4.90M
  int i, pcrel_p, num_printed;
3841
4.90M
  struct aarch64_styler styler;
3842
4.90M
  struct obstack content;
3843
4.90M
  obstack_init (&content);
3844
3845
4.90M
  styler.apply_style = aarch64_apply_style;
3846
4.90M
  styler.state = (void *) &content;
3847
3848
15.5M
  for (i = 0, num_printed = 0; i < AARCH64_MAX_OPND_NUM; ++i)
3849
15.5M
    {
3850
15.5M
      char str[128];
3851
15.5M
      char cmt[128];
3852
3853
      /* We regard the opcode operand info more, however we also look into
3854
   the inst->operands to support the disassembling of the optional
3855
   operand.
3856
   The two operand code should be the same in all cases, apart from
3857
   when the operand can be optional.  */
3858
15.5M
      if (opcode->operands[i] == AARCH64_OPND_NIL
3859
15.5M
    || opnds[i].type == AARCH64_OPND_NIL)
3860
4.90M
  break;
3861
3862
      /* Generate the operand string in STR.  */
3863
10.6M
      aarch64_print_operand (str, sizeof (str), pc, opcode, opnds, i, &pcrel_p,
3864
10.6M
           &info->target, &notes, cmt, sizeof (cmt),
3865
10.6M
           arch_variant, &styler);
3866
3867
      /* Print the delimiter (taking account of omitted operand(s)).  */
3868
10.6M
      if (str[0] != '\0')
3869
10.6M
  (*info->fprintf_styled_func) (info->stream, dis_style_text, "%s",
3870
10.6M
              num_printed++ == 0 ? "\t" : ", ");
3871
3872
      /* Print the operand.  */
3873
10.6M
      if (pcrel_p)
3874
1.08M
  (*info->print_address_func) (info->target, info);
3875
9.56M
      else
3876
9.56M
  {
3877
    /* This operand came from aarch64_print_operand, and will include
3878
       embedded strings indicating which style each character should
3879
       have.  In the following code we split the text based on
3880
       CURR_STYLE, and call the styled print callback to print each
3881
       block of text in the appropriate style.  */
3882
9.56M
    char *start, *curr;
3883
9.56M
    enum disassembler_style curr_style = dis_style_text;
3884
3885
9.56M
    start = curr = str;
3886
9.56M
    do
3887
80.9M
      {
3888
80.9M
        if (*curr == '\0'
3889
80.9M
      || (*curr == STYLE_MARKER_CHAR
3890
71.3M
          && ISXDIGIT (*(curr + 1))
3891
71.3M
          && *(curr + 2) == STYLE_MARKER_CHAR))
3892
33.0M
    {
3893
      /* Output content between our START position and CURR.  */
3894
33.0M
      int len = curr - start;
3895
33.0M
      if (len > 0)
3896
16.8M
        {
3897
16.8M
          if ((*info->fprintf_styled_func) (info->stream,
3898
16.8M
              curr_style,
3899
16.8M
              "%.*s",
3900
16.8M
              len, start) < 0)
3901
0
      break;
3902
16.8M
        }
3903
3904
33.0M
      if (*curr == '\0')
3905
9.56M
        break;
3906
3907
      /* Skip over the initial STYLE_MARKER_CHAR.  */
3908
23.5M
      ++curr;
3909
3910
      /* Update the CURR_STYLE.  As there are less than 16
3911
         styles, it is possible, that if the input is corrupted
3912
         in some way, that we might set CURR_STYLE to an
3913
         invalid value.  Don't worry though, we check for this
3914
         situation.  */
3915
23.5M
      if (*curr >= '0' && *curr <= '9')
3916
23.5M
        curr_style = (enum disassembler_style) (*curr - '0');
3917
0
      else if (*curr >= 'a' && *curr <= 'f')
3918
0
        curr_style = (enum disassembler_style) (*curr - 'a' + 10);
3919
0
      else
3920
0
        curr_style = dis_style_text;
3921
3922
      /* Check for an invalid style having been selected.  This
3923
         should never happen, but it doesn't hurt to be a
3924
         little paranoid.  */
3925
23.5M
      if (curr_style > dis_style_comment_start)
3926
0
        curr_style = dis_style_text;
3927
3928
      /* Skip the hex character, and the closing STYLE_MARKER_CHAR.  */
3929
23.5M
      curr += 2;
3930
3931
      /* Reset the START to after the style marker.  */
3932
23.5M
      start = curr;
3933
23.5M
    }
3934
47.8M
        else
3935
47.8M
    ++curr;
3936
80.9M
      }
3937
9.56M
    while (true);
3938
9.56M
  }
3939
3940
      /* Print the comment.  This works because only the last operand ever
3941
   adds a comment.  If that ever changes then we'll need to be
3942
   smarter here.  */
3943
10.6M
      if (cmt[0] != '\0')
3944
64.6k
  (*info->fprintf_styled_func) (info->stream, dis_style_comment_start,
3945
64.6k
              "\t// %s", cmt);
3946
10.6M
    }
3947
3948
4.90M
    if (notes && !no_notes)
3949
0
      {
3950
0
  *has_notes = true;
3951
0
  (*info->fprintf_styled_func) (info->stream, dis_style_comment_start,
3952
0
              "  // note: %s", notes);
3953
0
      }
3954
3955
4.90M
    obstack_free (&content, NULL);
3956
4.90M
}
3957
3958
/* Set NAME to a copy of INST's mnemonic with the "." suffix removed.  */
3959
3960
static void
3961
remove_dot_suffix (char *name, const aarch64_inst *inst)
3962
76.9k
{
3963
76.9k
  char *ptr;
3964
76.9k
  size_t len;
3965
3966
76.9k
  ptr = strchr (inst->opcode->name, '.');
3967
76.9k
  assert (ptr && inst->cond);
3968
76.9k
  len = ptr - inst->opcode->name;
3969
76.9k
  assert (len < 8);
3970
76.9k
  strncpy (name, inst->opcode->name, len);
3971
76.9k
  name[len] = '\0';
3972
76.9k
}
3973
3974
/* Print the instruction mnemonic name.  */
3975
3976
static void
3977
print_mnemonic_name (const aarch64_inst *inst, struct disassemble_info *info)
3978
4.90M
{
3979
4.90M
  if (inst->opcode->flags & F_COND)
3980
38.4k
    {
3981
      /* For instructions that are truly conditionally executed, e.g. b.cond,
3982
   prepare the full mnemonic name with the corresponding condition
3983
   suffix.  */
3984
38.4k
      char name[8];
3985
3986
38.4k
      remove_dot_suffix (name, inst);
3987
38.4k
      (*info->fprintf_styled_func) (info->stream, dis_style_mnemonic,
3988
38.4k
            "%s.%s", name, inst->cond->names[0]);
3989
38.4k
    }
3990
4.86M
  else
3991
4.86M
    (*info->fprintf_styled_func) (info->stream, dis_style_mnemonic,
3992
4.86M
          "%s", inst->opcode->name);
3993
4.90M
}
3994
3995
/* Decide whether we need to print a comment after the operands of
3996
   instruction INST.  */
3997
3998
static void
3999
print_comment (const aarch64_inst *inst, struct disassemble_info *info)
4000
4.90M
{
4001
4.90M
  if (inst->opcode->flags & F_COND)
4002
38.4k
    {
4003
38.4k
      char name[8];
4004
38.4k
      unsigned int i, num_conds;
4005
4006
38.4k
      remove_dot_suffix (name, inst);
4007
38.4k
      num_conds = ARRAY_SIZE (inst->cond->names);
4008
71.3k
      for (i = 1; i < num_conds && inst->cond->names[i]; ++i)
4009
32.8k
  (*info->fprintf_styled_func) (info->stream, dis_style_comment_start,
4010
32.8k
              "%s %s.%s",
4011
32.8k
              i == 1 ? "  //" : ",",
4012
32.8k
              name, inst->cond->names[i]);
4013
38.4k
    }
4014
4.90M
}
4015
4016
/* Build notes from verifiers into a string for printing.  */
4017
4018
static void
4019
print_verifier_notes (aarch64_operand_error *detail,
4020
          struct disassemble_info *info)
4021
6.00k
{
4022
6.00k
  if (no_notes)
4023
6.00k
    return;
4024
4025
  /* The output of the verifier cannot be a fatal error, otherwise the assembly
4026
     would not have succeeded.  We can safely ignore these.  */
4027
0
  assert (detail->non_fatal);
4028
4029
0
  (*info->fprintf_styled_func) (info->stream, dis_style_comment_start,
4030
0
        "  // note: ");
4031
0
  switch (detail->kind)
4032
0
    {
4033
0
    case AARCH64_OPDE_A_SHOULD_FOLLOW_B:
4034
0
      (*info->fprintf_styled_func) (info->stream, dis_style_text,
4035
0
            _("this `%s' should have an immediately"
4036
0
              " preceding `%s'"),
4037
0
            detail->data[0].s, detail->data[1].s);
4038
0
      break;
4039
4040
0
    case AARCH64_OPDE_EXPECTED_A_AFTER_B:
4041
0
      (*info->fprintf_styled_func) (info->stream, dis_style_text,
4042
0
            _("expected `%s' after previous `%s'"),
4043
0
            detail->data[0].s, detail->data[1].s);
4044
0
      break;
4045
4046
0
    default:
4047
0
      assert (detail->error);
4048
0
      (*info->fprintf_styled_func) (info->stream, dis_style_text,
4049
0
            "%s", detail->error);
4050
0
      if (detail->index >= 0)
4051
0
  (*info->fprintf_styled_func) (info->stream, dis_style_text,
4052
0
              " at operand %d", detail->index + 1);
4053
0
      break;
4054
0
    }
4055
0
}
4056
4057
/* Print the instruction according to *INST.  */
4058
4059
static void
4060
print_aarch64_insn (bfd_vma pc, const aarch64_inst *inst,
4061
        const aarch64_insn code,
4062
        struct disassemble_info *info,
4063
        aarch64_operand_error *mismatch_details)
4064
4.90M
{
4065
4.90M
  bool has_notes = false;
4066
4067
4.90M
  print_mnemonic_name (inst, info);
4068
4.90M
  print_operands (pc, inst->opcode, inst->operands, info, &has_notes);
4069
4.90M
  print_comment (inst, info);
4070
4071
  /* We've already printed a note, not enough space to print more so exit.
4072
     Usually notes shouldn't overlap so it shouldn't happen that we have a note
4073
     from a register and instruction at the same time.  */
4074
4.90M
  if (has_notes)
4075
0
    return;
4076
4077
  /* Always run constraint verifiers, this is needed because constraints need to
4078
     maintain a global state regardless of whether the instruction has the flag
4079
     set or not.  */
4080
4.90M
  enum err_type result = verify_constraints (inst, code, pc, false,
4081
4.90M
               mismatch_details, &insn_sequence);
4082
4.90M
  switch (result)
4083
4.90M
    {
4084
6.00k
    case ERR_VFI:
4085
6.00k
      print_verifier_notes (mismatch_details, info);
4086
6.00k
      break;
4087
0
    case ERR_UND:
4088
0
    case ERR_UNP:
4089
0
    case ERR_NYI:
4090
4.90M
    default:
4091
4.90M
      break;
4092
4.90M
    }
4093
4.90M
}
4094
4095
/* Entry-point of the instruction disassembler and printer.  */
4096
4097
static void
4098
print_insn_aarch64_word (bfd_vma pc,
4099
       uint32_t word,
4100
       struct disassemble_info *info,
4101
       aarch64_operand_error *errors)
4102
12.0M
{
4103
12.0M
  static const char *err_msg[ERR_NR_ENTRIES+1] =
4104
12.0M
    {
4105
12.0M
      [ERR_OK]  = "_",
4106
12.0M
      [ERR_UND] = "undefined",
4107
12.0M
      [ERR_UNP] = "unpredictable",
4108
12.0M
      [ERR_NYI] = "NYI"
4109
12.0M
    };
4110
4111
12.0M
  enum err_type ret;
4112
12.0M
  aarch64_inst inst;
4113
4114
12.0M
  info->insn_info_valid = 1;
4115
12.0M
  info->branch_delay_insns = 0;
4116
12.0M
  info->data_size = 0;
4117
12.0M
  info->target = 0;
4118
12.0M
  info->target2 = 0;
4119
4120
12.0M
  if (info->flags & INSN_HAS_RELOC)
4121
    /* If the instruction has a reloc associated with it, then
4122
       the offset field in the instruction will actually be the
4123
       addend for the reloc.  (If we are using REL type relocs).
4124
       In such cases, we can ignore the pc when computing
4125
       addresses, since the addend is not currently pc-relative.  */
4126
12
    pc = 0;
4127
4128
12.0M
  ret = aarch64_decode_insn (word, &inst, no_aliases, errors);
4129
4130
12.0M
  if (((word >> 21) & 0x3ff) == 1)
4131
111k
    {
4132
      /* RESERVED for ALES.  */
4133
111k
      assert (ret != ERR_OK);
4134
111k
      ret = ERR_NYI;
4135
111k
    }
4136
4137
12.0M
  switch (ret)
4138
12.0M
    {
4139
6.98M
    case ERR_UND:
4140
6.98M
    case ERR_UNP:
4141
7.09M
    case ERR_NYI:
4142
      /* Handle undefined instructions.  */
4143
7.09M
      info->insn_type = dis_noninsn;
4144
7.09M
      (*info->fprintf_styled_func) (info->stream,
4145
7.09M
            dis_style_assembler_directive,
4146
7.09M
            ".inst\t");
4147
7.09M
      (*info->fprintf_styled_func) (info->stream, dis_style_immediate,
4148
7.09M
            "0x%08x", word);
4149
7.09M
      (*info->fprintf_styled_func) (info->stream, dis_style_comment_start,
4150
7.09M
            " ; %s", err_msg[ret]);
4151
7.09M
      break;
4152
4.90M
    case ERR_OK:
4153
4.90M
      user_friendly_fixup (&inst);
4154
4.90M
      if (inst.opcode->iclass == condbranch
4155
4.90M
    || inst.opcode->iclass == testbranch
4156
4.90M
    || inst.opcode->iclass == compbranch)
4157
313k
        info->insn_type = dis_condbranch;
4158
4.59M
      else if (inst.opcode->iclass == branch_imm)
4159
226k
        info->insn_type = dis_jsr;
4160
4.90M
      print_aarch64_insn (pc, &inst, word, info, errors);
4161
4.90M
      break;
4162
0
    default:
4163
0
      abort ();
4164
12.0M
    }
4165
12.0M
}
4166
4167
/* Disallow mapping symbols ($x, $d etc) from
4168
   being displayed in symbol relative addresses.  */
4169
4170
bool
4171
aarch64_symbol_is_valid (asymbol * sym,
4172
       struct disassemble_info * info ATTRIBUTE_UNUSED)
4173
103k
{
4174
103k
  const char * name;
4175
4176
103k
  if (sym == NULL)
4177
0
    return false;
4178
4179
103k
  name = bfd_asymbol_name (sym);
4180
4181
103k
  return name
4182
103k
    && (name[0] != '$'
4183
103k
  || (name[1] != 'x' && name[1] != 'd')
4184
103k
  || (name[2] != '\0' && name[2] != '.'));
4185
103k
}
4186
4187
/* Print data bytes on INFO->STREAM.  */
4188
4189
static void
4190
print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED,
4191
     uint32_t word,
4192
     struct disassemble_info *info,
4193
     aarch64_operand_error *errors ATTRIBUTE_UNUSED)
4194
0
{
4195
0
  switch (info->bytes_per_chunk)
4196
0
    {
4197
0
    case 1:
4198
0
      info->fprintf_styled_func (info->stream, dis_style_assembler_directive,
4199
0
         ".byte\t");
4200
0
      info->fprintf_styled_func (info->stream, dis_style_immediate,
4201
0
         "0x%02x", word);
4202
0
      break;
4203
0
    case 2:
4204
0
      info->fprintf_styled_func (info->stream, dis_style_assembler_directive,
4205
0
         ".short\t");
4206
0
      info->fprintf_styled_func (info->stream, dis_style_immediate,
4207
0
         "0x%04x", word);
4208
0
      break;
4209
0
    case 4:
4210
0
      info->fprintf_styled_func (info->stream, dis_style_assembler_directive,
4211
0
         ".word\t");
4212
0
      info->fprintf_styled_func (info->stream, dis_style_immediate,
4213
0
         "0x%08x", word);
4214
0
      break;
4215
0
    default:
4216
0
      abort ();
4217
0
    }
4218
0
}
4219
4220
/* Try to infer the code or data type from a symbol.
4221
   Returns nonzero if *MAP_TYPE was set.  */
4222
4223
static int
4224
get_sym_code_type (struct disassemble_info *info, int n,
4225
       enum map_type *map_type)
4226
3.30M
{
4227
3.30M
  asymbol * as;
4228
3.30M
  elf_symbol_type *es;
4229
3.30M
  unsigned int type;
4230
3.30M
  const char *name;
4231
4232
  /* If the symbol is in a different section, ignore it.  */
4233
3.30M
  if (info->section != NULL && info->section != info->symtab[n]->section)
4234
968k
    return false;
4235
4236
2.34M
  if (n >= info->symtab_size)
4237
0
    return false;
4238
4239
2.34M
  as = info->symtab[n];
4240
2.34M
  if (bfd_asymbol_flavour (as) != bfd_target_elf_flavour)
4241
82.0k
    return false;
4242
2.25M
  es = (elf_symbol_type *) as;
4243
4244
2.25M
  type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
4245
4246
  /* If the symbol has function type then use that.  */
4247
2.25M
  if (type == STT_FUNC)
4248
144k
    {
4249
144k
      *map_type = MAP_INSN;
4250
144k
      return true;
4251
144k
    }
4252
4253
  /* Check for mapping symbols.  */
4254
2.11M
  name = bfd_asymbol_name(info->symtab[n]);
4255
2.11M
  if (name[0] == '$'
4256
2.11M
      && (name[1] == 'x' || name[1] == 'd')
4257
2.11M
      && (name[2] == '\0' || name[2] == '.'))
4258
0
    {
4259
0
      *map_type = (name[1] == 'x' ? MAP_INSN : MAP_DATA);
4260
0
      return true;
4261
0
    }
4262
4263
2.11M
  return false;
4264
2.11M
}
4265
4266
/* Set the feature bits in arch_variant in order to get the correct disassembly
4267
   for the chosen architecture variant.
4268
4269
   Currently we only restrict disassembly for Armv8-R and otherwise enable all
4270
   non-R-profile features.  */
4271
static void
4272
select_aarch64_variant (unsigned mach)
4273
2
{
4274
2
  switch (mach)
4275
2
    {
4276
0
    case bfd_mach_aarch64_8R:
4277
0
      AARCH64_SET_FEATURE (arch_variant, AARCH64_ARCH_V8R);
4278
0
      break;
4279
2
    default:
4280
2
      arch_variant = (aarch64_feature_set) AARCH64_ALL_FEATURES;
4281
2
      AARCH64_CLEAR_FEATURE (arch_variant, arch_variant, V8R);
4282
2
    }
4283
2
}
4284
4285
/* Entry-point of the AArch64 disassembler.  */
4286
4287
int
4288
print_insn_aarch64 (bfd_vma pc,
4289
        struct disassemble_info *info)
4290
12.0M
{
4291
12.0M
  bfd_byte  buffer[INSNLEN];
4292
12.0M
  int   status;
4293
12.0M
  void    (*printer) (bfd_vma, uint32_t, struct disassemble_info *,
4294
12.0M
          aarch64_operand_error *);
4295
12.0M
  bool   found = false;
4296
12.0M
  unsigned int  size = 4;
4297
12.0M
  unsigned long data;
4298
12.0M
  aarch64_operand_error errors;
4299
12.0M
  static bool set_features;
4300
4301
12.0M
  if (info->disassembler_options)
4302
0
    {
4303
0
      set_default_aarch64_dis_options (info);
4304
4305
0
      parse_aarch64_dis_options (info->disassembler_options);
4306
4307
      /* To avoid repeated parsing of these options, we remove them here.  */
4308
0
      info->disassembler_options = NULL;
4309
0
    }
4310
4311
12.0M
  if (!set_features)
4312
2
    {
4313
2
      select_aarch64_variant (info->mach);
4314
2
      set_features = true;
4315
2
    }
4316
4317
  /* Aarch64 instructions are always little-endian */
4318
12.0M
  info->endian_code = BFD_ENDIAN_LITTLE;
4319
4320
  /* Default to DATA.  A text section is required by the ABI to contain an
4321
     INSN mapping symbol at the start.  A data section has no such
4322
     requirement, hence if no mapping symbol is found the section must
4323
     contain only data.  This however isn't very useful if the user has
4324
     fully stripped the binaries.  If this is the case use the section
4325
     attributes to determine the default.  If we have no section default to
4326
     INSN as well, as we may be disassembling some raw bytes on a baremetal
4327
     HEX file or similar.  */
4328
12.0M
  enum map_type type = MAP_DATA;
4329
12.0M
  if ((info->section && info->section->flags & SEC_CODE) || !info->section)
4330
8.07M
    type = MAP_INSN;
4331
4332
  /* First check the full symtab for a mapping symbol, even if there
4333
     are no usable non-mapping symbols for this address.  */
4334
12.0M
  if (info->symtab_size != 0
4335
12.0M
      && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour)
4336
205k
    {
4337
205k
      int last_sym = -1;
4338
205k
      bfd_vma addr, section_vma = 0;
4339
205k
      bool can_use_search_opt_p;
4340
205k
      int n;
4341
4342
205k
      if (pc <= last_mapping_addr)
4343
69
  last_mapping_sym = -1;
4344
4345
      /* Start scanning at the start of the function, or wherever
4346
   we finished last time.  */
4347
205k
      n = info->symtab_pos + 1;
4348
4349
      /* If the last stop offset is different from the current one it means we
4350
   are disassembling a different glob of bytes.  As such the optimization
4351
   would not be safe and we should start over.  */
4352
205k
      can_use_search_opt_p = last_mapping_sym >= 0
4353
205k
           && info->stop_offset == last_stop_offset;
4354
4355
205k
      if (n >= last_mapping_sym && can_use_search_opt_p)
4356
142k
  n = last_mapping_sym;
4357
4358
      /* Look down while we haven't passed the location being disassembled.
4359
   The reason for this is that there's no defined order between a symbol
4360
   and an mapping symbol that may be at the same address.  We may have to
4361
   look at least one position ahead.  */
4362
1.31M
      for (; n < info->symtab_size; n++)
4363
1.31M
  {
4364
1.31M
    addr = bfd_asymbol_value (info->symtab[n]);
4365
1.31M
    if (addr > pc)
4366
205k
      break;
4367
1.11M
    if (get_sym_code_type (info, n, &type))
4368
142k
      {
4369
142k
        last_sym = n;
4370
142k
        found = true;
4371
142k
      }
4372
1.11M
  }
4373
4374
205k
      if (!found)
4375
63.1k
  {
4376
63.1k
    n = info->symtab_pos;
4377
63.1k
    if (n >= last_mapping_sym && can_use_search_opt_p)
4378
0
      n = last_mapping_sym;
4379
4380
    /* No mapping symbol found at this address.  Look backwards
4381
       for a preceeding one, but don't go pass the section start
4382
       otherwise a data section with no mapping symbol can pick up
4383
       a text mapping symbol of a preceeding section.  The documentation
4384
       says section can be NULL, in which case we will seek up all the
4385
       way to the top.  */
4386
63.1k
    if (info->section)
4387
63.1k
      section_vma = info->section->vma;
4388
4389
2.26M
    for (; n >= 0; n--)
4390
2.22M
      {
4391
2.22M
        addr = bfd_asymbol_value (info->symtab[n]);
4392
2.22M
        if (addr < section_vma)
4393
30.6k
    break;
4394
4395
2.19M
        if (get_sym_code_type (info, n, &type))
4396
1.39k
    {
4397
1.39k
      last_sym = n;
4398
1.39k
      found = true;
4399
1.39k
      break;
4400
1.39k
    }
4401
2.19M
      }
4402
63.1k
  }
4403
4404
205k
      last_mapping_sym = last_sym;
4405
205k
      last_type = type;
4406
205k
      last_stop_offset = info->stop_offset;
4407
4408
      /* Look a little bit ahead to see if we should print out
4409
   less than four bytes of data.  If there's a symbol,
4410
   mapping or otherwise, after two bytes then don't
4411
   print more.  */
4412
205k
      if (last_type == MAP_DATA)
4413
60.4k
  {
4414
60.4k
    size = 4 - (pc & 3);
4415
50.8M
    for (n = last_sym + 1; n < info->symtab_size; n++)
4416
50.8M
      {
4417
50.8M
        addr = bfd_asymbol_value (info->symtab[n]);
4418
50.8M
        if (addr > pc)
4419
60.4k
    {
4420
60.4k
      if (addr - pc < size)
4421
37
        size = addr - pc;
4422
60.4k
      break;
4423
60.4k
    }
4424
50.8M
      }
4425
    /* If the next symbol is after three bytes, we need to
4426
       print only part of the data, so that we can use either
4427
       .byte or .short.  */
4428
60.4k
    if (size == 3)
4429
11
      size = (pc & 1) ? 1 : 2;
4430
60.4k
  }
4431
205k
    }
4432
11.8M
  else
4433
11.8M
    last_type = type;
4434
4435
  /* PR 10263: Disassemble data if requested to do so by the user.  */
4436
12.0M
  if (last_type == MAP_DATA && ((info->flags & DISASSEMBLE_DATA) == 0))
4437
0
    {
4438
      /* size was set above.  */
4439
0
      info->bytes_per_chunk = size;
4440
0
      info->display_endian = info->endian;
4441
0
      printer = print_insn_data;
4442
0
    }
4443
12.0M
  else
4444
12.0M
    {
4445
12.0M
      info->bytes_per_chunk = size = INSNLEN;
4446
12.0M
      info->display_endian = info->endian_code;
4447
12.0M
      printer = print_insn_aarch64_word;
4448
12.0M
    }
4449
4450
12.0M
  status = (*info->read_memory_func) (pc, buffer, size, info);
4451
12.0M
  if (status != 0)
4452
5.47k
    {
4453
5.47k
      (*info->memory_error_func) (status, pc, info);
4454
5.47k
      return -1;
4455
5.47k
    }
4456
4457
12.0M
  data = bfd_get_bits (buffer, size * 8,
4458
12.0M
           info->display_endian == BFD_ENDIAN_BIG);
4459
4460
12.0M
  (*printer) (pc, data, info, &errors);
4461
4462
12.0M
  return size;
4463
12.0M
}
4464

4465
void
4466
print_aarch64_disassembler_options (FILE *stream)
4467
0
{
4468
0
  fprintf (stream, _("\n\
4469
0
The following AARCH64 specific disassembler options are supported for use\n\
4470
0
with the -M switch (multiple options should be separated by commas):\n"));
4471
4472
0
  fprintf (stream, _("\n\
4473
0
  no-aliases         Don't print instruction aliases.\n"));
4474
4475
0
  fprintf (stream, _("\n\
4476
0
  aliases            Do print instruction aliases.\n"));
4477
4478
0
  fprintf (stream, _("\n\
4479
0
  no-notes         Don't print instruction notes.\n"));
4480
4481
0
  fprintf (stream, _("\n\
4482
0
  notes            Do print instruction notes.\n"));
4483
4484
#ifdef DEBUG_AARCH64
4485
  fprintf (stream, _("\n\
4486
  debug_dump         Temp switch for debug trace.\n"));
4487
#endif /* DEBUG_AARCH64 */
4488
4489
0
  fprintf (stream, _("\n"));
4490
0
}