Coverage Report

Created: 2024-05-21 06:29

/src/binutils-gdb/opcodes/alpha-dis.c
Line
Count
Source (jump to first uncovered line)
1
/* alpha-dis.c -- Disassemble Alpha AXP instructions
2
   Copyright (C) 1996-2024 Free Software Foundation, Inc.
3
   Contributed by Richard Henderson <rth@tamu.edu>,
4
   patterned after the PPC opcode handling written by Ian Lance Taylor.
5
6
   This file is part of libopcodes.
7
8
   This library is free software; you can redistribute it and/or modify
9
   it under the terms of the GNU General Public License as published by
10
   the Free Software Foundation; either version 3, or (at your option)
11
   any later version.
12
13
   It is distributed in the hope that it will be useful, but WITHOUT
14
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
16
   License for more details.
17
18
   You should have received a copy of the GNU General Public License
19
   along with this file; see the file COPYING.  If not, write to the Free
20
   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21
   02110-1301, USA.  */
22
23
#include "sysdep.h"
24
#include <stdio.h>
25
#include "disassemble.h"
26
#include "opcode/alpha.h"
27
28
/* OSF register names.  */
29
30
static const char * const osf_regnames[64] = {
31
  "v0", "t0", "t1", "t2", "t3", "t4", "t5", "t6",
32
  "t7", "s0", "s1", "s2", "s3", "s4", "s5", "fp",
33
  "a0", "a1", "a2", "a3", "a4", "a5", "t8", "t9",
34
  "t10", "t11", "ra", "t12", "at", "gp", "sp", "zero",
35
  "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
36
  "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
37
  "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
38
  "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31"
39
};
40
41
/* VMS register names.  */
42
43
static const char * const vms_regnames[64] = {
44
  "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7",
45
  "R8", "R9", "R10", "R11", "R12", "R13", "R14", "R15",
46
  "R16", "R17", "R18", "R19", "R20", "R21", "R22", "R23",
47
  "R24", "AI", "RA", "PV", "AT", "FP", "SP", "RZ",
48
  "F0", "F1", "F2", "F3", "F4", "F5", "F6", "F7",
49
  "F8", "F9", "F10", "F11", "F12", "F13", "F14", "F15",
50
  "F16", "F17", "F18", "F19", "F20", "F21", "F22", "F23",
51
  "F24", "F25", "F26", "F27", "F28", "F29", "F30", "FZ"
52
};
53
54
/* Disassemble Alpha instructions.  */
55
56
int
57
print_insn_alpha (bfd_vma memaddr, struct disassemble_info *info)
58
503k
{
59
503k
  static const struct alpha_opcode *opcode_index[AXP_NOPS+1];
60
503k
  const char * const * regnames;
61
503k
  const struct alpha_opcode *opcode, *opcode_end;
62
503k
  const unsigned char *opindex;
63
503k
  unsigned insn, op, isa_mask;
64
503k
  int need_comma;
65
66
  /* Initialize the majorop table the first time through */
67
503k
  if (!opcode_index[0])
68
2
    {
69
2
      opcode = alpha_opcodes;
70
2
      opcode_end = opcode + alpha_num_opcodes;
71
72
130
      for (op = 0; op < AXP_NOPS; ++op)
73
128
  {
74
128
    opcode_index[op] = opcode;
75
2.12k
    while (opcode < opcode_end && op == AXP_OP (opcode->opcode))
76
2.00k
      ++opcode;
77
128
  }
78
2
      opcode_index[op] = opcode;
79
2
    }
80
81
503k
  if (info->flavour == bfd_target_evax_flavour)
82
44.2k
    regnames = vms_regnames;
83
459k
  else
84
459k
    regnames = osf_regnames;
85
86
503k
  isa_mask = AXP_OPCODE_NOPAL;
87
503k
  switch (info->mach)
88
503k
    {
89
82
    case bfd_mach_alpha_ev4:
90
82
      isa_mask |= AXP_OPCODE_EV4;
91
82
      break;
92
1.06k
    case bfd_mach_alpha_ev5:
93
1.06k
      isa_mask |= AXP_OPCODE_EV5;
94
1.06k
      break;
95
7.86k
    case bfd_mach_alpha_ev6:
96
7.86k
      isa_mask |= AXP_OPCODE_EV6;
97
7.86k
      break;
98
503k
    }
99
100
  /* Read the insn into a host word */
101
503k
  {
102
503k
    bfd_byte buffer[4];
103
503k
    int status = (*info->read_memory_func) (memaddr, buffer, 4, info);
104
503k
    if (status != 0)
105
118
      {
106
118
  (*info->memory_error_func) (status, memaddr, info);
107
118
  return -1;
108
118
      }
109
503k
    insn = bfd_getl32 (buffer);
110
503k
  }
111
112
  /* Get the major opcode of the instruction.  */
113
503k
  op = AXP_OP (insn);
114
115
  /* Find the first match in the opcode table.  */
116
503k
  opcode_end = opcode_index[op + 1];
117
5.27M
  for (opcode = opcode_index[op]; opcode < opcode_end; ++opcode)
118
5.21M
    {
119
5.21M
      if ((insn ^ opcode->opcode) & opcode->mask)
120
4.59M
  continue;
121
122
625k
      if (!(opcode->flags & isa_mask))
123
93.2k
  continue;
124
125
      /* Make two passes over the operands.  First see if any of them
126
   have extraction functions, and, if they do, make sure the
127
   instruction is valid.  */
128
532k
      {
129
532k
  int invalid = 0;
130
1.62M
  for (opindex = opcode->operands; *opindex != 0; opindex++)
131
1.08M
    {
132
1.08M
      const struct alpha_operand *operand = alpha_operands + *opindex;
133
1.08M
      if (operand->extract)
134
273k
        (*operand->extract) (insn, &invalid);
135
1.08M
    }
136
532k
  if (invalid)
137
84.3k
    continue;
138
532k
      }
139
140
      /* The instruction is valid.  */
141
448k
      goto found;
142
532k
    }
143
144
  /* No instruction found */
145
55.2k
  (*info->fprintf_func) (info->stream, ".long %#08x", insn);
146
147
55.2k
  return 4;
148
149
448k
 found:
150
448k
  (*info->fprintf_func) (info->stream, "%s", opcode->name);
151
448k
  if (opcode->operands[0] != 0)
152
404k
    (*info->fprintf_func) (info->stream, "\t");
153
154
  /* Now extract and print the operands.  */
155
448k
  need_comma = 0;
156
1.29M
  for (opindex = opcode->operands; *opindex != 0; opindex++)
157
849k
    {
158
849k
      const struct alpha_operand *operand = alpha_operands + *opindex;
159
849k
      int value;
160
161
      /* Operands that are marked FAKE are simply ignored.  We
162
   already made sure that the extract function considered
163
   the instruction to be valid.  */
164
849k
      if ((operand->flags & AXP_OPERAND_FAKE) != 0)
165
56.3k
  continue;
166
167
      /* Extract the value from the instruction.  */
168
793k
      if (operand->extract)
169
86.3k
  value = (*operand->extract) (insn, (int *) NULL);
170
707k
      else
171
707k
  {
172
707k
    value = (insn >> operand->shift) & ((1 << operand->bits) - 1);
173
707k
    if (operand->flags & AXP_OPERAND_SIGNED)
174
120k
      {
175
120k
        int signbit = 1 << (operand->bits - 1);
176
120k
        value = (value ^ signbit) - signbit;
177
120k
      }
178
707k
  }
179
180
793k
      if (need_comma &&
181
793k
    ((operand->flags & (AXP_OPERAND_PARENS | AXP_OPERAND_COMMA))
182
410k
     != AXP_OPERAND_PARENS))
183
294k
  {
184
294k
    (*info->fprintf_func) (info->stream, ",");
185
294k
  }
186
793k
      if (operand->flags & AXP_OPERAND_PARENS)
187
146k
  (*info->fprintf_func) (info->stream, "(");
188
189
      /* Print the operand as directed by the flags.  */
190
793k
      if (operand->flags & AXP_OPERAND_IR)
191
417k
  (*info->fprintf_func) (info->stream, "%s", regnames[value]);
192
375k
      else if (operand->flags & AXP_OPERAND_FPR)
193
21.9k
  (*info->fprintf_func) (info->stream, "%s", regnames[value + 32]);
194
353k
      else if (operand->flags & AXP_OPERAND_RELATIVE)
195
86.3k
  (*info->print_address_func) (memaddr + 4 + value, info);
196
267k
      else if (operand->flags & AXP_OPERAND_SIGNED)
197
120k
  (*info->fprintf_func) (info->stream, "%d", value);
198
147k
      else
199
147k
  (*info->fprintf_func) (info->stream, "%#x", value);
200
201
793k
      if (operand->flags & AXP_OPERAND_PARENS)
202
146k
  (*info->fprintf_func) (info->stream, ")");
203
793k
      need_comma = 1;
204
793k
    }
205
206
448k
  return 4;
207
503k
}