Coverage Report

Created: 2024-05-21 06:29

/src/binutils-gdb/opcodes/arm-dis.c
Line
Count
Source (jump to first uncovered line)
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/* Instruction printing code for the ARM
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   Copyright (C) 1994-2024 Free Software Foundation, Inc.
3
   Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4
   Modification by James G. Smith (jsmith@cygnus.co.uk)
5
6
   This file is part of libopcodes.
7
8
   This library is free software; you can redistribute it and/or modify
9
   it under the terms of the GNU General Public License as published by
10
   the Free Software Foundation; either version 3 of the License, or
11
   (at your option) any later version.
12
13
   It is distributed in the hope that it will be useful, but WITHOUT
14
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
16
   License for more details.
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18
   You should have received a copy of the GNU General Public License
19
   along with this program; if not, write to the Free Software
20
   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21
   MA 02110-1301, USA.  */
22
23
#include "sysdep.h"
24
#include <assert.h>
25
26
#include "disassemble.h"
27
#include "opcode/arm.h"
28
#include "opintl.h"
29
#include "safe-ctype.h"
30
#include "libiberty.h"
31
#include "floatformat.h"
32
33
/* FIXME: This shouldn't be done here.  */
34
#include "coff/internal.h"
35
#include "libcoff.h"
36
#include "bfd.h"
37
#include "elf-bfd.h"
38
#include "elf/internal.h"
39
#include "elf/arm.h"
40
#include "mach-o.h"
41
42
/* Cached mapping symbol state.  */
43
enum map_type
44
{
45
  MAP_ARM,
46
  MAP_THUMB,
47
  MAP_DATA
48
};
49
50
struct arm_private_data
51
{
52
  /* The features to use when disassembling optional instructions.  */
53
  arm_feature_set features;
54
55
  /* Track the last type (although this doesn't seem to be useful) */
56
  enum map_type last_type;
57
58
  /* Tracking symbol table information */
59
  int last_mapping_sym;
60
61
  /* The end range of the current range being disassembled.  */
62
  bfd_vma last_stop_offset;
63
  bfd_vma last_mapping_addr;
64
};
65
66
enum mve_instructions
67
{
68
  MVE_VPST,
69
  MVE_VPT_FP_T1,
70
  MVE_VPT_FP_T2,
71
  MVE_VPT_VEC_T1,
72
  MVE_VPT_VEC_T2,
73
  MVE_VPT_VEC_T3,
74
  MVE_VPT_VEC_T4,
75
  MVE_VPT_VEC_T5,
76
  MVE_VPT_VEC_T6,
77
  MVE_VCMP_FP_T1,
78
  MVE_VCMP_FP_T2,
79
  MVE_VCMP_VEC_T1,
80
  MVE_VCMP_VEC_T2,
81
  MVE_VCMP_VEC_T3,
82
  MVE_VCMP_VEC_T4,
83
  MVE_VCMP_VEC_T5,
84
  MVE_VCMP_VEC_T6,
85
  MVE_VDUP,
86
  MVE_VEOR,
87
  MVE_VFMAS_FP_SCALAR,
88
  MVE_VFMA_FP_SCALAR,
89
  MVE_VFMA_FP,
90
  MVE_VFMS_FP,
91
  MVE_VHADD_T1,
92
  MVE_VHADD_T2,
93
  MVE_VHSUB_T1,
94
  MVE_VHSUB_T2,
95
  MVE_VRHADD,
96
  MVE_VLD2,
97
  MVE_VLD4,
98
  MVE_VST2,
99
  MVE_VST4,
100
  MVE_VLDRB_T1,
101
  MVE_VLDRH_T2,
102
  MVE_VLDRB_T5,
103
  MVE_VLDRH_T6,
104
  MVE_VLDRW_T7,
105
  MVE_VSTRB_T1,
106
  MVE_VSTRH_T2,
107
  MVE_VSTRB_T5,
108
  MVE_VSTRH_T6,
109
  MVE_VSTRW_T7,
110
  MVE_VLDRB_GATHER_T1,
111
  MVE_VLDRH_GATHER_T2,
112
  MVE_VLDRW_GATHER_T3,
113
  MVE_VLDRD_GATHER_T4,
114
  MVE_VLDRW_GATHER_T5,
115
  MVE_VLDRD_GATHER_T6,
116
  MVE_VSTRB_SCATTER_T1,
117
  MVE_VSTRH_SCATTER_T2,
118
  MVE_VSTRW_SCATTER_T3,
119
  MVE_VSTRD_SCATTER_T4,
120
  MVE_VSTRW_SCATTER_T5,
121
  MVE_VSTRD_SCATTER_T6,
122
  MVE_VCVT_FP_FIX_VEC,
123
  MVE_VCVT_BETWEEN_FP_INT,
124
  MVE_VCVT_FP_HALF_FP,
125
  MVE_VCVT_FROM_FP_TO_INT,
126
  MVE_VRINT_FP,
127
  MVE_VMOV_HFP_TO_GP,
128
  MVE_VMOV_GP_TO_VEC_LANE,
129
  MVE_VMOV_IMM_TO_VEC,
130
  MVE_VMOV_VEC_TO_VEC,
131
  MVE_VMOV2_VEC_LANE_TO_GP,
132
  MVE_VMOV2_GP_TO_VEC_LANE,
133
  MVE_VMOV_VEC_LANE_TO_GP,
134
  MVE_VMVN_IMM,
135
  MVE_VMVN_REG,
136
  MVE_VORR_IMM,
137
  MVE_VORR_REG,
138
  MVE_VORN,
139
  MVE_VBIC_IMM,
140
  MVE_VBIC_REG,
141
  MVE_VMOVX,
142
  MVE_VMOVL,
143
  MVE_VMOVN,
144
  MVE_VMULL_INT,
145
  MVE_VMULL_POLY,
146
  MVE_VQDMULL_T1,
147
  MVE_VQDMULL_T2,
148
  MVE_VQMOVN,
149
  MVE_VQMOVUN,
150
  MVE_VADDV,
151
  MVE_VMLADAV_T1,
152
  MVE_VMLADAV_T2,
153
  MVE_VMLALDAV,
154
  MVE_VMLAS,
155
  MVE_VADDLV,
156
  MVE_VMLSDAV_T1,
157
  MVE_VMLSDAV_T2,
158
  MVE_VMLSLDAV,
159
  MVE_VRMLALDAVH,
160
  MVE_VRMLSLDAVH,
161
  MVE_VQDMLADH,
162
  MVE_VQRDMLADH,
163
  MVE_VQDMLAH,
164
  MVE_VQRDMLAH,
165
  MVE_VQDMLASH,
166
  MVE_VQRDMLASH,
167
  MVE_VQDMLSDH,
168
  MVE_VQRDMLSDH,
169
  MVE_VQDMULH_T1,
170
  MVE_VQRDMULH_T2,
171
  MVE_VQDMULH_T3,
172
  MVE_VQRDMULH_T4,
173
  MVE_VDDUP,
174
  MVE_VDWDUP,
175
  MVE_VIWDUP,
176
  MVE_VIDUP,
177
  MVE_VCADD_FP,
178
  MVE_VCADD_VEC,
179
  MVE_VHCADD,
180
  MVE_VCMLA_FP,
181
  MVE_VCMUL_FP,
182
  MVE_VQRSHL_T1,
183
  MVE_VQRSHL_T2,
184
  MVE_VQRSHRN,
185
  MVE_VQRSHRUN,
186
  MVE_VQSHL_T1,
187
  MVE_VQSHL_T2,
188
  MVE_VQSHLU_T3,
189
  MVE_VQSHL_T4,
190
  MVE_VQSHRN,
191
  MVE_VQSHRUN,
192
  MVE_VRSHL_T1,
193
  MVE_VRSHL_T2,
194
  MVE_VRSHR,
195
  MVE_VRSHRN,
196
  MVE_VSHL_T1,
197
  MVE_VSHL_T2,
198
  MVE_VSHL_T3,
199
  MVE_VSHLC,
200
  MVE_VSHLL_T1,
201
  MVE_VSHLL_T2,
202
  MVE_VSHR,
203
  MVE_VSHRN,
204
  MVE_VSLI,
205
  MVE_VSRI,
206
  MVE_VADC,
207
  MVE_VABAV,
208
  MVE_VABD_FP,
209
  MVE_VABD_VEC,
210
  MVE_VABS_FP,
211
  MVE_VABS_VEC,
212
  MVE_VADD_FP_T1,
213
  MVE_VADD_FP_T2,
214
  MVE_VADD_VEC_T1,
215
  MVE_VADD_VEC_T2,
216
  MVE_VSBC,
217
  MVE_VSUB_FP_T1,
218
  MVE_VSUB_FP_T2,
219
  MVE_VSUB_VEC_T1,
220
  MVE_VSUB_VEC_T2,
221
  MVE_VAND,
222
  MVE_VBRSR,
223
  MVE_VCLS,
224
  MVE_VCLZ,
225
  MVE_VCTP,
226
  MVE_VMAX,
227
  MVE_VMAXA,
228
  MVE_VMAXNM_FP,
229
  MVE_VMAXNMA_FP,
230
  MVE_VMAXNMV_FP,
231
  MVE_VMAXNMAV_FP,
232
  MVE_VMAXV,
233
  MVE_VMAXAV,
234
  MVE_VMIN,
235
  MVE_VMINA,
236
  MVE_VMINNM_FP,
237
  MVE_VMINNMA_FP,
238
  MVE_VMINNMV_FP,
239
  MVE_VMINNMAV_FP,
240
  MVE_VMINV,
241
  MVE_VMINAV,
242
  MVE_VMLA,
243
  MVE_VMUL_FP_T1,
244
  MVE_VMUL_FP_T2,
245
  MVE_VMUL_VEC_T1,
246
  MVE_VMUL_VEC_T2,
247
  MVE_VMULH,
248
  MVE_VRMULH,
249
  MVE_VNEG_FP,
250
  MVE_VNEG_VEC,
251
  MVE_VPNOT,
252
  MVE_VPSEL,
253
  MVE_VQABS,
254
  MVE_VQADD_T1,
255
  MVE_VQADD_T2,
256
  MVE_VQSUB_T1,
257
  MVE_VQSUB_T2,
258
  MVE_VQNEG,
259
  MVE_VREV16,
260
  MVE_VREV32,
261
  MVE_VREV64,
262
  MVE_LSLL,
263
  MVE_LSLLI,
264
  MVE_LSRL,
265
  MVE_ASRL,
266
  MVE_ASRLI,
267
  MVE_SQRSHRL,
268
  MVE_SQRSHR,
269
  MVE_UQRSHL,
270
  MVE_UQRSHLL,
271
  MVE_UQSHL,
272
  MVE_UQSHLL,
273
  MVE_URSHRL,
274
  MVE_URSHR,
275
  MVE_SRSHRL,
276
  MVE_SRSHR,
277
  MVE_SQSHLL,
278
  MVE_SQSHL,
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  MVE_CINC,
280
  MVE_CINV,
281
  MVE_CNEG,
282
  MVE_CSINC,
283
  MVE_CSINV,
284
  MVE_CSET,
285
  MVE_CSETM,
286
  MVE_CSNEG,
287
  MVE_CSEL,
288
  MVE_NONE
289
};
290
291
enum mve_unpredictable
292
{
293
  UNPRED_IT_BLOCK,    /* Unpredictable because mve insn in it block.
294
         */
295
  UNPRED_FCA_0_FCB_1,   /* Unpredictable because fcA = 0 and
296
           fcB = 1 (vpt).  */
297
  UNPRED_R13,     /* Unpredictable because r13 (sp) or
298
           r15 (sp) used.  */
299
  UNPRED_R15,     /* Unpredictable because r15 (pc) is used.  */
300
  UNPRED_Q_GT_4,    /* Unpredictable because
301
           vec reg start > 4 (vld4/st4).  */
302
  UNPRED_Q_GT_6,    /* Unpredictable because
303
           vec reg start > 6 (vld2/st2).  */
304
  UNPRED_R13_AND_WB,    /* Unpredictable becase gp reg = r13
305
           and WB bit = 1.  */
306
  UNPRED_Q_REGS_EQUAL,    /* Unpredictable because vector registers are
307
           equal.  */
308
  UNPRED_OS,      /* Unpredictable because offset scaled == 1.  */
309
  UNPRED_GP_REGS_EQUAL,   /* Unpredictable because gp registers are the
310
           same.  */
311
  UNPRED_Q_REGS_EQ_AND_SIZE_1,  /* Unpredictable because q regs equal and
312
           size = 1.  */
313
  UNPRED_Q_REGS_EQ_AND_SIZE_2,  /* Unpredictable because q regs equal and
314
           size = 2.  */
315
  UNPRED_NONE     /* No unpredictable behavior.  */
316
};
317
318
enum mve_undefined
319
{
320
  UNDEF_SIZE,     /* undefined size.  */
321
  UNDEF_SIZE_0,     /* undefined because size == 0.  */
322
  UNDEF_SIZE_2,     /* undefined because size == 2.  */
323
  UNDEF_SIZE_3,     /* undefined because size == 3.  */
324
  UNDEF_SIZE_LE_1,    /* undefined because size <= 1.  */
325
  UNDEF_SIZE_NOT_0,   /* undefined because size != 0.  */
326
  UNDEF_SIZE_NOT_2,   /* undefined because size != 2.  */
327
  UNDEF_SIZE_NOT_3,   /* undefined because size != 3.  */
328
  UNDEF_NOT_UNS_SIZE_0,   /* undefined because U == 0 and
329
           size == 0.  */
330
  UNDEF_NOT_UNS_SIZE_1,   /* undefined because U == 0 and
331
           size == 1.  */
332
  UNDEF_NOT_UNSIGNED,   /* undefined because U == 0.  */
333
  UNDEF_VCVT_IMM6,    /* imm6 < 32.  */
334
  UNDEF_VCVT_FSI_IMM6,    /* fsi = 0 and 32 >= imm6 <= 47.  */
335
  UNDEF_BAD_OP1_OP2,    /* undefined with op2 = 2 and
336
           op1 == (0 or 1).  */
337
  UNDEF_BAD_U_OP1_OP2,    /* undefined with U = 1 and
338
           op2 == 0 and op1 == (0 or 1).  */
339
  UNDEF_OP_0_BAD_CMODE,   /* undefined because op == 0 and cmode
340
           in {0xx1, x0x1}.  */
341
  UNDEF_XCHG_UNS,   /* undefined because X == 1 and U == 1.  */
342
  UNDEF_NONE      /* no undefined behavior.  */
343
};
344
345
struct opcode32
346
{
347
  arm_feature_set arch;   /* Architecture defining this insn.  */
348
  unsigned long value;    /* If arch is 0 then value is a sentinel.  */
349
  unsigned long mask;   /* Recognise insn if (op & mask) == value.  */
350
  const char *  assembler;  /* How to disassemble this insn.  */
351
};
352
353
struct cdeopcode32
354
{
355
  arm_feature_set arch;   /* Architecture defining this insn.  */
356
  uint8_t coproc_shift;   /* coproc is this far into op.  */
357
  uint16_t coproc_mask;   /* Length of coproc field in op.  */
358
  unsigned long value;    /* If arch is 0 then value is a sentinel.  */
359
  unsigned long mask;   /* Recognise insn if (op & mask) == value.  */
360
  const char *  assembler;  /* How to disassemble this insn.  */
361
};
362
363
/* MVE opcodes.  */
364
365
struct mopcode32
366
{
367
  arm_feature_set arch;   /* Architecture defining this insn.  */
368
  enum mve_instructions mve_op;  /* Specific mve instruction for faster
369
            decoding.  */
370
  unsigned long value;    /* If arch is 0 then value is a sentinel.  */
371
  unsigned long mask;   /* Recognise insn if (op & mask) == value.  */
372
  const char *  assembler;  /* How to disassemble this insn.  */
373
};
374
375
enum isa {
376
  ANY,
377
  T32,
378
  ARM
379
};
380
381
382
/* Shared (between Arm and Thumb mode) opcode.  */
383
struct sopcode32
384
{
385
  enum isa isa;     /* Execution mode instruction availability.  */
386
  arm_feature_set arch;   /* Architecture defining this insn.  */
387
  unsigned long value;    /* If arch is 0 then value is a sentinel.  */
388
  unsigned long mask;   /* Recognise insn if (op & mask) == value.  */
389
  const char *  assembler;  /* How to disassemble this insn.  */
390
};
391
392
struct opcode16
393
{
394
  arm_feature_set arch;   /* Architecture defining this insn.  */
395
  unsigned short value, mask; /* Recognise insn if (op & mask) == value.  */
396
  const char *assembler;  /* How to disassemble this insn.  */
397
};
398
399
/* print_insn_coprocessor recognizes the following format control codes:
400
401
   %%     %
402
403
   %c     print condition code (always bits 28-31 in ARM mode)
404
   %b     print condition code allowing cp_num == 9
405
   %q     print shifter argument
406
   %u     print condition code (unconditional in ARM mode,
407
                          UNPREDICTABLE if not AL in Thumb)
408
   %A     print address for ldc/stc/ldf/stf instruction
409
   %B     print vstm/vldm register list
410
   %C     print vscclrm register list
411
   %I                   print cirrus signed shift immediate: bits 0..3|4..6
412
   %J     print register for VLDR instruction
413
   %K     print address for VLDR instruction
414
   %F     print the COUNT field of a LFM/SFM instruction.
415
   %P     print floating point precision in arithmetic insn
416
   %Q     print floating point precision in ldf/stf insn
417
   %R     print floating point rounding mode
418
419
   %<bitfield>c   print as a condition code (for vsel)
420
   %<bitfield>r   print as an ARM register
421
   %<bitfield>R   as %<>r but r15 is UNPREDICTABLE
422
   %<bitfield>ru        as %<>r but each u register must be unique.
423
   %<bitfield>d   print the bitfield in decimal
424
   %<bitfield>k   print immediate for VFPv3 conversion instruction
425
   %<bitfield>x   print the bitfield in hex
426
   %<bitfield>X   print the bitfield as 1 hex digit without leading "0x"
427
   %<bitfield>f   print a floating point constant if >7 else a
428
      floating point register
429
   %<bitfield>w         print as an iWMMXt width field - [bhwd]ss/us
430
   %<bitfield>g         print as an iWMMXt 64-bit register
431
   %<bitfield>G         print as an iWMMXt general purpose or control register
432
   %<bitfield>D   print as a NEON D register
433
   %<bitfield>Q   print as a NEON Q register
434
   %<bitfield>V   print as a NEON D or Q register
435
   %<bitfield>E   print a quarter-float immediate value
436
437
   %y<code>   print a single precision VFP reg.
438
        Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
439
   %z<code>   print a double precision VFP reg
440
        Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
441
442
   %<bitfield>'c  print specified char iff bitfield is all ones
443
   %<bitfield>`c  print specified char iff bitfield is all zeroes
444
   %<bitfield>?ab...    select from array of values in big endian order
445
446
   %L     print as an iWMMXt N/M width field.
447
   %Z     print the Immediate of a WSHUFH instruction.
448
   %l     like 'A' except use byte offsets for 'B' & 'H'
449
      versions.
450
   %i     print 5-bit immediate in bits 8,3..0
451
      (print "32" when 0)
452
   %r     print register offset address for wldt/wstr instruction.  */
453
454
enum opcode_sentinel_enum
455
{
456
  SENTINEL_IWMMXT_START = 1,
457
  SENTINEL_IWMMXT_END,
458
  SENTINEL_GENERIC_START
459
} opcode_sentinels;
460
461
#define UNDEFINED_INSTRUCTION      "\t\t@ <UNDEFINED> instruction: %0-31x"
462
26.3k
#define UNKNOWN_INSTRUCTION_32BIT  "\t\t@ <UNDEFINED> instruction: %08x"
463
0
#define UNKNOWN_INSTRUCTION_16BIT  "\t\t@ <UNDEFINED> instruction: %04x"
464
160k
#define UNPREDICTABLE_INSTRUCTION  "\t@ <UNPREDICTABLE>"
465
466
/* Common coprocessor opcodes shared between Arm and Thumb-2.  */
467
468
/* print_insn_cde recognizes the following format control codes:
469
470
   %%     %
471
472
   %a     print 'a' iff bit 28 is 1
473
   %p     print bits 8-10 as coprocessor
474
   %<bitfield>d   print as decimal
475
   %<bitfield>r   print as an ARM register
476
   %<bitfield>n   print as an ARM register but r15 is APSR_nzcv
477
   %<bitfield>T   print as an ARM register + 1
478
   %<bitfield>R   as %r but r13 is UNPREDICTABLE
479
   %<bitfield>S   as %r but rX where X > 10 is UNPREDICTABLE
480
   %j     print immediate taken from bits (16..21,7,0..5)
481
   %k     print immediate taken from bits (20..21,7,0..5).
482
   %l     print immediate taken from bits (20..22,7,4..5).  */
483
484
/* At the moment there is only one valid position for the coprocessor number,
485
   and hence that's encoded in the macro below.  */
486
#define CDE_OPCODE(ARCH, VALUE, MASK, ASM) \
487
  { ARCH, 8, 7, VALUE, MASK, ASM }
488
static const struct cdeopcode32 cde_opcodes[] =
489
{
490
  /* Custom Datapath Extension instructions.  */
491
  CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
492
        0xee000000, 0xefc00840,
493
        "cx1%a\t%p, %12-15n, %{I:#%0-5,7,16-21d%}"),
494
  CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
495
        0xee000040, 0xefc00840,
496
        "cx1d%a\t%p, %12-15S, %12-15T, %{I:#%0-5,7,16-21d%}"),
497
498
  CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
499
        0xee400000, 0xefc00840,
500
        "cx2%a\t%p, %12-15n, %16-19n, %{I:#%0-5,7,20-21d%}"),
501
  CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
502
        0xee400040, 0xefc00840,
503
        "cx2d%a\t%p, %12-15S, %12-15T, %16-19n, %{I:#%0-5,7,20-21d%}"),
504
505
  CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
506
        0xee800000, 0xef800840,
507
        "cx3%a\t%p, %0-3n, %16-19n, %12-15n, %{I:#%4-5,7,20-22d%}"),
508
  CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
509
        0xee800040, 0xef800840,
510
       "cx3d%a\t%p, %0-3S, %0-3T, %16-19n, %12-15n, %{I:#%4-5,7,20-22d%}"),
511
512
  CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
513
        0xec200000, 0xeeb00840,
514
        "vcx1%a\t%p, %12-15,22V, %{I:#%0-5,7,16-19d%}"),
515
  CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
516
        0xec200040, 0xeeb00840,
517
        "vcx1%a\t%p, %12-15,22V, %{I:#%0-5,7,16-19,24d%}"),
518
519
  CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
520
        0xec300000, 0xeeb00840,
521
        "vcx2%a\t%p, %12-15,22V, %0-3,5V, %{I:#%4,7,16-19d%}"),
522
  CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
523
        0xec300040, 0xeeb00840,
524
        "vcx2%a\t%p, %12-15,22V, %0-3,5V, %{I:#%4,7,16-19,24d%}"),
525
526
  CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
527
        0xec800000, 0xee800840,
528
        "vcx3%a\t%p, %12-15,22V, %16-19,7V, %0-3,5V, %{I:#%4,20-21d%}"),
529
  CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
530
        0xec800040, 0xee800840,
531
        "vcx3%a\t%p, %12-15,22V, %16-19,7V, %0-3,5V, %{I:#%4,20-21,24d%}"),
532
533
  CDE_OPCODE (ARM_FEATURE_CORE_LOW (0), 0, 0, 0)
534
535
};
536
537
static const struct sopcode32 coprocessor_opcodes[] =
538
{
539
  /* XScale instructions.  */
540
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
541
    0x0e200010, 0x0fff0ff0,
542
    "mia%c\t%{R:acc0%}, %0-3r, %12-15r"},
543
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
544
    0x0e280010, 0x0fff0ff0,
545
    "miaph%c\t%{R:acc0%}, %0-3r, %12-15r"},
546
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
547
    0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\t%{R:acc0%}, %0-3r, %12-15r"},
548
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
549
    0x0c400000, 0x0ff00fff, "mar%c\t%{R:acc0%}, %12-15r, %16-19r"},
550
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
551
    0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, %{R:acc0%}"},
552
553
  /* Intel Wireless MMX technology instructions.  */
554
  {ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START, 0, "" },
555
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT),
556
    0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
557
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
558
    0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
559
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
560
    0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, %{I:#%0-2d%}"},
561
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
562
    0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, %{I:#%0-2d%}"},
563
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
564
    0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, %{I:#%0-2d%}"},
565
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
566
    0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
567
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
568
    0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
569
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
570
    0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
571
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
572
    0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
573
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
574
    0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
575
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
576
    0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
577
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
578
    0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
579
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
580
    0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
581
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
582
    0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
583
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
584
    0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
585
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
586
    0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
587
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
588
    0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
589
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
590
    0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
591
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
592
    0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
593
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
594
    0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
595
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
596
    0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, %{I:#%20-22d%}"},
597
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
598
    0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
599
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
600
    0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
601
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
602
    0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
603
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
604
    0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"},
605
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
606
    0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
607
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
608
    0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
609
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
610
    0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"},
611
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
612
    0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
613
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
614
    0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
615
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
616
    0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
617
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
618
    0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"},
619
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
620
    0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"},
621
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
622
    0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
623
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
624
    0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, %{I:#%21-23d%}"},
625
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
626
    0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
627
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
628
    0x0e800120, 0x0f800ff0,
629
    "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
630
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
631
    0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
632
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
633
    0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"},
634
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
635
    0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"},
636
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
637
    0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"},
638
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
639
    0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"},
640
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
641
    0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"},
642
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
643
    0x0e8000a0, 0x0f800ff0,
644
    "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
645
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
646
    0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"},
647
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
648
    0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"},
649
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
650
    0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
651
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
652
    0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
653
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
654
    0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, %{I:#%i%}"},
655
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
656
    0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
657
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
658
    0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"},
659
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
660
    0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
661
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
662
    0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, %{I:#%Z%}"},
663
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
664
    0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, %{I:#%i%}"},
665
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
666
    0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
667
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
668
    0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
669
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
670
    0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, %{I:#%i%}"},
671
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
672
    0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
673
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
674
    0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
675
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
676
    0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, %{I:#%i%}"},
677
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
678
    0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
679
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
680
    0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
681
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
682
    0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"},
683
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
684
    0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
685
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
686
    0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
687
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
688
    0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
689
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
690
    0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"},
691
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
692
    0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"},
693
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
694
    0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"},
695
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
696
    0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"},
697
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
698
    0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
699
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
700
    0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
701
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
702
    0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
703
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
704
    0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
705
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
706
    0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
707
  {ANY, ARM_FEATURE_CORE_LOW (0),
708
    SENTINEL_IWMMXT_END, 0, "" },
709
710
  /* Floating point coprocessor (FPA) instructions.  */
711
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
712
    0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
713
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
714
    0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
715
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
716
    0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
717
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
718
    0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
719
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
720
    0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
721
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
722
    0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
723
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
724
    0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
725
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
726
    0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
727
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
728
    0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
729
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
730
    0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
731
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
732
    0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
733
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
734
    0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
735
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
736
    0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
737
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
738
    0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
739
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
740
    0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
741
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
742
    0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
743
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
744
    0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
745
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
746
    0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
747
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
748
    0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
749
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
750
    0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
751
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
752
    0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
753
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
754
    0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
755
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
756
    0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
757
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
758
    0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
759
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
760
    0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
761
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
762
    0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
763
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
764
    0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
765
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
766
    0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
767
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
768
    0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
769
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
770
    0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
771
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
772
    0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
773
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
774
    0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
775
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
776
    0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
777
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
778
    0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
779
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
780
    0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
781
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
782
    0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
783
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
784
    0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
785
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
786
    0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
787
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
788
    0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
789
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
790
    0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
791
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
792
    0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
793
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
794
    0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
795
  {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
796
    0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
797
798
  /* Armv8.1-M Mainline instructions.  */
799
  {T32, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
800
    0xec9f0b00, 0xffbf0f01, "vscclrm%c\t%C"},
801
  {T32, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
802
    0xec9f0a00, 0xffbf0f00, "vscclrm%c\t%C"},
803
804
  /* ARMv8-M Mainline Security Extensions instructions.  */
805
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
806
    0xec300a00, 0xfff0ffff, "vlldm\t%16-19r"},
807
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
808
    0xec200a00, 0xfff0ffff, "vlstm\t%16-19r"},
809
810
  /* Register load/store.  */
811
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
812
    0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
813
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
814
    0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"},
815
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
816
    0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"},
817
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
818
    0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
819
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
820
    0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"},
821
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
822
    0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
823
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
824
    0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"},
825
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
826
    0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"},
827
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
828
    0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"},
829
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
830
    0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"},
831
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
832
    0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"},
833
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
834
    0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"},
835
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
836
    0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"},
837
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
838
    0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"},
839
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
840
    0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"},
841
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
842
    0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"},
843
  {ANY, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN),
844
    0xec100f80, 0xfe101f80, "vldr%c\t%J, %K"},
845
  {ANY, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN),
846
    0xec000f80, 0xfe101f80, "vstr%c\t%J, %K"},
847
848
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
849
    0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t@ Deprecated"},
850
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
851
    0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t@ Deprecated"},
852
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
853
    0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t@ Deprecated"},
854
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
855
    0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t@ Deprecated"},
856
857
  /* Data transfer between ARM and NEON registers.  */
858
  {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
859
    0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
860
  {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
861
    0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
862
  {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
863
    0x0e000b10, 0x0fd00f70, "vmov%c.32\t%{R:%16-19,7D[%21d]%}, %12-15r"},
864
  {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
865
    0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %{R:%16-19,7D[%21d]%}"},
866
  {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
867
    0x0e000b30, 0x0fd00f30, "vmov%c.16\t%{R:%16-19,7D[%6,21d]%}, %12-15r"},
868
  {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
869
    0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %{R:%16-19,7D[%6,21d]%}"},
870
  {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
871
    0x0e400b10, 0x0fd00f10, "vmov%c.8\t%{R:%16-19,7D[%5,6,21d]%}, %12-15r"},
872
  {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
873
    0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %{R:%16-19,7D[%5,6,21d]%}"},
874
  /* Half-precision conversion instructions.  */
875
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
876
    0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"},
877
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
878
    0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"},
879
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
880
    0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"},
881
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
882
    0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"},
883
884
  /* Floating point coprocessor (VFP) instructions.  */
885
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
886
    0x0ee00a10, 0x0fff0fff, "vmsr%c\t%{R:fpsid%}, %12-15r"},
887
  {ANY, ARM_FEATURE (0, ARM_EXT2_V8_1M_MAIN, FPU_VFP_EXT_V1xD),
888
    0x0ee10a10, 0x0fff0fff, "vmsr%c\t%{R:fpscr%}, %12-15r"},
889
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
890
    0x0ee20a10, 0x0fff0fff, "vmsr%c\t%{R:fpscr_nzcvqc%}, %12-15r"},
891
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
892
    0x0ee60a10, 0x0fff0fff, "vmsr%c\t%{R:mvfr1%}, %12-15r"},
893
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
894
    0x0ee70a10, 0x0fff0fff, "vmsr%c\t%{R:mvfr0%}, %12-15r"},
895
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
896
    0x0ee50a10, 0x0fff0fff, "vmsr%c\t%{R:mvfr2%}, %12-15r"},
897
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
898
    0x0ee80a10, 0x0fff0fff, "vmsr%c\t%{R:fpexc%}, %12-15r"},
899
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
900
    0x0ee90a10, 0x0fff0fff, "vmsr%c\t%{R:fpinst%}, %12-15r\t@ Impl def"},
901
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
902
    0x0eea0a10, 0x0fff0fff, "vmsr%c\t%{R:fpinst2%}, %12-15r\t@ Impl def"},
903
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
904
    0x0eec0a10, 0x0fff0fff, "vmsr%c\t%{R:vpr%}, %12-15r"},
905
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
906
    0x0eed0a10, 0x0fff0fff, "vmsr%c\t%{R:p0%}, %12-15r"},
907
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
908
    0x0eee0a10, 0x0fff0fff, "vmsr%c\t%{R:fpcxt_ns%}, %12-15r"},
909
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
910
    0x0eef0a10, 0x0fff0fff, "vmsr%c\t%{R:fpcxt_s%}, %12-15r"},
911
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
912
    0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpsid%}"},
913
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
914
    0x0ef1fa10, 0x0fffffff, "vmrs%c\t%{R:APSR_nzcv%}, %{R:fpscr%}"},
915
  {ANY, ARM_FEATURE (0, ARM_EXT2_V8_1M_MAIN, FPU_VFP_EXT_V1xD),
916
    0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpscr%}"},
917
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
918
    0x0ef20a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpscr_nzcvqc%}"},
919
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
920
    0x0ef50a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:mvfr2%}"},
921
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
922
    0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:mvfr1%}"},
923
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
924
    0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:mvfr0%}"},
925
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
926
    0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpexc%}"},
927
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
928
    0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpinst%}\t@ Impl def"},
929
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
930
    0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpinst2%}\t@ Impl def"},
931
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
932
    0x0efc0a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:vpr%}"},
933
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
934
    0x0efd0a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:p0%}"},
935
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
936
    0x0efe0a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpcxt_ns%}"},
937
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
938
    0x0eff0a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpcxt_s%}"},
939
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
940
    0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%{I:%21d%}], %12-15r"},
941
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
942
    0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%{I:%21d%}]"},
943
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
944
    0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"},
945
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
946
    0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"},
947
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
948
    0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"},
949
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
950
    0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"},
951
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
952
    0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, %{I:#0.0%}"},
953
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
954
    0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, %{I:#0.0%}"},
955
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
956
    0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"},
957
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
958
    0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"},
959
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
960
    0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"},
961
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
962
    0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"},
963
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
964
    0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"},
965
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
966
    0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"},
967
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
968
    0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"},
969
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
970
    0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"},
971
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
972
    0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"},
973
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
974
    0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"},
975
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
976
    0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"},
977
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
978
    0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"},
979
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
980
    0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"},
981
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
982
    0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"},
983
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
984
    0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, %{I:#%5,0-3k%}"},
985
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
986
    0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, %{I:#%5,0-3k%}"},
987
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
988
    0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"},
989
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
990
    0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"},
991
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
992
    0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, %{I:#%5,0-3k%}"},
993
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
994
    0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, %{I:#%5,0-3k%}"},
995
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
996
    0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"},
997
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
998
    0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, %{I:#%0-3,16-19E%}"},
999
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
1000
    0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, %{I:#%0-3,16-19E%}"},
1001
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
1002
    0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"},
1003
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
1004
    0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"},
1005
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
1006
    0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"},
1007
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
1008
    0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"},
1009
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
1010
    0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"},
1011
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
1012
    0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"},
1013
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
1014
    0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"},
1015
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
1016
    0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"},
1017
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
1018
    0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"},
1019
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
1020
    0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"},
1021
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
1022
    0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"},
1023
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
1024
    0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"},
1025
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
1026
    0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"},
1027
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
1028
    0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"},
1029
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
1030
    0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"},
1031
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
1032
    0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"},
1033
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
1034
    0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"},
1035
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
1036
    0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"},
1037
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
1038
    0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"},
1039
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
1040
    0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"},
1041
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
1042
    0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"},
1043
1044
  /* VFP Fused multiply add instructions.  */
1045
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
1046
    0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"},
1047
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
1048
    0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"},
1049
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
1050
    0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"},
1051
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
1052
    0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"},
1053
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
1054
    0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"},
1055
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
1056
    0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"},
1057
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
1058
    0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"},
1059
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
1060
    0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"},
1061
1062
  /* FP v5.  */
1063
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1064
    0xfe000a00, 0xff800f50, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
1065
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1066
    0xfe000b00, 0xff800f50, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
1067
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1068
    0xfe800a00, 0xffb00f50, "vmaxnm%u.f32\t%y1, %y2, %y0"},
1069
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1070
    0xfe800b00, 0xffb00f50, "vmaxnm%u.f64\t%z1, %z2, %z0"},
1071
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1072
    0xfe800a40, 0xffb00f50, "vminnm%u.f32\t%y1, %y2, %y0"},
1073
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1074
    0xfe800b40, 0xffb00f50, "vminnm%u.f64\t%z1, %z2, %z0"},
1075
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1076
    0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"},
1077
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1078
    0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"},
1079
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1080
    0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"},
1081
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1082
    0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"},
1083
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1084
    0xfeb80a40, 0xffbc0fd0, "vrint%16-17?mpna%u.f32\t%y1, %y0"},
1085
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1086
    0xfeb80b40, 0xffbc0fd0, "vrint%16-17?mpna%u.f64\t%z1, %z0"},
1087
1088
  {ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START, 0, "" },
1089
  /* ARMv8.3 AdvSIMD instructions in the space of coprocessor 8.  */
1090
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1091
    0xfc800800, 0xfeb00f10, "vcadd%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, %{I:#%24?29%24'70%}"},
1092
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1093
    0xfc900800, 0xfeb00f10, "vcadd%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, %{I:#%24?29%24'70%}"},
1094
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1095
    0xfc200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, %{I:#%23'90%}"},
1096
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1097
    0xfd200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, %{I:#%23?21%23?780%}"},
1098
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1099
    0xfc300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, %{I:#%23'90%}"},
1100
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1101
    0xfd300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, %{I:#%23?21%23?780%}"},
1102
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1103
    0xfe000800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %{R:%0-3D[%5?10]%}, %{I:#%20'90%}"},
1104
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1105
    0xfe200800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %{R:%0-3D[%5?10]%}, %{I:#%20?21%20?780%}"},
1106
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1107
    0xfe800800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %{R:%0-3,5D[0]%}, %{I:#%20'90%}"},
1108
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1109
    0xfea00800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %{R:%0-3,5D[0]%}, %{I:#%20?21%20?780%}"},
1110
1111
  /* BFloat16 instructions.  */
1112
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1113
    0x0eb30940, 0x0fbf0f50, "vcvt%7?tb%b.bf16.f32\t%y1, %y0"},
1114
1115
  /* Dot Product instructions in the space of coprocessor 13.  */
1116
  {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
1117
    0xfc200d00, 0xffb00f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3,5V"},
1118
  {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
1119
    0xfe200d00, 0xff200f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %{R:%0-3D[%5?10]%}"},
1120
1121
  /* ARMv8.2 FMAC Long instructions in the space of coprocessor 8.  */
1122
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1123
    0xfc200810, 0xffb00f50, "vfmal.f16\t%12-15,22D, %{R:s%7,16-19d%}, %{R:s%5,0-3d%}"},
1124
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1125
    0xfca00810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, %{R:s%7,16-19d%}, %{R:s%5,0-3d%}"},
1126
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1127
    0xfc200850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, %{R:d%16-19,7d%}, %{R:d%0-3,5d%}"},
1128
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1129
    0xfca00850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, %{R:d%16-19,7d%}, %{R:d%0-3,5d%}"},
1130
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1131
    0xfe000810, 0xffb00f50, "vfmal.f16\t%12-15,22D, %{R:s%7,16-19d%}, %{R:s%5,0-2d[%3d]%}"},
1132
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1133
    0xfe100810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, %{R:s%7,16-19d%}, %{R:s%5,0-2d[%3d]%}"},
1134
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1135
    0xfe000850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, %{R:d%16-19,7d%}, %{R:d%0-2d[%3,5d]%}"},
1136
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1137
    0xfe100850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, %{R:d%16-19,7d%}, %{R:d%0-2d[%3,5d]%}"},
1138
1139
  /* ARMv8.2 half-precision Floating point coprocessor 9 (VFP) instructions.
1140
     cp_num: bit <11:8> == 0b1001.
1141
     cond: bit <31:28> == 0b1110, otherwise, it's UNPREDICTABLE.  */
1142
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1143
    0x0eb009c0, 0x0fbf0fd0, "vabs%c.f16\t%y1, %y0"},
1144
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1145
    0x0e300900, 0x0fb00f50, "vadd%c.f16\t%y1, %y2, %y0"},
1146
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1147
    0x0eb40940, 0x0fbf0f50, "vcmp%7'e%c.f16\t%y1, %y0"},
1148
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1149
    0x0eb50940, 0x0fbf0f70, "vcmp%7'e%c.f16\t%y1, %{I:#0.0%}"},
1150
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1151
    0x0eba09c0, 0x0fbe0fd0, "vcvt%c.f16.%16?us%7?31%7?26\t%y1, %y1, %{I:#%5,0-3k%}"},
1152
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1153
    0x0ebe09c0, 0x0fbe0fd0, "vcvt%c.%16?us%7?31%7?26.f16\t%y1, %y1, %{I:#%5,0-3k%}"},
1154
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1155
    0x0ebc0940, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f16\t%y1, %y0"},
1156
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1157
    0x0eb80940, 0x0fbf0f50, "vcvt%c.f16.%7?su32\t%y1, %y0"},
1158
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1159
    0xfebc0940, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f16\t%y1, %y0"},
1160
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1161
    0x0e800900, 0x0fb00f50, "vdiv%c.f16\t%y1, %y2, %y0"},
1162
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1163
    0x0ea00900, 0x0fb00f50, "vfma%c.f16\t%y1, %y2, %y0"},
1164
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1165
    0x0ea00940, 0x0fb00f50, "vfms%c.f16\t%y1, %y2, %y0"},
1166
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1167
    0x0e900940, 0x0fb00f50, "vfnma%c.f16\t%y1, %y2, %y0"},
1168
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1169
    0x0e900900, 0x0fb00f50, "vfnms%c.f16\t%y1, %y2, %y0"},
1170
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1171
    0xfeb00ac0, 0xffbf0fd0, "vins.f16\t%y1, %y0"},
1172
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1173
    0xfeb00a40, 0xffbf0fd0, "vmovx%c.f16\t%y1, %y0"},
1174
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1175
    0x0d100900, 0x0f300f00, "vldr%c.16\t%y1, %A"},
1176
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1177
    0x0d000900, 0x0f300f00, "vstr%c.16\t%y1, %A"},
1178
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1179
    0xfe800900, 0xffb00f50, "vmaxnm%c.f16\t%y1, %y2, %y0"},
1180
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1181
    0xfe800940, 0xffb00f50, "vminnm%c.f16\t%y1, %y2, %y0"},
1182
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1183
    0x0e000900, 0x0fb00f50, "vmla%c.f16\t%y1, %y2, %y0"},
1184
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1185
    0x0e000940, 0x0fb00f50, "vmls%c.f16\t%y1, %y2, %y0"},
1186
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1187
    0x0e100910, 0x0ff00f7f, "vmov%c.f16\t%12-15r, %y2"},
1188
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1189
    0x0e000910, 0x0ff00f7f, "vmov%c.f16\t%y2, %12-15r"},
1190
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1191
    0xeb00900, 0x0fb00ff0, "vmov%c.f16\t%y1, %{I:#%0-3,16-19E%}"},
1192
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1193
    0x0e200900, 0x0fb00f50, "vmul%c.f16\t%y1, %y2, %y0"},
1194
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1195
    0x0eb10940, 0x0fbf0fd0, "vneg%c.f16\t%y1, %y0"},
1196
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1197
    0x0e100940, 0x0fb00f50, "vnmla%c.f16\t%y1, %y2, %y0"},
1198
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1199
    0x0e100900, 0x0fb00f50, "vnmls%c.f16\t%y1, %y2, %y0"},
1200
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1201
    0x0e200940, 0x0fb00f50, "vnmul%c.f16\t%y1, %y2, %y0"},
1202
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1203
    0x0eb60940, 0x0fbe0f50, "vrint%7,16??xzr%c.f16\t%y1, %y0"},
1204
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1205
    0xfeb80940, 0xffbc0fd0, "vrint%16-17?mpna%u.f16\t%y1, %y0"},
1206
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1207
    0xfe000900, 0xff800f50, "vsel%20-21c%u.f16\t%y1, %y2, %y0"},
1208
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1209
    0x0eb109c0, 0x0fbf0fd0, "vsqrt%c.f16\t%y1, %y0"},
1210
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1211
    0x0e300940, 0x0fb00f50, "vsub%c.f16\t%y1, %y2, %y0"},
1212
1213
  /* ARMv8.3 javascript conversion instruction.  */
1214
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1215
    0x0eb90bc0, 0x0fbf0fd0, "vjcvt%c.s32.f64\t%y1, %z0"},
1216
1217
  {ANY, ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
1218
};
1219
1220
/* Generic coprocessor instructions.  These are only matched if a more specific
1221
   SIMD or co-processor instruction does not match first.  */
1222
1223
static const struct sopcode32 generic_coprocessor_opcodes[] =
1224
{
1225
  /* Generic coprocessor instructions.  */
1226
  {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
1227
    0x0c400000, 0x0ff00000, "mcrr%c\t%{I:%8-11d%}, %{I:%4-7d%}, %12-15R, %16-19r, %{R:cr%0-3d%}"},
1228
  {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
1229
    0x0c500000, 0x0ff00000,
1230
    "mrrc%c\t%{I:%8-11d%}, %{I:%4-7d%}, %12-15Ru, %16-19Ru, %{R:cr%0-3d%}"},
1231
  {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1232
    0x0e000000, 0x0f000010,
1233
    "cdp%c\t%{I:%8-11d%}, %{I:%20-23d%}, %{R:cr%12-15d%}, %{R:cr%16-19d%}, %{R:cr%0-3d%}, {%{I:%5-7d%}}"},
1234
  {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1235
    0x0e10f010, 0x0f10f010,
1236
    "mrc%c\t%{I:%8-11d%}, %{I:%21-23d%}, %{R:APSR_nzcv%}, %{R:cr%16-19d%}, %{R:cr%0-3d%}, {%{I:%5-7d%}}"},
1237
  {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1238
    0x0e100010, 0x0f100010,
1239
    "mrc%c\t%{I:%8-11d%}, %{I:%21-23d%}, %12-15r, %{R:cr%16-19d%}, %{R:cr%0-3d%}, {%{I:%5-7d%}}"},
1240
  {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1241
    0x0e000010, 0x0f100010,
1242
    "mcr%c\t%{I:%8-11d%}, %{I:%21-23d%}, %12-15R, %{R:cr%16-19d%}, %{R:cr%0-3d%}, {%{I:%5-7d%}}"},
1243
  {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1244
    0x0c000000, 0x0e100000, "stc%22'l%c\t%{I:%8-11d%}, %{R:cr%12-15d%}, %A"},
1245
  {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1246
    0x0c100000, 0x0e100000, "ldc%22'l%c\t%{I:%8-11d%}, %{R:cr%12-15d%}, %A"},
1247
1248
  /* V6 coprocessor instructions.  */
1249
  {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1250
    0xfc500000, 0xfff00000,
1251
    "mrrc2%c\t%{I:%8-11d%}, %{I:%4-7d%}, %12-15Ru, %16-19Ru, %{R:cr%0-3d%}"},
1252
  {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1253
    0xfc400000, 0xfff00000,
1254
    "mcrr2%c\t%{I:%8-11d%}, %{I:%4-7d%}, %12-15R, %16-19R, %{R:cr%0-3d%}"},
1255
1256
  /* V5 coprocessor instructions.  */
1257
  {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1258
    0xfc100000, 0xfe100000, "ldc2%22'l%c\t%{I:%8-11d%}, %{R:cr%12-15d%}, %A"},
1259
  {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1260
    0xfc000000, 0xfe100000, "stc2%22'l%c\t%{I:%8-11d%}, %{R:cr%12-15d%}, %A"},
1261
  {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1262
    0xfe000000, 0xff000010,
1263
    "cdp2%c\t%{I:%8-11d%}, %{I:%20-23d%}, %{R:cr%12-15d%}, %{R:cr%16-19d%}, %{R:cr%0-3d%}, {%{I:%5-7d%}}"},
1264
  {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1265
    0xfe000010, 0xff100010,
1266
    "mcr2%c\t%{I:%8-11d%}, %{I:%21-23d%}, %12-15R, %{R:cr%16-19d%}, %{R:cr%0-3d%}, {%{I:%5-7d%}}"},
1267
  {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1268
    0xfe100010, 0xff100010,
1269
    "mrc2%c\t%{I:%8-11d%}, %{I:%21-23d%}, %12-15r, %{R:cr%16-19d%}, %{R:cr%0-3d%}, {%{I:%5-7d%}}"},
1270
1271
  {ANY, ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
1272
};
1273
1274
/* Neon opcode table:  This does not encode the top byte -- that is
1275
   checked by the print_insn_neon routine, as it depends on whether we are
1276
   doing thumb32 or arm32 disassembly.  */
1277
1278
/* print_insn_neon recognizes the following format control codes:
1279
1280
   %%     %
1281
1282
   %c     print condition code
1283
   %u     print condition code (unconditional in ARM mode,
1284
                          UNPREDICTABLE if not AL in Thumb)
1285
   %A     print v{st,ld}[1234] operands
1286
   %B     print v{st,ld}[1234] any one operands
1287
   %C     print v{st,ld}[1234] single->all operands
1288
   %D     print scalar
1289
   %E     print vmov, vmvn, vorr, vbic encoded constant
1290
   %F     print vtbl,vtbx register list
1291
1292
   %<bitfield>r   print as an ARM register
1293
   %<bitfield>d   print the bitfield in decimal
1294
   %<bitfield>e         print the 2^N - bitfield in decimal
1295
   %<bitfield>D   print as a NEON D register
1296
   %<bitfield>Q   print as a NEON Q register
1297
   %<bitfield>R   print as a NEON D or Q register
1298
   %<bitfield>Sn  print byte scaled width limited by n
1299
   %<bitfield>Tn  print short scaled width limited by n
1300
   %<bitfield>Un  print long scaled width limited by n
1301
1302
   %<bitfield>'c  print specified char iff bitfield is all ones
1303
   %<bitfield>`c  print specified char iff bitfield is all zeroes
1304
   %<bitfield>?ab...    select from array of values in big endian order.  */
1305
1306
static const struct opcode32 neon_opcodes[] =
1307
{
1308
  /* Extract.  */
1309
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1310
    0xf2b00840, 0xffb00850,
1311
    "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, %{I:#%8-11d%}"},
1312
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1313
    0xf2b00000, 0xffb00810,
1314
    "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, %{I:#%8-11d%}"},
1315
1316
  /* Data transfer between ARM and NEON registers.  */
1317
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1318
    0x0e800b10, 0x0ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
1319
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1320
    0x0e800b30, 0x0ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
1321
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1322
    0x0ea00b10, 0x0ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
1323
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1324
    0x0ea00b30, 0x0ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
1325
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1326
    0x0ec00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
1327
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1328
    0x0ee00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
1329
1330
  /* Move data element to all lanes.  */
1331
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1332
    0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %{R:%0-3,5D[%19d]%}"},
1333
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1334
    0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %{R:%0-3,5D[%18-19d]%}"},
1335
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1336
    0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %{R:%0-3,5D[%17-19d]%}"},
1337
1338
  /* Table lookup.  */
1339
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1340
    0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"},
1341
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1342
    0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"},
1343
1344
  /* Half-precision conversions.  */
1345
  {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1346
    0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"},
1347
  {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1348
    0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"},
1349
1350
  /* NEON fused multiply add instructions.  */
1351
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
1352
    0xf2000c10, 0xffb00f10, "vfma%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1353
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1354
    0xf2100c10, 0xffb00f10, "vfma%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1355
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
1356
    0xf2200c10, 0xffb00f10, "vfms%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1357
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1358
    0xf2300c10, 0xffb00f10, "vfms%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1359
1360
  /* BFloat16 instructions.  */
1361
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1362
    0xfc000d00, 0xffb00f10, "vdot.bf16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1363
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1364
    0xfe000d00, 0xffb00f10, "vdot.bf16\t%12-15,22R, %16-19,7R, %{R:d%0-3d[%5d]%}"},
1365
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1366
    0xfc000c40, 0xffb00f50, "vmmla.bf16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1367
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1368
    0xf3b60640, 0xffbf0fd0, "vcvt%c.bf16.f32\t%12-15,22D, %0-3,5Q"},
1369
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1370
    0xfc300810, 0xffb00f10, "vfma%6?tb.bf16\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1371
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1372
    0xfe300810, 0xffb00f10, "vfma%6?tb.bf16\t%12-15,22Q, %16-19,7Q, %{R:%0-2D[%3,5d]%}"},
1373
1374
  /* Matrix Multiply instructions.  */
1375
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
1376
    0xfc200c40, 0xffb00f50, "vsmmla.s8\t%12-15,22R, %16-19,7R, %0-3,5R"},
1377
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
1378
    0xfc200c50, 0xffb00f50, "vummla.u8\t%12-15,22R, %16-19,7R, %0-3,5R"},
1379
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
1380
    0xfca00c40, 0xffb00f50, "vusmmla.s8\t%12-15,22R, %16-19,7R, %0-3,5R"},
1381
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
1382
    0xfca00d00, 0xffb00f10, "vusdot.s8\t%12-15,22R, %16-19,7R, %0-3,5R"},
1383
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
1384
    0xfe800d00, 0xffb00f10, "vusdot.s8\t%12-15,22R, %16-19,7R, %{R:d%0-3d[%5d]%}"},
1385
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
1386
    0xfe800d10, 0xffb00f10, "vsudot.u8\t%12-15,22R, %16-19,7R, %{R:d%0-3d[%5d]%}"},
1387
1388
  /* Two registers, miscellaneous.  */
1389
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1390
    0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"},
1391
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1392
    0xf3b60400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f16\t%12-15,22R, %0-3,5R"},
1393
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1394
    0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"},
1395
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1396
    0xf3b70000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us16.f16\t%12-15,22R, %0-3,5R"},
1397
  {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1398
    0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"},
1399
  {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1400
    0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"},
1401
  {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1402
    0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"},
1403
  {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1404
    0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"},
1405
  {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1406
    0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"},
1407
  {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1408
    0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"},
1409
  {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1410
    0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"},
1411
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1412
    0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
1413
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1414
    0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
1415
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1416
    0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
1417
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1418
    0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"},
1419
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1420
    0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"},
1421
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1422
    0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"},
1423
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1424
    0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"},
1425
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1426
    0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1427
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1428
    0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1429
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1430
    0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
1431
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1432
    0xf3b20300, 0xffb30fd0,
1433
    "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, %{I:#%18-19S2%}"},
1434
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1435
    0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1436
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1437
    0xf3b70400, 0xffbf0e90, "vrecpe%c.%8?fu16\t%12-15,22R, %0-3,5R"},
1438
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1439
    0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1440
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1441
    0xf3b70480, 0xffbf0e90, "vrsqrte%c.%8?fu16\t%12-15,22R, %0-3,5R"},
1442
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1443
    0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1444
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1445
    0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1446
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1447
    0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1448
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1449
    0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1450
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1451
    0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"},
1452
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1453
    0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1454
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1455
    0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1456
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1457
    0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1458
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1459
    0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1460
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1461
    0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1462
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1463
    0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, %{I:#0%}"},
1464
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1465
    0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, %{I:#0%}"},
1466
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1467
    0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, %{I:#0%}"},
1468
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1469
    0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, %{I:#0%}"},
1470
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1471
    0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, %{I:#0%}"},
1472
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1473
    0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1474
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1475
    0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1476
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1477
    0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1478
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1479
    0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1480
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1481
    0xf3bb0600, 0xffbf0e10,
1482
    "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
1483
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1484
    0xf3b70600, 0xffbf0e10,
1485
    "vcvt%c.%7-8?usff16.%7-8?ffus16\t%12-15,22R, %0-3,5R"},
1486
1487
  /* Three registers of the same length.  */
1488
  {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1489
    0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1490
  {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1491
    0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1492
  {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1493
    0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1494
  {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1495
    0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1496
  {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1497
    0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1498
  {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1499
    0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1500
  {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1501
    0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1502
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1503
    0xf3000f10, 0xffb00f10, "vmaxnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1504
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1505
    0xf3100f10, 0xffb00f10, "vmaxnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1506
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1507
    0xf3200f10, 0xffb00f10, "vminnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1508
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1509
    0xf3300f10, 0xffb00f10, "vminnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1510
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1511
    0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1512
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1513
    0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1514
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1515
    0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1516
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1517
    0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1518
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1519
    0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1520
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1521
    0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1522
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1523
    0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1524
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1525
    0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1526
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1527
    0xf2000d00, 0xffb00f10, "vadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1528
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1529
    0xf2100d00, 0xffb00f10, "vadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1530
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1531
    0xf2000d10, 0xffb00f10, "vmla%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1532
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1533
    0xf2100d10, 0xffb00f10, "vmla%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1534
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1535
    0xf2000e00, 0xffb00f10, "vceq%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1536
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1537
    0xf2100e00, 0xffb00f10, "vceq%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1538
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1539
    0xf2000f00, 0xffb00f10, "vmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1540
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1541
    0xf2100f00, 0xffb00f10, "vmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1542
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1543
    0xf2000f10, 0xffb00f10, "vrecps%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1544
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1545
    0xf2100f10, 0xffb00f10, "vrecps%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1546
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1547
    0xf2200d00, 0xffb00f10, "vsub%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1548
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1549
    0xf2300d00, 0xffb00f10, "vsub%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1550
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1551
    0xf2200d10, 0xffb00f10, "vmls%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1552
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1553
    0xf2300d10, 0xffb00f10, "vmls%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1554
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1555
    0xf2200f00, 0xffb00f10, "vmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1556
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1557
    0xf2300f00, 0xffb00f10, "vmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1558
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1559
    0xf2200f10, 0xffb00f10, "vrsqrts%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1560
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1561
    0xf2300f10, 0xffb00f10, "vrsqrts%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1562
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1563
    0xf3000d00, 0xffb00f10, "vpadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1564
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1565
    0xf3100d00, 0xffb00f10, "vpadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1566
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1567
    0xf3000d10, 0xffb00f10, "vmul%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1568
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1569
    0xf3100d10, 0xffb00f10, "vmul%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1570
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1571
    0xf3000e00, 0xffb00f10, "vcge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1572
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1573
    0xf3100e00, 0xffb00f10, "vcge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1574
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1575
    0xf3000e10, 0xffb00f10, "vacge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1576
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1577
    0xf3100e10, 0xffb00f10, "vacge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1578
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1579
    0xf3000f00, 0xffb00f10, "vpmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1580
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1581
    0xf3100f00, 0xffb00f10, "vpmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1582
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1583
    0xf3200d00, 0xffb00f10, "vabd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1584
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1585
    0xf3300d00, 0xffb00f10, "vabd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1586
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1587
    0xf3200e00, 0xffb00f10, "vcgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1588
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1589
    0xf3300e00, 0xffb00f10, "vcgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1590
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1591
    0xf3200e10, 0xffb00f10, "vacgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1592
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1593
    0xf3300e10, 0xffb00f10, "vacgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1594
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1595
    0xf3200f00, 0xffb00f10, "vpmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1596
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1597
    0xf3300f00, 0xffb00f10, "vpmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1598
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1599
    0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1600
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1601
    0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1602
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1603
    0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1604
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1605
    0xf2000b00, 0xff800f10,
1606
    "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1607
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1608
    0xf2000b10, 0xff800f10,
1609
    "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1610
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1611
    0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1612
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1613
    0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1614
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1615
    0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1616
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1617
    0xf3000b00, 0xff800f10,
1618
    "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1619
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1620
    0xf2000000, 0xfe800f10,
1621
    "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1622
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1623
    0xf2000010, 0xfe800f10,
1624
    "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1625
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1626
    0xf2000100, 0xfe800f10,
1627
    "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1628
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1629
    0xf2000200, 0xfe800f10,
1630
    "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1631
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1632
    0xf2000210, 0xfe800f10,
1633
    "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1634
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1635
    0xf2000300, 0xfe800f10,
1636
    "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1637
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1638
    0xf2000310, 0xfe800f10,
1639
    "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1640
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1641
    0xf2000400, 0xfe800f10,
1642
    "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1643
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1644
    0xf2000410, 0xfe800f10,
1645
    "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1646
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1647
    0xf2000500, 0xfe800f10,
1648
    "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1649
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1650
    0xf2000510, 0xfe800f10,
1651
    "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1652
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1653
    0xf2000600, 0xfe800f10,
1654
    "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1655
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1656
    0xf2000610, 0xfe800f10,
1657
    "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1658
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1659
    0xf2000700, 0xfe800f10,
1660
    "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1661
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1662
    0xf2000710, 0xfe800f10,
1663
    "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1664
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1665
    0xf2000910, 0xfe800f10,
1666
    "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1667
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1668
    0xf2000a00, 0xfe800f10,
1669
    "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1670
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1671
    0xf2000a10, 0xfe800f10,
1672
    "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1673
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1674
    0xf3000b10, 0xff800f10,
1675
    "vqrdmlah%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1676
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1677
    0xf3000c10, 0xff800f10,
1678
    "vqrdmlsh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1679
1680
  /* One register and an immediate value.  */
1681
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1682
    0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"},
1683
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1684
    0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"},
1685
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1686
    0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"},
1687
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1688
    0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"},
1689
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1690
    0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"},
1691
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1692
    0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"},
1693
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1694
    0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"},
1695
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1696
    0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"},
1697
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1698
    0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"},
1699
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1700
    0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"},
1701
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1702
    0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"},
1703
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1704
    0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"},
1705
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1706
    0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"},
1707
1708
  /* Two registers and a shift amount.  */
1709
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1710
    0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, %{I:#%16-18e%}"},
1711
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1712
    0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, %{I:#%16-18e%}"},
1713
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1714
    0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, %{I:#%16-18e%}"},
1715
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1716
    0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, %{I:#%16-18e%}"},
1717
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1718
    0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, %{I:#%16-18e%}"},
1719
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1720
    0xf2880950, 0xfeb80fd0,
1721
    "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, %{I:#%16-18e%}"},
1722
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1723
    0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, %{I:#%16-18d%}"},
1724
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1725
    0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, %{I:#%16-19e%}"},
1726
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1727
    0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, %{I:#%16-19e%}"},
1728
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1729
    0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, %{I:#%16-18d%}"},
1730
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1731
    0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, %{I:#%16-18e%}"},
1732
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1733
    0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, %{I:#%16-18d%}"},
1734
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1735
    0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, %{I:#%16-18d%}"},
1736
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1737
    0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, %{I:#%16-19e%}"},
1738
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1739
    0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, %{I:#%16-19e%}"},
1740
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1741
    0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, %{I:#%16-19e%}"},
1742
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1743
    0xf2900950, 0xfeb00fd0,
1744
    "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, %{I:#%16-19e%}"},
1745
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1746
    0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, %{I:#%16-19d%}"},
1747
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1748
    0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, %{I:#%16-18e%}"},
1749
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1750
    0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, %{I:#%16-18e%}"},
1751
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1752
    0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, %{I:#%16-18e%}"},
1753
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1754
    0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, %{I:#%16-18e%}"},
1755
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1756
    0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, %{I:#%16-18d%}"},
1757
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1758
    0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, %{I:#%16-20e%}"},
1759
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1760
    0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, %{I:#%16-20e%}"},
1761
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1762
    0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, %{I:#%16-19d%}"},
1763
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1764
    0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, %{I:#%16-19e%}"},
1765
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1766
    0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, %{I:#%16-19d%}"},
1767
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1768
    0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, %{I:#%16-19d%}"},
1769
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1770
    0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, %{I:#%16-20d%}"},
1771
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1772
    0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, %{I:#%16-19e%}"},
1773
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1774
    0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, %{I:#%16-19e%}"},
1775
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1776
    0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, %{I:#%16-19e%}"},
1777
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1778
    0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, %{I:#%16-19e%}"},
1779
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1780
    0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, %{I:#%16-19d%}"},
1781
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1782
    0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, %{I:#%16-20e%}"},
1783
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1784
    0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, %{I:#%16-20e%}"},
1785
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1786
    0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, %{I:#%16-20e%}"},
1787
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1788
    0xf2a00950, 0xfea00fd0,
1789
    "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, %{I:#%16-20e%}"},
1790
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1791
    0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, %{I:#%16-20d%}"},
1792
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1793
    0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, %{I:#%16-20e%}"},
1794
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1795
    0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, %{I:#%16-20d%}"},
1796
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1797
    0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, %{I:#%16-20d%}"},
1798
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1799
    0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, %{I:#%16-20e%}"},
1800
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1801
    0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, %{I:#%16-20e%}"},
1802
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1803
    0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, %{I:#%16-20e%}"},
1804
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1805
    0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, %{I:#%16-20e%}"},
1806
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1807
    0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, %{I:#%16-20d%}"},
1808
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1809
    0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, %{I:#%16-21d%}"},
1810
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1811
    0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, %{I:#%16-21e%}"},
1812
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1813
    0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, %{I:#%16-21d%}"},
1814
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1815
    0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, %{I:#%16-21d%}"},
1816
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1817
    0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, %{I:#%16-21e%}"},
1818
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1819
    0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, %{I:#%16-21e%}"},
1820
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1821
    0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, %{I:#%16-21e%}"},
1822
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1823
    0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, %{I:#%16-21e%}"},
1824
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1825
    0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, %{I:#%16-21d%}"},
1826
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1827
    0xf2a00e10, 0xfea00e90,
1828
    "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, %{I:#%16-20e%}"},
1829
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1830
    0xf2a00c10, 0xfea00e90,
1831
    "vcvt%c.%24,8?usff16.%24,8?ffus16\t%12-15,22R, %0-3,5R, %{I:#%16-20e%}"},
1832
1833
  /* Three registers of different lengths.  */
1834
  {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1835
    0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1836
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1837
    0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1838
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1839
    0xf2800400, 0xff800f50,
1840
    "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1841
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1842
    0xf2800600, 0xff800f50,
1843
    "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1844
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1845
    0xf2800900, 0xff800f50,
1846
    "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1847
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1848
    0xf2800b00, 0xff800f50,
1849
    "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1850
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1851
    0xf2800d00, 0xff800f50,
1852
    "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1853
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1854
    0xf3800400, 0xff800f50,
1855
    "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1856
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1857
    0xf3800600, 0xff800f50,
1858
    "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1859
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1860
    0xf2800000, 0xfe800f50,
1861
    "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1862
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1863
    0xf2800100, 0xfe800f50,
1864
    "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1865
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1866
    0xf2800200, 0xfe800f50,
1867
    "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1868
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1869
    0xf2800300, 0xfe800f50,
1870
    "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1871
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1872
    0xf2800500, 0xfe800f50,
1873
    "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1874
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1875
    0xf2800700, 0xfe800f50,
1876
    "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1877
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1878
    0xf2800800, 0xfe800f50,
1879
    "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1880
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1881
    0xf2800a00, 0xfe800f50,
1882
    "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1883
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1884
    0xf2800c00, 0xfe800f50,
1885
    "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1886
1887
  /* Two registers and a scalar.  */
1888
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1889
    0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1890
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1891
    0xf2800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1892
  {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1893
    0xf2900140, 0xffb00f50, "vmla%c.f16\t%12-15,22D, %16-19,7D, %D"},
1894
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1895
    0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1896
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1897
    0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1898
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1899
    0xf2800540, 0xff900f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1900
  {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1901
    0xf2900540, 0xffb00f50, "vmls%c.f16\t%12-15,22D, %16-19,7D, %D"},
1902
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1903
    0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1904
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1905
    0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1906
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1907
    0xf2800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1908
  {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1909
    0xf2900940, 0xffb00f50, "vmul%c.f16\t%12-15,22D, %16-19,7D, %D"},
1910
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1911
    0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1912
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1913
    0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1914
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1915
    0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1916
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1917
    0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1918
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1919
    0xf3800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1920
  {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1921
    0xf3900140, 0xffb00f50, "vmla%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
1922
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1923
    0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1924
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1925
    0xf3800540, 0xff900f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1926
  {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1927
    0xf3900540, 0xffb00f50, "vmls%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
1928
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1929
    0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1930
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1931
    0xf3800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1932
  {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1933
    0xf3900940, 0xffb00f50, "vmul%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
1934
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1935
    0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1936
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1937
    0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1938
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1939
    0xf2800240, 0xfe800f50,
1940
    "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1941
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1942
    0xf2800640, 0xfe800f50,
1943
    "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1944
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1945
    0xf2800a40, 0xfe800f50,
1946
    "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1947
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1948
    0xf2800e40, 0xff800f50,
1949
   "vqrdmlah%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1950
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1951
    0xf2800f40, 0xff800f50,
1952
   "vqrdmlsh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1953
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1954
    0xf3800e40, 0xff800f50,
1955
   "vqrdmlah%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1956
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1957
    0xf3800f40, 0xff800f50,
1958
   "vqrdmlsh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"
1959
  },
1960
1961
  /* Element and structure load/store.  */
1962
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1963
    0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"},
1964
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1965
    0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"},
1966
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1967
    0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"},
1968
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1969
    0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"},
1970
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1971
    0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"},
1972
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1973
    0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1974
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1975
    0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1976
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1977
    0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1978
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1979
    0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1980
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1981
    0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1982
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1983
    0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1984
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1985
    0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1986
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1987
    0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1988
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1989
    0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1990
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1991
    0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"},
1992
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1993
    0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"},
1994
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1995
    0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"},
1996
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1997
    0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"},
1998
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1999
    0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"},
2000
2001
  {ARM_FEATURE_CORE_LOW (0), 0 ,0, 0}
2002
};
2003
2004
/* mve opcode table.  */
2005
2006
/* print_insn_mve recognizes the following format control codes:
2007
2008
   %%     %
2009
2010
   %a     print '+' or '-' or imm offset in vldr[bhwd] and
2011
      vstr[bhwd]
2012
   %c     print condition code
2013
   %d     print addr mode of MVE vldr[bhw] and vstr[bhw]
2014
   %u     print 'U' (unsigned) or 'S' for various mve instructions
2015
   %i     print MVE predicate(s) for vpt and vpst
2016
   %j     print a 5-bit immediate from hw2[14:12,7:6]
2017
   %k     print 48 if the 7th position bit is set else print 64.
2018
   %m     print rounding mode for vcvt and vrint
2019
   %n     print vector comparison code for predicated instruction
2020
   %s     print size for various vcvt instructions
2021
   %v     print vector predicate for instruction in predicated
2022
      block
2023
   %o     print offset scaled for vldr[hwd] and vstr[hwd]
2024
   %w     print writeback mode for MVE v{st,ld}[24]
2025
   %B     print v{st,ld}[24] any one operands
2026
   %E     print vmov, vmvn, vorr, vbic encoded constant
2027
   %N     print generic index for vmov
2028
   %T     print bottom ('b') or top ('t') of source register
2029
   %X     print exchange field in vmla* instructions
2030
2031
   %<bitfield>r   print as an ARM register
2032
   %<bitfield>d   print the bitfield in decimal
2033
   %<bitfield>A   print accumulate or not
2034
   %<bitfield>c   print bitfield as a condition code
2035
   %<bitfield>C   print bitfield as an inverted condition code
2036
   %<bitfield>Q   print as a MVE Q register
2037
   %<bitfield>F   print as a MVE S register
2038
   %<bitfield>Z   as %<>r but r15 is ZR instead of PC and r13 is
2039
      UNPREDICTABLE
2040
2041
   %<bitfield>S   as %<>r but r15 or r13 is UNPREDICTABLE
2042
   %<bitfield>s   print size for vector predicate & non VMOV instructions
2043
   %<bitfield>I   print carry flag or not
2044
   %<bitfield>i   print immediate for vstr/vldr reg +/- imm
2045
   %<bitfield>h   print high half of 64-bit destination reg
2046
   %<bitfield>k   print immediate for vector conversion instruction
2047
   %<bitfield>l   print low half of 64-bit destination reg
2048
   %<bitfield>o   print rotate value for vcmul
2049
   %<bitfield>u   print immediate value for vddup/vdwdup
2050
   %<bitfield>x   print the bitfield in hex.
2051
  */
2052
2053
static const struct mopcode32 mve_opcodes[] =
2054
{
2055
  /* MVE.  */
2056
2057
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2058
   MVE_VPST,
2059
   0xfe310f4d, 0xffbf1fff,
2060
   "vpst%i"
2061
  },
2062
2063
  /* Floating point VPT T1.  */
2064
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2065
   MVE_VPT_FP_T1,
2066
   0xee310f00, 0xefb10f50,
2067
   "vpt%i.f%28s\t%n, %17-19Q, %1-3,5Q"},
2068
  /* Floating point VPT T2.  */
2069
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2070
   MVE_VPT_FP_T2,
2071
   0xee310f40, 0xefb10f50,
2072
   "vpt%i.f%28s\t%n, %17-19Q, %0-3Z"},
2073
2074
  /* Vector VPT T1.  */
2075
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2076
   MVE_VPT_VEC_T1,
2077
   0xfe010f00, 0xff811f51,
2078
   "vpt%i.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
2079
  /* Vector VPT T2.  */
2080
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2081
   MVE_VPT_VEC_T2,
2082
   0xfe010f01, 0xff811f51,
2083
   "vpt%i.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
2084
  /* Vector VPT T3.  */
2085
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2086
   MVE_VPT_VEC_T3,
2087
   0xfe011f00, 0xff811f50,
2088
   "vpt%i.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
2089
  /* Vector VPT T4.  */
2090
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2091
   MVE_VPT_VEC_T4,
2092
   0xfe010f40, 0xff811f70,
2093
   "vpt%i.i%20-21s\t%n, %17-19Q, %0-3Z"},
2094
  /* Vector VPT T5.  */
2095
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2096
   MVE_VPT_VEC_T5,
2097
   0xfe010f60, 0xff811f70,
2098
   "vpt%i.u%20-21s\t%n, %17-19Q, %0-3Z"},
2099
  /* Vector VPT T6.  */
2100
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2101
   MVE_VPT_VEC_T6,
2102
   0xfe011f40, 0xff811f50,
2103
   "vpt%i.s%20-21s\t%n, %17-19Q, %0-3Z"},
2104
2105
  /* Vector VBIC immediate.  */
2106
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2107
   MVE_VBIC_IMM,
2108
   0xef800070, 0xefb81070,
2109
   "vbic%v.i%8-11s\t%13-15,22Q, %E"},
2110
2111
  /* Vector VBIC register.  */
2112
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2113
   MVE_VBIC_REG,
2114
   0xef100150, 0xffb11f51,
2115
   "vbic%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2116
2117
  /* Vector VABAV.  */
2118
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2119
   MVE_VABAV,
2120
   0xee800f01, 0xefc10f51,
2121
   "vabav%v.%u%20-21s\t%12-15r, %17-19,7Q, %1-3,5Q"},
2122
2123
  /* Vector VABD floating point.  */
2124
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2125
   MVE_VABD_FP,
2126
   0xff200d40, 0xffa11f51,
2127
   "vabd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2128
2129
  /* Vector VABD.  */
2130
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2131
   MVE_VABD_VEC,
2132
   0xef000740, 0xef811f51,
2133
   "vabd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2134
2135
  /* Vector VABS floating point.  */
2136
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2137
   MVE_VABS_FP,
2138
   0xFFB10740, 0xFFB31FD1,
2139
   "vabs%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
2140
  /* Vector VABS.  */
2141
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2142
   MVE_VABS_VEC,
2143
   0xffb10340, 0xffb31fd1,
2144
   "vabs%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2145
2146
  /* Vector VADD floating point T1.  */
2147
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2148
   MVE_VADD_FP_T1,
2149
   0xef000d40, 0xffa11f51,
2150
   "vadd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2151
  /* Vector VADD floating point T2.  */
2152
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2153
   MVE_VADD_FP_T2,
2154
   0xee300f40, 0xefb11f70,
2155
   "vadd%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2156
  /* Vector VADD T1.  */
2157
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2158
   MVE_VADD_VEC_T1,
2159
   0xef000840, 0xff811f51,
2160
   "vadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2161
  /* Vector VADD T2.  */
2162
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2163
   MVE_VADD_VEC_T2,
2164
   0xee010f40, 0xff811f70,
2165
   "vadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2166
2167
  /* Vector VADDLV.  */
2168
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2169
   MVE_VADDLV,
2170
   0xee890f00, 0xef8f1fd1,
2171
   "vaddlv%5A%v.%u32\t%13-15l, %20-22h, %1-3Q"},
2172
2173
  /* Vector VADDV.  */
2174
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2175
   MVE_VADDV,
2176
   0xeef10f00, 0xeff31fd1,
2177
   "vaddv%5A%v.%u%18-19s\t%13-15l, %1-3Q"},
2178
2179
  /* Vector VADC.  */
2180
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2181
   MVE_VADC,
2182
   0xee300f00, 0xffb10f51,
2183
   "vadc%12I%v.i32\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2184
2185
  /* Vector VAND.  */
2186
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2187
   MVE_VAND,
2188
   0xef000150, 0xffb11f51,
2189
   "vand%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2190
2191
  /* Vector VBRSR register.  */
2192
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2193
   MVE_VBRSR,
2194
   0xfe011e60, 0xff811f70,
2195
   "vbrsr%v.%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2196
2197
  /* Vector VCADD floating point.  */
2198
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2199
   MVE_VCADD_FP,
2200
   0xfc800840, 0xfea11f51,
2201
   "vcadd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, %{I:#%24o%}"},
2202
2203
  /* Vector VCADD.  */
2204
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2205
   MVE_VCADD_VEC,
2206
   0xfe000f00, 0xff810f51,
2207
   "vcadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, %{I:#%12o%}"},
2208
2209
  /* Vector VCLS.  */
2210
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2211
   MVE_VCLS,
2212
   0xffb00440, 0xffb31fd1,
2213
   "vcls%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2214
2215
  /* Vector VCLZ.  */
2216
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2217
   MVE_VCLZ,
2218
   0xffb004c0, 0xffb31fd1,
2219
   "vclz%v.i%18-19s\t%13-15,22Q, %1-3,5Q"},
2220
2221
  /* Vector VCMLA.  */
2222
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2223
   MVE_VCMLA_FP,
2224
   0xfc200840, 0xfe211f51,
2225
   "vcmla%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, %{I:#%23-24o%}"},
2226
2227
  /* Vector VCMP floating point T1.  */
2228
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2229
   MVE_VCMP_FP_T1,
2230
   0xee310f00, 0xeff1ef50,
2231
   "vcmp%v.f%28s\t%n, %17-19Q, %1-3,5Q"},
2232
2233
  /* Vector VCMP floating point T2.  */
2234
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2235
   MVE_VCMP_FP_T2,
2236
   0xee310f40, 0xeff1ef50,
2237
   "vcmp%v.f%28s\t%n, %17-19Q, %0-3Z"},
2238
2239
  /* Vector VCMP T1.  */
2240
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2241
   MVE_VCMP_VEC_T1,
2242
   0xfe010f00, 0xffc1ff51,
2243
   "vcmp%v.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
2244
  /* Vector VCMP T2.  */
2245
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2246
   MVE_VCMP_VEC_T2,
2247
   0xfe010f01, 0xffc1ff51,
2248
   "vcmp%v.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
2249
  /* Vector VCMP T3.  */
2250
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2251
   MVE_VCMP_VEC_T3,
2252
   0xfe011f00, 0xffc1ff50,
2253
   "vcmp%v.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
2254
  /* Vector VCMP T4.  */
2255
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2256
   MVE_VCMP_VEC_T4,
2257
   0xfe010f40, 0xffc1ff70,
2258
   "vcmp%v.i%20-21s\t%n, %17-19Q, %0-3Z"},
2259
  /* Vector VCMP T5.  */
2260
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2261
   MVE_VCMP_VEC_T5,
2262
   0xfe010f60, 0xffc1ff70,
2263
   "vcmp%v.u%20-21s\t%n, %17-19Q, %0-3Z"},
2264
  /* Vector VCMP T6.  */
2265
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2266
   MVE_VCMP_VEC_T6,
2267
   0xfe011f40, 0xffc1ff50,
2268
   "vcmp%v.s%20-21s\t%n, %17-19Q, %0-3Z"},
2269
2270
  /* Vector VDUP.  */
2271
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2272
   MVE_VDUP,
2273
   0xeea00b10, 0xffb10f5f,
2274
   "vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
2275
2276
  /* Vector VEOR.  */
2277
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2278
   MVE_VEOR,
2279
   0xff000150, 0xffd11f51,
2280
   "veor%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2281
2282
  /* Vector VFMA, vector * scalar.  */
2283
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2284
   MVE_VFMA_FP_SCALAR,
2285
   0xee310e40, 0xefb11f70,
2286
   "vfma%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2287
2288
  /* Vector VFMA floating point.  */
2289
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2290
   MVE_VFMA_FP,
2291
   0xef000c50, 0xffa11f51,
2292
   "vfma%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2293
2294
  /* Vector VFMS floating point.  */
2295
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2296
   MVE_VFMS_FP,
2297
   0xef200c50, 0xffa11f51,
2298
   "vfms%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2299
2300
  /* Vector VFMAS, vector * scalar.  */
2301
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2302
   MVE_VFMAS_FP_SCALAR,
2303
   0xee311e40, 0xefb11f70,
2304
   "vfmas%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2305
2306
  /* Vector VHADD T1.  */
2307
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2308
   MVE_VHADD_T1,
2309
   0xef000040, 0xef811f51,
2310
   "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2311
2312
  /* Vector VHADD T2.  */
2313
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2314
   MVE_VHADD_T2,
2315
   0xee000f40, 0xef811f70,
2316
   "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2317
2318
  /* Vector VHSUB T1.  */
2319
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2320
   MVE_VHSUB_T1,
2321
   0xef000240, 0xef811f51,
2322
   "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2323
2324
  /* Vector VHSUB T2.  */
2325
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2326
   MVE_VHSUB_T2,
2327
   0xee001f40, 0xef811f70,
2328
   "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2329
2330
  /* Vector VCMUL.  */
2331
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2332
   MVE_VCMUL_FP,
2333
   0xee300e00, 0xefb10f50,
2334
   "vcmul%v.f%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, %{I:#%0,12o%}"},
2335
2336
   /* Vector VCTP.  */
2337
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2338
   MVE_VCTP,
2339
   0xf000e801, 0xffc0ffff,
2340
   "vctp%v.%20-21s\t%16-19r"},
2341
2342
  /* Vector VDUP.  */
2343
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2344
   MVE_VDUP,
2345
   0xeea00b10, 0xffb10f5f,
2346
   "vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
2347
2348
  /* Vector VRHADD.  */
2349
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2350
   MVE_VRHADD,
2351
   0xef000140, 0xef811f51,
2352
   "vrhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2353
2354
  /* Vector VCVT.  */
2355
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2356
   MVE_VCVT_FP_FIX_VEC,
2357
   0xef800c50, 0xef801cd1,
2358
   "vcvt%v.%s\t%13-15,22Q, %1-3,5Q, %{I:#%16-21k%}"},
2359
2360
  /* Vector VCVT.  */
2361
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2362
   MVE_VCVT_BETWEEN_FP_INT,
2363
   0xffb30640, 0xffb31e51,
2364
   "vcvt%v.%s\t%13-15,22Q, %1-3,5Q"},
2365
2366
  /* Vector VCVT between single and half-precision float, bottom half.  */
2367
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2368
   MVE_VCVT_FP_HALF_FP,
2369
   0xee3f0e01, 0xefbf1fd1,
2370
   "vcvtb%v.%s\t%13-15,22Q, %1-3,5Q"},
2371
2372
  /* Vector VCVT between single and half-precision float, top half.  */
2373
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2374
   MVE_VCVT_FP_HALF_FP,
2375
   0xee3f1e01, 0xefbf1fd1,
2376
   "vcvtt%v.%s\t%13-15,22Q, %1-3,5Q"},
2377
2378
  /* Vector VCVT.  */
2379
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2380
   MVE_VCVT_FROM_FP_TO_INT,
2381
   0xffb30040, 0xffb31c51,
2382
   "vcvt%m%v.%s\t%13-15,22Q, %1-3,5Q"},
2383
2384
  /* Vector VDDUP.  */
2385
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2386
   MVE_VDDUP,
2387
   0xee011f6e, 0xff811f7e,
2388
   "vddup%v.u%20-21s\t%13-15,22Q, %17-19l, %{I:#%0,7u%}"},
2389
2390
  /* Vector VDWDUP.  */
2391
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2392
   MVE_VDWDUP,
2393
   0xee011f60, 0xff811f70,
2394
   "vdwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, %{I:#%0,7u%}"},
2395
2396
  /* Vector VHCADD.  */
2397
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2398
   MVE_VHCADD,
2399
   0xee000f00, 0xff810f51,
2400
   "vhcadd%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, %{I:#%12o%}"},
2401
2402
  /* Vector VIWDUP.  */
2403
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2404
   MVE_VIWDUP,
2405
   0xee010f60, 0xff811f70,
2406
   "viwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, %{I:#%0,7u%}"},
2407
2408
  /* Vector VIDUP.  */
2409
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2410
   MVE_VIDUP,
2411
   0xee010f6e, 0xff811f7e,
2412
   "vidup%v.u%20-21s\t%13-15,22Q, %17-19l, %{I:#%0,7u%}"},
2413
2414
  /* Vector VLD2.  */
2415
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2416
   MVE_VLD2,
2417
   0xfc901e00, 0xff901e5f,
2418
   "vld2%5d.%7-8s\t%B, [%16-19r]%w"},
2419
2420
  /* Vector VLD4.  */
2421
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2422
   MVE_VLD4,
2423
   0xfc901e01, 0xff901e1f,
2424
   "vld4%5-6d.%7-8s\t%B, [%16-19r]%w"},
2425
2426
  /* Vector VLDRB gather load.  */
2427
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2428
   MVE_VLDRB_GATHER_T1,
2429
   0xec900e00, 0xefb01e50,
2430
   "vldrb%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"},
2431
2432
  /* Vector VLDRH gather load.  */
2433
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2434
   MVE_VLDRH_GATHER_T2,
2435
   0xec900e10, 0xefb01e50,
2436
   "vldrh%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2437
2438
  /* Vector VLDRW gather load.  */
2439
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2440
   MVE_VLDRW_GATHER_T3,
2441
   0xfc900f40, 0xffb01fd0,
2442
   "vldrw%v.u32\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2443
2444
  /* Vector VLDRD gather load.  */
2445
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2446
   MVE_VLDRD_GATHER_T4,
2447
   0xec900fd0, 0xefb01fd0,
2448
   "vldrd%v.u64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2449
2450
  /* Vector VLDRW gather load.  */
2451
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2452
   MVE_VLDRW_GATHER_T5,
2453
   0xfd101e00, 0xff111f00,
2454
   "vldrw%v.u32\t%13-15,22Q, [%17-19,7Q, %{I:#%a%0-6i%}]%w"},
2455
2456
  /* Vector VLDRD gather load, variant T6.  */
2457
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2458
   MVE_VLDRD_GATHER_T6,
2459
   0xfd101f00, 0xff111f00,
2460
   "vldrd%v.u64\t%13-15,22Q, [%17-19,7Q, %{I:#%a%0-6i%}]%w"},
2461
2462
  /* Vector VLDRB.  */
2463
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2464
   MVE_VLDRB_T1,
2465
   0xec100e00, 0xee581e00,
2466
   "vldrb%v.%u%7-8s\t%13-15Q, %d"},
2467
2468
  /* Vector VLDRH.  */
2469
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2470
   MVE_VLDRH_T2,
2471
   0xec180e00, 0xee581e00,
2472
   "vldrh%v.%u%7-8s\t%13-15Q, %d"},
2473
2474
  /* Vector VLDRB unsigned, variant T5.  */
2475
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2476
   MVE_VLDRB_T5,
2477
   0xec101e00, 0xfe101f80,
2478
   "vldrb%v.u8\t%13-15,22Q, %d"},
2479
2480
  /* Vector VLDRH unsigned, variant T6.  */
2481
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2482
   MVE_VLDRH_T6,
2483
   0xec101e80, 0xfe101f80,
2484
   "vldrh%v.u16\t%13-15,22Q, %d"},
2485
2486
  /* Vector VLDRW unsigned, variant T7.  */
2487
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2488
   MVE_VLDRW_T7,
2489
   0xec101f00, 0xfe101f80,
2490
   "vldrw%v.u32\t%13-15,22Q, %d"},
2491
2492
  /* Vector VMAX.  */
2493
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2494
   MVE_VMAX,
2495
   0xef000640, 0xef811f51,
2496
   "vmax%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2497
2498
  /* Vector VMAXA.  */
2499
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2500
   MVE_VMAXA,
2501
   0xee330e81, 0xffb31fd1,
2502
   "vmaxa%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2503
2504
  /* Vector VMAXNM floating point.  */
2505
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2506
   MVE_VMAXNM_FP,
2507
   0xff000f50, 0xffa11f51,
2508
   "vmaxnm%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2509
2510
  /* Vector VMAXNMA floating point.  */
2511
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2512
   MVE_VMAXNMA_FP,
2513
   0xee3f0e81, 0xefbf1fd1,
2514
   "vmaxnma%v.f%28s\t%13-15,22Q, %1-3,5Q"},
2515
2516
  /* Vector VMAXNMV floating point.  */
2517
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2518
   MVE_VMAXNMV_FP,
2519
   0xeeee0f00, 0xefff0fd1,
2520
   "vmaxnmv%v.f%28s\t%12-15r, %1-3,5Q"},
2521
2522
  /* Vector VMAXNMAV floating point.  */
2523
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2524
   MVE_VMAXNMAV_FP,
2525
   0xeeec0f00, 0xefff0fd1,
2526
   "vmaxnmav%v.f%28s\t%12-15r, %1-3,5Q"},
2527
2528
  /* Vector VMAXV.  */
2529
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2530
   MVE_VMAXV,
2531
   0xeee20f00, 0xeff30fd1,
2532
   "vmaxv%v.%u%18-19s\t%12-15r, %1-3,5Q"},
2533
2534
  /* Vector VMAXAV.  */
2535
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2536
   MVE_VMAXAV,
2537
   0xeee00f00, 0xfff30fd1,
2538
   "vmaxav%v.s%18-19s\t%12-15r, %1-3,5Q"},
2539
2540
  /* Vector VMIN.  */
2541
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2542
   MVE_VMIN,
2543
   0xef000650, 0xef811f51,
2544
   "vmin%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2545
2546
  /* Vector VMINA.  */
2547
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2548
   MVE_VMINA,
2549
   0xee331e81, 0xffb31fd1,
2550
   "vmina%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2551
2552
  /* Vector VMINNM floating point.  */
2553
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2554
   MVE_VMINNM_FP,
2555
   0xff200f50, 0xffa11f51,
2556
   "vminnm%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2557
2558
  /* Vector VMINNMA floating point.  */
2559
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2560
   MVE_VMINNMA_FP,
2561
   0xee3f1e81, 0xefbf1fd1,
2562
   "vminnma%v.f%28s\t%13-15,22Q, %1-3,5Q"},
2563
2564
  /* Vector VMINNMV floating point.  */
2565
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2566
   MVE_VMINNMV_FP,
2567
   0xeeee0f80, 0xefff0fd1,
2568
   "vminnmv%v.f%28s\t%12-15r, %1-3,5Q"},
2569
2570
  /* Vector VMINNMAV floating point.  */
2571
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2572
   MVE_VMINNMAV_FP,
2573
   0xeeec0f80, 0xefff0fd1,
2574
   "vminnmav%v.f%28s\t%12-15r, %1-3,5Q"},
2575
2576
  /* Vector VMINV.  */
2577
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2578
   MVE_VMINV,
2579
   0xeee20f80, 0xeff30fd1,
2580
   "vminv%v.%u%18-19s\t%12-15r, %1-3,5Q"},
2581
2582
  /* Vector VMINAV.  */
2583
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2584
   MVE_VMINAV,
2585
   0xeee00f80, 0xfff30fd1,
2586
   "vminav%v.s%18-19s\t%12-15r, %1-3,5Q"},
2587
2588
  /* Vector VMLA.  */
2589
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2590
   MVE_VMLA,
2591
   0xee010e40, 0xef811f70,
2592
   "vmla%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2593
2594
  /* Vector VMLALDAV.  Note must appear before VMLADAV due to instruction
2595
     opcode aliasing.  */
2596
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2597
   MVE_VMLALDAV,
2598
   0xee801e00, 0xef801f51,
2599
   "vmlaldav%5Ax%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2600
2601
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2602
   MVE_VMLALDAV,
2603
   0xee800e00, 0xef801f51,
2604
   "vmlalv%5A%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2605
2606
  /* Vector VMLAV T1 variant, same as VMLADAV but with X == 0.  */
2607
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2608
   MVE_VMLADAV_T1,
2609
   0xeef00e00, 0xeff01f51,
2610
   "vmlav%5A%v.%u%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2611
2612
  /* Vector VMLAV T2 variant, same as VMLADAV but with X == 0.  */
2613
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2614
   MVE_VMLADAV_T2,
2615
   0xeef00f00, 0xeff11f51,
2616
   "vmlav%5A%v.%u8\t%13-15l, %17-19,7Q, %1-3Q"},
2617
2618
  /* Vector VMLADAV T1 variant.  */
2619
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2620
   MVE_VMLADAV_T1,
2621
   0xeef01e00, 0xeff01f51,
2622
   "vmladav%5Ax%v.%u%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2623
2624
  /* Vector VMLADAV T2 variant.  */
2625
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2626
   MVE_VMLADAV_T2,
2627
   0xeef01f00, 0xeff11f51,
2628
   "vmladav%5Ax%v.%u8\t%13-15l, %17-19,7Q, %1-3Q"},
2629
2630
  /* Vector VMLAS.  */
2631
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2632
   MVE_VMLAS,
2633
   0xee011e40, 0xef811f70,
2634
   "vmlas%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2635
2636
  /* Vector VRMLSLDAVH.  Note must appear before VMLSDAV due to instruction
2637
     opcode aliasing.  */
2638
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2639
   MVE_VRMLSLDAVH,
2640
   0xfe800e01, 0xff810f51,
2641
   "vrmlsldavh%5A%X%v.s32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2642
2643
  /* Vector VMLSLDAV.  Note must appear before VMLSDAV due to instruction
2644
     opcdoe aliasing.  */
2645
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2646
   MVE_VMLSLDAV,
2647
   0xee800e01, 0xff800f51,
2648
   "vmlsldav%5A%X%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2649
2650
  /* Vector VMLSDAV T1 Variant.  */
2651
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2652
   MVE_VMLSDAV_T1,
2653
   0xeef00e01, 0xfff00f51,
2654
   "vmlsdav%5A%X%v.s%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2655
2656
  /* Vector VMLSDAV T2 Variant.  */
2657
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2658
   MVE_VMLSDAV_T2,
2659
   0xfef00e01, 0xfff10f51,
2660
   "vmlsdav%5A%X%v.s8\t%13-15l, %17-19,7Q, %1-3Q"},
2661
2662
  /* Vector VMOV between gpr and half precision register, op == 0.  */
2663
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2664
   MVE_VMOV_HFP_TO_GP,
2665
   0xee000910, 0xfff00f7f,
2666
   "vmov.f16\t%7,16-19F, %12-15r"},
2667
2668
  /* Vector VMOV between gpr and half precision register, op == 1.  */
2669
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2670
   MVE_VMOV_HFP_TO_GP,
2671
   0xee100910, 0xfff00f7f,
2672
   "vmov.f16\t%12-15r, %7,16-19F"},
2673
2674
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2675
   MVE_VMOV_GP_TO_VEC_LANE,
2676
   0xee000b10, 0xff900f1f,
2677
   "vmov%c.%5-6,21-22s\t%{R:%17-19,7Q[%N]%}, %12-15r"},
2678
2679
  /* Vector VORR immediate to vector.
2680
     NOTE: MVE_VORR_IMM must appear in the table
2681
     before MVE_VMOV_IMM_TO_VEC due to opcode aliasing.  */
2682
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2683
   MVE_VORR_IMM,
2684
   0xef800050, 0xefb810f0,
2685
   "vorr%v.i%8-11s\t%13-15,22Q, %E"},
2686
2687
  /* Vector VQSHL T2 Variant.
2688
     NOTE: MVE_VQSHL_T2 must appear in the table before
2689
     before MVE_VMOV_IMM_TO_VEC due to opcode aliasing.  */
2690
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2691
   MVE_VQSHL_T2,
2692
   0xef800750, 0xef801fd1,
2693
   "vqshl%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
2694
2695
  /* Vector VQSHLU T3 Variant
2696
     NOTE: MVE_VQSHL_T2 must appear in the table before
2697
     before MVE_VMOV_IMM_TO_VEC due to opcode aliasing.  */
2698
2699
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2700
   MVE_VQSHLU_T3,
2701
   0xff800650, 0xff801fd1,
2702
   "vqshlu%v.s%19-21s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
2703
2704
  /* Vector VRSHR
2705
     NOTE: MVE_VRSHR must appear in the table before
2706
     before MVE_VMOV_IMM_TO_VEC due to opcode aliasing.  */
2707
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2708
   MVE_VRSHR,
2709
   0xef800250, 0xef801fd1,
2710
   "vrshr%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
2711
2712
  /* Vector VSHL.
2713
     NOTE: MVE_VSHL must appear in the table before
2714
     before MVE_VMOV_IMM_TO_VEC due to opcode aliasing.  */
2715
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2716
   MVE_VSHL_T1,
2717
   0xef800550, 0xff801fd1,
2718
   "vshl%v.i%19-21s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
2719
2720
  /* Vector VSHR
2721
     NOTE: MVE_VSHR must appear in the table before
2722
     before MVE_VMOV_IMM_TO_VEC due to opcode aliasing.  */
2723
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2724
   MVE_VSHR,
2725
   0xef800050, 0xef801fd1,
2726
   "vshr%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
2727
2728
  /* Vector VSLI
2729
     NOTE: MVE_VSLI must appear in the table before
2730
     before MVE_VMOV_IMM_TO_VEC due to opcode aliasing.  */
2731
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2732
   MVE_VSLI,
2733
   0xff800550, 0xff801fd1,
2734
   "vsli%v.%19-21s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
2735
2736
  /* Vector VSRI
2737
     NOTE: MVE_VSRI must appear in the table before
2738
     before MVE_VMOV_IMM_TO_VEC due to opcode aliasing.  */
2739
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2740
   MVE_VSRI,
2741
   0xff800450, 0xff801fd1,
2742
   "vsri%v.%19-21s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
2743
2744
  /* Vector VMOV immediate to vector,
2745
     undefinded for cmode == 1111 */
2746
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2747
   MVE_VMVN_IMM, 0xef800f70, 0xefb81ff0, UNDEFINED_INSTRUCTION},
2748
2749
  /* Vector VMOV immediate to vector,
2750
     cmode == 1101 */
2751
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2752
   MVE_VMOV_IMM_TO_VEC, 0xef800d50, 0xefb81fd0,
2753
   "vmov%v.%5,8-11s\t%13-15,22Q, %E"},
2754
2755
  /* Vector VMOV immediate to vector.  */
2756
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2757
   MVE_VMOV_IMM_TO_VEC,
2758
   0xef800050, 0xefb810d0,
2759
   "vmov%v.%5,8-11s\t%13-15,22Q, %E"},
2760
2761
  /* Vector VMOV two 32-bit lanes to two gprs, idx = 0.  */
2762
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2763
   MVE_VMOV2_VEC_LANE_TO_GP,
2764
   0xec000f00, 0xffb01ff0,
2765
   "vmov%c\t%0-3r, %16-19r, %{R:%13-15,22Q[2]%}, %{R:%13-15,22Q[0]%}"},
2766
2767
  /* Vector VMOV two 32-bit lanes to two gprs, idx = 1.  */
2768
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2769
   MVE_VMOV2_VEC_LANE_TO_GP,
2770
   0xec000f10, 0xffb01ff0,
2771
   "vmov%c\t%0-3r, %16-19r, %{R:%13-15,22Q[3]%}, %{R:%13-15,22Q[1]%}"},
2772
2773
  /* Vector VMOV Two gprs to two 32-bit lanes, idx = 0.  */
2774
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2775
   MVE_VMOV2_GP_TO_VEC_LANE,
2776
   0xec100f00, 0xffb01ff0,
2777
   "vmov%c\t%{R:%13-15,22Q[2]%}, %{R:%13-15,22Q[0]%}, %0-3r, %16-19r"},
2778
2779
  /* Vector VMOV Two gprs to two 32-bit lanes, idx = 1.  */
2780
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2781
   MVE_VMOV2_GP_TO_VEC_LANE,
2782
   0xec100f10, 0xffb01ff0,
2783
   "vmov%c\t%{R:%13-15,22Q[3]%}, %{R:%13-15,22Q[1]%}, %0-3r, %16-19r"},
2784
2785
  /* Vector VMOV Vector lane to gpr.  */
2786
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2787
   MVE_VMOV_VEC_LANE_TO_GP,
2788
   0xee100b10, 0xff100f1f,
2789
   "vmov%c.%u%5-6,21-22s\t%12-15r, %{R:%17-19,7Q[%N]%}"},
2790
2791
  /* Vector VSHLL T1 Variant.  Note: VSHLL T1 must appear before MVE_VMOVL due
2792
     to instruction opcode aliasing.  */
2793
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2794
   MVE_VSHLL_T1,
2795
   0xeea00f40, 0xefa00fd1,
2796
   "vshll%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
2797
2798
  /* Vector VMOVL long.  */
2799
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2800
   MVE_VMOVL,
2801
   0xeea00f40, 0xefa70fd1,
2802
   "vmovl%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q"},
2803
2804
  /* Vector VMOV and narrow.  */
2805
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2806
   MVE_VMOVN,
2807
   0xfe310e81, 0xffb30fd1,
2808
   "vmovn%T%v.i%18-19s\t%13-15,22Q, %1-3,5Q"},
2809
2810
  /* Floating point move extract.  */
2811
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2812
   MVE_VMOVX,
2813
   0xfeb00a40, 0xffbf0fd0,
2814
   "vmovx.f16\t%22,12-15F, %5,0-3F"},
2815
2816
  /* Vector VMUL floating-point T1 variant.  */
2817
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2818
   MVE_VMUL_FP_T1,
2819
   0xff000d50, 0xffa11f51,
2820
   "vmul%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2821
2822
  /* Vector VMUL floating-point T2 variant.  */
2823
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2824
   MVE_VMUL_FP_T2,
2825
   0xee310e60, 0xefb11f70,
2826
   "vmul%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2827
2828
  /* Vector VMUL T1 variant.  */
2829
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2830
   MVE_VMUL_VEC_T1,
2831
   0xef000950, 0xff811f51,
2832
   "vmul%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2833
2834
  /* Vector VMUL T2 variant.  */
2835
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2836
   MVE_VMUL_VEC_T2,
2837
   0xee011e60, 0xff811f70,
2838
   "vmul%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2839
2840
  /* Vector VMULH.  */
2841
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2842
   MVE_VMULH,
2843
   0xee010e01, 0xef811f51,
2844
   "vmulh%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2845
2846
  /* Vector VRMULH.  */
2847
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2848
   MVE_VRMULH,
2849
   0xee011e01, 0xef811f51,
2850
   "vrmulh%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2851
2852
  /* Vector VMULL integer.  */
2853
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2854
   MVE_VMULL_INT,
2855
   0xee010e00, 0xef810f51,
2856
   "vmull%T%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2857
2858
  /* Vector VMULL polynomial.  */
2859
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2860
   MVE_VMULL_POLY,
2861
   0xee310e00, 0xefb10f51,
2862
   "vmull%T%v.%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2863
2864
  /* Vector VMVN immediate to vector.  */
2865
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2866
   MVE_VMVN_IMM,
2867
   0xef800070, 0xefb810f0,
2868
   "vmvn%v.i%8-11s\t%13-15,22Q, %E"},
2869
2870
  /* Vector VMVN register.  */
2871
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2872
   MVE_VMVN_REG,
2873
   0xffb005c0, 0xffbf1fd1,
2874
   "vmvn%v\t%13-15,22Q, %1-3,5Q"},
2875
2876
  /* Vector VNEG floating point.  */
2877
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2878
   MVE_VNEG_FP,
2879
   0xffb107c0, 0xffb31fd1,
2880
   "vneg%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
2881
2882
  /* Vector VNEG.  */
2883
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2884
   MVE_VNEG_VEC,
2885
   0xffb103c0, 0xffb31fd1,
2886
   "vneg%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2887
2888
  /* Vector VORN, vector bitwise or not.  */
2889
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2890
   MVE_VORN,
2891
   0xef300150, 0xffb11f51,
2892
   "vorn%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2893
2894
  /* Vector VORR register.  */
2895
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2896
   MVE_VORR_REG,
2897
   0xef200150, 0xffb11f51,
2898
   "vorr%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2899
2900
  /* Vector VMOV, vector to vector move. While decoding MVE_VORR_REG if
2901
     "Qm==Qn", VORR should replaced by its alias VMOV. For that to happen
2902
     MVE_VMOV_VEC_TO_VEC need to placed after MVE_VORR_REG in this mve_opcodes
2903
     array.  */
2904
2905
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2906
   MVE_VMOV_VEC_TO_VEC,
2907
   0xef200150, 0xffb11f51,
2908
   "vmov%v\t%13-15,22Q, %17-19,7Q"},
2909
2910
  /* Vector VQDMULL T1 variant.  */
2911
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2912
   MVE_VQDMULL_T1,
2913
   0xee300f01, 0xefb10f51,
2914
   "vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2915
2916
  /* Vector VPNOT.  */
2917
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2918
   MVE_VPNOT,
2919
   0xfe310f4d, 0xffffffff,
2920
   "vpnot%v"},
2921
2922
  /* Vector VPSEL.  */
2923
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2924
   MVE_VPSEL,
2925
   0xfe310f01, 0xffb11f51,
2926
   "vpsel%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2927
2928
  /* Vector VQABS.  */
2929
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2930
   MVE_VQABS,
2931
   0xffb00740, 0xffb31fd1,
2932
   "vqabs%v.s%18-19s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2933
2934
  /* Vector VQADD T1 variant.  */
2935
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2936
   MVE_VQADD_T1,
2937
   0xef000050, 0xef811f51,
2938
   "vqadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2939
2940
  /* Vector VQADD T2 variant.  */
2941
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2942
   MVE_VQADD_T2,
2943
   0xee000f60, 0xef811f70,
2944
   "vqadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2945
2946
  /* Vector VQDMULL T2 variant.  */
2947
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2948
   MVE_VQDMULL_T2,
2949
   0xee300f60, 0xefb10f70,
2950
   "vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2951
2952
  /* Vector VQMOVN.  */
2953
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2954
   MVE_VQMOVN,
2955
   0xee330e01, 0xefb30fd1,
2956
   "vqmovn%T%v.%u%18-19s\t%13-15,22Q, %1-3,5Q"},
2957
2958
  /* Vector VQMOVUN.  */
2959
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2960
   MVE_VQMOVUN,
2961
   0xee310e81, 0xffb30fd1,
2962
   "vqmovun%T%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2963
2964
  /* Vector VQDMLADH.  */
2965
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2966
   MVE_VQDMLADH,
2967
   0xee000e00, 0xff810f51,
2968
   "vqdmladh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2969
2970
  /* Vector VQRDMLADH.  */
2971
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2972
   MVE_VQRDMLADH,
2973
   0xee000e01, 0xff810f51,
2974
   "vqrdmladh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2975
2976
  /* Vector VQDMLAH.  */
2977
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2978
   MVE_VQDMLAH,
2979
   0xee000e60, 0xff811f70,
2980
   "vqdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2981
2982
  /* Vector VQRDMLAH.  */
2983
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2984
   MVE_VQRDMLAH,
2985
   0xee000e40, 0xff811f70,
2986
   "vqrdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2987
2988
  /* Vector VQDMLASH.  */
2989
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2990
   MVE_VQDMLASH,
2991
   0xee001e60, 0xff811f70,
2992
   "vqdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2993
2994
  /* Vector VQRDMLASH.  */
2995
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2996
   MVE_VQRDMLASH,
2997
   0xee001e40, 0xff811f70,
2998
   "vqrdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2999
3000
  /* Vector VQDMLSDH.  */
3001
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3002
   MVE_VQDMLSDH,
3003
   0xfe000e00, 0xff810f51,
3004
   "vqdmlsdh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3005
3006
  /* Vector VQRDMLSDH.  */
3007
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3008
   MVE_VQRDMLSDH,
3009
   0xfe000e01, 0xff810f51,
3010
   "vqrdmlsdh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3011
3012
  /* Vector VQDMULH T1 variant.  */
3013
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3014
   MVE_VQDMULH_T1,
3015
   0xef000b40, 0xff811f51,
3016
   "vqdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3017
3018
  /* Vector VQRDMULH T2 variant.  */
3019
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3020
   MVE_VQRDMULH_T2,
3021
   0xff000b40, 0xff811f51,
3022
   "vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3023
3024
  /* Vector VQDMULH T3 variant.  */
3025
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3026
   MVE_VQDMULH_T3,
3027
   0xee010e60, 0xff811f70,
3028
   "vqdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3029
3030
  /* Vector VQRDMULH T4 variant.  */
3031
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3032
   MVE_VQRDMULH_T4,
3033
   0xfe010e60, 0xff811f70,
3034
   "vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3035
3036
  /* Vector VQNEG.  */
3037
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3038
   MVE_VQNEG,
3039
   0xffb007c0, 0xffb31fd1,
3040
   "vqneg%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
3041
3042
  /* Vector VQRSHL T1 variant.  */
3043
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3044
   MVE_VQRSHL_T1,
3045
   0xef000550, 0xef811f51,
3046
   "vqrshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3047
3048
  /* Vector VQRSHL T2 variant.  */
3049
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3050
   MVE_VQRSHL_T2,
3051
   0xee331ee0, 0xefb31ff0,
3052
   "vqrshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3053
3054
  /* Vector VQRSHRN.  */
3055
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3056
   MVE_VQRSHRN,
3057
   0xee800f41, 0xefa00fd1,
3058
   "vqrshrn%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
3059
3060
  /* Vector VQRSHRUN.  */
3061
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3062
   MVE_VQRSHRUN,
3063
   0xfe800fc0, 0xffa00fd1,
3064
   "vqrshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
3065
3066
  /* Vector VQSHL T1 Variant.  */
3067
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3068
   MVE_VQSHL_T1,
3069
   0xee311ee0, 0xefb31ff0,
3070
   "vqshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3071
3072
  /* Vector VQSHL T4 Variant.  */
3073
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3074
   MVE_VQSHL_T4,
3075
   0xef000450, 0xef811f51,
3076
   "vqshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3077
3078
  /* Vector VQSHRN.  */
3079
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3080
   MVE_VQSHRN,
3081
   0xee800f40, 0xefa00fd1,
3082
   "vqshrn%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
3083
3084
  /* Vector VQSHRUN.  */
3085
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3086
   MVE_VQSHRUN,
3087
   0xee800fc0, 0xffa00fd1,
3088
   "vqshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
3089
3090
  /* Vector VQSUB T1 Variant.  */
3091
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3092
   MVE_VQSUB_T1,
3093
   0xef000250, 0xef811f51,
3094
   "vqsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3095
3096
  /* Vector VQSUB T2 Variant.  */
3097
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3098
   MVE_VQSUB_T2,
3099
   0xee001f60, 0xef811f70,
3100
   "vqsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3101
3102
  /* Vector VREV16.  */
3103
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3104
   MVE_VREV16,
3105
   0xffb00140, 0xffb31fd1,
3106
   "vrev16%v.8\t%13-15,22Q, %1-3,5Q"},
3107
3108
  /* Vector VREV32.  */
3109
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3110
   MVE_VREV32,
3111
   0xffb000c0, 0xffb31fd1,
3112
   "vrev32%v.%18-19s\t%13-15,22Q, %1-3,5Q"},
3113
3114
  /* Vector VREV64.  */
3115
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3116
   MVE_VREV64,
3117
   0xffb00040, 0xffb31fd1,
3118
   "vrev64%v.%18-19s\t%13-15,22Q, %1-3,5Q"},
3119
3120
  /* Vector VRINT floating point.  */
3121
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
3122
   MVE_VRINT_FP,
3123
   0xffb20440, 0xffb31c51,
3124
   "vrint%m%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
3125
3126
  /* Vector VRMLALDAVH.  */
3127
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3128
   MVE_VRMLALDAVH,
3129
   0xee800f00, 0xef811f51,
3130
   "vrmlalvh%5A%v.%u32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
3131
3132
  /* Vector VRMLALDAVH.  */
3133
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3134
   MVE_VRMLALDAVH,
3135
   0xee801f00, 0xef811f51,
3136
   "vrmlaldavh%5Ax%v.%u32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
3137
3138
  /* Vector VRSHL T1 Variant.  */
3139
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3140
   MVE_VRSHL_T1,
3141
   0xef000540, 0xef811f51,
3142
   "vrshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3143
3144
  /* Vector VRSHL T2 Variant.  */
3145
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3146
   MVE_VRSHL_T2,
3147
   0xee331e60, 0xefb31ff0,
3148
   "vrshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3149
3150
  /* Vector VRSHRN.  */
3151
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3152
   MVE_VRSHRN,
3153
   0xfe800fc1, 0xffa00fd1,
3154
   "vrshrn%T%v.i%19-20s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
3155
3156
  /* Vector VSBC.  */
3157
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3158
   MVE_VSBC,
3159
   0xfe300f00, 0xffb10f51,
3160
   "vsbc%12I%v.i32\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3161
3162
  /* Vector VSHL T2 Variant.  */
3163
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3164
   MVE_VSHL_T2,
3165
   0xee311e60, 0xefb31ff0,
3166
   "vshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3167
3168
  /* Vector VSHL T3 Variant.  */
3169
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3170
   MVE_VSHL_T3,
3171
   0xef000440, 0xef811f51,
3172
   "vshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3173
3174
  /* Vector VSHLC.  */
3175
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3176
   MVE_VSHLC,
3177
   0xeea00fc0, 0xffa01ff0,
3178
   "vshlc%v\t%13-15,22Q, %0-3r, %{I:#%16-20d%}"},
3179
3180
  /* Vector VSHLL T2 Variant.  */
3181
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3182
   MVE_VSHLL_T2,
3183
   0xee310e01, 0xefb30fd1,
3184
   "vshll%T%v.%u%18-19s\t%13-15,22Q, %1-3,5Q, %{I:#%18-19d%}"},
3185
3186
  /* Vector VSHRN.  */
3187
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3188
   MVE_VSHRN,
3189
   0xee800fc1, 0xffa00fd1,
3190
   "vshrn%T%v.i%19-20s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
3191
3192
  /* Vector VST2 no writeback.  */
3193
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3194
   MVE_VST2,
3195
   0xfc801e00, 0xffb01e5f,
3196
   "vst2%5d.%7-8s\t%B, [%16-19r]"},
3197
3198
  /* Vector VST2 writeback.  */
3199
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3200
   MVE_VST2,
3201
   0xfca01e00, 0xffb01e5f,
3202
   "vst2%5d.%7-8s\t%B, [%16-19r]!"},
3203
3204
  /* Vector VST4 no writeback.  */
3205
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3206
   MVE_VST4,
3207
   0xfc801e01, 0xffb01e1f,
3208
   "vst4%5-6d.%7-8s\t%B, [%16-19r]"},
3209
3210
  /* Vector VST4 writeback.  */
3211
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3212
   MVE_VST4,
3213
   0xfca01e01, 0xffb01e1f,
3214
   "vst4%5-6d.%7-8s\t%B, [%16-19r]!"},
3215
3216
  /* Vector VSTRB scatter store, T1 variant.  */
3217
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3218
   MVE_VSTRB_SCATTER_T1,
3219
   0xec800e00, 0xffb01e50,
3220
   "vstrb%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"},
3221
3222
  /* Vector VSTRH scatter store, T2 variant.  */
3223
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3224
   MVE_VSTRH_SCATTER_T2,
3225
   0xec800e10, 0xffb01e50,
3226
   "vstrh%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
3227
3228
  /* Vector VSTRW scatter store, T3 variant.  */
3229
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3230
   MVE_VSTRW_SCATTER_T3,
3231
   0xec800e40, 0xffb01e50,
3232
   "vstrw%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
3233
3234
  /* Vector VSTRD scatter store, T4 variant.  */
3235
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3236
   MVE_VSTRD_SCATTER_T4,
3237
   0xec800fd0, 0xffb01fd0,
3238
   "vstrd%v.64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
3239
3240
  /* Vector VSTRW scatter store, T5 variant.  */
3241
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3242
   MVE_VSTRW_SCATTER_T5,
3243
   0xfd001e00, 0xff111f00,
3244
   "vstrw%v.32\t%13-15,22Q, [%17-19,7Q, %{I:#%a%0-6i%}]%w"},
3245
3246
  /* Vector VSTRD scatter store, T6 variant.  */
3247
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3248
   MVE_VSTRD_SCATTER_T6,
3249
   0xfd001f00, 0xff111f00,
3250
   "vstrd%v.64\t%13-15,22Q, [%17-19,7Q, %{I:#%a%0-6i%}]%w"},
3251
3252
  /* Vector VSTRB.  */
3253
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3254
   MVE_VSTRB_T1,
3255
   0xec000e00, 0xfe581e00,
3256
   "vstrb%v.%7-8s\t%13-15Q, %d"},
3257
3258
  /* Vector VSTRH.  */
3259
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3260
   MVE_VSTRH_T2,
3261
   0xec080e00, 0xfe581e00,
3262
   "vstrh%v.%7-8s\t%13-15Q, %d"},
3263
3264
  /* Vector VSTRB variant T5.  */
3265
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3266
   MVE_VSTRB_T5,
3267
   0xec001e00, 0xfe101f80,
3268
   "vstrb%v.8\t%13-15,22Q, %d"},
3269
3270
  /* Vector VSTRH variant T6.  */
3271
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3272
   MVE_VSTRH_T6,
3273
   0xec001e80, 0xfe101f80,
3274
   "vstrh%v.16\t%13-15,22Q, %d"},
3275
3276
  /* Vector VSTRW variant T7.  */
3277
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3278
   MVE_VSTRW_T7,
3279
   0xec001f00, 0xfe101f80,
3280
   "vstrw%v.32\t%13-15,22Q, %d"},
3281
3282
  /* Vector VSUB floating point T1 variant.  */
3283
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
3284
   MVE_VSUB_FP_T1,
3285
   0xef200d40, 0xffa11f51,
3286
   "vsub%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3287
3288
  /* Vector VSUB floating point T2 variant.  */
3289
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
3290
   MVE_VSUB_FP_T2,
3291
   0xee301f40, 0xefb11f70,
3292
   "vsub%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3293
3294
  /* Vector VSUB T1 variant.  */
3295
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3296
   MVE_VSUB_VEC_T1,
3297
   0xff000840, 0xff811f51,
3298
   "vsub%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3299
3300
  /* Vector VSUB T2 variant.  */
3301
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3302
   MVE_VSUB_VEC_T2,
3303
   0xee011f40, 0xff811f70,
3304
   "vsub%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3305
3306
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3307
   MVE_ASRLI,
3308
   0xea50012f, 0xfff1813f,
3309
   "asrl%c\t%17-19l, %9-11h, %j"},
3310
3311
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3312
   MVE_ASRL,
3313
   0xea50012d, 0xfff101ff,
3314
   "asrl%c\t%17-19l, %9-11h, %12-15S"},
3315
3316
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3317
   MVE_LSLLI,
3318
   0xea50010f, 0xfff1813f,
3319
   "lsll%c\t%17-19l, %9-11h, %j"},
3320
3321
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3322
   MVE_LSLL,
3323
   0xea50010d, 0xfff101ff,
3324
   "lsll%c\t%17-19l, %9-11h, %12-15S"},
3325
3326
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3327
   MVE_LSRL,
3328
   0xea50011f, 0xfff1813f,
3329
   "lsrl%c\t%17-19l, %9-11h, %j"},
3330
3331
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3332
   MVE_SQRSHRL,
3333
   0xea51012d, 0xfff1017f,
3334
   "sqrshrl%c\t%17-19l, %9-11h, %k, %12-15S"},
3335
3336
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3337
   MVE_SQRSHR,
3338
   0xea500f2d, 0xfff00fff,
3339
   "sqrshr%c\t%16-19S, %12-15S"},
3340
3341
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3342
   MVE_SQSHLL,
3343
   0xea51013f, 0xfff1813f,
3344
   "sqshll%c\t%17-19l, %9-11h, %j"},
3345
3346
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3347
   MVE_SQSHL,
3348
   0xea500f3f, 0xfff08f3f,
3349
   "sqshl%c\t%16-19S, %j"},
3350
3351
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3352
   MVE_SRSHRL,
3353
   0xea51012f, 0xfff1813f,
3354
   "srshrl%c\t%17-19l, %9-11h, %j"},
3355
3356
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3357
   MVE_SRSHR,
3358
   0xea500f2f, 0xfff08f3f,
3359
   "srshr%c\t%16-19S, %j"},
3360
3361
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3362
   MVE_UQRSHLL,
3363
   0xea51010d, 0xfff1017f,
3364
   "uqrshll%c\t%17-19l, %9-11h, %k, %12-15S"},
3365
3366
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3367
   MVE_UQRSHL,
3368
   0xea500f0d, 0xfff00fff,
3369
   "uqrshl%c\t%16-19S, %12-15S"},
3370
3371
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3372
   MVE_UQSHLL,
3373
    0xea51010f, 0xfff1813f,
3374
   "uqshll%c\t%17-19l, %9-11h, %j"},
3375
3376
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3377
   MVE_UQSHL,
3378
   0xea500f0f, 0xfff08f3f,
3379
   "uqshl%c\t%16-19S, %j"},
3380
3381
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3382
   MVE_URSHRL,
3383
    0xea51011f, 0xfff1813f,
3384
   "urshrl%c\t%17-19l, %9-11h, %j"},
3385
3386
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3387
   MVE_URSHR,
3388
   0xea500f1f, 0xfff08f3f,
3389
   "urshr%c\t%16-19S, %j"},
3390
3391
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3392
   MVE_CSINC,
3393
   0xea509000, 0xfff0f000,
3394
   "csinc\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3395
3396
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3397
   MVE_CSINV,
3398
   0xea50a000, 0xfff0f000,
3399
   "csinv\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3400
3401
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3402
   MVE_CSET,
3403
   0xea5f900f, 0xfffff00f,
3404
   "cset\t%8-11S, %4-7C"},
3405
3406
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3407
   MVE_CSETM,
3408
   0xea5fa00f, 0xfffff00f,
3409
   "csetm\t%8-11S, %4-7C"},
3410
3411
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3412
   MVE_CSEL,
3413
   0xea508000, 0xfff0f000,
3414
   "csel\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3415
3416
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3417
   MVE_CSNEG,
3418
   0xea50b000, 0xfff0f000,
3419
   "csneg\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3420
3421
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3422
   MVE_CINC,
3423
   0xea509000, 0xfff0f000,
3424
   "cinc\t%8-11S, %16-19Z, %4-7C"},
3425
3426
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3427
   MVE_CINV,
3428
   0xea50a000, 0xfff0f000,
3429
   "cinv\t%8-11S, %16-19Z, %4-7C"},
3430
3431
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3432
   MVE_CNEG,
3433
   0xea50b000, 0xfff0f000,
3434
   "cneg\t%8-11S, %16-19Z, %4-7C"},
3435
3436
  {ARM_FEATURE_CORE_LOW (0),
3437
   MVE_NONE,
3438
   0x00000000, 0x00000000, 0}
3439
};
3440
3441
/* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb.  All three are partially
3442
   ordered: they must be searched linearly from the top to obtain a correct
3443
   match.  */
3444
3445
/* print_insn_arm recognizes the following format control codes:
3446
3447
   %%     %
3448
3449
   %a     print address for ldr/str instruction
3450
   %s                   print address for ldr/str halfword/signextend instruction
3451
   %S                   like %s but allow UNPREDICTABLE addressing
3452
   %b     print branch destination
3453
   %c     print condition code (always bits 28-31)
3454
   %m     print register mask for ldm/stm instruction
3455
   %o     print operand2 (immediate or register + shift)
3456
   %p     print 'p' iff bits 12-15 are 15
3457
   %t     print 't' iff bit 21 set and bit 24 clear
3458
   %B     print arm BLX(1) destination
3459
   %C     print the PSR sub type.
3460
   %U     print barrier type.
3461
   %P     print address for pli instruction.
3462
3463
   %<bitfield>r   print as an ARM register
3464
   %<bitfield>T   print as an ARM register + 1
3465
   %<bitfield>R   as %r but r15 is UNPREDICTABLE
3466
   %<bitfield>{r|R}u    as %{r|R} but if matches the other %u field then is UNPREDICTABLE
3467
   %<bitfield>{r|R}U    as %{r|R} but if matches the other %U field then is UNPREDICTABLE
3468
   %<bitfield>d   print the bitfield in decimal
3469
   %<bitfield>W         print the bitfield plus one in decimal
3470
   %<bitfield>x   print the bitfield in hex
3471
   %<bitfield>X   print the bitfield as 1 hex digit without leading "0x"
3472
3473
   %<bitfield>'c  print specified char iff bitfield is all ones
3474
   %<bitfield>`c  print specified char iff bitfield is all zeroes
3475
   %<bitfield>?ab...    select from array of values in big endian order
3476
3477
   %e                   print arm SMI operand (bits 0..7,8..19).
3478
   %E     print the LSB and WIDTH fields of a BFI or BFC instruction.
3479
   %V                   print the 16-bit immediate field of a MOVT or MOVW instruction.
3480
   %R     print the SPSR/CPSR or banked register of an MRS.  */
3481
3482
static const struct opcode32 arm_opcodes[] =
3483
{
3484
  /* ARM instructions.  */
3485
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3486
    0xe1a00000, 0xffffffff, "nop\t\t\t@ (mov r0, r0)"},
3487
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3488
    0xe7f000f0, 0xfff000f0, "udf\t%{I:#%e%}"},
3489
3490
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T | ARM_EXT_V5),
3491
    0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
3492
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
3493
    0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"},
3494
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
3495
    0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3496
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V2S),
3497
    0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"},
3498
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
3499
    0x00800090, 0x0fa000f0,
3500
    "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3501
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
3502
    0x00a00090, 0x0fa000f0,
3503
    "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3504
3505
  /* V8.2 RAS extension instructions.  */
3506
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
3507
    0xe320f010, 0xffffffff, "esb"},
3508
3509
  /* V8-R instructions.  */
3510
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8R),
3511
    0xf57ff04c, 0xffffffff, "dfb"},
3512
3513
  /* V8 instructions.  */
3514
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3515
    0x0320f005, 0x0fffffff, "sevl"},
3516
  /* Defined in V8 but is in NOP space so available to all arch.  */
3517
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3518
    0xe1000070, 0xfff000f0, "hlt\t%{I:0x%16-19X%12-15X%8-11X%0-3X%}"},
3519
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS),
3520
    0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"},
3521
  {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3522
    0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
3523
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3524
    0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"},
3525
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3526
    0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"},
3527
  {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3528
    0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"},
3529
  {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3530
    0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
3531
  {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3532
    0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"},
3533
  {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3534
    0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
3535
  {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3536
    0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"},
3537
  {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3538
    0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"},
3539
  {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3540
    0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"},
3541
  {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3542
    0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"},
3543
  {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3544
    0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"},
3545
  {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3546
    0x01f00c9f, 0x0ff00fff, "ldah%c\t%12-15r, [%16-19R]"},
3547
  /* CRC32 instructions.  */
3548
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
3549
    0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"},
3550
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
3551
    0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"},
3552
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
3553
    0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"},
3554
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
3555
    0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"},
3556
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
3557
    0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"},
3558
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
3559
    0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"},
3560
3561
  /* Privileged Access Never extension instructions.  */
3562
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),
3563
    0xf1100000, 0xfffffdff, "setpan\t%{I:#%9-9d%}"},
3564
3565
  /* Virtualization Extension instructions.  */
3566
  {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x0160006e, 0x0fffffff, "eret%c"},
3567
  {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x01400070, 0x0ff000f0, "hvc%c\t%e"},
3568
3569
  /* Integer Divide Extension instructions.  */
3570
  {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
3571
    0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"},
3572
  {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
3573
    0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"},
3574
3575
  /* MP Extension instructions.  */
3576
  {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf410f000, 0xfc70f000, "pldw\t%a"},
3577
3578
  /* Speculation Barriers.  */
3579
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xe320f014, 0xffffffff, "csdb"},
3580
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff040, 0xffffffff, "ssbb"},
3581
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff044, 0xffffffff, "pssbb"},
3582
3583
  /* V7 instructions.  */
3584
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf450f000, 0xfd70f000, "pli\t%P"},
3585
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0x0320f0f0, 0x0ffffff0, "dbg%c\t%{I:#%0-3d%}"},
3586
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff051, 0xfffffff3, "dmb\t%U"},
3587
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff041, 0xfffffff3, "dsb\t%U"},
3588
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff050, 0xfffffff0, "dmb\t%U"},
3589
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff040, 0xfffffff0, "dsb\t%U"},
3590
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff060, 0xfffffff0, "isb\t%U"},
3591
   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
3592
    0x0320f000, 0x0fffffff, "nop%c\t{%{I:%0-7d%}}"},
3593
3594
  /* ARM V6T2 instructions.  */
3595
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3596
    0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"},
3597
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3598
    0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"},
3599
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3600
    0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3601
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3602
    0x002000b0, 0x0f3000f0, "strht%c\t%12-15R, %S"},
3603
3604
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3605
    0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION },
3606
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3607
    0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"},
3608
3609
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3610
    0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"},
3611
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3612
    0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"},
3613
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3614
    0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"},
3615
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3616
    0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, %{I:#%7-11d%}, %{I:#%16-20W%}"},
3617
3618
  /* ARM Security extension instructions.  */
3619
  {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
3620
    0x01600070, 0x0ff000f0, "smc%c\t%e"},
3621
3622
  /* ARM V6K instructions.  */
3623
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3624
    0xf57ff01f, 0xffffffff, "clrex"},
3625
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3626
    0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"},
3627
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3628
    0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"},
3629
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3630
    0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"},
3631
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3632
    0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"},
3633
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3634
    0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"},
3635
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3636
    0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"},
3637
3638
  /* ARMv8.5-A instructions.  */
3639
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf57ff070, 0xffffffff, "sb"},
3640
3641
  /* ARM V6K NOP hints.  */
3642
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3643
    0x0320f001, 0x0fffffff, "yield%c"},
3644
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3645
    0x0320f002, 0x0fffffff, "wfe%c"},
3646
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3647
    0x0320f003, 0x0fffffff, "wfi%c"},
3648
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3649
    0x0320f004, 0x0fffffff, "sev%c"},
3650
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3651
    0x0320f000, 0x0fffff00, "nop%c\t{%{I:%0-7d%}}"},
3652
3653
  /* ARM V6 instructions.  */
3654
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3655
    0xf1080000, 0xfffffe3f, "cpsie\t%{B:%8'a%7'i%6'f%}"},
3656
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3657
    0xf10a0000, 0xfffffe20, "cpsie\t%{B:%8'a%7'i%6'f%}, %{I:#%0-4d%}"},
3658
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3659
    0xf10C0000, 0xfffffe3f, "cpsid\t%{B:%8'a%7'i%6'f%}"},
3660
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3661
    0xf10e0000, 0xfffffe20, "cpsid\t%{B:%8'a%7'i%6'f%}, %{I:#%0-4d%}"},
3662
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3663
    0xf1000000, 0xfff1fe20, "cps\t%{I:#%0-4d%}"},
3664
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3665
    0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"},
3666
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3667
    0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, %{B:lsl%} %{I:#%7-11d%}"},
3668
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3669
    0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, %{B:asr%} %{I:#32%}"},
3670
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3671
    0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, %{B:asr%} %{I:#%7-11d%}"},
3672
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3673
    0x01900f9f, 0x0ff00fff, "ldrex%c\t%{R:r%12-15d%}, [%16-19R]"},
3674
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3675
    0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"},
3676
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3677
    0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"},
3678
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3679
    0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"},
3680
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3681
    0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"},
3682
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3683
    0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"},
3684
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3685
    0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"},
3686
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3687
    0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"},
3688
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3689
    0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"},
3690
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3691
    0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"},
3692
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3693
    0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"},
3694
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3695
    0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"},
3696
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3697
    0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"},
3698
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3699
    0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"},
3700
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3701
    0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"},
3702
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3703
    0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"},
3704
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3705
    0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"},
3706
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3707
    0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"},
3708
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3709
    0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"},
3710
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3711
    0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"},
3712
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3713
    0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"},
3714
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3715
    0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"},
3716
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3717
    0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"},
3718
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3719
    0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"},
3720
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3721
    0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"},
3722
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3723
    0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"},
3724
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3725
    0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"},
3726
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3727
    0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"},
3728
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3729
    0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"},
3730
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3731
    0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"},
3732
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3733
    0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"},
3734
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3735
    0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"},
3736
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3737
    0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"},
3738
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3739
    0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"},
3740
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3741
    0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"},
3742
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3743
    0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"},
3744
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3745
    0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"},
3746
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3747
    0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"},
3748
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3749
    0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"},
3750
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3751
    0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"},
3752
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3753
    0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"},
3754
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3755
    0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"},
3756
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3757
    0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, %{B:ror%} %{I:#8%}"},
3758
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3759
    0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, %{B:ror%} %{I:#16%}"},
3760
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3761
    0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, %{B:ror%} %{I:#24%}"},
3762
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3763
    0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"},
3764
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3765
    0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, %{B:ror%} %{I:#8%}"},
3766
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3767
    0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, %{B:ror%} %{I:#16%}"},
3768
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3769
    0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, %{B:ror%} %{I:#24%}"},
3770
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3771
    0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"},
3772
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3773
    0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, %{B:ror%} %{I:#8%}"},
3774
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3775
    0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, %{B:ror%} %{I:#16%}"},
3776
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3777
    0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, %{B:ror%} %{I:#24%}"},
3778
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3779
    0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"},
3780
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3781
    0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, %{B:ror%} %{I:#8%}"},
3782
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3783
    0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, %{B:ror%} %{I:#16%}"},
3784
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3785
    0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, %{B:ror%} %{I:#24%}"},
3786
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3787
    0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"},
3788
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3789
    0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, %{B:ror%} %{I:#8%}"},
3790
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3791
    0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, %{B:ror%} %{I:#16%}"},
3792
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3793
    0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, %{B:ror%} %{I:#24%}"},
3794
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3795
    0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"},
3796
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3797
    0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, %{B:ror%} %{I:#8%}"},
3798
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3799
    0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, %{B:ror%} %{I:#16%}"},
3800
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3801
    0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, %{B:ror%} %{I:#24%}"},
3802
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3803
    0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"},
3804
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3805
    0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#8%}"},
3806
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3807
    0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#16%}"},
3808
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3809
    0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#24%}"},
3810
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3811
    0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"},
3812
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3813
    0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#8%}"},
3814
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3815
    0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#16%}"},
3816
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3817
    0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#24%}"},
3818
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3819
    0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"},
3820
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3821
    0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#8%}"},
3822
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3823
    0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#16%}"},
3824
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3825
    0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#24%}"},
3826
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3827
    0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"},
3828
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3829
    0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#8%}"},
3830
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3831
    0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#16%}"},
3832
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3833
    0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#24%}"},
3834
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3835
    0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"},
3836
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3837
    0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#8%}"},
3838
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3839
    0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#16%}"},
3840
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3841
    0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR %{I:#24%}"},
3842
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3843
    0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"},
3844
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3845
    0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#8%}"},
3846
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3847
    0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#16%}"},
3848
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3849
    0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#24%}"},
3850
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3851
    0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"},
3852
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3853
    0xf1010000, 0xfffffc00, "setend\t%{B:%9?ble%}"},
3854
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3855
    0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"},
3856
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3857
    0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"},
3858
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3859
    0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3860
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3861
    0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3862
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3863
    0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3864
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3865
    0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3866
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3867
    0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"},
3868
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3869
    0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3870
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3871
    0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3872
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3873
    0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, %{I:#%0-4d%}"},
3874
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3875
    0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, %{I:#%16-20W%}, %0-3R"},
3876
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3877
    0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, %{I:#%16-20W%}, %0-3R, %{B:lsl%} %{I:#%7-11d%}"},
3878
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3879
    0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, %{I:#%16-20W%}, %0-3R, %{B:asr%} %{I:#%7-11d%}"},
3880
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3881
    0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, %{I:#%16-19W%}, %0-3r"},
3882
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3883
    0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"},
3884
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3885
    0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"},
3886
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3887
    0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"},
3888
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3889
    0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3890
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3891
    0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, %{I:#%16-20d%}, %0-3R"},
3892
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3893
    0x06e00010, 0x0fe00070, "usat%c\t%12-15R, %{I:#%16-20d%}, %0-3R, %{B:lsl%} %{I:#%7-11d%}"},
3894
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3895
    0x06e00050, 0x0fe00070, "usat%c\t%12-15R, %{I:#%16-20d%}, %0-3R, %{B:asr%} %{I:#%7-11d%}"},
3896
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3897
    0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, %{I:#%16-19d%}, %0-3R"},
3898
3899
  /* V5J instruction.  */
3900
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5J),
3901
    0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"},
3902
3903
  /* V5 Instructions.  */
3904
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
3905
    0xe1200070, 0xfff000f0,
3906
    "bkpt\t%{I:0x%16-19X%12-15X%8-11X%0-3X%}"},
3907
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
3908
    0xfa000000, 0xfe000000, "blx\t%B"},
3909
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
3910
    0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"},
3911
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
3912
    0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"},
3913
3914
  /* V5E "El Segundo" Instructions.  */
3915
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
3916
    0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"},
3917
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
3918
    0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"},
3919
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
3920
    0xf450f000, 0xfc70f000, "pld\t%a"},
3921
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3922
    0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3923
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3924
    0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3925
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3926
    0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3927
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3928
    0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"},
3929
3930
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3931
    0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3932
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3933
    0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"},
3934
3935
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3936
    0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3937
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3938
    0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3939
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3940
    0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3941
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3942
    0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3943
3944
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3945
    0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"},
3946
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3947
    0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"},
3948
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3949
    0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"},
3950
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3951
    0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"},
3952
3953
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3954
    0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"},
3955
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3956
    0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"},
3957
3958
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3959
    0x01000050, 0x0ff00ff0,  "qadd%c\t%12-15R, %0-3R, %16-19R"},
3960
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3961
    0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"},
3962
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3963
    0x01200050, 0x0ff00ff0,  "qsub%c\t%12-15R, %0-3R, %16-19R"},
3964
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3965
    0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"},
3966
3967
  /* ARM Instructions.  */
3968
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3969
    0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t@ (str%c %12-15r, %a)"},
3970
3971
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3972
    0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"},
3973
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3974
    0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"},
3975
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3976
    0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"},
3977
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3978
    0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"},
3979
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3980
    0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"},
3981
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3982
    0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"},
3983
3984
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3985
    0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"},
3986
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3987
    0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"},
3988
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3989
    0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"},
3990
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3991
    0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"},
3992
3993
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3994
    0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION},
3995
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3996
    0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"},
3997
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3998
    0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION},
3999
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4000
    0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"},
4001
4002
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4003
    0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"},
4004
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4005
    0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"},
4006
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4007
    0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"},
4008
4009
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4010
    0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"},
4011
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4012
    0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"},
4013
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4014
    0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"},
4015
4016
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4017
    0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"},
4018
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4019
    0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"},
4020
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4021
    0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"},
4022
4023
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4024
    0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"},
4025
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4026
    0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"},
4027
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4028
    0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"},
4029
4030
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4031
    0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"},
4032
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4033
    0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"},
4034
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4035
    0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"},
4036
4037
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4038
    0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"},
4039
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4040
    0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"},
4041
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4042
    0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"},
4043
4044
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4045
    0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"},
4046
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4047
    0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"},
4048
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4049
    0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"},
4050
4051
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4052
    0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"},
4053
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4054
    0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"},
4055
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4056
    0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"},
4057
4058
  {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT),
4059
    0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"},
4060
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
4061
    0x0120f000, 0x0db0f000, "msr%c\t%C, %o"},
4062
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
4063
    0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"},
4064
4065
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4066
    0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"},
4067
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4068
    0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"},
4069
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4070
    0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"},
4071
4072
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4073
    0x03300000, 0x0ff00000, "teq%p%c\t%16-19r, %o"},
4074
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4075
    0x01300000, 0x0ff00010, "teq%p%c\t%16-19r, %o"},
4076
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4077
    0x01300010, 0x0ff00010, "teq%p%c\t%16-19R, %o"},
4078
4079
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4080
    0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"},
4081
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4082
    0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"},
4083
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4084
    0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"},
4085
4086
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4087
    0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"},
4088
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4089
    0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"},
4090
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4091
    0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"},
4092
4093
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4094
    0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"},
4095
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4096
    0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"},
4097
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4098
    0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"},
4099
4100
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4101
    0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"},
4102
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4103
    0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"},
4104
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4105
    0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"},
4106
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4107
    0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"},
4108
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4109
    0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"},
4110
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4111
    0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"},
4112
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4113
    0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"},
4114
4115
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4116
    0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"},
4117
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4118
    0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"},
4119
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4120
    0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"},
4121
4122
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4123
    0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"},
4124
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4125
    0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"},
4126
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4127
    0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"},
4128
4129
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4130
    0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION},
4131
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4132
    0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t@ (ldr%c %12-15r, %a)"},
4133
4134
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4135
    0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"},
4136
4137
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4138
    0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"},
4139
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4140
    0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"},
4141
4142
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4143
    0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4144
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4145
    0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4146
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4147
    0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4148
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4149
    0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4150
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4151
    0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4152
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4153
    0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4154
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4155
    0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4156
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4157
    0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4158
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4159
    0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4160
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4161
    0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4162
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4163
    0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4164
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4165
    0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4166
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4167
    0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4168
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4169
    0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4170
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4171
    0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4172
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4173
    0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4174
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4175
    0x092d0000, 0x0fff0000, "push%c\t%m"},
4176
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4177
    0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"},
4178
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4179
    0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
4180
4181
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4182
    0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4183
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4184
    0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4185
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4186
    0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4187
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4188
    0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4189
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4190
    0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4191
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4192
    0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4193
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4194
    0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4195
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4196
    0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4197
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4198
    0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4199
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4200
    0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4201
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4202
    0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4203
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4204
    0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4205
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4206
    0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4207
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4208
    0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4209
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4210
    0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4211
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4212
    0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4213
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4214
    0x08bd0000, 0x0fff0000, "pop%c\t%m"},
4215
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4216
    0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"},
4217
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4218
    0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
4219
4220
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4221
    0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
4222
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4223
    0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
4224
4225
  /* The rest.  */
4226
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
4227
    0x03200000, 0x0fff00ff, "nop%c\t{%{I:%0-7d%}}" UNPREDICTABLE_INSTRUCTION},
4228
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4229
    0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
4230
  {ARM_FEATURE_CORE_LOW (0),
4231
    0x00000000, 0x00000000, 0}
4232
};
4233
4234
/* print_insn_thumb16 recognizes the following format control codes:
4235
4236
   %S                   print Thumb register (bits 3..5 as high number if bit 6 set)
4237
   %D                   print Thumb register (bits 0..2 as high number if bit 7 set)
4238
   %<bitfield>I         print bitfield as a signed decimal
4239
          (top bit of range being the sign bit)
4240
   %N                   print Thumb register mask (with LR)
4241
   %O                   print Thumb register mask (with PC)
4242
   %M                   print Thumb register mask
4243
   %b     print CZB's 6-bit unsigned branch destination
4244
   %s     print Thumb right-shift immediate (6..10; 0 == 32).
4245
   %c     print the condition code
4246
   %C     print the condition code, or "s" if not conditional
4247
   %x     print warning if conditional an not at end of IT block"
4248
   %X     print "\t@ unpredictable <IT:code>" if conditional
4249
   %I     print IT instruction suffix and operands
4250
   %W     print Thumb Writeback indicator for LDMIA
4251
   %<bitfield>r   print bitfield as an ARM register
4252
   %<bitfield>d   print bitfield as a decimal
4253
   %<bitfield>H         print (bitfield * 2) as a decimal
4254
   %<bitfield>W         print (bitfield * 4) as a decimal
4255
   %<bitfield>a         print (bitfield * 4) as a pc-rel offset + decoded symbol
4256
   %<bitfield>B         print Thumb branch destination (signed displacement)
4257
   %<bitfield>c         print bitfield as a condition code
4258
   %<bitnum>'c    print specified char iff bit is one
4259
   %<bitnum>?ab   print a if bit is one else print b.  */
4260
4261
static const struct opcode16 thumb_opcodes[] =
4262
{
4263
  /* Thumb instructions.  */
4264
4265
  /* ARMv8-M Security Extensions instructions.  */
4266
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4784, 0xff87, "blxns\t%3-6r"},
4267
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4704, 0xff87, "bxns\t%3-6r"},
4268
4269
  /* ARM V8 instructions.  */
4270
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),  0xbf50, 0xffff, "sevl%c"},
4271
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),  0xba80, 0xffc0, "hlt\t%0-5x"},
4272
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),  0xb610, 0xfff7, "setpan\t%{I:#%3-3d%}"},
4273
4274
  /* ARM V6K no-argument instructions.  */
4275
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xffff, "nop%c"},
4276
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf10, 0xffff, "yield%c"},
4277
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf20, 0xffff, "wfe%c"},
4278
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf30, 0xffff, "wfi%c"},
4279
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf40, 0xffff, "sev%c"},
4280
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xff0f, "nop%c\t{%4-7d}"},
4281
4282
  /* ARM V6T2 instructions.  */
4283
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4284
    0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"},
4285
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4286
    0xb100, 0xfd00, "cbz\t%0-2r, %b%X"},
4287
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xbf00, 0xff00, "it%I%X"},
4288
4289
  /* ARM V6.  */
4290
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb660, 0xfff8, "cpsie\t%{B:%2'a%1'i%0'f%}%X"},
4291
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb670, 0xfff8, "cpsid\t%{B:%2'a%1'i%0'f%}%X"},
4292
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"},
4293
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"},
4294
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"},
4295
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"},
4296
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb650, 0xfff7, "setend\t%{B:%3?ble%}%X"},
4297
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"},
4298
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"},
4299
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"},
4300
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"},
4301
4302
  /* ARM V5 ISA extends Thumb.  */
4303
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
4304
    0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional.  */
4305
  /* This is BLX(2).  BLX(1) is a 32-bit instruction.  */
4306
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
4307
    0x4780, 0xff87, "blx%c\t%3-6r%x"},  /* note: 4 bit register number.  */
4308
  /* ARM V4T ISA (Thumb v1).  */
4309
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4310
    0x46C0, 0xFFFF, "nop%c\t\t\t@ (mov r8, r8)"},
4311
  /* Format 4.  */
4312
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
4313
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
4314
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"},
4315
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"},
4316
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"},
4317
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"},
4318
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"},
4319
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"},
4320
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"},
4321
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"},
4322
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"},
4323
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"},
4324
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"},
4325
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"},
4326
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"},
4327
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"},
4328
  /* format 13 */
4329
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB000, 0xFF80, "add%c\t%{R:sp%}, %{I:#%0-6W%}"},
4330
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB080, 0xFF80, "sub%c\t%{R:sp%}, %{I:#%0-6W%}"},
4331
  /* format 5 */
4332
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4700, 0xFF80, "bx%c\t%S%x"},
4333
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4400, 0xFF00, "add%c\t%D, %S"},
4334
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4500, 0xFF00, "cmp%c\t%D, %S"},
4335
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4600, 0xFF00, "mov%c\t%D, %S"},
4336
  /* format 14 */
4337
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB400, 0xFE00, "push%c\t%N"},
4338
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xBC00, 0xFE00, "pop%c\t%O"},
4339
  /* format 2 */
4340
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4341
    0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"},
4342
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4343
    0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"},
4344
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4345
    0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, %{I:#%6-8d%}"},
4346
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4347
    0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, %{I:#%6-8d%}"},
4348
  /* format 8 */
4349
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4350
    0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"},
4351
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4352
    0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"},
4353
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4354
    0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"},
4355
  /* format 7 */
4356
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4357
    0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
4358
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4359
    0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
4360
  /* format 1 */
4361
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"},
4362
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4363
    0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, %{I:#%6-10d%}"},
4364
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"},
4365
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"},
4366
  /* format 3 */
4367
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2000, 0xF800, "mov%C\t%8-10r, %{I:#%0-7d%}"},
4368
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2800, 0xF800, "cmp%c\t%8-10r, %{I:#%0-7d%}"},
4369
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3000, 0xF800, "add%C\t%8-10r, %{I:#%0-7d%}"},
4370
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3800, 0xF800, "sub%C\t%8-10r, %{I:#%0-7d%}"},
4371
  /* format 6 */
4372
  /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
4373
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4374
    0x4800, 0xF800,
4375
    "ldr%c\t%8-10r, [%{R:pc%}, %{I:#%0-7W%}]\t@ (%0-7a)"},
4376
  /* format 9 */
4377
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4378
    0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, %{I:#%6-10W%}]"},
4379
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4380
    0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, %{I:#%6-10W%}]"},
4381
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4382
    0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, %{I:#%6-10d%}]"},
4383
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4384
    0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, %{I:#%6-10d%}]"},
4385
  /* format 10 */
4386
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4387
    0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, %{I:#%6-10H%}]"},
4388
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4389
    0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, %{I:#%6-10H%}]"},
4390
  /* format 11 */
4391
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4392
    0x9000, 0xF800, "str%c\t%8-10r, [%{R:sp%}, %{I:#%0-7W%}]"},
4393
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4394
    0x9800, 0xF800, "ldr%c\t%8-10r, [%{R:sp%}, %{I:#%0-7W%}]"},
4395
  /* format 12 */
4396
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4397
    0xA000, 0xF800, "add%c\t%8-10r, %{R:pc%}, %{I:#%0-7W%}\t@ (adr %8-10r, %0-7a)"},
4398
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4399
    0xA800, 0xF800, "add%c\t%8-10r, %{R:sp%}, %{I:#%0-7W%}"},
4400
  /* format 15 */
4401
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
4402
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"},
4403
  /* format 17 */
4404
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDF00, 0xFF00, "svc%c\t%0-7d"},
4405
  /* format 16 */
4406
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFF00, "udf%c\t%{I:#%0-7d%}"},
4407
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION},
4408
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
4409
  /* format 18 */
4410
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xE000, 0xF800, "b%c.n\t%0-10B%x"},
4411
4412
  /* The E800 .. FFFF range is unconditionally redirected to the
4413
     32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
4414
     are processed via that table.  Thus, we can never encounter a
4415
     bare "second half of BL/BLX(1)" instruction here.  */
4416
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),  0x0000, 0x0000, UNDEFINED_INSTRUCTION},
4417
  {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
4418
};
4419
4420
/* Thumb32 opcodes use the same table structure as the ARM opcodes.
4421
   We adopt the convention that hw1 is the high 16 bits of .value and
4422
   .mask, hw2 the low 16 bits.
4423
4424
   print_insn_thumb32 recognizes the following format control codes:
4425
4426
       %%   %
4427
4428
       %I   print a 12-bit immediate from hw1[10],hw2[14:12,7:0]
4429
       %M   print a modified 12-bit immediate (same location)
4430
       %J   print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0]
4431
       %K   print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4]
4432
       %H   print a 16-bit immediate from hw2[3:0],hw1[11:0]
4433
       %S   print a possibly-shifted Rm
4434
4435
       %L   print address for a ldrd/strd instruction
4436
       %a   print the address of a plain load/store
4437
       %w   print the width and signedness of a core load/store
4438
       %m   print register mask for ldm/stm
4439
       %n   print register mask for clrm
4440
4441
       %E   print the lsb and width fields of a bfc/bfi instruction
4442
       %F   print the lsb and width fields of a sbfx/ubfx instruction
4443
       %G   print a fallback offset for Branch Future instructions
4444
       %W   print an offset for BF instruction
4445
       %Y   print an offset for BFL instruction
4446
       %Z   print an offset for BFCSEL instruction
4447
       %Q   print an offset for Low Overhead Loop instructions
4448
       %P   print an offset for Low Overhead Loop end instructions
4449
       %b   print a conditional branch offset
4450
       %B   print an unconditional branch offset
4451
       %s   print the shift field of an SSAT instruction
4452
       %R   print the rotation field of an SXT instruction
4453
       %U   print barrier type.
4454
       %P   print address for pli instruction.
4455
       %c   print the condition code
4456
       %x   print warning if conditional an not at end of IT block"
4457
       %X   print "\t@ unpredictable <IT:code>" if conditional
4458
4459
       %<bitfield>d print bitfield in decimal
4460
       %<bitfield>D     print bitfield plus one in decimal
4461
       %<bitfield>W print bitfield*4 in decimal
4462
       %<bitfield>r print bitfield as an ARM register
4463
       %<bitfield>R as %<>r but r15 is UNPREDICTABLE
4464
       %<bitfield>S as %<>r but r13 and r15 is UNPREDICTABLE
4465
       %<bitfield>c print bitfield as a condition code
4466
4467
       %<bitfield>'c  print specified char iff bitfield is all ones
4468
       %<bitfield>`c  print specified char iff bitfield is all zeroes
4469
       %<bitfield>?ab... select from array of values in big endian order
4470
4471
   With one exception at the bottom (done because BL and BLX(1) need
4472
   to come dead last), this table was machine-sorted first in
4473
   decreasing order of number of bits set in the mask, then in
4474
   increasing numeric order of mask, then in increasing numeric order
4475
   of opcode.  This order is not the clearest for a human reader, but
4476
   is guaranteed never to catch a special-case bit pattern with a more
4477
   general mask, which is important, because this instruction encoding
4478
   makes heavy use of special-case bit patterns.  */
4479
static const struct opcode32 thumb32_opcodes[] =
4480
{
4481
  /* Arm v8.1-M Mainline Pointer Authentication and Branch Target
4482
     Identification Extension.  */
4483
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4484
   0xf3af802d, 0xffffffff, "aut\t%{R:r12%}, %{R:lr%}, %{R:sp%}"},
4485
  {ARM_FEATURE_CORE_HIGH_HIGH (ARM_EXT3_PACBTI),
4486
   0xfb500f00, 0xfff00ff0, "autg%c\t%12-15r, %16-19r, %0-3r"},
4487
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4488
   0xf3af800f, 0xffffffff, "bti"},
4489
  {ARM_FEATURE_CORE_HIGH_HIGH (ARM_EXT3_PACBTI),
4490
   0xfb500f10, 0xfff00ff0, "bxaut%c\t%12-15r, %16-19r, %0-3r"},
4491
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4492
   0xf3af801d, 0xffffffff, "pac\t%{R:r12%}, %{R:lr%}, %{R:sp%}"},
4493
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4494
   0xf3af800d, 0xffffffff, "pacbti\t%{R:r12%}, %{R:lr%}, %{R:sp%}"},
4495
  {ARM_FEATURE_CORE_HIGH_HIGH (ARM_EXT3_PACBTI),
4496
   0xfb60f000, 0xfff0f0f0, "pacg%c\t%8-11r, %16-19r, %0-3r"},
4497
4498
  /* Armv8.1-M Mainline and Armv8.1-M Mainline Security Extensions
4499
     instructions.  */
4500
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4501
    0xf00fe001, 0xffffffff, "lctp%c"},
4502
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4503
    0xf02fc001, 0xfffff001, "le\t%P"},
4504
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4505
    0xf00fc001, 0xfffff001, "le\t%{R:lr%}, %P"},
4506
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4507
    0xf01fc001, 0xfffff001, "letp\t%{R:lr%}, %P"},
4508
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4509
    0xf040c001, 0xfff0f001, "wls\t%{R:lr%}, %16-19S, %Q"},
4510
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4511
    0xf000c001, 0xffc0f001, "wlstp.%20-21s\t%{R:lr%}, %16-19S, %Q"},
4512
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4513
    0xf040e001, 0xfff0ffff, "dls\t%{R:lr%}, %16-19S"},
4514
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4515
    0xf000e001, 0xffc0ffff, "dlstp.%20-21s\t%{R:lr%}, %16-19S"},
4516
4517
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4518
    0xf040e001, 0xf860f001, "bf%c\t%G, %W"},
4519
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4520
    0xf060e001, 0xf8f0f001, "bfx%c\t%G, %16-19S"},
4521
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4522
    0xf000c001, 0xf800f001, "bfl%c\t%G, %Y"},
4523
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4524
    0xf070e001, 0xf8f0f001, "bflx%c\t%G, %16-19S"},
4525
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4526
    0xf000e001, 0xf840f001, "bfcsel\t%G, %Z, %{B:%18-21c%}"},
4527
4528
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4529
    0xe89f0000, 0xffff2000, "clrm%c\t%n"},
4530
4531
  /* ARMv8-M and ARMv8-M Security Extensions instructions.  */
4532
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0xe97fe97f, 0xffffffff, "sg"},
4533
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4534
    0xe840f000, 0xfff0f0ff, "tt\t%8-11r, %16-19r"},
4535
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4536
    0xe840f040, 0xfff0f0ff, "ttt\t%8-11r, %16-19r"},
4537
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4538
    0xe840f080, 0xfff0f0ff, "tta\t%8-11r, %16-19r"},
4539
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4540
    0xe840f0c0, 0xfff0f0ff, "ttat\t%8-11r, %16-19r"},
4541
4542
  /* ARM V8.2 RAS extension instructions.  */
4543
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
4544
    0xf3af8010, 0xffffffff, "esb"},
4545
4546
  /* V8 instructions.  */
4547
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4548
    0xf3af8005, 0xffffffff, "sevl%c.w"},
4549
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4550
    0xf78f8000, 0xfffffffc, "dcps%0-1d"},
4551
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4552
    0xe8c00f8f, 0xfff00fff, "stlb%c\t%12-15r, [%16-19R]"},
4553
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4554
    0xe8c00f9f, 0xfff00fff, "stlh%c\t%12-15r, [%16-19R]"},
4555
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4556
    0xe8c00faf, 0xfff00fff, "stl%c\t%12-15r, [%16-19R]"},
4557
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4558
    0xe8c00fc0, 0xfff00ff0, "stlexb%c\t%0-3r, %12-15r, [%16-19R]"},
4559
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4560
    0xe8c00fd0, 0xfff00ff0, "stlexh%c\t%0-3r, %12-15r, [%16-19R]"},
4561
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4562
    0xe8c00fe0, 0xfff00ff0, "stlex%c\t%0-3r, %12-15r, [%16-19R]"},
4563
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4564
    0xe8c000f0, 0xfff000f0, "stlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"},
4565
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4566
    0xe8d00f8f, 0xfff00fff, "ldab%c\t%12-15r, [%16-19R]"},
4567
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4568
    0xe8d00f9f, 0xfff00fff, "ldah%c\t%12-15r, [%16-19R]"},
4569
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4570
    0xe8d00faf, 0xfff00fff, "lda%c\t%12-15r, [%16-19R]"},
4571
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4572
    0xe8d00fcf, 0xfff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
4573
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4574
    0xe8d00fdf, 0xfff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
4575
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4576
    0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
4577
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4578
    0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"},
4579
4580
  /* V8-R instructions.  */
4581
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8R),
4582
    0xf3bf8f4c, 0xffffffff, "dfb%c"},
4583
4584
  /* CRC32 instructions.  */
4585
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
4586
    0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11R, %16-19R, %0-3R"},
4587
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
4588
    0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11R, %16-19R, %0-3R"},
4589
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
4590
    0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11R, %16-19R, %0-3R"},
4591
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
4592
    0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11R, %16-19R, %0-3R"},
4593
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
4594
    0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11R, %16-19R, %0-3R"},
4595
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
4596
    0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11R, %16-19R, %0-3R"},
4597
4598
  /* Speculation Barriers.  */
4599
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8014, 0xffffffff, "csdb"},
4600
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f40, 0xffffffff, "ssbb"},
4601
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f44, 0xffffffff, "pssbb"},
4602
4603
  /* V7 instructions.  */
4604
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf910f000, 0xff70f000, "pli%c\t%a"},
4605
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3af80f0, 0xfffffff0, "dbg%c\t%{I:#%0-3d%}"},
4606
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"},
4607
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"},
4608
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"},
4609
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"},
4610
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"},
4611
  {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
4612
    0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"},
4613
  {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
4614
    0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"},
4615
4616
  /* Virtualization Extension instructions.  */
4617
  {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0xf7e08000, 0xfff0f000, "hvc%c\t%V"},
4618
  /* We skip ERET as that is SUBS pc, lr, #0.  */
4619
4620
  /* MP Extension instructions.  */
4621
  {ARM_FEATURE_CORE_LOW (ARM_EXT_MP),   0xf830f000, 0xff70f000, "pldw%c\t%a"},
4622
4623
  /* Security extension instructions.  */
4624
  {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),  0xf7f08000, 0xfff0f000, "smc%c\t%K"},
4625
4626
  /* ARMv8.5-A instructions.  */
4627
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf3bf8f70, 0xffffffff, "sb"},
4628
4629
  /* Instructions defined in the basic V6T2 set.  */
4630
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8000, 0xffffffff, "nop%c.w"},
4631
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8001, 0xffffffff, "yield%c.w"},
4632
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8002, 0xffffffff, "wfe%c.w"},
4633
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8003, 0xffffffff, "wfi%c.w"},
4634
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8004, 0xffffffff, "sev%c.w"},
4635
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4636
    0xf3af8000, 0xffffff00, "nop%c.w\t{%{I:%0-7d%}}"},
4637
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf7f0a000, 0xfff0f000, "udf%c.w\t%H"},
4638
4639
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4640
    0xf3bf8f2f, 0xffffffff, "clrex%c"},
4641
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4642
    0xf3af8400, 0xffffff1f, "cpsie.w\t%{B:%7'a%6'i%5'f%}%X"},
4643
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4644
    0xf3af8600, 0xffffff1f, "cpsid.w\t%{B:%7'a%6'i%5'f%}%X"},
4645
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4646
    0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"},
4647
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4648
    0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"},
4649
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4650
    0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"},
4651
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4652
    0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"},
4653
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4654
    0xf3af8100, 0xffffffe0, "cps\t%{I:#%0-4d%}%X"},
4655
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4656
    0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"},
4657
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4658
    0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, %{B:lsl%} %{I:#1%}]%x"},
4659
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4660
    0xf3af8500, 0xffffff00, "cpsie\t%{B:%7'a%6'i%5'f%}, %{I:#%0-4d%}%X"},
4661
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4662
    0xf3af8700, 0xffffff00, "cpsid\t%{B:%7'a%6'i%5'f%}, %{I:#%0-4d%}%X"},
4663
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4664
    0xf3de8f00, 0xffffff00, "subs%c\t%{R:pc%}, %{R:lr%}, %{I:#%0-7d%}"},
4665
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4666
    0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"},
4667
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4668
    0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"},
4669
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4670
    0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"},
4671
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4672
    0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, %{I:#%0-4d%}"},
4673
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4674
    0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, %{I:#%0-4d%}"},
4675
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4676
    0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"},
4677
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4678
    0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"},
4679
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4680
    0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"},
4681
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4682
    0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"},
4683
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4684
    0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"},
4685
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4686
    0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"},
4687
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4688
    0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"},
4689
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4690
    0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"},
4691
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4692
    0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"},
4693
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4694
    0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"},
4695
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4696
    0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"},
4697
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4698
    0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"},
4699
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4700
    0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"},
4701
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4702
    0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"},
4703
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4704
    0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"},
4705
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4706
    0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"},
4707
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4708
    0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"},
4709
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4710
    0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"},
4711
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4712
    0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"},
4713
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4714
    0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"},
4715
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4716
    0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"},
4717
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4718
    0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"},
4719
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4720
    0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"},
4721
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4722
    0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"},
4723
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4724
    0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"},
4725
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4726
    0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"},
4727
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4728
    0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"},
4729
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4730
    0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"},
4731
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4732
    0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"},
4733
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4734
    0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"},
4735
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4736
    0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"},
4737
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4738
    0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"},
4739
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4740
    0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"},
4741
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4742
    0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"},
4743
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4744
    0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"},
4745
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4746
    0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"},
4747
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4748
    0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"},
4749
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4750
    0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"},
4751
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4752
    0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"},
4753
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4754
    0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"},
4755
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4756
    0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"},
4757
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4758
    0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"},
4759
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4760
    0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"},
4761
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4762
    0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"},
4763
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4764
    0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"},
4765
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4766
    0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"},
4767
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4768
    0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"},
4769
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4770
    0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"},
4771
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4772
    0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"},
4773
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4774
    0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"},
4775
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4776
    0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"},
4777
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4778
    0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"},
4779
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4780
    0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"},
4781
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4782
    0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"},
4783
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4784
    0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"},
4785
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4786
    0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"},
4787
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4788
    0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4789
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4790
    0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4791
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4792
    0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4793
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4794
    0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"},
4795
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4796
    0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"},
4797
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4798
    0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, %{I:#%0-4D%}, %16-19r"},
4799
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4800
    0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, %{I:#%0-4d%}, %16-19r"},
4801
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4802
    0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"},
4803
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4804
    0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"},
4805
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4806
    0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"},
4807
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4808
    0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"},
4809
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4810
    0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"},
4811
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4812
    0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"},
4813
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4814
    0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
4815
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4816
    0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
4817
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4818
    0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"},
4819
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4820
    0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"},
4821
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4822
    0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"},
4823
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4824
    0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"},
4825
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4826
    0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"},
4827
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4828
    0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"},
4829
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4830
    0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"},
4831
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4832
    0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"},
4833
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4834
    0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"},
4835
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4836
    0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"},
4837
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4838
    0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"},
4839
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4840
    0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"},
4841
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4842
    0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"},
4843
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4844
    0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"},
4845
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4846
    0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"},
4847
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4848
    0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
4849
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4850
    0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
4851
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4852
    0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4853
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4854
    0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4855
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4856
    0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4857
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4858
    0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4859
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4860
    0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4861
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4862
    0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4863
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4864
    0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, %{I:#%0-7W%}]"},
4865
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4866
    0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"},
4867
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4868
    0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"},
4869
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4870
    0xf810f000, 0xff70f000, "pld%c\t%a"},
4871
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4872
    0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4873
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4874
    0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4875
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4876
    0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4877
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4878
    0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4879
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4880
    0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4881
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4882
    0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4883
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4884
    0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4885
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4886
    0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"},
4887
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4888
    0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"},
4889
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4890
    0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"},
4891
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4892
    0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"},
4893
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4894
    0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"},
4895
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4896
    0xfb100000, 0xfff000c0,
4897
    "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
4898
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4899
    0xfbc00080, 0xfff000c0,
4900
    "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
4901
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4902
    0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"},
4903
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4904
    0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"},
4905
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4906
    0xf3000000, 0xffd08020, "ssat%c\t%8-11r, %{I:#%0-4D%}, %16-19r%s"},
4907
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4908
    0xf3800000, 0xffd08020, "usat%c\t%8-11r, %{I:#%0-4d%}, %16-19r%s"},
4909
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4910
    0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"},
4911
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4912
    0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"},
4913
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4914
    0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"},
4915
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4916
    0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"},
4917
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4918
    0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"},
4919
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4920
    0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"},
4921
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4922
    0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"},
4923
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4924
    0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"},
4925
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4926
    0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"},
4927
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4928
    0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"},
4929
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4930
    0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"},
4931
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4932
    0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"},
4933
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4934
    0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"},
4935
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4936
    0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"},
4937
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4938
    0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, %{I:#%0-7W%}]"},
4939
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4940
    0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"},
4941
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4942
    0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"},
4943
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4944
    0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"},
4945
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4946
    0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"},
4947
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4948
    0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"},
4949
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4950
    0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"},
4951
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4952
    0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"},
4953
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4954
    0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"},
4955
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4956
    0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"},
4957
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4958
    0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"},
4959
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4960
    0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"},
4961
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4962
    0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"},
4963
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4964
    0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"},
4965
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4966
    0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"},
4967
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4968
    0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"},
4969
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4970
    0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"},
4971
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4972
    0xe9400000, 0xff500000,
4973
    "strd%c\t%12-15r, %8-11r, [%16-19r, %{I:#%23`-%0-7W%}]%21'!%L"},
4974
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4975
    0xe9500000, 0xff500000,
4976
    "ldrd%c\t%12-15r, %8-11r, [%16-19r, %{I:#%23`-%0-7W%}]%21'!%L"},
4977
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4978
    0xe8600000, 0xff700000,
4979
    "strd%c\t%12-15r, %8-11r, [%16-19r], %{I:#%23`-%0-7W%}%L"},
4980
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4981
    0xe8700000, 0xff700000,
4982
    "ldrd%c\t%12-15r, %8-11r, [%16-19r], %{I:#%23`-%0-7W%}%L"},
4983
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4984
    0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"},
4985
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4986
    0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"},
4987
4988
  /* Filter out Bcc with cond=E or F, which are used for other instructions.  */
4989
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4990
    0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"},
4991
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4992
    0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"},
4993
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4994
    0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"},
4995
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4996
    0xf0009000, 0xf800d000, "b%c.w\t%B%x"},
4997
4998
  /* These have been 32-bit since the invention of Thumb.  */
4999
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
5000
     0xf000c000, 0xf800d001, "blx%c\t%B%x"},
5001
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
5002
     0xf000d000, 0xf800d000, "bl%c\t%B%x"},
5003
5004
  /* Fallback.  */
5005
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
5006
      0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
5007
  {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
5008
};
5009
5010
static const char *const arm_conditional[] =
5011
{"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
5012
 "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""};
5013
5014
static const char *const arm_fp_const[] =
5015
{"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
5016
5017
static const char *const arm_shift[] =
5018
{"lsl", "lsr", "asr", "ror"};
5019
5020
typedef struct
5021
{
5022
  const char *name;
5023
  const char *description;
5024
  const char *reg_names[16];
5025
}
5026
arm_regname;
5027
5028
static const arm_regname regnames[] =
5029
{
5030
  { "reg-names-raw", N_("Select raw register names"),
5031
    { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
5032
  { "reg-names-gcc", N_("Select register names used by GCC"),
5033
    { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl",  "fp",  "ip",  "sp",  "lr",  "pc" }},
5034
  { "reg-names-std", N_("Select register names used in ARM's ISA documentation"),
5035
    { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp",  "lr",  "pc" }},
5036
  { "force-thumb", N_("Assume all insns are Thumb insns"), {NULL} },
5037
  { "no-force-thumb", N_("Examine preceding label to determine an insn's type"), {NULL} },
5038
  { "reg-names-apcs", N_("Select register names used in the APCS"),
5039
    { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl",  "fp",  "ip",  "sp",  "lr",  "pc" }},
5040
  { "reg-names-atpcs", N_("Select register names used in the ATPCS"),
5041
    { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7",  "v8",  "IP",  "SP",  "LR",  "PC" }},
5042
  { "reg-names-special-atpcs", N_("Select special register names used in the ATPCS"),
5043
    { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL",  "FP",  "IP",  "SP",  "LR",  "PC" }},
5044
  { "coproc<N>=(cde|generic)", N_("Enable CDE extensions for coprocessor N space"), { NULL } }
5045
};
5046
5047
static const char *const iwmmxt_wwnames[] =
5048
{"b", "h", "w", "d"};
5049
5050
static const char *const iwmmxt_wwssnames[] =
5051
{"b", "bus", "bc", "bss",
5052
 "h", "hus", "hc", "hss",
5053
 "w", "wus", "wc", "wss",
5054
 "d", "dus", "dc", "dss"
5055
};
5056
5057
static const char *const iwmmxt_regnames[] =
5058
{ "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7",
5059
  "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"
5060
};
5061
5062
static const char *const iwmmxt_cregnames[] =
5063
{ "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved",
5064
  "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"
5065
};
5066
5067
static const char *const vec_condnames[] =
5068
{ "eq", "ne", "cs", "hi", "ge", "lt", "gt", "le"
5069
};
5070
5071
static const char *const mve_predicatenames[] =
5072
{ "", "ttt", "tt", "tte", "t", "tee", "te", "tet", "",
5073
  "eee", "ee", "eet", "e", "ett", "et", "ete"
5074
};
5075
5076
/* Names for 2-bit size field for mve vector isntructions.  */
5077
static const char *const mve_vec_sizename[] =
5078
  { "8", "16", "32", "64"};
5079
5080
/* Indicates whether we are processing a then predicate,
5081
   else predicate or none at all.  */
5082
enum vpt_pred_state
5083
{
5084
  PRED_NONE,
5085
  PRED_THEN,
5086
  PRED_ELSE
5087
};
5088
5089
/* Information used to process a vpt block and subsequent instructions.  */
5090
struct vpt_block
5091
{
5092
  /* Are we in a vpt block.  */
5093
  bool in_vpt_block;
5094
5095
  /* Next predicate state if in vpt block.  */
5096
  enum vpt_pred_state next_pred_state;
5097
5098
  /* Mask from vpt/vpst instruction.  */
5099
  long predicate_mask;
5100
5101
  /* Instruction number in vpt block.  */
5102
  long current_insn_num;
5103
5104
  /* Number of instructions in vpt block..   */
5105
  long num_pred_insn;
5106
};
5107
5108
static struct vpt_block vpt_block_state =
5109
{
5110
  false,
5111
  PRED_NONE,
5112
  0,
5113
  0,
5114
  0
5115
};
5116
5117
/* Default to GCC register name set.  */
5118
static unsigned int regname_selected = 1;
5119
5120
2.57k
#define NUM_ARM_OPTIONS   ARRAY_SIZE (regnames)
5121
10.1M
#define arm_regnames      regnames[regname_selected].reg_names
5122
5123
static bool force_thumb = false;
5124
static uint16_t cde_coprocs = 0;
5125
5126
/* Current IT instruction state.  This contains the same state as the IT
5127
   bits in the CPSR.  */
5128
static unsigned int ifthen_state;
5129
/* IT state for the next instruction.  */
5130
static unsigned int ifthen_next_state;
5131
/* The address of the insn for which the IT state is valid.  */
5132
static bfd_vma ifthen_address;
5133
4.23M
#define IFTHEN_COND ((ifthen_state >> 4) & 0xf)
5134
/* Indicates that the current Conditional state is unconditional or outside
5135
   an IT block.  */
5136
327M
#define COND_UNCOND 16
5137
5138

5139
/* Functions.  */
5140
/* Extract the predicate mask for a VPT or VPST instruction.
5141
   The mask is composed of bits 13-15 (Mkl) and bit 22 (Mkh).  */
5142
5143
static long
5144
mve_extract_pred_mask (long given)
5145
17.7k
{
5146
17.7k
  return ((given & 0x00400000) >> 19) | ((given & 0xe000) >> 13);
5147
17.7k
}
5148
5149
/* Return the number of instructions in a MVE predicate block.  */
5150
static long
5151
num_instructions_vpt_block (long given)
5152
3.60k
{
5153
3.60k
  long mask = mve_extract_pred_mask (given);
5154
3.60k
  if (mask == 0)
5155
0
    return 0;
5156
5157
3.60k
  if (mask == 8)
5158
592
    return 1;
5159
5160
3.00k
  if ((mask & 7) == 4)
5161
1.22k
    return 2;
5162
5163
1.78k
  if ((mask & 3) == 2)
5164
469
    return 3;
5165
5166
1.31k
  if ((mask & 1) == 1)
5167
1.31k
    return 4;
5168
5169
0
  return 0;
5170
1.31k
}
5171
5172
static void
5173
mark_outside_vpt_block (void)
5174
3.60k
{
5175
3.60k
  vpt_block_state.in_vpt_block = false;
5176
3.60k
  vpt_block_state.next_pred_state = PRED_NONE;
5177
3.60k
  vpt_block_state.predicate_mask = 0;
5178
3.60k
  vpt_block_state.current_insn_num = 0;
5179
3.60k
  vpt_block_state.num_pred_insn = 0;
5180
3.60k
}
5181
5182
static void
5183
mark_inside_vpt_block (long given)
5184
3.60k
{
5185
3.60k
  vpt_block_state.in_vpt_block = true;
5186
3.60k
  vpt_block_state.next_pred_state = PRED_THEN;
5187
3.60k
  vpt_block_state.predicate_mask = mve_extract_pred_mask (given);
5188
3.60k
  vpt_block_state.current_insn_num = 0;
5189
3.60k
  vpt_block_state.num_pred_insn = num_instructions_vpt_block (given);
5190
3.60k
  assert (vpt_block_state.num_pred_insn >= 1);
5191
3.60k
}
5192
5193
static enum vpt_pred_state
5194
invert_next_predicate_state (enum vpt_pred_state astate)
5195
3.11k
{
5196
3.11k
  if (astate == PRED_THEN)
5197
2.03k
    return PRED_ELSE;
5198
1.08k
  else if (astate == PRED_ELSE)
5199
1.08k
    return PRED_THEN;
5200
0
  else
5201
0
    return PRED_NONE;
5202
3.11k
}
5203
5204
static enum vpt_pred_state
5205
update_next_predicate_state (void)
5206
6.10k
{
5207
6.10k
  long pred_mask = vpt_block_state.predicate_mask;
5208
6.10k
  long mask_for_insn = 0;
5209
5210
6.10k
  switch (vpt_block_state.current_insn_num)
5211
6.10k
    {
5212
3.00k
    case 1:
5213
3.00k
      mask_for_insn = 8;
5214
3.00k
      break;
5215
5216
1.78k
    case 2:
5217
1.78k
      mask_for_insn = 4;
5218
1.78k
      break;
5219
5220
1.31k
    case 3:
5221
1.31k
      mask_for_insn = 2;
5222
1.31k
      break;
5223
5224
0
    case 4:
5225
0
      return PRED_NONE;
5226
6.10k
    }
5227
5228
6.10k
  if (pred_mask & mask_for_insn)
5229
3.11k
    return invert_next_predicate_state (vpt_block_state.next_pred_state);
5230
2.99k
  else
5231
2.99k
    return vpt_block_state.next_pred_state;
5232
6.10k
}
5233
5234
static void
5235
update_vpt_block_state (void)
5236
9.70k
{
5237
9.70k
  vpt_block_state.current_insn_num++;
5238
9.70k
  if (vpt_block_state.current_insn_num == vpt_block_state.num_pred_insn)
5239
3.60k
    {
5240
      /* No more instructions to process in vpt block.  */
5241
3.60k
      mark_outside_vpt_block ();
5242
3.60k
      return;
5243
3.60k
    }
5244
5245
6.10k
  vpt_block_state.next_pred_state = update_next_predicate_state ();
5246
6.10k
}
5247
5248
/* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?.
5249
   Returns pointer to following character of the format string and
5250
   fills in *VALUEP and *WIDTHP with the extracted value and number of
5251
   bits extracted.  WIDTHP can be NULL.  */
5252
5253
static const char *
5254
arm_decode_bitfield (const char *ptr,
5255
         unsigned long insn,
5256
         unsigned long *valuep,
5257
         int *widthp)
5258
9.29M
{
5259
9.29M
  unsigned long value = 0;
5260
9.29M
  int width = 0;
5261
5262
9.29M
  do
5263
9.62M
    {
5264
9.62M
      int start, end;
5265
9.62M
      int bits;
5266
5267
27.2M
      for (start = 0; *ptr >= '0' && *ptr <= '9'; ptr++)
5268
17.5M
  start = start * 10 + *ptr - '0';
5269
9.62M
      if (*ptr == '-')
5270
18.6M
  for (end = 0, ptr++; *ptr >= '0' && *ptr <= '9'; ptr++)
5271
12.2M
    end = end * 10 + *ptr - '0';
5272
3.25M
      else
5273
3.25M
  end = start;
5274
9.62M
      bits = end - start;
5275
9.62M
      if (bits < 0)
5276
0
  abort ();
5277
9.62M
      value |= ((insn >> start) & ((2ul << bits) - 1)) << width;
5278
9.62M
      width += bits + 1;
5279
9.62M
    }
5280
9.62M
  while (*ptr++ == ',');
5281
9.29M
  *valuep = value;
5282
9.29M
  if (widthp)
5283
9.29M
    *widthp = width;
5284
9.29M
  return ptr - 1;
5285
9.29M
}
5286
5287
static void
5288
arm_decode_shift (long given, fprintf_styled_ftype func, void *stream,
5289
      bool print_shift)
5290
1.49M
{
5291
1.49M
  func (stream, dis_style_register, "%s", arm_regnames[given & 0xf]);
5292
5293
1.49M
  if ((given & 0xff0) != 0)
5294
885k
    {
5295
885k
      if ((given & 0x10) == 0)
5296
687k
  {
5297
687k
    int amount = (given & 0xf80) >> 7;
5298
687k
    int shift = (given & 0x60) >> 5;
5299
5300
687k
    if (amount == 0)
5301
84.2k
      {
5302
84.2k
        if (shift == 3)
5303
32.7k
    {
5304
32.7k
      func (stream, dis_style_text, ", ");
5305
32.7k
      func (stream, dis_style_sub_mnemonic, "rrx");
5306
32.7k
      return;
5307
32.7k
    }
5308
5309
51.4k
        amount = 32;
5310
51.4k
      }
5311
5312
655k
    if (print_shift)
5313
653k
      {
5314
653k
        func (stream, dis_style_text, ", ");
5315
653k
        func (stream, dis_style_sub_mnemonic, "%s ", arm_shift[shift]);
5316
653k
        func (stream, dis_style_immediate, "#%d", amount);
5317
653k
      }
5318
1.50k
    else
5319
1.50k
      {
5320
1.50k
        func (stream, dis_style_text, ", ");
5321
1.50k
        func (stream, dis_style_immediate, "#%d", amount);
5322
1.50k
      }
5323
655k
  }
5324
197k
      else if ((given & 0x80) == 0x80)
5325
1.16k
  func (stream, dis_style_comment_start,
5326
1.16k
        "\t@ <illegal shifter operand>");
5327
196k
      else if (print_shift)
5328
195k
  {
5329
195k
    func (stream, dis_style_text, ", ");
5330
195k
    func (stream, dis_style_sub_mnemonic, "%s ",
5331
195k
    arm_shift[(given & 0x60) >> 5]);
5332
195k
    func (stream, dis_style_register, "%s",
5333
195k
    arm_regnames[(given & 0xf00) >> 8]);
5334
195k
  }
5335
513
      else
5336
513
  {
5337
513
    func (stream, dis_style_text, ", ");
5338
513
    func (stream, dis_style_register, "%s",
5339
513
    arm_regnames[(given & 0xf00) >> 8]);
5340
513
  }
5341
885k
    }
5342
1.49M
}
5343
5344
/* Return TRUE if the MATCHED_INSN can be inside an IT block.  */
5345
5346
static bool
5347
is_mve_okay_in_it (enum mve_instructions matched_insn)
5348
7.67k
{
5349
7.67k
  switch (matched_insn)
5350
7.67k
    {
5351
578
    case MVE_VMOV_GP_TO_VEC_LANE:
5352
858
    case MVE_VMOV2_VEC_LANE_TO_GP:
5353
1.08k
    case MVE_VMOV2_GP_TO_VEC_LANE:
5354
1.47k
    case MVE_VMOV_VEC_LANE_TO_GP:
5355
1.79k
    case MVE_LSLL:
5356
2.04k
    case MVE_LSLLI:
5357
2.40k
    case MVE_LSRL:
5358
2.73k
    case MVE_ASRL:
5359
3.01k
    case MVE_ASRLI:
5360
3.33k
    case MVE_SQRSHRL:
5361
3.57k
    case MVE_SQRSHR:
5362
3.76k
    case MVE_UQRSHL:
5363
3.98k
    case MVE_UQRSHLL:
5364
4.20k
    case MVE_UQSHL:
5365
4.40k
    case MVE_UQSHLL:
5366
4.76k
    case MVE_URSHRL:
5367
4.97k
    case MVE_URSHR:
5368
5.43k
    case MVE_SRSHRL:
5369
5.64k
    case MVE_SRSHR:
5370
5.83k
    case MVE_SQSHLL:
5371
6.04k
    case MVE_SQSHL:
5372
6.04k
      return true;
5373
1.63k
    default:
5374
1.63k
      return false;
5375
7.67k
    }
5376
7.67k
}
5377
5378
static bool
5379
is_mve_architecture (struct disassemble_info *info)
5380
416k
{
5381
416k
  struct arm_private_data *private_data = info->private_data;
5382
416k
  arm_feature_set allowed_arches = private_data->features;
5383
5384
416k
  arm_feature_set arm_ext_v8_1m_main
5385
416k
    = ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN);
5386
5387
416k
  if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
5388
416k
      && !ARM_CPU_IS_ANY (allowed_arches))
5389
324k
    return true;
5390
91.8k
  else
5391
91.8k
    return false;
5392
416k
}
5393
5394
static bool
5395
is_vpt_instruction (long given)
5396
100k
{
5397
5398
  /* If mkh:mkl is '0000' then its not a vpt/vpst instruction.  */
5399
100k
  if ((given & 0x0040e000) == 0)
5400
8.77k
    return false;
5401
5402
  /* VPT floating point T1 variant.  */
5403
91.8k
  if (((given & 0xefb10f50) == 0xee310f00 && ((given & 0x1001) != 0x1))
5404
  /* VPT floating point T2 variant.  */
5405
91.8k
      || ((given & 0xefb10f50) == 0xee310f40)
5406
  /* VPT vector T1 variant.  */
5407
91.8k
      || ((given & 0xff811f51) == 0xfe010f00)
5408
  /* VPT vector T2 variant.  */
5409
91.8k
      || ((given & 0xff811f51) == 0xfe010f01
5410
90.6k
    && ((given & 0x300000) != 0x300000))
5411
  /* VPT vector T3 variant.  */
5412
91.8k
      || ((given & 0xff811f50) == 0xfe011f00)
5413
  /* VPT vector T4 variant.  */
5414
91.8k
      || ((given & 0xff811f70) == 0xfe010f40)
5415
  /* VPT vector T5 variant.  */
5416
91.8k
      || ((given & 0xff811f70) == 0xfe010f60)
5417
  /* VPT vector T6 variant.  */
5418
91.8k
      || ((given & 0xff811f50) == 0xfe011f40)
5419
  /* VPST vector T variant.  */
5420
91.8k
      || ((given & 0xffbf1fff) == 0xfe310f4d))
5421
3.60k
    return true;
5422
88.2k
  else
5423
88.2k
    return false;
5424
91.8k
}
5425
5426
/* Decode a bitfield from opcode GIVEN, with starting bitfield = START
5427
   and ending bitfield = END.  END must be greater than START.  */
5428
5429
static unsigned long
5430
arm_decode_field (unsigned long given, unsigned int start, unsigned int end)
5431
463k
{
5432
463k
  int bits = end - start;
5433
5434
463k
  if (bits < 0)
5435
0
    abort ();
5436
5437
463k
  return ((given >> start) & ((2ul << bits) - 1));
5438
463k
}
5439
5440
/* Decode a bitfield from opcode GIVEN, with multiple bitfields:
5441
   START:END and START2:END2.  END/END2 must be greater than
5442
   START/START2.  */
5443
5444
static unsigned long
5445
arm_decode_field_multiple (unsigned long given, unsigned int start,
5446
         unsigned int end, unsigned int start2,
5447
         unsigned int end2)
5448
46.7k
{
5449
46.7k
  int bits = end - start;
5450
46.7k
  int bits2 = end2 - start2;
5451
46.7k
  unsigned long value = 0;
5452
46.7k
  int width = 0;
5453
5454
46.7k
  if (bits2 < 0)
5455
0
    abort ();
5456
5457
46.7k
  value = arm_decode_field (given, start, end);
5458
46.7k
  width += bits + 1;
5459
5460
46.7k
  value |= ((given >> start2) & ((2ul << bits2) - 1)) << width;
5461
46.7k
  return value;
5462
46.7k
}
5463
5464
/* Return TRUE if the GIVEN encoding should not be decoded as MATCHED_INSN.
5465
   This helps us decode instructions that change mnemonic depending on specific
5466
   operand values/encodings.  */
5467
5468
static bool
5469
is_mve_encoding_conflict (unsigned long given,
5470
        enum mve_instructions matched_insn)
5471
151k
{
5472
151k
  switch (matched_insn)
5473
151k
    {
5474
969
    case MVE_VPST:
5475
969
      if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
5476
217
  return true;
5477
752
      else
5478
752
  return false;
5479
5480
1.67k
    case MVE_VPT_FP_T1:
5481
1.67k
      if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
5482
662
  return true;
5483
1.01k
      if ((arm_decode_field (given, 12, 12) == 0)
5484
1.01k
    && (arm_decode_field (given, 0, 0) == 1))
5485
226
  return true;
5486
788
      return false;
5487
5488
1.84k
    case MVE_VPT_FP_T2:
5489
1.84k
      if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
5490
710
  return true;
5491
1.13k
      if (arm_decode_field (given, 0, 3) == 0xd)
5492
489
  return true;
5493
642
      return false;
5494
5495
1.02k
    case MVE_VPT_VEC_T1:
5496
2.31k
    case MVE_VPT_VEC_T2:
5497
5.65k
    case MVE_VPT_VEC_T3:
5498
7.41k
    case MVE_VPT_VEC_T4:
5499
8.62k
    case MVE_VPT_VEC_T5:
5500
10.7k
    case MVE_VPT_VEC_T6:
5501
10.7k
      if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
5502
2.13k
  return true;
5503
8.60k
      if (arm_decode_field (given, 20, 21) == 3)
5504
236
  return true;
5505
8.37k
      return false;
5506
5507
662
    case MVE_VCMP_FP_T1:
5508
662
      if ((arm_decode_field (given, 12, 12) == 0)
5509
662
    && (arm_decode_field (given, 0, 0) == 1))
5510
247
  return true;
5511
415
      else
5512
415
  return false;
5513
5514
710
    case MVE_VCMP_FP_T2:
5515
710
      if (arm_decode_field (given, 0, 3) == 0xd)
5516
220
  return true;
5517
490
      else
5518
490
  return false;
5519
5520
763
    case MVE_VQADD_T2:
5521
2.11k
    case MVE_VQSUB_T2:
5522
2.79k
    case MVE_VMUL_VEC_T2:
5523
4.05k
    case MVE_VMULH:
5524
4.71k
    case MVE_VRMULH:
5525
4.97k
    case MVE_VMLA:
5526
5.23k
    case MVE_VMAX:
5527
5.45k
    case MVE_VMIN:
5528
8.13k
    case MVE_VBRSR:
5529
8.33k
    case MVE_VADD_VEC_T2:
5530
8.59k
    case MVE_VSUB_VEC_T2:
5531
8.83k
    case MVE_VABAV:
5532
9.06k
    case MVE_VQRSHL_T1:
5533
9.40k
    case MVE_VQSHL_T4:
5534
9.89k
    case MVE_VRSHL_T1:
5535
10.2k
    case MVE_VSHL_T3:
5536
10.8k
    case MVE_VCADD_VEC:
5537
11.3k
    case MVE_VHCADD:
5538
12.1k
    case MVE_VDDUP:
5539
12.5k
    case MVE_VIDUP:
5540
12.9k
    case MVE_VQRDMLADH:
5541
13.5k
    case MVE_VQDMLAH:
5542
13.7k
    case MVE_VQRDMLAH:
5543
13.9k
    case MVE_VQDMLASH:
5544
14.1k
    case MVE_VQRDMLASH:
5545
14.5k
    case MVE_VQDMLSDH:
5546
14.8k
    case MVE_VQRDMLSDH:
5547
15.7k
    case MVE_VQDMULH_T3:
5548
15.9k
    case MVE_VQRDMULH_T4:
5549
16.2k
    case MVE_VQDMLADH:
5550
16.7k
    case MVE_VMLAS:
5551
18.3k
    case MVE_VMULL_INT:
5552
18.6k
    case MVE_VHADD_T2:
5553
19.3k
    case MVE_VHSUB_T2:
5554
19.5k
    case MVE_VCMP_VEC_T1:
5555
19.8k
    case MVE_VCMP_VEC_T2:
5556
20.0k
    case MVE_VCMP_VEC_T3:
5557
20.5k
    case MVE_VCMP_VEC_T4:
5558
20.8k
    case MVE_VCMP_VEC_T5:
5559
21.0k
    case MVE_VCMP_VEC_T6:
5560
21.0k
      if (arm_decode_field (given, 20, 21) == 3)
5561
4.40k
  return true;
5562
16.6k
      else
5563
16.6k
  return false;
5564
5565
457
    case MVE_VLD2:
5566
1.22k
    case MVE_VLD4:
5567
2.01k
    case MVE_VST2:
5568
2.54k
    case MVE_VST4:
5569
2.54k
      if (arm_decode_field (given, 7, 8) == 3)
5570
197
  return true;
5571
2.34k
      else
5572
2.34k
  return false;
5573
5574
1.25k
    case MVE_VSTRB_T1:
5575
3.08k
    case MVE_VSTRH_T2:
5576
3.08k
      if ((arm_decode_field (given, 24, 24) == 0)
5577
3.08k
    && (arm_decode_field (given, 21, 21) == 0))
5578
433
  {
5579
433
      return true;
5580
433
  }
5581
2.65k
      else if ((arm_decode_field (given, 7, 8) == 3))
5582
934
  return true;
5583
1.71k
      else
5584
1.71k
  return false;
5585
5586
821
    case MVE_VLDRB_T1:
5587
2.55k
    case MVE_VLDRH_T2:
5588
3.06k
    case MVE_VLDRW_T7:
5589
3.71k
    case MVE_VSTRB_T5:
5590
4.46k
    case MVE_VSTRH_T6:
5591
4.93k
    case MVE_VSTRW_T7:
5592
4.93k
      if ((arm_decode_field (given, 24, 24) == 0)
5593
4.93k
    && (arm_decode_field (given, 21, 21) == 0))
5594
1.71k
  {
5595
1.71k
      return true;
5596
1.71k
  }
5597
3.21k
      else
5598
3.21k
  return false;
5599
5600
4.16k
    case MVE_VCVT_FP_FIX_VEC:
5601
4.16k
      return (arm_decode_field (given, 16, 21) & 0x38) == 0;
5602
5603
6.15k
    case MVE_VBIC_IMM:
5604
8.92k
    case MVE_VORR_IMM:
5605
8.92k
      {
5606
8.92k
  unsigned long cmode = arm_decode_field (given, 8, 11);
5607
5608
8.92k
  if ((cmode & 1) == 0)
5609
5.75k
    return true;
5610
3.16k
  else if ((cmode & 0xc) == 0xc)
5611
1.46k
    return true;
5612
1.70k
  else
5613
1.70k
    return false;
5614
8.92k
      }
5615
5616
3.16k
    case MVE_VMVN_IMM:
5617
3.16k
      {
5618
3.16k
  unsigned long cmode = arm_decode_field (given, 8, 11);
5619
5620
3.16k
  if (cmode == 0xe)
5621
0
    return true;
5622
3.16k
  else if ((cmode & 0x9) == 1)
5623
0
    return true;
5624
3.16k
  else if ((cmode & 0xd) == 9)
5625
0
    return true;
5626
3.16k
  else
5627
3.16k
    return false;
5628
3.16k
      }
5629
5630
7.07k
    case MVE_VMOV_IMM_TO_VEC:
5631
7.07k
      if ((arm_decode_field (given, 5, 5) == 1)
5632
7.07k
    && (arm_decode_field (given, 8, 11) != 0xe))
5633
3.72k
  return true;
5634
3.34k
      else
5635
3.34k
  return false;
5636
5637
398
    case MVE_VMOVL:
5638
398
      {
5639
398
  unsigned long size = arm_decode_field (given, 19, 20);
5640
398
  if ((size == 0) || (size == 3))
5641
0
    return true;
5642
398
  else
5643
398
    return false;
5644
398
      }
5645
5646
409
    case MVE_VMAXA:
5647
607
    case MVE_VMINA:
5648
808
    case MVE_VMAXV:
5649
1.15k
    case MVE_VMAXAV:
5650
1.35k
    case MVE_VMINV:
5651
1.56k
    case MVE_VMINAV:
5652
1.76k
    case MVE_VQRSHL_T2:
5653
1.95k
    case MVE_VQSHL_T1:
5654
2.29k
    case MVE_VRSHL_T2:
5655
2.51k
    case MVE_VSHL_T2:
5656
3.08k
    case MVE_VSHLL_T2:
5657
3.27k
    case MVE_VADDV:
5658
3.62k
    case MVE_VMOVN:
5659
3.92k
    case MVE_VQMOVUN:
5660
4.16k
    case MVE_VQMOVN:
5661
4.16k
      if (arm_decode_field (given, 18, 19) == 3)
5662
276
  return true;
5663
3.88k
      else
5664
3.88k
  return false;
5665
5666
1.14k
    case MVE_VMLSLDAV:
5667
1.56k
    case MVE_VRMLSLDAVH:
5668
3.18k
    case MVE_VMLALDAV:
5669
3.57k
    case MVE_VADDLV:
5670
3.57k
      if (arm_decode_field (given, 20, 22) == 7)
5671
995
  return true;
5672
2.57k
      else
5673
2.57k
  return false;
5674
5675
615
    case MVE_VRMLALDAVH:
5676
615
      if ((arm_decode_field (given, 20, 22) & 6) == 6)
5677
209
  return true;
5678
406
      else
5679
406
  return false;
5680
5681
1.57k
    case MVE_VDWDUP:
5682
2.47k
    case MVE_VIWDUP:
5683
2.47k
      if ((arm_decode_field (given, 20, 21) == 3)
5684
2.47k
    || (arm_decode_field (given, 1, 3) == 7))
5685
948
  return true;
5686
1.52k
      else
5687
1.52k
  return false;
5688
5689
5690
1.57k
    case MVE_VSHLL_T1:
5691
1.57k
      if (arm_decode_field (given, 16, 18) == 0)
5692
694
  {
5693
694
    unsigned long sz = arm_decode_field (given, 19, 20);
5694
5695
694
    if ((sz == 1) || (sz == 2))
5696
398
      return true;
5697
296
    else
5698
296
      return false;
5699
694
  }
5700
879
      else
5701
879
  return false;
5702
5703
543
    case MVE_VQSHL_T2:
5704
1.07k
    case MVE_VQSHLU_T3:
5705
1.64k
    case MVE_VRSHR:
5706
1.84k
    case MVE_VSHL_T1:
5707
2.42k
    case MVE_VSHR:
5708
2.67k
    case MVE_VSLI:
5709
3.07k
    case MVE_VSRI:
5710
3.07k
      if (arm_decode_field (given, 19, 21) == 0)
5711
735
  return true;
5712
2.33k
      else
5713
2.33k
  return false;
5714
5715
766
    case MVE_VCTP:
5716
766
    if (arm_decode_field (given, 16, 19) == 0xf)
5717
200
      return true;
5718
566
    else
5719
566
      return false;
5720
5721
297
    case MVE_ASRLI:
5722
948
    case MVE_ASRL:
5723
1.81k
    case MVE_LSLLI:
5724
2.44k
    case MVE_LSLL:
5725
3.10k
    case MVE_LSRL:
5726
3.90k
    case MVE_SQRSHRL:
5727
4.46k
    case MVE_SQSHLL:
5728
5.18k
    case MVE_SRSHRL:
5729
5.41k
    case MVE_UQRSHLL:
5730
5.83k
    case MVE_UQSHLL:
5731
6.25k
    case MVE_URSHRL:
5732
6.25k
      if (arm_decode_field (given, 9, 11) == 0x7)
5733
1.83k
  return true;
5734
4.42k
      else
5735
4.42k
  return false;
5736
5737
1.18k
    case MVE_CSINC:
5738
2.01k
    case MVE_CSINV:
5739
2.01k
      {
5740
2.01k
  unsigned long rm, rn;
5741
2.01k
  rm = arm_decode_field (given, 0, 3);
5742
2.01k
  rn = arm_decode_field (given, 16, 19);
5743
  /* CSET/CSETM.  */
5744
2.01k
  if (rm == 0xf && rn == 0xf)
5745
391
    return true;
5746
  /* CINC/CINV.  */
5747
1.62k
  else if (rn == rm && rn != 0xf)
5748
351
    return true;
5749
2.01k
      }
5750
    /* Fall through.  */
5751
1.47k
    case MVE_CSEL:
5752
2.45k
    case MVE_CSNEG:
5753
2.45k
      if (arm_decode_field (given, 0, 3) == 0xd)
5754
582
  return true;
5755
      /* CNEG.  */
5756
1.87k
      else if (matched_insn == MVE_CSNEG)
5757
940
  if (arm_decode_field (given, 0, 3) == arm_decode_field (given, 16, 19))
5758
536
    return true;
5759
1.33k
      return false;
5760
5761
52.8k
    default:
5762
53.0k
    case MVE_VADD_FP_T1:
5763
53.4k
    case MVE_VADD_FP_T2:
5764
53.6k
    case MVE_VADD_VEC_T1:
5765
53.6k
      return false;
5766
5767
151k
    }
5768
151k
}
5769
5770
static void
5771
print_mve_vld_str_addr (struct disassemble_info *info,
5772
      unsigned long given,
5773
      enum mve_instructions matched_insn)
5774
8.20k
{
5775
8.20k
  void *stream = info->stream;
5776
8.20k
  fprintf_styled_ftype func = info->fprintf_styled_func;
5777
5778
8.20k
  unsigned long p, w, gpr, imm, add, mod_imm;
5779
5780
8.20k
  imm = arm_decode_field (given, 0, 6);
5781
8.20k
  mod_imm = imm;
5782
5783
8.20k
  switch (matched_insn)
5784
8.20k
    {
5785
510
    case MVE_VLDRB_T1:
5786
1.14k
    case MVE_VSTRB_T1:
5787
1.14k
      gpr = arm_decode_field (given, 16, 18);
5788
1.14k
      break;
5789
5790
873
    case MVE_VLDRH_T2:
5791
1.95k
    case MVE_VSTRH_T2:
5792
1.95k
      gpr = arm_decode_field (given, 16, 18);
5793
1.95k
      mod_imm = imm << 1;
5794
1.95k
      break;
5795
5796
2.86k
    case MVE_VLDRH_T6:
5797
3.37k
    case MVE_VSTRH_T6:
5798
3.37k
      gpr = arm_decode_field (given, 16, 19);
5799
3.37k
      mod_imm = imm << 1;
5800
3.37k
      break;
5801
5802
487
    case MVE_VLDRW_T7:
5803
887
    case MVE_VSTRW_T7:
5804
887
      gpr = arm_decode_field (given, 16, 19);
5805
887
      mod_imm = imm << 2;
5806
887
      break;
5807
5808
411
    case MVE_VLDRB_T5:
5809
847
    case MVE_VSTRB_T5:
5810
847
      gpr = arm_decode_field (given, 16, 19);
5811
847
      break;
5812
5813
0
    default:
5814
0
      return;
5815
8.20k
    }
5816
5817
8.20k
  p = arm_decode_field (given, 24, 24);
5818
8.20k
  w = arm_decode_field (given, 21, 21);
5819
5820
8.20k
  add = arm_decode_field (given, 23, 23);
5821
5822
8.20k
  char * add_sub;
5823
5824
  /* Don't print anything for '+' as it is implied.  */
5825
8.20k
  if (add == 1)
5826
5.43k
    add_sub = "";
5827
2.77k
  else
5828
2.77k
    add_sub = "-";
5829
5830
8.20k
  func (stream, dis_style_text, "[");
5831
8.20k
  func (stream, dis_style_register, "%s", arm_regnames[gpr]);
5832
8.20k
  if (p == 1)
5833
5.63k
    {
5834
5.63k
      func (stream, dis_style_text, ", ");
5835
5.63k
      func (stream, dis_style_immediate, "#%s%lu", add_sub, mod_imm);
5836
      /* Offset mode.  */
5837
5.63k
      if (w == 0)
5838
3.78k
  func (stream, dis_style_text, "]");
5839
      /* Pre-indexed mode.  */
5840
1.84k
      else
5841
1.84k
  func (stream, dis_style_text, "]!");
5842
5.63k
    }
5843
2.57k
  else if ((p == 0) && (w == 1))
5844
2.18k
    {
5845
      /* Post-index mode.  */
5846
2.18k
      func (stream, dis_style_text, "], ");
5847
2.18k
      func (stream, dis_style_immediate, "#%s%lu", add_sub, mod_imm);
5848
2.18k
    }
5849
8.20k
}
5850
5851
/* Return FALSE if GIVEN is not an undefined encoding for MATCHED_INSN.
5852
   Otherwise, return TRUE and set UNDEFINED_CODE to give a reason as to why
5853
   this encoding is undefined.  */
5854
5855
static bool
5856
is_mve_undefined (unsigned long given, enum mve_instructions matched_insn,
5857
      enum mve_undefined *undefined_code)
5858
118k
{
5859
118k
  *undefined_code = UNDEF_NONE;
5860
5861
118k
  switch (matched_insn)
5862
118k
    {
5863
1.02k
    case MVE_VDUP:
5864
1.02k
      if (arm_decode_field_multiple (given, 5, 5, 22, 22) == 3)
5865
204
  {
5866
204
    *undefined_code = UNDEF_SIZE_3;
5867
204
    return true;
5868
204
  }
5869
823
      else
5870
823
  return false;
5871
5872
617
    case MVE_VQADD_T1:
5873
873
    case MVE_VQSUB_T1:
5874
1.06k
    case MVE_VMUL_VEC_T1:
5875
1.31k
    case MVE_VABD_VEC:
5876
1.51k
    case MVE_VADD_VEC_T1:
5877
1.73k
    case MVE_VSUB_VEC_T1:
5878
1.93k
    case MVE_VQDMULH_T1:
5879
2.12k
    case MVE_VQRDMULH_T2:
5880
2.34k
    case MVE_VRHADD:
5881
2.98k
    case MVE_VHADD_T1:
5882
3.19k
    case MVE_VHSUB_T1:
5883
3.19k
      if (arm_decode_field (given, 20, 21) == 3)
5884
450
  {
5885
450
    *undefined_code = UNDEF_SIZE_3;
5886
450
    return true;
5887
450
  }
5888
2.74k
      else
5889
2.74k
  return false;
5890
5891
510
    case MVE_VLDRB_T1:
5892
510
      if (arm_decode_field (given, 7, 8) == 3)
5893
220
  {
5894
220
    *undefined_code = UNDEF_SIZE_3;
5895
220
    return true;
5896
220
  }
5897
290
      else
5898
290
  return false;
5899
5900
873
    case MVE_VLDRH_T2:
5901
873
      if (arm_decode_field (given, 7, 8) <= 1)
5902
580
  {
5903
580
    *undefined_code = UNDEF_SIZE_LE_1;
5904
580
    return true;
5905
580
  }
5906
293
      else
5907
293
  return false;
5908
5909
639
    case MVE_VSTRB_T1:
5910
639
      if ((arm_decode_field (given, 7, 8) == 0))
5911
204
  {
5912
204
    *undefined_code = UNDEF_SIZE_0;
5913
204
    return true;
5914
204
  }
5915
435
      else
5916
435
  return false;
5917
5918
1.07k
    case MVE_VSTRH_T2:
5919
1.07k
      if ((arm_decode_field (given, 7, 8) <= 1))
5920
243
  {
5921
243
    *undefined_code = UNDEF_SIZE_LE_1;
5922
243
    return true;
5923
243
  }
5924
834
      else
5925
834
  return false;
5926
5927
958
    case MVE_VLDRB_GATHER_T1:
5928
958
      if (arm_decode_field (given, 7, 8) == 3)
5929
205
  {
5930
205
    *undefined_code = UNDEF_SIZE_3;
5931
205
    return true;
5932
205
  }
5933
753
      else if ((arm_decode_field (given, 28, 28) == 0)
5934
753
         && (arm_decode_field (given, 7, 8) == 0))
5935
204
  {
5936
204
    *undefined_code = UNDEF_NOT_UNS_SIZE_0;
5937
204
    return true;
5938
204
  }
5939
549
      else
5940
549
  return false;
5941
5942
1.15k
    case MVE_VLDRH_GATHER_T2:
5943
1.15k
      if (arm_decode_field (given, 7, 8) == 3)
5944
276
  {
5945
276
    *undefined_code = UNDEF_SIZE_3;
5946
276
    return true;
5947
276
  }
5948
882
      else if ((arm_decode_field (given, 28, 28) == 0)
5949
882
         && (arm_decode_field (given, 7, 8) == 1))
5950
448
  {
5951
448
    *undefined_code = UNDEF_NOT_UNS_SIZE_1;
5952
448
    return true;
5953
448
  }
5954
434
      else if (arm_decode_field (given, 7, 8) == 0)
5955
209
  {
5956
209
    *undefined_code = UNDEF_SIZE_0;
5957
209
    return true;
5958
209
  }
5959
225
      else
5960
225
  return false;
5961
5962
405
    case MVE_VLDRW_GATHER_T3:
5963
405
      if (arm_decode_field (given, 7, 8) != 2)
5964
0
  {
5965
0
    *undefined_code = UNDEF_SIZE_NOT_2;
5966
0
    return true;
5967
0
  }
5968
405
      else if (arm_decode_field (given, 28, 28) == 0)
5969
0
  {
5970
0
    *undefined_code = UNDEF_NOT_UNSIGNED;
5971
0
    return true;
5972
0
  }
5973
405
      else
5974
405
  return false;
5975
5976
396
    case MVE_VLDRD_GATHER_T4:
5977
396
      if (arm_decode_field (given, 7, 8) != 3)
5978
0
  {
5979
0
    *undefined_code = UNDEF_SIZE_NOT_3;
5980
0
    return true;
5981
0
  }
5982
396
      else if (arm_decode_field (given, 28, 28) == 0)
5983
196
  {
5984
196
    *undefined_code = UNDEF_NOT_UNSIGNED;
5985
196
    return true;
5986
196
  }
5987
200
      else
5988
200
  return false;
5989
5990
1.04k
    case MVE_VSTRB_SCATTER_T1:
5991
1.04k
      if (arm_decode_field (given, 7, 8) == 3)
5992
612
  {
5993
612
    *undefined_code = UNDEF_SIZE_3;
5994
612
    return true;
5995
612
  }
5996
436
      else
5997
436
  return false;
5998
5999
910
    case MVE_VSTRH_SCATTER_T2:
6000
910
      {
6001
910
  unsigned long size = arm_decode_field (given, 7, 8);
6002
910
  if (size == 3)
6003
365
    {
6004
365
      *undefined_code = UNDEF_SIZE_3;
6005
365
      return true;
6006
365
    }
6007
545
  else if (size == 0)
6008
206
    {
6009
206
      *undefined_code = UNDEF_SIZE_0;
6010
206
      return true;
6011
206
    }
6012
339
  else
6013
339
    return false;
6014
910
      }
6015
6016
913
    case MVE_VSTRW_SCATTER_T3:
6017
913
      if (arm_decode_field (given, 7, 8) != 2)
6018
627
  {
6019
627
    *undefined_code = UNDEF_SIZE_NOT_2;
6020
627
    return true;
6021
627
  }
6022
286
      else
6023
286
  return false;
6024
6025
79
    case MVE_VSTRD_SCATTER_T4:
6026
79
      if (arm_decode_field (given, 7, 8) != 3)
6027
0
  {
6028
0
    *undefined_code = UNDEF_SIZE_NOT_3;
6029
0
    return true;
6030
0
  }
6031
79
      else
6032
79
  return false;
6033
6034
2.56k
    case MVE_VCVT_FP_FIX_VEC:
6035
2.56k
      {
6036
2.56k
  unsigned long imm6 = arm_decode_field (given, 16, 21);
6037
2.56k
  if ((imm6 & 0x20) == 0)
6038
241
    {
6039
241
      *undefined_code = UNDEF_VCVT_IMM6;
6040
241
      return true;
6041
241
    }
6042
6043
2.32k
  if ((arm_decode_field (given, 9, 9) == 0)
6044
2.32k
      && ((imm6 & 0x30) == 0x20))
6045
999
    {
6046
999
      *undefined_code = UNDEF_VCVT_FSI_IMM6;
6047
999
      return true;
6048
999
    }
6049
6050
1.32k
  return false;
6051
2.32k
      }
6052
6053
280
    case MVE_VNEG_FP:
6054
482
    case MVE_VABS_FP:
6055
2.56k
    case MVE_VCVT_BETWEEN_FP_INT:
6056
4.40k
    case MVE_VCVT_FROM_FP_TO_INT:
6057
4.40k
      {
6058
4.40k
  unsigned long size = arm_decode_field (given, 18, 19);
6059
4.40k
  if (size == 0)
6060
218
    {
6061
218
      *undefined_code = UNDEF_SIZE_0;
6062
218
      return true;
6063
218
    }
6064
4.18k
  else if (size == 3)
6065
1.15k
    {
6066
1.15k
      *undefined_code = UNDEF_SIZE_3;
6067
1.15k
      return true;
6068
1.15k
    }
6069
3.02k
  else
6070
3.02k
    return false;
6071
4.40k
      }
6072
6073
4.18k
    case MVE_VMOV_VEC_LANE_TO_GP:
6074
4.18k
      {
6075
4.18k
  unsigned long op1 = arm_decode_field (given, 21, 22);
6076
4.18k
  unsigned long op2 = arm_decode_field (given, 5, 6);
6077
4.18k
  unsigned long u = arm_decode_field (given, 23, 23);
6078
6079
4.18k
  if ((op2 == 0) && (u == 1))
6080
1.03k
    {
6081
1.03k
      if ((op1 == 0) || (op1 == 1))
6082
657
        {
6083
657
    *undefined_code = UNDEF_BAD_U_OP1_OP2;
6084
657
    return true;
6085
657
        }
6086
379
      else
6087
379
        return false;
6088
1.03k
    }
6089
3.15k
  else if (op2 == 2)
6090
904
    {
6091
904
      if ((op1 == 0) || (op1 == 1))
6092
577
        {
6093
577
    *undefined_code = UNDEF_BAD_OP1_OP2;
6094
577
    return true;
6095
577
        }
6096
327
      else
6097
327
        return false;
6098
904
    }
6099
6100
2.24k
  return false;
6101
4.18k
      }
6102
6103
2.02k
    case MVE_VMOV_GP_TO_VEC_LANE:
6104
2.02k
      if (arm_decode_field (given, 5, 6) == 2)
6105
513
  {
6106
513
    unsigned long op1 = arm_decode_field (given, 21, 22);
6107
513
    if ((op1 == 0) || (op1 == 1))
6108
306
      {
6109
306
        *undefined_code = UNDEF_BAD_OP1_OP2;
6110
306
        return true;
6111
306
      }
6112
207
    else
6113
207
      return false;
6114
513
  }
6115
1.50k
      else
6116
1.50k
  return false;
6117
6118
593
    case MVE_VMOV_VEC_TO_VEC:
6119
593
      if ((arm_decode_field (given, 5, 5) == 1)
6120
593
    || (arm_decode_field (given, 22, 22) == 1))
6121
399
    return true;
6122
194
      return false;
6123
6124
3.34k
    case MVE_VMOV_IMM_TO_VEC:
6125
3.34k
      if (arm_decode_field (given, 5, 5) == 0)
6126
2.55k
      {
6127
2.55k
  unsigned long cmode = arm_decode_field (given, 8, 11);
6128
6129
2.55k
  if (((cmode & 9) == 1) || ((cmode & 5) == 1))
6130
0
    {
6131
0
      *undefined_code = UNDEF_OP_0_BAD_CMODE;
6132
0
      return true;
6133
0
    }
6134
2.55k
  else
6135
2.55k
    return false;
6136
2.55k
      }
6137
792
      else
6138
792
  return false;
6139
6140
542
    case MVE_VSHLL_T2:
6141
891
    case MVE_VMOVN:
6142
891
      if (arm_decode_field (given, 18, 19) == 2)
6143
332
  {
6144
332
    *undefined_code = UNDEF_SIZE_2;
6145
332
    return true;
6146
332
  }
6147
559
      else
6148
559
  return false;
6149
6150
406
    case MVE_VRMLALDAVH:
6151
873
    case MVE_VMLADAV_T1:
6152
1.09k
    case MVE_VMLADAV_T2:
6153
2.24k
    case MVE_VMLALDAV:
6154
2.24k
      if ((arm_decode_field (given, 28, 28) == 1)
6155
2.24k
    && (arm_decode_field (given, 12, 12) == 1))
6156
605
  {
6157
605
    *undefined_code = UNDEF_XCHG_UNS;
6158
605
    return true;
6159
605
  }
6160
1.64k
      else
6161
1.64k
  return false;
6162
6163
227
    case MVE_VQSHRN:
6164
825
    case MVE_VQSHRUN:
6165
2.00k
    case MVE_VSHLL_T1:
6166
2.60k
    case MVE_VSHRN:
6167
2.60k
      {
6168
2.60k
  unsigned long sz = arm_decode_field (given, 19, 20);
6169
2.60k
  if (sz == 1)
6170
1.09k
    return false;
6171
1.51k
  else if ((sz & 2) == 2)
6172
914
    return false;
6173
601
  else
6174
601
    {
6175
601
      *undefined_code = UNDEF_SIZE;
6176
601
      return true;
6177
601
    }
6178
2.60k
      }
6179
0
      break;
6180
6181
543
    case MVE_VQSHL_T2:
6182
924
    case MVE_VQSHLU_T3:
6183
1.13k
    case MVE_VRSHR:
6184
1.34k
    case MVE_VSHL_T1:
6185
1.89k
    case MVE_VSHR:
6186
2.13k
    case MVE_VSLI:
6187
2.33k
    case MVE_VSRI:
6188
2.33k
      {
6189
2.33k
  unsigned long sz = arm_decode_field (given, 19, 21);
6190
2.33k
  if ((sz & 7) == 1)
6191
242
    return false;
6192
2.09k
  else if ((sz & 6) == 2)
6193
464
    return false;
6194
1.63k
  else if ((sz & 4) == 4)
6195
1.63k
    return false;
6196
0
  else
6197
0
    {
6198
0
      *undefined_code = UNDEF_SIZE;
6199
0
      return true;
6200
0
    }
6201
2.33k
      }
6202
6203
247
    case MVE_VQRSHRN:
6204
552
    case MVE_VQRSHRUN:
6205
552
      if (arm_decode_field (given, 19, 20) == 0)
6206
307
  {
6207
307
    *undefined_code = UNDEF_SIZE_0;
6208
307
    return true;
6209
307
  }
6210
245
      else
6211
245
  return false;
6212
6213
430
    case MVE_VABS_VEC:
6214
430
  if (arm_decode_field (given, 18, 19) == 3)
6215
211
  {
6216
211
    *undefined_code = UNDEF_SIZE_3;
6217
211
    return true;
6218
211
  }
6219
219
  else
6220
219
    return false;
6221
6222
198
    case MVE_VQNEG:
6223
393
    case MVE_VQABS:
6224
603
    case MVE_VNEG_VEC:
6225
813
    case MVE_VCLS:
6226
1.02k
    case MVE_VCLZ:
6227
1.02k
      if (arm_decode_field (given, 18, 19) == 3)
6228
207
  {
6229
207
    *undefined_code = UNDEF_SIZE_3;
6230
207
    return true;
6231
207
  }
6232
816
      else
6233
816
  return false;
6234
6235
401
    case MVE_VREV16:
6236
401
      if (arm_decode_field (given, 18, 19) == 0)
6237
200
  return false;
6238
201
      else
6239
201
  {
6240
201
    *undefined_code = UNDEF_SIZE_NOT_0;
6241
201
    return true;
6242
201
  }
6243
6244
434
    case MVE_VREV32:
6245
434
      {
6246
434
  unsigned long size = arm_decode_field (given, 18, 19);
6247
434
  if ((size & 2) == 2)
6248
239
    {
6249
239
      *undefined_code = UNDEF_SIZE_2;
6250
239
      return true;
6251
239
    }
6252
195
  else
6253
195
    return false;
6254
434
      }
6255
6256
471
    case MVE_VREV64:
6257
471
      if (arm_decode_field (given, 18, 19) != 3)
6258
215
  return false;
6259
256
      else
6260
256
  {
6261
256
    *undefined_code = UNDEF_SIZE_3;
6262
256
    return true;
6263
256
  }
6264
6265
76.7k
    default:
6266
76.7k
      return false;
6267
118k
    }
6268
118k
}
6269
6270
/* Return FALSE if GIVEN is not an unpredictable encoding for MATCHED_INSN.
6271
   Otherwise, return TRUE and set UNPREDICTABLE_CODE to give a reason as to
6272
   why this encoding is unpredictable.  */
6273
6274
static bool
6275
is_mve_unpredictable (unsigned long given, enum mve_instructions matched_insn,
6276
          enum mve_unpredictable *unpredictable_code)
6277
116k
{
6278
116k
  *unpredictable_code = UNPRED_NONE;
6279
6280
116k
  switch (matched_insn)
6281
116k
    {
6282
490
    case MVE_VCMP_FP_T2:
6283
1.13k
    case MVE_VPT_FP_T2:
6284
1.13k
      if ((arm_decode_field (given, 12, 12) == 0)
6285
1.13k
    && (arm_decode_field (given, 5, 5) == 1))
6286
640
  {
6287
640
    *unpredictable_code = UNPRED_FCA_0_FCB_1;
6288
640
    return true;
6289
640
  }
6290
492
      else
6291
492
  return false;
6292
6293
1.31k
    case MVE_VPT_VEC_T4:
6294
2.13k
    case MVE_VPT_VEC_T5:
6295
4.03k
    case MVE_VPT_VEC_T6:
6296
4.24k
    case MVE_VCMP_VEC_T4:
6297
4.60k
    case MVE_VCMP_VEC_T5:
6298
4.81k
    case MVE_VCMP_VEC_T6:
6299
4.81k
      if (arm_decode_field (given, 0, 3) == 0xd)
6300
773
  {
6301
773
    *unpredictable_code = UNPRED_R13;
6302
773
    return true;
6303
773
  }
6304
4.03k
      else
6305
4.03k
  return false;
6306
6307
1.02k
    case MVE_VDUP:
6308
1.02k
      {
6309
1.02k
  unsigned long gpr = arm_decode_field (given, 12, 15);
6310
1.02k
  if (gpr == 0xd)
6311
195
    {
6312
195
      *unpredictable_code = UNPRED_R13;
6313
195
      return true;
6314
195
    }
6315
831
  else if (gpr == 0xf)
6316
196
    {
6317
196
      *unpredictable_code = UNPRED_R15;
6318
196
      return true;
6319
196
    }
6320
6321
635
  return false;
6322
1.02k
      }
6323
6324
272
    case MVE_VQADD_T2:
6325
1.61k
    case MVE_VQSUB_T2:
6326
2.08k
    case MVE_VMUL_FP_T2:
6327
2.56k
    case MVE_VMUL_VEC_T2:
6328
2.82k
    case MVE_VMLA:
6329
4.75k
    case MVE_VBRSR:
6330
5.13k
    case MVE_VADD_FP_T2:
6331
5.32k
    case MVE_VSUB_FP_T2:
6332
5.53k
    case MVE_VADD_VEC_T2:
6333
5.79k
    case MVE_VSUB_VEC_T2:
6334
5.98k
    case MVE_VQRSHL_T2:
6335
6.18k
    case MVE_VQSHL_T1:
6336
6.51k
    case MVE_VRSHL_T2:
6337
6.70k
    case MVE_VSHL_T2:
6338
7.25k
    case MVE_VSHLC:
6339
7.88k
    case MVE_VQDMLAH:
6340
8.09k
    case MVE_VQRDMLAH:
6341
8.30k
    case MVE_VQDMLASH:
6342
8.49k
    case MVE_VQRDMLASH:
6343
9.39k
    case MVE_VQDMULH_T3:
6344
9.59k
    case MVE_VQRDMULH_T4:
6345
10.0k
    case MVE_VMLAS:
6346
10.5k
    case MVE_VFMA_FP_SCALAR:
6347
10.9k
    case MVE_VFMAS_FP_SCALAR:
6348
11.2k
    case MVE_VHADD_T2:
6349
11.7k
    case MVE_VHSUB_T2:
6350
11.7k
      {
6351
11.7k
  unsigned long gpr = arm_decode_field (given, 0, 3);
6352
11.7k
  if (gpr == 0xd)
6353
2.83k
    {
6354
2.83k
      *unpredictable_code = UNPRED_R13;
6355
2.83k
      return true;
6356
2.83k
    }
6357
8.89k
  else if (gpr == 0xf)
6358
530
    {
6359
530
      *unpredictable_code = UNPRED_R15;
6360
530
      return true;
6361
530
    }
6362
6363
8.36k
  return false;
6364
11.7k
      }
6365
6366
261
    case MVE_VLD2:
6367
1.05k
    case MVE_VST2:
6368
1.05k
      {
6369
1.05k
  unsigned long rn = arm_decode_field (given, 16, 19);
6370
6371
1.05k
  if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
6372
199
    {
6373
199
      *unpredictable_code = UNPRED_R13_AND_WB;
6374
199
      return true;
6375
199
    }
6376
6377
858
  if (rn == 0xf)
6378
392
    {
6379
392
      *unpredictable_code = UNPRED_R15;
6380
392
      return true;
6381
392
    }
6382
6383
466
  if (arm_decode_field_multiple (given, 13, 15, 22, 22) > 6)
6384
254
    {
6385
254
      *unpredictable_code = UNPRED_Q_GT_6;
6386
254
      return true;
6387
254
    }
6388
212
  else
6389
212
    return false;
6390
466
      }
6391
6392
762
    case MVE_VLD4:
6393
1.28k
    case MVE_VST4:
6394
1.28k
      {
6395
1.28k
  unsigned long rn = arm_decode_field (given, 16, 19);
6396
6397
1.28k
  if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
6398
199
    {
6399
199
      *unpredictable_code = UNPRED_R13_AND_WB;
6400
199
      return true;
6401
199
    }
6402
6403
1.08k
  if (rn == 0xf)
6404
207
    {
6405
207
      *unpredictable_code = UNPRED_R15;
6406
207
      return true;
6407
207
    }
6408
6409
879
  if (arm_decode_field_multiple (given, 13, 15, 22, 22) > 4)
6410
556
    {
6411
556
      *unpredictable_code = UNPRED_Q_GT_4;
6412
556
      return true;
6413
556
    }
6414
323
  else
6415
323
    return false;
6416
879
      }
6417
6418
410
    case MVE_VLDRB_T5:
6419
3.27k
    case MVE_VLDRH_T6:
6420
3.76k
    case MVE_VLDRW_T7:
6421
4.20k
    case MVE_VSTRB_T5:
6422
4.70k
    case MVE_VSTRH_T6:
6423
5.10k
    case MVE_VSTRW_T7:
6424
5.10k
      {
6425
5.10k
  unsigned long rn = arm_decode_field (given, 16, 19);
6426
6427
5.10k
  if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
6428
407
    {
6429
407
      *unpredictable_code = UNPRED_R13_AND_WB;
6430
407
      return true;
6431
407
    }
6432
4.70k
  else if (rn == 0xf)
6433
623
    {
6434
623
      *unpredictable_code = UNPRED_R15;
6435
623
      return true;
6436
623
    }
6437
4.07k
  else
6438
4.07k
    return false;
6439
5.10k
      }
6440
6441
957
    case MVE_VLDRB_GATHER_T1:
6442
957
      if (arm_decode_field (given, 0, 0) == 1)
6443
213
  {
6444
213
    *unpredictable_code = UNPRED_OS;
6445
213
    return true;
6446
213
  }
6447
6448
      /*  fall through.  */
6449
      /* To handle common code with T2-T4 variants.  */
6450
1.90k
    case MVE_VLDRH_GATHER_T2:
6451
2.30k
    case MVE_VLDRW_GATHER_T3:
6452
2.70k
    case MVE_VLDRD_GATHER_T4:
6453
2.70k
      {
6454
2.70k
  unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6455
2.70k
  unsigned long qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6456
6457
2.70k
  if (qd == qm)
6458
674
    {
6459
674
      *unpredictable_code = UNPRED_Q_REGS_EQUAL;
6460
674
      return true;
6461
674
    }
6462
6463
2.02k
  if (arm_decode_field (given, 16, 19) == 0xf)
6464
1.55k
    {
6465
1.55k
      *unpredictable_code = UNPRED_R15;
6466
1.55k
      return true;
6467
1.55k
    }
6468
6469
473
  return false;
6470
2.02k
      }
6471
6472
794
    case MVE_VLDRW_GATHER_T5:
6473
1.15k
    case MVE_VLDRD_GATHER_T6:
6474
1.15k
      {
6475
1.15k
  unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6476
1.15k
  unsigned long qm = arm_decode_field_multiple (given, 17, 19, 7, 7);
6477
6478
1.15k
  if (qd == qm)
6479
446
    {
6480
446
      *unpredictable_code = UNPRED_Q_REGS_EQUAL;
6481
446
      return true;
6482
446
    }
6483
713
  else
6484
713
    return false;
6485
1.15k
      }
6486
6487
1.04k
    case MVE_VSTRB_SCATTER_T1:
6488
1.04k
      if (arm_decode_field (given, 16, 19) == 0xf)
6489
524
  {
6490
524
    *unpredictable_code = UNPRED_R15;
6491
524
    return true;
6492
524
  }
6493
524
      else if (arm_decode_field (given, 0, 0) == 1)
6494
319
  {
6495
319
    *unpredictable_code = UNPRED_OS;
6496
319
    return true;
6497
319
  }
6498
205
      else
6499
205
  return false;
6500
6501
910
    case MVE_VSTRH_SCATTER_T2:
6502
1.82k
    case MVE_VSTRW_SCATTER_T3:
6503
1.90k
    case MVE_VSTRD_SCATTER_T4:
6504
1.90k
      if (arm_decode_field (given, 16, 19) == 0xf)
6505
869
  {
6506
869
    *unpredictable_code = UNPRED_R15;
6507
869
    return true;
6508
869
  }
6509
1.03k
      else
6510
1.03k
  return false;
6511
6512
1.20k
    case MVE_VMOV2_VEC_LANE_TO_GP:
6513
2.19k
    case MVE_VMOV2_GP_TO_VEC_LANE:
6514
4.26k
    case MVE_VCVT_BETWEEN_FP_INT:
6515
6.09k
    case MVE_VCVT_FROM_FP_TO_INT:
6516
6.09k
      {
6517
6.09k
  unsigned long rt = arm_decode_field (given, 0, 3);
6518
6.09k
  unsigned long rt2 = arm_decode_field (given, 16, 19);
6519
6520
6.09k
  if ((rt == 0xd) || (rt2 == 0xd))
6521
723
    {
6522
723
      *unpredictable_code = UNPRED_R13;
6523
723
      return true;
6524
723
    }
6525
5.37k
  else if ((rt == 0xf) || (rt2 == 0xf))
6526
2.09k
    {
6527
2.09k
      *unpredictable_code = UNPRED_R15;
6528
2.09k
      return true;
6529
2.09k
    }
6530
3.28k
  else if (rt == rt2 && matched_insn != MVE_VMOV2_GP_TO_VEC_LANE)
6531
201
    {
6532
201
      *unpredictable_code = UNPRED_GP_REGS_EQUAL;
6533
201
      return true;
6534
201
    }
6535
6536
3.08k
  return false;
6537
6.09k
      }
6538
6539
201
    case MVE_VMAXV:
6540
547
    case MVE_VMAXAV:
6541
751
    case MVE_VMAXNMV_FP:
6542
964
    case MVE_VMAXNMAV_FP:
6543
1.27k
    case MVE_VMINNMV_FP:
6544
1.47k
    case MVE_VMINNMAV_FP:
6545
1.68k
    case MVE_VMINV:
6546
1.88k
    case MVE_VMINAV:
6547
2.12k
    case MVE_VABAV:
6548
2.32k
    case MVE_VMOV_HFP_TO_GP:
6549
4.34k
    case MVE_VMOV_GP_TO_VEC_LANE:
6550
8.53k
    case MVE_VMOV_VEC_LANE_TO_GP:
6551
8.53k
      {
6552
8.53k
  unsigned long rda = arm_decode_field (given, 12, 15);
6553
8.53k
  if (rda == 0xd)
6554
202
    {
6555
202
      *unpredictable_code = UNPRED_R13;
6556
202
      return true;
6557
202
    }
6558
8.33k
  else if (rda == 0xf)
6559
1.05k
    {
6560
1.05k
      *unpredictable_code = UNPRED_R15;
6561
1.05k
      return true;
6562
1.05k
    }
6563
6564
7.27k
  return false;
6565
8.53k
      }
6566
6567
1.09k
    case MVE_VMULL_INT:
6568
1.09k
      {
6569
1.09k
  unsigned long Qd;
6570
1.09k
  unsigned long Qm;
6571
1.09k
  unsigned long Qn;
6572
6573
1.09k
  if (arm_decode_field (given, 20, 21) == 2)
6574
866
    {
6575
866
      Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6576
866
      Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6577
866
      Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6578
6579
866
      if ((Qd == Qn) || (Qd == Qm))
6580
460
        {
6581
460
    *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_2;
6582
460
    return true;
6583
460
        }
6584
406
      else
6585
406
        return false;
6586
866
    }
6587
225
  else
6588
225
    return false;
6589
1.09k
      }
6590
6591
946
    case MVE_VCMUL_FP:
6592
1.23k
    case MVE_VQDMULL_T1:
6593
1.23k
      {
6594
1.23k
  unsigned long Qd;
6595
1.23k
  unsigned long Qm;
6596
1.23k
  unsigned long Qn;
6597
6598
1.23k
  if (arm_decode_field (given, 28, 28) == 1)
6599
920
    {
6600
920
      Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6601
920
      Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6602
920
      Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6603
6604
920
      if ((Qd == Qn) || (Qd == Qm))
6605
670
        {
6606
670
    *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
6607
670
    return true;
6608
670
        }
6609
250
      else
6610
250
        return false;
6611
920
    }
6612
317
  else
6613
317
    return false;
6614
1.23k
      }
6615
6616
1.56k
    case MVE_VQDMULL_T2:
6617
1.56k
      {
6618
1.56k
  unsigned long gpr = arm_decode_field (given, 0, 3);
6619
1.56k
  if (gpr == 0xd)
6620
207
    {
6621
207
      *unpredictable_code = UNPRED_R13;
6622
207
      return true;
6623
207
    }
6624
1.36k
  else if (gpr == 0xf)
6625
236
    {
6626
236
      *unpredictable_code = UNPRED_R15;
6627
236
      return true;
6628
236
    }
6629
6630
1.12k
  if (arm_decode_field (given, 28, 28) == 1)
6631
582
    {
6632
582
      unsigned long Qd
6633
582
        = arm_decode_field_multiple (given, 13, 15, 22, 22);
6634
582
      unsigned long Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6635
6636
582
      if (Qd == Qn)
6637
206
        {
6638
206
    *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
6639
206
    return true;
6640
206
        }
6641
376
      else
6642
376
        return false;
6643
582
    }
6644
6645
544
  return false;
6646
1.12k
      }
6647
6648
917
    case MVE_VMLSLDAV:
6649
1.23k
    case MVE_VRMLSLDAVH:
6650
2.37k
    case MVE_VMLALDAV:
6651
2.57k
    case MVE_VADDLV:
6652
2.57k
      if (arm_decode_field (given, 20, 22) == 6)
6653
1.31k
  {
6654
1.31k
    *unpredictable_code = UNPRED_R13;
6655
1.31k
    return true;
6656
1.31k
  }
6657
1.26k
      else
6658
1.26k
  return false;
6659
6660
1.09k
    case MVE_VDWDUP:
6661
1.52k
    case MVE_VIWDUP:
6662
1.52k
      if (arm_decode_field (given, 1, 3) == 6)
6663
538
  {
6664
538
    *unpredictable_code = UNPRED_R13;
6665
538
    return true;
6666
538
  }
6667
987
      else
6668
987
  return false;
6669
6670
300
    case MVE_VCADD_VEC:
6671
849
    case MVE_VHCADD:
6672
849
      {
6673
849
  unsigned long Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6674
849
  unsigned long Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6675
849
  if ((Qd == Qm) && arm_decode_field (given, 20, 21) == 2)
6676
224
    {
6677
224
      *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_2;
6678
224
      return true;
6679
224
    }
6680
625
  else
6681
625
    return false;
6682
849
      }
6683
6684
723
    case MVE_VCADD_FP:
6685
723
      {
6686
723
  unsigned long Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6687
723
  unsigned long Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6688
723
  if ((Qd == Qm) && arm_decode_field (given, 20, 20) == 1)
6689
202
    {
6690
202
      *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
6691
202
      return true;
6692
202
    }
6693
521
  else
6694
521
    return false;
6695
723
      }
6696
6697
981
    case MVE_VCMLA_FP:
6698
981
      {
6699
981
  unsigned long Qda;
6700
981
  unsigned long Qm;
6701
981
  unsigned long Qn;
6702
6703
981
  if (arm_decode_field (given, 20, 20) == 1)
6704
760
    {
6705
760
      Qda = arm_decode_field_multiple (given, 13, 15, 22, 22);
6706
760
      Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6707
760
      Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6708
6709
760
      if ((Qda == Qn) || (Qda == Qm))
6710
391
        {
6711
391
    *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
6712
391
    return true;
6713
391
        }
6714
369
      else
6715
369
        return false;
6716
760
    }
6717
221
  else
6718
221
    return false;
6719
6720
981
      }
6721
6722
566
    case MVE_VCTP:
6723
566
      if (arm_decode_field (given, 16, 19) == 0xd)
6724
329
  {
6725
329
    *unpredictable_code = UNPRED_R13;
6726
329
    return true;
6727
329
  }
6728
237
      else
6729
237
  return false;
6730
6731
471
    case MVE_VREV64:
6732
471
      {
6733
471
  unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6734
471
  unsigned long qm = arm_decode_field_multiple (given, 1, 3, 6, 6);
6735
6736
471
  if (qd == qm)
6737
199
    {
6738
199
      *unpredictable_code = UNPRED_Q_REGS_EQUAL;
6739
199
      return true;
6740
199
    }
6741
272
  else
6742
272
    return false;
6743
471
      }
6744
6745
439
    case MVE_LSLL:
6746
879
    case MVE_LSLLI:
6747
1.29k
    case MVE_LSRL:
6748
1.68k
    case MVE_ASRL:
6749
1.98k
    case MVE_ASRLI:
6750
2.39k
    case MVE_UQSHLL:
6751
2.61k
    case MVE_UQRSHLL:
6752
3.03k
    case MVE_URSHRL:
6753
3.52k
    case MVE_SRSHRL:
6754
4.06k
    case MVE_SQSHLL:
6755
4.42k
    case MVE_SQRSHRL:
6756
4.42k
      {
6757
4.42k
  unsigned long gpr = arm_decode_field (given, 9, 11);
6758
4.42k
  gpr = ((gpr << 1) | 1);
6759
4.42k
  if (gpr == 0xd)
6760
1.90k
    {
6761
1.90k
      *unpredictable_code = UNPRED_R13;
6762
1.90k
      return true;
6763
1.90k
    }
6764
2.52k
  else if (gpr == 0xf)
6765
0
    {
6766
0
      *unpredictable_code = UNPRED_R15;
6767
0
      return true;
6768
0
    }
6769
6770
2.52k
  return false;
6771
4.42k
      }
6772
6773
52.9k
    default:
6774
52.9k
      return false;
6775
116k
    }
6776
116k
}
6777
6778
static void
6779
print_mve_vmov_index (struct disassemble_info *info, unsigned long given)
6780
6.20k
{
6781
6.20k
  unsigned long op1 = arm_decode_field (given, 21, 22);
6782
6.20k
  unsigned long op2 = arm_decode_field (given, 5, 6);
6783
6.20k
  unsigned long h = arm_decode_field (given, 16, 16);
6784
6.20k
  unsigned long index_operand, esize, targetBeat, idx;
6785
6.20k
  void *stream = info->stream;
6786
6.20k
  fprintf_styled_ftype func = info->fprintf_styled_func;
6787
6788
6.20k
  if ((op1 & 0x2) == 0x2)
6789
2.70k
    {
6790
2.70k
      index_operand = op2;
6791
2.70k
      esize = 8;
6792
2.70k
    }
6793
3.50k
  else if (((op1 & 0x2) == 0x0) && ((op2 & 0x1) == 0x1))
6794
926
    {
6795
926
      index_operand = op2  >> 1;
6796
926
      esize = 16;
6797
926
    }
6798
2.57k
  else if (((op1 & 0x2) == 0) && ((op2 & 0x3) == 0))
6799
1.69k
    {
6800
1.69k
      index_operand = 0;
6801
1.69k
      esize = 32;
6802
1.69k
    }
6803
883
  else
6804
883
    {
6805
883
      func (stream, dis_style_text, "<undefined index>");
6806
883
      return;
6807
883
    }
6808
6809
5.32k
  targetBeat =  (op1 & 0x1) | (h << 1);
6810
5.32k
  idx = index_operand + targetBeat * (32/esize);
6811
6812
5.32k
  func (stream, dis_style_immediate, "%lu", idx);
6813
5.32k
}
6814
6815
/* Print neon and mve 8-bit immediate that can be a 8, 16, 32, or 64-bits
6816
   in length and integer of floating-point type.  */
6817
static void
6818
print_simd_imm8 (struct disassemble_info *info, unsigned long given,
6819
     unsigned int ibit_loc, const struct mopcode32 *insn)
6820
7.98k
{
6821
7.98k
  int bits = 0;
6822
7.98k
  int cmode = (given >> 8) & 0xf;
6823
7.98k
  int op = (given >> 5) & 0x1;
6824
7.98k
  unsigned long value = 0, hival = 0;
6825
7.98k
  unsigned shift;
6826
7.98k
  int size = 0;
6827
7.98k
  int isfloat = 0;
6828
7.98k
  void *stream = info->stream;
6829
7.98k
  fprintf_styled_ftype func = info->fprintf_styled_func;
6830
6831
  /* On Neon the 'i' bit is at bit 24, on mve it is
6832
     at bit 28.  */
6833
7.98k
  bits |= ((given >> ibit_loc) & 1) << 7;
6834
7.98k
  bits |= ((given >> 16) & 7) << 4;
6835
7.98k
  bits |= ((given >> 0) & 15) << 0;
6836
6837
7.98k
  if (cmode < 8)
6838
3.64k
    {
6839
3.64k
      shift = (cmode >> 1) & 3;
6840
3.64k
      value = (unsigned long) bits << (8 * shift);
6841
3.64k
      size = 32;
6842
3.64k
    }
6843
4.33k
  else if (cmode < 12)
6844
1.70k
    {
6845
1.70k
      shift = (cmode >> 1) & 1;
6846
1.70k
      value = (unsigned long) bits << (8 * shift);
6847
1.70k
      size = 16;
6848
1.70k
    }
6849
2.63k
  else if (cmode < 14)
6850
1.42k
    {
6851
1.42k
      shift = (cmode & 1) + 1;
6852
1.42k
      value = (unsigned long) bits << (8 * shift);
6853
1.42k
      value |= (1ul << (8 * shift)) - 1;
6854
1.42k
      size = 32;
6855
1.42k
    }
6856
1.21k
  else if (cmode == 14)
6857
994
    {
6858
994
      if (op)
6859
792
  {
6860
    /* Bit replication into bytes.  */
6861
792
    int ix;
6862
792
    unsigned long mask;
6863
6864
792
    value = 0;
6865
792
    hival = 0;
6866
7.12k
    for (ix = 7; ix >= 0; ix--)
6867
6.33k
      {
6868
6.33k
        mask = ((bits >> ix) & 1) ? 0xff : 0;
6869
6.33k
        if (ix <= 3)
6870
3.16k
    value = (value << 8) | mask;
6871
3.16k
        else
6872
3.16k
    hival = (hival << 8) | mask;
6873
6.33k
      }
6874
792
    size = 64;
6875
792
  }
6876
202
      else
6877
202
  {
6878
    /* Byte replication.  */
6879
202
    value = (unsigned long) bits;
6880
202
    size = 8;
6881
202
  }
6882
994
    }
6883
220
  else if (!op)
6884
220
    {
6885
      /* Floating point encoding.  */
6886
220
      int tmp;
6887
6888
220
      value = (unsigned long)  (bits & 0x7f) << 19;
6889
220
      value |= (unsigned long) (bits & 0x80) << 24;
6890
220
      tmp = bits & 0x40 ? 0x3c : 0x40;
6891
220
      value |= (unsigned long) tmp << 24;
6892
220
      size = 32;
6893
220
      isfloat = 1;
6894
220
    }
6895
0
  else
6896
0
    {
6897
0
      func (stream, dis_style_text, "<illegal constant %.8x:%x:%x>",
6898
0
      bits, cmode, op);
6899
0
      size = 32;
6900
0
      return;
6901
0
    }
6902
6903
  /* printU determines whether the immediate value should be printed as
6904
     unsigned.  */
6905
7.98k
  unsigned printU = 0;
6906
7.98k
  switch (insn->mve_op)
6907
7.98k
    {
6908
0
    default:
6909
0
      break;
6910
    /* We want this for instructions that don't have a 'signed' type.  */
6911
1.49k
    case MVE_VBIC_IMM:
6912
1.70k
    case MVE_VORR_IMM:
6913
4.63k
    case MVE_VMVN_IMM:
6914
7.98k
    case MVE_VMOV_IMM_TO_VEC:
6915
7.98k
      printU = 1;
6916
7.98k
      break;
6917
7.98k
    }
6918
7.98k
  switch (size)
6919
7.98k
    {
6920
202
    case 8:
6921
202
      func (stream, dis_style_immediate, "#%ld", value);
6922
202
      func (stream, dis_style_comment_start, "\t@ 0x%.2lx", value);
6923
202
      break;
6924
6925
1.70k
    case 16:
6926
1.70k
      func (stream, dis_style_immediate, printU ? "#%lu" : "#%ld", value);
6927
1.70k
      func (stream, dis_style_comment_start, "\t@ 0x%.4lx", value);
6928
1.70k
      break;
6929
6930
5.28k
    case 32:
6931
5.28k
      if (isfloat)
6932
220
  {
6933
220
    unsigned char valbytes[4];
6934
220
    double fvalue;
6935
6936
    /* Do this a byte at a time so we don't have to
6937
       worry about the host's endianness.  */
6938
220
    valbytes[0] = value & 0xff;
6939
220
    valbytes[1] = (value >> 8) & 0xff;
6940
220
    valbytes[2] = (value >> 16) & 0xff;
6941
220
    valbytes[3] = (value >> 24) & 0xff;
6942
6943
220
    floatformat_to_double
6944
220
      (& floatformat_ieee_single_little, valbytes,
6945
220
       & fvalue);
6946
6947
220
    func (stream, dis_style_immediate, "#%.7g", fvalue);
6948
220
    func (stream, dis_style_comment_start, "\t@ 0x%.8lx", value);
6949
220
  }
6950
5.06k
      else
6951
5.06k
  {
6952
5.06k
    func (stream, dis_style_immediate,
6953
5.06k
    printU ? "#%lu" : "#%ld",
6954
5.06k
    (long) (((value & 0x80000000L) != 0)
6955
5.06k
      && !printU
6956
5.06k
      ? value | ~0xffffffffL : value));
6957
5.06k
    func (stream, dis_style_comment_start, "\t@ 0x%.8lx", value);
6958
5.06k
  }
6959
5.28k
      break;
6960
6961
792
    case 64:
6962
792
      func (stream, dis_style_immediate, "#0x%.8lx%.8lx", hival, value);
6963
792
      break;
6964
6965
0
    default:
6966
0
      abort ();
6967
7.98k
    }
6968
6969
7.98k
}
6970
6971
static void
6972
print_mve_undefined (struct disassemble_info *info,
6973
         enum mve_undefined undefined_code)
6974
13.6k
{
6975
13.6k
  void *stream = info->stream;
6976
13.6k
  fprintf_styled_ftype func = info->fprintf_styled_func;
6977
  /* Initialize REASON to avoid compiler warning about uninitialized
6978
     usage, though such usage should be impossible.  */
6979
13.6k
  const char *reason = "??";
6980
6981
13.6k
  switch (undefined_code)
6982
13.6k
    {
6983
601
    case UNDEF_SIZE:
6984
601
      reason = "illegal size";
6985
601
      break;
6986
6987
2.06k
    case UNDEF_SIZE_0:
6988
2.06k
      reason = "size equals zero";
6989
2.06k
      break;
6990
6991
571
    case UNDEF_SIZE_2:
6992
571
      reason = "size equals two";
6993
571
      break;
6994
6995
4.16k
    case UNDEF_SIZE_3:
6996
4.16k
      reason = "size equals three";
6997
4.16k
      break;
6998
6999
823
    case UNDEF_SIZE_LE_1:
7000
823
      reason = "size <= 1";
7001
823
      break;
7002
7003
201
    case UNDEF_SIZE_NOT_0:
7004
201
      reason = "size not equal to 0";
7005
201
      break;
7006
7007
627
    case UNDEF_SIZE_NOT_2:
7008
627
      reason = "size not equal to 2";
7009
627
      break;
7010
7011
0
    case UNDEF_SIZE_NOT_3:
7012
0
      reason = "size not equal to 3";
7013
0
      break;
7014
7015
204
    case UNDEF_NOT_UNS_SIZE_0:
7016
204
      reason = "not unsigned and size = zero";
7017
204
      break;
7018
7019
448
    case UNDEF_NOT_UNS_SIZE_1:
7020
448
      reason = "not unsigned and size = one";
7021
448
      break;
7022
7023
196
    case UNDEF_NOT_UNSIGNED:
7024
196
      reason = "not unsigned";
7025
196
      break;
7026
7027
241
    case UNDEF_VCVT_IMM6:
7028
241
      reason = "invalid imm6";
7029
241
      break;
7030
7031
999
    case UNDEF_VCVT_FSI_IMM6:
7032
999
      reason = "fsi = 0 and invalid imm6";
7033
999
      break;
7034
7035
883
    case UNDEF_BAD_OP1_OP2:
7036
883
      reason = "bad size with op2 = 2 and op1 = 0 or 1";
7037
883
      break;
7038
7039
657
    case UNDEF_BAD_U_OP1_OP2:
7040
657
      reason = "unsigned with op2 = 0 and op1 = 0 or 1";
7041
657
      break;
7042
7043
0
    case UNDEF_OP_0_BAD_CMODE:
7044
0
      reason = "op field equal 0 and bad cmode";
7045
0
      break;
7046
7047
605
    case UNDEF_XCHG_UNS:
7048
605
      reason = "exchange and unsigned together";
7049
605
      break;
7050
7051
399
    case UNDEF_NONE:
7052
399
      reason = "";
7053
399
      break;
7054
13.6k
    }
7055
7056
13.6k
  func (stream, dis_style_text, "\t\tundefined instruction: %s", reason);
7057
13.6k
}
7058
7059
static void
7060
print_mve_unpredictable (struct disassemble_info *info,
7061
       enum mve_unpredictable unpredict_code)
7062
26.9k
{
7063
26.9k
  void *stream = info->stream;
7064
26.9k
  fprintf_styled_ftype func = info->fprintf_styled_func;
7065
  /* Initialize REASON to avoid compiler warning about uninitialized
7066
     usage, though such usage should be impossible.  */
7067
26.9k
  const char *reason = "??";
7068
7069
26.9k
  switch (unpredict_code)
7070
26.9k
    {
7071
1.63k
    case UNPRED_IT_BLOCK:
7072
1.63k
      reason = "mve instruction in it block";
7073
1.63k
      break;
7074
7075
640
    case UNPRED_FCA_0_FCB_1:
7076
640
      reason = "condition bits, fca = 0 and fcb = 1";
7077
640
      break;
7078
7079
9.02k
    case UNPRED_R13:
7080
9.02k
      reason = "use of r13 (sp)";
7081
9.02k
      break;
7082
7083
8.28k
    case UNPRED_R15:
7084
8.28k
      reason = "use of r15 (pc)";
7085
8.28k
      break;
7086
7087
556
    case UNPRED_Q_GT_4:
7088
556
      reason = "start register block > r4";
7089
556
      break;
7090
7091
254
    case UNPRED_Q_GT_6:
7092
254
      reason = "start register block > r6";
7093
254
      break;
7094
7095
805
    case UNPRED_R13_AND_WB:
7096
805
      reason = "use of r13 and write back";
7097
805
      break;
7098
7099
1.31k
    case UNPRED_Q_REGS_EQUAL:
7100
1.31k
      reason = "same vector register used for destination and other operand";
7101
1.31k
      break;
7102
7103
532
    case UNPRED_OS:
7104
532
      reason = "use of offset scaled";
7105
532
      break;
7106
7107
201
    case UNPRED_GP_REGS_EQUAL:
7108
201
      reason = "same general-purpose register used for both operands";
7109
201
      break;
7110
7111
1.46k
    case UNPRED_Q_REGS_EQ_AND_SIZE_1:
7112
1.46k
      reason = "use of identical q registers and size = 1";
7113
1.46k
      break;
7114
7115
684
    case UNPRED_Q_REGS_EQ_AND_SIZE_2:
7116
684
      reason = "use of identical q registers and size = 1";
7117
684
      break;
7118
7119
1.51k
    case UNPRED_NONE:
7120
1.51k
      reason = "";
7121
1.51k
      break;
7122
26.9k
    }
7123
7124
26.9k
  func (stream, dis_style_comment_start, "%s: %s",
7125
26.9k
  UNPREDICTABLE_INSTRUCTION, reason);
7126
26.9k
}
7127
7128
/* Print register block operand for mve vld2/vld4/vst2/vld4.  */
7129
7130
static void
7131
print_mve_register_blocks (struct disassemble_info *info,
7132
         unsigned long given,
7133
         enum mve_instructions matched_insn)
7134
2.34k
{
7135
2.34k
  void *stream = info->stream;
7136
2.34k
  fprintf_styled_ftype func = info->fprintf_styled_func;
7137
7138
2.34k
  unsigned long q_reg_start = arm_decode_field_multiple (given,
7139
2.34k
               13, 15,
7140
2.34k
               22, 22);
7141
2.34k
  switch (matched_insn)
7142
2.34k
    {
7143
261
    case MVE_VLD2:
7144
1.05k
    case MVE_VST2:
7145
1.05k
      if (q_reg_start <= 6)
7146
217
  {
7147
217
    func (stream, dis_style_text, "{");
7148
217
    func (stream, dis_style_register, "q%ld", q_reg_start);
7149
217
    func (stream, dis_style_text, ", ");
7150
217
    func (stream, dis_style_register, "q%ld", q_reg_start + 1);
7151
217
    func (stream, dis_style_text, "}");
7152
217
  }
7153
841
      else
7154
841
  func (stream, dis_style_text, "<illegal reg q%ld>", q_reg_start);
7155
1.05k
      break;
7156
7157
763
    case MVE_VLD4:
7158
1.29k
    case MVE_VST4:
7159
1.29k
      if (q_reg_start <= 4)
7160
323
  {
7161
323
    func (stream, dis_style_text, "{");
7162
323
    func (stream, dis_style_register, "q%ld", q_reg_start);
7163
323
    func (stream, dis_style_text, ", ");
7164
323
    func (stream, dis_style_register, "q%ld", q_reg_start + 1);
7165
323
    func (stream, dis_style_text, ", ");
7166
323
    func (stream, dis_style_register, "q%ld", q_reg_start + 2);
7167
323
    func (stream, dis_style_text, ", ");
7168
323
    func (stream, dis_style_register, "q%ld", q_reg_start + 3);
7169
323
    func (stream, dis_style_text, "}");
7170
323
  }
7171
968
      else
7172
968
  func (stream, dis_style_text, "<illegal reg q%ld>", q_reg_start);
7173
1.29k
      break;
7174
7175
0
    default:
7176
0
      break;
7177
2.34k
    }
7178
2.34k
}
7179
7180
static void
7181
print_mve_rounding_mode (struct disassemble_info *info,
7182
       unsigned long given,
7183
       enum mve_instructions matched_insn)
7184
3.57k
{
7185
3.57k
  void *stream = info->stream;
7186
3.57k
  fprintf_styled_ftype func = info->fprintf_styled_func;
7187
7188
3.57k
  switch (matched_insn)
7189
3.57k
    {
7190
1.84k
    case MVE_VCVT_FROM_FP_TO_INT:
7191
1.84k
      {
7192
1.84k
  switch (arm_decode_field (given, 8, 9))
7193
1.84k
    {
7194
919
    case 0:
7195
919
      func (stream, dis_style_mnemonic, "a");
7196
919
      break;
7197
7198
468
    case 1:
7199
468
      func (stream, dis_style_mnemonic, "n");
7200
468
      break;
7201
7202
243
    case 2:
7203
243
      func (stream, dis_style_mnemonic, "p");
7204
243
      break;
7205
7206
211
    case 3:
7207
211
      func (stream, dis_style_mnemonic, "m");
7208
211
      break;
7209
7210
0
    default:
7211
0
      break;
7212
1.84k
    }
7213
1.84k
      }
7214
1.84k
      break;
7215
7216
1.84k
    case MVE_VRINT_FP:
7217
1.73k
      {
7218
1.73k
  switch (arm_decode_field (given, 7, 9))
7219
1.73k
    {
7220
201
    case 0:
7221
201
      func (stream, dis_style_mnemonic, "n");
7222
201
      break;
7223
7224
345
    case 1:
7225
345
      func (stream, dis_style_mnemonic, "x");
7226
345
      break;
7227
7228
268
    case 2:
7229
268
      func (stream, dis_style_mnemonic, "a");
7230
268
      break;
7231
7232
208
    case 3:
7233
208
      func (stream, dis_style_mnemonic, "z");
7234
208
      break;
7235
7236
196
    case 5:
7237
196
      func (stream, dis_style_mnemonic, "m");
7238
196
      break;
7239
7240
324
    case 7:
7241
324
      func (stream, dis_style_mnemonic, "p");
7242
7243
325
    case 4:
7244
520
    case 6:
7245
520
    default:
7246
520
      break;
7247
1.73k
    }
7248
1.73k
      }
7249
1.73k
      break;
7250
7251
1.73k
    default:
7252
0
      break;
7253
3.57k
    }
7254
3.57k
}
7255
7256
static void
7257
print_mve_vcvt_size (struct disassemble_info *info,
7258
         unsigned long given,
7259
         enum mve_instructions matched_insn)
7260
6.89k
{
7261
6.89k
  unsigned long mode = 0;
7262
6.89k
  void *stream = info->stream;
7263
6.89k
  fprintf_styled_ftype func = info->fprintf_styled_func;
7264
7265
6.89k
  switch (matched_insn)
7266
6.89k
    {
7267
2.56k
    case MVE_VCVT_FP_FIX_VEC:
7268
2.56k
      {
7269
2.56k
  mode = (((given & 0x200) >> 7)
7270
2.56k
    | ((given & 0x10000000) >> 27)
7271
2.56k
    | ((given & 0x100) >> 8));
7272
7273
2.56k
  switch (mode)
7274
2.56k
    {
7275
292
    case 0:
7276
292
      func (stream, dis_style_mnemonic, "f16.s16");
7277
292
      break;
7278
7279
800
    case 1:
7280
800
      func (stream, dis_style_mnemonic, "s16.f16");
7281
800
      break;
7282
7283
198
    case 2:
7284
198
      func (stream, dis_style_mnemonic, "f16.u16");
7285
198
      break;
7286
7287
246
    case 3:
7288
246
      func (stream, dis_style_mnemonic, "u16.f16");
7289
246
      break;
7290
7291
220
    case 4:
7292
220
      func (stream, dis_style_mnemonic, "f32.s32");
7293
220
      break;
7294
7295
553
    case 5:
7296
553
      func (stream, dis_style_mnemonic, "s32.f32");
7297
553
      break;
7298
7299
36
    case 6:
7300
36
      func (stream, dis_style_mnemonic, "f32.u32");
7301
36
      break;
7302
7303
216
    case 7:
7304
216
      func (stream, dis_style_mnemonic, "u32.f32");
7305
216
      break;
7306
7307
0
    default:
7308
0
      break;
7309
2.56k
    }
7310
2.56k
  break;
7311
2.56k
      }
7312
2.56k
    case MVE_VCVT_BETWEEN_FP_INT:
7313
2.07k
      {
7314
2.07k
  unsigned long size = arm_decode_field (given, 18, 19);
7315
2.07k
  unsigned long op = arm_decode_field (given, 7, 8);
7316
7317
2.07k
  if (size == 1)
7318
908
    {
7319
908
      switch (op)
7320
908
        {
7321
196
        case 0:
7322
196
    func (stream, dis_style_mnemonic, "f16.s16");
7323
196
    break;
7324
7325
78
        case 1:
7326
78
    func (stream, dis_style_mnemonic, "f16.u16");
7327
78
    break;
7328
7329
384
        case 2:
7330
384
    func (stream, dis_style_mnemonic, "s16.f16");
7331
384
    break;
7332
7333
250
        case 3:
7334
250
    func (stream, dis_style_mnemonic, "u16.f16");
7335
250
    break;
7336
7337
0
        default:
7338
0
    break;
7339
908
        }
7340
908
    }
7341
1.17k
  else if (size == 2)
7342
851
    {
7343
851
      switch (op)
7344
851
        {
7345
195
        case 0:
7346
195
    func (stream, dis_style_mnemonic, "f32.s32");
7347
195
    break;
7348
7349
258
        case 1:
7350
258
    func (stream, dis_style_mnemonic, "f32.u32");
7351
258
    break;
7352
7353
198
        case 2:
7354
198
    func (stream, dis_style_mnemonic, "s32.f32");
7355
198
    break;
7356
7357
200
        case 3:
7358
200
    func (stream, dis_style_mnemonic, "u32.f32");
7359
200
    break;
7360
851
        }
7361
851
    }
7362
2.07k
      }
7363
2.07k
      break;
7364
7365
2.07k
    case MVE_VCVT_FP_HALF_FP:
7366
412
      {
7367
412
  unsigned long op = arm_decode_field (given, 28, 28);
7368
412
  if (op == 0)
7369
211
    func (stream, dis_style_mnemonic, "f16.f32");
7370
201
  else if (op == 1)
7371
201
    func (stream, dis_style_mnemonic, "f32.f16");
7372
412
      }
7373
412
      break;
7374
7375
1.84k
    case MVE_VCVT_FROM_FP_TO_INT:
7376
1.84k
      {
7377
1.84k
  unsigned long size = arm_decode_field_multiple (given, 7, 7, 18, 19);
7378
7379
1.84k
  switch (size)
7380
1.84k
    {
7381
210
    case 2:
7382
210
      func (stream, dis_style_mnemonic, "s16.f16");
7383
210
      break;
7384
7385
198
    case 3:
7386
198
      func (stream, dis_style_mnemonic, "u16.f16");
7387
198
      break;
7388
7389
207
    case 4:
7390
207
      func (stream, dis_style_mnemonic, "s32.f32");
7391
207
      break;
7392
7393
202
    case 5:
7394
202
      func (stream, dis_style_mnemonic, "u32.f32");
7395
202
      break;
7396
7397
1.02k
    default:
7398
1.02k
      break;
7399
1.84k
    }
7400
1.84k
      }
7401
1.84k
      break;
7402
7403
1.84k
    default:
7404
0
      break;
7405
6.89k
    }
7406
6.89k
}
7407
7408
static void
7409
print_mve_rotate (struct disassemble_info *info, unsigned long rot,
7410
      unsigned long rot_width)
7411
3.50k
{
7412
3.50k
  void *stream = info->stream;
7413
3.50k
  fprintf_styled_ftype func = info->fprintf_styled_func;
7414
7415
3.50k
  if (rot_width == 1)
7416
1.57k
    {
7417
1.57k
      switch (rot)
7418
1.57k
  {
7419
815
  case 0:
7420
815
    func (stream, dis_style_immediate, "90");
7421
815
    break;
7422
757
  case 1:
7423
757
    func (stream, dis_style_immediate, "270");
7424
757
    break;
7425
0
  default:
7426
0
    break;
7427
1.57k
  }
7428
1.57k
    }
7429
1.92k
  else if (rot_width == 2)
7430
1.92k
    {
7431
1.92k
      switch (rot)
7432
1.92k
  {
7433
222
  case 0:
7434
222
    func (stream, dis_style_immediate, "0");
7435
222
    break;
7436
1.03k
  case 1:
7437
1.03k
    func (stream, dis_style_immediate, "90");
7438
1.03k
    break;
7439
227
  case 2:
7440
227
    func (stream, dis_style_immediate, "180");
7441
227
    break;
7442
441
  case 3:
7443
441
    func (stream, dis_style_immediate, "270");
7444
441
    break;
7445
0
  default:
7446
0
    break;
7447
1.92k
  }
7448
1.92k
    }
7449
3.50k
}
7450
7451
static void
7452
print_instruction_predicate (struct disassemble_info *info)
7453
86.4k
{
7454
86.4k
  void *stream = info->stream;
7455
86.4k
  fprintf_styled_ftype func = info->fprintf_styled_func;
7456
7457
86.4k
  if (vpt_block_state.next_pred_state == PRED_THEN)
7458
1.73k
    func (stream, dis_style_mnemonic, "t");
7459
84.7k
  else if (vpt_block_state.next_pred_state == PRED_ELSE)
7460
774
    func (stream, dis_style_mnemonic, "e");
7461
86.4k
}
7462
7463
static void
7464
print_mve_size (struct disassemble_info *info,
7465
    unsigned long size,
7466
    enum mve_instructions matched_insn)
7467
86.3k
{
7468
86.3k
  void *stream = info->stream;
7469
86.3k
  fprintf_styled_ftype func = info->fprintf_styled_func;
7470
7471
86.3k
  switch (matched_insn)
7472
86.3k
    {
7473
241
    case MVE_VABAV:
7474
489
    case MVE_VABD_VEC:
7475
691
    case MVE_VABS_FP:
7476
1.12k
    case MVE_VABS_VEC:
7477
1.32k
    case MVE_VADD_VEC_T1:
7478
1.52k
    case MVE_VADD_VEC_T2:
7479
1.72k
    case MVE_VADDV:
7480
3.65k
    case MVE_VBRSR:
7481
3.95k
    case MVE_VCADD_VEC:
7482
4.16k
    case MVE_VCLS:
7483
4.37k
    case MVE_VCLZ:
7484
4.57k
    case MVE_VCMP_VEC_T1:
7485
4.77k
    case MVE_VCMP_VEC_T2:
7486
5.04k
    case MVE_VCMP_VEC_T3:
7487
5.24k
    case MVE_VCMP_VEC_T4:
7488
5.60k
    case MVE_VCMP_VEC_T5:
7489
5.81k
    case MVE_VCMP_VEC_T6:
7490
6.37k
    case MVE_VCTP:
7491
7.12k
    case MVE_VDDUP:
7492
8.21k
    case MVE_VDWDUP:
7493
8.85k
    case MVE_VHADD_T1:
7494
9.13k
    case MVE_VHADD_T2:
7495
9.68k
    case MVE_VHCADD:
7496
9.89k
    case MVE_VHSUB_T1:
7497
10.4k
    case MVE_VHSUB_T2:
7498
10.8k
    case MVE_VIDUP:
7499
11.3k
    case MVE_VIWDUP:
7500
11.5k
    case MVE_VLD2:
7501
12.3k
    case MVE_VLD4:
7502
13.3k
    case MVE_VLDRB_GATHER_T1:
7503
14.4k
    case MVE_VLDRH_GATHER_T2:
7504
14.4k
    case MVE_VLDRW_GATHER_T3:
7505
14.4k
    case MVE_VLDRD_GATHER_T4:
7506
14.9k
    case MVE_VLDRB_T1:
7507
15.8k
    case MVE_VLDRH_T2:
7508
16.0k
    case MVE_VMAX:
7509
16.2k
    case MVE_VMAXA:
7510
16.4k
    case MVE_VMAXV:
7511
16.8k
    case MVE_VMAXAV:
7512
17.0k
    case MVE_VMIN:
7513
17.2k
    case MVE_VMINA:
7514
17.4k
    case MVE_VMINV:
7515
17.6k
    case MVE_VMINAV:
7516
17.9k
    case MVE_VMLA:
7517
18.4k
    case MVE_VMLAS:
7518
18.6k
    case MVE_VMUL_VEC_T1:
7519
19.0k
    case MVE_VMUL_VEC_T2:
7520
19.3k
    case MVE_VMULH:
7521
19.8k
    case MVE_VRMULH:
7522
20.9k
    case MVE_VMULL_INT:
7523
21.2k
    case MVE_VNEG_FP:
7524
21.4k
    case MVE_VNEG_VEC:
7525
22.1k
    case MVE_VPT_VEC_T1:
7526
22.9k
    case MVE_VPT_VEC_T2:
7527
25.8k
    case MVE_VPT_VEC_T3:
7528
27.1k
    case MVE_VPT_VEC_T4:
7529
27.9k
    case MVE_VPT_VEC_T5:
7530
29.8k
    case MVE_VPT_VEC_T6:
7531
30.0k
    case MVE_VQABS:
7532
30.6k
    case MVE_VQADD_T1:
7533
30.9k
    case MVE_VQADD_T2:
7534
31.2k
    case MVE_VQDMLADH:
7535
31.6k
    case MVE_VQRDMLADH:
7536
32.2k
    case MVE_VQDMLAH:
7537
32.4k
    case MVE_VQRDMLAH:
7538
32.6k
    case MVE_VQDMLASH:
7539
32.8k
    case MVE_VQRDMLASH:
7540
33.1k
    case MVE_VQDMLSDH:
7541
33.4k
    case MVE_VQRDMLSDH:
7542
33.6k
    case MVE_VQDMULH_T1:
7543
33.8k
    case MVE_VQRDMULH_T2:
7544
34.7k
    case MVE_VQDMULH_T3:
7545
34.9k
    case MVE_VQRDMULH_T4:
7546
35.1k
    case MVE_VQNEG:
7547
35.3k
    case MVE_VQRSHL_T1:
7548
35.5k
    case MVE_VQRSHL_T2:
7549
35.7k
    case MVE_VQSHL_T1:
7550
35.9k
    case MVE_VQSHL_T4:
7551
36.2k
    case MVE_VQSUB_T1:
7552
37.5k
    case MVE_VQSUB_T2:
7553
38.0k
    case MVE_VREV32:
7554
38.4k
    case MVE_VREV64:
7555
38.7k
    case MVE_VRHADD:
7556
40.4k
    case MVE_VRINT_FP:
7557
40.6k
    case MVE_VRSHL_T1:
7558
41.0k
    case MVE_VRSHL_T2:
7559
41.2k
    case MVE_VSHL_T2:
7560
41.4k
    case MVE_VSHL_T3:
7561
41.9k
    case MVE_VSHLL_T2:
7562
42.7k
    case MVE_VST2:
7563
43.3k
    case MVE_VST4:
7564
44.3k
    case MVE_VSTRB_SCATTER_T1:
7565
45.2k
    case MVE_VSTRH_SCATTER_T2:
7566
46.1k
    case MVE_VSTRW_SCATTER_T3:
7567
46.8k
    case MVE_VSTRB_T1:
7568
47.8k
    case MVE_VSTRH_T2:
7569
48.1k
    case MVE_VSUB_VEC_T1:
7570
48.3k
    case MVE_VSUB_VEC_T2:
7571
48.3k
      if (size <= 3)
7572
48.3k
  func (stream, dis_style_mnemonic, "%s", mve_vec_sizename[size]);
7573
0
      else
7574
0
  func (stream, dis_style_text, "<undef size>");
7575
48.3k
      break;
7576
7577
206
    case MVE_VABD_FP:
7578
415
    case MVE_VADD_FP_T1:
7579
793
    case MVE_VADD_FP_T2:
7580
1.32k
    case MVE_VSUB_FP_T1:
7581
1.52k
    case MVE_VSUB_FP_T2:
7582
1.93k
    case MVE_VCMP_FP_T1:
7583
2.42k
    case MVE_VCMP_FP_T2:
7584
2.92k
    case MVE_VFMA_FP_SCALAR:
7585
3.14k
    case MVE_VFMA_FP:
7586
3.34k
    case MVE_VFMS_FP:
7587
3.68k
    case MVE_VFMAS_FP_SCALAR:
7588
3.97k
    case MVE_VMAXNM_FP:
7589
4.18k
    case MVE_VMAXNMA_FP:
7590
4.38k
    case MVE_VMAXNMV_FP:
7591
4.59k
    case MVE_VMAXNMAV_FP:
7592
4.87k
    case MVE_VMINNM_FP:
7593
5.07k
    case MVE_VMINNMA_FP:
7594
5.37k
    case MVE_VMINNMV_FP:
7595
5.58k
    case MVE_VMINNMAV_FP:
7596
5.78k
    case MVE_VMUL_FP_T1:
7597
6.25k
    case MVE_VMUL_FP_T2:
7598
7.04k
    case MVE_VPT_FP_T1:
7599
7.68k
    case MVE_VPT_FP_T2:
7600
7.68k
      if (size == 0)
7601
4.11k
  func (stream, dis_style_mnemonic, "32");
7602
3.56k
      else if (size == 1)
7603
3.56k
  func (stream, dis_style_mnemonic, "16");
7604
7.68k
      break;
7605
7606
723
    case MVE_VCADD_FP:
7607
1.70k
    case MVE_VCMLA_FP:
7608
2.65k
    case MVE_VCMUL_FP:
7609
3.11k
    case MVE_VMLADAV_T1:
7610
4.26k
    case MVE_VMLALDAV:
7611
4.49k
    case MVE_VMLSDAV_T1:
7612
5.40k
    case MVE_VMLSLDAV:
7613
5.75k
    case MVE_VMOVN:
7614
6.04k
    case MVE_VQDMULL_T1:
7615
7.61k
    case MVE_VQDMULL_T2:
7616
7.85k
    case MVE_VQMOVN:
7617
8.14k
    case MVE_VQMOVUN:
7618
8.14k
      if (size == 0)
7619
4.04k
  func (stream, dis_style_mnemonic, "16");
7620
4.10k
      else if (size == 1)
7621
3.50k
  func (stream, dis_style_mnemonic, "32");
7622
8.14k
      break;
7623
7624
398
    case MVE_VMOVL:
7625
398
      if (size == 1)
7626
199
  func (stream, dis_style_mnemonic, "8");
7627
199
      else if (size == 2)
7628
199
  func (stream, dis_style_mnemonic, "16");
7629
398
      break;
7630
7631
1.02k
    case MVE_VDUP:
7632
1.02k
      switch (size)
7633
1.02k
  {
7634
199
  case 0:
7635
199
    func (stream, dis_style_mnemonic, "32");
7636
199
    break;
7637
194
  case 1:
7638
194
    func (stream, dis_style_mnemonic, "16");
7639
194
    break;
7640
430
  case 2:
7641
430
    func (stream, dis_style_mnemonic, "8");
7642
430
    break;
7643
204
  default:
7644
204
    break;
7645
1.02k
  }
7646
1.02k
      break;
7647
7648
2.02k
    case MVE_VMOV_GP_TO_VEC_LANE:
7649
6.20k
    case MVE_VMOV_VEC_LANE_TO_GP:
7650
6.20k
      switch (size)
7651
6.20k
  {
7652
1.69k
  case 0: case 4:
7653
1.69k
    func (stream, dis_style_mnemonic, "32");
7654
1.69k
    break;
7655
7656
442
  case 1: case 3:
7657
926
  case 5: case 7:
7658
926
    func (stream, dis_style_mnemonic, "16");
7659
926
    break;
7660
7661
1.10k
  case 8: case 9: case 10: case 11:
7662
2.70k
  case 12: case 13: case 14: case 15:
7663
2.70k
    func (stream, dis_style_mnemonic, "8");
7664
2.70k
    break;
7665
7666
883
  default:
7667
883
    break;
7668
6.20k
  }
7669
6.20k
      break;
7670
7671
6.20k
    case MVE_VMOV_IMM_TO_VEC:
7672
3.34k
      switch (size)
7673
3.34k
  {
7674
902
  case 0: case 4: case 8:
7675
1.53k
  case 12: case 24: case 26:
7676
1.53k
    func (stream, dis_style_mnemonic, "i32");
7677
1.53k
    break;
7678
603
  case 16: case 20:
7679
603
    func (stream, dis_style_mnemonic, "i16");
7680
603
    break;
7681
202
  case 28:
7682
202
    func (stream, dis_style_mnemonic, "i8");
7683
202
    break;
7684
792
  case 29:
7685
792
    func (stream, dis_style_mnemonic, "i64");
7686
792
    break;
7687
220
  case 30:
7688
220
    func (stream, dis_style_mnemonic, "f32");
7689
220
    break;
7690
0
  default:
7691
0
    break;
7692
3.34k
  }
7693
3.34k
      break;
7694
7695
3.34k
    case MVE_VMULL_POLY:
7696
524
      if (size == 0)
7697
301
  func (stream, dis_style_mnemonic, "p8");
7698
223
      else if (size == 1)
7699
223
  func (stream, dis_style_mnemonic, "p16");
7700
524
      break;
7701
7702
2.93k
    case MVE_VMVN_IMM:
7703
2.93k
      switch (size)
7704
2.93k
  {
7705
1.28k
  case 0: case 2: case 4:
7706
2.52k
  case 6: case 12: case 13:
7707
2.52k
    func (stream, dis_style_mnemonic, "32");
7708
2.52k
    break;
7709
7710
406
  case 8: case 10:
7711
406
    func (stream, dis_style_mnemonic, "16");
7712
406
    break;
7713
7714
0
  default:
7715
0
    break;
7716
2.93k
  }
7717
2.93k
      break;
7718
7719
2.93k
    case MVE_VBIC_IMM:
7720
1.70k
    case MVE_VORR_IMM:
7721
1.70k
      switch (size)
7722
1.70k
  {
7723
602
  case 1: case 3:
7724
1.01k
  case 5: case 7:
7725
1.01k
    func (stream, dis_style_mnemonic, "32");
7726
1.01k
    break;
7727
7728
691
  case 9: case 11:
7729
691
    func (stream, dis_style_mnemonic, "16");
7730
691
    break;
7731
7732
0
  default:
7733
0
    break;
7734
1.70k
  }
7735
1.70k
      break;
7736
7737
1.70k
    case MVE_VQSHRN:
7738
825
    case MVE_VQSHRUN:
7739
1.07k
    case MVE_VQRSHRN:
7740
1.37k
    case MVE_VQRSHRUN:
7741
1.91k
    case MVE_VRSHRN:
7742
2.51k
    case MVE_VSHRN:
7743
2.51k
      {
7744
2.51k
  switch (size)
7745
2.51k
  {
7746
1.33k
  case 1:
7747
1.33k
    func (stream, dis_style_mnemonic, "16");
7748
1.33k
    break;
7749
7750
525
  case 2: case 3:
7751
525
    func (stream, dis_style_mnemonic, "32");
7752
525
    break;
7753
7754
660
  default:
7755
660
    break;
7756
2.51k
  }
7757
2.51k
      }
7758
2.51k
      break;
7759
7760
2.51k
    case MVE_VQSHL_T2:
7761
924
    case MVE_VQSHLU_T3:
7762
1.13k
    case MVE_VRSHR:
7763
1.34k
    case MVE_VSHL_T1:
7764
2.51k
    case MVE_VSHLL_T1:
7765
3.06k
    case MVE_VSHR:
7766
3.31k
    case MVE_VSLI:
7767
3.51k
    case MVE_VSRI:
7768
3.51k
      {
7769
3.51k
  switch (size)
7770
3.51k
  {
7771
464
  case 1:
7772
464
    func (stream, dis_style_mnemonic, "8");
7773
464
    break;
7774
7775
1.15k
  case 2: case 3:
7776
1.15k
    func (stream, dis_style_mnemonic, "16");
7777
1.15k
    break;
7778
7779
1.63k
  case 4: case 5: case 6: case 7:
7780
1.63k
    func (stream, dis_style_mnemonic, "32");
7781
1.63k
    break;
7782
7783
264
  default:
7784
264
    break;
7785
3.51k
  }
7786
3.51k
      }
7787
3.51k
      break;
7788
7789
3.51k
    default:
7790
0
      break;
7791
86.3k
    }
7792
86.3k
}
7793
7794
/* Return true if INSN is a shift insn with an immediate shift amount
7795
   which needs decoding as per print_mve_shift_n.  */
7796
7797
static bool
7798
mve_shift_insn_p (enum mve_instructions insn)
7799
9.46k
{
7800
9.46k
  switch (insn)
7801
9.46k
    {
7802
543
    case MVE_VQSHL_T2:
7803
924
    case MVE_VQSHLU_T3:
7804
1.15k
    case MVE_VQSHRN:
7805
1.74k
    case MVE_VQSHRUN:
7806
1.99k
    case MVE_VQRSHRN:
7807
2.30k
    case MVE_VQRSHRUN:
7808
2.51k
    case MVE_VRSHR:
7809
3.04k
    case MVE_VRSHRN:
7810
3.25k
    case MVE_VSHL_T1:
7811
4.42k
    case MVE_VSHLL_T1:
7812
4.97k
    case MVE_VSHR:
7813
5.58k
    case MVE_VSHRN:
7814
5.82k
    case MVE_VSLI:
7815
6.02k
    case MVE_VSRI:
7816
6.02k
      return true;
7817
3.43k
    default:
7818
3.43k
      return false;
7819
9.46k
    }
7820
9.46k
}
7821
7822
static void
7823
print_mve_shift_n (struct disassemble_info *info, long given,
7824
       enum mve_instructions matched_insn)
7825
6.02k
{
7826
6.02k
  void *stream = info->stream;
7827
6.02k
  fprintf_styled_ftype func = info->fprintf_styled_func;
7828
7829
6.02k
  int startAt0
7830
6.02k
    = matched_insn == MVE_VQSHL_T2
7831
6.02k
      || matched_insn == MVE_VQSHLU_T3
7832
6.02k
      || matched_insn == MVE_VSHL_T1
7833
6.02k
      || matched_insn == MVE_VSHLL_T1
7834
6.02k
      || matched_insn == MVE_VSLI;
7835
7836
6.02k
  unsigned imm6 = (given & 0x3f0000) >> 16;
7837
7838
6.02k
  if (matched_insn == MVE_VSHLL_T1)
7839
1.17k
    imm6 &= 0x1f;
7840
7841
6.02k
  unsigned shiftAmount = 0;
7842
6.02k
  if ((imm6 & 0x20) != 0)
7843
1.63k
    shiftAmount = startAt0 ? imm6 - 32 : 64 - imm6;
7844
4.39k
  else if ((imm6 & 0x10) != 0)
7845
1.67k
    shiftAmount = startAt0 ? imm6 - 16 : 32 - imm6;
7846
2.71k
  else if ((imm6 & 0x08) != 0)
7847
1.79k
    shiftAmount = startAt0 ? imm6 - 8 : 16 - imm6;
7848
924
  else
7849
924
    print_mve_undefined (info, UNDEF_SIZE_0);
7850
7851
6.02k
  func (stream, dis_style_immediate, "%u", shiftAmount);
7852
6.02k
}
7853
7854
static void
7855
print_vec_condition (struct disassemble_info *info, long given,
7856
         enum mve_instructions matched_insn)
7857
12.1k
{
7858
12.1k
  void *stream = info->stream;
7859
12.1k
  fprintf_styled_ftype func = info->fprintf_styled_func;
7860
12.1k
  long vec_cond = 0;
7861
7862
12.1k
  switch (matched_insn)
7863
12.1k
    {
7864
788
    case MVE_VPT_FP_T1:
7865
1.20k
    case MVE_VCMP_FP_T1:
7866
1.20k
      vec_cond = (((given & 0x1000) >> 10)
7867
1.20k
      | ((given & 1) << 1)
7868
1.20k
      | ((given & 0x0080) >> 7));
7869
1.20k
      func (stream, dis_style_sub_mnemonic, "%s", vec_condnames[vec_cond]);
7870
1.20k
      break;
7871
7872
642
    case MVE_VPT_FP_T2:
7873
1.13k
    case MVE_VCMP_FP_T2:
7874
1.13k
      vec_cond = (((given & 0x1000) >> 10)
7875
1.13k
      | ((given & 0x0020) >> 4)
7876
1.13k
      | ((given & 0x0080) >> 7));
7877
1.13k
      func (stream, dis_style_sub_mnemonic, "%s", vec_condnames[vec_cond]);
7878
1.13k
      break;
7879
7880
634
    case MVE_VPT_VEC_T1:
7881
833
    case MVE_VCMP_VEC_T1:
7882
833
      vec_cond = (given & 0x0080) >> 7;
7883
833
      func (stream, dis_style_sub_mnemonic, "%s", vec_condnames[vec_cond]);
7884
833
      break;
7885
7886
823
    case MVE_VPT_VEC_T2:
7887
1.01k
    case MVE_VCMP_VEC_T2:
7888
1.01k
      vec_cond = 2 | ((given & 0x0080) >> 7);
7889
1.01k
      func (stream, dis_style_sub_mnemonic, "%s", vec_condnames[vec_cond]);
7890
1.01k
      break;
7891
7892
2.87k
    case MVE_VPT_VEC_T3:
7893
3.14k
    case MVE_VCMP_VEC_T3:
7894
3.14k
      vec_cond = 4 | ((given & 1) << 1) | ((given & 0x0080) >> 7);
7895
3.14k
      func (stream, dis_style_sub_mnemonic, "%s", vec_condnames[vec_cond]);
7896
3.14k
      break;
7897
7898
1.31k
    case MVE_VPT_VEC_T4:
7899
1.52k
    case MVE_VCMP_VEC_T4:
7900
1.52k
      vec_cond = (given & 0x0080) >> 7;
7901
1.52k
      func (stream, dis_style_sub_mnemonic, "%s", vec_condnames[vec_cond]);
7902
1.52k
      break;
7903
7904
818
    case MVE_VPT_VEC_T5:
7905
1.17k
    case MVE_VCMP_VEC_T5:
7906
1.17k
      vec_cond = 2 | ((given & 0x0080) >> 7);
7907
1.17k
      func (stream, dis_style_sub_mnemonic, "%s", vec_condnames[vec_cond]);
7908
1.17k
      break;
7909
7910
1.90k
    case MVE_VPT_VEC_T6:
7911
2.11k
    case MVE_VCMP_VEC_T6:
7912
2.11k
      vec_cond = 4 | ((given & 0x0020) >> 4) | ((given & 0x0080) >> 7);
7913
2.11k
      func (stream, dis_style_sub_mnemonic, "%s", vec_condnames[vec_cond]);
7914
2.11k
      break;
7915
7916
0
    case MVE_NONE:
7917
0
    case MVE_VPST:
7918
0
    default:
7919
0
      break;
7920
12.1k
    }
7921
12.1k
}
7922
7923
686k
#define W_BIT 21
7924
142k
#define I_BIT 22
7925
1.19M
#define U_BIT 23
7926
876k
#define P_BIT 24
7927
7928
892k
#define WRITEBACK_BIT_SET (given & (1 << W_BIT))
7929
198k
#define IMMEDIATE_BIT_SET (given & (1 << I_BIT))
7930
1.37M
#define NEGATIVE_BIT_SET  ((given & (1 << U_BIT)) == 0)
7931
1.08M
#define PRE_BIT_SET   (given & (1 << P_BIT))
7932
7933
/* The assembler string for an instruction can include %{X:...%} patterns,
7934
   where the 'X' is one of the characters understood by this function.
7935
7936
   This function takes the X character, and returns a new style.  This new
7937
   style will be used by the caller to temporarily change the current base
7938
   style.  */
7939
7940
static enum disassembler_style
7941
decode_base_style (const char x)
7942
1.71M
{
7943
1.71M
  switch (x)
7944
1.71M
    {
7945
0
    case 'A': return dis_style_address;
7946
5.58k
    case 'B': return dis_style_sub_mnemonic;
7947
0
    case 'C': return dis_style_comment_start;
7948
0
    case 'D': return dis_style_assembler_directive;
7949
1.13M
    case 'I': return dis_style_immediate;
7950
0
    case 'M': return dis_style_mnemonic;
7951
0
    case 'O': return dis_style_address_offset;
7952
577k
    case 'R': return dis_style_register;
7953
0
    case 'S': return dis_style_symbol;
7954
0
    case 'T': return dis_style_text;
7955
0
    default:
7956
0
      abort ();
7957
1.71M
    }
7958
1.71M
}
7959
7960
/* Print one coprocessor instruction on INFO->STREAM.
7961
   Return TRUE if the instuction matched, FALSE if this is not a
7962
   recognised coprocessor instruction.  */
7963
7964
static bool
7965
print_insn_coprocessor_1 (const struct sopcode32 *opcodes,
7966
        bfd_vma pc,
7967
        struct disassemble_info *info,
7968
        long given,
7969
        bool thumb)
7970
7.56M
{
7971
7.56M
  const struct sopcode32 *insn;
7972
7.56M
  void *stream = info->stream;
7973
7.56M
  fprintf_styled_ftype func = info->fprintf_styled_func;
7974
7.56M
  unsigned long mask;
7975
7.56M
  unsigned long value = 0;
7976
7.56M
  int cond;
7977
7.56M
  int cp_num;
7978
7.56M
  struct arm_private_data *private_data = info->private_data;
7979
7.56M
  arm_feature_set allowed_arches = ARM_ARCH_NONE;
7980
7.56M
  arm_feature_set arm_ext_v8_1m_main =
7981
7.56M
    ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN);
7982
7.56M
  enum disassembler_style base_style = dis_style_mnemonic;
7983
7.56M
  enum disassembler_style old_base_style = base_style;
7984
7985
7.56M
  allowed_arches = private_data->features;
7986
7987
1.00G
  for (insn = opcodes; insn->assembler; insn++)
7988
1.00G
    {
7989
1.00G
      unsigned long u_reg = 16;
7990
1.00G
      bool is_unpredictable = false;
7991
1.00G
      signed long value_in_comment = 0;
7992
1.00G
      const char *c;
7993
7994
1.00G
      if (ARM_FEATURE_ZERO (insn->arch))
7995
7.82M
  switch (insn->value)
7996
7.82M
    {
7997
3.90M
    case SENTINEL_IWMMXT_START:
7998
3.90M
      if (info->mach != bfd_mach_arm_XScale
7999
3.90M
    && info->mach != bfd_mach_arm_iWMMXt
8000
3.90M
    && info->mach != bfd_mach_arm_iWMMXt2)
8001
3.83M
        do
8002
291M
    insn++;
8003
291M
        while ((! ARM_FEATURE_ZERO (insn->arch))
8004
291M
         && insn->value != SENTINEL_IWMMXT_END);
8005
3.90M
      continue;
8006
8007
69.9k
    case SENTINEL_IWMMXT_END:
8008
69.9k
      continue;
8009
8010
3.85M
    case SENTINEL_GENERIC_START:
8011
3.85M
      allowed_arches = private_data->features;
8012
3.85M
      continue;
8013
8014
0
    default:
8015
0
      abort ();
8016
7.82M
    }
8017
8018
993M
      mask = insn->mask;
8019
993M
      value = insn->value;
8020
993M
      cp_num = (given >> 8) & 0xf;
8021
8022
993M
      if (thumb)
8023
104M
  {
8024
    /* The high 4 bits are 0xe for Arm conditional instructions, and
8025
       0xe for arm unconditional instructions.  The rest of the
8026
       encoding is the same.  */
8027
104M
    mask |= 0xf0000000;
8028
104M
    value |= 0xe0000000;
8029
104M
    if (ifthen_state)
8030
4.04M
      cond = IFTHEN_COND;
8031
100M
    else
8032
100M
      cond = COND_UNCOND;
8033
104M
  }
8034
888M
      else
8035
888M
  {
8036
    /* Only match unconditional instuctions against unconditional
8037
       patterns.  */
8038
888M
    if ((given & 0xf0000000) == 0xf0000000)
8039
63.5M
      {
8040
63.5M
        mask |= 0xf0000000;
8041
63.5M
        cond = COND_UNCOND;
8042
63.5M
      }
8043
824M
    else
8044
824M
      {
8045
824M
        cond = (given >> 28) & 0xf;
8046
824M
        if (cond == 0xe)
8047
38.4M
    cond = COND_UNCOND;
8048
824M
      }
8049
888M
  }
8050
8051
993M
      if ((insn->isa == T32 && !thumb)
8052
993M
    || (insn->isa == ARM && thumb))
8053
6.93M
  continue;
8054
8055
986M
      if ((given & mask) != value)
8056
985M
  continue;
8057
8058
437k
      if (! ARM_CPU_HAS_FEATURE (insn->arch, allowed_arches))
8059
48.9k
  continue;
8060
8061
388k
      if (insn->value == 0xfe000010     /* mcr2  */
8062
388k
    || insn->value == 0xfe100010  /* mrc2  */
8063
388k
    || insn->value == 0xfc100000  /* ldc2  */
8064
388k
    || insn->value == 0xfc000000) /* stc2  */
8065
35.6k
  {
8066
35.6k
    if (cp_num == 9 || cp_num == 10 || cp_num == 11)
8067
5.30k
      is_unpredictable = true;
8068
8069
    /* Armv8.1-M Mainline FP & MVE instructions.  */
8070
35.6k
    if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
8071
35.6k
        && !ARM_CPU_IS_ANY (allowed_arches)
8072
35.6k
        && (cp_num == 8 || cp_num == 14 || cp_num == 15))
8073
8.85k
      continue;
8074
8075
35.6k
  }
8076
353k
      else if (insn->value == 0x0e000000     /* cdp  */
8077
353k
         || insn->value == 0xfe000000  /* cdp2  */
8078
353k
         || insn->value == 0x0e000010  /* mcr  */
8079
353k
         || insn->value == 0x0e100010  /* mrc  */
8080
353k
         || insn->value == 0x0c100000  /* ldc  */
8081
353k
         || insn->value == 0x0c000000) /* stc  */
8082
276k
  {
8083
    /* Floating-point instructions.  */
8084
276k
    if (cp_num == 9 || cp_num == 10 || cp_num == 11)
8085
17.5k
      continue;
8086
8087
    /* Armv8.1-M Mainline FP & MVE instructions.  */
8088
258k
    if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
8089
258k
        && !ARM_CPU_IS_ANY (allowed_arches)
8090
258k
        && (cp_num == 8 || cp_num == 14 || cp_num == 15))
8091
11.7k
      continue;
8092
258k
  }
8093
76.5k
      else if ((insn->value == 0xec100f80      /* vldr (system register) */
8094
76.5k
    || insn->value == 0xec000f80)  /* vstr (system register) */
8095
76.5k
         && arm_decode_field (given, 24, 24) == 0
8096
76.5k
         && arm_decode_field (given, 21, 21) == 0)
8097
  /* If the P and W bits are both 0 then these encodings match the MVE
8098
     VLDR and VSTR instructions, these are in a different table, so we
8099
     don't let it match here.  */
8100
1.84k
  continue;
8101
8102
8.96M
      for (c = insn->assembler; *c; c++)
8103
8.62M
  {
8104
8.62M
    if (*c == '%')
8105
3.85M
      {
8106
3.85M
        const char mod = *++c;
8107
8108
3.85M
        switch (mod)
8109
3.85M
    {
8110
980k
    case '{':
8111
980k
      ++c;
8112
980k
      if (*c == '\0')
8113
0
        abort ();
8114
980k
      old_base_style = base_style;
8115
980k
      base_style = decode_base_style (*c);
8116
980k
      ++c;
8117
980k
      if (*c != ':')
8118
0
        abort ();
8119
980k
      break;
8120
8121
980k
    case '}':
8122
980k
      base_style = old_base_style;
8123
980k
      break;
8124
8125
0
    case '%':
8126
0
      func (stream, base_style, "%%");
8127
0
      break;
8128
8129
190k
    case 'A':
8130
194k
    case 'K':
8131
194k
      {
8132
194k
        int rn = (given >> 16) & 0xf;
8133
194k
        bfd_vma offset = given & 0xff;
8134
8135
194k
        if (mod == 'K')
8136
4.34k
          offset = given & 0x7f;
8137
8138
194k
        func (stream, dis_style_text, "[");
8139
194k
        func (stream, dis_style_register, "%s",
8140
194k
        arm_regnames [(given >> 16) & 0xf]);
8141
8142
194k
        if (PRE_BIT_SET || WRITEBACK_BIT_SET)
8143
150k
          {
8144
      /* Not unindexed.  The offset is scaled.  */
8145
150k
      if (cp_num == 9)
8146
        /* vldr.16/vstr.16 will shift the address
8147
           left by 1 bit only.  */
8148
2.11k
        offset = offset * 2;
8149
148k
      else
8150
148k
        offset = offset * 4;
8151
8152
150k
      if (NEGATIVE_BIT_SET)
8153
90.4k
        offset = - offset;
8154
150k
      if (rn != 15)
8155
137k
        value_in_comment = offset;
8156
150k
          }
8157
8158
194k
        if (PRE_BIT_SET)
8159
103k
          {
8160
103k
      if (offset)
8161
86.1k
        {
8162
86.1k
          func (stream, dis_style_text, ", ");
8163
86.1k
          func (stream, dis_style_immediate, "#%d",
8164
86.1k
          (int) offset);
8165
86.1k
          func (stream, dis_style_text, "]%s",
8166
86.1k
          WRITEBACK_BIT_SET ? "!" : "");
8167
86.1k
        }
8168
17.6k
      else if (NEGATIVE_BIT_SET)
8169
14.3k
        {
8170
14.3k
          func (stream, dis_style_text, ", ");
8171
14.3k
          func (stream, dis_style_immediate, "#-0");
8172
14.3k
          func (stream, dis_style_text, "]");
8173
14.3k
        }
8174
3.35k
      else
8175
3.35k
        func (stream, dis_style_text, "]");
8176
103k
          }
8177
91.0k
        else
8178
91.0k
          {
8179
91.0k
      func (stream, dis_style_text, "]");
8180
8181
91.0k
      if (WRITEBACK_BIT_SET)
8182
46.8k
        {
8183
46.8k
          if (offset)
8184
41.7k
            {
8185
41.7k
        func (stream, dis_style_text, ", ");
8186
41.7k
        func (stream, dis_style_immediate,
8187
41.7k
              "#%d", (int) offset);
8188
41.7k
            }
8189
5.10k
          else if (NEGATIVE_BIT_SET)
8190
3.01k
            {
8191
3.01k
        func (stream, dis_style_text, ", ");
8192
3.01k
        func (stream, dis_style_immediate, "#-0");
8193
3.01k
            }
8194
46.8k
        }
8195
44.2k
      else
8196
44.2k
        {
8197
44.2k
          func (stream, dis_style_text, ", {");
8198
44.2k
          func (stream, dis_style_immediate, "%s%d",
8199
44.2k
          (NEGATIVE_BIT_SET && !offset) ? "-" : "",
8200
44.2k
          (int) offset);
8201
44.2k
          func (stream, dis_style_text, "}");
8202
44.2k
          value_in_comment = offset;
8203
44.2k
        }
8204
91.0k
          }
8205
194k
        if (rn == 15 && (PRE_BIT_SET || WRITEBACK_BIT_SET))
8206
13.3k
          {
8207
13.3k
      func (stream, dis_style_comment_start, "\t@ ");
8208
      /* For unaligned PCs, apply off-by-alignment
8209
         correction.  */
8210
13.3k
      info->print_address_func (offset + pc
8211
13.3k
              + info->bytes_per_chunk * 2
8212
13.3k
              - (pc & 3),
8213
13.3k
              info);
8214
13.3k
          }
8215
194k
      }
8216
194k
      break;
8217
8218
1.83k
    case 'B':
8219
1.83k
      {
8220
1.83k
        int regno = ((given >> 12) & 0xf) | ((given >> (22 - 4)) & 0x10);
8221
1.83k
        int offset = (given >> 1) & 0x3f;
8222
8223
1.83k
        func (stream, dis_style_text, "{");
8224
1.83k
        if (offset == 1)
8225
229
          func (stream, dis_style_register, "d%d", regno);
8226
1.60k
        else if (regno + offset > 32)
8227
1.01k
          {
8228
1.01k
      func (stream, dis_style_register, "d%d", regno);
8229
1.01k
      func (stream, dis_style_text, "-<overflow reg d%d>",
8230
1.01k
            regno + offset - 1);
8231
1.01k
          }
8232
586
        else
8233
586
          {
8234
586
      func (stream, dis_style_register, "d%d", regno);
8235
586
      func (stream, dis_style_text, "-");
8236
586
      func (stream, dis_style_register, "d%d",
8237
586
            regno + offset - 1);
8238
586
          }
8239
1.83k
        func (stream, dis_style_text, "}");
8240
1.83k
      }
8241
1.83k
      break;
8242
8243
1.10k
    case 'C':
8244
1.10k
      {
8245
1.10k
        bool single = ((given >> 8) & 1) == 0;
8246
1.10k
        char reg_prefix = single ? 's' : 'd';
8247
1.10k
        int Dreg = (given >> 22) & 0x1;
8248
1.10k
        int Vdreg = (given >> 12) & 0xf;
8249
1.10k
        int reg = single ? ((Vdreg << 1) | Dreg)
8250
1.10k
             : ((Dreg << 4) | Vdreg);
8251
1.10k
        int num = (given >> (single ? 0 : 1)) & 0x7f;
8252
1.10k
        int maxreg = single ? 31 : 15;
8253
1.10k
        int topreg = reg + num - 1;
8254
8255
1.10k
        func (stream, dis_style_text, "{");
8256
1.10k
        if (!num)
8257
194
          {
8258
      /* Nothing.  */
8259
194
          }
8260
909
        else if (num == 1)
8261
340
          {
8262
340
      func (stream, dis_style_register,
8263
340
            "%c%d", reg_prefix, reg);
8264
340
      func (stream, dis_style_text, ", ");
8265
340
          }
8266
569
        else if (topreg > maxreg)
8267
369
          {
8268
369
      func (stream, dis_style_register, "%c%d",
8269
369
            reg_prefix, reg);
8270
369
      func (stream, dis_style_text, "-<overflow reg d%d, ",
8271
369
            single ? topreg >> 1 : topreg);
8272
369
          }
8273
200
        else
8274
200
          {
8275
200
      func (stream, dis_style_register,
8276
200
            "%c%d", reg_prefix, reg);
8277
200
      func (stream, dis_style_text, "-");
8278
200
      func (stream, dis_style_register, "%c%d",
8279
200
            reg_prefix, topreg);
8280
200
      func (stream, dis_style_text, ", ");
8281
200
          }
8282
1.10k
        func (stream, dis_style_register, "VPR");
8283
1.10k
        func (stream, dis_style_text, "}");
8284
1.10k
      }
8285
1.10k
      break;
8286
8287
2.22k
    case 'u':
8288
2.22k
      if (cond != COND_UNCOND)
8289
195
        is_unpredictable = true;
8290
8291
      /* Fall through.  */
8292
342k
    case 'c':
8293
342k
      if (cond != COND_UNCOND && cp_num == 9)
8294
3.81k
        is_unpredictable = true;
8295
8296
      /* Fall through.  */
8297
342k
    case 'b':
8298
342k
      func (stream, dis_style_mnemonic, "%s",
8299
342k
      arm_conditional[cond]);
8300
342k
      break;
8301
8302
0
    case 'I':
8303
      /* Print a Cirrus/DSP shift immediate.  */
8304
      /* Immediates are 7bit signed ints with bits 0..3 in
8305
         bits 0..3 of opcode and bits 4..6 in bits 5..7
8306
         of opcode.  */
8307
0
      {
8308
0
        int imm;
8309
8310
0
        imm = (given & 0xf) | ((given & 0xe0) >> 1);
8311
8312
        /* Is ``imm'' a negative number?  */
8313
0
        if (imm & 0x40)
8314
0
          imm -= 0x80;
8315
8316
0
        func (stream, dis_style_immediate, "%d", imm);
8317
0
      }
8318
8319
0
      break;
8320
8321
4.34k
    case 'J':
8322
4.34k
      {
8323
4.34k
        unsigned long regno
8324
4.34k
          = arm_decode_field_multiple (given, 13, 15, 22, 22);
8325
8326
4.34k
        switch (regno)
8327
4.34k
          {
8328
505
          case 0x1:
8329
505
      func (stream, dis_style_register, "FPSCR");
8330
505
      break;
8331
358
          case 0x2:
8332
358
      func (stream, dis_style_register, "FPSCR_nzcvqc");
8333
358
      break;
8334
376
          case 0xc:
8335
376
      func (stream, dis_style_register, "VPR");
8336
376
      break;
8337
649
          case 0xd:
8338
649
      func (stream, dis_style_register, "P0");
8339
649
      break;
8340
1.05k
          case 0xe:
8341
1.05k
      func (stream, dis_style_register, "FPCXTNS");
8342
1.05k
      break;
8343
505
          case 0xf:
8344
505
      func (stream, dis_style_register, "FPCXTS");
8345
505
      break;
8346
893
          default:
8347
893
      func (stream, dis_style_text, "<invalid reg %lu>",
8348
893
            regno);
8349
893
      break;
8350
4.34k
          }
8351
4.34k
      }
8352
4.34k
      break;
8353
8354
10.0k
    case 'F':
8355
10.0k
      switch (given & 0x00408000)
8356
10.0k
        {
8357
3.12k
        case 0:
8358
3.12k
          func (stream, dis_style_immediate, "4");
8359
3.12k
          break;
8360
1.20k
        case 0x8000:
8361
1.20k
          func (stream, dis_style_immediate, "1");
8362
1.20k
          break;
8363
4.41k
        case 0x00400000:
8364
4.41k
          func (stream, dis_style_immediate, "2");
8365
4.41k
          break;
8366
1.31k
        default:
8367
1.31k
          func (stream, dis_style_immediate, "3");
8368
10.0k
        }
8369
10.0k
      break;
8370
8371
10.0k
    case 'P':
8372
4.94k
      switch (given & 0x00080080)
8373
4.94k
        {
8374
1.70k
        case 0:
8375
1.70k
          func (stream, dis_style_mnemonic, "s");
8376
1.70k
          break;
8377
625
        case 0x80:
8378
625
          func (stream, dis_style_mnemonic, "d");
8379
625
          break;
8380
1.57k
        case 0x00080000:
8381
1.57k
          func (stream, dis_style_mnemonic, "e");
8382
1.57k
          break;
8383
1.04k
        default:
8384
1.04k
          func (stream, dis_style_text, _("<illegal precision>"));
8385
1.04k
          break;
8386
4.94k
        }
8387
4.94k
      break;
8388
8389
10.9k
    case 'Q':
8390
10.9k
      switch (given & 0x00408000)
8391
10.9k
        {
8392
3.76k
        case 0:
8393
3.76k
          func (stream, dis_style_mnemonic, "s");
8394
3.76k
          break;
8395
1.80k
        case 0x8000:
8396
1.80k
          func (stream, dis_style_mnemonic, "d");
8397
1.80k
          break;
8398
4.06k
        case 0x00400000:
8399
4.06k
          func (stream, dis_style_mnemonic, "e");
8400
4.06k
          break;
8401
1.28k
        default:
8402
1.28k
          func (stream, dis_style_mnemonic, "p");
8403
1.28k
          break;
8404
10.9k
        }
8405
10.9k
      break;
8406
8407
10.9k
    case 'R':
8408
4.94k
      switch (given & 0x60)
8409
4.94k
        {
8410
1.64k
        case 0:
8411
1.64k
          break;
8412
1.13k
        case 0x20:
8413
1.13k
          func (stream, dis_style_mnemonic, "p");
8414
1.13k
          break;
8415
768
        case 0x40:
8416
768
          func (stream, dis_style_mnemonic, "m");
8417
768
          break;
8418
1.39k
        default:
8419
1.39k
          func (stream, dis_style_mnemonic, "z");
8420
1.39k
          break;
8421
4.94k
        }
8422
4.94k
      break;
8423
8424
882k
    case '0': case '1': case '2': case '3': case '4':
8425
1.28M
    case '5': case '6': case '7': case '8': case '9':
8426
1.28M
      {
8427
1.28M
        int width;
8428
8429
1.28M
        c = arm_decode_bitfield (c, given, &value, &width);
8430
8431
1.28M
        switch (*c)
8432
1.28M
          {
8433
33.5k
          case 'R':
8434
33.5k
      if (value == 15)
8435
3.36k
        is_unpredictable = true;
8436
      /* Fall through.  */
8437
64.8k
          case 'r':
8438
64.8k
      if (c[1] == 'u')
8439
9.42k
        {
8440
          /* Eat the 'u' character.  */
8441
9.42k
          ++ c;
8442
8443
9.42k
          if (u_reg == value)
8444
320
            is_unpredictable = true;
8445
9.42k
          u_reg = value;
8446
9.42k
        }
8447
64.8k
      func (stream, dis_style_register, "%s",
8448
64.8k
            arm_regnames[value]);
8449
64.8k
      break;
8450
5.85k
          case 'V':
8451
5.85k
      if (given & (1 << 6))
8452
3.54k
        goto Q;
8453
      /* FALLTHROUGH */
8454
8.49k
          case 'D':
8455
8.49k
      func (stream, dis_style_register, "d%ld", value);
8456
8.49k
      break;
8457
583
          case 'Q':
8458
4.13k
          Q:
8459
4.13k
      if (value & 1)
8460
1.33k
        func (stream, dis_style_text,
8461
1.33k
        "<illegal reg q%ld.5>", value >> 1);
8462
2.79k
      else
8463
2.79k
        func (stream, dis_style_register,
8464
2.79k
        "q%ld", value >> 1);
8465
4.13k
      break;
8466
972k
          case 'd':
8467
972k
      func (stream, base_style, "%ld", value);
8468
972k
      value_in_comment = value;
8469
972k
      break;
8470
1.00k
          case 'E':
8471
1.00k
                        {
8472
        /* Converts immediate 8 bit back to float value.  */
8473
1.00k
        unsigned floatVal = (value & 0x80) << 24
8474
1.00k
          | (value & 0x3F) << 19
8475
1.00k
          | ((value & 0x40) ? (0xF8 << 22) : (1 << 30));
8476
8477
        /* Quarter float have a maximum value of 31.0.
8478
           Get floating point value multiplied by 1e7.
8479
           The maximum value stays in limit of a 32-bit int.  */
8480
1.00k
        unsigned decVal =
8481
1.00k
          (78125 << (((floatVal >> 23) & 0xFF) - 124)) *
8482
1.00k
          (16 + (value & 0xF));
8483
8484
1.00k
        if (!(decVal % 1000000))
8485
434
          {
8486
434
            func (stream, dis_style_immediate, "%ld", value);
8487
434
            func (stream, dis_style_comment_start,
8488
434
            "\t@ 0x%08x %c%u.%01u",
8489
434
            floatVal, value & 0x80 ? '-' : ' ',
8490
434
            decVal / 10000000,
8491
434
            decVal % 10000000 / 1000000);
8492
434
          }
8493
571
        else if (!(decVal % 10000))
8494
249
          {
8495
249
            func (stream, dis_style_immediate, "%ld", value);
8496
249
            func (stream, dis_style_comment_start,
8497
249
            "\t@ 0x%08x %c%u.%03u",
8498
249
            floatVal, value & 0x80 ? '-' : ' ',
8499
249
            decVal / 10000000,
8500
249
            decVal % 10000000 / 10000);
8501
249
          }
8502
322
        else
8503
322
          {
8504
322
            func (stream, dis_style_immediate, "%ld", value);
8505
322
            func (stream, dis_style_comment_start,
8506
322
            "\t@ 0x%08x %c%u.%07u",
8507
322
            floatVal, value & 0x80 ? '-' : ' ',
8508
322
            decVal / 10000000, decVal % 10000000);
8509
322
          }
8510
1.00k
        break;
8511
583
      }
8512
553
          case 'k':
8513
553
      {
8514
553
        int from = (given & (1 << 7)) ? 32 : 16;
8515
553
        func (stream, dis_style_immediate, "%ld",
8516
553
        from - value);
8517
553
      }
8518
553
      break;
8519
8520
33.7k
          case 'f':
8521
33.7k
      if (value > 7)
8522
2.12k
        func (stream, dis_style_immediate, "#%s",
8523
2.12k
        arm_fp_const[value & 7]);
8524
31.6k
      else
8525
31.6k
        func (stream, dis_style_register, "f%ld", value);
8526
33.7k
      break;
8527
8528
626
          case 'w':
8529
626
      if (width == 2)
8530
419
        func (stream, dis_style_mnemonic, "%s",
8531
419
        iwmmxt_wwnames[value]);
8532
207
      else
8533
207
        func (stream, dis_style_mnemonic, "%s",
8534
207
        iwmmxt_wwssnames[value]);
8535
626
      break;
8536
8537
8.70k
          case 'g':
8538
8.70k
      func (stream, dis_style_register, "%s",
8539
8.70k
            iwmmxt_regnames[value]);
8540
8.70k
      break;
8541
495
          case 'G':
8542
495
      func (stream, dis_style_register, "%s",
8543
495
            iwmmxt_cregnames[value]);
8544
495
      break;
8545
8546
199
          case 'x':
8547
199
      func (stream, dis_style_immediate, "0x%lx",
8548
199
            (value & 0xffffffffUL));
8549
199
      break;
8550
8551
1.35k
          case 'c':
8552
1.35k
      switch (value)
8553
1.35k
        {
8554
544
        case 0:
8555
544
          func (stream, dis_style_mnemonic, "eq");
8556
544
          break;
8557
8558
208
        case 1:
8559
208
          func (stream, dis_style_mnemonic, "vs");
8560
208
          break;
8561
8562
357
        case 2:
8563
357
          func (stream, dis_style_mnemonic, "ge");
8564
357
          break;
8565
8566
247
        case 3:
8567
247
          func (stream, dis_style_mnemonic, "gt");
8568
247
          break;
8569
8570
0
        default:
8571
0
          func (stream, dis_style_text, "??");
8572
0
          break;
8573
1.35k
        }
8574
1.35k
      break;
8575
8576
1.35k
          case '`':
8577
636
      c++;
8578
636
      if (value == 0)
8579
242
        func (stream, dis_style_mnemonic, "%c", *c);
8580
636
      break;
8581
171k
          case '\'':
8582
171k
      c++;
8583
171k
      if (value == ((1ul << width) - 1))
8584
67.8k
        func (stream, base_style, "%c", *c);
8585
171k
      break;
8586
11.8k
          case '?':
8587
11.8k
      func (stream, base_style, "%c",
8588
11.8k
            c[(1 << width) - (int) value]);
8589
11.8k
      c += 1 << width;
8590
11.8k
      break;
8591
0
          default:
8592
0
      abort ();
8593
1.28M
          }
8594
1.28M
      }
8595
1.28M
      break;
8596
8597
1.28M
    case 'y':
8598
35.3k
    case 'z':
8599
35.3k
      {
8600
35.3k
        int single = *c++ == 'y';
8601
35.3k
        int regno;
8602
8603
35.3k
        switch (*c)
8604
35.3k
          {
8605
230
          case '4': /* Sm pair */
8606
9.87k
          case '0': /* Sm, Dm */
8607
9.87k
      regno = given & 0x0000000f;
8608
9.87k
      if (single)
8609
5.37k
        {
8610
5.37k
          regno <<= 1;
8611
5.37k
          regno += (given >> 5) & 1;
8612
5.37k
        }
8613
4.50k
      else
8614
4.50k
        regno += ((given >> 5) & 1) << 4;
8615
9.87k
      break;
8616
8617
13.8k
          case '1': /* Sd, Dd */
8618
13.8k
      regno = (given >> 12) & 0x0000000f;
8619
13.8k
      if (single)
8620
9.44k
        {
8621
9.44k
          regno <<= 1;
8622
9.44k
          regno += (given >> 22) & 1;
8623
9.44k
        }
8624
4.44k
      else
8625
4.44k
        regno += ((given >> 22) & 1) << 4;
8626
13.8k
      break;
8627
8628
7.85k
          case '2': /* Sn, Dn */
8629
7.85k
      regno = (given >> 16) & 0x0000000f;
8630
7.85k
      if (single)
8631
4.40k
        {
8632
4.40k
          regno <<= 1;
8633
4.40k
          regno += (given >> 7) & 1;
8634
4.40k
        }
8635
3.44k
      else
8636
3.44k
        regno += ((given >> 7) & 1) << 4;
8637
7.85k
      break;
8638
8639
3.71k
          case '3': /* List */
8640
3.71k
      func (stream, dis_style_text, "{");
8641
3.71k
      regno = (given >> 12) & 0x0000000f;
8642
3.71k
      if (single)
8643
2.51k
        {
8644
2.51k
          regno <<= 1;
8645
2.51k
          regno += (given >> 22) & 1;
8646
2.51k
        }
8647
1.20k
      else
8648
1.20k
        regno += ((given >> 22) & 1) << 4;
8649
3.71k
      break;
8650
8651
0
          default:
8652
0
      abort ();
8653
35.3k
          }
8654
8655
35.3k
        func (stream, dis_style_register, "%c%d",
8656
35.3k
        single ? 's' : 'd', regno);
8657
8658
35.3k
        if (*c == '3')
8659
3.71k
          {
8660
3.71k
      int count = given & 0xff;
8661
8662
3.71k
      if (single == 0)
8663
1.20k
        count >>= 1;
8664
8665
3.71k
      if (--count)
8666
3.33k
        {
8667
3.33k
          func (stream, dis_style_text, "-");
8668
3.33k
          func (stream, dis_style_register, "%c%d",
8669
3.33k
          single ? 's' : 'd',
8670
3.33k
          regno + count);
8671
3.33k
        }
8672
8673
3.71k
      func (stream, dis_style_text, "}");
8674
3.71k
          }
8675
31.6k
        else if (*c == '4')
8676
230
          {
8677
230
      func (stream, dis_style_text, ", ");
8678
230
      func (stream, dis_style_register, "%c%d",
8679
230
            single ? 's' : 'd', regno + 1);
8680
230
          }
8681
35.3k
      }
8682
0
      break;
8683
8684
1.94k
    case 'L':
8685
1.94k
      switch (given & 0x00400100)
8686
1.94k
        {
8687
356
        case 0x00000000:
8688
356
          func (stream, dis_style_mnemonic, "b");
8689
356
          break;
8690
320
        case 0x00400000:
8691
320
          func (stream, dis_style_mnemonic, "h");
8692
320
          break;
8693
713
        case 0x00000100:
8694
713
          func (stream, dis_style_mnemonic, "w");
8695
713
          break;
8696
560
        case 0x00400100:
8697
560
          func (stream, dis_style_mnemonic, "d");
8698
560
          break;
8699
0
        default:
8700
0
          break;
8701
1.94k
        }
8702
1.94k
      break;
8703
8704
1.94k
    case 'Z':
8705
220
      {
8706
        /* given (20, 23) | given (0, 3) */
8707
220
        value = ((given >> 16) & 0xf0) | (given & 0xf);
8708
220
        func (stream, dis_style_immediate, "%d", (int) value);
8709
220
      }
8710
220
      break;
8711
8712
1.94k
    case 'l':
8713
      /* This is like the 'A' operator, except that if
8714
         the width field "M" is zero, then the offset is
8715
         *not* multiplied by four.  */
8716
1.94k
      {
8717
1.94k
        int offset = given & 0xff;
8718
1.94k
        int multiplier = (given & 0x00000100) ? 4 : 1;
8719
8720
1.94k
        func (stream, dis_style_text, "[");
8721
1.94k
        func (stream, dis_style_register, "%s",
8722
1.94k
        arm_regnames [(given >> 16) & 0xf]);
8723
8724
1.94k
        if (multiplier > 1)
8725
1.27k
          {
8726
1.27k
      value_in_comment = offset * multiplier;
8727
1.27k
      if (NEGATIVE_BIT_SET)
8728
414
        value_in_comment = - value_in_comment;
8729
1.27k
          }
8730
8731
1.94k
        if (offset)
8732
1.43k
          {
8733
1.43k
      if (PRE_BIT_SET)
8734
847
        {
8735
847
          func (stream, dis_style_text, ", ");
8736
847
          func (stream, dis_style_immediate, "#%s%d",
8737
847
          NEGATIVE_BIT_SET ? "-" : "",
8738
847
          offset * multiplier);
8739
847
          func (stream, dis_style_text, "]%s",
8740
847
          WRITEBACK_BIT_SET ? "!" : "");
8741
847
        }
8742
584
      else
8743
584
        {
8744
584
          func (stream, dis_style_text, "], ");
8745
584
          func (stream, dis_style_immediate, "#%s%d",
8746
584
          NEGATIVE_BIT_SET ? "-" : "",
8747
584
          offset * multiplier);
8748
584
        }
8749
1.43k
          }
8750
518
        else
8751
518
          func (stream, dis_style_text, "]");
8752
1.94k
      }
8753
1.94k
      break;
8754
8755
3.51k
    case 'r':
8756
3.51k
      {
8757
3.51k
        int imm4 = (given >> 4) & 0xf;
8758
3.51k
        int puw_bits = ((given >> 22) & 6) | ((given >> W_BIT) & 1);
8759
3.51k
        int ubit = ! NEGATIVE_BIT_SET;
8760
3.51k
        const char *rm = arm_regnames [given & 0xf];
8761
3.51k
        const char *rn = arm_regnames [(given >> 16) & 0xf];
8762
8763
3.51k
        switch (puw_bits)
8764
3.51k
          {
8765
393
          case 1:
8766
1.55k
          case 3:
8767
1.55k
      func (stream, dis_style_text, "[");
8768
1.55k
      func (stream, dis_style_register, "%s", rn);
8769
1.55k
      func (stream, dis_style_text, "], ");
8770
1.55k
      func (stream, dis_style_text, "%c", ubit ? '+' : '-');
8771
1.55k
      func (stream, dis_style_register, "%s", rm);
8772
1.55k
      if (imm4)
8773
1.31k
        {
8774
1.31k
          func (stream, dis_style_text, ", ");
8775
1.31k
          func (stream, dis_style_sub_mnemonic, "lsl ");
8776
1.31k
          func (stream, dis_style_immediate, "#%d", imm4);
8777
1.31k
        }
8778
1.55k
      break;
8779
8780
310
          case 4:
8781
504
          case 5:
8782
700
          case 6:
8783
1.40k
          case 7:
8784
1.40k
      func (stream, dis_style_text, "[");
8785
1.40k
      func (stream, dis_style_register, "%s", rn);
8786
1.40k
      func (stream, dis_style_text, ", ");
8787
1.40k
      func (stream, dis_style_text, "%c", ubit ? '+' : '-');
8788
1.40k
      func (stream, dis_style_register, "%s", rm);
8789
1.40k
      if (imm4 > 0)
8790
1.04k
        {
8791
1.04k
          func (stream, dis_style_text, ", ");
8792
1.04k
          func (stream, dis_style_sub_mnemonic, "lsl ");
8793
1.04k
          func (stream, dis_style_immediate, "#%d", imm4);
8794
1.04k
        }
8795
1.40k
      func (stream, dis_style_text, "]");
8796
1.40k
      if (puw_bits == 5 || puw_bits == 7)
8797
897
        func (stream, dis_style_text, "!");
8798
1.40k
      break;
8799
8800
552
          default:
8801
552
      func (stream, dis_style_text, "INVALID");
8802
3.51k
          }
8803
3.51k
      }
8804
3.51k
      break;
8805
8806
3.51k
    case 'i':
8807
395
      {
8808
395
        long imm5;
8809
395
        imm5 = ((given & 0x100) >> 4) | (given & 0xf);
8810
395
        func (stream, dis_style_immediate, "%ld",
8811
395
        (imm5 == 0) ? 32 : imm5);
8812
395
      }
8813
395
      break;
8814
8815
0
    default:
8816
0
      abort ();
8817
3.85M
    }
8818
3.85M
      }
8819
4.76M
    else
8820
4.76M
      {
8821
4.76M
        if (*c == '@')
8822
1.20k
    base_style = dis_style_comment_start;
8823
8824
4.76M
        if (*c == '\t')
8825
349k
    base_style = dis_style_text;
8826
8827
4.76M
        func (stream, base_style, "%c", *c);
8828
4.76M
      }
8829
8.62M
  }
8830
8831
348k
      if (value_in_comment > 32 || value_in_comment < -16)
8832
131k
  func (stream, dis_style_comment_start, "\t@ 0x%lx",
8833
131k
        (value_in_comment & 0xffffffffUL));
8834
8835
348k
      if (is_unpredictable)
8836
12.8k
  func (stream, dis_style_comment_start, UNPREDICTABLE_INSTRUCTION);
8837
8838
348k
      return true;
8839
348k
    }
8840
7.21M
  return false;
8841
7.56M
}
8842
8843
static bool
8844
print_insn_coprocessor (bfd_vma pc,
8845
      struct disassemble_info *info,
8846
      long given,
8847
      bool thumb)
8848
3.90M
{
8849
3.90M
  return print_insn_coprocessor_1 (coprocessor_opcodes,
8850
3.90M
           pc, info, given, thumb);
8851
3.90M
}
8852
8853
static bool
8854
print_insn_generic_coprocessor (bfd_vma pc,
8855
        struct disassemble_info *info,
8856
        long given,
8857
        bool thumb)
8858
3.66M
{
8859
3.66M
  return print_insn_coprocessor_1 (generic_coprocessor_opcodes,
8860
3.66M
           pc, info, given, thumb);
8861
3.66M
}
8862
8863
/* Decodes and prints ARM addressing modes.  Returns the offset
8864
   used in the address, if any, if it is worthwhile printing the
8865
   offset as a hexadecimal value in a comment at the end of the
8866
   line of disassembly.  */
8867
8868
static signed long
8869
print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
8870
375k
{
8871
375k
  void *stream = info->stream;
8872
375k
  fprintf_styled_ftype func = info->fprintf_styled_func;
8873
375k
  bfd_vma offset = 0;
8874
8875
375k
  if (((given & 0x000f0000) == 0x000f0000)
8876
375k
      && ((given & 0x02000000) == 0))
8877
20.0k
    {
8878
20.0k
      offset = given & 0xfff;
8879
8880
20.0k
      func (stream, dis_style_text, "[");
8881
20.0k
      func (stream, dis_style_register, "pc");
8882
8883
20.0k
      if (PRE_BIT_SET)
8884
9.57k
  {
8885
    /* Pre-indexed.  Elide offset of positive zero when
8886
       non-writeback.  */
8887
9.57k
    if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
8888
8.73k
      {
8889
8.73k
        func (stream, dis_style_text, ", ");
8890
8.73k
        func (stream, dis_style_immediate, "#%s%d",
8891
8.73k
        NEGATIVE_BIT_SET ? "-" : "", (int) offset);
8892
8.73k
      }
8893
8894
9.57k
    if (NEGATIVE_BIT_SET)
8895
3.83k
      offset = -offset;
8896
8897
9.57k
    offset += pc + 8;
8898
8899
    /* Cope with the possibility of write-back
8900
       being used.  Probably a very dangerous thing
8901
       for the programmer to do, but who are we to
8902
       argue ?  */
8903
9.57k
    func (stream, dis_style_text, "]%s", WRITEBACK_BIT_SET ? "!" : "");
8904
9.57k
  }
8905
10.4k
      else  /* Post indexed.  */
8906
10.4k
  {
8907
10.4k
    func (stream, dis_style_text, "], ");
8908
10.4k
    func (stream, dis_style_immediate, "#%s%d",
8909
10.4k
    NEGATIVE_BIT_SET ? "-" : "", (int) offset);
8910
8911
    /* Ie ignore the offset.  */
8912
10.4k
    offset = pc + 8;
8913
10.4k
  }
8914
8915
20.0k
      func (stream, dis_style_comment_start, "\t@ ");
8916
20.0k
      info->print_address_func (offset, info);
8917
20.0k
      offset = 0;
8918
20.0k
    }
8919
355k
  else
8920
355k
    {
8921
355k
      func (stream, dis_style_text, "[");
8922
355k
      func (stream, dis_style_register, "%s",
8923
355k
      arm_regnames[(given >> 16) & 0xf]);
8924
8925
355k
      if (PRE_BIT_SET)
8926
170k
  {
8927
170k
    if ((given & 0x02000000) == 0)
8928
123k
      {
8929
        /* Elide offset of positive zero when non-writeback.  */
8930
123k
        offset = given & 0xfff;
8931
123k
        if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
8932
119k
    {
8933
119k
      func (stream, dis_style_text, ", ");
8934
119k
      func (stream, dis_style_immediate, "#%s%d",
8935
119k
      NEGATIVE_BIT_SET ? "-" : "", (int) offset);
8936
119k
    }
8937
123k
      }
8938
47.3k
    else
8939
47.3k
      {
8940
47.3k
        func (stream, dis_style_text, ", %s",
8941
47.3k
        NEGATIVE_BIT_SET ? "-" : "");
8942
47.3k
        arm_decode_shift (given, func, stream, true);
8943
47.3k
      }
8944
8945
170k
    func (stream, dis_style_text, "]%s",
8946
170k
    WRITEBACK_BIT_SET ? "!" : "");
8947
170k
  }
8948
184k
      else
8949
184k
  {
8950
184k
    if ((given & 0x02000000) == 0)
8951
130k
      {
8952
        /* Always show offset.  */
8953
130k
        offset = given & 0xfff;
8954
130k
        func (stream, dis_style_text, "], ");
8955
130k
        func (stream, dis_style_immediate, "#%s%d",
8956
130k
        NEGATIVE_BIT_SET ? "-" : "", (int) offset);
8957
130k
      }
8958
54.3k
    else
8959
54.3k
      {
8960
54.3k
        func (stream, dis_style_text, "], %s",
8961
54.3k
        NEGATIVE_BIT_SET ? "-" : "");
8962
54.3k
        arm_decode_shift (given, func, stream, true);
8963
54.3k
      }
8964
184k
  }
8965
355k
      if (NEGATIVE_BIT_SET)
8966
251k
  offset = -offset;
8967
355k
    }
8968
8969
375k
  return (signed long) offset;
8970
375k
}
8971
8972
8973
/* Print one cde instruction on INFO->STREAM.
8974
   Return TRUE if the instuction matched, FALSE if this is not a
8975
   recognised cde instruction.  */
8976
static bool
8977
print_insn_cde (struct disassemble_info *info, long given, bool thumb)
8978
260k
{
8979
260k
  const struct cdeopcode32 *insn;
8980
260k
  void *stream = info->stream;
8981
260k
  fprintf_styled_ftype func = info->fprintf_styled_func;
8982
260k
  enum disassembler_style base_style = dis_style_mnemonic;
8983
260k
  enum disassembler_style old_base_style = base_style;
8984
8985
260k
  if (thumb)
8986
260k
  {
8987
    /* Manually extract the coprocessor code from a known point.
8988
       This position is the same across all CDE instructions.  */
8989
3.24M
    for (insn = cde_opcodes; insn->assembler; insn++)
8990
3.00M
    {
8991
3.00M
      uint16_t coproc = (given >> insn->coproc_shift) & insn->coproc_mask;
8992
3.00M
      uint16_t coproc_mask = 1 << coproc;
8993
3.00M
      if (! (coproc_mask & cde_coprocs))
8994
1.51M
  continue;
8995
8996
1.48M
      if ((given & insn->mask) == insn->value)
8997
21.6k
      {
8998
21.6k
  bool is_unpredictable = false;
8999
21.6k
  const char *c;
9000
9001
470k
  for (c = insn->assembler; *c; c++)
9002
448k
  {
9003
448k
    if (*c == '%')
9004
166k
    {
9005
166k
      switch (*++c)
9006
166k
      {
9007
21.6k
        case '{':
9008
21.6k
    ++c;
9009
21.6k
    if (*c == '\0')
9010
0
      abort ();
9011
21.6k
    old_base_style = base_style;
9012
21.6k
    base_style = decode_base_style (*c);
9013
21.6k
    ++c;
9014
21.6k
    if (*c != ':')
9015
0
      abort ();
9016
21.6k
    break;
9017
9018
21.6k
        case '}':
9019
21.6k
    base_style = old_base_style;
9020
21.6k
    break;
9021
9022
0
        case '%':
9023
0
    func (stream, base_style, "%%");
9024
0
    break;
9025
9026
79.7k
        case '0': case '1': case '2': case '3': case '4':
9027
79.7k
        case '5': case '6': case '7': case '8': case '9':
9028
79.7k
        {
9029
79.7k
    int width;
9030
79.7k
    unsigned long value;
9031
9032
79.7k
    c = arm_decode_bitfield (c, given, &value, &width);
9033
9034
79.7k
    switch (*c)
9035
79.7k
    {
9036
6.52k
      case 'S':
9037
6.52k
        if (value > 10)
9038
4.43k
          is_unpredictable = true;
9039
        /* Fall through.  */
9040
6.52k
      case 'R':
9041
6.52k
        if (value == 13)
9042
1.13k
          is_unpredictable = true;
9043
        /* Fall through.  */
9044
6.52k
      case 'r':
9045
6.52k
        func (stream, dis_style_register, "%s",
9046
6.52k
        arm_regnames[value]);
9047
6.52k
        break;
9048
9049
25.4k
      case 'n':
9050
25.4k
        if (value == 15)
9051
2.35k
          func (stream, dis_style_register, "%s", "APSR_nzcv");
9052
23.0k
        else
9053
23.0k
          func (stream, dis_style_register, "%s",
9054
23.0k
          arm_regnames[value]);
9055
25.4k
        break;
9056
9057
6.52k
      case 'T':
9058
6.52k
        func (stream, dis_style_register, "%s",
9059
6.52k
        arm_regnames[(value + 1) & 15]);
9060
6.52k
        break;
9061
9062
21.6k
      case 'd':
9063
21.6k
        func (stream, dis_style_immediate, "%ld", value);
9064
21.6k
        break;
9065
9066
19.6k
      case 'V':
9067
19.6k
        if (given & (1 << 6))
9068
10.1k
          func (stream, dis_style_register, "q%ld", value >> 1);
9069
9.49k
        else if (given & (1 << 24))
9070
2.95k
          func (stream, dis_style_register, "d%ld", value);
9071
6.54k
        else
9072
6.54k
          {
9073
      /* Encoding for S register is different than for D and
9074
         Q registers.  S registers are encoded using the top
9075
         single bit in position 22 as the lowest bit of the
9076
         register number, while for Q and D it represents the
9077
         highest bit of the register number.  */
9078
6.54k
      uint8_t top_bit = (value >> 4) & 1;
9079
6.54k
      uint8_t tmp = (value << 1) & 0x1e;
9080
6.54k
      uint8_t res = tmp | top_bit;
9081
6.54k
      func (stream, dis_style_register, "s%u", res);
9082
6.54k
          }
9083
19.6k
        break;
9084
9085
0
    default:
9086
0
      abort ();
9087
79.7k
    }
9088
79.7k
        }
9089
79.7k
      break;
9090
9091
79.7k
      case 'p':
9092
21.6k
        {
9093
21.6k
    uint8_t proc_number = (given >> 8) & 0x7;
9094
21.6k
    func (stream, dis_style_register, "p%u", proc_number);
9095
21.6k
    break;
9096
79.7k
        }
9097
9098
21.6k
      case 'a':
9099
21.6k
        {
9100
21.6k
    uint8_t a_offset = 28;
9101
21.6k
    if (given & (1 << a_offset))
9102
9.13k
      func (stream, dis_style_mnemonic, "a");
9103
21.6k
    break;
9104
79.7k
        }
9105
0
    default:
9106
0
      abort ();
9107
166k
    }
9108
166k
  }
9109
282k
  else
9110
282k
    {
9111
282k
      if (*c == '@')
9112
0
        base_style = dis_style_comment_start;
9113
282k
      if (*c == '\t')
9114
21.6k
        base_style = dis_style_text;
9115
9116
282k
      func (stream, base_style, "%c", *c);
9117
282k
    }
9118
448k
      }
9119
9120
21.6k
      if (is_unpredictable)
9121
4.43k
  func (stream, dis_style_comment_start, UNPREDICTABLE_INSTRUCTION);
9122
9123
21.6k
      return true;
9124
21.6k
      }
9125
1.48M
    }
9126
238k
    return false;
9127
260k
  }
9128
0
  else
9129
0
    return false;
9130
260k
}
9131
9132
9133
/* Print one neon instruction on INFO->STREAM.
9134
   Return TRUE if the instuction matched, FALSE if this is not a
9135
   recognised neon instruction.  */
9136
9137
static bool
9138
print_insn_neon (struct disassemble_info *info, long given, bool thumb)
9139
3.53M
{
9140
3.53M
  const struct opcode32 *insn;
9141
3.53M
  void *stream = info->stream;
9142
3.53M
  fprintf_styled_ftype func = info->fprintf_styled_func;
9143
3.53M
  enum disassembler_style base_style = dis_style_mnemonic;
9144
3.53M
  enum disassembler_style old_base_style = base_style;
9145
9146
3.53M
  if (thumb)
9147
85.9k
    {
9148
85.9k
      if ((given & 0xef000000) == 0xef000000)
9149
15.0k
  {
9150
    /* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding.  */
9151
15.0k
    unsigned long bit28 = given & (1 << 28);
9152
9153
15.0k
    given &= 0x00ffffff;
9154
15.0k
    if (bit28)
9155
12.6k
            given |= 0xf3000000;
9156
2.43k
          else
9157
2.43k
      given |= 0xf2000000;
9158
15.0k
  }
9159
70.8k
      else if ((given & 0xff000000) == 0xf9000000)
9160
7.85k
  given ^= 0xf9000000 ^ 0xf4000000;
9161
      /* BFloat16 neon instructions without special top byte handling.  */
9162
63.0k
      else if ((given & 0xff000000) == 0xfe000000
9163
63.0k
         || (given & 0xff000000) == 0xfc000000)
9164
5.03k
  ;
9165
      /* vdup is also a valid neon instruction.  */
9166
58.0k
      else if ((given & 0xff900f5f) != 0xee800b10)
9167
57.7k
  return false;
9168
85.9k
    }
9169
9170
1.05G
  for (insn = neon_opcodes; insn->assembler; insn++)
9171
1.04G
    {
9172
1.04G
      unsigned long cond_mask = insn->mask;
9173
1.04G
      unsigned long cond_value = insn->value;
9174
1.04G
      int cond;
9175
9176
1.04G
      if (thumb)
9177
6.97M
        {
9178
6.97M
          if ((cond_mask & 0xf0000000) == 0) {
9179
              /* For the entries in neon_opcodes, an opcode mask/value with
9180
                 the high 4 bits equal to 0 indicates a conditional
9181
                 instruction. For thumb however, we need to include those
9182
                 bits in the instruction matching.  */
9183
168k
              cond_mask |= 0xf0000000;
9184
              /* Furthermore, the thumb encoding of a conditional instruction
9185
                 will have the high 4 bits equal to 0xe.  */
9186
168k
              cond_value |= 0xe0000000;
9187
168k
          }
9188
6.97M
          if (ifthen_state)
9189
145k
            cond = IFTHEN_COND;
9190
6.83M
          else
9191
6.83M
            cond = COND_UNCOND;
9192
6.97M
        }
9193
1.04G
      else
9194
1.04G
        {
9195
1.04G
          if ((given & 0xf0000000) == 0xf0000000)
9196
72.3M
            {
9197
              /* If the instruction is unconditional, update the mask to only
9198
                 match against unconditional opcode values.  */
9199
72.3M
              cond_mask |= 0xf0000000;
9200
72.3M
              cond = COND_UNCOND;
9201
72.3M
            }
9202
969M
          else
9203
969M
            {
9204
969M
              cond = (given >> 28) & 0xf;
9205
969M
              if (cond == 0xe)
9206
45.0M
                cond = COND_UNCOND;
9207
969M
            }
9208
1.04G
        }
9209
9210
1.04G
      if ((given & cond_mask) == cond_value)
9211
45.4k
  {
9212
45.4k
    signed long value_in_comment = 0;
9213
45.4k
    bool is_unpredictable = false;
9214
45.4k
    const char *c;
9215
9216
709k
    for (c = insn->assembler; *c; c++)
9217
667k
      {
9218
667k
        if (*c == '%')
9219
233k
    {
9220
233k
      switch (*++c)
9221
233k
        {
9222
7.42k
        case '{':
9223
7.42k
          ++c;
9224
7.42k
          if (*c == '\0')
9225
0
      abort ();
9226
7.42k
          old_base_style = base_style;
9227
7.42k
          base_style = decode_base_style (*c);
9228
7.42k
          ++c;
9229
7.42k
          if (*c != ':')
9230
0
      abort ();
9231
7.42k
          break;
9232
9233
7.42k
        case '}':
9234
7.42k
          base_style = old_base_style;
9235
7.42k
          break;
9236
9237
0
        case '%':
9238
0
          func (stream, base_style, "%%");
9239
0
          break;
9240
9241
1.62k
        case 'u':
9242
1.62k
          if (thumb && ifthen_state)
9243
196
      is_unpredictable = true;
9244
9245
          /* Fall through.  */
9246
44.7k
        case 'c':
9247
44.7k
          func (stream, dis_style_mnemonic, "%s",
9248
44.7k
          arm_conditional[cond]);
9249
44.7k
          break;
9250
9251
4.59k
        case 'A':
9252
4.59k
          {
9253
4.59k
      static const unsigned char enc[16] =
9254
4.59k
      {
9255
4.59k
        0x4, 0x14, /* st4 0,1 */
9256
4.59k
        0x4, /* st1 2 */
9257
4.59k
        0x4, /* st2 3 */
9258
4.59k
        0x3, /* st3 4 */
9259
4.59k
        0x13, /* st3 5 */
9260
4.59k
        0x3, /* st1 6 */
9261
4.59k
        0x1, /* st1 7 */
9262
4.59k
        0x2, /* st2 8 */
9263
4.59k
        0x12, /* st2 9 */
9264
4.59k
        0x2, /* st1 10 */
9265
4.59k
        0, 0, 0, 0, 0
9266
4.59k
      };
9267
4.59k
      int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
9268
4.59k
      int rn = ((given >> 16) & 0xf);
9269
4.59k
      int rm = ((given >> 0) & 0xf);
9270
4.59k
      int align = ((given >> 4) & 0x3);
9271
4.59k
      int type = ((given >> 8) & 0xf);
9272
4.59k
      int n = enc[type] & 0xf;
9273
4.59k
      int stride = (enc[type] >> 4) + 1;
9274
4.59k
      int ix;
9275
9276
4.59k
      func (stream, dis_style_text, "{");
9277
4.59k
      if (stride > 1)
9278
5.78k
        for (ix = 0; ix != n; ix++)
9279
4.42k
          {
9280
4.42k
            if (ix > 0)
9281
3.07k
        func (stream, dis_style_text, ",");
9282
4.42k
            func (stream, dis_style_register, "d%d",
9283
4.42k
            rd + ix * stride);
9284
4.42k
          }
9285
3.23k
      else if (n == 1)
9286
476
        func (stream, dis_style_register, "d%d", rd);
9287
2.76k
      else
9288
2.76k
        {
9289
2.76k
          func (stream, dis_style_register, "d%d", rd);
9290
2.76k
          func (stream, dis_style_text, "-");
9291
2.76k
          func (stream, dis_style_register, "d%d",
9292
2.76k
          rd + n - 1);
9293
2.76k
        }
9294
4.59k
      func (stream, dis_style_text, "}, [");
9295
4.59k
      func (stream, dis_style_register, "%s",
9296
4.59k
            arm_regnames[rn]);
9297
4.59k
      if (align)
9298
2.56k
        {
9299
2.56k
          func (stream, dis_style_text, " :");
9300
2.56k
          func (stream, dis_style_immediate, "%d",
9301
2.56k
          32 << align);
9302
2.56k
        }
9303
4.59k
      func (stream, dis_style_text, "]");
9304
4.59k
      if (rm == 0xd)
9305
304
        func (stream, dis_style_text, "!");
9306
4.28k
      else if (rm != 0xf)
9307
3.51k
        {
9308
3.51k
          func (stream, dis_style_text, ", ");
9309
3.51k
          func (stream, dis_style_register, "%s",
9310
3.51k
          arm_regnames[rm]);
9311
3.51k
        }
9312
4.59k
          }
9313
4.59k
          break;
9314
9315
8.50k
        case 'B':
9316
8.50k
          {
9317
8.50k
      int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
9318
8.50k
      int rn = ((given >> 16) & 0xf);
9319
8.50k
      int rm = ((given >> 0) & 0xf);
9320
8.50k
      int idx_align = ((given >> 4) & 0xf);
9321
8.50k
                        int align = 0;
9322
8.50k
      int size = ((given >> 10) & 0x3);
9323
8.50k
      int idx = idx_align >> (size + 1);
9324
8.50k
                        int length = ((given >> 8) & 3) + 1;
9325
8.50k
                        int stride = 1;
9326
8.50k
                        int i;
9327
9328
8.50k
                        if (length > 1 && size > 0)
9329
4.66k
                          stride = (idx_align & (1 << size)) ? 2 : 1;
9330
9331
8.50k
                        switch (length)
9332
8.50k
                          {
9333
2.88k
                          case 1:
9334
2.88k
                            {
9335
2.88k
                              int amask = (1 << size) - 1;
9336
2.88k
                              if ((idx_align & (1 << size)) != 0)
9337
1.34k
                                return false;
9338
1.54k
                              if (size > 0)
9339
961
                                {
9340
961
                                  if ((idx_align & amask) == amask)
9341
230
                                    align = 8 << size;
9342
731
                                  else if ((idx_align & amask) != 0)
9343
231
                                    return false;
9344
961
                                }
9345
1.54k
                              }
9346
1.30k
                            break;
9347
9348
1.62k
                          case 2:
9349
1.62k
                            if (size == 2 && (idx_align & 2) != 0)
9350
247
                              return false;
9351
1.38k
                            align = (idx_align & 1) ? 16 << size : 0;
9352
1.38k
                            break;
9353
9354
1.83k
                          case 3:
9355
1.83k
                            if ((size == 2 && (idx_align & 3) != 0)
9356
1.83k
                                || (idx_align & 1) != 0)
9357
1.09k
                              return false;
9358
732
                            break;
9359
9360
2.16k
                          case 4:
9361
2.16k
                            if (size == 2)
9362
597
                              {
9363
597
                                if ((idx_align & 3) == 3)
9364
245
                                  return false;
9365
352
                                align = (idx_align & 3) * 64;
9366
352
                              }
9367
1.56k
                            else
9368
1.56k
                              align = (idx_align & 1) ? 32 << size : 0;
9369
1.92k
                            break;
9370
9371
1.92k
                          default:
9372
0
                            abort ();
9373
8.50k
                          }
9374
9375
5.34k
      func (stream, dis_style_text, "{");
9376
19.2k
                        for (i = 0; i < length; i++)
9377
13.9k
        {
9378
13.9k
          if (i > 0)
9379
8.60k
            func (stream, dis_style_text, ",");
9380
13.9k
          func (stream, dis_style_register, "d%d[%d]",
9381
13.9k
          rd + i * stride, idx);
9382
13.9k
        }
9383
5.34k
      func (stream, dis_style_text, "}, [");
9384
5.34k
      func (stream, dis_style_register, "%s",
9385
5.34k
            arm_regnames[rn]);
9386
5.34k
      if (align)
9387
1.95k
        {
9388
1.95k
          func (stream, dis_style_text, " :");
9389
1.95k
          func (stream, dis_style_immediate, "%d", align);
9390
1.95k
        }
9391
5.34k
      func (stream, dis_style_text, "]");
9392
5.34k
      if (rm == 0xd)
9393
355
        func (stream, dis_style_text, "!");
9394
4.98k
      else if (rm != 0xf)
9395
3.75k
        {
9396
3.75k
          func (stream, dis_style_text, ", ");
9397
3.75k
          func (stream, dis_style_register, "%s",
9398
3.75k
          arm_regnames[rm]);
9399
3.75k
        }
9400
5.34k
          }
9401
0
          break;
9402
9403
3.08k
        case 'C':
9404
3.08k
          {
9405
3.08k
      int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
9406
3.08k
      int rn = ((given >> 16) & 0xf);
9407
3.08k
      int rm = ((given >> 0) & 0xf);
9408
3.08k
      int align = ((given >> 4) & 0x1);
9409
3.08k
      int size = ((given >> 6) & 0x3);
9410
3.08k
      int type = ((given >> 8) & 0x3);
9411
3.08k
      int n = type + 1;
9412
3.08k
      int stride = ((given >> 5) & 0x1);
9413
3.08k
      int ix;
9414
9415
3.08k
      if (stride && (n == 1))
9416
653
        n++;
9417
2.43k
      else
9418
2.43k
        stride++;
9419
9420
3.08k
      func (stream, dis_style_text, "{");
9421
3.08k
      if (stride > 1)
9422
7.51k
        for (ix = 0; ix != n; ix++)
9423
5.85k
          {
9424
5.85k
            if (ix > 0)
9425
4.19k
        func (stream, dis_style_text, ",");
9426
5.85k
            func (stream, dis_style_register, "d%d[]",
9427
5.85k
            rd + ix * stride);
9428
5.85k
          }
9429
1.42k
      else if (n == 1)
9430
233
        func (stream, dis_style_register, "d%d[]", rd);
9431
1.19k
      else
9432
1.19k
        {
9433
1.19k
          func (stream, dis_style_register, "d%d[]", rd);
9434
1.19k
          func (stream, dis_style_text, "-");
9435
1.19k
          func (stream, dis_style_register, "d%d[]",
9436
1.19k
          rd + n - 1);
9437
1.19k
        }
9438
3.08k
      func (stream, dis_style_text, "}, [");
9439
3.08k
      func (stream, dis_style_register, "%s",
9440
3.08k
            arm_regnames[rn]);
9441
3.08k
      if (align)
9442
1.99k
        {
9443
1.99k
                            align = (8 * (type + 1)) << size;
9444
1.99k
                            if (type == 3)
9445
932
                              align = (size > 1) ? align >> 1 : align;
9446
1.99k
          if (type == 2 || (type == 0 && !size))
9447
734
            func (stream, dis_style_text,
9448
734
            " :<bad align %d>", align);
9449
1.25k
          else
9450
1.25k
            {
9451
1.25k
        func (stream, dis_style_text, " :");
9452
1.25k
        func (stream, dis_style_immediate,
9453
1.25k
              "%d", align);
9454
1.25k
            }
9455
1.99k
        }
9456
3.08k
      func (stream, dis_style_text, "]");
9457
3.08k
      if (rm == 0xd)
9458
473
        func (stream, dis_style_text, "!");
9459
2.61k
      else if (rm != 0xf)
9460
2.05k
        {
9461
2.05k
          func (stream, dis_style_text, ", ");
9462
2.05k
          func (stream, dis_style_register, "%s",
9463
2.05k
          arm_regnames[rm]);
9464
2.05k
        }
9465
3.08k
          }
9466
3.08k
          break;
9467
9468
2.15k
        case 'D':
9469
2.15k
          {
9470
2.15k
      int raw_reg = (given & 0xf) | ((given >> 1) & 0x10);
9471
2.15k
      int size = (given >> 20) & 3;
9472
2.15k
      int reg = raw_reg & ((4 << size) - 1);
9473
2.15k
      int ix = raw_reg >> size >> 2;
9474
9475
2.15k
      func (stream, dis_style_register, "d%d[%d]", reg, ix);
9476
2.15k
          }
9477
2.15k
          break;
9478
9479
2.76k
        case 'E':
9480
          /* Neon encoded constant for mov, mvn, vorr, vbic.  */
9481
2.76k
          {
9482
2.76k
      int bits = 0;
9483
2.76k
      int cmode = (given >> 8) & 0xf;
9484
2.76k
      int op = (given >> 5) & 0x1;
9485
2.76k
      unsigned long value = 0, hival = 0;
9486
2.76k
      unsigned shift;
9487
2.76k
                        int size = 0;
9488
2.76k
                        int isfloat = 0;
9489
9490
2.76k
      bits |= ((given >> 24) & 1) << 7;
9491
2.76k
      bits |= ((given >> 16) & 7) << 4;
9492
2.76k
      bits |= ((given >> 0) & 15) << 0;
9493
9494
2.76k
      if (cmode < 8)
9495
644
        {
9496
644
          shift = (cmode >> 1) & 3;
9497
644
          value = (unsigned long) bits << (8 * shift);
9498
644
                            size = 32;
9499
644
        }
9500
2.11k
      else if (cmode < 12)
9501
220
        {
9502
220
          shift = (cmode >> 1) & 1;
9503
220
          value = (unsigned long) bits << (8 * shift);
9504
220
                            size = 16;
9505
220
        }
9506
1.89k
      else if (cmode < 14)
9507
247
        {
9508
247
          shift = (cmode & 1) + 1;
9509
247
          value = (unsigned long) bits << (8 * shift);
9510
247
          value |= (1ul << (8 * shift)) - 1;
9511
247
                            size = 32;
9512
247
        }
9513
1.65k
      else if (cmode == 14)
9514
1.13k
        {
9515
1.13k
          if (op)
9516
732
            {
9517
        /* Bit replication into bytes.  */
9518
732
        int ix;
9519
732
        unsigned long mask;
9520
9521
732
        value = 0;
9522
732
                                hival = 0;
9523
6.58k
        for (ix = 7; ix >= 0; ix--)
9524
5.85k
          {
9525
5.85k
            mask = ((bits >> ix) & 1) ? 0xff : 0;
9526
5.85k
                                    if (ix <= 3)
9527
2.92k
              value = (value << 8) | mask;
9528
2.92k
                                    else
9529
2.92k
                                      hival = (hival << 8) | mask;
9530
5.85k
          }
9531
732
                                size = 64;
9532
732
            }
9533
399
                            else
9534
399
                              {
9535
                                /* Byte replication.  */
9536
399
                                value = (unsigned long) bits;
9537
399
                                size = 8;
9538
399
                              }
9539
1.13k
        }
9540
520
      else if (!op)
9541
520
        {
9542
          /* Floating point encoding.  */
9543
520
          int tmp;
9544
9545
520
          value = (unsigned long)  (bits & 0x7f) << 19;
9546
520
          value |= (unsigned long) (bits & 0x80) << 24;
9547
520
          tmp = bits & 0x40 ? 0x3c : 0x40;
9548
520
          value |= (unsigned long) tmp << 24;
9549
520
                            size = 32;
9550
520
                            isfloat = 1;
9551
520
        }
9552
0
      else
9553
0
        {
9554
0
          func (stream, dis_style_text,
9555
0
          "<illegal constant %.8x:%x:%x>",
9556
0
                                  bits, cmode, op);
9557
0
                            size = 32;
9558
0
          break;
9559
0
        }
9560
2.76k
                        switch (size)
9561
2.76k
                          {
9562
399
                          case 8:
9563
399
          func (stream, dis_style_immediate, "#%ld", value);
9564
399
          func (stream, dis_style_comment_start,
9565
399
          "\t@ 0x%.2lx", value);
9566
399
                            break;
9567
9568
220
                          case 16:
9569
220
          func (stream, dis_style_immediate, "#%ld", value);
9570
220
          func (stream, dis_style_comment_start,
9571
220
          "\t@ 0x%.4lx", value);
9572
220
                            break;
9573
9574
1.41k
                          case 32:
9575
1.41k
                            if (isfloat)
9576
520
                              {
9577
520
                                unsigned char valbytes[4];
9578
520
                                double fvalue;
9579
9580
                                /* Do this a byte at a time so we don't have to
9581
                                   worry about the host's endianness.  */
9582
520
                                valbytes[0] = value & 0xff;
9583
520
                                valbytes[1] = (value >> 8) & 0xff;
9584
520
                                valbytes[2] = (value >> 16) & 0xff;
9585
520
                                valbytes[3] = (value >> 24) & 0xff;
9586
9587
520
                                floatformat_to_double
9588
520
                                  (& floatformat_ieee_single_little, valbytes,
9589
520
                                  & fvalue);
9590
9591
520
        func (stream, dis_style_immediate,
9592
520
              "#%.7g", fvalue);
9593
520
        func (stream, dis_style_comment_start,
9594
520
              "\t@ 0x%.8lx", value);
9595
520
                              }
9596
891
                            else
9597
891
            {
9598
891
        func (stream, dis_style_immediate, "#%ld",
9599
891
              (long) (((value & 0x80000000L) != 0)
9600
891
                ? value | ~0xffffffffL : value));
9601
891
        func (stream, dis_style_comment_start,
9602
891
              "\t@ 0x%.8lx", value);
9603
891
            }
9604
1.41k
                            break;
9605
9606
732
                          case 64:
9607
732
          func (stream, dis_style_immediate,
9608
732
          "#0x%.8lx%.8lx", hival, value);
9609
732
                            break;
9610
9611
0
                          default:
9612
0
                            abort ();
9613
2.76k
                          }
9614
2.76k
          }
9615
2.76k
          break;
9616
9617
2.76k
        case 'F':
9618
1.31k
          {
9619
1.31k
      int regno = ((given >> 16) & 0xf) | ((given >> (7 - 4)) & 0x10);
9620
1.31k
      int num = (given >> 8) & 0x3;
9621
9622
1.31k
      func (stream, dis_style_text, "{");
9623
1.31k
      if (!num)
9624
260
        func (stream, dis_style_register, "d%d", regno);
9625
1.05k
      else if (num + regno >= 32)
9626
436
        {
9627
436
          func (stream, dis_style_register, "d%d", regno);
9628
436
          func (stream, dis_style_text, "-<overflow reg d%d",
9629
436
          regno + num);
9630
436
        }
9631
614
      else
9632
614
        {
9633
614
          func (stream, dis_style_register, "d%d", regno);
9634
614
          func (stream, dis_style_text, "-");
9635
614
          func (stream, dis_style_register, "d%d",
9636
614
          regno + num);
9637
614
        }
9638
1.31k
      func (stream, dis_style_text, "}");
9639
1.31k
          }
9640
1.31k
          break;
9641
9642
9643
141k
        case '0': case '1': case '2': case '3': case '4':
9644
151k
        case '5': case '6': case '7': case '8': case '9':
9645
151k
          {
9646
151k
      int width;
9647
151k
      unsigned long value;
9648
9649
151k
      c = arm_decode_bitfield (c, given, &value, &width);
9650
9651
151k
      switch (*c)
9652
151k
        {
9653
311
        case 'r':
9654
311
          func (stream, dis_style_register, "%s",
9655
311
          arm_regnames[value]);
9656
311
          break;
9657
2.84k
        case 'd':
9658
2.84k
          func (stream, base_style, "%ld", value);
9659
2.84k
          value_in_comment = value;
9660
2.84k
          break;
9661
4.88k
        case 'e':
9662
4.88k
          func (stream, dis_style_immediate, "%ld",
9663
4.88k
          (1ul << width) - value);
9664
4.88k
          break;
9665
9666
29.1k
        case 'S':
9667
30.0k
        case 'T':
9668
30.0k
        case 'U':
9669
          /* Various width encodings.  */
9670
30.0k
          {
9671
30.0k
            int base = 8 << (*c - 'S'); /* 8,16 or 32 */
9672
30.0k
            int limit;
9673
30.0k
            unsigned low, high;
9674
9675
30.0k
            c++;
9676
30.0k
            if (*c >= '0' && *c <= '9')
9677
29.2k
        limit = *c - '0';
9678
814
            else if (*c >= 'a' && *c <= 'f')
9679
814
        limit = *c - 'a' + 10;
9680
0
            else
9681
0
        abort ();
9682
30.0k
            low = limit >> 2;
9683
30.0k
            high = limit & 3;
9684
9685
30.0k
            if (value < low || value > high)
9686
6.56k
        func (stream, dis_style_text,
9687
6.56k
              "<illegal width %d>", base << value);
9688
23.4k
            else
9689
23.4k
        func (stream, base_style, "%d",
9690
23.4k
              base << value);
9691
30.0k
          }
9692
0
          break;
9693
49.2k
        case 'R':
9694
49.2k
          if (given & (1 << 6))
9695
28.7k
            goto Q;
9696
          /* FALLTHROUGH */
9697
32.4k
        case 'D':
9698
32.4k
          func (stream, dis_style_register, "d%ld", value);
9699
32.4k
          break;
9700
9.63k
        case 'Q':
9701
38.4k
        Q:
9702
38.4k
          if (value & 1)
9703
18.3k
            func (stream, dis_style_text,
9704
18.3k
            "<illegal reg q%ld.5>", value >> 1);
9705
20.0k
          else
9706
20.0k
            func (stream, dis_style_register,
9707
20.0k
            "q%ld", value >> 1);
9708
38.4k
          break;
9709
9710
0
        case '`':
9711
0
          c++;
9712
0
          if (value == 0)
9713
0
            func (stream, dis_style_text, "%c", *c);
9714
0
          break;
9715
0
        case '\'':
9716
0
          c++;
9717
0
          if (value == ((1ul << width) - 1))
9718
0
            func (stream, dis_style_text, "%c", *c);
9719
0
          break;
9720
42.3k
        case '?':
9721
42.3k
          func (stream, dis_style_mnemonic, "%c",
9722
42.3k
          c[(1 << width) - (int) value]);
9723
42.3k
          c += 1 << width;
9724
42.3k
          break;
9725
0
        default:
9726
0
          abort ();
9727
151k
        }
9728
151k
          }
9729
151k
          break;
9730
9731
151k
        default:
9732
0
          abort ();
9733
233k
        }
9734
233k
    }
9735
434k
        else
9736
434k
    {
9737
434k
      if (*c == '@')
9738
0
        base_style = dis_style_comment_start;
9739
9740
434k
      if (*c == '\t')
9741
45.4k
        base_style = dis_style_text;
9742
9743
434k
      func (stream, base_style, "%c", *c);
9744
9745
434k
    }
9746
667k
      }
9747
9748
42.2k
    if (value_in_comment > 32 || value_in_comment < -16)
9749
714
      func (stream, dis_style_comment_start, "\t@ 0x%lx",
9750
714
      value_in_comment);
9751
9752
42.2k
    if (is_unpredictable)
9753
196
      func (stream, dis_style_comment_start, UNPREDICTABLE_INSTRUCTION);
9754
9755
42.2k
    return true;
9756
45.4k
  }
9757
1.04G
    }
9758
3.43M
  return false;
9759
3.47M
}
9760
9761
/* Print one mve instruction on INFO->STREAM.
9762
   Return TRUE if the instuction matched, FALSE if this is not a
9763
   recognised mve instruction.  */
9764
9765
static bool
9766
print_insn_mve (struct disassemble_info *info, long given)
9767
308k
{
9768
308k
  const struct mopcode32 *insn;
9769
308k
  void *stream = info->stream;
9770
308k
  fprintf_styled_ftype func = info->fprintf_styled_func;
9771
308k
  enum disassembler_style base_style = dis_style_mnemonic;
9772
308k
  enum disassembler_style old_base_style = base_style;
9773
9774
57.2M
  for (insn = mve_opcodes; insn->assembler; insn++)
9775
57.0M
    {
9776
57.0M
      if (((given & insn->mask) == insn->value)
9777
57.0M
    && !is_mve_encoding_conflict (given, insn->mve_op))
9778
118k
  {
9779
118k
    signed long value_in_comment = 0;
9780
118k
    bool is_unpredictable = false;
9781
118k
    bool is_undefined = false;
9782
118k
    const char *c;
9783
118k
    enum mve_unpredictable unpredictable_cond = UNPRED_NONE;
9784
118k
    enum mve_undefined undefined_cond = UNDEF_NONE;
9785
9786
    /* Most vector mve instruction are illegal in a it block.
9787
       There are a few exceptions; check for them.  */
9788
118k
    if (ifthen_state && !is_mve_okay_in_it (insn->mve_op))
9789
1.63k
      {
9790
1.63k
        is_unpredictable = true;
9791
1.63k
        unpredictable_cond = UNPRED_IT_BLOCK;
9792
1.63k
      }
9793
116k
    else if (is_mve_unpredictable (given, insn->mve_op,
9794
116k
           &unpredictable_cond))
9795
23.7k
      is_unpredictable = true;
9796
9797
118k
    if (is_mve_undefined (given, insn->mve_op, &undefined_cond))
9798
12.7k
      is_undefined = true;
9799
9800
    /* In "VORR Qd, Qm, Qn", if Qm==Qn, VORR is nothing but VMOV,
9801
       i.e "VMOV Qd, Qm".  */
9802
118k
    if ((insn->mve_op == MVE_VORR_REG)
9803
118k
        && (arm_decode_field (given, 1, 3)
9804
663
      == arm_decode_field (given, 17, 19)))
9805
593
      continue;
9806
9807
2.08M
    for (c = insn->assembler; *c; c++)
9808
1.97M
      {
9809
1.97M
        if (*c == '%')
9810
642k
    {
9811
642k
      switch (*++c)
9812
642k
        {
9813
28.2k
        case '{':
9814
28.2k
          ++c;
9815
28.2k
          if (*c == '\0')
9816
0
      abort ();
9817
28.2k
          old_base_style = base_style;
9818
28.2k
          base_style = decode_base_style (*c);
9819
28.2k
          ++c;
9820
28.2k
          if (*c != ':')
9821
0
      abort ();
9822
28.2k
          break;
9823
9824
28.2k
        case '}':
9825
28.2k
          base_style = old_base_style;
9826
28.2k
          break;
9827
9828
0
        case '%':
9829
0
          func (stream, base_style, "%%");
9830
0
          break;
9831
9832
1.75k
        case 'a':
9833
          /* Don't print anything for '+' as it is implied.  */
9834
1.75k
          if (arm_decode_field (given, 23, 23) == 0)
9835
877
      func (stream, dis_style_immediate, "-");
9836
1.75k
          break;
9837
9838
14.8k
        case 'c':
9839
14.8k
          if (ifthen_state)
9840
6.04k
      func (stream, dis_style_mnemonic, "%s",
9841
6.04k
            arm_conditional[IFTHEN_COND]);
9842
14.8k
          break;
9843
9844
8.20k
        case 'd':
9845
8.20k
          print_mve_vld_str_addr (info, given, insn->mve_op);
9846
8.20k
          break;
9847
9848
10.5k
        case 'i':
9849
10.5k
          {
9850
10.5k
      long mve_mask = mve_extract_pred_mask (given);
9851
10.5k
      func (stream, dis_style_mnemonic, "%s",
9852
10.5k
            mve_predicatenames[mve_mask]);
9853
10.5k
          }
9854
10.5k
          break;
9855
9856
4.14k
        case 'j':
9857
4.14k
          {
9858
4.14k
      unsigned int imm5 = 0;
9859
4.14k
      imm5 |= arm_decode_field (given, 6, 7);
9860
4.14k
      imm5 |= (arm_decode_field (given, 12, 14) << 2);
9861
4.14k
      func (stream, dis_style_immediate, "#%u",
9862
4.14k
            (imm5 == 0) ? 32 : imm5);
9863
4.14k
          }
9864
4.14k
          break;
9865
9866
588
        case 'k':
9867
588
          func (stream, dis_style_immediate, "#%u",
9868
588
          (arm_decode_field (given, 7, 7) == 0) ? 64 : 48);
9869
588
          break;
9870
9871
12.1k
        case 'n':
9872
12.1k
          print_vec_condition (info, given, insn->mve_op);
9873
12.1k
          break;
9874
9875
3.86k
        case 'o':
9876
3.86k
          if (arm_decode_field (given, 0, 0) == 1)
9877
2.55k
      {
9878
2.55k
        unsigned long size
9879
2.55k
          = arm_decode_field (given, 4, 4)
9880
2.55k
            | (arm_decode_field (given, 6, 6) << 1);
9881
9882
2.55k
        func (stream, dis_style_text, ", ");
9883
2.55k
        func (stream, dis_style_sub_mnemonic, "uxtw ");
9884
2.55k
        func (stream, dis_style_immediate, "#%lu", size);
9885
2.55k
      }
9886
3.86k
          break;
9887
9888
3.57k
        case 'm':
9889
3.57k
          print_mve_rounding_mode (info, given, insn->mve_op);
9890
3.57k
          break;
9891
9892
6.89k
        case 's':
9893
6.89k
          print_mve_vcvt_size (info, given, insn->mve_op);
9894
6.89k
          break;
9895
9896
26.5k
        case 'u':
9897
26.5k
          {
9898
26.5k
      unsigned long op1 = arm_decode_field (given, 21, 22);
9899
9900
26.5k
      if ((insn->mve_op == MVE_VMOV_VEC_LANE_TO_GP))
9901
4.18k
        {
9902
          /* Check for signed.  */
9903
4.18k
          if (arm_decode_field (given, 23, 23) == 0)
9904
1.87k
            {
9905
        /* We don't print 's' for S32.  */
9906
1.87k
        if ((arm_decode_field (given, 5, 6) == 0)
9907
1.87k
            && ((op1 == 0) || (op1 == 1)))
9908
690
          ;
9909
1.18k
        else
9910
1.18k
          func (stream, dis_style_mnemonic, "s");
9911
1.87k
            }
9912
2.31k
          else
9913
2.31k
            func (stream, dis_style_mnemonic, "u");
9914
4.18k
        }
9915
22.3k
      else
9916
22.3k
        {
9917
22.3k
          if (arm_decode_field (given, 28, 28) == 0)
9918
11.9k
            func (stream, dis_style_mnemonic, "s");
9919
10.4k
          else
9920
10.4k
            func (stream, dis_style_mnemonic, "u");
9921
22.3k
        }
9922
26.5k
          }
9923
26.5k
          break;
9924
9925
86.4k
        case 'v':
9926
86.4k
          print_instruction_predicate (info);
9927
86.4k
          break;
9928
9929
2.77k
        case 'w':
9930
2.77k
          if (arm_decode_field (given, 21, 21) == 1)
9931
1.88k
      func (stream, dis_style_text, "!");
9932
2.77k
          break;
9933
9934
2.34k
        case 'B':
9935
2.34k
          print_mve_register_blocks (info, given, insn->mve_op);
9936
2.34k
          break;
9937
9938
7.98k
        case 'E':
9939
          /* SIMD encoded constant for mov, mvn, vorr, vbic.  */
9940
9941
7.98k
          print_simd_imm8 (info, given, 28, insn);
9942
7.98k
          break;
9943
9944
6.20k
        case 'N':
9945
6.20k
          print_mve_vmov_index (info, given);
9946
6.20k
          break;
9947
9948
8.98k
        case 'T':
9949
8.98k
          if (arm_decode_field (given, 12, 12) == 0)
9950
5.09k
      func (stream, dis_style_mnemonic, "b");
9951
3.88k
          else
9952
3.88k
      func (stream, dis_style_mnemonic, "t");
9953
8.98k
          break;
9954
9955
2.86k
        case 'X':
9956
2.86k
          if (arm_decode_field (given, 12, 12) == 1)
9957
847
      func (stream, dis_style_mnemonic, "x");
9958
2.86k
          break;
9959
9960
335k
        case '0': case '1': case '2': case '3': case '4':
9961
375k
        case '5': case '6': case '7': case '8': case '9':
9962
375k
          {
9963
375k
      int width;
9964
375k
      unsigned long value;
9965
9966
375k
      c = arm_decode_bitfield (c, given, &value, &width);
9967
9968
375k
      switch (*c)
9969
375k
        {
9970
10.0k
        case 'Z':
9971
10.0k
          if (value == 13)
9972
1.47k
            is_unpredictable = true;
9973
8.60k
          else if (value == 15)
9974
2.55k
            func (stream, dis_style_register, "zr");
9975
6.05k
          else
9976
6.05k
            func (stream, dis_style_register, "%s",
9977
6.05k
            arm_regnames[value]);
9978
10.0k
          break;
9979
9980
1.33k
        case 'c':
9981
1.33k
          func (stream, dis_style_sub_mnemonic, "%s",
9982
1.33k
          arm_conditional[value]);
9983
1.33k
          break;
9984
9985
1.86k
        case 'C':
9986
1.86k
          value ^= 1;
9987
1.86k
          func (stream, dis_style_sub_mnemonic, "%s",
9988
1.86k
          arm_conditional[value]);
9989
1.86k
          break;
9990
9991
7.54k
        case 'S':
9992
7.54k
          if (value == 13 || value == 15)
9993
1.65k
            is_unpredictable = true;
9994
5.88k
          else
9995
5.88k
            func (stream, dis_style_register, "%s",
9996
5.88k
            arm_regnames[value]);
9997
7.54k
          break;
9998
9999
86.3k
        case 's':
10000
86.3k
          print_mve_size (info,
10001
86.3k
              value,
10002
86.3k
              insn->mve_op);
10003
86.3k
          break;
10004
472
        case 'I':
10005
472
          if (value == 1)
10006
221
            func (stream, dis_style_mnemonic, "i");
10007
472
          break;
10008
4.20k
        case 'A':
10009
4.20k
          if (value == 1)
10010
1.24k
            func (stream, dis_style_mnemonic, "a");
10011
4.20k
          break;
10012
8.93k
        case 'h':
10013
8.93k
          {
10014
8.93k
            unsigned int odd_reg = (value << 1) | 1;
10015
8.93k
            func (stream, dis_style_register, "%s",
10016
8.93k
            arm_regnames[odd_reg]);
10017
8.93k
          }
10018
8.93k
          break;
10019
1.75k
        case 'i':
10020
1.75k
          {
10021
1.75k
            unsigned long imm
10022
1.75k
        = arm_decode_field (given, 0, 6);
10023
1.75k
            unsigned long mod_imm = imm;
10024
10025
1.75k
            switch (insn->mve_op)
10026
1.75k
        {
10027
796
        case MVE_VLDRW_GATHER_T5:
10028
1.02k
        case MVE_VSTRW_SCATTER_T5:
10029
1.02k
          mod_imm = mod_imm << 2;
10030
1.02k
          break;
10031
355
        case MVE_VSTRD_SCATTER_T6:
10032
722
        case MVE_VLDRD_GATHER_T6:
10033
722
          mod_imm = mod_imm << 3;
10034
722
          break;
10035
10036
0
        default:
10037
0
          break;
10038
1.75k
        }
10039
10040
1.75k
            func (stream, dis_style_immediate, "%lu",
10041
1.75k
            mod_imm);
10042
1.75k
          }
10043
0
          break;
10044
2.56k
        case 'k':
10045
2.56k
          func (stream, dis_style_immediate, "%lu",
10046
2.56k
          64 - value);
10047
2.56k
          break;
10048
11.3k
        case 'l':
10049
11.3k
          {
10050
11.3k
            unsigned int even_reg = value << 1;
10051
11.3k
            func (stream, dis_style_register, "%s",
10052
11.3k
            arm_regnames[even_reg]);
10053
11.3k
          }
10054
11.3k
          break;
10055
2.73k
        case 'u':
10056
2.73k
          switch (value)
10057
2.73k
            {
10058
205
            case 0:
10059
205
        func (stream, dis_style_immediate, "1");
10060
205
        break;
10061
773
            case 1:
10062
773
        func (stream, dis_style_immediate, "2");
10063
773
        break;
10064
1.15k
            case 2:
10065
1.15k
        func (stream, dis_style_immediate, "4");
10066
1.15k
        break;
10067
604
            case 3:
10068
604
        func (stream, dis_style_immediate, "8");
10069
604
        break;
10070
0
            default:
10071
0
        break;
10072
2.73k
            }
10073
2.73k
          break;
10074
3.50k
        case 'o':
10075
3.50k
          print_mve_rotate (info, value, width);
10076
3.50k
          break;
10077
36.0k
        case 'r':
10078
36.0k
          func (stream, dis_style_register, "%s",
10079
36.0k
          arm_regnames[value]);
10080
36.0k
          break;
10081
9.46k
        case 'd':
10082
9.46k
          if (mve_shift_insn_p (insn->mve_op))
10083
6.02k
            print_mve_shift_n (info, given, insn->mve_op);
10084
3.43k
          else if (insn->mve_op == MVE_VSHLL_T2)
10085
542
            {
10086
542
        switch (value)
10087
542
          {
10088
222
          case 0x00:
10089
222
            func (stream, dis_style_immediate, "8");
10090
222
            break;
10091
320
          case 0x01:
10092
320
            func (stream, dis_style_immediate, "16");
10093
320
            break;
10094
0
          case 0x10:
10095
0
            print_mve_undefined (info, UNDEF_SIZE_0);
10096
0
            break;
10097
0
          default:
10098
0
            assert (0);
10099
0
            break;
10100
542
          }
10101
542
            }
10102
2.89k
          else
10103
2.89k
            {
10104
2.89k
        if (insn->mve_op == MVE_VSHLC && value == 0)
10105
194
          value = 32;
10106
2.89k
        func (stream, base_style, "%ld", value);
10107
2.89k
        value_in_comment = value;
10108
2.89k
            }
10109
9.46k
          break;
10110
9.46k
        case 'F':
10111
197
          func (stream, dis_style_register, "s%ld", value);
10112
197
          break;
10113
187k
        case 'Q':
10114
187k
          if (value & 0x8)
10115
89.5k
            func (stream, dis_style_text,
10116
89.5k
            "<illegal reg q%ld.5>", value);
10117
97.4k
          else
10118
97.4k
            func (stream, dis_style_register, "q%ld", value);
10119
187k
          break;
10120
233
        case 'x':
10121
233
          func (stream, dis_style_immediate,
10122
233
          "0x%08lx", value);
10123
233
          break;
10124
0
        default:
10125
0
          abort ();
10126
375k
        }
10127
375k
      break;
10128
375k
          default:
10129
0
      abort ();
10130
375k
          }
10131
642k
        }
10132
642k
    }
10133
1.32M
        else
10134
1.32M
    {
10135
1.32M
      if (*c == '@')
10136
233
        base_style = dis_style_comment_start;
10137
10138
1.32M
      if (*c == '\t')
10139
117k
        base_style = dis_style_text;
10140
10141
1.32M
      func (stream, base_style, "%c", *c);
10142
1.32M
    }
10143
1.97M
      }
10144
10145
117k
    if (value_in_comment > 32 || value_in_comment < -16)
10146
0
      func (stream, dis_style_comment_start, "\t@ 0x%lx",
10147
0
      value_in_comment);
10148
10149
117k
    if (is_unpredictable)
10150
26.9k
      print_mve_unpredictable (info, unpredictable_cond);
10151
10152
117k
    if (is_undefined)
10153
12.7k
      print_mve_undefined (info, undefined_cond);
10154
10155
117k
    if (!vpt_block_state.in_vpt_block
10156
117k
        && !ifthen_state
10157
117k
        && is_vpt_instruction (given))
10158
3.60k
      mark_inside_vpt_block (given);
10159
114k
    else if (vpt_block_state.in_vpt_block)
10160
9.70k
      update_vpt_block_state ();
10161
10162
117k
    return true;
10163
117k
  }
10164
57.0M
    }
10165
190k
  return false;
10166
308k
}
10167
10168
10169
/* Return the name of a v7A special register.  */
10170
10171
static const char *
10172
banked_regname (unsigned reg)
10173
51.9k
{
10174
51.9k
  switch (reg)
10175
51.9k
    {
10176
348
      case 15: return "CPSR";
10177
480
      case 32: return "R8_usr";
10178
341
      case 33: return "R9_usr";
10179
1.00k
      case 34: return "R10_usr";
10180
489
      case 35: return "R11_usr";
10181
259
      case 36: return "R12_usr";
10182
272
      case 37: return "SP_usr";
10183
248
      case 38: return "LR_usr";
10184
217
      case 40: return "R8_fiq";
10185
349
      case 41: return "R9_fiq";
10186
274
      case 42: return "R10_fiq";
10187
289
      case 43: return "R11_fiq";
10188
267
      case 44: return "R12_fiq";
10189
335
      case 45: return "SP_fiq";
10190
262
      case 46: return "LR_fiq";
10191
333
      case 48: return "LR_irq";
10192
545
      case 49: return "SP_irq";
10193
285
      case 50: return "LR_svc";
10194
280
      case 51: return "SP_svc";
10195
240
      case 52: return "LR_abt";
10196
339
      case 53: return "SP_abt";
10197
347
      case 54: return "LR_und";
10198
292
      case 55: return "SP_und";
10199
394
      case 60: return "LR_mon";
10200
291
      case 61: return "SP_mon";
10201
347
      case 62: return "ELR_hyp";
10202
505
      case 63: return "SP_hyp";
10203
423
      case 79: return "SPSR";
10204
220
      case 110: return "SPSR_fiq";
10205
311
      case 112: return "SPSR_irq";
10206
358
      case 114: return "SPSR_svc";
10207
422
      case 116: return "SPSR_abt";
10208
592
      case 118: return "SPSR_und";
10209
362
      case 124: return "SPSR_mon";
10210
262
      case 126: return "SPSR_hyp";
10211
39.3k
      default: return NULL;
10212
51.9k
    }
10213
51.9k
}
10214
10215
/* Return the name of the DMB/DSB option.  */
10216
static const char *
10217
data_barrier_option (unsigned option)
10218
1.07k
{
10219
1.07k
  switch (option & 0xf)
10220
1.07k
    {
10221
13
    case 0xf: return "sy";
10222
274
    case 0xe: return "st";
10223
230
    case 0xd: return "ld";
10224
3
    case 0xb: return "ish";
10225
2
    case 0xa: return "ishst";
10226
7
    case 0x9: return "ishld";
10227
15
    case 0x7: return "un";
10228
6
    case 0x6: return "unst";
10229
14
    case 0x5: return "nshld";
10230
4
    case 0x3: return "osh";
10231
89
    case 0x2: return "oshst";
10232
6
    case 0x1: return "oshld";
10233
411
    default:  return NULL;
10234
1.07k
    }
10235
1.07k
}
10236
10237
/* Print one ARM instruction from PC on INFO->STREAM.  */
10238
10239
static void
10240
print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
10241
3.49M
{
10242
3.49M
  const struct opcode32 *insn;
10243
3.49M
  void *stream = info->stream;
10244
3.49M
  fprintf_styled_ftype func = info->fprintf_styled_func;
10245
3.49M
  struct arm_private_data *private_data = info->private_data;
10246
3.49M
  enum disassembler_style base_style = dis_style_mnemonic;
10247
3.49M
  enum disassembler_style old_base_style = base_style;
10248
10249
3.49M
  if (print_insn_coprocessor (pc, info, given, false))
10250
43.7k
    return;
10251
10252
3.44M
  if (print_insn_neon (info, given, false))
10253
26.3k
    return;
10254
10255
3.42M
  if (print_insn_generic_coprocessor (pc, info, given, false))
10256
266k
    return;
10257
10258
835M
  for (insn = arm_opcodes; insn->assembler; insn++)
10259
835M
    {
10260
835M
      if ((given & insn->mask) != insn->value)
10261
831M
  continue;
10262
10263
3.36M
      if (! ARM_CPU_HAS_FEATURE (insn->arch, private_data->features))
10264
53.7k
  continue;
10265
10266
      /* Special case: an instruction with all bits set in the condition field
10267
   (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
10268
   or by the catchall at the end of the table.  */
10269
3.31M
      if ((given & 0xF0000000) != 0xF0000000
10270
3.31M
    || (insn->mask & 0xF0000000) == 0xF0000000
10271
3.31M
    || (insn->mask == 0 && insn->value == 0))
10272
3.12M
  {
10273
3.12M
    unsigned long u_reg = 16;
10274
3.12M
    unsigned long U_reg = 16;
10275
3.12M
    bool is_unpredictable = false;
10276
3.12M
    signed long value_in_comment = 0;
10277
3.12M
    const char *c;
10278
10279
44.0M
    for (c = insn->assembler; *c; c++)
10280
40.8M
      {
10281
40.8M
        if (*c == '%')
10282
13.0M
    {
10283
13.0M
      bool allow_unpredictable = false;
10284
10285
13.0M
      switch (*++c)
10286
13.0M
        {
10287
13.0k
        case '{':
10288
13.0k
          ++c;
10289
13.0k
          if (*c == '\0')
10290
0
      abort ();
10291
13.0k
          old_base_style = base_style;
10292
13.0k
          base_style = decode_base_style (*c);
10293
13.0k
          ++c;
10294
13.0k
          if (*c != ':')
10295
0
      abort ();
10296
13.0k
          break;
10297
10298
13.0k
        case '}':
10299
13.0k
          base_style = old_base_style;
10300
13.0k
          break;
10301
10302
0
        case '%':
10303
0
          func (stream, base_style, "%%");
10304
0
          break;
10305
10306
375k
        case 'a':
10307
375k
          value_in_comment = print_arm_address (pc, info, given);
10308
375k
          break;
10309
10310
494
        case 'P':
10311
          /* Set P address bit and use normal address
10312
       printing routine.  */
10313
494
          value_in_comment = print_arm_address (pc, info, given | (1 << P_BIT));
10314
494
          break;
10315
10316
14.8k
        case 'S':
10317
14.8k
          allow_unpredictable = true;
10318
          /* Fall through.  */
10319
94.6k
        case 's':
10320
94.6k
                      if ((given & 0x004f0000) == 0x004f0000)
10321
8.29k
      {
10322
                          /* PC relative with immediate offset.  */
10323
8.29k
        bfd_vma offset = ((given & 0xf00) >> 4) | (given & 0xf);
10324
10325
8.29k
        if (PRE_BIT_SET)
10326
2.10k
          {
10327
            /* Elide positive zero offset.  */
10328
2.10k
            if (offset || NEGATIVE_BIT_SET)
10329
1.90k
        {
10330
1.90k
          func (stream, dis_style_text, "[");
10331
1.90k
          func (stream, dis_style_register, "pc");
10332
1.90k
          func (stream, dis_style_text, ", ");
10333
1.90k
          func (stream, dis_style_immediate, "#%s%d",
10334
1.90k
          (NEGATIVE_BIT_SET ? "-" : ""),
10335
1.90k
          (int) offset);
10336
1.90k
          func (stream, dis_style_text, "]");
10337
1.90k
        }
10338
202
            else
10339
202
        {
10340
202
          func (stream, dis_style_text, "[");
10341
202
          func (stream, dis_style_register, "pc");
10342
202
          func (stream, dis_style_text, "]");
10343
202
        }
10344
2.10k
            if (NEGATIVE_BIT_SET)
10345
622
        offset = -offset;
10346
2.10k
            func (stream, dis_style_comment_start, "\t@ ");
10347
2.10k
            info->print_address_func (offset + pc + 8, info);
10348
2.10k
          }
10349
6.19k
        else
10350
6.19k
          {
10351
            /* Always show the offset.  */
10352
6.19k
            func (stream, dis_style_text, "[");
10353
6.19k
            func (stream, dis_style_register, "pc");
10354
6.19k
            func (stream, dis_style_text, "], ");
10355
6.19k
            func (stream, dis_style_immediate, "#%s%d",
10356
6.19k
            NEGATIVE_BIT_SET ? "-" : "", (int) offset);
10357
6.19k
            if (! allow_unpredictable)
10358
950
        is_unpredictable = true;
10359
6.19k
          }
10360
8.29k
      }
10361
86.3k
          else
10362
86.3k
      {
10363
86.3k
        int offset = ((given & 0xf00) >> 4) | (given & 0xf);
10364
10365
86.3k
        func (stream, dis_style_text, "[");
10366
86.3k
        func (stream, dis_style_register, "%s",
10367
86.3k
        arm_regnames[(given >> 16) & 0xf]);
10368
10369
86.3k
        if (PRE_BIT_SET)
10370
13.0k
          {
10371
13.0k
            if (IMMEDIATE_BIT_SET)
10372
7.93k
        {
10373
          /* Elide offset for non-writeback
10374
             positive zero.  */
10375
7.93k
          if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET
10376
7.93k
              || offset)
10377
7.66k
            {
10378
7.66k
              func (stream, dis_style_text, ", ");
10379
7.66k
              func (stream, dis_style_immediate,
10380
7.66k
              "#%s%d",
10381
7.66k
              (NEGATIVE_BIT_SET ? "-" : ""),
10382
7.66k
              offset);
10383
7.66k
            }
10384
10385
7.93k
          if (NEGATIVE_BIT_SET)
10386
2.53k
            offset = -offset;
10387
10388
7.93k
          value_in_comment = offset;
10389
7.93k
        }
10390
5.14k
            else
10391
5.14k
        {
10392
          /* Register Offset or Register Pre-Indexed.  */
10393
5.14k
          func (stream, dis_style_text, ", %s",
10394
5.14k
          NEGATIVE_BIT_SET ? "-" : "");
10395
5.14k
          func (stream, dis_style_register, "%s",
10396
5.14k
          arm_regnames[given & 0xf]);
10397
10398
          /* Writing back to the register that is the source/
10399
             destination of the load/store is unpredictable.  */
10400
5.14k
          if (! allow_unpredictable
10401
5.14k
              && WRITEBACK_BIT_SET
10402
5.14k
              && ((given & 0xf) == ((given >> 12) & 0xf)))
10403
459
            is_unpredictable = true;
10404
5.14k
        }
10405
10406
13.0k
            func (stream, dis_style_text, "]%s",
10407
13.0k
            WRITEBACK_BIT_SET ? "!" : "");
10408
13.0k
          }
10409
73.2k
        else
10410
73.2k
          {
10411
73.2k
            if (IMMEDIATE_BIT_SET)
10412
15.1k
        {
10413
          /* Immediate Post-indexed.  */
10414
          /* PR 10924: Offset must be printed, even if it is zero.  */
10415
15.1k
          func (stream, dis_style_text, "], ");
10416
15.1k
          func (stream, dis_style_immediate, "#%s%d",
10417
15.1k
          NEGATIVE_BIT_SET ? "-" : "", offset);
10418
15.1k
          if (NEGATIVE_BIT_SET)
10419
5.92k
            offset = -offset;
10420
15.1k
          value_in_comment = offset;
10421
15.1k
        }
10422
58.1k
            else
10423
58.1k
        {
10424
          /* Register Post-indexed.  */
10425
58.1k
          func (stream, dis_style_text, "], %s",
10426
58.1k
          NEGATIVE_BIT_SET ? "-" : "");
10427
58.1k
          func (stream, dis_style_register, "%s",
10428
58.1k
          arm_regnames[given & 0xf]);
10429
10430
          /* Writing back to the register that is the source/
10431
             destination of the load/store is unpredictable.  */
10432
58.1k
          if (! allow_unpredictable
10433
58.1k
              && (given & 0xf) == ((given >> 12) & 0xf))
10434
9.81k
            is_unpredictable = true;
10435
58.1k
        }
10436
10437
73.2k
            if (! allow_unpredictable)
10438
63.7k
        {
10439
          /* Writeback is automatically implied by post- addressing.
10440
             Setting the W bit is unnecessary and ARM specify it as
10441
             being unpredictable.  */
10442
63.7k
          if (WRITEBACK_BIT_SET
10443
              /* Specifying the PC register as the post-indexed
10444
           registers is also unpredictable.  */
10445
63.7k
              || (! IMMEDIATE_BIT_SET && ((given & 0xf) == 0xf)))
10446
26.6k
            is_unpredictable = true;
10447
63.7k
        }
10448
73.2k
          }
10449
86.3k
      }
10450
94.6k
          break;
10451
10452
188k
        case 'b':
10453
188k
          {
10454
188k
      bfd_vma disp = (((given & 0xffffff) ^ 0x800000) - 0x800000);
10455
188k
      bfd_vma target = disp * 4 + pc + 8;
10456
188k
      info->print_address_func (target, info);
10457
10458
      /* Fill in instruction information.  */
10459
188k
      info->insn_info_valid = 1;
10460
188k
      info->insn_type = dis_branch;
10461
188k
      info->target = target;
10462
188k
          }
10463
188k
          break;
10464
10465
2.81M
        case 'c':
10466
2.81M
          if (((given >> 28) & 0xf) != 0xe)
10467
2.69M
      func (stream, dis_style_mnemonic, "%s",
10468
2.69M
            arm_conditional [(given >> 28) & 0xf]);
10469
2.81M
          break;
10470
10471
241k
        case 'm':
10472
241k
          {
10473
241k
      int started = 0;
10474
241k
      int reg;
10475
10476
241k
      func (stream, dis_style_text, "{");
10477
4.10M
      for (reg = 0; reg < 16; reg++)
10478
3.86M
        if ((given & (1 << reg)) != 0)
10479
1.42M
          {
10480
1.42M
            if (started)
10481
1.22M
        func (stream, dis_style_text, ", ");
10482
1.42M
            started = 1;
10483
1.42M
            func (stream, dis_style_register, "%s",
10484
1.42M
            arm_regnames[reg]);
10485
1.42M
          }
10486
241k
      func (stream, dis_style_text, "}");
10487
241k
      if (! started)
10488
34.6k
        is_unpredictable = true;
10489
241k
          }
10490
241k
          break;
10491
10492
2.10k
        case 'q':
10493
2.10k
          arm_decode_shift (given, func, stream, false);
10494
2.10k
          break;
10495
10496
1.62M
        case 'o':
10497
1.62M
          if ((given & 0x02000000) != 0)
10498
238k
      {
10499
238k
        unsigned int rotate = (given & 0xf00) >> 7;
10500
238k
        unsigned int immed = (given & 0xff);
10501
238k
        unsigned int a, i;
10502
10503
238k
        a = (immed << ((32 - rotate) & 31)
10504
238k
             | immed >> rotate) & 0xffffffff;
10505
        /* If there is another encoding with smaller rotate,
10506
           the rotate should be specified directly.  */
10507
1.12M
        for (i = 0; i < 32; i += 2)
10508
1.12M
          if ((a << i | a >> ((32 - i) & 31)) <= 0xff)
10509
238k
            break;
10510
10511
238k
        if (i != rotate)
10512
48.1k
          {
10513
48.1k
            func (stream, dis_style_immediate, "#%d", immed);
10514
48.1k
            func (stream, dis_style_text, ", ");
10515
48.1k
            func (stream, dis_style_immediate, "%d", rotate);
10516
48.1k
          }
10517
190k
        else
10518
190k
          func (stream, dis_style_immediate, "#%d", a);
10519
238k
        value_in_comment = a;
10520
238k
      }
10521
1.38M
          else
10522
1.38M
      arm_decode_shift (given, func, stream, true);
10523
1.62M
          break;
10524
10525
125k
        case 'p':
10526
125k
          if ((given & 0x0000f000) == 0x0000f000)
10527
3.28k
      {
10528
3.28k
        arm_feature_set arm_ext_v6 =
10529
3.28k
          ARM_FEATURE_CORE_LOW (ARM_EXT_V6);
10530
10531
        /* The p-variants of tst/cmp/cmn/teq are the pre-V6
10532
           mechanism for setting PSR flag bits.  They are
10533
           obsolete in V6 onwards.  */
10534
3.28k
        if (! ARM_CPU_HAS_FEATURE (private_data->features, \
10535
3.28k
                 arm_ext_v6))
10536
378
          func (stream, dis_style_mnemonic, "p");
10537
2.90k
        else
10538
2.90k
          is_unpredictable = true;
10539
3.28k
      }
10540
125k
          break;
10541
10542
319k
        case 't':
10543
319k
          if ((given & 0x01200000) == 0x00200000)
10544
74.8k
      func (stream, dis_style_mnemonic, "t");
10545
319k
          break;
10546
10547
0
        case 'A':
10548
0
          {
10549
0
      int offset = given & 0xff;
10550
10551
0
      value_in_comment = offset * 4;
10552
0
      if (NEGATIVE_BIT_SET)
10553
0
        value_in_comment = - value_in_comment;
10554
10555
0
      func (stream, dis_style_text, "[%s",
10556
0
            arm_regnames [(given >> 16) & 0xf]);
10557
10558
0
      if (PRE_BIT_SET)
10559
0
        {
10560
0
          if (offset)
10561
0
            func (stream, dis_style_text, ", #%d]%s",
10562
0
            (int) value_in_comment,
10563
0
            WRITEBACK_BIT_SET ? "!" : "");
10564
0
          else
10565
0
            func (stream, dis_style_text, "]");
10566
0
        }
10567
0
      else
10568
0
        {
10569
0
          func (stream, dis_style_text, "]");
10570
10571
0
          if (WRITEBACK_BIT_SET)
10572
0
            {
10573
0
        if (offset)
10574
0
          func (stream, dis_style_text,
10575
0
          ", #%d", (int) value_in_comment);
10576
0
            }
10577
0
          else
10578
0
            {
10579
0
        func (stream, dis_style_text,
10580
0
              ", {%d}", (int) offset);
10581
0
        value_in_comment = offset;
10582
0
            }
10583
0
        }
10584
0
          }
10585
0
          break;
10586
10587
17.8k
        case 'B':
10588
          /* Print ARM V5 BLX(1) address: pc+25 bits.  */
10589
17.8k
          {
10590
17.8k
      bfd_vma address;
10591
17.8k
      bfd_vma offset = 0;
10592
10593
17.8k
      if (! NEGATIVE_BIT_SET)
10594
        /* Is signed, hi bits should be ones.  */
10595
12.4k
        offset = (-1) ^ 0x00ffffff;
10596
10597
      /* Offset is (SignExtend(offset field)<<2).  */
10598
17.8k
      offset += given & 0x00ffffff;
10599
17.8k
      offset <<= 2;
10600
17.8k
      address = offset + pc + 8;
10601
10602
17.8k
      if (given & 0x01000000)
10603
        /* H bit allows addressing to 2-byte boundaries.  */
10604
11.2k
        address += 2;
10605
10606
17.8k
            info->print_address_func (address, info);
10607
10608
      /* Fill in instruction information.  */
10609
17.8k
      info->insn_info_valid = 1;
10610
17.8k
      info->insn_type = dis_branch;
10611
17.8k
      info->target = address;
10612
17.8k
          }
10613
17.8k
          break;
10614
10615
4.04k
        case 'C':
10616
4.04k
          if ((given & 0x02000200) == 0x200)
10617
2.59k
      {
10618
2.59k
        const char * name;
10619
2.59k
        unsigned sysm = (given & 0x004f0000) >> 16;
10620
10621
2.59k
        sysm |= (given & 0x300) >> 4;
10622
2.59k
        name = banked_regname (sysm);
10623
10624
2.59k
        if (name != NULL)
10625
2.19k
          func (stream, dis_style_register, "%s", name);
10626
393
        else
10627
393
          func (stream, dis_style_text,
10628
393
          "(UNDEF: %lu)", (unsigned long) sysm);
10629
2.59k
      }
10630
1.45k
          else
10631
1.45k
      {
10632
1.45k
        func (stream, dis_style_register, "%cPSR_",
10633
1.45k
        (given & 0x00400000) ? 'S' : 'C');
10634
10635
1.45k
        if (given & 0x80000)
10636
920
          func (stream, dis_style_register, "f");
10637
1.45k
        if (given & 0x40000)
10638
784
          func (stream, dis_style_register, "s");
10639
1.45k
        if (given & 0x20000)
10640
948
          func (stream, dis_style_register, "x");
10641
1.45k
        if (given & 0x10000)
10642
848
          func (stream, dis_style_register, "c");
10643
1.45k
      }
10644
4.04k
          break;
10645
10646
840
        case 'U':
10647
840
          if ((given & 0xf0) == 0x60)
10648
314
      {
10649
314
        switch (given & 0xf)
10650
314
          {
10651
207
          case 0xf:
10652
207
            func (stream, dis_style_sub_mnemonic, "sy");
10653
207
            break;
10654
107
          default:
10655
107
            func (stream, dis_style_immediate, "#%d",
10656
107
            (int) given & 0xf);
10657
107
            break;
10658
314
          }
10659
314
      }
10660
526
          else
10661
526
      {
10662
526
        const char * opt = data_barrier_option (given & 0xf);
10663
526
        if (opt != NULL)
10664
380
          func (stream, dis_style_sub_mnemonic, "%s", opt);
10665
146
        else
10666
146
          func (stream, dis_style_immediate,
10667
146
          "#%d", (int) given & 0xf);
10668
526
      }
10669
840
          break;
10670
10671
7.07M
        case '0': case '1': case '2': case '3': case '4':
10672
7.16M
        case '5': case '6': case '7': case '8': case '9':
10673
7.16M
          {
10674
7.16M
      int width;
10675
7.16M
      unsigned long value;
10676
10677
7.16M
      c = arm_decode_bitfield (c, given, &value, &width);
10678
10679
7.16M
      switch (*c)
10680
7.16M
        {
10681
1.03M
        case 'R':
10682
1.03M
          if (value == 15)
10683
47.6k
            is_unpredictable = true;
10684
          /* Fall through.  */
10685
4.03M
        case 'r':
10686
4.03M
        case 'T':
10687
          /* We want register + 1 when decoding T.  */
10688
4.03M
          if (*c == 'T')
10689
197
            value = (value + 1) & 0xf;
10690
10691
4.03M
          if (c[1] == 'u')
10692
15.4k
            {
10693
        /* Eat the 'u' character.  */
10694
15.4k
        ++ c;
10695
10696
15.4k
        if (u_reg == value)
10697
618
          is_unpredictable = true;
10698
15.4k
        u_reg = value;
10699
15.4k
            }
10700
4.03M
          if (c[1] == 'U')
10701
1.32k
            {
10702
        /* Eat the 'U' character.  */
10703
1.32k
        ++ c;
10704
10705
1.32k
        if (U_reg == value)
10706
576
          is_unpredictable = true;
10707
1.32k
        U_reg = value;
10708
1.32k
            }
10709
4.03M
          func (stream, dis_style_register, "%s",
10710
4.03M
          arm_regnames[value]);
10711
4.03M
          break;
10712
6.59k
        case 'd':
10713
6.59k
          func (stream, base_style, "%ld", value);
10714
6.59k
          value_in_comment = value;
10715
6.59k
          break;
10716
0
        case 'b':
10717
0
          func (stream, dis_style_immediate,
10718
0
          "%ld", value * 8);
10719
0
          value_in_comment = value * 8;
10720
0
          break;
10721
2.35k
        case 'W':
10722
2.35k
          func (stream, dis_style_immediate,
10723
2.35k
          "%ld", value + 1);
10724
2.35k
          value_in_comment = value + 1;
10725
2.35k
          break;
10726
448k
        case 'x':
10727
448k
          func (stream, dis_style_immediate,
10728
448k
          "0x%08lx", value);
10729
10730
          /* Some SWI instructions have special
10731
             meanings.  */
10732
448k
          if ((given & 0x0fffffff) == 0x0FF00000)
10733
150
            func (stream, dis_style_comment_start,
10734
150
            "\t@ IMB");
10735
447k
          else if ((given & 0x0fffffff) == 0x0FF00001)
10736
209
            func (stream, dis_style_comment_start,
10737
209
            "\t@ IMBRange");
10738
448k
          break;
10739
736
        case 'X':
10740
736
          func (stream, dis_style_immediate,
10741
736
          "%01lx", value & 0xf);
10742
736
          value_in_comment = value;
10743
736
          break;
10744
0
        case '`':
10745
0
          c++;
10746
0
          if (value == 0)
10747
0
            func (stream, dis_style_text, "%c", *c);
10748
0
          break;
10749
2.22M
        case '\'':
10750
2.22M
          c++;
10751
2.22M
          if (value == ((1ul << width) - 1))
10752
575k
            func (stream, base_style, "%c", *c);
10753
2.22M
          break;
10754
452k
        case '?':
10755
452k
          func (stream, base_style, "%c",
10756
452k
          c[(1 << width) - (int) value]);
10757
452k
          c += 1 << width;
10758
452k
          break;
10759
0
        default:
10760
0
          abort ();
10761
7.16M
        }
10762
7.16M
          }
10763
7.16M
          break;
10764
10765
7.16M
        case 'e':
10766
1.91k
          {
10767
1.91k
      int imm;
10768
10769
1.91k
      imm = (given & 0xf) | ((given & 0xfff00) >> 4);
10770
1.91k
      func (stream, dis_style_immediate, "%d", imm);
10771
1.91k
      value_in_comment = imm;
10772
1.91k
          }
10773
1.91k
          break;
10774
10775
938
        case 'E':
10776
          /* LSB and WIDTH fields of BFI or BFC.  The machine-
10777
       language instruction encodes LSB and MSB.  */
10778
938
          {
10779
938
      long msb = (given & 0x001f0000) >> 16;
10780
938
      long lsb = (given & 0x00000f80) >> 7;
10781
938
      long w = msb - lsb + 1;
10782
10783
938
      if (w > 0)
10784
512
        {
10785
512
          func (stream, dis_style_immediate, "#%lu", lsb);
10786
512
          func (stream, dis_style_text, ", ");
10787
512
          func (stream, dis_style_immediate, "#%lu", w);
10788
512
        }
10789
426
      else
10790
426
        func (stream, dis_style_text,
10791
426
        "(invalid: %lu:%lu)", lsb, msb);
10792
938
          }
10793
938
          break;
10794
10795
38.4k
        case 'R':
10796
          /* Get the PSR/banked register name.  */
10797
38.4k
          {
10798
38.4k
      const char * name;
10799
38.4k
      unsigned sysm = (given & 0x004f0000) >> 16;
10800
10801
38.4k
      sysm |= (given & 0x300) >> 4;
10802
38.4k
      name = banked_regname (sysm);
10803
10804
38.4k
      if (name != NULL)
10805
2.54k
        func (stream, dis_style_register, "%s", name);
10806
35.8k
      else
10807
35.8k
        func (stream, dis_style_text,
10808
35.8k
        "(UNDEF: %lu)", (unsigned long) sysm);
10809
38.4k
          }
10810
38.4k
          break;
10811
10812
46.5k
        case 'V':
10813
          /* 16-bit unsigned immediate from a MOVT or MOVW
10814
       instruction, encoded in bits 0:11 and 15:19.  */
10815
46.5k
          {
10816
46.5k
      long hi = (given & 0x000f0000) >> 4;
10817
46.5k
      long lo = (given & 0x00000fff);
10818
46.5k
      long imm16 = hi | lo;
10819
10820
46.5k
      func (stream, dis_style_immediate, "#%lu", imm16);
10821
46.5k
      value_in_comment = imm16;
10822
46.5k
          }
10823
46.5k
          break;
10824
10825
0
        default:
10826
0
          abort ();
10827
13.0M
        }
10828
13.0M
    }
10829
27.8M
        else
10830
27.8M
    {
10831
10832
27.8M
      if (*c == '@')
10833
291k
        base_style = dis_style_comment_start;
10834
10835
27.8M
      if (*c == '\t')
10836
3.42M
        base_style = dis_style_text;
10837
10838
27.8M
      func (stream, base_style, "%c", *c);
10839
27.8M
    }
10840
40.8M
      }
10841
10842
3.12M
    if (value_in_comment > 32 || value_in_comment < -16)
10843
421k
      func (stream, dis_style_comment_start, "\t@ 0x%lx",
10844
421k
      (value_in_comment & 0xffffffffUL));
10845
10846
3.12M
    if (is_unpredictable)
10847
115k
      func (stream, dis_style_comment_start, UNPREDICTABLE_INSTRUCTION);
10848
10849
3.12M
    return;
10850
3.12M
  }
10851
3.31M
    }
10852
26.3k
  func (stream, dis_style_comment_start, UNKNOWN_INSTRUCTION_32BIT,
10853
26.3k
  (unsigned) given);
10854
26.3k
  return;
10855
3.15M
}
10856
10857
/* Print one 16-bit Thumb instruction from PC on INFO->STREAM.  */
10858
10859
static void
10860
print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
10861
1.05M
{
10862
1.05M
  const struct opcode16 *insn;
10863
1.05M
  void *stream = info->stream;
10864
1.05M
  fprintf_styled_ftype func = info->fprintf_styled_func;
10865
1.05M
  enum disassembler_style base_style = dis_style_mnemonic;
10866
1.05M
  enum disassembler_style old_base_style = base_style;
10867
10868
69.5M
  for (insn = thumb_opcodes; insn->assembler; insn++)
10869
69.5M
    if ((given & insn->mask) == insn->value)
10870
1.05M
      {
10871
1.05M
  signed long value_in_comment = 0;
10872
1.05M
  const char *c = insn->assembler;
10873
10874
15.0M
  for (; *c; c++)
10875
13.9M
    {
10876
13.9M
      int domaskpc = 0;
10877
13.9M
      int domasklr = 0;
10878
10879
13.9M
      if (*c != '%')
10880
9.05M
        {
10881
9.05M
    if (*c == '@')
10882
38.0k
      base_style = dis_style_comment_start;
10883
10884
9.05M
    if (*c == '\t')
10885
1.06M
      base_style = dis_style_text;
10886
10887
9.05M
    func (stream, base_style, "%c", *c);
10888
10889
9.05M
    continue;
10890
9.05M
        }
10891
10892
4.93M
      switch (*++c)
10893
4.93M
        {
10894
657k
    case '{':
10895
657k
      ++c;
10896
657k
      if (*c == '\0')
10897
0
        abort ();
10898
657k
      old_base_style = base_style;
10899
657k
      base_style = decode_base_style (*c);
10900
657k
      ++c;
10901
657k
      if (*c != ':')
10902
0
        abort ();
10903
657k
      break;
10904
10905
657k
    case '}':
10906
657k
      base_style = old_base_style;
10907
657k
      break;
10908
10909
0
        case '%':
10910
0
    func (stream, base_style, "%%");
10911
0
    break;
10912
10913
536k
        case 'c':
10914
536k
    if (ifthen_state)
10915
17.4k
      func (stream, dis_style_mnemonic, "%s",
10916
17.4k
      arm_conditional[IFTHEN_COND]);
10917
536k
    break;
10918
10919
447k
        case 'C':
10920
447k
    if (ifthen_state)
10921
8.61k
      func (stream, dis_style_mnemonic, "%s",
10922
8.61k
      arm_conditional[IFTHEN_COND]);
10923
439k
    else
10924
439k
      func (stream, dis_style_mnemonic, "s");
10925
447k
    break;
10926
10927
17.9k
        case 'I':
10928
17.9k
    {
10929
17.9k
      unsigned int tmp;
10930
10931
17.9k
      ifthen_next_state = given & 0xff;
10932
63.7k
      for (tmp = given << 1; tmp & 0xf; tmp <<= 1)
10933
45.8k
        func (stream, dis_style_mnemonic,
10934
45.8k
        ((given ^ tmp) & 0x10) ? "e" : "t");
10935
17.9k
      func (stream, dis_style_text, "\t");
10936
17.9k
      func (stream, dis_style_sub_mnemonic, "%s",
10937
17.9k
      arm_conditional[(given >> 4) & 0xf]);
10938
17.9k
    }
10939
17.9k
    break;
10940
10941
23.6k
        case 'x':
10942
23.6k
    if (ifthen_next_state)
10943
1.41k
      func (stream, dis_style_comment_start,
10944
1.41k
      "\t@ unpredictable branch in IT block\n");
10945
23.6k
    break;
10946
10947
58.2k
        case 'X':
10948
58.2k
    if (ifthen_state)
10949
9.17k
      func (stream, dis_style_comment_start,
10950
9.17k
      "\t@ unpredictable <IT:%s>",
10951
9.17k
      arm_conditional[IFTHEN_COND]);
10952
58.2k
    break;
10953
10954
31.6k
        case 'S':
10955
31.6k
    {
10956
31.6k
      long reg;
10957
10958
31.6k
      reg = (given >> 3) & 0x7;
10959
31.6k
      if (given & (1 << 6))
10960
25.8k
        reg += 8;
10961
10962
31.6k
      func (stream, dis_style_register, "%s", arm_regnames[reg]);
10963
31.6k
    }
10964
31.6k
    break;
10965
10966
30.8k
        case 'D':
10967
30.8k
    {
10968
30.8k
      long reg;
10969
10970
30.8k
      reg = given & 0x7;
10971
30.8k
      if (given & (1 << 7))
10972
6.98k
        reg += 8;
10973
10974
30.8k
      func (stream, dis_style_register, "%s", arm_regnames[reg]);
10975
30.8k
    }
10976
30.8k
    break;
10977
10978
3.99k
        case 'N':
10979
3.99k
    if (given & (1 << 8))
10980
2.29k
      domasklr = 1;
10981
    /* Fall through.  */
10982
20.4k
        case 'O':
10983
20.4k
    if (*c == 'O' && (given & (1 << 8)))
10984
14.4k
      domaskpc = 1;
10985
    /* Fall through.  */
10986
72.3k
        case 'M':
10987
72.3k
    {
10988
72.3k
      int started = 0;
10989
72.3k
      int reg;
10990
10991
72.3k
      func (stream, dis_style_text, "{");
10992
10993
      /* It would be nice if we could spot
10994
         ranges, and generate the rS-rE format: */
10995
651k
      for (reg = 0; (reg < 8); reg++)
10996
578k
        if ((given & (1 << reg)) != 0)
10997
342k
          {
10998
342k
      if (started)
10999
272k
        func (stream, dis_style_text, ", ");
11000
342k
      started = 1;
11001
342k
      func (stream, dis_style_register, "%s",
11002
342k
            arm_regnames[reg]);
11003
342k
          }
11004
11005
72.3k
      if (domasklr)
11006
2.29k
        {
11007
2.29k
          if (started)
11008
2.04k
      func (stream, dis_style_text, ", ");
11009
2.29k
          started = 1;
11010
2.29k
          func (stream, dis_style_register, "%s",
11011
2.29k
          arm_regnames[14] /* "lr" */);
11012
2.29k
        }
11013
11014
72.3k
      if (domaskpc)
11015
14.4k
        {
11016
14.4k
          if (started)
11017
13.8k
      func (stream, dis_style_text, ", ");
11018
14.4k
          func (stream, dis_style_register, "%s",
11019
14.4k
          arm_regnames[15] /* "pc" */);
11020
14.4k
        }
11021
11022
72.3k
      func (stream, dis_style_text, "}");
11023
72.3k
    }
11024
72.3k
    break;
11025
11026
25.6k
        case 'W':
11027
    /* Print writeback indicator for a LDMIA.  We are doing a
11028
       writeback if the base register is not in the register
11029
       mask.  */
11030
25.6k
    if ((given & (1 << ((given & 0x0700) >> 8))) == 0)
11031
9.30k
      func (stream, dis_style_text, "!");
11032
25.6k
    break;
11033
11034
3.39k
        case 'b':
11035
    /* Print ARM V6T2 CZB address: pc+4+6 bits.  */
11036
3.39k
    {
11037
3.39k
      bfd_vma address = (pc + 4
11038
3.39k
             + ((given & 0x00f8) >> 2)
11039
3.39k
             + ((given & 0x0200) >> 3));
11040
3.39k
      info->print_address_func (address, info);
11041
11042
      /* Fill in instruction information.  */
11043
3.39k
      info->insn_info_valid = 1;
11044
3.39k
      info->insn_type = dis_branch;
11045
3.39k
      info->target = address;
11046
3.39k
    }
11047
3.39k
    break;
11048
11049
60.6k
        case 's':
11050
    /* Right shift immediate -- bits 6..10; 1-31 print
11051
       as themselves, 0 prints as 32.  */
11052
60.6k
    {
11053
60.6k
      long imm = (given & 0x07c0) >> 6;
11054
60.6k
      if (imm == 0)
11055
3.78k
        imm = 32;
11056
60.6k
      func (stream, dis_style_immediate, "#%ld", imm);
11057
60.6k
    }
11058
60.6k
    break;
11059
11060
1.60M
        case '0': case '1': case '2': case '3': case '4':
11061
2.30M
        case '5': case '6': case '7': case '8': case '9':
11062
2.30M
    {
11063
2.30M
      int bitstart = *c++ - '0';
11064
2.30M
      int bitend = 0;
11065
11066
2.34M
      while (*c >= '0' && *c <= '9')
11067
31.6k
        bitstart = (bitstart * 10) + *c++ - '0';
11068
11069
2.30M
      switch (*c)
11070
2.30M
        {
11071
2.27M
        case '-':
11072
2.27M
          {
11073
2.27M
      bfd_vma reg;
11074
11075
2.27M
      c++;
11076
5.21M
      while (*c >= '0' && *c <= '9')
11077
2.94M
        bitend = (bitend * 10) + *c++ - '0';
11078
2.27M
      if (!bitend)
11079
0
        abort ();
11080
2.27M
      reg = given >> bitstart;
11081
2.27M
      reg &= ((bfd_vma) 2 << (bitend - bitstart)) - 1;
11082
11083
2.27M
      switch (*c)
11084
2.27M
        {
11085
1.57M
        case 'r':
11086
1.57M
          func (stream, dis_style_register, "%s",
11087
1.57M
          arm_regnames[reg]);
11088
1.57M
          break;
11089
11090
331k
        case 'd':
11091
331k
          func (stream, dis_style_immediate, "%ld",
11092
331k
          (long) reg);
11093
331k
          value_in_comment = reg;
11094
331k
          break;
11095
11096
52.6k
        case 'H':
11097
52.6k
          func (stream, dis_style_immediate, "%ld",
11098
52.6k
          (long) (reg << 1));
11099
52.6k
          value_in_comment = reg << 1;
11100
52.6k
          break;
11101
11102
182k
        case 'W':
11103
182k
          func (stream, dis_style_immediate, "%ld",
11104
182k
          (long) (reg << 2));
11105
182k
          value_in_comment = reg << 2;
11106
182k
          break;
11107
11108
34.0k
        case 'a':
11109
          /* PC-relative address -- the bottom two
11110
             bits of the address are dropped
11111
             before the calculation.  */
11112
34.0k
          info->print_address_func
11113
34.0k
            (((pc + 4) & ~3) + (reg << 2), info);
11114
34.0k
          value_in_comment = 0;
11115
34.0k
          break;
11116
11117
8.78k
        case 'x':
11118
8.78k
          func (stream, dis_style_immediate, "0x%04lx",
11119
8.78k
          (long) reg);
11120
8.78k
          break;
11121
11122
58.3k
        case 'B':
11123
58.3k
          reg = ((reg ^ (1 << bitend)) - (1 << bitend));
11124
58.3k
          bfd_vma target = reg * 2 + pc + 4;
11125
58.3k
          info->print_address_func (target, info);
11126
58.3k
          value_in_comment = 0;
11127
11128
          /* Fill in instruction information.  */
11129
58.3k
          info->insn_info_valid = 1;
11130
58.3k
          info->insn_type = dis_branch;
11131
58.3k
          info->target = target;
11132
58.3k
          break;
11133
11134
36.4k
        case 'c':
11135
36.4k
          func (stream, dis_style_mnemonic, "%s",
11136
36.4k
          arm_conditional [reg]);
11137
36.4k
          break;
11138
11139
0
        default:
11140
0
          abort ();
11141
2.27M
        }
11142
2.27M
          }
11143
2.27M
          break;
11144
11145
2.27M
        case '\'':
11146
21.5k
          c++;
11147
21.5k
          if ((given & (1 << bitstart)) != 0)
11148
9.54k
      func (stream, base_style, "%c", *c);
11149
21.5k
          break;
11150
11151
11.4k
        case '?':
11152
11.4k
          ++c;
11153
11.4k
          if ((given & (1 << bitstart)) != 0)
11154
6.31k
      func (stream, base_style, "%c", *c++);
11155
5.09k
          else
11156
5.09k
      func (stream, base_style, "%c", *++c);
11157
11.4k
          break;
11158
11159
0
        default:
11160
0
          abort ();
11161
2.30M
        }
11162
2.30M
    }
11163
2.30M
    break;
11164
11165
2.30M
        default:
11166
0
    abort ();
11167
4.93M
        }
11168
4.93M
    }
11169
11170
1.05M
  if (value_in_comment > 32 || value_in_comment < -16)
11171
227k
    func (stream, dis_style_comment_start,
11172
227k
    "\t@ 0x%lx", value_in_comment);
11173
1.05M
  return;
11174
1.05M
      }
11175
11176
  /* No match.  */
11177
0
  func (stream, dis_style_comment_start, UNKNOWN_INSTRUCTION_16BIT,
11178
0
  (unsigned) given);
11179
0
  return;
11180
1.05M
}
11181
11182
/* Return the name of an V7M special register.  */
11183
11184
static const char *
11185
psr_name (int regno)
11186
7.49k
{
11187
7.49k
  switch (regno)
11188
7.49k
    {
11189
0
    case 0x0: return "APSR";
11190
218
    case 0x1: return "IAPSR";
11191
200
    case 0x2: return "EAPSR";
11192
217
    case 0x3: return "PSR";
11193
216
    case 0x5: return "IPSR";
11194
437
    case 0x6: return "EPSR";
11195
197
    case 0x7: return "IEPSR";
11196
346
    case 0x8: return "MSP";
11197
201
    case 0x9: return "PSP";
11198
199
    case 0xa: return "MSPLIM";
11199
24
    case 0xb: return "PSPLIM";
11200
205
    case 0x10: return "PRIMASK";
11201
207
    case 0x11: return "BASEPRI";
11202
241
    case 0x12: return "BASEPRI_MAX";
11203
204
    case 0x13: return "FAULTMASK";
11204
212
    case 0x14: return "CONTROL";
11205
354
    case 0x88: return "MSP_NS";
11206
327
    case 0x89: return "PSP_NS";
11207
211
    case 0x8a: return "MSPLIM_NS";
11208
431
    case 0x8b: return "PSPLIM_NS";
11209
203
    case 0x90: return "PRIMASK_NS";
11210
215
    case 0x91: return "BASEPRI_NS";
11211
197
    case 0x93: return "FAULTMASK_NS";
11212
211
    case 0x94: return "CONTROL_NS";
11213
348
    case 0x98: return "SP_NS";
11214
1.67k
    default: return "<unknown>";
11215
7.49k
    }
11216
7.49k
}
11217
11218
/* Print one 32-bit Thumb instruction from PC on INFO->STREAM.  */
11219
11220
static void
11221
print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
11222
416k
{
11223
416k
  const struct opcode32 *insn;
11224
416k
  void *stream = info->stream;
11225
416k
  fprintf_styled_ftype func = info->fprintf_styled_func;
11226
416k
  bool is_mve = is_mve_architecture (info);
11227
416k
  enum disassembler_style base_style = dis_style_mnemonic;
11228
416k
  enum disassembler_style old_base_style = base_style;
11229
11230
416k
  if (print_insn_coprocessor (pc, info, given, true))
11231
22.0k
    return;
11232
11233
394k
  if (!is_mve && print_insn_neon (info, given, true))
11234
15.9k
    return;
11235
11236
378k
  if (is_mve && print_insn_mve (info, given))
11237
117k
    return;
11238
11239
260k
  if (print_insn_cde (info, given, true))
11240
21.6k
    return;
11241
11242
238k
  if (print_insn_generic_coprocessor (pc, info, given, true))
11243
16.5k
    return;
11244
11245
50.1M
  for (insn = thumb32_opcodes; insn->assembler; insn++)
11246
50.1M
    if ((given & insn->mask) == insn->value)
11247
222k
      {
11248
222k
  bool is_clrm = false;
11249
222k
  bool is_unpredictable = false;
11250
222k
  signed long value_in_comment = 0;
11251
222k
  const char *c = insn->assembler;
11252
11253
5.10M
  for (; *c; c++)
11254
4.88M
    {
11255
4.88M
      if (*c != '%')
11256
4.41M
        {
11257
4.41M
    if (*c == '@')
11258
130k
      base_style = dis_style_comment_start;
11259
4.41M
    if (*c == '\t')
11260
350k
      base_style = dis_style_text;
11261
4.41M
    func (stream, base_style, "%c", *c);
11262
4.41M
    continue;
11263
4.41M
        }
11264
11265
474k
      switch (*++c)
11266
474k
        {
11267
10.0k
        case '{':
11268
10.0k
    ++c;
11269
10.0k
    if (*c == '\0')
11270
0
      abort ();
11271
10.0k
    old_base_style = base_style;
11272
10.0k
    base_style = decode_base_style (*c);
11273
10.0k
    ++c;
11274
10.0k
    if (*c != ':')
11275
0
      abort ();
11276
10.0k
    break;
11277
11278
10.0k
        case '}':
11279
10.0k
    base_style = old_base_style;
11280
10.0k
    break;
11281
11282
0
        case '%':
11283
0
    func (stream, base_style, "%%");
11284
0
    break;
11285
11286
81.3k
        case 'c':
11287
81.3k
    if (ifthen_state)
11288
2.50k
      func (stream, dis_style_mnemonic, "%s",
11289
2.50k
      arm_conditional[IFTHEN_COND]);
11290
81.3k
    break;
11291
11292
24.4k
        case 'x':
11293
24.4k
    if (ifthen_next_state)
11294
586
      func (stream, dis_style_comment_start,
11295
586
      "\t@ unpredictable branch in IT block\n");
11296
24.4k
    break;
11297
11298
6.07k
        case 'X':
11299
6.07k
    if (ifthen_state)
11300
565
      func (stream, dis_style_comment_start,
11301
565
      "\t@ unpredictable <IT:%s>",
11302
565
      arm_conditional[IFTHEN_COND]);
11303
6.07k
    break;
11304
11305
560
        case 'I':
11306
560
    {
11307
560
      unsigned int imm12 = 0;
11308
11309
560
      imm12 |= (given & 0x000000ffu);
11310
560
      imm12 |= (given & 0x00007000u) >> 4;
11311
560
      imm12 |= (given & 0x04000000u) >> 15;
11312
560
      func (stream, dis_style_immediate, "#%u", imm12);
11313
560
      value_in_comment = imm12;
11314
560
    }
11315
560
    break;
11316
11317
2.06k
        case 'M':
11318
2.06k
    {
11319
2.06k
      unsigned int bits = 0, imm, imm8, mod;
11320
11321
2.06k
      bits |= (given & 0x000000ffu);
11322
2.06k
      bits |= (given & 0x00007000u) >> 4;
11323
2.06k
      bits |= (given & 0x04000000u) >> 15;
11324
2.06k
      imm8 = (bits & 0x0ff);
11325
2.06k
      mod = (bits & 0xf00) >> 8;
11326
2.06k
      switch (mod)
11327
2.06k
        {
11328
560
        case 0: imm = imm8; break;
11329
218
        case 1: imm = ((imm8 << 16) | imm8); break;
11330
347
        case 2: imm = ((imm8 << 24) | (imm8 << 8)); break;
11331
274
        case 3: imm = ((imm8 << 24) | (imm8 << 16) | (imm8 << 8) | imm8); break;
11332
661
        default:
11333
661
          mod  = (bits & 0xf80) >> 7;
11334
661
          imm8 = (bits & 0x07f) | 0x80;
11335
661
          imm  = (((imm8 << (32 - mod)) | (imm8 >> mod)) & 0xffffffff);
11336
2.06k
        }
11337
2.06k
      func (stream, dis_style_immediate, "#%u", imm);
11338
2.06k
      value_in_comment = imm;
11339
2.06k
    }
11340
0
    break;
11341
11342
5.28k
        case 'J':
11343
5.28k
    {
11344
5.28k
      unsigned int imm = 0;
11345
11346
5.28k
      imm |= (given & 0x000000ffu);
11347
5.28k
      imm |= (given & 0x00007000u) >> 4;
11348
5.28k
      imm |= (given & 0x04000000u) >> 15;
11349
5.28k
      imm |= (given & 0x000f0000u) >> 4;
11350
5.28k
      func (stream, dis_style_immediate, "#%u", imm);
11351
5.28k
      value_in_comment = imm;
11352
5.28k
    }
11353
5.28k
    break;
11354
11355
242
        case 'K':
11356
242
    {
11357
242
      unsigned int imm = 0;
11358
11359
242
      imm |= (given & 0x000f0000u) >> 16;
11360
242
      imm |= (given & 0x00000ff0u) >> 0;
11361
242
      imm |= (given & 0x0000000fu) << 12;
11362
242
      func (stream, dis_style_immediate, "#%u", imm);
11363
242
      value_in_comment = imm;
11364
242
    }
11365
242
    break;
11366
11367
222
        case 'H':
11368
222
    {
11369
222
      unsigned int imm = 0;
11370
11371
222
      imm |= (given & 0x000f0000u) >> 4;
11372
222
      imm |= (given & 0x00000fffu) >> 0;
11373
222
      func (stream, dis_style_immediate, "#%u", imm);
11374
222
      value_in_comment = imm;
11375
222
    }
11376
222
    break;
11377
11378
196
        case 'V':
11379
196
    {
11380
196
      unsigned int imm = 0;
11381
11382
196
      imm |= (given & 0x00000fffu);
11383
196
      imm |= (given & 0x000f0000u) >> 4;
11384
196
      func (stream, dis_style_immediate, "#%u", imm);
11385
196
      value_in_comment = imm;
11386
196
    }
11387
196
    break;
11388
11389
3.64k
        case 'S':
11390
3.64k
    {
11391
3.64k
      unsigned int reg = (given & 0x0000000fu);
11392
3.64k
      unsigned int stp = (given & 0x00000030u) >> 4;
11393
3.64k
      unsigned int imm = 0;
11394
3.64k
      imm |= (given & 0x000000c0u) >> 6;
11395
3.64k
      imm |= (given & 0x00007000u) >> 10;
11396
11397
3.64k
      func (stream, dis_style_register, "%s", arm_regnames[reg]);
11398
3.64k
      switch (stp)
11399
3.64k
        {
11400
1.09k
        case 0:
11401
1.09k
          if (imm > 0)
11402
372
      {
11403
372
        func (stream, dis_style_text, ", ");
11404
372
        func (stream, dis_style_sub_mnemonic, "lsl ");
11405
372
        func (stream, dis_style_immediate, "#%u", imm);
11406
372
      }
11407
1.09k
          break;
11408
11409
605
        case 1:
11410
605
          if (imm == 0)
11411
216
      imm = 32;
11412
605
          func (stream, dis_style_text, ", ");
11413
605
          func (stream, dis_style_sub_mnemonic, "lsr ");
11414
605
          func (stream, dis_style_immediate, "#%u", imm);
11415
605
          break;
11416
11417
1.11k
        case 2:
11418
1.11k
          if (imm == 0)
11419
205
      imm = 32;
11420
1.11k
          func (stream, dis_style_text, ", ");
11421
1.11k
          func (stream, dis_style_sub_mnemonic, "asr ");
11422
1.11k
          func (stream, dis_style_immediate, "#%u", imm);
11423
1.11k
          break;
11424
11425
835
        case 3:
11426
835
          if (imm == 0)
11427
225
      {
11428
225
        func (stream, dis_style_text, ", ");
11429
225
        func (stream, dis_style_sub_mnemonic, "rrx");
11430
225
      }
11431
610
          else
11432
610
      {
11433
610
        func (stream, dis_style_text, ", ");
11434
610
        func (stream, dis_style_sub_mnemonic, "ror ");
11435
610
        func (stream, dis_style_immediate, "#%u", imm);
11436
610
      }
11437
3.64k
        }
11438
3.64k
    }
11439
3.64k
    break;
11440
11441
11.2k
        case 'a':
11442
11.2k
    {
11443
11.2k
      unsigned int Rn  = (given & 0x000f0000) >> 16;
11444
11.2k
      unsigned int U   = ! NEGATIVE_BIT_SET;
11445
11.2k
      unsigned int op  = (given & 0x00000f00) >> 8;
11446
11.2k
      unsigned int i12 = (given & 0x00000fff);
11447
11.2k
      unsigned int i8  = (given & 0x000000ff);
11448
11.2k
      bool writeback = false, postind = false;
11449
11.2k
      bfd_vma offset = 0;
11450
11451
11.2k
      func (stream, dis_style_text, "[");
11452
11.2k
      func (stream, dis_style_register, "%s", arm_regnames[Rn]);
11453
11.2k
      if (U) /* 12-bit positive immediate offset.  */
11454
5.95k
        {
11455
5.95k
          offset = i12;
11456
5.95k
          if (Rn != 15)
11457
3.68k
      value_in_comment = offset;
11458
5.95k
        }
11459
5.33k
      else if (Rn == 15) /* 12-bit negative immediate offset.  */
11460
630
        offset = - (int) i12;
11461
4.70k
      else if (op == 0x0) /* Shifted register offset.  */
11462
1.12k
        {
11463
1.12k
          unsigned int Rm = (i8 & 0x0f);
11464
1.12k
          unsigned int sh = (i8 & 0x30) >> 4;
11465
11466
1.12k
          func (stream, dis_style_text, ", ");
11467
1.12k
          func (stream, dis_style_register, "%s",
11468
1.12k
          arm_regnames[Rm]);
11469
1.12k
          if (sh)
11470
513
      {
11471
513
        func (stream, dis_style_text, ", ");
11472
513
        func (stream, dis_style_sub_mnemonic, "lsl ");
11473
513
        func (stream, dis_style_immediate, "#%u", sh);
11474
513
      }
11475
1.12k
          func (stream, dis_style_text, "]");
11476
1.12k
          break;
11477
1.12k
        }
11478
3.58k
      else switch (op)
11479
3.58k
        {
11480
576
        case 0xE:  /* 8-bit positive immediate offset.  */
11481
576
          offset = i8;
11482
576
          break;
11483
11484
692
        case 0xC:  /* 8-bit negative immediate offset.  */
11485
692
          offset = -i8;
11486
692
          break;
11487
11488
314
        case 0xF:  /* 8-bit + preindex with wb.  */
11489
314
          offset = i8;
11490
314
          writeback = true;
11491
314
          break;
11492
11493
313
        case 0xD:  /* 8-bit - preindex with wb.  */
11494
313
          offset = -i8;
11495
313
          writeback = true;
11496
313
          break;
11497
11498
500
        case 0xB:  /* 8-bit + postindex.  */
11499
500
          offset = i8;
11500
500
          postind = true;
11501
500
          break;
11502
11503
332
        case 0x9:  /* 8-bit - postindex.  */
11504
332
          offset = -i8;
11505
332
          postind = true;
11506
332
          break;
11507
11508
853
        default:
11509
853
          func (stream, dis_style_text, ", <undefined>]");
11510
853
          goto skip;
11511
3.58k
        }
11512
11513
9.31k
      if (postind)
11514
832
        {
11515
832
          func (stream, dis_style_text, "], ");
11516
832
          func (stream, dis_style_immediate, "#%d", (int) offset);
11517
832
        }
11518
8.48k
      else
11519
8.48k
        {
11520
8.48k
          if (offset)
11521
7.50k
      {
11522
7.50k
        func (stream, dis_style_text, ", ");
11523
7.50k
        func (stream, dis_style_immediate, "#%d",
11524
7.50k
        (int) offset);
11525
7.50k
      }
11526
8.48k
          func (stream, dis_style_text, writeback ? "]!" : "]");
11527
8.48k
        }
11528
11529
9.31k
      if (Rn == 15)
11530
2.90k
        {
11531
2.90k
          func (stream, dis_style_comment_start, "\t@ ");
11532
2.90k
          info->print_address_func (((pc + 4) & ~3) + offset, info);
11533
2.90k
        }
11534
9.31k
    }
11535
10.1k
        skip:
11536
10.1k
    break;
11537
11538
0
        case 'A':
11539
0
    {
11540
0
      unsigned int U   = ! NEGATIVE_BIT_SET;
11541
0
      unsigned int W   = WRITEBACK_BIT_SET;
11542
0
      unsigned int Rn  = (given & 0x000f0000) >> 16;
11543
0
      unsigned int off = (given & 0x000000ff);
11544
11545
0
      func (stream, dis_style_text, "[");
11546
0
      func (stream, dis_style_register, "%s", arm_regnames[Rn]);
11547
11548
0
      if (PRE_BIT_SET)
11549
0
        {
11550
0
          if (off || !U)
11551
0
      {
11552
0
        func (stream, dis_style_text, ", ");
11553
0
        func (stream, dis_style_immediate, "#%c%u",
11554
0
        U ? '+' : '-', off * 4);
11555
0
        value_in_comment = off * 4 * (U ? 1 : -1);
11556
0
      }
11557
0
          func (stream, dis_style_text, "]");
11558
0
          if (W)
11559
0
      func (stream, dis_style_text, "!");
11560
0
        }
11561
0
      else
11562
0
        {
11563
0
          func (stream, dis_style_text, "], ");
11564
0
          if (W)
11565
0
      {
11566
0
        func (stream, dis_style_immediate, "#%c%u",
11567
0
        U ? '+' : '-', off * 4);
11568
0
        value_in_comment = off * 4 * (U ? 1 : -1);
11569
0
      }
11570
0
          else
11571
0
      {
11572
0
        func (stream, dis_style_text, "{");
11573
0
        func (stream, dis_style_immediate, "%u", off);
11574
0
        func (stream, dis_style_text, "}");
11575
0
        value_in_comment = off;
11576
0
      }
11577
0
        }
11578
0
    }
11579
0
    break;
11580
11581
11.2k
        case 'w':
11582
11.2k
    {
11583
11.2k
      unsigned int Sbit = (given & 0x01000000) >> 24;
11584
11.2k
      unsigned int type = (given & 0x00600000) >> 21;
11585
11586
11.2k
      switch (type)
11587
11.2k
        {
11588
1.88k
        case 0:
11589
1.88k
          func (stream, dis_style_mnemonic, Sbit ? "sb" : "b");
11590
1.88k
          break;
11591
1.49k
        case 1:
11592
1.49k
          func (stream, dis_style_mnemonic, Sbit ? "sh" : "h");
11593
1.49k
          break;
11594
2.05k
        case 2:
11595
2.05k
          if (Sbit)
11596
434
      func (stream, dis_style_text, "??");
11597
2.05k
          break;
11598
5.78k
        case 3:
11599
5.78k
          func (stream, dis_style_text, "??");
11600
5.78k
          break;
11601
11.2k
        }
11602
11.2k
    }
11603
11.2k
    break;
11604
11605
11.2k
        case 'n':
11606
482
    is_clrm = true;
11607
    /* Fall through.  */
11608
2.53k
        case 'm':
11609
2.53k
    {
11610
2.53k
      int started = 0;
11611
2.53k
      int reg;
11612
11613
2.53k
      func (stream, dis_style_text, "{");
11614
43.0k
      for (reg = 0; reg < 16; reg++)
11615
40.4k
        if ((given & (1 << reg)) != 0)
11616
23.7k
          {
11617
23.7k
      if (started)
11618
21.2k
        func (stream, dis_style_text, ", ");
11619
23.7k
      started = 1;
11620
23.7k
      if (is_clrm && reg == 13)
11621
0
        func (stream, dis_style_text, "(invalid: %s)",
11622
0
        arm_regnames[reg]);
11623
23.7k
      else if (is_clrm && reg == 15)
11624
379
        func (stream, dis_style_register, "%s", "APSR");
11625
23.4k
      else
11626
23.4k
        func (stream, dis_style_register, "%s",
11627
23.4k
        arm_regnames[reg]);
11628
23.7k
          }
11629
2.53k
      func (stream, dis_style_text, "}");
11630
2.53k
    }
11631
2.53k
    break;
11632
11633
227
        case 'E':
11634
227
    {
11635
227
      unsigned int msb = (given & 0x0000001f);
11636
227
      unsigned int lsb = 0;
11637
11638
227
      lsb |= (given & 0x000000c0u) >> 6;
11639
227
      lsb |= (given & 0x00007000u) >> 10;
11640
227
      func (stream, dis_style_immediate, "#%u", lsb);
11641
227
      func (stream, dis_style_text, ", ");
11642
227
      func (stream, dis_style_immediate, "#%u", msb - lsb + 1);
11643
227
    }
11644
227
    break;
11645
11646
324
        case 'F':
11647
324
    {
11648
324
      unsigned int width = (given & 0x0000001f) + 1;
11649
324
      unsigned int lsb = 0;
11650
11651
324
      lsb |= (given & 0x000000c0u) >> 6;
11652
324
      lsb |= (given & 0x00007000u) >> 10;
11653
324
      func (stream, dis_style_immediate, "#%u", lsb);
11654
324
      func (stream, dis_style_text, ", ");
11655
324
      func (stream, dis_style_immediate, "#%u", width);
11656
324
    }
11657
324
    break;
11658
11659
2.78k
        case 'G':
11660
2.78k
    {
11661
2.78k
      unsigned int boff = (((given & 0x07800000) >> 23) << 1);
11662
2.78k
      func (stream, dis_style_immediate, "%x", boff);
11663
2.78k
    }
11664
2.78k
    break;
11665
11666
452
        case 'W':
11667
452
    {
11668
452
      unsigned int immA = (given & 0x001f0000u) >> 16;
11669
452
      unsigned int immB = (given & 0x000007feu) >> 1;
11670
452
      unsigned int immC = (given & 0x00000800u) >> 11;
11671
452
      bfd_vma offset = 0;
11672
11673
452
      offset |= immA << 12;
11674
452
      offset |= immB << 2;
11675
452
      offset |= immC << 1;
11676
      /* Sign extend.  */
11677
452
      offset = (offset & 0x10000) ? offset - (1 << 17) : offset;
11678
11679
452
      info->print_address_func (pc + 4 + offset, info);
11680
452
    }
11681
452
    break;
11682
11683
1.21k
        case 'Y':
11684
1.21k
    {
11685
1.21k
      unsigned int immA = (given & 0x007f0000u) >> 16;
11686
1.21k
      unsigned int immB = (given & 0x000007feu) >> 1;
11687
1.21k
      unsigned int immC = (given & 0x00000800u) >> 11;
11688
1.21k
      bfd_vma offset = 0;
11689
11690
1.21k
      offset |= immA << 12;
11691
1.21k
      offset |= immB << 2;
11692
1.21k
      offset |= immC << 1;
11693
      /* Sign extend.  */
11694
1.21k
      offset = (offset & 0x40000) ? offset - (1 << 19) : offset;
11695
11696
1.21k
      info->print_address_func (pc + 4 + offset, info);
11697
1.21k
    }
11698
1.21k
    break;
11699
11700
1.08k
        case 'Z':
11701
1.08k
    {
11702
1.08k
      unsigned int immA = (given & 0x00010000u) >> 16;
11703
1.08k
      unsigned int immB = (given & 0x000007feu) >> 1;
11704
1.08k
      unsigned int immC = (given & 0x00000800u) >> 11;
11705
1.08k
      bfd_vma offset = 0;
11706
11707
1.08k
      offset |= immA << 12;
11708
1.08k
      offset |= immB << 2;
11709
1.08k
      offset |= immC << 1;
11710
      /* Sign extend.  */
11711
1.08k
      offset = (offset & 0x1000) ? offset - (1 << 13) : offset;
11712
11713
1.08k
      info->print_address_func (pc + 4 + offset, info);
11714
11715
1.08k
      unsigned int T    = (given & 0x00020000u) >> 17;
11716
1.08k
      unsigned int endoffset = (((given & 0x07800000) >> 23) << 1);
11717
1.08k
      unsigned int boffset   = (T == 1) ? 4 : 2;
11718
1.08k
      func (stream, dis_style_text, ", ");
11719
1.08k
      func (stream, dis_style_immediate, "%x",
11720
1.08k
      endoffset + boffset);
11721
1.08k
    }
11722
1.08k
    break;
11723
11724
1.02k
        case 'Q':
11725
1.02k
    {
11726
1.02k
      unsigned int immh = (given & 0x000007feu) >> 1;
11727
1.02k
      unsigned int imml = (given & 0x00000800u) >> 11;
11728
1.02k
      bfd_vma imm32 = 0;
11729
11730
1.02k
      imm32 |= immh << 2;
11731
1.02k
      imm32 |= imml << 1;
11732
11733
1.02k
      info->print_address_func (pc + 4 + imm32, info);
11734
1.02k
    }
11735
1.02k
    break;
11736
11737
227
        case 'P':
11738
227
    {
11739
227
      unsigned int immh = (given & 0x000007feu) >> 1;
11740
227
      unsigned int imml = (given & 0x00000800u) >> 11;
11741
227
      bfd_vma imm32 = 0;
11742
11743
227
      imm32 |= immh << 2;
11744
227
      imm32 |= imml << 1;
11745
11746
227
      info->print_address_func (pc + 4 - imm32, info);
11747
227
    }
11748
227
    break;
11749
11750
5.72k
        case 'b':
11751
5.72k
    {
11752
5.72k
      unsigned int S = (given & 0x04000000u) >> 26;
11753
5.72k
      unsigned int J1 = (given & 0x00002000u) >> 13;
11754
5.72k
      unsigned int J2 = (given & 0x00000800u) >> 11;
11755
5.72k
      bfd_vma offset = 0;
11756
11757
5.72k
      offset |= !S << 20;
11758
5.72k
      offset |= J2 << 19;
11759
5.72k
      offset |= J1 << 18;
11760
5.72k
      offset |= (given & 0x003f0000) >> 4;
11761
5.72k
      offset |= (given & 0x000007ff) << 1;
11762
5.72k
      offset -= (1 << 20);
11763
11764
5.72k
      bfd_vma target = pc + 4 + offset;
11765
5.72k
      info->print_address_func (target, info);
11766
11767
      /* Fill in instruction information.  */
11768
5.72k
      info->insn_info_valid = 1;
11769
5.72k
      info->insn_type = dis_branch;
11770
5.72k
      info->target = target;
11771
5.72k
    }
11772
5.72k
    break;
11773
11774
24.4k
        case 'B':
11775
24.4k
    {
11776
24.4k
      unsigned int S = (given & 0x04000000u) >> 26;
11777
24.4k
      unsigned int I1 = (given & 0x00002000u) >> 13;
11778
24.4k
      unsigned int I2 = (given & 0x00000800u) >> 11;
11779
24.4k
      bfd_vma offset = 0;
11780
11781
24.4k
      offset |= !S << 24;
11782
24.4k
      offset |= !(I1 ^ S) << 23;
11783
24.4k
      offset |= !(I2 ^ S) << 22;
11784
24.4k
      offset |= (given & 0x03ff0000u) >> 4;
11785
24.4k
      offset |= (given & 0x000007ffu) << 1;
11786
24.4k
      offset -= (1 << 24);
11787
24.4k
      offset += pc + 4;
11788
11789
      /* BLX target addresses are always word aligned.  */
11790
24.4k
      if ((given & 0x00001000u) == 0)
11791
7.88k
          offset &= ~2u;
11792
11793
24.4k
      info->print_address_func (offset, info);
11794
11795
      /* Fill in instruction information.  */
11796
24.4k
      info->insn_info_valid = 1;
11797
24.4k
      info->insn_type = dis_branch;
11798
24.4k
      info->target = offset;
11799
24.4k
    }
11800
24.4k
    break;
11801
11802
2.19k
        case 's':
11803
2.19k
    {
11804
2.19k
      unsigned int shift = 0;
11805
11806
2.19k
      shift |= (given & 0x000000c0u) >> 6;
11807
2.19k
      shift |= (given & 0x00007000u) >> 10;
11808
2.19k
      if (WRITEBACK_BIT_SET)
11809
252
        {
11810
252
          func (stream, dis_style_text, ", ");
11811
252
          func (stream, dis_style_sub_mnemonic, "asr ");
11812
252
          func (stream, dis_style_immediate, "#%u", shift);
11813
252
        }
11814
1.94k
      else if (shift)
11815
838
        {
11816
838
          func (stream, dis_style_text, ", ");
11817
838
          func (stream, dis_style_sub_mnemonic, "lsl ");
11818
838
          func (stream, dis_style_immediate, "#%u", shift);
11819
838
        }
11820
      /* else print nothing - lsl #0 */
11821
2.19k
    }
11822
2.19k
    break;
11823
11824
418
        case 'R':
11825
418
    {
11826
418
      unsigned int rot = (given & 0x00000030) >> 4;
11827
11828
418
      if (rot)
11829
212
        {
11830
212
          func (stream, dis_style_text, ", ");
11831
212
          func (stream, dis_style_sub_mnemonic, "ror ");
11832
212
          func (stream, dis_style_immediate, "#%u", rot * 8);
11833
212
        }
11834
418
    }
11835
418
    break;
11836
11837
986
        case 'U':
11838
986
    if ((given & 0xf0) == 0x60)
11839
438
      {
11840
438
        switch (given & 0xf)
11841
438
          {
11842
210
          case 0xf:
11843
210
      func (stream, dis_style_sub_mnemonic, "sy");
11844
210
      break;
11845
228
          default:
11846
228
      func (stream, dis_style_immediate, "#%d",
11847
228
            (int) given & 0xf);
11848
228
      break;
11849
438
          }
11850
438
      }
11851
548
    else
11852
548
      {
11853
548
        const char * opt = data_barrier_option (given & 0xf);
11854
548
        if (opt != NULL)
11855
283
          func (stream, dis_style_sub_mnemonic, "%s", opt);
11856
265
        else
11857
265
          func (stream, dis_style_immediate, "#%d",
11858
265
          (int) given & 0xf);
11859
548
       }
11860
986
    break;
11861
11862
8.54k
        case 'C':
11863
8.54k
    if ((given & 0xff) == 0)
11864
807
      {
11865
807
        func (stream, dis_style_register, "%cPSR_",
11866
807
        (given & 0x100000) ? 'S' : 'C');
11867
11868
807
        if (given & 0x800)
11869
305
          func (stream, dis_style_register, "f");
11870
807
        if (given & 0x400)
11871
380
          func (stream, dis_style_register, "s");
11872
807
        if (given & 0x200)
11873
396
          func (stream, dis_style_register, "x");
11874
807
        if (given & 0x100)
11875
457
          func (stream, dis_style_register, "c");
11876
807
      }
11877
7.73k
    else if ((given & 0x20) == 0x20)
11878
5.50k
      {
11879
5.50k
        char const* name;
11880
5.50k
        unsigned sysm = (given & 0xf00) >> 8;
11881
11882
5.50k
        sysm |= (given & 0x30);
11883
5.50k
        sysm |= (given & 0x00100000) >> 14;
11884
5.50k
        name = banked_regname (sysm);
11885
11886
5.50k
        if (name != NULL)
11887
4.60k
          func (stream, dis_style_register, "%s", name);
11888
896
        else
11889
896
          func (stream, dis_style_text,
11890
896
          "(UNDEF: %lu)", (unsigned long) sysm);
11891
5.50k
      }
11892
2.23k
    else
11893
2.23k
      {
11894
2.23k
        func (stream, dis_style_register, "%s",
11895
2.23k
        psr_name (given & 0xff));
11896
2.23k
      }
11897
8.54k
    break;
11898
11899
10.6k
        case 'D':
11900
10.6k
    if (((given & 0xff) == 0)
11901
10.6k
        || ((given & 0x20) == 0x20))
11902
5.43k
      {
11903
5.43k
        char const* name;
11904
5.43k
        unsigned sm = (given & 0xf0000) >> 16;
11905
11906
5.43k
        sm |= (given & 0x30);
11907
5.43k
        sm |= (given & 0x00100000) >> 14;
11908
5.43k
        name = banked_regname (sm);
11909
11910
5.43k
        if (name != NULL)
11911
3.23k
          func (stream, dis_style_register, "%s", name);
11912
2.19k
        else
11913
2.19k
          func (stream, dis_style_text,
11914
2.19k
          "(UNDEF: %lu)", (unsigned long) sm);
11915
5.43k
      }
11916
5.25k
    else
11917
5.25k
      func (stream, dis_style_register, "%s",
11918
5.25k
      psr_name (given & 0xff));
11919
10.6k
    break;
11920
11921
207k
        case '0': case '1': case '2': case '3': case '4':
11922
240k
        case '5': case '6': case '7': case '8': case '9':
11923
240k
    {
11924
240k
      int width;
11925
240k
      unsigned long val;
11926
11927
240k
      c = arm_decode_bitfield (c, given, &val, &width);
11928
11929
240k
      switch (*c)
11930
240k
        {
11931
1.02k
        case 's':
11932
1.02k
          if (val <= 3)
11933
1.02k
      func (stream, dis_style_mnemonic, "%s",
11934
1.02k
            mve_vec_sizename[val]);
11935
0
          else
11936
0
      func (stream, dis_style_text, "<undef size>");
11937
1.02k
          break;
11938
11939
1.04k
        case 'd':
11940
1.04k
          func (stream, base_style, "%lu", val);
11941
1.04k
          value_in_comment = val;
11942
1.04k
          break;
11943
11944
1.25k
        case 'D':
11945
1.25k
          func (stream, dis_style_immediate, "%lu", val + 1);
11946
1.25k
          value_in_comment = val + 1;
11947
1.25k
          break;
11948
11949
4.66k
        case 'W':
11950
4.66k
          func (stream, dis_style_immediate, "%lu", val * 4);
11951
4.66k
          value_in_comment = val * 4;
11952
4.66k
          break;
11953
11954
1.05k
        case 'S':
11955
1.05k
          if (val == 13)
11956
536
      is_unpredictable = true;
11957
          /* Fall through.  */
11958
3.38k
        case 'R':
11959
3.38k
          if (val == 15)
11960
565
      is_unpredictable = true;
11961
          /* Fall through.  */
11962
76.7k
        case 'r':
11963
76.7k
          func (stream, dis_style_register, "%s",
11964
76.7k
          arm_regnames[val]);
11965
76.7k
          break;
11966
11967
6.81k
        case 'c':
11968
6.81k
          func (stream, base_style, "%s", arm_conditional[val]);
11969
6.81k
          break;
11970
11971
12.8k
        case '\'':
11972
12.8k
          c++;
11973
12.8k
          if (val == ((1ul << width) - 1))
11974
5.99k
      func (stream, base_style, "%c", *c);
11975
12.8k
          break;
11976
11977
4.64k
        case '`':
11978
4.64k
          c++;
11979
4.64k
          if (val == 0)
11980
1.28k
      func (stream, dis_style_immediate, "%c", *c);
11981
4.64k
          break;
11982
11983
833
        case '?':
11984
833
          func (stream, dis_style_mnemonic, "%c",
11985
833
          c[(1 << width) - (int) val]);
11986
833
          c += 1 << width;
11987
833
          break;
11988
11989
130k
        case 'x':
11990
130k
          func (stream, dis_style_immediate, "0x%lx",
11991
130k
          val & 0xffffffffUL);
11992
130k
          break;
11993
11994
0
        default:
11995
0
          abort ();
11996
240k
        }
11997
240k
    }
11998
240k
    break;
11999
12000
240k
        case 'L':
12001
    /* PR binutils/12534
12002
       If we have a PC relative offset in an LDRD or STRD
12003
       instructions then display the decoded address.  */
12004
4.64k
    if (((given >> 16) & 0xf) == 0xf)
12005
948
      {
12006
948
        bfd_vma offset = (given & 0xff) * 4;
12007
12008
948
        if ((given & (1 << 23)) == 0)
12009
394
          offset = - offset;
12010
948
        func (stream, dis_style_comment_start, "\t@ ");
12011
948
        info->print_address_func ((pc & ~3) + 4 + offset, info);
12012
948
      }
12013
4.64k
    break;
12014
12015
0
        default:
12016
0
    abort ();
12017
474k
        }
12018
474k
    }
12019
12020
222k
  if (value_in_comment > 32 || value_in_comment < -16)
12021
12.0k
    func (stream, dis_style_comment_start, "\t@ 0x%lx",
12022
12.0k
    value_in_comment);
12023
12024
222k
  if (is_unpredictable)
12025
835
    func (stream, dis_style_comment_start, UNPREDICTABLE_INSTRUCTION);
12026
12027
222k
  return;
12028
222k
      }
12029
12030
  /* No match.  */
12031
0
  func (stream, dis_style_comment_start, UNKNOWN_INSTRUCTION_32BIT,
12032
0
  (unsigned) given);
12033
0
  return;
12034
222k
}
12035
12036
/* Print data bytes on INFO->STREAM.  */
12037
12038
static void
12039
print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED,
12040
     struct disassemble_info *info,
12041
     long given)
12042
0
{
12043
0
  fprintf_styled_ftype func = info->fprintf_styled_func;
12044
12045
0
  switch (info->bytes_per_chunk)
12046
0
    {
12047
0
    case 1:
12048
0
      func (info->stream, dis_style_assembler_directive, ".byte");
12049
0
      func (info->stream, dis_style_text, "\t");
12050
0
      func (info->stream, dis_style_immediate, "0x%02lx", given);
12051
0
      break;
12052
0
    case 2:
12053
0
      func (info->stream, dis_style_assembler_directive, ".short");
12054
0
      func (info->stream, dis_style_text, "\t");
12055
0
      func (info->stream, dis_style_immediate, "0x%04lx", given);
12056
0
      break;
12057
0
    case 4:
12058
0
      func (info->stream, dis_style_assembler_directive, ".word");
12059
0
      func (info->stream, dis_style_text, "\t");
12060
0
      func (info->stream, dis_style_immediate, "0x%08lx", given);
12061
0
      break;
12062
0
    default:
12063
0
      abort ();
12064
0
    }
12065
0
}
12066
12067
/* Disallow mapping symbols ($a, $b, $d, $t etc) from
12068
   being displayed in symbol relative addresses.
12069
12070
   Also disallow private symbol, with __tagsym$$ prefix,
12071
   from ARM RVCT toolchain being displayed.  */
12072
12073
bool
12074
arm_symbol_is_valid (asymbol * sym,
12075
         struct disassemble_info * info ATTRIBUTE_UNUSED)
12076
84.3k
{
12077
84.3k
  const char * name;
12078
12079
84.3k
  if (sym == NULL)
12080
0
    return false;
12081
12082
84.3k
  name = bfd_asymbol_name (sym);
12083
12084
84.3k
  return (name && *name != '$' && strncmp (name, "__tagsym$$", 10));
12085
84.3k
}
12086
12087
/* Parse the string of disassembler options.  */
12088
12089
static void
12090
parse_arm_disassembler_options (const char *options)
12091
17.4k
{
12092
17.4k
  const char *opt;
12093
12094
17.4k
  force_thumb = false;
12095
17.4k
  FOR_EACH_DISASSEMBLER_OPTION (opt, options)
12096
26.0k
    {
12097
26.0k
      if (startswith (opt, "reg-names-"))
12098
278
  {
12099
278
    unsigned int i;
12100
2.30k
    for (i = 0; i < NUM_ARM_OPTIONS; i++)
12101
2.08k
      if (disassembler_options_cmp (opt, regnames[i].name) == 0)
12102
60
        {
12103
60
    regname_selected = i;
12104
60
    break;
12105
60
        }
12106
12107
278
    if (i >= NUM_ARM_OPTIONS)
12108
      /* xgettext: c-format */
12109
218
      opcodes_error_handler (_("unrecognised register name set: %s"),
12110
218
           opt);
12111
278
  }
12112
25.7k
      else if (startswith (opt, "force-thumb"))
12113
12.6k
  force_thumb = 1;
12114
13.0k
      else if (startswith (opt, "no-force-thumb"))
12115
34
  force_thumb = 0;
12116
13.0k
      else if (startswith (opt, "coproc"))
12117
518
  {
12118
518
    const char *procptr = opt + sizeof ("coproc") - 1;
12119
518
    char *endptr;
12120
518
    uint8_t coproc_number = strtol (procptr, &endptr, 10);
12121
518
    if (endptr != procptr + 1 || coproc_number > 7)
12122
102
      {
12123
102
        opcodes_error_handler (_("cde coprocessor not between 0-7: %s"),
12124
102
             opt);
12125
102
        continue;
12126
102
      }
12127
416
    if (*endptr != '=')
12128
54
      {
12129
54
        opcodes_error_handler (_("coproc must have an argument: %s"),
12130
54
             opt);
12131
54
        continue;
12132
54
      }
12133
362
    endptr += 1;
12134
362
    if (startswith (endptr, "generic"))
12135
8
      cde_coprocs &= ~(1 << coproc_number);
12136
354
    else if (startswith (endptr, "cde")
12137
354
       || startswith (endptr, "CDE"))
12138
76
      cde_coprocs |= (1 << coproc_number);
12139
278
    else
12140
278
      {
12141
278
        opcodes_error_handler (
12142
278
      _("coprocN argument takes options \"generic\","
12143
278
        " \"cde\", or \"CDE\": %s"), opt);
12144
278
      }
12145
362
  }
12146
12.5k
      else
12147
  /* xgettext: c-format */
12148
12.5k
  opcodes_error_handler (_("unrecognised disassembler option: %s"), opt);
12149
26.0k
    }
12150
12151
17.4k
  return;
12152
17.4k
}
12153
12154
static bool
12155
mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
12156
       enum map_type *map_symbol);
12157
12158
/* Search back through the insn stream to determine if this instruction is
12159
   conditionally executed.  */
12160
12161
static void
12162
find_ifthen_state (bfd_vma pc,
12163
       struct disassemble_info *info,
12164
       bool little)
12165
12.8k
{
12166
12.8k
  unsigned char b[2];
12167
12.8k
  unsigned int insn;
12168
12.8k
  int status;
12169
  /* COUNT is twice the number of instructions seen.  It will be odd if we
12170
     just crossed an instruction boundary.  */
12171
12.8k
  int count;
12172
12.8k
  int it_count;
12173
12.8k
  unsigned int seen_it;
12174
12.8k
  bfd_vma addr;
12175
12176
12.8k
  ifthen_address = pc;
12177
12.8k
  ifthen_state = 0;
12178
12179
12.8k
  addr = pc;
12180
12.8k
  count = 1;
12181
12.8k
  it_count = 0;
12182
12.8k
  seen_it = 0;
12183
  /* Scan backwards looking for IT instructions, keeping track of where
12184
     instruction boundaries are.  We don't know if something is actually an
12185
     IT instruction until we find a definite instruction boundary.  */
12186
12.8k
  for (;;)
12187
13.2k
    {
12188
13.2k
      if (addr == 0 || info->symbol_at_address_func (addr, info))
12189
89
  {
12190
    /* A symbol must be on an instruction boundary, and will not
12191
       be within an IT block.  */
12192
89
    if (seen_it && (count & 1))
12193
0
      break;
12194
12195
89
    return;
12196
89
  }
12197
13.1k
      addr -= 2;
12198
13.1k
      status = info->read_memory_func (addr, (bfd_byte *) b, 2, info);
12199
13.1k
      if (status)
12200
12.5k
  return;
12201
12202
532
      if (little)
12203
8
  insn = (b[0]) | (b[1] << 8);
12204
524
      else
12205
524
  insn = (b[1]) | (b[0] << 8);
12206
532
      if (seen_it)
12207
0
  {
12208
0
    if ((insn & 0xf800) < 0xe800)
12209
0
      {
12210
        /* Addr + 2 is an instruction boundary.  See if this matches
12211
           the expected boundary based on the position of the last
12212
     IT candidate.  */
12213
0
        if (count & 1)
12214
0
    break;
12215
0
        seen_it = 0;
12216
0
      }
12217
0
  }
12218
532
      if ((insn & 0xff00) == 0xbf00 && (insn & 0xf) != 0)
12219
0
  {
12220
0
    enum map_type type = MAP_ARM;
12221
0
    bool found = mapping_symbol_for_insn (addr, info, &type);
12222
12223
0
    if (!found || (found && type == MAP_THUMB))
12224
0
      {
12225
        /* This could be an IT instruction.  */
12226
0
        seen_it = insn;
12227
0
        it_count = count >> 1;
12228
0
      }
12229
0
  }
12230
532
      if ((insn & 0xf800) >= 0xe800)
12231
0
  count++;
12232
532
      else
12233
532
  count = (count + 2) | 1;
12234
      /* IT blocks contain at most 4 instructions.  */
12235
532
      if (count >= 8 && !seen_it)
12236
133
  return;
12237
532
    }
12238
  /* We found an IT instruction.  */
12239
0
  ifthen_state = (seen_it & 0xe0) | ((seen_it << it_count) & 0x1f);
12240
0
  if ((ifthen_state & 0xf) == 0)
12241
0
    ifthen_state = 0;
12242
0
}
12243
12244
/* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a
12245
   mapping symbol.  */
12246
12247
static int
12248
is_mapping_symbol (struct disassemble_info *info,
12249
       int n,
12250
       enum map_type *map_type)
12251
128k
{
12252
128k
  const char *name = bfd_asymbol_name (info->symtab[n]);
12253
12254
128k
  if (name[0] == '$'
12255
128k
      && (name[1] == 'a' || name[1] == 't' || name[1] == 'd')
12256
128k
      && (name[2] == 0 || name[2] == '.'))
12257
0
    {
12258
0
      *map_type = ((name[1] == 'a') ? MAP_ARM
12259
0
       : (name[1] == 't') ? MAP_THUMB
12260
0
       : MAP_DATA);
12261
0
      return true;
12262
0
    }
12263
12264
128k
  return false;
12265
128k
}
12266
12267
/* Try to infer the code type (ARM or Thumb) from a mapping symbol.
12268
   Returns nonzero if *MAP_TYPE was set.  */
12269
12270
static int
12271
get_map_sym_type (struct disassemble_info *info,
12272
      int n,
12273
      enum map_type *map_type)
12274
15.7M
{
12275
  /* If the symbol is in a different section, ignore it.  */
12276
15.7M
  if (info->section != NULL && info->section != info->symtab[n]->section)
12277
15.6M
    return false;
12278
12279
128k
  return is_mapping_symbol (info, n, map_type);
12280
15.7M
}
12281
12282
/* Try to infer the code type (ARM or Thumb) from a non-mapping symbol.
12283
   Returns nonzero if *MAP_TYPE was set.  */
12284
12285
static int
12286
get_sym_code_type (struct disassemble_info *info,
12287
       int n,
12288
       enum map_type *map_type)
12289
76.2k
{
12290
76.2k
  elf_symbol_type *es;
12291
76.2k
  unsigned int type;
12292
76.2k
  asymbol * sym;
12293
12294
  /* If the symbol is in a different section, ignore it.  */
12295
76.2k
  if (info->section != NULL && info->section != info->symtab[n]->section)
12296
0
    return false;
12297
12298
  /* PR 30230: Reject non-ELF symbols, eg synthetic ones.  */
12299
76.2k
  sym = info->symtab[n];
12300
76.2k
  if (bfd_asymbol_flavour (sym) != bfd_target_elf_flavour)
12301
987
    return false;
12302
12303
75.2k
  es = (elf_symbol_type *) sym;
12304
75.2k
  type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
12305
12306
  /* If the symbol has function type then use that.  */
12307
75.2k
  if (type == STT_FUNC || type == STT_GNU_IFUNC)
12308
47.7k
    {
12309
47.7k
      if (ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
12310
47.7k
    == ST_BRANCH_TO_THUMB)
12311
47.7k
  *map_type = MAP_THUMB;
12312
15
      else
12313
15
  *map_type = MAP_ARM;
12314
47.7k
      return true;
12315
47.7k
    }
12316
12317
27.4k
  return false;
12318
75.2k
}
12319
12320
/* Search the mapping symbol state for instruction at pc.  This is only
12321
   applicable for elf target.
12322
12323
   There is an assumption Here, info->private_data contains the correct AND
12324
   up-to-date information about current scan process.  The information will be
12325
   used to speed this search process.
12326
12327
   Return TRUE if the mapping state can be determined, and map_symbol
12328
   will be updated accordingly.  Otherwise, return FALSE.  */
12329
12330
static bool
12331
mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
12332
       enum map_type *map_symbol)
12333
361k
{
12334
361k
  bfd_vma addr, section_vma = 0;
12335
361k
  int n, last_sym = -1;
12336
361k
  bool found = false;
12337
361k
  bool can_use_search_opt_p = false;
12338
12339
  /* Sanity check.  */
12340
361k
  if (info == NULL)
12341
0
    return false;
12342
12343
  /* Default to DATA.  A text section is required by the ABI to contain an
12344
     INSN mapping symbol at the start.  A data section has no such
12345
     requirement, hence if no mapping symbol is found the section must
12346
     contain only data.  This however isn't very useful if the user has
12347
     fully stripped the binaries.  If this is the case use the section
12348
     attributes to determine the default.  If we have no section default to
12349
     INSN as well, as we may be disassembling some raw bytes on a baremetal
12350
     HEX file or similar.  */
12351
361k
  enum map_type type = MAP_DATA;
12352
361k
  if ((info->section && info->section->flags & SEC_CODE) || !info->section)
12353
160k
    type = MAP_ARM;
12354
361k
  struct arm_private_data *private_data;
12355
12356
361k
  if (info->private_data == NULL || info->symtab == NULL
12357
361k
      || info->symtab_size == 0
12358
361k
      || bfd_asymbol_flavour (*info->symtab) != bfd_target_elf_flavour)
12359
0
    return false;
12360
12361
361k
  private_data = info->private_data;
12362
12363
  /* First, look for mapping symbols.  */
12364
361k
  if (pc <= private_data->last_mapping_addr)
12365
32
    private_data->last_mapping_sym = -1;
12366
12367
  /* Start scanning at the start of the function, or wherever
12368
     we finished last time.  */
12369
361k
  n = info->symtab_pos + 1;
12370
12371
  /* If the last stop offset is different from the current one it means we
12372
     are disassembling a different glob of bytes.  As such the optimization
12373
     would not be safe and we should start over.  */
12374
361k
  can_use_search_opt_p
12375
361k
    = (private_data->last_mapping_sym >= 0
12376
361k
       && info->stop_offset == private_data->last_stop_offset);
12377
12378
361k
  if (n >= private_data->last_mapping_sym && can_use_search_opt_p)
12379
47.7k
    n = private_data->last_mapping_sym;
12380
12381
  /* Look down while we haven't passed the location being disassembled.
12382
     The reason for this is that there's no defined order between a symbol
12383
     and an mapping symbol that may be at the same address.  We may have to
12384
     look at least one position ahead.  */
12385
15.5M
  for (; n < info->symtab_size; n++)
12386
15.5M
    {
12387
15.5M
      addr = bfd_asymbol_value (info->symtab[n]);
12388
15.5M
      if (addr > pc)
12389
361k
  break;
12390
15.1M
      if (get_map_sym_type (info, n, &type))
12391
0
  {
12392
0
    last_sym = n;
12393
0
    found = true;
12394
0
  }
12395
15.1M
    }
12396
12397
361k
  if (!found)
12398
361k
    {
12399
361k
      n = info->symtab_pos;
12400
361k
      if (n >= private_data->last_mapping_sym && can_use_search_opt_p)
12401
47.7k
  n = private_data->last_mapping_sym;
12402
12403
      /* No mapping symbol found at this address.  Look backwards
12404
   for a preceeding one, but don't go pass the section start
12405
   otherwise a data section with no mapping symbol can pick up
12406
   a text mapping symbol of a preceeding section.  The documentation
12407
   says section can be NULL, in which case we will seek up all the
12408
   way to the top.  */
12409
361k
      if (info->section)
12410
361k
  section_vma = info->section->vma;
12411
12412
976k
      for (; n >= 0; n--)
12413
665k
  {
12414
665k
    addr = bfd_asymbol_value (info->symtab[n]);
12415
665k
    if (addr < section_vma)
12416
50.6k
      break;
12417
12418
615k
    if (get_map_sym_type (info, n, &type))
12419
0
      {
12420
0
        last_sym = n;
12421
0
        found = true;
12422
0
        break;
12423
0
      }
12424
615k
  }
12425
361k
    }
12426
12427
  /* If no mapping symbol was found, try looking up without a mapping
12428
     symbol.  This is done by walking up from the current PC to the nearest
12429
     symbol.  We don't actually have to loop here since symtab_pos will
12430
     contain the nearest symbol already.  */
12431
361k
  if (!found)
12432
361k
    {
12433
361k
      n = info->symtab_pos;
12434
361k
      if (n >= 0 && get_sym_code_type (info, n, &type))
12435
47.7k
  {
12436
47.7k
    last_sym = n;
12437
47.7k
    found = true;
12438
47.7k
  }
12439
361k
    }
12440
12441
361k
  private_data->last_mapping_sym = last_sym;
12442
361k
  private_data->last_type = type;
12443
361k
  private_data->last_stop_offset = info->stop_offset;
12444
12445
361k
  *map_symbol = type;
12446
361k
  return found;
12447
361k
}
12448
12449
/* Given a bfd_mach_arm_XXX value, this function fills in the fields
12450
   of the supplied arm_feature_set structure with bitmasks indicating
12451
   the supported base architectures and coprocessor extensions.
12452
12453
   FIXME: This could more efficiently implemented as a constant array,
12454
   although it would also be less robust.  */
12455
12456
static void
12457
select_arm_features (unsigned long mach,
12458
         arm_feature_set * features)
12459
895
{
12460
895
  arm_feature_set arch_fset;
12461
895
  const arm_feature_set fpu_any = FPU_ANY;
12462
12463
895
#undef ARM_SET_FEATURES
12464
895
#define ARM_SET_FEATURES(FSET) \
12465
895
  {             \
12466
895
    const arm_feature_set fset = FSET;      \
12467
895
    arch_fset = fset;         \
12468
895
  }
12469
12470
  /* When several architecture versions share the same bfd_mach_arm_XXX value
12471
     the most featureful is chosen.  */
12472
895
  switch (mach)
12473
895
    {
12474
0
    case bfd_mach_arm_2:  ARM_SET_FEATURES (ARM_ARCH_V2); break;
12475
0
    case bfd_mach_arm_2a:  ARM_SET_FEATURES (ARM_ARCH_V2S); break;
12476
0
    case bfd_mach_arm_3:  ARM_SET_FEATURES (ARM_ARCH_V3); break;
12477
0
    case bfd_mach_arm_3M:  ARM_SET_FEATURES (ARM_ARCH_V3M); break;
12478
0
    case bfd_mach_arm_4:  ARM_SET_FEATURES (ARM_ARCH_V4); break;
12479
0
    case bfd_mach_arm_ep9312:
12480
0
    case bfd_mach_arm_4T:  ARM_SET_FEATURES (ARM_ARCH_V4T); break;
12481
0
    case bfd_mach_arm_5:  ARM_SET_FEATURES (ARM_ARCH_V5); break;
12482
0
    case bfd_mach_arm_5T:  ARM_SET_FEATURES (ARM_ARCH_V5T); break;
12483
0
    case bfd_mach_arm_5TE:  ARM_SET_FEATURES (ARM_ARCH_V5TE); break;
12484
0
    case bfd_mach_arm_XScale:  ARM_SET_FEATURES (ARM_ARCH_XSCALE); break;
12485
0
    case bfd_mach_arm_iWMMXt:  ARM_SET_FEATURES (ARM_ARCH_IWMMXT); break;
12486
0
    case bfd_mach_arm_iWMMXt2:  ARM_SET_FEATURES (ARM_ARCH_IWMMXT2); break;
12487
0
    case bfd_mach_arm_5TEJ:  ARM_SET_FEATURES (ARM_ARCH_V5TEJ); break;
12488
0
    case bfd_mach_arm_6:  ARM_SET_FEATURES (ARM_ARCH_V6); break;
12489
0
    case bfd_mach_arm_6KZ:  ARM_SET_FEATURES (ARM_ARCH_V6KZ); break;
12490
0
    case bfd_mach_arm_6T2:  ARM_SET_FEATURES (ARM_ARCH_V6KZT2); break;
12491
0
    case bfd_mach_arm_6K:  ARM_SET_FEATURES (ARM_ARCH_V6K); break;
12492
0
    case bfd_mach_arm_7:  ARM_SET_FEATURES (ARM_ARCH_V7VE); break;
12493
0
    case bfd_mach_arm_6M:  ARM_SET_FEATURES (ARM_ARCH_V6M); break;
12494
0
    case bfd_mach_arm_6SM:  ARM_SET_FEATURES (ARM_ARCH_V6SM); break;
12495
0
    case bfd_mach_arm_7EM:  ARM_SET_FEATURES (ARM_ARCH_V7EM); break;
12496
0
    case bfd_mach_arm_8:
12497
0
  {
12498
    /* Add bits for extensions that Armv8.6-A recognizes.  */
12499
0
    arm_feature_set armv8_6_ext_fset
12500
0
      = ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST);
12501
0
    ARM_SET_FEATURES (ARM_ARCH_V8_6A);
12502
0
    ARM_MERGE_FEATURE_SETS (arch_fset, arch_fset, armv8_6_ext_fset);
12503
0
    break;
12504
0
  }
12505
0
    case bfd_mach_arm_8R:  ARM_SET_FEATURES (ARM_ARCH_V8R); break;
12506
0
    case bfd_mach_arm_8M_BASE:  ARM_SET_FEATURES (ARM_ARCH_V8M_BASE); break;
12507
0
    case bfd_mach_arm_8M_MAIN:  ARM_SET_FEATURES (ARM_ARCH_V8M_MAIN); break;
12508
0
    case bfd_mach_arm_8_1M_MAIN:
12509
0
      ARM_SET_FEATURES (ARM_ARCH_V8_1M_MAIN);
12510
0
      arm_feature_set mve_all
12511
0
  = ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE | ARM_EXT2_MVE_FP);
12512
0
      ARM_MERGE_FEATURE_SETS (arch_fset, arch_fset, mve_all);
12513
0
      force_thumb = 1;
12514
0
      break;
12515
0
    case bfd_mach_arm_9:         ARM_SET_FEATURES (ARM_ARCH_V9A); break;
12516
      /* If the machine type is unknown allow all architecture types and all
12517
   extensions, with the exception of MVE as that clashes with NEON.  */
12518
895
    case bfd_mach_arm_unknown:
12519
895
      ARM_SET_FEATURES (ARM_ARCH_UNKNOWN);
12520
895
      break;
12521
0
    default:
12522
0
      abort ();
12523
895
    }
12524
895
#undef ARM_SET_FEATURES
12525
12526
  /* None of the feature bits related to -mfpu have an impact on Tag_CPU_arch
12527
     and thus on bfd_mach_arm_XXX value.  Therefore for a given
12528
     bfd_mach_arm_XXX value all coprocessor feature bits should be allowed.  */
12529
895
  ARM_MERGE_FEATURE_SETS (*features, arch_fset, fpu_any);
12530
895
}
12531
12532
12533
/* NOTE: There are no checks in these routines that
12534
   the relevant number of data bytes exist.  */
12535
12536
static int
12537
print_insn (bfd_vma pc, struct disassemble_info *info, bool little)
12538
4.96M
{
12539
4.96M
  unsigned char b[4];
12540
4.96M
  unsigned long given;
12541
4.96M
  int status;
12542
4.96M
  int is_thumb = false;
12543
4.96M
  int is_data = false;
12544
4.96M
  int little_code;
12545
4.96M
  unsigned int  size = 4;
12546
4.96M
  void (*printer) (bfd_vma, struct disassemble_info *, long);
12547
4.96M
  bool found = false;
12548
4.96M
  struct arm_private_data *private_data;
12549
12550
  /* Clear instruction information field.  */
12551
4.96M
  info->insn_info_valid = 0;
12552
4.96M
  info->branch_delay_insns = 0;
12553
4.96M
  info->data_size = 0;
12554
4.96M
  info->insn_type = dis_noninsn;
12555
4.96M
  info->target = 0;
12556
4.96M
  info->target2 = 0;
12557
12558
4.96M
  if (info->disassembler_options)
12559
17.4k
    {
12560
17.4k
      parse_arm_disassembler_options (info->disassembler_options);
12561
12562
      /* To avoid repeated parsing of these options, we remove them here.  */
12563
17.4k
      info->disassembler_options = NULL;
12564
17.4k
    }
12565
12566
  /* PR 10288: Control which instructions will be disassembled.  */
12567
4.96M
  if (info->private_data == NULL)
12568
895
    {
12569
895
      static struct arm_private_data private;
12570
12571
895
      if ((info->flags & USER_SPECIFIED_MACHINE_TYPE) == 0)
12572
  /* If the user did not use the -m command line switch then default to
12573
     disassembling all types of ARM instruction.
12574
12575
     The info->mach value has to be ignored as this will be based on
12576
     the default archictecture for the target and/or hints in the notes
12577
     section, but it will never be greater than the current largest arm
12578
     machine value (iWMMXt2), which is only equivalent to the V5TE
12579
     architecture.  ARM architectures have advanced beyond the machine
12580
     value encoding, and these newer architectures would be ignored if
12581
     the machine value was used.
12582
12583
     Ie the -m switch is used to restrict which instructions will be
12584
     disassembled.  If it is necessary to use the -m switch to tell
12585
     objdump that an ARM binary is being disassembled, eg because the
12586
     input is a raw binary file, but it is also desired to disassemble
12587
     all ARM instructions then use "-marm".  This will select the
12588
     "unknown" arm architecture which is compatible with any ARM
12589
     instruction.  */
12590
895
    info->mach = bfd_mach_arm_unknown;
12591
12592
      /* Compute the architecture bitmask from the machine number.
12593
   Note: This assumes that the machine number will not change
12594
   during disassembly....  */
12595
895
      select_arm_features (info->mach, & private.features);
12596
12597
895
      private.last_mapping_sym = -1;
12598
895
      private.last_mapping_addr = 0;
12599
895
      private.last_stop_offset = 0;
12600
12601
895
      info->private_data = & private;
12602
895
    }
12603
12604
4.96M
  private_data = info->private_data;
12605
12606
  /* Decide if our code is going to be little-endian, despite what the
12607
     function argument might say.  */
12608
4.96M
  little_code = ((info->endian_code == BFD_ENDIAN_LITTLE) || little);
12609
12610
  /* For ELF, consult the symbol table to determine what kind of code
12611
     or data we have.  */
12612
4.96M
  if (info->symtab_size != 0
12613
4.96M
      && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour)
12614
361k
    {
12615
361k
      bfd_vma addr;
12616
361k
      int n;
12617
361k
      int last_sym = -1;
12618
361k
      enum map_type type = MAP_ARM;
12619
12620
361k
      found = mapping_symbol_for_insn (pc, info, &type);
12621
361k
      last_sym = private_data->last_mapping_sym;
12622
12623
361k
      is_thumb = (private_data->last_type == MAP_THUMB);
12624
361k
      is_data = (private_data->last_type == MAP_DATA);
12625
12626
      /* Look a little bit ahead to see if we should print out
12627
   two or four bytes of data.  If there's a symbol,
12628
   mapping or otherwise, after two bytes then don't
12629
   print more.  */
12630
361k
      if (is_data)
12631
200k
  {
12632
200k
    size = 4 - (pc & 3);
12633
80.4M
    for (n = last_sym + 1; n < info->symtab_size; n++)
12634
80.2M
      {
12635
80.2M
        addr = bfd_asymbol_value (info->symtab[n]);
12636
80.2M
        if (addr > pc
12637
80.2M
      && (info->section == NULL
12638
73.4M
          || info->section == info->symtab[n]->section))
12639
9.49k
    {
12640
9.49k
      if (addr - pc < size)
12641
9
        size = addr - pc;
12642
9.49k
      break;
12643
9.49k
    }
12644
80.2M
      }
12645
    /* If the next symbol is after three bytes, we need to
12646
       print only part of the data, so that we can use either
12647
       .byte or .short.  */
12648
200k
    if (size == 3)
12649
7
      size = (pc & 1) ? 1 : 2;
12650
200k
  }
12651
361k
    }
12652
12653
4.96M
  if (info->symbols != NULL)
12654
274k
    {
12655
274k
      if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour)
12656
34
  {
12657
34
    coff_symbol_type * cs;
12658
12659
34
    cs = coffsymbol (*info->symbols);
12660
34
    is_thumb = (   cs->native->u.syment.n_sclass == C_THUMBEXT
12661
34
          || cs->native->u.syment.n_sclass == C_THUMBSTAT
12662
34
          || cs->native->u.syment.n_sclass == C_THUMBLABEL
12663
34
          || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC
12664
34
          || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC);
12665
34
  }
12666
274k
      else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour
12667
274k
         && !found)
12668
27.4k
  {
12669
    /* If no mapping symbol has been found then fall back to the type
12670
       of the function symbol.  */
12671
27.4k
    elf_symbol_type *  es;
12672
27.4k
    unsigned int       type;
12673
12674
27.4k
    es = *(elf_symbol_type **)(info->symbols);
12675
27.4k
    type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
12676
12677
27.4k
    is_thumb =
12678
27.4k
      ((ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
12679
27.4k
        == ST_BRANCH_TO_THUMB) || type == STT_ARM_16BIT);
12680
27.4k
  }
12681
247k
      else if (bfd_asymbol_flavour (*info->symbols)
12682
247k
         == bfd_target_mach_o_flavour)
12683
198k
  {
12684
198k
    bfd_mach_o_asymbol *asym = (bfd_mach_o_asymbol *)*info->symbols;
12685
12686
198k
    is_thumb = (asym->n_desc & BFD_MACH_O_N_ARM_THUMB_DEF);
12687
198k
  }
12688
274k
    }
12689
12690
4.96M
  if (force_thumb)
12691
1.23M
    is_thumb = true;
12692
12693
4.96M
  if (is_data)
12694
200k
    info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
12695
4.76M
  else
12696
4.76M
    info->display_endian = little_code ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
12697
12698
4.96M
  info->bytes_per_line = 4;
12699
12700
  /* PR 10263: Disassemble data if requested to do so by the user.  */
12701
4.96M
  if (is_data && ((info->flags & DISASSEMBLE_DATA) == 0))
12702
0
    {
12703
0
      int i;
12704
12705
      /* Size was already set above.  */
12706
0
      info->bytes_per_chunk = size;
12707
0
      printer = print_insn_data;
12708
12709
0
      status = info->read_memory_func (pc, (bfd_byte *) b, size, info);
12710
0
      given = 0;
12711
0
      if (little)
12712
0
  for (i = size - 1; i >= 0; i--)
12713
0
    given = b[i] | (given << 8);
12714
0
      else
12715
0
  for (i = 0; i < (int) size; i++)
12716
0
    given = b[i] | (given << 8);
12717
0
    }
12718
4.96M
  else if (!is_thumb)
12719
3.49M
    {
12720
      /* In ARM mode endianness is a straightforward issue: the instruction
12721
   is four bytes long and is either ordered 0123 or 3210.  */
12722
3.49M
      printer = print_insn_arm;
12723
3.49M
      info->bytes_per_chunk = 4;
12724
3.49M
      size = 4;
12725
12726
3.49M
      status = info->read_memory_func (pc, (bfd_byte *) b, 4, info);
12727
3.49M
      if (little_code)
12728
2.19M
  given = (b[0]) | (b[1] << 8) | (b[2] << 16) | ((unsigned) b[3] << 24);
12729
1.29M
      else
12730
1.29M
  given = (b[3]) | (b[2] << 8) | (b[1] << 16) | ((unsigned) b[0] << 24);
12731
3.49M
    }
12732
1.47M
  else
12733
1.47M
    {
12734
      /* In Thumb mode we have the additional wrinkle of two
12735
   instruction lengths.  Fortunately, the bits that determine
12736
   the length of the current instruction are always to be found
12737
   in the first two bytes.  */
12738
1.47M
      printer = print_insn_thumb16;
12739
1.47M
      info->bytes_per_chunk = 2;
12740
1.47M
      size = 2;
12741
12742
1.47M
      status = info->read_memory_func (pc, (bfd_byte *) b, 2, info);
12743
1.47M
      if (little_code)
12744
811k
  given = (b[0]) | (b[1] << 8);
12745
662k
      else
12746
662k
  given = (b[1]) | (b[0] << 8);
12747
12748
1.47M
      if (!status)
12749
1.46M
  {
12750
    /* These bit patterns signal a four-byte Thumb
12751
       instruction.  */
12752
1.46M
    if ((given & 0xF800) == 0xF800
12753
1.46M
        || (given & 0xF800) == 0xF000
12754
1.46M
        || (given & 0xF800) == 0xE800)
12755
417k
      {
12756
417k
        status = info->read_memory_func (pc + 2, (bfd_byte *) b, 2, info);
12757
417k
        if (little_code)
12758
217k
    given = (b[0]) | (b[1] << 8) | (given << 16);
12759
199k
        else
12760
199k
    given = (b[1]) | (b[0] << 8) | (given << 16);
12761
12762
417k
        printer = print_insn_thumb32;
12763
417k
        size = 4;
12764
417k
      }
12765
1.46M
  }
12766
12767
1.47M
      if (ifthen_address != pc)
12768
12.8k
  find_ifthen_state (pc, info, little_code);
12769
12770
1.47M
      if (ifthen_state)
12771
51.6k
  {
12772
51.6k
    if ((ifthen_state & 0xf) == 0x8)
12773
12.0k
      ifthen_next_state = 0;
12774
39.5k
    else
12775
39.5k
      ifthen_next_state = (ifthen_state & 0xe0)
12776
39.5k
        | ((ifthen_state & 0xf) << 1);
12777
51.6k
  }
12778
1.47M
    }
12779
12780
4.96M
  if (status)
12781
10.3k
    {
12782
10.3k
      info->memory_error_func (status, pc, info);
12783
10.3k
      return -1;
12784
10.3k
    }
12785
4.95M
  if (info->flags & INSN_HAS_RELOC)
12786
    /* If the instruction has a reloc associated with it, then
12787
       the offset field in the instruction will actually be the
12788
       addend for the reloc.  (We are using REL type relocs).
12789
       In such cases, we can ignore the pc when computing
12790
       addresses, since the addend is not currently pc-relative.  */
12791
33
    pc = 0;
12792
12793
4.95M
  printer (pc, info, given);
12794
12795
4.95M
  if (is_thumb)
12796
1.46M
    {
12797
1.46M
      ifthen_state = ifthen_next_state;
12798
1.46M
      ifthen_address += size;
12799
1.46M
    }
12800
4.95M
  return size;
12801
4.96M
}
12802
12803
int
12804
print_insn_big_arm (bfd_vma pc, struct disassemble_info *info)
12805
1.98M
{
12806
  /* Detect BE8-ness and record it in the disassembler info.  */
12807
1.98M
  if (info->flavour == bfd_target_elf_flavour
12808
1.98M
      && info->section != NULL
12809
1.98M
      && (elf_elfheader (info->section->owner)->e_flags & EF_ARM_BE8))
12810
29.8k
    info->endian_code = BFD_ENDIAN_LITTLE;
12811
12812
1.98M
  return print_insn (pc, info, false);
12813
1.98M
}
12814
12815
int
12816
print_insn_little_arm (bfd_vma pc, struct disassemble_info *info)
12817
2.98M
{
12818
2.98M
  return print_insn (pc, info, true);
12819
2.98M
}
12820
12821
const disasm_options_and_args_t *
12822
disassembler_options_arm (void)
12823
0
{
12824
0
  static disasm_options_and_args_t *opts_and_args;
12825
12826
0
  if (opts_and_args == NULL)
12827
0
    {
12828
0
      disasm_options_t *opts;
12829
0
      unsigned int i;
12830
12831
0
      opts_and_args = XNEW (disasm_options_and_args_t);
12832
0
      opts_and_args->args = NULL;
12833
12834
0
      opts = &opts_and_args->options;
12835
0
      opts->name = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
12836
0
      opts->description = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
12837
0
      opts->arg = NULL;
12838
0
      for (i = 0; i < NUM_ARM_OPTIONS; i++)
12839
0
  {
12840
0
    opts->name[i] = regnames[i].name;
12841
0
    if (regnames[i].description != NULL)
12842
0
      opts->description[i] = _(regnames[i].description);
12843
0
    else
12844
0
      opts->description[i] = NULL;
12845
0
  }
12846
      /* The array we return must be NULL terminated.  */
12847
0
      opts->name[i] = NULL;
12848
0
      opts->description[i] = NULL;
12849
0
    }
12850
12851
0
  return opts_and_args;
12852
0
}
12853
12854
void
12855
print_arm_disassembler_options (FILE *stream)
12856
0
{
12857
0
  unsigned int i, max_len = 0;
12858
0
  fprintf (stream, _("\n\
12859
0
The following ARM specific disassembler options are supported for use with\n\
12860
0
the -M switch:\n"));
12861
12862
0
  for (i = 0; i < NUM_ARM_OPTIONS; i++)
12863
0
    {
12864
0
      unsigned int len = strlen (regnames[i].name);
12865
0
      if (max_len < len)
12866
0
  max_len = len;
12867
0
    }
12868
12869
0
  for (i = 0, max_len++; i < NUM_ARM_OPTIONS; i++)
12870
0
    fprintf (stream, "  %s%*c %s\n",
12871
0
       regnames[i].name,
12872
0
       (int)(max_len - strlen (regnames[i].name)), ' ',
12873
0
       _(regnames[i].description));
12874
0
}