Coverage Report

Created: 2024-05-21 06:29

/src/binutils-gdb/opcodes/bfin-dis.c
Line
Count
Source (jump to first uncovered line)
1
/* Disassemble ADI Blackfin Instructions.
2
   Copyright (C) 2005-2024 Free Software Foundation, Inc.
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4
   This file is part of libopcodes.
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6
   This library is free software; you can redistribute it and/or modify
7
   it under the terms of the GNU General Public License as published by
8
   the Free Software Foundation; either version 3, or (at your option)
9
   any later version.
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11
   It is distributed in the hope that it will be useful, but WITHOUT
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   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
14
   License for more details.
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   You should have received a copy of the GNU General Public License
17
   along with this program; if not, write to the Free Software
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   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19
   MA 02110-1301, USA.  */
20
21
#include "sysdep.h"
22
#include <stdio.h>
23
24
#include "opcode/bfin.h"
25
26
#ifndef PRINTF
27
#define PRINTF printf
28
#endif
29
30
#ifndef EXIT
31
#define EXIT exit
32
#endif
33
34
typedef long TIword;
35
36
1.52M
#define SIGNBIT(bits)       (1ul << ((bits) - 1))
37
507k
#define MASKBITS(val, bits) ((val) & ((SIGNBIT (bits) << 1) - 1))
38
507k
#define SIGNEXTEND(v, n)    ((MASKBITS (v, n) ^ SIGNBIT (n)) - SIGNBIT (n))
39
40
#include "disassemble.h"
41
42
typedef unsigned int bu32;
43
44
struct private
45
{
46
  TIword iw0;
47
  bool comment, parallel;
48
};
49
50
typedef enum
51
{
52
  c_0, c_1, c_4, c_2, c_uimm2, c_uimm3, c_imm3, c_pcrel4,
53
  c_imm4, c_uimm4s4, c_uimm4s4d, c_uimm4, c_uimm4s2, c_negimm5s4, c_imm5, c_imm5d, c_uimm5, c_imm6,
54
  c_imm7, c_imm7d, c_imm8, c_uimm8, c_pcrel8, c_uimm8s4, c_pcrel8s4, c_lppcrel10, c_pcrel10,
55
  c_pcrel12, c_imm16s4, c_luimm16, c_imm16, c_imm16d, c_huimm16, c_rimm16, c_imm16s2, c_uimm16s4,
56
  c_uimm16s4d, c_uimm16, c_pcrel24, c_uimm32, c_imm32, c_huimm32, c_huimm32e,
57
} const_forms_t;
58
59
static const struct
60
{
61
  const char *name;
62
  const int nbits;
63
  const char reloc;
64
  const char issigned;
65
  const char pcrel;
66
  const char scale;
67
  const char offset;
68
  const char negative;
69
  const char positive;
70
  const char decimal;
71
  const char leading;
72
  const char exact;
73
} constant_formats[] =
74
{
75
  { "0",          0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
76
  { "1",          0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
77
  { "4",          0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
78
  { "2",          0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
79
  { "uimm2",      2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
80
  { "uimm3",      3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
81
  { "imm3",       3, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
82
  { "pcrel4",     4, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0},
83
  { "imm4",       4, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
84
  { "uimm4s4",    4, 0, 0, 0, 2, 0, 0, 1, 0, 0, 0},
85
  { "uimm4s4d",   4, 0, 0, 0, 2, 0, 0, 1, 1, 0, 0},
86
  { "uimm4",      4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
87
  { "uimm4s2",    4, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0},
88
  { "negimm5s4",  5, 0, 1, 0, 2, 0, 1, 0, 0, 0, 0},
89
  { "imm5",       5, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
90
  { "imm5d",      5, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0},
91
  { "uimm5",      5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
92
  { "imm6",       6, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
93
  { "imm7",       7, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
94
  { "imm7d",      7, 0, 1, 0, 0, 0, 0, 0, 1, 3, 0},
95
  { "imm8",       8, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
96
  { "uimm8",      8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
97
  { "pcrel8",     8, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0},
98
  { "uimm8s4",    8, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0},
99
  { "pcrel8s4",   8, 1, 1, 1, 2, 0, 0, 0, 0, 0, 0},
100
  { "lppcrel10", 10, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0},
101
  { "pcrel10",   10, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0},
102
  { "pcrel12",   12, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0},
103
  { "imm16s4",   16, 0, 1, 0, 2, 0, 0, 0, 0, 0, 0},
104
  { "luimm16",   16, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0},
105
  { "imm16",     16, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
106
  { "imm16d",    16, 0, 1, 0, 0, 0, 0, 0, 1, 3, 0},
107
  { "huimm16",   16, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0},
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  { "rimm16",    16, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0},
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  { "imm16s2",   16, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0},
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  { "uimm16s4",  16, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0},
111
  { "uimm16s4d", 16, 0, 0, 0, 2, 0, 0, 0, 1, 0, 0},
112
  { "uimm16",    16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
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  { "pcrel24",   24, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0},
114
  { "uimm32",    32, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
115
  { "imm32",     32, 0, 1, 0, 0, 0, 0, 0, 1, 3, 0},
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  { "huimm32",   32, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0},
117
  { "huimm32e",  32, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1},
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};
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static const char *
121
fmtconst (const_forms_t cf, TIword x, bfd_vma pc, disassemble_info *outf)
122
662k
{
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662k
  static char buf[60];
124
125
662k
  if (constant_formats[cf].reloc)
126
161k
    {
127
161k
      bfd_vma ea;
128
129
161k
      if (constant_formats[cf].pcrel)
130
158k
  x = SIGNEXTEND (x, constant_formats[cf].nbits);
131
161k
      ea = x + constant_formats[cf].offset;
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161k
      ea = ea << constant_formats[cf].scale;
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161k
      if (constant_formats[cf].pcrel)
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158k
  ea += pc;
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136
      /* truncate to 32-bits for proper symbol lookup/matching */
137
161k
      ea = (bu32)ea;
138
139
161k
      if (outf->symbol_at_address_func (ea, outf) || !constant_formats[cf].exact)
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158k
  {
141
158k
    outf->print_address_func (ea, outf);
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158k
    return "";
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158k
  }
144
2.69k
      else
145
2.69k
  {
146
2.69k
    sprintf (buf, "%lx", (unsigned long) x);
147
2.69k
    return buf;
148
2.69k
  }
149
161k
    }
150
151
  /* Negative constants have an implied sign bit.  */
152
501k
  if (constant_formats[cf].negative)
153
13.8k
    {
154
13.8k
      int nb = constant_formats[cf].nbits + 1;
155
156
13.8k
      x = x | (1ul << constant_formats[cf].nbits);
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13.8k
      x = SIGNEXTEND (x, nb);
158
13.8k
    }
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487k
  else if (constant_formats[cf].issigned)
160
273k
    x = SIGNEXTEND (x, constant_formats[cf].nbits);
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162
501k
  x += constant_formats[cf].offset;
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501k
  x = (unsigned long) x << constant_formats[cf].scale;
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165
501k
  if (constant_formats[cf].decimal)
166
147k
    sprintf (buf, "%*li", constant_formats[cf].leading, x);
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354k
  else
168
354k
    {
169
354k
      if (constant_formats[cf].issigned && x < 0)
170
68.7k
  sprintf (buf, "-0x%lx", (unsigned long)(- x));
171
285k
      else
172
285k
  sprintf (buf, "0x%lx", (unsigned long) x);
173
354k
    }
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175
501k
  return buf;
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662k
}
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178
static bu32
179
fmtconst_val (const_forms_t cf, unsigned int x, unsigned int pc)
180
63.8k
{
181
63.8k
  if (0 && constant_formats[cf].reloc)
182
0
    {
183
0
      bu32 ea;
184
185
0
      if (constant_formats[cf].pcrel)
186
0
  x = SIGNEXTEND (x, constant_formats[cf].nbits);
187
0
      ea = x + constant_formats[cf].offset;
188
0
      ea = ea << constant_formats[cf].scale;
189
0
      if (constant_formats[cf].pcrel)
190
0
  ea += pc;
191
192
0
      return ea;
193
0
    }
194
195
  /* Negative constants have an implied sign bit.  */
196
63.8k
  if (constant_formats[cf].negative)
197
0
    {
198
0
      int nb = constant_formats[cf].nbits + 1;
199
0
      x = x | (1ul << constant_formats[cf].nbits);
200
0
      x = SIGNEXTEND (x, nb);
201
0
    }
202
63.8k
  else if (constant_formats[cf].issigned)
203
61.1k
    x = SIGNEXTEND (x, constant_formats[cf].nbits);
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205
63.8k
  x += constant_formats[cf].offset;
206
63.8k
  x <<= constant_formats[cf].scale;
207
208
63.8k
  return x;
209
63.8k
}
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211
enum machine_registers
212
{
213
  REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7,
214
  REG_RH0, REG_RH1, REG_RH2, REG_RH3, REG_RH4, REG_RH5, REG_RH6, REG_RH7,
215
  REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
216
  REG_R1_0, REG_R3_2, REG_R5_4, REG_R7_6, REG_P0, REG_P1, REG_P2, REG_P3,
217
  REG_P4, REG_P5, REG_SP, REG_FP, REG_A0x, REG_A1x, REG_A0w, REG_A1w,
218
  REG_A0, REG_A1, REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1,
219
  REG_M2, REG_M3, REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1,
220
  REG_L2, REG_L3,
221
  REG_AZ, REG_AN, REG_AC0, REG_AC1, REG_AV0, REG_AV1, REG_AV0S, REG_AV1S,
222
  REG_AQ, REG_V, REG_VS,
223
  REG_sftreset, REG_omode, REG_excause, REG_emucause, REG_idle_req, REG_hwerrcause, REG_CC, REG_LC0,
224
  REG_LC1, REG_ASTAT, REG_RETS, REG_LT0, REG_LB0, REG_LT1, REG_LB1,
225
  REG_CYCLES, REG_CYCLES2, REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN,
226
  REG_RETE, REG_EMUDAT, REG_BR0, REG_BR1, REG_BR2, REG_BR3, REG_BR4, REG_BR5, REG_BR6,
227
  REG_BR7, REG_PL0, REG_PL1, REG_PL2, REG_PL3, REG_PL4, REG_PL5, REG_SLP, REG_FLP,
228
  REG_PH0, REG_PH1, REG_PH2, REG_PH3, REG_PH4, REG_PH5, REG_SHP, REG_FHP,
229
  REG_IL0, REG_IL1, REG_IL2, REG_IL3, REG_ML0, REG_ML1, REG_ML2, REG_ML3,
230
  REG_BL0, REG_BL1, REG_BL2, REG_BL3, REG_LL0, REG_LL1, REG_LL2, REG_LL3,
231
  REG_IH0, REG_IH1, REG_IH2, REG_IH3, REG_MH0, REG_MH1, REG_MH2, REG_MH3,
232
  REG_BH0, REG_BH1, REG_BH2, REG_BH3, REG_LH0, REG_LH1, REG_LH2, REG_LH3,
233
  REG_AC0_COPY, REG_V_COPY, REG_RND_MOD,
234
  REG_LASTREG,
235
};
236
237
enum reg_class
238
{
239
  rc_dregs_lo, rc_dregs_hi, rc_dregs, rc_dregs_pair, rc_pregs, rc_spfp, rc_dregs_hilo, rc_accum_ext,
240
  rc_accum_word, rc_accum, rc_iregs, rc_mregs, rc_bregs, rc_lregs, rc_dpregs, rc_gregs,
241
  rc_regs, rc_statbits, rc_ignore_bits, rc_ccstat, rc_counters, rc_dregs2_sysregs1, rc_open, rc_sysregs2,
242
  rc_sysregs3, rc_allregs,
243
  LIM_REG_CLASSES
244
};
245
246
static const char * const reg_names[] =
247
{
248
  "R0.L", "R1.L", "R2.L", "R3.L", "R4.L", "R5.L", "R6.L", "R7.L",
249
  "R0.H", "R1.H", "R2.H", "R3.H", "R4.H", "R5.H", "R6.H", "R7.H",
250
  "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7",
251
  "R1:0", "R3:2", "R5:4", "R7:6", "P0", "P1", "P2", "P3",
252
  "P4", "P5", "SP", "FP", "A0.X", "A1.X", "A0.W", "A1.W",
253
  "A0", "A1", "I0", "I1", "I2", "I3", "M0", "M1",
254
  "M2", "M3", "B0", "B1", "B2", "B3", "L0", "L1",
255
  "L2", "L3",
256
  "AZ", "AN", "AC0", "AC1", "AV0", "AV1", "AV0S", "AV1S",
257
  "AQ", "V", "VS",
258
  "sftreset", "omode", "excause", "emucause", "idle_req", "hwerrcause", "CC", "LC0",
259
  "LC1", "ASTAT", "RETS", "LT0", "LB0", "LT1", "LB1",
260
  "CYCLES", "CYCLES2", "USP", "SEQSTAT", "SYSCFG", "RETI", "RETX", "RETN",
261
  "RETE", "EMUDAT",
262
  "R0.B", "R1.B", "R2.B", "R3.B", "R4.B", "R5.B", "R6.B", "R7.B",
263
  "P0.L", "P1.L", "P2.L", "P3.L", "P4.L", "P5.L", "SP.L", "FP.L",
264
  "P0.H", "P1.H", "P2.H", "P3.H", "P4.H", "P5.H", "SP.H", "FP.H",
265
  "I0.L", "I1.L", "I2.L", "I3.L", "M0.L", "M1.L", "M2.L", "M3.L",
266
  "B0.L", "B1.L", "B2.L", "B3.L", "L0.L", "L1.L", "L2.L", "L3.L",
267
  "I0.H", "I1.H", "I2.H", "I3.H", "M0.H", "M1.H", "M2.H", "M3.H",
268
  "B0.H", "B1.H", "B2.H", "B3.H", "L0.H", "L1.H", "L2.H", "L3.H",
269
  "AC0_COPY", "V_COPY", "RND_MOD",
270
  "LASTREG",
271
  0
272
};
273
274
64.4k
#define REGNAME(x) ((x) < REG_LASTREG ? (reg_names[x]) : "...... Illegal register .......")
275
276
/* RL(0..7).  */
277
static const enum machine_registers decode_dregs_lo[] =
278
{
279
  REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7,
280
};
281
282
30.2k
#define dregs_lo(x) REGNAME (decode_dregs_lo[(x) & 7])
283
284
/* RH(0..7).  */
285
static const enum machine_registers decode_dregs_hi[] =
286
{
287
  REG_RH0, REG_RH1, REG_RH2, REG_RH3, REG_RH4, REG_RH5, REG_RH6, REG_RH7,
288
};
289
290
21.1k
#define dregs_hi(x) REGNAME (decode_dregs_hi[(x) & 7])
291
292
/* R(0..7).  */
293
static const enum machine_registers decode_dregs[] =
294
{
295
  REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
296
};
297
298
#define dregs(x) REGNAME (decode_dregs[(x) & 7])
299
300
/* R BYTE(0..7).  */
301
static const enum machine_registers decode_dregs_byte[] =
302
{
303
  REG_BR0, REG_BR1, REG_BR2, REG_BR3, REG_BR4, REG_BR5, REG_BR6, REG_BR7,
304
};
305
306
#define dregs_byte(x) REGNAME (decode_dregs_byte[(x) & 7])
307
308
/* P(0..5) SP FP.  */
309
static const enum machine_registers decode_pregs[] =
310
{
311
  REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
312
};
313
314
#define pregs(x)  REGNAME (decode_pregs[(x) & 7])
315
#define spfp(x)   REGNAME (decode_spfp[(x) & 1])
316
#define dregs_hilo(x, i)  REGNAME (decode_dregs_hilo[((i) << 3) | (x)])
317
#define accum_ext(x)  REGNAME (decode_accum_ext[(x) & 1])
318
#define accum_word(x) REGNAME (decode_accum_word[(x) & 1])
319
#define accum(x)  REGNAME (decode_accum[(x) & 1])
320
321
/* I(0..3).  */
322
static const enum machine_registers decode_iregs[] =
323
{
324
  REG_I0, REG_I1, REG_I2, REG_I3,
325
};
326
327
#define iregs(x) REGNAME (decode_iregs[(x) & 3])
328
329
/* M(0..3).  */
330
static const enum machine_registers decode_mregs[] =
331
{
332
  REG_M0, REG_M1, REG_M2, REG_M3,
333
};
334
335
#define mregs(x) REGNAME (decode_mregs[(x) & 3])
336
#define bregs(x) REGNAME (decode_bregs[(x) & 3])
337
#define lregs(x) REGNAME (decode_lregs[(x) & 3])
338
339
/* dregs pregs.  */
340
static const enum machine_registers decode_dpregs[] =
341
{
342
  REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
343
  REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
344
};
345
346
#define dpregs(x) REGNAME (decode_dpregs[(x) & 15])
347
348
/* [dregs pregs].  */
349
static const enum machine_registers decode_gregs[] =
350
{
351
  REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
352
  REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
353
};
354
355
#define gregs(x, i) REGNAME (decode_gregs[(((i) << 3) | (x)) & 15])
356
357
/* [dregs pregs (iregs mregs) (bregs lregs)].  */
358
static const enum machine_registers decode_regs[] =
359
{
360
  REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
361
  REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
362
  REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3,
363
  REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3,
364
};
365
366
#define regs(x, i) REGNAME (decode_regs[(((i) << 3) | (x)) & 31])
367
368
/* [dregs pregs (iregs mregs) (bregs lregs) Low Half].  */
369
static const enum machine_registers decode_regs_lo[] =
370
{
371
  REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7,
372
  REG_PL0, REG_PL1, REG_PL2, REG_PL3, REG_PL4, REG_PL5, REG_SLP, REG_FLP,
373
  REG_IL0, REG_IL1, REG_IL2, REG_IL3, REG_ML0, REG_ML1, REG_ML2, REG_ML3,
374
  REG_BL0, REG_BL1, REG_BL2, REG_BL3, REG_LL0, REG_LL1, REG_LL2, REG_LL3,
375
};
376
377
#define regs_lo(x, i) REGNAME (decode_regs_lo[(((i) << 3) | (x)) & 31])
378
379
/* [dregs pregs (iregs mregs) (bregs lregs) High Half].  */
380
static const enum machine_registers decode_regs_hi[] =
381
{
382
  REG_RH0, REG_RH1, REG_RH2, REG_RH3, REG_RH4, REG_RH5, REG_RH6, REG_RH7,
383
  REG_PH0, REG_PH1, REG_PH2, REG_PH3, REG_PH4, REG_PH5, REG_SHP, REG_FHP,
384
  REG_IH0, REG_IH1, REG_IH2, REG_IH3, REG_MH0, REG_MH1, REG_MH2, REG_MH3,
385
  REG_BH0, REG_BH1, REG_BH2, REG_BH3, REG_LH0, REG_LH1, REG_LH2, REG_LH3,
386
};
387
388
#define regs_hi(x, i) REGNAME (decode_regs_hi[(((i) << 3) | (x)) & 31])
389
390
static const enum machine_registers decode_statbits[] =
391
{
392
  REG_AZ,        REG_AN,        REG_AC0_COPY,    REG_V_COPY,
393
  REG_LASTREG,   REG_LASTREG,   REG_AQ,          REG_LASTREG,
394
  REG_RND_MOD,   REG_LASTREG,   REG_LASTREG,     REG_LASTREG,
395
  REG_AC0,       REG_AC1,       REG_LASTREG,     REG_LASTREG,
396
  REG_AV0,       REG_AV0S,      REG_AV1,         REG_AV1S,
397
  REG_LASTREG,   REG_LASTREG,   REG_LASTREG,     REG_LASTREG,
398
  REG_V,         REG_VS,        REG_LASTREG,     REG_LASTREG,
399
  REG_LASTREG,   REG_LASTREG,   REG_LASTREG,     REG_LASTREG,
400
};
401
402
13.0k
#define statbits(x) REGNAME (decode_statbits[(x) & 31])
403
404
/* LC0 LC1.  */
405
static const enum machine_registers decode_counters[] =
406
{
407
  REG_LC0, REG_LC1,
408
};
409
410
#define counters(x)        REGNAME (decode_counters[(x) & 1])
411
#define dregs2_sysregs1(x) REGNAME (decode_dregs2_sysregs1[(x) & 7])
412
413
/* [dregs pregs (iregs mregs) (bregs lregs)
414
   dregs2_sysregs1 open sysregs2 sysregs3].  */
415
static const enum machine_registers decode_allregs[] =
416
{
417
  REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
418
  REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
419
  REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3,
420
  REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3,
421
  REG_A0x, REG_A0w, REG_A1x, REG_A1w, REG_LASTREG, REG_LASTREG, REG_ASTAT, REG_RETS,
422
  REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG,
423
  REG_LC0, REG_LT0, REG_LB0, REG_LC1, REG_LT1, REG_LB1, REG_CYCLES, REG_CYCLES2,
424
  REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN, REG_RETE, REG_EMUDAT,
425
  REG_LASTREG,
426
};
427
428
28.8k
#define IS_DREG(g,r)  ((g) == 0 && (r) < 8)
429
111k
#define IS_PREG(g,r)  ((g) == 1 && (r) < 8)
430
#define IS_AREG(g,r)  ((g) == 4 && (r) >= 0 && (r) < 4)
431
#define IS_GENREG(g,r)  ((((g) == 0 || (g) == 1) && (r) < 8) || IS_AREG (g, r))
432
#define IS_DAGREG(g,r)  (((g) == 2 || (g) == 3) && (r) < 8)
433
#define IS_SYSREG(g,r) \
434
  (((g) == 4 && ((r) == 6 || (r) == 7)) || (g) == 6 || (g) == 7)
435
#define IS_RESERVEDREG(g,r) \
436
298k
  (((r) > 7) || ((g) == 4 && ((r) == 4 || (r) == 5)) || (g) == 5)
437
438
11.0k
#define allreg(r,g) (!IS_RESERVEDREG (g, r))
439
8.30k
#define mostreg(r,g)  (!(IS_DREG (g, r) || IS_PREG (g, r) || IS_RESERVEDREG (g, r)))
440
441
#define allregs(x, i) REGNAME (decode_allregs[((i) << 3) | (x)])
442
#define uimm16s4(x) fmtconst (c_uimm16s4, x, 0, outf)
443
#define uimm16s4d(x)  fmtconst (c_uimm16s4d, x, 0, outf)
444
#define pcrel4(x) fmtconst (c_pcrel4, x, pc, outf)
445
#define pcrel8(x) fmtconst (c_pcrel8, x, pc, outf)
446
#define pcrel8s4(x) fmtconst (c_pcrel8s4, x, pc, outf)
447
#define pcrel10(x)  fmtconst (c_pcrel10, x, pc, outf)
448
#define pcrel12(x)  fmtconst (c_pcrel12, x, pc, outf)
449
#define negimm5s4(x)  fmtconst (c_negimm5s4, x, 0, outf)
450
#define rimm16(x) fmtconst (c_rimm16, x, 0, outf)
451
#define huimm16(x)  fmtconst (c_huimm16, x, 0, outf)
452
#define imm16(x)  fmtconst (c_imm16, x, 0, outf)
453
#define imm16d(x) fmtconst (c_imm16d, x, 0, outf)
454
#define uimm2(x)  fmtconst (c_uimm2, x, 0, outf)
455
#define uimm3(x)  fmtconst (c_uimm3, x, 0, outf)
456
#define luimm16(x)  fmtconst (c_luimm16, x, 0, outf)
457
#define uimm4(x)  fmtconst (c_uimm4, x, 0, outf)
458
#define uimm5(x)  fmtconst (c_uimm5, x, 0, outf)
459
#define imm16s2(x)  fmtconst (c_imm16s2, x, 0, outf)
460
#define uimm8(x)  fmtconst (c_uimm8, x, 0, outf)
461
#define imm16s4(x)  fmtconst (c_imm16s4, x, 0, outf)
462
#define uimm4s2(x)  fmtconst (c_uimm4s2, x, 0, outf)
463
#define uimm4s4(x)  fmtconst (c_uimm4s4, x, 0, outf)
464
#define uimm4s4d(x) fmtconst (c_uimm4s4d, x, 0, outf)
465
#define lppcrel10(x)  fmtconst (c_lppcrel10, x, pc, outf)
466
#define imm3(x)   fmtconst (c_imm3, x, 0, outf)
467
#define imm4(x)   fmtconst (c_imm4, x, 0, outf)
468
#define uimm8s4(x)  fmtconst (c_uimm8s4, x, 0, outf)
469
#define imm5(x)   fmtconst (c_imm5, x, 0, outf)
470
#define imm5d(x)  fmtconst (c_imm5d, x, 0, outf)
471
#define imm6(x)   fmtconst (c_imm6, x, 0, outf)
472
#define imm7(x)   fmtconst (c_imm7, x, 0, outf)
473
#define imm7d(x)  fmtconst (c_imm7d, x, 0, outf)
474
#define imm8(x)   fmtconst (c_imm8, x, 0, outf)
475
#define pcrel24(x)  fmtconst (c_pcrel24, x, pc, outf)
476
#define uimm16(x) fmtconst (c_uimm16, x, 0, outf)
477
#define uimm32(x) fmtconst (c_uimm32, x, 0, outf)
478
#define imm32(x)  fmtconst (c_imm32, x, 0, outf)
479
#define huimm32(x)  fmtconst (c_huimm32, x, 0, outf)
480
#define huimm32e(x) fmtconst (c_huimm32e, x, 0, outf)
481
61.1k
#define imm7_val(x) fmtconst_val (c_imm7, x, 0)
482
444
#define imm16_val(x)  fmtconst_val (c_uimm16, x, 0)
483
2.24k
#define luimm16_val(x)  fmtconst_val (c_luimm16, x, 0)
484
485
/* (arch.pm)arch_disassembler_functions.  */
486
#ifndef OUTS
487
6.52M
#define OUTS(p, txt) (p)->fprintf_func ((p)->stream, "%s", txt)
488
#endif
489
12.3k
#define OUT(p, txt, ...) (p)->fprintf_func ((p)->stream, txt, ## __VA_ARGS__)
490
491
static void
492
amod0 (int s0, int x0, disassemble_info *outf)
493
5.94k
{
494
5.94k
  if (s0 == 1 && x0 == 0)
495
358
    OUTS (outf, " (S)");
496
5.58k
  else if (s0 == 0 && x0 == 1)
497
695
    OUTS (outf, " (CO)");
498
4.89k
  else if (s0 == 1 && x0 == 1)
499
816
    OUTS (outf, " (SCO)");
500
5.94k
}
501
502
static void
503
amod1 (int s0, int x0, disassemble_info *outf)
504
5.53k
{
505
5.53k
  if (s0 == 0 && x0 == 0)
506
2.44k
    OUTS (outf, " (NS)");
507
3.09k
  else if (s0 == 1 && x0 == 0)
508
945
    OUTS (outf, " (S)");
509
5.53k
}
510
511
static void
512
amod0amod2 (int s0, int x0, int aop0, disassemble_info *outf)
513
1.49k
{
514
1.49k
  if (s0 == 1 && x0 == 0 && aop0 == 0)
515
138
    OUTS (outf, " (S)");
516
1.35k
  else if (s0 == 0 && x0 == 1 && aop0 == 0)
517
174
    OUTS (outf, " (CO)");
518
1.18k
  else if (s0 == 1 && x0 == 1 && aop0 == 0)
519
177
    OUTS (outf, " (SCO)");
520
1.00k
  else if (s0 == 0 && x0 == 0 && aop0 == 2)
521
44
    OUTS (outf, " (ASR)");
522
964
  else if (s0 == 1 && x0 == 0 && aop0 == 2)
523
78
    OUTS (outf, " (S, ASR)");
524
886
  else if (s0 == 0 && x0 == 1 && aop0 == 2)
525
38
    OUTS (outf, " (CO, ASR)");
526
848
  else if (s0 == 1 && x0 == 1 && aop0 == 2)
527
217
    OUTS (outf, " (SCO, ASR)");
528
631
  else if (s0 == 0 && x0 == 0 && aop0 == 3)
529
69
    OUTS (outf, " (ASL)");
530
562
  else if (s0 == 1 && x0 == 0 && aop0 == 3)
531
13
    OUTS (outf, " (S, ASL)");
532
549
  else if (s0 == 0 && x0 == 1 && aop0 == 3)
533
163
    OUTS (outf, " (CO, ASL)");
534
386
  else if (s0 == 1 && x0 == 1 && aop0 == 3)
535
22
    OUTS (outf, " (SCO, ASL)");
536
1.49k
}
537
538
static void
539
searchmod (int r0, disassemble_info *outf)
540
334
{
541
334
  if (r0 == 0)
542
126
    OUTS (outf, "GT");
543
208
  else if (r0 == 1)
544
44
    OUTS (outf, "GE");
545
164
  else if (r0 == 2)
546
50
    OUTS (outf, "LT");
547
114
  else if (r0 == 3)
548
114
    OUTS (outf, "LE");
549
334
}
550
551
static void
552
aligndir (int r0, disassemble_info *outf)
553
1.19k
{
554
1.19k
  if (r0 == 1)
555
452
    OUTS (outf, " (R)");
556
1.19k
}
557
558
static int
559
decode_multfunc (int h0, int h1, int src0, int src1, disassemble_info *outf)
560
25.7k
{
561
25.7k
  const char *s0, *s1;
562
563
25.7k
  if (h0)
564
9.94k
    s0 = dregs_hi (src0);
565
15.7k
  else
566
15.7k
    s0 = dregs_lo (src0);
567
568
25.7k
  if (h1)
569
11.1k
    s1 = dregs_hi (src1);
570
14.5k
  else
571
14.5k
    s1 = dregs_lo (src1);
572
573
25.7k
  OUTS (outf, s0);
574
25.7k
  OUTS (outf, " * ");
575
25.7k
  OUTS (outf, s1);
576
25.7k
  return 0;
577
25.7k
}
578
579
static int
580
decode_macfunc (int which, int op, int h0, int h1, int src0, int src1, disassemble_info *outf)
581
20.0k
{
582
20.0k
  const char *a;
583
20.0k
  const char *sop = "<unknown op>";
584
585
20.0k
  if (which)
586
9.60k
    a = "A1";
587
10.4k
  else
588
10.4k
    a = "A0";
589
590
20.0k
  if (op == 3)
591
0
    {
592
0
      OUTS (outf, a);
593
0
      return 0;
594
0
    }
595
596
20.0k
  switch (op)
597
20.0k
    {
598
7.69k
    case 0: sop = " = ";   break;
599
5.52k
    case 1: sop = " += ";  break;
600
6.88k
    case 2: sop = " -= ";  break;
601
0
    default: break;
602
20.0k
    }
603
604
20.0k
  OUTS (outf, a);
605
20.0k
  OUTS (outf, sop);
606
20.0k
  decode_multfunc (h0, h1, src0, src1, outf);
607
608
20.0k
  return 0;
609
20.0k
}
610
611
static void
612
decode_optmode (int mod, int MM, disassemble_info *outf)
613
16.0k
{
614
16.0k
  if (mod == 0 && MM == 0)
615
3.12k
    return;
616
617
12.9k
  OUTS (outf, " (");
618
619
12.9k
  if (MM && !mod)
620
502
    {
621
502
      OUTS (outf, "M)");
622
502
      return;
623
502
    }
624
625
12.4k
  if (MM)
626
817
    OUTS (outf, "M, ");
627
628
12.4k
  if (mod == M_S2RND)
629
2.23k
    OUTS (outf, "S2RND");
630
10.2k
  else if (mod == M_T)
631
467
    OUTS (outf, "T");
632
9.75k
  else if (mod == M_W32)
633
106
    OUTS (outf, "W32");
634
9.64k
  else if (mod == M_FU)
635
591
    OUTS (outf, "FU");
636
9.05k
  else if (mod == M_TFU)
637
2.71k
    OUTS (outf, "TFU");
638
6.34k
  else if (mod == M_IS)
639
2.26k
    OUTS (outf, "IS");
640
4.08k
  else if (mod == M_ISS2)
641
633
    OUTS (outf, "ISS2");
642
3.44k
  else if (mod == M_IH)
643
684
    OUTS (outf, "IH");
644
2.76k
  else if (mod == M_IU)
645
2.76k
    OUTS (outf, "IU");
646
0
  else
647
0
    abort ();
648
649
12.4k
  OUTS (outf, ")");
650
12.4k
}
651
652
static struct saved_state
653
{
654
  bu32 dpregs[16], iregs[4], mregs[4], bregs[4], lregs[4];
655
  bu32 ax[2], aw[2];
656
  bu32 lt[2], lc[2], lb[2];
657
  bu32 rets;
658
} saved_state;
659
660
#define DREG(x)         (saved_state.dpregs[x])
661
#define GREG(x, i)      DPREG ((x) | ((i) << 3))
662
#define DPREG(x)        (saved_state.dpregs[x])
663
69.1k
#define DREG(x)         (saved_state.dpregs[x])
664
50.6k
#define PREG(x)         (saved_state.dpregs[(x) + 8])
665
#define SPREG           PREG (6)
666
#define FPREG           PREG (7)
667
641
#define IREG(x)         (saved_state.iregs[x])
668
154
#define MREG(x)         (saved_state.mregs[x])
669
157
#define BREG(x)         (saved_state.bregs[x])
670
662
#define LREG(x)         (saved_state.lregs[x])
671
0
#define AXREG(x)        (saved_state.ax[x])
672
0
#define AWREG(x)        (saved_state.aw[x])
673
0
#define LCREG(x)        (saved_state.lc[x])
674
0
#define LTREG(x)        (saved_state.lt[x])
675
0
#define LBREG(x)        (saved_state.lb[x])
676
0
#define RETSREG         (saved_state.rets)
677
678
static bu32 *
679
get_allreg (int grp, int reg)
680
121k
{
681
121k
  int fullreg = (grp << 3) | reg;
682
  /* REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
683
     REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
684
     REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3,
685
     REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3,
686
     REG_A0x, REG_A0w, REG_A1x, REG_A1w, , , REG_ASTAT, REG_RETS,
687
     , , , , , , , ,
688
     REG_LC0, REG_LT0, REG_LB0, REG_LC1, REG_LT1, REG_LB1, REG_CYCLES,
689
     REG_CYCLES2,
690
     REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN, REG_RETE,
691
     REG_LASTREG */
692
121k
  switch (fullreg >> 2)
693
121k
    {
694
69.1k
    case 0: case 1: return &DREG (reg);
695
50.6k
    case 2: case 3: return &PREG (reg);
696
641
    case 4: return &IREG (reg & 3);
697
154
    case 5: return &MREG (reg & 3);
698
157
    case 6: return &BREG (reg & 3);
699
662
    case 7: return &LREG (reg & 3);
700
0
    default:
701
0
      switch (fullreg)
702
0
  {
703
0
  case 32: return &AXREG (0);
704
0
  case 33: return &AWREG (0);
705
0
  case 34: return &AXREG (1);
706
0
  case 35: return &AWREG (1);
707
0
  case 39: return &RETSREG;
708
0
  case 48: return &LCREG (0);
709
0
  case 49: return &LTREG (0);
710
0
  case 50: return &LBREG (0);
711
0
  case 51: return &LCREG (1);
712
0
  case 52: return &LTREG (1);
713
0
  case 53: return &LBREG (1);
714
0
  }
715
121k
    }
716
0
  abort ();
717
121k
}
718
719
static int
720
decode_ProgCtrl_0 (TIword iw0, disassemble_info *outf)
721
295k
{
722
295k
  struct private *priv = outf->private_data;
723
  /* ProgCtrl
724
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
725
     | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |.prgfunc.......|.poprnd........|
726
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
727
295k
  int poprnd  = ((iw0 >> ProgCtrl_poprnd_bits) & ProgCtrl_poprnd_mask);
728
295k
  int prgfunc = ((iw0 >> ProgCtrl_prgfunc_bits) & ProgCtrl_prgfunc_mask);
729
730
295k
  if (prgfunc == 0 && poprnd == 0)
731
179k
    OUTS (outf, "NOP");
732
116k
  else if (priv->parallel)
733
6.91k
    return 0;
734
109k
  else if (prgfunc == 1 && poprnd == 0)
735
1.63k
    OUTS (outf, "RTS");
736
107k
  else if (prgfunc == 1 && poprnd == 1)
737
1.03k
    OUTS (outf, "RTI");
738
106k
  else if (prgfunc == 1 && poprnd == 2)
739
445
    OUTS (outf, "RTX");
740
105k
  else if (prgfunc == 1 && poprnd == 3)
741
347
    OUTS (outf, "RTN");
742
105k
  else if (prgfunc == 1 && poprnd == 4)
743
473
    OUTS (outf, "RTE");
744
105k
  else if (prgfunc == 2 && poprnd == 0)
745
949
    OUTS (outf, "IDLE");
746
104k
  else if (prgfunc == 2 && poprnd == 3)
747
595
    OUTS (outf, "CSYNC");
748
103k
  else if (prgfunc == 2 && poprnd == 4)
749
225
    OUTS (outf, "SSYNC");
750
103k
  else if (prgfunc == 2 && poprnd == 5)
751
553
    OUTS (outf, "EMUEXCPT");
752
102k
  else if (prgfunc == 3 && IS_DREG (0, poprnd))
753
4.45k
    {
754
4.45k
      OUTS (outf, "CLI ");
755
4.45k
      OUTS (outf, dregs (poprnd));
756
4.45k
    }
757
98.3k
  else if (prgfunc == 4 && IS_DREG (0, poprnd))
758
3.63k
    {
759
3.63k
      OUTS (outf, "STI ");
760
3.63k
      OUTS (outf, dregs (poprnd));
761
3.63k
    }
762
94.7k
  else if (prgfunc == 5 && IS_PREG (1, poprnd))
763
3.09k
    {
764
3.09k
      OUTS (outf, "JUMP (");
765
3.09k
      OUTS (outf, pregs (poprnd));
766
3.09k
      OUTS (outf, ")");
767
3.09k
    }
768
91.6k
  else if (prgfunc == 6 && IS_PREG (1, poprnd))
769
3.90k
    {
770
3.90k
      OUTS (outf, "CALL (");
771
3.90k
      OUTS (outf, pregs (poprnd));
772
3.90k
      OUTS (outf, ")");
773
3.90k
    }
774
87.7k
  else if (prgfunc == 7 && IS_PREG (1, poprnd))
775
3.19k
    {
776
3.19k
      OUTS (outf, "CALL (PC + ");
777
3.19k
      OUTS (outf, pregs (poprnd));
778
3.19k
      OUTS (outf, ")");
779
3.19k
    }
780
84.5k
  else if (prgfunc == 8 && IS_PREG (1, poprnd))
781
2.62k
    {
782
2.62k
      OUTS (outf, "JUMP (PC + ");
783
2.62k
      OUTS (outf, pregs (poprnd));
784
2.62k
      OUTS (outf, ")");
785
2.62k
    }
786
81.9k
  else if (prgfunc == 9)
787
4.80k
    {
788
4.80k
      OUTS (outf, "RAISE ");
789
4.80k
      OUTS (outf, uimm4 (poprnd));
790
4.80k
    }
791
77.1k
  else if (prgfunc == 10)
792
3.27k
    {
793
3.27k
      OUTS (outf, "EXCPT ");
794
3.27k
      OUTS (outf, uimm4 (poprnd));
795
3.27k
    }
796
73.8k
  else if (prgfunc == 11 && IS_PREG (1, poprnd) && poprnd <= 5)
797
957
    {
798
957
      OUTS (outf, "TESTSET (");
799
957
      OUTS (outf, pregs (poprnd));
800
957
      OUTS (outf, ")");
801
957
    }
802
72.9k
  else
803
72.9k
    return 0;
804
215k
  return 2;
805
295k
}
806
807
static int
808
decode_CaCTRL_0 (TIword iw0, disassemble_info *outf)
809
1.63k
{
810
1.63k
  struct private *priv = outf->private_data;
811
  /* CaCTRL
812
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
813
     | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |.a.|.op....|.reg.......|
814
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
815
1.63k
  int a   = ((iw0 >> CaCTRL_a_bits) & CaCTRL_a_mask);
816
1.63k
  int op  = ((iw0 >> CaCTRL_op_bits) & CaCTRL_op_mask);
817
1.63k
  int reg = ((iw0 >> CaCTRL_reg_bits) & CaCTRL_reg_mask);
818
819
1.63k
  if (priv->parallel)
820
339
    return 0;
821
822
1.30k
  if (a == 0 && op == 0)
823
370
    {
824
370
      OUTS (outf, "PREFETCH[");
825
370
      OUTS (outf, pregs (reg));
826
370
      OUTS (outf, "]");
827
370
    }
828
930
  else if (a == 0 && op == 1)
829
193
    {
830
193
      OUTS (outf, "FLUSHINV[");
831
193
      OUTS (outf, pregs (reg));
832
193
      OUTS (outf, "]");
833
193
    }
834
737
  else if (a == 0 && op == 2)
835
70
    {
836
70
      OUTS (outf, "FLUSH[");
837
70
      OUTS (outf, pregs (reg));
838
70
      OUTS (outf, "]");
839
70
    }
840
667
  else if (a == 0 && op == 3)
841
40
    {
842
40
      OUTS (outf, "IFLUSH[");
843
40
      OUTS (outf, pregs (reg));
844
40
      OUTS (outf, "]");
845
40
    }
846
627
  else if (a == 1 && op == 0)
847
182
    {
848
182
      OUTS (outf, "PREFETCH[");
849
182
      OUTS (outf, pregs (reg));
850
182
      OUTS (outf, "++]");
851
182
    }
852
445
  else if (a == 1 && op == 1)
853
156
    {
854
156
      OUTS (outf, "FLUSHINV[");
855
156
      OUTS (outf, pregs (reg));
856
156
      OUTS (outf, "++]");
857
156
    }
858
289
  else if (a == 1 && op == 2)
859
192
    {
860
192
      OUTS (outf, "FLUSH[");
861
192
      OUTS (outf, pregs (reg));
862
192
      OUTS (outf, "++]");
863
192
    }
864
97
  else if (a == 1 && op == 3)
865
97
    {
866
97
      OUTS (outf, "IFLUSH[");
867
97
      OUTS (outf, pregs (reg));
868
97
      OUTS (outf, "++]");
869
97
    }
870
0
  else
871
0
    return 0;
872
1.30k
  return 2;
873
1.30k
}
874
875
static int
876
decode_PushPopReg_0 (TIword iw0, disassemble_info *outf)
877
11.1k
{
878
11.1k
  struct private *priv = outf->private_data;
879
  /* PushPopReg
880
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
881
     | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |.W.|.grp.......|.reg.......|
882
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
883
11.1k
  int W   = ((iw0 >> PushPopReg_W_bits) & PushPopReg_W_mask);
884
11.1k
  int grp = ((iw0 >> PushPopReg_grp_bits) & PushPopReg_grp_mask);
885
11.1k
  int reg = ((iw0 >> PushPopReg_reg_bits) & PushPopReg_reg_mask);
886
887
11.1k
  if (priv->parallel)
888
507
    return 0;
889
890
10.6k
  if (W == 0 && mostreg (reg, grp))
891
1.94k
    {
892
1.94k
      OUTS (outf, allregs (reg, grp));
893
1.94k
      OUTS (outf, " = [SP++]");
894
1.94k
    }
895
8.68k
  else if (W == 1 && allreg (reg, grp) && !(grp == 1 && reg == 6))
896
1.67k
    {
897
1.67k
      OUTS (outf, "[--SP] = ");
898
1.67k
      OUTS (outf, allregs (reg, grp));
899
1.67k
    }
900
7.01k
  else
901
7.01k
    return 0;
902
3.61k
  return 2;
903
10.6k
}
904
905
static int
906
decode_PushPopMultiple_0 (TIword iw0, disassemble_info *outf)
907
24.3k
{
908
24.3k
  struct private *priv = outf->private_data;
909
  /* PushPopMultiple
910
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
911
     | 0 | 0 | 0 | 0 | 0 | 1 | 0 |.d.|.p.|.W.|.dr........|.pr........|
912
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
913
24.3k
  int p  = ((iw0 >> PushPopMultiple_p_bits) & PushPopMultiple_p_mask);
914
24.3k
  int d  = ((iw0 >> PushPopMultiple_d_bits) & PushPopMultiple_d_mask);
915
24.3k
  int W  = ((iw0 >> PushPopMultiple_W_bits) & PushPopMultiple_W_mask);
916
24.3k
  int dr = ((iw0 >> PushPopMultiple_dr_bits) & PushPopMultiple_dr_mask);
917
24.3k
  int pr = ((iw0 >> PushPopMultiple_pr_bits) & PushPopMultiple_pr_mask);
918
919
24.3k
  if (priv->parallel)
920
2.50k
    return 0;
921
922
21.8k
  if (pr > 5)
923
3.68k
    return 0;
924
925
18.1k
  if (W == 1 && d == 1 && p == 1)
926
2.91k
    {
927
2.91k
      OUTS (outf, "[--SP] = (R7:");
928
2.91k
      OUTS (outf, imm5d (dr));
929
2.91k
      OUTS (outf, ", P5:");
930
2.91k
      OUTS (outf, imm5d (pr));
931
2.91k
      OUTS (outf, ")");
932
2.91k
    }
933
15.2k
  else if (W == 1 && d == 1 && p == 0 && pr == 0)
934
78
    {
935
78
      OUTS (outf, "[--SP] = (R7:");
936
78
      OUTS (outf, imm5d (dr));
937
78
      OUTS (outf, ")");
938
78
    }
939
15.1k
  else if (W == 1 && d == 0 && p == 1 && dr == 0)
940
311
    {
941
311
      OUTS (outf, "[--SP] = (P5:");
942
311
      OUTS (outf, imm5d (pr));
943
311
      OUTS (outf, ")");
944
311
    }
945
14.8k
  else if (W == 0 && d == 1 && p == 1)
946
1.10k
    {
947
1.10k
      OUTS (outf, "(R7:");
948
1.10k
      OUTS (outf, imm5d (dr));
949
1.10k
      OUTS (outf, ", P5:");
950
1.10k
      OUTS (outf, imm5d (pr));
951
1.10k
      OUTS (outf, ") = [SP++]");
952
1.10k
    }
953
13.7k
  else if (W == 0 && d == 1 && p == 0 && pr == 0)
954
2.31k
    {
955
2.31k
      OUTS (outf, "(R7:");
956
2.31k
      OUTS (outf, imm5d (dr));
957
2.31k
      OUTS (outf, ") = [SP++]");
958
2.31k
    }
959
11.4k
  else if (W == 0 && d == 0 && p == 1 && dr == 0)
960
169
    {
961
169
      OUTS (outf, "(P5:");
962
169
      OUTS (outf, imm5d (pr));
963
169
      OUTS (outf, ") = [SP++]");
964
169
    }
965
11.2k
  else
966
11.2k
    return 0;
967
6.88k
  return 2;
968
18.1k
}
969
970
static int
971
decode_ccMV_0 (TIword iw0, disassemble_info *outf)
972
27.7k
{
973
27.7k
  struct private *priv = outf->private_data;
974
  /* ccMV
975
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
976
     | 0 | 0 | 0 | 0 | 0 | 1 | 1 |.T.|.d.|.s.|.dst.......|.src.......|
977
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
978
27.7k
  int s  = ((iw0 >> CCmv_s_bits) & CCmv_s_mask);
979
27.7k
  int d  = ((iw0 >> CCmv_d_bits) & CCmv_d_mask);
980
27.7k
  int T  = ((iw0 >> CCmv_T_bits) & CCmv_T_mask);
981
27.7k
  int src = ((iw0 >> CCmv_src_bits) & CCmv_src_mask);
982
27.7k
  int dst = ((iw0 >> CCmv_dst_bits) & CCmv_dst_mask);
983
984
27.7k
  if (priv->parallel)
985
3.73k
    return 0;
986
987
23.9k
  if (T == 1)
988
15.5k
    {
989
15.5k
      OUTS (outf, "IF CC ");
990
15.5k
      OUTS (outf, gregs (dst, d));
991
15.5k
      OUTS (outf, " = ");
992
15.5k
      OUTS (outf, gregs (src, s));
993
15.5k
    }
994
8.47k
  else if (T == 0)
995
8.47k
    {
996
8.47k
      OUTS (outf, "IF !CC ");
997
8.47k
      OUTS (outf, gregs (dst, d));
998
8.47k
      OUTS (outf, " = ");
999
8.47k
      OUTS (outf, gregs (src, s));
1000
8.47k
    }
1001
0
  else
1002
0
    return 0;
1003
23.9k
  return 2;
1004
23.9k
}
1005
1006
static int
1007
decode_CCflag_0 (TIword iw0, disassemble_info *outf)
1008
57.3k
{
1009
57.3k
  struct private *priv = outf->private_data;
1010
  /* CCflag
1011
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1012
     | 0 | 0 | 0 | 0 | 1 |.I.|.opc.......|.G.|.y.........|.x.........|
1013
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
1014
57.3k
  int x = ((iw0 >> CCflag_x_bits) & CCflag_x_mask);
1015
57.3k
  int y = ((iw0 >> CCflag_y_bits) & CCflag_y_mask);
1016
57.3k
  int I = ((iw0 >> CCflag_I_bits) & CCflag_I_mask);
1017
57.3k
  int G = ((iw0 >> CCflag_G_bits) & CCflag_G_mask);
1018
57.3k
  int opc = ((iw0 >> CCflag_opc_bits) & CCflag_opc_mask);
1019
1020
57.3k
  if (priv->parallel)
1021
2.31k
    return 0;
1022
1023
55.0k
  if (opc == 0 && I == 0 && G == 0)
1024
4.46k
    {
1025
4.46k
      OUTS (outf, "CC = ");
1026
4.46k
      OUTS (outf, dregs (x));
1027
4.46k
      OUTS (outf, " == ");
1028
4.46k
      OUTS (outf, dregs (y));
1029
4.46k
    }
1030
50.5k
  else if (opc == 1 && I == 0 && G == 0)
1031
448
    {
1032
448
      OUTS (outf, "CC = ");
1033
448
      OUTS (outf, dregs (x));
1034
448
      OUTS (outf, " < ");
1035
448
      OUTS (outf, dregs (y));
1036
448
    }
1037
50.1k
  else if (opc == 2 && I == 0 && G == 0)
1038
5.78k
    {
1039
5.78k
      OUTS (outf, "CC = ");
1040
5.78k
      OUTS (outf, dregs (x));
1041
5.78k
      OUTS (outf, " <= ");
1042
5.78k
      OUTS (outf, dregs (y));
1043
5.78k
    }
1044
44.3k
  else if (opc == 3 && I == 0 && G == 0)
1045
615
    {
1046
615
      OUTS (outf, "CC = ");
1047
615
      OUTS (outf, dregs (x));
1048
615
      OUTS (outf, " < ");
1049
615
      OUTS (outf, dregs (y));
1050
615
      OUTS (outf, " (IU)");
1051
615
    }
1052
43.7k
  else if (opc == 4 && I == 0 && G == 0)
1053
3.45k
    {
1054
3.45k
      OUTS (outf, "CC = ");
1055
3.45k
      OUTS (outf, dregs (x));
1056
3.45k
      OUTS (outf, " <= ");
1057
3.45k
      OUTS (outf, dregs (y));
1058
3.45k
      OUTS (outf, " (IU)");
1059
3.45k
    }
1060
40.2k
  else if (opc == 0 && I == 1 && G == 0)
1061
2.71k
    {
1062
2.71k
      OUTS (outf, "CC = ");
1063
2.71k
      OUTS (outf, dregs (x));
1064
2.71k
      OUTS (outf, " == ");
1065
2.71k
      OUTS (outf, imm3 (y));
1066
2.71k
    }
1067
37.5k
  else if (opc == 1 && I == 1 && G == 0)
1068
656
    {
1069
656
      OUTS (outf, "CC = ");
1070
656
      OUTS (outf, dregs (x));
1071
656
      OUTS (outf, " < ");
1072
656
      OUTS (outf, imm3 (y));
1073
656
    }
1074
36.8k
  else if (opc == 2 && I == 1 && G == 0)
1075
1.84k
    {
1076
1.84k
      OUTS (outf, "CC = ");
1077
1.84k
      OUTS (outf, dregs (x));
1078
1.84k
      OUTS (outf, " <= ");
1079
1.84k
      OUTS (outf, imm3 (y));
1080
1.84k
    }
1081
35.0k
  else if (opc == 3 && I == 1 && G == 0)
1082
542
    {
1083
542
      OUTS (outf, "CC = ");
1084
542
      OUTS (outf, dregs (x));
1085
542
      OUTS (outf, " < ");
1086
542
      OUTS (outf, uimm3 (y));
1087
542
      OUTS (outf, " (IU)");
1088
542
    }
1089
34.4k
  else if (opc == 4 && I == 1 && G == 0)
1090
4.90k
    {
1091
4.90k
      OUTS (outf, "CC = ");
1092
4.90k
      OUTS (outf, dregs (x));
1093
4.90k
      OUTS (outf, " <= ");
1094
4.90k
      OUTS (outf, uimm3 (y));
1095
4.90k
      OUTS (outf, " (IU)");
1096
4.90k
    }
1097
29.5k
  else if (opc == 0 && I == 0 && G == 1)
1098
809
    {
1099
809
      OUTS (outf, "CC = ");
1100
809
      OUTS (outf, pregs (x));
1101
809
      OUTS (outf, " == ");
1102
809
      OUTS (outf, pregs (y));
1103
809
    }
1104
28.7k
  else if (opc == 1 && I == 0 && G == 1)
1105
2.29k
    {
1106
2.29k
      OUTS (outf, "CC = ");
1107
2.29k
      OUTS (outf, pregs (x));
1108
2.29k
      OUTS (outf, " < ");
1109
2.29k
      OUTS (outf, pregs (y));
1110
2.29k
    }
1111
26.4k
  else if (opc == 2 && I == 0 && G == 1)
1112
1.45k
    {
1113
1.45k
      OUTS (outf, "CC = ");
1114
1.45k
      OUTS (outf, pregs (x));
1115
1.45k
      OUTS (outf, " <= ");
1116
1.45k
      OUTS (outf, pregs (y));
1117
1.45k
    }
1118
25.0k
  else if (opc == 3 && I == 0 && G == 1)
1119
2.65k
    {
1120
2.65k
      OUTS (outf, "CC = ");
1121
2.65k
      OUTS (outf, pregs (x));
1122
2.65k
      OUTS (outf, " < ");
1123
2.65k
      OUTS (outf, pregs (y));
1124
2.65k
      OUTS (outf, " (IU)");
1125
2.65k
    }
1126
22.3k
  else if (opc == 4 && I == 0 && G == 1)
1127
722
    {
1128
722
      OUTS (outf, "CC = ");
1129
722
      OUTS (outf, pregs (x));
1130
722
      OUTS (outf, " <= ");
1131
722
      OUTS (outf, pregs (y));
1132
722
      OUTS (outf, " (IU)");
1133
722
    }
1134
21.6k
  else if (opc == 0 && I == 1 && G == 1)
1135
333
    {
1136
333
      OUTS (outf, "CC = ");
1137
333
      OUTS (outf, pregs (x));
1138
333
      OUTS (outf, " == ");
1139
333
      OUTS (outf, imm3 (y));
1140
333
    }
1141
21.3k
  else if (opc == 1 && I == 1 && G == 1)
1142
1.01k
    {
1143
1.01k
      OUTS (outf, "CC = ");
1144
1.01k
      OUTS (outf, pregs (x));
1145
1.01k
      OUTS (outf, " < ");
1146
1.01k
      OUTS (outf, imm3 (y));
1147
1.01k
    }
1148
20.3k
  else if (opc == 2 && I == 1 && G == 1)
1149
368
    {
1150
368
      OUTS (outf, "CC = ");
1151
368
      OUTS (outf, pregs (x));
1152
368
      OUTS (outf, " <= ");
1153
368
      OUTS (outf, imm3 (y));
1154
368
    }
1155
19.9k
  else if (opc == 3 && I == 1 && G == 1)
1156
740
    {
1157
740
      OUTS (outf, "CC = ");
1158
740
      OUTS (outf, pregs (x));
1159
740
      OUTS (outf, " < ");
1160
740
      OUTS (outf, uimm3 (y));
1161
740
      OUTS (outf, " (IU)");
1162
740
    }
1163
19.2k
  else if (opc == 4 && I == 1 && G == 1)
1164
872
    {
1165
872
      OUTS (outf, "CC = ");
1166
872
      OUTS (outf, pregs (x));
1167
872
      OUTS (outf, " <= ");
1168
872
      OUTS (outf, uimm3 (y));
1169
872
      OUTS (outf, " (IU)");
1170
872
    }
1171
18.3k
  else if (opc == 5 && I == 0 && G == 0 && x == 0 && y == 0)
1172
629
    OUTS (outf, "CC = A0 == A1");
1173
1174
17.7k
  else if (opc == 6 && I == 0 && G == 0 && x == 0 && y == 0)
1175
705
    OUTS (outf, "CC = A0 < A1");
1176
1177
16.9k
  else if (opc == 7 && I == 0 && G == 0 && x == 0 && y == 0)
1178
256
    OUTS (outf, "CC = A0 <= A1");
1179
1180
16.7k
  else
1181
16.7k
    return 0;
1182
38.2k
  return 2;
1183
55.0k
}
1184
1185
static int
1186
decode_CC2dreg_0 (TIword iw0, disassemble_info *outf)
1187
4.09k
{
1188
4.09k
  struct private *priv = outf->private_data;
1189
  /* CC2dreg
1190
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1191
     | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 |.op....|.reg.......|
1192
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
1193
4.09k
  int op  = ((iw0 >> CC2dreg_op_bits) & CC2dreg_op_mask);
1194
4.09k
  int reg = ((iw0 >> CC2dreg_reg_bits) & CC2dreg_reg_mask);
1195
1196
4.09k
  if (priv->parallel)
1197
118
    return 0;
1198
1199
3.97k
  if (op == 0)
1200
3.05k
    {
1201
3.05k
      OUTS (outf, dregs (reg));
1202
3.05k
      OUTS (outf, " = CC");
1203
3.05k
    }
1204
922
  else if (op == 1)
1205
401
    {
1206
401
      OUTS (outf, "CC = ");
1207
401
      OUTS (outf, dregs (reg));
1208
401
    }
1209
521
  else if (op == 3 && reg == 0)
1210
97
    OUTS (outf, "CC = !CC");
1211
424
  else
1212
424
    return 0;
1213
1214
3.55k
  return 2;
1215
3.97k
}
1216
1217
static int
1218
decode_CC2stat_0 (TIword iw0, disassemble_info *outf)
1219
13.0k
{
1220
13.0k
  struct private *priv = outf->private_data;
1221
  /* CC2stat
1222
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1223
     | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |.D.|.op....|.cbit..............|
1224
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
1225
13.0k
  int D    = ((iw0 >> CC2stat_D_bits) & CC2stat_D_mask);
1226
13.0k
  int op   = ((iw0 >> CC2stat_op_bits) & CC2stat_op_mask);
1227
13.0k
  int cbit = ((iw0 >> CC2stat_cbit_bits) & CC2stat_cbit_mask);
1228
1229
13.0k
  const char *bitname = statbits (cbit);
1230
13.0k
  const char * const op_names[] = { "", "|", "&", "^" } ;
1231
1232
13.0k
  if (priv->parallel)
1233
462
    return 0;
1234
1235
12.5k
  if (decode_statbits[cbit] == REG_LASTREG)
1236
3.62k
    {
1237
      /* All ASTAT bits except CC may be operated on in hardware, but may
1238
         not have a dedicated insn, so still decode "valid" insns.  */
1239
3.62k
      static char bitnames[64];
1240
3.62k
      if (cbit != 5)
1241
3.38k
  sprintf (bitnames, "ASTAT[%i /* unused bit */]", cbit);
1242
245
      else
1243
245
  return 0;
1244
1245
3.38k
      bitname = bitnames;
1246
3.38k
    }
1247
1248
12.3k
  if (D == 0)
1249
8.52k
    OUT (outf, "CC %s= %s", op_names[op], bitname);
1250
3.79k
  else
1251
3.79k
    OUT (outf, "%s %s= CC", bitname, op_names[op]);
1252
1253
12.3k
  return 2;
1254
12.5k
}
1255
1256
static int
1257
decode_BRCC_0 (TIword iw0, bfd_vma pc, disassemble_info *outf)
1258
66.6k
{
1259
66.6k
  struct private *priv = outf->private_data;
1260
  /* BRCC
1261
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1262
     | 0 | 0 | 0 | 1 |.T.|.B.|.offset................................|
1263
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
1264
66.6k
  int B = ((iw0 >> BRCC_B_bits) & BRCC_B_mask);
1265
66.6k
  int T = ((iw0 >> BRCC_T_bits) & BRCC_T_mask);
1266
66.6k
  int offset = ((iw0 >> BRCC_offset_bits) & BRCC_offset_mask);
1267
1268
66.6k
  if (priv->parallel)
1269
2.22k
    return 0;
1270
1271
64.4k
  if (T == 1 && B == 1)
1272
13.9k
    {
1273
13.9k
      OUTS (outf, "IF CC JUMP 0x");
1274
13.9k
      OUTS (outf, pcrel10 (offset));
1275
13.9k
      OUTS (outf, " (BP)");
1276
13.9k
    }
1277
50.5k
  else if (T == 0 && B == 1)
1278
12.3k
    {
1279
12.3k
      OUTS (outf, "IF !CC JUMP 0x");
1280
12.3k
      OUTS (outf, pcrel10 (offset));
1281
12.3k
      OUTS (outf, " (BP)");
1282
12.3k
    }
1283
38.1k
  else if (T == 1)
1284
13.7k
    {
1285
13.7k
      OUTS (outf, "IF CC JUMP 0x");
1286
13.7k
      OUTS (outf, pcrel10 (offset));
1287
13.7k
    }
1288
24.4k
  else if (T == 0)
1289
24.4k
    {
1290
24.4k
      OUTS (outf, "IF !CC JUMP 0x");
1291
24.4k
      OUTS (outf, pcrel10 (offset));
1292
24.4k
    }
1293
0
  else
1294
0
    return 0;
1295
1296
64.4k
  return 2;
1297
64.4k
}
1298
1299
static int
1300
decode_UJUMP_0 (TIword iw0, bfd_vma pc, disassemble_info *outf)
1301
90.4k
{
1302
90.4k
  struct private *priv = outf->private_data;
1303
  /* UJUMP
1304
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1305
     | 0 | 0 | 1 | 0 |.offset........................................|
1306
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
1307
90.4k
  int offset = ((iw0 >> UJump_offset_bits) & UJump_offset_mask);
1308
1309
90.4k
  if (priv->parallel)
1310
4.77k
    return 0;
1311
1312
85.6k
  OUTS (outf, "JUMP.S 0x");
1313
85.6k
  OUTS (outf, pcrel12 (offset));
1314
85.6k
  return 2;
1315
90.4k
}
1316
1317
static int
1318
decode_REGMV_0 (TIword iw0, disassemble_info *outf)
1319
102k
{
1320
  /* REGMV
1321
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1322
     | 0 | 0 | 1 | 1 |.gd........|.gs........|.dst.......|.src.......|
1323
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
1324
102k
  int gs  = ((iw0 >> RegMv_gs_bits) & RegMv_gs_mask);
1325
102k
  int gd  = ((iw0 >> RegMv_gd_bits) & RegMv_gd_mask);
1326
102k
  int src = ((iw0 >> RegMv_src_bits) & RegMv_src_mask);
1327
102k
  int dst = ((iw0 >> RegMv_dst_bits) & RegMv_dst_mask);
1328
1329
  /* Reserved slots cannot be a src/dst.  */
1330
102k
  if (IS_RESERVEDREG (gs, src) || IS_RESERVEDREG (gd, dst))
1331
23.6k
    goto invalid_move;
1332
1333
  /* Standard register moves  */
1334
79.0k
  if ((gs < 2) ||                               /* Dregs/Pregs as source  */
1335
79.0k
      (gd < 2) ||                               /* Dregs/Pregs as dest    */
1336
79.0k
      (gs == 4 && src < 4) ||                   /* Accumulators as source */
1337
79.0k
      (gd == 4 && dst < 4 && (gs < 4)) ||       /* Accumulators as dest   */
1338
79.0k
      (gs == 7 && src == 7 && !(gd == 4 && dst < 4)) || /* EMUDAT as src  */
1339
79.0k
      (gd == 7 && dst == 7))                    /* EMUDAT as dest         */
1340
64.2k
    goto valid_move;
1341
1342
  /* dareg = dareg (IMBL) */
1343
14.7k
  if (gs < 4 && gd < 4)
1344
3.70k
    goto valid_move;
1345
1346
  /* USP can be src to sysregs, but not dagregs.  */
1347
11.0k
  if ((gs == 7 && src == 0) && (gd >= 4))
1348
710
    goto valid_move;
1349
1350
  /* USP can move between genregs (only check Accumulators).  */
1351
10.3k
  if (((gs == 7 && src == 0) && (gd == 4 && dst < 4)) ||
1352
10.3k
      ((gd == 7 && dst == 0) && (gs == 4 && src < 4)))
1353
0
    goto valid_move;
1354
1355
  /* Still here ?  Invalid reg pair.  */
1356
34.0k
 invalid_move:
1357
34.0k
  return 0;
1358
1359
68.6k
 valid_move:
1360
68.6k
  OUTS (outf, allregs (dst, gd));
1361
68.6k
  OUTS (outf, " = ");
1362
68.6k
  OUTS (outf, allregs (src, gs));
1363
68.6k
  return 2;
1364
10.3k
}
1365
1366
static int
1367
decode_ALU2op_0 (TIword iw0, disassemble_info *outf)
1368
34.0k
{
1369
  /* ALU2op
1370
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1371
     | 0 | 1 | 0 | 0 | 0 | 0 |.opc...........|.src.......|.dst.......|
1372
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
1373
34.0k
  int src = ((iw0 >> ALU2op_src_bits) & ALU2op_src_mask);
1374
34.0k
  int opc = ((iw0 >> ALU2op_opc_bits) & ALU2op_opc_mask);
1375
34.0k
  int dst = ((iw0 >> ALU2op_dst_bits) & ALU2op_dst_mask);
1376
1377
34.0k
  if (opc == 0)
1378
4.15k
    {
1379
4.15k
      OUTS (outf, dregs (dst));
1380
4.15k
      OUTS (outf, " >>>= ");
1381
4.15k
      OUTS (outf, dregs (src));
1382
4.15k
    }
1383
29.8k
  else if (opc == 1)
1384
3.70k
    {
1385
3.70k
      OUTS (outf, dregs (dst));
1386
3.70k
      OUTS (outf, " >>= ");
1387
3.70k
      OUTS (outf, dregs (src));
1388
3.70k
    }
1389
26.1k
  else if (opc == 2)
1390
977
    {
1391
977
      OUTS (outf, dregs (dst));
1392
977
      OUTS (outf, " <<= ");
1393
977
      OUTS (outf, dregs (src));
1394
977
    }
1395
25.1k
  else if (opc == 3)
1396
1.89k
    {
1397
1.89k
      OUTS (outf, dregs (dst));
1398
1.89k
      OUTS (outf, " *= ");
1399
1.89k
      OUTS (outf, dregs (src));
1400
1.89k
    }
1401
23.2k
  else if (opc == 4)
1402
1.80k
    {
1403
1.80k
      OUTS (outf, dregs (dst));
1404
1.80k
      OUTS (outf, " = (");
1405
1.80k
      OUTS (outf, dregs (dst));
1406
1.80k
      OUTS (outf, " + ");
1407
1.80k
      OUTS (outf, dregs (src));
1408
1.80k
      OUTS (outf, ") << 0x1");
1409
1.80k
    }
1410
21.4k
  else if (opc == 5)
1411
9.55k
    {
1412
9.55k
      OUTS (outf, dregs (dst));
1413
9.55k
      OUTS (outf, " = (");
1414
9.55k
      OUTS (outf, dregs (dst));
1415
9.55k
      OUTS (outf, " + ");
1416
9.55k
      OUTS (outf, dregs (src));
1417
9.55k
      OUTS (outf, ") << 0x2");
1418
9.55k
    }
1419
11.9k
  else if (opc == 8)
1420
1.01k
    {
1421
1.01k
      OUTS (outf, "DIVQ (");
1422
1.01k
      OUTS (outf, dregs (dst));
1423
1.01k
      OUTS (outf, ", ");
1424
1.01k
      OUTS (outf, dregs (src));
1425
1.01k
      OUTS (outf, ")");
1426
1.01k
    }
1427
10.8k
  else if (opc == 9)
1428
2.84k
    {
1429
2.84k
      OUTS (outf, "DIVS (");
1430
2.84k
      OUTS (outf, dregs (dst));
1431
2.84k
      OUTS (outf, ", ");
1432
2.84k
      OUTS (outf, dregs (src));
1433
2.84k
      OUTS (outf, ")");
1434
2.84k
    }
1435
8.05k
  else if (opc == 10)
1436
498
    {
1437
498
      OUTS (outf, dregs (dst));
1438
498
      OUTS (outf, " = ");
1439
498
      OUTS (outf, dregs_lo (src));
1440
498
      OUTS (outf, " (X)");
1441
498
    }
1442
7.55k
  else if (opc == 11)
1443
2.37k
    {
1444
2.37k
      OUTS (outf, dregs (dst));
1445
2.37k
      OUTS (outf, " = ");
1446
2.37k
      OUTS (outf, dregs_lo (src));
1447
2.37k
      OUTS (outf, " (Z)");
1448
2.37k
    }
1449
5.18k
  else if (opc == 12)
1450
742
    {
1451
742
      OUTS (outf, dregs (dst));
1452
742
      OUTS (outf, " = ");
1453
742
      OUTS (outf, dregs_byte (src));
1454
742
      OUTS (outf, " (X)");
1455
742
    }
1456
4.43k
  else if (opc == 13)
1457
1.69k
    {
1458
1.69k
      OUTS (outf, dregs (dst));
1459
1.69k
      OUTS (outf, " = ");
1460
1.69k
      OUTS (outf, dregs_byte (src));
1461
1.69k
      OUTS (outf, " (Z)");
1462
1.69k
    }
1463
2.74k
  else if (opc == 14)
1464
424
    {
1465
424
      OUTS (outf, dregs (dst));
1466
424
      OUTS (outf, " = -");
1467
424
      OUTS (outf, dregs (src));
1468
424
    }
1469
2.31k
  else if (opc == 15)
1470
484
    {
1471
484
      OUTS (outf, dregs (dst));
1472
484
      OUTS (outf, " =~ ");
1473
484
      OUTS (outf, dregs (src));
1474
484
    }
1475
1.83k
  else
1476
1.83k
    return 0;
1477
1478
32.1k
  return 2;
1479
34.0k
}
1480
1481
static int
1482
decode_PTR2op_0 (TIword iw0, disassemble_info *outf)
1483
11.6k
{
1484
  /* PTR2op
1485
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1486
     | 0 | 1 | 0 | 0 | 0 | 1 | 0 |.opc.......|.src.......|.dst.......|
1487
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
1488
11.6k
  int src = ((iw0 >> PTR2op_src_bits) & PTR2op_dst_mask);
1489
11.6k
  int opc = ((iw0 >> PTR2op_opc_bits) & PTR2op_opc_mask);
1490
11.6k
  int dst = ((iw0 >> PTR2op_dst_bits) & PTR2op_dst_mask);
1491
1492
11.6k
  if (opc == 0)
1493
2.45k
    {
1494
2.45k
      OUTS (outf, pregs (dst));
1495
2.45k
      OUTS (outf, " -= ");
1496
2.45k
      OUTS (outf, pregs (src));
1497
2.45k
    }
1498
9.15k
  else if (opc == 1)
1499
2.13k
    {
1500
2.13k
      OUTS (outf, pregs (dst));
1501
2.13k
      OUTS (outf, " = ");
1502
2.13k
      OUTS (outf, pregs (src));
1503
2.13k
      OUTS (outf, " << 0x2");
1504
2.13k
    }
1505
7.02k
  else if (opc == 3)
1506
1.42k
    {
1507
1.42k
      OUTS (outf, pregs (dst));
1508
1.42k
      OUTS (outf, " = ");
1509
1.42k
      OUTS (outf, pregs (src));
1510
1.42k
      OUTS (outf, " >> 0x2");
1511
1.42k
    }
1512
5.59k
  else if (opc == 4)
1513
914
    {
1514
914
      OUTS (outf, pregs (dst));
1515
914
      OUTS (outf, " = ");
1516
914
      OUTS (outf, pregs (src));
1517
914
      OUTS (outf, " >> 0x1");
1518
914
    }
1519
4.68k
  else if (opc == 5)
1520
2.37k
    {
1521
2.37k
      OUTS (outf, pregs (dst));
1522
2.37k
      OUTS (outf, " += ");
1523
2.37k
      OUTS (outf, pregs (src));
1524
2.37k
      OUTS (outf, " (BREV)");
1525
2.37k
    }
1526
2.30k
  else if (opc == 6)
1527
399
    {
1528
399
      OUTS (outf, pregs (dst));
1529
399
      OUTS (outf, " = (");
1530
399
      OUTS (outf, pregs (dst));
1531
399
      OUTS (outf, " + ");
1532
399
      OUTS (outf, pregs (src));
1533
399
      OUTS (outf, ") << 0x1");
1534
399
    }
1535
1.90k
  else if (opc == 7)
1536
595
    {
1537
595
      OUTS (outf, pregs (dst));
1538
595
      OUTS (outf, " = (");
1539
595
      OUTS (outf, pregs (dst));
1540
595
      OUTS (outf, " + ");
1541
595
      OUTS (outf, pregs (src));
1542
595
      OUTS (outf, ") << 0x2");
1543
595
    }
1544
1.31k
  else
1545
1.31k
    return 0;
1546
1547
10.3k
  return 2;
1548
11.6k
}
1549
1550
static int
1551
decode_LOGI2op_0 (TIword iw0, disassemble_info *outf)
1552
34.1k
{
1553
34.1k
  struct private *priv = outf->private_data;
1554
  /* LOGI2op
1555
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1556
     | 0 | 1 | 0 | 0 | 1 |.opc.......|.src...............|.dst.......|
1557
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
1558
34.1k
  int src = ((iw0 >> LOGI2op_src_bits) & LOGI2op_src_mask);
1559
34.1k
  int opc = ((iw0 >> LOGI2op_opc_bits) & LOGI2op_opc_mask);
1560
34.1k
  int dst = ((iw0 >> LOGI2op_dst_bits) & LOGI2op_dst_mask);
1561
1562
34.1k
  if (priv->parallel)
1563
871
    return 0;
1564
1565
33.2k
  if (opc == 0)
1566
4.18k
    {
1567
4.18k
      OUTS (outf, "CC = !BITTST (");
1568
4.18k
      OUTS (outf, dregs (dst));
1569
4.18k
      OUTS (outf, ", ");
1570
4.18k
      OUTS (outf, uimm5 (src));
1571
4.18k
      OUTS (outf, ");\t\t/* bit");
1572
4.18k
      OUTS (outf, imm7d (src));
1573
4.18k
      OUTS (outf, " */");
1574
4.18k
      priv->comment = true;
1575
4.18k
    }
1576
29.1k
  else if (opc == 1)
1577
3.93k
    {
1578
3.93k
      OUTS (outf, "CC = BITTST (");
1579
3.93k
      OUTS (outf, dregs (dst));
1580
3.93k
      OUTS (outf, ", ");
1581
3.93k
      OUTS (outf, uimm5 (src));
1582
3.93k
      OUTS (outf, ");\t\t/* bit");
1583
3.93k
      OUTS (outf, imm7d (src));
1584
3.93k
      OUTS (outf, " */");
1585
3.93k
      priv->comment = true;
1586
3.93k
    }
1587
25.1k
  else if (opc == 2)
1588
4.59k
    {
1589
4.59k
      OUTS (outf, "BITSET (");
1590
4.59k
      OUTS (outf, dregs (dst));
1591
4.59k
      OUTS (outf, ", ");
1592
4.59k
      OUTS (outf, uimm5 (src));
1593
4.59k
      OUTS (outf, ");\t\t/* bit");
1594
4.59k
      OUTS (outf, imm7d (src));
1595
4.59k
      OUTS (outf, " */");
1596
4.59k
      priv->comment = true;
1597
4.59k
    }
1598
20.5k
  else if (opc == 3)
1599
1.55k
    {
1600
1.55k
      OUTS (outf, "BITTGL (");
1601
1.55k
      OUTS (outf, dregs (dst));
1602
1.55k
      OUTS (outf, ", ");
1603
1.55k
      OUTS (outf, uimm5 (src));
1604
1.55k
      OUTS (outf, ");\t\t/* bit");
1605
1.55k
      OUTS (outf, imm7d (src));
1606
1.55k
      OUTS (outf, " */");
1607
1.55k
      priv->comment = true;
1608
1.55k
    }
1609
19.0k
  else if (opc == 4)
1610
3.41k
    {
1611
3.41k
      OUTS (outf, "BITCLR (");
1612
3.41k
      OUTS (outf, dregs (dst));
1613
3.41k
      OUTS (outf, ", ");
1614
3.41k
      OUTS (outf, uimm5 (src));
1615
3.41k
      OUTS (outf, ");\t\t/* bit");
1616
3.41k
      OUTS (outf, imm7d (src));
1617
3.41k
      OUTS (outf, " */");
1618
3.41k
      priv->comment = true;
1619
3.41k
    }
1620
15.6k
  else if (opc == 5)
1621
4.07k
    {
1622
4.07k
      OUTS (outf, dregs (dst));
1623
4.07k
      OUTS (outf, " >>>= ");
1624
4.07k
      OUTS (outf, uimm5 (src));
1625
4.07k
    }
1626
11.5k
  else if (opc == 6)
1627
3.09k
    {
1628
3.09k
      OUTS (outf, dregs (dst));
1629
3.09k
      OUTS (outf, " >>= ");
1630
3.09k
      OUTS (outf, uimm5 (src));
1631
3.09k
    }
1632
8.43k
  else if (opc == 7)
1633
8.43k
    {
1634
8.43k
      OUTS (outf, dregs (dst));
1635
8.43k
      OUTS (outf, " <<= ");
1636
8.43k
      OUTS (outf, uimm5 (src));
1637
8.43k
    }
1638
0
  else
1639
0
    return 0;
1640
1641
33.2k
  return 2;
1642
33.2k
}
1643
1644
static int
1645
decode_COMP3op_0 (TIword iw0, disassemble_info *outf)
1646
49.8k
{
1647
  /* COMP3op
1648
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1649
     | 0 | 1 | 0 | 1 |.opc.......|.dst.......|.src1......|.src0......|
1650
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
1651
49.8k
  int opc  = ((iw0 >> COMP3op_opc_bits) & COMP3op_opc_mask);
1652
49.8k
  int dst  = ((iw0 >> COMP3op_dst_bits) & COMP3op_dst_mask);
1653
49.8k
  int src0 = ((iw0 >> COMP3op_src0_bits) & COMP3op_src0_mask);
1654
49.8k
  int src1 = ((iw0 >> COMP3op_src1_bits) & COMP3op_src1_mask);
1655
1656
49.8k
  if (opc == 5 && src1 == src0)
1657
2.18k
    {
1658
2.18k
      OUTS (outf, pregs (dst));
1659
2.18k
      OUTS (outf, " = ");
1660
2.18k
      OUTS (outf, pregs (src0));
1661
2.18k
      OUTS (outf, " << 0x1");
1662
2.18k
    }
1663
47.6k
  else if (opc == 1)
1664
6.60k
    {
1665
6.60k
      OUTS (outf, dregs (dst));
1666
6.60k
      OUTS (outf, " = ");
1667
6.60k
      OUTS (outf, dregs (src0));
1668
6.60k
      OUTS (outf, " - ");
1669
6.60k
      OUTS (outf, dregs (src1));
1670
6.60k
    }
1671
41.0k
  else if (opc == 2)
1672
6.96k
    {
1673
6.96k
      OUTS (outf, dregs (dst));
1674
6.96k
      OUTS (outf, " = ");
1675
6.96k
      OUTS (outf, dregs (src0));
1676
6.96k
      OUTS (outf, " & ");
1677
6.96k
      OUTS (outf, dregs (src1));
1678
6.96k
    }
1679
34.1k
  else if (opc == 3)
1680
4.64k
    {
1681
4.64k
      OUTS (outf, dregs (dst));
1682
4.64k
      OUTS (outf, " = ");
1683
4.64k
      OUTS (outf, dregs (src0));
1684
4.64k
      OUTS (outf, " | ");
1685
4.64k
      OUTS (outf, dregs (src1));
1686
4.64k
    }
1687
29.4k
  else if (opc == 4)
1688
3.77k
    {
1689
3.77k
      OUTS (outf, dregs (dst));
1690
3.77k
      OUTS (outf, " = ");
1691
3.77k
      OUTS (outf, dregs (src0));
1692
3.77k
      OUTS (outf, " ^ ");
1693
3.77k
      OUTS (outf, dregs (src1));
1694
3.77k
    }
1695
25.6k
  else if (opc == 5)
1696
2.48k
    {
1697
2.48k
      OUTS (outf, pregs (dst));
1698
2.48k
      OUTS (outf, " = ");
1699
2.48k
      OUTS (outf, pregs (src0));
1700
2.48k
      OUTS (outf, " + ");
1701
2.48k
      OUTS (outf, pregs (src1));
1702
2.48k
    }
1703
23.2k
  else if (opc == 6)
1704
8.00k
    {
1705
8.00k
      OUTS (outf, pregs (dst));
1706
8.00k
      OUTS (outf, " = ");
1707
8.00k
      OUTS (outf, pregs (src0));
1708
8.00k
      OUTS (outf, " + (");
1709
8.00k
      OUTS (outf, pregs (src1));
1710
8.00k
      OUTS (outf, " << 0x1)");
1711
8.00k
    }
1712
15.1k
  else if (opc == 7)
1713
8.96k
    {
1714
8.96k
      OUTS (outf, pregs (dst));
1715
8.96k
      OUTS (outf, " = ");
1716
8.96k
      OUTS (outf, pregs (src0));
1717
8.96k
      OUTS (outf, " + (");
1718
8.96k
      OUTS (outf, pregs (src1));
1719
8.96k
      OUTS (outf, " << 0x2)");
1720
8.96k
    }
1721
6.23k
  else if (opc == 0)
1722
6.23k
    {
1723
6.23k
      OUTS (outf, dregs (dst));
1724
6.23k
      OUTS (outf, " = ");
1725
6.23k
      OUTS (outf, dregs (src0));
1726
6.23k
      OUTS (outf, " + ");
1727
6.23k
      OUTS (outf, dregs (src1));
1728
6.23k
    }
1729
0
  else
1730
0
    return 0;
1731
1732
49.8k
  return 2;
1733
49.8k
}
1734
1735
static int
1736
decode_COMPI2opD_0 (TIword iw0, disassemble_info *outf)
1737
63.9k
{
1738
63.9k
  struct private *priv = outf->private_data;
1739
  /* COMPI2opD
1740
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1741
     | 0 | 1 | 1 | 0 | 0 |.op|..src......................|.dst.......|
1742
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
1743
63.9k
  int op  = ((iw0 >> COMPI2opD_op_bits) & COMPI2opD_op_mask);
1744
63.9k
  int dst = ((iw0 >> COMPI2opD_dst_bits) & COMPI2opD_dst_mask);
1745
63.9k
  int src = ((iw0 >> COMPI2opD_src_bits) & COMPI2opD_src_mask);
1746
1747
63.9k
  bu32 *pval = get_allreg (0, dst);
1748
1749
63.9k
  if (priv->parallel)
1750
2.34k
    return 0;
1751
1752
  /* Since we don't have 32-bit immediate loads, we allow the disassembler
1753
     to combine them, so it prints out the right values.
1754
     Here we keep track of the registers.  */
1755
61.5k
  if (op == 0)
1756
37.5k
    {
1757
37.5k
      *pval = imm7_val (src);
1758
37.5k
      if (src & 0x40)
1759
16.0k
  *pval |= 0xFFFFFF80;
1760
21.5k
      else
1761
21.5k
  *pval &= 0x7F;
1762
37.5k
    }
1763
1764
61.5k
  if (op == 0)
1765
37.5k
    {
1766
37.5k
      OUTS (outf, dregs (dst));
1767
37.5k
      OUTS (outf, " = ");
1768
37.5k
      OUTS (outf, imm7 (src));
1769
37.5k
      OUTS (outf, " (X);\t\t/*\t\t");
1770
37.5k
      OUTS (outf, dregs (dst));
1771
37.5k
      OUTS (outf, "=");
1772
37.5k
      OUTS (outf, uimm32 (*pval));
1773
37.5k
      OUTS (outf, "(");
1774
37.5k
      OUTS (outf, imm32 (*pval));
1775
37.5k
      OUTS (outf, ") */");
1776
37.5k
      priv->comment = true;
1777
37.5k
    }
1778
24.0k
  else if (op == 1)
1779
24.0k
    {
1780
24.0k
      OUTS (outf, dregs (dst));
1781
24.0k
      OUTS (outf, " += ");
1782
24.0k
      OUTS (outf, imm7 (src));
1783
24.0k
      OUTS (outf, ";\t\t/* (");
1784
24.0k
      OUTS (outf, imm7d (src));
1785
24.0k
      OUTS (outf, ") */");
1786
24.0k
      priv->comment = true;
1787
24.0k
    }
1788
0
  else
1789
0
    return 0;
1790
1791
61.5k
  return 2;
1792
61.5k
}
1793
1794
static int
1795
decode_COMPI2opP_0 (TIword iw0, disassemble_info *outf)
1796
49.5k
{
1797
49.5k
  struct private *priv = outf->private_data;
1798
  /* COMPI2opP
1799
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1800
     | 0 | 1 | 1 | 0 | 1 |.op|.src.......................|.dst.......|
1801
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
1802
49.5k
  int op  = ((iw0 >> COMPI2opP_op_bits) & COMPI2opP_op_mask);
1803
49.5k
  int src = ((iw0 >> COMPI2opP_src_bits) & COMPI2opP_src_mask);
1804
49.5k
  int dst = ((iw0 >> COMPI2opP_dst_bits) & COMPI2opP_dst_mask);
1805
1806
49.5k
  bu32 *pval = get_allreg (1, dst);
1807
1808
49.5k
  if (priv->parallel)
1809
2.77k
    return 0;
1810
1811
46.8k
  if (op == 0)
1812
23.6k
    {
1813
23.6k
      *pval = imm7_val (src);
1814
23.6k
      if (src & 0x40)
1815
8.84k
  *pval |= 0xFFFFFF80;
1816
14.7k
      else
1817
14.7k
  *pval &= 0x7F;
1818
23.6k
    }
1819
1820
46.8k
  if (op == 0)
1821
23.6k
    {
1822
23.6k
      OUTS (outf, pregs (dst));
1823
23.6k
      OUTS (outf, " = ");
1824
23.6k
      OUTS (outf, imm7 (src));
1825
23.6k
      OUTS (outf, " (X);\t\t/*\t\t");
1826
23.6k
      OUTS (outf, pregs (dst));
1827
23.6k
      OUTS (outf, "=");
1828
23.6k
      OUTS (outf, uimm32 (*pval));
1829
23.6k
      OUTS (outf, "(");
1830
23.6k
      OUTS (outf, imm32 (*pval));
1831
23.6k
      OUTS (outf, ") */");
1832
23.6k
      priv->comment = true;
1833
23.6k
    }
1834
23.2k
  else if (op == 1)
1835
23.2k
    {
1836
23.2k
      OUTS (outf, pregs (dst));
1837
23.2k
      OUTS (outf, " += ");
1838
23.2k
      OUTS (outf, imm7 (src));
1839
23.2k
      OUTS (outf, ";\t\t/* (");
1840
23.2k
      OUTS (outf, imm7d (src));
1841
23.2k
      OUTS (outf, ") */");
1842
23.2k
      priv->comment = true;
1843
23.2k
    }
1844
0
  else
1845
0
    return 0;
1846
1847
46.8k
  return 2;
1848
46.8k
}
1849
1850
static int
1851
decode_LDSTpmod_0 (TIword iw0, disassemble_info *outf)
1852
58.4k
{
1853
  /* LDSTpmod
1854
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1855
     | 1 | 0 | 0 | 0 |.W.|.aop...|.reg.......|.idx.......|.ptr.......|
1856
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
1857
58.4k
  int W   = ((iw0 >> LDSTpmod_W_bits) & LDSTpmod_W_mask);
1858
58.4k
  int aop = ((iw0 >> LDSTpmod_aop_bits) & LDSTpmod_aop_mask);
1859
58.4k
  int idx = ((iw0 >> LDSTpmod_idx_bits) & LDSTpmod_idx_mask);
1860
58.4k
  int ptr = ((iw0 >> LDSTpmod_ptr_bits) & LDSTpmod_ptr_mask);
1861
58.4k
  int reg = ((iw0 >> LDSTpmod_reg_bits) & LDSTpmod_reg_mask);
1862
1863
58.4k
  if (aop == 1 && W == 0 && idx == ptr)
1864
707
    {
1865
707
      OUTS (outf, dregs_lo (reg));
1866
707
      OUTS (outf, " = W[");
1867
707
      OUTS (outf, pregs (ptr));
1868
707
      OUTS (outf, "]");
1869
707
    }
1870
57.7k
  else if (aop == 2 && W == 0 && idx == ptr)
1871
748
    {
1872
748
      OUTS (outf, dregs_hi (reg));
1873
748
      OUTS (outf, " = W[");
1874
748
      OUTS (outf, pregs (ptr));
1875
748
      OUTS (outf, "]");
1876
748
    }
1877
57.0k
  else if (aop == 1 && W == 1 && idx == ptr)
1878
568
    {
1879
568
      OUTS (outf, "W[");
1880
568
      OUTS (outf, pregs (ptr));
1881
568
      OUTS (outf, "] = ");
1882
568
      OUTS (outf, dregs_lo (reg));
1883
568
    }
1884
56.4k
  else if (aop == 2 && W == 1 && idx == ptr)
1885
701
    {
1886
701
      OUTS (outf, "W[");
1887
701
      OUTS (outf, pregs (ptr));
1888
701
      OUTS (outf, "] = ");
1889
701
      OUTS (outf, dregs_hi (reg));
1890
701
    }
1891
55.7k
  else if (aop == 0 && W == 0)
1892
18.0k
    {
1893
18.0k
      OUTS (outf, dregs (reg));
1894
18.0k
      OUTS (outf, " = [");
1895
18.0k
      OUTS (outf, pregs (ptr));
1896
18.0k
      OUTS (outf, " ++ ");
1897
18.0k
      OUTS (outf, pregs (idx));
1898
18.0k
      OUTS (outf, "]");
1899
18.0k
    }
1900
37.7k
  else if (aop == 1 && W == 0)
1901
5.41k
    {
1902
5.41k
      OUTS (outf, dregs_lo (reg));
1903
5.41k
      OUTS (outf, " = W[");
1904
5.41k
      OUTS (outf, pregs (ptr));
1905
5.41k
      OUTS (outf, " ++ ");
1906
5.41k
      OUTS (outf, pregs (idx));
1907
5.41k
      OUTS (outf, "]");
1908
5.41k
    }
1909
32.3k
  else if (aop == 2 && W == 0)
1910
5.78k
    {
1911
5.78k
      OUTS (outf, dregs_hi (reg));
1912
5.78k
      OUTS (outf, " = W[");
1913
5.78k
      OUTS (outf, pregs (ptr));
1914
5.78k
      OUTS (outf, " ++ ");
1915
5.78k
      OUTS (outf, pregs (idx));
1916
5.78k
      OUTS (outf, "]");
1917
5.78k
    }
1918
26.5k
  else if (aop == 3 && W == 0)
1919
5.30k
    {
1920
5.30k
      OUTS (outf, dregs (reg));
1921
5.30k
      OUTS (outf, " = W[");
1922
5.30k
      OUTS (outf, pregs (ptr));
1923
5.30k
      OUTS (outf, " ++ ");
1924
5.30k
      OUTS (outf, pregs (idx));
1925
5.30k
      OUTS (outf, "] (Z)");
1926
5.30k
    }
1927
21.2k
  else if (aop == 3 && W == 1)
1928
6.46k
    {
1929
6.46k
      OUTS (outf, dregs (reg));
1930
6.46k
      OUTS (outf, " = W[");
1931
6.46k
      OUTS (outf, pregs (ptr));
1932
6.46k
      OUTS (outf, " ++ ");
1933
6.46k
      OUTS (outf, pregs (idx));
1934
6.46k
      OUTS (outf, "] (X)");
1935
6.46k
    }
1936
14.7k
  else if (aop == 0 && W == 1)
1937
5.66k
    {
1938
5.66k
      OUTS (outf, "[");
1939
5.66k
      OUTS (outf, pregs (ptr));
1940
5.66k
      OUTS (outf, " ++ ");
1941
5.66k
      OUTS (outf, pregs (idx));
1942
5.66k
      OUTS (outf, "] = ");
1943
5.66k
      OUTS (outf, dregs (reg));
1944
5.66k
    }
1945
9.09k
  else if (aop == 1 && W == 1)
1946
5.62k
    {
1947
5.62k
      OUTS (outf, "W[");
1948
5.62k
      OUTS (outf, pregs (ptr));
1949
5.62k
      OUTS (outf, " ++ ");
1950
5.62k
      OUTS (outf, pregs (idx));
1951
5.62k
      OUTS (outf, "] = ");
1952
5.62k
      OUTS (outf, dregs_lo (reg));
1953
5.62k
    }
1954
3.47k
  else if (aop == 2 && W == 1)
1955
3.47k
    {
1956
3.47k
      OUTS (outf, "W[");
1957
3.47k
      OUTS (outf, pregs (ptr));
1958
3.47k
      OUTS (outf, " ++ ");
1959
3.47k
      OUTS (outf, pregs (idx));
1960
3.47k
      OUTS (outf, "] = ");
1961
3.47k
      OUTS (outf, dregs_hi (reg));
1962
3.47k
    }
1963
0
  else
1964
0
    return 0;
1965
1966
58.4k
  return 2;
1967
58.4k
}
1968
1969
static int
1970
decode_dagMODim_0 (TIword iw0, disassemble_info *outf)
1971
829
{
1972
  /* dagMODim
1973
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1974
     | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 0 |.br| 1 | 1 |.op|.m.....|.i.....|
1975
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
1976
829
  int i  = ((iw0 >> DagMODim_i_bits) & DagMODim_i_mask);
1977
829
  int m  = ((iw0 >> DagMODim_m_bits) & DagMODim_m_mask);
1978
829
  int br = ((iw0 >> DagMODim_br_bits) & DagMODim_br_mask);
1979
829
  int op = ((iw0 >> DagMODim_op_bits) & DagMODim_op_mask);
1980
1981
829
  if (op == 0 && br == 1)
1982
456
    {
1983
456
      OUTS (outf, iregs (i));
1984
456
      OUTS (outf, " += ");
1985
456
      OUTS (outf, mregs (m));
1986
456
      OUTS (outf, " (BREV)");
1987
456
    }
1988
373
  else if (op == 0)
1989
142
    {
1990
142
      OUTS (outf, iregs (i));
1991
142
      OUTS (outf, " += ");
1992
142
      OUTS (outf, mregs (m));
1993
142
    }
1994
231
  else if (op == 1 && br == 0)
1995
71
    {
1996
71
      OUTS (outf, iregs (i));
1997
71
      OUTS (outf, " -= ");
1998
71
      OUTS (outf, mregs (m));
1999
71
    }
2000
160
  else
2001
160
    return 0;
2002
2003
669
  return 2;
2004
829
}
2005
2006
static int
2007
decode_dagMODik_0 (TIword iw0, disassemble_info *outf)
2008
1.27k
{
2009
1.27k
  struct private *priv = outf->private_data;
2010
  /* dagMODik
2011
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2012
     | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 |.op....|.i.....|
2013
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
2014
1.27k
  int i  = ((iw0 >> DagMODik_i_bits) & DagMODik_i_mask);
2015
1.27k
  int op = ((iw0 >> DagMODik_op_bits) & DagMODik_op_mask);
2016
2017
1.27k
  if (op == 0)
2018
835
    {
2019
835
      OUTS (outf, iregs (i));
2020
835
      OUTS (outf, " += 0x2");
2021
835
    }
2022
444
  else if (op == 1)
2023
48
    {
2024
48
      OUTS (outf, iregs (i));
2025
48
      OUTS (outf, " -= 0x2");
2026
48
    }
2027
396
  else if (op == 2)
2028
143
    {
2029
143
      OUTS (outf, iregs (i));
2030
143
      OUTS (outf, " += 0x4");
2031
143
    }
2032
253
  else if (op == 3)
2033
253
    {
2034
253
      OUTS (outf, iregs (i));
2035
253
      OUTS (outf, " -= 0x4");
2036
253
    }
2037
0
  else
2038
0
    return 0;
2039
2040
1.27k
  if (!priv->parallel)
2041
1.27k
    {
2042
1.27k
      OUTS (outf, ";\t\t/* (  ");
2043
1.27k
      if (op == 0 || op == 1)
2044
875
  OUTS (outf, "2");
2045
396
      else if (op == 2 || op == 3)
2046
396
  OUTS (outf, "4");
2047
1.27k
      OUTS (outf, ") */");
2048
1.27k
      priv->comment = true;
2049
1.27k
    }
2050
2051
1.27k
  return 2;
2052
1.27k
}
2053
2054
static int
2055
decode_dspLDST_0 (TIword iw0, disassemble_info *outf)
2056
13.7k
{
2057
  /* dspLDST
2058
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2059
     | 1 | 0 | 0 | 1 | 1 | 1 |.W.|.aop...|.m.....|.i.....|.reg.......|
2060
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
2061
13.7k
  int i   = ((iw0 >> DspLDST_i_bits) & DspLDST_i_mask);
2062
13.7k
  int m   = ((iw0 >> DspLDST_m_bits) & DspLDST_m_mask);
2063
13.7k
  int W   = ((iw0 >> DspLDST_W_bits) & DspLDST_W_mask);
2064
13.7k
  int aop = ((iw0 >> DspLDST_aop_bits) & DspLDST_aop_mask);
2065
13.7k
  int reg = ((iw0 >> DspLDST_reg_bits) & DspLDST_reg_mask);
2066
2067
13.7k
  if (aop == 0 && W == 0 && m == 0)
2068
315
    {
2069
315
      OUTS (outf, dregs (reg));
2070
315
      OUTS (outf, " = [");
2071
315
      OUTS (outf, iregs (i));
2072
315
      OUTS (outf, "++]");
2073
315
    }
2074
13.4k
  else if (aop == 0 && W == 0 && m == 1)
2075
135
    {
2076
135
      OUTS (outf, dregs_lo (reg));
2077
135
      OUTS (outf, " = W[");
2078
135
      OUTS (outf, iregs (i));
2079
135
      OUTS (outf, "++]");
2080
135
    }
2081
13.3k
  else if (aop == 0 && W == 0 && m == 2)
2082
207
    {
2083
207
      OUTS (outf, dregs_hi (reg));
2084
207
      OUTS (outf, " = W[");
2085
207
      OUTS (outf, iregs (i));
2086
207
      OUTS (outf, "++]");
2087
207
    }
2088
13.1k
  else if (aop == 1 && W == 0 && m == 0)
2089
925
    {
2090
925
      OUTS (outf, dregs (reg));
2091
925
      OUTS (outf, " = [");
2092
925
      OUTS (outf, iregs (i));
2093
925
      OUTS (outf, "--]");
2094
925
    }
2095
12.2k
  else if (aop == 1 && W == 0 && m == 1)
2096
157
    {
2097
157
      OUTS (outf, dregs_lo (reg));
2098
157
      OUTS (outf, " = W[");
2099
157
      OUTS (outf, iregs (i));
2100
157
      OUTS (outf, "--]");
2101
157
    }
2102
12.0k
  else if (aop == 1 && W == 0 && m == 2)
2103
53
    {
2104
53
      OUTS (outf, dregs_hi (reg));
2105
53
      OUTS (outf, " = W[");
2106
53
      OUTS (outf, iregs (i));
2107
53
      OUTS (outf, "--]");
2108
53
    }
2109
12.0k
  else if (aop == 2 && W == 0 && m == 0)
2110
957
    {
2111
957
      OUTS (outf, dregs (reg));
2112
957
      OUTS (outf, " = [");
2113
957
      OUTS (outf, iregs (i));
2114
957
      OUTS (outf, "]");
2115
957
    }
2116
11.0k
  else if (aop == 2 && W == 0 && m == 1)
2117
409
    {
2118
409
      OUTS (outf, dregs_lo (reg));
2119
409
      OUTS (outf, " = W[");
2120
409
      OUTS (outf, iregs (i));
2121
409
      OUTS (outf, "]");
2122
409
    }
2123
10.6k
  else if (aop == 2 && W == 0 && m == 2)
2124
486
    {
2125
486
      OUTS (outf, dregs_hi (reg));
2126
486
      OUTS (outf, " = W[");
2127
486
      OUTS (outf, iregs (i));
2128
486
      OUTS (outf, "]");
2129
486
    }
2130
10.1k
  else if (aop == 0 && W == 1 && m == 0)
2131
537
    {
2132
537
      OUTS (outf, "[");
2133
537
      OUTS (outf, iregs (i));
2134
537
      OUTS (outf, "++] = ");
2135
537
      OUTS (outf, dregs (reg));
2136
537
    }
2137
9.61k
  else if (aop == 0 && W == 1 && m == 1)
2138
156
    {
2139
156
      OUTS (outf, "W[");
2140
156
      OUTS (outf, iregs (i));
2141
156
      OUTS (outf, "++] = ");
2142
156
      OUTS (outf, dregs_lo (reg));
2143
156
    }
2144
9.45k
  else if (aop == 0 && W == 1 && m == 2)
2145
319
    {
2146
319
      OUTS (outf, "W[");
2147
319
      OUTS (outf, iregs (i));
2148
319
      OUTS (outf, "++] = ");
2149
319
      OUTS (outf, dregs_hi (reg));
2150
319
    }
2151
9.13k
  else if (aop == 1 && W == 1 && m == 0)
2152
1.32k
    {
2153
1.32k
      OUTS (outf, "[");
2154
1.32k
      OUTS (outf, iregs (i));
2155
1.32k
      OUTS (outf, "--] = ");
2156
1.32k
      OUTS (outf, dregs (reg));
2157
1.32k
    }
2158
7.81k
  else if (aop == 1 && W == 1 && m == 1)
2159
377
    {
2160
377
      OUTS (outf, "W[");
2161
377
      OUTS (outf, iregs (i));
2162
377
      OUTS (outf, "--] = ");
2163
377
      OUTS (outf, dregs_lo (reg));
2164
377
    }
2165
7.43k
  else if (aop == 1 && W == 1 && m == 2)
2166
484
    {
2167
484
      OUTS (outf, "W[");
2168
484
      OUTS (outf, iregs (i));
2169
484
      OUTS (outf, "--] = ");
2170
484
      OUTS (outf, dregs_hi (reg));
2171
484
    }
2172
6.95k
  else if (aop == 2 && W == 1 && m == 0)
2173
647
    {
2174
647
      OUTS (outf, "[");
2175
647
      OUTS (outf, iregs (i));
2176
647
      OUTS (outf, "] = ");
2177
647
      OUTS (outf, dregs (reg));
2178
647
    }
2179
6.30k
  else if (aop == 2 && W == 1 && m == 1)
2180
192
    {
2181
192
      OUTS (outf, "W[");
2182
192
      OUTS (outf, iregs (i));
2183
192
      OUTS (outf, "] = ");
2184
192
      OUTS (outf, dregs_lo (reg));
2185
192
    }
2186
6.11k
  else if (aop == 2 && W == 1 && m == 2)
2187
99
    {
2188
99
      OUTS (outf, "W[");
2189
99
      OUTS (outf, iregs (i));
2190
99
      OUTS (outf, "] = ");
2191
99
      OUTS (outf, dregs_hi (reg));
2192
99
    }
2193
6.01k
  else if (aop == 3 && W == 0)
2194
1.46k
    {
2195
1.46k
      OUTS (outf, dregs (reg));
2196
1.46k
      OUTS (outf, " = [");
2197
1.46k
      OUTS (outf, iregs (i));
2198
1.46k
      OUTS (outf, " ++ ");
2199
1.46k
      OUTS (outf, mregs (m));
2200
1.46k
      OUTS (outf, "]");
2201
1.46k
    }
2202
4.54k
  else if (aop == 3 && W == 1)
2203
3.60k
    {
2204
3.60k
      OUTS (outf, "[");
2205
3.60k
      OUTS (outf, iregs (i));
2206
3.60k
      OUTS (outf, " ++ ");
2207
3.60k
      OUTS (outf, mregs (m));
2208
3.60k
      OUTS (outf, "] = ");
2209
3.60k
      OUTS (outf, dregs (reg));
2210
3.60k
    }
2211
946
  else
2212
946
    return 0;
2213
2214
12.8k
  return 2;
2215
13.7k
}
2216
2217
static int
2218
decode_LDST_0 (TIword iw0, disassemble_info *outf)
2219
45.1k
{
2220
  /* LDST
2221
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2222
     | 1 | 0 | 0 | 1 |.sz....|.W.|.aop...|.Z.|.ptr.......|.reg.......|
2223
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
2224
45.1k
  int Z   = ((iw0 >> LDST_Z_bits) & LDST_Z_mask);
2225
45.1k
  int W   = ((iw0 >> LDST_W_bits) & LDST_W_mask);
2226
45.1k
  int sz  = ((iw0 >> LDST_sz_bits) & LDST_sz_mask);
2227
45.1k
  int aop = ((iw0 >> LDST_aop_bits) & LDST_aop_mask);
2228
45.1k
  int reg = ((iw0 >> LDST_reg_bits) & LDST_reg_mask);
2229
45.1k
  int ptr = ((iw0 >> LDST_ptr_bits) & LDST_ptr_mask);
2230
2231
45.1k
  if (aop == 0 && sz == 0 && Z == 0 && W == 0)
2232
1.21k
    {
2233
1.21k
      OUTS (outf, dregs (reg));
2234
1.21k
      OUTS (outf, " = [");
2235
1.21k
      OUTS (outf, pregs (ptr));
2236
1.21k
      OUTS (outf, "++]");
2237
1.21k
    }
2238
43.9k
  else if (aop == 0 && sz == 0 && Z == 1 && W == 0 && reg != ptr)
2239
714
    {
2240
714
      OUTS (outf, pregs (reg));
2241
714
      OUTS (outf, " = [");
2242
714
      OUTS (outf, pregs (ptr));
2243
714
      OUTS (outf, "++]");
2244
714
    }
2245
43.2k
  else if (aop == 0 && sz == 1 && Z == 0 && W == 0)
2246
372
    {
2247
372
      OUTS (outf, dregs (reg));
2248
372
      OUTS (outf, " = W[");
2249
372
      OUTS (outf, pregs (ptr));
2250
372
      OUTS (outf, "++] (Z)");
2251
372
    }
2252
42.8k
  else if (aop == 0 && sz == 1 && Z == 1 && W == 0)
2253
191
    {
2254
191
      OUTS (outf, dregs (reg));
2255
191
      OUTS (outf, " = W[");
2256
191
      OUTS (outf, pregs (ptr));
2257
191
      OUTS (outf, "++] (X)");
2258
191
    }
2259
42.6k
  else if (aop == 0 && sz == 2 && Z == 0 && W == 0)
2260
552
    {
2261
552
      OUTS (outf, dregs (reg));
2262
552
      OUTS (outf, " = B[");
2263
552
      OUTS (outf, pregs (ptr));
2264
552
      OUTS (outf, "++] (Z)");
2265
552
    }
2266
42.0k
  else if (aop == 0 && sz == 2 && Z == 1 && W == 0)
2267
749
    {
2268
749
      OUTS (outf, dregs (reg));
2269
749
      OUTS (outf, " = B[");
2270
749
      OUTS (outf, pregs (ptr));
2271
749
      OUTS (outf, "++] (X)");
2272
749
    }
2273
41.3k
  else if (aop == 1 && sz == 0 && Z == 0 && W == 0)
2274
1.50k
    {
2275
1.50k
      OUTS (outf, dregs (reg));
2276
1.50k
      OUTS (outf, " = [");
2277
1.50k
      OUTS (outf, pregs (ptr));
2278
1.50k
      OUTS (outf, "--]");
2279
1.50k
    }
2280
39.8k
  else if (aop == 1 && sz == 0 && Z == 1 && W == 0 && reg != ptr)
2281
584
    {
2282
584
      OUTS (outf, pregs (reg));
2283
584
      OUTS (outf, " = [");
2284
584
      OUTS (outf, pregs (ptr));
2285
584
      OUTS (outf, "--]");
2286
584
    }
2287
39.2k
  else if (aop == 1 && sz == 1 && Z == 0 && W == 0)
2288
1.29k
    {
2289
1.29k
      OUTS (outf, dregs (reg));
2290
1.29k
      OUTS (outf, " = W[");
2291
1.29k
      OUTS (outf, pregs (ptr));
2292
1.29k
      OUTS (outf, "--] (Z)");
2293
1.29k
    }
2294
37.9k
  else if (aop == 1 && sz == 1 && Z == 1 && W == 0)
2295
467
    {
2296
467
      OUTS (outf, dregs (reg));
2297
467
      OUTS (outf, " = W[");
2298
467
      OUTS (outf, pregs (ptr));
2299
467
      OUTS (outf, "--] (X)");
2300
467
    }
2301
37.4k
  else if (aop == 1 && sz == 2 && Z == 0 && W == 0)
2302
1.57k
    {
2303
1.57k
      OUTS (outf, dregs (reg));
2304
1.57k
      OUTS (outf, " = B[");
2305
1.57k
      OUTS (outf, pregs (ptr));
2306
1.57k
      OUTS (outf, "--] (Z)");
2307
1.57k
    }
2308
35.9k
  else if (aop == 1 && sz == 2 && Z == 1 && W == 0)
2309
312
    {
2310
312
      OUTS (outf, dregs (reg));
2311
312
      OUTS (outf, " = B[");
2312
312
      OUTS (outf, pregs (ptr));
2313
312
      OUTS (outf, "--] (X)");
2314
312
    }
2315
35.6k
  else if (aop == 2 && sz == 0 && Z == 0 && W == 0)
2316
419
    {
2317
419
      OUTS (outf, dregs (reg));
2318
419
      OUTS (outf, " = [");
2319
419
      OUTS (outf, pregs (ptr));
2320
419
      OUTS (outf, "]");
2321
419
    }
2322
35.1k
  else if (aop == 2 && sz == 0 && Z == 1 && W == 0)
2323
593
    {
2324
593
      OUTS (outf, pregs (reg));
2325
593
      OUTS (outf, " = [");
2326
593
      OUTS (outf, pregs (ptr));
2327
593
      OUTS (outf, "]");
2328
593
    }
2329
34.5k
  else if (aop == 2 && sz == 1 && Z == 0 && W == 0)
2330
1.30k
    {
2331
1.30k
      OUTS (outf, dregs (reg));
2332
1.30k
      OUTS (outf, " = W[");
2333
1.30k
      OUTS (outf, pregs (ptr));
2334
1.30k
      OUTS (outf, "] (Z)");
2335
1.30k
    }
2336
33.2k
  else if (aop == 2 && sz == 1 && Z == 1 && W == 0)
2337
545
    {
2338
545
      OUTS (outf, dregs (reg));
2339
545
      OUTS (outf, " = W[");
2340
545
      OUTS (outf, pregs (ptr));
2341
545
      OUTS (outf, "] (X)");
2342
545
    }
2343
32.7k
  else if (aop == 2 && sz == 2 && Z == 0 && W == 0)
2344
658
    {
2345
658
      OUTS (outf, dregs (reg));
2346
658
      OUTS (outf, " = B[");
2347
658
      OUTS (outf, pregs (ptr));
2348
658
      OUTS (outf, "] (Z)");
2349
658
    }
2350
32.0k
  else if (aop == 2 && sz == 2 && Z == 1 && W == 0)
2351
380
    {
2352
380
      OUTS (outf, dregs (reg));
2353
380
      OUTS (outf, " = B[");
2354
380
      OUTS (outf, pregs (ptr));
2355
380
      OUTS (outf, "] (X)");
2356
380
    }
2357
31.7k
  else if (aop == 0 && sz == 0 && Z == 0 && W == 1)
2358
529
    {
2359
529
      OUTS (outf, "[");
2360
529
      OUTS (outf, pregs (ptr));
2361
529
      OUTS (outf, "++] = ");
2362
529
      OUTS (outf, dregs (reg));
2363
529
    }
2364
31.1k
  else if (aop == 0 && sz == 0 && Z == 1 && W == 1)
2365
242
    {
2366
242
      OUTS (outf, "[");
2367
242
      OUTS (outf, pregs (ptr));
2368
242
      OUTS (outf, "++] = ");
2369
242
      OUTS (outf, pregs (reg));
2370
242
    }
2371
30.9k
  else if (aop == 0 && sz == 1 && Z == 0 && W == 1)
2372
377
    {
2373
377
      OUTS (outf, "W[");
2374
377
      OUTS (outf, pregs (ptr));
2375
377
      OUTS (outf, "++] = ");
2376
377
      OUTS (outf, dregs (reg));
2377
377
    }
2378
30.5k
  else if (aop == 0 && sz == 2 && Z == 0 && W == 1)
2379
2.26k
    {
2380
2.26k
      OUTS (outf, "B[");
2381
2.26k
      OUTS (outf, pregs (ptr));
2382
2.26k
      OUTS (outf, "++] = ");
2383
2.26k
      OUTS (outf, dregs (reg));
2384
2.26k
    }
2385
28.2k
  else if (aop == 1 && sz == 0 && Z == 0 && W == 1)
2386
1.64k
    {
2387
1.64k
      OUTS (outf, "[");
2388
1.64k
      OUTS (outf, pregs (ptr));
2389
1.64k
      OUTS (outf, "--] = ");
2390
1.64k
      OUTS (outf, dregs (reg));
2391
1.64k
    }
2392
26.6k
  else if (aop == 1 && sz == 0 && Z == 1 && W == 1)
2393
586
    {
2394
586
      OUTS (outf, "[");
2395
586
      OUTS (outf, pregs (ptr));
2396
586
      OUTS (outf, "--] = ");
2397
586
      OUTS (outf, pregs (reg));
2398
586
    }
2399
26.0k
  else if (aop == 1 && sz == 1 && Z == 0 && W == 1)
2400
917
    {
2401
917
      OUTS (outf, "W[");
2402
917
      OUTS (outf, pregs (ptr));
2403
917
      OUTS (outf, "--] = ");
2404
917
      OUTS (outf, dregs (reg));
2405
917
    }
2406
25.1k
  else if (aop == 1 && sz == 2 && Z == 0 && W == 1)
2407
1.95k
    {
2408
1.95k
      OUTS (outf, "B[");
2409
1.95k
      OUTS (outf, pregs (ptr));
2410
1.95k
      OUTS (outf, "--] = ");
2411
1.95k
      OUTS (outf, dregs (reg));
2412
1.95k
    }
2413
23.2k
  else if (aop == 2 && sz == 0 && Z == 0 && W == 1)
2414
854
    {
2415
854
      OUTS (outf, "[");
2416
854
      OUTS (outf, pregs (ptr));
2417
854
      OUTS (outf, "] = ");
2418
854
      OUTS (outf, dregs (reg));
2419
854
    }
2420
22.3k
  else if (aop == 2 && sz == 0 && Z == 1 && W == 1)
2421
308
    {
2422
308
      OUTS (outf, "[");
2423
308
      OUTS (outf, pregs (ptr));
2424
308
      OUTS (outf, "] = ");
2425
308
      OUTS (outf, pregs (reg));
2426
308
    }
2427
22.0k
  else if (aop == 2 && sz == 1 && Z == 0 && W == 1)
2428
691
    {
2429
691
      OUTS (outf, "W[");
2430
691
      OUTS (outf, pregs (ptr));
2431
691
      OUTS (outf, "] = ");
2432
691
      OUTS (outf, dregs (reg));
2433
691
    }
2434
21.3k
  else if (aop == 2 && sz == 2 && Z == 0 && W == 1)
2435
1.16k
    {
2436
1.16k
      OUTS (outf, "B[");
2437
1.16k
      OUTS (outf, pregs (ptr));
2438
1.16k
      OUTS (outf, "] = ");
2439
1.16k
      OUTS (outf, dregs (reg));
2440
1.16k
    }
2441
20.1k
  else
2442
20.1k
    return 0;
2443
2444
24.9k
  return 2;
2445
45.1k
}
2446
2447
static int
2448
decode_LDSTiiFP_0 (TIword iw0, disassemble_info *outf)
2449
13.8k
{
2450
  /* LDSTiiFP
2451
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2452
     | 1 | 0 | 1 | 1 | 1 | 0 |.W.|.offset............|.reg...........|
2453
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
2454
13.8k
  int reg = ((iw0 >> LDSTiiFP_reg_bits) & LDSTiiFP_reg_mask);
2455
13.8k
  int offset = ((iw0 >> LDSTiiFP_offset_bits) & LDSTiiFP_offset_mask);
2456
13.8k
  int W = ((iw0 >> LDSTiiFP_W_bits) & LDSTiiFP_W_mask);
2457
2458
13.8k
  if (W == 0)
2459
7.76k
    {
2460
7.76k
      OUTS (outf, dpregs (reg));
2461
7.76k
      OUTS (outf, " = [FP ");
2462
7.76k
      OUTS (outf, negimm5s4 (offset));
2463
7.76k
      OUTS (outf, "]");
2464
7.76k
    }
2465
6.12k
  else if (W == 1)
2466
6.12k
    {
2467
6.12k
      OUTS (outf, "[FP ");
2468
6.12k
      OUTS (outf, negimm5s4 (offset));
2469
6.12k
      OUTS (outf, "] = ");
2470
6.12k
      OUTS (outf, dpregs (reg));
2471
6.12k
    }
2472
0
  else
2473
0
    return 0;
2474
2475
13.8k
  return 2;
2476
13.8k
}
2477
2478
static int
2479
decode_LDSTii_0 (TIword iw0, disassemble_info *outf)
2480
87.3k
{
2481
  /* LDSTii
2482
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2483
     | 1 | 0 | 1 |.W.|.op....|.offset........|.ptr.......|.reg.......|
2484
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
2485
87.3k
  int reg = ((iw0 >> LDSTii_reg_bit) & LDSTii_reg_mask);
2486
87.3k
  int ptr = ((iw0 >> LDSTii_ptr_bit) & LDSTii_ptr_mask);
2487
87.3k
  int offset = ((iw0 >> LDSTii_offset_bit) & LDSTii_offset_mask);
2488
87.3k
  int op = ((iw0 >> LDSTii_op_bit) & LDSTii_op_mask);
2489
87.3k
  int W = ((iw0 >> LDSTii_W_bit) & LDSTii_W_mask);
2490
2491
87.3k
  if (W == 0 && op == 0)
2492
18.0k
    {
2493
18.0k
      OUTS (outf, dregs (reg));
2494
18.0k
      OUTS (outf, " = [");
2495
18.0k
      OUTS (outf, pregs (ptr));
2496
18.0k
      OUTS (outf, " + ");
2497
18.0k
      OUTS (outf, uimm4s4 (offset));
2498
18.0k
      OUTS (outf, "]");
2499
18.0k
    }
2500
69.2k
  else if (W == 0 && op == 1)
2501
16.4k
    {
2502
16.4k
      OUTS (outf, dregs (reg));
2503
16.4k
      OUTS (outf, " = W[");
2504
16.4k
      OUTS (outf, pregs (ptr));
2505
16.4k
      OUTS (outf, " + ");
2506
16.4k
      OUTS (outf, uimm4s2 (offset));
2507
16.4k
      OUTS (outf, "] (Z)");
2508
16.4k
    }
2509
52.8k
  else if (W == 0 && op == 2)
2510
9.25k
    {
2511
9.25k
      OUTS (outf, dregs (reg));
2512
9.25k
      OUTS (outf, " = W[");
2513
9.25k
      OUTS (outf, pregs (ptr));
2514
9.25k
      OUTS (outf, " + ");
2515
9.25k
      OUTS (outf, uimm4s2 (offset));
2516
9.25k
      OUTS (outf, "] (X)");
2517
9.25k
    }
2518
43.5k
  else if (W == 0 && op == 3)
2519
10.0k
    {
2520
10.0k
      OUTS (outf, pregs (reg));
2521
10.0k
      OUTS (outf, " = [");
2522
10.0k
      OUTS (outf, pregs (ptr));
2523
10.0k
      OUTS (outf, " + ");
2524
10.0k
      OUTS (outf, uimm4s4 (offset));
2525
10.0k
      OUTS (outf, "]");
2526
10.0k
    }
2527
33.4k
  else if (W == 1 && op == 0)
2528
8.59k
    {
2529
8.59k
      OUTS (outf, "[");
2530
8.59k
      OUTS (outf, pregs (ptr));
2531
8.59k
      OUTS (outf, " + ");
2532
8.59k
      OUTS (outf, uimm4s4 (offset));
2533
8.59k
      OUTS (outf, "] = ");
2534
8.59k
      OUTS (outf, dregs (reg));
2535
8.59k
    }
2536
24.8k
  else if (W == 1 && op == 1)
2537
11.8k
    {
2538
11.8k
      OUTS (outf, "W[");
2539
11.8k
      OUTS (outf, pregs (ptr));
2540
11.8k
      OUTS (outf, " + ");
2541
11.8k
      OUTS (outf, uimm4s2 (offset));
2542
11.8k
      OUTS (outf, "] = ");
2543
11.8k
      OUTS (outf, dregs (reg));
2544
11.8k
    }
2545
13.0k
  else if (W == 1 && op == 3)
2546
13.0k
    {
2547
13.0k
      OUTS (outf, "[");
2548
13.0k
      OUTS (outf, pregs (ptr));
2549
13.0k
      OUTS (outf, " + ");
2550
13.0k
      OUTS (outf, uimm4s4 (offset));
2551
13.0k
      OUTS (outf, "] = ");
2552
13.0k
      OUTS (outf, pregs (reg));
2553
13.0k
    }
2554
0
  else
2555
0
    return 0;
2556
2557
87.3k
  return 2;
2558
87.3k
}
2559
2560
static int
2561
decode_LoopSetup_0 (TIword iw0, TIword iw1, bfd_vma pc, disassemble_info *outf)
2562
3.27k
{
2563
3.27k
  struct private *priv = outf->private_data;
2564
  /* LoopSetup
2565
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2566
     | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 |.rop...|.c.|.soffset.......|
2567
     |.reg...........| - | - |.eoffset...............................|
2568
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
2569
3.27k
  int c   = ((iw0 >> (LoopSetup_c_bits - 16)) & LoopSetup_c_mask);
2570
3.27k
  int reg = ((iw1 >> LoopSetup_reg_bits) & LoopSetup_reg_mask);
2571
3.27k
  int rop = ((iw0 >> (LoopSetup_rop_bits - 16)) & LoopSetup_rop_mask);
2572
3.27k
  int soffset = ((iw0 >> (LoopSetup_soffset_bits - 16)) & LoopSetup_soffset_mask);
2573
3.27k
  int eoffset = ((iw1 >> LoopSetup_eoffset_bits) & LoopSetup_eoffset_mask);
2574
2575
3.27k
  if (priv->parallel)
2576
60
    return 0;
2577
2578
3.21k
  if (reg > 7)
2579
2.02k
    return 0;
2580
2581
1.19k
  if (rop == 0)
2582
2
    {
2583
2
      OUTS (outf, "LSETUP");
2584
2
      OUTS (outf, "(0x");
2585
2
      OUTS (outf, pcrel4 (soffset));
2586
2
      OUTS (outf, ", 0x");
2587
2
      OUTS (outf, lppcrel10 (eoffset));
2588
2
      OUTS (outf, ") ");
2589
2
      OUTS (outf, counters (c));
2590
2
    }
2591
1.18k
  else if (rop == 1)
2592
52
    {
2593
52
      OUTS (outf, "LSETUP");
2594
52
      OUTS (outf, "(0x");
2595
52
      OUTS (outf, pcrel4 (soffset));
2596
52
      OUTS (outf, ", 0x");
2597
52
      OUTS (outf, lppcrel10 (eoffset));
2598
52
      OUTS (outf, ") ");
2599
52
      OUTS (outf, counters (c));
2600
52
      OUTS (outf, " = ");
2601
52
      OUTS (outf, pregs (reg));
2602
52
    }
2603
1.13k
  else if (rop == 3)
2604
1.09k
    {
2605
1.09k
      OUTS (outf, "LSETUP");
2606
1.09k
      OUTS (outf, "(0x");
2607
1.09k
      OUTS (outf, pcrel4 (soffset));
2608
1.09k
      OUTS (outf, ", 0x");
2609
1.09k
      OUTS (outf, lppcrel10 (eoffset));
2610
1.09k
      OUTS (outf, ") ");
2611
1.09k
      OUTS (outf, counters (c));
2612
1.09k
      OUTS (outf, " = ");
2613
1.09k
      OUTS (outf, pregs (reg));
2614
1.09k
      OUTS (outf, " >> 0x1");
2615
1.09k
    }
2616
42
  else
2617
42
    return 0;
2618
2619
1.14k
  return 4;
2620
1.19k
}
2621
2622
static int
2623
decode_LDIMMhalf_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2624
7.84k
{
2625
7.84k
  struct private *priv = outf->private_data;
2626
  /* LDIMMhalf
2627
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2628
     | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 |.Z.|.H.|.S.|.grp...|.reg.......|
2629
     |.hword.........................................................|
2630
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
2631
7.84k
  int H = ((iw0 >> (LDIMMhalf_H_bits - 16)) & LDIMMhalf_H_mask);
2632
7.84k
  int Z = ((iw0 >> (LDIMMhalf_Z_bits - 16)) & LDIMMhalf_Z_mask);
2633
7.84k
  int S = ((iw0 >> (LDIMMhalf_S_bits - 16)) & LDIMMhalf_S_mask);
2634
7.84k
  int reg = ((iw0 >> (LDIMMhalf_reg_bits - 16)) & LDIMMhalf_reg_mask);
2635
7.84k
  int grp = ((iw0 >> (LDIMMhalf_grp_bits - 16)) & LDIMMhalf_grp_mask);
2636
7.84k
  int hword = ((iw1 >> LDIMMhalf_hword_bits) & LDIMMhalf_hword_mask);
2637
2638
7.84k
  bu32 *pval = get_allreg (grp, reg);
2639
2640
7.84k
  if (priv->parallel)
2641
290
    return 0;
2642
2643
  /* Since we don't have 32-bit immediate loads, we allow the disassembler
2644
     to combine them, so it prints out the right values.
2645
     Here we keep track of the registers.  */
2646
7.55k
  if (H == 0 && S == 1 && Z == 0)
2647
444
    {
2648
      /* regs = imm16 (x) */
2649
444
      *pval = imm16_val (hword);
2650
444
      if (hword & 0x8000)
2651
319
  *pval |= 0xFFFF0000;
2652
125
      else
2653
125
  *pval &= 0xFFFF;
2654
444
    }
2655
7.11k
  else if (H == 0 && S == 0 && Z == 1)
2656
398
    {
2657
      /* regs = luimm16 (Z) */
2658
398
      *pval = luimm16_val (hword);
2659
398
      *pval &= 0xFFFF;
2660
398
    }
2661
6.71k
  else if (H == 0 && S == 0 && Z == 0)
2662
1.30k
    {
2663
      /* regs_lo = luimm16 */
2664
1.30k
      *pval &= 0xFFFF0000;
2665
1.30k
      *pval |= luimm16_val (hword);
2666
1.30k
    }
2667
5.41k
  else if (H == 1 && S == 0 && Z == 0)
2668
549
    {
2669
      /* regs_hi = huimm16 */
2670
549
      *pval &= 0xFFFF;
2671
549
      *pval |= luimm16_val (hword) << 16;
2672
549
    }
2673
2674
  /* Here we do the disassembly */
2675
7.55k
  if (grp == 0 && H == 0 && S == 0 && Z == 0)
2676
1.05k
    {
2677
1.05k
      OUTS (outf, dregs_lo (reg));
2678
1.05k
      OUTS (outf, " = ");
2679
1.05k
      OUTS (outf, uimm16 (hword));
2680
1.05k
    }
2681
6.49k
  else if (grp == 0 && H == 1 && S == 0 && Z == 0)
2682
272
    {
2683
272
      OUTS (outf, dregs_hi (reg));
2684
272
      OUTS (outf, " = ");
2685
272
      OUTS (outf, uimm16 (hword));
2686
272
    }
2687
6.22k
  else if (grp == 0 && H == 0 && S == 1 && Z == 0)
2688
111
    {
2689
111
      OUTS (outf, dregs (reg));
2690
111
      OUTS (outf, " = ");
2691
111
      OUTS (outf, imm16 (hword));
2692
111
      OUTS (outf, " (X)");
2693
111
    }
2694
6.11k
  else if (H == 0 && S == 1 && Z == 0)
2695
333
    {
2696
333
      OUTS (outf, regs (reg, grp));
2697
333
      OUTS (outf, " = ");
2698
333
      OUTS (outf, imm16 (hword));
2699
333
      OUTS (outf, " (X)");
2700
333
    }
2701
5.78k
  else if (H == 0 && S == 0 && Z == 1)
2702
398
    {
2703
398
      OUTS (outf, regs (reg, grp));
2704
398
      OUTS (outf, " = ");
2705
398
      OUTS (outf, uimm16 (hword));
2706
398
      OUTS (outf, " (Z)");
2707
398
    }
2708
5.38k
  else if (H == 0 && S == 0 && Z == 0)
2709
243
    {
2710
243
      OUTS (outf, regs_lo (reg, grp));
2711
243
      OUTS (outf, " = ");
2712
243
      OUTS (outf, uimm16 (hword));
2713
243
    }
2714
5.13k
  else if (H == 1 && S == 0 && Z == 0)
2715
277
    {
2716
277
      OUTS (outf, regs_hi (reg, grp));
2717
277
      OUTS (outf, " = ");
2718
277
      OUTS (outf, uimm16 (hword));
2719
277
    }
2720
4.86k
  else
2721
4.86k
    return 0;
2722
2723
  /* And we print out the 32-bit value if it is a pointer.  */
2724
2.69k
  if (S == 0 && Z == 0)
2725
1.85k
    {
2726
1.85k
      OUTS (outf, ";\t\t/* (");
2727
1.85k
      OUTS (outf, imm16d (hword));
2728
1.85k
      OUTS (outf, ")\t");
2729
2730
      /* If it is an MMR, don't print the symbol.  */
2731
1.85k
      if (*pval < 0xFFC00000 && grp == 1)
2732
79
  {
2733
79
    OUTS (outf, regs (reg, grp));
2734
79
    OUTS (outf, "=0x");
2735
79
    OUTS (outf, huimm32e (*pval));
2736
79
  }
2737
1.77k
      else
2738
1.77k
  {
2739
1.77k
    OUTS (outf, regs (reg, grp));
2740
1.77k
    OUTS (outf, "=0x");
2741
1.77k
    OUTS (outf, huimm32e (*pval));
2742
1.77k
    OUTS (outf, "(");
2743
1.77k
    OUTS (outf, imm32 (*pval));
2744
1.77k
    OUTS (outf, ")");
2745
1.77k
  }
2746
2747
1.85k
      OUTS (outf, " */");
2748
1.85k
      priv->comment = true;
2749
1.85k
    }
2750
2.69k
  if (S == 1 || Z == 1)
2751
842
    {
2752
842
      OUTS (outf, ";\t\t/*\t\t");
2753
842
      OUTS (outf, regs (reg, grp));
2754
842
      OUTS (outf, "=0x");
2755
842
      OUTS (outf, huimm32e (*pval));
2756
842
      OUTS (outf, "(");
2757
842
      OUTS (outf, imm32 (*pval));
2758
842
      OUTS (outf, ") */");
2759
842
      priv->comment = true;
2760
842
    }
2761
2.69k
  return 4;
2762
7.55k
}
2763
2764
static int
2765
decode_CALLa_0 (TIword iw0, TIword iw1, bfd_vma pc, disassemble_info *outf)
2766
6.34k
{
2767
6.34k
  struct private *priv = outf->private_data;
2768
  /* CALLa
2769
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2770
     | 1 | 1 | 1 | 0 | 0 | 0 | 1 |.S.|.msw...........................|
2771
     |.lsw...........................................................|
2772
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
2773
6.34k
  int S   = ((iw0 >> (CALLa_S_bits - 16)) & CALLa_S_mask);
2774
6.34k
  int lsw = ((iw1 >> 0) & 0xffff);
2775
6.34k
  int msw = ((iw0 >> 0) & 0xff);
2776
2777
6.34k
  if (priv->parallel)
2778
203
    return 0;
2779
2780
6.14k
  if (S == 1)
2781
2.33k
    OUTS (outf, "CALL 0x");
2782
3.81k
  else if (S == 0)
2783
3.81k
    OUTS (outf, "JUMP.L 0x");
2784
0
  else
2785
0
    return 0;
2786
2787
6.14k
  OUTS (outf, pcrel24 (((msw) << 16) | (lsw)));
2788
6.14k
  return 4;
2789
6.14k
}
2790
2791
static int
2792
decode_LDSTidxI_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2793
16.6k
{
2794
  /* LDSTidxI
2795
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2796
     | 1 | 1 | 1 | 0 | 0 | 1 |.W.|.Z.|.sz....|.ptr.......|.reg.......|
2797
     |.offset........................................................|
2798
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
2799
16.6k
  int Z = ((iw0 >> (LDSTidxI_Z_bits - 16)) & LDSTidxI_Z_mask);
2800
16.6k
  int W = ((iw0 >> (LDSTidxI_W_bits - 16)) & LDSTidxI_W_mask);
2801
16.6k
  int sz = ((iw0 >> (LDSTidxI_sz_bits - 16)) & LDSTidxI_sz_mask);
2802
16.6k
  int reg = ((iw0 >> (LDSTidxI_reg_bits - 16)) & LDSTidxI_reg_mask);
2803
16.6k
  int ptr = ((iw0 >> (LDSTidxI_ptr_bits - 16)) & LDSTidxI_ptr_mask);
2804
16.6k
  int offset = ((iw1 >> LDSTidxI_offset_bits) & LDSTidxI_offset_mask);
2805
2806
16.6k
  if (W == 0 && sz == 0 && Z == 0)
2807
1.23k
    {
2808
1.23k
      OUTS (outf, dregs (reg));
2809
1.23k
      OUTS (outf, " = [");
2810
1.23k
      OUTS (outf, pregs (ptr));
2811
1.23k
      OUTS (outf, " + ");
2812
1.23k
      OUTS (outf, imm16s4 (offset));
2813
1.23k
      OUTS (outf, "]");
2814
1.23k
    }
2815
15.3k
  else if (W == 0 && sz == 0 && Z == 1)
2816
1.26k
    {
2817
1.26k
      OUTS (outf, pregs (reg));
2818
1.26k
      OUTS (outf, " = [");
2819
1.26k
      OUTS (outf, pregs (ptr));
2820
1.26k
      OUTS (outf, " + ");
2821
1.26k
      OUTS (outf, imm16s4 (offset));
2822
1.26k
      OUTS (outf, "]");
2823
1.26k
    }
2824
14.1k
  else if (W == 0 && sz == 1 && Z == 0)
2825
1.68k
    {
2826
1.68k
      OUTS (outf, dregs (reg));
2827
1.68k
      OUTS (outf, " = W[");
2828
1.68k
      OUTS (outf, pregs (ptr));
2829
1.68k
      OUTS (outf, " + ");
2830
1.68k
      OUTS (outf, imm16s2 (offset));
2831
1.68k
      OUTS (outf, "] (Z)");
2832
1.68k
    }
2833
12.4k
  else if (W == 0 && sz == 1 && Z == 1)
2834
661
    {
2835
661
      OUTS (outf, dregs (reg));
2836
661
      OUTS (outf, " = W[");
2837
661
      OUTS (outf, pregs (ptr));
2838
661
      OUTS (outf, " + ");
2839
661
      OUTS (outf, imm16s2 (offset));
2840
661
      OUTS (outf, "] (X)");
2841
661
    }
2842
11.7k
  else if (W == 0 && sz == 2 && Z == 0)
2843
1.41k
    {
2844
1.41k
      OUTS (outf, dregs (reg));
2845
1.41k
      OUTS (outf, " = B[");
2846
1.41k
      OUTS (outf, pregs (ptr));
2847
1.41k
      OUTS (outf, " + ");
2848
1.41k
      OUTS (outf, imm16 (offset));
2849
1.41k
      OUTS (outf, "] (Z)");
2850
1.41k
    }
2851
10.3k
  else if (W == 0 && sz == 2 && Z == 1)
2852
670
    {
2853
670
      OUTS (outf, dregs (reg));
2854
670
      OUTS (outf, " = B[");
2855
670
      OUTS (outf, pregs (ptr));
2856
670
      OUTS (outf, " + ");
2857
670
      OUTS (outf, imm16 (offset));
2858
670
      OUTS (outf, "] (X)");
2859
670
    }
2860
9.67k
  else if (W == 1 && sz == 0 && Z == 0)
2861
798
    {
2862
798
      OUTS (outf, "[");
2863
798
      OUTS (outf, pregs (ptr));
2864
798
      OUTS (outf, " + ");
2865
798
      OUTS (outf, imm16s4 (offset));
2866
798
      OUTS (outf, "] = ");
2867
798
      OUTS (outf, dregs (reg));
2868
798
    }
2869
8.88k
  else if (W == 1 && sz == 0 && Z == 1)
2870
441
    {
2871
441
      OUTS (outf, "[");
2872
441
      OUTS (outf, pregs (ptr));
2873
441
      OUTS (outf, " + ");
2874
441
      OUTS (outf, imm16s4 (offset));
2875
441
      OUTS (outf, "] = ");
2876
441
      OUTS (outf, pregs (reg));
2877
441
    }
2878
8.44k
  else if (W == 1 && sz == 1 && Z == 0)
2879
555
    {
2880
555
      OUTS (outf, "W[");
2881
555
      OUTS (outf, pregs (ptr));
2882
555
      OUTS (outf, " + ");
2883
555
      OUTS (outf, imm16s2 (offset));
2884
555
      OUTS (outf, "] = ");
2885
555
      OUTS (outf, dregs (reg));
2886
555
    }
2887
7.88k
  else if (W == 1 && sz == 2 && Z == 0)
2888
300
    {
2889
300
      OUTS (outf, "B[");
2890
300
      OUTS (outf, pregs (ptr));
2891
300
      OUTS (outf, " + ");
2892
300
      OUTS (outf, imm16 (offset));
2893
300
      OUTS (outf, "] = ");
2894
300
      OUTS (outf, dregs (reg));
2895
300
    }
2896
7.58k
  else
2897
7.58k
    return 0;
2898
2899
9.02k
  return 4;
2900
16.6k
}
2901
2902
static int
2903
decode_linkage_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2904
363
{
2905
363
  struct private *priv = outf->private_data;
2906
  /* linkage
2907
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2908
     | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |.R.|
2909
     |.framesize.....................................................|
2910
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
2911
363
  int R = ((iw0 >> (Linkage_R_bits - 16)) & Linkage_R_mask);
2912
363
  int framesize = ((iw1 >> Linkage_framesize_bits) & Linkage_framesize_mask);
2913
2914
363
  if (priv->parallel)
2915
37
    return 0;
2916
2917
326
  if (R == 0)
2918
278
    {
2919
278
      OUTS (outf, "LINK ");
2920
278
      OUTS (outf, uimm16s4 (framesize));
2921
278
      OUTS (outf, ";\t\t/* (");
2922
278
      OUTS (outf, uimm16s4d (framesize));
2923
278
      OUTS (outf, ") */");
2924
278
      priv->comment = true;
2925
278
    }
2926
48
  else if (R == 1)
2927
48
    OUTS (outf, "UNLINK");
2928
0
  else
2929
0
    return 0;
2930
2931
326
  return 4;
2932
326
}
2933
2934
static int
2935
decode_dsp32mac_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2936
20.4k
{
2937
  /* dsp32mac
2938
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2939
     | 1 | 1 | 0 | 0 |.M.| 0 | 0 |.mmod..........|.MM|.P.|.w1|.op1...|
2940
     |.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1..|
2941
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
2942
20.4k
  int op1  = ((iw0 >> (DSP32Mac_op1_bits - 16)) & DSP32Mac_op1_mask);
2943
20.4k
  int w1   = ((iw0 >> (DSP32Mac_w1_bits - 16)) & DSP32Mac_w1_mask);
2944
20.4k
  int P    = ((iw0 >> (DSP32Mac_p_bits - 16)) & DSP32Mac_p_mask);
2945
20.4k
  int MM   = ((iw0 >> (DSP32Mac_MM_bits - 16)) & DSP32Mac_MM_mask);
2946
20.4k
  int mmod = ((iw0 >> (DSP32Mac_mmod_bits - 16)) & DSP32Mac_mmod_mask);
2947
20.4k
  int w0   = ((iw1 >> DSP32Mac_w0_bits) & DSP32Mac_w0_mask);
2948
20.4k
  int src0 = ((iw1 >> DSP32Mac_src0_bits) & DSP32Mac_src0_mask);
2949
20.4k
  int src1 = ((iw1 >> DSP32Mac_src1_bits) & DSP32Mac_src1_mask);
2950
20.4k
  int dst  = ((iw1 >> DSP32Mac_dst_bits) & DSP32Mac_dst_mask);
2951
20.4k
  int h10  = ((iw1 >> DSP32Mac_h10_bits) & DSP32Mac_h10_mask);
2952
20.4k
  int h00  = ((iw1 >> DSP32Mac_h00_bits) & DSP32Mac_h00_mask);
2953
20.4k
  int op0  = ((iw1 >> DSP32Mac_op0_bits) & DSP32Mac_op0_mask);
2954
20.4k
  int h11  = ((iw1 >> DSP32Mac_h11_bits) & DSP32Mac_h11_mask);
2955
20.4k
  int h01  = ((iw1 >> DSP32Mac_h01_bits) & DSP32Mac_h01_mask);
2956
2957
20.4k
  if (w0 == 0 && w1 == 0 && op1 == 3 && op0 == 3)
2958
46
    return 0;
2959
2960
20.3k
  if (op1 == 3 && MM)
2961
959
    return 0;
2962
2963
19.4k
  if ((w1 || w0) && mmod == M_W32)
2964
401
    return 0;
2965
2966
19.0k
  if (((1 << mmod) & (P ? 0x131b : 0x1b5f)) == 0)
2967
7.12k
    return 0;
2968
2969
11.8k
  if (w1 == 1 || op1 != 3)
2970
9.88k
    {
2971
9.88k
      if (w1)
2972
2.50k
  OUTS (outf, P ? dregs (dst + 1) : dregs_hi (dst));
2973
2974
9.88k
      if (op1 == 3)
2975
279
  OUTS (outf, " = A1");
2976
9.60k
      else
2977
9.60k
  {
2978
9.60k
    if (w1)
2979
2.22k
      OUTS (outf, " = (");
2980
9.60k
    decode_macfunc (1, op1, h01, h11, src0, src1, outf);
2981
9.60k
    if (w1)
2982
2.22k
      OUTS (outf, ")");
2983
9.60k
  }
2984
2985
9.88k
      if (w0 == 1 || op0 != 3)
2986
9.20k
  {
2987
9.20k
    if (MM)
2988
3.15k
      OUTS (outf, " (M)");
2989
9.20k
    OUTS (outf, ", ");
2990
9.20k
  }
2991
9.88k
    }
2992
2993
11.8k
  if (w0 == 1 || op0 != 3)
2994
11.2k
    {
2995
      /* Clear MM option since it only matters for MAC1, and if we made
2996
         it this far, we've already shown it or we want to ignore it.  */
2997
11.2k
      MM = 0;
2998
2999
11.2k
      if (w0)
3000
4.16k
  OUTS (outf, P ? dregs (dst) : dregs_lo (dst));
3001
3002
11.2k
      if (op0 == 3)
3003
719
  OUTS (outf, " = A0");
3004
10.4k
      else
3005
10.4k
  {
3006
10.4k
    if (w0)
3007
3.44k
      OUTS (outf, " = (");
3008
10.4k
    decode_macfunc (0, op0, h00, h10, src0, src1, outf);
3009
10.4k
    if (w0)
3010
3.44k
      OUTS (outf, ")");
3011
10.4k
  }
3012
11.2k
    }
3013
3014
11.8k
  decode_optmode (mmod, MM, outf);
3015
3016
11.8k
  return 4;
3017
19.0k
}
3018
3019
static int
3020
decode_dsp32mult_0 (TIword iw0, TIword iw1, disassemble_info *outf)
3021
14.0k
{
3022
  /* dsp32mult
3023
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
3024
     | 1 | 1 | 0 | 0 |.M.| 0 | 1 |.mmod..........|.MM|.P.|.w1|.op1...|
3025
     |.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1..|
3026
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
3027
14.0k
  int w1   = ((iw0 >> (DSP32Mac_w1_bits - 16)) & DSP32Mac_w1_mask);
3028
14.0k
  int P    = ((iw0 >> (DSP32Mac_p_bits - 16)) & DSP32Mac_p_mask);
3029
14.0k
  int MM   = ((iw0 >> (DSP32Mac_MM_bits - 16)) & DSP32Mac_MM_mask);
3030
14.0k
  int mmod = ((iw0 >> (DSP32Mac_mmod_bits - 16)) & DSP32Mac_mmod_mask);
3031
14.0k
  int w0   = ((iw1 >> DSP32Mac_w0_bits) & DSP32Mac_w0_mask);
3032
14.0k
  int src0 = ((iw1 >> DSP32Mac_src0_bits) & DSP32Mac_src0_mask);
3033
14.0k
  int src1 = ((iw1 >> DSP32Mac_src1_bits) & DSP32Mac_src1_mask);
3034
14.0k
  int dst  = ((iw1 >> DSP32Mac_dst_bits) & DSP32Mac_dst_mask);
3035
14.0k
  int h10  = ((iw1 >> DSP32Mac_h10_bits) & DSP32Mac_h10_mask);
3036
14.0k
  int h00  = ((iw1 >> DSP32Mac_h00_bits) & DSP32Mac_h00_mask);
3037
14.0k
  int h11  = ((iw1 >> DSP32Mac_h11_bits) & DSP32Mac_h11_mask);
3038
14.0k
  int h01  = ((iw1 >> DSP32Mac_h01_bits) & DSP32Mac_h01_mask);
3039
3040
14.0k
  if (w1 == 0 && w0 == 0)
3041
5.00k
    return 0;
3042
3043
9.08k
  if (((1 << mmod) & (P ? 0x313 : 0x1b57)) == 0)
3044
4.89k
    return 0;
3045
3046
4.19k
  if (w1)
3047
3.33k
    {
3048
3.33k
      OUTS (outf, P ? dregs (dst + 1) : dregs_hi (dst));
3049
3.33k
      OUTS (outf, " = ");
3050
3.33k
      decode_multfunc (h01, h11, src0, src1, outf);
3051
3052
3.33k
      if (w0)
3053
1.40k
  {
3054
1.40k
    if (MM)
3055
225
      OUTS (outf, " (M)");
3056
1.40k
    MM = 0;
3057
1.40k
    OUTS (outf, ", ");
3058
1.40k
  }
3059
3.33k
    }
3060
3061
4.19k
  if (w0)
3062
2.27k
    {
3063
2.27k
      OUTS (outf, P ? dregs (dst) : dregs_lo (dst));
3064
2.27k
      OUTS (outf, " = ");
3065
2.27k
      decode_multfunc (h00, h10, src0, src1, outf);
3066
2.27k
    }
3067
3068
4.19k
  decode_optmode (mmod, MM, outf);
3069
4.19k
  return 4;
3070
9.08k
}
3071
3072
static int
3073
decode_dsp32alu_0 (TIword iw0, TIword iw1, disassemble_info *outf)
3074
32.1k
{
3075
  /* dsp32alu
3076
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
3077
     | 1 | 1 | 0 | 0 |.M.| 1 | 0 | - | - | - |.HL|.aopcde............|
3078
     |.aop...|.s.|.x.|.dst0......|.dst1......|.src0......|.src1......|
3079
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
3080
32.1k
  int s    = ((iw1 >> DSP32Alu_s_bits) & DSP32Alu_s_mask);
3081
32.1k
  int x    = ((iw1 >> DSP32Alu_x_bits) & DSP32Alu_x_mask);
3082
32.1k
  int aop  = ((iw1 >> DSP32Alu_aop_bits) & DSP32Alu_aop_mask);
3083
32.1k
  int src0 = ((iw1 >> DSP32Alu_src0_bits) & DSP32Alu_src0_mask);
3084
32.1k
  int src1 = ((iw1 >> DSP32Alu_src1_bits) & DSP32Alu_src1_mask);
3085
32.1k
  int dst0 = ((iw1 >> DSP32Alu_dst0_bits) & DSP32Alu_dst0_mask);
3086
32.1k
  int dst1 = ((iw1 >> DSP32Alu_dst1_bits) & DSP32Alu_dst1_mask);
3087
32.1k
  int HL   = ((iw0 >> (DSP32Alu_HL_bits - 16)) & DSP32Alu_HL_mask);
3088
32.1k
  int aopcde = ((iw0 >> (DSP32Alu_aopcde_bits - 16)) & DSP32Alu_aopcde_mask);
3089
3090
32.1k
  if (aop == 0 && aopcde == 9 && HL == 0 && s == 0)
3091
276
    {
3092
276
      OUTS (outf, "A0.L = ");
3093
276
      OUTS (outf, dregs_lo (src0));
3094
276
    }
3095
31.9k
  else if (aop == 2 && aopcde == 9 && HL == 1 && s == 0)
3096
47
    {
3097
47
      OUTS (outf, "A1.H = ");
3098
47
      OUTS (outf, dregs_hi (src0));
3099
47
    }
3100
31.8k
  else if (aop == 2 && aopcde == 9 && HL == 0 && s == 0)
3101
11
    {
3102
11
      OUTS (outf, "A1.L = ");
3103
11
      OUTS (outf, dregs_lo (src0));
3104
11
    }
3105
31.8k
  else if (aop == 0 && aopcde == 9 && HL == 1 && s == 0)
3106
284
    {
3107
284
      OUTS (outf, "A0.H = ");
3108
284
      OUTS (outf, dregs_hi (src0));
3109
284
    }
3110
31.5k
  else if (x == 1 && HL == 1 && aop == 3 && aopcde == 5)
3111
197
    {
3112
197
      OUTS (outf, dregs_hi (dst0));
3113
197
      OUTS (outf, " = ");
3114
197
      OUTS (outf, dregs (src0));
3115
197
      OUTS (outf, " - ");
3116
197
      OUTS (outf, dregs (src1));
3117
197
      OUTS (outf, " (RND20)");
3118
197
    }
3119
31.3k
  else if (x == 1 && HL == 1 && aop == 2 && aopcde == 5)
3120
34
    {
3121
34
      OUTS (outf, dregs_hi (dst0));
3122
34
      OUTS (outf, " = ");
3123
34
      OUTS (outf, dregs (src0));
3124
34
      OUTS (outf, " + ");
3125
34
      OUTS (outf, dregs (src1));
3126
34
      OUTS (outf, " (RND20)");
3127
34
    }
3128
31.3k
  else if (x == 0 && HL == 0 && aop == 1 && aopcde == 5)
3129
27
    {
3130
27
      OUTS (outf, dregs_lo (dst0));
3131
27
      OUTS (outf, " = ");
3132
27
      OUTS (outf, dregs (src0));
3133
27
      OUTS (outf, " - ");
3134
27
      OUTS (outf, dregs (src1));
3135
27
      OUTS (outf, " (RND12)");
3136
27
    }
3137
31.3k
  else if (x == 0 && HL == 0 && aop == 0 && aopcde == 5)
3138
86
    {
3139
86
      OUTS (outf, dregs_lo (dst0));
3140
86
      OUTS (outf, " = ");
3141
86
      OUTS (outf, dregs (src0));
3142
86
      OUTS (outf, " + ");
3143
86
      OUTS (outf, dregs (src1));
3144
86
      OUTS (outf, " (RND12)");
3145
86
    }
3146
31.2k
  else if (x == 1 && HL == 0 && aop == 3 && aopcde == 5)
3147
515
    {
3148
515
      OUTS (outf, dregs_lo (dst0));
3149
515
      OUTS (outf, " = ");
3150
515
      OUTS (outf, dregs (src0));
3151
515
      OUTS (outf, " - ");
3152
515
      OUTS (outf, dregs (src1));
3153
515
      OUTS (outf, " (RND20)");
3154
515
    }
3155
30.7k
  else if (x == 0 && HL == 1 && aop == 0 && aopcde == 5)
3156
439
    {
3157
439
      OUTS (outf, dregs_hi (dst0));
3158
439
      OUTS (outf, " = ");
3159
439
      OUTS (outf, dregs (src0));
3160
439
      OUTS (outf, " + ");
3161
439
      OUTS (outf, dregs (src1));
3162
439
      OUTS (outf, " (RND12)");
3163
439
    }
3164
30.2k
  else if (x == 1 && HL == 0 && aop == 2 && aopcde == 5)
3165
143
    {
3166
143
      OUTS (outf, dregs_lo (dst0));
3167
143
      OUTS (outf, " = ");
3168
143
      OUTS (outf, dregs (src0));
3169
143
      OUTS (outf, " + ");
3170
143
      OUTS (outf, dregs (src1));
3171
143
      OUTS (outf, " (RND20)");
3172
143
    }
3173
30.1k
  else if (x == 0 && HL == 1 && aop == 1 && aopcde == 5)
3174
33
    {
3175
33
      OUTS (outf, dregs_hi (dst0));
3176
33
      OUTS (outf, " = ");
3177
33
      OUTS (outf, dregs (src0));
3178
33
      OUTS (outf, " - ");
3179
33
      OUTS (outf, dregs (src1));
3180
33
      OUTS (outf, " (RND12)");
3181
33
    }
3182
30.0k
  else if (HL == 1 && aop == 0 && aopcde == 2)
3183
196
    {
3184
196
      OUTS (outf, dregs_hi (dst0));
3185
196
      OUTS (outf, " = ");
3186
196
      OUTS (outf, dregs_lo (src0));
3187
196
      OUTS (outf, " + ");
3188
196
      OUTS (outf, dregs_lo (src1));
3189
196
      amod1 (s, x, outf);
3190
196
    }
3191
29.8k
  else if (HL == 1 && aop == 1 && aopcde == 2)
3192
345
    {
3193
345
      OUTS (outf, dregs_hi (dst0));
3194
345
      OUTS (outf, " = ");
3195
345
      OUTS (outf, dregs_lo (src0));
3196
345
      OUTS (outf, " + ");
3197
345
      OUTS (outf, dregs_hi (src1));
3198
345
      amod1 (s, x, outf);
3199
345
    }
3200
29.5k
  else if (HL == 1 && aop == 2 && aopcde == 2)
3201
124
    {
3202
124
      OUTS (outf, dregs_hi (dst0));
3203
124
      OUTS (outf, " = ");
3204
124
      OUTS (outf, dregs_hi (src0));
3205
124
      OUTS (outf, " + ");
3206
124
      OUTS (outf, dregs_lo (src1));
3207
124
      amod1 (s, x, outf);
3208
124
    }
3209
29.4k
  else if (HL == 1 && aop == 3 && aopcde == 2)
3210
340
    {
3211
340
      OUTS (outf, dregs_hi (dst0));
3212
340
      OUTS (outf, " = ");
3213
340
      OUTS (outf, dregs_hi (src0));
3214
340
      OUTS (outf, " + ");
3215
340
      OUTS (outf, dregs_hi (src1));
3216
340
      amod1 (s, x, outf);
3217
340
    }
3218
29.0k
  else if (HL == 0 && aop == 0 && aopcde == 3)
3219
455
    {
3220
455
      OUTS (outf, dregs_lo (dst0));
3221
455
      OUTS (outf, " = ");
3222
455
      OUTS (outf, dregs_lo (src0));
3223
455
      OUTS (outf, " - ");
3224
455
      OUTS (outf, dregs_lo (src1));
3225
455
      amod1 (s, x, outf);
3226
455
    }
3227
28.6k
  else if (HL == 0 && aop == 1 && aopcde == 3)
3228
230
    {
3229
230
      OUTS (outf, dregs_lo (dst0));
3230
230
      OUTS (outf, " = ");
3231
230
      OUTS (outf, dregs_lo (src0));
3232
230
      OUTS (outf, " - ");
3233
230
      OUTS (outf, dregs_hi (src1));
3234
230
      amod1 (s, x, outf);
3235
230
    }
3236
28.4k
  else if (HL == 0 && aop == 3 && aopcde == 2)
3237
75
    {
3238
75
      OUTS (outf, dregs_lo (dst0));
3239
75
      OUTS (outf, " = ");
3240
75
      OUTS (outf, dregs_hi (src0));
3241
75
      OUTS (outf, " + ");
3242
75
      OUTS (outf, dregs_hi (src1));
3243
75
      amod1 (s, x, outf);
3244
75
    }
3245
28.3k
  else if (HL == 1 && aop == 0 && aopcde == 3)
3246
169
    {
3247
169
      OUTS (outf, dregs_hi (dst0));
3248
169
      OUTS (outf, " = ");
3249
169
      OUTS (outf, dregs_lo (src0));
3250
169
      OUTS (outf, " - ");
3251
169
      OUTS (outf, dregs_lo (src1));
3252
169
      amod1 (s, x, outf);
3253
169
    }
3254
28.1k
  else if (HL == 1 && aop == 1 && aopcde == 3)
3255
665
    {
3256
665
      OUTS (outf, dregs_hi (dst0));
3257
665
      OUTS (outf, " = ");
3258
665
      OUTS (outf, dregs_lo (src0));
3259
665
      OUTS (outf, " - ");
3260
665
      OUTS (outf, dregs_hi (src1));
3261
665
      amod1 (s, x, outf);
3262
665
    }
3263
27.4k
  else if (HL == 1 && aop == 2 && aopcde == 3)
3264
65
    {
3265
65
      OUTS (outf, dregs_hi (dst0));
3266
65
      OUTS (outf, " = ");
3267
65
      OUTS (outf, dregs_hi (src0));
3268
65
      OUTS (outf, " - ");
3269
65
      OUTS (outf, dregs_lo (src1));
3270
65
      amod1 (s, x, outf);
3271
65
    }
3272
27.4k
  else if (HL == 1 && aop == 3 && aopcde == 3)
3273
294
    {
3274
294
      OUTS (outf, dregs_hi (dst0));
3275
294
      OUTS (outf, " = ");
3276
294
      OUTS (outf, dregs_hi (src0));
3277
294
      OUTS (outf, " - ");
3278
294
      OUTS (outf, dregs_hi (src1));
3279
294
      amod1 (s, x, outf);
3280
294
    }
3281
27.1k
  else if (HL == 0 && aop == 2 && aopcde == 2)
3282
26
    {
3283
26
      OUTS (outf, dregs_lo (dst0));
3284
26
      OUTS (outf, " = ");
3285
26
      OUTS (outf, dregs_hi (src0));
3286
26
      OUTS (outf, " + ");
3287
26
      OUTS (outf, dregs_lo (src1));
3288
26
      amod1 (s, x, outf);
3289
26
    }
3290
27.1k
  else if (HL == 0 && aop == 1 && aopcde == 2)
3291
14
    {
3292
14
      OUTS (outf, dregs_lo (dst0));
3293
14
      OUTS (outf, " = ");
3294
14
      OUTS (outf, dregs_lo (src0));
3295
14
      OUTS (outf, " + ");
3296
14
      OUTS (outf, dregs_hi (src1));
3297
14
      amod1 (s, x, outf);
3298
14
    }
3299
27.0k
  else if (HL == 0 && aop == 2 && aopcde == 3)
3300
203
    {
3301
203
      OUTS (outf, dregs_lo (dst0));
3302
203
      OUTS (outf, " = ");
3303
203
      OUTS (outf, dregs_hi (src0));
3304
203
      OUTS (outf, " - ");
3305
203
      OUTS (outf, dregs_lo (src1));
3306
203
      amod1 (s, x, outf);
3307
203
    }
3308
26.8k
  else if (HL == 0 && aop == 3 && aopcde == 3)
3309
766
    {
3310
766
      OUTS (outf, dregs_lo (dst0));
3311
766
      OUTS (outf, " = ");
3312
766
      OUTS (outf, dregs_hi (src0));
3313
766
      OUTS (outf, " - ");
3314
766
      OUTS (outf, dregs_hi (src1));
3315
766
      amod1 (s, x, outf);
3316
766
    }
3317
26.1k
  else if (HL == 0 && aop == 0 && aopcde == 2)
3318
372
    {
3319
372
      OUTS (outf, dregs_lo (dst0));
3320
372
      OUTS (outf, " = ");
3321
372
      OUTS (outf, dregs_lo (src0));
3322
372
      OUTS (outf, " + ");
3323
372
      OUTS (outf, dregs_lo (src1));
3324
372
      amod1 (s, x, outf);
3325
372
    }
3326
25.7k
  else if (aop == 0 && aopcde == 9 && s == 1)
3327
668
    {
3328
668
      OUTS (outf, "A0 = ");
3329
668
      OUTS (outf, dregs (src0));
3330
668
    }
3331
25.0k
  else if (aop == 3 && aopcde == 11 && s == 0)
3332
515
    OUTS (outf, "A0 -= A1");
3333
3334
24.5k
  else if (aop == 3 && aopcde == 11 && s == 1)
3335
265
    OUTS (outf, "A0 -= A1 (W32)");
3336
3337
24.3k
  else if (aop == 1 && aopcde == 22 && HL == 1)
3338
222
    {
3339
222
      OUTS (outf, dregs (dst0));
3340
222
      OUTS (outf, " = BYTEOP2P (");
3341
222
      OUTS (outf, dregs (src0 + 1));
3342
222
      OUTS (outf, ":");
3343
222
      OUTS (outf, imm5d (src0));
3344
222
      OUTS (outf, ", ");
3345
222
      OUTS (outf, dregs (src1 + 1));
3346
222
      OUTS (outf, ":");
3347
222
      OUTS (outf, imm5d (src1));
3348
222
      OUTS (outf, ") (TH");
3349
222
      if (s == 1)
3350
33
  OUTS (outf, ", R)");
3351
189
      else
3352
189
  OUTS (outf, ")");
3353
222
    }
3354
24.0k
  else if (aop == 1 && aopcde == 22 && HL == 0)
3355
221
    {
3356
221
      OUTS (outf, dregs (dst0));
3357
221
      OUTS (outf, " = BYTEOP2P (");
3358
221
      OUTS (outf, dregs (src0 + 1));
3359
221
      OUTS (outf, ":");
3360
221
      OUTS (outf, imm5d (src0));
3361
221
      OUTS (outf, ", ");
3362
221
      OUTS (outf, dregs (src1 + 1));
3363
221
      OUTS (outf, ":");
3364
221
      OUTS (outf, imm5d (src1));
3365
221
      OUTS (outf, ") (TL");
3366
221
      if (s == 1)
3367
45
  OUTS (outf, ", R)");
3368
176
      else
3369
176
  OUTS (outf, ")");
3370
221
    }
3371
23.8k
  else if (aop == 0 && aopcde == 22 && HL == 1)
3372
300
    {
3373
300
      OUTS (outf, dregs (dst0));
3374
300
      OUTS (outf, " = BYTEOP2P (");
3375
300
      OUTS (outf, dregs (src0 + 1));
3376
300
      OUTS (outf, ":");
3377
300
      OUTS (outf, imm5d (src0));
3378
300
      OUTS (outf, ", ");
3379
300
      OUTS (outf, dregs (src1 + 1));
3380
300
      OUTS (outf, ":");
3381
300
      OUTS (outf, imm5d (src1));
3382
300
      OUTS (outf, ") (RNDH");
3383
300
      if (s == 1)
3384
98
  OUTS (outf, ", R)");
3385
202
      else
3386
202
  OUTS (outf, ")");
3387
300
    }
3388
23.5k
  else if (aop == 0 && aopcde == 22 && HL == 0)
3389
329
    {
3390
329
      OUTS (outf, dregs (dst0));
3391
329
      OUTS (outf, " = BYTEOP2P (");
3392
329
      OUTS (outf, dregs (src0 + 1));
3393
329
      OUTS (outf, ":");
3394
329
      OUTS (outf, imm5d (src0));
3395
329
      OUTS (outf, ", ");
3396
329
      OUTS (outf, dregs (src1 + 1));
3397
329
      OUTS (outf, ":");
3398
329
      OUTS (outf, imm5d (src1));
3399
329
      OUTS (outf, ") (RNDL");
3400
329
      if (s == 1)
3401
229
  OUTS (outf, ", R)");
3402
100
      else
3403
100
  OUTS (outf, ")");
3404
329
    }
3405
23.2k
  else if (aop == 0 && s == 0 && aopcde == 8)
3406
76
    OUTS (outf, "A0 = 0");
3407
3408
23.1k
  else if (aop == 0 && s == 1 && aopcde == 8)
3409
130
    OUTS (outf, "A0 = A0 (S)");
3410
3411
23.0k
  else if (aop == 1 && s == 0 && aopcde == 8)
3412
53
    OUTS (outf, "A1 = 0");
3413
3414
22.9k
  else if (aop == 1 && s == 1 && aopcde == 8)
3415
50
    OUTS (outf, "A1 = A1 (S)");
3416
3417
22.9k
  else if (aop == 2 && s == 0 && aopcde == 8)
3418
49
    OUTS (outf, "A1 = A0 = 0");
3419
3420
22.8k
  else if (aop == 2 && s == 1 && aopcde == 8)
3421
71
    OUTS (outf, "A1 = A1 (S), A0 = A0 (S)");
3422
3423
22.8k
  else if (aop == 3 && s == 0 && aopcde == 8)
3424
637
    OUTS (outf, "A0 = A1");
3425
3426
22.1k
  else if (aop == 3 && s == 1 && aopcde == 8)
3427
940
    OUTS (outf, "A1 = A0");
3428
3429
21.2k
  else if (aop == 1 && aopcde == 9 && s == 0)
3430
16
    {
3431
16
      OUTS (outf, "A0.X = ");
3432
16
      OUTS (outf, dregs_lo (src0));
3433
16
    }
3434
21.2k
  else if (aop == 1 && HL == 0 && aopcde == 11)
3435
16
    {
3436
16
      OUTS (outf, dregs_lo (dst0));
3437
16
      OUTS (outf, " = (A0 += A1)");
3438
16
    }
3439
21.1k
  else if (aop == 3 && HL == 0 && aopcde == 16)
3440
401
    OUTS (outf, "A1 = ABS A1, A0 = ABS A0");
3441
3442
20.7k
  else if (aop == 0 && aopcde == 23 && HL == 1)
3443
92
    {
3444
92
      OUTS (outf, dregs (dst0));
3445
92
      OUTS (outf, " = BYTEOP3P (");
3446
92
      OUTS (outf, dregs (src0 + 1));
3447
92
      OUTS (outf, ":");
3448
92
      OUTS (outf, imm5d (src0));
3449
92
      OUTS (outf, ", ");
3450
92
      OUTS (outf, dregs (src1 + 1));
3451
92
      OUTS (outf, ":");
3452
92
      OUTS (outf, imm5d (src1));
3453
92
      OUTS (outf, ") (HI");
3454
92
      if (s == 1)
3455
49
  OUTS (outf, ", R)");
3456
43
      else
3457
43
  OUTS (outf, ")");
3458
92
    }
3459
20.7k
  else if (aop == 3 && aopcde == 9 && s == 0)
3460
75
    {
3461
75
      OUTS (outf, "A1.X = ");
3462
75
      OUTS (outf, dregs_lo (src0));
3463
75
    }
3464
20.6k
  else if (aop == 1 && HL == 1 && aopcde == 16)
3465
184
    OUTS (outf, "A1 = ABS A1");
3466
3467
20.4k
  else if (aop == 0 && HL == 1 && aopcde == 16)
3468
294
    OUTS (outf, "A1 = ABS A0");
3469
3470
20.1k
  else if (aop == 2 && aopcde == 9 && s == 1)
3471
70
    {
3472
70
      OUTS (outf, "A1 = ");
3473
70
      OUTS (outf, dregs (src0));
3474
70
    }
3475
20.0k
  else if (HL == 0 && aop == 3 && aopcde == 12)
3476
92
    {
3477
92
      OUTS (outf, dregs_lo (dst0));
3478
92
      OUTS (outf, " = ");
3479
92
      OUTS (outf, dregs (src0));
3480
92
      OUTS (outf, " (RND)");
3481
92
    }
3482
19.9k
  else if (aop == 1 && HL == 0 && aopcde == 16)
3483
37
    OUTS (outf, "A0 = ABS A1");
3484
3485
19.9k
  else if (aop == 0 && HL == 0 && aopcde == 16)
3486
828
    OUTS (outf, "A0 = ABS A0");
3487
3488
19.1k
  else if (aop == 3 && HL == 0 && aopcde == 15)
3489
115
    {
3490
115
      OUTS (outf, dregs (dst0));
3491
115
      OUTS (outf, " = -");
3492
115
      OUTS (outf, dregs (src0));
3493
115
      OUTS (outf, " (V)");
3494
115
    }
3495
19.0k
  else if (aop == 3 && s == 1 && HL == 0 && aopcde == 7)
3496
52
    {
3497
52
      OUTS (outf, dregs (dst0));
3498
52
      OUTS (outf, " = -");
3499
52
      OUTS (outf, dregs (src0));
3500
52
      OUTS (outf, " (S)");
3501
52
    }
3502
18.9k
  else if (aop == 3 && s == 0 && HL == 0 && aopcde == 7)
3503
252
    {
3504
252
      OUTS (outf, dregs (dst0));
3505
252
      OUTS (outf, " = -");
3506
252
      OUTS (outf, dregs (src0));
3507
252
      OUTS (outf, " (NS)");
3508
252
    }
3509
18.7k
  else if (aop == 1 && HL == 1 && aopcde == 11)
3510
81
    {
3511
81
      OUTS (outf, dregs_hi (dst0));
3512
81
      OUTS (outf, " = (A0 += A1)");
3513
81
    }
3514
18.6k
  else if (aop == 2 && aopcde == 11 && s == 0)
3515
238
    OUTS (outf, "A0 += A1");
3516
3517
18.3k
  else if (aop == 2 && aopcde == 11 && s == 1)
3518
203
    OUTS (outf, "A0 += A1 (W32)");
3519
3520
18.1k
  else if (aop == 3 && HL == 0 && aopcde == 14)
3521
69
    OUTS (outf, "A1 = -A1, A0 = -A0");
3522
3523
18.1k
  else if (HL == 1 && aop == 3 && aopcde == 12)
3524
26
    {
3525
26
      OUTS (outf, dregs_hi (dst0));
3526
26
      OUTS (outf, " = ");
3527
26
      OUTS (outf, dregs (src0));
3528
26
      OUTS (outf, " (RND)");
3529
26
    }
3530
18.0k
  else if (aop == 0 && aopcde == 23 && HL == 0)
3531
333
    {
3532
333
      OUTS (outf, dregs (dst0));
3533
333
      OUTS (outf, " = BYTEOP3P (");
3534
333
      OUTS (outf, dregs (src0 + 1));
3535
333
      OUTS (outf, ":");
3536
333
      OUTS (outf, imm5d (src0));
3537
333
      OUTS (outf, ", ");
3538
333
      OUTS (outf, dregs (src1 + 1));
3539
333
      OUTS (outf, ":");
3540
333
      OUTS (outf, imm5d (src1));
3541
333
      OUTS (outf, ") (LO");
3542
333
      if (s == 1)
3543
49
  OUTS (outf, ", R)");
3544
284
      else
3545
284
  OUTS (outf, ")");
3546
333
    }
3547
17.7k
  else if (aop == 0 && HL == 0 && aopcde == 14)
3548
302
    OUTS (outf, "A0 = -A0");
3549
3550
17.4k
  else if (aop == 1 && HL == 0 && aopcde == 14)
3551
328
    OUTS (outf, "A0 = -A1");
3552
3553
17.1k
  else if (aop == 0 && HL == 1 && aopcde == 14)
3554
108
    OUTS (outf, "A1 = -A0");
3555
3556
17.0k
  else if (aop == 1 && HL == 1 && aopcde == 14)
3557
19
    OUTS (outf, "A1 = -A1");
3558
3559
16.9k
  else if (aop == 0 && aopcde == 12)
3560
79
    {
3561
79
      OUTS (outf, dregs_hi (dst0));
3562
79
      OUTS (outf, " = ");
3563
79
      OUTS (outf, dregs_lo (dst0));
3564
79
      OUTS (outf, " = SIGN (");
3565
79
      OUTS (outf, dregs_hi (src0));
3566
79
      OUTS (outf, ") * ");
3567
79
      OUTS (outf, dregs_hi (src1));
3568
79
      OUTS (outf, " + SIGN (");
3569
79
      OUTS (outf, dregs_lo (src0));
3570
79
      OUTS (outf, ") * ");
3571
79
      OUTS (outf, dregs_lo (src1));
3572
79
    }
3573
16.9k
  else if (aop == 2 && aopcde == 0)
3574
242
    {
3575
242
      OUTS (outf, dregs (dst0));
3576
242
      OUTS (outf, " = ");
3577
242
      OUTS (outf, dregs (src0));
3578
242
      OUTS (outf, " -|+ ");
3579
242
      OUTS (outf, dregs (src1));
3580
242
      amod0 (s, x, outf);
3581
242
    }
3582
16.6k
  else if (aop == 1 && aopcde == 12)
3583
514
    {
3584
514
      OUTS (outf, dregs (dst1));
3585
514
      OUTS (outf, " = A1.L + A1.H, ");
3586
514
      OUTS (outf, dregs (dst0));
3587
514
      OUTS (outf, " = A0.L + A0.H");
3588
514
    }
3589
16.1k
  else if (aop == 2 && aopcde == 4)
3590
26
    {
3591
26
      OUTS (outf, dregs (dst1));
3592
26
      OUTS (outf, " = ");
3593
26
      OUTS (outf, dregs (src0));
3594
26
      OUTS (outf, " + ");
3595
26
      OUTS (outf, dregs (src1));
3596
26
      OUTS (outf, ", ");
3597
26
      OUTS (outf, dregs (dst0));
3598
26
      OUTS (outf, " = ");
3599
26
      OUTS (outf, dregs (src0));
3600
26
      OUTS (outf, " - ");
3601
26
      OUTS (outf, dregs (src1));
3602
26
      amod1 (s, x, outf);
3603
26
    }
3604
16.1k
  else if (HL == 0 && aopcde == 1)
3605
1.26k
    {
3606
1.26k
      OUTS (outf, dregs (dst1));
3607
1.26k
      OUTS (outf, " = ");
3608
1.26k
      OUTS (outf, dregs (src0));
3609
1.26k
      OUTS (outf, " +|+ ");
3610
1.26k
      OUTS (outf, dregs (src1));
3611
1.26k
      OUTS (outf, ", ");
3612
1.26k
      OUTS (outf, dregs (dst0));
3613
1.26k
      OUTS (outf, " = ");
3614
1.26k
      OUTS (outf, dregs (src0));
3615
1.26k
      OUTS (outf, " -|- ");
3616
1.26k
      OUTS (outf, dregs (src1));
3617
1.26k
      amod0amod2 (s, x, aop, outf);
3618
1.26k
    }
3619
14.8k
  else if (aop == 0 && aopcde == 11)
3620
778
    {
3621
778
      OUTS (outf, dregs (dst0));
3622
778
      OUTS (outf, " = (A0 += A1)");
3623
778
    }
3624
14.0k
  else if (aop == 0 && aopcde == 10)
3625
55
    {
3626
55
      OUTS (outf, dregs_lo (dst0));
3627
55
      OUTS (outf, " = A0.X");
3628
55
    }
3629
14.0k
  else if (aop == 1 && aopcde == 10)
3630
37
    {
3631
37
      OUTS (outf, dregs_lo (dst0));
3632
37
      OUTS (outf, " = A1.X");
3633
37
    }
3634
13.9k
  else if (aop == 1 && aopcde == 0)
3635
509
    {
3636
509
      OUTS (outf, dregs (dst0));
3637
509
      OUTS (outf, " = ");
3638
509
      OUTS (outf, dregs (src0));
3639
509
      OUTS (outf, " +|- ");
3640
509
      OUTS (outf, dregs (src1));
3641
509
      amod0 (s, x, outf);
3642
509
    }
3643
13.4k
  else if (aop == 3 && aopcde == 0)
3644
2.94k
    {
3645
2.94k
      OUTS (outf, dregs (dst0));
3646
2.94k
      OUTS (outf, " = ");
3647
2.94k
      OUTS (outf, dregs (src0));
3648
2.94k
      OUTS (outf, " -|- ");
3649
2.94k
      OUTS (outf, dregs (src1));
3650
2.94k
      amod0 (s, x, outf);
3651
2.94k
    }
3652
10.5k
  else if (aop == 1 && aopcde == 4)
3653
403
    {
3654
403
      OUTS (outf, dregs (dst0));
3655
403
      OUTS (outf, " = ");
3656
403
      OUTS (outf, dregs (src0));
3657
403
      OUTS (outf, " - ");
3658
403
      OUTS (outf, dregs (src1));
3659
403
      amod1 (s, x, outf);
3660
403
    }
3661
10.1k
  else if (aop == 0 && aopcde == 17)
3662
419
    {
3663
419
      OUTS (outf, dregs (dst1));
3664
419
      OUTS (outf, " = A1 + A0, ");
3665
419
      OUTS (outf, dregs (dst0));
3666
419
      OUTS (outf, " = A1 - A0");
3667
419
      amod1 (s, x, outf);
3668
419
    }
3669
9.72k
  else if (aop == 1 && aopcde == 17)
3670
84
    {
3671
84
      OUTS (outf, dregs (dst1));
3672
84
      OUTS (outf, " = A0 + A1, ");
3673
84
      OUTS (outf, dregs (dst0));
3674
84
      OUTS (outf, " = A0 - A1");
3675
84
      amod1 (s, x, outf);
3676
84
    }
3677
9.63k
  else if (aop == 0 && aopcde == 18)
3678
112
    {
3679
112
      OUTS (outf, "SAA (");
3680
112
      OUTS (outf, dregs (src0 + 1));
3681
112
      OUTS (outf, ":");
3682
112
      OUTS (outf, imm5d (src0));
3683
112
      OUTS (outf, ", ");
3684
112
      OUTS (outf, dregs (src1 + 1));
3685
112
      OUTS (outf, ":");
3686
112
      OUTS (outf, imm5d (src1));
3687
112
      OUTS (outf, ")");
3688
112
      aligndir (s, outf);
3689
112
    }
3690
9.52k
  else if (aop == 3 && aopcde == 18)
3691
51
    OUTS (outf, "DISALGNEXCPT");
3692
3693
9.47k
  else if (aop == 0 && aopcde == 20)
3694
271
    {
3695
271
      OUTS (outf, dregs (dst0));
3696
271
      OUTS (outf, " = BYTEOP1P (");
3697
271
      OUTS (outf, dregs (src0 + 1));
3698
271
      OUTS (outf, ":");
3699
271
      OUTS (outf, imm5d (src0));
3700
271
      OUTS (outf, ", ");
3701
271
      OUTS (outf, dregs (src1 + 1));
3702
271
      OUTS (outf, ":");
3703
271
      OUTS (outf, imm5d (src1));
3704
271
      OUTS (outf, ")");
3705
271
      aligndir (s, outf);
3706
271
    }
3707
9.20k
  else if (aop == 1 && aopcde == 20)
3708
155
    {
3709
155
      OUTS (outf, dregs (dst0));
3710
155
      OUTS (outf, " = BYTEOP1P (");
3711
155
      OUTS (outf, dregs (src0 + 1));
3712
155
      OUTS (outf, ":");
3713
155
      OUTS (outf, imm5d (src0));
3714
155
      OUTS (outf, ", ");
3715
155
      OUTS (outf, dregs (src1 + 1));
3716
155
      OUTS (outf, ":");
3717
155
      OUTS (outf, imm5d (src1));
3718
155
      OUTS (outf, ") (T");
3719
155
      if (s == 1)
3720
62
  OUTS (outf, ", R)");
3721
93
      else
3722
93
  OUTS (outf, ")");
3723
155
    }
3724
9.05k
  else if (aop == 0 && aopcde == 21)
3725
532
    {
3726
532
      OUTS (outf, "(");
3727
532
      OUTS (outf, dregs (dst1));
3728
532
      OUTS (outf, ", ");
3729
532
      OUTS (outf, dregs (dst0));
3730
532
      OUTS (outf, ") = BYTEOP16P (");
3731
532
      OUTS (outf, dregs (src0 + 1));
3732
532
      OUTS (outf, ":");
3733
532
      OUTS (outf, imm5d (src0));
3734
532
      OUTS (outf, ", ");
3735
532
      OUTS (outf, dregs (src1 + 1));
3736
532
      OUTS (outf, ":");
3737
532
      OUTS (outf, imm5d (src1));
3738
532
      OUTS (outf, ")");
3739
532
      aligndir (s, outf);
3740
532
    }
3741
8.51k
  else if (aop == 1 && aopcde == 21)
3742
41
    {
3743
41
      OUTS (outf, "(");
3744
41
      OUTS (outf, dregs (dst1));
3745
41
      OUTS (outf, ", ");
3746
41
      OUTS (outf, dregs (dst0));
3747
41
      OUTS (outf, ") = BYTEOP16M (");
3748
41
      OUTS (outf, dregs (src0 + 1));
3749
41
      OUTS (outf, ":");
3750
41
      OUTS (outf, imm5d (src0));
3751
41
      OUTS (outf, ", ");
3752
41
      OUTS (outf, dregs (src1 + 1));
3753
41
      OUTS (outf, ":");
3754
41
      OUTS (outf, imm5d (src1));
3755
41
      OUTS (outf, ")");
3756
41
      aligndir (s, outf);
3757
41
    }
3758
8.47k
  else if (aop == 2 && aopcde == 7)
3759
187
    {
3760
187
      OUTS (outf, dregs (dst0));
3761
187
      OUTS (outf, " = ABS ");
3762
187
      OUTS (outf, dregs (src0));
3763
187
    }
3764
8.29k
  else if (aop == 1 && aopcde == 7)
3765
19
    {
3766
19
      OUTS (outf, dregs (dst0));
3767
19
      OUTS (outf, " = MIN (");
3768
19
      OUTS (outf, dregs (src0));
3769
19
      OUTS (outf, ", ");
3770
19
      OUTS (outf, dregs (src1));
3771
19
      OUTS (outf, ")");
3772
19
    }
3773
8.27k
  else if (aop == 0 && aopcde == 7)
3774
178
    {
3775
178
      OUTS (outf, dregs (dst0));
3776
178
      OUTS (outf, " = MAX (");
3777
178
      OUTS (outf, dregs (src0));
3778
178
      OUTS (outf, ", ");
3779
178
      OUTS (outf, dregs (src1));
3780
178
      OUTS (outf, ")");
3781
178
    }
3782
8.09k
  else if (aop == 2 && aopcde == 6)
3783
126
    {
3784
126
      OUTS (outf, dregs (dst0));
3785
126
      OUTS (outf, " = ABS ");
3786
126
      OUTS (outf, dregs (src0));
3787
126
      OUTS (outf, " (V)");
3788
126
    }
3789
7.96k
  else if (aop == 1 && aopcde == 6)
3790
280
    {
3791
280
      OUTS (outf, dregs (dst0));
3792
280
      OUTS (outf, " = MIN (");
3793
280
      OUTS (outf, dregs (src0));
3794
280
      OUTS (outf, ", ");
3795
280
      OUTS (outf, dregs (src1));
3796
280
      OUTS (outf, ") (V)");
3797
280
    }
3798
7.68k
  else if (aop == 0 && aopcde == 6)
3799
177
    {
3800
177
      OUTS (outf, dregs (dst0));
3801
177
      OUTS (outf, " = MAX (");
3802
177
      OUTS (outf, dregs (src0));
3803
177
      OUTS (outf, ", ");
3804
177
      OUTS (outf, dregs (src1));
3805
177
      OUTS (outf, ") (V)");
3806
177
    }
3807
7.51k
  else if (HL == 1 && aopcde == 1)
3808
230
    {
3809
230
      OUTS (outf, dregs (dst1));
3810
230
      OUTS (outf, " = ");
3811
230
      OUTS (outf, dregs (src0));
3812
230
      OUTS (outf, " +|- ");
3813
230
      OUTS (outf, dregs (src1));
3814
230
      OUTS (outf, ", ");
3815
230
      OUTS (outf, dregs (dst0));
3816
230
      OUTS (outf, " = ");
3817
230
      OUTS (outf, dregs (src0));
3818
230
      OUTS (outf, " -|+ ");
3819
230
      OUTS (outf, dregs (src1));
3820
230
      amod0amod2 (s, x, aop, outf);
3821
230
    }
3822
7.28k
  else if (aop == 0 && aopcde == 4)
3823
262
    {
3824
262
      OUTS (outf, dregs (dst0));
3825
262
      OUTS (outf, " = ");
3826
262
      OUTS (outf, dregs (src0));
3827
262
      OUTS (outf, " + ");
3828
262
      OUTS (outf, dregs (src1));
3829
262
      amod1 (s, x, outf);
3830
262
    }
3831
7.01k
  else if (aop == 0 && aopcde == 0)
3832
2.25k
    {
3833
2.25k
      OUTS (outf, dregs (dst0));
3834
2.25k
      OUTS (outf, " = ");
3835
2.25k
      OUTS (outf, dregs (src0));
3836
2.25k
      OUTS (outf, " +|+ ");
3837
2.25k
      OUTS (outf, dregs (src1));
3838
2.25k
      amod0 (s, x, outf);
3839
2.25k
    }
3840
4.76k
  else if (aop == 0 && aopcde == 24)
3841
99
    {
3842
99
      OUTS (outf, dregs (dst0));
3843
99
      OUTS (outf, " = BYTEPACK (");
3844
99
      OUTS (outf, dregs (src0));
3845
99
      OUTS (outf, ", ");
3846
99
      OUTS (outf, dregs (src1));
3847
99
      OUTS (outf, ")");
3848
99
    }
3849
4.66k
  else if (aop == 1 && aopcde == 24)
3850
243
    {
3851
243
      OUTS (outf, "(");
3852
243
      OUTS (outf, dregs (dst1));
3853
243
      OUTS (outf, ", ");
3854
243
      OUTS (outf, dregs (dst0));
3855
243
      OUTS (outf, ") = BYTEUNPACK ");
3856
243
      OUTS (outf, dregs (src0 + 1));
3857
243
      OUTS (outf, ":");
3858
243
      OUTS (outf, imm5d (src0));
3859
243
      aligndir (s, outf);
3860
243
    }
3861
4.42k
  else if (aopcde == 13)
3862
334
    {
3863
334
      OUTS (outf, "(");
3864
334
      OUTS (outf, dregs (dst1));
3865
334
      OUTS (outf, ", ");
3866
334
      OUTS (outf, dregs (dst0));
3867
334
      OUTS (outf, ") = SEARCH ");
3868
334
      OUTS (outf, dregs (src0));
3869
334
      OUTS (outf, " (");
3870
334
      searchmod (aop, outf);
3871
334
      OUTS (outf, ")");
3872
334
    }
3873
4.09k
  else
3874
4.09k
    return 0;
3875
3876
28.0k
  return 4;
3877
32.1k
}
3878
3879
static int
3880
decode_dsp32shift_0 (TIword iw0, TIword iw1, disassemble_info *outf)
3881
16.7k
{
3882
  /* dsp32shift
3883
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
3884
     | 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 0 | - | - |.sopcde............|
3885
     |.sop...|.HLs...|.dst0......| - | - | - |.src0......|.src1......|
3886
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
3887
16.7k
  int HLs  = ((iw1 >> DSP32Shift_HLs_bits) & DSP32Shift_HLs_mask);
3888
16.7k
  int sop  = ((iw1 >> DSP32Shift_sop_bits) & DSP32Shift_sop_mask);
3889
16.7k
  int src0 = ((iw1 >> DSP32Shift_src0_bits) & DSP32Shift_src0_mask);
3890
16.7k
  int src1 = ((iw1 >> DSP32Shift_src1_bits) & DSP32Shift_src1_mask);
3891
16.7k
  int dst0 = ((iw1 >> DSP32Shift_dst0_bits) & DSP32Shift_dst0_mask);
3892
16.7k
  int sopcde = ((iw0 >> (DSP32Shift_sopcde_bits - 16)) & DSP32Shift_sopcde_mask);
3893
16.7k
  const char *acc01 = (HLs & 1) == 0 ? "A0" : "A1";
3894
3895
16.7k
  if (HLs == 0 && sop == 0 && sopcde == 0)
3896
289
    {
3897
289
      OUTS (outf, dregs_lo (dst0));
3898
289
      OUTS (outf, " = ASHIFT ");
3899
289
      OUTS (outf, dregs_lo (src1));
3900
289
      OUTS (outf, " BY ");
3901
289
      OUTS (outf, dregs_lo (src0));
3902
289
    }
3903
16.4k
  else if (HLs == 1 && sop == 0 && sopcde == 0)
3904
82
    {
3905
82
      OUTS (outf, dregs_lo (dst0));
3906
82
      OUTS (outf, " = ASHIFT ");
3907
82
      OUTS (outf, dregs_hi (src1));
3908
82
      OUTS (outf, " BY ");
3909
82
      OUTS (outf, dregs_lo (src0));
3910
82
    }
3911
16.4k
  else if (HLs == 2 && sop == 0 && sopcde == 0)
3912
356
    {
3913
356
      OUTS (outf, dregs_hi (dst0));
3914
356
      OUTS (outf, " = ASHIFT ");
3915
356
      OUTS (outf, dregs_lo (src1));
3916
356
      OUTS (outf, " BY ");
3917
356
      OUTS (outf, dregs_lo (src0));
3918
356
    }
3919
16.0k
  else if (HLs == 3 && sop == 0 && sopcde == 0)
3920
76
    {
3921
76
      OUTS (outf, dregs_hi (dst0));
3922
76
      OUTS (outf, " = ASHIFT ");
3923
76
      OUTS (outf, dregs_hi (src1));
3924
76
      OUTS (outf, " BY ");
3925
76
      OUTS (outf, dregs_lo (src0));
3926
76
    }
3927
15.9k
  else if (HLs == 0 && sop == 1 && sopcde == 0)
3928
565
    {
3929
565
      OUTS (outf, dregs_lo (dst0));
3930
565
      OUTS (outf, " = ASHIFT ");
3931
565
      OUTS (outf, dregs_lo (src1));
3932
565
      OUTS (outf, " BY ");
3933
565
      OUTS (outf, dregs_lo (src0));
3934
565
      OUTS (outf, " (S)");
3935
565
    }
3936
15.4k
  else if (HLs == 1 && sop == 1 && sopcde == 0)
3937
270
    {
3938
270
      OUTS (outf, dregs_lo (dst0));
3939
270
      OUTS (outf, " = ASHIFT ");
3940
270
      OUTS (outf, dregs_hi (src1));
3941
270
      OUTS (outf, " BY ");
3942
270
      OUTS (outf, dregs_lo (src0));
3943
270
      OUTS (outf, " (S)");
3944
270
    }
3945
15.1k
  else if (HLs == 2 && sop == 1 && sopcde == 0)
3946
69
    {
3947
69
      OUTS (outf, dregs_hi (dst0));
3948
69
      OUTS (outf, " = ASHIFT ");
3949
69
      OUTS (outf, dregs_lo (src1));
3950
69
      OUTS (outf, " BY ");
3951
69
      OUTS (outf, dregs_lo (src0));
3952
69
      OUTS (outf, " (S)");
3953
69
    }
3954
15.0k
  else if (HLs == 3 && sop == 1 && sopcde == 0)
3955
185
    {
3956
185
      OUTS (outf, dregs_hi (dst0));
3957
185
      OUTS (outf, " = ASHIFT ");
3958
185
      OUTS (outf, dregs_hi (src1));
3959
185
      OUTS (outf, " BY ");
3960
185
      OUTS (outf, dregs_lo (src0));
3961
185
      OUTS (outf, " (S)");
3962
185
    }
3963
14.8k
  else if (sop == 2 && sopcde == 0)
3964
147
    {
3965
147
      OUTS (outf, (HLs & 2) == 0 ? dregs_lo (dst0) : dregs_hi (dst0));
3966
147
      OUTS (outf, " = LSHIFT ");
3967
147
      OUTS (outf, (HLs & 1) == 0 ? dregs_lo (src1) : dregs_hi (src1));
3968
147
      OUTS (outf, " BY ");
3969
147
      OUTS (outf, dregs_lo (src0));
3970
147
    }
3971
14.7k
  else if (sop == 0 && sopcde == 3)
3972
143
    {
3973
143
      OUTS (outf, acc01);
3974
143
      OUTS (outf, " = ASHIFT ");
3975
143
      OUTS (outf, acc01);
3976
143
      OUTS (outf, " BY ");
3977
143
      OUTS (outf, dregs_lo (src0));
3978
143
    }
3979
14.6k
  else if (sop == 1 && sopcde == 3)
3980
234
    {
3981
234
      OUTS (outf, acc01);
3982
234
      OUTS (outf, " = LSHIFT ");
3983
234
      OUTS (outf, acc01);
3984
234
      OUTS (outf, " BY ");
3985
234
      OUTS (outf, dregs_lo (src0));
3986
234
    }
3987
14.3k
  else if (sop == 2 && sopcde == 3)
3988
361
    {
3989
361
      OUTS (outf, acc01);
3990
361
      OUTS (outf, " = ROT ");
3991
361
      OUTS (outf, acc01);
3992
361
      OUTS (outf, " BY ");
3993
361
      OUTS (outf, dregs_lo (src0));
3994
361
    }
3995
14.0k
  else if (sop == 3 && sopcde == 3)
3996
118
    {
3997
118
      OUTS (outf, dregs (dst0));
3998
118
      OUTS (outf, " = ROT ");
3999
118
      OUTS (outf, dregs (src1));
4000
118
      OUTS (outf, " BY ");
4001
118
      OUTS (outf, dregs_lo (src0));
4002
118
    }
4003
13.8k
  else if (sop == 1 && sopcde == 1)
4004
138
    {
4005
138
      OUTS (outf, dregs (dst0));
4006
138
      OUTS (outf, " = ASHIFT ");
4007
138
      OUTS (outf, dregs (src1));
4008
138
      OUTS (outf, " BY ");
4009
138
      OUTS (outf, dregs_lo (src0));
4010
138
      OUTS (outf, " (V, S)");
4011
138
    }
4012
13.7k
  else if (sop == 0 && sopcde == 1)
4013
325
    {
4014
325
      OUTS (outf, dregs (dst0));
4015
325
      OUTS (outf, " = ASHIFT ");
4016
325
      OUTS (outf, dregs (src1));
4017
325
      OUTS (outf, " BY ");
4018
325
      OUTS (outf, dregs_lo (src0));
4019
325
      OUTS (outf, " (V)");
4020
325
    }
4021
13.4k
  else if (sop == 0 && sopcde == 2)
4022
609
    {
4023
609
      OUTS (outf, dregs (dst0));
4024
609
      OUTS (outf, " = ASHIFT ");
4025
609
      OUTS (outf, dregs (src1));
4026
609
      OUTS (outf, " BY ");
4027
609
      OUTS (outf, dregs_lo (src0));
4028
609
    }
4029
12.8k
  else if (sop == 1 && sopcde == 2)
4030
910
    {
4031
910
      OUTS (outf, dregs (dst0));
4032
910
      OUTS (outf, " = ASHIFT ");
4033
910
      OUTS (outf, dregs (src1));
4034
910
      OUTS (outf, " BY ");
4035
910
      OUTS (outf, dregs_lo (src0));
4036
910
      OUTS (outf, " (S)");
4037
910
    }
4038
11.9k
  else if (sop == 2 && sopcde == 2)
4039
913
    {
4040
913
      OUTS (outf, dregs (dst0));
4041
913
      OUTS (outf, " = LSHIFT ");
4042
913
      OUTS (outf, dregs (src1));
4043
913
      OUTS (outf, " BY ");
4044
913
      OUTS (outf, dregs_lo (src0));
4045
913
    }
4046
10.9k
  else if (sop == 3 && sopcde == 2)
4047
244
    {
4048
244
      OUTS (outf, dregs (dst0));
4049
244
      OUTS (outf, " = ROT ");
4050
244
      OUTS (outf, dregs (src1));
4051
244
      OUTS (outf, " BY ");
4052
244
      OUTS (outf, dregs_lo (src0));
4053
244
    }
4054
10.7k
  else if (sop == 2 && sopcde == 1)
4055
86
    {
4056
86
      OUTS (outf, dregs (dst0));
4057
86
      OUTS (outf, " = LSHIFT ");
4058
86
      OUTS (outf, dregs (src1));
4059
86
      OUTS (outf, " BY ");
4060
86
      OUTS (outf, dregs_lo (src0));
4061
86
      OUTS (outf, " (V)");
4062
86
    }
4063
10.6k
  else if (sop == 0 && sopcde == 4)
4064
44
    {
4065
44
      OUTS (outf, dregs (dst0));
4066
44
      OUTS (outf, " = PACK (");
4067
44
      OUTS (outf, dregs_lo (src1));
4068
44
      OUTS (outf, ", ");
4069
44
      OUTS (outf, dregs_lo (src0));
4070
44
      OUTS (outf, ")");
4071
44
    }
4072
10.6k
  else if (sop == 1 && sopcde == 4)
4073
179
    {
4074
179
      OUTS (outf, dregs (dst0));
4075
179
      OUTS (outf, " = PACK (");
4076
179
      OUTS (outf, dregs_lo (src1));
4077
179
      OUTS (outf, ", ");
4078
179
      OUTS (outf, dregs_hi (src0));
4079
179
      OUTS (outf, ")");
4080
179
    }
4081
10.4k
  else if (sop == 2 && sopcde == 4)
4082
71
    {
4083
71
      OUTS (outf, dregs (dst0));
4084
71
      OUTS (outf, " = PACK (");
4085
71
      OUTS (outf, dregs_hi (src1));
4086
71
      OUTS (outf, ", ");
4087
71
      OUTS (outf, dregs_lo (src0));
4088
71
      OUTS (outf, ")");
4089
71
    }
4090
10.3k
  else if (sop == 3 && sopcde == 4)
4091
852
    {
4092
852
      OUTS (outf, dregs (dst0));
4093
852
      OUTS (outf, " = PACK (");
4094
852
      OUTS (outf, dregs_hi (src1));
4095
852
      OUTS (outf, ", ");
4096
852
      OUTS (outf, dregs_hi (src0));
4097
852
      OUTS (outf, ")");
4098
852
    }
4099
9.51k
  else if (sop == 0 && sopcde == 5)
4100
119
    {
4101
119
      OUTS (outf, dregs_lo (dst0));
4102
119
      OUTS (outf, " = SIGNBITS ");
4103
119
      OUTS (outf, dregs (src1));
4104
119
    }
4105
9.39k
  else if (sop == 1 && sopcde == 5)
4106
212
    {
4107
212
      OUTS (outf, dregs_lo (dst0));
4108
212
      OUTS (outf, " = SIGNBITS ");
4109
212
      OUTS (outf, dregs_lo (src1));
4110
212
    }
4111
9.18k
  else if (sop == 2 && sopcde == 5)
4112
48
    {
4113
48
      OUTS (outf, dregs_lo (dst0));
4114
48
      OUTS (outf, " = SIGNBITS ");
4115
48
      OUTS (outf, dregs_hi (src1));
4116
48
    }
4117
9.13k
  else if (sop == 0 && sopcde == 6)
4118
62
    {
4119
62
      OUTS (outf, dregs_lo (dst0));
4120
62
      OUTS (outf, " = SIGNBITS A0");
4121
62
    }
4122
9.07k
  else if (sop == 1 && sopcde == 6)
4123
10
    {
4124
10
      OUTS (outf, dregs_lo (dst0));
4125
10
      OUTS (outf, " = SIGNBITS A1");
4126
10
    }
4127
9.06k
  else if (sop == 3 && sopcde == 6)
4128
203
    {
4129
203
      OUTS (outf, dregs_lo (dst0));
4130
203
      OUTS (outf, " = ONES ");
4131
203
      OUTS (outf, dregs (src1));
4132
203
    }
4133
8.86k
  else if (sop == 0 && sopcde == 7)
4134
604
    {
4135
604
      OUTS (outf, dregs_lo (dst0));
4136
604
      OUTS (outf, " = EXPADJ (");
4137
604
      OUTS (outf, dregs (src1));
4138
604
      OUTS (outf, ", ");
4139
604
      OUTS (outf, dregs_lo (src0));
4140
604
      OUTS (outf, ")");
4141
604
    }
4142
8.25k
  else if (sop == 1 && sopcde == 7)
4143
449
    {
4144
449
      OUTS (outf, dregs_lo (dst0));
4145
449
      OUTS (outf, " = EXPADJ (");
4146
449
      OUTS (outf, dregs (src1));
4147
449
      OUTS (outf, ", ");
4148
449
      OUTS (outf, dregs_lo (src0));
4149
449
      OUTS (outf, ") (V)");
4150
449
    }
4151
7.80k
  else if (sop == 2 && sopcde == 7)
4152
87
    {
4153
87
      OUTS (outf, dregs_lo (dst0));
4154
87
      OUTS (outf, " = EXPADJ (");
4155
87
      OUTS (outf, dregs_lo (src1));
4156
87
      OUTS (outf, ", ");
4157
87
      OUTS (outf, dregs_lo (src0));
4158
87
      OUTS (outf, ")");
4159
87
    }
4160
7.72k
  else if (sop == 3 && sopcde == 7)
4161
1.30k
    {
4162
1.30k
      OUTS (outf, dregs_lo (dst0));
4163
1.30k
      OUTS (outf, " = EXPADJ (");
4164
1.30k
      OUTS (outf, dregs_hi (src1));
4165
1.30k
      OUTS (outf, ", ");
4166
1.30k
      OUTS (outf, dregs_lo (src0));
4167
1.30k
      OUTS (outf, ")");
4168
1.30k
    }
4169
6.42k
  else if (sop == 0 && sopcde == 8)
4170
223
    {
4171
223
      OUTS (outf, "BITMUX (");
4172
223
      OUTS (outf, dregs (src0));
4173
223
      OUTS (outf, ", ");
4174
223
      OUTS (outf, dregs (src1));
4175
223
      OUTS (outf, ", A0) (ASR)");
4176
223
    }
4177
6.19k
  else if (sop == 1 && sopcde == 8)
4178
187
    {
4179
187
      OUTS (outf, "BITMUX (");
4180
187
      OUTS (outf, dregs (src0));
4181
187
      OUTS (outf, ", ");
4182
187
      OUTS (outf, dregs (src1));
4183
187
      OUTS (outf, ", A0) (ASL)");
4184
187
    }
4185
6.01k
  else if (sop == 0 && sopcde == 9)
4186
221
    {
4187
221
      OUTS (outf, dregs_lo (dst0));
4188
221
      OUTS (outf, " = VIT_MAX (");
4189
221
      OUTS (outf, dregs (src1));
4190
221
      OUTS (outf, ") (ASL)");
4191
221
    }
4192
5.79k
  else if (sop == 1 && sopcde == 9)
4193
308
    {
4194
308
      OUTS (outf, dregs_lo (dst0));
4195
308
      OUTS (outf, " = VIT_MAX (");
4196
308
      OUTS (outf, dregs (src1));
4197
308
      OUTS (outf, ") (ASR)");
4198
308
    }
4199
5.48k
  else if (sop == 2 && sopcde == 9)
4200
386
    {
4201
386
      OUTS (outf, dregs (dst0));
4202
386
      OUTS (outf, " = VIT_MAX (");
4203
386
      OUTS (outf, dregs (src1));
4204
386
      OUTS (outf, ", ");
4205
386
      OUTS (outf, dregs (src0));
4206
386
      OUTS (outf, ") (ASL)");
4207
386
    }
4208
5.09k
  else if (sop == 3 && sopcde == 9)
4209
239
    {
4210
239
      OUTS (outf, dregs (dst0));
4211
239
      OUTS (outf, " = VIT_MAX (");
4212
239
      OUTS (outf, dregs (src1));
4213
239
      OUTS (outf, ", ");
4214
239
      OUTS (outf, dregs (src0));
4215
239
      OUTS (outf, ") (ASR)");
4216
239
    }
4217
4.85k
  else if (sop == 0 && sopcde == 10)
4218
212
    {
4219
212
      OUTS (outf, dregs (dst0));
4220
212
      OUTS (outf, " = EXTRACT (");
4221
212
      OUTS (outf, dregs (src1));
4222
212
      OUTS (outf, ", ");
4223
212
      OUTS (outf, dregs_lo (src0));
4224
212
      OUTS (outf, ") (Z)");
4225
212
    }
4226
4.64k
  else if (sop == 1 && sopcde == 10)
4227
88
    {
4228
88
      OUTS (outf, dregs (dst0));
4229
88
      OUTS (outf, " = EXTRACT (");
4230
88
      OUTS (outf, dregs (src1));
4231
88
      OUTS (outf, ", ");
4232
88
      OUTS (outf, dregs_lo (src0));
4233
88
      OUTS (outf, ") (X)");
4234
88
    }
4235
4.55k
  else if (sop == 2 && sopcde == 10)
4236
293
    {
4237
293
      OUTS (outf, dregs (dst0));
4238
293
      OUTS (outf, " = DEPOSIT (");
4239
293
      OUTS (outf, dregs (src1));
4240
293
      OUTS (outf, ", ");
4241
293
      OUTS (outf, dregs (src0));
4242
293
      OUTS (outf, ")");
4243
293
    }
4244
4.26k
  else if (sop == 3 && sopcde == 10)
4245
548
    {
4246
548
      OUTS (outf, dregs (dst0));
4247
548
      OUTS (outf, " = DEPOSIT (");
4248
548
      OUTS (outf, dregs (src1));
4249
548
      OUTS (outf, ", ");
4250
548
      OUTS (outf, dregs (src0));
4251
548
      OUTS (outf, ") (X)");
4252
548
    }
4253
3.71k
  else if (sop == 0 && sopcde == 11)
4254
140
    {
4255
140
      OUTS (outf, dregs_lo (dst0));
4256
140
      OUTS (outf, " = CC = BXORSHIFT (A0, ");
4257
140
      OUTS (outf, dregs (src0));
4258
140
      OUTS (outf, ")");
4259
140
    }
4260
3.57k
  else if (sop == 1 && sopcde == 11)
4261
24
    {
4262
24
      OUTS (outf, dregs_lo (dst0));
4263
24
      OUTS (outf, " = CC = BXOR (A0, ");
4264
24
      OUTS (outf, dregs (src0));
4265
24
      OUTS (outf, ")");
4266
24
    }
4267
3.55k
  else if (sop == 0 && sopcde == 12)
4268
275
    OUTS (outf, "A0 = BXORSHIFT (A0, A1, CC)");
4269
4270
3.27k
  else if (sop == 1 && sopcde == 12)
4271
597
    {
4272
597
      OUTS (outf, dregs_lo (dst0));
4273
597
      OUTS (outf, " = CC = BXOR (A0, A1, CC)");
4274
597
    }
4275
2.68k
  else if (sop == 0 && sopcde == 13)
4276
33
    {
4277
33
      OUTS (outf, dregs (dst0));
4278
33
      OUTS (outf, " = ALIGN8 (");
4279
33
      OUTS (outf, dregs (src1));
4280
33
      OUTS (outf, ", ");
4281
33
      OUTS (outf, dregs (src0));
4282
33
      OUTS (outf, ")");
4283
33
    }
4284
2.64k
  else if (sop == 1 && sopcde == 13)
4285
272
    {
4286
272
      OUTS (outf, dregs (dst0));
4287
272
      OUTS (outf, " = ALIGN16 (");
4288
272
      OUTS (outf, dregs (src1));
4289
272
      OUTS (outf, ", ");
4290
272
      OUTS (outf, dregs (src0));
4291
272
      OUTS (outf, ")");
4292
272
    }
4293
2.37k
  else if (sop == 2 && sopcde == 13)
4294
20
    {
4295
20
      OUTS (outf, dregs (dst0));
4296
20
      OUTS (outf, " = ALIGN24 (");
4297
20
      OUTS (outf, dregs (src1));
4298
20
      OUTS (outf, ", ");
4299
20
      OUTS (outf, dregs (src0));
4300
20
      OUTS (outf, ")");
4301
20
    }
4302
2.35k
  else
4303
2.35k
    return 0;
4304
4305
14.4k
  return 4;
4306
16.7k
}
4307
4308
static int
4309
decode_dsp32shiftimm_0 (TIword iw0, TIword iw1, disassemble_info *outf)
4310
9.61k
{
4311
  /* dsp32shiftimm
4312
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
4313
     | 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 1 | - | - |.sopcde............|
4314
     |.sop...|.HLs...|.dst0......|.immag.................|.src1......|
4315
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
4316
9.61k
  int src1     = ((iw1 >> DSP32ShiftImm_src1_bits) & DSP32ShiftImm_src1_mask);
4317
9.61k
  int sop      = ((iw1 >> DSP32ShiftImm_sop_bits) & DSP32ShiftImm_sop_mask);
4318
9.61k
  int bit8     = ((iw1 >> 8) & 0x1);
4319
9.61k
  int immag    = ((iw1 >> DSP32ShiftImm_immag_bits) & DSP32ShiftImm_immag_mask);
4320
9.61k
  int newimmag = (-(iw1 >> DSP32ShiftImm_immag_bits) & DSP32ShiftImm_immag_mask);
4321
9.61k
  int dst0     = ((iw1 >> DSP32ShiftImm_dst0_bits) & DSP32ShiftImm_dst0_mask);
4322
9.61k
  int sopcde   = ((iw0 >> (DSP32ShiftImm_sopcde_bits - 16)) & DSP32ShiftImm_sopcde_mask);
4323
9.61k
  int HLs      = ((iw1 >> DSP32ShiftImm_HLs_bits) & DSP32ShiftImm_HLs_mask);
4324
4325
9.61k
  if (sop == 0 && sopcde == 0)
4326
628
    {
4327
628
      OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4328
628
      OUTS (outf, " = ");
4329
628
      OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4330
628
      OUTS (outf, " >>> ");
4331
628
      OUTS (outf, uimm4 (newimmag));
4332
628
    }
4333
8.98k
  else if (sop == 1 && sopcde == 0 && bit8 == 0)
4334
27
    {
4335
27
      OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4336
27
      OUTS (outf, " = ");
4337
27
      OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4338
27
      OUTS (outf, " << ");
4339
27
      OUTS (outf, uimm4 (immag));
4340
27
      OUTS (outf, " (S)");
4341
27
    }
4342
8.95k
  else if (sop == 1 && sopcde == 0 && bit8 == 1)
4343
131
    {
4344
131
      OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4345
131
      OUTS (outf, " = ");
4346
131
      OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4347
131
      OUTS (outf, " >>> ");
4348
131
      OUTS (outf, uimm4 (newimmag));
4349
131
      OUTS (outf, " (S)");
4350
131
    }
4351
8.82k
  else if (sop == 2 && sopcde == 0 && bit8 == 0)
4352
44
    {
4353
44
      OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4354
44
      OUTS (outf, " = ");
4355
44
      OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4356
44
      OUTS (outf, " << ");
4357
44
      OUTS (outf, uimm4 (immag));
4358
44
    }
4359
8.78k
  else if (sop == 2 && sopcde == 0 && bit8 == 1)
4360
131
    {
4361
131
      OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4362
131
      OUTS (outf, " = ");
4363
131
      OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4364
131
      OUTS (outf, " >> ");
4365
131
      OUTS (outf, uimm4 (newimmag));
4366
131
    }
4367
8.65k
  else if (sop == 2 && sopcde == 3 && HLs == 1)
4368
18
    {
4369
18
      OUTS (outf, "A1 = ROT A1 BY ");
4370
18
      OUTS (outf, imm6 (immag));
4371
18
    }
4372
8.63k
  else if (sop == 0 && sopcde == 3 && HLs == 0 && bit8 == 0)
4373
331
    {
4374
331
      OUTS (outf, "A0 = A0 << ");
4375
331
      OUTS (outf, uimm5 (immag));
4376
331
    }
4377
8.30k
  else if (sop == 0 && sopcde == 3 && HLs == 0 && bit8 == 1)
4378
190
    {
4379
190
      OUTS (outf, "A0 = A0 >>> ");
4380
190
      OUTS (outf, uimm5 (newimmag));
4381
190
    }
4382
8.11k
  else if (sop == 0 && sopcde == 3 && HLs == 1 && bit8 == 0)
4383
82
    {
4384
82
      OUTS (outf, "A1 = A1 << ");
4385
82
      OUTS (outf, uimm5 (immag));
4386
82
    }
4387
8.02k
  else if (sop == 0 && sopcde == 3 && HLs == 1 && bit8 == 1)
4388
13
    {
4389
13
      OUTS (outf, "A1 = A1 >>> ");
4390
13
      OUTS (outf, uimm5 (newimmag));
4391
13
    }
4392
8.01k
  else if (sop == 1 && sopcde == 3 && HLs == 0)
4393
4
    {
4394
4
      OUTS (outf, "A0 = A0 >> ");
4395
4
      OUTS (outf, uimm5 (newimmag));
4396
4
    }
4397
8.01k
  else if (sop == 1 && sopcde == 3 && HLs == 1)
4398
11
    {
4399
11
      OUTS (outf, "A1 = A1 >> ");
4400
11
      OUTS (outf, uimm5 (newimmag));
4401
11
    }
4402
8.00k
  else if (sop == 2 && sopcde == 3 && HLs == 0)
4403
322
    {
4404
322
      OUTS (outf, "A0 = ROT A0 BY ");
4405
322
      OUTS (outf, imm6 (immag));
4406
322
    }
4407
7.67k
  else if (sop == 1 && sopcde == 1 && bit8 == 0)
4408
20
    {
4409
20
      OUTS (outf, dregs (dst0));
4410
20
      OUTS (outf, " = ");
4411
20
      OUTS (outf, dregs (src1));
4412
20
      OUTS (outf, " << ");
4413
20
      OUTS (outf, uimm5 (immag));
4414
20
      OUTS (outf, " (V, S)");
4415
20
    }
4416
7.65k
  else if (sop == 1 && sopcde == 1 && bit8 == 1)
4417
13
    {
4418
13
      OUTS (outf, dregs (dst0));
4419
13
      OUTS (outf, " = ");
4420
13
      OUTS (outf, dregs (src1));
4421
13
      OUTS (outf, " >>> ");
4422
13
      OUTS (outf, imm5 (-immag));
4423
13
      OUTS (outf, " (V, S)");
4424
13
    }
4425
7.64k
  else if (sop == 2 && sopcde == 1 && bit8 == 1)
4426
158
    {
4427
158
      OUTS (outf, dregs (dst0));
4428
158
      OUTS (outf, " = ");
4429
158
      OUTS (outf, dregs (src1));
4430
158
      OUTS (outf, " >> ");
4431
158
      OUTS (outf, uimm5 (newimmag));
4432
158
      OUTS (outf, " (V)");
4433
158
    }
4434
7.48k
  else if (sop == 2 && sopcde == 1 && bit8 == 0)
4435
385
    {
4436
385
      OUTS (outf, dregs (dst0));
4437
385
      OUTS (outf, " = ");
4438
385
      OUTS (outf, dregs (src1));
4439
385
      OUTS (outf, " << ");
4440
385
      OUTS (outf, imm5 (immag));
4441
385
      OUTS (outf, " (V)");
4442
385
    }
4443
7.10k
  else if (sop == 0 && sopcde == 1)
4444
296
    {
4445
296
      OUTS (outf, dregs (dst0));
4446
296
      OUTS (outf, " = ");
4447
296
      OUTS (outf, dregs (src1));
4448
296
      OUTS (outf, " >>> ");
4449
296
      OUTS (outf, uimm5 (newimmag));
4450
296
      OUTS (outf, " (V)");
4451
296
    }
4452
6.80k
  else if (sop == 1 && sopcde == 2)
4453
118
    {
4454
118
      OUTS (outf, dregs (dst0));
4455
118
      OUTS (outf, " = ");
4456
118
      OUTS (outf, dregs (src1));
4457
118
      OUTS (outf, " << ");
4458
118
      OUTS (outf, uimm5 (immag));
4459
118
      OUTS (outf, " (S)");
4460
118
    }
4461
6.68k
  else if (sop == 2 && sopcde == 2 && bit8 == 1)
4462
76
    {
4463
76
      OUTS (outf, dregs (dst0));
4464
76
      OUTS (outf, " = ");
4465
76
      OUTS (outf, dregs (src1));
4466
76
      OUTS (outf, " >> ");
4467
76
      OUTS (outf, uimm5 (newimmag));
4468
76
    }
4469
6.61k
  else if (sop == 2 && sopcde == 2 && bit8 == 0)
4470
168
    {
4471
168
      OUTS (outf, dregs (dst0));
4472
168
      OUTS (outf, " = ");
4473
168
      OUTS (outf, dregs (src1));
4474
168
      OUTS (outf, " << ");
4475
168
      OUTS (outf, uimm5 (immag));
4476
168
    }
4477
6.44k
  else if (sop == 3 && sopcde == 2)
4478
1.50k
    {
4479
1.50k
      OUTS (outf, dregs (dst0));
4480
1.50k
      OUTS (outf, " = ROT ");
4481
1.50k
      OUTS (outf, dregs (src1));
4482
1.50k
      OUTS (outf, " BY ");
4483
1.50k
      OUTS (outf, imm6 (immag));
4484
1.50k
    }
4485
4.94k
  else if (sop == 0 && sopcde == 2)
4486
70
    {
4487
70
      OUTS (outf, dregs (dst0));
4488
70
      OUTS (outf, " = ");
4489
70
      OUTS (outf, dregs (src1));
4490
70
      OUTS (outf, " >>> ");
4491
70
      OUTS (outf, uimm5 (newimmag));
4492
70
    }
4493
4.87k
  else
4494
4.87k
    return 0;
4495
4496
4.74k
  return 4;
4497
9.61k
}
4498
4499
static int
4500
decode_pseudoDEBUG_0 (TIword iw0, disassemble_info *outf)
4501
11.1k
{
4502
11.1k
  struct private *priv = outf->private_data;
4503
  /* pseudoDEBUG
4504
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
4505
     | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 |.fn....|.grp.......|.reg.......|
4506
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
4507
11.1k
  int fn  = ((iw0 >> PseudoDbg_fn_bits) & PseudoDbg_fn_mask);
4508
11.1k
  int grp = ((iw0 >> PseudoDbg_grp_bits) & PseudoDbg_grp_mask);
4509
11.1k
  int reg = ((iw0 >> PseudoDbg_reg_bits) & PseudoDbg_reg_mask);
4510
4511
11.1k
  if (priv->parallel)
4512
949
    return 0;
4513
4514
10.2k
  if (reg == 0 && fn == 3)
4515
3.38k
    OUTS (outf, "DBG A0");
4516
4517
6.86k
  else if (reg == 1 && fn == 3)
4518
80
    OUTS (outf, "DBG A1");
4519
4520
6.78k
  else if (reg == 3 && fn == 3)
4521
60
    OUTS (outf, "ABORT");
4522
4523
6.72k
  else if (reg == 4 && fn == 3)
4524
899
    OUTS (outf, "HLT");
4525
4526
5.82k
  else if (reg == 5 && fn == 3)
4527
191
    OUTS (outf, "DBGHALT");
4528
4529
5.63k
  else if (reg == 6 && fn == 3)
4530
287
    {
4531
287
      OUTS (outf, "DBGCMPLX (");
4532
287
      OUTS (outf, dregs (grp));
4533
287
      OUTS (outf, ")");
4534
287
    }
4535
5.34k
  else if (reg == 7 && fn == 3)
4536
732
    OUTS (outf, "DBG");
4537
4538
4.61k
  else if (grp == 0 && fn == 2)
4539
245
    {
4540
245
      OUTS (outf, "OUTC ");
4541
245
      OUTS (outf, dregs (reg));
4542
245
    }
4543
4.36k
  else if (fn == 0)
4544
2.55k
    {
4545
2.55k
      OUTS (outf, "DBG ");
4546
2.55k
      OUTS (outf, allregs (reg, grp));
4547
2.55k
    }
4548
1.81k
  else if (fn == 1)
4549
816
    {
4550
816
      OUTS (outf, "PRNT ");
4551
816
      OUTS (outf, allregs (reg, grp));
4552
816
    }
4553
994
  else
4554
994
    return 0;
4555
4556
9.25k
  return 2;
4557
10.2k
}
4558
4559
static int
4560
decode_pseudoOChar_0 (TIword iw0, disassemble_info *outf)
4561
6.74k
{
4562
6.74k
  struct private *priv = outf->private_data;
4563
  /* psedoOChar
4564
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
4565
     | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |.ch............................|
4566
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
4567
6.74k
  int ch = ((iw0 >> PseudoChr_ch_bits) & PseudoChr_ch_mask);
4568
4569
6.74k
  if (priv->parallel)
4570
201
    return 0;
4571
4572
6.54k
  OUTS (outf, "OUTC ");
4573
6.54k
  OUTS (outf, uimm8 (ch));
4574
4575
6.54k
  return 2;
4576
6.74k
}
4577
4578
static int
4579
decode_pseudodbg_assert_0 (TIword iw0, TIword iw1, disassemble_info *outf)
4580
5.24k
{
4581
5.24k
  struct private *priv = outf->private_data;
4582
  /* pseudodbg_assert
4583
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
4584
     | 1 | 1 | 1 | 1 | 0 | - | - | - | dbgop |.grp.......|.regtest...|
4585
     |.expected......................................................|
4586
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
4587
5.24k
  int expected = ((iw1 >> PseudoDbg_Assert_expected_bits) & PseudoDbg_Assert_expected_mask);
4588
5.24k
  int dbgop    = ((iw0 >> (PseudoDbg_Assert_dbgop_bits - 16)) & PseudoDbg_Assert_dbgop_mask);
4589
5.24k
  int grp      = ((iw0 >> (PseudoDbg_Assert_grp_bits - 16)) & PseudoDbg_Assert_grp_mask);
4590
5.24k
  int regtest  = ((iw0 >> (PseudoDbg_Assert_regtest_bits - 16)) & PseudoDbg_Assert_regtest_mask);
4591
4592
5.24k
  if (priv->parallel)
4593
203
    return 0;
4594
4595
5.03k
  if (dbgop == 0)
4596
1.78k
    {
4597
1.78k
      OUTS (outf, "DBGA (");
4598
1.78k
      OUTS (outf, regs_lo (regtest, grp));
4599
1.78k
      OUTS (outf, ", ");
4600
1.78k
      OUTS (outf, uimm16 (expected));
4601
1.78k
      OUTS (outf, ")");
4602
1.78k
    }
4603
3.25k
  else if (dbgop == 1)
4604
909
    {
4605
909
      OUTS (outf, "DBGA (");
4606
909
      OUTS (outf, regs_hi (regtest, grp));
4607
909
      OUTS (outf, ", ");
4608
909
      OUTS (outf, uimm16 (expected));
4609
909
      OUTS (outf, ")");
4610
909
    }
4611
2.34k
  else if (dbgop == 2)
4612
400
    {
4613
400
      OUTS (outf, "DBGAL (");
4614
400
      OUTS (outf, allregs (regtest, grp));
4615
400
      OUTS (outf, ", ");
4616
400
      OUTS (outf, uimm16 (expected));
4617
400
      OUTS (outf, ")");
4618
400
    }
4619
1.94k
  else if (dbgop == 3)
4620
1.94k
    {
4621
1.94k
      OUTS (outf, "DBGAH (");
4622
1.94k
      OUTS (outf, allregs (regtest, grp));
4623
1.94k
      OUTS (outf, ", ");
4624
1.94k
      OUTS (outf, uimm16 (expected));
4625
1.94k
      OUTS (outf, ")");
4626
1.94k
    }
4627
0
  else
4628
0
    return 0;
4629
5.03k
  return 4;
4630
5.03k
}
4631
4632
static int
4633
ifetch (bfd_vma pc, disassemble_info *outf, TIword *iw)
4634
2.13M
{
4635
2.13M
  bfd_byte buf[2];
4636
2.13M
  int status;
4637
4638
2.13M
  status = (*outf->read_memory_func) (pc, buf, 2, outf);
4639
2.13M
  if (status != 0)
4640
551
    {
4641
551
      (*outf->memory_error_func) (status, pc, outf);
4642
551
      return -1;
4643
551
    }
4644
4645
2.13M
  *iw = bfd_getl16 (buf);
4646
2.13M
  return 0;
4647
2.13M
}
4648
4649
static int
4650
_print_insn_bfin (bfd_vma pc, disassemble_info *outf)
4651
1.69M
{
4652
1.69M
  struct private *priv = outf->private_data;
4653
1.69M
  TIword iw0;
4654
1.69M
  TIword iw1;
4655
1.69M
  int rv = 0;
4656
4657
  /* The PC must be 16-bit aligned.  */
4658
1.69M
  if (pc & 1)
4659
0
    {
4660
0
      OUTS (outf, "ILLEGAL (UNALIGNED)");
4661
      /* For people dumping data, just re-align the return value.  */
4662
0
      return 1;
4663
0
    }
4664
4665
1.69M
  if (ifetch (pc, outf, &iw0))
4666
473
    return -1;
4667
1.69M
  priv->iw0 = iw0;
4668
4669
1.69M
  if (((iw0 & 0xc000) == 0xc000) && ((iw0 & 0xff00) != 0xf800))
4670
432k
    {
4671
      /* 32-bit insn.  */
4672
432k
      if (ifetch (pc + 2, outf, &iw1))
4673
78
  return -1;
4674
432k
    }
4675
1.26M
  else
4676
    /* 16-bit insn.  */
4677
1.26M
    iw1 = 0;
4678
4679
1.69M
  if ((iw0 & 0xf7ff) == 0xc003 && iw1 == 0x1800)
4680
40
    {
4681
40
      if (priv->parallel)
4682
20
  {
4683
20
    OUTS (outf, "ILLEGAL");
4684
20
    return 0;
4685
20
  }
4686
20
      OUTS (outf, "MNOP");
4687
20
      return 4;
4688
40
    }
4689
1.69M
  else if ((iw0 & 0xff00) == 0x0000)
4690
295k
    rv = decode_ProgCtrl_0 (iw0, outf);
4691
1.40M
  else if ((iw0 & 0xffc0) == 0x0240)
4692
1.63k
    rv = decode_CaCTRL_0 (iw0, outf);
4693
1.40M
  else if ((iw0 & 0xff80) == 0x0100)
4694
11.1k
    rv = decode_PushPopReg_0 (iw0, outf);
4695
1.39M
  else if ((iw0 & 0xfe00) == 0x0400)
4696
24.3k
    rv = decode_PushPopMultiple_0 (iw0, outf);
4697
1.36M
  else if ((iw0 & 0xfe00) == 0x0600)
4698
27.7k
    rv = decode_ccMV_0 (iw0, outf);
4699
1.33M
  else if ((iw0 & 0xf800) == 0x0800)
4700
57.3k
    rv = decode_CCflag_0 (iw0, outf);
4701
1.28M
  else if ((iw0 & 0xffe0) == 0x0200)
4702
4.09k
    rv = decode_CC2dreg_0 (iw0, outf);
4703
1.27M
  else if ((iw0 & 0xff00) == 0x0300)
4704
13.0k
    rv = decode_CC2stat_0 (iw0, outf);
4705
1.26M
  else if ((iw0 & 0xf000) == 0x1000)
4706
66.6k
    rv = decode_BRCC_0 (iw0, pc, outf);
4707
1.19M
  else if ((iw0 & 0xf000) == 0x2000)
4708
90.4k
    rv = decode_UJUMP_0 (iw0, pc, outf);
4709
1.10M
  else if ((iw0 & 0xf000) == 0x3000)
4710
102k
    rv = decode_REGMV_0 (iw0, outf);
4711
1.00M
  else if ((iw0 & 0xfc00) == 0x4000)
4712
34.0k
    rv = decode_ALU2op_0 (iw0, outf);
4713
970k
  else if ((iw0 & 0xfe00) == 0x4400)
4714
11.6k
    rv = decode_PTR2op_0 (iw0, outf);
4715
958k
  else if ((iw0 & 0xf800) == 0x4800)
4716
34.1k
    rv = decode_LOGI2op_0 (iw0, outf);
4717
924k
  else if ((iw0 & 0xf000) == 0x5000)
4718
49.8k
    rv = decode_COMP3op_0 (iw0, outf);
4719
874k
  else if ((iw0 & 0xf800) == 0x6000)
4720
63.9k
    rv = decode_COMPI2opD_0 (iw0, outf);
4721
811k
  else if ((iw0 & 0xf800) == 0x6800)
4722
49.5k
    rv = decode_COMPI2opP_0 (iw0, outf);
4723
761k
  else if ((iw0 & 0xf000) == 0x8000)
4724
58.4k
    rv = decode_LDSTpmod_0 (iw0, outf);
4725
702k
  else if ((iw0 & 0xff60) == 0x9e60)
4726
829
    rv = decode_dagMODim_0 (iw0, outf);
4727
702k
  else if ((iw0 & 0xfff0) == 0x9f60)
4728
1.27k
    rv = decode_dagMODik_0 (iw0, outf);
4729
700k
  else if ((iw0 & 0xfc00) == 0x9c00)
4730
13.7k
    rv = decode_dspLDST_0 (iw0, outf);
4731
687k
  else if ((iw0 & 0xf000) == 0x9000)
4732
45.1k
    rv = decode_LDST_0 (iw0, outf);
4733
641k
  else if ((iw0 & 0xfc00) == 0xb800)
4734
13.8k
    rv = decode_LDSTiiFP_0 (iw0, outf);
4735
628k
  else if ((iw0 & 0xe000) == 0xA000)
4736
87.3k
    rv = decode_LDSTii_0 (iw0, outf);
4737
540k
  else if ((iw0 & 0xff80) == 0xe080 && (iw1 & 0x0C00) == 0x0000)
4738
3.27k
    rv = decode_LoopSetup_0 (iw0, iw1, pc, outf);
4739
537k
  else if ((iw0 & 0xff00) == 0xe100 && (iw1 & 0x0000) == 0x0000)
4740
7.84k
    rv = decode_LDIMMhalf_0 (iw0, iw1, outf);
4741
529k
  else if ((iw0 & 0xfe00) == 0xe200 && (iw1 & 0x0000) == 0x0000)
4742
6.34k
    rv = decode_CALLa_0 (iw0, iw1, pc, outf);
4743
523k
  else if ((iw0 & 0xfc00) == 0xe400 && (iw1 & 0x0000) == 0x0000)
4744
16.6k
    rv = decode_LDSTidxI_0 (iw0, iw1, outf);
4745
506k
  else if ((iw0 & 0xfffe) == 0xe800 && (iw1 & 0x0000) == 0x0000)
4746
363
    rv = decode_linkage_0 (iw0, iw1, outf);
4747
506k
  else if ((iw0 & 0xf600) == 0xc000 && (iw1 & 0x0000) == 0x0000)
4748
20.4k
    rv = decode_dsp32mac_0 (iw0, iw1, outf);
4749
485k
  else if ((iw0 & 0xf600) == 0xc200 && (iw1 & 0x0000) == 0x0000)
4750
14.0k
    rv = decode_dsp32mult_0 (iw0, iw1, outf);
4751
471k
  else if ((iw0 & 0xf7c0) == 0xc400 && (iw1 & 0x0000) == 0x0000)
4752
32.1k
    rv = decode_dsp32alu_0 (iw0, iw1, outf);
4753
439k
  else if ((iw0 & 0xf780) == 0xc600 && (iw1 & 0x01c0) == 0x0000)
4754
16.7k
    rv = decode_dsp32shift_0 (iw0, iw1, outf);
4755
422k
  else if ((iw0 & 0xf780) == 0xc680 && (iw1 & 0x0000) == 0x0000)
4756
9.61k
    rv = decode_dsp32shiftimm_0 (iw0, iw1, outf);
4757
413k
  else if ((iw0 & 0xff00) == 0xf800)
4758
11.1k
    rv = decode_pseudoDEBUG_0 (iw0, outf);
4759
401k
  else if ((iw0 & 0xFF00) == 0xF900)
4760
6.74k
    rv = decode_pseudoOChar_0 (iw0, outf);
4761
395k
  else if ((iw0 & 0xFF00) == 0xf000 && (iw1 & 0x0000) == 0x0000)
4762
5.24k
    rv = decode_pseudodbg_assert_0 (iw0, iw1, outf);
4763
4764
1.69M
  if (rv == 0)
4765
637k
    OUTS (outf, "ILLEGAL");
4766
4767
1.69M
  return rv;
4768
1.69M
}
4769
4770
int
4771
print_insn_bfin (bfd_vma pc, disassemble_info *outf)
4772
1.62M
{
4773
1.62M
  struct private priv;
4774
1.62M
  int count;
4775
4776
1.62M
  priv.parallel = false;
4777
1.62M
  priv.comment = false;
4778
1.62M
  outf->private_data = &priv;
4779
4780
1.62M
  count = _print_insn_bfin (pc, outf);
4781
1.62M
  if (count == -1)
4782
537
    return -1;
4783
4784
  /* Proper display of multiple issue instructions.  */
4785
4786
1.61M
  if (count == 4 && (priv.iw0 & 0xc000) == 0xc000 && (priv.iw0 & BIT_MULTI_INS)
4787
1.61M
      && ((priv.iw0 & 0xe800) != 0xe800 /* Not Linkage.  */ ))
4788
39.7k
    {
4789
39.7k
      bool legal = true;
4790
39.7k
      int len;
4791
4792
39.7k
      priv.parallel = true;
4793
39.7k
      OUTS (outf, " || ");
4794
39.7k
      len = _print_insn_bfin (pc + 4, outf);
4795
39.7k
      if (len == -1)
4796
4
  return -1;
4797
39.7k
      OUTS (outf, " || ");
4798
39.7k
      if (len != 2)
4799
31.8k
  legal = false;
4800
39.7k
      len = _print_insn_bfin (pc + 6, outf);
4801
39.7k
      if (len == -1)
4802
10
  return -1;
4803
39.7k
      if (len != 2)
4804
30.4k
  legal = false;
4805
4806
39.7k
      if (legal)
4807
3.15k
  count = 8;
4808
36.5k
      else
4809
36.5k
  {
4810
36.5k
    OUTS (outf, ";\t\t/* ILLEGAL PARALLEL INSTRUCTION */");
4811
36.5k
    priv.comment = true;
4812
36.5k
    count = 0;
4813
36.5k
  }
4814
39.7k
    }
4815
4816
1.61M
  if (!priv.comment)
4817
1.45M
    OUTS (outf, ";");
4818
4819
1.61M
  if (count == 0)
4820
624k
    return 2;
4821
4822
995k
  return count;
4823
1.61M
}