Coverage Report

Created: 2024-05-21 06:29

/src/binutils-gdb/opcodes/d10v-dis.c
Line
Count
Source (jump to first uncovered line)
1
/* Disassemble D10V instructions.
2
   Copyright (C) 1996-2024 Free Software Foundation, Inc.
3
4
   This file is part of the GNU opcodes library.
5
6
   This library is free software; you can redistribute it and/or modify
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   it under the terms of the GNU General Public License as published by
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   the Free Software Foundation; either version 3, or (at your option)
9
   any later version.
10
11
   It is distributed in the hope that it will be useful, but WITHOUT
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   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
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   License for more details.
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16
   You should have received a copy of the GNU General Public License
17
   along with this program; if not, write to the Free Software
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   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
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   MA 02110-1301, USA.  */
20
21
#include "sysdep.h"
22
#include <stdio.h>
23
#include "opcode/d10v.h"
24
#include "disassemble.h"
25
26
/* The PC wraps at 18 bits, except for the segment number,
27
   so use this mask to keep the parts we want.  */
28
2.22k
#define PC_MASK 0x0303FFFF
29
30
static void
31
print_operand (struct d10v_operand *oper,
32
         unsigned long insn,
33
         struct d10v_opcode *op,
34
         bfd_vma memaddr,
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         struct disassemble_info *info)
36
113k
{
37
113k
  int num, shift;
38
39
113k
  if (oper->flags == OPERAND_ATMINUS)
40
63
    {
41
63
      (*info->fprintf_func) (info->stream, "@-");
42
63
      return;
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63
    }
44
113k
  if (oper->flags == OPERAND_MINUS)
45
1.34k
    {
46
1.34k
      (*info->fprintf_func) (info->stream, "-");
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1.34k
      return;
48
1.34k
    }
49
111k
  if (oper->flags == OPERAND_PLUS)
50
1.23k
    {
51
1.23k
      (*info->fprintf_func) (info->stream, "+");
52
1.23k
      return;
53
1.23k
    }
54
110k
  if (oper->flags == OPERAND_ATSIGN)
55
5.83k
    {
56
5.83k
      (*info->fprintf_func) (info->stream, "@");
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5.83k
      return;
58
5.83k
    }
59
104k
  if (oper->flags == OPERAND_ATPAR)
60
1.21k
    {
61
1.21k
      (*info->fprintf_func) (info->stream, "@(");
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1.21k
      return;
63
1.21k
    }
64
65
103k
  shift = oper->shift;
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67
  /* The LONG_L format shifts registers over by 15.  */
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103k
  if (op->format == LONG_L && (oper->flags & OPERAND_REG))
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3.73k
    shift += 15;
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71
103k
  num = (insn >> shift) & (0x7FFFFFFF >> (31 - oper->bits));
72
73
103k
  if (oper->flags & OPERAND_REG)
74
90.6k
    {
75
90.6k
      int i;
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90.6k
      int match = 0;
77
78
90.6k
      num += (oper->flags
79
90.6k
        & (OPERAND_GPR | OPERAND_FFLAG | OPERAND_CFLAG | OPERAND_CONTROL));
80
90.6k
      if (oper->flags & (OPERAND_ACC0 | OPERAND_ACC1))
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10.1k
  num += num ? OPERAND_ACC1 : OPERAND_ACC0;
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3.31M
      for (i = 0; i < d10v_reg_name_cnt (); i++)
83
3.31M
  {
84
3.31M
    if (num == (d10v_predefined_registers[i].value & ~ OPERAND_SP))
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90.6k
      {
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90.6k
        if (d10v_predefined_registers[i].pname)
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8.06k
    (*info->fprintf_func) (info->stream, "%s",
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8.06k
               d10v_predefined_registers[i].pname);
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82.5k
        else
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82.5k
    (*info->fprintf_func) (info->stream, "%s",
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82.5k
               d10v_predefined_registers[i].name);
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90.6k
        match = 1;
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90.6k
        break;
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90.6k
      }
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3.31M
  }
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90.6k
      if (match == 0)
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0
  {
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    /* This would only get executed if a register was not in the
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       register table.  */
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0
    if (oper->flags & (OPERAND_ACC0 | OPERAND_ACC1))
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0
      (*info->fprintf_func) (info->stream, "a");
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0
    else if (oper->flags & OPERAND_CONTROL)
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0
      (*info->fprintf_func) (info->stream, "cr");
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0
    else if (oper->flags & OPERAND_REG)
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0
      (*info->fprintf_func) (info->stream, "r");
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0
    (*info->fprintf_func) (info->stream, "%d", num & REGISTER_MASK);
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0
  }
108
90.6k
    }
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13.0k
  else
110
13.0k
    {
111
      /* Addresses are right-shifted by 2.  */
112
13.0k
      if (oper->flags & OPERAND_ADDR)
113
2.22k
  {
114
2.22k
    long max;
115
2.22k
    int neg = 0;
116
117
2.22k
    max = (1 << (oper->bits - 1));
118
2.22k
    if (num & max)
119
1.03k
      {
120
1.03k
        num = -num & ((1 << oper->bits) - 1);
121
1.03k
        neg = 1;
122
1.03k
      }
123
2.22k
    num = num << 2;
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2.22k
    if (info->flags & INSN_HAS_RELOC)
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0
      (*info->print_address_func) (num & PC_MASK, info);
126
2.22k
    else
127
2.22k
      {
128
2.22k
        if (neg)
129
1.03k
    (*info->print_address_func) ((memaddr - num) & PC_MASK, info);
130
1.18k
        else
131
1.18k
    (*info->print_address_func) ((memaddr + num) & PC_MASK, info);
132
2.22k
      }
133
2.22k
  }
134
10.8k
      else
135
10.8k
  {
136
10.8k
    if (oper->flags & OPERAND_SIGNED)
137
4.15k
      {
138
4.15k
        int max = (1 << (oper->bits - 1));
139
4.15k
        if (num & max)
140
1.73k
    {
141
1.73k
      num = -num & ((1 << oper->bits) - 1);
142
1.73k
      (*info->fprintf_func) (info->stream, "-");
143
1.73k
    }
144
4.15k
      }
145
10.8k
    (*info->fprintf_func) (info->stream, "0x%x", num);
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10.8k
  }
147
13.0k
    }
148
103k
}
149
150
static void
151
dis_long (unsigned long insn,
152
    bfd_vma memaddr,
153
    struct disassemble_info *info)
154
11.1k
{
155
11.1k
  int i;
156
11.1k
  struct d10v_opcode *op = (struct d10v_opcode *) d10v_opcodes;
157
11.1k
  struct d10v_operand *oper;
158
11.1k
  int need_paren = 0;
159
11.1k
  int match = 0;
160
161
1.76M
  while (op->name)
162
1.75M
    {
163
1.75M
      if ((op->format & LONG_OPCODE)
164
1.75M
    && ((op->mask & insn) == (unsigned long) op->opcode))
165
2.12k
  {
166
2.12k
    match = 1;
167
2.12k
    (*info->fprintf_func) (info->stream, "%s\t", op->name);
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169
9.40k
    for (i = 0; op->operands[i]; i++)
170
7.28k
      {
171
7.28k
        oper = (struct d10v_operand *) &d10v_operands[op->operands[i]];
172
7.28k
        if (oper->flags == OPERAND_ATPAR)
173
1.21k
    need_paren = 1;
174
7.28k
        print_operand (oper, insn, op, memaddr, info);
175
7.28k
        if (op->operands[i + 1] && oper->bits
176
7.28k
      && d10v_operands[op->operands[i + 1]].flags != OPERAND_PLUS
177
7.28k
      && d10v_operands[op->operands[i + 1]].flags != OPERAND_MINUS)
178
3.90k
    (*info->fprintf_func) (info->stream, ", ");
179
7.28k
      }
180
2.12k
    break;
181
2.12k
  }
182
1.75M
      op++;
183
1.75M
    }
184
185
11.1k
  if (!match)
186
9.04k
    (*info->fprintf_func) (info->stream, ".long\t0x%08lx", insn);
187
188
11.1k
  if (need_paren)
189
1.21k
    (*info->fprintf_func) (info->stream, ")");
190
11.1k
}
191
192
static void
193
dis_2_short (unsigned long insn,
194
       bfd_vma memaddr,
195
       struct disassemble_info *info,
196
       int order)
197
35.7k
{
198
35.7k
  int i, j;
199
35.7k
  unsigned int ins[2];
200
35.7k
  struct d10v_opcode *op;
201
35.7k
  int match, num_match = 0;
202
35.7k
  struct d10v_operand *oper;
203
35.7k
  int need_paren = 0;
204
205
35.7k
  ins[0] = (insn & 0x3FFFFFFF) >> 15;
206
35.7k
  ins[1] = insn & 0x00007FFF;
207
208
107k
  for (j = 0; j < 2; j++)
209
71.5k
    {
210
71.5k
      op = (struct d10v_opcode *) d10v_opcodes;
211
71.5k
      match = 0;
212
9.08M
      while (op->name)
213
9.05M
  {
214
9.05M
    if ((op->format & SHORT_OPCODE)
215
9.05M
        && ((((unsigned int) op->mask) & ins[j])
216
6.59M
      == (unsigned int) op->opcode))
217
45.6k
      {
218
45.6k
        (*info->fprintf_func) (info->stream, "%s\t", op->name);
219
151k
        for (i = 0; op->operands[i]; i++)
220
106k
    {
221
106k
      oper = (struct d10v_operand *) &d10v_operands[op->operands[i]];
222
106k
      if (oper->flags == OPERAND_ATPAR)
223
0
        need_paren = 1;
224
106k
      print_operand (oper, ins[j], op, memaddr, info);
225
106k
      if (op->operands[i + 1] && oper->bits
226
106k
          && d10v_operands[op->operands[i + 1]].flags != OPERAND_PLUS
227
106k
          && d10v_operands[op->operands[i + 1]].flags != OPERAND_MINUS)
228
52.0k
        (*info->fprintf_func) (info->stream, ", ");
229
106k
    }
230
45.6k
        match = 1;
231
45.6k
        num_match++;
232
45.6k
        break;
233
45.6k
      }
234
9.01M
    op++;
235
9.01M
  }
236
71.5k
      if (!match)
237
25.8k
  (*info->fprintf_func) (info->stream, "unknown");
238
239
71.5k
      switch (order)
240
71.5k
  {
241
10.8k
  case 0:
242
10.8k
    (*info->fprintf_func) (info->stream, "\t->\t");
243
10.8k
    order = -1;
244
10.8k
    break;
245
9.36k
  case 1:
246
9.36k
    (*info->fprintf_func) (info->stream, "\t<-\t");
247
9.36k
    order = -1;
248
9.36k
    break;
249
15.5k
  case 2:
250
15.5k
    (*info->fprintf_func) (info->stream, "\t||\t");
251
15.5k
    order = -1;
252
15.5k
    break;
253
35.7k
  default:
254
35.7k
    break;
255
71.5k
  }
256
71.5k
    }
257
258
35.7k
  if (num_match == 0)
259
5.22k
    (*info->fprintf_func) (info->stream, ".long\t0x%08lx", insn);
260
261
35.7k
  if (need_paren)
262
0
    (*info->fprintf_func) (info->stream, ")");
263
35.7k
}
264
265
int
266
print_insn_d10v (bfd_vma memaddr, struct disassemble_info *info)
267
47.0k
{
268
47.0k
  int status;
269
47.0k
  bfd_byte buffer[4];
270
47.0k
  unsigned long insn;
271
272
47.0k
  status = (*info->read_memory_func) (memaddr, buffer, 4, info);
273
47.0k
  if (status != 0)
274
82
    {
275
82
      (*info->memory_error_func) (status, memaddr, info);
276
82
      return -1;
277
82
    }
278
46.9k
  insn = bfd_getb32 (buffer);
279
280
46.9k
  status = insn & FM11;
281
46.9k
  switch (status)
282
46.9k
    {
283
15.5k
    case 0:
284
15.5k
      dis_2_short (insn, memaddr, info, 2);
285
15.5k
      break;
286
10.8k
    case FM01:
287
10.8k
      dis_2_short (insn, memaddr, info, 0);
288
10.8k
      break;
289
9.36k
    case FM10:
290
9.36k
      dis_2_short (insn, memaddr, info, 1);
291
9.36k
      break;
292
11.1k
    case FM11:
293
11.1k
      dis_long (insn, memaddr, info);
294
11.1k
      break;
295
46.9k
    }
296
46.9k
  return 4;
297
46.9k
}