Coverage Report

Created: 2024-05-21 06:29

/src/binutils-gdb/opcodes/frv-dis.c
Line
Count
Source (jump to first uncovered line)
1
/* DO NOT EDIT!  -*- buffer-read-only: t -*- vi:set ro:  */
2
/* Disassembler interface for targets using CGEN. -*- C -*-
3
   CGEN: Cpu tools GENerator
4
5
   THIS FILE IS MACHINE GENERATED WITH CGEN.
6
   - the resultant file is machine generated, cgen-dis.in isn't
7
8
   Copyright (C) 1996-2024 Free Software Foundation, Inc.
9
10
   This file is part of libopcodes.
11
12
   This library is free software; you can redistribute it and/or modify
13
   it under the terms of the GNU General Public License as published by
14
   the Free Software Foundation; either version 3, or (at your option)
15
   any later version.
16
17
   It is distributed in the hope that it will be useful, but WITHOUT
18
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
19
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
20
   License for more details.
21
22
   You should have received a copy of the GNU General Public License
23
   along with this program; if not, write to the Free Software Foundation, Inc.,
24
   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
25
26
/* ??? Eventually more and more of this stuff can go to cpu-independent files.
27
   Keep that in mind.  */
28
29
#include "sysdep.h"
30
#include <stdio.h>
31
#include "ansidecl.h"
32
#include "disassemble.h"
33
#include "bfd.h"
34
#include "symcat.h"
35
#include "libiberty.h"
36
#include "frv-desc.h"
37
#include "frv-opc.h"
38
#include "opintl.h"
39
40
/* Default text to print if an instruction isn't recognized.  */
41
16.5k
#define UNKNOWN_INSN_MSG _("*unknown*")
42
43
static void print_normal
44
  (CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int);
45
static void print_address
46
  (CGEN_CPU_DESC, void *, bfd_vma, unsigned int, bfd_vma, int) ATTRIBUTE_UNUSED;
47
static void print_keyword
48
  (CGEN_CPU_DESC, void *, CGEN_KEYWORD *, long, unsigned int) ATTRIBUTE_UNUSED;
49
static void print_insn_normal
50
  (CGEN_CPU_DESC, void *, const CGEN_INSN *, CGEN_FIELDS *, bfd_vma, int);
51
static int print_insn
52
  (CGEN_CPU_DESC, bfd_vma,  disassemble_info *, bfd_byte *, unsigned);
53
static int default_print_insn
54
  (CGEN_CPU_DESC, bfd_vma, disassemble_info *) ATTRIBUTE_UNUSED;
55
static int read_insn
56
  (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, int, CGEN_EXTRACT_INFO *,
57
   unsigned long *);
58

59
/* -- disassembler routines inserted here.  */
60
61
/* -- dis.c */
62
static void
63
print_at (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
64
    void * dis_info,
65
    long reloc_ann ATTRIBUTE_UNUSED,
66
    long value ATTRIBUTE_UNUSED,
67
    bfd_vma pc ATTRIBUTE_UNUSED,
68
    int length ATTRIBUTE_UNUSED)
69
91
{
70
91
  disassemble_info *info = (disassemble_info *) dis_info;
71
72
91
  (*info->fprintf_func) (info->stream, "@");
73
91
}
74
75
static void
76
print_spr (CGEN_CPU_DESC cd,
77
     void * dis_info,
78
     CGEN_KEYWORD *names,
79
     long regno,
80
     unsigned int attrs)
81
17
{
82
  /* Use the register index format for any unnamed registers.  */
83
17
  if (cgen_keyword_lookup_value (names, regno) == NULL)
84
13
    {
85
13
      disassemble_info *info = (disassemble_info *) dis_info;
86
13
      (*info->fprintf_func) (info->stream, "spr[%ld]", regno);
87
13
    }
88
4
  else
89
4
    print_keyword (cd, dis_info, names, regno, attrs);
90
17
}
91
92
static void
93
print_hi (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
94
    void * dis_info,
95
    long value,
96
    unsigned int attrs ATTRIBUTE_UNUSED,
97
    bfd_vma pc ATTRIBUTE_UNUSED,
98
    int length ATTRIBUTE_UNUSED)
99
634
{
100
634
  disassemble_info *info = (disassemble_info *) dis_info;
101
102
634
  (*info->fprintf_func) (info->stream, value ? "0x%lx" : "hi(0x%lx)", value);
103
634
}
104
105
static void
106
print_lo (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
107
    void * dis_info,
108
    long value,
109
    unsigned int attrs ATTRIBUTE_UNUSED,
110
    bfd_vma pc ATTRIBUTE_UNUSED,
111
    int length ATTRIBUTE_UNUSED)
112
950
{
113
950
  disassemble_info *info = (disassemble_info *) dis_info;
114
950
  if (value)
115
799
    (*info->fprintf_func) (info->stream, "0x%lx", value);
116
151
  else
117
151
    (*info->fprintf_func) (info->stream, "lo(0x%lx)", value);
118
950
}
119
120
/* -- */
121
122
void frv_cgen_print_operand
123
  (CGEN_CPU_DESC, int, void *, CGEN_FIELDS *, void const *, bfd_vma, int);
124
125
/* Main entry point for printing operands.
126
   XINFO is a `void *' and not a `disassemble_info *' to not put a requirement
127
   of dis-asm.h on cgen.h.
128
129
   This function is basically just a big switch statement.  Earlier versions
130
   used tables to look up the function to use, but
131
   - if the table contains both assembler and disassembler functions then
132
     the disassembler contains much of the assembler and vice-versa,
133
   - there's a lot of inlining possibilities as things grow,
134
   - using a switch statement avoids the function call overhead.
135
136
   This function could be moved into `print_insn_normal', but keeping it
137
   separate makes clear the interface between `print_insn_normal' and each of
138
   the handlers.  */
139
140
void
141
frv_cgen_print_operand (CGEN_CPU_DESC cd,
142
         int opindex,
143
         void * xinfo,
144
         CGEN_FIELDS *fields,
145
         void const *attrs ATTRIBUTE_UNUSED,
146
         bfd_vma pc,
147
         int length)
148
344k
{
149
344k
  disassemble_info *info = (disassemble_info *) xinfo;
150
151
344k
  switch (opindex)
152
344k
    {
153
5
    case FRV_OPERAND_A0 :
154
5
      print_normal (cd, info, fields->f_A, 0, pc, length);
155
5
      break;
156
0
    case FRV_OPERAND_A1 :
157
0
      print_normal (cd, info, fields->f_A, 0, pc, length);
158
0
      break;
159
245
    case FRV_OPERAND_ACC40SI :
160
245
      print_keyword (cd, info, & frv_cgen_opval_acc_names, fields->f_ACC40Si, 0);
161
245
      break;
162
557
    case FRV_OPERAND_ACC40SK :
163
557
      print_keyword (cd, info, & frv_cgen_opval_acc_names, fields->f_ACC40Sk, 0);
164
557
      break;
165
0
    case FRV_OPERAND_ACC40UI :
166
0
      print_keyword (cd, info, & frv_cgen_opval_acc_names, fields->f_ACC40Ui, 0);
167
0
      break;
168
1.08k
    case FRV_OPERAND_ACC40UK :
169
1.08k
      print_keyword (cd, info, & frv_cgen_opval_acc_names, fields->f_ACC40Uk, 0);
170
1.08k
      break;
171
3
    case FRV_OPERAND_ACCGI :
172
3
      print_keyword (cd, info, & frv_cgen_opval_accg_names, fields->f_ACCGi, 0);
173
3
      break;
174
4
    case FRV_OPERAND_ACCGK :
175
4
      print_keyword (cd, info, & frv_cgen_opval_accg_names, fields->f_ACCGk, 0);
176
4
      break;
177
11.2k
    case FRV_OPERAND_CCI :
178
11.2k
      print_keyword (cd, info, & frv_cgen_opval_cccr_names, fields->f_CCi, 0);
179
11.2k
      break;
180
33
    case FRV_OPERAND_CPRDOUBLEK :
181
33
      print_keyword (cd, info, & frv_cgen_opval_cpr_names, fields->f_CPRk, 0);
182
33
      break;
183
9.13k
    case FRV_OPERAND_CPRI :
184
9.13k
      print_keyword (cd, info, & frv_cgen_opval_cpr_names, fields->f_CPRi, 0);
185
9.13k
      break;
186
9.13k
    case FRV_OPERAND_CPRJ :
187
9.13k
      print_keyword (cd, info, & frv_cgen_opval_cpr_names, fields->f_CPRj, 0);
188
9.13k
      break;
189
9.18k
    case FRV_OPERAND_CPRK :
190
9.18k
      print_keyword (cd, info, & frv_cgen_opval_cpr_names, fields->f_CPRk, 0);
191
9.18k
      break;
192
0
    case FRV_OPERAND_CRI :
193
0
      print_keyword (cd, info, & frv_cgen_opval_cccr_names, fields->f_CRi, 0);
194
0
      break;
195
0
    case FRV_OPERAND_CRJ :
196
0
      print_keyword (cd, info, & frv_cgen_opval_cccr_names, fields->f_CRj, 0);
197
0
      break;
198
4
    case FRV_OPERAND_CRJ_FLOAT :
199
4
      print_keyword (cd, info, & frv_cgen_opval_cccr_names, fields->f_CRj_float, 0);
200
4
      break;
201
26
    case FRV_OPERAND_CRJ_INT :
202
26
      print_keyword (cd, info, & frv_cgen_opval_cccr_names, fields->f_CRj_int, 0);
203
26
      break;
204
0
    case FRV_OPERAND_CRK :
205
0
      print_keyword (cd, info, & frv_cgen_opval_cccr_names, fields->f_CRk, 0);
206
0
      break;
207
0
    case FRV_OPERAND_FCCI_1 :
208
0
      print_keyword (cd, info, & frv_cgen_opval_fccr_names, fields->f_FCCi_1, 0);
209
0
      break;
210
733
    case FRV_OPERAND_FCCI_2 :
211
733
      print_keyword (cd, info, & frv_cgen_opval_fccr_names, fields->f_FCCi_2, 0);
212
733
      break;
213
4
    case FRV_OPERAND_FCCI_3 :
214
4
      print_keyword (cd, info, & frv_cgen_opval_fccr_names, fields->f_FCCi_3, 0);
215
4
      break;
216
6
    case FRV_OPERAND_FCCK :
217
6
      print_keyword (cd, info, & frv_cgen_opval_fccr_names, fields->f_FCCk, 0);
218
6
      break;
219
80
    case FRV_OPERAND_FRDOUBLEI :
220
80
      print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRi, 0);
221
80
      break;
222
90
    case FRV_OPERAND_FRDOUBLEJ :
223
90
      print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRj, 0);
224
90
      break;
225
2.43k
    case FRV_OPERAND_FRDOUBLEK :
226
2.43k
      print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRk, 0);
227
2.43k
      break;
228
1.01k
    case FRV_OPERAND_FRI :
229
1.01k
      print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRi, 0);
230
1.01k
      break;
231
2.92k
    case FRV_OPERAND_FRINTI :
232
2.92k
      print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRi, 0);
233
2.92k
      break;
234
903
    case FRV_OPERAND_FRINTIEVEN :
235
903
      print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRi, 0);
236
903
      break;
237
2.00k
    case FRV_OPERAND_FRINTJ :
238
2.00k
      print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRj, 0);
239
2.00k
      break;
240
893
    case FRV_OPERAND_FRINTJEVEN :
241
893
      print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRj, 0);
242
893
      break;
243
8.22k
    case FRV_OPERAND_FRINTK :
244
8.22k
      print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRk, 0);
245
8.22k
      break;
246
1.32k
    case FRV_OPERAND_FRINTKEVEN :
247
1.32k
      print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRk, 0);
248
1.32k
      break;
249
1.01k
    case FRV_OPERAND_FRJ :
250
1.01k
      print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRj, 0);
251
1.01k
      break;
252
1.00k
    case FRV_OPERAND_FRK :
253
1.00k
      print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRk, 0);
254
1.00k
      break;
255
21
    case FRV_OPERAND_FRKHI :
256
21
      print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRk, 0);
257
21
      break;
258
9
    case FRV_OPERAND_FRKLO :
259
9
      print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRk, 0);
260
9
      break;
261
5.23k
    case FRV_OPERAND_GRDOUBLEK :
262
5.23k
      print_keyword (cd, info, & frv_cgen_opval_gr_names, fields->f_GRk, 0);
263
5.23k
      break;
264
58.9k
    case FRV_OPERAND_GRI :
265
58.9k
      print_keyword (cd, info, & frv_cgen_opval_gr_names, fields->f_GRi, 0);
266
58.9k
      break;
267
23.8k
    case FRV_OPERAND_GRJ :
268
23.8k
      print_keyword (cd, info, & frv_cgen_opval_gr_names, fields->f_GRj, 0);
269
23.8k
      break;
270
43.0k
    case FRV_OPERAND_GRK :
271
43.0k
      print_keyword (cd, info, & frv_cgen_opval_gr_names, fields->f_GRk, 0);
272
43.0k
      break;
273
634
    case FRV_OPERAND_GRKHI :
274
634
      print_keyword (cd, info, & frv_cgen_opval_gr_names, fields->f_GRk, 0);
275
634
      break;
276
358
    case FRV_OPERAND_GRKLO :
277
358
      print_keyword (cd, info, & frv_cgen_opval_gr_names, fields->f_GRk, 0);
278
358
      break;
279
10.6k
    case FRV_OPERAND_ICCI_1 :
280
10.6k
      print_keyword (cd, info, & frv_cgen_opval_iccr_names, fields->f_ICCi_1, 0);
281
10.6k
      break;
282
1.11k
    case FRV_OPERAND_ICCI_2 :
283
1.11k
      print_keyword (cd, info, & frv_cgen_opval_iccr_names, fields->f_ICCi_2, 0);
284
1.11k
      break;
285
14
    case FRV_OPERAND_ICCI_3 :
286
14
      print_keyword (cd, info, & frv_cgen_opval_iccr_names, fields->f_ICCi_3, 0);
287
14
      break;
288
0
    case FRV_OPERAND_LI :
289
0
      print_normal (cd, info, fields->f_LI, 0, pc, length);
290
0
      break;
291
13
    case FRV_OPERAND_LRAD :
292
13
      print_normal (cd, info, fields->f_LRAD, 0, pc, length);
293
13
      break;
294
13
    case FRV_OPERAND_LRAE :
295
13
      print_normal (cd, info, fields->f_LRAE, 0, pc, length);
296
13
      break;
297
13
    case FRV_OPERAND_LRAS :
298
13
      print_normal (cd, info, fields->f_LRAS, 0, pc, length);
299
13
      break;
300
5
    case FRV_OPERAND_TLBPRL :
301
5
      print_normal (cd, info, fields->f_TLBPRL, 0, pc, length);
302
5
      break;
303
5
    case FRV_OPERAND_TLBPROPX :
304
5
      print_normal (cd, info, fields->f_TLBPRopx, 0, pc, length);
305
5
      break;
306
0
    case FRV_OPERAND_AE :
307
0
      print_normal (cd, info, fields->f_ae, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
308
0
      break;
309
6
    case FRV_OPERAND_CALLANN :
310
6
      print_at (cd, info, fields->f_reloc_ann, 0, pc, length);
311
6
      break;
312
0
    case FRV_OPERAND_CCOND :
313
0
      print_normal (cd, info, fields->f_ccond, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
314
0
      break;
315
11.2k
    case FRV_OPERAND_COND :
316
11.2k
      print_normal (cd, info, fields->f_cond, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
317
11.2k
      break;
318
19.8k
    case FRV_OPERAND_D12 :
319
19.8k
      print_normal (cd, info, fields->f_d12, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
320
19.8k
      break;
321
8
    case FRV_OPERAND_DEBUG :
322
8
      print_normal (cd, info, fields->f_debug, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
323
8
      break;
324
0
    case FRV_OPERAND_EIR :
325
0
      print_normal (cd, info, fields->f_eir, 0, pc, length);
326
0
      break;
327
578
    case FRV_OPERAND_HINT :
328
578
      print_normal (cd, info, fields->f_hint, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
329
578
      break;
330
44
    case FRV_OPERAND_HINT_NOT_TAKEN :
331
44
      print_keyword (cd, info, & frv_cgen_opval_h_hint_not_taken, fields->f_hint, 0);
332
44
      break;
333
4
    case FRV_OPERAND_HINT_TAKEN :
334
4
      print_keyword (cd, info, & frv_cgen_opval_h_hint_taken, fields->f_hint, 0);
335
4
      break;
336
582
    case FRV_OPERAND_LABEL16 :
337
582
      print_address (cd, info, fields->f_label16, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
338
582
      break;
339
758
    case FRV_OPERAND_LABEL24 :
340
758
      print_address (cd, info, fields->f_label24, 0|(1<<CGEN_OPERAND_PCREL_ADDR)|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
341
758
      break;
342
78
    case FRV_OPERAND_LDANN :
343
78
      print_at (cd, info, fields->f_reloc_ann, 0, pc, length);
344
78
      break;
345
7
    case FRV_OPERAND_LDDANN :
346
7
      print_at (cd, info, fields->f_reloc_ann, 0, pc, length);
347
7
      break;
348
13
    case FRV_OPERAND_LOCK :
349
13
      print_normal (cd, info, fields->f_lock, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
350
13
      break;
351
76.5k
    case FRV_OPERAND_PACK :
352
76.5k
      print_keyword (cd, info, & frv_cgen_opval_h_pack, fields->f_pack, 0);
353
76.5k
      break;
354
6.62k
    case FRV_OPERAND_S10 :
355
6.62k
      print_normal (cd, info, fields->f_s10, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
356
6.62k
      break;
357
8.73k
    case FRV_OPERAND_S12 :
358
8.73k
      print_normal (cd, info, fields->f_d12, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
359
8.73k
      break;
360
0
    case FRV_OPERAND_S16 :
361
0
      print_normal (cd, info, fields->f_s16, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
362
0
      break;
363
16
    case FRV_OPERAND_S5 :
364
16
      print_normal (cd, info, fields->f_s5, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
365
16
      break;
366
226
    case FRV_OPERAND_S6 :
367
226
      print_normal (cd, info, fields->f_s6, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
368
226
      break;
369
9.13k
    case FRV_OPERAND_S6_1 :
370
9.13k
      print_normal (cd, info, fields->f_s6_1, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
371
9.13k
      break;
372
592
    case FRV_OPERAND_SLO16 :
373
592
      print_lo (cd, info, fields->f_s16, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
374
592
      break;
375
17
    case FRV_OPERAND_SPR :
376
17
      print_spr (cd, info, & frv_cgen_opval_spr_names, fields->f_spr, 0|(1<<CGEN_OPERAND_VIRTUAL));
377
17
      break;
378
119
    case FRV_OPERAND_U12 :
379
119
      print_normal (cd, info, fields->f_u12, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
380
119
      break;
381
0
    case FRV_OPERAND_U16 :
382
0
      print_normal (cd, info, fields->f_u16, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
383
0
      break;
384
931
    case FRV_OPERAND_U6 :
385
931
      print_normal (cd, info, fields->f_u6, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
386
931
      break;
387
634
    case FRV_OPERAND_UHI16 :
388
634
      print_hi (cd, info, fields->f_u16, 0, pc, length);
389
634
      break;
390
358
    case FRV_OPERAND_ULO16 :
391
358
      print_lo (cd, info, fields->f_u16, 0, pc, length);
392
358
      break;
393
394
0
    default :
395
      /* xgettext:c-format */
396
0
      opcodes_error_handler
397
0
  (_("internal error: unrecognized field %d while printing insn"),
398
0
   opindex);
399
0
      abort ();
400
344k
  }
401
344k
}
402
403
cgen_print_fn * const frv_cgen_print_handlers[] =
404
{
405
  print_insn_normal,
406
};
407
408
409
void
410
frv_cgen_init_dis (CGEN_CPU_DESC cd)
411
4
{
412
4
  frv_cgen_init_opcode_table (cd);
413
4
  frv_cgen_init_ibld_table (cd);
414
4
  cd->print_handlers = & frv_cgen_print_handlers[0];
415
4
  cd->print_operand = frv_cgen_print_operand;
416
4
}
417
418

419
/* Default print handler.  */
420
421
static void
422
print_normal (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
423
        void *dis_info,
424
        long value,
425
        unsigned int attrs,
426
        bfd_vma pc ATTRIBUTE_UNUSED,
427
        int length ATTRIBUTE_UNUSED)
428
57.4k
{
429
57.4k
  disassemble_info *info = (disassemble_info *) dis_info;
430
431
  /* Print the operand as directed by the attributes.  */
432
57.4k
  if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
433
0
    ; /* nothing to do */
434
57.4k
  else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
435
44.6k
    (*info->fprintf_func) (info->stream, "%ld", value);
436
12.7k
  else
437
12.7k
    (*info->fprintf_func) (info->stream, "0x%lx", value);
438
57.4k
}
439
440
/* Default address handler.  */
441
442
static void
443
print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
444
         void *dis_info,
445
         bfd_vma value,
446
         unsigned int attrs,
447
         bfd_vma pc ATTRIBUTE_UNUSED,
448
         int length ATTRIBUTE_UNUSED)
449
1.34k
{
450
1.34k
  disassemble_info *info = (disassemble_info *) dis_info;
451
452
  /* Print the operand as directed by the attributes.  */
453
1.34k
  if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
454
0
    ; /* Nothing to do.  */
455
1.34k
  else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR))
456
1.34k
    (*info->print_address_func) (value, info);
457
0
  else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR))
458
0
    (*info->print_address_func) (value, info);
459
0
  else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
460
0
    (*info->fprintf_func) (info->stream, "%ld", (long) value);
461
0
  else
462
0
    (*info->fprintf_func) (info->stream, "0x%lx", (long) value);
463
1.34k
}
464
465
/* Keyword print handler.  */
466
467
static void
468
print_keyword (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
469
         void *dis_info,
470
         CGEN_KEYWORD *keyword_table,
471
         long value,
472
         unsigned int attrs ATTRIBUTE_UNUSED)
473
283k
{
474
283k
  disassemble_info *info = (disassemble_info *) dis_info;
475
283k
  const CGEN_KEYWORD_ENTRY *ke;
476
477
283k
  ke = cgen_keyword_lookup_value (keyword_table, value);
478
283k
  if (ke != NULL)
479
283k
    (*info->fprintf_func) (info->stream, "%s", ke->name);
480
0
  else
481
0
    (*info->fprintf_func) (info->stream, "???");
482
283k
}
483

484
/* Default insn printer.
485
486
   DIS_INFO is defined as `void *' so the disassembler needn't know anything
487
   about disassemble_info.  */
488
489
static void
490
print_insn_normal (CGEN_CPU_DESC cd,
491
       void *dis_info,
492
       const CGEN_INSN *insn,
493
       CGEN_FIELDS *fields,
494
       bfd_vma pc,
495
       int length)
496
76.5k
{
497
76.5k
  const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
498
76.5k
  disassemble_info *info = (disassemble_info *) dis_info;
499
76.5k
  const CGEN_SYNTAX_CHAR_TYPE *syn;
500
501
76.5k
  CGEN_INIT_PRINT (cd);
502
503
841k
  for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
504
764k
    {
505
764k
      if (CGEN_SYNTAX_MNEMONIC_P (*syn))
506
76.5k
  {
507
76.5k
    (*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn));
508
76.5k
    continue;
509
76.5k
  }
510
688k
      if (CGEN_SYNTAX_CHAR_P (*syn))
511
343k
  {
512
343k
    (*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn));
513
343k
    continue;
514
343k
  }
515
516
      /* We have an operand.  */
517
344k
      frv_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info,
518
344k
         fields, CGEN_INSN_ATTRS (insn), pc, length);
519
344k
    }
520
76.5k
}
521

522
/* Subroutine of print_insn. Reads an insn into the given buffers and updates
523
   the extract info.
524
   Returns 0 if all is well, non-zero otherwise.  */
525
526
static int
527
read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
528
     bfd_vma pc,
529
     disassemble_info *info,
530
     bfd_byte *buf,
531
     int buflen,
532
     CGEN_EXTRACT_INFO *ex_info,
533
     unsigned long *insn_value)
534
0
{
535
0
  int status = (*info->read_memory_func) (pc, buf, buflen, info);
536
537
0
  if (status != 0)
538
0
    {
539
0
      (*info->memory_error_func) (status, pc, info);
540
0
      return -1;
541
0
    }
542
543
0
  ex_info->dis_info = info;
544
0
  ex_info->valid = (1 << buflen) - 1;
545
0
  ex_info->insn_bytes = buf;
546
547
0
  *insn_value = bfd_get_bits (buf, buflen * 8, info->endian == BFD_ENDIAN_BIG);
548
0
  return 0;
549
0
}
550
551
/* Utility to print an insn.
552
   BUF is the base part of the insn, target byte order, BUFLEN bytes long.
553
   The result is the size of the insn in bytes or zero for an unknown insn
554
   or -1 if an error occurs fetching data (memory_error_func will have
555
   been called).  */
556
557
static int
558
print_insn (CGEN_CPU_DESC cd,
559
      bfd_vma pc,
560
      disassemble_info *info,
561
      bfd_byte *buf,
562
      unsigned int buflen)
563
93.0k
{
564
93.0k
  CGEN_INSN_INT insn_value;
565
93.0k
  const CGEN_INSN_LIST *insn_list;
566
93.0k
  CGEN_EXTRACT_INFO ex_info;
567
93.0k
  int basesize;
568
569
  /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */
570
93.0k
  basesize = cd->base_insn_bitsize < buflen * 8 ?
571
93.0k
                                     cd->base_insn_bitsize : buflen * 8;
572
93.0k
  insn_value = cgen_get_insn_value (cd, buf, basesize, cd->insn_endian);
573
574
575
  /* Fill in ex_info fields like read_insn would.  Don't actually call
576
     read_insn, since the incoming buffer is already read (and possibly
577
     modified a la m32r).  */
578
93.0k
  ex_info.valid = (1 << buflen) - 1;
579
93.0k
  ex_info.dis_info = info;
580
93.0k
  ex_info.insn_bytes = buf;
581
582
  /* The instructions are stored in hash lists.
583
     Pick the first one and keep trying until we find the right one.  */
584
585
93.0k
  insn_list = CGEN_DIS_LOOKUP_INSN (cd, (char *) buf, insn_value);
586
469k
  while (insn_list != NULL)
587
453k
    {
588
453k
      const CGEN_INSN *insn = insn_list->insn;
589
453k
      CGEN_FIELDS fields;
590
453k
      int length;
591
453k
      unsigned long insn_value_cropped;
592
593
#ifdef CGEN_VALIDATE_INSN_SUPPORTED
594
      /* Not needed as insn shouldn't be in hash lists if not supported.  */
595
      /* Supported by this cpu?  */
596
      if (! frv_cgen_insn_supported (cd, insn))
597
        {
598
          insn_list = CGEN_DIS_NEXT_INSN (insn_list);
599
    continue;
600
        }
601
#endif
602
603
      /* Basic bit mask must be correct.  */
604
      /* ??? May wish to allow target to defer this check until the extract
605
   handler.  */
606
607
      /* Base size may exceed this instruction's size.  Extract the
608
         relevant part from the buffer. */
609
453k
      if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen &&
610
453k
    (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
611
0
  insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
612
0
             info->endian == BFD_ENDIAN_BIG);
613
453k
      else
614
453k
  insn_value_cropped = insn_value;
615
616
453k
      if ((insn_value_cropped & CGEN_INSN_BASE_MASK (insn))
617
453k
    == CGEN_INSN_BASE_VALUE (insn))
618
76.5k
  {
619
    /* Printing is handled in two passes.  The first pass parses the
620
       machine insn and extracts the fields.  The second pass prints
621
       them.  */
622
623
    /* Make sure the entire insn is loaded into insn_value, if it
624
       can fit.  */
625
76.5k
    if (((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize) &&
626
76.5k
        (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
627
0
      {
628
0
        unsigned long full_insn_value;
629
0
        int rc = read_insn (cd, pc, info, buf,
630
0
          CGEN_INSN_BITSIZE (insn) / 8,
631
0
          & ex_info, & full_insn_value);
632
0
        if (rc != 0)
633
0
    return rc;
634
0
        length = CGEN_EXTRACT_FN (cd, insn)
635
0
    (cd, insn, &ex_info, full_insn_value, &fields, pc);
636
0
      }
637
76.5k
    else
638
76.5k
      length = CGEN_EXTRACT_FN (cd, insn)
639
76.5k
        (cd, insn, &ex_info, insn_value_cropped, &fields, pc);
640
641
    /* Length < 0 -> error.  */
642
76.5k
    if (length < 0)
643
0
      return length;
644
76.5k
    if (length > 0)
645
76.5k
      {
646
76.5k
        CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length);
647
        /* Length is in bits, result is in bytes.  */
648
76.5k
        return length / 8;
649
76.5k
      }
650
76.5k
  }
651
652
376k
      insn_list = CGEN_DIS_NEXT_INSN (insn_list);
653
376k
    }
654
655
16.5k
  return 0;
656
93.0k
}
657
658
/* Default value for CGEN_PRINT_INSN.
659
   The result is the size of the insn in bytes or zero for an unknown insn
660
   or -1 if an error occured fetching bytes.  */
661
662
#ifndef CGEN_PRINT_INSN
663
93.1k
#define CGEN_PRINT_INSN default_print_insn
664
#endif
665
666
static int
667
default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
668
93.1k
{
669
93.1k
  bfd_byte buf[CGEN_MAX_INSN_SIZE];
670
93.1k
  int buflen;
671
93.1k
  int status;
672
673
  /* Attempt to read the base part of the insn.  */
674
93.1k
  buflen = cd->base_insn_bitsize / 8;
675
93.1k
  status = (*info->read_memory_func) (pc, buf, buflen, info);
676
677
  /* Try again with the minimum part, if min < base.  */
678
93.1k
  if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize))
679
0
    {
680
0
      buflen = cd->min_insn_bitsize / 8;
681
0
      status = (*info->read_memory_func) (pc, buf, buflen, info);
682
0
    }
683
684
93.1k
  if (status != 0)
685
121
    {
686
121
      (*info->memory_error_func) (status, pc, info);
687
121
      return -1;
688
121
    }
689
690
93.0k
  return print_insn (cd, pc, info, buf, buflen);
691
93.1k
}
692
693
/* Main entry point.
694
   Print one instruction from PC on INFO->STREAM.
695
   Return the size of the instruction (in bytes).  */
696
697
typedef struct cpu_desc_list
698
{
699
  struct cpu_desc_list *next;
700
  CGEN_BITSET *isa;
701
  int mach;
702
  int endian;
703
  int insn_endian;
704
  CGEN_CPU_DESC cd;
705
} cpu_desc_list;
706
707
int
708
print_insn_frv (bfd_vma pc, disassemble_info *info)
709
93.1k
{
710
93.1k
  static cpu_desc_list *cd_list = 0;
711
93.1k
  cpu_desc_list *cl = 0;
712
93.1k
  static CGEN_CPU_DESC cd = 0;
713
93.1k
  static CGEN_BITSET *prev_isa;
714
93.1k
  static int prev_mach;
715
93.1k
  static int prev_endian;
716
93.1k
  static int prev_insn_endian;
717
93.1k
  int length;
718
93.1k
  CGEN_BITSET *isa;
719
93.1k
  int mach;
720
93.1k
  int endian = (info->endian == BFD_ENDIAN_BIG
721
93.1k
    ? CGEN_ENDIAN_BIG
722
93.1k
    : CGEN_ENDIAN_LITTLE);
723
93.1k
  int insn_endian = (info->endian_code == BFD_ENDIAN_BIG
724
93.1k
                     ? CGEN_ENDIAN_BIG
725
93.1k
                     : CGEN_ENDIAN_LITTLE);
726
93.1k
  enum bfd_architecture arch;
727
728
  /* ??? gdb will set mach but leave the architecture as "unknown" */
729
93.1k
#ifndef CGEN_BFD_ARCH
730
93.1k
#define CGEN_BFD_ARCH bfd_arch_frv
731
93.1k
#endif
732
93.1k
  arch = info->arch;
733
93.1k
  if (arch == bfd_arch_unknown)
734
0
    arch = CGEN_BFD_ARCH;
735
736
  /* There's no standard way to compute the machine or isa number
737
     so we leave it to the target.  */
738
#ifdef CGEN_COMPUTE_MACH
739
  mach = CGEN_COMPUTE_MACH (info);
740
#else
741
93.1k
  mach = info->mach;
742
93.1k
#endif
743
744
#ifdef CGEN_COMPUTE_ISA
745
  {
746
    static CGEN_BITSET *permanent_isa;
747
748
    if (!permanent_isa)
749
      permanent_isa = cgen_bitset_create (MAX_ISAS);
750
    isa = permanent_isa;
751
    cgen_bitset_clear (isa);
752
    cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info));
753
  }
754
#else
755
93.1k
  isa = info->private_data;
756
93.1k
#endif
757
758
  /* If we've switched cpu's, try to find a handle we've used before */
759
93.1k
  if (cd
760
93.1k
      && (cgen_bitset_compare (isa, prev_isa) != 0
761
93.1k
    || mach != prev_mach
762
93.1k
    || endian != prev_endian))
763
93.0k
    {
764
93.0k
      cd = 0;
765
278k
      for (cl = cd_list; cl; cl = cl->next)
766
278k
  {
767
278k
    if (cgen_bitset_compare (cl->isa, isa) == 0 &&
768
278k
        cl->mach == mach &&
769
278k
        cl->endian == endian)
770
93.0k
      {
771
93.0k
        cd = cl->cd;
772
93.0k
        prev_isa = cd->isas;
773
93.0k
        break;
774
93.0k
      }
775
278k
  }
776
93.0k
    }
777
778
  /* If we haven't initialized yet, initialize the opcode table.  */
779
93.1k
  if (! cd)
780
4
    {
781
4
      const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach);
782
4
      const char *mach_name;
783
784
4
      if (!arch_type)
785
0
  abort ();
786
4
      mach_name = arch_type->printable_name;
787
788
4
      prev_isa = cgen_bitset_copy (isa);
789
4
      prev_mach = mach;
790
4
      prev_endian = endian;
791
4
      prev_insn_endian = insn_endian;
792
4
      cd = frv_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa,
793
4
         CGEN_CPU_OPEN_BFDMACH, mach_name,
794
4
         CGEN_CPU_OPEN_ENDIAN, prev_endian,
795
4
                                 CGEN_CPU_OPEN_INSN_ENDIAN, prev_insn_endian,
796
4
         CGEN_CPU_OPEN_END);
797
4
      if (!cd)
798
0
  abort ();
799
800
      /* Save this away for future reference.  */
801
4
      cl = xmalloc (sizeof (struct cpu_desc_list));
802
4
      cl->cd = cd;
803
4
      cl->isa = prev_isa;
804
4
      cl->mach = mach;
805
4
      cl->endian = endian;
806
4
      cl->next = cd_list;
807
4
      cd_list = cl;
808
809
4
      frv_cgen_init_dis (cd);
810
4
    }
811
812
  /* We try to have as much common code as possible.
813
     But at this point some targets need to take over.  */
814
  /* ??? Some targets may need a hook elsewhere.  Try to avoid this,
815
     but if not possible try to move this hook elsewhere rather than
816
     have two hooks.  */
817
93.1k
  length = CGEN_PRINT_INSN (cd, pc, info);
818
93.1k
  if (length > 0)
819
76.5k
    return length;
820
16.6k
  if (length < 0)
821
121
    return -1;
822
823
16.5k
  (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
824
16.5k
  return cd->default_insn_bitsize / 8;
825
16.6k
}