Coverage Report

Created: 2024-05-21 06:29

/src/binutils-gdb/opcodes/i386-dis.c
Line
Count
Source (jump to first uncovered line)
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/* Print i386 instructions for GDB, the GNU debugger.
2
   Copyright (C) 1988-2024 Free Software Foundation, Inc.
3
4
   This file is part of the GNU opcodes library.
5
6
   This library is free software; you can redistribute it and/or modify
7
   it under the terms of the GNU General Public License as published by
8
   the Free Software Foundation; either version 3, or (at your option)
9
   any later version.
10
11
   It is distributed in the hope that it will be useful, but WITHOUT
12
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
14
   License for more details.
15
16
   You should have received a copy of the GNU General Public License
17
   along with this program; if not, write to the Free Software
18
   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19
   MA 02110-1301, USA.  */
20
21
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/* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
23
   July 1988
24
    modified by John Hassey (hassey@dg-rtp.dg.com)
25
    x86-64 support added by Jan Hubicka (jh@suse.cz)
26
    VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
27
28
/* The main tables describing the instructions is essentially a copy
29
   of the "Opcode Map" chapter (Appendix A) of the Intel 80386
30
   Programmers Manual.  Usually, there is a capital letter, followed
31
   by a small letter.  The capital letter tell the addressing mode,
32
   and the small letter tells about the operand size.  Refer to
33
   the Intel manual for details.  */
34
35
#include "sysdep.h"
36
#include "disassemble.h"
37
#include "opintl.h"
38
#include "opcode/i386.h"
39
#include "libiberty.h"
40
#include "safe-ctype.h"
41
42
typedef struct instr_info instr_info;
43
44
static bool dofloat (instr_info *, int);
45
static int putop (instr_info *, const char *, int);
46
static void oappend_with_style (instr_info *, const char *,
47
        enum disassembler_style);
48
49
static bool OP_E (instr_info *, int, int);
50
static bool OP_E_memory (instr_info *, int, int);
51
static bool OP_indirE (instr_info *, int, int);
52
static bool OP_G (instr_info *, int, int);
53
static bool OP_ST (instr_info *, int, int);
54
static bool OP_STi (instr_info *, int, int);
55
static bool OP_Skip_MODRM (instr_info *, int, int);
56
static bool OP_REG (instr_info *, int, int);
57
static bool OP_IMREG (instr_info *, int, int);
58
static bool OP_I (instr_info *, int, int);
59
static bool OP_I64 (instr_info *, int, int);
60
static bool OP_sI (instr_info *, int, int);
61
static bool OP_J (instr_info *, int, int);
62
static bool OP_SEG (instr_info *, int, int);
63
static bool OP_DIR (instr_info *, int, int);
64
static bool OP_OFF (instr_info *, int, int);
65
static bool OP_OFF64 (instr_info *, int, int);
66
static bool OP_ESreg (instr_info *, int, int);
67
static bool OP_DSreg (instr_info *, int, int);
68
static bool OP_C (instr_info *, int, int);
69
static bool OP_D (instr_info *, int, int);
70
static bool OP_T (instr_info *, int, int);
71
static bool OP_MMX (instr_info *, int, int);
72
static bool OP_XMM (instr_info *, int, int);
73
static bool OP_EM (instr_info *, int, int);
74
static bool OP_EX (instr_info *, int, int);
75
static bool OP_EMC (instr_info *, int,int);
76
static bool OP_MXC (instr_info *, int,int);
77
static bool OP_R (instr_info *, int, int);
78
static bool OP_M (instr_info *, int, int);
79
static bool OP_VEX (instr_info *, int, int);
80
static bool OP_VexR (instr_info *, int, int);
81
static bool OP_VexW (instr_info *, int, int);
82
static bool OP_Rounding (instr_info *, int, int);
83
static bool OP_REG_VexI4 (instr_info *, int, int);
84
static bool OP_VexI4 (instr_info *, int, int);
85
static bool OP_0f07 (instr_info *, int, int);
86
static bool OP_Monitor (instr_info *, int, int);
87
static bool OP_Mwait (instr_info *, int, int);
88
89
static bool PCLMUL_Fixup (instr_info *, int, int);
90
static bool VPCMP_Fixup (instr_info *, int, int);
91
static bool VPCOM_Fixup (instr_info *, int, int);
92
static bool NOP_Fixup (instr_info *, int, int);
93
static bool OP_3DNowSuffix (instr_info *, int, int);
94
static bool CMP_Fixup (instr_info *, int, int);
95
static bool REP_Fixup (instr_info *, int, int);
96
static bool SEP_Fixup (instr_info *, int, int);
97
static bool BND_Fixup (instr_info *, int, int);
98
static bool NOTRACK_Fixup (instr_info *, int, int);
99
static bool HLE_Fixup1 (instr_info *, int, int);
100
static bool HLE_Fixup2 (instr_info *, int, int);
101
static bool HLE_Fixup3 (instr_info *, int, int);
102
static bool CMPXCHG8B_Fixup (instr_info *, int, int);
103
static bool XMM_Fixup (instr_info *, int, int);
104
static bool FXSAVE_Fixup (instr_info *, int, int);
105
static bool MOVSXD_Fixup (instr_info *, int, int);
106
static bool DistinctDest_Fixup (instr_info *, int, int);
107
static bool PREFETCHI_Fixup (instr_info *, int, int);
108
static bool PUSH2_POP2_Fixup (instr_info *, int, int);
109
static bool JMPABS_Fixup (instr_info *, int, int);
110
111
static void ATTRIBUTE_PRINTF_3 i386_dis_printf (const disassemble_info *,
112
            enum disassembler_style,
113
            const char *, ...);
114
115
/* This character is used to encode style information within the output
116
   buffers.  See oappend_insert_style for more details.  */
117
873M
#define STYLE_MARKER_CHAR '\002'
118
119
/* The maximum operand buffer size.  */
120
#define MAX_OPERAND_BUFFER_SIZE 128
121
122
enum address_mode
123
{
124
  mode_16bit,
125
  mode_32bit,
126
  mode_64bit
127
};
128
129
static const char *prefix_name (enum address_mode, uint8_t, int);
130
131
enum x86_64_isa
132
{
133
  amd64 = 1,
134
  intel64
135
};
136
137
enum evex_type
138
{
139
  evex_default = 0,
140
  evex_from_legacy,
141
  evex_from_vex,
142
};
143
144
struct instr_info
145
{
146
  enum address_mode address_mode;
147
148
  /* Flags for the prefixes for the current instruction.  See below.  */
149
  int prefixes;
150
151
  /* REX prefix the current instruction.  See below.  */
152
  uint8_t rex;
153
  /* Bits of REX we've already used.  */
154
  uint8_t rex_used;
155
156
  /* Record W R4 X4 B4 bits for rex2.  */
157
  unsigned char rex2;
158
  /* Bits of rex2 we've already used.  */
159
  unsigned char rex2_used;
160
  unsigned char rex2_payload;
161
162
  bool need_modrm;
163
  unsigned char need_vex;
164
  bool has_sib;
165
166
  /* Flags for ins->prefixes which we somehow handled when printing the
167
     current instruction.  */
168
  int used_prefixes;
169
170
  /* Flags for EVEX bits which we somehow handled when printing the
171
     current instruction.  */
172
  int evex_used;
173
174
  char obuf[MAX_OPERAND_BUFFER_SIZE];
175
  char *obufp;
176
  char *mnemonicendp;
177
  const uint8_t *start_codep;
178
  uint8_t *codep;
179
  const uint8_t *end_codep;
180
  unsigned char nr_prefixes;
181
  signed char last_lock_prefix;
182
  signed char last_repz_prefix;
183
  signed char last_repnz_prefix;
184
  signed char last_data_prefix;
185
  signed char last_addr_prefix;
186
  signed char last_rex_prefix;
187
  signed char last_rex2_prefix;
188
  signed char last_seg_prefix;
189
  signed char fwait_prefix;
190
  /* The active segment register prefix.  */
191
  unsigned char active_seg_prefix;
192
193
39.7M
#define MAX_CODE_LENGTH 15
194
  /* We can up to 14 ins->prefixes since the maximum instruction length is
195
     15bytes.  */
196
  uint8_t all_prefixes[MAX_CODE_LENGTH - 1];
197
  disassemble_info *info;
198
199
  struct
200
  {
201
    int mod;
202
    int reg;
203
    int rm;
204
  }
205
  modrm;
206
207
  struct
208
  {
209
    int scale;
210
    int index;
211
    int base;
212
  }
213
  sib;
214
215
  struct
216
  {
217
    int register_specifier;
218
    int length;
219
    int prefix;
220
    int mask_register_specifier;
221
    int ll;
222
    bool w;
223
    bool evex;
224
    bool v;
225
    bool zeroing;
226
    bool b;
227
    bool no_broadcast;
228
    bool nf;
229
  }
230
  vex;
231
232
/* For APX EVEX-promoted prefix, EVEX.ND shares the same bit as vex.b.  */
233
53.9M
#define nd b
234
235
  enum evex_type evex_type;
236
237
  /* Remember if the current op is a jump instruction.  */
238
  bool op_is_jump;
239
240
  bool two_source_ops;
241
242
  /* Record whether EVEX masking is used incorrectly.  */
243
  bool illegal_masking;
244
245
  /* Record whether the modrm byte has been skipped.  */
246
  bool has_skipped_modrm;
247
248
  unsigned char op_ad;
249
  signed char op_index[MAX_OPERANDS];
250
  bool op_riprel[MAX_OPERANDS];
251
  char *op_out[MAX_OPERANDS];
252
  bfd_vma op_address[MAX_OPERANDS];
253
  bfd_vma start_pc;
254
255
  /* On the 386's of 1988, the maximum length of an instruction is 15 bytes.
256
   *   (see topic "Redundant ins->prefixes" in the "Differences from 8086"
257
   *   section of the "Virtual 8086 Mode" chapter.)
258
   * 'pc' should be the address of this instruction, it will
259
   *   be used to print the target address if this is a relative jump or call
260
   * The function returns the length of this instruction in bytes.
261
   */
262
  char intel_syntax;
263
  bool intel_mnemonic;
264
  char open_char;
265
  char close_char;
266
  char separator_char;
267
  char scale_char;
268
269
  enum x86_64_isa isa64;
270
};
271
272
struct dis_private {
273
  bfd_vma insn_start;
274
  int orig_sizeflag;
275
276
  /* Indexes first byte not fetched.  */
277
  unsigned int fetched;
278
  uint8_t the_buffer[2 * MAX_CODE_LENGTH - 1];
279
};
280
281
/* Mark parts used in the REX prefix.  When we are testing for
282
   empty prefix (for 8bit register REX extension), just mask it
283
   out.  Otherwise test for REX bit is excuse for existence of REX
284
   only in case value is nonzero.  */
285
#define USED_REX(value)         \
286
30.2M
  {             \
287
30.2M
    if (value)           \
288
30.2M
      {             \
289
28.8M
  if (ins->rex & value)       \
290
28.8M
    ins->rex_used |= (value) | REX_OPCODE; \
291
28.8M
  if (ins->rex2 & value)       \
292
28.8M
    {           \
293
41.8k
      ins->rex2_used |= (value);      \
294
41.8k
      ins->rex_used |= REX_OPCODE;   \
295
41.8k
    }            \
296
28.8M
      }              \
297
30.2M
    else            \
298
30.2M
      ins->rex_used |= REX_OPCODE;     \
299
30.2M
  }
300
301
302
28.1k
#define EVEX_b_used 1
303
76.9k
#define EVEX_len_used 2
304
305
306
/* {rex2} is not printed when the REX2_SPECIAL is set.  */
307
23.8k
#define REX2_SPECIAL 16
308
309
/* Flags stored in PREFIXES.  */
310
848k
#define PREFIX_REPZ 1
311
1.92M
#define PREFIX_REPNZ 2
312
23.6M
#define PREFIX_CS 4
313
18.8M
#define PREFIX_SS 8
314
23.0M
#define PREFIX_DS 0x10
315
18.7M
#define PREFIX_ES 0x20
316
19.0M
#define PREFIX_FS 0x40
317
19.0M
#define PREFIX_GS 0x80
318
6.52M
#define PREFIX_LOCK 0x100
319
46.3M
#define PREFIX_DATA 0x200
320
47.6M
#define PREFIX_ADDR 0x400
321
18.9M
#define PREFIX_FWAIT 0x800
322
37.5M
#define PREFIX_REX2 0x1000
323
88.9k
#define PREFIX_NP_OR_DATA 0x2000
324
73.7k
#define NO_PREFIX   0x4000
325
326
/* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
327
   to ADDR (exclusive) are valid.  Returns true for success, false
328
   on error.  */
329
static bool
330
fetch_code (struct disassemble_info *info, const uint8_t *until)
331
59.9M
{
332
59.9M
  int status = -1;
333
59.9M
  struct dis_private *priv = info->private_data;
334
59.9M
  bfd_vma start = priv->insn_start + priv->fetched;
335
59.9M
  uint8_t *fetch_end = priv->the_buffer + priv->fetched;
336
59.9M
  ptrdiff_t needed = until - fetch_end;
337
338
59.9M
  if (needed <= 0)
339
18.9M
    return true;
340
341
40.9M
  if (priv->fetched + (size_t) needed <= ARRAY_SIZE (priv->the_buffer))
342
40.9M
    status = (*info->read_memory_func) (start, fetch_end, needed, info);
343
40.9M
  if (status != 0)
344
15.5k
    {
345
      /* If we did manage to read at least one byte, then
346
   print_insn_i386 will do something sensible.  Otherwise, print
347
   an error.  We do that here because this is where we know
348
   STATUS.  */
349
15.5k
      if (!priv->fetched)
350
548
  (*info->memory_error_func) (status, start, info);
351
15.5k
      return false;
352
15.5k
    }
353
354
40.9M
  priv->fetched += needed;
355
40.9M
  return true;
356
40.9M
}
357
358
static bool
359
fetch_modrm (instr_info *ins)
360
11.8M
{
361
11.8M
  if (!fetch_code (ins->info, ins->codep + 1))
362
4.39k
    return false;
363
364
11.8M
  ins->modrm.mod = (*ins->codep >> 6) & 3;
365
11.8M
  ins->modrm.reg = (*ins->codep >> 3) & 7;
366
11.8M
  ins->modrm.rm = *ins->codep & 7;
367
368
11.8M
  return true;
369
11.8M
}
370
371
static int
372
fetch_error (const instr_info *ins)
373
16.5k
{
374
  /* Getting here means we tried for data but didn't get it.  That
375
     means we have an incomplete instruction of some sort.  Just
376
     print the first byte as a prefix or a .byte pseudo-op.  */
377
16.5k
  const struct dis_private *priv = ins->info->private_data;
378
16.5k
  const char *name = NULL;
379
380
16.5k
  if (ins->codep <= priv->the_buffer)
381
548
    return -1;
382
383
16.0k
  if (ins->prefixes || ins->fwait_prefix >= 0 || (ins->rex & REX_OPCODE))
384
3.83k
    name = prefix_name (ins->address_mode, priv->the_buffer[0],
385
3.83k
      priv->orig_sizeflag);
386
16.0k
  if (name != NULL)
387
3.83k
    i386_dis_printf (ins->info, dis_style_mnemonic, "%s", name);
388
12.1k
  else
389
12.1k
    {
390
      /* Just print the first byte as a .byte instruction.  */
391
12.1k
      i386_dis_printf (ins->info, dis_style_assembler_directive, ".byte ");
392
12.1k
      i386_dis_printf (ins->info, dis_style_immediate, "%#x",
393
12.1k
           (unsigned int) priv->the_buffer[0]);
394
12.1k
    }
395
396
16.0k
  return 1;
397
16.5k
}
398
399
/* Possible values for prefix requirement.  */
400
37.5M
#define PREFIX_IGNORED_SHIFT  16
401
7.90k
#define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
402
7.90k
#define PREFIX_IGNORED_REPNZ  (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
403
7.90k
#define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
404
#define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
405
#define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
406
37.5M
#define PREFIX_REX2_ILLEGAL (PREFIX_REX2 << PREFIX_IGNORED_SHIFT)
407
408
/* Opcode prefixes.  */
409
51.0k
#define PREFIX_OPCODE   (PREFIX_REPZ \
410
51.0k
         | PREFIX_REPNZ \
411
51.0k
         | PREFIX_DATA)
412
413
/* Prefixes ignored.  */
414
7.90k
#define PREFIX_IGNORED    (PREFIX_IGNORED_REPZ \
415
7.90k
         | PREFIX_IGNORED_REPNZ \
416
7.90k
         | PREFIX_IGNORED_DATA)
417
418
#define XX { NULL, 0 }
419
#define Bad_Opcode NULL, { { NULL, 0 } }, 0
420
421
#define Eb { OP_E, b_mode }
422
#define Ebnd { OP_E, bnd_mode }
423
#define EbS { OP_E, b_swap_mode }
424
#define EbndS { OP_E, bnd_swap_mode }
425
#define Ev { OP_E, v_mode }
426
#define Eva { OP_E, va_mode }
427
#define Ev_bnd { OP_E, v_bnd_mode }
428
#define EvS { OP_E, v_swap_mode }
429
#define Ed { OP_E, d_mode }
430
#define Edq { OP_E, dq_mode }
431
#define Edb { OP_E, db_mode }
432
#define Edw { OP_E, dw_mode }
433
#define Eq { OP_E, q_mode }
434
#define indirEv { OP_indirE, indir_v_mode }
435
#define indirEp { OP_indirE, f_mode }
436
#define stackEv { OP_E, stack_v_mode }
437
#define Em { OP_E, m_mode }
438
#define Ew { OP_E, w_mode }
439
#define M { OP_M, 0 }   /* lea, lgdt, etc. */
440
#define Ma { OP_M, a_mode }
441
#define Mb { OP_M, b_mode }
442
#define Md { OP_M, d_mode }
443
#define Mdq { OP_M, dq_mode }
444
#define Mo { OP_M, o_mode }
445
#define Mp { OP_M, f_mode }   /* 32 or 48 bit memory operand for LDS, LES etc */
446
#define Mq { OP_M, q_mode }
447
#define Mv { OP_M, v_mode }
448
#define Mv_bnd { OP_M, v_bndmk_mode }
449
#define Mw { OP_M, w_mode }
450
#define Mx { OP_M, x_mode }
451
#define Mxmm { OP_M, xmm_mode }
452
#define Mymm { OP_M, ymm_mode }
453
#define Gb { OP_G, b_mode }
454
#define Gbnd { OP_G, bnd_mode }
455
#define Gv { OP_G, v_mode }
456
#define Gd { OP_G, d_mode }
457
#define Gdq { OP_G, dq_mode }
458
#define Gq { OP_G, q_mode }
459
#define Gm { OP_G, m_mode }
460
#define Gva { OP_G, va_mode }
461
#define Gw { OP_G, w_mode }
462
#define Ib { OP_I, b_mode }
463
#define sIb { OP_sI, b_mode } /* sign extened byte */
464
#define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
465
#define Iv { OP_I, v_mode }
466
#define sIv { OP_sI, v_mode }
467
#define Iv64 { OP_I64, v_mode }
468
#define Id { OP_I, d_mode }
469
#define Iw { OP_I, w_mode }
470
#define I1 { OP_I, const_1_mode }
471
#define Jb { OP_J, b_mode }
472
#define Jv { OP_J, v_mode }
473
#define Jdqw { OP_J, dqw_mode }
474
#define Cm { OP_C, m_mode }
475
#define Dm { OP_D, m_mode }
476
#define Td { OP_T, d_mode }
477
#define Skip_MODRM { OP_Skip_MODRM, 0 }
478
479
#define RMeAX { OP_REG, eAX_reg }
480
#define RMeBX { OP_REG, eBX_reg }
481
#define RMeCX { OP_REG, eCX_reg }
482
#define RMeDX { OP_REG, eDX_reg }
483
#define RMeSP { OP_REG, eSP_reg }
484
#define RMeBP { OP_REG, eBP_reg }
485
#define RMeSI { OP_REG, eSI_reg }
486
#define RMeDI { OP_REG, eDI_reg }
487
#define RMrAX { OP_REG, rAX_reg }
488
#define RMrBX { OP_REG, rBX_reg }
489
#define RMrCX { OP_REG, rCX_reg }
490
#define RMrDX { OP_REG, rDX_reg }
491
#define RMrSP { OP_REG, rSP_reg }
492
#define RMrBP { OP_REG, rBP_reg }
493
#define RMrSI { OP_REG, rSI_reg }
494
#define RMrDI { OP_REG, rDI_reg }
495
#define RMAL { OP_REG, al_reg }
496
#define RMCL { OP_REG, cl_reg }
497
#define RMDL { OP_REG, dl_reg }
498
#define RMBL { OP_REG, bl_reg }
499
#define RMAH { OP_REG, ah_reg }
500
#define RMCH { OP_REG, ch_reg }
501
#define RMDH { OP_REG, dh_reg }
502
#define RMBH { OP_REG, bh_reg }
503
#define RMAX { OP_REG, ax_reg }
504
#define RMDX { OP_REG, dx_reg }
505
506
#define eAX { OP_IMREG, eAX_reg }
507
#define AL { OP_IMREG, al_reg }
508
#define CL { OP_IMREG, cl_reg }
509
#define zAX { OP_IMREG, z_mode_ax_reg }
510
#define indirDX { OP_IMREG, indir_dx_reg }
511
512
#define Sw { OP_SEG, w_mode }
513
#define Sv { OP_SEG, v_mode }
514
#define Ap { OP_DIR, 0 }
515
#define Ob { OP_OFF64, b_mode }
516
#define Ov { OP_OFF64, v_mode }
517
#define Xb { OP_DSreg, eSI_reg }
518
#define Xv { OP_DSreg, eSI_reg }
519
#define Xz { OP_DSreg, eSI_reg }
520
#define Yb { OP_ESreg, eDI_reg }
521
#define Yv { OP_ESreg, eDI_reg }
522
#define DSBX { OP_DSreg, eBX_reg }
523
524
#define es { OP_REG, es_reg }
525
#define ss { OP_REG, ss_reg }
526
#define cs { OP_REG, cs_reg }
527
#define ds { OP_REG, ds_reg }
528
#define fs { OP_REG, fs_reg }
529
#define gs { OP_REG, gs_reg }
530
531
#define MX { OP_MMX, 0 }
532
#define XM { OP_XMM, 0 }
533
#define XMScalar { OP_XMM, scalar_mode }
534
#define XMGatherD { OP_XMM, vex_vsib_d_w_dq_mode }
535
#define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
536
#define XMM { OP_XMM, xmm_mode }
537
#define TMM { OP_XMM, tmm_mode }
538
#define XMxmmq { OP_XMM, xmmq_mode }
539
#define EM { OP_EM, v_mode }
540
#define EMS { OP_EM, v_swap_mode }
541
#define EMd { OP_EM, d_mode }
542
#define EMx { OP_EM, x_mode }
543
#define EXbwUnit { OP_EX, bw_unit_mode }
544
#define EXb { OP_EX, b_mode }
545
#define EXw { OP_EX, w_mode }
546
#define EXd { OP_EX, d_mode }
547
#define EXdS { OP_EX, d_swap_mode }
548
#define EXwS { OP_EX, w_swap_mode }
549
#define EXq { OP_EX, q_mode }
550
#define EXqS { OP_EX, q_swap_mode }
551
#define EXdq { OP_EX, dq_mode }
552
#define EXx { OP_EX, x_mode }
553
#define EXxh { OP_EX, xh_mode }
554
#define EXxS { OP_EX, x_swap_mode }
555
#define EXxmm { OP_EX, xmm_mode }
556
#define EXymm { OP_EX, ymm_mode }
557
#define EXxmmq { OP_EX, xmmq_mode }
558
#define EXxmmqh { OP_EX, evex_half_bcst_xmmqh_mode }
559
#define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
560
#define EXxmmdw { OP_EX, xmmdw_mode }
561
#define EXxmmqd { OP_EX, xmmqd_mode }
562
#define EXxmmqdh { OP_EX, evex_half_bcst_xmmqdh_mode }
563
#define EXymmq { OP_EX, ymmq_mode }
564
#define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
565
#define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
566
#define Rd { OP_R, d_mode }
567
#define Rdq { OP_R, dq_mode }
568
#define Rq { OP_R, q_mode }
569
#define Nq { OP_R, q_mm_mode }
570
#define Ux { OP_R, x_mode }
571
#define Uxmm { OP_R, xmm_mode }
572
#define Rxmmq { OP_R, xmmq_mode }
573
#define Rymm { OP_R, ymm_mode }
574
#define Rtmm { OP_R, tmm_mode }
575
#define EMCq { OP_EMC, q_mode }
576
#define MXC { OP_MXC, 0 }
577
#define OPSUF { OP_3DNowSuffix, 0 }
578
#define SEP { SEP_Fixup, 0 }
579
#define CMP { CMP_Fixup, 0 }
580
#define XMM0 { XMM_Fixup, 0 }
581
#define FXSAVE { FXSAVE_Fixup, 0 }
582
583
#define Vex { OP_VEX, x_mode }
584
#define VexW { OP_VexW, x_mode }
585
#define VexScalar { OP_VEX, scalar_mode }
586
#define VexScalarR { OP_VexR, scalar_mode }
587
#define VexGatherD { OP_VEX, vex_vsib_d_w_dq_mode }
588
#define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
589
#define VexGdq { OP_VEX, dq_mode }
590
#define VexGb { OP_VEX, b_mode }
591
#define VexGv { OP_VEX, v_mode }
592
#define VexTmm { OP_VEX, tmm_mode }
593
#define XMVexI4 { OP_REG_VexI4, x_mode }
594
#define XMVexScalarI4 { OP_REG_VexI4, scalar_mode }
595
#define VexI4 { OP_VexI4, 0 }
596
#define PCLMUL { PCLMUL_Fixup, 0 }
597
#define VPCMP { VPCMP_Fixup, 0 }
598
#define VPCOM { VPCOM_Fixup, 0 }
599
600
#define EXxEVexR { OP_Rounding, evex_rounding_mode }
601
#define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
602
#define EXxEVexS { OP_Rounding, evex_sae_mode }
603
604
#define MaskG { OP_G, mask_mode }
605
#define MaskE { OP_E, mask_mode }
606
#define MaskR { OP_R, mask_mode }
607
#define MaskBDE { OP_E, mask_bd_mode }
608
#define MaskVex { OP_VEX, mask_mode }
609
610
#define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
611
#define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
612
613
#define MVexSIBMEM { OP_M, vex_sibmem_mode }
614
615
/* Used handle "rep" prefix for string instructions.  */
616
#define Xbr { REP_Fixup, eSI_reg }
617
#define Xvr { REP_Fixup, eSI_reg }
618
#define Ybr { REP_Fixup, eDI_reg }
619
#define Yvr { REP_Fixup, eDI_reg }
620
#define Yzr { REP_Fixup, eDI_reg }
621
#define indirDXr { REP_Fixup, indir_dx_reg }
622
#define ALr { REP_Fixup, al_reg }
623
#define eAXr { REP_Fixup, eAX_reg }
624
625
/* Used handle HLE prefix for lockable instructions.  */
626
#define Ebh1 { HLE_Fixup1, b_mode }
627
#define Evh1 { HLE_Fixup1, v_mode }
628
#define Ebh2 { HLE_Fixup2, b_mode }
629
#define Evh2 { HLE_Fixup2, v_mode }
630
#define Ebh3 { HLE_Fixup3, b_mode }
631
#define Evh3 { HLE_Fixup3, v_mode }
632
633
#define BND { BND_Fixup, 0 }
634
#define NOTRACK { NOTRACK_Fixup, 0 }
635
636
#define cond_jump_flag { NULL, cond_jump_mode }
637
#define loop_jcxz_flag { NULL, loop_jcxz_mode }
638
639
/* bits in sizeflag */
640
15.3M
#define SUFFIX_ALWAYS 4
641
49.7M
#define AFLAG 2
642
27.1M
#define DFLAG 1
643
644
enum
645
{
646
  /* byte operand */
647
  b_mode = 1,
648
  /* byte operand with operand swapped */
649
  b_swap_mode,
650
  /* byte operand, sign extend like 'T' suffix */
651
  b_T_mode,
652
  /* operand size depends on prefixes */
653
  v_mode,
654
  /* operand size depends on prefixes with operand swapped */
655
  v_swap_mode,
656
  /* operand size depends on address prefix */
657
  va_mode,
658
  /* word operand */
659
  w_mode,
660
  /* double word operand  */
661
  d_mode,
662
  /* word operand with operand swapped  */
663
  w_swap_mode,
664
  /* double word operand with operand swapped */
665
  d_swap_mode,
666
  /* quad word operand */
667
  q_mode,
668
  /* 8-byte MM operand */
669
  q_mm_mode,
670
  /* quad word operand with operand swapped */
671
  q_swap_mode,
672
  /* ten-byte operand */
673
  t_mode,
674
  /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
675
     broadcast enabled.  */
676
  x_mode,
677
  /* Similar to x_mode, but with different EVEX mem shifts.  */
678
  evex_x_gscat_mode,
679
  /* Similar to x_mode, but with yet different EVEX mem shifts.  */
680
  bw_unit_mode,
681
  /* Similar to x_mode, but with disabled broadcast.  */
682
  evex_x_nobcst_mode,
683
  /* Similar to x_mode, but with operands swapped and disabled broadcast
684
     in EVEX.  */
685
  x_swap_mode,
686
  /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
687
     broadcast of 16bit enabled.  */
688
  xh_mode,
689
  /* 16-byte XMM operand */
690
  xmm_mode,
691
  /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
692
     memory operand (depending on vector length).  Broadcast isn't
693
     allowed.  */
694
  xmmq_mode,
695
  /* Same as xmmq_mode, but broadcast is allowed.  */
696
  evex_half_bcst_xmmq_mode,
697
  /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
698
     memory operand (depending on vector length).  16bit broadcast.  */
699
  evex_half_bcst_xmmqh_mode,
700
  /* 16-byte XMM, word, double word or quad word operand.  */
701
  xmmdw_mode,
702
  /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
703
  xmmqd_mode,
704
  /* 16-byte XMM, double word, quad word operand or xmm word operand.
705
     16bit broadcast.  */
706
  evex_half_bcst_xmmqdh_mode,
707
  /* 32-byte YMM operand */
708
  ymm_mode,
709
  /* quad word, ymmword or zmmword memory operand.  */
710
  ymmq_mode,
711
  /* TMM operand */
712
  tmm_mode,
713
  /* d_mode in 32bit, q_mode in 64bit mode.  */
714
  m_mode,
715
  /* pair of v_mode operands */
716
  a_mode,
717
  cond_jump_mode,
718
  loop_jcxz_mode,
719
  movsxd_mode,
720
  v_bnd_mode,
721
  /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode.  */
722
  v_bndmk_mode,
723
  /* operand size depends on REX.W / VEX.W.  */
724
  dq_mode,
725
  /* Displacements like v_mode without considering Intel64 ISA.  */
726
  dqw_mode,
727
  /* bounds operand */
728
  bnd_mode,
729
  /* bounds operand with operand swapped */
730
  bnd_swap_mode,
731
  /* 4- or 6-byte pointer operand */
732
  f_mode,
733
  const_1_mode,
734
  /* v_mode for indirect branch opcodes.  */
735
  indir_v_mode,
736
  /* v_mode for stack-related opcodes.  */
737
  stack_v_mode,
738
  /* non-quad operand size depends on prefixes */
739
  z_mode,
740
  /* 16-byte operand */
741
  o_mode,
742
  /* registers like d_mode, memory like b_mode.  */
743
  db_mode,
744
  /* registers like d_mode, memory like w_mode.  */
745
  dw_mode,
746
747
  /* Operand size depends on the VEX.W bit, with VSIB dword indices.  */
748
  vex_vsib_d_w_dq_mode,
749
  /* Operand size depends on the VEX.W bit, with VSIB qword indices.  */
750
  vex_vsib_q_w_dq_mode,
751
  /* mandatory non-vector SIB.  */
752
  vex_sibmem_mode,
753
754
  /* scalar, ignore vector length.  */
755
  scalar_mode,
756
757
  /* Static rounding.  */
758
  evex_rounding_mode,
759
  /* Static rounding, 64-bit mode only.  */
760
  evex_rounding_64_mode,
761
  /* Supress all exceptions.  */
762
  evex_sae_mode,
763
764
  /* Mask register operand.  */
765
  mask_mode,
766
  /* Mask register operand.  */
767
  mask_bd_mode,
768
769
  es_reg,
770
  cs_reg,
771
  ss_reg,
772
  ds_reg,
773
  fs_reg,
774
  gs_reg,
775
776
  eAX_reg,
777
  eCX_reg,
778
  eDX_reg,
779
  eBX_reg,
780
  eSP_reg,
781
  eBP_reg,
782
  eSI_reg,
783
  eDI_reg,
784
785
  al_reg,
786
  cl_reg,
787
  dl_reg,
788
  bl_reg,
789
  ah_reg,
790
  ch_reg,
791
  dh_reg,
792
  bh_reg,
793
794
  ax_reg,
795
  cx_reg,
796
  dx_reg,
797
  bx_reg,
798
  sp_reg,
799
  bp_reg,
800
  si_reg,
801
  di_reg,
802
803
  rAX_reg,
804
  rCX_reg,
805
  rDX_reg,
806
  rBX_reg,
807
  rSP_reg,
808
  rBP_reg,
809
  rSI_reg,
810
  rDI_reg,
811
812
  z_mode_ax_reg,
813
  indir_dx_reg
814
};
815
816
enum
817
{
818
  FLOATCODE = 1,
819
  USE_REG_TABLE,
820
  USE_MOD_TABLE,
821
  USE_RM_TABLE,
822
  USE_PREFIX_TABLE,
823
  USE_X86_64_TABLE,
824
  USE_X86_64_EVEX_FROM_VEX_TABLE,
825
  USE_X86_64_EVEX_PFX_TABLE,
826
  USE_X86_64_EVEX_W_TABLE,
827
  USE_X86_64_EVEX_MEM_W_TABLE,
828
  USE_3BYTE_TABLE,
829
  USE_XOP_8F_TABLE,
830
  USE_VEX_C4_TABLE,
831
  USE_VEX_C5_TABLE,
832
  USE_VEX_LEN_TABLE,
833
  USE_VEX_W_TABLE,
834
  USE_EVEX_TABLE,
835
  USE_EVEX_LEN_TABLE
836
};
837
838
#define FLOAT     NULL, { { NULL, FLOATCODE } }, 0
839
840
#define DIS386(T, I)    NULL, { { NULL, (T)}, { NULL,  (I) } }, 0
841
#define REG_TABLE(I)    DIS386 (USE_REG_TABLE, (I))
842
#define MOD_TABLE(I)    DIS386 (USE_MOD_TABLE, (I))
843
#define RM_TABLE(I)   DIS386 (USE_RM_TABLE, (I))
844
#define PREFIX_TABLE(I)   DIS386 (USE_PREFIX_TABLE, (I))
845
#define X86_64_TABLE(I)   DIS386 (USE_X86_64_TABLE, (I))
846
#define X86_64_EVEX_FROM_VEX_TABLE(I) \
847
  DIS386 (USE_X86_64_EVEX_FROM_VEX_TABLE, (I))
848
#define X86_64_EVEX_PFX_TABLE(I) DIS386 (USE_X86_64_EVEX_PFX_TABLE, (I))
849
#define X86_64_EVEX_W_TABLE(I) DIS386 (USE_X86_64_EVEX_W_TABLE, (I))
850
#define X86_64_EVEX_MEM_W_TABLE(I) DIS386 (USE_X86_64_EVEX_MEM_W_TABLE, (I))
851
#define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
852
#define XOP_8F_TABLE()    DIS386 (USE_XOP_8F_TABLE, 0)
853
#define VEX_C4_TABLE()    DIS386 (USE_VEX_C4_TABLE, 0)
854
#define VEX_C5_TABLE()    DIS386 (USE_VEX_C5_TABLE, 0)
855
#define VEX_LEN_TABLE(I)  DIS386 (USE_VEX_LEN_TABLE, (I))
856
#define VEX_W_TABLE(I)    DIS386 (USE_VEX_W_TABLE, (I))
857
#define EVEX_TABLE()    DIS386 (USE_EVEX_TABLE, 0)
858
#define EVEX_LEN_TABLE(I) DIS386 (USE_EVEX_LEN_TABLE, (I))
859
860
enum
861
{
862
  REG_80 = 0,
863
  REG_81,
864
  REG_83,
865
  REG_8F,
866
  REG_C0,
867
  REG_C1,
868
  REG_C6,
869
  REG_C7,
870
  REG_D0,
871
  REG_D1,
872
  REG_D2,
873
  REG_D3,
874
  REG_F6,
875
  REG_F7,
876
  REG_FE,
877
  REG_FF,
878
  REG_0F00,
879
  REG_0F01,
880
  REG_0F0D,
881
  REG_0F18,
882
  REG_0F1C_P_0_MOD_0,
883
  REG_0F1E_P_1_MOD_3,
884
  REG_0F38D8_PREFIX_1,
885
  REG_0F3A0F_P_1,
886
  REG_0F71,
887
  REG_0F72,
888
  REG_0F73,
889
  REG_0FA6,
890
  REG_0FA7,
891
  REG_0FAE,
892
  REG_0FBA,
893
  REG_0FC7,
894
  REG_VEX_0F71,
895
  REG_VEX_0F72,
896
  REG_VEX_0F73,
897
  REG_VEX_0FAE,
898
  REG_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0,
899
  REG_VEX_0F38F3_L_0_P_0,
900
  REG_VEX_MAP7_F8_L_0_W_0,
901
902
  REG_XOP_09_01_L_0,
903
  REG_XOP_09_02_L_0,
904
  REG_XOP_09_12_L_0,
905
  REG_XOP_0A_12_L_0,
906
907
  REG_EVEX_0F71,
908
  REG_EVEX_0F72,
909
  REG_EVEX_0F73,
910
  REG_EVEX_0F38C6_L_2,
911
  REG_EVEX_0F38C7_L_2,
912
  REG_EVEX_MAP4_80,
913
  REG_EVEX_MAP4_81,
914
  REG_EVEX_MAP4_83,
915
  REG_EVEX_MAP4_8F,
916
  REG_EVEX_MAP4_F6,
917
  REG_EVEX_MAP4_F7,
918
  REG_EVEX_MAP4_FE,
919
  REG_EVEX_MAP4_FF,
920
};
921
922
enum
923
{
924
  MOD_62_32BIT = 0,
925
  MOD_C4_32BIT,
926
  MOD_C5_32BIT,
927
  MOD_0F01_REG_0,
928
  MOD_0F01_REG_1,
929
  MOD_0F01_REG_2,
930
  MOD_0F01_REG_3,
931
  MOD_0F01_REG_5,
932
  MOD_0F01_REG_7,
933
  MOD_0F12_PREFIX_0,
934
  MOD_0F16_PREFIX_0,
935
  MOD_0F18_REG_0,
936
  MOD_0F18_REG_1,
937
  MOD_0F18_REG_2,
938
  MOD_0F18_REG_3,
939
  MOD_0F18_REG_6,
940
  MOD_0F18_REG_7,
941
  MOD_0F1A_PREFIX_0,
942
  MOD_0F1B_PREFIX_0,
943
  MOD_0F1B_PREFIX_1,
944
  MOD_0F1C_PREFIX_0,
945
  MOD_0F1E_PREFIX_1,
946
  MOD_0FAE_REG_0,
947
  MOD_0FAE_REG_1,
948
  MOD_0FAE_REG_2,
949
  MOD_0FAE_REG_3,
950
  MOD_0FAE_REG_4,
951
  MOD_0FAE_REG_5,
952
  MOD_0FAE_REG_6,
953
  MOD_0FAE_REG_7,
954
  MOD_0FC7_REG_6,
955
  MOD_0FC7_REG_7,
956
  MOD_0F38DC_PREFIX_1,
957
  MOD_0F38F8,
958
959
  MOD_VEX_0F3849_X86_64_L_0_W_0,
960
961
  MOD_EVEX_MAP4_F8_P_1,
962
  MOD_EVEX_MAP4_F8_P_3,
963
};
964
965
enum
966
{
967
  RM_C6_REG_7 = 0,
968
  RM_C7_REG_7,
969
  RM_0F01_REG_0,
970
  RM_0F01_REG_1,
971
  RM_0F01_REG_2,
972
  RM_0F01_REG_3,
973
  RM_0F01_REG_5_MOD_3,
974
  RM_0F01_REG_7_MOD_3,
975
  RM_0F1E_P_1_MOD_3_REG_7,
976
  RM_0FAE_REG_6_MOD_3_P_0,
977
  RM_0FAE_REG_7_MOD_3,
978
  RM_0F3A0F_P_1_R_0,
979
980
  RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0_R_0,
981
  RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_3,
982
};
983
984
enum
985
{
986
  PREFIX_90 = 0,
987
  PREFIX_0F00_REG_6_X86_64,
988
  PREFIX_0F01_REG_0_MOD_3_RM_6,
989
  PREFIX_0F01_REG_0_MOD_3_RM_7,
990
  PREFIX_0F01_REG_1_RM_2,
991
  PREFIX_0F01_REG_1_RM_4,
992
  PREFIX_0F01_REG_1_RM_5,
993
  PREFIX_0F01_REG_1_RM_6,
994
  PREFIX_0F01_REG_1_RM_7,
995
  PREFIX_0F01_REG_3_RM_1,
996
  PREFIX_0F01_REG_5_MOD_0,
997
  PREFIX_0F01_REG_5_MOD_3_RM_0,
998
  PREFIX_0F01_REG_5_MOD_3_RM_1,
999
  PREFIX_0F01_REG_5_MOD_3_RM_2,
1000
  PREFIX_0F01_REG_5_MOD_3_RM_4,
1001
  PREFIX_0F01_REG_5_MOD_3_RM_5,
1002
  PREFIX_0F01_REG_5_MOD_3_RM_6,
1003
  PREFIX_0F01_REG_5_MOD_3_RM_7,
1004
  PREFIX_0F01_REG_7_MOD_3_RM_2,
1005
  PREFIX_0F01_REG_7_MOD_3_RM_5,
1006
  PREFIX_0F01_REG_7_MOD_3_RM_6,
1007
  PREFIX_0F01_REG_7_MOD_3_RM_7,
1008
  PREFIX_0F09,
1009
  PREFIX_0F10,
1010
  PREFIX_0F11,
1011
  PREFIX_0F12,
1012
  PREFIX_0F16,
1013
  PREFIX_0F18_REG_6_MOD_0_X86_64,
1014
  PREFIX_0F18_REG_7_MOD_0_X86_64,
1015
  PREFIX_0F1A,
1016
  PREFIX_0F1B,
1017
  PREFIX_0F1C,
1018
  PREFIX_0F1E,
1019
  PREFIX_0F2A,
1020
  PREFIX_0F2B,
1021
  PREFIX_0F2C,
1022
  PREFIX_0F2D,
1023
  PREFIX_0F2E,
1024
  PREFIX_0F2F,
1025
  PREFIX_0F51,
1026
  PREFIX_0F52,
1027
  PREFIX_0F53,
1028
  PREFIX_0F58,
1029
  PREFIX_0F59,
1030
  PREFIX_0F5A,
1031
  PREFIX_0F5B,
1032
  PREFIX_0F5C,
1033
  PREFIX_0F5D,
1034
  PREFIX_0F5E,
1035
  PREFIX_0F5F,
1036
  PREFIX_0F60,
1037
  PREFIX_0F61,
1038
  PREFIX_0F62,
1039
  PREFIX_0F6F,
1040
  PREFIX_0F70,
1041
  PREFIX_0F78,
1042
  PREFIX_0F79,
1043
  PREFIX_0F7C,
1044
  PREFIX_0F7D,
1045
  PREFIX_0F7E,
1046
  PREFIX_0F7F,
1047
  PREFIX_0FAE_REG_0_MOD_3,
1048
  PREFIX_0FAE_REG_1_MOD_3,
1049
  PREFIX_0FAE_REG_2_MOD_3,
1050
  PREFIX_0FAE_REG_3_MOD_3,
1051
  PREFIX_0FAE_REG_4_MOD_0,
1052
  PREFIX_0FAE_REG_4_MOD_3,
1053
  PREFIX_0FAE_REG_5_MOD_3,
1054
  PREFIX_0FAE_REG_6_MOD_0,
1055
  PREFIX_0FAE_REG_6_MOD_3,
1056
  PREFIX_0FAE_REG_7_MOD_0,
1057
  PREFIX_0FB8,
1058
  PREFIX_0FBC,
1059
  PREFIX_0FBD,
1060
  PREFIX_0FC2,
1061
  PREFIX_0FC7_REG_6_MOD_0,
1062
  PREFIX_0FC7_REG_6_MOD_3,
1063
  PREFIX_0FC7_REG_7_MOD_3,
1064
  PREFIX_0FD0,
1065
  PREFIX_0FD6,
1066
  PREFIX_0FE6,
1067
  PREFIX_0FE7,
1068
  PREFIX_0FF0,
1069
  PREFIX_0FF7,
1070
  PREFIX_0F38D8,
1071
  PREFIX_0F38DC,
1072
  PREFIX_0F38DD,
1073
  PREFIX_0F38DE,
1074
  PREFIX_0F38DF,
1075
  PREFIX_0F38F0,
1076
  PREFIX_0F38F1,
1077
  PREFIX_0F38F6,
1078
  PREFIX_0F38F8_M_0,
1079
  PREFIX_0F38F8_M_1_X86_64,
1080
  PREFIX_0F38FA,
1081
  PREFIX_0F38FB,
1082
  PREFIX_0F38FC,
1083
  PREFIX_0F3A0F,
1084
  PREFIX_VEX_0F12,
1085
  PREFIX_VEX_0F16,
1086
  PREFIX_VEX_0F2A,
1087
  PREFIX_VEX_0F2C,
1088
  PREFIX_VEX_0F2D,
1089
  PREFIX_VEX_0F41_L_1_W_0,
1090
  PREFIX_VEX_0F41_L_1_W_1,
1091
  PREFIX_VEX_0F42_L_1_W_0,
1092
  PREFIX_VEX_0F42_L_1_W_1,
1093
  PREFIX_VEX_0F44_L_0_W_0,
1094
  PREFIX_VEX_0F44_L_0_W_1,
1095
  PREFIX_VEX_0F45_L_1_W_0,
1096
  PREFIX_VEX_0F45_L_1_W_1,
1097
  PREFIX_VEX_0F46_L_1_W_0,
1098
  PREFIX_VEX_0F46_L_1_W_1,
1099
  PREFIX_VEX_0F47_L_1_W_0,
1100
  PREFIX_VEX_0F47_L_1_W_1,
1101
  PREFIX_VEX_0F4A_L_1_W_0,
1102
  PREFIX_VEX_0F4A_L_1_W_1,
1103
  PREFIX_VEX_0F4B_L_1_W_0,
1104
  PREFIX_VEX_0F4B_L_1_W_1,
1105
  PREFIX_VEX_0F6F,
1106
  PREFIX_VEX_0F70,
1107
  PREFIX_VEX_0F7E,
1108
  PREFIX_VEX_0F7F,
1109
  PREFIX_VEX_0F90_L_0_W_0,
1110
  PREFIX_VEX_0F90_L_0_W_1,
1111
  PREFIX_VEX_0F91_L_0_W_0,
1112
  PREFIX_VEX_0F91_L_0_W_1,
1113
  PREFIX_VEX_0F92_L_0_W_0,
1114
  PREFIX_VEX_0F92_L_0_W_1,
1115
  PREFIX_VEX_0F93_L_0_W_0,
1116
  PREFIX_VEX_0F93_L_0_W_1,
1117
  PREFIX_VEX_0F98_L_0_W_0,
1118
  PREFIX_VEX_0F98_L_0_W_1,
1119
  PREFIX_VEX_0F99_L_0_W_0,
1120
  PREFIX_VEX_0F99_L_0_W_1,
1121
  PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_0,
1122
  PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_1,
1123
  PREFIX_VEX_0F384B_X86_64_L_0_W_0,
1124
  PREFIX_VEX_0F3850_W_0,
1125
  PREFIX_VEX_0F3851_W_0,
1126
  PREFIX_VEX_0F385C_X86_64_L_0_W_0,
1127
  PREFIX_VEX_0F385E_X86_64_L_0_W_0,
1128
  PREFIX_VEX_0F386C_X86_64_L_0_W_0,
1129
  PREFIX_VEX_0F3872,
1130
  PREFIX_VEX_0F38B0_W_0,
1131
  PREFIX_VEX_0F38B1_W_0,
1132
  PREFIX_VEX_0F38D2_W_0,
1133
  PREFIX_VEX_0F38D3_W_0,
1134
  PREFIX_VEX_0F38CB,
1135
  PREFIX_VEX_0F38CC,
1136
  PREFIX_VEX_0F38CD,
1137
  PREFIX_VEX_0F38DA_W_0,
1138
  PREFIX_VEX_0F38F2_L_0,
1139
  PREFIX_VEX_0F38F3_L_0,
1140
  PREFIX_VEX_0F38F5_L_0,
1141
  PREFIX_VEX_0F38F6_L_0,
1142
  PREFIX_VEX_0F38F7_L_0,
1143
  PREFIX_VEX_0F3AF0_L_0,
1144
  PREFIX_VEX_MAP7_F8_L_0_W_0_R_0_X86_64,
1145
1146
  PREFIX_EVEX_0F5B,
1147
  PREFIX_EVEX_0F6F,
1148
  PREFIX_EVEX_0F70,
1149
  PREFIX_EVEX_0F78,
1150
  PREFIX_EVEX_0F79,
1151
  PREFIX_EVEX_0F7A,
1152
  PREFIX_EVEX_0F7B,
1153
  PREFIX_EVEX_0F7E,
1154
  PREFIX_EVEX_0F7F,
1155
  PREFIX_EVEX_0FC2,
1156
  PREFIX_EVEX_0FE6,
1157
  PREFIX_EVEX_0F3810,
1158
  PREFIX_EVEX_0F3811,
1159
  PREFIX_EVEX_0F3812,
1160
  PREFIX_EVEX_0F3813,
1161
  PREFIX_EVEX_0F3814,
1162
  PREFIX_EVEX_0F3815,
1163
  PREFIX_EVEX_0F3820,
1164
  PREFIX_EVEX_0F3821,
1165
  PREFIX_EVEX_0F3822,
1166
  PREFIX_EVEX_0F3823,
1167
  PREFIX_EVEX_0F3824,
1168
  PREFIX_EVEX_0F3825,
1169
  PREFIX_EVEX_0F3826,
1170
  PREFIX_EVEX_0F3827,
1171
  PREFIX_EVEX_0F3828,
1172
  PREFIX_EVEX_0F3829,
1173
  PREFIX_EVEX_0F382A,
1174
  PREFIX_EVEX_0F3830,
1175
  PREFIX_EVEX_0F3831,
1176
  PREFIX_EVEX_0F3832,
1177
  PREFIX_EVEX_0F3833,
1178
  PREFIX_EVEX_0F3834,
1179
  PREFIX_EVEX_0F3835,
1180
  PREFIX_EVEX_0F3838,
1181
  PREFIX_EVEX_0F3839,
1182
  PREFIX_EVEX_0F383A,
1183
  PREFIX_EVEX_0F3852,
1184
  PREFIX_EVEX_0F3853,
1185
  PREFIX_EVEX_0F3868,
1186
  PREFIX_EVEX_0F3872,
1187
  PREFIX_EVEX_0F389A,
1188
  PREFIX_EVEX_0F389B,
1189
  PREFIX_EVEX_0F38AA,
1190
  PREFIX_EVEX_0F38AB,
1191
1192
  PREFIX_EVEX_0F3A08,
1193
  PREFIX_EVEX_0F3A0A,
1194
  PREFIX_EVEX_0F3A26,
1195
  PREFIX_EVEX_0F3A27,
1196
  PREFIX_EVEX_0F3A56,
1197
  PREFIX_EVEX_0F3A57,
1198
  PREFIX_EVEX_0F3A66,
1199
  PREFIX_EVEX_0F3A67,
1200
  PREFIX_EVEX_0F3AC2,
1201
1202
  PREFIX_EVEX_MAP4_F0,
1203
  PREFIX_EVEX_MAP4_F1,
1204
  PREFIX_EVEX_MAP4_F2,
1205
  PREFIX_EVEX_MAP4_F8,
1206
1207
  PREFIX_EVEX_MAP5_10,
1208
  PREFIX_EVEX_MAP5_11,
1209
  PREFIX_EVEX_MAP5_1D,
1210
  PREFIX_EVEX_MAP5_2A,
1211
  PREFIX_EVEX_MAP5_2C,
1212
  PREFIX_EVEX_MAP5_2D,
1213
  PREFIX_EVEX_MAP5_2E,
1214
  PREFIX_EVEX_MAP5_2F,
1215
  PREFIX_EVEX_MAP5_51,
1216
  PREFIX_EVEX_MAP5_58,
1217
  PREFIX_EVEX_MAP5_59,
1218
  PREFIX_EVEX_MAP5_5A,
1219
  PREFIX_EVEX_MAP5_5B,
1220
  PREFIX_EVEX_MAP5_5C,
1221
  PREFIX_EVEX_MAP5_5D,
1222
  PREFIX_EVEX_MAP5_5E,
1223
  PREFIX_EVEX_MAP5_5F,
1224
  PREFIX_EVEX_MAP5_78,
1225
  PREFIX_EVEX_MAP5_79,
1226
  PREFIX_EVEX_MAP5_7A,
1227
  PREFIX_EVEX_MAP5_7B,
1228
  PREFIX_EVEX_MAP5_7C,
1229
  PREFIX_EVEX_MAP5_7D,
1230
1231
  PREFIX_EVEX_MAP6_13,
1232
  PREFIX_EVEX_MAP6_56,
1233
  PREFIX_EVEX_MAP6_57,
1234
  PREFIX_EVEX_MAP6_D6,
1235
  PREFIX_EVEX_MAP6_D7,
1236
};
1237
1238
enum
1239
{
1240
  X86_64_06 = 0,
1241
  X86_64_07,
1242
  X86_64_0E,
1243
  X86_64_16,
1244
  X86_64_17,
1245
  X86_64_1E,
1246
  X86_64_1F,
1247
  X86_64_27,
1248
  X86_64_2F,
1249
  X86_64_37,
1250
  X86_64_3F,
1251
  X86_64_60,
1252
  X86_64_61,
1253
  X86_64_62,
1254
  X86_64_63,
1255
  X86_64_6D,
1256
  X86_64_6F,
1257
  X86_64_82,
1258
  X86_64_9A,
1259
  X86_64_C2,
1260
  X86_64_C3,
1261
  X86_64_C4,
1262
  X86_64_C5,
1263
  X86_64_CE,
1264
  X86_64_D4,
1265
  X86_64_D5,
1266
  X86_64_E8,
1267
  X86_64_E9,
1268
  X86_64_EA,
1269
  X86_64_0F00_REG_6,
1270
  X86_64_0F01_REG_0,
1271
  X86_64_0F01_REG_0_MOD_3_RM_6_P_1,
1272
  X86_64_0F01_REG_0_MOD_3_RM_6_P_3,
1273
  X86_64_0F01_REG_0_MOD_3_RM_7_P_0,
1274
  X86_64_0F01_REG_1,
1275
  X86_64_0F01_REG_1_RM_2_PREFIX_1,
1276
  X86_64_0F01_REG_1_RM_2_PREFIX_3,
1277
  X86_64_0F01_REG_1_RM_5_PREFIX_2,
1278
  X86_64_0F01_REG_1_RM_6_PREFIX_2,
1279
  X86_64_0F01_REG_1_RM_7_PREFIX_2,
1280
  X86_64_0F01_REG_2,
1281
  X86_64_0F01_REG_3,
1282
  X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1,
1283
  X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1,
1284
  X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1,
1285
  X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1,
1286
  X86_64_0F01_REG_7_MOD_3_RM_5_PREFIX_1,
1287
  X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1,
1288
  X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3,
1289
  X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1,
1290
  X86_64_0F18_REG_6_MOD_0,
1291
  X86_64_0F18_REG_7_MOD_0,
1292
  X86_64_0F24,
1293
  X86_64_0F26,
1294
  X86_64_0F38F8_M_1,
1295
  X86_64_0FC7_REG_6_MOD_3_PREFIX_1,
1296
1297
  X86_64_VEX_0F3849,
1298
  X86_64_VEX_0F384B,
1299
  X86_64_VEX_0F385C,
1300
  X86_64_VEX_0F385E,
1301
  X86_64_VEX_0F386C,
1302
  X86_64_VEX_0F38E0,
1303
  X86_64_VEX_0F38E1,
1304
  X86_64_VEX_0F38E2,
1305
  X86_64_VEX_0F38E3,
1306
  X86_64_VEX_0F38E4,
1307
  X86_64_VEX_0F38E5,
1308
  X86_64_VEX_0F38E6,
1309
  X86_64_VEX_0F38E7,
1310
  X86_64_VEX_0F38E8,
1311
  X86_64_VEX_0F38E9,
1312
  X86_64_VEX_0F38EA,
1313
  X86_64_VEX_0F38EB,
1314
  X86_64_VEX_0F38EC,
1315
  X86_64_VEX_0F38ED,
1316
  X86_64_VEX_0F38EE,
1317
  X86_64_VEX_0F38EF,
1318
1319
  X86_64_VEX_MAP7_F8_L_0_W_0_R_0,
1320
};
1321
1322
enum
1323
{
1324
  THREE_BYTE_0F38 = 0,
1325
  THREE_BYTE_0F3A
1326
};
1327
1328
enum
1329
{
1330
  XOP_08 = 0,
1331
  XOP_09,
1332
  XOP_0A
1333
};
1334
1335
enum
1336
{
1337
  VEX_0F = 0,
1338
  VEX_0F38,
1339
  VEX_0F3A,
1340
  VEX_MAP7,
1341
};
1342
1343
enum
1344
{
1345
  EVEX_0F = 0,
1346
  EVEX_0F38,
1347
  EVEX_0F3A,
1348
  EVEX_MAP4,
1349
  EVEX_MAP5,
1350
  EVEX_MAP6,
1351
  EVEX_MAP7,
1352
};
1353
1354
enum
1355
{
1356
  VEX_LEN_0F12_P_0 = 0,
1357
  VEX_LEN_0F12_P_2,
1358
  VEX_LEN_0F13,
1359
  VEX_LEN_0F16_P_0,
1360
  VEX_LEN_0F16_P_2,
1361
  VEX_LEN_0F17,
1362
  VEX_LEN_0F41,
1363
  VEX_LEN_0F42,
1364
  VEX_LEN_0F44,
1365
  VEX_LEN_0F45,
1366
  VEX_LEN_0F46,
1367
  VEX_LEN_0F47,
1368
  VEX_LEN_0F4A,
1369
  VEX_LEN_0F4B,
1370
  VEX_LEN_0F6E,
1371
  VEX_LEN_0F77,
1372
  VEX_LEN_0F7E_P_1,
1373
  VEX_LEN_0F7E_P_2,
1374
  VEX_LEN_0F90,
1375
  VEX_LEN_0F91,
1376
  VEX_LEN_0F92,
1377
  VEX_LEN_0F93,
1378
  VEX_LEN_0F98,
1379
  VEX_LEN_0F99,
1380
  VEX_LEN_0FAE_R_2,
1381
  VEX_LEN_0FAE_R_3,
1382
  VEX_LEN_0FC4,
1383
  VEX_LEN_0FD6,
1384
  VEX_LEN_0F3816,
1385
  VEX_LEN_0F3819,
1386
  VEX_LEN_0F381A,
1387
  VEX_LEN_0F3836,
1388
  VEX_LEN_0F3841,
1389
  VEX_LEN_0F3849_X86_64,
1390
  VEX_LEN_0F384B_X86_64,
1391
  VEX_LEN_0F385A,
1392
  VEX_LEN_0F385C_X86_64,
1393
  VEX_LEN_0F385E_X86_64,
1394
  VEX_LEN_0F386C_X86_64,
1395
  VEX_LEN_0F38CB_P_3_W_0,
1396
  VEX_LEN_0F38CC_P_3_W_0,
1397
  VEX_LEN_0F38CD_P_3_W_0,
1398
  VEX_LEN_0F38DA_W_0_P_0,
1399
  VEX_LEN_0F38DA_W_0_P_2,
1400
  VEX_LEN_0F38DB,
1401
  VEX_LEN_0F38F2,
1402
  VEX_LEN_0F38F3,
1403
  VEX_LEN_0F38F5,
1404
  VEX_LEN_0F38F6,
1405
  VEX_LEN_0F38F7,
1406
  VEX_LEN_0F3A00,
1407
  VEX_LEN_0F3A01,
1408
  VEX_LEN_0F3A06,
1409
  VEX_LEN_0F3A14,
1410
  VEX_LEN_0F3A15,
1411
  VEX_LEN_0F3A16,
1412
  VEX_LEN_0F3A17,
1413
  VEX_LEN_0F3A18,
1414
  VEX_LEN_0F3A19,
1415
  VEX_LEN_0F3A20,
1416
  VEX_LEN_0F3A21,
1417
  VEX_LEN_0F3A22,
1418
  VEX_LEN_0F3A30,
1419
  VEX_LEN_0F3A31,
1420
  VEX_LEN_0F3A32,
1421
  VEX_LEN_0F3A33,
1422
  VEX_LEN_0F3A38,
1423
  VEX_LEN_0F3A39,
1424
  VEX_LEN_0F3A41,
1425
  VEX_LEN_0F3A46,
1426
  VEX_LEN_0F3A60,
1427
  VEX_LEN_0F3A61,
1428
  VEX_LEN_0F3A62,
1429
  VEX_LEN_0F3A63,
1430
  VEX_LEN_0F3ADE_W_0,
1431
  VEX_LEN_0F3ADF,
1432
  VEX_LEN_0F3AF0,
1433
  VEX_LEN_MAP7_F8,
1434
  VEX_LEN_XOP_08_85,
1435
  VEX_LEN_XOP_08_86,
1436
  VEX_LEN_XOP_08_87,
1437
  VEX_LEN_XOP_08_8E,
1438
  VEX_LEN_XOP_08_8F,
1439
  VEX_LEN_XOP_08_95,
1440
  VEX_LEN_XOP_08_96,
1441
  VEX_LEN_XOP_08_97,
1442
  VEX_LEN_XOP_08_9E,
1443
  VEX_LEN_XOP_08_9F,
1444
  VEX_LEN_XOP_08_A3,
1445
  VEX_LEN_XOP_08_A6,
1446
  VEX_LEN_XOP_08_B6,
1447
  VEX_LEN_XOP_08_C0,
1448
  VEX_LEN_XOP_08_C1,
1449
  VEX_LEN_XOP_08_C2,
1450
  VEX_LEN_XOP_08_C3,
1451
  VEX_LEN_XOP_08_CC,
1452
  VEX_LEN_XOP_08_CD,
1453
  VEX_LEN_XOP_08_CE,
1454
  VEX_LEN_XOP_08_CF,
1455
  VEX_LEN_XOP_08_EC,
1456
  VEX_LEN_XOP_08_ED,
1457
  VEX_LEN_XOP_08_EE,
1458
  VEX_LEN_XOP_08_EF,
1459
  VEX_LEN_XOP_09_01,
1460
  VEX_LEN_XOP_09_02,
1461
  VEX_LEN_XOP_09_12,
1462
  VEX_LEN_XOP_09_82_W_0,
1463
  VEX_LEN_XOP_09_83_W_0,
1464
  VEX_LEN_XOP_09_90,
1465
  VEX_LEN_XOP_09_91,
1466
  VEX_LEN_XOP_09_92,
1467
  VEX_LEN_XOP_09_93,
1468
  VEX_LEN_XOP_09_94,
1469
  VEX_LEN_XOP_09_95,
1470
  VEX_LEN_XOP_09_96,
1471
  VEX_LEN_XOP_09_97,
1472
  VEX_LEN_XOP_09_98,
1473
  VEX_LEN_XOP_09_99,
1474
  VEX_LEN_XOP_09_9A,
1475
  VEX_LEN_XOP_09_9B,
1476
  VEX_LEN_XOP_09_C1,
1477
  VEX_LEN_XOP_09_C2,
1478
  VEX_LEN_XOP_09_C3,
1479
  VEX_LEN_XOP_09_C6,
1480
  VEX_LEN_XOP_09_C7,
1481
  VEX_LEN_XOP_09_CB,
1482
  VEX_LEN_XOP_09_D1,
1483
  VEX_LEN_XOP_09_D2,
1484
  VEX_LEN_XOP_09_D3,
1485
  VEX_LEN_XOP_09_D6,
1486
  VEX_LEN_XOP_09_D7,
1487
  VEX_LEN_XOP_09_DB,
1488
  VEX_LEN_XOP_09_E1,
1489
  VEX_LEN_XOP_09_E2,
1490
  VEX_LEN_XOP_09_E3,
1491
  VEX_LEN_XOP_0A_12,
1492
};
1493
1494
enum
1495
{
1496
  EVEX_LEN_0F3816 = 0,
1497
  EVEX_LEN_0F3819,
1498
  EVEX_LEN_0F381A,
1499
  EVEX_LEN_0F381B,
1500
  EVEX_LEN_0F3836,
1501
  EVEX_LEN_0F385A,
1502
  EVEX_LEN_0F385B,
1503
  EVEX_LEN_0F38C6,
1504
  EVEX_LEN_0F38C7,
1505
  EVEX_LEN_0F3A00,
1506
  EVEX_LEN_0F3A01,
1507
  EVEX_LEN_0F3A18,
1508
  EVEX_LEN_0F3A19,
1509
  EVEX_LEN_0F3A1A,
1510
  EVEX_LEN_0F3A1B,
1511
  EVEX_LEN_0F3A23,
1512
  EVEX_LEN_0F3A38,
1513
  EVEX_LEN_0F3A39,
1514
  EVEX_LEN_0F3A3A,
1515
  EVEX_LEN_0F3A3B,
1516
  EVEX_LEN_0F3A43
1517
};
1518
1519
enum
1520
{
1521
  VEX_W_0F41_L_1 = 0,
1522
  VEX_W_0F42_L_1,
1523
  VEX_W_0F44_L_0,
1524
  VEX_W_0F45_L_1,
1525
  VEX_W_0F46_L_1,
1526
  VEX_W_0F47_L_1,
1527
  VEX_W_0F4A_L_1,
1528
  VEX_W_0F4B_L_1,
1529
  VEX_W_0F90_L_0,
1530
  VEX_W_0F91_L_0,
1531
  VEX_W_0F92_L_0,
1532
  VEX_W_0F93_L_0,
1533
  VEX_W_0F98_L_0,
1534
  VEX_W_0F99_L_0,
1535
  VEX_W_0F380C,
1536
  VEX_W_0F380D,
1537
  VEX_W_0F380E,
1538
  VEX_W_0F380F,
1539
  VEX_W_0F3813,
1540
  VEX_W_0F3816_L_1,
1541
  VEX_W_0F3818,
1542
  VEX_W_0F3819_L_1,
1543
  VEX_W_0F381A_L_1,
1544
  VEX_W_0F382C,
1545
  VEX_W_0F382D,
1546
  VEX_W_0F382E,
1547
  VEX_W_0F382F,
1548
  VEX_W_0F3836,
1549
  VEX_W_0F3846,
1550
  VEX_W_0F3849_X86_64_L_0,
1551
  VEX_W_0F384B_X86_64_L_0,
1552
  VEX_W_0F3850,
1553
  VEX_W_0F3851,
1554
  VEX_W_0F3852,
1555
  VEX_W_0F3853,
1556
  VEX_W_0F3858,
1557
  VEX_W_0F3859,
1558
  VEX_W_0F385A_L_0,
1559
  VEX_W_0F385C_X86_64_L_0,
1560
  VEX_W_0F385E_X86_64_L_0,
1561
  VEX_W_0F386C_X86_64_L_0,
1562
  VEX_W_0F3872_P_1,
1563
  VEX_W_0F3878,
1564
  VEX_W_0F3879,
1565
  VEX_W_0F38B0,
1566
  VEX_W_0F38B1,
1567
  VEX_W_0F38B4,
1568
  VEX_W_0F38B5,
1569
  VEX_W_0F38CB_P_3,
1570
  VEX_W_0F38CC_P_3,
1571
  VEX_W_0F38CD_P_3,
1572
  VEX_W_0F38CF,
1573
  VEX_W_0F38D2,
1574
  VEX_W_0F38D3,
1575
  VEX_W_0F38DA,
1576
  VEX_W_0F3A00_L_1,
1577
  VEX_W_0F3A01_L_1,
1578
  VEX_W_0F3A02,
1579
  VEX_W_0F3A04,
1580
  VEX_W_0F3A05,
1581
  VEX_W_0F3A06_L_1,
1582
  VEX_W_0F3A18_L_1,
1583
  VEX_W_0F3A19_L_1,
1584
  VEX_W_0F3A1D,
1585
  VEX_W_0F3A38_L_1,
1586
  VEX_W_0F3A39_L_1,
1587
  VEX_W_0F3A46_L_1,
1588
  VEX_W_0F3A4A,
1589
  VEX_W_0F3A4B,
1590
  VEX_W_0F3A4C,
1591
  VEX_W_0F3ACE,
1592
  VEX_W_0F3ACF,
1593
  VEX_W_0F3ADE,
1594
  VEX_W_MAP7_F8_L_0,
1595
1596
  VEX_W_XOP_08_85_L_0,
1597
  VEX_W_XOP_08_86_L_0,
1598
  VEX_W_XOP_08_87_L_0,
1599
  VEX_W_XOP_08_8E_L_0,
1600
  VEX_W_XOP_08_8F_L_0,
1601
  VEX_W_XOP_08_95_L_0,
1602
  VEX_W_XOP_08_96_L_0,
1603
  VEX_W_XOP_08_97_L_0,
1604
  VEX_W_XOP_08_9E_L_0,
1605
  VEX_W_XOP_08_9F_L_0,
1606
  VEX_W_XOP_08_A6_L_0,
1607
  VEX_W_XOP_08_B6_L_0,
1608
  VEX_W_XOP_08_C0_L_0,
1609
  VEX_W_XOP_08_C1_L_0,
1610
  VEX_W_XOP_08_C2_L_0,
1611
  VEX_W_XOP_08_C3_L_0,
1612
  VEX_W_XOP_08_CC_L_0,
1613
  VEX_W_XOP_08_CD_L_0,
1614
  VEX_W_XOP_08_CE_L_0,
1615
  VEX_W_XOP_08_CF_L_0,
1616
  VEX_W_XOP_08_EC_L_0,
1617
  VEX_W_XOP_08_ED_L_0,
1618
  VEX_W_XOP_08_EE_L_0,
1619
  VEX_W_XOP_08_EF_L_0,
1620
1621
  VEX_W_XOP_09_80,
1622
  VEX_W_XOP_09_81,
1623
  VEX_W_XOP_09_82,
1624
  VEX_W_XOP_09_83,
1625
  VEX_W_XOP_09_C1_L_0,
1626
  VEX_W_XOP_09_C2_L_0,
1627
  VEX_W_XOP_09_C3_L_0,
1628
  VEX_W_XOP_09_C6_L_0,
1629
  VEX_W_XOP_09_C7_L_0,
1630
  VEX_W_XOP_09_CB_L_0,
1631
  VEX_W_XOP_09_D1_L_0,
1632
  VEX_W_XOP_09_D2_L_0,
1633
  VEX_W_XOP_09_D3_L_0,
1634
  VEX_W_XOP_09_D6_L_0,
1635
  VEX_W_XOP_09_D7_L_0,
1636
  VEX_W_XOP_09_DB_L_0,
1637
  VEX_W_XOP_09_E1_L_0,
1638
  VEX_W_XOP_09_E2_L_0,
1639
  VEX_W_XOP_09_E3_L_0,
1640
1641
  EVEX_W_0F5B_P_0,
1642
  EVEX_W_0F62,
1643
  EVEX_W_0F66,
1644
  EVEX_W_0F6A,
1645
  EVEX_W_0F6B,
1646
  EVEX_W_0F6C,
1647
  EVEX_W_0F6D,
1648
  EVEX_W_0F6F_P_1,
1649
  EVEX_W_0F6F_P_2,
1650
  EVEX_W_0F6F_P_3,
1651
  EVEX_W_0F70_P_2,
1652
  EVEX_W_0F72_R_2,
1653
  EVEX_W_0F72_R_6,
1654
  EVEX_W_0F73_R_2,
1655
  EVEX_W_0F73_R_6,
1656
  EVEX_W_0F76,
1657
  EVEX_W_0F78_P_0,
1658
  EVEX_W_0F78_P_2,
1659
  EVEX_W_0F79_P_0,
1660
  EVEX_W_0F79_P_2,
1661
  EVEX_W_0F7A_P_1,
1662
  EVEX_W_0F7A_P_2,
1663
  EVEX_W_0F7A_P_3,
1664
  EVEX_W_0F7B_P_2,
1665
  EVEX_W_0F7E_P_1,
1666
  EVEX_W_0F7F_P_1,
1667
  EVEX_W_0F7F_P_2,
1668
  EVEX_W_0F7F_P_3,
1669
  EVEX_W_0FD2,
1670
  EVEX_W_0FD3,
1671
  EVEX_W_0FD4,
1672
  EVEX_W_0FD6,
1673
  EVEX_W_0FE6_P_1,
1674
  EVEX_W_0FE7,
1675
  EVEX_W_0FF2,
1676
  EVEX_W_0FF3,
1677
  EVEX_W_0FF4,
1678
  EVEX_W_0FFA,
1679
  EVEX_W_0FFB,
1680
  EVEX_W_0FFE,
1681
1682
  EVEX_W_0F3810_P_1,
1683
  EVEX_W_0F3810_P_2,
1684
  EVEX_W_0F3811_P_1,
1685
  EVEX_W_0F3811_P_2,
1686
  EVEX_W_0F3812_P_1,
1687
  EVEX_W_0F3812_P_2,
1688
  EVEX_W_0F3813_P_1,
1689
  EVEX_W_0F3814_P_1,
1690
  EVEX_W_0F3815_P_1,
1691
  EVEX_W_0F3819_L_n,
1692
  EVEX_W_0F381A_L_n,
1693
  EVEX_W_0F381B_L_2,
1694
  EVEX_W_0F381E,
1695
  EVEX_W_0F381F,
1696
  EVEX_W_0F3820_P_1,
1697
  EVEX_W_0F3821_P_1,
1698
  EVEX_W_0F3822_P_1,
1699
  EVEX_W_0F3823_P_1,
1700
  EVEX_W_0F3824_P_1,
1701
  EVEX_W_0F3825_P_1,
1702
  EVEX_W_0F3825_P_2,
1703
  EVEX_W_0F3828_P_2,
1704
  EVEX_W_0F3829_P_2,
1705
  EVEX_W_0F382A_P_1,
1706
  EVEX_W_0F382A_P_2,
1707
  EVEX_W_0F382B,
1708
  EVEX_W_0F3830_P_1,
1709
  EVEX_W_0F3831_P_1,
1710
  EVEX_W_0F3832_P_1,
1711
  EVEX_W_0F3833_P_1,
1712
  EVEX_W_0F3834_P_1,
1713
  EVEX_W_0F3835_P_1,
1714
  EVEX_W_0F3835_P_2,
1715
  EVEX_W_0F3837,
1716
  EVEX_W_0F383A_P_1,
1717
  EVEX_W_0F3859,
1718
  EVEX_W_0F385A_L_n,
1719
  EVEX_W_0F385B_L_2,
1720
  EVEX_W_0F3870,
1721
  EVEX_W_0F3872_P_2,
1722
  EVEX_W_0F387A,
1723
  EVEX_W_0F387B,
1724
  EVEX_W_0F3883,
1725
1726
  EVEX_W_0F3A18_L_n,
1727
  EVEX_W_0F3A19_L_n,
1728
  EVEX_W_0F3A1A_L_2,
1729
  EVEX_W_0F3A1B_L_2,
1730
  EVEX_W_0F3A21,
1731
  EVEX_W_0F3A23_L_n,
1732
  EVEX_W_0F3A38_L_n,
1733
  EVEX_W_0F3A39_L_n,
1734
  EVEX_W_0F3A3A_L_2,
1735
  EVEX_W_0F3A3B_L_2,
1736
  EVEX_W_0F3A42,
1737
  EVEX_W_0F3A43_L_n,
1738
  EVEX_W_0F3A70,
1739
  EVEX_W_0F3A72,
1740
1741
  EVEX_W_MAP4_8F_R_0,
1742
  EVEX_W_MAP4_F8_P1_M_1,
1743
  EVEX_W_MAP4_F8_P3_M_1,
1744
  EVEX_W_MAP4_FF_R_6,
1745
1746
  EVEX_W_MAP5_5B_P_0,
1747
  EVEX_W_MAP5_7A_P_3,
1748
};
1749
1750
typedef bool (*op_rtn) (instr_info *ins, int bytemode, int sizeflag);
1751
1752
struct dis386 {
1753
  const char *name;
1754
  struct
1755
    {
1756
      op_rtn rtn;
1757
      int bytemode;
1758
    } op[MAX_OPERANDS];
1759
  unsigned int prefix_requirement;
1760
};
1761
1762
/* Upper case letters in the instruction names here are macros.
1763
   'A' => print 'b' if no (suitable) register operand or suffix_always is true
1764
   'B' => print 'b' if suffix_always is true
1765
   'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
1766
    size prefix
1767
   'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
1768
    suffix_always is true
1769
   'E' => print 'e' if 32-bit form of jcxz
1770
   'F' => print 'w' or 'l' depending on address size prefix (loop insns)
1771
   'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
1772
   'H' => print ",pt" or ",pn" branch hint
1773
   'I' unused.
1774
   'J' unused.
1775
   'K' => print 'd' or 'q' if rex prefix is present.
1776
   'L' => print 'l' or 'q' if suffix_always is true
1777
   'M' => print 'r' if intel_mnemonic is false.
1778
   'N' => print 'n' if instruction has no wait "prefix"
1779
   'O' => print 'd' or 'o' (or 'q' in Intel mode)
1780
   'P' => behave as 'T' except with register operand outside of suffix_always
1781
    mode
1782
   'Q' => print 'w', 'l' or 'q' if no (suitable) register operand or
1783
    suffix_always is true
1784
   'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
1785
   'S' => print 'w', 'l' or 'q' if suffix_always is true
1786
   'T' => print 'w', 'l'/'d', or 'q' if instruction has an operand size
1787
    prefix or if suffix_always is true.
1788
   'U' unused.
1789
   'V' => print 'v' for VEX/EVEX and nothing for legacy encodings.
1790
   'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
1791
   'X' => print 's', 'd' depending on data16 prefix (for XMM)
1792
   'Y' => no output, mark EVEX.aaa != 0 as bad.
1793
   'Z' => print 'q' in 64bit mode and 'l' otherwise, if suffix_always is true.
1794
   '!' => change condition from true to false or from false to true.
1795
   '%' => add 1 upper case letter to the macro.
1796
   '^' => print 'w', 'l', or 'q' (Intel64 ISA only) depending on operand size
1797
    prefix or suffix_always is true (lcall/ljmp).
1798
   '@' => in 64bit mode for Intel64 ISA or if instruction
1799
    has no operand sizing prefix, print 'q' if suffix_always is true or
1800
    nothing otherwise; behave as 'P' in all other cases
1801
1802
   2 upper case letter macros:
1803
   "XY" => print 'x' or 'y' if suffix_always is true or no register
1804
     operands and no broadcast.
1805
   "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
1806
     register operands and no broadcast.
1807
   "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
1808
   "XD" => print 'd' if !EVEX or EVEX.W=1, EVEX.W=0 is not a valid encoding
1809
   "XH" => print 'h' if EVEX.W=0, EVEX.W=1 is not a valid encoding (for FP16)
1810
   "XS" => print 's' if !EVEX or EVEX.W=0, EVEX.W=1 is not a valid encoding
1811
   "XV" => print "{vex} " pseudo prefix
1812
   "XE" => print "{evex} " pseudo prefix if no EVEX-specific functionality is
1813
     is used by an EVEX-encoded (AVX512VL) instruction.
1814
   "ME" => print "{evex} " pseudo prefix for ins->modrm.mod != 3,if no
1815
     EVEX-specific functionality is used by an EVEX-encoded (AVX512VL)
1816
     instruction.
1817
   "NF" => print "{nf} " pseudo prefix when EVEX.NF = 1 and print "{evex} "
1818
     pseudo prefix when instructions without NF, EGPR and VVVV,
1819
   "YK" keep unused, to avoid ambiguity with the combined use of Y and K.
1820
   "YX" keep unused, to avoid ambiguity with the combined use of Y and X.
1821
   "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand, cond
1822
     being false, or no operand at all in 64bit mode, or if suffix_always
1823
     is true.
1824
   "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
1825
   "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
1826
   "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
1827
   "DQ" => print 'd' or 'q' depending on the VEX.W bit
1828
   "BW" => print 'b' or 'w' depending on the VEX.W bit
1829
   "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
1830
     an operand size prefix, or suffix_always is true.  print
1831
     'q' if rex prefix is present.
1832
1833
   Many of the above letters print nothing in Intel mode.  See "putop"
1834
   for the details.
1835
1836
   Braces '{' and '}', and vertical bars '|', indicate alternative
1837
   mnemonic strings for AT&T and Intel.  */
1838
1839
static const struct dis386 dis386[] = {
1840
  /* 00 */
1841
  { "addB",   { Ebh1, Gb }, 0 },
1842
  { "addS",   { Evh1, Gv }, 0 },
1843
  { "addB",   { Gb, EbS }, 0 },
1844
  { "addS",   { Gv, EvS }, 0 },
1845
  { "addB",   { AL, Ib }, 0 },
1846
  { "addS",   { eAX, Iv }, 0 },
1847
  { X86_64_TABLE (X86_64_06) },
1848
  { X86_64_TABLE (X86_64_07) },
1849
  /* 08 */
1850
  { "orB",    { Ebh1, Gb }, 0 },
1851
  { "orS",    { Evh1, Gv }, 0 },
1852
  { "orB",    { Gb, EbS }, 0 },
1853
  { "orS",    { Gv, EvS }, 0 },
1854
  { "orB",    { AL, Ib }, 0 },
1855
  { "orS",    { eAX, Iv }, 0 },
1856
  { X86_64_TABLE (X86_64_0E) },
1857
  { Bad_Opcode }, /* 0x0f extended opcode escape */
1858
  /* 10 */
1859
  { "adcB",   { Ebh1, Gb }, 0 },
1860
  { "adcS",   { Evh1, Gv }, 0 },
1861
  { "adcB",   { Gb, EbS }, 0 },
1862
  { "adcS",   { Gv, EvS }, 0 },
1863
  { "adcB",   { AL, Ib }, 0 },
1864
  { "adcS",   { eAX, Iv }, 0 },
1865
  { X86_64_TABLE (X86_64_16) },
1866
  { X86_64_TABLE (X86_64_17) },
1867
  /* 18 */
1868
  { "sbbB",   { Ebh1, Gb }, 0 },
1869
  { "sbbS",   { Evh1, Gv }, 0 },
1870
  { "sbbB",   { Gb, EbS }, 0 },
1871
  { "sbbS",   { Gv, EvS }, 0 },
1872
  { "sbbB",   { AL, Ib }, 0 },
1873
  { "sbbS",   { eAX, Iv }, 0 },
1874
  { X86_64_TABLE (X86_64_1E) },
1875
  { X86_64_TABLE (X86_64_1F) },
1876
  /* 20 */
1877
  { "andB",   { Ebh1, Gb }, 0 },
1878
  { "andS",   { Evh1, Gv }, 0 },
1879
  { "andB",   { Gb, EbS }, 0 },
1880
  { "andS",   { Gv, EvS }, 0 },
1881
  { "andB",   { AL, Ib }, 0 },
1882
  { "andS",   { eAX, Iv }, 0 },
1883
  { Bad_Opcode }, /* SEG ES prefix */
1884
  { X86_64_TABLE (X86_64_27) },
1885
  /* 28 */
1886
  { "subB",   { Ebh1, Gb }, 0 },
1887
  { "subS",   { Evh1, Gv }, 0 },
1888
  { "subB",   { Gb, EbS }, 0 },
1889
  { "subS",   { Gv, EvS }, 0 },
1890
  { "subB",   { AL, Ib }, 0 },
1891
  { "subS",   { eAX, Iv }, 0 },
1892
  { Bad_Opcode }, /* SEG CS prefix */
1893
  { X86_64_TABLE (X86_64_2F) },
1894
  /* 30 */
1895
  { "xorB",   { Ebh1, Gb }, 0 },
1896
  { "xorS",   { Evh1, Gv }, 0 },
1897
  { "xorB",   { Gb, EbS }, 0 },
1898
  { "xorS",   { Gv, EvS }, 0 },
1899
  { "xorB",   { AL, Ib }, 0 },
1900
  { "xorS",   { eAX, Iv }, 0 },
1901
  { Bad_Opcode }, /* SEG SS prefix */
1902
  { X86_64_TABLE (X86_64_37) },
1903
  /* 38 */
1904
  { "cmpB",   { Eb, Gb }, 0 },
1905
  { "cmpS",   { Ev, Gv }, 0 },
1906
  { "cmpB",   { Gb, EbS }, 0 },
1907
  { "cmpS",   { Gv, EvS }, 0 },
1908
  { "cmpB",   { AL, Ib }, 0 },
1909
  { "cmpS",   { eAX, Iv }, 0 },
1910
  { Bad_Opcode }, /* SEG DS prefix */
1911
  { X86_64_TABLE (X86_64_3F) },
1912
  /* 40 */
1913
  { "inc{S|}",    { RMeAX }, 0 },
1914
  { "inc{S|}",    { RMeCX }, 0 },
1915
  { "inc{S|}",    { RMeDX }, 0 },
1916
  { "inc{S|}",    { RMeBX }, 0 },
1917
  { "inc{S|}",    { RMeSP }, 0 },
1918
  { "inc{S|}",    { RMeBP }, 0 },
1919
  { "inc{S|}",    { RMeSI }, 0 },
1920
  { "inc{S|}",    { RMeDI }, 0 },
1921
  /* 48 */
1922
  { "dec{S|}",    { RMeAX }, 0 },
1923
  { "dec{S|}",    { RMeCX }, 0 },
1924
  { "dec{S|}",    { RMeDX }, 0 },
1925
  { "dec{S|}",    { RMeBX }, 0 },
1926
  { "dec{S|}",    { RMeSP }, 0 },
1927
  { "dec{S|}",    { RMeBP }, 0 },
1928
  { "dec{S|}",    { RMeSI }, 0 },
1929
  { "dec{S|}",    { RMeDI }, 0 },
1930
  /* 50 */
1931
  { "push!P",   { RMrAX }, 0 },
1932
  { "push!P",   { RMrCX }, 0 },
1933
  { "push!P",   { RMrDX }, 0 },
1934
  { "push!P",   { RMrBX }, 0 },
1935
  { "push!P",   { RMrSP }, 0 },
1936
  { "push!P",   { RMrBP }, 0 },
1937
  { "push!P",   { RMrSI }, 0 },
1938
  { "push!P",   { RMrDI }, 0 },
1939
  /* 58 */
1940
  { "pop!P",    { RMrAX }, 0 },
1941
  { "pop!P",    { RMrCX }, 0 },
1942
  { "pop!P",    { RMrDX }, 0 },
1943
  { "pop!P",    { RMrBX }, 0 },
1944
  { "pop!P",    { RMrSP }, 0 },
1945
  { "pop!P",    { RMrBP }, 0 },
1946
  { "pop!P",    { RMrSI }, 0 },
1947
  { "pop!P",    { RMrDI }, 0 },
1948
  /* 60 */
1949
  { X86_64_TABLE (X86_64_60) },
1950
  { X86_64_TABLE (X86_64_61) },
1951
  { X86_64_TABLE (X86_64_62) },
1952
  { X86_64_TABLE (X86_64_63) },
1953
  { Bad_Opcode }, /* seg fs */
1954
  { Bad_Opcode }, /* seg gs */
1955
  { Bad_Opcode }, /* op size prefix */
1956
  { Bad_Opcode }, /* adr size prefix */
1957
  /* 68 */
1958
  { "pushP",    { sIv }, 0 },
1959
  { "imulS",    { Gv, Ev, Iv }, 0 },
1960
  { "pushP",    { sIbT }, 0 },
1961
  { "imulS",    { Gv, Ev, sIb }, 0 },
1962
  { "ins{b|}",    { Ybr, indirDX }, 0 },
1963
  { X86_64_TABLE (X86_64_6D) },
1964
  { "outs{b|}",   { indirDXr, Xb }, 0 },
1965
  { X86_64_TABLE (X86_64_6F) },
1966
  /* 70 */
1967
  { "joH",    { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1968
  { "jnoH",   { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1969
  { "jbH",    { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1970
  { "jaeH",   { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1971
  { "jeH",    { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1972
  { "jneH",   { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1973
  { "jbeH",   { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1974
  { "jaH",    { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1975
  /* 78 */
1976
  { "jsH",    { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1977
  { "jnsH",   { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1978
  { "jpH",    { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1979
  { "jnpH",   { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1980
  { "jlH",    { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1981
  { "jgeH",   { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1982
  { "jleH",   { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1983
  { "jgH",    { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1984
  /* 80 */
1985
  { REG_TABLE (REG_80) },
1986
  { REG_TABLE (REG_81) },
1987
  { X86_64_TABLE (X86_64_82) },
1988
  { REG_TABLE (REG_83) },
1989
  { "testB",    { Eb, Gb }, 0 },
1990
  { "testS",    { Ev, Gv }, 0 },
1991
  { "xchgB",    { Ebh2, Gb }, 0 },
1992
  { "xchgS",    { Evh2, Gv }, 0 },
1993
  /* 88 */
1994
  { "movB",   { Ebh3, Gb }, 0 },
1995
  { "movS",   { Evh3, Gv }, 0 },
1996
  { "movB",   { Gb, EbS }, 0 },
1997
  { "movS",   { Gv, EvS }, 0 },
1998
  { "movD",   { Sv, Sw }, 0 },
1999
  { "leaS",   { Gv, M }, 0 },
2000
  { "movD",   { Sw, Sv }, 0 },
2001
  { REG_TABLE (REG_8F) },
2002
  /* 90 */
2003
  { PREFIX_TABLE (PREFIX_90) },
2004
  { "xchgS",    { RMeCX, eAX }, 0 },
2005
  { "xchgS",    { RMeDX, eAX }, 0 },
2006
  { "xchgS",    { RMeBX, eAX }, 0 },
2007
  { "xchgS",    { RMeSP, eAX }, 0 },
2008
  { "xchgS",    { RMeBP, eAX }, 0 },
2009
  { "xchgS",    { RMeSI, eAX }, 0 },
2010
  { "xchgS",    { RMeDI, eAX }, 0 },
2011
  /* 98 */
2012
  { "cW{t|}R",    { XX }, 0 },
2013
  { "cR{t|}O",    { XX }, 0 },
2014
  { X86_64_TABLE (X86_64_9A) },
2015
  { Bad_Opcode }, /* fwait */
2016
  { "pushfP",   { XX }, 0 },
2017
  { "popfP",    { XX }, 0 },
2018
  { "sahf",   { XX }, 0 },
2019
  { "lahf",   { XX }, 0 },
2020
  /* a0 */
2021
  { "mov%LB",   { AL, Ob }, PREFIX_REX2_ILLEGAL },
2022
  { "mov%LS",   { { JMPABS_Fixup, eAX_reg }, { JMPABS_Fixup, v_mode } }, PREFIX_REX2_ILLEGAL },
2023
  { "mov%LB",   { Ob, AL }, PREFIX_REX2_ILLEGAL },
2024
  { "mov%LS",   { Ov, eAX }, PREFIX_REX2_ILLEGAL },
2025
  { "movs{b|}",   { Ybr, Xb }, PREFIX_REX2_ILLEGAL },
2026
  { "movs{R|}",   { Yvr, Xv }, PREFIX_REX2_ILLEGAL },
2027
  { "cmps{b|}",   { Xb, Yb }, PREFIX_REX2_ILLEGAL },
2028
  { "cmps{R|}",   { Xv, Yv }, PREFIX_REX2_ILLEGAL },
2029
  /* a8 */
2030
  { "testB",    { AL, Ib }, PREFIX_REX2_ILLEGAL },
2031
  { "testS",    { eAX, Iv }, PREFIX_REX2_ILLEGAL },
2032
  { "stosB",    { Ybr, AL }, PREFIX_REX2_ILLEGAL },
2033
  { "stosS",    { Yvr, eAX }, PREFIX_REX2_ILLEGAL },
2034
  { "lodsB",    { ALr, Xb }, PREFIX_REX2_ILLEGAL },
2035
  { "lodsS",    { eAXr, Xv }, PREFIX_REX2_ILLEGAL },
2036
  { "scasB",    { AL, Yb }, PREFIX_REX2_ILLEGAL },
2037
  { "scasS",    { eAX, Yv }, PREFIX_REX2_ILLEGAL },
2038
  /* b0 */
2039
  { "movB",   { RMAL, Ib }, 0 },
2040
  { "movB",   { RMCL, Ib }, 0 },
2041
  { "movB",   { RMDL, Ib }, 0 },
2042
  { "movB",   { RMBL, Ib }, 0 },
2043
  { "movB",   { RMAH, Ib }, 0 },
2044
  { "movB",   { RMCH, Ib }, 0 },
2045
  { "movB",   { RMDH, Ib }, 0 },
2046
  { "movB",   { RMBH, Ib }, 0 },
2047
  /* b8 */
2048
  { "mov%LV",   { RMeAX, Iv64 }, 0 },
2049
  { "mov%LV",   { RMeCX, Iv64 }, 0 },
2050
  { "mov%LV",   { RMeDX, Iv64 }, 0 },
2051
  { "mov%LV",   { RMeBX, Iv64 }, 0 },
2052
  { "mov%LV",   { RMeSP, Iv64 }, 0 },
2053
  { "mov%LV",   { RMeBP, Iv64 }, 0 },
2054
  { "mov%LV",   { RMeSI, Iv64 }, 0 },
2055
  { "mov%LV",   { RMeDI, Iv64 }, 0 },
2056
  /* c0 */
2057
  { REG_TABLE (REG_C0) },
2058
  { REG_TABLE (REG_C1) },
2059
  { X86_64_TABLE (X86_64_C2) },
2060
  { X86_64_TABLE (X86_64_C3) },
2061
  { X86_64_TABLE (X86_64_C4) },
2062
  { X86_64_TABLE (X86_64_C5) },
2063
  { REG_TABLE (REG_C6) },
2064
  { REG_TABLE (REG_C7) },
2065
  /* c8 */
2066
  { "enterP",   { Iw, Ib }, 0 },
2067
  { "leaveP",   { XX }, 0 },
2068
  { "{l|}ret{|f}%LP", { Iw }, 0 },
2069
  { "{l|}ret{|f}%LP", { XX }, 0 },
2070
  { "int3",   { XX }, 0 },
2071
  { "int",    { Ib }, 0 },
2072
  { X86_64_TABLE (X86_64_CE) },
2073
  { "iret%LP",    { XX }, 0 },
2074
  /* d0 */
2075
  { REG_TABLE (REG_D0) },
2076
  { REG_TABLE (REG_D1) },
2077
  { REG_TABLE (REG_D2) },
2078
  { REG_TABLE (REG_D3) },
2079
  { X86_64_TABLE (X86_64_D4) },
2080
  { X86_64_TABLE (X86_64_D5) },
2081
  { Bad_Opcode },
2082
  { "xlat",   { DSBX }, 0 },
2083
  /* d8 */
2084
  { FLOAT },
2085
  { FLOAT },
2086
  { FLOAT },
2087
  { FLOAT },
2088
  { FLOAT },
2089
  { FLOAT },
2090
  { FLOAT },
2091
  { FLOAT },
2092
  /* e0 */
2093
  { "loopneFH",   { Jb, XX, loop_jcxz_flag }, PREFIX_REX2_ILLEGAL },
2094
  { "loopeFH",    { Jb, XX, loop_jcxz_flag }, PREFIX_REX2_ILLEGAL },
2095
  { "loopFH",   { Jb, XX, loop_jcxz_flag }, PREFIX_REX2_ILLEGAL },
2096
  { "jEcxzH",   { Jb, XX, loop_jcxz_flag }, PREFIX_REX2_ILLEGAL },
2097
  { "inB",    { AL, Ib }, PREFIX_REX2_ILLEGAL },
2098
  { "inG",    { zAX, Ib }, PREFIX_REX2_ILLEGAL },
2099
  { "outB",   { Ib, AL }, PREFIX_REX2_ILLEGAL },
2100
  { "outG",   { Ib, zAX }, PREFIX_REX2_ILLEGAL },
2101
  /* e8 */
2102
  { X86_64_TABLE (X86_64_E8) },
2103
  { X86_64_TABLE (X86_64_E9) },
2104
  { X86_64_TABLE (X86_64_EA) },
2105
  { "jmp",    { Jb, BND }, PREFIX_REX2_ILLEGAL },
2106
  { "inB",    { AL, indirDX }, PREFIX_REX2_ILLEGAL },
2107
  { "inG",    { zAX, indirDX }, PREFIX_REX2_ILLEGAL },
2108
  { "outB",   { indirDX, AL }, PREFIX_REX2_ILLEGAL },
2109
  { "outG",   { indirDX, zAX }, PREFIX_REX2_ILLEGAL },
2110
  /* f0 */
2111
  { Bad_Opcode }, /* lock prefix */
2112
  { "int1",   { XX }, 0 },
2113
  { Bad_Opcode }, /* repne */
2114
  { Bad_Opcode }, /* repz */
2115
  { "hlt",    { XX }, 0 },
2116
  { "cmc",    { XX }, 0 },
2117
  { REG_TABLE (REG_F6) },
2118
  { REG_TABLE (REG_F7) },
2119
  /* f8 */
2120
  { "clc",    { XX }, 0 },
2121
  { "stc",    { XX }, 0 },
2122
  { "cli",    { XX }, 0 },
2123
  { "sti",    { XX }, 0 },
2124
  { "cld",    { XX }, 0 },
2125
  { "std",    { XX }, 0 },
2126
  { REG_TABLE (REG_FE) },
2127
  { REG_TABLE (REG_FF) },
2128
};
2129
2130
static const struct dis386 dis386_twobyte[] = {
2131
  /* 00 */
2132
  { REG_TABLE (REG_0F00 ) },
2133
  { REG_TABLE (REG_0F01 ) },
2134
  { "larS",   { Gv, Sv }, 0 },
2135
  { "lslS",   { Gv, Sv }, 0 },
2136
  { Bad_Opcode },
2137
  { "syscall",    { XX }, 0 },
2138
  { "clts",   { XX }, 0 },
2139
  { "sysret%LQ",    { XX }, 0 },
2140
  /* 08 */
2141
  { "invd",   { XX }, 0 },
2142
  { PREFIX_TABLE (PREFIX_0F09) },
2143
  { Bad_Opcode },
2144
  { "ud2",    { XX }, 0 },
2145
  { Bad_Opcode },
2146
  { REG_TABLE (REG_0F0D) },
2147
  { "femms",    { XX }, 0 },
2148
  { "",     { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix.  */
2149
  /* 10 */
2150
  { PREFIX_TABLE (PREFIX_0F10) },
2151
  { PREFIX_TABLE (PREFIX_0F11) },
2152
  { PREFIX_TABLE (PREFIX_0F12) },
2153
  { "movlpX",   { Mq, XM }, PREFIX_OPCODE },
2154
  { "unpcklpX",   { XM, EXx }, PREFIX_OPCODE },
2155
  { "unpckhpX",   { XM, EXx }, PREFIX_OPCODE },
2156
  { PREFIX_TABLE (PREFIX_0F16) },
2157
  { "movhpX",   { Mq, XM }, PREFIX_OPCODE },
2158
  /* 18 */
2159
  { REG_TABLE (REG_0F18) },
2160
  { "nopQ",   { Ev }, 0 },
2161
  { PREFIX_TABLE (PREFIX_0F1A) },
2162
  { PREFIX_TABLE (PREFIX_0F1B) },
2163
  { PREFIX_TABLE (PREFIX_0F1C) },
2164
  { "nopQ",   { Ev }, 0 },
2165
  { PREFIX_TABLE (PREFIX_0F1E) },
2166
  { "nopQ",   { Ev }, 0 },
2167
  /* 20 */
2168
  { "movZ",   { Em, Cm }, 0 },
2169
  { "movZ",   { Em, Dm }, 0 },
2170
  { "movZ",   { Cm, Em }, 0 },
2171
  { "movZ",   { Dm, Em }, 0 },
2172
  { X86_64_TABLE (X86_64_0F24) },
2173
  { Bad_Opcode },
2174
  { X86_64_TABLE (X86_64_0F26) },
2175
  { Bad_Opcode },
2176
  /* 28 */
2177
  { "movapX",   { XM, EXx }, PREFIX_OPCODE },
2178
  { "movapX",   { EXxS, XM }, PREFIX_OPCODE },
2179
  { PREFIX_TABLE (PREFIX_0F2A) },
2180
  { PREFIX_TABLE (PREFIX_0F2B) },
2181
  { PREFIX_TABLE (PREFIX_0F2C) },
2182
  { PREFIX_TABLE (PREFIX_0F2D) },
2183
  { PREFIX_TABLE (PREFIX_0F2E) },
2184
  { PREFIX_TABLE (PREFIX_0F2F) },
2185
  /* 30 */
2186
  { "wrmsr",    { XX }, PREFIX_REX2_ILLEGAL },
2187
  { "rdtsc",    { XX }, PREFIX_REX2_ILLEGAL },
2188
  { "rdmsr",    { XX }, PREFIX_REX2_ILLEGAL },
2189
  { "rdpmc",    { XX }, PREFIX_REX2_ILLEGAL },
2190
  { "sysenter",   { SEP }, PREFIX_REX2_ILLEGAL },
2191
  { "sysexit%LQ", { SEP }, PREFIX_REX2_ILLEGAL },
2192
  { Bad_Opcode },
2193
  { "getsec",   { XX }, 0 },
2194
  /* 38 */
2195
  { THREE_BYTE_TABLE (THREE_BYTE_0F38) },
2196
  { Bad_Opcode },
2197
  { THREE_BYTE_TABLE (THREE_BYTE_0F3A) },
2198
  { Bad_Opcode },
2199
  { Bad_Opcode },
2200
  { Bad_Opcode },
2201
  { Bad_Opcode },
2202
  { Bad_Opcode },
2203
  /* 40 */
2204
  { "cmovoS",   { Gv, Ev }, 0 },
2205
  { "cmovnoS",    { Gv, Ev }, 0 },
2206
  { "cmovbS",   { Gv, Ev }, 0 },
2207
  { "cmovaeS",    { Gv, Ev }, 0 },
2208
  { "cmoveS",   { Gv, Ev }, 0 },
2209
  { "cmovneS",    { Gv, Ev }, 0 },
2210
  { "cmovbeS",    { Gv, Ev }, 0 },
2211
  { "cmovaS",   { Gv, Ev }, 0 },
2212
  /* 48 */
2213
  { "cmovsS",   { Gv, Ev }, 0 },
2214
  { "cmovnsS",    { Gv, Ev }, 0 },
2215
  { "cmovpS",   { Gv, Ev }, 0 },
2216
  { "cmovnpS",    { Gv, Ev }, 0 },
2217
  { "cmovlS",   { Gv, Ev }, 0 },
2218
  { "cmovgeS",    { Gv, Ev }, 0 },
2219
  { "cmovleS",    { Gv, Ev }, 0 },
2220
  { "cmovgS",   { Gv, Ev }, 0 },
2221
  /* 50 */
2222
  { "movmskpX",   { Gdq, Ux }, PREFIX_OPCODE },
2223
  { PREFIX_TABLE (PREFIX_0F51) },
2224
  { PREFIX_TABLE (PREFIX_0F52) },
2225
  { PREFIX_TABLE (PREFIX_0F53) },
2226
  { "andpX",    { XM, EXx }, PREFIX_OPCODE },
2227
  { "andnpX",   { XM, EXx }, PREFIX_OPCODE },
2228
  { "orpX",   { XM, EXx }, PREFIX_OPCODE },
2229
  { "xorpX",    { XM, EXx }, PREFIX_OPCODE },
2230
  /* 58 */
2231
  { PREFIX_TABLE (PREFIX_0F58) },
2232
  { PREFIX_TABLE (PREFIX_0F59) },
2233
  { PREFIX_TABLE (PREFIX_0F5A) },
2234
  { PREFIX_TABLE (PREFIX_0F5B) },
2235
  { PREFIX_TABLE (PREFIX_0F5C) },
2236
  { PREFIX_TABLE (PREFIX_0F5D) },
2237
  { PREFIX_TABLE (PREFIX_0F5E) },
2238
  { PREFIX_TABLE (PREFIX_0F5F) },
2239
  /* 60 */
2240
  { PREFIX_TABLE (PREFIX_0F60) },
2241
  { PREFIX_TABLE (PREFIX_0F61) },
2242
  { PREFIX_TABLE (PREFIX_0F62) },
2243
  { "packsswb",   { MX, EM }, PREFIX_OPCODE },
2244
  { "pcmpgtb",    { MX, EM }, PREFIX_OPCODE },
2245
  { "pcmpgtw",    { MX, EM }, PREFIX_OPCODE },
2246
  { "pcmpgtd",    { MX, EM }, PREFIX_OPCODE },
2247
  { "packuswb",   { MX, EM }, PREFIX_OPCODE },
2248
  /* 68 */
2249
  { "punpckhbw",  { MX, EM }, PREFIX_OPCODE },
2250
  { "punpckhwd",  { MX, EM }, PREFIX_OPCODE },
2251
  { "punpckhdq",  { MX, EM }, PREFIX_OPCODE },
2252
  { "packssdw",   { MX, EM }, PREFIX_OPCODE },
2253
  { "punpcklqdq", { XM, EXx }, PREFIX_DATA },
2254
  { "punpckhqdq", { XM, EXx }, PREFIX_DATA },
2255
  { "movK",   { MX, Edq }, PREFIX_OPCODE },
2256
  { PREFIX_TABLE (PREFIX_0F6F) },
2257
  /* 70 */
2258
  { PREFIX_TABLE (PREFIX_0F70) },
2259
  { REG_TABLE (REG_0F71) },
2260
  { REG_TABLE (REG_0F72) },
2261
  { REG_TABLE (REG_0F73) },
2262
  { "pcmpeqb",    { MX, EM }, PREFIX_OPCODE },
2263
  { "pcmpeqw",    { MX, EM }, PREFIX_OPCODE },
2264
  { "pcmpeqd",    { MX, EM }, PREFIX_OPCODE },
2265
  { "emms",   { XX }, PREFIX_OPCODE },
2266
  /* 78 */
2267
  { PREFIX_TABLE (PREFIX_0F78) },
2268
  { PREFIX_TABLE (PREFIX_0F79) },
2269
  { Bad_Opcode },
2270
  { Bad_Opcode },
2271
  { PREFIX_TABLE (PREFIX_0F7C) },
2272
  { PREFIX_TABLE (PREFIX_0F7D) },
2273
  { PREFIX_TABLE (PREFIX_0F7E) },
2274
  { PREFIX_TABLE (PREFIX_0F7F) },
2275
  /* 80 */
2276
  { "joH",    { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2277
  { "jnoH",   { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2278
  { "jbH",    { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2279
  { "jaeH",   { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2280
  { "jeH",    { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2281
  { "jneH",   { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2282
  { "jbeH",   { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2283
  { "jaH",    { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2284
  /* 88 */
2285
  { "jsH",    { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2286
  { "jnsH",   { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2287
  { "jpH",    { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2288
  { "jnpH",   { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2289
  { "jlH",    { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2290
  { "jgeH",   { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2291
  { "jleH",   { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2292
  { "jgH",    { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2293
  /* 90 */
2294
  { "seto",   { Eb }, 0 },
2295
  { "setno",    { Eb }, 0 },
2296
  { "setb",   { Eb }, 0 },
2297
  { "setae",    { Eb }, 0 },
2298
  { "sete",   { Eb }, 0 },
2299
  { "setne",    { Eb }, 0 },
2300
  { "setbe",    { Eb }, 0 },
2301
  { "seta",   { Eb }, 0 },
2302
  /* 98 */
2303
  { "sets",   { Eb }, 0 },
2304
  { "setns",    { Eb }, 0 },
2305
  { "setp",   { Eb }, 0 },
2306
  { "setnp",    { Eb }, 0 },
2307
  { "setl",   { Eb }, 0 },
2308
  { "setge",    { Eb }, 0 },
2309
  { "setle",    { Eb }, 0 },
2310
  { "setg",   { Eb }, 0 },
2311
  /* a0 */
2312
  { "pushP",    { fs }, 0 },
2313
  { "popP",   { fs }, 0 },
2314
  { "cpuid",    { XX }, 0 },
2315
  { "btS",    { Ev, Gv }, 0 },
2316
  { "shldS",    { Ev, Gv, Ib }, 0 },
2317
  { "shldS",    { Ev, Gv, CL }, 0 },
2318
  { REG_TABLE (REG_0FA6) },
2319
  { REG_TABLE (REG_0FA7) },
2320
  /* a8 */
2321
  { "pushP",    { gs }, 0 },
2322
  { "popP",   { gs }, 0 },
2323
  { "rsm",    { XX }, 0 },
2324
  { "btsS",   { Evh1, Gv }, 0 },
2325
  { "shrdS",    { Ev, Gv, Ib }, 0 },
2326
  { "shrdS",    { Ev, Gv, CL }, 0 },
2327
  { REG_TABLE (REG_0FAE) },
2328
  { "imulS",    { Gv, Ev }, 0 },
2329
  /* b0 */
2330
  { "cmpxchgB",   { Ebh1, Gb }, 0 },
2331
  { "cmpxchgS",   { Evh1, Gv }, 0 },
2332
  { "lssS",   { Gv, Mp }, 0 },
2333
  { "btrS",   { Evh1, Gv }, 0 },
2334
  { "lfsS",   { Gv, Mp }, 0 },
2335
  { "lgsS",   { Gv, Mp }, 0 },
2336
  { "movz{bR|x}", { Gv, Eb }, 0 },
2337
  { "movz{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
2338
  /* b8 */
2339
  { PREFIX_TABLE (PREFIX_0FB8) },
2340
  { "ud1S",   { Gv, Ev }, 0 },
2341
  { REG_TABLE (REG_0FBA) },
2342
  { "btcS",   { Evh1, Gv }, 0 },
2343
  { PREFIX_TABLE (PREFIX_0FBC) },
2344
  { PREFIX_TABLE (PREFIX_0FBD) },
2345
  { "movs{bR|x}", { Gv, Eb }, 0 },
2346
  { "movs{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
2347
  /* c0 */
2348
  { "xaddB",    { Ebh1, Gb }, 0 },
2349
  { "xaddS",    { Evh1, Gv }, 0 },
2350
  { PREFIX_TABLE (PREFIX_0FC2) },
2351
  { "movntiS",    { Mdq, Gdq }, PREFIX_OPCODE },
2352
  { "pinsrw",   { MX, Edw, Ib }, PREFIX_OPCODE },
2353
  { "pextrw",   { Gd, Nq, Ib }, PREFIX_OPCODE },
2354
  { "shufpX",   { XM, EXx, Ib }, PREFIX_OPCODE },
2355
  { REG_TABLE (REG_0FC7) },
2356
  /* c8 */
2357
  { "bswap",    { RMeAX }, 0 },
2358
  { "bswap",    { RMeCX }, 0 },
2359
  { "bswap",    { RMeDX }, 0 },
2360
  { "bswap",    { RMeBX }, 0 },
2361
  { "bswap",    { RMeSP }, 0 },
2362
  { "bswap",    { RMeBP }, 0 },
2363
  { "bswap",    { RMeSI }, 0 },
2364
  { "bswap",    { RMeDI }, 0 },
2365
  /* d0 */
2366
  { PREFIX_TABLE (PREFIX_0FD0) },
2367
  { "psrlw",    { MX, EM }, PREFIX_OPCODE },
2368
  { "psrld",    { MX, EM }, PREFIX_OPCODE },
2369
  { "psrlq",    { MX, EM }, PREFIX_OPCODE },
2370
  { "paddq",    { MX, EM }, PREFIX_OPCODE },
2371
  { "pmullw",   { MX, EM }, PREFIX_OPCODE },
2372
  { PREFIX_TABLE (PREFIX_0FD6) },
2373
  { "pmovmskb",   { Gdq, Nq }, PREFIX_OPCODE },
2374
  /* d8 */
2375
  { "psubusb",    { MX, EM }, PREFIX_OPCODE },
2376
  { "psubusw",    { MX, EM }, PREFIX_OPCODE },
2377
  { "pminub",   { MX, EM }, PREFIX_OPCODE },
2378
  { "pand",   { MX, EM }, PREFIX_OPCODE },
2379
  { "paddusb",    { MX, EM }, PREFIX_OPCODE },
2380
  { "paddusw",    { MX, EM }, PREFIX_OPCODE },
2381
  { "pmaxub",   { MX, EM }, PREFIX_OPCODE },
2382
  { "pandn",    { MX, EM }, PREFIX_OPCODE },
2383
  /* e0 */
2384
  { "pavgb",    { MX, EM }, PREFIX_OPCODE },
2385
  { "psraw",    { MX, EM }, PREFIX_OPCODE },
2386
  { "psrad",    { MX, EM }, PREFIX_OPCODE },
2387
  { "pavgw",    { MX, EM }, PREFIX_OPCODE },
2388
  { "pmulhuw",    { MX, EM }, PREFIX_OPCODE },
2389
  { "pmulhw",   { MX, EM }, PREFIX_OPCODE },
2390
  { PREFIX_TABLE (PREFIX_0FE6) },
2391
  { PREFIX_TABLE (PREFIX_0FE7) },
2392
  /* e8 */
2393
  { "psubsb",   { MX, EM }, PREFIX_OPCODE },
2394
  { "psubsw",   { MX, EM }, PREFIX_OPCODE },
2395
  { "pminsw",   { MX, EM }, PREFIX_OPCODE },
2396
  { "por",    { MX, EM }, PREFIX_OPCODE },
2397
  { "paddsb",   { MX, EM }, PREFIX_OPCODE },
2398
  { "paddsw",   { MX, EM }, PREFIX_OPCODE },
2399
  { "pmaxsw",   { MX, EM }, PREFIX_OPCODE },
2400
  { "pxor",   { MX, EM }, PREFIX_OPCODE },
2401
  /* f0 */
2402
  { PREFIX_TABLE (PREFIX_0FF0) },
2403
  { "psllw",    { MX, EM }, PREFIX_OPCODE },
2404
  { "pslld",    { MX, EM }, PREFIX_OPCODE },
2405
  { "psllq",    { MX, EM }, PREFIX_OPCODE },
2406
  { "pmuludq",    { MX, EM }, PREFIX_OPCODE },
2407
  { "pmaddwd",    { MX, EM }, PREFIX_OPCODE },
2408
  { "psadbw",   { MX, EM }, PREFIX_OPCODE },
2409
  { PREFIX_TABLE (PREFIX_0FF7) },
2410
  /* f8 */
2411
  { "psubb",    { MX, EM }, PREFIX_OPCODE },
2412
  { "psubw",    { MX, EM }, PREFIX_OPCODE },
2413
  { "psubd",    { MX, EM }, PREFIX_OPCODE },
2414
  { "psubq",    { MX, EM }, PREFIX_OPCODE },
2415
  { "paddb",    { MX, EM }, PREFIX_OPCODE },
2416
  { "paddw",    { MX, EM }, PREFIX_OPCODE },
2417
  { "paddd",    { MX, EM }, PREFIX_OPCODE },
2418
  { "ud0S",   { Gv, Ev }, 0 },
2419
};
2420
2421
static const bool onebyte_has_modrm[256] = {
2422
  /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2423
  /*       -------------------------------        */
2424
  /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2425
  /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2426
  /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2427
  /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2428
  /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2429
  /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2430
  /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2431
  /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2432
  /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2433
  /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2434
  /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2435
  /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2436
  /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2437
  /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2438
  /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2439
  /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
2440
  /*       -------------------------------        */
2441
  /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2442
};
2443
2444
static const bool twobyte_has_modrm[256] = {
2445
  /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2446
  /*       -------------------------------        */
2447
  /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2448
  /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2449
  /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2450
  /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2451
  /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2452
  /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2453
  /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2454
  /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2455
  /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2456
  /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2457
  /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2458
  /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2459
  /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2460
  /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2461
  /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2462
  /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1  /* ff */
2463
  /*       -------------------------------        */
2464
  /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2465
};
2466
2467
2468
struct op
2469
  {
2470
    const char *name;
2471
    unsigned int len;
2472
  };
2473
2474
/* If we are accessing mod/rm/reg without need_modrm set, then the
2475
   values are stale.  Hitting this abort likely indicates that you
2476
   need to update onebyte_has_modrm or twobyte_has_modrm.  */
2477
10.3M
#define MODRM_CHECK  if (!ins->need_modrm) abort ()
2478
2479
static const char intel_index16[][6] = {
2480
  "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2481
};
2482
2483
static const char att_names64[][8] = {
2484
  "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2485
  "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
2486
  "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
2487
  "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
2488
};
2489
static const char att_names32[][8] = {
2490
  "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2491
  "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d",
2492
  "%r16d", "%r17d", "%r18d", "%r19d", "%r20d", "%r21d", "%r22d", "%r23d",
2493
  "%r24d", "%r25d", "%r26d", "%r27d", "%r28d", "%r29d", "%r30d", "%r31d",
2494
};
2495
static const char att_names16[][8] = {
2496
  "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2497
  "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w",
2498
  "%r16w", "%r17w", "%r18w", "%r19w", "%r20w", "%r21w", "%r22w", "%r23w",
2499
  "%r24w", "%r25w", "%r26w", "%r27w", "%r28w", "%r29w", "%r30w", "%r31w",
2500
};
2501
static const char att_names8[][8] = {
2502
  "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2503
};
2504
static const char att_names8rex[][8] = {
2505
  "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2506
  "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b",
2507
  "%r16b", "%r17b", "%r18b", "%r19b", "%r20b", "%r21b", "%r22b", "%r23b",
2508
  "%r24b", "%r25b", "%r26b", "%r27b", "%r28b", "%r29b", "%r30b", "%r31b",
2509
};
2510
static const char att_names_seg[][4] = {
2511
  "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2512
};
2513
static const char att_index64[] = "%riz";
2514
static const char att_index32[] = "%eiz";
2515
static const char att_index16[][8] = {
2516
  "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2517
};
2518
2519
static const char att_names_mm[][8] = {
2520
  "%mm0", "%mm1", "%mm2", "%mm3",
2521
  "%mm4", "%mm5", "%mm6", "%mm7"
2522
};
2523
2524
static const char att_names_bnd[][8] = {
2525
  "%bnd0", "%bnd1", "%bnd2", "%bnd3"
2526
};
2527
2528
static const char att_names_xmm[][8] = {
2529
  "%xmm0", "%xmm1", "%xmm2", "%xmm3",
2530
  "%xmm4", "%xmm5", "%xmm6", "%xmm7",
2531
  "%xmm8", "%xmm9", "%xmm10", "%xmm11",
2532
  "%xmm12", "%xmm13", "%xmm14", "%xmm15",
2533
  "%xmm16", "%xmm17", "%xmm18", "%xmm19",
2534
  "%xmm20", "%xmm21", "%xmm22", "%xmm23",
2535
  "%xmm24", "%xmm25", "%xmm26", "%xmm27",
2536
  "%xmm28", "%xmm29", "%xmm30", "%xmm31"
2537
};
2538
2539
static const char att_names_ymm[][8] = {
2540
  "%ymm0", "%ymm1", "%ymm2", "%ymm3",
2541
  "%ymm4", "%ymm5", "%ymm6", "%ymm7",
2542
  "%ymm8", "%ymm9", "%ymm10", "%ymm11",
2543
  "%ymm12", "%ymm13", "%ymm14", "%ymm15",
2544
  "%ymm16", "%ymm17", "%ymm18", "%ymm19",
2545
  "%ymm20", "%ymm21", "%ymm22", "%ymm23",
2546
  "%ymm24", "%ymm25", "%ymm26", "%ymm27",
2547
  "%ymm28", "%ymm29", "%ymm30", "%ymm31"
2548
};
2549
2550
static const char att_names_zmm[][8] = {
2551
  "%zmm0", "%zmm1", "%zmm2", "%zmm3",
2552
  "%zmm4", "%zmm5", "%zmm6", "%zmm7",
2553
  "%zmm8", "%zmm9", "%zmm10", "%zmm11",
2554
  "%zmm12", "%zmm13", "%zmm14", "%zmm15",
2555
  "%zmm16", "%zmm17", "%zmm18", "%zmm19",
2556
  "%zmm20", "%zmm21", "%zmm22", "%zmm23",
2557
  "%zmm24", "%zmm25", "%zmm26", "%zmm27",
2558
  "%zmm28", "%zmm29", "%zmm30", "%zmm31"
2559
};
2560
2561
static const char att_names_tmm[][8] = {
2562
  "%tmm0", "%tmm1", "%tmm2", "%tmm3",
2563
  "%tmm4", "%tmm5", "%tmm6", "%tmm7"
2564
};
2565
2566
static const char att_names_mask[][8] = {
2567
  "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
2568
};
2569
2570
static const char *const names_rounding[] =
2571
{
2572
  "{rn-",
2573
  "{rd-",
2574
  "{ru-",
2575
  "{rz-"
2576
};
2577
2578
static const struct dis386 reg_table[][8] = {
2579
  /* REG_80 */
2580
  {
2581
    { "addA", { Ebh1, Ib }, 0 },
2582
    { "orA",  { Ebh1, Ib }, 0 },
2583
    { "adcA", { Ebh1, Ib }, 0 },
2584
    { "sbbA", { Ebh1, Ib }, 0 },
2585
    { "andA", { Ebh1, Ib }, 0 },
2586
    { "subA", { Ebh1, Ib }, 0 },
2587
    { "xorA", { Ebh1, Ib }, 0 },
2588
    { "cmpA", { Eb, Ib }, 0 },
2589
  },
2590
  /* REG_81 */
2591
  {
2592
    { "addQ", { Evh1, Iv }, 0 },
2593
    { "orQ",  { Evh1, Iv }, 0 },
2594
    { "adcQ", { Evh1, Iv }, 0 },
2595
    { "sbbQ", { Evh1, Iv }, 0 },
2596
    { "andQ", { Evh1, Iv }, 0 },
2597
    { "subQ", { Evh1, Iv }, 0 },
2598
    { "xorQ", { Evh1, Iv }, 0 },
2599
    { "cmpQ", { Ev, Iv }, 0 },
2600
  },
2601
  /* REG_83 */
2602
  {
2603
    { "addQ", { Evh1, sIb }, 0 },
2604
    { "orQ",  { Evh1, sIb }, 0 },
2605
    { "adcQ", { Evh1, sIb }, 0 },
2606
    { "sbbQ", { Evh1, sIb }, 0 },
2607
    { "andQ", { Evh1, sIb }, 0 },
2608
    { "subQ", { Evh1, sIb }, 0 },
2609
    { "xorQ", { Evh1, sIb }, 0 },
2610
    { "cmpQ", { Ev, sIb }, 0 },
2611
  },
2612
  /* REG_8F */
2613
  {
2614
    { "pop{P|}", { stackEv }, 0 },
2615
    { XOP_8F_TABLE () },
2616
    { Bad_Opcode },
2617
    { Bad_Opcode },
2618
    { Bad_Opcode },
2619
    { XOP_8F_TABLE () },
2620
  },
2621
  /* REG_C0 */
2622
  {
2623
    { "%NFrolA",  { VexGb, Eb, Ib }, NO_PREFIX },
2624
    { "%NFrorA",  { VexGb, Eb, Ib }, NO_PREFIX },
2625
    { "rclA", { VexGb, Eb, Ib }, NO_PREFIX },
2626
    { "rcrA", { VexGb, Eb, Ib }, NO_PREFIX },
2627
    { "%NFshlA",  { VexGb, Eb, Ib }, NO_PREFIX },
2628
    { "%NFshrA",  { VexGb, Eb, Ib }, NO_PREFIX },
2629
    { "%NFshlA",  { VexGb, Eb, Ib }, NO_PREFIX },
2630
    { "%NFsarA",  { VexGb, Eb, Ib }, NO_PREFIX },
2631
  },
2632
  /* REG_C1 */
2633
  {
2634
    { "%NFrolQ",  { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA },
2635
    { "%NFrorQ",  { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA },
2636
    { "rclQ", { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA },
2637
    { "rcrQ", { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA },
2638
    { "%NFshlQ",  { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA },
2639
    { "%NFshrQ",  { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA },
2640
    { "%NFshlQ",  { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA },
2641
    { "%NFsarQ",  { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA },
2642
  },
2643
  /* REG_C6 */
2644
  {
2645
    { "movA", { Ebh3, Ib }, 0 },
2646
    { Bad_Opcode },
2647
    { Bad_Opcode },
2648
    { Bad_Opcode },
2649
    { Bad_Opcode },
2650
    { Bad_Opcode },
2651
    { Bad_Opcode },
2652
    { RM_TABLE (RM_C6_REG_7) },
2653
  },
2654
  /* REG_C7 */
2655
  {
2656
    { "movQ", { Evh3, Iv }, 0 },
2657
    { Bad_Opcode },
2658
    { Bad_Opcode },
2659
    { Bad_Opcode },
2660
    { Bad_Opcode },
2661
    { Bad_Opcode },
2662
    { Bad_Opcode },
2663
    { RM_TABLE (RM_C7_REG_7) },
2664
  },
2665
  /* REG_D0 */
2666
  {
2667
    { "%NFrolA",  { VexGb, Eb, I1 }, NO_PREFIX },
2668
    { "%NFrorA",  { VexGb, Eb, I1 }, NO_PREFIX },
2669
    { "rclA", { VexGb, Eb, I1 }, NO_PREFIX },
2670
    { "rcrA", { VexGb, Eb, I1 }, NO_PREFIX },
2671
    { "%NFshlA",  { VexGb, Eb, I1 }, NO_PREFIX },
2672
    { "%NFshrA",  { VexGb, Eb, I1 }, NO_PREFIX },
2673
    { "%NFshlA",  { VexGb, Eb, I1 }, NO_PREFIX },
2674
    { "%NFsarA",  { VexGb, Eb, I1 }, NO_PREFIX },
2675
  },
2676
  /* REG_D1 */
2677
  {
2678
    { "%NFrolQ",  { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA },
2679
    { "%NFrorQ",  { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA },
2680
    { "rclQ", { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA },
2681
    { "rcrQ", { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA },
2682
    { "%NFshlQ",  { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA },
2683
    { "%NFshrQ",  { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA },
2684
    { "%NFshlQ",  { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA },
2685
    { "%NFsarQ",  { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA },
2686
  },
2687
  /* REG_D2 */
2688
  {
2689
    { "%NFrolA",  { VexGb, Eb, CL }, NO_PREFIX },
2690
    { "%NFrorA",  { VexGb, Eb, CL }, NO_PREFIX },
2691
    { "rclA", { VexGb, Eb, CL }, NO_PREFIX },
2692
    { "rcrA", { VexGb, Eb, CL }, NO_PREFIX },
2693
    { "%NFshlA",  { VexGb, Eb, CL }, NO_PREFIX },
2694
    { "%NFshrA",  { VexGb, Eb, CL }, NO_PREFIX },
2695
    { "%NFshlA",  { VexGb, Eb, CL }, NO_PREFIX },
2696
    { "%NFsarA",  { VexGb, Eb, CL }, NO_PREFIX },
2697
  },
2698
  /* REG_D3 */
2699
  {
2700
    { "%NFrolQ",  { VexGv, Ev, CL }, PREFIX_NP_OR_DATA },
2701
    { "%NFrorQ",  { VexGv, Ev, CL }, PREFIX_NP_OR_DATA },
2702
    { "rclQ", { VexGv, Ev, CL }, PREFIX_NP_OR_DATA },
2703
    { "rcrQ", { VexGv, Ev, CL }, PREFIX_NP_OR_DATA },
2704
    { "%NFshlQ",  { VexGv, Ev, CL }, PREFIX_NP_OR_DATA },
2705
    { "%NFshrQ",  { VexGv, Ev, CL }, PREFIX_NP_OR_DATA },
2706
    { "%NFshlQ",  { VexGv, Ev, CL }, PREFIX_NP_OR_DATA },
2707
    { "%NFsarQ",  { VexGv, Ev, CL }, PREFIX_NP_OR_DATA },
2708
  },
2709
  /* REG_F6 */
2710
  {
2711
    { "testA",  { Eb, Ib }, 0 },
2712
    { "testA",  { Eb, Ib }, 0 },
2713
    { "notA", { Ebh1 }, 0 },
2714
    { "negA", { Ebh1 }, 0 },
2715
    { "mulA", { Eb }, 0 },  /* Don't print the implicit %al register,  */
2716
    { "imulA",  { Eb }, 0 },  /* to distinguish these opcodes from other */
2717
    { "divA", { Eb }, 0 },  /* mul/imul opcodes.  Do the same for div  */
2718
    { "idivA",  { Eb }, 0 },  /* and idiv for consistency.       */
2719
  },
2720
  /* REG_F7 */
2721
  {
2722
    { "testQ",  { Ev, Iv }, 0 },
2723
    { "testQ",  { Ev, Iv }, 0 },
2724
    { "notQ", { Evh1 }, 0 },
2725
    { "negQ", { Evh1 }, 0 },
2726
    { "mulQ", { Ev }, 0 },  /* Don't print the implicit register.  */
2727
    { "imulQ",  { Ev }, 0 },
2728
    { "divQ", { Ev }, 0 },
2729
    { "idivQ",  { Ev }, 0 },
2730
  },
2731
  /* REG_FE */
2732
  {
2733
    { "incA", { Ebh1 }, 0 },
2734
    { "decA", { Ebh1 }, 0 },
2735
  },
2736
  /* REG_FF */
2737
  {
2738
    { "incQ", { Evh1 }, 0 },
2739
    { "decQ", { Evh1 }, 0 },
2740
    { "call{@|}", { NOTRACK, indirEv, BND }, 0 },
2741
    { "{l|}call^", { indirEp }, 0 },
2742
    { "jmp{@|}", { NOTRACK, indirEv, BND }, 0 },
2743
    { "{l|}jmp^", { indirEp }, 0 },
2744
    { "push{P|}", { stackEv }, 0 },
2745
    { Bad_Opcode },
2746
  },
2747
  /* REG_0F00 */
2748
  {
2749
    { "sldtD",  { Sv }, 0 },
2750
    { "strD", { Sv }, 0 },
2751
    { "lldtD",  { Sv }, 0 },
2752
    { "ltrD", { Sv }, 0 },
2753
    { "verrD",  { Sv }, 0 },
2754
    { "verwD",  { Sv }, 0 },
2755
    { X86_64_TABLE (X86_64_0F00_REG_6) },
2756
    { Bad_Opcode },
2757
  },
2758
  /* REG_0F01 */
2759
  {
2760
    { MOD_TABLE (MOD_0F01_REG_0) },
2761
    { MOD_TABLE (MOD_0F01_REG_1) },
2762
    { MOD_TABLE (MOD_0F01_REG_2) },
2763
    { MOD_TABLE (MOD_0F01_REG_3) },
2764
    { "smswD",  { Sv }, 0 },
2765
    { MOD_TABLE (MOD_0F01_REG_5) },
2766
    { "lmsw", { Ew }, 0 },
2767
    { MOD_TABLE (MOD_0F01_REG_7) },
2768
  },
2769
  /* REG_0F0D */
2770
  {
2771
    { "prefetch", { Mb }, 0 },
2772
    { "prefetchw",  { Mb }, 0 },
2773
    { "prefetchwt1",  { Mb }, 0 },
2774
    { "prefetch", { Mb }, 0 },
2775
    { "prefetch", { Mb }, 0 },
2776
    { "prefetch", { Mb }, 0 },
2777
    { "prefetch", { Mb }, 0 },
2778
    { "prefetch", { Mb }, 0 },
2779
  },
2780
  /* REG_0F18 */
2781
  {
2782
    { MOD_TABLE (MOD_0F18_REG_0) },
2783
    { MOD_TABLE (MOD_0F18_REG_1) },
2784
    { MOD_TABLE (MOD_0F18_REG_2) },
2785
    { MOD_TABLE (MOD_0F18_REG_3) },
2786
    { "nopQ",   { Ev }, 0 },
2787
    { "nopQ",   { Ev }, 0 },
2788
    { MOD_TABLE (MOD_0F18_REG_6) },
2789
    { MOD_TABLE (MOD_0F18_REG_7) },
2790
  },
2791
  /* REG_0F1C_P_0_MOD_0 */
2792
  {
2793
    { "cldemote", { Mb }, 0 },
2794
    { "nopQ",   { Ev }, 0 },
2795
    { "nopQ",   { Ev }, 0 },
2796
    { "nopQ",   { Ev }, 0 },
2797
    { "nopQ",   { Ev }, 0 },
2798
    { "nopQ",   { Ev }, 0 },
2799
    { "nopQ",   { Ev }, 0 },
2800
    { "nopQ",   { Ev }, 0 },
2801
  },
2802
  /* REG_0F1E_P_1_MOD_3 */
2803
  {
2804
    { "nopQ",   { Ev }, PREFIX_IGNORED },
2805
    { "rdsspK",   { Edq }, 0 },
2806
    { "nopQ",   { Ev }, PREFIX_IGNORED },
2807
    { "nopQ",   { Ev }, PREFIX_IGNORED },
2808
    { "nopQ",   { Ev }, PREFIX_IGNORED },
2809
    { "nopQ",   { Ev }, PREFIX_IGNORED },
2810
    { "nopQ",   { Ev }, PREFIX_IGNORED },
2811
    { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7) },
2812
  },
2813
  /* REG_0F38D8_PREFIX_1 */
2814
  {
2815
    { "aesencwide128kl",  { M }, 0 },
2816
    { "aesdecwide128kl",  { M }, 0 },
2817
    { "aesencwide256kl",  { M }, 0 },
2818
    { "aesdecwide256kl",  { M }, 0 },
2819
  },
2820
  /* REG_0F3A0F_P_1 */
2821
  {
2822
    { RM_TABLE (RM_0F3A0F_P_1_R_0) },
2823
  },
2824
  /* REG_0F71 */
2825
  {
2826
    { Bad_Opcode },
2827
    { Bad_Opcode },
2828
    { "psrlw",    { Nq, Ib }, PREFIX_OPCODE },
2829
    { Bad_Opcode },
2830
    { "psraw",    { Nq, Ib }, PREFIX_OPCODE },
2831
    { Bad_Opcode },
2832
    { "psllw",    { Nq, Ib }, PREFIX_OPCODE },
2833
  },
2834
  /* REG_0F72 */
2835
  {
2836
    { Bad_Opcode },
2837
    { Bad_Opcode },
2838
    { "psrld",    { Nq, Ib }, PREFIX_OPCODE },
2839
    { Bad_Opcode },
2840
    { "psrad",    { Nq, Ib }, PREFIX_OPCODE },
2841
    { Bad_Opcode },
2842
    { "pslld",    { Nq, Ib }, PREFIX_OPCODE },
2843
  },
2844
  /* REG_0F73 */
2845
  {
2846
    { Bad_Opcode },
2847
    { Bad_Opcode },
2848
    { "psrlq",    { Nq, Ib }, PREFIX_OPCODE },
2849
    { "psrldq",   { Ux, Ib }, PREFIX_DATA },
2850
    { Bad_Opcode },
2851
    { Bad_Opcode },
2852
    { "psllq",    { Nq, Ib }, PREFIX_OPCODE },
2853
    { "pslldq",   { Ux, Ib }, PREFIX_DATA },
2854
  },
2855
  /* REG_0FA6 */
2856
  {
2857
    { "montmul",  { { OP_0f07, 0 } }, 0 },
2858
    { "xsha1",    { { OP_0f07, 0 } }, 0 },
2859
    { "xsha256",  { { OP_0f07, 0 } }, 0 },
2860
  },
2861
  /* REG_0FA7 */
2862
  {
2863
    { "xstore-rng", { { OP_0f07, 0 } }, 0 },
2864
    { "xcrypt-ecb", { { OP_0f07, 0 } }, 0 },
2865
    { "xcrypt-cbc", { { OP_0f07, 0 } }, 0 },
2866
    { "xcrypt-ctr", { { OP_0f07, 0 } }, 0 },
2867
    { "xcrypt-cfb", { { OP_0f07, 0 } }, 0 },
2868
    { "xcrypt-ofb", { { OP_0f07, 0 } }, 0 },
2869
  },
2870
  /* REG_0FAE */
2871
  {
2872
    { MOD_TABLE (MOD_0FAE_REG_0) },
2873
    { MOD_TABLE (MOD_0FAE_REG_1) },
2874
    { MOD_TABLE (MOD_0FAE_REG_2) },
2875
    { MOD_TABLE (MOD_0FAE_REG_3) },
2876
    { MOD_TABLE (MOD_0FAE_REG_4) },
2877
    { MOD_TABLE (MOD_0FAE_REG_5) },
2878
    { MOD_TABLE (MOD_0FAE_REG_6) },
2879
    { MOD_TABLE (MOD_0FAE_REG_7) },
2880
  },
2881
  /* REG_0FBA */
2882
  {
2883
    { Bad_Opcode },
2884
    { Bad_Opcode },
2885
    { Bad_Opcode },
2886
    { Bad_Opcode },
2887
    { "btQ",  { Ev, Ib }, 0 },
2888
    { "btsQ", { Evh1, Ib }, 0 },
2889
    { "btrQ", { Evh1, Ib }, 0 },
2890
    { "btcQ", { Evh1, Ib }, 0 },
2891
  },
2892
  /* REG_0FC7 */
2893
  {
2894
    { Bad_Opcode },
2895
    { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
2896
    { Bad_Opcode },
2897
    { "xrstors", { FXSAVE }, PREFIX_REX2_ILLEGAL },
2898
    { "xsavec", { FXSAVE }, PREFIX_REX2_ILLEGAL },
2899
    { "xsaves", { FXSAVE }, PREFIX_REX2_ILLEGAL },
2900
    { MOD_TABLE (MOD_0FC7_REG_6) },
2901
    { MOD_TABLE (MOD_0FC7_REG_7) },
2902
  },
2903
  /* REG_VEX_0F71 */
2904
  {
2905
    { Bad_Opcode },
2906
    { Bad_Opcode },
2907
    { "vpsrlw",   { Vex, Ux, Ib }, PREFIX_DATA },
2908
    { Bad_Opcode },
2909
    { "vpsraw",   { Vex, Ux, Ib }, PREFIX_DATA },
2910
    { Bad_Opcode },
2911
    { "vpsllw",   { Vex, Ux, Ib }, PREFIX_DATA },
2912
  },
2913
  /* REG_VEX_0F72 */
2914
  {
2915
    { Bad_Opcode },
2916
    { Bad_Opcode },
2917
    { "vpsrld",   { Vex, Ux, Ib }, PREFIX_DATA },
2918
    { Bad_Opcode },
2919
    { "vpsrad",   { Vex, Ux, Ib }, PREFIX_DATA },
2920
    { Bad_Opcode },
2921
    { "vpslld",   { Vex, Ux, Ib }, PREFIX_DATA },
2922
  },
2923
  /* REG_VEX_0F73 */
2924
  {
2925
    { Bad_Opcode },
2926
    { Bad_Opcode },
2927
    { "vpsrlq",   { Vex, Ux, Ib }, PREFIX_DATA },
2928
    { "vpsrldq",  { Vex, Ux, Ib }, PREFIX_DATA },
2929
    { Bad_Opcode },
2930
    { Bad_Opcode },
2931
    { "vpsllq",   { Vex, Ux, Ib }, PREFIX_DATA },
2932
    { "vpslldq",  { Vex, Ux, Ib }, PREFIX_DATA },
2933
  },
2934
  /* REG_VEX_0FAE */
2935
  {
2936
    { Bad_Opcode },
2937
    { Bad_Opcode },
2938
    { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2) },
2939
    { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3) },
2940
  },
2941
  /* REG_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0 */
2942
  {
2943
    { RM_TABLE (RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0_R_0) },
2944
  },
2945
  /* REG_VEX_0F38F3_L_0_P_0 */
2946
  {
2947
    { Bad_Opcode },
2948
    { "%NFblsrS",   { VexGdq, Edq }, 0 },
2949
    { "%NFblsmskS",   { VexGdq, Edq }, 0 },
2950
    { "%NFblsiS",   { VexGdq, Edq }, 0 },
2951
  },
2952
  /* REG_VEX_MAP7_F8_L_0_W_0 */
2953
  {
2954
    { X86_64_TABLE (X86_64_VEX_MAP7_F8_L_0_W_0_R_0) },
2955
  },
2956
  /* REG_XOP_09_01_L_0 */
2957
  {
2958
    { Bad_Opcode },
2959
    { "blcfill",  { VexGdq, Edq }, 0 },
2960
    { "blsfill",  { VexGdq, Edq }, 0 },
2961
    { "blcs", { VexGdq, Edq }, 0 },
2962
    { "tzmsk",  { VexGdq, Edq }, 0 },
2963
    { "blcic",  { VexGdq, Edq }, 0 },
2964
    { "blsic",  { VexGdq, Edq }, 0 },
2965
    { "t1mskc", { VexGdq, Edq }, 0 },
2966
  },
2967
  /* REG_XOP_09_02_L_0 */
2968
  {
2969
    { Bad_Opcode },
2970
    { "blcmsk", { VexGdq, Edq }, 0 },
2971
    { Bad_Opcode },
2972
    { Bad_Opcode },
2973
    { Bad_Opcode },
2974
    { Bad_Opcode },
2975
    { "blci", { VexGdq, Edq }, 0 },
2976
  },
2977
  /* REG_XOP_09_12_L_0 */
2978
  {
2979
    { "llwpcb", { Rdq }, 0 },
2980
    { "slwpcb", { Rdq }, 0 },
2981
  },
2982
  /* REG_XOP_0A_12_L_0 */
2983
  {
2984
    { "lwpins", { VexGdq, Ed, Id }, 0 },
2985
    { "lwpval", { VexGdq, Ed, Id }, 0 },
2986
  },
2987
2988
#include "i386-dis-evex-reg.h"
2989
};
2990
2991
static const struct dis386 prefix_table[][4] = {
2992
  /* PREFIX_90 */
2993
  {
2994
    { "xchgS", { { NOP_Fixup, 0 }, { NOP_Fixup, 1 } }, 0 },
2995
    { "pause", { XX }, 0 },
2996
    { "xchgS", { { NOP_Fixup, 0 }, { NOP_Fixup, 1 } }, 0 },
2997
    { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
2998
  },
2999
3000
  /* PREFIX_0F00_REG_6_X86_64 */
3001
  {
3002
    { Bad_Opcode },
3003
    { Bad_Opcode },
3004
    { Bad_Opcode },
3005
    { "lkgsD", { Sv }, 0 },
3006
  },
3007
3008
  /* PREFIX_0F01_REG_0_MOD_3_RM_6 */
3009
  {
3010
    { "wrmsrns",        { Skip_MODRM }, 0 },
3011
    { X86_64_TABLE (X86_64_0F01_REG_0_MOD_3_RM_6_P_1) },
3012
    { Bad_Opcode },
3013
    { X86_64_TABLE (X86_64_0F01_REG_0_MOD_3_RM_6_P_3) },
3014
  },
3015
3016
  /* PREFIX_0F01_REG_0_MOD_3_RM_7 */
3017
  {
3018
    { X86_64_TABLE (X86_64_0F01_REG_0_MOD_3_RM_7_P_0) },
3019
  },
3020
3021
  /* PREFIX_0F01_REG_1_RM_2 */
3022
  {
3023
    { "clac",   { Skip_MODRM }, 0 },
3024
    { X86_64_TABLE (X86_64_0F01_REG_1_RM_2_PREFIX_1) },
3025
    { Bad_Opcode },
3026
    { X86_64_TABLE (X86_64_0F01_REG_1_RM_2_PREFIX_3)},
3027
  },
3028
3029
  /* PREFIX_0F01_REG_1_RM_4 */
3030
  {
3031
    { Bad_Opcode },
3032
    { Bad_Opcode },
3033
    { "tdcall",   { Skip_MODRM }, 0 },
3034
    { Bad_Opcode },
3035
  },
3036
3037
  /* PREFIX_0F01_REG_1_RM_5 */
3038
  {
3039
    { Bad_Opcode },
3040
    { Bad_Opcode },
3041
    { X86_64_TABLE (X86_64_0F01_REG_1_RM_5_PREFIX_2) },
3042
    { Bad_Opcode },
3043
  },
3044
3045
  /* PREFIX_0F01_REG_1_RM_6 */
3046
  {
3047
    { Bad_Opcode },
3048
    { Bad_Opcode },
3049
    { X86_64_TABLE (X86_64_0F01_REG_1_RM_6_PREFIX_2) },
3050
    { Bad_Opcode },
3051
  },
3052
3053
  /* PREFIX_0F01_REG_1_RM_7 */
3054
  {
3055
    { "encls",    { Skip_MODRM }, 0 },
3056
    { Bad_Opcode },
3057
    { X86_64_TABLE (X86_64_0F01_REG_1_RM_7_PREFIX_2) },
3058
    { Bad_Opcode },
3059
  },
3060
3061
  /* PREFIX_0F01_REG_3_RM_1 */
3062
  {
3063
    { "vmmcall",  { Skip_MODRM }, 0 },
3064
    { "vmgexit",  { Skip_MODRM }, 0 },
3065
    { Bad_Opcode },
3066
    { "vmgexit",  { Skip_MODRM }, 0 },
3067
  },
3068
3069
  /* PREFIX_0F01_REG_5_MOD_0 */
3070
  {
3071
    { Bad_Opcode },
3072
    { "rstorssp", { Mq }, PREFIX_OPCODE },
3073
  },
3074
3075
  /* PREFIX_0F01_REG_5_MOD_3_RM_0 */
3076
  {
3077
    { "serialize",  { Skip_MODRM }, PREFIX_OPCODE },
3078
    { "setssbsy", { Skip_MODRM }, PREFIX_OPCODE },
3079
    { Bad_Opcode },
3080
    { "xsusldtrk",  { Skip_MODRM }, PREFIX_OPCODE },
3081
  },
3082
3083
  /* PREFIX_0F01_REG_5_MOD_3_RM_1 */
3084
  {
3085
    { Bad_Opcode },
3086
    { Bad_Opcode },
3087
    { Bad_Opcode },
3088
    { "xresldtrk",     { Skip_MODRM }, PREFIX_OPCODE },
3089
  },
3090
3091
  /* PREFIX_0F01_REG_5_MOD_3_RM_2 */
3092
  {
3093
    { Bad_Opcode },
3094
    { "saveprevssp",  { Skip_MODRM }, PREFIX_OPCODE },
3095
  },
3096
3097
  /* PREFIX_0F01_REG_5_MOD_3_RM_4 */
3098
  {
3099
    { Bad_Opcode },
3100
    { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1) },
3101
  },
3102
3103
  /* PREFIX_0F01_REG_5_MOD_3_RM_5 */
3104
  {
3105
    { Bad_Opcode },
3106
    { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1) },
3107
  },
3108
3109
  /* PREFIX_0F01_REG_5_MOD_3_RM_6 */
3110
  {
3111
    { "rdpkru", { Skip_MODRM }, 0 },
3112
    { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1) },
3113
  },
3114
3115
  /* PREFIX_0F01_REG_5_MOD_3_RM_7 */
3116
  {
3117
    { "wrpkru", { Skip_MODRM }, 0 },
3118
    { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1) },
3119
  },
3120
3121
  /* PREFIX_0F01_REG_7_MOD_3_RM_2 */
3122
  {
3123
    { "monitorx", { { OP_Monitor, 0 } }, 0  },
3124
    { "mcommit",  { Skip_MODRM }, 0 },
3125
  },
3126
3127
  /* PREFIX_0F01_REG_7_MOD_3_RM_5 */
3128
  {
3129
    { "rdpru", { Skip_MODRM }, 0 },
3130
    { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_5_PREFIX_1) },
3131
  },
3132
3133
  /* PREFIX_0F01_REG_7_MOD_3_RM_6 */
3134
  {
3135
    { "invlpgb",        { Skip_MODRM }, 0 },
3136
    { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1) },
3137
    { Bad_Opcode },
3138
    { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3) },
3139
  },
3140
3141
  /* PREFIX_0F01_REG_7_MOD_3_RM_7 */
3142
  {
3143
    { "tlbsync",        { Skip_MODRM }, 0 },
3144
    { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1) },
3145
    { Bad_Opcode },
3146
    { "pvalidate",      { Skip_MODRM }, 0 },
3147
  },
3148
3149
  /* PREFIX_0F09 */
3150
  {
3151
    { "wbinvd",   { XX }, 0 },
3152
    { "wbnoinvd", { XX }, 0 },
3153
  },
3154
3155
  /* PREFIX_0F10 */
3156
  {
3157
    { "%XEVmovupX", { XM, EXEvexXNoBcst }, 0 },
3158
    { "%XEVmovs%XS",  { XMScalar, VexScalarR, EXd }, 0 },
3159
    { "%XEVmovupX", { XM, EXEvexXNoBcst }, 0 },
3160
    { "%XEVmovs%XD",  { XMScalar, VexScalarR, EXq }, 0 },
3161
  },
3162
3163
  /* PREFIX_0F11 */
3164
  {
3165
    { "%XEVmovupX", { EXxS, XM }, 0 },
3166
    { "%XEVmovs%XS",  { EXdS, VexScalarR, XMScalar }, 0 },
3167
    { "%XEVmovupX", { EXxS, XM }, 0 },
3168
    { "%XEVmovs%XD",  { EXqS, VexScalarR, XMScalar }, 0 },
3169
  },
3170
3171
  /* PREFIX_0F12 */
3172
  {
3173
    { MOD_TABLE (MOD_0F12_PREFIX_0) },
3174
    { "movsldup", { XM, EXx }, 0 },
3175
    { "%XEVmovlpYX",  { XM, Vex, Mq }, 0 },
3176
    { "movddup",  { XM, EXq }, 0 },
3177
  },
3178
3179
  /* PREFIX_0F16 */
3180
  {
3181
    { MOD_TABLE (MOD_0F16_PREFIX_0) },
3182
    { "movshdup", { XM, EXx }, 0 },
3183
    { "%XEVmovhpYX",  { XM, Vex, Mq }, 0 },
3184
  },
3185
3186
  /* PREFIX_0F18_REG_6_MOD_0_X86_64 */
3187
  {
3188
    { "prefetchit1",  { { PREFETCHI_Fixup, b_mode } }, 0 },
3189
    { "nopQ",   { Ev }, 0 },
3190
    { "nopQ",   { Ev }, 0 },
3191
    { "nopQ",   { Ev }, 0 },
3192
  },
3193
3194
  /* PREFIX_0F18_REG_7_MOD_0_X86_64 */
3195
  {
3196
    { "prefetchit0",  { { PREFETCHI_Fixup, b_mode } }, 0 },
3197
    { "nopQ",   { Ev }, 0 },
3198
    { "nopQ",   { Ev }, 0 },
3199
    { "nopQ",   { Ev }, 0 },
3200
  },
3201
3202
  /* PREFIX_0F1A */
3203
  {
3204
    { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3205
    { "bndcl",  { Gbnd, Ev_bnd }, 0 },
3206
    { "bndmov", { Gbnd, Ebnd }, 0 },
3207
    { "bndcu",  { Gbnd, Ev_bnd }, 0 },
3208
  },
3209
3210
  /* PREFIX_0F1B */
3211
  {
3212
    { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3213
    { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3214
    { "bndmov", { EbndS, Gbnd }, 0 },
3215
    { "bndcn",  { Gbnd, Ev_bnd }, 0 },
3216
  },
3217
3218
  /* PREFIX_0F1C */
3219
  {
3220
    { MOD_TABLE (MOD_0F1C_PREFIX_0) },
3221
    { "nopQ", { Ev }, PREFIX_IGNORED },
3222
    { "nopQ", { Ev }, 0 },
3223
    { "nopQ", { Ev }, PREFIX_IGNORED },
3224
  },
3225
3226
  /* PREFIX_0F1E */
3227
  {
3228
    { "nopQ", { Ev }, 0 },
3229
    { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3230
    { "nopQ", { Ev }, 0 },
3231
    { NULL, { XX }, PREFIX_IGNORED },
3232
  },
3233
3234
  /* PREFIX_0F2A */
3235
  {
3236
    { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3237
    { "cvtsi2ss{%LQ|}", { XM, Edq }, PREFIX_OPCODE },
3238
    { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3239
    { "cvtsi2sd{%LQ|}", { XM, Edq }, 0 },
3240
  },
3241
3242
  /* PREFIX_0F2B */
3243
  {
3244
    { "movntps", { Mx, XM }, 0 },
3245
    { "movntss", { Md, XM }, 0 },
3246
    { "movntpd", { Mx, XM }, 0 },
3247
    { "movntsd", { Mq, XM }, 0 },
3248
  },
3249
3250
  /* PREFIX_0F2C */
3251
  {
3252
    { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3253
    { "cvttss2si", { Gdq, EXd }, PREFIX_OPCODE },
3254
    { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3255
    { "cvttsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3256
  },
3257
3258
  /* PREFIX_0F2D */
3259
  {
3260
    { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3261
    { "cvtss2si", { Gdq, EXd }, PREFIX_OPCODE },
3262
    { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3263
    { "cvtsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3264
  },
3265
3266
  /* PREFIX_0F2E */
3267
  {
3268
    { "%XEVucomisYX", { XMScalar, EXd, EXxEVexS }, 0 },
3269
    { Bad_Opcode },
3270
    { "%XEVucomisYX", { XMScalar, EXq, EXxEVexS }, 0 },
3271
  },
3272
3273
  /* PREFIX_0F2F */
3274
  {
3275
    { "%XEVcomisYX",  { XMScalar, EXd, EXxEVexS }, 0 },
3276
    { Bad_Opcode },
3277
    { "%XEVcomisYX",  { XMScalar, EXq, EXxEVexS }, 0 },
3278
  },
3279
3280
  /* PREFIX_0F51 */
3281
  {
3282
    { "%XEVsqrtpX", { XM, EXx, EXxEVexR }, 0 },
3283
    { "%XEVsqrts%XS", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3284
    { "%XEVsqrtpX", { XM, EXx, EXxEVexR }, 0 },
3285
    { "%XEVsqrts%XD", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3286
  },
3287
3288
  /* PREFIX_0F52 */
3289
  {
3290
    { "Vrsqrtps", { XM, EXx }, 0 },
3291
    { "Vrsqrtss", { XMScalar, VexScalar, EXd }, 0 },
3292
  },
3293
3294
  /* PREFIX_0F53 */
3295
  {
3296
    { "Vrcpps",   { XM, EXx }, 0 },
3297
    { "Vrcpss",   { XMScalar, VexScalar, EXd }, 0 },
3298
  },
3299
3300
  /* PREFIX_0F58 */
3301
  {
3302
    { "%XEVaddpX",  { XM, Vex, EXx, EXxEVexR }, 0 },
3303
    { "%XEVadds%XS",  { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3304
    { "%XEVaddpX",  { XM, Vex, EXx, EXxEVexR }, 0 },
3305
    { "%XEVadds%XD",  { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3306
  },
3307
3308
  /* PREFIX_0F59 */
3309
  {
3310
    { "%XEVmulpX",  { XM, Vex, EXx, EXxEVexR }, 0 },
3311
    { "%XEVmuls%XS",  { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3312
    { "%XEVmulpX",  { XM, Vex, EXx, EXxEVexR }, 0 },
3313
    { "%XEVmuls%XD",  { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3314
  },
3315
3316
  /* PREFIX_0F5A */
3317
  {
3318
    { "%XEVcvtp%XS2pd", { XM, EXEvexHalfBcstXmmq, EXxEVexS }, 0 },
3319
    { "%XEVcvts%XS2sd", { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
3320
    { "%XEVcvtp%XD2ps%XY", { XMxmmq, EXx, EXxEVexR }, 0 },
3321
    { "%XEVcvts%XD2ss", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3322
  },
3323
3324
  /* PREFIX_0F5B */
3325
  {
3326
    { "Vcvtdq2ps",  { XM, EXx }, 0 },
3327
    { "Vcvttps2dq", { XM, EXx }, 0 },
3328
    { "Vcvtps2dq",  { XM, EXx }, 0 },
3329
  },
3330
3331
  /* PREFIX_0F5C */
3332
  {
3333
    { "%XEVsubpX",  { XM, Vex, EXx, EXxEVexR }, 0 },
3334
    { "%XEVsubs%XS",  { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3335
    { "%XEVsubpX",  { XM, Vex, EXx, EXxEVexR }, 0 },
3336
    { "%XEVsubs%XD",  { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3337
  },
3338
3339
  /* PREFIX_0F5D */
3340
  {
3341
    { "%XEVminpX",  { XM, Vex, EXx, EXxEVexS }, 0 },
3342
    { "%XEVmins%XS",  { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
3343
    { "%XEVminpX",  { XM, Vex, EXx, EXxEVexS }, 0 },
3344
    { "%XEVmins%XD",  { XMScalar, VexScalar, EXq, EXxEVexS }, 0 },
3345
  },
3346
3347
  /* PREFIX_0F5E */
3348
  {
3349
    { "%XEVdivpX",  { XM, Vex, EXx, EXxEVexR }, 0 },
3350
    { "%XEVdivs%XS",  { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3351
    { "%XEVdivpX",  { XM, Vex, EXx, EXxEVexR }, 0 },
3352
    { "%XEVdivs%XD",  { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3353
  },
3354
3355
  /* PREFIX_0F5F */
3356
  {
3357
    { "%XEVmaxpX",  { XM, Vex, EXx, EXxEVexS }, 0 },
3358
    { "%XEVmaxs%XS",  { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
3359
    { "%XEVmaxpX",  { XM, Vex, EXx, EXxEVexS }, 0 },
3360
    { "%XEVmaxs%XD",  { XMScalar, VexScalar, EXq, EXxEVexS }, 0 },
3361
  },
3362
3363
  /* PREFIX_0F60 */
3364
  {
3365
    { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3366
    { Bad_Opcode },
3367
    { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3368
  },
3369
3370
  /* PREFIX_0F61 */
3371
  {
3372
    { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3373
    { Bad_Opcode },
3374
    { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3375
  },
3376
3377
  /* PREFIX_0F62 */
3378
  {
3379
    { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
3380
    { Bad_Opcode },
3381
    { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
3382
  },
3383
3384
  /* PREFIX_0F6F */
3385
  {
3386
    { "movq", { MX, EM }, PREFIX_OPCODE },
3387
    { "movdqu", { XM, EXx }, PREFIX_OPCODE },
3388
    { "movdqa", { XM, EXx }, PREFIX_OPCODE },
3389
  },
3390
3391
  /* PREFIX_0F70 */
3392
  {
3393
    { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
3394
    { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3395
    { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
3396
    { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3397
  },
3398
3399
  /* PREFIX_0F78 */
3400
  {
3401
    {"vmread",  { Em, Gm }, 0 },
3402
    { Bad_Opcode },
3403
    {"extrq", { Uxmm, Ib, Ib }, 0 },
3404
    {"insertq", { XM, Uxmm, Ib, Ib }, 0 },
3405
  },
3406
3407
  /* PREFIX_0F79 */
3408
  {
3409
    {"vmwrite", { Gm, Em }, 0 },
3410
    { Bad_Opcode },
3411
    {"extrq", { XM, Uxmm }, 0 },
3412
    {"insertq", { XM, Uxmm }, 0 },
3413
  },
3414
3415
  /* PREFIX_0F7C */
3416
  {
3417
    { Bad_Opcode },
3418
    { Bad_Opcode },
3419
    { "Vhaddpd",  { XM, Vex, EXx }, 0 },
3420
    { "Vhaddps",  { XM, Vex, EXx }, 0 },
3421
  },
3422
3423
  /* PREFIX_0F7D */
3424
  {
3425
    { Bad_Opcode },
3426
    { Bad_Opcode },
3427
    { "Vhsubpd",  { XM, Vex, EXx }, 0 },
3428
    { "Vhsubps",  { XM, Vex, EXx }, 0 },
3429
  },
3430
3431
  /* PREFIX_0F7E */
3432
  {
3433
    { "movK", { Edq, MX }, PREFIX_OPCODE },
3434
    { "movq", { XM, EXq }, PREFIX_OPCODE },
3435
    { "movK", { Edq, XM }, PREFIX_OPCODE },
3436
  },
3437
3438
  /* PREFIX_0F7F */
3439
  {
3440
    { "movq", { EMS, MX }, PREFIX_OPCODE },
3441
    { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
3442
    { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
3443
  },
3444
3445
  /* PREFIX_0FAE_REG_0_MOD_3 */
3446
  {
3447
    { Bad_Opcode },
3448
    { "rdfsbase", { Ev }, 0 },
3449
  },
3450
3451
  /* PREFIX_0FAE_REG_1_MOD_3 */
3452
  {
3453
    { Bad_Opcode },
3454
    { "rdgsbase", { Ev }, 0 },
3455
  },
3456
3457
  /* PREFIX_0FAE_REG_2_MOD_3 */
3458
  {
3459
    { Bad_Opcode },
3460
    { "wrfsbase", { Ev }, 0 },
3461
  },
3462
3463
  /* PREFIX_0FAE_REG_3_MOD_3 */
3464
  {
3465
    { Bad_Opcode },
3466
    { "wrgsbase", { Ev }, 0 },
3467
  },
3468
3469
  /* PREFIX_0FAE_REG_4_MOD_0 */
3470
  {
3471
    { "xsave",  { FXSAVE }, PREFIX_REX2_ILLEGAL },
3472
    { "ptwrite{%LQ|}", { Edq }, 0 },
3473
  },
3474
3475
  /* PREFIX_0FAE_REG_4_MOD_3 */
3476
  {
3477
    { Bad_Opcode },
3478
    { "ptwrite{%LQ|}", { Edq }, 0 },
3479
  },
3480
3481
  /* PREFIX_0FAE_REG_5_MOD_3 */
3482
  {
3483
    { "lfence",   { Skip_MODRM }, 0 },
3484
    { "incsspK",  { Edq }, PREFIX_OPCODE },
3485
  },
3486
3487
  /* PREFIX_0FAE_REG_6_MOD_0 */
3488
  {
3489
    { "xsaveopt", { FXSAVE }, PREFIX_OPCODE | PREFIX_REX2_ILLEGAL },
3490
    { "clrssbsy", { Mq }, PREFIX_OPCODE },
3491
    { "clwb", { Mb }, PREFIX_OPCODE },
3492
  },
3493
3494
  /* PREFIX_0FAE_REG_6_MOD_3 */
3495
  {
3496
    { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0) },
3497
    { "umonitor", { Eva }, PREFIX_OPCODE },
3498
    { "tpause", { Edq }, PREFIX_OPCODE },
3499
    { "umwait", { Edq }, PREFIX_OPCODE },
3500
  },
3501
3502
  /* PREFIX_0FAE_REG_7_MOD_0 */
3503
  {
3504
    { "clflush",  { Mb }, 0 },
3505
    { Bad_Opcode },
3506
    { "clflushopt", { Mb }, 0 },
3507
  },
3508
3509
  /* PREFIX_0FB8 */
3510
  {
3511
    { Bad_Opcode },
3512
    { "popcntS", { Gv, Ev }, 0 },
3513
  },
3514
3515
  /* PREFIX_0FBC */
3516
  {
3517
    { "bsfS", { Gv, Ev }, 0 },
3518
    { "tzcntS", { Gv, Ev }, 0 },
3519
    { "bsfS", { Gv, Ev }, 0 },
3520
  },
3521
3522
  /* PREFIX_0FBD */
3523
  {
3524
    { "bsrS", { Gv, Ev }, 0 },
3525
    { "lzcntS", { Gv, Ev }, 0 },
3526
    { "bsrS", { Gv, Ev }, 0 },
3527
  },
3528
3529
  /* PREFIX_0FC2 */
3530
  {
3531
    { "VcmppX", { XM, Vex, EXx, CMP }, 0 },
3532
    { "Vcmpss", { XMScalar, VexScalar, EXd, CMP }, 0 },
3533
    { "VcmppX", { XM, Vex, EXx, CMP }, 0 },
3534
    { "Vcmpsd", { XMScalar, VexScalar, EXq, CMP }, 0 },
3535
  },
3536
3537
  /* PREFIX_0FC7_REG_6_MOD_0 */
3538
  {
3539
    { "vmptrld",{ Mq }, 0 },
3540
    { "vmxon",  { Mq }, 0 },
3541
    { "vmclear",{ Mq }, 0 },
3542
  },
3543
3544
  /* PREFIX_0FC7_REG_6_MOD_3 */
3545
  {
3546
    { "rdrand", { Ev }, 0 },
3547
    { X86_64_TABLE (X86_64_0FC7_REG_6_MOD_3_PREFIX_1) },
3548
    { "rdrand", { Ev }, 0 }
3549
  },
3550
3551
  /* PREFIX_0FC7_REG_7_MOD_3 */
3552
  {
3553
    { "rdseed", { Ev }, 0 },
3554
    { "rdpid",  { Em }, 0 },
3555
    { "rdseed", { Ev }, 0 },
3556
  },
3557
3558
  /* PREFIX_0FD0 */
3559
  {
3560
    { Bad_Opcode },
3561
    { Bad_Opcode },
3562
    { "VaddsubpX",  { XM, Vex, EXx }, 0 },
3563
    { "VaddsubpX",  { XM, Vex, EXx }, 0 },
3564
  },
3565
3566
  /* PREFIX_0FD6 */
3567
  {
3568
    { Bad_Opcode },
3569
    { "movq2dq",{ XM, Nq }, 0 },
3570
    { "movq", { EXqS, XM }, 0 },
3571
    { "movdq2q",{ MX, Ux }, 0 },
3572
  },
3573
3574
  /* PREFIX_0FE6 */
3575
  {
3576
    { Bad_Opcode },
3577
    { "Vcvtdq2pd",  { XM, EXxmmq }, 0 },
3578
    { "Vcvttpd2dq%XY",  { XMM, EXx }, 0 },
3579
    { "Vcvtpd2dq%XY", { XMM, EXx }, 0 },
3580
  },
3581
3582
  /* PREFIX_0FE7 */
3583
  {
3584
    { "movntq",   { Mq, MX }, 0 },
3585
    { Bad_Opcode },
3586
    { "movntdq",  { Mx, XM }, 0 },
3587
  },
3588
3589
  /* PREFIX_0FF0 */
3590
  {
3591
    { Bad_Opcode },
3592
    { Bad_Opcode },
3593
    { Bad_Opcode },
3594
    { "Vlddqu",   { XM, M }, 0 },
3595
  },
3596
3597
  /* PREFIX_0FF7 */
3598
  {
3599
    { "maskmovq", { MX, Nq }, PREFIX_OPCODE },
3600
    { Bad_Opcode },
3601
    { "maskmovdqu", { XM, Ux }, PREFIX_OPCODE },
3602
  },
3603
3604
  /* PREFIX_0F38D8 */
3605
  {
3606
    { Bad_Opcode },
3607
    { REG_TABLE (REG_0F38D8_PREFIX_1) },
3608
  },
3609
3610
  /* PREFIX_0F38DC */
3611
  {
3612
    { Bad_Opcode },
3613
    { MOD_TABLE (MOD_0F38DC_PREFIX_1) },
3614
    { "aesenc", { XM, EXx }, 0 },
3615
  },
3616
3617
  /* PREFIX_0F38DD */
3618
  {
3619
    { Bad_Opcode },
3620
    { "aesdec128kl", { XM, M }, 0 },
3621
    { "aesenclast", { XM, EXx }, 0 },
3622
  },
3623
3624
  /* PREFIX_0F38DE */
3625
  {
3626
    { Bad_Opcode },
3627
    { "aesenc256kl", { XM, M }, 0 },
3628
    { "aesdec", { XM, EXx }, 0 },
3629
  },
3630
3631
  /* PREFIX_0F38DF */
3632
  {
3633
    { Bad_Opcode },
3634
    { "aesdec256kl", { XM, M }, 0 },
3635
    { "aesdeclast", { XM, EXx }, 0 },
3636
  },
3637
3638
  /* PREFIX_0F38F0 */
3639
  {
3640
    { "movbeS", { Gv, Mv }, PREFIX_OPCODE },
3641
    { Bad_Opcode },
3642
    { "movbeS", { Gv, Mv }, PREFIX_OPCODE },
3643
    { "crc32A", { Gdq, Eb }, PREFIX_OPCODE },
3644
  },
3645
3646
  /* PREFIX_0F38F1 */
3647
  {
3648
    { "movbeS", { Mv, Gv }, PREFIX_OPCODE },
3649
    { Bad_Opcode },
3650
    { "movbeS", { Mv, Gv }, PREFIX_OPCODE },
3651
    { "crc32Q", { Gdq, Ev }, PREFIX_OPCODE },
3652
  },
3653
3654
  /* PREFIX_0F38F6 */
3655
  {
3656
    { "wrssK",  { M, Gdq }, 0 },
3657
    { "adoxL",  { VexGdq, Gdq, Edq }, 0 },
3658
    { "adcxL",  { VexGdq, Gdq, Edq }, 0 },
3659
    { Bad_Opcode },
3660
  },
3661
3662
  /* PREFIX_0F38F8_M_0 */
3663
  {
3664
    { Bad_Opcode },
3665
    { "enqcmds", { Gva, M }, 0 },
3666
    { "movdir64b", { Gva, M }, 0 },
3667
    { "enqcmd", { Gva, M }, 0 },
3668
  },
3669
3670
  /* PREFIX_0F38F8_M_1_X86_64 */
3671
  {
3672
    { Bad_Opcode },
3673
    { "uwrmsr",   { Gq, Rq }, 0 },
3674
    { Bad_Opcode },
3675
    { "urdmsr",   { Rq, Gq }, 0 },
3676
  },
3677
3678
  /* PREFIX_0F38FA */
3679
  {
3680
    { Bad_Opcode },
3681
    { "encodekey128", { Gd, Rd }, 0 },
3682
  },
3683
3684
  /* PREFIX_0F38FB */
3685
  {
3686
    { Bad_Opcode },
3687
    { "encodekey256", { Gd, Rd }, 0 },
3688
  },
3689
3690
  /* PREFIX_0F38FC */
3691
  {
3692
    { "aadd", { Mdq, Gdq }, 0 },
3693
    { "axor", { Mdq, Gdq }, 0 },
3694
    { "aand", { Mdq, Gdq }, 0 },
3695
    { "aor",  { Mdq, Gdq }, 0 },
3696
  },
3697
3698
  /* PREFIX_0F3A0F */
3699
  {
3700
    { Bad_Opcode },
3701
    { REG_TABLE (REG_0F3A0F_P_1) },
3702
  },
3703
3704
  /* PREFIX_VEX_0F12 */
3705
  {
3706
    { VEX_LEN_TABLE (VEX_LEN_0F12_P_0) },
3707
    { "%XEvmov%XSldup", { XM, EXEvexXNoBcst }, 0 },
3708
    { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
3709
    { "%XEvmov%XDdup",  { XM, EXymmq }, 0 },
3710
  },
3711
3712
  /* PREFIX_VEX_0F16 */
3713
  {
3714
    { VEX_LEN_TABLE (VEX_LEN_0F16_P_0) },
3715
    { "%XEvmov%XShdup", { XM, EXEvexXNoBcst }, 0 },
3716
    { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
3717
  },
3718
3719
  /* PREFIX_VEX_0F2A */
3720
  {
3721
    { Bad_Opcode },
3722
    { "%XEvcvtsi2ssY{%LQ|}",  { XMScalar, VexScalar, EXxEVexR, Edq }, 0 },
3723
    { Bad_Opcode },
3724
    { "%XEvcvtsi2sdY{%LQ|}",  { XMScalar, VexScalar, EXxEVexR64, Edq }, 0 },
3725
  },
3726
3727
  /* PREFIX_VEX_0F2C */
3728
  {
3729
    { Bad_Opcode },
3730
    { "%XEvcvttss2si",  { Gdq, EXd, EXxEVexS }, 0 },
3731
    { Bad_Opcode },
3732
    { "%XEvcvttsd2si",  { Gdq, EXq, EXxEVexS }, 0 },
3733
  },
3734
3735
  /* PREFIX_VEX_0F2D */
3736
  {
3737
    { Bad_Opcode },
3738
    { "%XEvcvtss2si", { Gdq, EXd, EXxEVexR }, 0 },
3739
    { Bad_Opcode },
3740
    { "%XEvcvtsd2si", { Gdq, EXq, EXxEVexR }, 0 },
3741
  },
3742
3743
  /* PREFIX_VEX_0F41_L_1_W_0 */
3744
  {
3745
    { "kandw",          { MaskG, MaskVex, MaskR }, 0 },
3746
    { Bad_Opcode },
3747
    { "kandb",          { MaskG, MaskVex, MaskR }, 0 },
3748
  },
3749
3750
  /* PREFIX_VEX_0F41_L_1_W_1 */
3751
  {
3752
    { "kandq",          { MaskG, MaskVex, MaskR }, 0 },
3753
    { Bad_Opcode },
3754
    { "kandd",          { MaskG, MaskVex, MaskR }, 0 },
3755
  },
3756
3757
  /* PREFIX_VEX_0F42_L_1_W_0 */
3758
  {
3759
    { "kandnw",         { MaskG, MaskVex, MaskR }, 0 },
3760
    { Bad_Opcode },
3761
    { "kandnb",         { MaskG, MaskVex, MaskR }, 0 },
3762
  },
3763
3764
  /* PREFIX_VEX_0F42_L_1_W_1 */
3765
  {
3766
    { "kandnq",         { MaskG, MaskVex, MaskR }, 0 },
3767
    { Bad_Opcode },
3768
    { "kandnd",         { MaskG, MaskVex, MaskR }, 0 },
3769
  },
3770
3771
  /* PREFIX_VEX_0F44_L_0_W_0 */
3772
  {
3773
    { "knotw",          { MaskG, MaskR }, 0 },
3774
    { Bad_Opcode },
3775
    { "knotb",          { MaskG, MaskR }, 0 },
3776
  },
3777
3778
  /* PREFIX_VEX_0F44_L_0_W_1 */
3779
  {
3780
    { "knotq",          { MaskG, MaskR }, 0 },
3781
    { Bad_Opcode },
3782
    { "knotd",          { MaskG, MaskR }, 0 },
3783
  },
3784
3785
  /* PREFIX_VEX_0F45_L_1_W_0 */
3786
  {
3787
    { "korw",       { MaskG, MaskVex, MaskR }, 0 },
3788
    { Bad_Opcode },
3789
    { "korb",       { MaskG, MaskVex, MaskR }, 0 },
3790
  },
3791
3792
  /* PREFIX_VEX_0F45_L_1_W_1 */
3793
  {
3794
    { "korq",       { MaskG, MaskVex, MaskR }, 0 },
3795
    { Bad_Opcode },
3796
    { "kord",       { MaskG, MaskVex, MaskR }, 0 },
3797
  },
3798
3799
  /* PREFIX_VEX_0F46_L_1_W_0 */
3800
  {
3801
    { "kxnorw",     { MaskG, MaskVex, MaskR }, 0 },
3802
    { Bad_Opcode },
3803
    { "kxnorb",     { MaskG, MaskVex, MaskR }, 0 },
3804
  },
3805
3806
  /* PREFIX_VEX_0F46_L_1_W_1 */
3807
  {
3808
    { "kxnorq",     { MaskG, MaskVex, MaskR }, 0 },
3809
    { Bad_Opcode },
3810
    { "kxnord",     { MaskG, MaskVex, MaskR }, 0 },
3811
  },
3812
3813
  /* PREFIX_VEX_0F47_L_1_W_0 */
3814
  {
3815
    { "kxorw",      { MaskG, MaskVex, MaskR }, 0 },
3816
    { Bad_Opcode },
3817
    { "kxorb",      { MaskG, MaskVex, MaskR }, 0 },
3818
  },
3819
3820
  /* PREFIX_VEX_0F47_L_1_W_1 */
3821
  {
3822
    { "kxorq",      { MaskG, MaskVex, MaskR }, 0 },
3823
    { Bad_Opcode },
3824
    { "kxord",      { MaskG, MaskVex, MaskR }, 0 },
3825
  },
3826
3827
  /* PREFIX_VEX_0F4A_L_1_W_0 */
3828
  {
3829
    { "kaddw",          { MaskG, MaskVex, MaskR }, 0 },
3830
    { Bad_Opcode },
3831
    { "kaddb",          { MaskG, MaskVex, MaskR }, 0 },
3832
  },
3833
3834
  /* PREFIX_VEX_0F4A_L_1_W_1 */
3835
  {
3836
    { "kaddq",          { MaskG, MaskVex, MaskR }, 0 },
3837
    { Bad_Opcode },
3838
    { "kaddd",          { MaskG, MaskVex, MaskR }, 0 },
3839
  },
3840
3841
  /* PREFIX_VEX_0F4B_L_1_W_0 */
3842
  {
3843
    { "kunpckwd",   { MaskG, MaskVex, MaskR }, 0 },
3844
    { Bad_Opcode },
3845
    { "kunpckbw",   { MaskG, MaskVex, MaskR }, 0 },
3846
  },
3847
3848
  /* PREFIX_VEX_0F4B_L_1_W_1 */
3849
  {
3850
    { "kunpckdq",   { MaskG, MaskVex, MaskR }, 0 },
3851
  },
3852
3853
  /* PREFIX_VEX_0F6F */
3854
  {
3855
    { Bad_Opcode },
3856
    { "vmovdqu",  { XM, EXx }, 0 },
3857
    { "vmovdqa",  { XM, EXx }, 0 },
3858
  },
3859
3860
  /* PREFIX_VEX_0F70 */
3861
  {
3862
    { Bad_Opcode },
3863
    { "vpshufhw", { XM, EXx, Ib }, 0 },
3864
    { "vpshufd",  { XM, EXx, Ib }, 0 },
3865
    { "vpshuflw", { XM, EXx, Ib }, 0 },
3866
  },
3867
3868
  /* PREFIX_VEX_0F7E */
3869
  {
3870
    { Bad_Opcode },
3871
    { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
3872
    { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
3873
  },
3874
3875
  /* PREFIX_VEX_0F7F */
3876
  {
3877
    { Bad_Opcode },
3878
    { "vmovdqu",  { EXxS, XM }, 0 },
3879
    { "vmovdqa",  { EXxS, XM }, 0 },
3880
  },
3881
3882
  /* PREFIX_VEX_0F90_L_0_W_0 */
3883
  {
3884
    { "%XEkmovw",   { MaskG, MaskE }, 0 },
3885
    { Bad_Opcode },
3886
    { "%XEkmovb",   { MaskG, MaskBDE }, 0 },
3887
  },
3888
3889
  /* PREFIX_VEX_0F90_L_0_W_1 */
3890
  {
3891
    { "%XEkmovq",   { MaskG, MaskE }, 0 },
3892
    { Bad_Opcode },
3893
    { "%XEkmovd",   { MaskG, MaskBDE }, 0 },
3894
  },
3895
3896
  /* PREFIX_VEX_0F91_L_0_W_0 */
3897
  {
3898
    { "%XEkmovw",   { Mw, MaskG }, 0 },
3899
    { Bad_Opcode },
3900
    { "%XEkmovb",   { Mb, MaskG }, 0 },
3901
  },
3902
3903
  /* PREFIX_VEX_0F91_L_0_W_1 */
3904
  {
3905
    { "%XEkmovq",   { Mq, MaskG }, 0 },
3906
    { Bad_Opcode },
3907
    { "%XEkmovd",   { Md, MaskG }, 0 },
3908
  },
3909
3910
  /* PREFIX_VEX_0F92_L_0_W_0 */
3911
  {
3912
    { "%XEkmovw",   { MaskG, Rdq }, 0 },
3913
    { Bad_Opcode },
3914
    { "%XEkmovb",   { MaskG, Rdq }, 0 },
3915
    { "%XEkmovd",   { MaskG, Rdq }, 0 },
3916
  },
3917
3918
  /* PREFIX_VEX_0F92_L_0_W_1 */
3919
  {
3920
    { Bad_Opcode },
3921
    { Bad_Opcode },
3922
    { Bad_Opcode },
3923
    { "%XEkmovK",   { MaskG, Rdq }, 0 },
3924
  },
3925
3926
  /* PREFIX_VEX_0F93_L_0_W_0 */
3927
  {
3928
    { "%XEkmovw",   { Gdq, MaskR }, 0 },
3929
    { Bad_Opcode },
3930
    { "%XEkmovb",   { Gdq, MaskR }, 0 },
3931
    { "%XEkmovd",   { Gdq, MaskR }, 0 },
3932
  },
3933
3934
  /* PREFIX_VEX_0F93_L_0_W_1 */
3935
  {
3936
    { Bad_Opcode },
3937
    { Bad_Opcode },
3938
    { Bad_Opcode },
3939
    { "%XEkmovK",   { Gdq, MaskR }, 0 },
3940
  },
3941
3942
  /* PREFIX_VEX_0F98_L_0_W_0 */
3943
  {
3944
    { "kortestw", { MaskG, MaskR }, 0 },
3945
    { Bad_Opcode },
3946
    { "kortestb", { MaskG, MaskR }, 0 },
3947
  },
3948
3949
  /* PREFIX_VEX_0F98_L_0_W_1 */
3950
  {
3951
    { "kortestq", { MaskG, MaskR }, 0 },
3952
    { Bad_Opcode },
3953
    { "kortestd", { MaskG, MaskR }, 0 },
3954
  },
3955
3956
  /* PREFIX_VEX_0F99_L_0_W_0 */
3957
  {
3958
    { "ktestw", { MaskG, MaskR }, 0 },
3959
    { Bad_Opcode },
3960
    { "ktestb", { MaskG, MaskR }, 0 },
3961
  },
3962
3963
  /* PREFIX_VEX_0F99_L_0_W_1 */
3964
  {
3965
    { "ktestq", { MaskG, MaskR }, 0 },
3966
    { Bad_Opcode },
3967
    { "ktestd", { MaskG, MaskR }, 0 },
3968
  },
3969
3970
  /* PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_0 */
3971
  {
3972
    { "ldtilecfg", { M }, 0 },
3973
    { Bad_Opcode },
3974
    { "sttilecfg", { M }, 0 },
3975
  },
3976
3977
  /* PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_1 */
3978
  {
3979
    { REG_TABLE (REG_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0) },
3980
    { Bad_Opcode },
3981
    { Bad_Opcode },
3982
    { RM_TABLE (RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_3) },
3983
  },
3984
3985
  /* PREFIX_VEX_0F384B_X86_64_L_0_W_0 */
3986
  {
3987
    { Bad_Opcode },
3988
    { "tilestored", { MVexSIBMEM, TMM }, 0 },
3989
    { "tileloaddt1",  { TMM, MVexSIBMEM }, 0 },
3990
    { "tileloadd",  { TMM, MVexSIBMEM }, 0 },
3991
  },
3992
3993
  /* PREFIX_VEX_0F3850_W_0 */
3994
  {
3995
    { "vpdpbuud", { XM, Vex, EXx }, 0 },
3996
    { "vpdpbsud", { XM, Vex, EXx }, 0 },
3997
    { "%XVvpdpbusd",  { XM, Vex, EXx }, 0 },
3998
    { "vpdpbssd", { XM, Vex, EXx }, 0 },
3999
  },
4000
4001
  /* PREFIX_VEX_0F3851_W_0 */
4002
  {
4003
    { "vpdpbuuds",  { XM, Vex, EXx }, 0 },
4004
    { "vpdpbsuds",  { XM, Vex, EXx }, 0 },
4005
    { "%XVvpdpbusds", { XM, Vex, EXx }, 0 },
4006
    { "vpdpbssds",  { XM, Vex, EXx }, 0 },
4007
  },
4008
  /* PREFIX_VEX_0F385C_X86_64_L_0_W_0 */
4009
  {
4010
    { Bad_Opcode },
4011
    { "tdpbf16ps", { TMM, Rtmm, VexTmm }, 0 },
4012
    { Bad_Opcode },
4013
    { "tdpfp16ps", { TMM, Rtmm, VexTmm }, 0 },
4014
  },
4015
4016
  /* PREFIX_VEX_0F385E_X86_64_L_0_W_0 */
4017
  {
4018
    { "tdpbuud", {TMM, Rtmm, VexTmm }, 0 },
4019
    { "tdpbsud", {TMM, Rtmm, VexTmm }, 0 },
4020
    { "tdpbusd", {TMM, Rtmm, VexTmm }, 0 },
4021
    { "tdpbssd", {TMM, Rtmm, VexTmm }, 0 },
4022
  },
4023
4024
  /* PREFIX_VEX_0F386C_X86_64_L_0_W_0 */
4025
  {
4026
    { "tcmmrlfp16ps", { TMM, Rtmm, VexTmm }, 0 },
4027
    { Bad_Opcode },
4028
    { "tcmmimfp16ps", { TMM, Rtmm, VexTmm }, 0 },
4029
  },
4030
4031
  /* PREFIX_VEX_0F3872 */
4032
  {
4033
    { Bad_Opcode },
4034
    { VEX_W_TABLE (VEX_W_0F3872_P_1) },
4035
  },
4036
4037
  /* PREFIX_VEX_0F38B0_W_0 */
4038
  {
4039
    { "vcvtneoph2ps", { XM, Mx }, 0 },
4040
    { "vcvtneebf162ps", { XM, Mx }, 0 },
4041
    { "vcvtneeph2ps", { XM, Mx }, 0 },
4042
    { "vcvtneobf162ps", { XM, Mx }, 0 },
4043
  },
4044
4045
  /* PREFIX_VEX_0F38B1_W_0 */
4046
  {
4047
    { Bad_Opcode },
4048
    { "vbcstnebf162ps", { XM, Mw }, 0 },
4049
    { "vbcstnesh2ps", { XM, Mw }, 0 },
4050
  },
4051
 
4052
  /* PREFIX_VEX_0F38D2_W_0 */
4053
  {
4054
    { "vpdpwuud", { XM, Vex, EXx }, 0 },
4055
    { "vpdpwsud", { XM, Vex, EXx }, 0 },
4056
    { "vpdpwusd", { XM, Vex, EXx }, 0 },
4057
  },
4058
4059
  /* PREFIX_VEX_0F38D3_W_0 */
4060
  {
4061
    { "vpdpwuuds",  { XM, Vex, EXx }, 0 },
4062
    { "vpdpwsuds",  { XM, Vex, EXx }, 0 },
4063
    { "vpdpwusds",  { XM, Vex, EXx }, 0 },
4064
  },
4065
4066
  /* PREFIX_VEX_0F38CB */
4067
  {
4068
    { Bad_Opcode },
4069
    { Bad_Opcode },
4070
    { Bad_Opcode },
4071
    { VEX_W_TABLE (VEX_W_0F38CB_P_3) },
4072
  },
4073
4074
  /* PREFIX_VEX_0F38CC */
4075
  {
4076
    { Bad_Opcode },
4077
    { Bad_Opcode },
4078
    { Bad_Opcode },
4079
    { VEX_W_TABLE (VEX_W_0F38CC_P_3) },
4080
  },
4081
4082
  /* PREFIX_VEX_0F38CD */
4083
  {
4084
    { Bad_Opcode },
4085
    { Bad_Opcode },
4086
    { Bad_Opcode },
4087
    { VEX_W_TABLE (VEX_W_0F38CD_P_3) },
4088
  },
4089
4090
  /* PREFIX_VEX_0F38DA_W_0 */
4091
  {
4092
    { VEX_LEN_TABLE (VEX_LEN_0F38DA_W_0_P_0) },
4093
    { "vsm4key4", { XM, Vex, EXx }, 0 },
4094
    { VEX_LEN_TABLE (VEX_LEN_0F38DA_W_0_P_2) },
4095
    { "vsm4rnds4", { XM, Vex, EXx }, 0 },
4096
  },
4097
4098
  /* PREFIX_VEX_0F38F2_L_0 */
4099
  {
4100
    { "%NFandnS",          { Gdq, VexGdq, Edq }, 0 },
4101
  },
4102
4103
  /* PREFIX_VEX_0F38F3_L_0 */
4104
  {
4105
    { REG_TABLE (REG_VEX_0F38F3_L_0_P_0) },
4106
  },
4107
4108
  /* PREFIX_VEX_0F38F5_L_0 */
4109
  {
4110
    { "%NFbzhiS", { Gdq, Edq, VexGdq }, 0 },
4111
    { "%XEpextS",   { Gdq, VexGdq, Edq }, 0 },
4112
    { Bad_Opcode },
4113
    { "%XEpdepS",   { Gdq, VexGdq, Edq }, 0 },
4114
  },
4115
4116
  /* PREFIX_VEX_0F38F6_L_0 */
4117
  {
4118
    { Bad_Opcode },
4119
    { Bad_Opcode },
4120
    { Bad_Opcode },
4121
    { "%XEmulxS",   { Gdq, VexGdq, Edq }, 0 },
4122
  },
4123
4124
  /* PREFIX_VEX_0F38F7_L_0 */
4125
  {
4126
    { "%NFbextrS",  { Gdq, Edq, VexGdq }, 0 },
4127
    { "%XEsarxS",   { Gdq, Edq, VexGdq }, 0 },
4128
    { "%XEshlxS",   { Gdq, Edq, VexGdq }, 0 },
4129
    { "%XEshrxS",   { Gdq, Edq, VexGdq }, 0 },
4130
  },
4131
4132
  /* PREFIX_VEX_0F3AF0_L_0 */
4133
  {
4134
    { Bad_Opcode },
4135
    { Bad_Opcode },
4136
    { Bad_Opcode },
4137
    { "%XErorxS",   { Gdq, Edq, Ib }, 0 },
4138
  },
4139
4140
  /* PREFIX_VEX_MAP7_F8_L_0_W_0_R_0_X86_64 */
4141
  {
4142
    { Bad_Opcode },
4143
    { "uwrmsr", { Skip_MODRM, Id, Rq }, 0 },
4144
    { Bad_Opcode },
4145
    { "urdmsr", { Rq, Id }, 0 },
4146
  },
4147
4148
#include "i386-dis-evex-prefix.h"
4149
};
4150
4151
static const struct dis386 x86_64_table[][2] = {
4152
  /* X86_64_06 */
4153
  {
4154
    { "pushP", { es }, 0 },
4155
  },
4156
4157
  /* X86_64_07 */
4158
  {
4159
    { "popP", { es }, 0 },
4160
  },
4161
4162
  /* X86_64_0E */
4163
  {
4164
    { "pushP", { cs }, 0 },
4165
  },
4166
4167
  /* X86_64_16 */
4168
  {
4169
    { "pushP", { ss }, 0 },
4170
  },
4171
4172
  /* X86_64_17 */
4173
  {
4174
    { "popP", { ss }, 0 },
4175
  },
4176
4177
  /* X86_64_1E */
4178
  {
4179
    { "pushP", { ds }, 0 },
4180
  },
4181
4182
  /* X86_64_1F */
4183
  {
4184
    { "popP", { ds }, 0 },
4185
  },
4186
4187
  /* X86_64_27 */
4188
  {
4189
    { "daa", { XX }, 0 },
4190
  },
4191
4192
  /* X86_64_2F */
4193
  {
4194
    { "das", { XX }, 0 },
4195
  },
4196
4197
  /* X86_64_37 */
4198
  {
4199
    { "aaa", { XX }, 0 },
4200
  },
4201
4202
  /* X86_64_3F */
4203
  {
4204
    { "aas", { XX }, 0 },
4205
  },
4206
4207
  /* X86_64_60 */
4208
  {
4209
    { "pushaP", { XX }, 0 },
4210
  },
4211
4212
  /* X86_64_61 */
4213
  {
4214
    { "popaP", { XX }, 0 },
4215
  },
4216
4217
  /* X86_64_62 */
4218
  {
4219
    { MOD_TABLE (MOD_62_32BIT) },
4220
    { EVEX_TABLE () },
4221
  },
4222
4223
  /* X86_64_63 */
4224
  {
4225
    { "arplS", { Sv, Gv }, 0 },
4226
    { "movs", { Gv, { MOVSXD_Fixup, movsxd_mode } }, 0 },
4227
  },
4228
4229
  /* X86_64_6D */
4230
  {
4231
    { "ins{R|}", { Yzr, indirDX }, 0 },
4232
    { "ins{G|}", { Yzr, indirDX }, 0 },
4233
  },
4234
4235
  /* X86_64_6F */
4236
  {
4237
    { "outs{R|}", { indirDXr, Xz }, 0 },
4238
    { "outs{G|}", { indirDXr, Xz }, 0 },
4239
  },
4240
4241
  /* X86_64_82 */
4242
  {
4243
    /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode.  */
4244
    { REG_TABLE (REG_80) },
4245
  },
4246
4247
  /* X86_64_9A */
4248
  {
4249
    { "{l|}call{P|}", { Ap }, 0 },
4250
  },
4251
4252
  /* X86_64_C2 */
4253
  {
4254
    { "retP",   { Iw, BND }, 0 },
4255
    { "ret@",   { Iw, BND }, 0 },
4256
  },
4257
4258
  /* X86_64_C3 */
4259
  {
4260
    { "retP",   { BND }, 0 },
4261
    { "ret@",   { BND }, 0 },
4262
  },
4263
4264
  /* X86_64_C4 */
4265
  {
4266
    { MOD_TABLE (MOD_C4_32BIT) },
4267
    { VEX_C4_TABLE () },
4268
  },
4269
4270
  /* X86_64_C5 */
4271
  {
4272
    { MOD_TABLE (MOD_C5_32BIT) },
4273
    { VEX_C5_TABLE () },
4274
  },
4275
4276
  /* X86_64_CE */
4277
  {
4278
    { "into", { XX }, 0 },
4279
  },
4280
4281
  /* X86_64_D4 */
4282
  {
4283
    { "aam", { Ib }, 0 },
4284
  },
4285
4286
  /* X86_64_D5 */
4287
  {
4288
    { "aad", { Ib }, 0 },
4289
  },
4290
4291
  /* X86_64_E8 */
4292
  {
4293
    { "callP",    { Jv, BND }, 0 },
4294
    { "call@",    { Jv, BND }, PREFIX_REX2_ILLEGAL }
4295
  },
4296
4297
  /* X86_64_E9 */
4298
  {
4299
    { "jmpP",   { Jv, BND }, 0 },
4300
    { "jmp@",   { Jv, BND }, PREFIX_REX2_ILLEGAL }
4301
  },
4302
4303
  /* X86_64_EA */
4304
  {
4305
    { "{l|}jmp{P|}", { Ap }, 0 },
4306
  },
4307
4308
  /* X86_64_0F00_REG_6 */
4309
  {
4310
    { Bad_Opcode },
4311
    { PREFIX_TABLE (PREFIX_0F00_REG_6_X86_64) },
4312
  },
4313
4314
  /* X86_64_0F01_REG_0 */
4315
  {
4316
    { "sgdt{Q|Q}", { M }, 0 },
4317
    { "sgdt", { M }, 0 },
4318
  },
4319
4320
  /* X86_64_0F01_REG_0_MOD_3_RM_6_P_1 */
4321
  {
4322
    { Bad_Opcode },
4323
    { "wrmsrlist",  { Skip_MODRM }, 0 },
4324
  },
4325
4326
  /* X86_64_0F01_REG_0_MOD_3_RM_6_P_3 */
4327
  {
4328
    { Bad_Opcode },
4329
    { "rdmsrlist",  { Skip_MODRM }, 0 },
4330
  },
4331
4332
  /* X86_64_0F01_REG_0_MOD_3_RM_7_P_0 */
4333
  {
4334
    { Bad_Opcode },
4335
    { "pbndkb",   { Skip_MODRM }, 0 },
4336
  },
4337
4338
  /* X86_64_0F01_REG_1 */
4339
  {
4340
    { "sidt{Q|Q}", { M }, 0 },
4341
    { "sidt", { M }, 0 },
4342
  },
4343
4344
  /* X86_64_0F01_REG_1_RM_2_PREFIX_1 */
4345
  {
4346
    { Bad_Opcode },
4347
    { "eretu",    { Skip_MODRM }, 0 },
4348
  },
4349
4350
  /* X86_64_0F01_REG_1_RM_2_PREFIX_3 */
4351
  {
4352
    { Bad_Opcode },
4353
    { "erets",    { Skip_MODRM }, 0 },
4354
  },
4355
4356
  /* X86_64_0F01_REG_1_RM_5_PREFIX_2 */
4357
  {
4358
    { Bad_Opcode },
4359
    { "seamret",  { Skip_MODRM }, 0 },
4360
  },
4361
4362
  /* X86_64_0F01_REG_1_RM_6_PREFIX_2 */
4363
  {
4364
    { Bad_Opcode },
4365
    { "seamops",  { Skip_MODRM }, 0 },
4366
  },
4367
4368
  /* X86_64_0F01_REG_1_RM_7_PREFIX_2 */
4369
  {
4370
    { Bad_Opcode },
4371
    { "seamcall", { Skip_MODRM }, 0 },
4372
  },
4373
4374
  /* X86_64_0F01_REG_2 */
4375
  {
4376
    { "lgdt{Q|Q}", { M }, 0 },
4377
    { "lgdt", { M }, 0 },
4378
  },
4379
4380
  /* X86_64_0F01_REG_3 */
4381
  {
4382
    { "lidt{Q|Q}", { M }, 0 },
4383
    { "lidt", { M }, 0 },
4384
  },
4385
4386
  /* X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1 */
4387
  {
4388
    { Bad_Opcode },
4389
    { "uiret",  { Skip_MODRM }, 0 },
4390
  },
4391
4392
  /* X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1 */
4393
  {
4394
    { Bad_Opcode },
4395
    { "testui", { Skip_MODRM }, 0 },
4396
  },
4397
4398
  /* X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1 */
4399
  {
4400
    { Bad_Opcode },
4401
    { "clui", { Skip_MODRM }, 0 },
4402
  },
4403
4404
  /* X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1 */
4405
  {
4406
    { Bad_Opcode },
4407
    { "stui", { Skip_MODRM }, 0 },
4408
  },
4409
4410
  /* X86_64_0F01_REG_7_MOD_3_RM_5_PREFIX_1 */
4411
  {
4412
    { Bad_Opcode },
4413
    { "rmpquery", { Skip_MODRM }, 0 },
4414
  },
4415
4416
  /* X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1 */
4417
  {
4418
    { Bad_Opcode },
4419
    { "rmpadjust",  { Skip_MODRM }, 0 },
4420
  },
4421
4422
  /* X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3 */
4423
  {
4424
    { Bad_Opcode },
4425
    { "rmpupdate",  { Skip_MODRM }, 0 },
4426
  },
4427
4428
  /* X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1 */
4429
  {
4430
    { Bad_Opcode },
4431
    { "psmash", { Skip_MODRM }, 0 },
4432
  },
4433
4434
  /* X86_64_0F18_REG_6_MOD_0 */
4435
  {
4436
    { "nopQ",   { Ev }, 0 },
4437
    { PREFIX_TABLE (PREFIX_0F18_REG_6_MOD_0_X86_64) },
4438
  },
4439
4440
  /* X86_64_0F18_REG_7_MOD_0 */
4441
  {
4442
    { "nopQ",   { Ev }, 0 },
4443
    { PREFIX_TABLE (PREFIX_0F18_REG_7_MOD_0_X86_64) },
4444
  },
4445
4446
  {
4447
    /* X86_64_0F24 */
4448
    { "movZ",   { Em, Td }, 0 },
4449
  },
4450
4451
  {
4452
    /* X86_64_0F26 */
4453
    { "movZ",   { Td, Em }, 0 },
4454
  },
4455
4456
  {
4457
    /* X86_64_0F38F8_M_1 */
4458
    { Bad_Opcode },
4459
    { PREFIX_TABLE (PREFIX_0F38F8_M_1_X86_64) },
4460
  },
4461
4462
  /* X86_64_0FC7_REG_6_MOD_3_PREFIX_1 */
4463
  {
4464
    { Bad_Opcode },
4465
    { "senduipi", { Eq }, 0 },
4466
  },
4467
4468
  /* X86_64_VEX_0F3849 */
4469
  {
4470
    { Bad_Opcode },
4471
    { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64) },
4472
  },
4473
4474
  /* X86_64_VEX_0F384B */
4475
  {
4476
    { Bad_Opcode },
4477
    { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64) },
4478
  },
4479
4480
  /* X86_64_VEX_0F385C */
4481
  {
4482
    { Bad_Opcode },
4483
    { VEX_LEN_TABLE (VEX_LEN_0F385C_X86_64) },
4484
  },
4485
4486
  /* X86_64_VEX_0F385E */
4487
  {
4488
    { Bad_Opcode },
4489
    { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64) },
4490
  },
4491
4492
  /* X86_64_VEX_0F386C */
4493
  {
4494
    { Bad_Opcode },
4495
    { VEX_LEN_TABLE (VEX_LEN_0F386C_X86_64) },
4496
  },
4497
4498
  /* X86_64_VEX_0F38E0 */
4499
  {
4500
    { Bad_Opcode },
4501
    { "%XEcmpoxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4502
  },
4503
4504
  /* X86_64_VEX_0F38E1 */
4505
  {
4506
    { Bad_Opcode },
4507
    { "%XEcmpnoxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4508
  },
4509
4510
  /* X86_64_VEX_0F38E2 */
4511
  {
4512
    { Bad_Opcode },
4513
    { "%XEcmpbxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4514
  },
4515
4516
  /* X86_64_VEX_0F38E3 */
4517
  {
4518
    { Bad_Opcode },
4519
    { "%XEcmpnbxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4520
  },
4521
4522
  /* X86_64_VEX_0F38E4 */
4523
  {
4524
    { Bad_Opcode },
4525
    { "%XEcmpzxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4526
  },
4527
4528
  /* X86_64_VEX_0F38E5 */
4529
  {
4530
    { Bad_Opcode },
4531
    { "%XEcmpnzxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4532
  },
4533
4534
  /* X86_64_VEX_0F38E6 */
4535
  {
4536
    { Bad_Opcode },
4537
    { "%XEcmpbexadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4538
  },
4539
4540
  /* X86_64_VEX_0F38E7 */
4541
  {
4542
    { Bad_Opcode },
4543
    { "%XEcmpnbexadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4544
  },
4545
4546
  /* X86_64_VEX_0F38E8 */
4547
  {
4548
    { Bad_Opcode },
4549
    { "%XEcmpsxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4550
  },
4551
4552
  /* X86_64_VEX_0F38E9 */
4553
  {
4554
    { Bad_Opcode },
4555
    { "%XEcmpnsxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4556
  },
4557
4558
  /* X86_64_VEX_0F38EA */
4559
  {
4560
    { Bad_Opcode },
4561
    { "%XEcmppxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4562
  },
4563
4564
  /* X86_64_VEX_0F38EB */
4565
  {
4566
    { Bad_Opcode },
4567
    { "%XEcmpnpxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4568
  },
4569
4570
  /* X86_64_VEX_0F38EC */
4571
  {
4572
    { Bad_Opcode },
4573
    { "%XEcmplxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4574
  },
4575
4576
  /* X86_64_VEX_0F38ED */
4577
  {
4578
    { Bad_Opcode },
4579
    { "%XEcmpnlxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4580
  },
4581
4582
  /* X86_64_VEX_0F38EE */
4583
  {
4584
    { Bad_Opcode },
4585
    { "%XEcmplexadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4586
  },
4587
4588
  /* X86_64_VEX_0F38EF */
4589
  {
4590
    { Bad_Opcode },
4591
    { "%XEcmpnlexadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4592
  },
4593
4594
  /* X86_64_VEX_MAP7_F8_L_0_W_0_R_0 */
4595
  {
4596
    { Bad_Opcode },
4597
    { PREFIX_TABLE (PREFIX_VEX_MAP7_F8_L_0_W_0_R_0_X86_64) },
4598
  },
4599
};
4600
4601
static const struct dis386 three_byte_table[][256] = {
4602
4603
  /* THREE_BYTE_0F38 */
4604
  {
4605
    /* 00 */
4606
    { "pshufb",   { MX, EM }, PREFIX_OPCODE },
4607
    { "phaddw",   { MX, EM }, PREFIX_OPCODE },
4608
    { "phaddd",   { MX, EM }, PREFIX_OPCODE },
4609
    { "phaddsw",  { MX, EM }, PREFIX_OPCODE },
4610
    { "pmaddubsw",  { MX, EM }, PREFIX_OPCODE },
4611
    { "phsubw",   { MX, EM }, PREFIX_OPCODE },
4612
    { "phsubd",   { MX, EM }, PREFIX_OPCODE },
4613
    { "phsubsw",  { MX, EM }, PREFIX_OPCODE },
4614
    /* 08 */
4615
    { "psignb",   { MX, EM }, PREFIX_OPCODE },
4616
    { "psignw",   { MX, EM }, PREFIX_OPCODE },
4617
    { "psignd",   { MX, EM }, PREFIX_OPCODE },
4618
    { "pmulhrsw", { MX, EM }, PREFIX_OPCODE },
4619
    { Bad_Opcode },
4620
    { Bad_Opcode },
4621
    { Bad_Opcode },
4622
    { Bad_Opcode },
4623
    /* 10 */
4624
    { "pblendvb", { XM, EXx, XMM0 }, PREFIX_DATA },
4625
    { Bad_Opcode },
4626
    { Bad_Opcode },
4627
    { Bad_Opcode },
4628
    { "blendvps", { XM, EXx, XMM0 }, PREFIX_DATA },
4629
    { "blendvpd", { XM, EXx, XMM0 }, PREFIX_DATA },
4630
    { Bad_Opcode },
4631
    { "ptest",  { XM, EXx }, PREFIX_DATA },
4632
    /* 18 */
4633
    { Bad_Opcode },
4634
    { Bad_Opcode },
4635
    { Bad_Opcode },
4636
    { Bad_Opcode },
4637
    { "pabsb",    { MX, EM }, PREFIX_OPCODE },
4638
    { "pabsw",    { MX, EM }, PREFIX_OPCODE },
4639
    { "pabsd",    { MX, EM }, PREFIX_OPCODE },
4640
    { Bad_Opcode },
4641
    /* 20 */
4642
    { "pmovsxbw", { XM, EXq }, PREFIX_DATA },
4643
    { "pmovsxbd", { XM, EXd }, PREFIX_DATA },
4644
    { "pmovsxbq", { XM, EXw }, PREFIX_DATA },
4645
    { "pmovsxwd", { XM, EXq }, PREFIX_DATA },
4646
    { "pmovsxwq", { XM, EXd }, PREFIX_DATA },
4647
    { "pmovsxdq", { XM, EXq }, PREFIX_DATA },
4648
    { Bad_Opcode },
4649
    { Bad_Opcode },
4650
    /* 28 */
4651
    { "pmuldq", { XM, EXx }, PREFIX_DATA },
4652
    { "pcmpeqq", { XM, EXx }, PREFIX_DATA },
4653
    { "movntdqa", { XM, Mx }, PREFIX_DATA },
4654
    { "packusdw", { XM, EXx }, PREFIX_DATA },
4655
    { Bad_Opcode },
4656
    { Bad_Opcode },
4657
    { Bad_Opcode },
4658
    { Bad_Opcode },
4659
    /* 30 */
4660
    { "pmovzxbw", { XM, EXq }, PREFIX_DATA },
4661
    { "pmovzxbd", { XM, EXd }, PREFIX_DATA },
4662
    { "pmovzxbq", { XM, EXw }, PREFIX_DATA },
4663
    { "pmovzxwd", { XM, EXq }, PREFIX_DATA },
4664
    { "pmovzxwq", { XM, EXd }, PREFIX_DATA },
4665
    { "pmovzxdq", { XM, EXq }, PREFIX_DATA },
4666
    { Bad_Opcode },
4667
    { "pcmpgtq", { XM, EXx }, PREFIX_DATA },
4668
    /* 38 */
4669
    { "pminsb", { XM, EXx }, PREFIX_DATA },
4670
    { "pminsd", { XM, EXx }, PREFIX_DATA },
4671
    { "pminuw", { XM, EXx }, PREFIX_DATA },
4672
    { "pminud", { XM, EXx }, PREFIX_DATA },
4673
    { "pmaxsb", { XM, EXx }, PREFIX_DATA },
4674
    { "pmaxsd", { XM, EXx }, PREFIX_DATA },
4675
    { "pmaxuw", { XM, EXx }, PREFIX_DATA },
4676
    { "pmaxud", { XM, EXx }, PREFIX_DATA },
4677
    /* 40 */
4678
    { "pmulld", { XM, EXx }, PREFIX_DATA },
4679
    { "phminposuw", { XM, EXx }, PREFIX_DATA },
4680
    { Bad_Opcode },
4681
    { Bad_Opcode },
4682
    { Bad_Opcode },
4683
    { Bad_Opcode },
4684
    { Bad_Opcode },
4685
    { Bad_Opcode },
4686
    /* 48 */
4687
    { Bad_Opcode },
4688
    { Bad_Opcode },
4689
    { Bad_Opcode },
4690
    { Bad_Opcode },
4691
    { Bad_Opcode },
4692
    { Bad_Opcode },
4693
    { Bad_Opcode },
4694
    { Bad_Opcode },
4695
    /* 50 */
4696
    { Bad_Opcode },
4697
    { Bad_Opcode },
4698
    { Bad_Opcode },
4699
    { Bad_Opcode },
4700
    { Bad_Opcode },
4701
    { Bad_Opcode },
4702
    { Bad_Opcode },
4703
    { Bad_Opcode },
4704
    /* 58 */
4705
    { Bad_Opcode },
4706
    { Bad_Opcode },
4707
    { Bad_Opcode },
4708
    { Bad_Opcode },
4709
    { Bad_Opcode },
4710
    { Bad_Opcode },
4711
    { Bad_Opcode },
4712
    { Bad_Opcode },
4713
    /* 60 */
4714
    { Bad_Opcode },
4715
    { Bad_Opcode },
4716
    { Bad_Opcode },
4717
    { Bad_Opcode },
4718
    { Bad_Opcode },
4719
    { Bad_Opcode },
4720
    { Bad_Opcode },
4721
    { Bad_Opcode },
4722
    /* 68 */
4723
    { Bad_Opcode },
4724
    { Bad_Opcode },
4725
    { Bad_Opcode },
4726
    { Bad_Opcode },
4727
    { Bad_Opcode },
4728
    { Bad_Opcode },
4729
    { Bad_Opcode },
4730
    { Bad_Opcode },
4731
    /* 70 */
4732
    { Bad_Opcode },
4733
    { Bad_Opcode },
4734
    { Bad_Opcode },
4735
    { Bad_Opcode },
4736
    { Bad_Opcode },
4737
    { Bad_Opcode },
4738
    { Bad_Opcode },
4739
    { Bad_Opcode },
4740
    /* 78 */
4741
    { Bad_Opcode },
4742
    { Bad_Opcode },
4743
    { Bad_Opcode },
4744
    { Bad_Opcode },
4745
    { Bad_Opcode },
4746
    { Bad_Opcode },
4747
    { Bad_Opcode },
4748
    { Bad_Opcode },
4749
    /* 80 */
4750
    { "invept", { Gm, Mo }, PREFIX_DATA },
4751
    { "invvpid", { Gm, Mo }, PREFIX_DATA },
4752
    { "invpcid", { Gm, M }, PREFIX_DATA },
4753
    { Bad_Opcode },
4754
    { Bad_Opcode },
4755
    { Bad_Opcode },
4756
    { Bad_Opcode },
4757
    { Bad_Opcode },
4758
    /* 88 */
4759
    { Bad_Opcode },
4760
    { Bad_Opcode },
4761
    { Bad_Opcode },
4762
    { Bad_Opcode },
4763
    { Bad_Opcode },
4764
    { Bad_Opcode },
4765
    { Bad_Opcode },
4766
    { Bad_Opcode },
4767
    /* 90 */
4768
    { Bad_Opcode },
4769
    { Bad_Opcode },
4770
    { Bad_Opcode },
4771
    { Bad_Opcode },
4772
    { Bad_Opcode },
4773
    { Bad_Opcode },
4774
    { Bad_Opcode },
4775
    { Bad_Opcode },
4776
    /* 98 */
4777
    { Bad_Opcode },
4778
    { Bad_Opcode },
4779
    { Bad_Opcode },
4780
    { Bad_Opcode },
4781
    { Bad_Opcode },
4782
    { Bad_Opcode },
4783
    { Bad_Opcode },
4784
    { Bad_Opcode },
4785
    /* a0 */
4786
    { Bad_Opcode },
4787
    { Bad_Opcode },
4788
    { Bad_Opcode },
4789
    { Bad_Opcode },
4790
    { Bad_Opcode },
4791
    { Bad_Opcode },
4792
    { Bad_Opcode },
4793
    { Bad_Opcode },
4794
    /* a8 */
4795
    { Bad_Opcode },
4796
    { Bad_Opcode },
4797
    { Bad_Opcode },
4798
    { Bad_Opcode },
4799
    { Bad_Opcode },
4800
    { Bad_Opcode },
4801
    { Bad_Opcode },
4802
    { Bad_Opcode },
4803
    /* b0 */
4804
    { Bad_Opcode },
4805
    { Bad_Opcode },
4806
    { Bad_Opcode },
4807
    { Bad_Opcode },
4808
    { Bad_Opcode },
4809
    { Bad_Opcode },
4810
    { Bad_Opcode },
4811
    { Bad_Opcode },
4812
    /* b8 */
4813
    { Bad_Opcode },
4814
    { Bad_Opcode },
4815
    { Bad_Opcode },
4816
    { Bad_Opcode },
4817
    { Bad_Opcode },
4818
    { Bad_Opcode },
4819
    { Bad_Opcode },
4820
    { Bad_Opcode },
4821
    /* c0 */
4822
    { Bad_Opcode },
4823
    { Bad_Opcode },
4824
    { Bad_Opcode },
4825
    { Bad_Opcode },
4826
    { Bad_Opcode },
4827
    { Bad_Opcode },
4828
    { Bad_Opcode },
4829
    { Bad_Opcode },
4830
    /* c8 */
4831
    { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4832
    { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4833
    { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4834
    { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4835
    { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4836
    { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4837
    { Bad_Opcode },
4838
    { "gf2p8mulb", { XM, EXxmm }, PREFIX_DATA },
4839
    /* d0 */
4840
    { Bad_Opcode },
4841
    { Bad_Opcode },
4842
    { Bad_Opcode },
4843
    { Bad_Opcode },
4844
    { Bad_Opcode },
4845
    { Bad_Opcode },
4846
    { Bad_Opcode },
4847
    { Bad_Opcode },
4848
    /* d8 */
4849
    { PREFIX_TABLE (PREFIX_0F38D8) },
4850
    { Bad_Opcode },
4851
    { Bad_Opcode },
4852
    { "aesimc", { XM, EXx }, PREFIX_DATA },
4853
    { PREFIX_TABLE (PREFIX_0F38DC) },
4854
    { PREFIX_TABLE (PREFIX_0F38DD) },
4855
    { PREFIX_TABLE (PREFIX_0F38DE) },
4856
    { PREFIX_TABLE (PREFIX_0F38DF) },
4857
    /* e0 */
4858
    { Bad_Opcode },
4859
    { Bad_Opcode },
4860
    { Bad_Opcode },
4861
    { Bad_Opcode },
4862
    { Bad_Opcode },
4863
    { Bad_Opcode },
4864
    { Bad_Opcode },
4865
    { Bad_Opcode },
4866
    /* e8 */
4867
    { Bad_Opcode },
4868
    { Bad_Opcode },
4869
    { Bad_Opcode },
4870
    { Bad_Opcode },
4871
    { Bad_Opcode },
4872
    { Bad_Opcode },
4873
    { Bad_Opcode },
4874
    { Bad_Opcode },
4875
    /* f0 */
4876
    { PREFIX_TABLE (PREFIX_0F38F0) },
4877
    { PREFIX_TABLE (PREFIX_0F38F1) },
4878
    { Bad_Opcode },
4879
    { Bad_Opcode },
4880
    { Bad_Opcode },
4881
    { "wrussK",   { M, Gdq }, PREFIX_DATA },
4882
    { PREFIX_TABLE (PREFIX_0F38F6) },
4883
    { Bad_Opcode },
4884
    /* f8 */
4885
    { MOD_TABLE (MOD_0F38F8) },
4886
    { "movdiri",  { Mdq, Gdq }, PREFIX_OPCODE },
4887
    { PREFIX_TABLE (PREFIX_0F38FA) },
4888
    { PREFIX_TABLE (PREFIX_0F38FB) },
4889
    { PREFIX_TABLE (PREFIX_0F38FC) },
4890
    { Bad_Opcode },
4891
    { Bad_Opcode },
4892
    { Bad_Opcode },
4893
  },
4894
  /* THREE_BYTE_0F3A */
4895
  {
4896
    /* 00 */
4897
    { Bad_Opcode },
4898
    { Bad_Opcode },
4899
    { Bad_Opcode },
4900
    { Bad_Opcode },
4901
    { Bad_Opcode },
4902
    { Bad_Opcode },
4903
    { Bad_Opcode },
4904
    { Bad_Opcode },
4905
    /* 08 */
4906
    { "roundps", { XM, EXx, Ib }, PREFIX_DATA },
4907
    { "roundpd", { XM, EXx, Ib }, PREFIX_DATA },
4908
    { "roundss", { XM, EXd, Ib }, PREFIX_DATA },
4909
    { "roundsd", { XM, EXq, Ib }, PREFIX_DATA },
4910
    { "blendps", { XM, EXx, Ib }, PREFIX_DATA },
4911
    { "blendpd", { XM, EXx, Ib }, PREFIX_DATA },
4912
    { "pblendw", { XM, EXx, Ib }, PREFIX_DATA },
4913
    { "palignr",  { MX, EM, Ib }, PREFIX_OPCODE },
4914
    /* 10 */
4915
    { Bad_Opcode },
4916
    { Bad_Opcode },
4917
    { Bad_Opcode },
4918
    { Bad_Opcode },
4919
    { "pextrb", { Edb, XM, Ib }, PREFIX_DATA },
4920
    { "pextrw", { Edw, XM, Ib }, PREFIX_DATA },
4921
    { "pextrK", { Edq, XM, Ib }, PREFIX_DATA },
4922
    { "extractps", { Ed, XM, Ib }, PREFIX_DATA },
4923
    /* 18 */
4924
    { Bad_Opcode },
4925
    { Bad_Opcode },
4926
    { Bad_Opcode },
4927
    { Bad_Opcode },
4928
    { Bad_Opcode },
4929
    { Bad_Opcode },
4930
    { Bad_Opcode },
4931
    { Bad_Opcode },
4932
    /* 20 */
4933
    { "pinsrb", { XM, Edb, Ib }, PREFIX_DATA },
4934
    { "insertps", { XM, EXd, Ib }, PREFIX_DATA },
4935
    { "pinsrK", { XM, Edq, Ib }, PREFIX_DATA },
4936
    { Bad_Opcode },
4937
    { Bad_Opcode },
4938
    { Bad_Opcode },
4939
    { Bad_Opcode },
4940
    { Bad_Opcode },
4941
    /* 28 */
4942
    { Bad_Opcode },
4943
    { Bad_Opcode },
4944
    { Bad_Opcode },
4945
    { Bad_Opcode },
4946
    { Bad_Opcode },
4947
    { Bad_Opcode },
4948
    { Bad_Opcode },
4949
    { Bad_Opcode },
4950
    /* 30 */
4951
    { Bad_Opcode },
4952
    { Bad_Opcode },
4953
    { Bad_Opcode },
4954
    { Bad_Opcode },
4955
    { Bad_Opcode },
4956
    { Bad_Opcode },
4957
    { Bad_Opcode },
4958
    { Bad_Opcode },
4959
    /* 38 */
4960
    { Bad_Opcode },
4961
    { Bad_Opcode },
4962
    { Bad_Opcode },
4963
    { Bad_Opcode },
4964
    { Bad_Opcode },
4965
    { Bad_Opcode },
4966
    { Bad_Opcode },
4967
    { Bad_Opcode },
4968
    /* 40 */
4969
    { "dpps", { XM, EXx, Ib }, PREFIX_DATA },
4970
    { "dppd", { XM, EXx, Ib }, PREFIX_DATA },
4971
    { "mpsadbw", { XM, EXx, Ib }, PREFIX_DATA },
4972
    { Bad_Opcode },
4973
    { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_DATA },
4974
    { Bad_Opcode },
4975
    { Bad_Opcode },
4976
    { Bad_Opcode },
4977
    /* 48 */
4978
    { Bad_Opcode },
4979
    { Bad_Opcode },
4980
    { Bad_Opcode },
4981
    { Bad_Opcode },
4982
    { Bad_Opcode },
4983
    { Bad_Opcode },
4984
    { Bad_Opcode },
4985
    { Bad_Opcode },
4986
    /* 50 */
4987
    { Bad_Opcode },
4988
    { Bad_Opcode },
4989
    { Bad_Opcode },
4990
    { Bad_Opcode },
4991
    { Bad_Opcode },
4992
    { Bad_Opcode },
4993
    { Bad_Opcode },
4994
    { Bad_Opcode },
4995
    /* 58 */
4996
    { Bad_Opcode },
4997
    { Bad_Opcode },
4998
    { Bad_Opcode },
4999
    { Bad_Opcode },
5000
    { Bad_Opcode },
5001
    { Bad_Opcode },
5002
    { Bad_Opcode },
5003
    { Bad_Opcode },
5004
    /* 60 */
5005
    { "pcmpestrm!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
5006
    { "pcmpestri!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
5007
    { "pcmpistrm", { XM, EXx, Ib }, PREFIX_DATA },
5008
    { "pcmpistri", { XM, EXx, Ib }, PREFIX_DATA },
5009
    { Bad_Opcode },
5010
    { Bad_Opcode },
5011
    { Bad_Opcode },
5012
    { Bad_Opcode },
5013
    /* 68 */
5014
    { Bad_Opcode },
5015
    { Bad_Opcode },
5016
    { Bad_Opcode },
5017
    { Bad_Opcode },
5018
    { Bad_Opcode },
5019
    { Bad_Opcode },
5020
    { Bad_Opcode },
5021
    { Bad_Opcode },
5022
    /* 70 */
5023
    { Bad_Opcode },
5024
    { Bad_Opcode },
5025
    { Bad_Opcode },
5026
    { Bad_Opcode },
5027
    { Bad_Opcode },
5028
    { Bad_Opcode },
5029
    { Bad_Opcode },
5030
    { Bad_Opcode },
5031
    /* 78 */
5032
    { Bad_Opcode },
5033
    { Bad_Opcode },
5034
    { Bad_Opcode },
5035
    { Bad_Opcode },
5036
    { Bad_Opcode },
5037
    { Bad_Opcode },
5038
    { Bad_Opcode },
5039
    { Bad_Opcode },
5040
    /* 80 */
5041
    { Bad_Opcode },
5042
    { Bad_Opcode },
5043
    { Bad_Opcode },
5044
    { Bad_Opcode },
5045
    { Bad_Opcode },
5046
    { Bad_Opcode },
5047
    { Bad_Opcode },
5048
    { Bad_Opcode },
5049
    /* 88 */
5050
    { Bad_Opcode },
5051
    { Bad_Opcode },
5052
    { Bad_Opcode },
5053
    { Bad_Opcode },
5054
    { Bad_Opcode },
5055
    { Bad_Opcode },
5056
    { Bad_Opcode },
5057
    { Bad_Opcode },
5058
    /* 90 */
5059
    { Bad_Opcode },
5060
    { Bad_Opcode },
5061
    { Bad_Opcode },
5062
    { Bad_Opcode },
5063
    { Bad_Opcode },
5064
    { Bad_Opcode },
5065
    { Bad_Opcode },
5066
    { Bad_Opcode },
5067
    /* 98 */
5068
    { Bad_Opcode },
5069
    { Bad_Opcode },
5070
    { Bad_Opcode },
5071
    { Bad_Opcode },
5072
    { Bad_Opcode },
5073
    { Bad_Opcode },
5074
    { Bad_Opcode },
5075
    { Bad_Opcode },
5076
    /* a0 */
5077
    { Bad_Opcode },
5078
    { Bad_Opcode },
5079
    { Bad_Opcode },
5080
    { Bad_Opcode },
5081
    { Bad_Opcode },
5082
    { Bad_Opcode },
5083
    { Bad_Opcode },
5084
    { Bad_Opcode },
5085
    /* a8 */
5086
    { Bad_Opcode },
5087
    { Bad_Opcode },
5088
    { Bad_Opcode },
5089
    { Bad_Opcode },
5090
    { Bad_Opcode },
5091
    { Bad_Opcode },
5092
    { Bad_Opcode },
5093
    { Bad_Opcode },
5094
    /* b0 */
5095
    { Bad_Opcode },
5096
    { Bad_Opcode },
5097
    { Bad_Opcode },
5098
    { Bad_Opcode },
5099
    { Bad_Opcode },
5100
    { Bad_Opcode },
5101
    { Bad_Opcode },
5102
    { Bad_Opcode },
5103
    /* b8 */
5104
    { Bad_Opcode },
5105
    { Bad_Opcode },
5106
    { Bad_Opcode },
5107
    { Bad_Opcode },
5108
    { Bad_Opcode },
5109
    { Bad_Opcode },
5110
    { Bad_Opcode },
5111
    { Bad_Opcode },
5112
    /* c0 */
5113
    { Bad_Opcode },
5114
    { Bad_Opcode },
5115
    { Bad_Opcode },
5116
    { Bad_Opcode },
5117
    { Bad_Opcode },
5118
    { Bad_Opcode },
5119
    { Bad_Opcode },
5120
    { Bad_Opcode },
5121
    /* c8 */
5122
    { Bad_Opcode },
5123
    { Bad_Opcode },
5124
    { Bad_Opcode },
5125
    { Bad_Opcode },
5126
    { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
5127
    { Bad_Opcode },
5128
    { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_DATA },
5129
    { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_DATA },
5130
    /* d0 */
5131
    { Bad_Opcode },
5132
    { Bad_Opcode },
5133
    { Bad_Opcode },
5134
    { Bad_Opcode },
5135
    { Bad_Opcode },
5136
    { Bad_Opcode },
5137
    { Bad_Opcode },
5138
    { Bad_Opcode },
5139
    /* d8 */
5140
    { Bad_Opcode },
5141
    { Bad_Opcode },
5142
    { Bad_Opcode },
5143
    { Bad_Opcode },
5144
    { Bad_Opcode },
5145
    { Bad_Opcode },
5146
    { Bad_Opcode },
5147
    { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_DATA },
5148
    /* e0 */
5149
    { Bad_Opcode },
5150
    { Bad_Opcode },
5151
    { Bad_Opcode },
5152
    { Bad_Opcode },
5153
    { Bad_Opcode },
5154
    { Bad_Opcode },
5155
    { Bad_Opcode },
5156
    { Bad_Opcode },
5157
    /* e8 */
5158
    { Bad_Opcode },
5159
    { Bad_Opcode },
5160
    { Bad_Opcode },
5161
    { Bad_Opcode },
5162
    { Bad_Opcode },
5163
    { Bad_Opcode },
5164
    { Bad_Opcode },
5165
    { Bad_Opcode },
5166
    /* f0 */
5167
    { PREFIX_TABLE (PREFIX_0F3A0F) },
5168
    { Bad_Opcode },
5169
    { Bad_Opcode },
5170
    { Bad_Opcode },
5171
    { Bad_Opcode },
5172
    { Bad_Opcode },
5173
    { Bad_Opcode },
5174
    { Bad_Opcode },
5175
    /* f8 */
5176
    { Bad_Opcode },
5177
    { Bad_Opcode },
5178
    { Bad_Opcode },
5179
    { Bad_Opcode },
5180
    { Bad_Opcode },
5181
    { Bad_Opcode },
5182
    { Bad_Opcode },
5183
    { Bad_Opcode },
5184
  },
5185
};
5186
5187
static const struct dis386 xop_table[][256] = {
5188
  /* XOP_08 */
5189
  {
5190
    /* 00 */
5191
    { Bad_Opcode },
5192
    { Bad_Opcode },
5193
    { Bad_Opcode },
5194
    { Bad_Opcode },
5195
    { Bad_Opcode },
5196
    { Bad_Opcode },
5197
    { Bad_Opcode },
5198
    { Bad_Opcode },
5199
    /* 08 */
5200
    { Bad_Opcode },
5201
    { Bad_Opcode },
5202
    { Bad_Opcode },
5203
    { Bad_Opcode },
5204
    { Bad_Opcode },
5205
    { Bad_Opcode },
5206
    { Bad_Opcode },
5207
    { Bad_Opcode },
5208
    /* 10 */
5209
    { Bad_Opcode },
5210
    { Bad_Opcode },
5211
    { Bad_Opcode },
5212
    { Bad_Opcode },
5213
    { Bad_Opcode },
5214
    { Bad_Opcode },
5215
    { Bad_Opcode },
5216
    { Bad_Opcode },
5217
    /* 18 */
5218
    { Bad_Opcode },
5219
    { Bad_Opcode },
5220
    { Bad_Opcode },
5221
    { Bad_Opcode },
5222
    { Bad_Opcode },
5223
    { Bad_Opcode },
5224
    { Bad_Opcode },
5225
    { Bad_Opcode },
5226
    /* 20 */
5227
    { Bad_Opcode },
5228
    { Bad_Opcode },
5229
    { Bad_Opcode },
5230
    { Bad_Opcode },
5231
    { Bad_Opcode },
5232
    { Bad_Opcode },
5233
    { Bad_Opcode },
5234
    { Bad_Opcode },
5235
    /* 28 */
5236
    { Bad_Opcode },
5237
    { Bad_Opcode },
5238
    { Bad_Opcode },
5239
    { Bad_Opcode },
5240
    { Bad_Opcode },
5241
    { Bad_Opcode },
5242
    { Bad_Opcode },
5243
    { Bad_Opcode },
5244
    /* 30 */
5245
    { Bad_Opcode },
5246
    { Bad_Opcode },
5247
    { Bad_Opcode },
5248
    { Bad_Opcode },
5249
    { Bad_Opcode },
5250
    { Bad_Opcode },
5251
    { Bad_Opcode },
5252
    { Bad_Opcode },
5253
    /* 38 */
5254
    { Bad_Opcode },
5255
    { Bad_Opcode },
5256
    { Bad_Opcode },
5257
    { Bad_Opcode },
5258
    { Bad_Opcode },
5259
    { Bad_Opcode },
5260
    { Bad_Opcode },
5261
    { Bad_Opcode },
5262
    /* 40 */
5263
    { Bad_Opcode },
5264
    { Bad_Opcode },
5265
    { Bad_Opcode },
5266
    { Bad_Opcode },
5267
    { Bad_Opcode },
5268
    { Bad_Opcode },
5269
    { Bad_Opcode },
5270
    { Bad_Opcode },
5271
    /* 48 */
5272
    { Bad_Opcode },
5273
    { Bad_Opcode },
5274
    { Bad_Opcode },
5275
    { Bad_Opcode },
5276
    { Bad_Opcode },
5277
    { Bad_Opcode },
5278
    { Bad_Opcode },
5279
    { Bad_Opcode },
5280
    /* 50 */
5281
    { Bad_Opcode },
5282
    { Bad_Opcode },
5283
    { Bad_Opcode },
5284
    { Bad_Opcode },
5285
    { Bad_Opcode },
5286
    { Bad_Opcode },
5287
    { Bad_Opcode },
5288
    { Bad_Opcode },
5289
    /* 58 */
5290
    { Bad_Opcode },
5291
    { Bad_Opcode },
5292
    { Bad_Opcode },
5293
    { Bad_Opcode },
5294
    { Bad_Opcode },
5295
    { Bad_Opcode },
5296
    { Bad_Opcode },
5297
    { Bad_Opcode },
5298
    /* 60 */
5299
    { Bad_Opcode },
5300
    { Bad_Opcode },
5301
    { Bad_Opcode },
5302
    { Bad_Opcode },
5303
    { Bad_Opcode },
5304
    { Bad_Opcode },
5305
    { Bad_Opcode },
5306
    { Bad_Opcode },
5307
    /* 68 */
5308
    { Bad_Opcode },
5309
    { Bad_Opcode },
5310
    { Bad_Opcode },
5311
    { Bad_Opcode },
5312
    { Bad_Opcode },
5313
    { Bad_Opcode },
5314
    { Bad_Opcode },
5315
    { Bad_Opcode },
5316
    /* 70 */
5317
    { Bad_Opcode },
5318
    { Bad_Opcode },
5319
    { Bad_Opcode },
5320
    { Bad_Opcode },
5321
    { Bad_Opcode },
5322
    { Bad_Opcode },
5323
    { Bad_Opcode },
5324
    { Bad_Opcode },
5325
    /* 78 */
5326
    { Bad_Opcode },
5327
    { Bad_Opcode },
5328
    { Bad_Opcode },
5329
    { Bad_Opcode },
5330
    { Bad_Opcode },
5331
    { Bad_Opcode },
5332
    { Bad_Opcode },
5333
    { Bad_Opcode },
5334
    /* 80 */
5335
    { Bad_Opcode },
5336
    { Bad_Opcode },
5337
    { Bad_Opcode },
5338
    { Bad_Opcode },
5339
    { Bad_Opcode },
5340
    { VEX_LEN_TABLE (VEX_LEN_XOP_08_85) },
5341
    { VEX_LEN_TABLE (VEX_LEN_XOP_08_86) },
5342
    { VEX_LEN_TABLE (VEX_LEN_XOP_08_87) },
5343
    /* 88 */
5344
    { Bad_Opcode },
5345
    { Bad_Opcode },
5346
    { Bad_Opcode },
5347
    { Bad_Opcode },
5348
    { Bad_Opcode },
5349
    { Bad_Opcode },
5350
    { VEX_LEN_TABLE (VEX_LEN_XOP_08_8E) },
5351
    { VEX_LEN_TABLE (VEX_LEN_XOP_08_8F) },
5352
    /* 90 */
5353
    { Bad_Opcode },
5354
    { Bad_Opcode },
5355
    { Bad_Opcode },
5356
    { Bad_Opcode },
5357
    { Bad_Opcode },
5358
    { VEX_LEN_TABLE (VEX_LEN_XOP_08_95) },
5359
    { VEX_LEN_TABLE (VEX_LEN_XOP_08_96) },
5360
    { VEX_LEN_TABLE (VEX_LEN_XOP_08_97) },
5361
    /* 98 */
5362
    { Bad_Opcode },
5363
    { Bad_Opcode },
5364
    { Bad_Opcode },
5365
    { Bad_Opcode },
5366
    { Bad_Opcode },
5367
    { Bad_Opcode },
5368
    { VEX_LEN_TABLE (VEX_LEN_XOP_08_9E) },
5369
    { VEX_LEN_TABLE (VEX_LEN_XOP_08_9F) },
5370
    /* a0 */
5371
    { Bad_Opcode },
5372
    { Bad_Opcode },
5373
    { "vpcmov",   { XM, Vex, EXx, XMVexI4 }, 0 },
5374
    { VEX_LEN_TABLE (VEX_LEN_XOP_08_A3) },
5375
    { Bad_Opcode },
5376
    { Bad_Opcode },
5377
    { VEX_LEN_TABLE (VEX_LEN_XOP_08_A6) },
5378
    { Bad_Opcode },
5379
    /* a8 */
5380
    { Bad_Opcode },
5381
    { Bad_Opcode },
5382
    { Bad_Opcode },
5383
    { Bad_Opcode },
5384
    { Bad_Opcode },
5385
    { Bad_Opcode },
5386
    { Bad_Opcode },
5387
    { Bad_Opcode },
5388
    /* b0 */
5389
    { Bad_Opcode },
5390
    { Bad_Opcode },
5391
    { Bad_Opcode },
5392
    { Bad_Opcode },
5393
    { Bad_Opcode },
5394
    { Bad_Opcode },
5395
    { VEX_LEN_TABLE (VEX_LEN_XOP_08_B6) },
5396
    { Bad_Opcode },
5397
    /* b8 */
5398
    { Bad_Opcode },
5399
    { Bad_Opcode },
5400
    { Bad_Opcode },
5401
    { Bad_Opcode },
5402
    { Bad_Opcode },
5403
    { Bad_Opcode },
5404
    { Bad_Opcode },
5405
    { Bad_Opcode },
5406
    /* c0 */
5407
    { VEX_LEN_TABLE (VEX_LEN_XOP_08_C0) },
5408
    { VEX_LEN_TABLE (VEX_LEN_XOP_08_C1) },
5409
    { VEX_LEN_TABLE (VEX_LEN_XOP_08_C2) },
5410
    { VEX_LEN_TABLE (VEX_LEN_XOP_08_C3) },
5411
    { Bad_Opcode },
5412
    { Bad_Opcode },
5413
    { Bad_Opcode },
5414
    { Bad_Opcode },
5415
    /* c8 */
5416
    { Bad_Opcode },
5417
    { Bad_Opcode },
5418
    { Bad_Opcode },
5419
    { Bad_Opcode },
5420
    { VEX_LEN_TABLE (VEX_LEN_XOP_08_CC) },
5421
    { VEX_LEN_TABLE (VEX_LEN_XOP_08_CD) },
5422
    { VEX_LEN_TABLE (VEX_LEN_XOP_08_CE) },
5423
    { VEX_LEN_TABLE (VEX_LEN_XOP_08_CF) },
5424
    /* d0 */
5425
    { Bad_Opcode },
5426
    { Bad_Opcode },
5427
    { Bad_Opcode },
5428
    { Bad_Opcode },
5429
    { Bad_Opcode },
5430
    { Bad_Opcode },
5431
    { Bad_Opcode },
5432
    { Bad_Opcode },
5433
    /* d8 */
5434
    { Bad_Opcode },
5435
    { Bad_Opcode },
5436
    { Bad_Opcode },
5437
    { Bad_Opcode },
5438
    { Bad_Opcode },
5439
    { Bad_Opcode },
5440
    { Bad_Opcode },
5441
    { Bad_Opcode },
5442
    /* e0 */
5443
    { Bad_Opcode },
5444
    { Bad_Opcode },
5445
    { Bad_Opcode },
5446
    { Bad_Opcode },
5447
    { Bad_Opcode },
5448
    { Bad_Opcode },
5449
    { Bad_Opcode },
5450
    { Bad_Opcode },
5451
    /* e8 */
5452
    { Bad_Opcode },
5453
    { Bad_Opcode },
5454
    { Bad_Opcode },
5455
    { Bad_Opcode },
5456
    { VEX_LEN_TABLE (VEX_LEN_XOP_08_EC) },
5457
    { VEX_LEN_TABLE (VEX_LEN_XOP_08_ED) },
5458
    { VEX_LEN_TABLE (VEX_LEN_XOP_08_EE) },
5459
    { VEX_LEN_TABLE (VEX_LEN_XOP_08_EF) },
5460
    /* f0 */
5461
    { Bad_Opcode },
5462
    { Bad_Opcode },
5463
    { Bad_Opcode },
5464
    { Bad_Opcode },
5465
    { Bad_Opcode },
5466
    { Bad_Opcode },
5467
    { Bad_Opcode },
5468
    { Bad_Opcode },
5469
    /* f8 */
5470
    { Bad_Opcode },
5471
    { Bad_Opcode },
5472
    { Bad_Opcode },
5473
    { Bad_Opcode },
5474
    { Bad_Opcode },
5475
    { Bad_Opcode },
5476
    { Bad_Opcode },
5477
    { Bad_Opcode },
5478
  },
5479
  /* XOP_09 */
5480
  {
5481
    /* 00 */
5482
    { Bad_Opcode },
5483
    { VEX_LEN_TABLE (VEX_LEN_XOP_09_01) },
5484
    { VEX_LEN_TABLE (VEX_LEN_XOP_09_02) },
5485
    { Bad_Opcode },
5486
    { Bad_Opcode },
5487
    { Bad_Opcode },
5488
    { Bad_Opcode },
5489
    { Bad_Opcode },
5490
    /* 08 */
5491
    { Bad_Opcode },
5492
    { Bad_Opcode },
5493
    { Bad_Opcode },
5494
    { Bad_Opcode },
5495
    { Bad_Opcode },
5496
    { Bad_Opcode },
5497
    { Bad_Opcode },
5498
    { Bad_Opcode },
5499
    /* 10 */
5500
    { Bad_Opcode },
5501
    { Bad_Opcode },
5502
    { VEX_LEN_TABLE (VEX_LEN_XOP_09_12) },
5503
    { Bad_Opcode },
5504
    { Bad_Opcode },
5505
    { Bad_Opcode },
5506
    { Bad_Opcode },
5507
    { Bad_Opcode },
5508
    /* 18 */
5509
    { Bad_Opcode },
5510
    { Bad_Opcode },
5511
    { Bad_Opcode },
5512
    { Bad_Opcode },
5513
    { Bad_Opcode },
5514
    { Bad_Opcode },
5515
    { Bad_Opcode },
5516
    { Bad_Opcode },
5517
    /* 20 */
5518
    { Bad_Opcode },
5519
    { Bad_Opcode },
5520
    { Bad_Opcode },
5521
    { Bad_Opcode },
5522
    { Bad_Opcode },
5523
    { Bad_Opcode },
5524
    { Bad_Opcode },
5525
    { Bad_Opcode },
5526
    /* 28 */
5527
    { Bad_Opcode },
5528
    { Bad_Opcode },
5529
    { Bad_Opcode },
5530
    { Bad_Opcode },
5531
    { Bad_Opcode },
5532
    { Bad_Opcode },
5533
    { Bad_Opcode },
5534
    { Bad_Opcode },
5535
    /* 30 */
5536
    { Bad_Opcode },
5537
    { Bad_Opcode },
5538
    { Bad_Opcode },
5539
    { Bad_Opcode },
5540
    { Bad_Opcode },
5541
    { Bad_Opcode },
5542
    { Bad_Opcode },
5543
    { Bad_Opcode },
5544
    /* 38 */
5545
    { Bad_Opcode },
5546
    { Bad_Opcode },
5547
    { Bad_Opcode },
5548
    { Bad_Opcode },
5549
    { Bad_Opcode },
5550
    { Bad_Opcode },
5551
    { Bad_Opcode },
5552
    { Bad_Opcode },
5553
    /* 40 */
5554
    { Bad_Opcode },
5555
    { Bad_Opcode },
5556
    { Bad_Opcode },
5557
    { Bad_Opcode },
5558
    { Bad_Opcode },
5559
    { Bad_Opcode },
5560
    { Bad_Opcode },
5561
    { Bad_Opcode },
5562
    /* 48 */
5563
    { Bad_Opcode },
5564
    { Bad_Opcode },
5565
    { Bad_Opcode },
5566
    { Bad_Opcode },
5567
    { Bad_Opcode },
5568
    { Bad_Opcode },
5569
    { Bad_Opcode },
5570
    { Bad_Opcode },
5571
    /* 50 */
5572
    { Bad_Opcode },
5573
    { Bad_Opcode },
5574
    { Bad_Opcode },
5575
    { Bad_Opcode },
5576
    { Bad_Opcode },
5577
    { Bad_Opcode },
5578
    { Bad_Opcode },
5579
    { Bad_Opcode },
5580
    /* 58 */
5581
    { Bad_Opcode },
5582
    { Bad_Opcode },
5583
    { Bad_Opcode },
5584
    { Bad_Opcode },
5585
    { Bad_Opcode },
5586
    { Bad_Opcode },
5587
    { Bad_Opcode },
5588
    { Bad_Opcode },
5589
    /* 60 */
5590
    { Bad_Opcode },
5591
    { Bad_Opcode },
5592
    { Bad_Opcode },
5593
    { Bad_Opcode },
5594
    { Bad_Opcode },
5595
    { Bad_Opcode },
5596
    { Bad_Opcode },
5597
    { Bad_Opcode },
5598
    /* 68 */
5599
    { Bad_Opcode },
5600
    { Bad_Opcode },
5601
    { Bad_Opcode },
5602
    { Bad_Opcode },
5603
    { Bad_Opcode },
5604
    { Bad_Opcode },
5605
    { Bad_Opcode },
5606
    { Bad_Opcode },
5607
    /* 70 */
5608
    { Bad_Opcode },
5609
    { Bad_Opcode },
5610
    { Bad_Opcode },
5611
    { Bad_Opcode },
5612
    { Bad_Opcode },
5613
    { Bad_Opcode },
5614
    { Bad_Opcode },
5615
    { Bad_Opcode },
5616
    /* 78 */
5617
    { Bad_Opcode },
5618
    { Bad_Opcode },
5619
    { Bad_Opcode },
5620
    { Bad_Opcode },
5621
    { Bad_Opcode },
5622
    { Bad_Opcode },
5623
    { Bad_Opcode },
5624
    { Bad_Opcode },
5625
    /* 80 */
5626
    { VEX_W_TABLE (VEX_W_XOP_09_80) },
5627
    { VEX_W_TABLE (VEX_W_XOP_09_81) },
5628
    { VEX_W_TABLE (VEX_W_XOP_09_82) },
5629
    { VEX_W_TABLE (VEX_W_XOP_09_83) },
5630
    { Bad_Opcode },
5631
    { Bad_Opcode },
5632
    { Bad_Opcode },
5633
    { Bad_Opcode },
5634
    /* 88 */
5635
    { Bad_Opcode },
5636
    { Bad_Opcode },
5637
    { Bad_Opcode },
5638
    { Bad_Opcode },
5639
    { Bad_Opcode },
5640
    { Bad_Opcode },
5641
    { Bad_Opcode },
5642
    { Bad_Opcode },
5643
    /* 90 */
5644
    { VEX_LEN_TABLE (VEX_LEN_XOP_09_90) },
5645
    { VEX_LEN_TABLE (VEX_LEN_XOP_09_91) },
5646
    { VEX_LEN_TABLE (VEX_LEN_XOP_09_92) },
5647
    { VEX_LEN_TABLE (VEX_LEN_XOP_09_93) },
5648
    { VEX_LEN_TABLE (VEX_LEN_XOP_09_94) },
5649
    { VEX_LEN_TABLE (VEX_LEN_XOP_09_95) },
5650
    { VEX_LEN_TABLE (VEX_LEN_XOP_09_96) },
5651
    { VEX_LEN_TABLE (VEX_LEN_XOP_09_97) },
5652
    /* 98 */
5653
    { VEX_LEN_TABLE (VEX_LEN_XOP_09_98) },
5654
    { VEX_LEN_TABLE (VEX_LEN_XOP_09_99) },
5655
    { VEX_LEN_TABLE (VEX_LEN_XOP_09_9A) },
5656
    { VEX_LEN_TABLE (VEX_LEN_XOP_09_9B) },
5657
    { Bad_Opcode },
5658
    { Bad_Opcode },
5659
    { Bad_Opcode },
5660
    { Bad_Opcode },
5661
    /* a0 */
5662
    { Bad_Opcode },
5663
    { Bad_Opcode },
5664
    { Bad_Opcode },
5665
    { Bad_Opcode },
5666
    { Bad_Opcode },
5667
    { Bad_Opcode },
5668
    { Bad_Opcode },
5669
    { Bad_Opcode },
5670
    /* a8 */
5671
    { Bad_Opcode },
5672
    { Bad_Opcode },
5673
    { Bad_Opcode },
5674
    { Bad_Opcode },
5675
    { Bad_Opcode },
5676
    { Bad_Opcode },
5677
    { Bad_Opcode },
5678
    { Bad_Opcode },
5679
    /* b0 */
5680
    { Bad_Opcode },
5681
    { Bad_Opcode },
5682
    { Bad_Opcode },
5683
    { Bad_Opcode },
5684
    { Bad_Opcode },
5685
    { Bad_Opcode },
5686
    { Bad_Opcode },
5687
    { Bad_Opcode },
5688
    /* b8 */
5689
    { Bad_Opcode },
5690
    { Bad_Opcode },
5691
    { Bad_Opcode },
5692
    { Bad_Opcode },
5693
    { Bad_Opcode },
5694
    { Bad_Opcode },
5695
    { Bad_Opcode },
5696
    { Bad_Opcode },
5697
    /* c0 */
5698
    { Bad_Opcode },
5699
    { VEX_LEN_TABLE (VEX_LEN_XOP_09_C1) },
5700
    { VEX_LEN_TABLE (VEX_LEN_XOP_09_C2) },
5701
    { VEX_LEN_TABLE (VEX_LEN_XOP_09_C3) },
5702
    { Bad_Opcode },
5703
    { Bad_Opcode },
5704
    { VEX_LEN_TABLE (VEX_LEN_XOP_09_C6) },
5705
    { VEX_LEN_TABLE (VEX_LEN_XOP_09_C7) },
5706
    /* c8 */
5707
    { Bad_Opcode },
5708
    { Bad_Opcode },
5709
    { Bad_Opcode },
5710
    { VEX_LEN_TABLE (VEX_LEN_XOP_09_CB) },
5711
    { Bad_Opcode },
5712
    { Bad_Opcode },
5713
    { Bad_Opcode },
5714
    { Bad_Opcode },
5715
    /* d0 */
5716
    { Bad_Opcode },
5717
    { VEX_LEN_TABLE (VEX_LEN_XOP_09_D1) },
5718
    { VEX_LEN_TABLE (VEX_LEN_XOP_09_D2) },
5719
    { VEX_LEN_TABLE (VEX_LEN_XOP_09_D3) },
5720
    { Bad_Opcode },
5721
    { Bad_Opcode },
5722
    { VEX_LEN_TABLE (VEX_LEN_XOP_09_D6) },
5723
    { VEX_LEN_TABLE (VEX_LEN_XOP_09_D7) },
5724
    /* d8 */
5725
    { Bad_Opcode },
5726
    { Bad_Opcode },
5727
    { Bad_Opcode },
5728
    { VEX_LEN_TABLE (VEX_LEN_XOP_09_DB) },
5729
    { Bad_Opcode },
5730
    { Bad_Opcode },
5731
    { Bad_Opcode },
5732
    { Bad_Opcode },
5733
    /* e0 */
5734
    { Bad_Opcode },
5735
    { VEX_LEN_TABLE (VEX_LEN_XOP_09_E1) },
5736
    { VEX_LEN_TABLE (VEX_LEN_XOP_09_E2) },
5737
    { VEX_LEN_TABLE (VEX_LEN_XOP_09_E3) },
5738
    { Bad_Opcode },
5739
    { Bad_Opcode },
5740
    { Bad_Opcode },
5741
    { Bad_Opcode },
5742
    /* e8 */
5743
    { Bad_Opcode },
5744
    { Bad_Opcode },
5745
    { Bad_Opcode },
5746
    { Bad_Opcode },
5747
    { Bad_Opcode },
5748
    { Bad_Opcode },
5749
    { Bad_Opcode },
5750
    { Bad_Opcode },
5751
    /* f0 */
5752
    { Bad_Opcode },
5753
    { Bad_Opcode },
5754
    { Bad_Opcode },
5755
    { Bad_Opcode },
5756
    { Bad_Opcode },
5757
    { Bad_Opcode },
5758
    { Bad_Opcode },
5759
    { Bad_Opcode },
5760
    /* f8 */
5761
    { Bad_Opcode },
5762
    { Bad_Opcode },
5763
    { Bad_Opcode },
5764
    { Bad_Opcode },
5765
    { Bad_Opcode },
5766
    { Bad_Opcode },
5767
    { Bad_Opcode },
5768
    { Bad_Opcode },
5769
  },
5770
  /* XOP_0A */
5771
  {
5772
    /* 00 */
5773
    { Bad_Opcode },
5774
    { Bad_Opcode },
5775
    { Bad_Opcode },
5776
    { Bad_Opcode },
5777
    { Bad_Opcode },
5778
    { Bad_Opcode },
5779
    { Bad_Opcode },
5780
    { Bad_Opcode },
5781
    /* 08 */
5782
    { Bad_Opcode },
5783
    { Bad_Opcode },
5784
    { Bad_Opcode },
5785
    { Bad_Opcode },
5786
    { Bad_Opcode },
5787
    { Bad_Opcode },
5788
    { Bad_Opcode },
5789
    { Bad_Opcode },
5790
    /* 10 */
5791
    { "bextrS", { Gdq, Edq, Id }, 0 },
5792
    { Bad_Opcode },
5793
    { VEX_LEN_TABLE (VEX_LEN_XOP_0A_12) },
5794
    { Bad_Opcode },
5795
    { Bad_Opcode },
5796
    { Bad_Opcode },
5797
    { Bad_Opcode },
5798
    { Bad_Opcode },
5799
    /* 18 */
5800
    { Bad_Opcode },
5801
    { Bad_Opcode },
5802
    { Bad_Opcode },
5803
    { Bad_Opcode },
5804
    { Bad_Opcode },
5805
    { Bad_Opcode },
5806
    { Bad_Opcode },
5807
    { Bad_Opcode },
5808
    /* 20 */
5809
    { Bad_Opcode },
5810
    { Bad_Opcode },
5811
    { Bad_Opcode },
5812
    { Bad_Opcode },
5813
    { Bad_Opcode },
5814
    { Bad_Opcode },
5815
    { Bad_Opcode },
5816
    { Bad_Opcode },
5817
    /* 28 */
5818
    { Bad_Opcode },
5819
    { Bad_Opcode },
5820
    { Bad_Opcode },
5821
    { Bad_Opcode },
5822
    { Bad_Opcode },
5823
    { Bad_Opcode },
5824
    { Bad_Opcode },
5825
    { Bad_Opcode },
5826
    /* 30 */
5827
    { Bad_Opcode },
5828
    { Bad_Opcode },
5829
    { Bad_Opcode },
5830
    { Bad_Opcode },
5831
    { Bad_Opcode },
5832
    { Bad_Opcode },
5833
    { Bad_Opcode },
5834
    { Bad_Opcode },
5835
    /* 38 */
5836
    { Bad_Opcode },
5837
    { Bad_Opcode },
5838
    { Bad_Opcode },
5839
    { Bad_Opcode },
5840
    { Bad_Opcode },
5841
    { Bad_Opcode },
5842
    { Bad_Opcode },
5843
    { Bad_Opcode },
5844
    /* 40 */
5845
    { Bad_Opcode },
5846
    { Bad_Opcode },
5847
    { Bad_Opcode },
5848
    { Bad_Opcode },
5849
    { Bad_Opcode },
5850
    { Bad_Opcode },
5851
    { Bad_Opcode },
5852
    { Bad_Opcode },
5853
    /* 48 */
5854
    { Bad_Opcode },
5855
    { Bad_Opcode },
5856
    { Bad_Opcode },
5857
    { Bad_Opcode },
5858
    { Bad_Opcode },
5859
    { Bad_Opcode },
5860
    { Bad_Opcode },
5861
    { Bad_Opcode },
5862
    /* 50 */
5863
    { Bad_Opcode },
5864
    { Bad_Opcode },
5865
    { Bad_Opcode },
5866
    { Bad_Opcode },
5867
    { Bad_Opcode },
5868
    { Bad_Opcode },
5869
    { Bad_Opcode },
5870
    { Bad_Opcode },
5871
    /* 58 */
5872
    { Bad_Opcode },
5873
    { Bad_Opcode },
5874
    { Bad_Opcode },
5875
    { Bad_Opcode },
5876
    { Bad_Opcode },
5877
    { Bad_Opcode },
5878
    { Bad_Opcode },
5879
    { Bad_Opcode },
5880
    /* 60 */
5881
    { Bad_Opcode },
5882
    { Bad_Opcode },
5883
    { Bad_Opcode },
5884
    { Bad_Opcode },
5885
    { Bad_Opcode },
5886
    { Bad_Opcode },
5887
    { Bad_Opcode },
5888
    { Bad_Opcode },
5889
    /* 68 */
5890
    { Bad_Opcode },
5891
    { Bad_Opcode },
5892
    { Bad_Opcode },
5893
    { Bad_Opcode },
5894
    { Bad_Opcode },
5895
    { Bad_Opcode },
5896
    { Bad_Opcode },
5897
    { Bad_Opcode },
5898
    /* 70 */
5899
    { Bad_Opcode },
5900
    { Bad_Opcode },
5901
    { Bad_Opcode },
5902
    { Bad_Opcode },
5903
    { Bad_Opcode },
5904
    { Bad_Opcode },
5905
    { Bad_Opcode },
5906
    { Bad_Opcode },
5907
    /* 78 */
5908
    { Bad_Opcode },
5909
    { Bad_Opcode },
5910
    { Bad_Opcode },
5911
    { Bad_Opcode },
5912
    { Bad_Opcode },
5913
    { Bad_Opcode },
5914
    { Bad_Opcode },
5915
    { Bad_Opcode },
5916
    /* 80 */
5917
    { Bad_Opcode },
5918
    { Bad_Opcode },
5919
    { Bad_Opcode },
5920
    { Bad_Opcode },
5921
    { Bad_Opcode },
5922
    { Bad_Opcode },
5923
    { Bad_Opcode },
5924
    { Bad_Opcode },
5925
    /* 88 */
5926
    { Bad_Opcode },
5927
    { Bad_Opcode },
5928
    { Bad_Opcode },
5929
    { Bad_Opcode },
5930
    { Bad_Opcode },
5931
    { Bad_Opcode },
5932
    { Bad_Opcode },
5933
    { Bad_Opcode },
5934
    /* 90 */
5935
    { Bad_Opcode },
5936
    { Bad_Opcode },
5937
    { Bad_Opcode },
5938
    { Bad_Opcode },
5939
    { Bad_Opcode },
5940
    { Bad_Opcode },
5941
    { Bad_Opcode },
5942
    { Bad_Opcode },
5943
    /* 98 */
5944
    { Bad_Opcode },
5945
    { Bad_Opcode },
5946
    { Bad_Opcode },
5947
    { Bad_Opcode },
5948
    { Bad_Opcode },
5949
    { Bad_Opcode },
5950
    { Bad_Opcode },
5951
    { Bad_Opcode },
5952
    /* a0 */
5953
    { Bad_Opcode },
5954
    { Bad_Opcode },
5955
    { Bad_Opcode },
5956
    { Bad_Opcode },
5957
    { Bad_Opcode },
5958
    { Bad_Opcode },
5959
    { Bad_Opcode },
5960
    { Bad_Opcode },
5961
    /* a8 */
5962
    { Bad_Opcode },
5963
    { Bad_Opcode },
5964
    { Bad_Opcode },
5965
    { Bad_Opcode },
5966
    { Bad_Opcode },
5967
    { Bad_Opcode },
5968
    { Bad_Opcode },
5969
    { Bad_Opcode },
5970
    /* b0 */
5971
    { Bad_Opcode },
5972
    { Bad_Opcode },
5973
    { Bad_Opcode },
5974
    { Bad_Opcode },
5975
    { Bad_Opcode },
5976
    { Bad_Opcode },
5977
    { Bad_Opcode },
5978
    { Bad_Opcode },
5979
    /* b8 */
5980
    { Bad_Opcode },
5981
    { Bad_Opcode },
5982
    { Bad_Opcode },
5983
    { Bad_Opcode },
5984
    { Bad_Opcode },
5985
    { Bad_Opcode },
5986
    { Bad_Opcode },
5987
    { Bad_Opcode },
5988
    /* c0 */
5989
    { Bad_Opcode },
5990
    { Bad_Opcode },
5991
    { Bad_Opcode },
5992
    { Bad_Opcode },
5993
    { Bad_Opcode },
5994
    { Bad_Opcode },
5995
    { Bad_Opcode },
5996
    { Bad_Opcode },
5997
    /* c8 */
5998
    { Bad_Opcode },
5999
    { Bad_Opcode },
6000
    { Bad_Opcode },
6001
    { Bad_Opcode },
6002
    { Bad_Opcode },
6003
    { Bad_Opcode },
6004
    { Bad_Opcode },
6005
    { Bad_Opcode },
6006
    /* d0 */
6007
    { Bad_Opcode },
6008
    { Bad_Opcode },
6009
    { Bad_Opcode },
6010
    { Bad_Opcode },
6011
    { Bad_Opcode },
6012
    { Bad_Opcode },
6013
    { Bad_Opcode },
6014
    { Bad_Opcode },
6015
    /* d8 */
6016
    { Bad_Opcode },
6017
    { Bad_Opcode },
6018
    { Bad_Opcode },
6019
    { Bad_Opcode },
6020
    { Bad_Opcode },
6021
    { Bad_Opcode },
6022
    { Bad_Opcode },
6023
    { Bad_Opcode },
6024
    /* e0 */
6025
    { Bad_Opcode },
6026
    { Bad_Opcode },
6027
    { Bad_Opcode },
6028
    { Bad_Opcode },
6029
    { Bad_Opcode },
6030
    { Bad_Opcode },
6031
    { Bad_Opcode },
6032
    { Bad_Opcode },
6033
    /* e8 */
6034
    { Bad_Opcode },
6035
    { Bad_Opcode },
6036
    { Bad_Opcode },
6037
    { Bad_Opcode },
6038
    { Bad_Opcode },
6039
    { Bad_Opcode },
6040
    { Bad_Opcode },
6041
    { Bad_Opcode },
6042
    /* f0 */
6043
    { Bad_Opcode },
6044
    { Bad_Opcode },
6045
    { Bad_Opcode },
6046
    { Bad_Opcode },
6047
    { Bad_Opcode },
6048
    { Bad_Opcode },
6049
    { Bad_Opcode },
6050
    { Bad_Opcode },
6051
    /* f8 */
6052
    { Bad_Opcode },
6053
    { Bad_Opcode },
6054
    { Bad_Opcode },
6055
    { Bad_Opcode },
6056
    { Bad_Opcode },
6057
    { Bad_Opcode },
6058
    { Bad_Opcode },
6059
    { Bad_Opcode },
6060
  },
6061
};
6062
6063
static const struct dis386 vex_table[][256] = {
6064
  /* VEX_0F */
6065
  {
6066
    /* 00 */
6067
    { Bad_Opcode },
6068
    { Bad_Opcode },
6069
    { Bad_Opcode },
6070
    { Bad_Opcode },
6071
    { Bad_Opcode },
6072
    { Bad_Opcode },
6073
    { Bad_Opcode },
6074
    { Bad_Opcode },
6075
    /* 08 */
6076
    { Bad_Opcode },
6077
    { Bad_Opcode },
6078
    { Bad_Opcode },
6079
    { Bad_Opcode },
6080
    { Bad_Opcode },
6081
    { Bad_Opcode },
6082
    { Bad_Opcode },
6083
    { Bad_Opcode },
6084
    /* 10 */
6085
    { PREFIX_TABLE (PREFIX_0F10) },
6086
    { PREFIX_TABLE (PREFIX_0F11) },
6087
    { PREFIX_TABLE (PREFIX_VEX_0F12) },
6088
    { VEX_LEN_TABLE (VEX_LEN_0F13) },
6089
    { "vunpcklpX",  { XM, Vex, EXx }, PREFIX_OPCODE },
6090
    { "vunpckhpX",  { XM, Vex, EXx }, PREFIX_OPCODE },
6091
    { PREFIX_TABLE (PREFIX_VEX_0F16) },
6092
    { VEX_LEN_TABLE (VEX_LEN_0F17) },
6093
    /* 18 */
6094
    { Bad_Opcode },
6095
    { Bad_Opcode },
6096
    { Bad_Opcode },
6097
    { Bad_Opcode },
6098
    { Bad_Opcode },
6099
    { Bad_Opcode },
6100
    { Bad_Opcode },
6101
    { Bad_Opcode },
6102
    /* 20 */
6103
    { Bad_Opcode },
6104
    { Bad_Opcode },
6105
    { Bad_Opcode },
6106
    { Bad_Opcode },
6107
    { Bad_Opcode },
6108
    { Bad_Opcode },
6109
    { Bad_Opcode },
6110
    { Bad_Opcode },
6111
    /* 28 */
6112
    { "vmovapX",  { XM, EXx }, PREFIX_OPCODE },
6113
    { "vmovapX",  { EXxS, XM }, PREFIX_OPCODE },
6114
    { PREFIX_TABLE (PREFIX_VEX_0F2A) },
6115
    { "vmovntpX", { Mx, XM }, PREFIX_OPCODE },
6116
    { PREFIX_TABLE (PREFIX_VEX_0F2C) },
6117
    { PREFIX_TABLE (PREFIX_VEX_0F2D) },
6118
    { PREFIX_TABLE (PREFIX_0F2E) },
6119
    { PREFIX_TABLE (PREFIX_0F2F) },
6120
    /* 30 */
6121
    { Bad_Opcode },
6122
    { Bad_Opcode },
6123
    { Bad_Opcode },
6124
    { Bad_Opcode },
6125
    { Bad_Opcode },
6126
    { Bad_Opcode },
6127
    { Bad_Opcode },
6128
    { Bad_Opcode },
6129
    /* 38 */
6130
    { Bad_Opcode },
6131
    { Bad_Opcode },
6132
    { Bad_Opcode },
6133
    { Bad_Opcode },
6134
    { Bad_Opcode },
6135
    { Bad_Opcode },
6136
    { Bad_Opcode },
6137
    { Bad_Opcode },
6138
    /* 40 */
6139
    { Bad_Opcode },
6140
    { VEX_LEN_TABLE (VEX_LEN_0F41) },
6141
    { VEX_LEN_TABLE (VEX_LEN_0F42) },
6142
    { Bad_Opcode },
6143
    { VEX_LEN_TABLE (VEX_LEN_0F44) },
6144
    { VEX_LEN_TABLE (VEX_LEN_0F45) },
6145
    { VEX_LEN_TABLE (VEX_LEN_0F46) },
6146
    { VEX_LEN_TABLE (VEX_LEN_0F47) },
6147
    /* 48 */
6148
    { Bad_Opcode },
6149
    { Bad_Opcode },
6150
    { VEX_LEN_TABLE (VEX_LEN_0F4A) },
6151
    { VEX_LEN_TABLE (VEX_LEN_0F4B) },
6152
    { Bad_Opcode },
6153
    { Bad_Opcode },
6154
    { Bad_Opcode },
6155
    { Bad_Opcode },
6156
    /* 50 */
6157
    { "vmovmskpX",  { Gdq, Ux }, PREFIX_OPCODE },
6158
    { PREFIX_TABLE (PREFIX_0F51) },
6159
    { PREFIX_TABLE (PREFIX_0F52) },
6160
    { PREFIX_TABLE (PREFIX_0F53) },
6161
    { "vandpX",   { XM, Vex, EXx }, PREFIX_OPCODE },
6162
    { "vandnpX",  { XM, Vex, EXx }, PREFIX_OPCODE },
6163
    { "vorpX",    { XM, Vex, EXx }, PREFIX_OPCODE },
6164
    { "vxorpX",   { XM, Vex, EXx }, PREFIX_OPCODE },
6165
    /* 58 */
6166
    { PREFIX_TABLE (PREFIX_0F58) },
6167
    { PREFIX_TABLE (PREFIX_0F59) },
6168
    { PREFIX_TABLE (PREFIX_0F5A) },
6169
    { PREFIX_TABLE (PREFIX_0F5B) },
6170
    { PREFIX_TABLE (PREFIX_0F5C) },
6171
    { PREFIX_TABLE (PREFIX_0F5D) },
6172
    { PREFIX_TABLE (PREFIX_0F5E) },
6173
    { PREFIX_TABLE (PREFIX_0F5F) },
6174
    /* 60 */
6175
    { "vpunpcklbw", { XM, Vex, EXx }, PREFIX_DATA },
6176
    { "vpunpcklwd", { XM, Vex, EXx }, PREFIX_DATA },
6177
    { "vpunpckldq", { XM, Vex, EXx }, PREFIX_DATA },
6178
    { "vpacksswb",  { XM, Vex, EXx }, PREFIX_DATA },
6179
    { "vpcmpgtb", { XM, Vex, EXx }, PREFIX_DATA },
6180
    { "vpcmpgtw", { XM, Vex, EXx }, PREFIX_DATA },
6181
    { "vpcmpgtd", { XM, Vex, EXx }, PREFIX_DATA },
6182
    { "vpackuswb",  { XM, Vex, EXx }, PREFIX_DATA },
6183
    /* 68 */
6184
    { "vpunpckhbw", { XM, Vex, EXx }, PREFIX_DATA },
6185
    { "vpunpckhwd", { XM, Vex, EXx }, PREFIX_DATA },
6186
    { "vpunpckhdq", { XM, Vex, EXx }, PREFIX_DATA },
6187
    { "vpackssdw",  { XM, Vex, EXx }, PREFIX_DATA },
6188
    { "vpunpcklqdq",  { XM, Vex, EXx }, PREFIX_DATA },
6189
    { "vpunpckhqdq",  { XM, Vex, EXx }, PREFIX_DATA },
6190
    { VEX_LEN_TABLE (VEX_LEN_0F6E) },
6191
    { PREFIX_TABLE (PREFIX_VEX_0F6F) },
6192
    /* 70 */
6193
    { PREFIX_TABLE (PREFIX_VEX_0F70) },
6194
    { REG_TABLE (REG_VEX_0F71) },
6195
    { REG_TABLE (REG_VEX_0F72) },
6196
    { REG_TABLE (REG_VEX_0F73) },
6197
    { "vpcmpeqb", { XM, Vex, EXx }, PREFIX_DATA },
6198
    { "vpcmpeqw", { XM, Vex, EXx }, PREFIX_DATA },
6199
    { "vpcmpeqd", { XM, Vex, EXx }, PREFIX_DATA },
6200
    { VEX_LEN_TABLE (VEX_LEN_0F77) },
6201
    /* 78 */
6202
    { Bad_Opcode },
6203
    { Bad_Opcode },
6204
    { Bad_Opcode },
6205
    { Bad_Opcode },
6206
    { PREFIX_TABLE (PREFIX_0F7C) },
6207
    { PREFIX_TABLE (PREFIX_0F7D) },
6208
    { PREFIX_TABLE (PREFIX_VEX_0F7E) },
6209
    { PREFIX_TABLE (PREFIX_VEX_0F7F) },
6210
    /* 80 */
6211
    { Bad_Opcode },
6212
    { Bad_Opcode },
6213
    { Bad_Opcode },
6214
    { Bad_Opcode },
6215
    { Bad_Opcode },
6216
    { Bad_Opcode },
6217
    { Bad_Opcode },
6218
    { Bad_Opcode },
6219
    /* 88 */
6220
    { Bad_Opcode },
6221
    { Bad_Opcode },
6222
    { Bad_Opcode },
6223
    { Bad_Opcode },
6224
    { Bad_Opcode },
6225
    { Bad_Opcode },
6226
    { Bad_Opcode },
6227
    { Bad_Opcode },
6228
    /* 90 */
6229
    { VEX_LEN_TABLE (VEX_LEN_0F90) },
6230
    { VEX_LEN_TABLE (VEX_LEN_0F91) },
6231
    { VEX_LEN_TABLE (VEX_LEN_0F92) },
6232
    { VEX_LEN_TABLE (VEX_LEN_0F93) },
6233
    { Bad_Opcode },
6234
    { Bad_Opcode },
6235
    { Bad_Opcode },
6236
    { Bad_Opcode },
6237
    /* 98 */
6238
    { VEX_LEN_TABLE (VEX_LEN_0F98) },
6239
    { VEX_LEN_TABLE (VEX_LEN_0F99) },
6240
    { Bad_Opcode },
6241
    { Bad_Opcode },
6242
    { Bad_Opcode },
6243
    { Bad_Opcode },
6244
    { Bad_Opcode },
6245
    { Bad_Opcode },
6246
    /* a0 */
6247
    { Bad_Opcode },
6248
    { Bad_Opcode },
6249
    { Bad_Opcode },
6250
    { Bad_Opcode },
6251
    { Bad_Opcode },
6252
    { Bad_Opcode },
6253
    { Bad_Opcode },
6254
    { Bad_Opcode },
6255
    /* a8 */
6256
    { Bad_Opcode },
6257
    { Bad_Opcode },
6258
    { Bad_Opcode },
6259
    { Bad_Opcode },
6260
    { Bad_Opcode },
6261
    { Bad_Opcode },
6262
    { REG_TABLE (REG_VEX_0FAE) },
6263
    { Bad_Opcode },
6264
    /* b0 */
6265
    { Bad_Opcode },
6266
    { Bad_Opcode },
6267
    { Bad_Opcode },
6268
    { Bad_Opcode },
6269
    { Bad_Opcode },
6270
    { Bad_Opcode },
6271
    { Bad_Opcode },
6272
    { Bad_Opcode },
6273
    /* b8 */
6274
    { Bad_Opcode },
6275
    { Bad_Opcode },
6276
    { Bad_Opcode },
6277
    { Bad_Opcode },
6278
    { Bad_Opcode },
6279
    { Bad_Opcode },
6280
    { Bad_Opcode },
6281
    { Bad_Opcode },
6282
    /* c0 */
6283
    { Bad_Opcode },
6284
    { Bad_Opcode },
6285
    { PREFIX_TABLE (PREFIX_0FC2) },
6286
    { Bad_Opcode },
6287
    { VEX_LEN_TABLE (VEX_LEN_0FC4) },
6288
    { "vpextrw",  { Gd, Uxmm, Ib }, PREFIX_DATA },
6289
    { "vshufpX",  { XM, Vex, EXx, Ib }, PREFIX_OPCODE },
6290
    { Bad_Opcode },
6291
    /* c8 */
6292
    { Bad_Opcode },
6293
    { Bad_Opcode },
6294
    { Bad_Opcode },
6295
    { Bad_Opcode },
6296
    { Bad_Opcode },
6297
    { Bad_Opcode },
6298
    { Bad_Opcode },
6299
    { Bad_Opcode },
6300
    /* d0 */
6301
    { PREFIX_TABLE (PREFIX_0FD0) },
6302
    { "vpsrlw",   { XM, Vex, EXxmm }, PREFIX_DATA },
6303
    { "vpsrld",   { XM, Vex, EXxmm }, PREFIX_DATA },
6304
    { "vpsrlq",   { XM, Vex, EXxmm }, PREFIX_DATA },
6305
    { "vpaddq",   { XM, Vex, EXx }, PREFIX_DATA },
6306
    { "vpmullw",  { XM, Vex, EXx }, PREFIX_DATA },
6307
    { VEX_LEN_TABLE (VEX_LEN_0FD6) },
6308
    { "vpmovmskb",  { Gdq, Ux }, PREFIX_DATA },
6309
    /* d8 */
6310
    { "vpsubusb", { XM, Vex, EXx }, PREFIX_DATA },
6311
    { "vpsubusw", { XM, Vex, EXx }, PREFIX_DATA },
6312
    { "vpminub",  { XM, Vex, EXx }, PREFIX_DATA },
6313
    { "vpand",    { XM, Vex, EXx }, PREFIX_DATA },
6314
    { "vpaddusb", { XM, Vex, EXx }, PREFIX_DATA },
6315
    { "vpaddusw", { XM, Vex, EXx }, PREFIX_DATA },
6316
    { "vpmaxub",  { XM, Vex, EXx }, PREFIX_DATA },
6317
    { "vpandn",   { XM, Vex, EXx }, PREFIX_DATA },
6318
    /* e0 */
6319
    { "vpavgb",   { XM, Vex, EXx }, PREFIX_DATA },
6320
    { "vpsraw",   { XM, Vex, EXxmm }, PREFIX_DATA },
6321
    { "vpsrad",   { XM, Vex, EXxmm }, PREFIX_DATA },
6322
    { "vpavgw",   { XM, Vex, EXx }, PREFIX_DATA },
6323
    { "vpmulhuw", { XM, Vex, EXx }, PREFIX_DATA },
6324
    { "vpmulhw",  { XM, Vex, EXx }, PREFIX_DATA },
6325
    { PREFIX_TABLE (PREFIX_0FE6) },
6326
    { "vmovntdq", { Mx, XM }, PREFIX_DATA },
6327
    /* e8 */
6328
    { "vpsubsb",  { XM, Vex, EXx }, PREFIX_DATA },
6329
    { "vpsubsw",  { XM, Vex, EXx }, PREFIX_DATA },
6330
    { "vpminsw",  { XM, Vex, EXx }, PREFIX_DATA },
6331
    { "vpor",   { XM, Vex, EXx }, PREFIX_DATA },
6332
    { "vpaddsb",  { XM, Vex, EXx }, PREFIX_DATA },
6333
    { "vpaddsw",  { XM, Vex, EXx }, PREFIX_DATA },
6334
    { "vpmaxsw",  { XM, Vex, EXx }, PREFIX_DATA },
6335
    { "vpxor",    { XM, Vex, EXx }, PREFIX_DATA },
6336
    /* f0 */
6337
    { PREFIX_TABLE (PREFIX_0FF0) },
6338
    { "vpsllw",   { XM, Vex, EXxmm }, PREFIX_DATA },
6339
    { "vpslld",   { XM, Vex, EXxmm }, PREFIX_DATA },
6340
    { "vpsllq",   { XM, Vex, EXxmm }, PREFIX_DATA },
6341
    { "vpmuludq", { XM, Vex, EXx }, PREFIX_DATA },
6342
    { "vpmaddwd", { XM, Vex, EXx }, PREFIX_DATA },
6343
    { "vpsadbw",  { XM, Vex, EXx }, PREFIX_DATA },
6344
    { "vmaskmovdqu",  { XM, Uxmm }, PREFIX_DATA },
6345
    /* f8 */
6346
    { "vpsubb",   { XM, Vex, EXx }, PREFIX_DATA },
6347
    { "vpsubw",   { XM, Vex, EXx }, PREFIX_DATA },
6348
    { "vpsubd",   { XM, Vex, EXx }, PREFIX_DATA },
6349
    { "vpsubq",   { XM, Vex, EXx }, PREFIX_DATA },
6350
    { "vpaddb",   { XM, Vex, EXx }, PREFIX_DATA },
6351
    { "vpaddw",   { XM, Vex, EXx }, PREFIX_DATA },
6352
    { "vpaddd",   { XM, Vex, EXx }, PREFIX_DATA },
6353
    { Bad_Opcode },
6354
  },
6355
  /* VEX_0F38 */
6356
  {
6357
    /* 00 */
6358
    { "vpshufb",  { XM, Vex, EXx }, PREFIX_DATA },
6359
    { "vphaddw",  { XM, Vex, EXx }, PREFIX_DATA },
6360
    { "vphaddd",  { XM, Vex, EXx }, PREFIX_DATA },
6361
    { "vphaddsw", { XM, Vex, EXx }, PREFIX_DATA },
6362
    { "vpmaddubsw", { XM, Vex, EXx }, PREFIX_DATA },
6363
    { "vphsubw",  { XM, Vex, EXx }, PREFIX_DATA },
6364
    { "vphsubd",  { XM, Vex, EXx }, PREFIX_DATA },
6365
    { "vphsubsw", { XM, Vex, EXx }, PREFIX_DATA },
6366
    /* 08 */
6367
    { "vpsignb",  { XM, Vex, EXx }, PREFIX_DATA },
6368
    { "vpsignw",  { XM, Vex, EXx }, PREFIX_DATA },
6369
    { "vpsignd",  { XM, Vex, EXx }, PREFIX_DATA },
6370
    { "vpmulhrsw",  { XM, Vex, EXx }, PREFIX_DATA },
6371
    { VEX_W_TABLE (VEX_W_0F380C) },
6372
    { VEX_W_TABLE (VEX_W_0F380D) },
6373
    { VEX_W_TABLE (VEX_W_0F380E) },
6374
    { VEX_W_TABLE (VEX_W_0F380F) },
6375
    /* 10 */
6376
    { Bad_Opcode },
6377
    { Bad_Opcode },
6378
    { Bad_Opcode },
6379
    { VEX_W_TABLE (VEX_W_0F3813) },
6380
    { Bad_Opcode },
6381
    { Bad_Opcode },
6382
    { VEX_LEN_TABLE (VEX_LEN_0F3816) },
6383
    { "vptest",   { XM, EXx }, PREFIX_DATA },
6384
    /* 18 */
6385
    { VEX_W_TABLE (VEX_W_0F3818) },
6386
    { VEX_LEN_TABLE (VEX_LEN_0F3819) },
6387
    { VEX_LEN_TABLE (VEX_LEN_0F381A) },
6388
    { Bad_Opcode },
6389
    { "vpabsb",   { XM, EXx }, PREFIX_DATA },
6390
    { "vpabsw",   { XM, EXx }, PREFIX_DATA },
6391
    { "vpabsd",   { XM, EXx }, PREFIX_DATA },
6392
    { Bad_Opcode },
6393
    /* 20 */
6394
    { "vpmovsxbw",  { XM, EXxmmq }, PREFIX_DATA },
6395
    { "vpmovsxbd",  { XM, EXxmmqd }, PREFIX_DATA },
6396
    { "vpmovsxbq",  { XM, EXxmmdw }, PREFIX_DATA },
6397
    { "vpmovsxwd",  { XM, EXxmmq }, PREFIX_DATA },
6398
    { "vpmovsxwq",  { XM, EXxmmqd }, PREFIX_DATA },
6399
    { "vpmovsxdq",  { XM, EXxmmq }, PREFIX_DATA },
6400
    { Bad_Opcode },
6401
    { Bad_Opcode },
6402
    /* 28 */
6403
    { "vpmuldq",  { XM, Vex, EXx }, PREFIX_DATA },
6404
    { "vpcmpeqq", { XM, Vex, EXx }, PREFIX_DATA },
6405
    { "vmovntdqa",  { XM, Mx }, PREFIX_DATA },
6406
    { "vpackusdw",  { XM, Vex, EXx }, PREFIX_DATA },
6407
    { VEX_W_TABLE (VEX_W_0F382C) },
6408
    { VEX_W_TABLE (VEX_W_0F382D) },
6409
    { VEX_W_TABLE (VEX_W_0F382E) },
6410
    { VEX_W_TABLE (VEX_W_0F382F) },
6411
    /* 30 */
6412
    { "vpmovzxbw",  { XM, EXxmmq }, PREFIX_DATA },
6413
    { "vpmovzxbd",  { XM, EXxmmqd }, PREFIX_DATA },
6414
    { "vpmovzxbq",  { XM, EXxmmdw }, PREFIX_DATA },
6415
    { "vpmovzxwd",  { XM, EXxmmq }, PREFIX_DATA },
6416
    { "vpmovzxwq",  { XM, EXxmmqd }, PREFIX_DATA },
6417
    { "vpmovzxdq",  { XM, EXxmmq }, PREFIX_DATA },
6418
    { VEX_LEN_TABLE (VEX_LEN_0F3836) },
6419
    { "vpcmpgtq", { XM, Vex, EXx }, PREFIX_DATA },
6420
    /* 38 */
6421
    { "vpminsb",  { XM, Vex, EXx }, PREFIX_DATA },
6422
    { "vpminsd",  { XM, Vex, EXx }, PREFIX_DATA },
6423
    { "vpminuw",  { XM, Vex, EXx }, PREFIX_DATA },
6424
    { "vpminud",  { XM, Vex, EXx }, PREFIX_DATA },
6425
    { "vpmaxsb",  { XM, Vex, EXx }, PREFIX_DATA },
6426
    { "vpmaxsd",  { XM, Vex, EXx }, PREFIX_DATA },
6427
    { "vpmaxuw",  { XM, Vex, EXx }, PREFIX_DATA },
6428
    { "vpmaxud",  { XM, Vex, EXx }, PREFIX_DATA },
6429
    /* 40 */
6430
    { "vpmulld",  { XM, Vex, EXx }, PREFIX_DATA },
6431
    { VEX_LEN_TABLE (VEX_LEN_0F3841) },
6432
    { Bad_Opcode },
6433
    { Bad_Opcode },
6434
    { Bad_Opcode },
6435
    { "vpsrlv%DQ", { XM, Vex, EXx }, PREFIX_DATA },
6436
    { VEX_W_TABLE (VEX_W_0F3846) },
6437
    { "vpsllv%DQ", { XM, Vex, EXx }, PREFIX_DATA },
6438
    /* 48 */
6439
    { Bad_Opcode },
6440
    { X86_64_TABLE (X86_64_VEX_0F3849) },
6441
    { Bad_Opcode },
6442
    { X86_64_TABLE (X86_64_VEX_0F384B) },
6443
    { Bad_Opcode },
6444
    { Bad_Opcode },
6445
    { Bad_Opcode },
6446
    { Bad_Opcode },
6447
    /* 50 */
6448
    { VEX_W_TABLE (VEX_W_0F3850) },
6449
    { VEX_W_TABLE (VEX_W_0F3851) },
6450
    { VEX_W_TABLE (VEX_W_0F3852) },
6451
    { VEX_W_TABLE (VEX_W_0F3853) },
6452
    { Bad_Opcode },
6453
    { Bad_Opcode },
6454
    { Bad_Opcode },
6455
    { Bad_Opcode },
6456
    /* 58 */
6457
    { VEX_W_TABLE (VEX_W_0F3858) },
6458
    { VEX_W_TABLE (VEX_W_0F3859) },
6459
    { VEX_LEN_TABLE (VEX_LEN_0F385A) },
6460
    { Bad_Opcode },
6461
    { X86_64_TABLE (X86_64_VEX_0F385C) },
6462
    { Bad_Opcode },
6463
    { X86_64_TABLE (X86_64_VEX_0F385E) },
6464
    { Bad_Opcode },
6465
    /* 60 */
6466
    { Bad_Opcode },
6467
    { Bad_Opcode },
6468
    { Bad_Opcode },
6469
    { Bad_Opcode },
6470
    { Bad_Opcode },
6471
    { Bad_Opcode },
6472
    { Bad_Opcode },
6473
    { Bad_Opcode },
6474
    /* 68 */
6475
    { Bad_Opcode },
6476
    { Bad_Opcode },
6477
    { Bad_Opcode },
6478
    { Bad_Opcode },
6479
    { X86_64_TABLE (X86_64_VEX_0F386C) },
6480
    { Bad_Opcode },
6481
    { Bad_Opcode },
6482
    { Bad_Opcode },
6483
    /* 70 */
6484
    { Bad_Opcode },
6485
    { Bad_Opcode },
6486
    { PREFIX_TABLE (PREFIX_VEX_0F3872) },
6487
    { Bad_Opcode },
6488
    { Bad_Opcode },
6489
    { Bad_Opcode },
6490
    { Bad_Opcode },
6491
    { Bad_Opcode },
6492
    /* 78 */
6493
    { VEX_W_TABLE (VEX_W_0F3878) },
6494
    { VEX_W_TABLE (VEX_W_0F3879) },
6495
    { Bad_Opcode },
6496
    { Bad_Opcode },
6497
    { Bad_Opcode },
6498
    { Bad_Opcode },
6499
    { Bad_Opcode },
6500
    { Bad_Opcode },
6501
    /* 80 */
6502
    { Bad_Opcode },
6503
    { Bad_Opcode },
6504
    { Bad_Opcode },
6505
    { Bad_Opcode },
6506
    { Bad_Opcode },
6507
    { Bad_Opcode },
6508
    { Bad_Opcode },
6509
    { Bad_Opcode },
6510
    /* 88 */
6511
    { Bad_Opcode },
6512
    { Bad_Opcode },
6513
    { Bad_Opcode },
6514
    { Bad_Opcode },
6515
    { "vpmaskmov%DQ", { XM, Vex, Mx }, PREFIX_DATA },
6516
    { Bad_Opcode },
6517
    { "vpmaskmov%DQ", { Mx, Vex, XM }, PREFIX_DATA },
6518
    { Bad_Opcode },
6519
    /* 90 */
6520
    { "vpgatherd%DQ", { XM, MVexVSIBDWpX, VexGatherD }, PREFIX_DATA },
6521
    { "vpgatherq%DQ", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, PREFIX_DATA },
6522
    { "vgatherdp%XW", { XM, MVexVSIBDWpX, VexGatherD }, PREFIX_DATA },
6523
    { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, PREFIX_DATA },
6524
    { Bad_Opcode },
6525
    { Bad_Opcode },
6526
    { "vfmaddsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6527
    { "vfmsubadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6528
    /* 98 */
6529
    { "vfmadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6530
    { "vfmadd132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6531
    { "vfmsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6532
    { "vfmsub132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6533
    { "vfnmadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6534
    { "vfnmadd132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6535
    { "vfnmsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6536
    { "vfnmsub132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6537
    /* a0 */
6538
    { Bad_Opcode },
6539
    { Bad_Opcode },
6540
    { Bad_Opcode },
6541
    { Bad_Opcode },
6542
    { Bad_Opcode },
6543
    { Bad_Opcode },
6544
    { "vfmaddsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6545
    { "vfmsubadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6546
    /* a8 */
6547
    { "vfmadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6548
    { "vfmadd213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6549
    { "vfmsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6550
    { "vfmsub213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6551
    { "vfnmadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6552
    { "vfnmadd213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6553
    { "vfnmsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6554
    { "vfnmsub213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6555
    /* b0 */
6556
    { VEX_W_TABLE (VEX_W_0F38B0) },
6557
    { VEX_W_TABLE (VEX_W_0F38B1) },
6558
    { Bad_Opcode },
6559
    { Bad_Opcode },
6560
    { VEX_W_TABLE (VEX_W_0F38B4) },
6561
    { VEX_W_TABLE (VEX_W_0F38B5) },
6562
    { "vfmaddsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6563
    { "vfmsubadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6564
    /* b8 */
6565
    { "vfmadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6566
    { "vfmadd231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6567
    { "vfmsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6568
    { "vfmsub231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6569
    { "vfnmadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6570
    { "vfnmadd231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6571
    { "vfnmsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6572
    { "vfnmsub231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6573
    /* c0 */
6574
    { Bad_Opcode },
6575
    { Bad_Opcode },
6576
    { Bad_Opcode },
6577
    { Bad_Opcode },
6578
    { Bad_Opcode },
6579
    { Bad_Opcode },
6580
    { Bad_Opcode },
6581
    { Bad_Opcode },
6582
    /* c8 */
6583
    { Bad_Opcode },
6584
    { Bad_Opcode },
6585
    { Bad_Opcode },
6586
    { PREFIX_TABLE (PREFIX_VEX_0F38CB) },
6587
    { PREFIX_TABLE (PREFIX_VEX_0F38CC) },
6588
    { PREFIX_TABLE (PREFIX_VEX_0F38CD) },
6589
    { Bad_Opcode },
6590
    { VEX_W_TABLE (VEX_W_0F38CF) },
6591
    /* d0 */
6592
    { Bad_Opcode },
6593
    { Bad_Opcode },
6594
    { VEX_W_TABLE (VEX_W_0F38D2) },
6595
    { VEX_W_TABLE (VEX_W_0F38D3) },
6596
    { Bad_Opcode },
6597
    { Bad_Opcode },
6598
    { Bad_Opcode },
6599
    { Bad_Opcode },
6600
    /* d8 */
6601
    { Bad_Opcode },
6602
    { Bad_Opcode },
6603
    { VEX_W_TABLE (VEX_W_0F38DA) },
6604
    { VEX_LEN_TABLE (VEX_LEN_0F38DB) },
6605
    { "vaesenc",  { XM, Vex, EXx }, PREFIX_DATA },
6606
    { "vaesenclast",  { XM, Vex, EXx }, PREFIX_DATA },
6607
    { "vaesdec",  { XM, Vex, EXx }, PREFIX_DATA },
6608
    { "vaesdeclast",  { XM, Vex, EXx }, PREFIX_DATA },
6609
    /* e0 */
6610
    { X86_64_TABLE (X86_64_VEX_0F38E0) },
6611
    { X86_64_TABLE (X86_64_VEX_0F38E1) },
6612
    { X86_64_TABLE (X86_64_VEX_0F38E2) },
6613
    { X86_64_TABLE (X86_64_VEX_0F38E3) },
6614
    { X86_64_TABLE (X86_64_VEX_0F38E4) },
6615
    { X86_64_TABLE (X86_64_VEX_0F38E5) },
6616
    { X86_64_TABLE (X86_64_VEX_0F38E6) },
6617
    { X86_64_TABLE (X86_64_VEX_0F38E7) },
6618
    /* e8 */
6619
    { X86_64_TABLE (X86_64_VEX_0F38E8) },
6620
    { X86_64_TABLE (X86_64_VEX_0F38E9) },
6621
    { X86_64_TABLE (X86_64_VEX_0F38EA) },
6622
    { X86_64_TABLE (X86_64_VEX_0F38EB) },
6623
    { X86_64_TABLE (X86_64_VEX_0F38EC) },
6624
    { X86_64_TABLE (X86_64_VEX_0F38ED) },
6625
    { X86_64_TABLE (X86_64_VEX_0F38EE) },
6626
    { X86_64_TABLE (X86_64_VEX_0F38EF) },
6627
    /* f0 */
6628
    { Bad_Opcode },
6629
    { Bad_Opcode },
6630
    { VEX_LEN_TABLE (VEX_LEN_0F38F2) },
6631
    { VEX_LEN_TABLE (VEX_LEN_0F38F3) },
6632
    { Bad_Opcode },
6633
    { VEX_LEN_TABLE (VEX_LEN_0F38F5) },
6634
    { VEX_LEN_TABLE (VEX_LEN_0F38F6) },
6635
    { VEX_LEN_TABLE (VEX_LEN_0F38F7) },
6636
    /* f8 */
6637
    { Bad_Opcode },
6638
    { Bad_Opcode },
6639
    { Bad_Opcode },
6640
    { Bad_Opcode },
6641
    { Bad_Opcode },
6642
    { Bad_Opcode },
6643
    { Bad_Opcode },
6644
    { Bad_Opcode },
6645
  },
6646
  /* VEX_0F3A */
6647
  {
6648
    /* 00 */
6649
    { VEX_LEN_TABLE (VEX_LEN_0F3A00) },
6650
    { VEX_LEN_TABLE (VEX_LEN_0F3A01) },
6651
    { VEX_W_TABLE (VEX_W_0F3A02) },
6652
    { Bad_Opcode },
6653
    { VEX_W_TABLE (VEX_W_0F3A04) },
6654
    { VEX_W_TABLE (VEX_W_0F3A05) },
6655
    { VEX_LEN_TABLE (VEX_LEN_0F3A06) },
6656
    { Bad_Opcode },
6657
    /* 08 */
6658
    { "vroundps", { XM, EXx, Ib }, PREFIX_DATA },
6659
    { "vroundpd", { XM, EXx, Ib }, PREFIX_DATA },
6660
    { "vroundss", { XMScalar, VexScalar, EXd, Ib }, PREFIX_DATA },
6661
    { "vroundsd", { XMScalar, VexScalar, EXq, Ib }, PREFIX_DATA },
6662
    { "vblendps", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6663
    { "vblendpd", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6664
    { "vpblendw", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6665
    { "vpalignr", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6666
    /* 10 */
6667
    { Bad_Opcode },
6668
    { Bad_Opcode },
6669
    { Bad_Opcode },
6670
    { Bad_Opcode },
6671
    { VEX_LEN_TABLE (VEX_LEN_0F3A14) },
6672
    { VEX_LEN_TABLE (VEX_LEN_0F3A15) },
6673
    { VEX_LEN_TABLE (VEX_LEN_0F3A16) },
6674
    { VEX_LEN_TABLE (VEX_LEN_0F3A17) },
6675
    /* 18 */
6676
    { VEX_LEN_TABLE (VEX_LEN_0F3A18) },
6677
    { VEX_LEN_TABLE (VEX_LEN_0F3A19) },
6678
    { Bad_Opcode },
6679
    { Bad_Opcode },
6680
    { Bad_Opcode },
6681
    { VEX_W_TABLE (VEX_W_0F3A1D) },
6682
    { Bad_Opcode },
6683
    { Bad_Opcode },
6684
    /* 20 */
6685
    { VEX_LEN_TABLE (VEX_LEN_0F3A20) },
6686
    { VEX_LEN_TABLE (VEX_LEN_0F3A21) },
6687
    { VEX_LEN_TABLE (VEX_LEN_0F3A22) },
6688
    { Bad_Opcode },
6689
    { Bad_Opcode },
6690
    { Bad_Opcode },
6691
    { Bad_Opcode },
6692
    { Bad_Opcode },
6693
    /* 28 */
6694
    { Bad_Opcode },
6695
    { Bad_Opcode },
6696
    { Bad_Opcode },
6697
    { Bad_Opcode },
6698
    { Bad_Opcode },
6699
    { Bad_Opcode },
6700
    { Bad_Opcode },
6701
    { Bad_Opcode },
6702
    /* 30 */
6703
    { VEX_LEN_TABLE (VEX_LEN_0F3A30) },
6704
    { VEX_LEN_TABLE (VEX_LEN_0F3A31) },
6705
    { VEX_LEN_TABLE (VEX_LEN_0F3A32) },
6706
    { VEX_LEN_TABLE (VEX_LEN_0F3A33) },
6707
    { Bad_Opcode },
6708
    { Bad_Opcode },
6709
    { Bad_Opcode },
6710
    { Bad_Opcode },
6711
    /* 38 */
6712
    { VEX_LEN_TABLE (VEX_LEN_0F3A38) },
6713
    { VEX_LEN_TABLE (VEX_LEN_0F3A39) },
6714
    { Bad_Opcode },
6715
    { Bad_Opcode },
6716
    { Bad_Opcode },
6717
    { Bad_Opcode },
6718
    { Bad_Opcode },
6719
    { Bad_Opcode },
6720
    /* 40 */
6721
    { "vdpps",    { XM, Vex, EXx, Ib }, PREFIX_DATA },
6722
    { VEX_LEN_TABLE (VEX_LEN_0F3A41) },
6723
    { "vmpsadbw", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6724
    { Bad_Opcode },
6725
    { "vpclmulqdq", { XM, Vex, EXx, PCLMUL }, PREFIX_DATA },
6726
    { Bad_Opcode },
6727
    { VEX_LEN_TABLE (VEX_LEN_0F3A46) },
6728
    { Bad_Opcode },
6729
    /* 48 */
6730
    { "vpermil2ps", { XM, Vex, EXx, XMVexI4, VexI4 }, PREFIX_DATA },
6731
    { "vpermil2pd", { XM, Vex, EXx, XMVexI4, VexI4 }, PREFIX_DATA },
6732
    { VEX_W_TABLE (VEX_W_0F3A4A) },
6733
    { VEX_W_TABLE (VEX_W_0F3A4B) },
6734
    { VEX_W_TABLE (VEX_W_0F3A4C) },
6735
    { Bad_Opcode },
6736
    { Bad_Opcode },
6737
    { Bad_Opcode },
6738
    /* 50 */
6739
    { Bad_Opcode },
6740
    { Bad_Opcode },
6741
    { Bad_Opcode },
6742
    { Bad_Opcode },
6743
    { Bad_Opcode },
6744
    { Bad_Opcode },
6745
    { Bad_Opcode },
6746
    { Bad_Opcode },
6747
    /* 58 */
6748
    { Bad_Opcode },
6749
    { Bad_Opcode },
6750
    { Bad_Opcode },
6751
    { Bad_Opcode },
6752
    { "vfmaddsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6753
    { "vfmaddsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6754
    { "vfmsubaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6755
    { "vfmsubaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6756
    /* 60 */
6757
    { VEX_LEN_TABLE (VEX_LEN_0F3A60) },
6758
    { VEX_LEN_TABLE (VEX_LEN_0F3A61) },
6759
    { VEX_LEN_TABLE (VEX_LEN_0F3A62) },
6760
    { VEX_LEN_TABLE (VEX_LEN_0F3A63) },
6761
    { Bad_Opcode },
6762
    { Bad_Opcode },
6763
    { Bad_Opcode },
6764
    { Bad_Opcode },
6765
    /* 68 */
6766
    { "vfmaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6767
    { "vfmaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6768
    { "vfmaddss", { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA },
6769
    { "vfmaddsd", { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA },
6770
    { "vfmsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6771
    { "vfmsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6772
    { "vfmsubss", { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA },
6773
    { "vfmsubsd", { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA },
6774
    /* 70 */
6775
    { Bad_Opcode },
6776
    { Bad_Opcode },
6777
    { Bad_Opcode },
6778
    { Bad_Opcode },
6779
    { Bad_Opcode },
6780
    { Bad_Opcode },
6781
    { Bad_Opcode },
6782
    { Bad_Opcode },
6783
    /* 78 */
6784
    { "vfnmaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6785
    { "vfnmaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6786
    { "vfnmaddss",  { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA },
6787
    { "vfnmaddsd",  { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA },
6788
    { "vfnmsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6789
    { "vfnmsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6790
    { "vfnmsubss",  { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA },
6791
    { "vfnmsubsd",  { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA },
6792
    /* 80 */
6793
    { Bad_Opcode },
6794
    { Bad_Opcode },
6795
    { Bad_Opcode },
6796
    { Bad_Opcode },
6797
    { Bad_Opcode },
6798
    { Bad_Opcode },
6799
    { Bad_Opcode },
6800
    { Bad_Opcode },
6801
    /* 88 */
6802
    { Bad_Opcode },
6803
    { Bad_Opcode },
6804
    { Bad_Opcode },
6805
    { Bad_Opcode },
6806
    { Bad_Opcode },
6807
    { Bad_Opcode },
6808
    { Bad_Opcode },
6809
    { Bad_Opcode },
6810
    /* 90 */
6811
    { Bad_Opcode },
6812
    { Bad_Opcode },
6813
    { Bad_Opcode },
6814
    { Bad_Opcode },
6815
    { Bad_Opcode },
6816
    { Bad_Opcode },
6817
    { Bad_Opcode },
6818
    { Bad_Opcode },
6819
    /* 98 */
6820
    { Bad_Opcode },
6821
    { Bad_Opcode },
6822
    { Bad_Opcode },
6823
    { Bad_Opcode },
6824
    { Bad_Opcode },
6825
    { Bad_Opcode },
6826
    { Bad_Opcode },
6827
    { Bad_Opcode },
6828
    /* a0 */
6829
    { Bad_Opcode },
6830
    { Bad_Opcode },
6831
    { Bad_Opcode },
6832
    { Bad_Opcode },
6833
    { Bad_Opcode },
6834
    { Bad_Opcode },
6835
    { Bad_Opcode },
6836
    { Bad_Opcode },
6837
    /* a8 */
6838
    { Bad_Opcode },
6839
    { Bad_Opcode },
6840
    { Bad_Opcode },
6841
    { Bad_Opcode },
6842
    { Bad_Opcode },
6843
    { Bad_Opcode },
6844
    { Bad_Opcode },
6845
    { Bad_Opcode },
6846
    /* b0 */
6847
    { Bad_Opcode },
6848
    { Bad_Opcode },
6849
    { Bad_Opcode },
6850
    { Bad_Opcode },
6851
    { Bad_Opcode },
6852
    { Bad_Opcode },
6853
    { Bad_Opcode },
6854
    { Bad_Opcode },
6855
    /* b8 */
6856
    { Bad_Opcode },
6857
    { Bad_Opcode },
6858
    { Bad_Opcode },
6859
    { Bad_Opcode },
6860
    { Bad_Opcode },
6861
    { Bad_Opcode },
6862
    { Bad_Opcode },
6863
    { Bad_Opcode },
6864
    /* c0 */
6865
    { Bad_Opcode },
6866
    { Bad_Opcode },
6867
    { Bad_Opcode },
6868
    { Bad_Opcode },
6869
    { Bad_Opcode },
6870
    { Bad_Opcode },
6871
    { Bad_Opcode },
6872
    { Bad_Opcode },
6873
    /* c8 */
6874
    { Bad_Opcode },
6875
    { Bad_Opcode },
6876
    { Bad_Opcode },
6877
    { Bad_Opcode },
6878
    { Bad_Opcode },
6879
    { Bad_Opcode },
6880
    { VEX_W_TABLE (VEX_W_0F3ACE) },
6881
    { VEX_W_TABLE (VEX_W_0F3ACF) },
6882
    /* d0 */
6883
    { Bad_Opcode },
6884
    { Bad_Opcode },
6885
    { Bad_Opcode },
6886
    { Bad_Opcode },
6887
    { Bad_Opcode },
6888
    { Bad_Opcode },
6889
    { Bad_Opcode },
6890
    { Bad_Opcode },
6891
    /* d8 */
6892
    { Bad_Opcode },
6893
    { Bad_Opcode },
6894
    { Bad_Opcode },
6895
    { Bad_Opcode },
6896
    { Bad_Opcode },
6897
    { Bad_Opcode },
6898
    { VEX_W_TABLE (VEX_W_0F3ADE) },
6899
    { VEX_LEN_TABLE (VEX_LEN_0F3ADF) },
6900
    /* e0 */
6901
    { Bad_Opcode },
6902
    { Bad_Opcode },
6903
    { Bad_Opcode },
6904
    { Bad_Opcode },
6905
    { Bad_Opcode },
6906
    { Bad_Opcode },
6907
    { Bad_Opcode },
6908
    { Bad_Opcode },
6909
    /* e8 */
6910
    { Bad_Opcode },
6911
    { Bad_Opcode },
6912
    { Bad_Opcode },
6913
    { Bad_Opcode },
6914
    { Bad_Opcode },
6915
    { Bad_Opcode },
6916
    { Bad_Opcode },
6917
    { Bad_Opcode },
6918
    /* f0 */
6919
    { VEX_LEN_TABLE (VEX_LEN_0F3AF0) },
6920
    { Bad_Opcode },
6921
    { Bad_Opcode },
6922
    { Bad_Opcode },
6923
    { Bad_Opcode },
6924
    { Bad_Opcode },
6925
    { Bad_Opcode },
6926
    { Bad_Opcode },
6927
    /* f8 */
6928
    { Bad_Opcode },
6929
    { Bad_Opcode },
6930
    { Bad_Opcode },
6931
    { Bad_Opcode },
6932
    { Bad_Opcode },
6933
    { Bad_Opcode },
6934
    { Bad_Opcode },
6935
    { Bad_Opcode },
6936
  },
6937
};
6938
6939
#include "i386-dis-evex.h"
6940
6941
static const struct dis386 vex_len_table[][2] = {
6942
  /* VEX_LEN_0F12_P_0 */
6943
  {
6944
    { MOD_TABLE (MOD_0F12_PREFIX_0) },
6945
  },
6946
6947
  /* VEX_LEN_0F12_P_2 */
6948
  {
6949
    { "%XEVmovlpYX",  { XM, Vex, Mq }, 0 },
6950
  },
6951
6952
  /* VEX_LEN_0F13 */
6953
  {
6954
    { "%XEVmovlpYX",  { Mq, XM }, PREFIX_OPCODE },
6955
  },
6956
6957
  /* VEX_LEN_0F16_P_0 */
6958
  {
6959
    { MOD_TABLE (MOD_0F16_PREFIX_0) },
6960
  },
6961
6962
  /* VEX_LEN_0F16_P_2 */
6963
  {
6964
    { "%XEVmovhpYX",  { XM, Vex, Mq }, 0 },
6965
  },
6966
6967
  /* VEX_LEN_0F17 */
6968
  {
6969
    { "%XEVmovhpYX",  { Mq, XM }, PREFIX_OPCODE },
6970
  },
6971
6972
  /* VEX_LEN_0F41 */
6973
  {
6974
    { Bad_Opcode },
6975
    { VEX_W_TABLE (VEX_W_0F41_L_1) },
6976
  },
6977
6978
  /* VEX_LEN_0F42 */
6979
  {
6980
    { Bad_Opcode },
6981
    { VEX_W_TABLE (VEX_W_0F42_L_1) },
6982
  },
6983
6984
  /* VEX_LEN_0F44 */
6985
  {
6986
    { VEX_W_TABLE (VEX_W_0F44_L_0) },
6987
  },
6988
6989
  /* VEX_LEN_0F45 */
6990
  {
6991
    { Bad_Opcode },
6992
    { VEX_W_TABLE (VEX_W_0F45_L_1) },
6993
  },
6994
6995
  /* VEX_LEN_0F46 */
6996
  {
6997
    { Bad_Opcode },
6998
    { VEX_W_TABLE (VEX_W_0F46_L_1) },
6999
  },
7000
7001
  /* VEX_LEN_0F47 */
7002
  {
7003
    { Bad_Opcode },
7004
    { VEX_W_TABLE (VEX_W_0F47_L_1) },
7005
  },
7006
7007
  /* VEX_LEN_0F4A */
7008
  {
7009
    { Bad_Opcode },
7010
    { VEX_W_TABLE (VEX_W_0F4A_L_1) },
7011
  },
7012
7013
  /* VEX_LEN_0F4B */
7014
  {
7015
    { Bad_Opcode },
7016
    { VEX_W_TABLE (VEX_W_0F4B_L_1) },
7017
  },
7018
7019
  /* VEX_LEN_0F6E */
7020
  {
7021
    { "%XEvmovYK",  { XMScalar, Edq }, PREFIX_DATA },
7022
  },
7023
7024
  /* VEX_LEN_0F77 */
7025
  {
7026
    { "vzeroupper", { XX }, 0 },
7027
    { "vzeroall", { XX }, 0 },
7028
  },
7029
7030
  /* VEX_LEN_0F7E_P_1 */
7031
  {
7032
    { "%XEvmovqY",  { XMScalar, EXq }, 0 },
7033
  },
7034
7035
  /* VEX_LEN_0F7E_P_2 */
7036
  {
7037
    { "%XEvmovK", { Edq, XMScalar }, 0 },
7038
  },
7039
7040
  /* VEX_LEN_0F90 */
7041
  {
7042
    { VEX_W_TABLE (VEX_W_0F90_L_0) },
7043
  },
7044
7045
  /* VEX_LEN_0F91 */
7046
  {
7047
    { VEX_W_TABLE (VEX_W_0F91_L_0) },
7048
  },
7049
7050
  /* VEX_LEN_0F92 */
7051
  {
7052
    { VEX_W_TABLE (VEX_W_0F92_L_0) },
7053
  },
7054
7055
  /* VEX_LEN_0F93 */
7056
  {
7057
    { VEX_W_TABLE (VEX_W_0F93_L_0) },
7058
  },
7059
7060
  /* VEX_LEN_0F98 */
7061
  {
7062
    { VEX_W_TABLE (VEX_W_0F98_L_0) },
7063
  },
7064
7065
  /* VEX_LEN_0F99 */
7066
  {
7067
    { VEX_W_TABLE (VEX_W_0F99_L_0) },
7068
  },
7069
7070
  /* VEX_LEN_0FAE_R_2 */
7071
  {
7072
    { "vldmxcsr", { Md }, 0 },
7073
  },
7074
7075
  /* VEX_LEN_0FAE_R_3 */
7076
  {
7077
    { "vstmxcsr", { Md }, 0 },
7078
  },
7079
7080
  /* VEX_LEN_0FC4 */
7081
  {
7082
    { "%XEvpinsrwY",  { XM, Vex, Edw, Ib }, PREFIX_DATA },
7083
  },
7084
7085
  /* VEX_LEN_0FD6 */
7086
  {
7087
    { "%XEvmovqY",  { EXqS, XMScalar }, PREFIX_DATA },
7088
  },
7089
7090
  /* VEX_LEN_0F3816 */
7091
  {
7092
    { Bad_Opcode },
7093
    { VEX_W_TABLE (VEX_W_0F3816_L_1) },
7094
  },
7095
7096
  /* VEX_LEN_0F3819 */
7097
  {
7098
    { Bad_Opcode },
7099
    { VEX_W_TABLE (VEX_W_0F3819_L_1) },
7100
  },
7101
7102
  /* VEX_LEN_0F381A */
7103
  {
7104
    { Bad_Opcode },
7105
    { VEX_W_TABLE (VEX_W_0F381A_L_1) },
7106
  },
7107
7108
  /* VEX_LEN_0F3836 */
7109
  {
7110
    { Bad_Opcode },
7111
    { VEX_W_TABLE (VEX_W_0F3836) },
7112
  },
7113
7114
  /* VEX_LEN_0F3841 */
7115
  {
7116
    { "vphminposuw",  { XM, EXx }, PREFIX_DATA },
7117
  },
7118
7119
  /* VEX_LEN_0F3849_X86_64 */
7120
  {
7121
    { VEX_W_TABLE (VEX_W_0F3849_X86_64_L_0) },
7122
  },
7123
7124
  /* VEX_LEN_0F384B_X86_64 */
7125
  {
7126
    { VEX_W_TABLE (VEX_W_0F384B_X86_64_L_0) },
7127
  },
7128
7129
  /* VEX_LEN_0F385A */
7130
  {
7131
    { Bad_Opcode },
7132
    { VEX_W_TABLE (VEX_W_0F385A_L_0) },
7133
  },
7134
7135
  /* VEX_LEN_0F385C_X86_64 */
7136
  {
7137
    { VEX_W_TABLE (VEX_W_0F385C_X86_64_L_0) },
7138
  },
7139
7140
  /* VEX_LEN_0F385E_X86_64 */
7141
  {
7142
    { VEX_W_TABLE (VEX_W_0F385E_X86_64_L_0) },
7143
  },
7144
7145
  /* VEX_LEN_0F386C_X86_64 */
7146
  {
7147
    { VEX_W_TABLE (VEX_W_0F386C_X86_64_L_0) },
7148
  },
7149
7150
  /* VEX_LEN_0F38CB_P_3_W_0 */
7151
  {
7152
    { Bad_Opcode },
7153
    { "vsha512rnds2", { XM, Vex, Rxmmq }, 0 },
7154
  },
7155
7156
  /* VEX_LEN_0F38CC_P_3_W_0 */
7157
  {
7158
    { Bad_Opcode },
7159
    { "vsha512msg1", { XM, Rxmmq }, 0 },
7160
  },
7161
7162
  /* VEX_LEN_0F38CD_P_3_W_0 */
7163
  {
7164
    { Bad_Opcode },
7165
    { "vsha512msg2", { XM, Rymm }, 0 },
7166
  },
7167
7168
  /* VEX_LEN_0F38DA_W_0_P_0 */
7169
  {
7170
    { "vsm3msg1", { XM, Vex, EXxmm }, 0 },
7171
  },
7172
7173
  /* VEX_LEN_0F38DA_W_0_P_2 */
7174
  {
7175
    { "vsm3msg2", { XM, Vex, EXxmm }, 0 },
7176
  },
7177
7178
  /* VEX_LEN_0F38DB */
7179
  {
7180
    { "vaesimc",  { XM, EXx }, PREFIX_DATA },
7181
  },
7182
7183
  /* VEX_LEN_0F38F2 */
7184
  {
7185
    { PREFIX_TABLE (PREFIX_VEX_0F38F2_L_0) },
7186
  },
7187
7188
  /* VEX_LEN_0F38F3 */
7189
  {
7190
    { PREFIX_TABLE (PREFIX_VEX_0F38F3_L_0) },
7191
  },
7192
7193
  /* VEX_LEN_0F38F5 */
7194
  {
7195
    { PREFIX_TABLE(PREFIX_VEX_0F38F5_L_0) },
7196
  },
7197
7198
  /* VEX_LEN_0F38F6 */
7199
  {
7200
    { PREFIX_TABLE(PREFIX_VEX_0F38F6_L_0) },
7201
  },
7202
7203
  /* VEX_LEN_0F38F7 */
7204
  {
7205
    { PREFIX_TABLE(PREFIX_VEX_0F38F7_L_0) },
7206
  },
7207
7208
  /* VEX_LEN_0F3A00 */
7209
  {
7210
    { Bad_Opcode },
7211
    { VEX_W_TABLE (VEX_W_0F3A00_L_1) },
7212
  },
7213
7214
  /* VEX_LEN_0F3A01 */
7215
  {
7216
    { Bad_Opcode },
7217
    { VEX_W_TABLE (VEX_W_0F3A01_L_1) },
7218
  },
7219
7220
  /* VEX_LEN_0F3A06 */
7221
  {
7222
    { Bad_Opcode },
7223
    { VEX_W_TABLE (VEX_W_0F3A06_L_1) },
7224
  },
7225
7226
  /* VEX_LEN_0F3A14 */
7227
  {
7228
    { "%XEvpextrb", { Edb, XM, Ib }, PREFIX_DATA },
7229
  },
7230
7231
  /* VEX_LEN_0F3A15 */
7232
  {
7233
    { "%XEvpextrw", { Edw, XM, Ib }, PREFIX_DATA },
7234
  },
7235
7236
  /* VEX_LEN_0F3A16  */
7237
  {
7238
    { "%XEvpextrK", { Edq, XM, Ib }, PREFIX_DATA },
7239
  },
7240
7241
  /* VEX_LEN_0F3A17 */
7242
  {
7243
    { "%XEvextractps",  { Ed, XM, Ib }, PREFIX_DATA },
7244
  },
7245
7246
  /* VEX_LEN_0F3A18 */
7247
  {
7248
    { Bad_Opcode },
7249
    { VEX_W_TABLE (VEX_W_0F3A18_L_1) },
7250
  },
7251
7252
  /* VEX_LEN_0F3A19 */
7253
  {
7254
    { Bad_Opcode },
7255
    { VEX_W_TABLE (VEX_W_0F3A19_L_1) },
7256
  },
7257
7258
  /* VEX_LEN_0F3A20 */
7259
  {
7260
    { "%XEvpinsrbY",  { XM, Vex, Edb, Ib }, PREFIX_DATA },
7261
  },
7262
7263
  /* VEX_LEN_0F3A21 */
7264
  {
7265
    { "%XEvinsertpsY",  { XM, Vex, EXd, Ib }, PREFIX_DATA },
7266
  },
7267
7268
  /* VEX_LEN_0F3A22 */
7269
  {
7270
    { "%XEvpinsrYK",  { XM, Vex, Edq, Ib }, PREFIX_DATA },
7271
  },
7272
7273
  /* VEX_LEN_0F3A30 */
7274
  {
7275
    { "kshiftr%BW", { MaskG, MaskR, Ib }, PREFIX_DATA },
7276
  },
7277
7278
  /* VEX_LEN_0F3A31 */
7279
  {
7280
    { "kshiftr%DQ", { MaskG, MaskR, Ib }, PREFIX_DATA },
7281
  },
7282
7283
  /* VEX_LEN_0F3A32 */
7284
  {
7285
    { "kshiftl%BW", { MaskG, MaskR, Ib }, PREFIX_DATA },
7286
  },
7287
7288
  /* VEX_LEN_0F3A33 */
7289
  {
7290
    { "kshiftl%DQ", { MaskG, MaskR, Ib }, PREFIX_DATA },
7291
  },
7292
7293
  /* VEX_LEN_0F3A38 */
7294
  {
7295
    { Bad_Opcode },
7296
    { VEX_W_TABLE (VEX_W_0F3A38_L_1) },
7297
  },
7298
7299
  /* VEX_LEN_0F3A39 */
7300
  {
7301
    { Bad_Opcode },
7302
    { VEX_W_TABLE (VEX_W_0F3A39_L_1) },
7303
  },
7304
7305
  /* VEX_LEN_0F3A41 */
7306
  {
7307
    { "vdppd",    { XM, Vex, EXx, Ib }, PREFIX_DATA },
7308
  },
7309
7310
  /* VEX_LEN_0F3A46 */
7311
  {
7312
    { Bad_Opcode },
7313
    { VEX_W_TABLE (VEX_W_0F3A46_L_1) },
7314
  },
7315
7316
  /* VEX_LEN_0F3A60 */
7317
  {
7318
    { "vpcmpestrm!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
7319
  },
7320
7321
  /* VEX_LEN_0F3A61 */
7322
  {
7323
    { "vpcmpestri!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
7324
  },
7325
7326
  /* VEX_LEN_0F3A62 */
7327
  {
7328
    { "vpcmpistrm", { XM, EXx, Ib }, PREFIX_DATA },
7329
  },
7330
7331
  /* VEX_LEN_0F3A63 */
7332
  {
7333
    { "vpcmpistri", { XM, EXx, Ib }, PREFIX_DATA },
7334
  },
7335
7336
  /* VEX_LEN_0F3ADE_W_0 */
7337
  {
7338
    { "vsm3rnds2", { XM, Vex, EXxmm, Ib }, PREFIX_DATA },
7339
  },
7340
7341
  /* VEX_LEN_0F3ADF */
7342
  {
7343
    { "vaeskeygenassist", { XM, EXx, Ib }, PREFIX_DATA },
7344
  },
7345
7346
  /* VEX_LEN_0F3AF0 */
7347
  {
7348
    { PREFIX_TABLE (PREFIX_VEX_0F3AF0_L_0) },
7349
  },
7350
7351
  /* VEX_LEN_MAP7_F8 */
7352
  {
7353
    { VEX_W_TABLE (VEX_W_MAP7_F8_L_0) },
7354
  },
7355
7356
  /* VEX_LEN_XOP_08_85 */
7357
  {
7358
    { VEX_W_TABLE (VEX_W_XOP_08_85_L_0) },
7359
  },
7360
7361
  /* VEX_LEN_XOP_08_86 */
7362
  {
7363
    { VEX_W_TABLE (VEX_W_XOP_08_86_L_0) },
7364
  },
7365
7366
  /* VEX_LEN_XOP_08_87 */
7367
  {
7368
    { VEX_W_TABLE (VEX_W_XOP_08_87_L_0) },
7369
  },
7370
7371
  /* VEX_LEN_XOP_08_8E */
7372
  {
7373
    { VEX_W_TABLE (VEX_W_XOP_08_8E_L_0) },
7374
  },
7375
7376
  /* VEX_LEN_XOP_08_8F */
7377
  {
7378
    { VEX_W_TABLE (VEX_W_XOP_08_8F_L_0) },
7379
  },
7380
7381
  /* VEX_LEN_XOP_08_95 */
7382
  {
7383
    { VEX_W_TABLE (VEX_W_XOP_08_95_L_0) },
7384
  },
7385
7386
  /* VEX_LEN_XOP_08_96 */
7387
  {
7388
    { VEX_W_TABLE (VEX_W_XOP_08_96_L_0) },
7389
  },
7390
7391
  /* VEX_LEN_XOP_08_97 */
7392
  {
7393
    { VEX_W_TABLE (VEX_W_XOP_08_97_L_0) },
7394
  },
7395
7396
  /* VEX_LEN_XOP_08_9E */
7397
  {
7398
    { VEX_W_TABLE (VEX_W_XOP_08_9E_L_0) },
7399
  },
7400
7401
  /* VEX_LEN_XOP_08_9F */
7402
  {
7403
    { VEX_W_TABLE (VEX_W_XOP_08_9F_L_0) },
7404
  },
7405
7406
  /* VEX_LEN_XOP_08_A3 */
7407
  {
7408
    { "vpperm",   { XM, Vex, EXx, XMVexI4 }, 0 },
7409
  },
7410
7411
  /* VEX_LEN_XOP_08_A6 */
7412
  {
7413
    { VEX_W_TABLE (VEX_W_XOP_08_A6_L_0) },
7414
  },
7415
7416
  /* VEX_LEN_XOP_08_B6 */
7417
  {
7418
    { VEX_W_TABLE (VEX_W_XOP_08_B6_L_0) },
7419
  },
7420
7421
  /* VEX_LEN_XOP_08_C0 */
7422
  {
7423
    { VEX_W_TABLE (VEX_W_XOP_08_C0_L_0) },
7424
  },
7425
7426
  /* VEX_LEN_XOP_08_C1 */
7427
  {
7428
    { VEX_W_TABLE (VEX_W_XOP_08_C1_L_0) },
7429
  },
7430
7431
  /* VEX_LEN_XOP_08_C2 */
7432
  {
7433
    { VEX_W_TABLE (VEX_W_XOP_08_C2_L_0) },
7434
  },
7435
7436
  /* VEX_LEN_XOP_08_C3 */
7437
  {
7438
    { VEX_W_TABLE (VEX_W_XOP_08_C3_L_0) },
7439
  },
7440
7441
  /* VEX_LEN_XOP_08_CC */
7442
  {
7443
    { VEX_W_TABLE (VEX_W_XOP_08_CC_L_0) },
7444
  },
7445
7446
  /* VEX_LEN_XOP_08_CD */
7447
  {
7448
    { VEX_W_TABLE (VEX_W_XOP_08_CD_L_0) },
7449
  },
7450
7451
  /* VEX_LEN_XOP_08_CE */
7452
  {
7453
    { VEX_W_TABLE (VEX_W_XOP_08_CE_L_0) },
7454
  },
7455
7456
  /* VEX_LEN_XOP_08_CF */
7457
  {
7458
    { VEX_W_TABLE (VEX_W_XOP_08_CF_L_0) },
7459
  },
7460
7461
  /* VEX_LEN_XOP_08_EC */
7462
  {
7463
    { VEX_W_TABLE (VEX_W_XOP_08_EC_L_0) },
7464
  },
7465
7466
  /* VEX_LEN_XOP_08_ED */
7467
  {
7468
    { VEX_W_TABLE (VEX_W_XOP_08_ED_L_0) },
7469
  },
7470
7471
  /* VEX_LEN_XOP_08_EE */
7472
  {
7473
    { VEX_W_TABLE (VEX_W_XOP_08_EE_L_0) },
7474
  },
7475
7476
  /* VEX_LEN_XOP_08_EF */
7477
  {
7478
    { VEX_W_TABLE (VEX_W_XOP_08_EF_L_0) },
7479
  },
7480
7481
  /* VEX_LEN_XOP_09_01 */
7482
  {
7483
    { REG_TABLE (REG_XOP_09_01_L_0) },
7484
  },
7485
7486
  /* VEX_LEN_XOP_09_02 */
7487
  {
7488
    { REG_TABLE (REG_XOP_09_02_L_0) },
7489
  },
7490
7491
  /* VEX_LEN_XOP_09_12 */
7492
  {
7493
    { REG_TABLE (REG_XOP_09_12_L_0) },
7494
  },
7495
7496
  /* VEX_LEN_XOP_09_82_W_0 */
7497
  {
7498
    { "vfrczss",  { XM, EXd }, 0 },
7499
  },
7500
7501
  /* VEX_LEN_XOP_09_83_W_0 */
7502
  {
7503
    { "vfrczsd",  { XM, EXq }, 0 },
7504
  },
7505
7506
  /* VEX_LEN_XOP_09_90 */
7507
  {
7508
    { "vprotb",   { XM, EXx, VexW }, 0 },
7509
  },
7510
7511
  /* VEX_LEN_XOP_09_91 */
7512
  {
7513
    { "vprotw",   { XM, EXx, VexW }, 0 },
7514
  },
7515
7516
  /* VEX_LEN_XOP_09_92 */
7517
  {
7518
    { "vprotd",   { XM, EXx, VexW }, 0 },
7519
  },
7520
7521
  /* VEX_LEN_XOP_09_93 */
7522
  {
7523
    { "vprotq",   { XM, EXx, VexW }, 0 },
7524
  },
7525
7526
  /* VEX_LEN_XOP_09_94 */
7527
  {
7528
    { "vpshlb",   { XM, EXx, VexW }, 0 },
7529
  },
7530
7531
  /* VEX_LEN_XOP_09_95 */
7532
  {
7533
    { "vpshlw",   { XM, EXx, VexW }, 0 },
7534
  },
7535
7536
  /* VEX_LEN_XOP_09_96 */
7537
  {
7538
    { "vpshld",   { XM, EXx, VexW }, 0 },
7539
  },
7540
7541
  /* VEX_LEN_XOP_09_97 */
7542
  {
7543
    { "vpshlq",   { XM, EXx, VexW }, 0 },
7544
  },
7545
7546
  /* VEX_LEN_XOP_09_98 */
7547
  {
7548
    { "vpshab",   { XM, EXx, VexW }, 0 },
7549
  },
7550
7551
  /* VEX_LEN_XOP_09_99 */
7552
  {
7553
    { "vpshaw",   { XM, EXx, VexW }, 0 },
7554
  },
7555
7556
  /* VEX_LEN_XOP_09_9A */
7557
  {
7558
    { "vpshad",   { XM, EXx, VexW }, 0 },
7559
  },
7560
7561
  /* VEX_LEN_XOP_09_9B */
7562
  {
7563
    { "vpshaq",   { XM, EXx, VexW }, 0 },
7564
  },
7565
7566
  /* VEX_LEN_XOP_09_C1 */
7567
  {
7568
    { VEX_W_TABLE (VEX_W_XOP_09_C1_L_0) },
7569
  },
7570
7571
  /* VEX_LEN_XOP_09_C2 */
7572
  {
7573
    { VEX_W_TABLE (VEX_W_XOP_09_C2_L_0) },
7574
  },
7575
7576
  /* VEX_LEN_XOP_09_C3 */
7577
  {
7578
    { VEX_W_TABLE (VEX_W_XOP_09_C3_L_0) },
7579
  },
7580
7581
  /* VEX_LEN_XOP_09_C6 */
7582
  {
7583
    { VEX_W_TABLE (VEX_W_XOP_09_C6_L_0) },
7584
  },
7585
7586
  /* VEX_LEN_XOP_09_C7 */
7587
  {
7588
    { VEX_W_TABLE (VEX_W_XOP_09_C7_L_0) },
7589
  },
7590
7591
  /* VEX_LEN_XOP_09_CB */
7592
  {
7593
    { VEX_W_TABLE (VEX_W_XOP_09_CB_L_0) },
7594
  },
7595
7596
  /* VEX_LEN_XOP_09_D1 */
7597
  {
7598
    { VEX_W_TABLE (VEX_W_XOP_09_D1_L_0) },
7599
  },
7600
7601
  /* VEX_LEN_XOP_09_D2 */
7602
  {
7603
    { VEX_W_TABLE (VEX_W_XOP_09_D2_L_0) },
7604
  },
7605
7606
  /* VEX_LEN_XOP_09_D3 */
7607
  {
7608
    { VEX_W_TABLE (VEX_W_XOP_09_D3_L_0) },
7609
  },
7610
7611
  /* VEX_LEN_XOP_09_D6 */
7612
  {
7613
    { VEX_W_TABLE (VEX_W_XOP_09_D6_L_0) },
7614
  },
7615
7616
  /* VEX_LEN_XOP_09_D7 */
7617
  {
7618
    { VEX_W_TABLE (VEX_W_XOP_09_D7_L_0) },
7619
  },
7620
7621
  /* VEX_LEN_XOP_09_DB */
7622
  {
7623
    { VEX_W_TABLE (VEX_W_XOP_09_DB_L_0) },
7624
  },
7625
7626
  /* VEX_LEN_XOP_09_E1 */
7627
  {
7628
    { VEX_W_TABLE (VEX_W_XOP_09_E1_L_0) },
7629
  },
7630
7631
  /* VEX_LEN_XOP_09_E2 */
7632
  {
7633
    { VEX_W_TABLE (VEX_W_XOP_09_E2_L_0) },
7634
  },
7635
7636
  /* VEX_LEN_XOP_09_E3 */
7637
  {
7638
    { VEX_W_TABLE (VEX_W_XOP_09_E3_L_0) },
7639
  },
7640
7641
  /* VEX_LEN_XOP_0A_12 */
7642
  {
7643
    { REG_TABLE (REG_XOP_0A_12_L_0) },
7644
  },
7645
};
7646
7647
#include "i386-dis-evex-len.h"
7648
7649
static const struct dis386 vex_w_table[][2] = {
7650
  {
7651
    /* VEX_W_0F41_L_1_M_1 */
7652
    { PREFIX_TABLE (PREFIX_VEX_0F41_L_1_W_0) },
7653
    { PREFIX_TABLE (PREFIX_VEX_0F41_L_1_W_1) },
7654
  },
7655
  {
7656
    /* VEX_W_0F42_L_1_M_1 */
7657
    { PREFIX_TABLE (PREFIX_VEX_0F42_L_1_W_0) },
7658
    { PREFIX_TABLE (PREFIX_VEX_0F42_L_1_W_1) },
7659
  },
7660
  {
7661
    /* VEX_W_0F44_L_0_M_1 */
7662
    { PREFIX_TABLE (PREFIX_VEX_0F44_L_0_W_0) },
7663
    { PREFIX_TABLE (PREFIX_VEX_0F44_L_0_W_1) },
7664
  },
7665
  {
7666
    /* VEX_W_0F45_L_1_M_1 */
7667
    { PREFIX_TABLE (PREFIX_VEX_0F45_L_1_W_0) },
7668
    { PREFIX_TABLE (PREFIX_VEX_0F45_L_1_W_1) },
7669
  },
7670
  {
7671
    /* VEX_W_0F46_L_1_M_1 */
7672
    { PREFIX_TABLE (PREFIX_VEX_0F46_L_1_W_0) },
7673
    { PREFIX_TABLE (PREFIX_VEX_0F46_L_1_W_1) },
7674
  },
7675
  {
7676
    /* VEX_W_0F47_L_1_M_1 */
7677
    { PREFIX_TABLE (PREFIX_VEX_0F47_L_1_W_0) },
7678
    { PREFIX_TABLE (PREFIX_VEX_0F47_L_1_W_1) },
7679
  },
7680
  {
7681
    /* VEX_W_0F4A_L_1_M_1 */
7682
    { PREFIX_TABLE (PREFIX_VEX_0F4A_L_1_W_0) },
7683
    { PREFIX_TABLE (PREFIX_VEX_0F4A_L_1_W_1) },
7684
  },
7685
  {
7686
    /* VEX_W_0F4B_L_1_M_1 */
7687
    { PREFIX_TABLE (PREFIX_VEX_0F4B_L_1_W_0) },
7688
    { PREFIX_TABLE (PREFIX_VEX_0F4B_L_1_W_1) },
7689
  },
7690
  {
7691
    /* VEX_W_0F90_L_0 */
7692
    { PREFIX_TABLE (PREFIX_VEX_0F90_L_0_W_0) },
7693
    { PREFIX_TABLE (PREFIX_VEX_0F90_L_0_W_1) },
7694
  },
7695
  {
7696
    /* VEX_W_0F91_L_0_M_0 */
7697
    { PREFIX_TABLE (PREFIX_VEX_0F91_L_0_W_0) },
7698
    { PREFIX_TABLE (PREFIX_VEX_0F91_L_0_W_1) },
7699
  },
7700
  {
7701
    /* VEX_W_0F92_L_0_M_1 */
7702
    { PREFIX_TABLE (PREFIX_VEX_0F92_L_0_W_0) },
7703
    { PREFIX_TABLE (PREFIX_VEX_0F92_L_0_W_1) },
7704
  },
7705
  {
7706
    /* VEX_W_0F93_L_0_M_1 */
7707
    { PREFIX_TABLE (PREFIX_VEX_0F93_L_0_W_0) },
7708
    { PREFIX_TABLE (PREFIX_VEX_0F93_L_0_W_1) },
7709
  },
7710
  {
7711
    /* VEX_W_0F98_L_0_M_1 */
7712
    { PREFIX_TABLE (PREFIX_VEX_0F98_L_0_W_0) },
7713
    { PREFIX_TABLE (PREFIX_VEX_0F98_L_0_W_1) },
7714
  },
7715
  {
7716
    /* VEX_W_0F99_L_0_M_1 */
7717
    { PREFIX_TABLE (PREFIX_VEX_0F99_L_0_W_0) },
7718
    { PREFIX_TABLE (PREFIX_VEX_0F99_L_0_W_1) },
7719
  },
7720
  {
7721
    /* VEX_W_0F380C  */
7722
    { "%XEvpermilps", { XM, Vex, EXx }, PREFIX_DATA },
7723
  },
7724
  {
7725
    /* VEX_W_0F380D  */
7726
    { "vpermilpd",  { XM, Vex, EXx }, PREFIX_DATA },
7727
  },
7728
  {
7729
    /* VEX_W_0F380E  */
7730
    { "vtestps",  { XM, EXx }, PREFIX_DATA },
7731
  },
7732
  {
7733
    /* VEX_W_0F380F  */
7734
    { "vtestpd",  { XM, EXx }, PREFIX_DATA },
7735
  },
7736
  {
7737
    /* VEX_W_0F3813 */
7738
    { "vcvtph2ps", { XM, EXxmmq }, PREFIX_DATA },
7739
  },
7740
  {
7741
    /* VEX_W_0F3816_L_1  */
7742
    { "vpermps",  { XM, Vex, EXx }, PREFIX_DATA },
7743
  },
7744
  {
7745
    /* VEX_W_0F3818 */
7746
    { "%XEvbroadcastss",  { XM, EXd }, PREFIX_DATA },
7747
  },
7748
  {
7749
    /* VEX_W_0F3819_L_1 */
7750
    { "vbroadcastsd", { XM, EXq }, PREFIX_DATA },
7751
  },
7752
  {
7753
    /* VEX_W_0F381A_L_1 */
7754
    { "vbroadcastf128", { XM, Mxmm }, PREFIX_DATA },
7755
  },
7756
  {
7757
    /* VEX_W_0F382C */
7758
    { "vmaskmovps", { XM, Vex, Mx }, PREFIX_DATA },
7759
  },
7760
  {
7761
    /* VEX_W_0F382D */
7762
    { "vmaskmovpd", { XM, Vex, Mx }, PREFIX_DATA },
7763
  },
7764
  {
7765
    /* VEX_W_0F382E */
7766
    { "vmaskmovps", { Mx, Vex, XM }, PREFIX_DATA },
7767
  },
7768
  {
7769
    /* VEX_W_0F382F */
7770
    { "vmaskmovpd", { Mx, Vex, XM }, PREFIX_DATA },
7771
  },
7772
  {
7773
    /* VEX_W_0F3836  */
7774
    { "vpermd",   { XM, Vex, EXx }, PREFIX_DATA },
7775
  },
7776
  {
7777
    /* VEX_W_0F3846 */
7778
    { "vpsravd",  { XM, Vex, EXx }, PREFIX_DATA },
7779
  },
7780
  {
7781
    /* VEX_W_0F3849_X86_64_L_0 */
7782
    { MOD_TABLE (MOD_VEX_0F3849_X86_64_L_0_W_0) },
7783
  },
7784
  {
7785
    /* VEX_W_0F384B_X86_64_L_0 */
7786
    { PREFIX_TABLE (PREFIX_VEX_0F384B_X86_64_L_0_W_0) },
7787
  },
7788
  {
7789
    /* VEX_W_0F3850 */
7790
    { PREFIX_TABLE (PREFIX_VEX_0F3850_W_0) },
7791
  },
7792
  {
7793
    /* VEX_W_0F3851 */
7794
    { PREFIX_TABLE (PREFIX_VEX_0F3851_W_0) },
7795
  },
7796
  {
7797
    /* VEX_W_0F3852 */
7798
    { "%XVvpdpwssd",  { XM, Vex, EXx }, PREFIX_DATA },
7799
  },
7800
  {
7801
    /* VEX_W_0F3853 */
7802
    { "%XVvpdpwssds", { XM, Vex, EXx }, PREFIX_DATA },
7803
  },
7804
  {
7805
    /* VEX_W_0F3858 */
7806
    { "%XEvpbroadcastd", { XM, EXd }, PREFIX_DATA },
7807
  },
7808
  {
7809
    /* VEX_W_0F3859 */
7810
    { "vpbroadcastq", { XM, EXq }, PREFIX_DATA },
7811
  },
7812
  {
7813
    /* VEX_W_0F385A_L_0 */
7814
    { "vbroadcasti128", { XM, Mxmm }, PREFIX_DATA },
7815
  },
7816
  {
7817
    /* VEX_W_0F385C_X86_64_L_0 */
7818
    { PREFIX_TABLE (PREFIX_VEX_0F385C_X86_64_L_0_W_0) },
7819
  },
7820
  {
7821
    /* VEX_W_0F385E_X86_64_L_0 */
7822
    { PREFIX_TABLE (PREFIX_VEX_0F385E_X86_64_L_0_W_0) },
7823
  },
7824
  {
7825
    /* VEX_W_0F386C_X86_64_L_0 */
7826
    { PREFIX_TABLE (PREFIX_VEX_0F386C_X86_64_L_0_W_0) },
7827
  },
7828
  {
7829
    /* VEX_W_0F3872_P_1 */
7830
    { "%XVvcvtneps2bf16%XY", { XMM, EXx }, 0 },
7831
  },
7832
  {
7833
    /* VEX_W_0F3878 */
7834
    { "%XEvpbroadcastb",  { XM, EXb }, PREFIX_DATA },
7835
  },
7836
  {
7837
    /* VEX_W_0F3879 */
7838
    { "%XEvpbroadcastw",  { XM, EXw }, PREFIX_DATA },
7839
  },
7840
  {
7841
    /* VEX_W_0F38B0 */
7842
    { PREFIX_TABLE (PREFIX_VEX_0F38B0_W_0) },
7843
  },
7844
  {
7845
    /* VEX_W_0F38B1 */
7846
    { PREFIX_TABLE (PREFIX_VEX_0F38B1_W_0) },
7847
  },
7848
  {
7849
    /* VEX_W_0F38B4 */
7850
    { Bad_Opcode },
7851
    { "%XVvpmadd52luq", { XM, Vex, EXx }, PREFIX_DATA },
7852
  },
7853
  {
7854
    /* VEX_W_0F38B5 */
7855
    { Bad_Opcode },
7856
    { "%XVvpmadd52huq", { XM, Vex, EXx }, PREFIX_DATA },
7857
  },
7858
  {
7859
    /* VEX_W_0F38CB_P_3 */
7860
    { VEX_LEN_TABLE (VEX_LEN_0F38CB_P_3_W_0) },
7861
  },
7862
  {
7863
    /* VEX_W_0F38CC_P_3 */
7864
    { VEX_LEN_TABLE (VEX_LEN_0F38CC_P_3_W_0) },
7865
  },
7866
  {
7867
    /* VEX_W_0F38CD_P_3 */
7868
    { VEX_LEN_TABLE (VEX_LEN_0F38CD_P_3_W_0) },
7869
  },
7870
  {
7871
    /* VEX_W_0F38CF */
7872
    { "%XEvgf2p8mulb", { XM, Vex, EXx }, PREFIX_DATA },
7873
  },
7874
  {
7875
    /* VEX_W_0F38D2 */
7876
    { PREFIX_TABLE (PREFIX_VEX_0F38D2_W_0) },
7877
  },
7878
  {
7879
    /* VEX_W_0F38D3 */
7880
    { PREFIX_TABLE (PREFIX_VEX_0F38D3_W_0) },
7881
  },
7882
  {
7883
    /* VEX_W_0F38DA */
7884
    { PREFIX_TABLE (PREFIX_VEX_0F38DA_W_0) },
7885
  },
7886
  {
7887
    /* VEX_W_0F3A00_L_1 */
7888
    { Bad_Opcode },
7889
    { "%XEvpermq",    { XM, EXx, Ib }, PREFIX_DATA },
7890
  },
7891
  {
7892
    /* VEX_W_0F3A01_L_1 */
7893
    { Bad_Opcode },
7894
    { "%XEvpermpd", { XM, EXx, Ib }, PREFIX_DATA },
7895
  },
7896
  {
7897
    /* VEX_W_0F3A02 */
7898
    { "vpblendd", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7899
  },
7900
  {
7901
    /* VEX_W_0F3A04 */
7902
    { "%XEvpermilps", { XM, EXx, Ib }, PREFIX_DATA },
7903
  },
7904
  {
7905
    /* VEX_W_0F3A05 */
7906
    { "vpermilpd",  { XM, EXx, Ib }, PREFIX_DATA },
7907
  },
7908
  {
7909
    /* VEX_W_0F3A06_L_1 */
7910
    { "vperm2f128", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7911
  },
7912
  {
7913
    /* VEX_W_0F3A18_L_1 */
7914
    { "vinsertf128",  { XM, Vex, EXxmm, Ib }, PREFIX_DATA },
7915
  },
7916
  {
7917
    /* VEX_W_0F3A19_L_1 */
7918
    { "vextractf128", { EXxmm, XM, Ib }, PREFIX_DATA },
7919
  },
7920
  {
7921
    /* VEX_W_0F3A1D */
7922
    { "%XEvcvtps2ph", { EXxmmq, XM, EXxEVexS, Ib }, PREFIX_DATA },
7923
  },
7924
  {
7925
    /* VEX_W_0F3A38_L_1 */
7926
    { "vinserti128",  { XM, Vex, EXxmm, Ib }, PREFIX_DATA },
7927
  },
7928
  {
7929
    /* VEX_W_0F3A39_L_1 */
7930
    { "vextracti128", { EXxmm, XM, Ib }, PREFIX_DATA },
7931
  },
7932
  {
7933
    /* VEX_W_0F3A46_L_1 */
7934
    { "vperm2i128", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7935
  },
7936
  {
7937
    /* VEX_W_0F3A4A */
7938
    { "vblendvps",  { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7939
  },
7940
  {
7941
    /* VEX_W_0F3A4B */
7942
    { "vblendvpd",  { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7943
  },
7944
  {
7945
    /* VEX_W_0F3A4C */
7946
    { "vpblendvb",  { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7947
  },
7948
  {
7949
    /* VEX_W_0F3ACE */
7950
    { Bad_Opcode },
7951
    { "%XEvgf2p8affineqb", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7952
  },
7953
  {
7954
    /* VEX_W_0F3ACF */
7955
    { Bad_Opcode },
7956
    { "%XEvgf2p8affineinvqb",  { XM, Vex, EXx, Ib }, PREFIX_DATA },
7957
  },
7958
  {
7959
    /* VEX_W_0F3ADE */
7960
    { VEX_LEN_TABLE (VEX_LEN_0F3ADE_W_0) },
7961
  },
7962
  {
7963
    /* VEX_W_MAP7_F8_L_0 */
7964
    { REG_TABLE (REG_VEX_MAP7_F8_L_0_W_0) },
7965
  },
7966
  /* VEX_W_XOP_08_85_L_0 */
7967
  {
7968
    { "vpmacssww",  { XM, Vex, EXx, XMVexI4 }, 0 },
7969
  },
7970
  /* VEX_W_XOP_08_86_L_0 */
7971
  {
7972
    { "vpmacsswd",  { XM, Vex, EXx, XMVexI4 }, 0 },
7973
  },
7974
  /* VEX_W_XOP_08_87_L_0 */
7975
  {
7976
    { "vpmacssdql",   { XM, Vex, EXx, XMVexI4 }, 0 },
7977
  },
7978
  /* VEX_W_XOP_08_8E_L_0 */
7979
  {
7980
    { "vpmacssdd",  { XM, Vex, EXx, XMVexI4 }, 0 },
7981
  },
7982
  /* VEX_W_XOP_08_8F_L_0 */
7983
  {
7984
    { "vpmacssdqh",   { XM, Vex, EXx, XMVexI4 }, 0 },
7985
  },
7986
  /* VEX_W_XOP_08_95_L_0 */
7987
  {
7988
    { "vpmacsww",   { XM, Vex, EXx, XMVexI4 }, 0 },
7989
  },
7990
  /* VEX_W_XOP_08_96_L_0 */
7991
  {
7992
    { "vpmacswd",   { XM, Vex, EXx, XMVexI4 }, 0 },
7993
  },
7994
  /* VEX_W_XOP_08_97_L_0 */
7995
  {
7996
    { "vpmacsdql",  { XM, Vex, EXx, XMVexI4 }, 0 },
7997
  },
7998
  /* VEX_W_XOP_08_9E_L_0 */
7999
  {
8000
    { "vpmacsdd",   { XM, Vex, EXx, XMVexI4 }, 0 },
8001
  },
8002
  /* VEX_W_XOP_08_9F_L_0 */
8003
  {
8004
    { "vpmacsdqh",  { XM, Vex, EXx, XMVexI4 }, 0 },
8005
  },
8006
  /* VEX_W_XOP_08_A6_L_0 */
8007
  {
8008
    { "vpmadcsswd",   { XM, Vex, EXx, XMVexI4 }, 0 },
8009
  },
8010
  /* VEX_W_XOP_08_B6_L_0 */
8011
  {
8012
    { "vpmadcswd",  { XM, Vex, EXx, XMVexI4 }, 0 },
8013
  },
8014
  /* VEX_W_XOP_08_C0_L_0 */
8015
  {
8016
    { "vprotb",   { XM, EXx, Ib }, 0 },
8017
  },
8018
  /* VEX_W_XOP_08_C1_L_0 */
8019
  {
8020
    { "vprotw",   { XM, EXx, Ib }, 0 },
8021
  },
8022
  /* VEX_W_XOP_08_C2_L_0 */
8023
  {
8024
    { "vprotd",   { XM, EXx, Ib }, 0 },
8025
  },
8026
  /* VEX_W_XOP_08_C3_L_0 */
8027
  {
8028
    { "vprotq",   { XM, EXx, Ib }, 0 },
8029
  },
8030
  /* VEX_W_XOP_08_CC_L_0 */
8031
  {
8032
     { "vpcomb",  { XM, Vex, EXx, VPCOM }, 0 },
8033
  },
8034
  /* VEX_W_XOP_08_CD_L_0 */
8035
  {
8036
     { "vpcomw",  { XM, Vex, EXx, VPCOM }, 0 },
8037
  },
8038
  /* VEX_W_XOP_08_CE_L_0 */
8039
  {
8040
     { "vpcomd",  { XM, Vex, EXx, VPCOM }, 0 },
8041
  },
8042
  /* VEX_W_XOP_08_CF_L_0 */
8043
  {
8044
     { "vpcomq",  { XM, Vex, EXx, VPCOM }, 0 },
8045
  },
8046
  /* VEX_W_XOP_08_EC_L_0 */
8047
  {
8048
     { "vpcomub", { XM, Vex, EXx, VPCOM }, 0 },
8049
  },
8050
  /* VEX_W_XOP_08_ED_L_0 */
8051
  {
8052
     { "vpcomuw", { XM, Vex, EXx, VPCOM }, 0 },
8053
  },
8054
  /* VEX_W_XOP_08_EE_L_0 */
8055
  {
8056
     { "vpcomud", { XM, Vex, EXx, VPCOM }, 0 },
8057
  },
8058
  /* VEX_W_XOP_08_EF_L_0 */
8059
  {
8060
     { "vpcomuq", { XM, Vex, EXx, VPCOM }, 0 },
8061
  },
8062
  /* VEX_W_XOP_09_80 */
8063
  {
8064
    { "vfrczps",  { XM, EXx }, 0 },
8065
  },
8066
  /* VEX_W_XOP_09_81 */
8067
  {
8068
    { "vfrczpd",  { XM, EXx }, 0 },
8069
  },
8070
  /* VEX_W_XOP_09_82 */
8071
  {
8072
    { VEX_LEN_TABLE (VEX_LEN_XOP_09_82_W_0) },
8073
  },
8074
  /* VEX_W_XOP_09_83 */
8075
  {
8076
    { VEX_LEN_TABLE (VEX_LEN_XOP_09_83_W_0) },
8077
  },
8078
  /* VEX_W_XOP_09_C1_L_0 */
8079
  {
8080
    { "vphaddbw", { XM, EXxmm }, 0 },
8081
  },
8082
  /* VEX_W_XOP_09_C2_L_0 */
8083
  {
8084
    { "vphaddbd", { XM, EXxmm }, 0 },
8085
  },
8086
  /* VEX_W_XOP_09_C3_L_0 */
8087
  {
8088
    { "vphaddbq", { XM, EXxmm }, 0 },
8089
  },
8090
  /* VEX_W_XOP_09_C6_L_0 */
8091
  {
8092
    { "vphaddwd", { XM, EXxmm }, 0 },
8093
  },
8094
  /* VEX_W_XOP_09_C7_L_0 */
8095
  {
8096
    { "vphaddwq", { XM, EXxmm }, 0 },
8097
  },
8098
  /* VEX_W_XOP_09_CB_L_0 */
8099
  {
8100
    { "vphadddq", { XM, EXxmm }, 0 },
8101
  },
8102
  /* VEX_W_XOP_09_D1_L_0 */
8103
  {
8104
    { "vphaddubw",  { XM, EXxmm }, 0 },
8105
  },
8106
  /* VEX_W_XOP_09_D2_L_0 */
8107
  {
8108
    { "vphaddubd",  { XM, EXxmm }, 0 },
8109
  },
8110
  /* VEX_W_XOP_09_D3_L_0 */
8111
  {
8112
    { "vphaddubq",  { XM, EXxmm }, 0 },
8113
  },
8114
  /* VEX_W_XOP_09_D6_L_0 */
8115
  {
8116
    { "vphadduwd",  { XM, EXxmm }, 0 },
8117
  },
8118
  /* VEX_W_XOP_09_D7_L_0 */
8119
  {
8120
    { "vphadduwq",  { XM, EXxmm }, 0 },
8121
  },
8122
  /* VEX_W_XOP_09_DB_L_0 */
8123
  {
8124
    { "vphaddudq",  { XM, EXxmm }, 0 },
8125
  },
8126
  /* VEX_W_XOP_09_E1_L_0 */
8127
  {
8128
    { "vphsubbw", { XM, EXxmm }, 0 },
8129
  },
8130
  /* VEX_W_XOP_09_E2_L_0 */
8131
  {
8132
    { "vphsubwd", { XM, EXxmm }, 0 },
8133
  },
8134
  /* VEX_W_XOP_09_E3_L_0 */
8135
  {
8136
    { "vphsubdq", { XM, EXxmm }, 0 },
8137
  },
8138
8139
#include "i386-dis-evex-w.h"
8140
};
8141
8142
static const struct dis386 mod_table[][2] = {
8143
  {
8144
    /* MOD_62_32BIT */
8145
    { "bound{S|}",  { Gv, Ma }, 0 },
8146
    { EVEX_TABLE () },
8147
  },
8148
  {
8149
    /* MOD_C4_32BIT */
8150
    { "lesS",   { Gv, Mp }, 0 },
8151
    { VEX_C4_TABLE () },
8152
  },
8153
  {
8154
    /* MOD_C5_32BIT */
8155
    { "ldsS",   { Gv, Mp }, 0 },
8156
    { VEX_C5_TABLE () },
8157
  },
8158
  {
8159
    /* MOD_0F01_REG_0 */
8160
    { X86_64_TABLE (X86_64_0F01_REG_0) },
8161
    { RM_TABLE (RM_0F01_REG_0) },
8162
  },
8163
  {
8164
    /* MOD_0F01_REG_1 */
8165
    { X86_64_TABLE (X86_64_0F01_REG_1) },
8166
    { RM_TABLE (RM_0F01_REG_1) },
8167
  },
8168
  {
8169
    /* MOD_0F01_REG_2 */
8170
    { X86_64_TABLE (X86_64_0F01_REG_2) },
8171
    { RM_TABLE (RM_0F01_REG_2) },
8172
  },
8173
  {
8174
    /* MOD_0F01_REG_3 */
8175
    { X86_64_TABLE (X86_64_0F01_REG_3) },
8176
    { RM_TABLE (RM_0F01_REG_3) },
8177
  },
8178
  {
8179
    /* MOD_0F01_REG_5 */
8180
    { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0) },
8181
    { RM_TABLE (RM_0F01_REG_5_MOD_3) },
8182
  },
8183
  {
8184
    /* MOD_0F01_REG_7 */
8185
    { "invlpg",   { Mb }, 0 },
8186
    { RM_TABLE (RM_0F01_REG_7_MOD_3) },
8187
  },
8188
  {
8189
    /* MOD_0F12_PREFIX_0 */
8190
    { "%XEVmovlpYX",  { XM, Vex, EXq }, 0 },
8191
    { "%XEVmovhlpY%XS", { XM, Vex, EXq }, 0 },
8192
  },
8193
  {
8194
    /* MOD_0F16_PREFIX_0 */
8195
    { "%XEVmovhpYX",  { XM, Vex, EXq }, 0 },
8196
    { "%XEVmovlhpY%XS", { XM, Vex, EXq }, 0 },
8197
  },
8198
  {
8199
    /* MOD_0F18_REG_0 */
8200
    { "prefetchnta",  { Mb }, 0 },
8201
    { "nopQ",   { Ev }, 0 },
8202
  },
8203
  {
8204
    /* MOD_0F18_REG_1 */
8205
    { "prefetcht0", { Mb }, 0 },
8206
    { "nopQ",   { Ev }, 0 },
8207
  },
8208
  {
8209
    /* MOD_0F18_REG_2 */
8210
    { "prefetcht1", { Mb }, 0 },
8211
    { "nopQ",   { Ev }, 0 },
8212
  },
8213
  {
8214
    /* MOD_0F18_REG_3 */
8215
    { "prefetcht2", { Mb }, 0 },
8216
    { "nopQ",   { Ev }, 0 },
8217
  },
8218
  {
8219
    /* MOD_0F18_REG_6 */
8220
    { X86_64_TABLE (X86_64_0F18_REG_6_MOD_0) },
8221
    { "nopQ",   { Ev }, 0 },
8222
  },
8223
  {
8224
    /* MOD_0F18_REG_7 */
8225
    { X86_64_TABLE (X86_64_0F18_REG_7_MOD_0) },
8226
    { "nopQ",   { Ev }, 0 },
8227
  },
8228
  {
8229
    /* MOD_0F1A_PREFIX_0 */
8230
    { "bndldx",   { Gbnd, Mv_bnd }, 0 },
8231
    { "nopQ",   { Ev }, 0 },
8232
  },
8233
  {
8234
    /* MOD_0F1B_PREFIX_0 */
8235
    { "bndstx",   { Mv_bnd, Gbnd }, 0 },
8236
    { "nopQ",   { Ev }, 0 },
8237
  },
8238
  {
8239
    /* MOD_0F1B_PREFIX_1 */
8240
    { "bndmk",    { Gbnd, Mv_bnd }, 0 },
8241
    { "nopQ",   { Ev }, PREFIX_IGNORED },
8242
  },
8243
  {
8244
    /* MOD_0F1C_PREFIX_0 */
8245
    { REG_TABLE (REG_0F1C_P_0_MOD_0) },
8246
    { "nopQ",   { Ev }, 0 },
8247
  },
8248
  {
8249
    /* MOD_0F1E_PREFIX_1 */
8250
    { "nopQ",   { Ev }, PREFIX_IGNORED },
8251
    { REG_TABLE (REG_0F1E_P_1_MOD_3) },
8252
  },
8253
  {
8254
    /* MOD_0FAE_REG_0 */
8255
    { "fxsave",   { FXSAVE }, 0 },
8256
    { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3) },
8257
  },
8258
  {
8259
    /* MOD_0FAE_REG_1 */
8260
    { "fxrstor",  { FXSAVE }, 0 },
8261
    { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3) },
8262
  },
8263
  {
8264
    /* MOD_0FAE_REG_2 */
8265
    { "ldmxcsr",  { Md }, 0 },
8266
    { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3) },
8267
  },
8268
  {
8269
    /* MOD_0FAE_REG_3 */
8270
    { "stmxcsr",  { Md }, 0 },
8271
    { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3) },
8272
  },
8273
  {
8274
    /* MOD_0FAE_REG_4 */
8275
    { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0) },
8276
    { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3) },
8277
  },
8278
  {
8279
    /* MOD_0FAE_REG_5 */
8280
    { "xrstor",   { FXSAVE }, PREFIX_OPCODE | PREFIX_REX2_ILLEGAL },
8281
    { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3) },
8282
  },
8283
  {
8284
    /* MOD_0FAE_REG_6 */
8285
    { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0) },
8286
    { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3) },
8287
  },
8288
  {
8289
    /* MOD_0FAE_REG_7 */
8290
    { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0) },
8291
    { RM_TABLE (RM_0FAE_REG_7_MOD_3) },
8292
  },
8293
  {
8294
    /* MOD_0FC7_REG_6 */
8295
    { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0) },
8296
    { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3) }
8297
  },
8298
  {
8299
    /* MOD_0FC7_REG_7 */
8300
    { "vmptrst",  { Mq }, 0 },
8301
    { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3) }
8302
  },
8303
  {
8304
    /* MOD_0F38DC_PREFIX_1 */
8305
    { "aesenc128kl",    { XM, M }, 0 },
8306
    { "loadiwkey",      { XM, EXx }, 0 },
8307
  },
8308
  /* MOD_0F38F8 */
8309
  {
8310
    { PREFIX_TABLE (PREFIX_0F38F8_M_0) },
8311
    { X86_64_TABLE (X86_64_0F38F8_M_1) },
8312
  },
8313
  {
8314
    /* MOD_VEX_0F3849_X86_64_L_0_W_0 */
8315
    { PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_0) },
8316
    { PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_1) },
8317
  },
8318
8319
#include "i386-dis-evex-mod.h"
8320
};
8321
8322
static const struct dis386 rm_table[][8] = {
8323
  {
8324
    /* RM_C6_REG_7 */
8325
    { "xabort",   { Skip_MODRM, Ib }, 0 },
8326
  },
8327
  {
8328
    /* RM_C7_REG_7 */
8329
    { "xbeginT",  { Skip_MODRM, Jdqw }, 0 },
8330
  },
8331
  {
8332
    /* RM_0F01_REG_0 */
8333
    { "enclv",    { Skip_MODRM }, 0 },
8334
    { "vmcall",   { Skip_MODRM }, 0 },
8335
    { "vmlaunch", { Skip_MODRM }, 0 },
8336
    { "vmresume", { Skip_MODRM }, 0 },
8337
    { "vmxoff",   { Skip_MODRM }, 0 },
8338
    { "pconfig",  { Skip_MODRM }, 0 },
8339
    { PREFIX_TABLE (PREFIX_0F01_REG_0_MOD_3_RM_6) },
8340
    { PREFIX_TABLE (PREFIX_0F01_REG_0_MOD_3_RM_7) },
8341
  },
8342
  {
8343
    /* RM_0F01_REG_1 */
8344
    { "monitor",  { { OP_Monitor, 0 } }, 0 },
8345
    { "mwait",    { { OP_Mwait, 0 } }, 0 },
8346
    { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_2) },
8347
    { "stac",   { Skip_MODRM }, 0 },
8348
    { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_4) },
8349
    { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_5) },
8350
    { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_6) },
8351
    { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_7) },
8352
  },
8353
  {
8354
    /* RM_0F01_REG_2 */
8355
    { "xgetbv",   { Skip_MODRM }, 0 },
8356
    { "xsetbv",   { Skip_MODRM }, 0 },
8357
    { Bad_Opcode },
8358
    { Bad_Opcode },
8359
    { "vmfunc",   { Skip_MODRM }, 0 },
8360
    { "xend",   { Skip_MODRM }, 0 },
8361
    { "xtest",    { Skip_MODRM }, 0 },
8362
    { "enclu",    { Skip_MODRM }, 0 },
8363
  },
8364
  {
8365
    /* RM_0F01_REG_3 */
8366
    { "vmrun",    { Skip_MODRM }, 0 },
8367
    { PREFIX_TABLE (PREFIX_0F01_REG_3_RM_1) },
8368
    { "vmload",   { Skip_MODRM }, 0 },
8369
    { "vmsave",   { Skip_MODRM }, 0 },
8370
    { "stgi",   { Skip_MODRM }, 0 },
8371
    { "clgi",   { Skip_MODRM }, 0 },
8372
    { "skinit",   { Skip_MODRM }, 0 },
8373
    { "invlpga",  { Skip_MODRM }, 0 },
8374
  },
8375
  {
8376
    /* RM_0F01_REG_5_MOD_3 */
8377
    { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0) },
8378
    { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_1) },
8379
    { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2) },
8380
    { Bad_Opcode },
8381
    { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_4) },
8382
    { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_5) },
8383
    { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_6) },
8384
    { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_7) },
8385
  },
8386
  {
8387
    /* RM_0F01_REG_7_MOD_3 */
8388
    { "swapgs",   { Skip_MODRM }, 0  },
8389
    { "rdtscp",   { Skip_MODRM }, 0  },
8390
    { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2) },
8391
    { "mwaitx",   { { OP_Mwait, eBX_reg } }, PREFIX_OPCODE },
8392
    { "clzero",   { Skip_MODRM }, 0  },
8393
    { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_5) },
8394
    { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_6) },
8395
    { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_7) },
8396
  },
8397
  {
8398
    /* RM_0F1E_P_1_MOD_3_REG_7 */
8399
    { "nopQ",   { Ev }, PREFIX_IGNORED },
8400
    { "nopQ",   { Ev }, PREFIX_IGNORED },
8401
    { "endbr64",  { Skip_MODRM }, 0 },
8402
    { "endbr32",  { Skip_MODRM }, 0 },
8403
    { "nopQ",   { Ev }, PREFIX_IGNORED },
8404
    { "nopQ",   { Ev }, PREFIX_IGNORED },
8405
    { "nopQ",   { Ev }, PREFIX_IGNORED },
8406
    { "nopQ",   { Ev }, PREFIX_IGNORED },
8407
  },
8408
  {
8409
    /* RM_0FAE_REG_6_MOD_3 */
8410
    { "mfence",   { Skip_MODRM }, 0 },
8411
  },
8412
  {
8413
    /* RM_0FAE_REG_7_MOD_3 */
8414
    { "sfence",   { Skip_MODRM }, 0 },
8415
  },
8416
  {
8417
    /* RM_0F3A0F_P_1_R_0 */
8418
    { "hreset",   { Skip_MODRM, Ib }, 0 },
8419
  },
8420
  {
8421
    /* RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0_R_0 */
8422
    { "tilerelease",  { Skip_MODRM }, 0 },
8423
  },
8424
  {
8425
    /* RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_3 */
8426
    { "tilezero", { TMM, Skip_MODRM }, 0 },
8427
  },
8428
};
8429
8430
0
#define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
8431
8432
/* The values used here must be non-zero, fit in 'unsigned char', and not be
8433
   in conflict with actual prefix opcodes.  */
8434
1.76k
#define REP_PREFIX  0x01
8435
1.70k
#define XACQUIRE_PREFIX 0x02
8436
3.02k
#define XRELEASE_PREFIX 0x03
8437
5.00k
#define BND_PREFIX  0x04
8438
1.37k
#define NOTRACK_PREFIX  0x05
8439
8440
static enum {
8441
  ckp_okay,
8442
  ckp_bogus,
8443
  ckp_fetch_error,
8444
}
8445
ckprefix (instr_info *ins)
8446
19.1M
{
8447
19.1M
  int i, length;
8448
19.1M
  uint8_t newrex;
8449
8450
19.1M
  i = 0;
8451
19.1M
  length = 0;
8452
  /* The maximum instruction length is 15bytes.  */
8453
21.0M
  while (length < MAX_CODE_LENGTH - 1)
8454
21.0M
    {
8455
21.0M
      if (!fetch_code (ins->info, ins->codep + 1))
8456
2.04k
  return ckp_fetch_error;
8457
21.0M
      newrex = 0;
8458
21.0M
      switch (*ins->codep)
8459
21.0M
  {
8460
  /* REX prefixes family.  */
8461
60.5k
  case 0x40:
8462
191k
  case 0x41:
8463
234k
  case 0x42:
8464
297k
  case 0x43:
8465
399k
  case 0x44:
8466
505k
  case 0x45:
8467
557k
  case 0x46:
8468
610k
  case 0x47:
8469
890k
  case 0x48:
8470
1.00M
  case 0x49:
8471
1.04M
  case 0x4a:
8472
1.07M
  case 0x4b:
8473
1.40M
  case 0x4c:
8474
1.47M
  case 0x4d:
8475
1.55M
  case 0x4e:
8476
1.61M
  case 0x4f:
8477
1.61M
    if (ins->address_mode == mode_64bit)
8478
1.23M
      newrex = *ins->codep;
8479
378k
    else
8480
378k
      return ckp_okay;
8481
1.23M
    ins->last_rex_prefix = i;
8482
1.23M
    break;
8483
  /* REX2 must be the last prefix. */
8484
27.2k
  case REX2_OPCODE:
8485
27.2k
    if (ins->address_mode == mode_64bit)
8486
23.2k
      {
8487
23.2k
        if (ins->last_rex_prefix >= 0)
8488
1.00k
    return ckp_bogus;
8489
8490
22.2k
        ins->codep++;
8491
22.2k
        if (!fetch_code (ins->info, ins->codep + 1))
8492
11
    return ckp_fetch_error;
8493
22.1k
        ins->rex2_payload = *ins->codep;
8494
22.1k
        ins->rex2 = ins->rex2_payload >> 4;
8495
22.1k
        ins->rex = (ins->rex2_payload & 0xf) | REX_OPCODE;
8496
22.1k
        ins->codep++;
8497
22.1k
        ins->last_rex2_prefix = i;
8498
22.1k
        ins->all_prefixes[i] = REX2_OPCODE;
8499
22.1k
      }
8500
26.2k
    return ckp_okay;
8501
35.5k
  case 0xf3:
8502
35.5k
    ins->prefixes |= PREFIX_REPZ;
8503
35.5k
    ins->last_repz_prefix = i;
8504
35.5k
    break;
8505
42.2k
  case 0xf2:
8506
42.2k
    ins->prefixes |= PREFIX_REPNZ;
8507
42.2k
    ins->last_repnz_prefix = i;
8508
42.2k
    break;
8509
39.1k
  case 0xf0:
8510
39.1k
    ins->prefixes |= PREFIX_LOCK;
8511
39.1k
    ins->last_lock_prefix = i;
8512
39.1k
    break;
8513
102k
  case 0x2e:
8514
102k
    ins->prefixes |= PREFIX_CS;
8515
102k
    ins->last_seg_prefix = i;
8516
102k
    if (ins->address_mode != mode_64bit)
8517
21.8k
      ins->active_seg_prefix = PREFIX_CS;
8518
102k
    break;
8519
59.2k
  case 0x36:
8520
59.2k
    ins->prefixes |= PREFIX_SS;
8521
59.2k
    ins->last_seg_prefix = i;
8522
59.2k
    if (ins->address_mode != mode_64bit)
8523
9.65k
      ins->active_seg_prefix = PREFIX_SS;
8524
59.2k
    break;
8525
43.6k
  case 0x3e:
8526
43.6k
    ins->prefixes |= PREFIX_DS;
8527
43.6k
    ins->last_seg_prefix = i;
8528
43.6k
    if (ins->address_mode != mode_64bit)
8529
12.7k
      ins->active_seg_prefix = PREFIX_DS;
8530
43.6k
    break;
8531
35.7k
  case 0x26:
8532
35.7k
    ins->prefixes |= PREFIX_ES;
8533
35.7k
    ins->last_seg_prefix = i;
8534
35.7k
    if (ins->address_mode != mode_64bit)
8535
11.3k
      ins->active_seg_prefix = PREFIX_ES;
8536
35.7k
    break;
8537
114k
  case 0x64:
8538
114k
    ins->prefixes |= PREFIX_FS;
8539
114k
    ins->last_seg_prefix = i;
8540
114k
    ins->active_seg_prefix = PREFIX_FS;
8541
114k
    break;
8542
144k
  case 0x65:
8543
144k
    ins->prefixes |= PREFIX_GS;
8544
144k
    ins->last_seg_prefix = i;
8545
144k
    ins->active_seg_prefix = PREFIX_GS;
8546
144k
    break;
8547
127k
  case 0x66:
8548
127k
    ins->prefixes |= PREFIX_DATA;
8549
127k
    ins->last_data_prefix = i;
8550
127k
    break;
8551
92.3k
  case 0x67:
8552
92.3k
    ins->prefixes |= PREFIX_ADDR;
8553
92.3k
    ins->last_addr_prefix = i;
8554
92.3k
    break;
8555
33.7k
  case FWAIT_OPCODE:
8556
    /* fwait is really an instruction.  If there are prefixes
8557
       before the fwait, they belong to the fwait, *not* to the
8558
       following instruction.  */
8559
33.7k
    ins->fwait_prefix = i;
8560
33.7k
    if (ins->prefixes || ins->rex)
8561
7.69k
      {
8562
7.69k
        ins->prefixes |= PREFIX_FWAIT;
8563
7.69k
        ins->codep++;
8564
        /* This ensures that the previous REX prefixes are noticed
8565
     as unused prefixes, as in the return case below.  */
8566
7.69k
        return ins->rex ? ckp_bogus : ckp_okay;
8567
7.69k
      }
8568
26.1k
    ins->prefixes = PREFIX_FWAIT;
8569
26.1k
    break;
8570
18.5M
  default:
8571
18.5M
    return ckp_okay;
8572
21.0M
  }
8573
      /* Rex is ignored when followed by another prefix.  */
8574
2.09M
      if (ins->rex)
8575
201k
  return ckp_bogus;
8576
1.89M
      if (*ins->codep != FWAIT_OPCODE)
8577
1.86M
  ins->all_prefixes[i++] = *ins->codep;
8578
1.89M
      ins->rex = newrex;
8579
1.89M
      ins->codep++;
8580
1.89M
      length++;
8581
1.89M
    }
8582
5.08k
  return ckp_bogus;
8583
19.1M
}
8584
8585
/* Return the name of the prefix byte PREF, or NULL if PREF is not a
8586
   prefix byte.  */
8587
8588
static const char *
8589
prefix_name (enum address_mode mode, uint8_t pref, int sizeflag)
8590
1.09M
{
8591
1.09M
  static const char *rexes [16] =
8592
1.09M
    {
8593
1.09M
      "rex",    /* 0x40 */
8594
1.09M
      "rex.B",    /* 0x41 */
8595
1.09M
      "rex.X",    /* 0x42 */
8596
1.09M
      "rex.XB",   /* 0x43 */
8597
1.09M
      "rex.R",    /* 0x44 */
8598
1.09M
      "rex.RB",   /* 0x45 */
8599
1.09M
      "rex.RX",   /* 0x46 */
8600
1.09M
      "rex.RXB",  /* 0x47 */
8601
1.09M
      "rex.W",    /* 0x48 */
8602
1.09M
      "rex.WB",   /* 0x49 */
8603
1.09M
      "rex.WX",   /* 0x4a */
8604
1.09M
      "rex.WXB",  /* 0x4b */
8605
1.09M
      "rex.WR",   /* 0x4c */
8606
1.09M
      "rex.WRB",  /* 0x4d */
8607
1.09M
      "rex.WRX",  /* 0x4e */
8608
1.09M
      "rex.WRXB", /* 0x4f */
8609
1.09M
    };
8610
8611
1.09M
  switch (pref)
8612
1.09M
    {
8613
    /* REX prefixes family.  */
8614
36.4k
    case 0x40:
8615
56.6k
    case 0x41:
8616
79.8k
    case 0x42:
8617
116k
    case 0x43:
8618
153k
    case 0x44:
8619
197k
    case 0x45:
8620
227k
    case 0x46:
8621
258k
    case 0x47:
8622
284k
    case 0x48:
8623
323k
    case 0x49:
8624
348k
    case 0x4a:
8625
367k
    case 0x4b:
8626
410k
    case 0x4c:
8627
445k
    case 0x4d:
8628
495k
    case 0x4e:
8629
532k
    case 0x4f:
8630
532k
      return rexes [pref - 0x40];
8631
28.4k
    case 0xf3:
8632
28.4k
      return "repz";
8633
34.4k
    case 0xf2:
8634
34.4k
      return "repnz";
8635
36.3k
    case 0xf0:
8636
36.3k
      return "lock";
8637
69.3k
    case 0x2e:
8638
69.3k
      return "cs";
8639
51.6k
    case 0x36:
8640
51.6k
      return "ss";
8641
31.9k
    case 0x3e:
8642
31.9k
      return "ds";
8643
29.6k
    case 0x26:
8644
29.6k
      return "es";
8645
66.5k
    case 0x64:
8646
66.5k
      return "fs";
8647
86.0k
    case 0x65:
8648
86.0k
      return "gs";
8649
51.3k
    case 0x66:
8650
51.3k
      return (sizeflag & DFLAG) ? "data16" : "data32";
8651
52.6k
    case 0x67:
8652
52.6k
      if (mode == mode_64bit)
8653
38.2k
  return (sizeflag & AFLAG) ? "addr32" : "addr64";
8654
14.4k
      else
8655
14.4k
  return (sizeflag & AFLAG) ? "addr16" : "addr32";
8656
60
    case FWAIT_OPCODE:
8657
60
      return "fwait";
8658
884
    case REP_PREFIX:
8659
884
      return "rep";
8660
852
    case XACQUIRE_PREFIX:
8661
852
      return "xacquire";
8662
1.51k
    case XRELEASE_PREFIX:
8663
1.51k
      return "xrelease";
8664
2.50k
    case BND_PREFIX:
8665
2.50k
      return "bnd";
8666
688
    case NOTRACK_PREFIX:
8667
688
      return "notrack";
8668
16.7k
    case REX2_OPCODE:
8669
16.7k
      return "rex2";
8670
0
    default:
8671
0
      return NULL;
8672
1.09M
    }
8673
1.09M
}
8674
8675
void
8676
print_i386_disassembler_options (FILE *stream)
8677
0
{
8678
0
  fprintf (stream, _("\n\
8679
0
The following i386/x86-64 specific disassembler options are supported for use\n\
8680
0
with the -M switch (multiple options should be separated by commas):\n"));
8681
8682
0
  fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
8683
0
  fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
8684
0
  fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
8685
0
  fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
8686
0
  fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
8687
0
  fprintf (stream, _("  att-mnemonic  (AT&T syntax only)\n"
8688
0
         "              Display instruction with AT&T mnemonic\n"));
8689
0
  fprintf (stream, _("  intel-mnemonic  (AT&T syntax only)\n"
8690
0
         "              Display instruction with Intel mnemonic\n"));
8691
0
  fprintf (stream, _("  addr64      Assume 64bit address size\n"));
8692
0
  fprintf (stream, _("  addr32      Assume 32bit address size\n"));
8693
0
  fprintf (stream, _("  addr16      Assume 16bit address size\n"));
8694
0
  fprintf (stream, _("  data32      Assume 32bit data size\n"));
8695
0
  fprintf (stream, _("  data16      Assume 16bit data size\n"));
8696
0
  fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
8697
0
  fprintf (stream, _("  amd64       Display instruction in AMD64 ISA\n"));
8698
0
  fprintf (stream, _("  intel64     Display instruction in Intel64 ISA\n"));
8699
0
}
8700
8701
/* Bad opcode.  */
8702
static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
8703
8704
/* Fetch error indicator.  */
8705
static const struct dis386 err_opcode = { NULL, { XX }, 0 };
8706
8707
static const struct dis386 map7_f8_opcode = { VEX_LEN_TABLE (VEX_LEN_MAP7_F8) };
8708
8709
/* Get a pointer to struct dis386 with a valid name.  */
8710
8711
static const struct dis386 *
8712
get_valid_dis386 (const struct dis386 *dp, instr_info *ins)
8713
20.8M
{
8714
20.8M
  int vindex, vex_table_index;
8715
8716
20.8M
  if (dp->name != NULL)
8717
14.7M
    return dp;
8718
8719
6.14M
  switch (dp->op[0].bytemode)
8720
6.14M
    {
8721
2.02M
    case USE_REG_TABLE:
8722
2.02M
      dp = &reg_table[dp->op[1].bytemode][ins->modrm.reg];
8723
2.02M
      break;
8724
8725
56.5k
    case USE_MOD_TABLE:
8726
56.5k
      vindex = ins->modrm.mod == 0x3 ? 1 : 0;
8727
56.5k
      dp = &mod_table[dp->op[1].bytemode][vindex];
8728
56.5k
      break;
8729
8730
9.19k
    case USE_RM_TABLE:
8731
9.19k
      dp = &rm_table[dp->op[1].bytemode][ins->modrm.rm];
8732
9.19k
      break;
8733
8734
197k
    case USE_PREFIX_TABLE:
8735
198k
    use_prefix_table:
8736
198k
      if (ins->need_vex)
8737
37.3k
  {
8738
    /* The prefix in VEX is implicit.  */
8739
37.3k
    switch (ins->vex.prefix)
8740
37.3k
      {
8741
6.22k
      case 0:
8742
6.22k
        vindex = 0;
8743
6.22k
        break;
8744
10.9k
      case REPE_PREFIX_OPCODE:
8745
10.9k
        vindex = 1;
8746
10.9k
        break;
8747
12.9k
      case DATA_PREFIX_OPCODE:
8748
12.9k
        vindex = 2;
8749
12.9k
        break;
8750
7.26k
      case REPNE_PREFIX_OPCODE:
8751
7.26k
        vindex = 3;
8752
7.26k
        break;
8753
0
      default:
8754
0
        abort ();
8755
0
        break;
8756
37.3k
      }
8757
37.3k
  }
8758
160k
      else
8759
160k
  {
8760
160k
    int last_prefix = -1;
8761
160k
    int prefix = 0;
8762
160k
    vindex = 0;
8763
    /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
8764
       When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
8765
       last one wins.  */
8766
160k
    if ((ins->prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
8767
6.72k
      {
8768
6.72k
        if (ins->last_repz_prefix > ins->last_repnz_prefix)
8769
3.61k
    {
8770
3.61k
      vindex = 1;
8771
3.61k
      prefix = PREFIX_REPZ;
8772
3.61k
      last_prefix = ins->last_repz_prefix;
8773
3.61k
    }
8774
3.10k
        else
8775
3.10k
    {
8776
3.10k
      vindex = 3;
8777
3.10k
      prefix = PREFIX_REPNZ;
8778
3.10k
      last_prefix = ins->last_repnz_prefix;
8779
3.10k
    }
8780
8781
        /* Check if prefix should be ignored.  */
8782
6.72k
        if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
8783
6.72k
         & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
8784
6.72k
       & prefix) != 0
8785
6.72k
      && !prefix_table[dp->op[1].bytemode][vindex].name)
8786
434
    vindex = 0;
8787
6.72k
      }
8788
8789
160k
    if (vindex == 0 && (ins->prefixes & PREFIX_DATA) != 0)
8790
9.98k
      {
8791
9.98k
        vindex = 2;
8792
9.98k
        prefix = PREFIX_DATA;
8793
9.98k
        last_prefix = ins->last_data_prefix;
8794
9.98k
      }
8795
8796
160k
    if (vindex != 0)
8797
16.2k
      {
8798
16.2k
        ins->used_prefixes |= prefix;
8799
16.2k
        ins->all_prefixes[last_prefix] = 0;
8800
16.2k
      }
8801
160k
  }
8802
198k
      dp = &prefix_table[dp->op[1].bytemode][vindex];
8803
198k
      break;
8804
8805
849
    case USE_X86_64_EVEX_FROM_VEX_TABLE:
8806
2.05k
    case USE_X86_64_EVEX_PFX_TABLE:
8807
2.30k
    case USE_X86_64_EVEX_W_TABLE:
8808
3.08k
    case USE_X86_64_EVEX_MEM_W_TABLE:
8809
3.08k
      ins->evex_type = evex_from_vex;
8810
      /* EVEX from VEX instructions are 64-bit only and require that EVEX.z,
8811
   EVEX.L'L, EVEX.b, and the lower 2 bits of EVEX.aaa must be 0.  */
8812
3.08k
      if (ins->address_mode != mode_64bit
8813
3.08k
    || (ins->vex.mask_register_specifier & 0x3) != 0
8814
3.08k
    || ins->vex.ll != 0
8815
3.08k
    || ins->vex.zeroing != 0
8816
3.08k
    || ins->vex.b)
8817
1.70k
  return &bad_opcode;
8818
8819
1.38k
      if (dp->op[0].bytemode == USE_X86_64_EVEX_PFX_TABLE)
8820
609
  goto use_prefix_table;
8821
775
      if (dp->op[0].bytemode == USE_X86_64_EVEX_W_TABLE)
8822
190
  goto use_vex_w_table;
8823
585
      if (dp->op[0].bytemode == USE_X86_64_EVEX_MEM_W_TABLE)
8824
380
  {
8825
380
    if (ins->modrm.mod == 3)
8826
190
      return &bad_opcode;
8827
190
    goto use_vex_w_table;
8828
380
  }
8829
8830
      /* Fall through.  */
8831
1.72M
    case USE_X86_64_TABLE:
8832
1.72M
      vindex = ins->address_mode == mode_64bit ? 1 : 0;
8833
1.72M
      dp = &x86_64_table[dp->op[1].bytemode][vindex];
8834
1.72M
      break;
8835
8836
6.78k
    case USE_3BYTE_TABLE:
8837
6.78k
      if (ins->last_rex2_prefix >= 0)
8838
1.05k
  return &err_opcode;
8839
5.72k
      if (!fetch_code (ins->info, ins->codep + 2))
8840
14
  return &err_opcode;
8841
5.71k
      vindex = *ins->codep++;
8842
5.71k
      dp = &three_byte_table[dp->op[1].bytemode][vindex];
8843
5.71k
      ins->end_codep = ins->codep;
8844
5.71k
      if (!fetch_modrm (ins))
8845
0
  return &err_opcode;
8846
5.71k
      break;
8847
8848
12.5k
    case USE_VEX_LEN_TABLE:
8849
12.5k
      if (!ins->need_vex)
8850
0
  abort ();
8851
8852
12.5k
      switch (ins->vex.length)
8853
12.5k
  {
8854
10.1k
  case 128:
8855
10.1k
    vindex = 0;
8856
10.1k
    break;
8857
475
  case 512:
8858
    /* This allows re-using in particular table entries where only
8859
       128-bit operand size (VEX.L=0 / EVEX.L'L=0) are valid.  */
8860
475
    if (ins->vex.evex)
8861
475
      {
8862
2.35k
  case 256:
8863
2.35k
        vindex = 1;
8864
2.35k
        break;
8865
475
      }
8866
  /* Fall through.  */
8867
0
  default:
8868
0
    abort ();
8869
0
    break;
8870
12.5k
  }
8871
8872
12.5k
      dp = &vex_len_table[dp->op[1].bytemode][vindex];
8873
12.5k
      break;
8874
8875
2.32k
    case USE_EVEX_LEN_TABLE:
8876
2.32k
      if (!ins->vex.evex)
8877
0
  abort ();
8878
8879
2.32k
      switch (ins->vex.length)
8880
2.32k
  {
8881
1.29k
  case 128:
8882
1.29k
    vindex = 0;
8883
1.29k
    break;
8884
478
  case 256:
8885
478
    vindex = 1;
8886
478
    break;
8887
547
  case 512:
8888
547
    vindex = 2;
8889
547
    break;
8890
0
  default:
8891
0
    abort ();
8892
0
    break;
8893
2.32k
  }
8894
8895
2.32k
      dp = &evex_len_table[dp->op[1].bytemode][vindex];
8896
2.32k
      break;
8897
8898
402k
    case USE_XOP_8F_TABLE:
8899
402k
      if (!fetch_code (ins->info, ins->codep + 3))
8900
24
  return &err_opcode;
8901
402k
      ins->rex = ~(*ins->codep >> 5) & 0x7;
8902
8903
      /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
8904
402k
      switch ((*ins->codep & 0x1f))
8905
402k
  {
8906
396k
  default:
8907
396k
    dp = &bad_opcode;
8908
396k
    return dp;
8909
1.41k
  case 0x8:
8910
1.41k
    vex_table_index = XOP_08;
8911
1.41k
    break;
8912
1.60k
  case 0x9:
8913
1.60k
    vex_table_index = XOP_09;
8914
1.60k
    break;
8915
2.86k
  case 0xa:
8916
2.86k
    vex_table_index = XOP_0A;
8917
2.86k
    break;
8918
402k
  }
8919
5.88k
      ins->codep++;
8920
5.88k
      ins->vex.w = *ins->codep & 0x80;
8921
5.88k
      if (ins->vex.w && ins->address_mode == mode_64bit)
8922
2.61k
  ins->rex |= REX_W;
8923
8924
5.88k
      ins->vex.register_specifier = (~(*ins->codep >> 3)) & 0xf;
8925
5.88k
      if (ins->address_mode != mode_64bit)
8926
1.96k
  {
8927
    /* In 16/32-bit mode REX_B is silently ignored.  */
8928
1.96k
    ins->rex &= ~REX_B;
8929
1.96k
  }
8930
8931
5.88k
      ins->vex.length = (*ins->codep & 0x4) ? 256 : 128;
8932
5.88k
      switch ((*ins->codep & 0x3))
8933
5.88k
  {
8934
4.71k
  case 0:
8935
4.71k
    break;
8936
231
  case 1:
8937
231
    ins->vex.prefix = DATA_PREFIX_OPCODE;
8938
231
    break;
8939
480
  case 2:
8940
480
    ins->vex.prefix = REPE_PREFIX_OPCODE;
8941
480
    break;
8942
468
  case 3:
8943
468
    ins->vex.prefix = REPNE_PREFIX_OPCODE;
8944
468
    break;
8945
5.88k
  }
8946
5.88k
      ins->need_vex = 3;
8947
5.88k
      ins->codep++;
8948
5.88k
      vindex = *ins->codep++;
8949
5.88k
      dp = &xop_table[vex_table_index][vindex];
8950
8951
5.88k
      ins->end_codep = ins->codep;
8952
5.88k
      if (!fetch_modrm (ins))
8953
44
  return &err_opcode;
8954
8955
      /* No XOP encoding so far allows for a non-zero embedded prefix. Avoid
8956
   having to decode the bits for every otherwise valid encoding.  */
8957
5.84k
      if (ins->vex.prefix)
8958
1.16k
  return &bad_opcode;
8959
4.68k
      break;
8960
8961
38.8k
    case USE_VEX_C4_TABLE:
8962
      /* VEX prefix.  */
8963
38.8k
      if (!fetch_code (ins->info, ins->codep + 3))
8964
23
  return &err_opcode;
8965
38.8k
      ins->rex = ~(*ins->codep >> 5) & 0x7;
8966
38.8k
      switch ((*ins->codep & 0x1f))
8967
38.8k
  {
8968
22.8k
  default:
8969
22.8k
    dp = &bad_opcode;
8970
22.8k
    return dp;
8971
2.39k
  case 0x1:
8972
2.39k
    vex_table_index = VEX_0F;
8973
2.39k
    break;
8974
9.04k
  case 0x2:
8975
9.04k
    vex_table_index = VEX_0F38;
8976
9.04k
    break;
8977
3.49k
  case 0x3:
8978
3.49k
    vex_table_index = VEX_0F3A;
8979
3.49k
    break;
8980
1.04k
  case 0x7:
8981
1.04k
    vex_table_index = VEX_MAP7;
8982
1.04k
    break;
8983
38.8k
  }
8984
15.9k
      ins->codep++;
8985
15.9k
      ins->vex.w = *ins->codep & 0x80;
8986
15.9k
      if (ins->address_mode == mode_64bit)
8987
13.0k
  {
8988
13.0k
    if (ins->vex.w)
8989
5.03k
      ins->rex |= REX_W;
8990
13.0k
  }
8991
2.95k
      else
8992
2.95k
  {
8993
    /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
8994
       is ignored, other REX bits are 0 and the highest bit in
8995
       VEX.vvvv is also ignored (but we mustn't clear it here).  */
8996
2.95k
    ins->rex = 0;
8997
2.95k
  }
8998
15.9k
      ins->vex.register_specifier = (~(*ins->codep >> 3)) & 0xf;
8999
15.9k
      ins->vex.length = (*ins->codep & 0x4) ? 256 : 128;
9000
15.9k
      switch ((*ins->codep & 0x3))
9001
15.9k
  {
9002
6.60k
  case 0:
9003
6.60k
    break;
9004
3.87k
  case 1:
9005
3.87k
    ins->vex.prefix = DATA_PREFIX_OPCODE;
9006
3.87k
    break;
9007
4.10k
  case 2:
9008
4.10k
    ins->vex.prefix = REPE_PREFIX_OPCODE;
9009
4.10k
    break;
9010
1.40k
  case 3:
9011
1.40k
    ins->vex.prefix = REPNE_PREFIX_OPCODE;
9012
1.40k
    break;
9013
15.9k
  }
9014
15.9k
      ins->need_vex = 3;
9015
15.9k
      ins->codep++;
9016
15.9k
      vindex = *ins->codep++;
9017
15.9k
      if (vex_table_index != VEX_MAP7)
9018
14.9k
  dp = &vex_table[vex_table_index][vindex];
9019
1.04k
      else if (vindex == 0xf8)
9020
224
  dp = &map7_f8_opcode;
9021
817
      else
9022
817
  dp = &bad_opcode;
9023
15.9k
      ins->end_codep = ins->codep;
9024
      /* There is no MODRM byte for VEX0F 77.  */
9025
15.9k
      if ((vex_table_index != VEX_0F || vindex != 0x77)
9026
15.9k
    && !fetch_modrm (ins))
9027
3
  return &err_opcode;
9028
15.9k
      break;
9029
9030
28.6k
    case USE_VEX_C5_TABLE:
9031
      /* VEX prefix.  */
9032
28.6k
      if (!fetch_code (ins->info, ins->codep + 2))
9033
31
  return &err_opcode;
9034
28.5k
      ins->rex = (*ins->codep & 0x80) ? 0 : REX_R;
9035
9036
      /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
9037
   VEX.vvvv is 1.  */
9038
28.5k
      ins->vex.register_specifier = (~(*ins->codep >> 3)) & 0xf;
9039
28.5k
      ins->vex.length = (*ins->codep & 0x4) ? 256 : 128;
9040
28.5k
      switch ((*ins->codep & 0x3))
9041
28.5k
  {
9042
5.21k
  case 0:
9043
5.21k
    break;
9044
11.6k
  case 1:
9045
11.6k
    ins->vex.prefix = DATA_PREFIX_OPCODE;
9046
11.6k
    break;
9047
4.47k
  case 2:
9048
4.47k
    ins->vex.prefix = REPE_PREFIX_OPCODE;
9049
4.47k
    break;
9050
7.22k
  case 3:
9051
7.22k
    ins->vex.prefix = REPNE_PREFIX_OPCODE;
9052
7.22k
    break;
9053
28.5k
  }
9054
28.5k
      ins->need_vex = 2;
9055
28.5k
      ins->codep++;
9056
28.5k
      vindex = *ins->codep++;
9057
28.5k
      dp = &vex_table[VEX_0F][vindex];
9058
28.5k
      ins->end_codep = ins->codep;
9059
      /* There is no MODRM byte for VEX 77.  */
9060
28.5k
      if (vindex != 0x77 && !fetch_modrm (ins))
9061
10
  return &err_opcode;
9062
28.5k
      break;
9063
9064
28.5k
    case USE_VEX_W_TABLE:
9065
15.4k
    use_vex_w_table:
9066
15.4k
      if (!ins->need_vex)
9067
0
  abort ();
9068
9069
15.4k
      dp = &vex_w_table[dp->op[1].bytemode][ins->vex.w];
9070
15.4k
      break;
9071
9072
118k
    case USE_EVEX_TABLE:
9073
118k
      ins->two_source_ops = false;
9074
      /* EVEX prefix.  */
9075
118k
      ins->vex.evex = true;
9076
118k
      if (!fetch_code (ins->info, ins->codep + 4))
9077
161
  return &err_opcode;
9078
      /* The first byte after 0x62.  */
9079
118k
      if (*ins->codep & 0x8)
9080
20.4k
  ins->rex2 |= REX_B;
9081
118k
      if (!(*ins->codep & 0x10))
9082
68.4k
  ins->rex2 |= REX_R;
9083
9084
118k
      ins->rex = ~(*ins->codep >> 5) & 0x7;
9085
118k
      switch (*ins->codep & 0x7)
9086
118k
  {
9087
10.2k
  default:
9088
10.2k
    return &bad_opcode;
9089
16.9k
  case 0x1:
9090
16.9k
    vex_table_index = EVEX_0F;
9091
16.9k
    break;
9092
21.8k
  case 0x2:
9093
21.8k
    vex_table_index = EVEX_0F38;
9094
21.8k
    break;
9095
15.5k
  case 0x3:
9096
15.5k
    vex_table_index = EVEX_0F3A;
9097
15.5k
    break;
9098
16.2k
  case 0x4:
9099
16.2k
    vex_table_index = EVEX_MAP4;
9100
16.2k
    ins->evex_type = evex_from_legacy;
9101
16.2k
    if (ins->address_mode != mode_64bit)
9102
631
      return &bad_opcode;
9103
15.6k
    break;
9104
18.0k
  case 0x5:
9105
18.0k
    vex_table_index = EVEX_MAP5;
9106
18.0k
    break;
9107
11.9k
  case 0x6:
9108
11.9k
    vex_table_index = EVEX_MAP6;
9109
11.9k
    break;
9110
7.73k
  case 0x7:
9111
7.73k
    vex_table_index = EVEX_MAP7;
9112
7.73k
    break;
9113
118k
  }
9114
9115
      /* The second byte after 0x62.  */
9116
107k
      ins->codep++;
9117
107k
      ins->vex.w = *ins->codep & 0x80;
9118
107k
      if (ins->vex.w && ins->address_mode == mode_64bit)
9119
27.3k
  ins->rex |= REX_W;
9120
9121
107k
      ins->vex.register_specifier = (~(*ins->codep >> 3)) & 0xf;
9122
9123
107k
      if (!(*ins->codep & 0x4))
9124
30.6k
  ins->rex2 |= REX_X;
9125
9126
107k
      switch ((*ins->codep & 0x3))
9127
107k
  {
9128
28.1k
  case 0:
9129
28.1k
    break;
9130
20.3k
  case 1:
9131
20.3k
    ins->vex.prefix = DATA_PREFIX_OPCODE;
9132
20.3k
    break;
9133
31.4k
  case 2:
9134
31.4k
    ins->vex.prefix = REPE_PREFIX_OPCODE;
9135
31.4k
    break;
9136
27.7k
  case 3:
9137
27.7k
    ins->vex.prefix = REPNE_PREFIX_OPCODE;
9138
27.7k
    break;
9139
107k
  }
9140
9141
      /* The third byte after 0x62.  */
9142
107k
      ins->codep++;
9143
9144
      /* Remember the static rounding bits.  */
9145
107k
      ins->vex.ll = (*ins->codep >> 5) & 3;
9146
107k
      ins->vex.b = *ins->codep & 0x10;
9147
9148
107k
      ins->vex.v = *ins->codep & 0x8;
9149
107k
      ins->vex.mask_register_specifier = *ins->codep & 0x7;
9150
107k
      ins->vex.zeroing = *ins->codep & 0x80;
9151
      /* Set the NF bit for EVEX-Promoted instructions, this bit will be cleared
9152
   when it's an evex_default one.  */
9153
107k
      ins->vex.nf = *ins->codep & 0x4;
9154
9155
107k
      if (ins->address_mode != mode_64bit)
9156
7.97k
  {
9157
    /* Report bad for !evex_default and when two fixed values of evex
9158
       change..  */
9159
7.97k
    if (ins->evex_type != evex_default
9160
7.97k
        || (ins->rex2 & (REX_B | REX_X)))
9161
862
      return &bad_opcode;
9162
    /* In 16/32-bit mode silently ignore following bits.  */
9163
7.11k
    ins->rex &= ~REX_B;
9164
7.11k
    ins->rex2 &= ~REX_R;
9165
7.11k
  }
9166
9167
      /* EVEX from legacy instructions, when the EVEX.ND bit is 0,
9168
   all bits of EVEX.vvvv and EVEX.V' must be 1.  */
9169
106k
      if (ins->evex_type == evex_from_legacy && !ins->vex.nd
9170
106k
    && (ins->vex.register_specifier || !ins->vex.v))
9171
3.34k
  return &bad_opcode;
9172
9173
103k
      ins->need_vex = 4;
9174
9175
      /* EVEX from legacy instructions require that EVEX.z, EVEX.L’L and the
9176
   lower 2 bits of EVEX.aaa must be 0.  */
9177
103k
      if (ins->evex_type == evex_from_legacy
9178
103k
    && ((ins->vex.mask_register_specifier & 0x3) != 0
9179
12.3k
        || ins->vex.ll != 0
9180
12.3k
        || ins->vex.zeroing != 0))
9181
5.09k
  return &bad_opcode;
9182
9183
98.4k
      ins->codep++;
9184
98.4k
      vindex = *ins->codep++;
9185
98.4k
      if (vex_table_index != EVEX_MAP7)
9186
90.8k
  dp = &evex_table[vex_table_index][vindex];
9187
7.60k
      else if (vindex == 0xf8)
9188
190
  dp = &map7_f8_opcode;
9189
7.41k
      else
9190
7.41k
  dp = &bad_opcode;
9191
98.4k
      ins->end_codep = ins->codep;
9192
98.4k
      if (!fetch_modrm (ins))
9193
41
  return &err_opcode;
9194
9195
98.4k
      if (ins->modrm.mod == 3 && (ins->rex2 & REX_X))
9196
2.80k
  return &bad_opcode;
9197
9198
      /* Set vector length. For EVEX-promoted instructions, evex.ll == 0b00,
9199
   which has the same encoding as vex.length == 128 and they can share
9200
   the same processing with vex.length in OP_VEX.  */
9201
95.6k
      if (ins->modrm.mod == 3 && ins->vex.b && ins->evex_type != evex_from_legacy)
9202
6.71k
  ins->vex.length = 512;
9203
88.9k
      else
9204
88.9k
  {
9205
88.9k
    switch (ins->vex.ll)
9206
88.9k
      {
9207
32.1k
      case 0x0:
9208
32.1k
        ins->vex.length = 128;
9209
32.1k
        break;
9210
17.5k
      case 0x1:
9211
17.5k
        ins->vex.length = 256;
9212
17.5k
        break;
9213
21.9k
      case 0x2:
9214
21.9k
        ins->vex.length = 512;
9215
21.9k
        break;
9216
17.2k
      default:
9217
17.2k
        return &bad_opcode;
9218
88.9k
      }
9219
88.9k
  }
9220
78.3k
      break;
9221
9222
1.50M
    case 0:
9223
1.50M
      dp = &bad_opcode;
9224
1.50M
      break;
9225
9226
0
    default:
9227
0
      abort ();
9228
6.14M
    }
9229
9230
5.68M
  if (dp->name != NULL)
9231
3.45M
    return dp;
9232
2.22M
  else
9233
2.22M
    return get_valid_dis386 (dp, ins);
9234
5.68M
}
9235
9236
static bool
9237
get_sib (instr_info *ins, int sizeflag)
9238
18.8M
{
9239
  /* If modrm.mod == 3, operand must be register.  */
9240
18.8M
  if (ins->need_modrm
9241
18.8M
      && ((sizeflag & AFLAG) || ins->address_mode == mode_64bit)
9242
18.8M
      && ins->modrm.mod != 3
9243
18.8M
      && ins->modrm.rm == 4)
9244
608k
    {
9245
608k
      if (!fetch_code (ins->info, ins->codep + 2))
9246
374
  return false;
9247
607k
      ins->sib.index = (ins->codep[1] >> 3) & 7;
9248
607k
      ins->sib.scale = (ins->codep[1] >> 6) & 3;
9249
607k
      ins->sib.base = ins->codep[1] & 7;
9250
607k
      ins->has_sib = true;
9251
607k
    }
9252
18.2M
  else
9253
18.2M
    ins->has_sib = false;
9254
9255
18.8M
  return true;
9256
18.8M
}
9257
9258
/* Like oappend_with_style (below) but always with text style.  */
9259
9260
static void
9261
oappend (instr_info *ins, const char *s)
9262
3.16M
{
9263
3.16M
  oappend_with_style (ins, s, dis_style_text);
9264
3.16M
}
9265
9266
/* Like oappend (above), but S is a string starting with '%'.  In
9267
   Intel syntax, the '%' is elided.  */
9268
9269
static void
9270
oappend_register (instr_info *ins, const char *s)
9271
24.9M
{
9272
24.9M
  oappend_with_style (ins, s + ins->intel_syntax, dis_style_register);
9273
24.9M
}
9274
9275
/* Wrap around a call to INS->info->fprintf_styled_func, printing FMT.
9276
   STYLE is the default style to use in the fprintf_styled_func calls,
9277
   however, FMT might include embedded style markers (see oappend_style),
9278
   these embedded markers are not printed, but instead change the style
9279
   used in the next fprintf_styled_func call.  */
9280
9281
static void ATTRIBUTE_PRINTF_3
9282
i386_dis_printf (const disassemble_info *info, enum disassembler_style style,
9283
     const char *fmt, ...)
9284
59.6M
{
9285
59.6M
  va_list ap;
9286
59.6M
  enum disassembler_style curr_style = style;
9287
59.6M
  const char *start, *curr;
9288
59.6M
  char staging_area[40];
9289
9290
59.6M
  va_start (ap, fmt);
9291
  /* In particular print_insn()'s processing of op_txt[] can hand rather long
9292
     strings here.  Bypass vsnprintf() in such cases to avoid capacity issues
9293
     with the staging area.  */
9294
59.6M
  if (strcmp (fmt, "%s"))
9295
32.6M
    {
9296
32.6M
      int res = vsnprintf (staging_area, sizeof (staging_area), fmt, ap);
9297
9298
32.6M
      va_end (ap);
9299
9300
32.6M
      if (res < 0)
9301
0
  return;
9302
9303
32.6M
      if ((size_t) res >= sizeof (staging_area))
9304
0
  abort ();
9305
9306
32.6M
      start = curr = staging_area;
9307
32.6M
    }
9308
26.9M
  else
9309
26.9M
    {
9310
26.9M
      start = curr = va_arg (ap, const char *);
9311
26.9M
      va_end (ap);
9312
26.9M
    }
9313
9314
59.6M
  do
9315
409M
    {
9316
409M
      if (*curr == '\0'
9317
409M
    || (*curr == STYLE_MARKER_CHAR
9318
349M
        && ISXDIGIT (*(curr + 1))
9319
349M
        && *(curr + 2) == STYLE_MARKER_CHAR))
9320
115M
  {
9321
    /* Output content between our START position and CURR.  */
9322
115M
    int len = curr - start;
9323
115M
    int n = (*info->fprintf_styled_func) (info->stream, curr_style,
9324
115M
            "%.*s", len, start);
9325
115M
    if (n < 0)
9326
0
      break;
9327
9328
115M
    if (*curr == '\0')
9329
59.6M
      break;
9330
9331
    /* Skip over the initial STYLE_MARKER_CHAR.  */
9332
56.2M
    ++curr;
9333
9334
    /* Update the CURR_STYLE.  As there are less than 16 styles, it
9335
       is possible, that if the input is corrupted in some way, that
9336
       we might set CURR_STYLE to an invalid value.  Don't worry
9337
       though, we check for this situation.  */
9338
56.2M
    if (*curr >= '0' && *curr <= '9')
9339
56.2M
      curr_style = (enum disassembler_style) (*curr - '0');
9340
0
    else if (*curr >= 'a' && *curr <= 'f')
9341
0
      curr_style = (enum disassembler_style) (*curr - 'a' + 10);
9342
0
    else
9343
0
      curr_style = dis_style_text;
9344
9345
    /* Check for an invalid style having been selected.  This should
9346
       never happen, but it doesn't hurt to be a little paranoid.  */
9347
56.2M
    if (curr_style > dis_style_comment_start)
9348
0
      curr_style = dis_style_text;
9349
9350
    /* Skip the hex character, and the closing STYLE_MARKER_CHAR.  */
9351
56.2M
    curr += 2;
9352
9353
    /* Reset the START to after the style marker.  */
9354
56.2M
    start = curr;
9355
56.2M
  }
9356
293M
      else
9357
293M
  ++curr;
9358
409M
    }
9359
59.6M
  while (true);
9360
59.6M
}
9361
9362
static int
9363
print_insn (bfd_vma pc, disassemble_info *info, int intel_syntax)
9364
19.1M
{
9365
19.1M
  const struct dis386 *dp;
9366
19.1M
  int i;
9367
19.1M
  int ret;
9368
19.1M
  char *op_txt[MAX_OPERANDS];
9369
19.1M
  int needcomma;
9370
19.1M
  bool intel_swap_2_3;
9371
19.1M
  int sizeflag, orig_sizeflag;
9372
19.1M
  const char *p;
9373
19.1M
  struct dis_private priv;
9374
19.1M
  int prefix_length;
9375
19.1M
  int op_count;
9376
19.1M
  instr_info ins = {
9377
19.1M
    .info = info,
9378
19.1M
    .intel_syntax = intel_syntax >= 0
9379
19.1M
        ? intel_syntax
9380
19.1M
        : (info->mach & bfd_mach_i386_intel_syntax) != 0,
9381
19.1M
    .intel_mnemonic = !SYSV386_COMPAT,
9382
19.1M
    .op_index[0 ... MAX_OPERANDS - 1] = -1,
9383
19.1M
    .start_pc = pc,
9384
19.1M
    .start_codep = priv.the_buffer,
9385
19.1M
    .codep = priv.the_buffer,
9386
19.1M
    .obufp = ins.obuf,
9387
19.1M
    .last_lock_prefix = -1,
9388
19.1M
    .last_repz_prefix = -1,
9389
19.1M
    .last_repnz_prefix = -1,
9390
19.1M
    .last_data_prefix = -1,
9391
19.1M
    .last_addr_prefix = -1,
9392
19.1M
    .last_rex_prefix = -1,
9393
19.1M
    .last_rex2_prefix = -1,
9394
19.1M
    .last_seg_prefix = -1,
9395
19.1M
    .fwait_prefix = -1,
9396
19.1M
  };
9397
19.1M
  char op_out[MAX_OPERANDS][MAX_OPERAND_BUFFER_SIZE];
9398
9399
19.1M
  priv.orig_sizeflag = AFLAG | DFLAG;
9400
19.1M
  if ((info->mach & bfd_mach_i386_i386) != 0)
9401
4.87M
    ins.address_mode = mode_32bit;
9402
14.2M
  else if (info->mach == bfd_mach_i386_i8086)
9403
262k
    {
9404
262k
      ins.address_mode = mode_16bit;
9405
262k
      priv.orig_sizeflag = 0;
9406
262k
    }
9407
13.9M
  else
9408
13.9M
    ins.address_mode = mode_64bit;
9409
9410
19.7M
  for (p = info->disassembler_options; p != NULL;)
9411
641k
    {
9412
641k
      if (startswith (p, "amd64"))
9413
1.92k
  ins.isa64 = amd64;
9414
639k
      else if (startswith (p, "intel64"))
9415
4.95k
  ins.isa64 = intel64;
9416
634k
      else if (startswith (p, "x86-64"))
9417
14.8k
  {
9418
14.8k
    ins.address_mode = mode_64bit;
9419
14.8k
    priv.orig_sizeflag |= AFLAG | DFLAG;
9420
14.8k
  }
9421
619k
      else if (startswith (p, "i386"))
9422
3.56k
  {
9423
3.56k
    ins.address_mode = mode_32bit;
9424
3.56k
    priv.orig_sizeflag |= AFLAG | DFLAG;
9425
3.56k
  }
9426
615k
      else if (startswith (p, "i8086"))
9427
40.9k
  {
9428
40.9k
    ins.address_mode = mode_16bit;
9429
40.9k
    priv.orig_sizeflag &= ~(AFLAG | DFLAG);
9430
40.9k
  }
9431
574k
      else if (startswith (p, "intel"))
9432
57.9k
  {
9433
57.9k
    if (startswith (p + 5, "-mnemonic"))
9434
908
      ins.intel_mnemonic = true;
9435
57.0k
    else
9436
57.0k
      ins.intel_syntax = 1;
9437
57.9k
  }
9438
516k
      else if (startswith (p, "att"))
9439
7.40k
  {
9440
7.40k
    ins.intel_syntax = 0;
9441
7.40k
    if (startswith (p + 3, "-mnemonic"))
9442
256
      ins.intel_mnemonic = false;
9443
7.40k
  }
9444
509k
      else if (startswith (p, "addr"))
9445
34.6k
  {
9446
34.6k
    if (ins.address_mode == mode_64bit)
9447
29.6k
      {
9448
29.6k
        if (p[4] == '3' && p[5] == '2')
9449
15.1k
    priv.orig_sizeflag &= ~AFLAG;
9450
14.4k
        else if (p[4] == '6' && p[5] == '4')
9451
240
    priv.orig_sizeflag |= AFLAG;
9452
29.6k
      }
9453
5.05k
    else
9454
5.05k
      {
9455
5.05k
        if (p[4] == '1' && p[5] == '6')
9456
682
    priv.orig_sizeflag &= ~AFLAG;
9457
4.37k
        else if (p[4] == '3' && p[5] == '2')
9458
876
    priv.orig_sizeflag |= AFLAG;
9459
5.05k
      }
9460
34.6k
  }
9461
474k
      else if (startswith (p, "data"))
9462
30.2k
  {
9463
30.2k
    if (p[4] == '1' && p[5] == '6')
9464
20.0k
      priv.orig_sizeflag &= ~DFLAG;
9465
10.1k
    else if (p[4] == '3' && p[5] == '2')
9466
562
      priv.orig_sizeflag |= DFLAG;
9467
30.2k
  }
9468
444k
      else if (startswith (p, "suffix"))
9469
18.7k
  priv.orig_sizeflag |= SUFFIX_ALWAYS;
9470
9471
641k
      p = strchr (p, ',');
9472
641k
      if (p != NULL)
9473
205k
  p++;
9474
641k
    }
9475
9476
19.1M
  if (ins.address_mode == mode_64bit && sizeof (bfd_vma) < 8)
9477
0
    {
9478
0
      i386_dis_printf (info, dis_style_text, _("64-bit address is disabled"));
9479
0
      return -1;
9480
0
    }
9481
9482
19.1M
  if (ins.intel_syntax)
9483
646k
    {
9484
646k
      ins.open_char = '[';
9485
646k
      ins.close_char = ']';
9486
646k
      ins.separator_char = '+';
9487
646k
      ins.scale_char = '*';
9488
646k
    }
9489
18.4M
  else
9490
18.4M
    {
9491
18.4M
      ins.open_char = '(';
9492
18.4M
      ins.close_char =  ')';
9493
18.4M
      ins.separator_char = ',';
9494
18.4M
      ins.scale_char = ',';
9495
18.4M
    }
9496
9497
  /* The output looks better if we put 7 bytes on a line, since that
9498
     puts most long word instructions on a single line.  */
9499
19.1M
  info->bytes_per_line = 7;
9500
9501
19.1M
  info->private_data = &priv;
9502
19.1M
  priv.fetched = 0;
9503
19.1M
  priv.insn_start = pc;
9504
9505
114M
  for (i = 0; i < MAX_OPERANDS; ++i)
9506
95.6M
    {
9507
95.6M
      op_out[i][0] = 0;
9508
95.6M
      ins.op_out[i] = op_out[i];
9509
95.6M
    }
9510
9511
19.1M
  sizeflag = priv.orig_sizeflag;
9512
9513
19.1M
  switch (ckprefix (&ins))
9514
19.1M
    {
9515
18.9M
    case ckp_okay:
9516
18.9M
      break;
9517
9518
208k
    case ckp_bogus:
9519
      /* Too many prefixes or unused REX prefixes.  */
9520
208k
      for (i = 0;
9521
489k
     i < (int) ARRAY_SIZE (ins.all_prefixes) && ins.all_prefixes[i];
9522
280k
     i++)
9523
280k
  i386_dis_printf (info, dis_style_mnemonic, "%s%s",
9524
280k
       (i == 0 ? "" : " "),
9525
280k
       prefix_name (ins.address_mode, ins.all_prefixes[i],
9526
280k
              sizeflag));
9527
208k
      ret = i;
9528
208k
      goto out;
9529
9530
2.05k
    case ckp_fetch_error:
9531
2.05k
      goto fetch_error_out;
9532
19.1M
    }
9533
9534
18.9M
  ins.nr_prefixes = ins.codep - ins.start_codep;
9535
9536
18.9M
  if (!fetch_code (info, ins.codep + 1))
9537
8
    {
9538
16.5k
    fetch_error_out:
9539
16.5k
      ret = fetch_error (&ins);
9540
16.5k
      goto out;
9541
8
    }
9542
9543
18.9M
  ins.two_source_ops = (*ins.codep == 0x62 || *ins.codep == 0xc8);
9544
9545
18.9M
  if ((ins.prefixes & PREFIX_FWAIT)
9546
18.9M
      && (*ins.codep < 0xd8 || *ins.codep > 0xdf))
9547
24.9k
    {
9548
      /* Handle ins.prefixes before fwait.  */
9549
26.9k
      for (i = 0; i < ins.fwait_prefix && ins.all_prefixes[i];
9550
24.9k
     i++)
9551
2.02k
  i386_dis_printf (info, dis_style_mnemonic, "%s ",
9552
2.02k
       prefix_name (ins.address_mode, ins.all_prefixes[i],
9553
2.02k
              sizeflag));
9554
24.9k
      i386_dis_printf (info, dis_style_mnemonic, "fwait");
9555
24.9k
      ret = i + 1;
9556
24.9k
      goto out;
9557
24.9k
    }
9558
9559
  /* REX2.M in rex2 prefix represents map0 or map1.  */
9560
18.8M
  if (ins.last_rex2_prefix < 0 ? *ins.codep == 0x0f : (ins.rex2 & REX2_M))
9561
331k
    {
9562
331k
      if (!ins.rex2)
9563
321k
  {
9564
321k
    ins.codep++;
9565
321k
    if (!fetch_code (info, ins.codep + 1))
9566
102
      goto fetch_error_out;
9567
321k
  }
9568
9569
331k
      dp = &dis386_twobyte[*ins.codep];
9570
331k
      ins.need_modrm = twobyte_has_modrm[*ins.codep];
9571
331k
    }
9572
18.5M
  else
9573
18.5M
    {
9574
18.5M
      dp = &dis386[*ins.codep];
9575
18.5M
      ins.need_modrm = onebyte_has_modrm[*ins.codep];
9576
18.5M
    }
9577
18.8M
  ins.codep++;
9578
9579
  /* Save sizeflag for printing the extra ins.prefixes later before updating
9580
     it for mnemonic and operand processing.  The prefix names depend
9581
     only on the address mode.  */
9582
18.8M
  orig_sizeflag = sizeflag;
9583
18.8M
  if (ins.prefixes & PREFIX_ADDR)
9584
63.5k
    sizeflag ^= AFLAG;
9585
18.8M
  if ((ins.prefixes & PREFIX_DATA))
9586
102k
    sizeflag ^= DFLAG;
9587
9588
18.8M
  ins.end_codep = ins.codep;
9589
18.8M
  if (ins.need_modrm && !fetch_modrm (&ins))
9590
4.30k
    goto fetch_error_out;
9591
9592
18.8M
  if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
9593
221k
    {
9594
221k
      if (!get_sib (&ins, sizeflag)
9595
221k
    || !dofloat (&ins, sizeflag))
9596
20
  goto fetch_error_out;
9597
221k
    }
9598
18.6M
  else
9599
18.6M
    {
9600
18.6M
      dp = get_valid_dis386 (dp, &ins);
9601
18.6M
      if (dp == &err_opcode)
9602
1.40k
  goto fetch_error_out;
9603
9604
      /* For APX instructions promoted from legacy maps 0/1, embedded prefix
9605
   is interpreted as the operand size override.  */
9606
18.6M
      if (ins.evex_type == evex_from_legacy
9607
18.6M
    && ins.vex.prefix == DATA_PREFIX_OPCODE)
9608
3.20k
  sizeflag ^= DFLAG;
9609
9610
18.6M
      if(ins.evex_type == evex_default)
9611
18.6M
  ins.vex.nf = false;
9612
19.3k
      else
9613
  /* For EVEX-promoted formats, we need to clear EVEX.NF (ccmp and ctest
9614
     are cleared separately.) in mask_register_specifier and keep the low
9615
     2 bits of mask_register_specifier to report errors for invalid cases
9616
     .  */
9617
19.3k
  ins.vex.mask_register_specifier &= 0x3;
9618
9619
18.6M
      if (dp != NULL && putop (&ins, dp->name, sizeflag) == 0)
9620
18.6M
  {
9621
18.6M
    if (!get_sib (&ins, sizeflag))
9622
369
      goto fetch_error_out;
9623
111M
    for (i = 0; i < MAX_OPERANDS; ++i)
9624
93.2M
      {
9625
93.2M
        ins.obufp = ins.op_out[i];
9626
93.2M
        ins.op_ad = MAX_OPERANDS - 1 - i;
9627
93.2M
        if (dp->op[i].rtn
9628
93.2M
      && !dp->op[i].rtn (&ins, dp->op[i].bytemode, sizeflag))
9629
8.32k
    goto fetch_error_out;
9630
        /* For EVEX instruction after the last operand masking
9631
     should be printed.  */
9632
93.2M
        if (i == 0 && ins.vex.evex)
9633
118k
    {
9634
      /* Don't print {%k0}.  */
9635
118k
      if (ins.vex.mask_register_specifier)
9636
74.9k
        {
9637
74.9k
          const char *reg_name
9638
74.9k
      = att_names_mask[ins.vex.mask_register_specifier];
9639
9640
74.9k
          oappend (&ins, "{");
9641
74.9k
          oappend_register (&ins, reg_name);
9642
74.9k
          oappend (&ins, "}");
9643
9644
74.9k
          if (ins.vex.zeroing)
9645
19.1k
      oappend (&ins, "{z}");
9646
74.9k
        }
9647
43.6k
      else if (ins.vex.zeroing)
9648
2.98k
        {
9649
2.98k
          oappend (&ins, "{bad}");
9650
2.98k
          continue;
9651
2.98k
        }
9652
9653
      /* Instructions with a mask register destination allow for
9654
         zeroing-masking only (if any masking at all), which is
9655
         _not_ expressed by EVEX.z.  */
9656
115k
      if (ins.vex.zeroing && dp->op[0].bytemode == mask_mode)
9657
2.66k
        ins.illegal_masking = true;
9658
9659
      /* S/G insns require a mask and don't allow
9660
         zeroing-masking.  */
9661
115k
      if ((dp->op[0].bytemode == vex_vsib_d_w_dq_mode
9662
115k
           || dp->op[0].bytemode == vex_vsib_q_w_dq_mode)
9663
115k
          && (ins.vex.mask_register_specifier == 0
9664
3.96k
        || ins.vex.zeroing))
9665
1.42k
        ins.illegal_masking = true;
9666
9667
115k
      if (ins.illegal_masking)
9668
7.17k
        oappend (&ins, "/(bad)");
9669
115k
    }
9670
93.2M
      }
9671
    /* vex.nf is cleared after being consumed.  */
9672
18.6M
    if (ins.vex.nf)
9673
7.18k
      oappend (&ins, "{bad-nf}");
9674
9675
    /* Check whether rounding control was enabled for an insn not
9676
       supporting it, when evex.b is not treated as evex.nd.  */
9677
18.6M
    if (ins.modrm.mod == 3 && ins.vex.b && ins.evex_type == evex_default
9678
18.6M
        && !(ins.evex_used & EVEX_b_used))
9679
5.24k
      {
9680
13.8k
        for (i = 0; i < MAX_OPERANDS; ++i)
9681
13.8k
    {
9682
13.8k
      ins.obufp = ins.op_out[i];
9683
13.8k
      if (*ins.obufp)
9684
8.61k
        continue;
9685
5.24k
      oappend (&ins, names_rounding[ins.vex.ll]);
9686
5.24k
      oappend (&ins, "bad}");
9687
5.24k
      break;
9688
13.8k
    }
9689
5.24k
      }
9690
18.6M
  }
9691
18.6M
    }
9692
9693
  /* Clear instruction information.  */
9694
18.8M
  info->insn_info_valid = 0;
9695
18.8M
  info->branch_delay_insns = 0;
9696
18.8M
  info->data_size = 0;
9697
18.8M
  info->insn_type = dis_noninsn;
9698
18.8M
  info->target = 0;
9699
18.8M
  info->target2 = 0;
9700
9701
  /* Reset jump operation indicator.  */
9702
18.8M
  ins.op_is_jump = false;
9703
18.8M
  {
9704
18.8M
    int jump_detection = 0;
9705
9706
    /* Extract flags.  */
9707
113M
    for (i = 0; i < MAX_OPERANDS; ++i)
9708
94.3M
      {
9709
94.3M
  if ((dp->op[i].rtn == OP_J)
9710
94.3M
      || (dp->op[i].rtn == OP_indirE))
9711
1.62M
    jump_detection |= 1;
9712
92.7M
  else if ((dp->op[i].rtn == BND_Fixup)
9713
92.7M
     || (!dp->op[i].rtn && !dp->op[i].bytemode))
9714
63.9M
    jump_detection |= 2;
9715
28.8M
  else if ((dp->op[i].bytemode == cond_jump_mode)
9716
28.8M
     || (dp->op[i].bytemode == loop_jcxz_mode))
9717
1.21M
    jump_detection |= 4;
9718
94.3M
      }
9719
9720
    /* Determine if this is a jump or branch.  */
9721
18.8M
    if ((jump_detection & 0x3) == 0x3)
9722
1.62M
      {
9723
1.62M
  ins.op_is_jump = true;
9724
1.62M
  if (jump_detection & 0x4)
9725
1.21M
    info->insn_type = dis_condbranch;
9726
405k
  else
9727
405k
    info->insn_type = (dp->name && !strncmp (dp->name, "call", 4))
9728
405k
      ? dis_jsr : dis_branch;
9729
1.62M
      }
9730
18.8M
  }
9731
9732
  /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
9733
     are all 0s in inverted form.  */
9734
18.8M
  if (ins.need_vex && ins.vex.register_specifier != 0)
9735
101k
    {
9736
101k
      i386_dis_printf (info, dis_style_text, "(bad)");
9737
101k
      ret = ins.end_codep - priv.the_buffer;
9738
101k
      goto out;
9739
101k
    }
9740
9741
18.7M
  if ((dp->prefix_requirement & PREFIX_REX2_ILLEGAL)
9742
18.7M
      && ins.last_rex2_prefix >= 0 && (ins.rex2 & REX2_SPECIAL) == 0)
9743
1.92k
    {
9744
1.92k
      i386_dis_printf (info, dis_style_text, "(bad)");
9745
1.92k
      ret = ins.end_codep - priv.the_buffer;
9746
1.92k
      goto out;
9747
1.92k
    }
9748
9749
18.7M
  switch (dp->prefix_requirement & ~PREFIX_REX2_ILLEGAL)
9750
18.7M
    {
9751
27.6k
    case PREFIX_DATA:
9752
      /* If only the data prefix is marked as mandatory, its absence renders
9753
   the encoding invalid.  Most other PREFIX_OPCODE rules still apply.  */
9754
27.6k
      if (ins.need_vex ? !ins.vex.prefix : !(ins.prefixes & PREFIX_DATA))
9755
12.9k
  {
9756
12.9k
    i386_dis_printf (info, dis_style_text, "(bad)");
9757
12.9k
    ret = ins.end_codep - priv.the_buffer;
9758
12.9k
    goto out;
9759
12.9k
  }
9760
14.7k
      ins.used_prefixes |= PREFIX_DATA;
9761
      /* Fall through.  */
9762
46.5k
    case PREFIX_OPCODE:
9763
      /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
9764
   unused, opcode is invalid.  Since the PREFIX_DATA prefix may be
9765
   used by putop and MMX/SSE operand and may be overridden by the
9766
   PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
9767
   separately.  */
9768
46.5k
      if (((ins.need_vex
9769
46.5k
      ? ins.vex.prefix == REPE_PREFIX_OPCODE
9770
16.1k
        || ins.vex.prefix == REPNE_PREFIX_OPCODE
9771
46.5k
      : (ins.prefixes
9772
30.4k
         & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
9773
46.5k
     && (ins.used_prefixes
9774
10.7k
         & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
9775
46.5k
    || (((ins.need_vex
9776
36.6k
    ? ins.vex.prefix == DATA_PREFIX_OPCODE
9777
36.6k
    : ((ins.prefixes
9778
30.0k
        & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
9779
30.0k
       == PREFIX_DATA))
9780
36.6k
         && (ins.used_prefixes & PREFIX_DATA) == 0))
9781
46.5k
    || (ins.vex.evex && dp->prefix_requirement != PREFIX_DATA
9782
36.2k
        && !ins.vex.w != !(ins.used_prefixes & PREFIX_DATA)))
9783
10.7k
  {
9784
10.7k
    i386_dis_printf (info, dis_style_text, "(bad)");
9785
10.7k
    ret = ins.end_codep - priv.the_buffer;
9786
10.7k
    goto out;
9787
10.7k
  }
9788
35.8k
      break;
9789
9790
35.8k
    case PREFIX_IGNORED:
9791
      /* Zap data size and rep prefixes from used_prefixes and reinstate their
9792
   origins in all_prefixes.  */
9793
1.17k
      ins.used_prefixes &= ~PREFIX_OPCODE;
9794
1.17k
      if (ins.last_data_prefix >= 0)
9795
450
  ins.all_prefixes[ins.last_data_prefix] = 0x66;
9796
1.17k
      if (ins.last_repz_prefix >= 0)
9797
593
  ins.all_prefixes[ins.last_repz_prefix] = 0xf3;
9798
1.17k
      if (ins.last_repnz_prefix >= 0)
9799
588
  ins.all_prefixes[ins.last_repnz_prefix] = 0xf2;
9800
1.17k
      break;
9801
9802
88.9k
    case PREFIX_NP_OR_DATA:
9803
88.9k
      if (ins.vex.prefix == REPE_PREFIX_OPCODE
9804
88.9k
    || ins.vex.prefix == REPNE_PREFIX_OPCODE)
9805
1.61k
  {
9806
1.61k
    i386_dis_printf (info, dis_style_text, "(bad)");
9807
1.61k
    ret = ins.end_codep - priv.the_buffer;
9808
1.61k
    goto out;
9809
1.61k
  }
9810
87.3k
      break;
9811
9812
87.3k
    case NO_PREFIX:
9813
73.7k
      if (ins.vex.prefix)
9814
846
  {
9815
846
    i386_dis_printf (info, dis_style_text, "(bad)");
9816
846
    ret = ins.end_codep - priv.the_buffer;
9817
846
    goto out;
9818
846
  }
9819
72.8k
      break;
9820
18.7M
    }
9821
9822
  /* Check if the REX prefix is used.  */
9823
18.7M
  if ((ins.rex ^ ins.rex_used) == 0
9824
18.7M
      && !ins.need_vex && ins.last_rex_prefix >= 0)
9825
508k
    ins.all_prefixes[ins.last_rex_prefix] = 0;
9826
9827
  /* Check if the REX2 prefix is used.  */
9828
18.7M
  if (ins.last_rex2_prefix >= 0
9829
18.7M
      && ((ins.rex2 & REX2_SPECIAL)
9830
19.0k
    || (((ins.rex2 & 7) ^ (ins.rex2_used & 7)) == 0
9831
17.5k
        && (ins.rex ^ ins.rex_used) == 0
9832
17.5k
        && (ins.rex2 & 7))))
9833
2.59k
    ins.all_prefixes[ins.last_rex2_prefix] = 0;
9834
9835
  /* Check if the SEG prefix is used.  */
9836
18.7M
  if ((ins.prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
9837
18.7M
           | PREFIX_FS | PREFIX_GS)) != 0
9838
18.7M
      && (ins.used_prefixes & ins.active_seg_prefix) != 0)
9839
129k
    ins.all_prefixes[ins.last_seg_prefix] = 0;
9840
9841
  /* Check if the ADDR prefix is used.  */
9842
18.7M
  if ((ins.prefixes & PREFIX_ADDR) != 0
9843
18.7M
      && (ins.used_prefixes & PREFIX_ADDR) != 0)
9844
32.7k
    ins.all_prefixes[ins.last_addr_prefix] = 0;
9845
9846
  /* Check if the DATA prefix is used.  */
9847
18.7M
  if ((ins.prefixes & PREFIX_DATA) != 0
9848
18.7M
      && (ins.used_prefixes & PREFIX_DATA) != 0
9849
18.7M
      && !ins.need_vex)
9850
69.1k
    ins.all_prefixes[ins.last_data_prefix] = 0;
9851
9852
  /* Print the extra ins.prefixes.  */
9853
18.7M
  prefix_length = 0;
9854
281M
  for (i = 0; i < (int) ARRAY_SIZE (ins.all_prefixes); i++)
9855
262M
    if (ins.all_prefixes[i])
9856
807k
      {
9857
807k
  const char *name = prefix_name (ins.address_mode, ins.all_prefixes[i],
9858
807k
          orig_sizeflag);
9859
9860
807k
  if (name == NULL)
9861
0
    abort ();
9862
807k
  prefix_length += strlen (name) + 1;
9863
807k
  if (ins.all_prefixes[i] == REX2_OPCODE)
9864
16.4k
    i386_dis_printf (info, dis_style_mnemonic, "{%s 0x%x} ", name,
9865
16.4k
         (unsigned int) ins.rex2_payload);
9866
790k
  else
9867
790k
    i386_dis_printf (info, dis_style_mnemonic, "%s ", name);
9868
807k
      }
9869
9870
  /* Check maximum code length.  */
9871
18.7M
  if ((ins.codep - ins.start_codep) > MAX_CODE_LENGTH)
9872
2.42k
    {
9873
2.42k
      i386_dis_printf (info, dis_style_text, "(bad)");
9874
2.42k
      ret = MAX_CODE_LENGTH;
9875
2.42k
      goto out;
9876
2.42k
    }
9877
9878
  /* Calculate the number of operands this instruction has.  */
9879
18.7M
  op_count = 0;
9880
112M
  for (i = 0; i < MAX_OPERANDS; ++i)
9881
93.7M
    if (*ins.op_out[i] != '\0')
9882
28.5M
      ++op_count;
9883
9884
  /* Calculate the number of spaces to print after the mnemonic.  */
9885
18.7M
  ins.obufp = ins.mnemonicendp;
9886
18.7M
  if (op_count > 0)
9887
16.0M
    {
9888
16.0M
      i = strlen (ins.obuf) + prefix_length;
9889
16.0M
      if (i < 7)
9890
15.4M
  i = 7 - i;
9891
552k
      else
9892
552k
  i = 1;
9893
16.0M
    }
9894
2.69M
  else
9895
2.69M
    i = 0;
9896
9897
  /* Print the instruction mnemonic along with any trailing whitespace.  */
9898
18.7M
  i386_dis_printf (info, dis_style_mnemonic, "%s%*s", ins.obuf, i, "");
9899
9900
  /* The enter and bound instructions are printed with operands in the same
9901
     order as the intel book; everything else is printed in reverse order.  */
9902
18.7M
  intel_swap_2_3 = false;
9903
18.7M
  if (ins.intel_syntax || ins.two_source_ops)
9904
633k
    {
9905
3.80M
      for (i = 0; i < MAX_OPERANDS; ++i)
9906
3.16M
  op_txt[i] = ins.op_out[i];
9907
9908
633k
      if (ins.intel_syntax && dp && dp->op[2].rtn == OP_Rounding
9909
633k
          && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
9910
658
  {
9911
658
    op_txt[2] = ins.op_out[3];
9912
658
    op_txt[3] = ins.op_out[2];
9913
658
    intel_swap_2_3 = true;
9914
658
  }
9915
9916
1.90M
      for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
9917
1.26M
  {
9918
1.26M
    bool riprel;
9919
9920
1.26M
    ins.op_ad = ins.op_index[i];
9921
1.26M
    ins.op_index[i] = ins.op_index[MAX_OPERANDS - 1 - i];
9922
1.26M
    ins.op_index[MAX_OPERANDS - 1 - i] = ins.op_ad;
9923
1.26M
    riprel = ins.op_riprel[i];
9924
1.26M
    ins.op_riprel[i] = ins.op_riprel[MAX_OPERANDS - 1 - i];
9925
1.26M
    ins.op_riprel[MAX_OPERANDS - 1 - i] = riprel;
9926
1.26M
  }
9927
633k
    }
9928
18.1M
  else
9929
18.1M
    {
9930
108M
      for (i = 0; i < MAX_OPERANDS; ++i)
9931
90.5M
  op_txt[MAX_OPERANDS - 1 - i] = ins.op_out[i];
9932
18.1M
    }
9933
9934
18.7M
  needcomma = 0;
9935
112M
  for (i = 0; i < MAX_OPERANDS; ++i)
9936
93.7M
    if (*op_txt[i])
9937
28.5M
      {
9938
  /* In Intel syntax embedded rounding / SAE are not separate operands.
9939
     Instead they're attached to the prior register operand.  Simply
9940
     suppress emission of the comma to achieve that effect.  */
9941
28.5M
  switch (i & -(ins.intel_syntax && dp))
9942
28.5M
    {
9943
18.4k
    case 2:
9944
18.4k
      if (dp->op[2].rtn == OP_Rounding && !intel_swap_2_3)
9945
190
        needcomma = 0;
9946
18.4k
      break;
9947
3.68k
    case 3:
9948
3.68k
      if (dp->op[3].rtn == OP_Rounding || intel_swap_2_3)
9949
818
        needcomma = 0;
9950
3.68k
      break;
9951
28.5M
    }
9952
28.5M
  if (needcomma)
9953
12.4M
    i386_dis_printf (info, dis_style_text, ",");
9954
28.5M
  if (ins.op_index[i] != -1 && !ins.op_riprel[i])
9955
1.53M
    {
9956
1.53M
      bfd_vma target = (bfd_vma) ins.op_address[ins.op_index[i]];
9957
9958
1.53M
      if (ins.op_is_jump)
9959
1.53M
        {
9960
1.53M
    info->insn_info_valid = 1;
9961
1.53M
    info->branch_delay_insns = 0;
9962
1.53M
    info->data_size = 0;
9963
1.53M
    info->target = target;
9964
1.53M
    info->target2 = 0;
9965
1.53M
        }
9966
1.53M
      (*info->print_address_func) (target, info);
9967
1.53M
    }
9968
26.9M
  else
9969
26.9M
    i386_dis_printf (info, dis_style_text, "%s", op_txt[i]);
9970
28.5M
  needcomma = 1;
9971
28.5M
      }
9972
9973
112M
  for (i = 0; i < MAX_OPERANDS; i++)
9974
93.6M
    if (ins.op_index[i] != -1 && ins.op_riprel[i])
9975
208k
      {
9976
208k
  i386_dis_printf (info, dis_style_comment_start, "        # ");
9977
208k
  (*info->print_address_func)
9978
208k
    ((bfd_vma)(ins.start_pc + (ins.codep - ins.start_codep)
9979
208k
         + ins.op_address[ins.op_index[i]]),
9980
208k
    info);
9981
208k
  break;
9982
208k
      }
9983
18.7M
  ret = ins.codep - priv.the_buffer;
9984
19.1M
 out:
9985
19.1M
  info->private_data = NULL;
9986
19.1M
  return ret;
9987
18.7M
}
9988
9989
/* Here for backwards compatibility.  When gdb stops using
9990
   print_insn_i386_att and print_insn_i386_intel these functions can
9991
   disappear, and print_insn_i386 be merged into print_insn.  */
9992
int
9993
print_insn_i386_att (bfd_vma pc, disassemble_info *info)
9994
0
{
9995
0
  return print_insn (pc, info, 0);
9996
0
}
9997
9998
int
9999
print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
10000
0
{
10001
0
  return print_insn (pc, info, 1);
10002
0
}
10003
10004
int
10005
print_insn_i386 (bfd_vma pc, disassemble_info *info)
10006
19.1M
{
10007
19.1M
  return print_insn (pc, info, -1);
10008
19.1M
}
10009
10010
static const char *float_mem[] = {
10011
  /* d8 */
10012
  "fadd{s|}",
10013
  "fmul{s|}",
10014
  "fcom{s|}",
10015
  "fcomp{s|}",
10016
  "fsub{s|}",
10017
  "fsubr{s|}",
10018
  "fdiv{s|}",
10019
  "fdivr{s|}",
10020
  /* d9 */
10021
  "fld{s|}",
10022
  "(bad)",
10023
  "fst{s|}",
10024
  "fstp{s|}",
10025
  "fldenv{C|C}",
10026
  "fldcw",
10027
  "fNstenv{C|C}",
10028
  "fNstcw",
10029
  /* da */
10030
  "fiadd{l|}",
10031
  "fimul{l|}",
10032
  "ficom{l|}",
10033
  "ficomp{l|}",
10034
  "fisub{l|}",
10035
  "fisubr{l|}",
10036
  "fidiv{l|}",
10037
  "fidivr{l|}",
10038
  /* db */
10039
  "fild{l|}",
10040
  "fisttp{l|}",
10041
  "fist{l|}",
10042
  "fistp{l|}",
10043
  "(bad)",
10044
  "fld{t|}",
10045
  "(bad)",
10046
  "fstp{t|}",
10047
  /* dc */
10048
  "fadd{l|}",
10049
  "fmul{l|}",
10050
  "fcom{l|}",
10051
  "fcomp{l|}",
10052
  "fsub{l|}",
10053
  "fsubr{l|}",
10054
  "fdiv{l|}",
10055
  "fdivr{l|}",
10056
  /* dd */
10057
  "fld{l|}",
10058
  "fisttp{ll|}",
10059
  "fst{l||}",
10060
  "fstp{l|}",
10061
  "frstor{C|C}",
10062
  "(bad)",
10063
  "fNsave{C|C}",
10064
  "fNstsw",
10065
  /* de */
10066
  "fiadd{s|}",
10067
  "fimul{s|}",
10068
  "ficom{s|}",
10069
  "ficomp{s|}",
10070
  "fisub{s|}",
10071
  "fisubr{s|}",
10072
  "fidiv{s|}",
10073
  "fidivr{s|}",
10074
  /* df */
10075
  "fild{s|}",
10076
  "fisttp{s|}",
10077
  "fist{s|}",
10078
  "fistp{s|}",
10079
  "fbld",
10080
  "fild{ll|}",
10081
  "fbstp",
10082
  "fistp{ll|}",
10083
};
10084
10085
static const unsigned char float_mem_mode[] = {
10086
  /* d8 */
10087
  d_mode,
10088
  d_mode,
10089
  d_mode,
10090
  d_mode,
10091
  d_mode,
10092
  d_mode,
10093
  d_mode,
10094
  d_mode,
10095
  /* d9 */
10096
  d_mode,
10097
  0,
10098
  d_mode,
10099
  d_mode,
10100
  0,
10101
  w_mode,
10102
  0,
10103
  w_mode,
10104
  /* da */
10105
  d_mode,
10106
  d_mode,
10107
  d_mode,
10108
  d_mode,
10109
  d_mode,
10110
  d_mode,
10111
  d_mode,
10112
  d_mode,
10113
  /* db */
10114
  d_mode,
10115
  d_mode,
10116
  d_mode,
10117
  d_mode,
10118
  0,
10119
  t_mode,
10120
  0,
10121
  t_mode,
10122
  /* dc */
10123
  q_mode,
10124
  q_mode,
10125
  q_mode,
10126
  q_mode,
10127
  q_mode,
10128
  q_mode,
10129
  q_mode,
10130
  q_mode,
10131
  /* dd */
10132
  q_mode,
10133
  q_mode,
10134
  q_mode,
10135
  q_mode,
10136
  0,
10137
  0,
10138
  0,
10139
  w_mode,
10140
  /* de */
10141
  w_mode,
10142
  w_mode,
10143
  w_mode,
10144
  w_mode,
10145
  w_mode,
10146
  w_mode,
10147
  w_mode,
10148
  w_mode,
10149
  /* df */
10150
  w_mode,
10151
  w_mode,
10152
  w_mode,
10153
  w_mode,
10154
  t_mode,
10155
  q_mode,
10156
  t_mode,
10157
  q_mode
10158
};
10159
10160
#define ST { OP_ST, 0 }
10161
#define STi { OP_STi, 0 }
10162
10163
#define FGRPd9_2 NULL, { { NULL, 1 } }, 0
10164
#define FGRPd9_4 NULL, { { NULL, 2 } }, 0
10165
#define FGRPd9_5 NULL, { { NULL, 3 } }, 0
10166
#define FGRPd9_6 NULL, { { NULL, 4 } }, 0
10167
#define FGRPd9_7 NULL, { { NULL, 5 } }, 0
10168
#define FGRPda_5 NULL, { { NULL, 6 } }, 0
10169
#define FGRPdb_4 NULL, { { NULL, 7 } }, 0
10170
#define FGRPde_3 NULL, { { NULL, 8 } }, 0
10171
#define FGRPdf_4 NULL, { { NULL, 9 } }, 0
10172
10173
static const struct dis386 float_reg[][8] = {
10174
  /* d8 */
10175
  {
10176
    { "fadd", { ST, STi }, 0 },
10177
    { "fmul", { ST, STi }, 0 },
10178
    { "fcom", { STi }, 0 },
10179
    { "fcomp",  { STi }, 0 },
10180
    { "fsub", { ST, STi }, 0 },
10181
    { "fsubr",  { ST, STi }, 0 },
10182
    { "fdiv", { ST, STi }, 0 },
10183
    { "fdivr",  { ST, STi }, 0 },
10184
  },
10185
  /* d9 */
10186
  {
10187
    { "fld",  { STi }, 0 },
10188
    { "fxch", { STi }, 0 },
10189
    { FGRPd9_2 },
10190
    { Bad_Opcode },
10191
    { FGRPd9_4 },
10192
    { FGRPd9_5 },
10193
    { FGRPd9_6 },
10194
    { FGRPd9_7 },
10195
  },
10196
  /* da */
10197
  {
10198
    { "fcmovb", { ST, STi }, 0 },
10199
    { "fcmove", { ST, STi }, 0 },
10200
    { "fcmovbe",{ ST, STi }, 0 },
10201
    { "fcmovu", { ST, STi }, 0 },
10202
    { Bad_Opcode },
10203
    { FGRPda_5 },
10204
    { Bad_Opcode },
10205
    { Bad_Opcode },
10206
  },
10207
  /* db */
10208
  {
10209
    { "fcmovnb",{ ST, STi }, 0 },
10210
    { "fcmovne",{ ST, STi }, 0 },
10211
    { "fcmovnbe",{ ST, STi }, 0 },
10212
    { "fcmovnu",{ ST, STi }, 0 },
10213
    { FGRPdb_4 },
10214
    { "fucomi", { ST, STi }, 0 },
10215
    { "fcomi",  { ST, STi }, 0 },
10216
    { Bad_Opcode },
10217
  },
10218
  /* dc */
10219
  {
10220
    { "fadd", { STi, ST }, 0 },
10221
    { "fmul", { STi, ST }, 0 },
10222
    { Bad_Opcode },
10223
    { Bad_Opcode },
10224
    { "fsub{!M|r}", { STi, ST }, 0 },
10225
    { "fsub{M|}", { STi, ST }, 0 },
10226
    { "fdiv{!M|r}", { STi, ST }, 0 },
10227
    { "fdiv{M|}", { STi, ST }, 0 },
10228
  },
10229
  /* dd */
10230
  {
10231
    { "ffree",  { STi }, 0 },
10232
    { Bad_Opcode },
10233
    { "fst",  { STi }, 0 },
10234
    { "fstp", { STi }, 0 },
10235
    { "fucom",  { STi }, 0 },
10236
    { "fucomp", { STi }, 0 },
10237
    { Bad_Opcode },
10238
    { Bad_Opcode },
10239
  },
10240
  /* de */
10241
  {
10242
    { "faddp",  { STi, ST }, 0 },
10243
    { "fmulp",  { STi, ST }, 0 },
10244
    { Bad_Opcode },
10245
    { FGRPde_3 },
10246
    { "fsub{!M|r}p",  { STi, ST }, 0 },
10247
    { "fsub{M|}p",  { STi, ST }, 0 },
10248
    { "fdiv{!M|r}p",  { STi, ST }, 0 },
10249
    { "fdiv{M|}p",  { STi, ST }, 0 },
10250
  },
10251
  /* df */
10252
  {
10253
    { "ffreep", { STi }, 0 },
10254
    { Bad_Opcode },
10255
    { Bad_Opcode },
10256
    { Bad_Opcode },
10257
    { FGRPdf_4 },
10258
    { "fucomip", { ST, STi }, 0 },
10259
    { "fcomip", { ST, STi }, 0 },
10260
    { Bad_Opcode },
10261
  },
10262
};
10263
10264
static const char *const fgrps[][8] = {
10265
  /* Bad opcode 0 */
10266
  {
10267
    "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10268
  },
10269
10270
  /* d9_2  1 */
10271
  {
10272
    "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10273
  },
10274
10275
  /* d9_4  2 */
10276
  {
10277
    "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
10278
  },
10279
10280
  /* d9_5  3 */
10281
  {
10282
    "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
10283
  },
10284
10285
  /* d9_6  4 */
10286
  {
10287
    "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
10288
  },
10289
10290
  /* d9_7  5 */
10291
  {
10292
    "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
10293
  },
10294
10295
  /* da_5  6 */
10296
  {
10297
    "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10298
  },
10299
10300
  /* db_4  7 */
10301
  {
10302
    "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
10303
    "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
10304
  },
10305
10306
  /* de_3  8 */
10307
  {
10308
    "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10309
  },
10310
10311
  /* df_4  9 */
10312
  {
10313
    "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10314
  },
10315
};
10316
10317
static void
10318
swap_operand (instr_info *ins)
10319
1.78k
{
10320
1.78k
  ins->mnemonicendp[0] = '.';
10321
1.78k
  ins->mnemonicendp[1] = 's';
10322
1.78k
  ins->mnemonicendp[2] = '\0';
10323
1.78k
  ins->mnemonicendp += 2;
10324
1.78k
}
10325
10326
static bool
10327
dofloat (instr_info *ins, int sizeflag)
10328
221k
{
10329
221k
  const struct dis386 *dp;
10330
221k
  unsigned char floatop = ins->codep[-1];
10331
10332
221k
  if (ins->modrm.mod != 3)
10333
122k
    {
10334
122k
      int fp_indx = (floatop - 0xd8) * 8 + ins->modrm.reg;
10335
10336
122k
      putop (ins, float_mem[fp_indx], sizeflag);
10337
122k
      ins->obufp = ins->op_out[0];
10338
122k
      ins->op_ad = 2;
10339
122k
      return OP_E (ins, float_mem_mode[fp_indx], sizeflag);
10340
122k
    }
10341
  /* Skip mod/rm byte.  */
10342
99.1k
  MODRM_CHECK;
10343
99.1k
  ins->codep++;
10344
10345
99.1k
  dp = &float_reg[floatop - 0xd8][ins->modrm.reg];
10346
99.1k
  if (dp->name == NULL)
10347
24.7k
    {
10348
24.7k
      putop (ins, fgrps[dp->op[0].bytemode][ins->modrm.rm], sizeflag);
10349
10350
      /* Instruction fnstsw is only one with strange arg.  */
10351
24.7k
      if (floatop == 0xdf && ins->codep[-1] == 0xe0)
10352
3.24k
  strcpy (ins->op_out[0], att_names16[0] + ins->intel_syntax);
10353
24.7k
    }
10354
74.3k
  else
10355
74.3k
    {
10356
74.3k
      putop (ins, dp->name, sizeflag);
10357
10358
74.3k
      ins->obufp = ins->op_out[0];
10359
74.3k
      ins->op_ad = 2;
10360
74.3k
      if (dp->op[0].rtn
10361
74.3k
    && !dp->op[0].rtn (ins, dp->op[0].bytemode, sizeflag))
10362
0
  return false;
10363
10364
74.3k
      ins->obufp = ins->op_out[1];
10365
74.3k
      ins->op_ad = 1;
10366
74.3k
      if (dp->op[1].rtn
10367
74.3k
    && !dp->op[1].rtn (ins, dp->op[1].bytemode, sizeflag))
10368
0
  return false;
10369
74.3k
    }
10370
99.1k
  return true;
10371
99.1k
}
10372
10373
static bool
10374
OP_ST (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
10375
       int sizeflag ATTRIBUTE_UNUSED)
10376
52.8k
{
10377
52.8k
  oappend_register (ins, "%st");
10378
52.8k
  return true;
10379
52.8k
}
10380
10381
static bool
10382
OP_STi (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
10383
  int sizeflag ATTRIBUTE_UNUSED)
10384
74.3k
{
10385
74.3k
  char scratch[8];
10386
74.3k
  int res = snprintf (scratch, ARRAY_SIZE (scratch), "%%st(%d)", ins->modrm.rm);
10387
10388
74.3k
  if (res < 0 || (size_t) res >= ARRAY_SIZE (scratch))
10389
0
    abort ();
10390
74.3k
  oappend_register (ins, scratch);
10391
74.3k
  return true;
10392
74.3k
}
10393
10394
/* Capital letters in template are macros.  */
10395
static int
10396
putop (instr_info *ins, const char *in_template, int sizeflag)
10397
18.8M
{
10398
18.8M
  const char *p;
10399
18.8M
  int alt = 0;
10400
18.8M
  int cond = 1;
10401
18.8M
  unsigned int l = 0, len = 0;
10402
18.8M
  char last[4];
10403
18.8M
  bool evex_printed = false;
10404
10405
  /* We don't want to add any prefix or suffix to (bad), so return early.  */
10406
18.8M
  if (!strncmp (in_template, "(bad)", 5))
10407
1.99M
    {
10408
1.99M
      oappend (ins, "(bad)");
10409
1.99M
      *ins->obufp = 0;
10410
1.99M
      ins->mnemonicendp = ins->obufp;
10411
1.99M
      return 0;
10412
1.99M
    }
10413
10414
90.8M
  for (p = in_template; *p; p++)
10415
73.9M
    {
10416
73.9M
      if (len > l)
10417
573k
  {
10418
573k
    if (l >= sizeof (last) || !ISUPPER (*p))
10419
0
      abort ();
10420
573k
    last[l++] = *p;
10421
573k
    continue;
10422
573k
  }
10423
73.4M
      switch (*p)
10424
73.4M
  {
10425
53.3M
  default:
10426
53.3M
    if (ins->evex_type == evex_from_legacy && !ins->vex.nd
10427
53.3M
        && !(ins->rex2 & 7) && !evex_printed)
10428
240
      {
10429
240
        oappend (ins, "{evex} ");
10430
240
        evex_printed = true;
10431
240
      }
10432
53.3M
    *ins->obufp++ = *p;
10433
53.3M
    break;
10434
573k
  case '%':
10435
573k
    len++;
10436
573k
    break;
10437
954k
  case '!':
10438
954k
    cond = 0;
10439
954k
    break;
10440
1.23M
  case '{':
10441
1.23M
    if (ins->intel_syntax)
10442
64.9k
      {
10443
129k
        while (*++p != '|')
10444
64.4k
    if (*p == '}' || *p == '\0')
10445
0
      abort ();
10446
64.9k
        alt = 1;
10447
64.9k
      }
10448
1.23M
    break;
10449
1.23M
  case '|':
10450
1.24M
    while (*++p != '}')
10451
75.1k
      {
10452
75.1k
        if (*p == '\0')
10453
0
    abort ();
10454
75.1k
      }
10455
1.17M
    break;
10456
1.17M
  case '}':
10457
64.8k
    alt = 0;
10458
64.8k
    break;
10459
263k
  case 'A':
10460
263k
    if (ins->intel_syntax)
10461
5.88k
      break;
10462
257k
    if ((ins->need_modrm && ins->modrm.mod != 3 && !ins->vex.nd)
10463
257k
        || (sizeflag & SUFFIX_ALWAYS))
10464
197k
      *ins->obufp++ = 'b';
10465
257k
    break;
10466
7.39M
  case 'B':
10467
7.39M
    if (l == 0)
10468
7.34M
      {
10469
7.39M
      case_B:
10470
7.39M
        if (ins->intel_syntax)
10471
161k
    break;
10472
7.23M
        if (sizeflag & SUFFIX_ALWAYS)
10473
3.66k
    *ins->obufp++ = 'b';
10474
7.23M
      }
10475
48.2k
    else if (l == 1 && last[0] == 'L')
10476
48.2k
      {
10477
48.2k
        if (ins->address_mode == mode_64bit
10478
48.2k
      && !(ins->prefixes & PREFIX_ADDR))
10479
38.1k
    {
10480
38.1k
      *ins->obufp++ = 'a';
10481
38.1k
      *ins->obufp++ = 'b';
10482
38.1k
      *ins->obufp++ = 's';
10483
38.1k
    }
10484
10485
48.2k
        goto case_B;
10486
48.2k
      }
10487
0
    else
10488
0
      abort ();
10489
7.23M
    break;
10490
7.23M
  case 'C':
10491
4.72k
    if (ins->intel_syntax && !alt)
10492
0
      break;
10493
4.72k
    if ((ins->prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
10494
636
      {
10495
636
        if (sizeflag & DFLAG)
10496
256
    *ins->obufp++ = ins->intel_syntax ? 'd' : 'l';
10497
380
        else
10498
380
    *ins->obufp++ = ins->intel_syntax ? 'w' : 's';
10499
636
        ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10500
636
      }
10501
4.72k
    break;
10502
66.2k
  case 'D':
10503
66.2k
    if (l == 1)
10504
3.23k
      {
10505
3.23k
        switch (last[0])
10506
3.23k
        {
10507
3.23k
        case 'X':
10508
3.23k
    if (!ins->vex.evex || ins->vex.w)
10509
2.99k
      *ins->obufp++ = 'd';
10510
236
    else
10511
236
      oappend (ins, "{bad}");
10512
3.23k
    break;
10513
0
        default:
10514
0
    abort ();
10515
3.23k
        }
10516
3.23k
        break;
10517
3.23k
      }
10518
63.0k
    if (l)
10519
0
      abort ();
10520
63.0k
    if (ins->intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
10521
62.0k
      break;
10522
1.02k
    USED_REX (REX_W);
10523
1.02k
    if (ins->modrm.mod == 3)
10524
674
      {
10525
674
        if (ins->rex & REX_W)
10526
248
    *ins->obufp++ = 'q';
10527
426
        else
10528
426
    {
10529
426
      if (sizeflag & DFLAG)
10530
230
        *ins->obufp++ = ins->intel_syntax ? 'd' : 'l';
10531
196
      else
10532
196
        *ins->obufp++ = 'w';
10533
426
      ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10534
426
    }
10535
674
      }
10536
352
    else
10537
352
      *ins->obufp++ = 'w';
10538
1.02k
    break;
10539
49.7k
  case 'E':
10540
49.7k
    if (l == 1)
10541
30.3k
      {
10542
30.3k
        switch (last[0])
10543
30.3k
    {
10544
29.6k
    case 'X':
10545
29.6k
      if (!ins->vex.evex || ins->vex.b || ins->vex.ll >= 2
10546
29.6k
          || (ins->rex2 & 7)
10547
29.6k
          || (ins->modrm.mod == 3 && (ins->rex & REX_X))
10548
29.6k
          || !ins->vex.v || ins->vex.mask_register_specifier)
10549
28.5k
        break;
10550
      /* AVX512 extends a number of V*D insns to also have V*Q variants,
10551
         merely distinguished by EVEX.W.  Look for a use of the
10552
         respective macro.  */
10553
1.15k
      if (ins->vex.w)
10554
621
        {
10555
621
          const char *pct = strchr (p + 1, '%');
10556
10557
621
          if (pct != NULL && pct[1] == 'D' && pct[2] == 'Q')
10558
190
      break;
10559
621
        }
10560
961
      *ins->obufp++ = '{';
10561
961
      *ins->obufp++ = 'e';
10562
961
      *ins->obufp++ = 'v';
10563
961
      *ins->obufp++ = 'e';
10564
961
      *ins->obufp++ = 'x';
10565
961
      *ins->obufp++ = '}';
10566
961
      *ins->obufp++ = ' ';
10567
961
      break;
10568
666
    case 'M':
10569
666
      if (ins->modrm.mod != 3 && !(ins->rex2 & 7))
10570
196
        oappend (ins, "{evex} ");
10571
666
      evex_printed = true;
10572
666
      break;
10573
0
    default:
10574
0
      abort ();
10575
30.3k
    }
10576
30.3k
    break;
10577
30.3k
      }
10578
    /* For jcxz/jecxz */
10579
19.4k
    if (ins->address_mode == mode_64bit)
10580
14.7k
      {
10581
14.7k
        if (sizeflag & AFLAG)
10582
14.4k
    *ins->obufp++ = 'r';
10583
281
        else
10584
281
    *ins->obufp++ = 'e';
10585
14.7k
      }
10586
4.68k
    else
10587
4.68k
      if (sizeflag & AFLAG)
10588
3.18k
        *ins->obufp++ = 'e';
10589
19.4k
    ins->used_prefixes |= (ins->prefixes & PREFIX_ADDR);
10590
19.4k
    break;
10591
213k
  case 'F':
10592
213k
    if (l == 0)
10593
83.7k
      {
10594
83.7k
        if (ins->intel_syntax)
10595
6.96k
    break;
10596
76.7k
        if ((ins->prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
10597
691
    {
10598
691
      if (sizeflag & AFLAG)
10599
234
        *ins->obufp++ = ins->address_mode == mode_64bit ? 'q' : 'l';
10600
457
      else
10601
457
        *ins->obufp++ = ins->address_mode == mode_64bit ? 'l' : 'w';
10602
691
      ins->used_prefixes |= (ins->prefixes & PREFIX_ADDR);
10603
691
    }
10604
76.7k
      }
10605
129k
    else if (l == 1 && last[0] == 'C')
10606
2.36k
      break;
10607
127k
    else if (l == 1 && last[0] == 'N')
10608
127k
      {
10609
127k
        if (ins->vex.nf)
10610
658
    {
10611
658
      oappend (ins, "{nf} ");
10612
      /* This bit needs to be cleared after it is consumed.  */
10613
658
      ins->vex.nf = false;
10614
658
      evex_printed = true;
10615
658
    }
10616
126k
        else if (ins->evex_type == evex_from_vex && !(ins->rex2 & 7)
10617
126k
           && ins->vex.v)
10618
190
    {
10619
190
      oappend (ins, "{evex} ");
10620
190
      evex_printed = true;
10621
190
    }
10622
127k
      }
10623
0
    else
10624
0
      abort ();
10625
204k
    break;
10626
204k
  case 'G':
10627
176k
    if (ins->intel_syntax || (ins->obufp[-1] != 's'
10628
168k
            && !(sizeflag & SUFFIX_ALWAYS)))
10629
79.0k
      break;
10630
97.6k
    if ((ins->rex & REX_W) || (sizeflag & DFLAG))
10631
94.8k
      *ins->obufp++ = 'l';
10632
2.72k
    else
10633
2.72k
      *ins->obufp++ = 'w';
10634
97.6k
    if (!(ins->rex & REX_W))
10635
96.6k
      ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10636
97.6k
    break;
10637
1.22M
  case 'H':
10638
1.22M
    if (l == 0)
10639
1.21M
      {
10640
1.21M
        if (ins->intel_syntax)
10641
32.6k
          break;
10642
1.18M
        if ((ins->prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
10643
1.18M
      || (ins->prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
10644
20.6k
    {
10645
20.6k
      ins->used_prefixes |= ins->prefixes & (PREFIX_CS | PREFIX_DS);
10646
20.6k
      *ins->obufp++ = ',';
10647
20.6k
      *ins->obufp++ = 'p';
10648
10649
      /* Set active_seg_prefix even if not set in 64-bit mode
10650
         because here it is a valid branch hint. */
10651
20.6k
      if (ins->prefixes & PREFIX_DS)
10652
1.49k
        {
10653
1.49k
          ins->active_seg_prefix = PREFIX_DS;
10654
1.49k
          *ins->obufp++ = 't';
10655
1.49k
        }
10656
19.1k
      else
10657
19.1k
        {
10658
19.1k
          ins->active_seg_prefix = PREFIX_CS;
10659
19.1k
          *ins->obufp++ = 'n';
10660
19.1k
        }
10661
20.6k
    }
10662
1.18M
      }
10663
11.5k
    else if (l == 1 && last[0] == 'X')
10664
11.5k
      {
10665
11.5k
        if (!ins->vex.w)
10666
5.71k
    *ins->obufp++ = 'h';
10667
5.79k
        else
10668
5.79k
    oappend (ins, "{bad}");
10669
11.5k
      }
10670
0
    else
10671
0
      abort ();
10672
1.19M
    break;
10673
1.19M
  case 'K':
10674
1.50k
    USED_REX (REX_W);
10675
1.50k
    if (ins->rex & REX_W)
10676
582
      *ins->obufp++ = 'q';
10677
918
    else
10678
918
      *ins->obufp++ = 'd';
10679
1.50k
    break;
10680
948
  case 'L':
10681
948
    if (ins->intel_syntax)
10682
216
      break;
10683
732
    if (sizeflag & SUFFIX_ALWAYS)
10684
382
      {
10685
382
        if (ins->rex & REX_W)
10686
190
    *ins->obufp++ = 'q';
10687
192
        else
10688
192
    *ins->obufp++ = 'l';
10689
382
      }
10690
732
    break;
10691
5.26k
  case 'M':
10692
5.26k
    if (ins->intel_mnemonic != cond)
10693
2.76k
      *ins->obufp++ = 'r';
10694
5.26k
    break;
10695
10.1k
  case 'N':
10696
10.1k
    if ((ins->prefixes & PREFIX_FWAIT) == 0)
10697
8.80k
      *ins->obufp++ = 'n';
10698
1.33k
    else
10699
1.33k
      ins->used_prefixes |= PREFIX_FWAIT;
10700
10.1k
    break;
10701
18.5k
  case 'O':
10702
18.5k
    USED_REX (REX_W);
10703
18.5k
    if (ins->rex & REX_W)
10704
643
      *ins->obufp++ = 'o';
10705
17.9k
    else if (ins->intel_syntax && (sizeflag & DFLAG))
10706
1.30k
      *ins->obufp++ = 'q';
10707
16.6k
    else
10708
16.6k
      *ins->obufp++ = 'd';
10709
18.5k
    if (!(ins->rex & REX_W))
10710
17.9k
      ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10711
18.5k
    break;
10712
238k
  case '@':
10713
238k
    if (ins->address_mode == mode_64bit
10714
238k
        && (ins->isa64 == intel64 || (ins->rex & REX_W)
10715
219k
      || !(ins->prefixes & PREFIX_DATA)))
10716
218k
      {
10717
218k
        if (sizeflag & SUFFIX_ALWAYS)
10718
386
    *ins->obufp++ = 'q';
10719
218k
        break;
10720
218k
      }
10721
    /* Fall through.  */
10722
1.65M
  case 'P':
10723
1.65M
    if (l == 0)
10724
1.59M
      {
10725
1.59M
        if (!cond && ins->last_rex2_prefix >= 0 && (ins->rex & REX_W))
10726
232
    {
10727
      /* For pushp and popp, p is printed and do not print {rex2}
10728
         for them.  */
10729
232
      *ins->obufp++ = 'p';
10730
232
      ins->rex2 |= REX2_SPECIAL;
10731
232
      break;
10732
232
    }
10733
10734
        /* For "!P" print nothing else in Intel syntax.  */
10735
1.58M
        if (!cond && ins->intel_syntax)
10736
24.8k
    break;
10737
10738
1.56M
        if ((ins->modrm.mod == 3 || !cond)
10739
1.56M
      && !(sizeflag & SUFFIX_ALWAYS))
10740
935k
    break;
10741
    /* Fall through.  */
10742
630k
  case 'T':
10743
630k
        if ((!(ins->rex & REX_W) && (ins->prefixes & PREFIX_DATA))
10744
630k
      || ((sizeflag & SUFFIX_ALWAYS)
10745
627k
          && ins->address_mode != mode_64bit))
10746
3.79k
    {
10747
3.79k
      *ins->obufp++ = (sizeflag & DFLAG)
10748
3.79k
          ? ins->intel_syntax ? 'd' : 'l' : 'w';
10749
3.79k
      ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10750
3.79k
    }
10751
626k
        else if (sizeflag & SUFFIX_ALWAYS)
10752
528
    *ins->obufp++ = 'q';
10753
630k
      }
10754
64.6k
    else if (l == 1 && last[0] == 'L')
10755
64.6k
      {
10756
64.6k
        if ((ins->prefixes & PREFIX_DATA)
10757
64.6k
      || (ins->rex & REX_W)
10758
64.6k
      || (sizeflag & SUFFIX_ALWAYS))
10759
2.72k
    {
10760
2.72k
      USED_REX (REX_W);
10761
2.72k
      if (ins->rex & REX_W)
10762
1.40k
        *ins->obufp++ = 'q';
10763
1.31k
      else
10764
1.31k
        {
10765
1.31k
          if (sizeflag & DFLAG)
10766
453
      *ins->obufp++ = ins->intel_syntax ? 'd' : 'l';
10767
865
          else
10768
865
      *ins->obufp++ = 'w';
10769
1.31k
          ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10770
1.31k
        }
10771
2.72k
    }
10772
64.6k
      }
10773
0
    else
10774
0
      abort ();
10775
695k
    break;
10776
695k
  case 'Q':
10777
481k
    if (l == 0)
10778
472k
      {
10779
472k
        if (ins->intel_syntax && !alt)
10780
16.2k
    break;
10781
456k
        USED_REX (REX_W);
10782
456k
        if ((ins->need_modrm && ins->modrm.mod != 3 && !ins->vex.nd)
10783
456k
      || (sizeflag & SUFFIX_ALWAYS))
10784
252k
    {
10785
252k
      if (ins->rex & REX_W)
10786
12.4k
        *ins->obufp++ = 'q';
10787
240k
      else
10788
240k
        {
10789
240k
          if (sizeflag & DFLAG)
10790
227k
      *ins->obufp++ = ins->intel_syntax ? 'd' : 'l';
10791
13.4k
          else
10792
13.4k
      *ins->obufp++ = 'w';
10793
240k
          ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10794
240k
        }
10795
252k
    }
10796
456k
      }
10797
8.87k
    else if (l == 1 && last[0] == 'D')
10798
5.69k
      *ins->obufp++ = ins->vex.w ? 'q' : 'd';
10799
3.17k
    else if (l == 1 && last[0] == 'L')
10800
3.17k
      {
10801
3.17k
        if (cond ? ins->modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)
10802
3.17k
           : ins->address_mode != mode_64bit)
10803
802
    break;
10804
2.37k
        if ((ins->rex & REX_W))
10805
461
    {
10806
461
      USED_REX (REX_W);
10807
461
      *ins->obufp++ = 'q';
10808
461
    }
10809
1.90k
        else if ((ins->address_mode == mode_64bit && cond)
10810
1.90k
          || (sizeflag & SUFFIX_ALWAYS))
10811
1.09k
    *ins->obufp++ = ins->intel_syntax? 'd' : 'l';
10812
2.37k
      }
10813
0
    else
10814
0
      abort ();
10815
464k
    break;
10816
464k
  case 'R':
10817
147k
    USED_REX (REX_W);
10818
147k
    if (ins->rex & REX_W)
10819
2.60k
      *ins->obufp++ = 'q';
10820
144k
    else if (sizeflag & DFLAG)
10821
136k
      {
10822
136k
        if (ins->intel_syntax)
10823
3.26k
      *ins->obufp++ = 'd';
10824
133k
        else
10825
133k
      *ins->obufp++ = 'l';
10826
136k
      }
10827
7.92k
    else
10828
7.92k
      *ins->obufp++ = 'w';
10829
147k
    if (ins->intel_syntax && !p[1]
10830
147k
        && ((ins->rex & REX_W) || (sizeflag & DFLAG)))
10831
2.19k
      *ins->obufp++ = 'e';
10832
147k
    if (!(ins->rex & REX_W))
10833
144k
      ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10834
147k
    break;
10835
3.83M
  case 'S':
10836
3.83M
    if (l == 0)
10837
3.78M
      {
10838
4.04M
      case_S:
10839
4.04M
        if (ins->intel_syntax)
10840
81.4k
    break;
10841
3.96M
        if (sizeflag & SUFFIX_ALWAYS)
10842
1.15k
    {
10843
1.15k
      if (ins->rex & REX_W)
10844
258
        *ins->obufp++ = 'q';
10845
896
      else
10846
896
        {
10847
896
          if (sizeflag & DFLAG)
10848
540
      *ins->obufp++ = 'l';
10849
356
          else
10850
356
      *ins->obufp++ = 'w';
10851
896
          ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10852
896
        }
10853
1.15k
    }
10854
3.96M
        break;
10855
4.04M
      }
10856
53.0k
    if (l != 1)
10857
0
      abort ();
10858
53.0k
    switch (last[0])
10859
53.0k
      {
10860
48.9k
      case 'L':
10861
48.9k
        if (ins->address_mode == mode_64bit
10862
48.9k
      && !(ins->prefixes & PREFIX_ADDR))
10863
26.3k
    {
10864
26.3k
      *ins->obufp++ = 'a';
10865
26.3k
      *ins->obufp++ = 'b';
10866
26.3k
      *ins->obufp++ = 's';
10867
26.3k
    }
10868
10869
48.9k
        goto case_S;
10870
4.12k
      case 'X':
10871
4.12k
        if (!ins->vex.evex || !ins->vex.w)
10872
2.12k
    *ins->obufp++ = 's';
10873
2.00k
        else
10874
2.00k
    oappend (ins, "{bad}");
10875
4.12k
        break;
10876
0
      default:
10877
0
        abort ();
10878
53.0k
      }
10879
4.12k
    break;
10880
228k
  case 'V':
10881
228k
    if (l == 0)
10882
18.5k
      {
10883
18.5k
        if (ins->need_vex)
10884
10.1k
    *ins->obufp++ = 'v';
10885
18.5k
      }
10886
209k
    else if (l == 1)
10887
209k
      {
10888
209k
        switch (last[0])
10889
209k
    {
10890
661
    case 'X':
10891
661
      if (ins->vex.evex)
10892
254
        break;
10893
407
      *ins->obufp++ = '{';
10894
407
      *ins->obufp++ = 'v';
10895
407
      *ins->obufp++ = 'e';
10896
407
      *ins->obufp++ = 'x';
10897
407
      *ins->obufp++ = '}';
10898
407
      *ins->obufp++ = ' ';
10899
407
      break;
10900
208k
    case 'L':
10901
208k
      if (ins->rex & REX_W)
10902
5.96k
        {
10903
5.96k
          *ins->obufp++ = 'a';
10904
5.96k
          *ins->obufp++ = 'b';
10905
5.96k
          *ins->obufp++ = 's';
10906
5.96k
        }
10907
208k
      goto case_S;
10908
0
    default:
10909
0
      abort ();
10910
209k
    }
10911
209k
      }
10912
0
    else
10913
0
      abort ();
10914
19.2k
    break;
10915
38.3k
  case 'W':
10916
38.3k
    if (l == 0)
10917
30.3k
      {
10918
        /* operand size flag for cwtl, cbtw */
10919
30.3k
        USED_REX (REX_W);
10920
30.3k
        if (ins->rex & REX_W)
10921
1.23k
    {
10922
1.23k
      if (ins->intel_syntax)
10923
242
        *ins->obufp++ = 'd';
10924
996
      else
10925
996
        *ins->obufp++ = 'l';
10926
1.23k
    }
10927
29.1k
        else if (sizeflag & DFLAG)
10928
27.6k
    *ins->obufp++ = 'w';
10929
1.47k
        else
10930
1.47k
    *ins->obufp++ = 'b';
10931
30.3k
        if (!(ins->rex & REX_W))
10932
29.1k
    ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10933
30.3k
      }
10934
8.00k
    else if (l == 1)
10935
8.00k
      {
10936
8.00k
        if (!ins->need_vex)
10937
0
    abort ();
10938
8.00k
        if (last[0] == 'X')
10939
6.66k
    *ins->obufp++ = ins->vex.w ? 'd': 's';
10940
1.34k
        else if (last[0] == 'B')
10941
1.34k
    *ins->obufp++ = ins->vex.w ? 'w': 'b';
10942
0
        else
10943
0
    abort ();
10944
8.00k
      }
10945
0
    else
10946
0
      abort ();
10947
38.3k
    break;
10948
38.3k
  case 'X':
10949
19.1k
    if (l != 0)
10950
0
      abort ();
10951
19.1k
    if (ins->need_vex
10952
19.1k
        ? ins->vex.prefix == DATA_PREFIX_OPCODE
10953
19.1k
        : ins->prefixes & PREFIX_DATA)
10954
4.00k
      {
10955
4.00k
        *ins->obufp++ = 'd';
10956
4.00k
        ins->used_prefixes |= PREFIX_DATA;
10957
4.00k
      }
10958
15.0k
    else
10959
15.0k
      *ins->obufp++ = 's';
10960
19.1k
    break;
10961
9.04k
  case 'Y':
10962
9.04k
    if (l == 0)
10963
6.17k
      {
10964
6.17k
        if (ins->vex.mask_register_specifier)
10965
2.47k
    ins->illegal_masking = true;
10966
6.17k
      }
10967
2.86k
    else if (l == 1 && last[0] == 'X')
10968
2.86k
      {
10969
2.86k
        if (!ins->need_vex)
10970
218
    break;
10971
2.65k
        if (ins->intel_syntax
10972
2.65k
      || ((ins->modrm.mod == 3 || ins->vex.b)
10973
1.57k
          && !(sizeflag & SUFFIX_ALWAYS)))
10974
1.63k
    break;
10975
1.01k
        switch (ins->vex.length)
10976
1.01k
    {
10977
437
    case 128:
10978
437
      *ins->obufp++ = 'x';
10979
437
      break;
10980
387
    case 256:
10981
387
      *ins->obufp++ = 'y';
10982
387
      break;
10983
190
    case 512:
10984
190
      if (!ins->vex.evex)
10985
0
    default:
10986
0
        abort ();
10987
1.01k
    }
10988
1.01k
      }
10989
0
    else
10990
0
      abort ();
10991
7.18k
    break;
10992
7.24k
  case 'Z':
10993
7.24k
    if (l == 0)
10994
3.97k
      {
10995
        /* These insns ignore ModR/M.mod: Force it to 3 for OP_E().  */
10996
3.97k
        ins->modrm.mod = 3;
10997
3.97k
        if (!ins->intel_syntax && (sizeflag & SUFFIX_ALWAYS))
10998
194
    *ins->obufp++ = ins->address_mode == mode_64bit ? 'q' : 'l';
10999
3.97k
      }
11000
3.27k
    else if (l == 1 && last[0] == 'X')
11001
3.27k
      {
11002
3.27k
        if (!ins->vex.evex)
11003
0
    abort ();
11004
3.27k
        if (ins->intel_syntax
11005
3.27k
      || ((ins->modrm.mod == 3 || ins->vex.b)
11006
2.14k
          && !(sizeflag & SUFFIX_ALWAYS)))
11007
1.62k
    break;
11008
1.64k
        switch (ins->vex.length)
11009
1.64k
    {
11010
397
    case 128:
11011
397
      *ins->obufp++ = 'x';
11012
397
      break;
11013
384
    case 256:
11014
384
      *ins->obufp++ = 'y';
11015
384
      break;
11016
868
    case 512:
11017
868
      *ins->obufp++ = 'z';
11018
868
      break;
11019
0
    default:
11020
0
      abort ();
11021
1.64k
    }
11022
1.64k
      }
11023
0
    else
11024
0
      abort ();
11025
5.62k
    break;
11026
29.0k
  case '^':
11027
29.0k
    if (ins->intel_syntax)
11028
4.60k
      break;
11029
24.4k
    if (ins->isa64 == intel64 && (ins->rex & REX_W))
11030
210
      {
11031
210
        USED_REX (REX_W);
11032
210
        *ins->obufp++ = 'q';
11033
210
        break;
11034
210
      }
11035
24.2k
    if ((ins->prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
11036
755
      {
11037
755
        if (sizeflag & DFLAG)
11038
455
    *ins->obufp++ = 'l';
11039
300
        else
11040
300
    *ins->obufp++ = 'w';
11041
755
        ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11042
755
      }
11043
24.2k
    break;
11044
73.4M
  }
11045
11046
73.4M
      if (len == l)
11047
72.8M
  len = l = 0;
11048
73.4M
    }
11049
16.8M
  *ins->obufp = 0;
11050
16.8M
  ins->mnemonicendp = ins->obufp;
11051
16.8M
  return 0;
11052
16.8M
}
11053
11054
/* Add a style marker to *INS->obufp that encodes STYLE.  This assumes that
11055
   the buffer pointed to by INS->obufp has space.  A style marker is made
11056
   from the STYLE_MARKER_CHAR followed by STYLE converted to a single hex
11057
   digit, followed by another STYLE_MARKER_CHAR.  This function assumes
11058
   that the number of styles is not greater than 16.  */
11059
11060
static void
11061
oappend_insert_style (instr_info *ins, enum disassembler_style style)
11062
58.6M
{
11063
58.6M
  unsigned num = (unsigned) style;
11064
11065
  /* We currently assume that STYLE can be encoded as a single hex
11066
     character.  If more styles are added then this might start to fail,
11067
     and we'll need to expand this code.  */
11068
58.6M
  if (num > 0xf)
11069
0
    abort ();
11070
11071
58.6M
  *ins->obufp++ = STYLE_MARKER_CHAR;
11072
58.6M
  *ins->obufp++ = (num < 10 ? ('0' + num)
11073
58.6M
       : ((num < 16) ? ('a' + (num - 10)) : '0'));
11074
58.6M
  *ins->obufp++ = STYLE_MARKER_CHAR;
11075
11076
  /* This final null character is not strictly necessary, after inserting a
11077
     style marker we should always be inserting some additional content.
11078
     However, having the buffer null terminated doesn't cost much, and make
11079
     it easier to debug what's going on.  Also, if we do ever forget to add
11080
     any additional content after this style marker, then the buffer will
11081
     still be well formed.  */
11082
58.6M
  *ins->obufp = '\0';
11083
58.6M
}
11084
11085
static void
11086
oappend_with_style (instr_info *ins, const char *s,
11087
        enum disassembler_style style)
11088
34.8M
{
11089
34.8M
  oappend_insert_style (ins, style);
11090
34.8M
  ins->obufp = stpcpy (ins->obufp, s);
11091
34.8M
}
11092
11093
/* Add a single character C to the buffer pointer to by INS->obufp, marking
11094
   the style for the character as STYLE.  */
11095
11096
static void
11097
oappend_char_with_style (instr_info *ins, const char c,
11098
       enum disassembler_style style)
11099
23.7M
{
11100
23.7M
  oappend_insert_style (ins, style);
11101
23.7M
  *ins->obufp++ = c;
11102
23.7M
  *ins->obufp = '\0';
11103
23.7M
}
11104
11105
/* Like oappend_char_with_style, but always uses dis_style_text.  */
11106
11107
static void
11108
oappend_char (instr_info *ins, const char c)
11109
20.3M
{
11110
20.3M
  oappend_char_with_style (ins, c, dis_style_text);
11111
20.3M
}
11112
11113
static void
11114
append_seg (instr_info *ins)
11115
9.50M
{
11116
  /* Only print the active segment register.  */
11117
9.50M
  if (!ins->active_seg_prefix)
11118
9.08M
    return;
11119
11120
415k
  ins->used_prefixes |= ins->active_seg_prefix;
11121
415k
  switch (ins->active_seg_prefix)
11122
415k
    {
11123
8.75k
    case PREFIX_CS:
11124
8.75k
      oappend_register (ins, att_names_seg[1]);
11125
8.75k
      break;
11126
316k
    case PREFIX_DS:
11127
316k
      oappend_register (ins, att_names_seg[3]);
11128
316k
      break;
11129
4.45k
    case PREFIX_SS:
11130
4.45k
      oappend_register (ins, att_names_seg[2]);
11131
4.45k
      break;
11132
3.28k
    case PREFIX_ES:
11133
3.28k
      oappend_register (ins, att_names_seg[0]);
11134
3.28k
      break;
11135
34.7k
    case PREFIX_FS:
11136
34.7k
      oappend_register (ins, att_names_seg[4]);
11137
34.7k
      break;
11138
46.9k
    case PREFIX_GS:
11139
46.9k
      oappend_register (ins, att_names_seg[5]);
11140
46.9k
      break;
11141
0
    default:
11142
0
      break;
11143
415k
    }
11144
415k
  oappend_char (ins, ':');
11145
415k
}
11146
11147
static void
11148
print_operand_value (instr_info *ins, bfd_vma disp,
11149
         enum disassembler_style style)
11150
4.22M
{
11151
4.22M
  char tmp[30];
11152
11153
4.22M
  if (ins->address_mode != mode_64bit)
11154
1.21M
    disp &= 0xffffffff;
11155
4.22M
  sprintf (tmp, "0x%" PRIx64, (uint64_t) disp);
11156
4.22M
  oappend_with_style (ins, tmp, style);
11157
4.22M
}
11158
11159
/* Like oappend, but called for immediate operands.  */
11160
11161
static void
11162
oappend_immediate (instr_info *ins, bfd_vma imm)
11163
2.51M
{
11164
2.51M
  if (!ins->intel_syntax)
11165
2.43M
    oappend_char_with_style (ins, '$', dis_style_immediate);
11166
2.51M
  print_operand_value (ins, imm, dis_style_immediate);
11167
2.51M
}
11168
11169
/* Put DISP in BUF as signed hex number.  */
11170
11171
static void
11172
print_displacement (instr_info *ins, bfd_signed_vma val)
11173
2.31M
{
11174
2.31M
  char tmp[30];
11175
11176
2.31M
  if (val < 0)
11177
559k
    {
11178
559k
      oappend_char_with_style (ins, '-', dis_style_address_offset);
11179
559k
      val = (bfd_vma) 0 - val;
11180
11181
      /* Check for possible overflow.  */
11182
559k
      if (val < 0)
11183
0
  {
11184
0
    switch (ins->address_mode)
11185
0
      {
11186
0
      case mode_64bit:
11187
0
        oappend_with_style (ins, "0x8000000000000000",
11188
0
          dis_style_address_offset);
11189
0
        break;
11190
0
      case mode_32bit:
11191
0
        oappend_with_style (ins, "0x80000000",
11192
0
          dis_style_address_offset);
11193
0
        break;
11194
0
      case mode_16bit:
11195
0
        oappend_with_style (ins, "0x8000",
11196
0
          dis_style_address_offset);
11197
0
        break;
11198
0
      }
11199
0
    return;
11200
0
  }
11201
559k
    }
11202
11203
2.31M
  sprintf (tmp, "0x%" PRIx64, (int64_t) val);
11204
2.31M
  oappend_with_style (ins, tmp, dis_style_address_offset);
11205
2.31M
}
11206
11207
static void
11208
intel_operand_size (instr_info *ins, int bytemode, int sizeflag)
11209
264k
{
11210
  /* Check if there is a broadcast, when evex.b is not treated as evex.nd.  */
11211
264k
  if (ins->vex.b && ins->evex_type == evex_default)
11212
3.90k
    {
11213
3.90k
      if (!ins->vex.no_broadcast)
11214
3.52k
  switch (bytemode)
11215
3.52k
    {
11216
828
    case x_mode:
11217
1.08k
    case evex_half_bcst_xmmq_mode:
11218
1.08k
      if (ins->vex.w)
11219
381
        oappend (ins, "QWORD BCST ");
11220
700
      else
11221
700
        oappend (ins, "DWORD BCST ");
11222
1.08k
      break;
11223
352
    case xh_mode:
11224
679
    case evex_half_bcst_xmmqh_mode:
11225
897
    case evex_half_bcst_xmmqdh_mode:
11226
897
      oappend (ins, "WORD BCST ");
11227
897
      break;
11228
1.55k
    default:
11229
1.55k
      ins->vex.no_broadcast = true;
11230
1.55k
      break;
11231
3.52k
    }
11232
3.90k
      return;
11233
3.90k
    }
11234
260k
  switch (bytemode)
11235
260k
    {
11236
129k
    case b_mode:
11237
138k
    case b_swap_mode:
11238
138k
    case db_mode:
11239
138k
      oappend (ins, "BYTE PTR ");
11240
138k
      break;
11241
5.03k
    case w_mode:
11242
5.23k
    case w_swap_mode:
11243
5.49k
    case dw_mode:
11244
5.49k
      oappend (ins, "WORD PTR ");
11245
5.49k
      break;
11246
4.29k
    case indir_v_mode:
11247
4.29k
      if (ins->address_mode == mode_64bit && ins->isa64 == intel64)
11248
194
  {
11249
194
    oappend (ins, "QWORD PTR ");
11250
194
    break;
11251
194
  }
11252
      /* Fall through.  */
11253
7.04k
    case stack_v_mode:
11254
7.04k
      if (ins->address_mode == mode_64bit && ((sizeflag & DFLAG)
11255
5.07k
                || (ins->rex & REX_W)))
11256
4.38k
  {
11257
4.38k
    oappend (ins, "QWORD PTR ");
11258
4.38k
    break;
11259
4.38k
  }
11260
      /* Fall through.  */
11261
47.8k
    case v_mode:
11262
58.3k
    case v_swap_mode:
11263
59.0k
    case dq_mode:
11264
59.0k
      USED_REX (REX_W);
11265
59.0k
      if (ins->rex & REX_W)
11266
2.15k
  oappend (ins, "QWORD PTR ");
11267
56.8k
      else if (bytemode == dq_mode)
11268
408
  oappend (ins, "DWORD PTR ");
11269
56.4k
      else
11270
56.4k
  {
11271
56.4k
    if (sizeflag & DFLAG)
11272
51.2k
      oappend (ins, "DWORD PTR ");
11273
5.27k
    else
11274
5.27k
      oappend (ins, "WORD PTR ");
11275
56.4k
    ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11276
56.4k
  }
11277
59.0k
      break;
11278
13.1k
    case z_mode:
11279
13.1k
      if ((ins->rex & REX_W) || (sizeflag & DFLAG))
11280
12.2k
  *ins->obufp++ = 'D';
11281
13.1k
      oappend (ins, "WORD PTR ");
11282
13.1k
      if (!(ins->rex & REX_W))
11283
12.5k
  ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11284
13.1k
      break;
11285
1.94k
    case a_mode:
11286
1.94k
      if (sizeflag & DFLAG)
11287
1.25k
  oappend (ins, "QWORD PTR ");
11288
694
      else
11289
694
  oappend (ins, "DWORD PTR ");
11290
1.94k
      ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11291
1.94k
      break;
11292
1.86k
    case movsxd_mode:
11293
1.86k
      if (!(sizeflag & DFLAG) && ins->isa64 == intel64)
11294
190
  oappend (ins, "WORD PTR ");
11295
1.67k
      else
11296
1.67k
  oappend (ins, "DWORD PTR ");
11297
1.86k
      ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11298
1.86k
      break;
11299
2.49k
    case d_mode:
11300
2.77k
    case d_swap_mode:
11301
2.77k
      oappend (ins, "DWORD PTR ");
11302
2.77k
      break;
11303
6.69k
    case q_mode:
11304
6.89k
    case q_swap_mode:
11305
6.89k
      oappend (ins, "QWORD PTR ");
11306
6.89k
      break;
11307
523
    case m_mode:
11308
523
      if (ins->address_mode == mode_64bit)
11309
239
  oappend (ins, "QWORD PTR ");
11310
284
      else
11311
284
  oappend (ins, "DWORD PTR ");
11312
523
      break;
11313
5.68k
    case f_mode:
11314
5.68k
      if (sizeflag & DFLAG)
11315
5.01k
  oappend (ins, "FWORD PTR ");
11316
674
      else
11317
674
  oappend (ins, "DWORD PTR ");
11318
5.68k
      ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11319
5.68k
      break;
11320
497
    case t_mode:
11321
497
      oappend (ins, "TBYTE PTR ");
11322
497
      break;
11323
5.87k
    case x_mode:
11324
7.06k
    case xh_mode:
11325
7.82k
    case x_swap_mode:
11326
8.01k
    case evex_x_gscat_mode:
11327
8.21k
    case evex_x_nobcst_mode:
11328
8.43k
    case bw_unit_mode:
11329
8.43k
      if (ins->need_vex)
11330
5.14k
  {
11331
5.14k
    switch (ins->vex.length)
11332
5.14k
      {
11333
1.86k
      case 128:
11334
1.86k
        oappend (ins, "XMMWORD PTR ");
11335
1.86k
        break;
11336
1.69k
      case 256:
11337
1.69k
        oappend (ins, "YMMWORD PTR ");
11338
1.69k
        break;
11339
1.58k
      case 512:
11340
1.58k
        oappend (ins, "ZMMWORD PTR ");
11341
1.58k
        break;
11342
0
      default:
11343
0
        abort ();
11344
5.14k
      }
11345
5.14k
  }
11346
3.29k
      else
11347
3.29k
  oappend (ins, "XMMWORD PTR ");
11348
8.43k
      break;
11349
8.43k
    case xmm_mode:
11350
355
      oappend (ins, "XMMWORD PTR ");
11351
355
      break;
11352
284
    case ymm_mode:
11353
284
      oappend (ins, "YMMWORD PTR ");
11354
284
      break;
11355
262
    case xmmq_mode:
11356
463
    case evex_half_bcst_xmmqh_mode:
11357
996
    case evex_half_bcst_xmmq_mode:
11358
996
      switch (ins->vex.length)
11359
996
  {
11360
206
  case 0:
11361
421
  case 128:
11362
421
    oappend (ins, "QWORD PTR ");
11363
421
    break;
11364
301
  case 256:
11365
301
    oappend (ins, "XMMWORD PTR ");
11366
301
    break;
11367
274
  case 512:
11368
274
    oappend (ins, "YMMWORD PTR ");
11369
274
    break;
11370
0
  default:
11371
0
    abort ();
11372
996
  }
11373
996
      break;
11374
996
    case xmmdw_mode:
11375
673
      if (!ins->need_vex)
11376
0
  abort ();
11377
11378
673
      switch (ins->vex.length)
11379
673
  {
11380
227
  case 128:
11381
227
    oappend (ins, "WORD PTR ");
11382
227
    break;
11383
255
  case 256:
11384
255
    oappend (ins, "DWORD PTR ");
11385
255
    break;
11386
191
  case 512:
11387
191
    oappend (ins, "QWORD PTR ");
11388
191
    break;
11389
0
  default:
11390
0
    abort ();
11391
673
  }
11392
673
      break;
11393
673
    case xmmqd_mode:
11394
768
    case evex_half_bcst_xmmqdh_mode:
11395
768
      if (!ins->need_vex)
11396
0
  abort ();
11397
11398
768
      switch (ins->vex.length)
11399
768
  {
11400
228
  case 128:
11401
228
    oappend (ins, "DWORD PTR ");
11402
228
    break;
11403
325
  case 256:
11404
325
    oappend (ins, "QWORD PTR ");
11405
325
    break;
11406
215
  case 512:
11407
215
    oappend (ins, "XMMWORD PTR ");
11408
215
    break;
11409
0
  default:
11410
0
    abort ();
11411
768
  }
11412
768
      break;
11413
768
    case ymmq_mode:
11414
681
      if (!ins->need_vex)
11415
0
  abort ();
11416
11417
681
      switch (ins->vex.length)
11418
681
  {
11419
232
  case 128:
11420
232
    oappend (ins, "QWORD PTR ");
11421
232
    break;
11422
213
  case 256:
11423
213
    oappend (ins, "YMMWORD PTR ");
11424
213
    break;
11425
236
  case 512:
11426
236
    oappend (ins, "ZMMWORD PTR ");
11427
236
    break;
11428
0
  default:
11429
0
    abort ();
11430
681
  }
11431
681
      break;
11432
681
    case o_mode:
11433
190
      oappend (ins, "OWORD PTR ");
11434
190
      break;
11435
1.16k
    case vex_vsib_d_w_dq_mode:
11436
1.81k
    case vex_vsib_q_w_dq_mode:
11437
1.81k
      if (!ins->need_vex)
11438
0
  abort ();
11439
1.81k
      if (ins->vex.w)
11440
727
  oappend (ins, "QWORD PTR ");
11441
1.08k
      else
11442
1.08k
  oappend (ins, "DWORD PTR ");
11443
1.81k
      break;
11444
550
    case mask_bd_mode:
11445
550
      if (!ins->need_vex || ins->vex.length != 128)
11446
0
  abort ();
11447
550
      if (ins->vex.w)
11448
336
  oappend (ins, "DWORD PTR ");
11449
214
      else
11450
214
  oappend (ins, "BYTE PTR ");
11451
550
      break;
11452
508
    case mask_mode:
11453
508
      if (!ins->need_vex)
11454
0
  abort ();
11455
508
      if (ins->vex.w)
11456
302
  oappend (ins, "QWORD PTR ");
11457
206
      else
11458
206
  oappend (ins, "WORD PTR ");
11459
508
      break;
11460
410
    case v_bnd_mode:
11461
881
    case v_bndmk_mode:
11462
3.77k
    default:
11463
3.77k
      break;
11464
260k
    }
11465
260k
}
11466
11467
static void
11468
print_register (instr_info *ins, unsigned int reg, unsigned int rexmask,
11469
    int bytemode, int sizeflag)
11470
10.2M
{
11471
10.2M
  const char (*names)[8];
11472
11473
  /* Masking is invalid for insns with GPR destination. Set the flag uniformly,
11474
     as the consumer will inspect it only for the destination operand.  */
11475
10.2M
  if (bytemode != mask_mode && ins->vex.mask_register_specifier)
11476
1.29k
    ins->illegal_masking = true;
11477
11478
10.2M
  USED_REX (rexmask);
11479
10.2M
  if (ins->rex & rexmask)
11480
275k
    reg += 8;
11481
10.2M
  if (ins->rex2 & rexmask)
11482
9.64k
    reg += 16;
11483
11484
10.2M
  switch (bytemode)
11485
10.2M
    {
11486
6.88M
    case b_mode:
11487
6.92M
    case b_swap_mode:
11488
6.92M
      if (reg & 4)
11489
1.35M
  USED_REX (0);
11490
6.92M
      if (ins->rex || ins->rex2)
11491
118k
  names = att_names8rex;
11492
6.81M
      else
11493
6.81M
  names = att_names8;
11494
6.92M
      break;
11495
1.30k
    case w_mode:
11496
1.30k
      names = att_names16;
11497
1.30k
      break;
11498
7.89k
    case d_mode:
11499
8.15k
    case dw_mode:
11500
8.37k
    case db_mode:
11501
8.37k
      names = att_names32;
11502
8.37k
      break;
11503
1.78k
    case q_mode:
11504
1.78k
      names = att_names64;
11505
1.78k
      break;
11506
4.86k
    case m_mode:
11507
5.10k
    case v_bnd_mode:
11508
5.10k
      names = ins->address_mode == mode_64bit ? att_names64 : att_names32;
11509
5.10k
      break;
11510
4.12k
    case bnd_mode:
11511
4.41k
    case bnd_swap_mode:
11512
4.41k
      if (reg > 0x3)
11513
2.27k
  {
11514
2.27k
    oappend (ins, "(bad)");
11515
2.27k
    return;
11516
2.27k
  }
11517
2.14k
      names = att_names_bnd;
11518
2.14k
      break;
11519
10.3k
    case indir_v_mode:
11520
10.3k
      if (ins->address_mode == mode_64bit && ins->isa64 == intel64)
11521
190
  {
11522
190
    names = att_names64;
11523
190
    break;
11524
190
  }
11525
      /* Fall through.  */
11526
17.0k
    case stack_v_mode:
11527
17.0k
      if (ins->address_mode == mode_64bit && ((sizeflag & DFLAG)
11528
11.9k
                || (ins->rex & REX_W)))
11529
11.5k
  {
11530
11.5k
    names = att_names64;
11531
11.5k
    break;
11532
11.5k
  }
11533
5.53k
      bytemode = v_mode;
11534
      /* Fall through.  */
11535
3.12M
    case v_mode:
11536
3.23M
    case v_swap_mode:
11537
3.23M
    case dq_mode:
11538
3.23M
      USED_REX (REX_W);
11539
3.23M
      if (ins->rex & REX_W)
11540
486k
  names = att_names64;
11541
2.74M
      else if (bytemode != v_mode && bytemode != v_swap_mode)
11542
4.64k
  names = att_names32;
11543
2.74M
      else
11544
2.74M
  {
11545
2.74M
    if (sizeflag & DFLAG)
11546
2.67M
      names = att_names32;
11547
65.3k
    else
11548
65.3k
      names = att_names16;
11549
2.74M
    ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11550
2.74M
  }
11551
3.23M
      break;
11552
7.22k
    case movsxd_mode:
11553
7.22k
      if (!(sizeflag & DFLAG) && ins->isa64 == intel64)
11554
190
  names = att_names16;
11555
7.03k
      else
11556
7.03k
  names = att_names32;
11557
7.22k
      ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11558
7.22k
      break;
11559
924
    case va_mode:
11560
924
      names = (ins->address_mode == mode_64bit
11561
924
         ? att_names64 : att_names32);
11562
924
      if (!(ins->prefixes & PREFIX_ADDR))
11563
627
  names = (ins->address_mode == mode_16bit
11564
627
         ? att_names16 : names);
11565
297
      else
11566
297
  {
11567
    /* Remove "addr16/addr32".  */
11568
297
    ins->all_prefixes[ins->last_addr_prefix] = 0;
11569
297
    names = (ins->address_mode != mode_32bit
11570
297
           ? att_names32 : att_names16);
11571
297
    ins->used_prefixes |= PREFIX_ADDR;
11572
297
  }
11573
924
      break;
11574
728
    case mask_bd_mode:
11575
11.5k
    case mask_mode:
11576
11.5k
      if (reg > 0x7)
11577
6.67k
  {
11578
6.67k
    oappend (ins, "(bad)");
11579
6.67k
    return;
11580
6.67k
  }
11581
4.89k
      names = att_names_mask;
11582
4.89k
      break;
11583
322
    case 0:
11584
322
      return;
11585
0
    default:
11586
0
      oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
11587
0
      return;
11588
10.2M
    }
11589
10.2M
  oappend_register (ins, names[reg]);
11590
10.2M
}
11591
11592
static bool
11593
get8s (instr_info *ins, bfd_vma *res)
11594
2.80M
{
11595
2.80M
  if (!fetch_code (ins->info, ins->codep + 1))
11596
1.98k
    return false;
11597
2.80M
  *res = ((bfd_vma) *ins->codep++ ^ 0x80) - 0x80;
11598
2.80M
  return true;
11599
2.80M
}
11600
11601
static bool
11602
get16 (instr_info *ins, bfd_vma *res)
11603
120k
{
11604
120k
  if (!fetch_code (ins->info, ins->codep + 2))
11605
858
    return false;
11606
119k
  *res = *ins->codep++;
11607
119k
  *res |= (bfd_vma) *ins->codep++ << 8;
11608
119k
  return true;
11609
120k
}
11610
11611
static bool
11612
get16s (instr_info *ins, bfd_vma *res)
11613
18.0k
{
11614
18.0k
  if (!get16 (ins, res))
11615
362
    return false;
11616
17.6k
  *res = (*res ^ 0x8000) - 0x8000;
11617
17.6k
  return true;
11618
18.0k
}
11619
11620
static bool
11621
get32 (instr_info *ins, bfd_vma *res)
11622
2.49M
{
11623
2.49M
  if (!fetch_code (ins->info, ins->codep + 4))
11624
4.22k
    return false;
11625
2.49M
  *res = *ins->codep++;
11626
2.49M
  *res |= (bfd_vma) *ins->codep++ << 8;
11627
2.49M
  *res |= (bfd_vma) *ins->codep++ << 16;
11628
2.49M
  *res |= (bfd_vma) *ins->codep++ << 24;
11629
2.49M
  return true;
11630
2.49M
}
11631
11632
static bool
11633
get32s (instr_info *ins, bfd_vma *res)
11634
1.48M
{
11635
1.48M
  if (!get32 (ins, res))
11636
1.98k
    return false;
11637
11638
1.48M
  *res = (*res ^ ((bfd_vma) 1 << 31)) - ((bfd_vma) 1 << 31);
11639
11640
1.48M
  return true;
11641
1.48M
}
11642
11643
static bool
11644
get64 (instr_info *ins, uint64_t *res)
11645
70.0k
{
11646
70.0k
  unsigned int a;
11647
70.0k
  unsigned int b;
11648
11649
70.0k
  if (!fetch_code (ins->info, ins->codep + 8))
11650
332
    return false;
11651
69.7k
  a = *ins->codep++;
11652
69.7k
  a |= (unsigned int) *ins->codep++ << 8;
11653
69.7k
  a |= (unsigned int) *ins->codep++ << 16;
11654
69.7k
  a |= (unsigned int) *ins->codep++ << 24;
11655
69.7k
  b = *ins->codep++;
11656
69.7k
  b |= (unsigned int) *ins->codep++ << 8;
11657
69.7k
  b |= (unsigned int) *ins->codep++ << 16;
11658
69.7k
  b |= (unsigned int) *ins->codep++ << 24;
11659
69.7k
  *res = a + ((uint64_t) b << 32);
11660
69.7k
  return true;
11661
70.0k
}
11662
11663
static void
11664
set_op (instr_info *ins, bfd_vma op, bool riprel)
11665
1.74M
{
11666
1.74M
  ins->op_index[ins->op_ad] = ins->op_ad;
11667
1.74M
  if (ins->address_mode == mode_64bit)
11668
1.27M
    ins->op_address[ins->op_ad] = op;
11669
468k
  else /* Mask to get a 32-bit address.  */
11670
468k
    ins->op_address[ins->op_ad] = op & 0xffffffff;
11671
1.74M
  ins->op_riprel[ins->op_ad] = riprel;
11672
1.74M
}
11673
11674
static bool
11675
BadOp (instr_info *ins)
11676
70.1k
{
11677
  /* Throw away prefixes and 1st. opcode byte.  */
11678
70.1k
  struct dis_private *priv = ins->info->private_data;
11679
11680
70.1k
  ins->codep = priv->the_buffer + ins->nr_prefixes + ins->need_vex + 1;
11681
70.1k
  ins->obufp = stpcpy (ins->obufp, "(bad)");
11682
70.1k
  return true;
11683
70.1k
}
11684
11685
static bool
11686
OP_Skip_MODRM (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
11687
         int sizeflag ATTRIBUTE_UNUSED)
11688
1.42k
{
11689
1.42k
  if (ins->modrm.mod != 3)
11690
387
    return BadOp (ins);
11691
11692
  /* Skip mod/rm byte.  */
11693
1.03k
  MODRM_CHECK;
11694
1.03k
  ins->codep++;
11695
1.03k
  ins->has_skipped_modrm = true;
11696
1.03k
  return true;
11697
1.03k
}
11698
11699
static bool
11700
OP_E_memory (instr_info *ins, int bytemode, int sizeflag)
11701
9.08M
{
11702
9.08M
  int add = (ins->rex & REX_B) ? 8 : 0;
11703
9.08M
  int riprel = 0;
11704
9.08M
  int shift;
11705
11706
9.08M
  add += (ins->rex2 & REX_B) ? 16 : 0;
11707
11708
  /* Handles EVEX other than APX EVEX-promoted instructions.  */
11709
9.08M
  if (ins->vex.evex && ins->evex_type == evex_default)
11710
30.1k
    {
11711
11712
      /* Zeroing-masking is invalid for memory destinations. Set the flag
11713
   uniformly, as the consumer will inspect it only for the destination
11714
   operand.  */
11715
30.1k
      if (ins->vex.zeroing)
11716
8.59k
  ins->illegal_masking = true;
11717
11718
30.1k
      switch (bytemode)
11719
30.1k
  {
11720
284
  case dw_mode:
11721
865
  case w_mode:
11722
1.06k
  case w_swap_mode:
11723
1.06k
    shift = 1;
11724
1.06k
    break;
11725
264
  case db_mode:
11726
739
  case b_mode:
11727
739
    shift = 0;
11728
739
    break;
11729
666
  case dq_mode:
11730
666
    if (ins->address_mode != mode_64bit)
11731
230
      {
11732
1.84k
  case d_mode:
11733
2.12k
  case d_swap_mode:
11734
2.12k
        shift = 2;
11735
2.12k
        break;
11736
1.84k
      }
11737
      /* fall through */
11738
1.75k
  case vex_vsib_d_w_dq_mode:
11739
4.07k
  case vex_vsib_q_w_dq_mode:
11740
4.28k
  case evex_x_gscat_mode:
11741
4.28k
    shift = ins->vex.w ? 3 : 2;
11742
4.28k
    break;
11743
3.83k
  case xh_mode:
11744
4.58k
  case evex_half_bcst_xmmqh_mode:
11745
5.21k
  case evex_half_bcst_xmmqdh_mode:
11746
5.21k
    if (ins->vex.b)
11747
2.73k
      {
11748
2.73k
        shift = ins->vex.w ? 2 : 1;
11749
2.73k
        break;
11750
2.73k
      }
11751
    /* Fall through.  */
11752
13.5k
  case x_mode:
11753
14.4k
  case evex_half_bcst_xmmq_mode:
11754
14.4k
    if (ins->vex.b)
11755
5.09k
      {
11756
5.09k
        shift = ins->vex.w ? 3 : 2;
11757
5.09k
        break;
11758
5.09k
      }
11759
    /* Fall through.  */
11760
9.99k
  case xmmqd_mode:
11761
10.3k
  case xmmdw_mode:
11762
10.6k
  case xmmq_mode:
11763
11.3k
  case ymmq_mode:
11764
11.5k
  case evex_x_nobcst_mode:
11765
11.8k
  case x_swap_mode:
11766
11.8k
    switch (ins->vex.length)
11767
11.8k
      {
11768
4.12k
      case 128:
11769
4.12k
        shift = 4;
11770
4.12k
        break;
11771
3.32k
      case 256:
11772
3.32k
        shift = 5;
11773
3.32k
        break;
11774
4.37k
      case 512:
11775
4.37k
        shift = 6;
11776
4.37k
        break;
11777
0
      default:
11778
0
        abort ();
11779
11.8k
      }
11780
    /* Make necessary corrections to shift for modes that need it.  */
11781
11.8k
    if (bytemode == xmmq_mode
11782
11.8k
        || bytemode == evex_half_bcst_xmmqh_mode
11783
11.8k
        || bytemode == evex_half_bcst_xmmq_mode
11784
11.8k
        || (bytemode == ymmq_mode && ins->vex.length == 128))
11785
1.27k
      shift -= 1;
11786
10.5k
    else if (bytemode == xmmqd_mode
11787
10.5k
             || bytemode == evex_half_bcst_xmmqdh_mode)
11788
856
      shift -= 2;
11789
9.69k
    else if (bytemode == xmmdw_mode)
11790
384
      shift -= 3;
11791
11.8k
    break;
11792
290
  case ymm_mode:
11793
290
    shift = 5;
11794
290
    break;
11795
268
  case xmm_mode:
11796
268
    shift = 4;
11797
268
    break;
11798
698
  case q_mode:
11799
925
  case q_swap_mode:
11800
925
    shift = 3;
11801
925
    break;
11802
781
  case bw_unit_mode:
11803
781
    shift = ins->vex.w ? 1 : 0;
11804
781
    break;
11805
0
  default:
11806
0
    abort ();
11807
30.1k
  }
11808
30.1k
    }
11809
9.05M
  else
11810
9.05M
    shift = 0;
11811
11812
9.08M
  USED_REX (REX_B);
11813
9.08M
  if (ins->intel_syntax)
11814
218k
    intel_operand_size (ins, bytemode, sizeflag);
11815
9.08M
  append_seg (ins);
11816
11817
9.08M
  if ((sizeflag & AFLAG) || ins->address_mode == mode_64bit)
11818
8.95M
    {
11819
      /* 32/64 bit address mode */
11820
8.95M
      bfd_vma disp = 0;
11821
8.95M
      int havedisp;
11822
8.95M
      int havebase;
11823
8.95M
      int needindex;
11824
8.95M
      int needaddr32;
11825
8.95M
      int base, rbase;
11826
8.95M
      int vindex = 0;
11827
8.95M
      int scale = 0;
11828
8.95M
      int addr32flag = !((sizeflag & AFLAG)
11829
8.95M
       || bytemode == v_bnd_mode
11830
8.95M
       || bytemode == v_bndmk_mode
11831
8.95M
       || bytemode == bnd_mode
11832
8.95M
       || bytemode == bnd_swap_mode);
11833
8.95M
      bool check_gather = false;
11834
8.95M
      const char (*indexes)[8] = NULL;
11835
11836
8.95M
      havebase = 1;
11837
8.95M
      base = ins->modrm.rm;
11838
11839
8.95M
      if (base == 4)
11840
584k
  {
11841
584k
    vindex = ins->sib.index;
11842
584k
    USED_REX (REX_X);
11843
584k
    if (ins->rex & REX_X)
11844
8.41k
      vindex += 8;
11845
584k
    switch (bytemode)
11846
584k
      {
11847
1.58k
      case vex_vsib_d_w_dq_mode:
11848
3.30k
      case vex_vsib_q_w_dq_mode:
11849
3.30k
        if (!ins->need_vex)
11850
0
    abort ();
11851
3.30k
        if (ins->vex.evex)
11852
2.36k
    {
11853
      /* S/G EVEX insns require EVEX.X4 not to be set.  */
11854
2.36k
      if (ins->rex2 & REX_X)
11855
208
        {
11856
208
          oappend (ins, "(bad)");
11857
208
          return true;
11858
208
        }
11859
11860
2.15k
      if (!ins->vex.v)
11861
1.24k
        vindex += 16;
11862
2.15k
      check_gather = ins->obufp == ins->op_out[1];
11863
2.15k
    }
11864
11865
3.10k
        switch (ins->vex.length)
11866
3.10k
    {
11867
403
    case 128:
11868
403
      indexes = att_names_xmm;
11869
403
      break;
11870
1.48k
    case 256:
11871
1.48k
      if (!ins->vex.w
11872
1.48k
          || bytemode == vex_vsib_q_w_dq_mode)
11873
1.12k
        indexes = att_names_ymm;
11874
366
      else
11875
366
        indexes = att_names_xmm;
11876
1.48k
      break;
11877
1.21k
    case 512:
11878
1.21k
      if (!ins->vex.w
11879
1.21k
          || bytemode == vex_vsib_q_w_dq_mode)
11880
852
        indexes = att_names_zmm;
11881
359
      else
11882
359
        indexes = att_names_ymm;
11883
1.21k
      break;
11884
0
    default:
11885
0
      abort ();
11886
3.10k
    }
11887
3.10k
        break;
11888
581k
      default:
11889
581k
        if (ins->rex2 & REX_X)
11890
1.40k
    vindex += 16;
11891
11892
581k
        if (vindex != 4)
11893
411k
    indexes = ins->address_mode == mode_64bit && !addr32flag
11894
411k
        ? att_names64 : att_names32;
11895
581k
        break;
11896
584k
      }
11897
584k
    scale = ins->sib.scale;
11898
584k
    base = ins->sib.base;
11899
584k
    ins->codep++;
11900
584k
  }
11901
8.37M
      else
11902
8.37M
  {
11903
    /* Check for mandatory SIB.  */
11904
8.37M
    if (bytemode == vex_vsib_d_w_dq_mode
11905
8.37M
        || bytemode == vex_vsib_q_w_dq_mode
11906
8.37M
        || bytemode == vex_sibmem_mode)
11907
1.95k
      {
11908
1.95k
        oappend (ins, "(bad)");
11909
1.95k
        return true;
11910
1.95k
      }
11911
8.37M
  }
11912
8.95M
      rbase = base + add;
11913
11914
8.95M
      switch (ins->modrm.mod)
11915
8.95M
  {
11916
6.89M
  case 0:
11917
6.89M
    if (base == 5)
11918
304k
      {
11919
304k
        havebase = 0;
11920
304k
        if (ins->address_mode == mode_64bit && !ins->has_sib)
11921
209k
    riprel = 1;
11922
304k
        if (!get32s (ins, &disp))
11923
555
    return false;
11924
303k
        if (riprel && bytemode == v_bndmk_mode)
11925
202
    {
11926
202
      oappend (ins, "(bad)");
11927
202
      return true;
11928
202
    }
11929
303k
      }
11930
6.89M
    break;
11931
6.89M
  case 1:
11932
1.34M
    if (!get8s (ins, &disp))
11933
788
      return false;
11934
1.34M
    if (ins->vex.evex && shift > 0)
11935
14.9k
      disp <<= shift;
11936
1.34M
    break;
11937
709k
  case 2:
11938
709k
    if (!get32s (ins, &disp))
11939
1.11k
      return false;
11940
708k
    break;
11941
8.95M
  }
11942
11943
8.95M
      needindex = 0;
11944
8.95M
      needaddr32 = 0;
11945
8.95M
      if (ins->has_sib
11946
8.95M
    && !havebase
11947
8.95M
    && !indexes
11948
8.95M
    && ins->address_mode != mode_16bit)
11949
3.18k
  {
11950
3.18k
    if (ins->address_mode == mode_64bit)
11951
2.61k
      {
11952
2.61k
        if (addr32flag)
11953
1.17k
    {
11954
      /* Without base nor index registers, zero-extend the
11955
         lower 32-bit displacement to 64 bits.  */
11956
1.17k
      disp &= 0xffffffff;
11957
1.17k
      needindex = 1;
11958
1.17k
    }
11959
2.61k
        needaddr32 = 1;
11960
2.61k
      }
11961
571
    else
11962
571
      {
11963
        /* In 32-bit mode, we need index register to tell [offset]
11964
     from [eiz*1 + offset].  */
11965
571
        needindex = 1;
11966
571
      }
11967
3.18k
  }
11968
11969
8.95M
      havedisp = (havebase
11970
8.95M
      || needindex
11971
8.95M
      || (ins->has_sib && (indexes || scale != 0)));
11972
11973
8.95M
      if (!ins->intel_syntax)
11974
8.74M
  if (ins->modrm.mod != 0 || base == 5)
11975
2.29M
    {
11976
2.29M
      if (havedisp || riprel)
11977
2.21M
        print_displacement (ins, disp);
11978
75.2k
      else
11979
75.2k
        print_operand_value (ins, disp, dis_style_address_offset);
11980
2.29M
      if (riprel)
11981
205k
        {
11982
205k
    set_op (ins, disp, true);
11983
205k
    oappend_char (ins, '(');
11984
205k
    oappend_with_style (ins, !addr32flag ? "%rip" : "%eip",
11985
205k
            dis_style_register);
11986
205k
    oappend_char (ins, ')');
11987
205k
        }
11988
2.29M
    }
11989
11990
8.95M
      if ((havebase || indexes || needindex || needaddr32 || riprel)
11991
8.95M
    && (ins->address_mode != mode_64bit
11992
8.87M
        || ((bytemode != v_bnd_mode)
11993
6.52M
      && (bytemode != v_bndmk_mode)
11994
6.52M
      && (bytemode != bnd_mode)
11995
6.52M
      && (bytemode != bnd_swap_mode))))
11996
8.87M
  ins->used_prefixes |= PREFIX_ADDR;
11997
11998
8.95M
      if (havedisp || (ins->intel_syntax && riprel))
11999
8.67M
  {
12000
8.67M
    oappend_char (ins, ins->open_char);
12001
8.67M
    if (ins->intel_syntax && riprel)
12002
3.50k
      {
12003
3.50k
        set_op (ins, disp, true);
12004
3.50k
        oappend_with_style (ins, !addr32flag ? "rip" : "eip",
12005
3.50k
          dis_style_register);
12006
3.50k
      }
12007
8.67M
    if (havebase)
12008
8.65M
      oappend_register
12009
8.65M
        (ins,
12010
8.65M
         (ins->address_mode == mode_64bit && !addr32flag
12011
8.65M
    ? att_names64 : att_names32)[rbase]);
12012
8.67M
    if (ins->has_sib)
12013
583k
      {
12014
        /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
12015
     print index to tell base + index from base.  */
12016
583k
        if (scale != 0
12017
583k
      || needindex
12018
583k
      || indexes
12019
583k
      || (havebase && base != ESP_REG_NUM))
12020
463k
    {
12021
463k
      if (!ins->intel_syntax || havebase)
12022
462k
        oappend_char (ins, ins->separator_char);
12023
463k
      if (indexes)
12024
414k
        {
12025
414k
          if (ins->address_mode == mode_64bit || vindex < 16)
12026
414k
      oappend_register (ins, indexes[vindex]);
12027
436
          else
12028
436
      oappend (ins, "(bad)");
12029
414k
        }
12030
48.6k
      else
12031
48.6k
        oappend_register (ins,
12032
48.6k
              ins->address_mode == mode_64bit
12033
48.6k
              && !addr32flag
12034
48.6k
              ? att_index64
12035
48.6k
              : att_index32);
12036
12037
463k
      oappend_char (ins, ins->scale_char);
12038
463k
      oappend_char_with_style (ins, '0' + (1 << scale),
12039
463k
             dis_style_immediate);
12040
463k
    }
12041
583k
      }
12042
8.67M
    if (ins->intel_syntax
12043
8.67M
        && (disp || ins->modrm.mod != 0 || base == 5))
12044
62.8k
      {
12045
62.8k
        if (!havedisp || (bfd_signed_vma) disp >= 0)
12046
41.2k
      oappend_char (ins, '+');
12047
62.8k
        if (havedisp)
12048
59.3k
    print_displacement (ins, disp);
12049
3.50k
        else
12050
3.50k
    print_operand_value (ins, disp, dis_style_address_offset);
12051
62.8k
      }
12052
12053
8.67M
    oappend_char (ins, ins->close_char);
12054
12055
8.67M
    if (check_gather)
12056
1.27k
      {
12057
        /* Both XMM/YMM/ZMM registers must be distinct.  */
12058
1.27k
        int modrm_reg = ins->modrm.reg;
12059
12060
1.27k
        if (ins->rex & REX_R)
12061
520
          modrm_reg += 8;
12062
1.27k
        if (ins->rex2 & REX_R)
12063
332
          modrm_reg += 16;
12064
1.27k
        if (vindex == modrm_reg)
12065
199
    oappend (ins, "/(bad)");
12066
1.27k
      }
12067
8.67M
  }
12068
282k
      else if (ins->intel_syntax)
12069
2.48k
  {
12070
2.48k
    if (ins->modrm.mod != 0 || base == 5)
12071
2.48k
      {
12072
2.48k
        if (!ins->active_seg_prefix)
12073
1.92k
    {
12074
1.92k
      oappend_register (ins, att_names_seg[ds_reg - es_reg]);
12075
1.92k
      oappend (ins, ":");
12076
1.92k
    }
12077
2.48k
        print_operand_value (ins, disp, dis_style_text);
12078
2.48k
      }
12079
2.48k
  }
12080
8.95M
    }
12081
122k
  else if (bytemode == v_bnd_mode
12082
122k
     || bytemode == v_bndmk_mode
12083
122k
     || bytemode == bnd_mode
12084
122k
     || bytemode == bnd_swap_mode
12085
122k
     || bytemode == vex_vsib_d_w_dq_mode
12086
122k
     || bytemode == vex_vsib_q_w_dq_mode)
12087
1.81k
    {
12088
1.81k
      oappend (ins, "(bad)");
12089
1.81k
      return true;
12090
1.81k
    }
12091
120k
  else
12092
120k
    {
12093
      /* 16 bit address mode */
12094
120k
      bfd_vma disp = 0;
12095
12096
120k
      ins->used_prefixes |= ins->prefixes & PREFIX_ADDR;
12097
120k
      switch (ins->modrm.mod)
12098
120k
  {
12099
88.2k
  case 0:
12100
88.2k
    if (ins->modrm.rm == 6)
12101
3.38k
      {
12102
14.8k
  case 2:
12103
14.8k
        if (!get16s (ins, &disp))
12104
250
    return false;
12105
14.8k
      }
12106
99.4k
    break;
12107
99.4k
  case 1:
12108
21.1k
    if (!get8s (ins, &disp))
12109
143
      return false;
12110
20.9k
    if (ins->vex.evex && shift > 0)
12111
1.13k
      disp <<= shift;
12112
20.9k
    break;
12113
120k
  }
12114
12115
120k
      if (!ins->intel_syntax)
12116
110k
  if (ins->modrm.mod != 0 || ins->modrm.rm == 6)
12117
31.9k
    print_displacement (ins, disp);
12118
12119
120k
      if (ins->modrm.mod != 0 || ins->modrm.rm != 6)
12120
117k
  {
12121
117k
    oappend_char (ins, ins->open_char);
12122
117k
    oappend (ins, ins->intel_syntax ? intel_index16[ins->modrm.rm]
12123
117k
            : att_index16[ins->modrm.rm]);
12124
117k
    if (ins->intel_syntax
12125
117k
        && (disp || ins->modrm.mod != 0 || ins->modrm.rm == 6))
12126
2.91k
      {
12127
2.91k
        if ((bfd_signed_vma) disp >= 0)
12128
1.78k
    oappend_char (ins, '+');
12129
2.91k
        print_displacement (ins, disp);
12130
2.91k
      }
12131
12132
117k
    oappend_char (ins, ins->close_char);
12133
117k
  }
12134
3.31k
      else if (ins->intel_syntax)
12135
699
  {
12136
699
    if (!ins->active_seg_prefix)
12137
395
      {
12138
395
        oappend_register (ins, att_names_seg[ds_reg - es_reg]);
12139
395
        oappend (ins, ":");
12140
395
      }
12141
699
    print_operand_value (ins, disp & 0xffff, dis_style_text);
12142
699
  }
12143
120k
    }
12144
9.07M
  if (ins->vex.b && ins->evex_type == evex_default)
12145
12.4k
    {
12146
12.4k
      ins->evex_used |= EVEX_b_used;
12147
12148
      /* Broadcast can only ever be valid for memory sources.  */
12149
12.4k
      if (ins->obufp == ins->op_out[0])
12150
0
  ins->vex.no_broadcast = true;
12151
12152
12.4k
      if (!ins->vex.no_broadcast
12153
12.4k
    && (!ins->intel_syntax || !(ins->evex_used & EVEX_len_used)))
12154
8.70k
  {
12155
8.70k
    if (bytemode == xh_mode)
12156
1.61k
      {
12157
1.61k
        switch (ins->vex.length)
12158
1.61k
    {
12159
390
    case 128:
12160
390
      oappend (ins, "{1to8}");
12161
390
      break;
12162
966
    case 256:
12163
966
      oappend (ins, "{1to16}");
12164
966
      break;
12165
255
    case 512:
12166
255
      oappend (ins, "{1to32}");
12167
255
      break;
12168
0
    default:
12169
0
      abort ();
12170
1.61k
    }
12171
1.61k
      }
12172
7.09k
    else if (bytemode == q_mode
12173
7.09k
       || bytemode == ymmq_mode)
12174
562
      ins->vex.no_broadcast = true;
12175
6.53k
    else if (ins->vex.w
12176
6.53k
       || bytemode == evex_half_bcst_xmmqdh_mode
12177
6.53k
       || bytemode == evex_half_bcst_xmmq_mode)
12178
3.56k
      {
12179
3.56k
        switch (ins->vex.length)
12180
3.56k
    {
12181
707
    case 128:
12182
707
      oappend (ins, "{1to2}");
12183
707
      break;
12184
1.50k
    case 256:
12185
1.50k
      oappend (ins, "{1to4}");
12186
1.50k
      break;
12187
1.35k
    case 512:
12188
1.35k
      oappend (ins, "{1to8}");
12189
1.35k
      break;
12190
0
    default:
12191
0
      abort ();
12192
3.56k
    }
12193
3.56k
      }
12194
2.96k
    else if (bytemode == x_mode
12195
2.96k
       || bytemode == evex_half_bcst_xmmqh_mode)
12196
1.87k
      {
12197
1.87k
        switch (ins->vex.length)
12198
1.87k
    {
12199
541
    case 128:
12200
541
      oappend (ins, "{1to4}");
12201
541
      break;
12202
336
    case 256:
12203
336
      oappend (ins, "{1to8}");
12204
336
      break;
12205
1.00k
    case 512:
12206
1.00k
      oappend (ins, "{1to16}");
12207
1.00k
      break;
12208
0
    default:
12209
0
      abort ();
12210
1.87k
    }
12211
1.87k
      }
12212
1.09k
    else
12213
1.09k
      ins->vex.no_broadcast = true;
12214
8.70k
  }
12215
12.4k
      if (ins->vex.no_broadcast)
12216
3.86k
  oappend (ins, "{bad}");
12217
12.4k
    }
12218
12219
9.07M
  return true;
12220
9.07M
}
12221
12222
static bool
12223
OP_E (instr_info *ins, int bytemode, int sizeflag)
12224
10.0M
{
12225
  /* Skip mod/rm byte.  */
12226
10.0M
  MODRM_CHECK;
12227
10.0M
  if (!ins->has_skipped_modrm)
12228
10.0M
    {
12229
10.0M
      ins->codep++;
12230
10.0M
      ins->has_skipped_modrm = true;
12231
10.0M
    }
12232
12233
10.0M
  if (ins->modrm.mod == 3)
12234
1.15M
    {
12235
1.15M
      if ((sizeflag & SUFFIX_ALWAYS)
12236
1.15M
    && (bytemode == b_swap_mode
12237
3.19k
        || bytemode == bnd_swap_mode
12238
3.19k
        || bytemode == v_swap_mode))
12239
698
  swap_operand (ins);
12240
12241
1.15M
      print_register (ins, ins->modrm.rm, REX_B, bytemode, sizeflag);
12242
1.15M
      return true;
12243
1.15M
    }
12244
12245
  /* Masking is invalid for insns with GPR-like memory destination. Set the
12246
     flag uniformly, as the consumer will inspect it only for the destination
12247
     operand.  */
12248
8.86M
  if (ins->vex.mask_register_specifier)
12249
937
    ins->illegal_masking = true;
12250
12251
8.86M
  return OP_E_memory (ins, bytemode, sizeflag);
12252
10.0M
}
12253
12254
static bool
12255
OP_indirE (instr_info *ins, int bytemode, int sizeflag)
12256
84.9k
{
12257
84.9k
  if (ins->modrm.mod == 3 && bytemode == f_mode)
12258
    /* bad lcall/ljmp */
12259
7.50k
    return BadOp (ins);
12260
77.4k
  if (!ins->intel_syntax)
12261
68.3k
    oappend (ins, "*");
12262
77.4k
  return OP_E (ins, bytemode, sizeflag);
12263
84.9k
}
12264
12265
static bool
12266
OP_G (instr_info *ins, int bytemode, int sizeflag)
12267
9.06M
{
12268
9.06M
  print_register (ins, ins->modrm.reg, REX_R, bytemode, sizeflag);
12269
9.06M
  return true;
12270
9.06M
}
12271
12272
static bool
12273
OP_REG (instr_info *ins, int code, int sizeflag)
12274
2.02M
{
12275
2.02M
  const char *s;
12276
2.02M
  int add = 0;
12277
12278
2.02M
  switch (code)
12279
2.02M
    {
12280
129k
    case es_reg: case ss_reg: case cs_reg:
12281
145k
    case ds_reg: case fs_reg: case gs_reg:
12282
145k
      oappend_register (ins, att_names_seg[code - es_reg]);
12283
145k
      return true;
12284
2.02M
    }
12285
12286
1.87M
  USED_REX (REX_B);
12287
1.87M
  if (ins->rex & REX_B)
12288
96.8k
    add = 8;
12289
1.87M
  if (ins->rex2 & REX_B)
12290
2.08k
    add += 16;
12291
12292
1.87M
  switch (code)
12293
1.87M
    {
12294
0
    case ax_reg: case cx_reg: case dx_reg: case bx_reg:
12295
0
    case sp_reg: case bp_reg: case si_reg: case di_reg:
12296
0
      s = att_names16[code - ax_reg + add];
12297
0
      break;
12298
77.0k
    case ah_reg: case ch_reg: case dh_reg: case bh_reg:
12299
77.0k
      USED_REX (0);
12300
      /* Fall through.  */
12301
167k
    case al_reg: case cl_reg: case dl_reg: case bl_reg:
12302
167k
      if (ins->rex)
12303
5.34k
  s = att_names8rex[code - al_reg + add];
12304
162k
      else
12305
162k
  s = att_names8[code - al_reg];
12306
167k
      break;
12307
364k
    case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
12308
951k
    case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
12309
951k
      if (ins->address_mode == mode_64bit
12310
951k
    && ((sizeflag & DFLAG) || (ins->rex & REX_W)))
12311
681k
  {
12312
681k
    s = att_names64[code - rAX_reg + add];
12313
681k
    break;
12314
681k
  }
12315
270k
      code += eAX_reg - rAX_reg;
12316
      /* Fall through.  */
12317
550k
    case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
12318
1.02M
    case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
12319
1.02M
      USED_REX (REX_W);
12320
1.02M
      if (ins->rex & REX_W)
12321
10.7k
  s = att_names64[code - eAX_reg + add];
12322
1.01M
      else
12323
1.01M
  {
12324
1.01M
    if (sizeflag & DFLAG)
12325
974k
      s = att_names32[code - eAX_reg + add];
12326
41.1k
    else
12327
41.1k
      s = att_names16[code - eAX_reg + add];
12328
1.01M
    ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12329
1.01M
  }
12330
1.02M
      break;
12331
0
    default:
12332
0
      oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
12333
0
      return true;
12334
1.87M
    }
12335
1.87M
  oappend_register (ins, s);
12336
1.87M
  return true;
12337
1.87M
}
12338
12339
static bool
12340
OP_IMREG (instr_info *ins, int code, int sizeflag)
12341
2.17M
{
12342
2.17M
  const char *s;
12343
12344
2.17M
  switch (code)
12345
2.17M
    {
12346
445k
    case indir_dx_reg:
12347
445k
      if (!ins->intel_syntax)
12348
418k
  {
12349
418k
    oappend (ins, "(%dx)");
12350
418k
    return true;
12351
418k
  }
12352
26.0k
      s = att_names16[dx_reg - ax_reg];
12353
26.0k
      break;
12354
765k
    case al_reg: case cl_reg:
12355
765k
      s = att_names8[code - al_reg];
12356
765k
      break;
12357
888k
    case eAX_reg:
12358
888k
      USED_REX (REX_W);
12359
888k
      if (ins->rex & REX_W)
12360
15.1k
  {
12361
15.1k
    s = *att_names64;
12362
15.1k
    break;
12363
15.1k
  }
12364
      /* Fall through.  */
12365
952k
    case z_mode_ax_reg:
12366
952k
      if ((ins->rex & REX_W) || (sizeflag & DFLAG))
12367
921k
  s = *att_names32;
12368
31.3k
      else
12369
31.3k
  s = *att_names16;
12370
952k
      if (!(ins->rex & REX_W))
12371
951k
  ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12372
952k
      break;
12373
0
    default:
12374
0
      oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
12375
0
      return true;
12376
2.17M
    }
12377
1.75M
  oappend_register (ins, s);
12378
1.75M
  return true;
12379
2.17M
}
12380
12381
static bool
12382
OP_I (instr_info *ins, int bytemode, int sizeflag)
12383
2.19M
{
12384
2.19M
  bfd_vma op;
12385
12386
2.19M
  switch (bytemode)
12387
2.19M
    {
12388
1.06M
    case b_mode:
12389
1.06M
      if (!fetch_code (ins->info, ins->codep + 1))
12390
860
  return false;
12391
1.06M
      op = *ins->codep++;
12392
1.06M
      break;
12393
1.02M
    case v_mode:
12394
1.02M
      USED_REX (REX_W);
12395
1.02M
      if (ins->rex & REX_W)
12396
21.3k
  {
12397
21.3k
    if (!get32s (ins, &op))
12398
6
      return false;
12399
21.3k
  }
12400
1.00M
      else
12401
1.00M
  {
12402
1.00M
    ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12403
1.00M
    if (sizeflag & DFLAG)
12404
978k
      {
12405
980k
    case d_mode:
12406
980k
        if (!get32 (ins, &op))
12407
2.13k
    return false;
12408
980k
      }
12409
22.3k
    else
12410
22.3k
      {
12411
        /* Fall through.  */
12412
81.0k
    case w_mode:
12413
81.0k
        if (!get16 (ins, &op))
12414
225
    return false;
12415
81.0k
      }
12416
1.00M
  }
12417
1.08M
      break;
12418
1.08M
    case const_1_mode:
12419
45.0k
      if (ins->intel_syntax)
12420
1.27k
  oappend (ins, "1");
12421
43.7k
      else
12422
43.7k
  oappend (ins, "$1");
12423
45.0k
      return true;
12424
0
    default:
12425
0
      oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
12426
0
      return true;
12427
2.19M
    }
12428
12429
2.14M
  oappend_immediate (ins, op);
12430
2.14M
  return true;
12431
2.19M
}
12432
12433
static bool
12434
OP_I64 (instr_info *ins, int bytemode, int sizeflag)
12435
208k
{
12436
208k
  uint64_t op;
12437
12438
208k
  if (bytemode != v_mode || ins->address_mode != mode_64bit
12439
208k
      || !(ins->rex & REX_W))
12440
202k
    return OP_I (ins, bytemode, sizeflag);
12441
12442
5.96k
  USED_REX (REX_W);
12443
12444
5.96k
  if (!get64 (ins, &op))
12445
6
    return false;
12446
12447
5.95k
  oappend_immediate (ins, op);
12448
5.95k
  return true;
12449
5.96k
}
12450
12451
static bool
12452
OP_sI (instr_info *ins, int bytemode, int sizeflag)
12453
354k
{
12454
354k
  bfd_vma op;
12455
12456
354k
  switch (bytemode)
12457
354k
    {
12458
188k
    case b_mode:
12459
281k
    case b_T_mode:
12460
281k
      if (!get8s (ins, &op))
12461
144
  return false;
12462
280k
      if (bytemode == b_T_mode)
12463
92.7k
  {
12464
92.7k
    if (ins->address_mode != mode_64bit
12465
92.7k
        || !((sizeflag & DFLAG) || (ins->rex & REX_W)))
12466
16.4k
      {
12467
        /* The operand-size prefix is overridden by a REX prefix.  */
12468
16.4k
        if ((sizeflag & DFLAG) || (ins->rex & REX_W))
12469
15.0k
    op &= 0xffffffff;
12470
1.37k
        else
12471
1.37k
    op &= 0xffff;
12472
16.4k
    }
12473
92.7k
  }
12474
188k
      else
12475
188k
  {
12476
188k
    if (!(ins->rex & REX_W))
12477
160k
      {
12478
160k
        if (sizeflag & DFLAG)
12479
155k
    op &= 0xffffffff;
12480
4.72k
        else
12481
4.72k
    op &= 0xffff;
12482
160k
      }
12483
188k
  }
12484
280k
      break;
12485
73.1k
    case v_mode:
12486
      /* The operand-size prefix is overridden by a REX prefix.  */
12487
73.1k
      if (!(sizeflag & DFLAG) && !(ins->rex & REX_W))
12488
2.75k
  {
12489
2.75k
    if (!get16 (ins, &op))
12490
63
      return false;
12491
2.75k
  }
12492
70.4k
      else if (!get32s (ins, &op))
12493
117
  return false;
12494
73.0k
      break;
12495
73.0k
    default:
12496
0
      oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
12497
0
      return true;
12498
354k
    }
12499
12500
353k
  oappend_immediate (ins, op);
12501
353k
  return true;
12502
354k
}
12503
12504
static bool
12505
OP_J (instr_info *ins, int bytemode, int sizeflag)
12506
1.53M
{
12507
1.53M
  bfd_vma disp;
12508
1.53M
  bfd_vma mask = -1;
12509
1.53M
  bfd_vma segment = 0;
12510
12511
1.53M
  switch (bytemode)
12512
1.53M
    {
12513
1.15M
    case b_mode:
12514
1.15M
      if (!get8s (ins, &disp))
12515
905
  return false;
12516
1.15M
      break;
12517
1.15M
    case v_mode:
12518
381k
    case dqw_mode:
12519
381k
      if ((sizeflag & DFLAG)
12520
381k
    || (ins->address_mode == mode_64bit
12521
3.66k
        && ((ins->isa64 == intel64 && bytemode != dqw_mode)
12522
1.32k
      || (ins->rex & REX_W))))
12523
378k
  {
12524
378k
    if (!get32s (ins, &disp))
12525
195
      return false;
12526
378k
  }
12527
3.13k
      else
12528
3.13k
  {
12529
3.13k
    if (!get16s (ins, &disp))
12530
112
      return false;
12531
    /* In 16bit mode, address is wrapped around at 64k within
12532
       the same segment.  Otherwise, a data16 prefix on a jump
12533
       instruction means that the pc is masked to 16 bits after
12534
       the displacement is added!  */
12535
3.02k
    mask = 0xffff;
12536
3.02k
    if ((ins->prefixes & PREFIX_DATA) == 0)
12537
2.76k
      segment = ((ins->start_pc + (ins->codep - ins->start_codep))
12538
2.76k
           & ~((bfd_vma) 0xffff));
12539
3.02k
  }
12540
381k
      if (ins->address_mode != mode_64bit
12541
381k
    || (ins->isa64 != intel64 && !(ins->rex & REX_W)))
12542
380k
  ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12543
381k
      break;
12544
0
    default:
12545
0
      oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
12546
0
      return true;
12547
1.53M
    }
12548
1.53M
  disp = ((ins->start_pc + (ins->codep - ins->start_codep) + disp) & mask)
12549
1.53M
   | segment;
12550
1.53M
  set_op (ins, disp, false);
12551
1.53M
  print_operand_value (ins, disp, dis_style_text);
12552
1.53M
  return true;
12553
1.53M
}
12554
12555
static bool
12556
OP_SEG (instr_info *ins, int bytemode, int sizeflag)
12557
122k
{
12558
122k
  if (bytemode == w_mode)
12559
38.5k
    {
12560
38.5k
      oappend_register (ins, att_names_seg[ins->modrm.reg]);
12561
38.5k
      return true;
12562
38.5k
    }
12563
84.0k
  return OP_E (ins, ins->modrm.mod == 3 ? bytemode : w_mode, sizeflag);
12564
122k
}
12565
12566
static bool
12567
OP_DIR (instr_info *ins, int dummy ATTRIBUTE_UNUSED, int sizeflag)
12568
8.90k
{
12569
8.90k
  bfd_vma seg, offset;
12570
8.90k
  int res;
12571
8.90k
  char scratch[24];
12572
12573
8.90k
  if (sizeflag & DFLAG)
12574
7.43k
    {
12575
7.43k
      if (!get32 (ins, &offset))
12576
7.40k
  return false;;
12577
7.40k
    }
12578
1.47k
  else if (!get16 (ins, &offset))
12579
57
    return false;
12580
8.81k
  if (!get16 (ins, &seg))
12581
8.79k
    return false;;
12582
8.79k
  ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12583
12584
8.79k
  res = snprintf (scratch, ARRAY_SIZE (scratch),
12585
8.79k
      ins->intel_syntax ? "0x%x:0x%x" : "$0x%x,$0x%x",
12586
8.79k
      (unsigned) seg, (unsigned) offset);
12587
8.79k
  if (res < 0 || (size_t) res >= ARRAY_SIZE (scratch))
12588
0
    abort ();
12589
8.79k
  oappend (ins, scratch);
12590
8.79k
  return true;
12591
8.79k
}
12592
12593
static bool
12594
OP_OFF (instr_info *ins, int bytemode, int sizeflag)
12595
32.7k
{
12596
32.7k
  bfd_vma off;
12597
12598
32.7k
  if (ins->intel_syntax && (sizeflag & SUFFIX_ALWAYS))
12599
236
    intel_operand_size (ins, bytemode, sizeflag);
12600
32.7k
  append_seg (ins);
12601
12602
32.7k
  if ((sizeflag & AFLAG) || ins->address_mode == mode_64bit)
12603
24.8k
    {
12604
24.8k
      if (!get32 (ins, &off))
12605
80
  return false;
12606
24.8k
    }
12607
7.92k
  else
12608
7.92k
    {
12609
7.92k
      if (!get16 (ins, &off))
12610
126
  return false;
12611
7.92k
    }
12612
12613
32.5k
  if (ins->intel_syntax)
12614
3.27k
    {
12615
3.27k
      if (!ins->active_seg_prefix)
12616
2.84k
  {
12617
2.84k
    oappend_register (ins, att_names_seg[ds_reg - es_reg]);
12618
2.84k
    oappend (ins, ":");
12619
2.84k
  }
12620
3.27k
    }
12621
32.5k
  print_operand_value (ins, off, dis_style_address_offset);
12622
32.5k
  return true;
12623
32.7k
}
12624
12625
static bool
12626
OP_OFF64 (instr_info *ins, int bytemode, int sizeflag)
12627
95.5k
{
12628
95.5k
  uint64_t off;
12629
12630
95.5k
  if (ins->address_mode != mode_64bit
12631
95.5k
      || (ins->prefixes & PREFIX_ADDR))
12632
32.7k
    return OP_OFF (ins, bytemode, sizeflag);
12633
12634
62.7k
  if (ins->intel_syntax && (sizeflag & SUFFIX_ALWAYS))
12635
204
    intel_operand_size (ins, bytemode, sizeflag);
12636
62.7k
  append_seg (ins);
12637
12638
62.7k
  if (!get64 (ins, &off))
12639
326
    return false;
12640
12641
62.4k
  if (ins->intel_syntax)
12642
4.61k
    {
12643
4.61k
      if (!ins->active_seg_prefix)
12644
4.30k
  {
12645
4.30k
    oappend_register (ins, att_names_seg[ds_reg - es_reg]);
12646
4.30k
    oappend (ins, ":");
12647
4.30k
  }
12648
4.61k
    }
12649
62.4k
  print_operand_value (ins, off, dis_style_address_offset);
12650
62.4k
  return true;
12651
62.7k
}
12652
12653
static void
12654
ptr_reg (instr_info *ins, int code, int sizeflag)
12655
638k
{
12656
638k
  const char *s;
12657
12658
638k
  *ins->obufp++ = ins->open_char;
12659
638k
  ins->used_prefixes |= (ins->prefixes & PREFIX_ADDR);
12660
638k
  if (ins->address_mode == mode_64bit)
12661
484k
    {
12662
484k
      if (!(sizeflag & AFLAG))
12663
7.68k
  s = att_names32[code - eAX_reg];
12664
476k
      else
12665
476k
  s = att_names64[code - eAX_reg];
12666
484k
    }
12667
154k
  else if (sizeflag & AFLAG)
12668
138k
    s = att_names32[code - eAX_reg];
12669
16.3k
  else
12670
16.3k
    s = att_names16[code - eAX_reg];
12671
638k
  oappend_register (ins, s);
12672
638k
  oappend_char (ins, ins->close_char);
12673
638k
}
12674
12675
static bool
12676
OP_ESreg (instr_info *ins, int code, int sizeflag)
12677
312k
{
12678
312k
  if (ins->intel_syntax)
12679
19.2k
    {
12680
19.2k
      switch (ins->codep[-1])
12681
19.2k
  {
12682
3.03k
  case 0x6d:  /* insw/insl */
12683
3.03k
    intel_operand_size (ins, z_mode, sizeflag);
12684
3.03k
    break;
12685
2.28k
  case 0xa5:  /* movsw/movsl/movsq */
12686
4.01k
  case 0xa7:  /* cmpsw/cmpsl/cmpsq */
12687
5.10k
  case 0xab:  /* stosw/stosl */
12688
6.43k
  case 0xaf:  /* scasw/scasl */
12689
6.43k
    intel_operand_size (ins, v_mode, sizeflag);
12690
6.43k
    break;
12691
9.82k
  default:
12692
9.82k
    intel_operand_size (ins, b_mode, sizeflag);
12693
19.2k
  }
12694
19.2k
    }
12695
312k
  oappend_register (ins, att_names_seg[0]);
12696
312k
  oappend_char (ins, ':');
12697
312k
  ptr_reg (ins, code, sizeflag);
12698
312k
  return true;
12699
312k
}
12700
12701
static bool
12702
OP_DSreg (instr_info *ins, int code, int sizeflag)
12703
326k
{
12704
326k
  if (ins->intel_syntax)
12705
26.1k
    {
12706
26.1k
      switch (ins->codep[-1])
12707
26.1k
  {
12708
10.0k
  case 0x6f:  /* outsw/outsl */
12709
10.0k
    intel_operand_size (ins, z_mode, sizeflag);
12710
10.0k
    break;
12711
2.28k
  case 0xa5:  /* movsw/movsl/movsq */
12712
4.01k
  case 0xa7:  /* cmpsw/cmpsl/cmpsq */
12713
6.13k
  case 0xad:  /* lodsw/lodsl/lodsq */
12714
6.13k
    intel_operand_size (ins, v_mode, sizeflag);
12715
6.13k
    break;
12716
9.93k
  default:
12717
9.93k
    intel_operand_size (ins, b_mode, sizeflag);
12718
26.1k
  }
12719
26.1k
    }
12720
  /* Set ins->active_seg_prefix to PREFIX_DS if it is unset so that the
12721
     default segment register DS is printed.  */
12722
326k
  if (!ins->active_seg_prefix)
12723
311k
    ins->active_seg_prefix = PREFIX_DS;
12724
326k
  append_seg (ins);
12725
326k
  ptr_reg (ins, code, sizeflag);
12726
326k
  return true;
12727
326k
}
12728
12729
static bool
12730
OP_C (instr_info *ins, int dummy ATTRIBUTE_UNUSED,
12731
      int sizeflag ATTRIBUTE_UNUSED)
12732
2.84k
{
12733
2.84k
  int add, res;
12734
2.84k
  char scratch[8];
12735
12736
2.84k
  if (ins->rex & REX_R)
12737
1.54k
    {
12738
1.54k
      USED_REX (REX_R);
12739
1.54k
      add = 8;
12740
1.54k
    }
12741
1.30k
  else if (ins->address_mode != mode_64bit && (ins->prefixes & PREFIX_LOCK))
12742
286
    {
12743
286
      ins->all_prefixes[ins->last_lock_prefix] = 0;
12744
286
      ins->used_prefixes |= PREFIX_LOCK;
12745
286
      add = 8;
12746
286
    }
12747
1.01k
  else
12748
1.01k
    add = 0;
12749
2.84k
  res = snprintf (scratch, ARRAY_SIZE (scratch), "%%cr%d",
12750
2.84k
      ins->modrm.reg + add);
12751
2.84k
  if (res < 0 || (size_t) res >= ARRAY_SIZE (scratch))
12752
0
    abort ();
12753
2.84k
  oappend_register (ins, scratch);
12754
2.84k
  return true;
12755
2.84k
}
12756
12757
static bool
12758
OP_D (instr_info *ins, int dummy ATTRIBUTE_UNUSED,
12759
      int sizeflag ATTRIBUTE_UNUSED)
12760
793
{
12761
793
  int add, res;
12762
793
  char scratch[8];
12763
12764
793
  USED_REX (REX_R);
12765
793
  if (ins->rex & REX_R)
12766
221
    add = 8;
12767
572
  else
12768
572
    add = 0;
12769
793
  res = snprintf (scratch, ARRAY_SIZE (scratch),
12770
793
      ins->intel_syntax ? "dr%d" : "%%db%d",
12771
793
      ins->modrm.reg + add);
12772
793
  if (res < 0 || (size_t) res >= ARRAY_SIZE (scratch))
12773
0
    abort ();
12774
793
  oappend (ins, scratch);
12775
793
  return true;
12776
793
}
12777
12778
static bool
12779
OP_T (instr_info *ins, int dummy ATTRIBUTE_UNUSED,
12780
      int sizeflag ATTRIBUTE_UNUSED)
12781
338
{
12782
338
  int res;
12783
338
  char scratch[8];
12784
12785
338
  res = snprintf (scratch, ARRAY_SIZE (scratch), "%%tr%d", ins->modrm.reg);
12786
338
  if (res < 0 || (size_t) res >= ARRAY_SIZE (scratch))
12787
0
    abort ();
12788
338
  oappend_register (ins, scratch);
12789
338
  return true;
12790
338
}
12791
12792
static bool
12793
OP_MMX (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
12794
  int sizeflag ATTRIBUTE_UNUSED)
12795
67.8k
{
12796
67.8k
  int reg = ins->modrm.reg;
12797
67.8k
  const char (*names)[8];
12798
12799
67.8k
  ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12800
67.8k
  if (ins->prefixes & PREFIX_DATA)
12801
4.48k
    {
12802
4.48k
      names = att_names_xmm;
12803
4.48k
      USED_REX (REX_R);
12804
4.48k
      if (ins->rex & REX_R)
12805
3.53k
  reg += 8;
12806
4.48k
    }
12807
63.3k
  else
12808
63.3k
    names = att_names_mm;
12809
67.8k
  oappend_register (ins, names[reg]);
12810
67.8k
  return true;
12811
67.8k
}
12812
12813
static void
12814
print_vector_reg (instr_info *ins, unsigned int reg, int bytemode)
12815
102k
{
12816
102k
  const char (*names)[8];
12817
12818
102k
  if (bytemode == xmmq_mode
12819
102k
      || bytemode == evex_half_bcst_xmmqh_mode
12820
102k
      || bytemode == evex_half_bcst_xmmq_mode)
12821
2.27k
    {
12822
2.27k
      switch (ins->vex.length)
12823
2.27k
  {
12824
266
  case 0:
12825
1.34k
  case 128:
12826
1.69k
  case 256:
12827
1.69k
    names = att_names_xmm;
12828
1.69k
    break;
12829
578
  case 512:
12830
578
    names = att_names_ymm;
12831
578
    ins->evex_used |= EVEX_len_used;
12832
578
    break;
12833
0
  default:
12834
0
    abort ();
12835
2.27k
  }
12836
2.27k
    }
12837
99.8k
  else if (bytemode == ymm_mode)
12838
194
    names = att_names_ymm;
12839
99.6k
  else if (bytemode == tmm_mode)
12840
3.25k
    {
12841
3.25k
      if (reg >= 8)
12842
1.31k
  {
12843
1.31k
    oappend (ins, "(bad)");
12844
1.31k
    return;
12845
1.31k
  }
12846
1.94k
      names = att_names_tmm;
12847
1.94k
    }
12848
96.4k
  else if (ins->need_vex
12849
96.4k
     && bytemode != xmm_mode
12850
96.4k
     && bytemode != scalar_mode
12851
96.4k
     && bytemode != xmmdw_mode
12852
96.4k
     && bytemode != xmmqd_mode
12853
96.4k
     && bytemode != evex_half_bcst_xmmqdh_mode
12854
96.4k
     && bytemode != w_swap_mode
12855
96.4k
     && bytemode != b_mode
12856
96.4k
     && bytemode != w_mode
12857
96.4k
     && bytemode != d_mode
12858
96.4k
     && bytemode != q_mode)
12859
51.7k
    {
12860
51.7k
      ins->evex_used |= EVEX_len_used;
12861
51.7k
      switch (ins->vex.length)
12862
51.7k
  {
12863
21.9k
  case 128:
12864
21.9k
    names = att_names_xmm;
12865
21.9k
    break;
12866
15.4k
  case 256:
12867
15.4k
    if (ins->vex.w
12868
15.4k
        || bytemode != vex_vsib_q_w_dq_mode)
12869
13.6k
      names = att_names_ymm;
12870
1.79k
    else
12871
1.79k
      names = att_names_xmm;
12872
15.4k
    break;
12873
14.3k
  case 512:
12874
14.3k
    if (ins->vex.w
12875
14.3k
        || bytemode != vex_vsib_q_w_dq_mode)
12876
13.6k
      names = att_names_zmm;
12877
751
    else
12878
751
      names = att_names_ymm;
12879
14.3k
    break;
12880
0
  default:
12881
0
    abort ();
12882
51.7k
  }
12883
51.7k
    }
12884
44.6k
  else
12885
44.6k
    names = att_names_xmm;
12886
100k
  oappend_register (ins, names[reg]);
12887
100k
}
12888
12889
static bool
12890
OP_XMM (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
12891
80.2k
{
12892
80.2k
  unsigned int reg = ins->modrm.reg;
12893
12894
80.2k
  USED_REX (REX_R);
12895
80.2k
  if (ins->rex & REX_R)
12896
26.4k
    reg += 8;
12897
80.2k
  if (ins->vex.evex)
12898
31.0k
    {
12899
31.0k
      if (ins->rex2 & REX_R)
12900
16.8k
  reg += 16;
12901
31.0k
    }
12902
12903
80.2k
  if (bytemode == tmm_mode)
12904
1.77k
    ins->modrm.reg = reg;
12905
78.4k
  else if (bytemode == scalar_mode)
12906
11.8k
    ins->vex.no_broadcast = true;
12907
12908
80.2k
  print_vector_reg (ins, reg, bytemode);
12909
80.2k
  return true;
12910
80.2k
}
12911
12912
static bool
12913
OP_EM (instr_info *ins, int bytemode, int sizeflag)
12914
67.3k
{
12915
67.3k
  int reg;
12916
67.3k
  const char (*names)[8];
12917
12918
67.3k
  if (ins->modrm.mod != 3)
12919
57.4k
    {
12920
57.4k
      if (ins->intel_syntax
12921
57.4k
    && (bytemode == v_mode || bytemode == v_swap_mode))
12922
4.39k
  {
12923
4.39k
    bytemode = (ins->prefixes & PREFIX_DATA) ? x_mode : q_mode;
12924
4.39k
    ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12925
4.39k
  }
12926
57.4k
      return OP_E (ins, bytemode, sizeflag);
12927
57.4k
    }
12928
12929
9.89k
  if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
12930
190
    swap_operand (ins);
12931
12932
  /* Skip mod/rm byte.  */
12933
9.89k
  MODRM_CHECK;
12934
9.89k
  ins->codep++;
12935
9.89k
  ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12936
9.89k
  reg = ins->modrm.rm;
12937
9.89k
  if (ins->prefixes & PREFIX_DATA)
12938
3.53k
    {
12939
3.53k
      names = att_names_xmm;
12940
3.53k
      USED_REX (REX_B);
12941
3.53k
      if (ins->rex & REX_B)
12942
3.05k
  reg += 8;
12943
3.53k
    }
12944
6.35k
  else
12945
6.35k
    names = att_names_mm;
12946
9.89k
  oappend_register (ins, names[reg]);
12947
9.89k
  return true;
12948
9.89k
}
12949
12950
/* cvt* are the only instructions in sse2 which have
12951
   both SSE and MMX operands and also have 0x66 prefix
12952
   in their opcode. 0x66 was originally used to differentiate
12953
   between SSE and MMX instruction(operands). So we have to handle the
12954
   cvt* separately using OP_EMC and OP_MXC */
12955
static bool
12956
OP_EMC (instr_info *ins, int bytemode, int sizeflag)
12957
908
{
12958
908
  if (ins->modrm.mod != 3)
12959
564
    {
12960
564
      if (ins->intel_syntax && bytemode == v_mode)
12961
0
  {
12962
0
    bytemode = (ins->prefixes & PREFIX_DATA) ? x_mode : q_mode;
12963
0
    ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12964
0
  }
12965
564
      return OP_E (ins, bytemode, sizeflag);
12966
564
    }
12967
12968
  /* Skip mod/rm byte.  */
12969
344
  MODRM_CHECK;
12970
344
  ins->codep++;
12971
344
  ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12972
344
  oappend_register (ins, att_names_mm[ins->modrm.rm]);
12973
344
  return true;
12974
344
}
12975
12976
static bool
12977
OP_MXC (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
12978
  int sizeflag ATTRIBUTE_UNUSED)
12979
508
{
12980
508
  ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12981
508
  oappend_register (ins, att_names_mm[ins->modrm.reg]);
12982
508
  return true;
12983
508
}
12984
12985
static bool
12986
OP_EX (instr_info *ins, int bytemode, int sizeflag)
12987
72.8k
{
12988
72.8k
  int reg;
12989
12990
  /* Skip mod/rm byte.  */
12991
72.8k
  MODRM_CHECK;
12992
72.8k
  ins->codep++;
12993
12994
72.8k
  if (bytemode == dq_mode)
12995
553
    bytemode = ins->vex.w ? q_mode : d_mode;
12996
12997
72.8k
  if (ins->modrm.mod != 3)
12998
50.9k
    return OP_E_memory (ins, bytemode, sizeflag);
12999
13000
21.8k
  reg = ins->modrm.rm;
13001
21.8k
  USED_REX (REX_B);
13002
21.8k
  if (ins->rex & REX_B)
13003
6.25k
    reg += 8;
13004
21.8k
  if (ins->rex2 & REX_B)
13005
459
    reg += 16;
13006
21.8k
  if (ins->vex.evex)
13007
7.81k
    {
13008
7.81k
      USED_REX (REX_X);
13009
7.81k
      if ((ins->rex & REX_X))
13010
1.58k
  reg += 16;
13011
7.81k
    }
13012
13013
21.8k
  if ((sizeflag & SUFFIX_ALWAYS)
13014
21.8k
      && (bytemode == x_swap_mode
13015
2.06k
    || bytemode == w_swap_mode
13016
2.06k
    || bytemode == d_swap_mode
13017
2.06k
    || bytemode == q_swap_mode))
13018
898
    swap_operand (ins);
13019
13020
21.8k
  if (bytemode == tmm_mode)
13021
1.47k
    ins->modrm.rm = reg;
13022
13023
21.8k
  print_vector_reg (ins, reg, bytemode);
13024
21.8k
  return true;
13025
72.8k
}
13026
13027
static bool
13028
OP_R (instr_info *ins, int bytemode, int sizeflag)
13029
9.94k
{
13030
9.94k
  if (ins->modrm.mod != 3)
13031
1.59k
    return BadOp (ins);
13032
13033
8.35k
  switch (bytemode)
13034
8.35k
    {
13035
1.76k
    case d_mode:
13036
1.97k
    case dq_mode:
13037
2.19k
    case q_mode:
13038
3.09k
    case mask_mode:
13039
3.09k
      return OP_E (ins, bytemode, sizeflag);
13040
672
    case q_mm_mode:
13041
672
      return OP_EM (ins, x_mode, sizeflag);
13042
3.01k
    case xmm_mode:
13043
3.01k
      if (ins->vex.length <= 128)
13044
529
  break;
13045
2.48k
      return BadOp (ins);
13046
8.35k
    }
13047
13048
2.10k
  return OP_EX (ins, bytemode, sizeflag);
13049
8.35k
}
13050
13051
static bool
13052
OP_M (instr_info *ins, int bytemode, int sizeflag)
13053
174k
{
13054
  /* Skip mod/rm byte.  */
13055
174k
  MODRM_CHECK;
13056
174k
  ins->codep++;
13057
13058
174k
  if (ins->modrm.mod == 3)
13059
    /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
13060
6.47k
    return BadOp (ins);
13061
13062
168k
  if (bytemode == x_mode)
13063
618
    ins->vex.no_broadcast = true;
13064
13065
168k
  return OP_E_memory (ins, bytemode, sizeflag);
13066
174k
}
13067
13068
static bool
13069
OP_0f07 (instr_info *ins, int bytemode, int sizeflag)
13070
1.78k
{
13071
1.78k
  if (ins->modrm.mod != 3 || ins->modrm.rm != 0)
13072
1.46k
    return BadOp (ins);
13073
322
  return OP_E (ins, bytemode, sizeflag);
13074
1.78k
}
13075
13076
/* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
13077
   32bit mode and "xchg %rax,%rax" in 64bit mode.  */
13078
13079
static bool
13080
NOP_Fixup (instr_info *ins, int opnd, int sizeflag)
13081
256k
{
13082
256k
  if ((ins->prefixes & PREFIX_DATA) == 0 && (ins->rex & REX_B) == 0)
13083
242k
    {
13084
242k
      ins->mnemonicendp = stpcpy (ins->obuf, "nop");
13085
242k
      return true;
13086
242k
    }
13087
13.0k
  if (opnd == 0)
13088
6.54k
    return OP_REG (ins, eAX_reg, sizeflag);
13089
6.54k
  return OP_IMREG (ins, eAX_reg, sizeflag);
13090
13.0k
}
13091
13092
static const char *const Suffix3DNow[] = {
13093
/* 00 */  NULL,   NULL,   NULL,   NULL,
13094
/* 04 */  NULL,   NULL,   NULL,   NULL,
13095
/* 08 */  NULL,   NULL,   NULL,   NULL,
13096
/* 0C */  "pi2fw",  "pi2fd",  NULL,   NULL,
13097
/* 10 */  NULL,   NULL,   NULL,   NULL,
13098
/* 14 */  NULL,   NULL,   NULL,   NULL,
13099
/* 18 */  NULL,   NULL,   NULL,   NULL,
13100
/* 1C */  "pf2iw",  "pf2id",  NULL,   NULL,
13101
/* 20 */  NULL,   NULL,   NULL,   NULL,
13102
/* 24 */  NULL,   NULL,   NULL,   NULL,
13103
/* 28 */  NULL,   NULL,   NULL,   NULL,
13104
/* 2C */  NULL,   NULL,   NULL,   NULL,
13105
/* 30 */  NULL,   NULL,   NULL,   NULL,
13106
/* 34 */  NULL,   NULL,   NULL,   NULL,
13107
/* 38 */  NULL,   NULL,   NULL,   NULL,
13108
/* 3C */  NULL,   NULL,   NULL,   NULL,
13109
/* 40 */  NULL,   NULL,   NULL,   NULL,
13110
/* 44 */  NULL,   NULL,   NULL,   NULL,
13111
/* 48 */  NULL,   NULL,   NULL,   NULL,
13112
/* 4C */  NULL,   NULL,   NULL,   NULL,
13113
/* 50 */  NULL,   NULL,   NULL,   NULL,
13114
/* 54 */  NULL,   NULL,   NULL,   NULL,
13115
/* 58 */  NULL,   NULL,   NULL,   NULL,
13116
/* 5C */  NULL,   NULL,   NULL,   NULL,
13117
/* 60 */  NULL,   NULL,   NULL,   NULL,
13118
/* 64 */  NULL,   NULL,   NULL,   NULL,
13119
/* 68 */  NULL,   NULL,   NULL,   NULL,
13120
/* 6C */  NULL,   NULL,   NULL,   NULL,
13121
/* 70 */  NULL,   NULL,   NULL,   NULL,
13122
/* 74 */  NULL,   NULL,   NULL,   NULL,
13123
/* 78 */  NULL,   NULL,   NULL,   NULL,
13124
/* 7C */  NULL,   NULL,   NULL,   NULL,
13125
/* 80 */  NULL,   NULL,   NULL,   NULL,
13126
/* 84 */  NULL,   NULL,   NULL,   NULL,
13127
/* 88 */  NULL,   NULL,   "pfnacc", NULL,
13128
/* 8C */  NULL,   NULL,   "pfpnacc",  NULL,
13129
/* 90 */  "pfcmpge",  NULL,   NULL,   NULL,
13130
/* 94 */  "pfmin",  NULL,   "pfrcp",  "pfrsqrt",
13131
/* 98 */  NULL,   NULL,   "pfsub",  NULL,
13132
/* 9C */  NULL,   NULL,   "pfadd",  NULL,
13133
/* A0 */  "pfcmpgt",  NULL,   NULL,   NULL,
13134
/* A4 */  "pfmax",  NULL,   "pfrcpit1", "pfrsqit1",
13135
/* A8 */  NULL,   NULL,   "pfsubr", NULL,
13136
/* AC */  NULL,   NULL,   "pfacc",  NULL,
13137
/* B0 */  "pfcmpeq",  NULL,   NULL,   NULL,
13138
/* B4 */  "pfmul",  NULL,   "pfrcpit2", "pmulhrw",
13139
/* B8 */  NULL,   NULL,   NULL,   "pswapd",
13140
/* BC */  NULL,   NULL,   NULL,   "pavgusb",
13141
/* C0 */  NULL,   NULL,   NULL,   NULL,
13142
/* C4 */  NULL,   NULL,   NULL,   NULL,
13143
/* C8 */  NULL,   NULL,   NULL,   NULL,
13144
/* CC */  NULL,   NULL,   NULL,   NULL,
13145
/* D0 */  NULL,   NULL,   NULL,   NULL,
13146
/* D4 */  NULL,   NULL,   NULL,   NULL,
13147
/* D8 */  NULL,   NULL,   NULL,   NULL,
13148
/* DC */  NULL,   NULL,   NULL,   NULL,
13149
/* E0 */  NULL,   NULL,   NULL,   NULL,
13150
/* E4 */  NULL,   NULL,   NULL,   NULL,
13151
/* E8 */  NULL,   NULL,   NULL,   NULL,
13152
/* EC */  NULL,   NULL,   NULL,   NULL,
13153
/* F0 */  NULL,   NULL,   NULL,   NULL,
13154
/* F4 */  NULL,   NULL,   NULL,   NULL,
13155
/* F8 */  NULL,   NULL,   NULL,   NULL,
13156
/* FC */  NULL,   NULL,   NULL,   NULL,
13157
};
13158
13159
static bool
13160
OP_3DNowSuffix (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13161
    int sizeflag ATTRIBUTE_UNUSED)
13162
50.2k
{
13163
50.2k
  const char *mnemonic;
13164
13165
50.2k
  if (!fetch_code (ins->info, ins->codep + 1))
13166
60
    return false;
13167
  /* AMD 3DNow! instructions are specified by an opcode suffix in the
13168
     place where an 8-bit immediate would normally go.  ie. the last
13169
     byte of the instruction.  */
13170
50.2k
  ins->obufp = ins->mnemonicendp;
13171
50.2k
  mnemonic = Suffix3DNow[*ins->codep++];
13172
50.2k
  if (mnemonic)
13173
208
    ins->obufp = stpcpy (ins->obufp, mnemonic);
13174
50.0k
  else
13175
50.0k
    {
13176
      /* Since a variable sized ins->modrm/ins->sib chunk is between the start
13177
   of the opcode (0x0f0f) and the opcode suffix, we need to do
13178
   all the ins->modrm processing first, and don't know until now that
13179
   we have a bad opcode.  This necessitates some cleaning up.  */
13180
50.0k
      ins->op_out[0][0] = '\0';
13181
50.0k
      ins->op_out[1][0] = '\0';
13182
50.0k
      BadOp (ins);
13183
50.0k
    }
13184
50.2k
  ins->mnemonicendp = ins->obufp;
13185
50.2k
  return true;
13186
50.2k
}
13187
13188
static const struct op simd_cmp_op[] =
13189
{
13190
  { STRING_COMMA_LEN ("eq") },
13191
  { STRING_COMMA_LEN ("lt") },
13192
  { STRING_COMMA_LEN ("le") },
13193
  { STRING_COMMA_LEN ("unord") },
13194
  { STRING_COMMA_LEN ("neq") },
13195
  { STRING_COMMA_LEN ("nlt") },
13196
  { STRING_COMMA_LEN ("nle") },
13197
  { STRING_COMMA_LEN ("ord") }
13198
};
13199
13200
static const struct op vex_cmp_op[] =
13201
{
13202
  { STRING_COMMA_LEN ("eq_uq") },
13203
  { STRING_COMMA_LEN ("nge") },
13204
  { STRING_COMMA_LEN ("ngt") },
13205
  { STRING_COMMA_LEN ("false") },
13206
  { STRING_COMMA_LEN ("neq_oq") },
13207
  { STRING_COMMA_LEN ("ge") },
13208
  { STRING_COMMA_LEN ("gt") },
13209
  { STRING_COMMA_LEN ("true") },
13210
  { STRING_COMMA_LEN ("eq_os") },
13211
  { STRING_COMMA_LEN ("lt_oq") },
13212
  { STRING_COMMA_LEN ("le_oq") },
13213
  { STRING_COMMA_LEN ("unord_s") },
13214
  { STRING_COMMA_LEN ("neq_us") },
13215
  { STRING_COMMA_LEN ("nlt_uq") },
13216
  { STRING_COMMA_LEN ("nle_uq") },
13217
  { STRING_COMMA_LEN ("ord_s") },
13218
  { STRING_COMMA_LEN ("eq_us") },
13219
  { STRING_COMMA_LEN ("nge_uq") },
13220
  { STRING_COMMA_LEN ("ngt_uq") },
13221
  { STRING_COMMA_LEN ("false_os") },
13222
  { STRING_COMMA_LEN ("neq_os") },
13223
  { STRING_COMMA_LEN ("ge_oq") },
13224
  { STRING_COMMA_LEN ("gt_oq") },
13225
  { STRING_COMMA_LEN ("true_us") },
13226
};
13227
13228
static bool
13229
CMP_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13230
     int sizeflag ATTRIBUTE_UNUSED)
13231
2.78k
{
13232
2.78k
  unsigned int cmp_type;
13233
13234
2.78k
  if (!fetch_code (ins->info, ins->codep + 1))
13235
5
    return false;
13236
2.78k
  cmp_type = *ins->codep++;
13237
2.78k
  if (cmp_type < ARRAY_SIZE (simd_cmp_op))
13238
424
    {
13239
424
      char suffix[3];
13240
424
      char *p = ins->mnemonicendp - 2;
13241
424
      suffix[0] = p[0];
13242
424
      suffix[1] = p[1];
13243
424
      suffix[2] = '\0';
13244
424
      sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
13245
424
      ins->mnemonicendp += simd_cmp_op[cmp_type].len;
13246
424
    }
13247
2.35k
  else if (ins->need_vex
13248
2.35k
     && cmp_type < ARRAY_SIZE (simd_cmp_op) + ARRAY_SIZE (vex_cmp_op))
13249
214
    {
13250
214
      char suffix[3];
13251
214
      char *p = ins->mnemonicendp - 2;
13252
214
      suffix[0] = p[0];
13253
214
      suffix[1] = p[1];
13254
214
      suffix[2] = '\0';
13255
214
      cmp_type -= ARRAY_SIZE (simd_cmp_op);
13256
214
      sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
13257
214
      ins->mnemonicendp += vex_cmp_op[cmp_type].len;
13258
214
    }
13259
2.14k
  else
13260
2.14k
    {
13261
      /* We have a reserved extension byte.  Output it directly.  */
13262
2.14k
      oappend_immediate (ins, cmp_type);
13263
2.14k
    }
13264
2.78k
  return true;
13265
2.78k
}
13266
13267
static bool
13268
OP_Mwait (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13269
965
{
13270
  /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx  */
13271
965
  if (!ins->intel_syntax)
13272
548
    {
13273
548
      strcpy (ins->op_out[0], att_names32[0] + ins->intel_syntax);
13274
548
      strcpy (ins->op_out[1], att_names32[1] + ins->intel_syntax);
13275
548
      if (bytemode == eBX_reg)
13276
274
  strcpy (ins->op_out[2], att_names32[3] + ins->intel_syntax);
13277
548
      ins->two_source_ops = true;
13278
548
    }
13279
  /* Skip mod/rm byte.  */
13280
965
  MODRM_CHECK;
13281
965
  ins->codep++;
13282
965
  return true;
13283
965
}
13284
13285
static bool
13286
OP_Monitor (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13287
      int sizeflag ATTRIBUTE_UNUSED)
13288
4.03k
{
13289
  /* monitor %{e,r,}ax,%ecx,%edx"  */
13290
4.03k
  if (!ins->intel_syntax)
13291
2.29k
    {
13292
2.29k
      const char (*names)[8] = (ins->address_mode == mode_64bit
13293
2.29k
        ? att_names64 : att_names32);
13294
13295
2.29k
      if (ins->prefixes & PREFIX_ADDR)
13296
287
  {
13297
    /* Remove "addr16/addr32".  */
13298
287
    ins->all_prefixes[ins->last_addr_prefix] = 0;
13299
287
    names = (ins->address_mode != mode_32bit
13300
287
       ? att_names32 : att_names16);
13301
287
    ins->used_prefixes |= PREFIX_ADDR;
13302
287
  }
13303
2.01k
      else if (ins->address_mode == mode_16bit)
13304
588
  names = att_names16;
13305
2.29k
      strcpy (ins->op_out[0], names[0] + ins->intel_syntax);
13306
2.29k
      strcpy (ins->op_out[1], att_names32[1] + ins->intel_syntax);
13307
2.29k
      strcpy (ins->op_out[2], att_names32[2] + ins->intel_syntax);
13308
2.29k
      ins->two_source_ops = true;
13309
2.29k
    }
13310
  /* Skip mod/rm byte.  */
13311
4.03k
  MODRM_CHECK;
13312
4.03k
  ins->codep++;
13313
4.03k
  return true;
13314
4.03k
}
13315
13316
static bool
13317
REP_Fixup (instr_info *ins, int bytemode, int sizeflag)
13318
475k
{
13319
  /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
13320
     lods and stos.  */
13321
475k
  if (ins->prefixes & PREFIX_REPZ)
13322
884
    ins->all_prefixes[ins->last_repz_prefix] = REP_PREFIX;
13323
13324
475k
  switch (bytemode)
13325
475k
    {
13326
26.5k
    case al_reg:
13327
44.6k
    case eAX_reg:
13328
229k
    case indir_dx_reg:
13329
229k
      return OP_IMREG (ins, bytemode, sizeflag);
13330
245k
    case eDI_reg:
13331
245k
      return OP_ESreg (ins, bytemode, sizeflag);
13332
0
    case eSI_reg:
13333
0
      return OP_DSreg (ins, bytemode, sizeflag);
13334
0
    default:
13335
0
      abort ();
13336
0
      break;
13337
475k
    }
13338
0
  return true;
13339
475k
}
13340
13341
static bool
13342
SEP_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13343
     int sizeflag ATTRIBUTE_UNUSED)
13344
1.10k
{
13345
1.10k
  if (ins->isa64 != amd64)
13346
902
    return true;
13347
13348
198
  ins->obufp = ins->obuf;
13349
198
  BadOp (ins);
13350
198
  ins->mnemonicendp = ins->obufp;
13351
198
  ++ins->codep;
13352
198
  return true;
13353
1.10k
}
13354
13355
/* For BND-prefixed instructions 0xF2 prefix should be displayed as
13356
   "bnd".  */
13357
13358
static bool
13359
BND_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13360
     int sizeflag ATTRIBUTE_UNUSED)
13361
1.54M
{
13362
1.54M
  if (ins->prefixes & PREFIX_REPNZ)
13363
2.50k
    ins->all_prefixes[ins->last_repnz_prefix] = BND_PREFIX;
13364
1.54M
  return true;
13365
1.54M
}
13366
13367
/* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
13368
   "notrack".  */
13369
13370
static bool
13371
NOTRACK_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13372
         int sizeflag ATTRIBUTE_UNUSED)
13373
55.8k
{
13374
  /* Since active_seg_prefix is not set in 64-bit mode, check whether
13375
     we've seen a PREFIX_DS.  */
13376
55.8k
  if ((ins->prefixes & PREFIX_DS) != 0
13377
55.8k
      && (ins->address_mode != mode_64bit || ins->last_data_prefix < 0))
13378
688
    {
13379
      /* NOTRACK prefix is only valid on indirect branch instructions.
13380
   NB: DATA prefix is unsupported for Intel64.  */
13381
688
      ins->active_seg_prefix = 0;
13382
688
      ins->all_prefixes[ins->last_seg_prefix] = NOTRACK_PREFIX;
13383
688
    }
13384
55.8k
  return true;
13385
55.8k
}
13386
13387
/* Similar to OP_E.  But the 0xf2/0xf3 ins->prefixes should be displayed as
13388
   "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
13389
 */
13390
13391
static bool
13392
HLE_Fixup1 (instr_info *ins, int bytemode, int sizeflag)
13393
7.01M
{
13394
7.01M
  if (ins->modrm.mod != 3
13395
7.01M
      && (ins->prefixes & PREFIX_LOCK) != 0)
13396
5.68k
    {
13397
5.68k
      if (ins->prefixes & PREFIX_REPZ)
13398
375
  ins->all_prefixes[ins->last_repz_prefix] = XRELEASE_PREFIX;
13399
5.68k
      if (ins->prefixes & PREFIX_REPNZ)
13400
202
  ins->all_prefixes[ins->last_repnz_prefix] = XACQUIRE_PREFIX;
13401
5.68k
    }
13402
13403
7.01M
  return OP_E (ins, bytemode, sizeflag);
13404
7.01M
}
13405
13406
/* Similar to OP_E.  But the 0xf2/0xf3 ins->prefixes should be displayed as
13407
   "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
13408
 */
13409
13410
static bool
13411
HLE_Fixup2 (instr_info *ins, int bytemode, int sizeflag)
13412
41.9k
{
13413
41.9k
  if (ins->modrm.mod != 3)
13414
37.0k
    {
13415
37.0k
      if (ins->prefixes & PREFIX_REPZ)
13416
383
  ins->all_prefixes[ins->last_repz_prefix] = XRELEASE_PREFIX;
13417
37.0k
      if (ins->prefixes & PREFIX_REPNZ)
13418
434
  ins->all_prefixes[ins->last_repnz_prefix] = XACQUIRE_PREFIX;
13419
37.0k
    }
13420
13421
41.9k
  return OP_E (ins, bytemode, sizeflag);
13422
41.9k
}
13423
13424
/* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
13425
   "xrelease" for memory operand.  No check for LOCK prefix.   */
13426
13427
static bool
13428
HLE_Fixup3 (instr_info *ins, int bytemode, int sizeflag)
13429
427k
{
13430
427k
  if (ins->modrm.mod != 3
13431
427k
      && ins->last_repz_prefix > ins->last_repnz_prefix
13432
427k
      && (ins->prefixes & PREFIX_REPZ) != 0)
13433
419
    ins->all_prefixes[ins->last_repz_prefix] = XRELEASE_PREFIX;
13434
13435
427k
  return OP_E (ins, bytemode, sizeflag);
13436
427k
}
13437
13438
static bool
13439
CMPXCHG8B_Fixup (instr_info *ins, int bytemode, int sizeflag)
13440
1.95k
{
13441
1.95k
  USED_REX (REX_W);
13442
1.95k
  if (ins->rex & REX_W)
13443
259
    {
13444
      /* Change cmpxchg8b to cmpxchg16b.  */
13445
259
      char *p = ins->mnemonicendp - 2;
13446
259
      ins->mnemonicendp = stpcpy (p, "16b");
13447
259
      bytemode = o_mode;
13448
259
    }
13449
1.69k
  else if ((ins->prefixes & PREFIX_LOCK) != 0)
13450
764
    {
13451
764
      if (ins->prefixes & PREFIX_REPZ)
13452
335
  ins->all_prefixes[ins->last_repz_prefix] = XRELEASE_PREFIX;
13453
764
      if (ins->prefixes & PREFIX_REPNZ)
13454
216
  ins->all_prefixes[ins->last_repnz_prefix] = XACQUIRE_PREFIX;
13455
764
    }
13456
13457
1.95k
  return OP_M (ins, bytemode, sizeflag);
13458
1.95k
}
13459
13460
static bool
13461
XMM_Fixup (instr_info *ins, int reg, int sizeflag ATTRIBUTE_UNUSED)
13462
408
{
13463
408
  const char (*names)[8] = att_names_xmm;
13464
13465
408
  if (ins->need_vex)
13466
0
    {
13467
0
      switch (ins->vex.length)
13468
0
  {
13469
0
  case 128:
13470
0
    break;
13471
0
  case 256:
13472
0
    names = att_names_ymm;
13473
0
    break;
13474
0
  default:
13475
0
    abort ();
13476
0
  }
13477
0
    }
13478
408
  oappend_register (ins, names[reg]);
13479
408
  return true;
13480
408
}
13481
13482
static bool
13483
FXSAVE_Fixup (instr_info *ins, int bytemode, int sizeflag)
13484
884
{
13485
  /* Add proper suffix to "fxsave" and "fxrstor".  */
13486
884
  USED_REX (REX_W);
13487
884
  if (ins->rex & REX_W)
13488
402
    {
13489
402
      char *p = ins->mnemonicendp;
13490
402
      *p++ = '6';
13491
402
      *p++ = '4';
13492
402
      *p = '\0';
13493
402
      ins->mnemonicendp = p;
13494
402
    }
13495
884
  return OP_M (ins, bytemode, sizeflag);
13496
884
}
13497
13498
/* Display the destination register operand for instructions with
13499
   VEX. */
13500
13501
static bool
13502
OP_VEX (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13503
206k
{
13504
206k
  int reg, modrm_reg, sib_index = -1;
13505
206k
  const char (*names)[8];
13506
13507
206k
  if (!ins->need_vex)
13508
160k
    return true;
13509
13510
45.9k
  if (ins->evex_type == evex_from_legacy)
13511
4.70k
    {
13512
4.70k
      ins->evex_used |= EVEX_b_used;
13513
4.70k
      if (!ins->vex.nd)
13514
596
  return true;
13515
4.70k
    }
13516
13517
45.3k
  reg = ins->vex.register_specifier;
13518
45.3k
  ins->vex.register_specifier = 0;
13519
45.3k
  if (ins->address_mode != mode_64bit)
13520
6.81k
    {
13521
6.81k
      if (ins->vex.evex && !ins->vex.v)
13522
1.52k
  {
13523
1.52k
    oappend (ins, "(bad)");
13524
1.52k
    return true;
13525
1.52k
  }
13526
13527
5.28k
      reg &= 7;
13528
5.28k
    }
13529
38.5k
  else if (ins->vex.evex && !ins->vex.v)
13530
9.46k
    reg += 16;
13531
13532
43.8k
  switch (bytemode)
13533
43.8k
    {
13534
8.06k
    case scalar_mode:
13535
8.06k
      oappend_register (ins, att_names_xmm[reg]);
13536
8.06k
      return true;
13537
13538
2.24k
    case vex_vsib_d_w_dq_mode:
13539
3.83k
    case vex_vsib_q_w_dq_mode:
13540
      /* This must be the 3rd operand.  */
13541
3.83k
      if (ins->obufp != ins->op_out[2])
13542
0
  abort ();
13543
3.83k
      if (ins->vex.length == 128
13544
3.83k
    || (bytemode != vex_vsib_d_w_dq_mode
13545
1.87k
        && !ins->vex.w))
13546
2.47k
  oappend_register (ins, att_names_xmm[reg]);
13547
1.36k
      else
13548
1.36k
  oappend_register (ins, att_names_ymm[reg]);
13549
13550
      /* All 3 XMM/YMM registers must be distinct.  */
13551
3.83k
      modrm_reg = ins->modrm.reg;
13552
3.83k
      if (ins->rex & REX_R)
13553
1.49k
  modrm_reg += 8;
13554
13555
3.83k
      if (ins->has_sib && ins->modrm.rm == 4)
13556
941
  {
13557
941
    sib_index = ins->sib.index;
13558
941
    if (ins->rex & REX_X)
13559
269
      sib_index += 8;
13560
941
  }
13561
13562
3.83k
      if (reg == modrm_reg || reg == sib_index)
13563
727
  strcpy (ins->obufp, "/(bad)");
13564
3.83k
      if (modrm_reg == sib_index || modrm_reg == reg)
13565
795
  strcat (ins->op_out[0], "/(bad)");
13566
3.83k
      if (sib_index == modrm_reg || sib_index == reg)
13567
514
  strcat (ins->op_out[1], "/(bad)");
13568
13569
3.83k
      return true;
13570
13571
1.58k
    case tmm_mode:
13572
      /* All 3 TMM registers must be distinct.  */
13573
1.58k
      if (reg >= 8)
13574
358
  oappend (ins, "(bad)");
13575
1.22k
      else
13576
1.22k
  {
13577
    /* This must be the 3rd operand.  */
13578
1.22k
    if (ins->obufp != ins->op_out[2])
13579
0
      abort ();
13580
1.22k
    oappend_register (ins, att_names_tmm[reg]);
13581
1.22k
    if (reg == ins->modrm.reg || reg == ins->modrm.rm)
13582
686
      strcpy (ins->obufp, "/(bad)");
13583
1.22k
  }
13584
13585
1.58k
      if (ins->modrm.reg == ins->modrm.rm || ins->modrm.reg == reg
13586
1.58k
    || ins->modrm.rm == reg)
13587
1.28k
  {
13588
1.28k
    if (ins->modrm.reg <= 8
13589
1.28k
        && (ins->modrm.reg == ins->modrm.rm || ins->modrm.reg == reg))
13590
669
      strcat (ins->op_out[0], "/(bad)");
13591
1.28k
    if (ins->modrm.rm <= 8
13592
1.28k
        && (ins->modrm.rm == ins->modrm.reg || ins->modrm.rm == reg))
13593
610
      strcat (ins->op_out[1], "/(bad)");
13594
1.28k
  }
13595
13596
1.58k
      return true;
13597
43.8k
    }
13598
13599
30.3k
  switch (ins->vex.length)
13600
30.3k
    {
13601
15.9k
    case 128:
13602
15.9k
      switch (bytemode)
13603
15.9k
  {
13604
9.52k
  case x_mode:
13605
9.52k
    names = att_names_xmm;
13606
9.52k
    ins->evex_used |= EVEX_len_used;
13607
9.52k
    break;
13608
3.24k
  case v_mode:
13609
5.54k
  case dq_mode:
13610
5.54k
    if (ins->rex & REX_W)
13611
1.61k
      names = att_names64;
13612
3.93k
    else if (bytemode == v_mode
13613
3.93k
       && !(sizeflag & DFLAG))
13614
394
      names = att_names16;
13615
3.53k
    else
13616
3.53k
      names = att_names32;
13617
5.54k
    break;
13618
404
  case b_mode:
13619
404
    names = att_names8rex;
13620
404
    break;
13621
458
  case q_mode:
13622
458
    names = att_names64;
13623
458
    break;
13624
0
  case mask_bd_mode:
13625
0
  case mask_mode:
13626
0
    if (reg > 0x7)
13627
0
      {
13628
0
        oappend (ins, "(bad)");
13629
0
        return true;
13630
0
      }
13631
0
    names = att_names_mask;
13632
0
    break;
13633
0
  default:
13634
0
    abort ();
13635
0
    return true;
13636
15.9k
  }
13637
15.9k
      break;
13638
15.9k
    case 256:
13639
8.68k
      switch (bytemode)
13640
8.68k
  {
13641
7.44k
  case x_mode:
13642
7.44k
    names = att_names_ymm;
13643
7.44k
    ins->evex_used |= EVEX_len_used;
13644
7.44k
    break;
13645
0
  case mask_bd_mode:
13646
932
  case mask_mode:
13647
932
    if (reg <= 0x7)
13648
533
      {
13649
533
        names = att_names_mask;
13650
533
        break;
13651
533
      }
13652
    /* Fall through.  */
13653
702
  default:
13654
    /* See PR binutils/20893 for a reproducer.  */
13655
702
    oappend (ins, "(bad)");
13656
702
    return true;
13657
8.68k
  }
13658
7.98k
      break;
13659
7.98k
    case 512:
13660
5.72k
      names = att_names_zmm;
13661
5.72k
      ins->evex_used |= EVEX_len_used;
13662
5.72k
      break;
13663
0
    default:
13664
0
      abort ();
13665
0
      break;
13666
30.3k
    }
13667
29.6k
  oappend_register (ins, names[reg]);
13668
29.6k
  return true;
13669
30.3k
}
13670
13671
static bool
13672
OP_VexR (instr_info *ins, int bytemode, int sizeflag)
13673
1.91k
{
13674
1.91k
  if (ins->modrm.mod == 3)
13675
918
    return OP_VEX (ins, bytemode, sizeflag);
13676
1.00k
  return true;
13677
1.91k
}
13678
13679
static bool
13680
OP_VexW (instr_info *ins, int bytemode, int sizeflag)
13681
754
{
13682
754
  OP_VEX (ins, bytemode, sizeflag);
13683
13684
754
  if (ins->vex.w)
13685
517
    {
13686
      /* Swap 2nd and 3rd operands.  */
13687
517
      char *tmp = ins->op_out[2];
13688
13689
517
      ins->op_out[2] = ins->op_out[1];
13690
517
      ins->op_out[1] = tmp;
13691
517
    }
13692
754
  return true;
13693
754
}
13694
13695
static bool
13696
OP_REG_VexI4 (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13697
2.19k
{
13698
2.19k
  int reg;
13699
2.19k
  const char (*names)[8] = att_names_xmm;
13700
13701
2.19k
  if (!fetch_code (ins->info, ins->codep + 1))
13702
1
    return false;
13703
2.19k
  reg = *ins->codep++;
13704
13705
2.19k
  if (bytemode != x_mode && bytemode != scalar_mode)
13706
0
    abort ();
13707
13708
2.19k
  reg >>= 4;
13709
2.19k
  if (ins->address_mode != mode_64bit)
13710
345
    reg &= 7;
13711
13712
2.19k
  if (bytemode == x_mode && ins->vex.length == 256)
13713
1.44k
    names = att_names_ymm;
13714
13715
2.19k
  oappend_register (ins, names[reg]);
13716
13717
2.19k
  if (ins->vex.w)
13718
1.59k
    {
13719
      /* Swap 3rd and 4th operands.  */
13720
1.59k
      char *tmp = ins->op_out[3];
13721
13722
1.59k
      ins->op_out[3] = ins->op_out[2];
13723
1.59k
      ins->op_out[2] = tmp;
13724
1.59k
    }
13725
2.19k
  return true;
13726
2.19k
}
13727
13728
static bool
13729
OP_VexI4 (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13730
    int sizeflag ATTRIBUTE_UNUSED)
13731
1.74k
{
13732
1.74k
  oappend_immediate (ins, ins->codep[-1] & 0xf);
13733
1.74k
  return true;
13734
1.74k
}
13735
13736
static bool
13737
VPCMP_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13738
       int sizeflag ATTRIBUTE_UNUSED)
13739
1.67k
{
13740
1.67k
  unsigned int cmp_type;
13741
13742
1.67k
  if (!ins->vex.evex)
13743
0
    abort ();
13744
13745
1.67k
  if (!fetch_code (ins->info, ins->codep + 1))
13746
12
    return false;
13747
1.65k
  cmp_type = *ins->codep++;
13748
  /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
13749
     If it's the case, print suffix, otherwise - print the immediate.  */
13750
1.65k
  if (cmp_type < ARRAY_SIZE (simd_cmp_op)
13751
1.65k
      && cmp_type != 3
13752
1.65k
      && cmp_type != 7)
13753
659
    {
13754
659
      char suffix[3];
13755
659
      char *p = ins->mnemonicendp - 2;
13756
13757
      /* vpcmp* can have both one- and two-lettered suffix.  */
13758
659
      if (p[0] == 'p')
13759
203
  {
13760
203
    p++;
13761
203
    suffix[0] = p[0];
13762
203
    suffix[1] = '\0';
13763
203
  }
13764
456
      else
13765
456
  {
13766
456
    suffix[0] = p[0];
13767
456
    suffix[1] = p[1];
13768
456
    suffix[2] = '\0';
13769
456
  }
13770
13771
659
      sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
13772
659
      ins->mnemonicendp += simd_cmp_op[cmp_type].len;
13773
659
    }
13774
999
  else
13775
999
    {
13776
      /* We have a reserved extension byte.  Output it directly.  */
13777
999
      oappend_immediate (ins, cmp_type);
13778
999
    }
13779
1.65k
  return true;
13780
1.67k
}
13781
13782
static const struct op xop_cmp_op[] =
13783
{
13784
  { STRING_COMMA_LEN ("lt") },
13785
  { STRING_COMMA_LEN ("le") },
13786
  { STRING_COMMA_LEN ("gt") },
13787
  { STRING_COMMA_LEN ("ge") },
13788
  { STRING_COMMA_LEN ("eq") },
13789
  { STRING_COMMA_LEN ("neq") },
13790
  { STRING_COMMA_LEN ("false") },
13791
  { STRING_COMMA_LEN ("true") }
13792
};
13793
13794
static bool
13795
VPCOM_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13796
       int sizeflag ATTRIBUTE_UNUSED)
13797
951
{
13798
951
  unsigned int cmp_type;
13799
13800
951
  if (!fetch_code (ins->info, ins->codep + 1))
13801
0
    return false;
13802
951
  cmp_type = *ins->codep++;
13803
951
  if (cmp_type < ARRAY_SIZE (xop_cmp_op))
13804
459
    {
13805
459
      char suffix[3];
13806
459
      char *p = ins->mnemonicendp - 2;
13807
13808
      /* vpcom* can have both one- and two-lettered suffix.  */
13809
459
      if (p[0] == 'm')
13810
194
  {
13811
194
    p++;
13812
194
    suffix[0] = p[0];
13813
194
    suffix[1] = '\0';
13814
194
  }
13815
265
      else
13816
265
  {
13817
265
    suffix[0] = p[0];
13818
265
    suffix[1] = p[1];
13819
265
    suffix[2] = '\0';
13820
265
  }
13821
13822
459
      sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix);
13823
459
      ins->mnemonicendp += xop_cmp_op[cmp_type].len;
13824
459
    }
13825
492
  else
13826
492
    {
13827
      /* We have a reserved extension byte.  Output it directly.  */
13828
492
      oappend_immediate (ins, cmp_type);
13829
492
    }
13830
951
  return true;
13831
951
}
13832
13833
static const struct op pclmul_op[] =
13834
{
13835
  { STRING_COMMA_LEN ("lql") },
13836
  { STRING_COMMA_LEN ("hql") },
13837
  { STRING_COMMA_LEN ("lqh") },
13838
  { STRING_COMMA_LEN ("hqh") }
13839
};
13840
13841
static bool
13842
PCLMUL_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13843
        int sizeflag ATTRIBUTE_UNUSED)
13844
1.51k
{
13845
1.51k
  unsigned int pclmul_type;
13846
13847
1.51k
  if (!fetch_code (ins->info, ins->codep + 1))
13848
5
    return false;
13849
1.50k
  pclmul_type = *ins->codep++;
13850
1.50k
  switch (pclmul_type)
13851
1.50k
    {
13852
197
    case 0x10:
13853
197
      pclmul_type = 2;
13854
197
      break;
13855
192
    case 0x11:
13856
192
      pclmul_type = 3;
13857
192
      break;
13858
1.12k
    default:
13859
1.12k
      break;
13860
1.50k
    }
13861
1.50k
  if (pclmul_type < ARRAY_SIZE (pclmul_op))
13862
564
    {
13863
564
      char suffix[4];
13864
564
      char *p = ins->mnemonicendp - 3;
13865
564
      suffix[0] = p[0];
13866
564
      suffix[1] = p[1];
13867
564
      suffix[2] = p[2];
13868
564
      suffix[3] = '\0';
13869
564
      sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
13870
564
      ins->mnemonicendp += pclmul_op[pclmul_type].len;
13871
564
    }
13872
945
  else
13873
945
    {
13874
      /* We have a reserved extension byte.  Output it directly.  */
13875
945
      oappend_immediate (ins, pclmul_type);
13876
945
    }
13877
1.50k
  return true;
13878
1.50k
}
13879
13880
static bool
13881
MOVSXD_Fixup (instr_info *ins, int bytemode, int sizeflag)
13882
61.0k
{
13883
  /* Add proper suffix to "movsxd".  */
13884
61.0k
  char *p = ins->mnemonicendp;
13885
13886
61.0k
  switch (bytemode)
13887
61.0k
    {
13888
61.0k
    case movsxd_mode:
13889
61.0k
      if (!ins->intel_syntax)
13890
58.4k
  {
13891
58.4k
    USED_REX (REX_W);
13892
58.4k
    if (ins->rex & REX_W)
13893
6.80k
      {
13894
6.80k
        *p++ = 'l';
13895
6.80k
        *p++ = 'q';
13896
6.80k
        break;
13897
6.80k
      }
13898
58.4k
  }
13899
13900
54.2k
      *p++ = 'x';
13901
54.2k
      *p++ = 'd';
13902
54.2k
      break;
13903
0
    default:
13904
0
      oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
13905
0
      break;
13906
61.0k
    }
13907
13908
61.0k
  ins->mnemonicendp = p;
13909
61.0k
  *p = '\0';
13910
61.0k
  return OP_E (ins, bytemode, sizeflag);
13911
61.0k
}
13912
13913
static bool
13914
DistinctDest_Fixup (instr_info *ins, int bytemode, int sizeflag)
13915
4.54k
{
13916
4.54k
  unsigned int reg = ins->vex.register_specifier;
13917
4.54k
  unsigned int modrm_reg = ins->modrm.reg;
13918
4.54k
  unsigned int modrm_rm = ins->modrm.rm;
13919
13920
  /* Calc destination register number.  */
13921
4.54k
  if (ins->rex & REX_R)
13922
863
    modrm_reg += 8;
13923
4.54k
  if (ins->rex2 & REX_R)
13924
2.03k
    modrm_reg += 16;
13925
13926
  /* Calc src1 register number.  */
13927
4.54k
  if (ins->address_mode != mode_64bit)
13928
790
    reg &= 7;
13929
3.75k
  else if (ins->vex.evex && !ins->vex.v)
13930
2.13k
    reg += 16;
13931
13932
  /* Calc src2 register number.  */
13933
4.54k
  if (ins->modrm.mod == 3)
13934
2.03k
    {
13935
2.03k
      if (ins->rex & REX_B)
13936
1.44k
        modrm_rm += 8;
13937
2.03k
      if (ins->rex & REX_X)
13938
595
        modrm_rm += 16;
13939
2.03k
    }
13940
13941
  /* Destination and source registers must be distinct, output bad if
13942
     dest == src1 or dest == src2.  */
13943
4.54k
  if (modrm_reg == reg
13944
4.54k
      || (ins->modrm.mod == 3
13945
3.67k
    && modrm_reg == modrm_rm))
13946
1.17k
    {
13947
1.17k
      oappend (ins, "(bad)");
13948
1.17k
      return true;
13949
1.17k
    }
13950
3.37k
  return OP_XMM (ins, bytemode, sizeflag);
13951
4.54k
}
13952
13953
static bool
13954
OP_Rounding (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13955
19.6k
{
13956
19.6k
  if (ins->modrm.mod != 3 || !ins->vex.b)
13957
16.3k
    return true;
13958
13959
3.29k
  switch (bytemode)
13960
3.29k
    {
13961
622
    case evex_rounding_64_mode:
13962
622
      if (ins->address_mode != mode_64bit || !ins->vex.w)
13963
420
        return true;
13964
      /* Fall through.  */
13965
2.42k
    case evex_rounding_mode:
13966
2.42k
      ins->evex_used |= EVEX_b_used;
13967
2.42k
      oappend (ins, names_rounding[ins->vex.ll]);
13968
2.42k
      break;
13969
443
    case evex_sae_mode:
13970
443
      ins->evex_used |= EVEX_b_used;
13971
443
      oappend (ins, "{");
13972
443
      break;
13973
0
    default:
13974
0
      abort ();
13975
3.29k
    }
13976
2.87k
  oappend (ins, "sae}");
13977
2.87k
  return true;
13978
3.29k
}
13979
13980
static bool
13981
PREFETCHI_Fixup (instr_info *ins, int bytemode, int sizeflag)
13982
1.98k
{
13983
1.98k
  if (ins->modrm.mod != 0 || ins->modrm.rm != 5)
13984
1.79k
    {
13985
1.79k
      if (ins->intel_syntax)
13986
810
  {
13987
810
    ins->mnemonicendp = stpcpy (ins->obuf, "nop   ");
13988
810
  }
13989
985
      else
13990
985
  {
13991
985
    USED_REX (REX_W);
13992
985
    if (ins->rex & REX_W)
13993
341
      ins->mnemonicendp = stpcpy (ins->obuf, "nopq  ");
13994
644
    else
13995
644
      {
13996
644
        if (sizeflag & DFLAG)
13997
454
    ins->mnemonicendp = stpcpy (ins->obuf, "nopl  ");
13998
190
        else
13999
190
    ins->mnemonicendp = stpcpy (ins->obuf, "nopw  ");
14000
644
        ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
14001
644
      }
14002
985
  }
14003
1.79k
      bytemode = v_mode;
14004
1.79k
    }
14005
14006
1.98k
  return OP_M (ins, bytemode, sizeflag);
14007
1.98k
}
14008
14009
static bool
14010
PUSH2_POP2_Fixup (instr_info *ins, int bytemode, int sizeflag)
14011
1.49k
{
14012
1.49k
  if (ins->modrm.mod != 3)
14013
196
    return true;
14014
14015
1.29k
  unsigned int vvvv_reg = ins->vex.register_specifier
14016
1.29k
    | (!ins->vex.v << 4);
14017
1.29k
  unsigned int rm_reg = ins->modrm.rm + (ins->rex & REX_B ? 8 : 0)
14018
1.29k
    + (ins->rex2 & REX_B ? 16 : 0);
14019
14020
  /* Push2/Pop2 cannot use RSP and Pop2 cannot pop two same registers.  */
14021
1.29k
  if (!ins->vex.nd || vvvv_reg == 0x4 || rm_reg == 0x4
14022
1.29k
      || (!ins->modrm.reg
14023
648
    && vvvv_reg == rm_reg))
14024
838
    {
14025
838
      oappend (ins, "(bad)");
14026
838
      return true;
14027
838
    }
14028
14029
458
  return OP_VEX (ins, bytemode, sizeflag);
14030
1.29k
}
14031
14032
static bool
14033
JMPABS_Fixup (instr_info *ins, int bytemode, int sizeflag)
14034
50.3k
{
14035
50.3k
  if (ins->last_rex2_prefix >= 0)
14036
3.30k
    {
14037
3.30k
      uint64_t op;
14038
14039
3.30k
      if ((ins->prefixes & (PREFIX_OPCODE | PREFIX_ADDR | PREFIX_LOCK)) != 0x0
14040
3.30k
    || (ins->rex & REX_W) != 0x0)
14041
692
  {
14042
692
    oappend (ins, "(bad)");
14043
692
    return true;
14044
692
  }
14045
14046
2.60k
      if (bytemode == eAX_reg)
14047
1.30k
  return true;
14048
14049
1.30k
      if (!get64 (ins, &op))
14050
0
  return false;
14051
14052
1.30k
      ins->mnemonicendp = stpcpy (ins->obuf, "jmpabs");
14053
1.30k
      ins->rex2 |= REX2_SPECIAL;
14054
1.30k
      oappend_immediate (ins, op);
14055
14056
1.30k
      return true;
14057
1.30k
    }
14058
14059
47.0k
  if (bytemode == eAX_reg)
14060
23.5k
    return OP_IMREG (ins, bytemode, sizeflag);
14061
23.5k
  return OP_OFF64 (ins, bytemode, sizeflag);
14062
47.0k
}