Coverage Report

Created: 2024-05-21 06:29

/src/binutils-gdb/opcodes/microblaze-dis.c
Line
Count
Source (jump to first uncovered line)
1
/* Disassemble Xilinx microblaze instructions.
2
3
   Copyright (C) 2009-2024 Free Software Foundation, Inc.
4
5
   This file is part of the GNU opcodes library.
6
7
   This library is free software; you can redistribute it and/or modify
8
   it under the terms of the GNU General Public License as published by
9
   the Free Software Foundation; either version 3, or (at your option)
10
   any later version.
11
12
   It is distributed in the hope that it will be useful, but WITHOUT
13
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
15
   License for more details.
16
17
   You should have received a copy of the GNU General Public License
18
   along with this file; see the file COPYING.  If not, write to the
19
   Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
20
   MA 02110-1301, USA.  */
21
22
23
#include "sysdep.h"
24
#define STATIC_TABLE
25
#define DEFINE_TABLE
26
27
#include "disassemble.h"
28
#include <strings.h>
29
#include "microblaze-opc.h"
30
#include "microblaze-dis.h"
31
32
17.8k
#define get_field_rd(buf, instr)   get_field (buf, instr, RD_MASK, RD_LOW)
33
18.0k
#define get_field_r1(buf, instr)   get_field (buf, instr, RA_MASK, RA_LOW)
34
1.82k
#define get_field_r2(buf, instr)   get_field (buf, instr, RB_MASK, RB_LOW)
35
7.49k
#define get_int_field_imm(instr)   ((instr & IMM_MASK) >> IMM_LOW)
36
13.8k
#define get_int_field_r1(instr)    ((instr & RA_MASK) >> RA_LOW)
37
38
57.5k
#define NUM_STRBUFS 4
39
#define STRBUF_SIZE 25
40
41
struct string_buf
42
{
43
  unsigned int which;
44
  char str[NUM_STRBUFS][STRBUF_SIZE];
45
};
46
47
static inline char *
48
strbuf (struct string_buf *buf)
49
57.5k
{
50
57.5k
#ifdef ENABLE_CHECKING
51
57.5k
  if (buf->which >= NUM_STRBUFS)
52
0
    abort ();
53
57.5k
#endif
54
57.5k
  return buf->str[buf->which++];
55
57.5k
}
56
57
static char *
58
get_field (struct string_buf *buf, long instr, long mask, unsigned short low)
59
37.7k
{
60
37.7k
  char *p = strbuf (buf);
61
62
37.7k
  sprintf (p, "%s%d", register_prefix, (int)((instr & mask) >> low));
63
37.7k
  return p;
64
37.7k
}
65
66
static char *
67
get_field_imm (struct string_buf *buf, long instr)
68
16.8k
{
69
16.8k
  char *p = strbuf (buf);
70
71
16.8k
  sprintf (p, "%d", (short)((instr & IMM_MASK) >> IMM_LOW));
72
16.8k
  return p;
73
16.8k
}
74
75
static char *
76
get_field_imm5 (struct string_buf *buf, long instr)
77
86
{
78
86
  char *p = strbuf (buf);
79
80
86
  sprintf (p, "%d", (short)((instr & IMM5_MASK) >> IMM_LOW));
81
86
  return p;
82
86
}
83
84
static char *
85
get_field_imm5_mbar (struct string_buf *buf, long instr)
86
79
{
87
79
  char *p = strbuf (buf);
88
89
79
  sprintf (p, "%d", (short)((instr & IMM5_MBAR_MASK) >> IMM_MBAR));
90
79
  return p;
91
79
}
92
93
static char *
94
get_field_immw (struct string_buf *buf, long instr)
95
81
{
96
81
  char *p = strbuf (buf);
97
98
81
  if (instr & 0x00004000)
99
2
    sprintf (p, "%d", (short)(((instr & IMM5_WIDTH_MASK)
100
2
        >> IMM_WIDTH_LOW))); /* bsefi */
101
79
  else
102
79
    sprintf (p, "%d", (short)(((instr & IMM5_WIDTH_MASK) >>
103
79
        IMM_WIDTH_LOW) - ((instr & IMM5_MASK) >>
104
79
        IMM_LOW) + 1)); /* bsifi */
105
81
  return p;
106
81
}
107
108
static char *
109
get_field_rfsl (struct string_buf *buf, long instr)
110
2.27k
{
111
2.27k
  char *p = strbuf (buf);
112
113
2.27k
  sprintf (p, "%s%d", fsl_register_prefix,
114
2.27k
     (short)((instr & RFSL_MASK) >> IMM_LOW));
115
2.27k
  return p;
116
2.27k
}
117
118
static char *
119
get_field_imm15 (struct string_buf *buf, long instr)
120
6
{
121
6
  char *p = strbuf (buf);
122
123
6
  sprintf (p, "%d", (short)((instr & IMM15_MASK) >> IMM_LOW));
124
6
  return p;
125
6
}
126
127
static char *
128
get_field_special (struct string_buf *buf, long instr,
129
       const struct op_code_struct *op)
130
348
{
131
348
  char *p = strbuf (buf);
132
348
  char *spr;
133
134
348
  switch ((((instr & IMM_MASK) >> IMM_LOW) ^ op->immval_mask))
135
348
    {
136
0
    case REG_MSR_MASK :
137
0
      spr = "msr";
138
0
      break;
139
0
    case REG_PC_MASK :
140
0
      spr = "pc";
141
0
      break;
142
21
    case REG_EAR_MASK :
143
21
      spr = "ear";
144
21
      break;
145
0
    case REG_ESR_MASK :
146
0
      spr = "esr";
147
0
      break;
148
0
    case REG_FSR_MASK :
149
0
      spr = "fsr";
150
0
      break;
151
0
    case REG_BTR_MASK :
152
0
      spr = "btr";
153
0
      break;
154
9
    case REG_EDR_MASK :
155
9
      spr = "edr";
156
9
      break;
157
10
    case REG_PID_MASK :
158
10
      spr = "pid";
159
10
      break;
160
10
    case REG_ZPR_MASK :
161
10
      spr = "zpr";
162
10
      break;
163
0
    case REG_TLBX_MASK :
164
0
      spr = "tlbx";
165
0
      break;
166
70
    case REG_TLBLO_MASK :
167
70
      spr = "tlblo";
168
70
      break;
169
0
    case REG_TLBHI_MASK :
170
0
      spr = "tlbhi";
171
0
      break;
172
0
    case REG_TLBSX_MASK :
173
0
      spr = "tlbsx";
174
0
      break;
175
0
    case REG_SHR_MASK :
176
0
      spr = "shr";
177
0
      break;
178
0
    case REG_SLR_MASK :
179
0
      spr = "slr";
180
0
      break;
181
228
    default :
182
228
      if (((((instr & IMM_MASK) >> IMM_LOW) ^ op->immval_mask) & 0xE000)
183
228
    == REG_PVR_MASK)
184
107
  {
185
107
    sprintf (p, "%spvr%d", register_prefix,
186
107
       (unsigned short)(((instr & IMM_MASK) >> IMM_LOW)
187
107
            ^ op->immval_mask) ^ REG_PVR_MASK);
188
107
    return p;
189
107
  }
190
121
      else
191
121
  spr = "pc";
192
121
      break;
193
348
    }
194
195
241
   sprintf (p, "%s%s", register_prefix, spr);
196
241
   return p;
197
348
}
198
199
static unsigned long
200
read_insn_microblaze (bfd_vma memaddr,
201
          struct disassemble_info *info,
202
          const struct op_code_struct **opr)
203
44.1k
{
204
44.1k
  unsigned char       ibytes[4];
205
44.1k
  int                 status;
206
44.1k
  const struct op_code_struct *op;
207
44.1k
  unsigned long inst;
208
209
44.1k
  status = info->read_memory_func (memaddr, ibytes, 4, info);
210
211
44.1k
  if (status != 0)
212
27
    {
213
27
      info->memory_error_func (status, memaddr, info);
214
27
      return 0;
215
27
    }
216
217
44.0k
  if (info->endian == BFD_ENDIAN_BIG)
218
1.10k
    inst = (((unsigned) ibytes[0] << 24) | (ibytes[1] << 16)
219
1.10k
      | (ibytes[2] << 8) | ibytes[3]);
220
42.9k
  else if (info->endian == BFD_ENDIAN_LITTLE)
221
42.9k
    inst = (((unsigned) ibytes[3] << 24) | (ibytes[2] << 16)
222
42.9k
      | (ibytes[1] << 8) | ibytes[0]);
223
0
  else
224
0
    abort ();
225
226
  /* Just a linear search of the table.  */
227
8.23M
  for (op = microblaze_opcodes; op->name != 0; op ++)
228
8.21M
    if (op->bit_sequence == (inst & op->opcode_mask))
229
22.2k
      break;
230
231
44.0k
  *opr = op;
232
44.0k
  return inst;
233
44.0k
}
234
235
236
int
237
print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info)
238
43.5k
{
239
43.5k
  fprintf_ftype print_func = info->fprintf_func;
240
43.5k
  void *stream = info->stream;
241
43.5k
  unsigned long inst, prev_inst;
242
43.5k
  const struct op_code_struct *op, *pop;
243
43.5k
  int immval = 0;
244
43.5k
  bool immfound = false;
245
43.5k
  static bfd_vma prev_insn_addr = -1; /* Init the prev insn addr.  */
246
43.5k
  static int prev_insn_vma = -1;  /* Init the prev insn vma.  */
247
43.5k
  int curr_insn_vma = info->buffer_vma;
248
43.5k
  struct string_buf buf;
249
250
43.5k
  buf.which = 0;
251
43.5k
  info->bytes_per_chunk = 4;
252
253
43.5k
  inst = read_insn_microblaze (memaddr, info, &op);
254
43.5k
  if (inst == 0)
255
60
    return -1;
256
257
43.5k
  if (prev_insn_vma == curr_insn_vma)
258
560
    {
259
560
      if (memaddr-(info->bytes_per_chunk) == prev_insn_addr)
260
545
  {
261
545
    prev_inst = read_insn_microblaze (prev_insn_addr, info, &pop);
262
545
    if (prev_inst == 0)
263
0
      return -1;
264
545
    if (pop->instr == imm)
265
0
      {
266
0
        immval = (get_int_field_imm (prev_inst) << 16) & 0xffff0000;
267
0
        immfound = true;
268
0
      }
269
545
    else
270
545
      {
271
545
        immval = 0;
272
545
        immfound = false;
273
545
      }
274
545
  }
275
560
    }
276
277
  /* Make curr insn as prev insn.  */
278
43.5k
  prev_insn_addr = memaddr;
279
43.5k
  prev_insn_vma = curr_insn_vma;
280
281
43.5k
  if (op->name == NULL)
282
21.5k
    print_func (stream, ".long 0x%04x", (unsigned int) inst);
283
21.9k
  else
284
21.9k
    {
285
21.9k
      print_func (stream, "%s", op->name);
286
287
21.9k
      switch (op->inst_type)
288
21.9k
  {
289
778
  case INST_TYPE_RD_R1_R2:
290
778
    print_func (stream, "\t%s, %s, %s", get_field_rd (&buf, inst),
291
778
          get_field_r1 (&buf, inst), get_field_r2 (&buf, inst));
292
778
    break;
293
13.8k
  case INST_TYPE_RD_R1_IMM:
294
13.8k
    print_func (stream, "\t%s, %s, %s", get_field_rd (&buf, inst),
295
13.8k
          get_field_r1 (&buf, inst), get_field_imm (&buf, inst));
296
13.8k
    if (info->print_address_func && get_int_field_r1 (inst) == 0
297
13.8k
        && info->symbol_at_address_func)
298
4.55k
      {
299
4.55k
        if (immfound)
300
0
    immval |= (get_int_field_imm (inst) & 0x0000ffff);
301
4.55k
        else
302
4.55k
    {
303
4.55k
      immval = get_int_field_imm (inst);
304
4.55k
      if (immval & 0x8000)
305
1.23k
        immval |= 0xFFFF0000;
306
4.55k
    }
307
4.55k
        if (immval > 0 && info->symbol_at_address_func (immval, info))
308
0
    {
309
0
      print_func (stream, "\t// ");
310
0
      info->print_address_func (immval, info);
311
0
    }
312
4.55k
      }
313
13.8k
    break;
314
5
  case INST_TYPE_RD_R1_IMM5:
315
5
    print_func (stream, "\t%s, %s, %s", get_field_rd (&buf, inst),
316
5
          get_field_r1 (&buf, inst), get_field_imm5 (&buf, inst));
317
5
    break;
318
2.08k
  case INST_TYPE_RD_RFSL:
319
2.08k
    print_func (stream, "\t%s, %s", get_field_rd (&buf, inst),
320
2.08k
          get_field_rfsl (&buf, inst));
321
2.08k
    break;
322
40
  case INST_TYPE_R1_RFSL:
323
40
    print_func (stream, "\t%s, %s", get_field_r1 (&buf, inst),
324
40
          get_field_rfsl (&buf, inst));
325
40
    break;
326
348
  case INST_TYPE_RD_SPECIAL:
327
348
    print_func (stream, "\t%s, %s", get_field_rd (&buf, inst),
328
348
          get_field_special (&buf, inst, op));
329
348
    break;
330
0
  case INST_TYPE_SPECIAL_R1:
331
0
    print_func (stream, "\t%s, %s", get_field_special (&buf, inst, op),
332
0
          get_field_r1 (&buf, inst));
333
0
    break;
334
366
  case INST_TYPE_RD_R1:
335
366
    print_func (stream, "\t%s, %s", get_field_rd (&buf, inst),
336
366
          get_field_r1 (&buf, inst));
337
366
    break;
338
579
  case INST_TYPE_R1_R2:
339
579
    print_func (stream, "\t%s, %s", get_field_r1 (&buf, inst),
340
579
          get_field_r2 (&buf, inst));
341
579
    break;
342
2.17k
  case INST_TYPE_R1_IMM:
343
2.17k
    print_func (stream, "\t%s, %s", get_field_r1 (&buf, inst),
344
2.17k
          get_field_imm (&buf, inst));
345
    /* The non-pc relative instructions are returns, which shouldn't
346
       have a label printed.  */
347
2.17k
    if (info->print_address_func && op->inst_offset_type == INST_PC_OFFSET
348
2.17k
        && info->symbol_at_address_func)
349
2.14k
      {
350
2.14k
        if (immfound)
351
0
    immval |= (get_int_field_imm (inst) & 0x0000ffff);
352
2.14k
        else
353
2.14k
    {
354
2.14k
      immval = get_int_field_imm (inst);
355
2.14k
      if (immval & 0x8000)
356
1.97k
        immval |= 0xFFFF0000;
357
2.14k
    }
358
2.14k
        immval += memaddr;
359
2.14k
        if (immval > 0 && info->symbol_at_address_func (immval, info))
360
0
    {
361
0
      print_func (stream, "\t// ");
362
0
      info->print_address_func (immval, info);
363
0
    }
364
2.14k
        else
365
2.14k
    {
366
2.14k
      print_func (stream, "\t\t// ");
367
2.14k
      print_func (stream, "%x", immval);
368
2.14k
    }
369
2.14k
      }
370
2.17k
    break;
371
54
  case INST_TYPE_RD_IMM:
372
54
    print_func (stream, "\t%s, %s", get_field_rd (&buf, inst),
373
54
          get_field_imm (&buf, inst));
374
54
    if (info->print_address_func && info->symbol_at_address_func)
375
54
      {
376
54
        if (immfound)
377
0
    immval |= (get_int_field_imm (inst) & 0x0000ffff);
378
54
        else
379
54
    {
380
54
      immval = get_int_field_imm (inst);
381
54
      if (immval & 0x8000)
382
37
        immval |= 0xFFFF0000;
383
54
    }
384
54
        if (op->inst_offset_type == INST_PC_OFFSET)
385
14
    immval += (int) memaddr;
386
54
        if (info->symbol_at_address_func (immval, info))
387
0
    {
388
0
      print_func (stream, "\t// ");
389
0
      info->print_address_func (immval, info);
390
0
    }
391
54
      }
392
54
    break;
393
766
  case INST_TYPE_IMM:
394
766
    print_func (stream, "\t%s", get_field_imm (&buf, inst));
395
766
    if (info->print_address_func && info->symbol_at_address_func
396
766
        && op->instr != imm)
397
746
      {
398
746
        if (immfound)
399
0
    immval |= (get_int_field_imm (inst) & 0x0000ffff);
400
746
        else
401
746
    {
402
746
      immval = get_int_field_imm (inst);
403
746
      if (immval & 0x8000)
404
237
        immval |= 0xFFFF0000;
405
746
    }
406
746
        if (op->inst_offset_type == INST_PC_OFFSET)
407
394
    immval += (int) memaddr;
408
746
        if (immval > 0 && info->symbol_at_address_func (immval, info))
409
0
    {
410
0
      print_func (stream, "\t// ");
411
0
      info->print_address_func (immval, info);
412
0
    }
413
746
        else if (op->inst_offset_type == INST_PC_OFFSET)
414
394
    {
415
394
      print_func (stream, "\t\t// ");
416
394
      print_func (stream, "%x", immval);
417
394
    }
418
746
      }
419
766
    break;
420
239
  case INST_TYPE_RD_R2:
421
239
    print_func (stream, "\t%s, %s", get_field_rd (&buf, inst),
422
239
          get_field_r2 (&buf, inst));
423
239
    break;
424
90
  case INST_TYPE_R2:
425
90
    print_func (stream, "\t%s", get_field_r2 (&buf, inst));
426
90
    break;
427
0
  case INST_TYPE_R1:
428
0
    print_func (stream, "\t%s", get_field_r1 (&buf, inst));
429
0
    break;
430
141
  case INST_TYPE_R1_R2_SPECIAL:
431
141
    print_func (stream, "\t%s, %s", get_field_r1 (&buf, inst),
432
141
          get_field_r2 (&buf, inst));
433
141
    break;
434
6
  case INST_TYPE_RD_IMM15:
435
6
    print_func (stream, "\t%s, %s", get_field_rd (&buf, inst),
436
6
          get_field_imm15 (&buf, inst));
437
6
    break;
438
    /* For mbar insn.  */
439
79
  case INST_TYPE_IMM5:
440
79
    print_func (stream, "\t%s", get_field_imm5_mbar (&buf, inst));
441
79
    break;
442
    /* For mbar 16 or sleep insn.  */
443
86
  case INST_TYPE_NONE:
444
86
    break;
445
    /* For bit field insns.  */
446
81
  case INST_TYPE_RD_R1_IMMW_IMMS:
447
81
    print_func (stream, "\t%s, %s, %s, %s",
448
81
          get_field_rd (&buf, inst),
449
81
          get_field_r1 (&buf, inst),
450
81
          get_field_immw (&buf, inst),
451
81
          get_field_imm5 (&buf, inst));
452
81
    break;
453
    /* For tuqula instruction */
454
0
  case INST_TYPE_RD:
455
0
    print_func (stream, "\t%s", get_field_rd (&buf, inst));
456
0
    break;
457
151
  case INST_TYPE_RFSL:
458
151
    print_func (stream, "\t%s", get_field_rfsl (&buf, inst));
459
151
    break;
460
0
  default:
461
    /* If the disassembler lags the instruction set.  */
462
0
    print_func (stream, "\tundecoded operands, inst is 0x%04x",
463
0
          (unsigned int) inst);
464
0
    break;
465
21.9k
  }
466
21.9k
    }
467
468
  /* Say how many bytes we consumed.  */
469
43.5k
  return 4;
470
43.5k
}
471
472
enum microblaze_instr
473
get_insn_microblaze (long inst,
474
           bool *isunsignedimm,
475
           enum microblaze_instr_type *insn_type,
476
           short *delay_slots)
477
0
{
478
0
  const struct op_code_struct *op;
479
0
  *isunsignedimm = false;
480
481
  /* Just a linear search of the table.  */
482
0
  for (op = microblaze_opcodes; op->name != 0; op ++)
483
0
    if (op->bit_sequence == (inst & op->opcode_mask))
484
0
      break;
485
486
0
  if (op->name == 0)
487
0
    return invalid_inst;
488
0
  else
489
0
    {
490
0
      *isunsignedimm = (op->inst_type == INST_TYPE_RD_R1_UNSIGNED_IMM);
491
0
      *insn_type = op->instr_type;
492
0
      *delay_slots = op->delay_slots;
493
0
      return op->instr;
494
0
    }
495
0
}
496
497
enum microblaze_instr
498
microblaze_decode_insn (long insn, int *rd, int *ra, int *rb, int *immed)
499
0
{
500
0
  enum microblaze_instr op;
501
0
  bool t1;
502
0
  enum microblaze_instr_type t2;
503
0
  short t3;
504
505
0
  op = get_insn_microblaze (insn, &t1, &t2, &t3);
506
0
  *rd = (insn & RD_MASK) >> RD_LOW;
507
0
  *ra = (insn & RA_MASK) >> RA_LOW;
508
0
  *rb = (insn & RB_MASK) >> RB_LOW;
509
0
  t3 = (insn & IMM_MASK) >> IMM_LOW;
510
0
  *immed = (int) t3;
511
0
  return (op);
512
0
}
513
514
unsigned long
515
microblaze_get_target_address (long inst, bool immfound, int immval,
516
             long pcval, long r1val, long r2val,
517
             bool *targetvalid,
518
             bool *unconditionalbranch)
519
0
{
520
0
  const struct op_code_struct *op;
521
0
  long targetaddr = 0;
522
523
0
  *unconditionalbranch = false;
524
  /* Just a linear search of the table.  */
525
0
  for (op = microblaze_opcodes; op->name != 0; op ++)
526
0
    if (op->bit_sequence == (inst & op->opcode_mask))
527
0
      break;
528
529
0
  if (op->name == 0)
530
0
    {
531
0
      *targetvalid = false;
532
0
    }
533
0
  else if (op->instr_type == branch_inst)
534
0
    {
535
0
      switch (op->inst_type)
536
0
  {
537
0
        case INST_TYPE_R2:
538
0
          *unconditionalbranch = true;
539
        /* Fall through.  */
540
0
        case INST_TYPE_RD_R2:
541
0
        case INST_TYPE_R1_R2:
542
0
          targetaddr = r2val;
543
0
          *targetvalid = true;
544
0
          if (op->inst_offset_type == INST_PC_OFFSET)
545
0
      targetaddr += pcval;
546
0
          break;
547
0
        case INST_TYPE_IMM:
548
0
          *unconditionalbranch = true;
549
        /* Fall through.  */
550
0
        case INST_TYPE_RD_IMM:
551
0
        case INST_TYPE_R1_IMM:
552
0
          if (immfound)
553
0
      {
554
0
        targetaddr = (immval << 16) & 0xffff0000;
555
0
        targetaddr |= (get_int_field_imm (inst) & 0x0000ffff);
556
0
      }
557
0
    else
558
0
      {
559
0
        targetaddr = get_int_field_imm (inst);
560
0
        if (targetaddr & 0x8000)
561
0
          targetaddr |= 0xFFFF0000;
562
0
            }
563
0
          if (op->inst_offset_type == INST_PC_OFFSET)
564
0
      targetaddr += pcval;
565
0
          *targetvalid = true;
566
0
          break;
567
0
  default:
568
0
    *targetvalid = false;
569
0
    break;
570
0
        }
571
0
    }
572
0
  else if (op->instr_type == return_inst)
573
0
    {
574
0
      if (immfound)
575
0
  {
576
0
    targetaddr = (immval << 16) & 0xffff0000;
577
0
    targetaddr |= (get_int_field_imm (inst) & 0x0000ffff);
578
0
  }
579
0
      else
580
0
  {
581
0
    targetaddr = get_int_field_imm (inst);
582
0
    if (targetaddr & 0x8000)
583
0
      targetaddr |= 0xFFFF0000;
584
0
  }
585
0
      targetaddr += r1val;
586
0
      *targetvalid = true;
587
0
    }
588
0
  else
589
0
    *targetvalid = false;
590
0
  return targetaddr;
591
0
}