Coverage Report

Created: 2024-05-21 06:29

/src/binutils-gdb/opcodes/sparc-dis.c
Line
Count
Source (jump to first uncovered line)
1
/* Print SPARC instructions.
2
   Copyright (C) 1989-2024 Free Software Foundation, Inc.
3
4
   This file is part of the GNU opcodes library.
5
6
   This library is free software; you can redistribute it and/or modify
7
   it under the terms of the GNU General Public License as published by
8
   the Free Software Foundation; either version 3, or (at your option)
9
   any later version.
10
11
   It is distributed in the hope that it will be useful, but WITHOUT
12
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
14
   License for more details.
15
16
   You should have received a copy of the GNU General Public License
17
   along with this program; if not, write to the Free Software
18
   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19
   MA 02110-1301, USA.  */
20
21
#include "sysdep.h"
22
#include <stdio.h>
23
#include "opcode/sparc.h"
24
#include "dis-asm.h"
25
#include "libiberty.h"
26
#include "opintl.h"
27
28
/* Bitmask of v9 architectures.  */
29
#define MASK_V9 ((1 << SPARC_OPCODE_ARCH_V9) \
30
     | (1 << SPARC_OPCODE_ARCH_V9A) \
31
     | (1 << SPARC_OPCODE_ARCH_V9B) \
32
     | (1 << SPARC_OPCODE_ARCH_V9C) \
33
     | (1 << SPARC_OPCODE_ARCH_V9D) \
34
     | (1 << SPARC_OPCODE_ARCH_V9E) \
35
     | (1 << SPARC_OPCODE_ARCH_V9V) \
36
     | (1 << SPARC_OPCODE_ARCH_V9M) \
37
     | (1 << SPARC_OPCODE_ARCH_M8))
38
/* 1 if INSN is for v9 only.  */
39
#define V9_ONLY_P(insn) (! ((insn)->architecture & ~MASK_V9))
40
/* 1 if INSN is for v9.  */
41
#define V9_P(insn) (((insn)->architecture & MASK_V9) != 0)
42
43
/* The sorted opcode table.  */
44
static const sparc_opcode **sorted_opcodes;
45
46
/* For faster lookup, after insns are sorted they are hashed.  */
47
/* ??? I think there is room for even more improvement.  */
48
49
288
#define HASH_SIZE 256
50
/* It is important that we only look at insn code bits as that is how the
51
   opcode table is hashed.  OPCODE_BITS is a table of valid bits for each
52
   of the main types (0,1,2,3).  */
53
static int opcode_bits[4] = { 0x01c00000, 0x0, 0x01f80000, 0x01f80000 };
54
#define HASH_INSN(INSN) \
55
3.25M
  ((((INSN) >> 24) & 0xc0) | (((INSN) & opcode_bits[((INSN) >> 30) & 3]) >> 19))
56
typedef struct sparc_opcode_hash
57
{
58
  struct sparc_opcode_hash *next;
59
  const sparc_opcode *opcode;
60
} sparc_opcode_hash;
61
62
static sparc_opcode_hash *opcode_hash_table[HASH_SIZE];
63
64
/* Sign-extend a value which is N bits long.  */
65
#define SEX(value, bits) \
66
1.49M
  ((int) (((value & ((1u << (bits - 1) << 1) - 1))  \
67
1.49M
     ^ (1u << (bits - 1))) - (1u << (bits - 1))))
68
69
static  char *reg_names[] =
70
{ "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
71
  "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",
72
  "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
73
  "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7",
74
  "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
75
  "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
76
  "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
77
  "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
78
  "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39",
79
  "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47",
80
  "f48", "f49", "f50", "f51", "f52", "f53", "f54", "f55",
81
  "f56", "f57", "f58", "f59", "f60", "f61", "f62", "f63",
82
/* psr, wim, tbr, fpsr, cpsr are v8 only.  */
83
  "y", "psr", "wim", "tbr", "pc", "npc", "fpsr", "cpsr"
84
};
85
86
24.5k
#define freg_names  (&reg_names[4 * 8])
87
88
/* These are ordered according to there register number in
89
   rdpr and wrpr insns.  */
90
static char *v9_priv_reg_names[] =
91
{
92
  "tpc", "tnpc", "tstate", "tt", "tick", "tba", "pstate", "tl",
93
  "pil", "cwp", "cansave", "canrestore", "cleanwin", "otherwin",
94
  "wstate", "fq", "gl"
95
  /* "ver" and "pmcdper" - special cased */
96
};
97
98
/* These are ordered according to there register number in
99
   rdhpr and wrhpr insns.  */
100
static char *v9_hpriv_reg_names[] =
101
{
102
  "hpstate", "htstate", "resv2", "hintp", "resv4", "htba", "hver",
103
  "resv7", "resv8", "resv9", "resv10", "resv11", "resv12", "resv13",
104
  "resv14", "resv15", "resv16", "resv17", "resv18", "resv19", "resv20",
105
  "resv21", "resv22", "hmcdper", "hmcddfr", "resv25", "resv26", "hva_mask_nz",
106
  "hstick_offset", "hstick_enable", "resv30", "hstick_cmpr"
107
};
108
109
/* These are ordered according to there register number in
110
   rd and wr insns (-16).  */
111
static char *v9a_asr_reg_names[] =
112
{
113
  "pcr", "pic", "dcr", "gsr", "softint_set", "softint_clear",
114
  "softint", "tick_cmpr", "stick", "stick_cmpr", "cfr",
115
  "pause", "mwait"
116
};
117
118
/* Macros used to extract instruction fields.  Not all fields have
119
   macros defined here, only those which are actually used.  */
120
121
8.19M
#define X_RD(i)      (((i) >> 25) & 0x1f)
122
2.06M
#define X_RS1(i)     (((i) >> 14) & 0x1f)
123
20
#define X_LDST_I(i)  (((i) >> 13) & 1)
124
13.4k
#define X_ASI(i)     (((i) >> 5) & 0xff)
125
2.03M
#define X_RS2(i)     (((i) >> 0) & 0x1f)
126
4
#define X_RS3(i)     (((i) >> 9) & 0x1f)
127
25.1k
#define X_IMM(i,n)   (((i) >> 0) & ((1 << (n)) - 1))
128
293k
#define X_SIMM(i,n)  SEX (X_IMM ((i), (n)), (n))
129
283k
#define X_DISP22(i)  (((i) >> 0) & 0x3fffff)
130
283k
#define X_IMM22(i)   X_DISP22 (i)
131
#define X_DISP30(i)  (((i) >> 0) & 0x3fffffff)
132
196
#define X_IMM2(i)    (((i & 0x10) >> 3) | (i & 0x1))
133
134
/* These are for v9.  */
135
#define X_DISP16(i)  (((((i) >> 20) & 3) << 14) | (((i) >> 0) & 0x3fff))
136
#define X_DISP10(i)  (((((i) >> 19) & 3) << 8) | (((i) >> 5) & 0xff))
137
#define X_DISP19(i)  (((i) >> 0) & 0x7ffff)
138
0
#define X_MEMBAR(i)  ((i) & 0x7f)
139
140
/* Here is the union which was used to extract instruction fields
141
   before the shift and mask macros were written.
142
143
   union sparc_insn
144
     {
145
       unsigned long int code;
146
       struct
147
   {
148
     unsigned int anop:2;
149
     #define  op  ldst.anop
150
     unsigned int anrd:5;
151
     #define  rd  ldst.anrd
152
     unsigned int op3:6;
153
     unsigned int anrs1:5;
154
     #define  rs1 ldst.anrs1
155
     unsigned int i:1;
156
     unsigned int anasi:8;
157
     #define  asi ldst.anasi
158
     unsigned int anrs2:5;
159
     #define  rs2 ldst.anrs2
160
     #define  shcnt rs2
161
   } ldst;
162
       struct
163
   {
164
     unsigned int anop:2, anrd:5, op3:6, anrs1:5, i:1;
165
     unsigned int IMM13:13;
166
     #define  imm13 IMM13.IMM13
167
   } IMM13;
168
       struct
169
   {
170
     unsigned int anop:2;
171
     unsigned int a:1;
172
     unsigned int cond:4;
173
     unsigned int op2:3;
174
     unsigned int DISP22:22;
175
     #define  disp22  branch.DISP22
176
     #define  imm22 disp22
177
   } branch;
178
       struct
179
   {
180
     unsigned int anop:2;
181
     unsigned int a:1;
182
     unsigned int z:1;
183
     unsigned int rcond:3;
184
     unsigned int op2:3;
185
     unsigned int DISP16HI:2;
186
     unsigned int p:1;
187
     unsigned int _rs1:5;
188
     unsigned int DISP16LO:14;
189
   } branch16;
190
       struct
191
   {
192
     unsigned int anop:2;
193
     unsigned int adisp30:30;
194
     #define  disp30  call.adisp30
195
   } call;
196
     };  */
197
198
/* Nonzero if INSN is the opcode for a delayed branch.  */
199
200
static int
201
is_delayed_branch (unsigned long insn)
202
191k
{
203
191k
  sparc_opcode_hash *op;
204
205
3.01M
  for (op = opcode_hash_table[HASH_INSN (insn)]; op; op = op->next)
206
3.00M
    {
207
3.00M
      const sparc_opcode *opcode = op->opcode;
208
209
3.00M
      if ((opcode->match & insn) == opcode->match
210
3.00M
    && (opcode->lose & insn) == 0)
211
185k
  return opcode->flags & F_DELAYED;
212
3.00M
    }
213
6.06k
  return 0;
214
191k
}
215
216
/* extern void qsort (); */
217
218
/* Records current mask of SPARC_OPCODE_ARCH_FOO values, used to pass value
219
   to compare_opcodes.  */
220
static unsigned int current_arch_mask;
221
222
/* Given BFD mach number, return a mask of SPARC_OPCODE_ARCH_FOO values.  */
223
224
static int
225
compute_arch_mask (unsigned long mach)
226
144
{
227
144
  switch (mach)
228
144
    {
229
24
    case 0 :
230
30
    case bfd_mach_sparc :
231
30
      return (SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8)
232
30
              | SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_LEON));
233
4
    case bfd_mach_sparc_sparclet :
234
4
      return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLET);
235
10
    case bfd_mach_sparc_sparclite :
236
10
    case bfd_mach_sparc_sparclite_le :
237
      /* sparclites insns are recognized by default (because that's how
238
   they've always been treated, for better or worse).  Kludge this by
239
   indicating generic v8 is also selected.  */
240
10
      return (SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLITE)
241
10
        | SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8));
242
7
    case bfd_mach_sparc_v8plus :
243
16
    case bfd_mach_sparc_v9 :
244
16
      return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9);
245
2
    case bfd_mach_sparc_v8plusa :
246
4
    case bfd_mach_sparc_v9a :
247
4
      return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A);
248
4
    case bfd_mach_sparc_v8plusb :
249
5
    case bfd_mach_sparc_v9b :
250
5
      return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9B);
251
0
    case bfd_mach_sparc_v8plusc :
252
9
    case bfd_mach_sparc_v9c :
253
9
      return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9C);
254
1
    case bfd_mach_sparc_v8plusd :
255
3
    case bfd_mach_sparc_v9d :
256
3
      return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9D);
257
1
    case bfd_mach_sparc_v8pluse :
258
12
    case bfd_mach_sparc_v9e :
259
12
      return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9E);
260
8
    case bfd_mach_sparc_v8plusv :
261
10
    case bfd_mach_sparc_v9v :
262
10
      return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9V);
263
0
    case bfd_mach_sparc_v8plusm :
264
3
    case bfd_mach_sparc_v9m :
265
3
      return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9M);
266
31
    case bfd_mach_sparc_v8plusm8 :
267
38
    case bfd_mach_sparc_v9m8 :
268
38
      return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_M8);
269
144
    }
270
0
  abort ();
271
144
}
272
273
/* Compare opcodes A and B.  */
274
275
static int
276
compare_opcodes (const void * a, const void * b)
277
5.09M
{
278
5.09M
  sparc_opcode *op0 = * (sparc_opcode **) a;
279
5.09M
  sparc_opcode *op1 = * (sparc_opcode **) b;
280
5.09M
  unsigned long int match0 = op0->match, match1 = op1->match;
281
5.09M
  unsigned long int lose0 = op0->lose, lose1 = op1->lose;
282
5.09M
  register unsigned int i;
283
284
  /* If one (and only one) insn isn't supported by the current architecture,
285
     prefer the one that is.  If neither are supported, but they're both for
286
     the same architecture, continue processing.  Otherwise (both unsupported
287
     and for different architectures), prefer lower numbered arch's (fudged
288
     by comparing the bitmasks).  */
289
5.09M
  if (op0->architecture & current_arch_mask)
290
3.53M
    {
291
3.53M
      if (! (op1->architecture & current_arch_mask))
292
89.8k
  return -1;
293
3.53M
    }
294
1.56M
  else
295
1.56M
    {
296
1.56M
      if (op1->architecture & current_arch_mask)
297
56.9k
  return 1;
298
1.50M
      else if (op0->architecture != op1->architecture)
299
203k
  return op0->architecture - op1->architecture;
300
1.56M
    }
301
302
  /* If a bit is set in both match and lose, there is something
303
     wrong with the opcode table.  */
304
4.74M
  if (match0 & lose0)
305
0
    {
306
0
      opcodes_error_handler
307
  /* xgettext:c-format */
308
0
  (_("internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"),
309
0
   op0->name, match0, lose0);
310
0
      op0->lose &= ~op0->match;
311
0
      lose0 = op0->lose;
312
0
    }
313
314
4.74M
  if (match1 & lose1)
315
0
    {
316
0
      opcodes_error_handler
317
  /* xgettext:c-format */
318
0
  (_("internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"),
319
0
   op1->name, match1, lose1);
320
0
      op1->lose &= ~op1->match;
321
0
      lose1 = op1->lose;
322
0
    }
323
324
  /* Because the bits that are variable in one opcode are constant in
325
     another, it is important to order the opcodes in the right order.  */
326
94.0M
  for (i = 0; i < 32; ++i)
327
93.7M
    {
328
93.7M
      unsigned long int x = 1ul << i;
329
93.7M
      int x0 = (match0 & x) != 0;
330
93.7M
      int x1 = (match1 & x) != 0;
331
332
93.7M
      if (x0 != x1)
333
4.41M
  return x1 - x0;
334
93.7M
    }
335
336
7.17M
  for (i = 0; i < 32; ++i)
337
6.99M
    {
338
6.99M
      unsigned long int x = 1ul << i;
339
6.99M
      int x0 = (lose0 & x) != 0;
340
6.99M
      int x1 = (lose1 & x) != 0;
341
342
6.99M
      if (x0 != x1)
343
153k
  return x1 - x0;
344
6.99M
    }
345
346
  /* They are functionally equal.  So as long as the opcode table is
347
     valid, we can put whichever one first we want, on aesthetic grounds.  */
348
349
  /* Our first aesthetic ground is that aliases defer to real insns.  */
350
181k
  {
351
181k
    int alias_diff = (op0->flags & F_ALIAS) - (op1->flags & F_ALIAS);
352
353
181k
    if (alias_diff != 0)
354
      /* Put the one that isn't an alias first.  */
355
92.8k
      return alias_diff;
356
181k
  }
357
358
  /* Except for aliases, two "identical" instructions had
359
     better have the same opcode.  This is a sanity check on the table.  */
360
89.1k
  i = strcmp (op0->name, op1->name);
361
89.1k
  if (i)
362
22.6k
    {
363
22.6k
      if (op0->flags & F_ALIAS)
364
22.6k
  {
365
22.6k
    if (op0->flags & F_PREFERRED)
366
2.59k
      return -1;
367
20.0k
    if (op1->flags & F_PREFERRED)
368
0
      return 1;
369
370
    /* If they're both aliases, and neither is marked as preferred,
371
       be arbitrary.  */
372
20.0k
    return i;
373
20.0k
  }
374
0
      else
375
0
  opcodes_error_handler
376
    /* xgettext:c-format */
377
0
    (_("internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n"),
378
0
     op0->name, op1->name);
379
22.6k
    }
380
381
  /* Fewer arguments are preferred.  */
382
66.4k
  {
383
66.4k
    int length_diff = strlen (op0->args) - strlen (op1->args);
384
385
66.4k
    if (length_diff != 0)
386
      /* Put the one with fewer arguments first.  */
387
43.0k
      return length_diff;
388
66.4k
  }
389
390
  /* Put 1+i before i+1.  */
391
23.4k
  {
392
23.4k
    char *p0 = (char *) strchr (op0->args, '+');
393
23.4k
    char *p1 = (char *) strchr (op1->args, '+');
394
395
23.4k
    if (p0 && p1)
396
18.5k
      {
397
  /* There is a plus in both operands.  Note that a plus
398
     sign cannot be the first character in args,
399
     so the following [-1]'s are valid.  */
400
18.5k
  if (p0[-1] == 'i' && p1[1] == 'i')
401
    /* op0 is i+1 and op1 is 1+i, so op1 goes first.  */
402
0
    return 1;
403
18.5k
  if (p0[1] == 'i' && p1[-1] == 'i')
404
    /* op0 is 1+i and op1 is i+1, so op0 goes first.  */
405
16.7k
    return -1;
406
18.5k
      }
407
23.4k
  }
408
409
  /* Put 1,i before i,1.  */
410
6.76k
  {
411
6.76k
    int i0 = strncmp (op0->args, "i,1", 3) == 0;
412
6.76k
    int i1 = strncmp (op1->args, "i,1", 3) == 0;
413
414
6.76k
    if (i0 ^ i1)
415
4.46k
      return i0 - i1;
416
6.76k
  }
417
418
  /* They are, as far as we can tell, identical.
419
     Since qsort may have rearranged the table partially, there is
420
     no way to tell which one was first in the opcode table as
421
     written, so just say there are equal.  */
422
  /* ??? This is no longer true now that we sort a vector of pointers,
423
     not the table itself.  */
424
2.30k
  return 0;
425
6.76k
}
426
427
/* Build a hash table from the opcode table.
428
   OPCODE_TABLE is a sorted list of pointers into the opcode table.  */
429
430
static void
431
build_hash_table (const sparc_opcode **opcode_table,
432
      sparc_opcode_hash **hash_table,
433
      int num_opcodes)
434
144
{
435
144
  int i;
436
144
  int hash_count[HASH_SIZE];
437
144
  static sparc_opcode_hash *hash_buf = NULL;
438
439
  /* Start at the end of the table and work backwards so that each
440
     chain is sorted.  */
441
442
144
  memset (hash_table, 0, HASH_SIZE * sizeof (hash_table[0]));
443
144
  memset (hash_count, 0, HASH_SIZE * sizeof (hash_count[0]));
444
144
  free (hash_buf);
445
144
  hash_buf = xmalloc (sizeof (* hash_buf) * num_opcodes);
446
509k
  for (i = num_opcodes - 1; i >= 0; --i)
447
509k
    {
448
509k
      int hash = HASH_INSN (opcode_table[i]->match);
449
509k
      sparc_opcode_hash *h = &hash_buf[i];
450
451
509k
      h->next = hash_table[hash];
452
509k
      h->opcode = opcode_table[i];
453
509k
      hash_table[hash] = h;
454
509k
      ++hash_count[hash];
455
509k
    }
456
457
#if 0 /* for debugging */
458
  {
459
    int min_count = num_opcodes, max_count = 0;
460
    int total;
461
462
    for (i = 0; i < HASH_SIZE; ++i)
463
      {
464
        if (hash_count[i] < min_count)
465
    min_count = hash_count[i];
466
  if (hash_count[i] > max_count)
467
    max_count = hash_count[i];
468
  total += hash_count[i];
469
      }
470
471
    printf ("Opcode hash table stats: min %d, max %d, ave %f\n",
472
      min_count, max_count, (double) total / HASH_SIZE);
473
  }
474
#endif
475
144
}
476
477
/* Print one instruction from MEMADDR on INFO->STREAM.
478
479
   We suffix the instruction with a comment that gives the absolute
480
   address involved, as well as its symbolic form, if the instruction
481
   is preceded by a findable `sethi' and it either adds an immediate
482
   displacement to that register, or it is an `add' or `or' instruction
483
   on that register.  */
484
485
int
486
print_insn_sparc (bfd_vma memaddr, disassemble_info *info)
487
2.55M
{
488
2.55M
  FILE *stream = info->stream;
489
2.55M
  bfd_byte buffer[4];
490
2.55M
  unsigned long insn;
491
2.55M
  sparc_opcode_hash *op;
492
  /* Nonzero of opcode table has been initialized.  */
493
2.55M
  static int opcodes_initialized = 0;
494
  /* bfd mach number of last call.  */
495
2.55M
  static unsigned long current_mach = 0;
496
2.55M
  bfd_vma (*getword) (const void *);
497
498
2.55M
  if (!opcodes_initialized
499
2.55M
      || info->mach != current_mach)
500
144
    {
501
144
      int i;
502
503
144
      current_arch_mask = compute_arch_mask (info->mach);
504
505
144
      if (!opcodes_initialized)
506
2
  sorted_opcodes =
507
2
    xmalloc (sparc_num_opcodes * sizeof (sparc_opcode *));
508
      /* Reset the sorted table so we can resort it.  */
509
509k
      for (i = 0; i < sparc_num_opcodes; ++i)
510
509k
  sorted_opcodes[i] = &sparc_opcodes[i];
511
144
      qsort ((char *) sorted_opcodes, sparc_num_opcodes,
512
144
       sizeof (sorted_opcodes[0]), compare_opcodes);
513
514
144
      build_hash_table (sorted_opcodes, opcode_hash_table, sparc_num_opcodes);
515
144
      current_mach = info->mach;
516
144
      opcodes_initialized = 1;
517
144
    }
518
519
2.55M
  {
520
2.55M
    int status =
521
2.55M
      (*info->read_memory_func) (memaddr, buffer, sizeof (buffer), info);
522
523
2.55M
    if (status != 0)
524
230
      {
525
230
  (*info->memory_error_func) (status, memaddr, info);
526
230
  return -1;
527
230
      }
528
2.55M
  }
529
530
  /* On SPARClite variants such as DANlite (sparc86x), instructions
531
     are always big-endian even when the machine is in little-endian mode.  */
532
2.55M
  if (info->endian == BFD_ENDIAN_BIG || info->mach == bfd_mach_sparc_sparclite)
533
2.44M
    getword = bfd_getb32;
534
102k
  else
535
102k
    getword = bfd_getl32;
536
537
2.55M
  insn = getword (buffer);
538
539
2.55M
  info->insn_info_valid = 1;      /* We do return this info.  */
540
2.55M
  info->insn_type = dis_nonbranch;    /* Assume non branch insn.  */
541
2.55M
  info->branch_delay_insns = 0;     /* Assume no delay.  */
542
2.55M
  info->target = 0;       /* Assume no target known.  */
543
544
70.1M
  for (op = opcode_hash_table[HASH_INSN (insn)]; op; op = op->next)
545
69.6M
    {
546
69.6M
      const sparc_opcode *opcode = op->opcode;
547
548
      /* If the insn isn't supported by the current architecture, skip it.  */
549
69.6M
      if (! (opcode->architecture & current_arch_mask))
550
53.0M
  continue;
551
552
16.5M
      if ((opcode->match & insn) == opcode->match
553
16.5M
    && (opcode->lose & insn) == 0)
554
2.04M
  {
555
    /* Nonzero means that we have found an instruction which has
556
       the effect of adding or or'ing the imm13 field to rs1.  */
557
2.04M
    int imm_added_to_rs1 = 0;
558
2.04M
    int imm_ored_to_rs1 = 0;
559
560
    /* Nonzero means that we have found a plus sign in the args
561
       field of the opcode table.  */
562
2.04M
    int found_plus = 0;
563
564
    /* Nonzero means we have an annulled branch.  */
565
2.04M
    int is_annulled = 0;
566
567
    /* Do we have an `add' or `or' instruction combining an
568
             immediate with rs1?  */
569
2.04M
    if (opcode->match == 0x80102000) /* or */
570
62.3k
      imm_ored_to_rs1 = 1;
571
2.04M
    if (opcode->match == 0x80002000) /* add */
572
25.9k
      imm_added_to_rs1 = 1;
573
574
2.04M
    if (X_RS1 (insn) != X_RD (insn)
575
2.04M
        && strchr (opcode->args, 'r') != 0)
576
        /* Can't do simple format if source and dest are different.  */
577
4.27k
        continue;
578
2.03M
    if (X_RS2 (insn) != X_RD (insn)
579
2.03M
        && strchr (opcode->args, 'O') != 0)
580
        /* Can't do simple format if source and dest are different.  */
581
807
        continue;
582
583
2.03M
    (*info->fprintf_func) (stream, "%s", opcode->name);
584
585
2.03M
    {
586
2.03M
      const char *s;
587
588
2.03M
      if (opcode->args[0] != ',')
589
1.98M
        (*info->fprintf_func) (stream, " ");
590
591
5.70M
      for (s = opcode->args; *s != '\0'; ++s)
592
3.66M
        {
593
4.67M
    while (*s == ',')
594
1.00M
      {
595
1.00M
        (*info->fprintf_func) (stream, ",");
596
1.00M
        ++s;
597
1.00M
        switch (*s)
598
1.00M
          {
599
36.7k
          case 'a':
600
36.7k
      (*info->fprintf_func) (stream, "a");
601
36.7k
      is_annulled = 1;
602
36.7k
      ++s;
603
36.7k
      continue;
604
14.6k
          case 'N':
605
14.6k
      (*info->fprintf_func) (stream, "pn");
606
14.6k
      ++s;
607
14.6k
      continue;
608
609
0
          case 'T':
610
0
      (*info->fprintf_func) (stream, "pt");
611
0
      ++s;
612
0
      continue;
613
614
954k
          default:
615
954k
      break;
616
1.00M
          }
617
1.00M
      }
618
619
3.66M
    (*info->fprintf_func) (stream, " ");
620
621
3.66M
    switch (*s)
622
3.66M
      {
623
142k
      case '+':
624
142k
        found_plus = 1;
625
        /* Fall through.  */
626
627
556k
      default:
628
556k
        (*info->fprintf_func) (stream, "%c", *s);
629
556k
        break;
630
631
0
      case '#':
632
0
        (*info->fprintf_func) (stream, "0");
633
0
        break;
634
635
1.27M
#define reg(n)  (*info->fprintf_func) (stream, "%%%s", reg_names[n])
636
423k
      case '1':
637
434k
      case 'r':
638
434k
        reg (X_RS1 (insn));
639
434k
        break;
640
641
167k
      case '2':
642
167k
      case 'O':
643
167k
        reg (X_RS2 (insn));
644
167k
        break;
645
646
677k
      case 'd':
647
677k
        reg (X_RD (insn));
648
677k
        break;
649
0
#undef  reg
650
651
17.0k
#define freg(n)   (*info->fprintf_func) (stream, "%%%s", freg_names[n])
652
7.47k
#define fregx(n)  (*info->fprintf_func) (stream, "%%%s", freg_names[((n) & ~1) | (((n) & 1) << 5)])
653
1.44k
      case 'e':
654
1.44k
        freg (X_RS1 (insn));
655
1.44k
        break;
656
1.25k
      case 'v': /* Double/even.  */
657
1.26k
      case 'V': /* Quad/multiple of 4.  */
658
1.28k
                  case ';': /* Double/even multiple of 8 doubles.  */
659
1.28k
        fregx (X_RS1 (insn));
660
1.28k
        break;
661
662
2.44k
      case 'f':
663
2.44k
        freg (X_RS2 (insn));
664
2.44k
        break;
665
1.36k
      case 'B': /* Double/even.  */
666
1.38k
      case 'R': /* Quad/multiple of 4.  */
667
1.39k
                  case ':': /* Double/even multiple of 8 doubles.  */
668
1.39k
        fregx (X_RS2 (insn));
669
1.39k
        break;
670
671
794
      case '4':
672
794
        freg (X_RS3 (insn));
673
794
        break;
674
156
      case '5': /* Double/even.  */
675
156
        fregx (X_RS3 (insn));
676
156
        break;
677
678
12.3k
      case 'g':
679
12.3k
        freg (X_RD (insn));
680
12.3k
        break;
681
3.95k
      case 'H': /* Double/even.  */
682
4.42k
      case 'J': /* Quad/multiple of 4.  */
683
4.42k
      case '}':     /* Double/even.  */
684
4.42k
        fregx (X_RD (insn));
685
4.42k
        break;
686
                    
687
17
                  case '^': /* Double/even multiple of 8 doubles.  */
688
17
                    fregx (X_RD (insn) & ~0x6);
689
17
                    break;
690
                    
691
196
                  case '\'':  /* Double/even in FPCMPSHL.  */
692
196
                    fregx (X_RS2 (insn | 0x11));
693
196
                    break;
694
                    
695
0
#undef  freg
696
0
#undef  fregx
697
698
1.27k
#define creg(n) (*info->fprintf_func) (stream, "%%c%u", (unsigned int) (n))
699
0
      case 'b':
700
0
        creg (X_RS1 (insn));
701
0
        break;
702
703
0
      case 'c':
704
0
        creg (X_RS2 (insn));
705
0
        break;
706
707
1.27k
      case 'D':
708
1.27k
        creg (X_RD (insn));
709
1.27k
        break;
710
0
#undef  creg
711
712
267k
      case 'h':
713
267k
        (*info->fprintf_func) (stream, "%%hi(%#x)",
714
267k
             (unsigned) X_IMM22 (insn) << 10);
715
267k
        break;
716
717
276k
      case 'i': /* 13 bit immediate.  */
718
277k
      case 'I': /* 11 bit immediate.  */
719
277k
      case 'j': /* 10 bit immediate.  */
720
277k
        {
721
277k
          int imm;
722
723
277k
          if (*s == 'i')
724
276k
            imm = X_SIMM (insn, 13);
725
594
          else if (*s == 'I')
726
454
      imm = X_SIMM (insn, 11);
727
140
          else
728
140
      imm = X_SIMM (insn, 10);
729
730
          /* Check to see whether we have a 1+i, and take
731
       note of that fact.
732
733
       Note: because of the way we sort the table,
734
       we will be matching 1+i rather than i+1,
735
       so it is OK to assume that i is after +,
736
       not before it.  */
737
277k
          if (found_plus)
738
109k
      imm_added_to_rs1 = 1;
739
740
277k
          if (imm <= 9)
741
165k
      (*info->fprintf_func) (stream, "%d", imm);
742
111k
          else
743
111k
      (*info->fprintf_func) (stream, "%#x", imm);
744
277k
        }
745
277k
        break;
746
747
4
      case ')': /* 5 bit unsigned immediate from RS3.  */
748
4
        (info->fprintf_func) (stream, "%#x", (unsigned int) X_RS3 (insn));
749
4
        break;
750
751
12.5k
      case 'X': /* 5 bit unsigned immediate.  */
752
12.5k
      case 'Y': /* 6 bit unsigned immediate.  */
753
12.5k
        {
754
12.5k
          int imm = X_IMM (insn, *s == 'X' ? 5 : 6);
755
756
12.5k
          if (imm <= 9)
757
7.16k
      (info->fprintf_func) (stream, "%d", imm);
758
5.42k
          else
759
5.42k
      (info->fprintf_func) (stream, "%#x", (unsigned) imm);
760
12.5k
        }
761
12.5k
        break;
762
763
0
      case '3':
764
0
        (info->fprintf_func) (stream, "%ld", X_IMM (insn, 3));
765
0
        break;
766
767
0
      case 'K':
768
0
        {
769
0
          int mask = X_MEMBAR (insn);
770
0
          int bit = 0x40, printed_one = 0;
771
0
          const char *name;
772
773
0
          if (mask == 0)
774
0
      (info->fprintf_func) (stream, "0");
775
0
          else
776
0
      while (bit)
777
0
        {
778
0
          if (mask & bit)
779
0
            {
780
0
        if (printed_one)
781
0
          (info->fprintf_func) (stream, "|");
782
0
        name = sparc_decode_membar (bit);
783
0
        (info->fprintf_func) (stream, "%s", name);
784
0
        printed_one = 1;
785
0
            }
786
0
          bit >>= 1;
787
0
        }
788
0
          break;
789
12.5k
        }
790
791
453
      case '=':
792
453
        info->target = memaddr + SEX (X_DISP10 (insn), 10) * 4;
793
453
        (*info->print_address_func) (info->target, info);
794
453
        break;
795
796
606
      case 'k':
797
606
        info->target = memaddr + SEX (X_DISP16 (insn), 16) * 4;
798
606
        (*info->print_address_func) (info->target, info);
799
606
        break;
800
801
29.7k
      case 'G':
802
29.7k
        info->target = memaddr + SEX (X_DISP19 (insn), 19) * 4;
803
29.7k
        (*info->print_address_func) (info->target, info);
804
29.7k
        break;
805
806
747
      case '6':
807
1.14k
      case '7':
808
2.12k
      case '8':
809
2.98k
      case '9':
810
2.98k
        (*info->fprintf_func) (stream, "%%fcc%c", *s - '6' + '0');
811
2.98k
        break;
812
813
17.9k
      case 'z':
814
17.9k
        (*info->fprintf_func) (stream, "%%icc");
815
17.9k
        break;
816
817
9.49k
      case 'Z':
818
9.49k
        (*info->fprintf_func) (stream, "%%xcc");
819
9.49k
        break;
820
821
19
      case 'E':
822
19
        (*info->fprintf_func) (stream, "%%ccr");
823
19
        break;
824
825
22
      case 's':
826
22
        (*info->fprintf_func) (stream, "%%fprs");
827
22
        break;
828
829
109
      case '{':
830
109
        (*info->fprintf_func) (stream, "%%mcdper");
831
109
        break;
832
833
0
                  case '&':
834
0
                    (*info->fprintf_func) (stream, "%%entropy");
835
0
                    break;
836
837
4.51k
      case 'o':
838
4.51k
        (*info->fprintf_func) (stream, "%%asi");
839
4.51k
        break;
840
841
25
      case 'W':
842
25
        (*info->fprintf_func) (stream, "%%tick");
843
25
        break;
844
845
30
      case 'P':
846
30
        (*info->fprintf_func) (stream, "%%pc");
847
30
        break;
848
849
22
      case '?':
850
22
        if (X_RS1 (insn) == 31)
851
0
          (*info->fprintf_func) (stream, "%%ver");
852
22
        else if (X_RS1 (insn) == 23)
853
0
          (*info->fprintf_func) (stream, "%%pmcdper");
854
22
        else if ((unsigned) X_RS1 (insn) < 17)
855
22
          (*info->fprintf_func) (stream, "%%%s",
856
22
               v9_priv_reg_names[X_RS1 (insn)]);
857
0
        else
858
0
          (*info->fprintf_func) (stream, "%%reserved");
859
22
        break;
860
861
1.51k
      case '!':
862
1.51k
                    if (X_RD (insn) == 31)
863
1
                      (*info->fprintf_func) (stream, "%%ver");
864
1.51k
        else if (X_RD (insn) == 23)
865
17
          (*info->fprintf_func) (stream, "%%pmcdper");
866
1.49k
        else if ((unsigned) X_RD (insn) < 17)
867
1.49k
          (*info->fprintf_func) (stream, "%%%s",
868
1.49k
               v9_priv_reg_names[X_RD (insn)]);
869
0
        else
870
0
          (*info->fprintf_func) (stream, "%%reserved");
871
1.51k
        break;
872
873
8
      case '$':
874
8
        if ((unsigned) X_RS1 (insn) < 32)
875
8
          (*info->fprintf_func) (stream, "%%%s",
876
8
               v9_hpriv_reg_names[X_RS1 (insn)]);
877
0
        else
878
0
          (*info->fprintf_func) (stream, "%%reserved");
879
8
        break;
880
881
55
      case '%':
882
55
        if ((unsigned) X_RD (insn) < 32)
883
55
          (*info->fprintf_func) (stream, "%%%s",
884
55
               v9_hpriv_reg_names[X_RD (insn)]);
885
0
        else
886
0
          (*info->fprintf_func) (stream, "%%reserved");
887
55
        break;
888
889
35
      case '/':
890
35
        if (X_RS1 (insn) < 16 || X_RS1 (insn) > 28)
891
0
          (*info->fprintf_func) (stream, "%%reserved");
892
35
        else
893
35
          (*info->fprintf_func) (stream, "%%%s",
894
35
               v9a_asr_reg_names[X_RS1 (insn)-16]);
895
35
        break;
896
897
157
      case '_':
898
157
        if (X_RD (insn) < 16 || X_RD (insn) > 28)
899
0
          (*info->fprintf_func) (stream, "%%reserved");
900
157
        else
901
157
          (*info->fprintf_func) (stream, "%%%s",
902
157
               v9a_asr_reg_names[X_RD (insn)-16]);
903
157
        break;
904
905
1.22k
      case '*':
906
1.22k
        {
907
1.22k
          const char *name = sparc_decode_prefetch (X_RD (insn));
908
909
1.22k
          if (name)
910
889
      (*info->fprintf_func) (stream, "%s", name);
911
338
          else
912
338
      (*info->fprintf_func) (stream, "%ld", X_RD (insn));
913
1.22k
          break;
914
2.12k
        }
915
916
58
      case 'M':
917
58
        (*info->fprintf_func) (stream, "%%asr%ld", X_RS1 (insn));
918
58
        break;
919
920
821
      case 'm':
921
821
        (*info->fprintf_func) (stream, "%%asr%ld", X_RD (insn));
922
821
        break;
923
924
479k
      case 'L':
925
479k
        info->target = memaddr + SEX (X_DISP30 (insn), 30) * 4;
926
479k
        (*info->print_address_func) (info->target, info);
927
479k
        break;
928
929
517k
      case 'n':
930
517k
        (*info->fprintf_func)
931
517k
          (stream, "%#x", SEX (X_DISP22 (insn), 22));
932
517k
        break;
933
934
170k
      case 'l':
935
170k
        info->target = memaddr + SEX (X_DISP22 (insn), 22) * 4;
936
170k
        (*info->print_address_func) (info->target, info);
937
170k
        break;
938
939
8.42k
      case 'A':
940
8.42k
        {
941
8.42k
          const char *name = sparc_decode_asi (X_ASI (insn));
942
943
8.42k
          if (name)
944
3.44k
      (*info->fprintf_func) (stream, "%s", name);
945
4.98k
          else
946
4.98k
      (*info->fprintf_func) (stream, "(%ld)", X_ASI (insn));
947
8.42k
          break;
948
2.12k
        }
949
950
442
      case 'C':
951
442
        (*info->fprintf_func) (stream, "%%csr");
952
442
        break;
953
954
29
      case 'F':
955
29
        (*info->fprintf_func) (stream, "%%fsr");
956
29
        break;
957
958
15
      case '(':
959
15
        (*info->fprintf_func) (stream, "%%efsr");
960
15
        break;
961
962
31
      case 'p':
963
31
        (*info->fprintf_func) (stream, "%%psr");
964
31
        break;
965
966
286
      case 'q':
967
286
        (*info->fprintf_func) (stream, "%%fq");
968
286
        break;
969
970
100
      case 'Q':
971
100
        (*info->fprintf_func) (stream, "%%cq");
972
100
        break;
973
974
41
      case 't':
975
41
        (*info->fprintf_func) (stream, "%%tbr");
976
41
        break;
977
978
4
      case 'w':
979
4
        (*info->fprintf_func) (stream, "%%wim");
980
4
        break;
981
982
20
      case 'x':
983
20
        (*info->fprintf_func) (stream, "%ld",
984
20
             ((X_LDST_I (insn) << 8)
985
20
              + X_ASI (insn)));
986
20
        break;
987
988
196
                  case '|': /* 2-bit immediate  */
989
196
                    (*info->fprintf_func) (stream, "%ld", X_IMM2 (insn));
990
196
                    break;
991
992
290
      case 'y':
993
290
        (*info->fprintf_func) (stream, "%%y");
994
290
        break;
995
996
11
      case 'u':
997
13
      case 'U':
998
13
        {
999
13
          int val = *s == 'U' ? X_RS1 (insn) : X_RD (insn);
1000
13
          const char *name = sparc_decode_sparclet_cpreg (val);
1001
1002
13
          if (name)
1003
3
      (*info->fprintf_func) (stream, "%s", name);
1004
10
          else
1005
10
      (*info->fprintf_func) (stream, "%%cpreg(%d)", val);
1006
13
          break;
1007
11
        }
1008
3.66M
      }
1009
3.66M
        }
1010
2.03M
    }
1011
1012
    /* If we are adding or or'ing something to rs1, then
1013
       check to see whether the previous instruction was
1014
       a sethi to the same register as in the sethi.
1015
       If so, attempt to print the result of the add or
1016
       or (in this context add and or do the same thing)
1017
       and its symbolic value.  */
1018
2.03M
    if (imm_ored_to_rs1 || imm_added_to_rs1)
1019
197k
      {
1020
197k
        unsigned long prev_insn;
1021
197k
        int errcode;
1022
1023
197k
        if (memaddr >= 4)
1024
197k
    errcode =
1025
197k
      (*info->read_memory_func)
1026
197k
      (memaddr - 4, buffer, sizeof (buffer), info);
1027
3
        else
1028
3
    errcode = 1;
1029
1030
197k
        prev_insn = getword (buffer);
1031
1032
197k
        if (errcode == 0)
1033
191k
    {
1034
      /* If it is a delayed branch, we need to look at the
1035
         instruction before the delayed branch.  This handles
1036
         sequences such as:
1037
1038
         sethi %o1, %hi(_foo), %o1
1039
         call _printf
1040
         or %o1, %lo(_foo), %o1  */
1041
1042
191k
      if (is_delayed_branch (prev_insn))
1043
58.9k
        {
1044
58.9k
          if (memaddr >= 8)
1045
58.9k
      errcode = (*info->read_memory_func)
1046
58.9k
        (memaddr - 8, buffer, sizeof (buffer), info);
1047
1
          else
1048
1
      errcode = 1;
1049
1050
58.9k
          prev_insn = getword (buffer);
1051
58.9k
        }
1052
191k
    }
1053
1054
        /* If there was a problem reading memory, then assume
1055
     the previous instruction was not sethi.  */
1056
197k
        if (errcode == 0)
1057
191k
    {
1058
      /* Is it sethi to the same register?  */
1059
191k
      if ((prev_insn & 0xc1c00000) == 0x01000000
1060
191k
          && X_RD (prev_insn) == X_RS1 (insn))
1061
16.0k
        {
1062
16.0k
          (*info->fprintf_func) (stream, "\t! ");
1063
16.0k
          info->target = (unsigned) X_IMM22 (prev_insn) << 10;
1064
16.0k
          if (imm_added_to_rs1)
1065
9.79k
      info->target += X_SIMM (insn, 13);
1066
6.28k
          else
1067
6.28k
      info->target |= X_SIMM (insn, 13);
1068
16.0k
          (*info->print_address_func) (info->target, info);
1069
16.0k
          info->insn_type = dis_dref;
1070
16.0k
          info->data_size = 4;  /* FIXME!!! */
1071
16.0k
        }
1072
191k
    }
1073
197k
      }
1074
1075
2.03M
    if (opcode->flags & (F_UNBR|F_CONDBR|F_JSR))
1076
688k
      {
1077
        /* FIXME -- check is_annulled flag.  */
1078
688k
        (void) is_annulled;
1079
688k
        if (opcode->flags & F_UNBR)
1080
64.0k
    info->insn_type = dis_branch;
1081
688k
        if (opcode->flags & F_CONDBR)
1082
142k
    info->insn_type = dis_condbranch;
1083
688k
        if (opcode->flags & F_JSR)
1084
481k
    info->insn_type = dis_jsr;
1085
688k
        if (opcode->flags & F_DELAYED)
1086
687k
    info->branch_delay_insns = 1;
1087
688k
      }
1088
1089
2.03M
    return sizeof (buffer);
1090
2.03M
  }
1091
16.5M
    }
1092
1093
517k
  info->insn_type = dis_noninsn;  /* Mark as non-valid instruction.  */
1094
517k
  (*info->fprintf_func) (stream, _("unknown"));
1095
517k
  return sizeof (buffer);
1096
2.55M
}