Coverage Report

Created: 2024-05-21 06:29

/src/binutils-gdb/opcodes/tic30-dis.c
Line
Count
Source (jump to first uncovered line)
1
/* Disassembly routines for TMS320C30 architecture
2
   Copyright (C) 1998-2024 Free Software Foundation, Inc.
3
   Contributed by Steven Haworth (steve@pm.cse.rmit.edu.au)
4
5
   This file is part of the GNU opcodes library.
6
7
   This library is free software; you can redistribute it and/or modify
8
   it under the terms of the GNU General Public License as published by
9
   the Free Software Foundation; either version 3, or (at your option)
10
   any later version.
11
12
   It is distributed in the hope that it will be useful, but WITHOUT
13
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
15
   License for more details.
16
17
   You should have received a copy of the GNU General Public License
18
   along with this file; see the file COPYING.  If not, write to the
19
   Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
20
   MA 02110-1301, USA.  */
21
22
#include "sysdep.h"
23
#include <errno.h>
24
#include <math.h>
25
#include "disassemble.h"
26
#include "opcode/tic30.h"
27
28
344k
#define NORMAL_INSN   1
29
11.3k
#define PARALLEL_INSN 2
30
31
/* Gets the type of instruction based on the top 2 or 3 bits of the
32
   instruction word.  */
33
96.0M
#define GET_TYPE(insn) (insn & 0x80000000 ? insn & 0xC0000000 : insn & 0xE0000000)
34
35
/* Instruction types.  */
36
661k
#define TWO_OPERAND_1 0x00000000
37
669k
#define TWO_OPERAND_2 0x40000000
38
341k
#define THREE_OPERAND 0x20000000
39
15.5k
#define PAR_STORE     0xC0000000
40
14.9k
#define MUL_ADDS      0x80000000
41
12.3k
#define BRANCHES      0x60000000
42
43
/* Specific instruction id bits.  */
44
12.3M
#define NORMAL_IDEN    0x1F800000
45
274k
#define PAR_STORE_IDEN 0x3E000000
46
18.5k
#define MUL_ADD_IDEN   0x2C000000
47
36.3k
#define BR_IMM_IDEN    0x1F000000
48
1.59M
#define BR_COND_IDEN   0x1C3F0000
49
50
/* Addressing modes.  */
51
139k
#define AM_REGISTER 0x00000000
52
6.03k
#define AM_DIRECT   0x00200000
53
4.96k
#define AM_INDIRECT 0x00400000
54
33.0k
#define AM_IMM      0x00600000
55
56
2.71k
#define P_FIELD 0x03000000
57
58
916
#define REG_AR0 0x08
59
32.8k
#define LDP_INSN 0x08700000
60
61
/* TMS320C30 program counter for current instruction.  */
62
static unsigned int _pc;
63
64
struct instruction
65
{
66
  int type;
67
  insn_template *tm;
68
  partemplate *ptm;
69
};
70
71
static int
72
get_tic30_instruction (unsigned long insn_word, struct instruction *insn)
73
355k
{
74
355k
  switch (GET_TYPE (insn_word))
75
355k
    {
76
330k
    case TWO_OPERAND_1:
77
334k
    case TWO_OPERAND_2:
78
337k
    case THREE_OPERAND:
79
337k
      insn->type = NORMAL_INSN;
80
337k
      {
81
337k
  insn_template *current_optab = (insn_template *) tic30_optab;
82
83
46.2M
  for (; current_optab < tic30_optab_end; current_optab++)
84
46.2M
    {
85
46.2M
      if (GET_TYPE (current_optab->base_opcode) == GET_TYPE (insn_word))
86
6.90M
        {
87
6.90M
    if (current_optab->operands == 0)
88
719k
      {
89
719k
        if (current_optab->base_opcode == insn_word)
90
288
          {
91
288
      insn->tm = current_optab;
92
288
      break;
93
288
          }
94
719k
      }
95
6.18M
    else if ((current_optab->base_opcode & NORMAL_IDEN) == (insn_word & NORMAL_IDEN))
96
335k
      {
97
335k
        insn->tm = current_optab;
98
335k
        break;
99
335k
      }
100
6.90M
        }
101
46.2M
    }
102
337k
      }
103
337k
      break;
104
105
7.79k
    case PAR_STORE:
106
7.79k
      insn->type = PARALLEL_INSN;
107
7.79k
      {
108
7.79k
  partemplate *current_optab = (partemplate *) tic30_paroptab;
109
110
161k
  for (; current_optab < tic30_paroptab_end; current_optab++)
111
159k
    {
112
159k
      if (GET_TYPE (current_optab->base_opcode) == GET_TYPE (insn_word))
113
137k
        {
114
137k
    if ((current_optab->base_opcode & PAR_STORE_IDEN)
115
137k
        == (insn_word & PAR_STORE_IDEN))
116
5.20k
      {
117
5.20k
        insn->ptm = current_optab;
118
5.20k
        break;
119
5.20k
      }
120
137k
        }
121
159k
    }
122
7.79k
      }
123
7.79k
      break;
124
125
3.58k
    case MUL_ADDS:
126
3.58k
      insn->type = PARALLEL_INSN;
127
3.58k
      {
128
3.58k
  partemplate *current_optab = (partemplate *) tic30_paroptab;
129
130
68.9k
  for (; current_optab < tic30_paroptab_end; current_optab++)
131
68.1k
    {
132
68.1k
      if (GET_TYPE (current_optab->base_opcode) == GET_TYPE (insn_word))
133
9.29k
        {
134
9.29k
    if ((current_optab->base_opcode & MUL_ADD_IDEN)
135
9.29k
        == (insn_word & MUL_ADD_IDEN))
136
2.71k
      {
137
2.71k
        insn->ptm = current_optab;
138
2.71k
        break;
139
2.71k
      }
140
9.29k
        }
141
68.1k
    }
142
3.58k
      }
143
3.58k
      break;
144
145
6.17k
    case BRANCHES:
146
6.17k
      insn->type = NORMAL_INSN;
147
6.17k
      {
148
6.17k
  insn_template *current_optab = (insn_template *) tic30_optab;
149
150
1.22M
  for (; current_optab < tic30_optab_end; current_optab++)
151
1.22M
    {
152
1.22M
      if (GET_TYPE (current_optab->base_opcode) == GET_TYPE (insn_word))
153
816k
        {
154
816k
    if (current_optab->operand_types[0] & Imm24)
155
18.1k
      {
156
18.1k
        if ((current_optab->base_opcode & BR_IMM_IDEN)
157
18.1k
      == (insn_word & BR_IMM_IDEN))
158
1.03k
          {
159
1.03k
      insn->tm = current_optab;
160
1.03k
      break;
161
1.03k
          }
162
18.1k
      }
163
798k
    else if (current_optab->operands > 0)
164
640k
      {
165
640k
        if ((current_optab->base_opcode & BR_COND_IDEN)
166
640k
      == (insn_word & BR_COND_IDEN))
167
2.95k
          {
168
2.95k
      insn->tm = current_optab;
169
2.95k
      break;
170
2.95k
          }
171
640k
      }
172
157k
    else
173
157k
      {
174
157k
        if ((current_optab->base_opcode & (BR_COND_IDEN | 0x00800000))
175
157k
      == (insn_word & (BR_COND_IDEN | 0x00800000)))
176
606
          {
177
606
      insn->tm = current_optab;
178
606
      break;
179
606
          }
180
157k
      }
181
816k
        }
182
1.22M
    }
183
6.17k
      }
184
6.17k
      break;
185
0
    default:
186
0
      return 0;
187
355k
    }
188
355k
  return 1;
189
355k
}
190
191
1.17M
#define OPERAND_BUFFER_LEN 15
192
193
static int
194
get_register_operand (unsigned char fragment, char *buffer)
195
501k
{
196
501k
  const reg *current_reg = tic30_regtab;
197
198
501k
  if (buffer == NULL)
199
0
    return 0;
200
4.80M
  for (; current_reg < tic30_regtab_end; current_reg++)
201
4.80M
    {
202
4.80M
      if ((fragment & 0x1F) == current_reg->opcode)
203
496k
  {
204
496k
    strncpy (buffer, current_reg->name, OPERAND_BUFFER_LEN - 1);
205
496k
    buffer[OPERAND_BUFFER_LEN - 1] = 0;
206
496k
    return 1;
207
496k
  }
208
4.80M
    }
209
4.55k
  return 0;
210
501k
}
211
212
static int
213
get_indirect_operand (unsigned short fragment,
214
          int size,
215
          char *buffer)
216
21.6k
{
217
21.6k
  unsigned char mod;
218
21.6k
  unsigned arnum;
219
21.6k
  unsigned char disp;
220
221
21.6k
  if (buffer == NULL)
222
0
    return 0;
223
  /* Determine which bits identify the sections of the indirect
224
     operand based on the size in bytes.  */
225
21.6k
  switch (size)
226
21.6k
    {
227
16.7k
    case 1:
228
16.7k
      mod = (fragment & 0x00F8) >> 3;
229
16.7k
      arnum = (fragment & 0x0007);
230
16.7k
      disp = 0;
231
16.7k
      break;
232
4.83k
    case 2:
233
4.83k
      mod = (fragment & 0xF800) >> 11;
234
4.83k
      arnum = (fragment & 0x0700) >> 8;
235
4.83k
      disp = (fragment & 0x00FF);
236
4.83k
      break;
237
0
    default:
238
0
      return 0;
239
21.6k
    }
240
21.6k
  {
241
21.6k
    const ind_addr_type *current_ind = tic30_indaddr_tab;
242
243
440k
    for (; current_ind < tic30_indaddrtab_end; current_ind++)
244
434k
      {
245
434k
  if (current_ind->modfield == mod)
246
17.5k
    {
247
17.5k
      if (current_ind->displacement == IMPLIED_DISP && size == 2)
248
2.52k
        continue;
249
250
14.9k
      else
251
14.9k
        {
252
14.9k
    size_t i, len;
253
14.9k
    int bufcnt;
254
255
14.9k
    len = strlen (current_ind->syntax);
256
257
112k
    for (i = 0, bufcnt = 0; i < len; i++, bufcnt++)
258
97.7k
      {
259
97.7k
        buffer[bufcnt] = current_ind->syntax[i];
260
261
97.7k
        if (bufcnt > 0
262
97.7k
      && bufcnt < OPERAND_BUFFER_LEN - 1
263
97.7k
      && buffer[bufcnt - 1] == 'a'
264
97.7k
      && buffer[bufcnt] == 'r')
265
14.9k
          buffer[++bufcnt] = arnum + '0';
266
        
267
97.7k
        if (bufcnt < OPERAND_BUFFER_LEN - 1
268
97.7k
      && buffer[bufcnt] == '('
269
97.7k
      && current_ind->displacement == DISP_REQUIRED)
270
2.52k
          {
271
2.52k
      snprintf (buffer + (bufcnt + 1),
272
2.52k
         OPERAND_BUFFER_LEN - (bufcnt + 1),
273
2.52k
         "%u", disp);
274
2.52k
      bufcnt += strlen (buffer + (bufcnt + 1));
275
2.52k
          }
276
97.7k
      }
277
14.9k
    buffer[bufcnt + 1] = '\0';
278
14.9k
    break;
279
14.9k
        }
280
17.5k
    }
281
434k
      }
282
21.6k
  }
283
21.6k
  return 1;
284
21.6k
}
285
286
static int
287
cnvt_tmsfloat_ieee (unsigned long tmsfloat, int size, float *ieeefloat)
288
30.3k
{
289
30.3k
  unsigned long exponent, sign, mant;
290
30.3k
  union
291
30.3k
  {
292
30.3k
    unsigned long l;
293
30.3k
    float f;
294
30.3k
  } val;
295
296
30.3k
  if (size == 2)
297
30.3k
    {
298
30.3k
      if ((tmsfloat & 0x0000F000) == 0x00008000)
299
5
  tmsfloat = 0x80000000;
300
30.3k
      else
301
30.3k
  {
302
30.3k
    tmsfloat <<= 16;
303
30.3k
    tmsfloat = (long) tmsfloat >> 4;
304
30.3k
  }
305
30.3k
    }
306
30.3k
  exponent = tmsfloat & 0xFF000000;
307
30.3k
  if (exponent == 0x80000000)
308
5
    {
309
5
      *ieeefloat = 0.0;
310
5
      return 1;
311
5
    }
312
30.3k
  exponent += 0x7F000000;
313
30.3k
  sign = (tmsfloat & 0x00800000) << 8;
314
30.3k
  mant = tmsfloat & 0x007FFFFF;
315
30.3k
  if (exponent == 0xFF000000)
316
0
    {
317
0
      if (mant == 0)
318
0
  *ieeefloat = ERANGE;
319
0
#ifdef HUGE_VALF
320
0
      if (sign == 0)
321
0
  *ieeefloat = HUGE_VALF;
322
0
      else
323
0
  *ieeefloat = -HUGE_VALF;
324
#else
325
      if (sign == 0)
326
  *ieeefloat = 1.0 / 0.0;
327
      else
328
  *ieeefloat = -1.0 / 0.0;
329
#endif
330
0
      return 1;
331
0
    }
332
30.3k
  exponent >>= 1;
333
30.3k
  if (sign)
334
422
    {
335
422
      mant = (~mant) & 0x007FFFFF;
336
422
      mant += 1;
337
422
      exponent += mant & 0x00800000;
338
422
      exponent &= 0x7F800000;
339
422
      mant &= 0x007FFFFF;
340
422
    }
341
30.3k
  if (tmsfloat == 0x80000000)
342
0
    sign = mant = exponent = 0;
343
30.3k
  tmsfloat = sign | exponent | mant;
344
30.3k
  val.l = tmsfloat;
345
30.3k
  *ieeefloat = val.f;
346
30.3k
  return 1;
347
30.3k
}
348
349
static int
350
print_two_operand (disassemble_info *info,
351
       unsigned long insn_word,
352
       struct instruction *insn)
353
334k
{
354
334k
  char name[12];
355
334k
  char operand[2][OPERAND_BUFFER_LEN] =
356
334k
  {
357
334k
    {0},
358
334k
    {0}
359
334k
  };
360
334k
  float f_number;
361
362
334k
  if (insn->tm == NULL)
363
746
    return 0;
364
333k
  strcpy (name, insn->tm->name);
365
333k
  if (insn->tm->opcode_modifier == AddressMode)
366
181k
    {
367
181k
      int src_op, dest_op;
368
      /* Determine whether instruction is a store or a normal instruction.  */
369
181k
      if ((insn->tm->operand_types[1] & (Direct | Indirect))
370
181k
    == (Direct | Indirect))
371
11.6k
  {
372
11.6k
    src_op = 1;
373
11.6k
    dest_op = 0;
374
11.6k
  }
375
170k
      else
376
170k
  {
377
170k
    src_op = 0;
378
170k
    dest_op = 1;
379
170k
  }
380
      /* Get the destination register.  */
381
181k
      if (insn->tm->operands == 2)
382
181k
  get_register_operand ((insn_word & 0x001F0000) >> 16, operand[dest_op]);
383
      /* Get the source operand based on addressing mode.  */
384
181k
      switch (insn_word & AddressMode)
385
181k
  {
386
138k
  case AM_REGISTER:
387
    /* Check for the NOP instruction before getting the operand.  */
388
138k
    if ((insn->tm->operand_types[0] & NotReq) == 0)
389
138k
      get_register_operand ((insn_word & 0x0000001F), operand[src_op]);
390
138k
    break;
391
5.47k
  case AM_DIRECT:
392
5.47k
    sprintf (operand[src_op], "@0x%lX", (insn_word & 0x0000FFFF));
393
5.47k
    break;
394
4.83k
  case AM_INDIRECT:
395
4.83k
    get_indirect_operand ((insn_word & 0x0000FFFF), 2, operand[src_op]);
396
4.83k
    break;
397
32.9k
  case AM_IMM:
398
    /* Get the value of the immediate operand based on variable type.  */
399
32.9k
    switch (insn->tm->imm_arg_type)
400
32.9k
      {
401
30.3k
      case Imm_Float:
402
30.3k
        cnvt_tmsfloat_ieee ((insn_word & 0x0000FFFF), 2, &f_number);
403
30.3k
        sprintf (operand[src_op], "%2.2f", f_number);
404
30.3k
        break;
405
2.33k
      case Imm_SInt:
406
2.33k
        sprintf (operand[src_op], "%d", (short) (insn_word & 0x0000FFFF));
407
2.33k
        break;
408
177
      case Imm_UInt:
409
177
        sprintf (operand[src_op], "%lu", (insn_word & 0x0000FFFF));
410
177
        break;
411
49
      default:
412
49
        return 0;
413
32.9k
      }
414
    /* Handle special case for LDP instruction.  */
415
32.8k
    if ((insn_word & 0xFFFFFF00) == LDP_INSN)
416
0
      {
417
0
        strcpy (name, "ldp");
418
0
        sprintf (operand[0], "0x%06lX", (insn_word & 0x000000FF) << 16);
419
0
        operand[1][0] = '\0';
420
0
      }
421
181k
  }
422
181k
    }
423
  /* Handle case for stack and rotate instructions.  */
424
152k
  else if (insn->tm->operands == 1)
425
151k
    {
426
151k
      if (insn->tm->opcode_modifier == StackOp)
427
151k
  get_register_operand ((insn_word & 0x001F0000) >> 16, operand[0]);
428
151k
    }
429
  /* Output instruction to stream.  */
430
333k
  info->fprintf_func (info->stream, "   %s %s%c%s", name,
431
333k
          operand[0][0] ? operand[0] : "",
432
333k
          operand[1][0] ? ',' : ' ',
433
333k
          operand[1][0] ? operand[1] : "");
434
333k
  return 1;
435
333k
}
436
437
static int
438
print_three_operand (disassemble_info *info,
439
         unsigned long insn_word,
440
         struct instruction *insn)
441
3.39k
{
442
3.39k
  char operand[3][OPERAND_BUFFER_LEN] =
443
3.39k
  {
444
3.39k
    {0},
445
3.39k
    {0},
446
3.39k
    {0}
447
3.39k
  };
448
449
3.39k
  if (insn->tm == NULL)
450
1.67k
    return 0;
451
1.71k
  switch (insn_word & AddressMode)
452
1.71k
    {
453
880
    case AM_REGISTER:
454
880
      get_register_operand ((insn_word & 0x000000FF), operand[0]);
455
880
      get_register_operand ((insn_word & 0x0000FF00) >> 8, operand[1]);
456
880
      break;
457
565
    case AM_DIRECT:
458
565
      get_register_operand ((insn_word & 0x000000FF), operand[0]);
459
565
      get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1]);
460
565
      break;
461
137
    case AM_INDIRECT:
462
137
      get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0]);
463
137
      get_register_operand ((insn_word & 0x0000FF00) >> 8, operand[1]);
464
137
      break;
465
130
    case AM_IMM:
466
130
      get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0]);
467
130
      get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1]);
468
130
      break;
469
0
    default:
470
0
      return 0;
471
1.71k
    }
472
1.71k
  if (insn->tm->operands == 3)
473
1.60k
    get_register_operand ((insn_word & 0x001F0000) >> 16, operand[2]);
474
1.71k
  info->fprintf_func (info->stream, "   %s %s,%s%c%s", insn->tm->name,
475
1.71k
          operand[0], operand[1],
476
1.71k
          operand[2][0] ? ',' : ' ',
477
1.71k
          operand[2][0] ? operand[2] : "");
478
1.71k
  return 1;
479
1.71k
}
480
481
static int
482
print_par_insn (disassemble_info *info,
483
    unsigned long insn_word,
484
    struct instruction *insn)
485
11.3k
{
486
11.3k
  size_t i, len;
487
11.3k
  char *name1, *name2;
488
11.3k
  char operand[2][3][OPERAND_BUFFER_LEN] =
489
11.3k
  {
490
11.3k
    {
491
11.3k
      {0},
492
11.3k
      {0},
493
11.3k
      {0}
494
11.3k
    },
495
11.3k
    {
496
11.3k
      {0},
497
11.3k
      {0},
498
11.3k
      {0}
499
11.3k
    }
500
11.3k
  };
501
502
11.3k
  if (insn->ptm == NULL)
503
3.46k
    return 0;
504
  /* Parse out the names of each of the parallel instructions from the
505
     q_insn1_insn2 format.  */
506
7.91k
  name1 = (char *) strdup (insn->ptm->name + 2);
507
7.91k
  name2 = "";
508
7.91k
  len = strlen (name1);
509
40.4k
  for (i = 0; i < len; i++)
510
40.4k
    {
511
40.4k
      if (name1[i] == '_')
512
7.91k
  {
513
7.91k
    name2 = &name1[i + 1];
514
7.91k
    name1[i] = '\0';
515
7.91k
    break;
516
7.91k
  }
517
40.4k
    }
518
  /* Get the operands of the instruction based on the operand order.  */
519
7.91k
  switch (insn->ptm->oporder)
520
7.91k
    {
521
2.50k
    case OO_4op1:
522
2.50k
      get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0][0]);
523
2.50k
      get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1][1]);
524
2.50k
      get_register_operand ((insn_word >> 16) & 0x07, operand[1][0]);
525
2.50k
      get_register_operand ((insn_word >> 22) & 0x07, operand[0][1]);
526
2.50k
      break;
527
217
    case OO_4op2:
528
217
      get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0][0]);
529
217
      get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1][0]);
530
217
      get_register_operand ((insn_word >> 19) & 0x07, operand[1][1]);
531
217
      get_register_operand ((insn_word >> 22) & 0x07, operand[0][1]);
532
217
      break;
533
562
    case OO_4op3:
534
562
      get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0][1]);
535
562
      get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1][1]);
536
562
      get_register_operand ((insn_word >> 16) & 0x07, operand[1][0]);
537
562
      get_register_operand ((insn_word >> 22) & 0x07, operand[0][0]);
538
562
      break;
539
1.00k
    case OO_5op1:
540
1.00k
      get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0][0]);
541
1.00k
      get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1][1]);
542
1.00k
      get_register_operand ((insn_word >> 16) & 0x07, operand[1][0]);
543
1.00k
      get_register_operand ((insn_word >> 19) & 0x07, operand[0][1]);
544
1.00k
      get_register_operand ((insn_word >> 22) & 0x07, operand[0][2]);
545
1.00k
      break;
546
908
    case OO_5op2:
547
908
      get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0][1]);
548
908
      get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1][1]);
549
908
      get_register_operand ((insn_word >> 16) & 0x07, operand[1][0]);
550
908
      get_register_operand ((insn_word >> 19) & 0x07, operand[0][0]);
551
908
      get_register_operand ((insn_word >> 22) & 0x07, operand[0][2]);
552
908
      break;
553
2.71k
    case OO_PField:
554
2.71k
      if (insn_word & 0x00800000)
555
1.38k
  get_register_operand (0x01, operand[0][2]);
556
1.33k
      else
557
1.33k
  get_register_operand (0x00, operand[0][2]);
558
2.71k
      if (insn_word & 0x00400000)
559
509
  get_register_operand (0x03, operand[1][2]);
560
2.20k
      else
561
2.20k
  get_register_operand (0x02, operand[1][2]);
562
2.71k
      switch (insn_word & P_FIELD)
563
2.71k
  {
564
862
  case 0x00000000:
565
862
    get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0][1]);
566
862
    get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[0][0]);
567
862
    get_register_operand ((insn_word >> 16) & 0x07, operand[1][1]);
568
862
    get_register_operand ((insn_word >> 19) & 0x07, operand[1][0]);
569
862
    break;
570
707
  case 0x01000000:
571
707
    get_indirect_operand ((insn_word & 0x000000FF), 1, operand[1][0]);
572
707
    get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[0][0]);
573
707
    get_register_operand ((insn_word >> 16) & 0x07, operand[1][1]);
574
707
    get_register_operand ((insn_word >> 19) & 0x07, operand[0][1]);
575
707
    break;
576
574
  case 0x02000000:
577
574
    get_indirect_operand ((insn_word & 0x000000FF), 1, operand[1][1]);
578
574
    get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1][0]);
579
574
    get_register_operand ((insn_word >> 16) & 0x07, operand[0][1]);
580
574
    get_register_operand ((insn_word >> 19) & 0x07, operand[0][0]);
581
574
    break;
582
573
  case 0x03000000:
583
573
    get_indirect_operand ((insn_word & 0x000000FF), 1, operand[1][1]);
584
573
    get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[0][0]);
585
573
    get_register_operand ((insn_word >> 16) & 0x07, operand[1][0]);
586
573
    get_register_operand ((insn_word >> 19) & 0x07, operand[0][1]);
587
573
    break;
588
2.71k
  }
589
2.71k
      break;
590
2.71k
    default:
591
0
      return 0;
592
7.91k
    }
593
7.91k
  info->fprintf_func (info->stream, "   %s %s,%s%c%s", name1,
594
7.91k
          operand[0][0], operand[0][1],
595
7.91k
          operand[0][2][0] ? ',' : ' ',
596
7.91k
          operand[0][2][0] ? operand[0][2] : "");
597
7.91k
  info->fprintf_func (info->stream, "\n\t\t\t|| %s %s,%s%c%s", name2,
598
7.91k
          operand[1][0], operand[1][1],
599
7.91k
          operand[1][2][0] ? ',' : ' ',
600
7.91k
          operand[1][2][0] ? operand[1][2] : "");
601
7.91k
  free (name1);
602
7.91k
  return 1;
603
7.91k
}
604
605
static int
606
print_branch (disassemble_info *info,
607
        unsigned long insn_word,
608
        struct instruction *insn)
609
6.17k
{
610
6.17k
  char operand[2][OPERAND_BUFFER_LEN] =
611
6.17k
  {
612
6.17k
    {0},
613
6.17k
    {0}
614
6.17k
  };
615
6.17k
  unsigned long address;
616
6.17k
  int print_label = 0;
617
618
6.17k
  if (insn->tm == NULL)
619
1.58k
    return 0;
620
  /* Get the operands for 24-bit immediate jumps.  */
621
4.59k
  if (insn->tm->operand_types[0] & Imm24)
622
1.03k
    {
623
1.03k
      address = insn_word & 0x00FFFFFF;
624
1.03k
      sprintf (operand[0], "0x%lX", address);
625
1.03k
      print_label = 1;
626
1.03k
    }
627
  /* Get the operand for the trap instruction.  */
628
3.56k
  else if (insn->tm->operand_types[0] & IVector)
629
360
    {
630
360
      address = insn_word & 0x0000001F;
631
360
      sprintf (operand[0], "0x%lX", address);
632
360
    }
633
3.20k
  else
634
3.20k
    {
635
3.20k
      address = insn_word & 0x0000FFFF;
636
      /* Get the operands for the DB instructions.  */
637
3.20k
      if (insn->tm->operands == 2)
638
916
  {
639
916
    get_register_operand (((insn_word & 0x01C00000) >> 22) + REG_AR0, operand[0]);
640
916
    if (insn_word & PCRel)
641
539
      {
642
539
        sprintf (operand[1], "%d", (short) address);
643
539
        print_label = 1;
644
539
      }
645
377
    else
646
377
      get_register_operand (insn_word & 0x0000001F, operand[1]);
647
916
  }
648
      /* Get the operands for the standard branches.  */
649
2.28k
      else if (insn->tm->operands == 1)
650
1.67k
  {
651
1.67k
    if (insn_word & PCRel)
652
741
      {
653
741
        address = (short) address;
654
741
        sprintf (operand[0], "%ld", address);
655
741
        print_label = 1;
656
741
      }
657
937
    else
658
937
      get_register_operand (insn_word & 0x0000001F, operand[0]);
659
1.67k
  }
660
3.20k
    }
661
4.59k
  info->fprintf_func (info->stream, "   %s %s%c%s", insn->tm->name,
662
4.59k
          operand[0][0] ? operand[0] : "",
663
4.59k
          operand[1][0] ? ',' : ' ',
664
4.59k
          operand[1][0] ? operand[1] : "");
665
  /* Print destination of branch in relation to current symbol.  */
666
4.59k
  if (print_label && info->symbols)
667
0
    {
668
0
      asymbol *sym = *info->symbols;
669
670
0
      if ((insn->tm->opcode_modifier == PCRel) && (insn_word & PCRel))
671
0
  {
672
0
    address = (_pc + 1 + (short) address) - ((sym->section->vma + sym->value) / 4);
673
    /* Check for delayed instruction, if so adjust destination.  */
674
0
    if (insn_word & 0x00200000)
675
0
      address += 2;
676
0
  }
677
0
      else
678
0
  {
679
0
    address -= ((sym->section->vma + sym->value) / 4);
680
0
  }
681
0
      if (address == 0)
682
0
  info->fprintf_func (info->stream, " <%s>", sym->name);
683
0
      else
684
0
  info->fprintf_func (info->stream, " <%s %c %lu>", sym->name,
685
0
          ((short) address < 0) ? '-' : '+',
686
0
          address);
687
0
    }
688
4.59k
  return 1;
689
6.17k
}
690
691
int
692
print_insn_tic30 (bfd_vma pc, disassemble_info *info)
693
356k
{
694
356k
  unsigned long insn_word;
695
356k
  struct instruction insn = { 0, NULL, NULL };
696
356k
  bfd_vma bufaddr = pc - info->buffer_vma;
697
698
356k
  if (bufaddr + 3 >= info->buffer_length)
699
1.05k
    return -1;
700
701
  /* Obtain the current instruction word from the buffer.  */
702
355k
  insn_word = (((unsigned) *(info->buffer + bufaddr) << 24)
703
355k
         | (*(info->buffer + bufaddr + 1) << 16)
704
355k
         | (*(info->buffer + bufaddr + 2) << 8)
705
355k
         | *(info->buffer + bufaddr + 3));
706
355k
  _pc = pc / 4;
707
  /* Get the instruction referred to by the current instruction word
708
     and print it out based on its type.  */
709
355k
  if (!get_tic30_instruction (insn_word, &insn))
710
0
    return -1;
711
355k
  switch (GET_TYPE (insn_word))
712
355k
    {
713
330k
    case TWO_OPERAND_1:
714
334k
    case TWO_OPERAND_2:
715
334k
      if (!print_two_operand (info, insn_word, &insn))
716
795
  return -1;
717
333k
      break;
718
333k
    case THREE_OPERAND:
719
3.39k
      if (!print_three_operand (info, insn_word, &insn))
720
1.67k
  return -1;
721
1.71k
      break;
722
7.79k
    case PAR_STORE:
723
11.3k
    case MUL_ADDS:
724
11.3k
      if (!print_par_insn (info, insn_word, &insn))
725
3.46k
  return -1;
726
7.91k
      break;
727
7.91k
    case BRANCHES:
728
6.17k
      if (!print_branch (info, insn_word, &insn))
729
1.58k
  return -1;
730
4.59k
      break;
731
355k
    }
732
347k
  return 4;
733
355k
}