Coverage Report

Created: 2024-05-21 06:29

/src/binutils-gdb/opcodes/tic4x-dis.c
Line
Count
Source (jump to first uncovered line)
1
/* Print instructions for the Texas TMS320C[34]X, for GDB and GNU Binutils.
2
3
   Copyright (C) 2002-2024 Free Software Foundation, Inc.
4
5
   Contributed by Michael P. Hayes (m.hayes@elec.canterbury.ac.nz)
6
7
   This file is part of the GNU opcodes library.
8
9
   This library is free software; you can redistribute it and/or modify
10
   it under the terms of the GNU General Public License as published by
11
   the Free Software Foundation; either version 3, or (at your option)
12
   any later version.
13
14
   It is distributed in the hope that it will be useful, but WITHOUT
15
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
17
   License for more details.
18
19
   You should have received a copy of the GNU General Public License
20
   along with this program; if not, write to the Free Software
21
   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
22
   MA 02110-1301, USA.  */
23
24
#include "sysdep.h"
25
#include <math.h>
26
#include "libiberty.h"
27
#include "disassemble.h"
28
#include "opcode/tic4x.h"
29
30
#define TIC4X_DEBUG 0
31
32
662k
#define TIC4X_HASH_SIZE   11   /* 11 (bits) and above should give unique entries.  */
33
264k
#define TIC4X_SPESOP_SIZE 8    /* Max 8. ops for special instructions.  */
34
35
typedef enum
36
{
37
  IMMED_SINT,
38
  IMMED_SUINT,
39
  IMMED_SFLOAT,
40
  IMMED_INT,
41
  IMMED_UINT,
42
  IMMED_FLOAT
43
}
44
immed_t;
45
46
typedef enum
47
{
48
  INDIRECT_SHORT,
49
  INDIRECT_LONG,
50
  INDIRECT_TIC4X
51
}
52
indirect_t;
53
54
static unsigned long tic4x_version = 0;
55
static unsigned int tic4x_dp = 0;
56
static tic4x_inst_t **optab = NULL;
57
static tic4x_inst_t **optab_special = NULL;
58
static const char *registernames[REG_TABLE_SIZE];
59
60
static int
61
tic4x_pc_offset (unsigned int op)
62
8.19k
{
63
  /* Determine the PC offset for a C[34]x instruction.
64
     This could be simplified using some boolean algebra
65
     but at the expense of readability.  */
66
8.19k
  switch (op >> 24)
67
8.19k
    {
68
420
    case 0x60:  /* br */
69
1.79k
    case 0x62:  /* call  (C4x) */
70
2.41k
    case 0x64:  /* rptb  (C4x) */
71
2.41k
      return 1;
72
856
    case 0x61:  /* brd */
73
1.34k
    case 0x63:  /* laj */
74
1.78k
    case 0x65:  /* rptbd (C4x) */
75
1.78k
      return 3;
76
0
    case 0x66:  /* swi */
77
0
    case 0x67:
78
0
      return 0;
79
3.99k
    default:
80
3.99k
      break;
81
8.19k
    }
82
83
3.99k
  switch ((op & 0xffe00000) >> 20)
84
3.99k
    {
85
134
    case 0x6a0: /* bB */
86
418
    case 0x720: /* callB */
87
418
    case 0x740: /* trapB */
88
418
      return 1;
89
90
96
    case 0x6a2: /* bBd */
91
1.45k
    case 0x6a6: /* bBat */
92
1.47k
    case 0x6aa: /* bBaf */
93
1.73k
    case 0x722: /* lajB */
94
1.73k
    case 0x748: /* latB */
95
1.73k
    case 0x798: /* rptbd */
96
1.73k
      return 3;
97
98
1.84k
    default:
99
1.84k
      break;
100
3.99k
    }
101
102
1.84k
  switch ((op & 0xfe200000) >> 20)
103
1.84k
    {
104
254
    case 0x6e0: /* dbB */
105
254
      return 1;
106
107
1.59k
    case 0x6e2: /* dbBd */
108
1.59k
      return 3;
109
110
0
    default:
111
0
      break;
112
1.84k
    }
113
114
0
  return 0;
115
1.84k
}
116
117
static int
118
tic4x_print_char (struct disassemble_info * info, char ch)
119
772k
{
120
772k
  if (info != NULL)
121
309k
    (*info->fprintf_func) (info->stream, "%c", ch);
122
772k
  return 1;
123
772k
}
124
125
static int
126
tic4x_print_str (struct disassemble_info *info, const char *str)
127
65.4k
{
128
65.4k
  if (info != NULL)
129
28.5k
    (*info->fprintf_func) (info->stream, "%s", str);
130
65.4k
  return 1;
131
65.4k
}
132
133
static int
134
tic4x_print_register (struct disassemble_info *info, unsigned long regno)
135
191k
{
136
191k
  unsigned int i;
137
138
191k
  if (registernames[REG_R0] == NULL)
139
117
    {
140
4.32k
      for (i = 0; i < tic3x_num_registers; i++)
141
4.21k
  registernames[tic3x_registers[i].regno] = tic3x_registers[i].name;
142
117
      if (IS_CPU_TIC4X (tic4x_version))
143
78
  {
144
    /* Add C4x additional registers, overwriting
145
       any C3x registers if necessary.  */
146
1.09k
    for (i = 0; i < tic4x_num_registers; i++)
147
1.01k
      registernames[tic4x_registers[i].regno] = tic4x_registers[i].name;
148
78
  }
149
117
    }
150
191k
  if (regno > (IS_CPU_TIC4X (tic4x_version) ? TIC4X_REG_MAX : TIC3X_REG_MAX))
151
15.7k
    return 0;
152
175k
  if (info != NULL)
153
79.2k
    (*info->fprintf_func) (info->stream, "%s", registernames[regno]);
154
175k
  return 1;
155
191k
}
156
157
static int
158
tic4x_print_addr (struct disassemble_info *info, unsigned long addr)
159
12.7k
{
160
12.7k
  if (info != NULL)
161
8.06k
    (*info->print_address_func)(addr, info);
162
12.7k
  return 1;
163
12.7k
}
164
165
static int
166
tic4x_print_relative (struct disassemble_info *info,
167
          unsigned long pc,
168
          long offset,
169
          unsigned long opcode)
170
8.19k
{
171
8.19k
  return tic4x_print_addr (info, pc + offset + tic4x_pc_offset (opcode));
172
8.19k
}
173
174
static int
175
tic4x_print_direct (struct disassemble_info *info, unsigned long arg)
176
6.77k
{
177
6.77k
  if (info != NULL)
178
3.37k
    {
179
3.37k
      (*info->fprintf_func) (info->stream, "@");
180
3.37k
      tic4x_print_addr (info, arg + (tic4x_dp << 16));
181
3.37k
    }
182
6.77k
  return 1;
183
6.77k
}
184
#if 0
185
/* FIXME: make the floating point stuff not rely on host
186
   floating point arithmetic.  */
187
188
static void
189
tic4x_print_ftoa (unsigned int val, FILE *stream, fprintf_ftype pfunc)
190
{
191
  int e;
192
  int s;
193
  int f;
194
  double num = 0.0;
195
196
  e = EXTRS (val, 31, 24);  /* Exponent.  */
197
  if (e != -128)
198
    {
199
      s = EXTRU (val, 23, 23);  /* Sign bit.  */
200
      f = EXTRU (val, 22, 0); /* Mantissa.  */
201
      if (s)
202
  f += -2 * (1 << 23);
203
      else
204
  f += (1 << 23);
205
      num = f / (double)(1 << 23);
206
      num = ldexp (num, e);
207
    }
208
  (*pfunc)(stream, "%.9g", num);
209
}
210
#endif
211
212
static int
213
tic4x_print_immed (struct disassemble_info *info,
214
       immed_t type,
215
       unsigned long arg)
216
32.3k
{
217
32.3k
  int s;
218
32.3k
  int f;
219
32.3k
  int e;
220
32.3k
  double num = 0.0;
221
222
32.3k
  if (info == NULL)
223
17.7k
    return 1;
224
14.5k
  switch (type)
225
14.5k
    {
226
2.04k
    case IMMED_SINT:
227
2.04k
    case IMMED_INT:
228
2.04k
      (*info->fprintf_func) (info->stream, "%ld", (long) arg);
229
2.04k
      break;
230
231
520
    case IMMED_SUINT:
232
10.9k
    case IMMED_UINT:
233
10.9k
      (*info->fprintf_func) (info->stream, "%lu", arg);
234
10.9k
      break;
235
236
1.58k
    case IMMED_SFLOAT:
237
1.58k
      e = EXTRS (arg, 15, 12);
238
1.58k
      if (e != -8)
239
1.52k
  {
240
1.52k
    s = EXTRU (arg, 11, 11);
241
1.52k
    f = EXTRU (arg, 10, 0);
242
1.52k
    if (s)
243
601
      f += -2 * (1 << 11);
244
921
    else
245
921
      f += (1 << 11);
246
1.52k
    num = f / (double)(1 << 11);
247
1.52k
    num = ldexp (num, e);
248
1.52k
  }
249
1.58k
      (*info->fprintf_func) (info->stream, "%f", num);
250
1.58k
      break;
251
0
    case IMMED_FLOAT:
252
0
      e = EXTRS (arg, 31, 24);
253
0
      if (e != -128)
254
0
  {
255
0
    s = EXTRU (arg, 23, 23);
256
0
    f = EXTRU (arg, 22, 0);
257
0
    if (s)
258
0
      f += -2 * (1 << 23);
259
0
    else
260
0
      f += (1 << 23);
261
0
    num = f / (double)(1 << 23);
262
0
    num = ldexp (num, e);
263
0
  }
264
0
      (*info->fprintf_func) (info->stream, "%f", num);
265
0
      break;
266
14.5k
    }
267
14.5k
  return 1;
268
14.5k
}
269
270
static int
271
tic4x_print_cond (struct disassemble_info *info, unsigned int cond)
272
14.4k
{
273
14.4k
  static tic4x_cond_t **condtable = NULL;
274
14.4k
  unsigned int i;
275
276
14.4k
  if (condtable == NULL)
277
1
    {
278
1
      condtable = xcalloc (32, sizeof (tic4x_cond_t *));
279
29
      for (i = 0; i < tic4x_num_conds; i++)
280
28
  condtable[tic4x_conds[i].cond] = (tic4x_cond_t *)(tic4x_conds + i);
281
1
    }
282
14.4k
  if (cond > 31 || condtable[cond] == NULL)
283
2.82k
    return 0;
284
11.5k
  if (info != NULL)
285
3.77k
    (*info->fprintf_func) (info->stream, "%s", condtable[cond]->name);
286
11.5k
  return 1;
287
14.4k
}
288
289
static int
290
tic4x_print_indirect (struct disassemble_info *info,
291
          indirect_t type,
292
          unsigned long arg)
293
54.4k
{
294
54.4k
  unsigned int aregno;
295
54.4k
  unsigned int modn;
296
54.4k
  unsigned int disp;
297
54.4k
  const char *a;
298
299
54.4k
  aregno = 0;
300
54.4k
  modn = 0;
301
54.4k
  disp = 1;
302
54.4k
  switch(type)
303
54.4k
    {
304
6.18k
    case INDIRECT_TIC4X:    /* *+ARn(disp) */
305
6.18k
      disp = EXTRU (arg, 7, 3);
306
6.18k
      aregno = EXTRU (arg, 2, 0) + REG_AR0;
307
6.18k
      modn = 0;
308
6.18k
      break;
309
43.3k
    case INDIRECT_SHORT:
310
43.3k
      disp = 1;
311
43.3k
      aregno = EXTRU (arg, 2, 0) + REG_AR0;
312
43.3k
      modn = EXTRU (arg, 7, 3);
313
43.3k
      break;
314
4.88k
    case INDIRECT_LONG:
315
4.88k
      disp = EXTRU (arg, 7, 0);
316
4.88k
      aregno = EXTRU (arg, 10, 8) + REG_AR0;
317
4.88k
      modn = EXTRU (arg, 15, 11);
318
4.88k
      if (modn > 7 && disp != 0)
319
3.00k
  return 0;
320
1.88k
      break;
321
1.88k
    default:
322
0
        (*info->fprintf_func)(info->stream, "# internal error: Unknown indirect type %d", type);
323
0
        return 0;
324
54.4k
    }
325
51.4k
  if (modn > TIC3X_MODN_MAX)
326
4.88k
    return 0;
327
46.5k
  a = tic4x_indirects[modn].name;
328
341k
  while (*a)
329
294k
    {
330
294k
      switch (*a)
331
294k
  {
332
46.5k
  case 'a':
333
46.5k
    tic4x_print_register (info, aregno);
334
46.5k
    break;
335
23.5k
  case 'd':
336
23.5k
    tic4x_print_immed (info, IMMED_UINT, disp);
337
23.5k
    break;
338
10.4k
  case 'y':
339
10.4k
    tic4x_print_str (info, "ir0");
340
10.4k
    break;
341
9.47k
  case 'z':
342
9.47k
    tic4x_print_str (info, "ir1");
343
9.47k
    break;
344
204k
  default:
345
204k
    tic4x_print_char (info, *a);
346
204k
    break;
347
294k
  }
348
294k
      a++;
349
294k
    }
350
46.5k
  return 1;
351
46.5k
}
352
353
static int
354
tic4x_print_op (struct disassemble_info *info,
355
    unsigned long instruction,
356
    tic4x_inst_t *p,
357
    unsigned long pc)
358
92.6k
{
359
92.6k
  int val;
360
92.6k
  const char *s;
361
92.6k
  const char *parallel = NULL;
362
363
  /* Print instruction name.  */
364
92.6k
  s = p->name;
365
470k
  while (*s && parallel == NULL)
366
380k
    {
367
380k
      switch (*s)
368
380k
  {
369
6.27k
  case 'B':
370
6.27k
    if (! tic4x_print_cond (info, EXTRU (instruction, 20, 16)))
371
265
      return 0;
372
6.01k
    break;
373
8.13k
  case 'C':
374
8.13k
    if (! tic4x_print_cond (info, EXTRU (instruction, 27, 23)))
375
2.55k
      return 0;
376
5.58k
    break;
377
23.7k
  case '_':
378
23.7k
    parallel = s + 1; /* Skip past `_' in name.  */
379
23.7k
    break;
380
342k
  default:
381
342k
    tic4x_print_char (info, *s);
382
342k
    break;
383
380k
  }
384
378k
      s++;
385
378k
    }
386
387
  /* Print arguments.  */
388
89.8k
  s = p->args;
389
89.8k
  if (*s)
390
89.5k
    tic4x_print_char (info, ' ');
391
392
425k
  while (*s)
393
359k
    {
394
359k
      switch (*s)
395
359k
  {
396
4.88k
  case '*': /* Indirect 0--15.  */
397
4.88k
    if (! tic4x_print_indirect (info, INDIRECT_LONG,
398
4.88k
              EXTRU (instruction, 15, 0)))
399
3.04k
      return 0;
400
1.84k
    break;
401
402
1.84k
  case '#': /* Only used for ldp, ldpk.  */
403
14
    tic4x_print_immed (info, IMMED_UINT, EXTRU (instruction, 15, 0));
404
14
    break;
405
406
6.77k
  case '@': /* Direct 0--15.  */
407
6.77k
    tic4x_print_direct (info, EXTRU (instruction, 15, 0));
408
6.77k
    break;
409
410
2.72k
  case 'A': /* Address register 24--22.  */
411
2.72k
    if (! tic4x_print_register (info, EXTRU (instruction, 24, 22) +
412
2.72k
              REG_AR0))
413
0
      return 0;
414
2.72k
    break;
415
416
5.37k
  case 'B': /* 24-bit unsigned int immediate br(d)/call/rptb
417
         address 0--23.  */
418
5.37k
    if (IS_CPU_TIC4X (tic4x_version))
419
4.19k
      tic4x_print_relative (info, pc, EXTRS (instruction, 23, 0),
420
4.19k
          p->opcode);
421
1.17k
    else
422
1.17k
      tic4x_print_addr (info, EXTRU (instruction, 23, 0));
423
5.37k
    break;
424
425
4.12k
  case 'C': /* Indirect (short C4x) 0--7.  */
426
4.12k
    if (! IS_CPU_TIC4X (tic4x_version))
427
0
      return 0;
428
4.12k
    if (! tic4x_print_indirect (info, INDIRECT_TIC4X,
429
4.12k
              EXTRU (instruction, 7, 0)))
430
0
      return 0;
431
4.12k
    break;
432
433
4.12k
  case 'D':
434
    /* Cockup if get here...  */
435
0
    break;
436
437
2.83k
  case 'E': /* Register 0--7.  */
438
3.15k
        case 'e':
439
3.15k
    if (! tic4x_print_register (info, EXTRU (instruction, 7, 0)))
440
1.34k
      return 0;
441
1.81k
    break;
442
443
3.26k
  case 'F': /* 16-bit float immediate 0--15.  */
444
3.26k
    tic4x_print_immed (info, IMMED_SFLOAT,
445
3.26k
           EXTRU (instruction, 15, 0));
446
3.26k
    break;
447
448
23.7k
        case 'i': /* Extended indirect 0--7.  */
449
23.7k
          if (EXTRU (instruction, 7, 5) == 7)
450
4.95k
            {
451
4.95k
              if (!tic4x_print_register (info, EXTRU (instruction, 4, 0)))
452
122
                return 0;
453
4.82k
              break;
454
4.95k
            }
455
          /* Fallthrough */
456
457
19.5k
  case 'I': /* Indirect (short) 0--7.  */
458
19.5k
    if (! tic4x_print_indirect (info, INDIRECT_SHORT,
459
19.5k
              EXTRU (instruction, 7, 0)))
460
887
      return 0;
461
18.6k
    break;
462
463
18.6k
        case 'j': /* Extended indirect 8--15 */
464
6.06k
          if (EXTRU (instruction, 15, 13) == 7)
465
887
            {
466
887
              if (! tic4x_print_register (info, EXTRU (instruction, 12, 8)))
467
66
                return 0;
468
821
              break;
469
887
            }
470
    /* Fall through.  */
471
472
23.7k
  case 'J': /* Indirect (short) 8--15.  */
473
23.7k
    if (! tic4x_print_indirect (info, INDIRECT_SHORT,
474
23.7k
              EXTRU (instruction, 15, 8)))
475
3.95k
      return 0;
476
19.8k
    break;
477
478
19.8k
  case 'G': /* Register 8--15.  */
479
3.67k
        case 'g':
480
3.67k
    if (! tic4x_print_register (info, EXTRU (instruction, 15, 8)))
481
2.56k
      return 0;
482
1.10k
    break;
483
484
21.9k
  case 'H': /* Register 16--18.  */
485
21.9k
    if (! tic4x_print_register (info, EXTRU (instruction, 18, 16)))
486
0
      return 0;
487
21.9k
    break;
488
489
21.9k
  case 'K': /* Register 19--21.  */
490
14.2k
    if (! tic4x_print_register (info, EXTRU (instruction, 21, 19)))
491
0
      return 0;
492
14.2k
    break;
493
494
16.8k
  case 'L': /* Register 22--24.  */
495
16.8k
    if (! tic4x_print_register (info, EXTRU (instruction, 24, 22)))
496
0
      return 0;
497
16.8k
    break;
498
499
16.8k
  case 'M': /* Register 22--22.  */
500
5.87k
    tic4x_print_register (info, EXTRU (instruction, 22, 22) + REG_R2);
501
5.87k
    break;
502
503
5.92k
  case 'N': /* Register 23--23.  */
504
5.92k
    tic4x_print_register (info, EXTRU (instruction, 23, 23) + REG_R0);
505
5.92k
    break;
506
507
2.06k
  case 'O': /* Indirect (short C4x) 8--15.  */
508
2.06k
    if (! IS_CPU_TIC4X (tic4x_version))
509
0
      return 0;
510
2.06k
    if (! tic4x_print_indirect (info, INDIRECT_TIC4X,
511
2.06k
              EXTRU (instruction, 15, 8)))
512
0
      return 0;
513
2.06k
    break;
514
515
3.99k
  case 'P': /* Displacement 0--15 (used by Bcond and BcondD).  */
516
3.99k
    tic4x_print_relative (info, pc, EXTRS (instruction, 15, 0),
517
3.99k
        p->opcode);
518
3.99k
    break;
519
520
5.79k
  case 'Q': /* Register 0--15.  */
521
27.8k
        case 'q':
522
27.8k
    if (! tic4x_print_register (info, EXTRU (instruction, 15, 0)))
523
11.3k
      return 0;
524
16.5k
    break;
525
526
16.5k
  case 'R': /* Register 16--20.  */
527
36.7k
        case 'r':
528
36.7k
    if (! tic4x_print_register (info, EXTRU (instruction, 20, 16)))
529
304
      return 0;
530
36.4k
    break;
531
532
36.4k
  case 'S': /* 16-bit signed immediate 0--15.  */
533
3.59k
    tic4x_print_immed (info, IMMED_SINT,
534
3.59k
           EXTRS (instruction, 15, 0));
535
3.59k
    break;
536
537
185
  case 'T': /* 5-bit signed immediate 16--20  (C4x stik).  */
538
185
    if (! IS_CPU_TIC4X (tic4x_version))
539
0
      return 0;
540
185
    if (! tic4x_print_immed (info, IMMED_SUINT,
541
185
           EXTRU (instruction, 20, 16)))
542
0
      return 0;
543
185
    break;
544
545
658
  case 'U': /* 16-bit unsigned int immediate 0--15.  */
546
658
    tic4x_print_immed (info, IMMED_SUINT, EXTRU (instruction, 15, 0));
547
658
    break;
548
549
234
  case 'V': /* 5/9-bit unsigned vector 0--4/8.  */
550
234
    tic4x_print_immed (info, IMMED_SUINT,
551
234
           IS_CPU_TIC4X (tic4x_version) ?
552
212
           EXTRU (instruction, 8, 0) :
553
234
           EXTRU (instruction, 4, 0) & ~0x20);
554
234
    break;
555
556
855
  case 'W': /* 8-bit signed immediate 0--7.  */
557
855
    if (! IS_CPU_TIC4X (tic4x_version))
558
0
      return 0;
559
855
    tic4x_print_immed (info, IMMED_SINT, EXTRS (instruction, 7, 0));
560
855
    break;
561
562
202
  case 'X': /* Expansion register 4--0.  */
563
202
    val = EXTRU (instruction, 4, 0) + REG_IVTP;
564
202
    if (val < REG_IVTP || val > REG_TVTP)
565
54
      return 0;
566
148
    if (! tic4x_print_register (info, val))
567
0
      return 0;
568
148
    break;
569
570
148
  case 'Y': /* Address register 16--20.  */
571
135
    val = EXTRU (instruction, 20, 16);
572
135
    if (val < REG_AR0 || val > REG_SP)
573
43
      return 0;
574
92
    if (! tic4x_print_register (info, val))
575
0
      return 0;
576
92
    break;
577
578
92
  case 'Z': /* Expansion register 16--20.  */
579
5
    val = EXTRU (instruction, 20, 16) + REG_IVTP;
580
5
    if (val < REG_IVTP || val > REG_TVTP)
581
5
      return 0;
582
0
    if (! tic4x_print_register (info, val))
583
0
      return 0;
584
0
    break;
585
586
22.7k
  case '|': /* Parallel instruction.  */
587
22.7k
    tic4x_print_str (info, " || ");
588
22.7k
    tic4x_print_str (info, parallel);
589
22.7k
    tic4x_print_char (info, ' ');
590
22.7k
    break;
591
592
63.7k
  case ';':
593
63.7k
    tic4x_print_char (info, ',');
594
63.7k
    break;
595
596
48.4k
  default:
597
48.4k
    tic4x_print_char (info, *s);
598
48.4k
    break;
599
359k
  }
600
335k
      s++;
601
335k
    }
602
66.0k
  return 1;
603
89.8k
}
604
605
static void
606
tic4x_hash_opcode_special (tic4x_inst_t **optable_special,
607
         const tic4x_inst_t *inst)
608
702
{
609
702
  int i;
610
611
5.14k
  for (i = 0;i < TIC4X_SPESOP_SIZE; i++)
612
4.68k
    if (optable_special[i] != NULL
613
4.68k
        && optable_special[i]->opcode == inst->opcode)
614
234
      {
615
        /* Collision (we have it already) - overwrite.  */
616
234
        optable_special[i] = (tic4x_inst_t *) inst;
617
234
        return;
618
234
      }
619
620
1.17k
  for (i = 0; i < TIC4X_SPESOP_SIZE; i++)
621
1.17k
    if (optable_special[i] == NULL)
622
468
      {
623
        /* Add the new opcode.  */
624
468
        optable_special[i] = (tic4x_inst_t *) inst;
625
468
        return;
626
468
      }
627
628
  /* This should never occur. This happens if the number of special
629
     instructions exceeds TIC4X_SPESOP_SIZE. Please increase the variable
630
     of this variable */
631
#if TIC4X_DEBUG
632
  printf ("optable_special[] is full, please increase TIC4X_SPESOP_SIZE!\n");
633
#endif
634
468
}
635
636
static void
637
tic4x_hash_opcode (tic4x_inst_t **optable,
638
       tic4x_inst_t **optable_special,
639
       const tic4x_inst_t *inst,
640
       const unsigned long tic4x_oplevel)
641
119k
{
642
119k
  unsigned int j;
643
119k
  unsigned int opcode = inst->opcode >> (32 - TIC4X_HASH_SIZE);
644
119k
  unsigned int opmask = inst->opmask >> (32 - TIC4X_HASH_SIZE);
645
646
  /* Use a TIC4X_HASH_SIZE bit index as a hash index.  We should
647
     have unique entries so there's no point having a linked list
648
     for each entry?  */
649
156M
  for (j = opcode; j < opmask; j++)
650
156M
    if ((j & opmask) == opcode
651
156M
         && inst->oplevel & tic4x_oplevel)
652
486k
      {
653
#if TIC4X_DEBUG
654
  /* We should only have collisions for synonyms like
655
     ldp for ldi.  */
656
  if (optable[j] != NULL)
657
    printf ("Collision at index %d, %s and %s\n",
658
      j, optable[j]->name, inst->name);
659
#endif
660
        /* Catch those ops that collide with others already inside the
661
           hash, and have a opmask greater than the one we use in the
662
           hash. Store them in a special-list, that will handle full
663
           32-bit INSN, not only the first 11-bit (or so). */
664
486k
        if (optable[j] != NULL
665
486k
      && inst->opmask & ~(opmask << (32 - TIC4X_HASH_SIZE)))
666
351
          {
667
            /* Add the instruction already on the list.  */
668
351
            tic4x_hash_opcode_special (optable_special, optable[j]);
669
670
            /* Add the new instruction.  */
671
351
            tic4x_hash_opcode_special (optable_special, inst);
672
351
          }
673
674
486k
        optable[j] = (tic4x_inst_t *) inst;
675
486k
      }
676
119k
}
677
678
/* Disassemble the instruction in 'instruction'.
679
   'pc' should be the address of this instruction, it will
680
   be used to print the target address if this is a relative jump or call
681
   the disassembled instruction is written to 'info'.
682
   The function returns the length of this instruction in words.  */
683
684
static int
685
tic4x_disassemble (unsigned long pc,
686
       unsigned long instruction,
687
       struct disassemble_info *info)
688
85.5k
{
689
85.5k
  tic4x_inst_t *p;
690
85.5k
  int i;
691
85.5k
  unsigned long tic4x_oplevel;
692
693
85.5k
  if (tic4x_version != info->mach)
694
116
    {
695
116
      tic4x_version = info->mach;
696
      /* Don't stash anything from a previous call using a different
697
   machine.  */
698
116
      free (optab);
699
116
      optab = NULL;
700
116
      free (optab_special);
701
116
      optab_special = NULL;
702
116
      registernames[REG_R0] = NULL;
703
116
    }
704
705
85.5k
  tic4x_oplevel  = (IS_CPU_TIC4X (tic4x_version)) ? OP_C4X : 0;
706
85.5k
  tic4x_oplevel |= OP_C3X | OP_LPWR | OP_IDLE2 | OP_ENH;
707
708
85.5k
  if (optab == NULL)
709
117
    {
710
117
      optab = xcalloc ((1 << TIC4X_HASH_SIZE), sizeof (tic4x_inst_t *));
711
712
117
      optab_special = xcalloc (TIC4X_SPESOP_SIZE, sizeof (tic4x_inst_t *));
713
714
      /* Install opcodes in reverse order so that preferred
715
   forms overwrite synonyms.  */
716
119k
      for (i = tic4x_num_insts - 1; i >= 0; i--)
717
119k
  tic4x_hash_opcode (optab, optab_special, &tic4x_insts[i],
718
119k
         tic4x_oplevel);
719
720
      /* We now need to remove the insn that are special from the
721
   "normal" optable, to make the disasm search this extra list
722
   for them.  */
723
1.05k
      for (i = 0; i < TIC4X_SPESOP_SIZE; i++)
724
936
  if (optab_special[i] != NULL)
725
468
    optab[optab_special[i]->opcode >> (32 - TIC4X_HASH_SIZE)] = NULL;
726
117
    }
727
728
  /* See if we can pick up any loading of the DP register...  */
729
85.5k
  if ((instruction >> 16) == 0x5070 || (instruction >> 16) == 0x1f70)
730
16
    tic4x_dp = EXTRU (instruction, 15, 0);
731
732
85.5k
  p = optab[instruction >> (32 - TIC4X_HASH_SIZE)];
733
85.5k
  if (p != NULL)
734
59.8k
    {
735
59.8k
      if (((instruction & p->opmask) == p->opcode)
736
59.8k
    && tic4x_print_op (NULL, instruction, p, pc))
737
33.0k
  tic4x_print_op (info, instruction, p, pc);
738
26.7k
      else
739
26.7k
  (*info->fprintf_func) (info->stream, "%08lx", instruction);
740
59.8k
    }
741
25.7k
  else
742
25.7k
    {
743
231k
      for (i = 0; i<TIC4X_SPESOP_SIZE; i++)
744
205k
  if (optab_special[i] != NULL
745
205k
      && optab_special[i]->opcode == instruction)
746
59
    {
747
59
      (*info->fprintf_func)(info->stream, "%s", optab_special[i]->name);
748
59
      break;
749
59
    }
750
25.7k
      if (i == TIC4X_SPESOP_SIZE)
751
25.6k
  (*info->fprintf_func) (info->stream, "%08lx", instruction);
752
25.7k
    }
753
754
  /* Return size of insn in words.  */
755
85.5k
  return 1;
756
85.5k
}
757
758
/* The entry point from objdump and gdb.  */
759
int
760
print_insn_tic4x (bfd_vma memaddr, struct disassemble_info *info)
761
85.7k
{
762
85.7k
  int status;
763
85.7k
  unsigned long pc;
764
85.7k
  unsigned long op;
765
85.7k
  bfd_byte buffer[4];
766
767
85.7k
  status = (*info->read_memory_func) (memaddr, buffer, 4, info);
768
85.7k
  if (status != 0)
769
147
    {
770
147
      (*info->memory_error_func) (status, memaddr, info);
771
147
      return -1;
772
147
    }
773
774
85.5k
  pc = memaddr;
775
85.5k
  op = bfd_getl32 (buffer);
776
85.5k
  info->bytes_per_line = 4;
777
85.5k
  info->bytes_per_chunk = 4;
778
85.5k
  info->octets_per_byte = 4;
779
85.5k
  info->display_endian = BFD_ENDIAN_LITTLE;
780
85.5k
  return tic4x_disassemble (pc, op, info) * 4;
781
85.7k
}