/* V850-specific support for 32-bit ELF

   Copyright (C) 1996-2025 Free Software Foundation, Inc.

   This file is part of BFD, the Binary File Descriptor library.

   This program is free software; you can redistribute it and/or modify

   it under the terms of the GNU General Public License as published by

   the Free Software Foundation; either version 3 of the License, or

   (at your option) any later version.

   This program is distributed in the hope that it will be useful,

   but WITHOUT ANY WARRANTY; without even the implied warranty of

   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License

   along with this program; if not, write to the Free Software

   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,

   MA 02110-1301, USA.  */

/* XXX FIXME: This code is littered with 32bit int, 16bit short, 8bit char

   dependencies.  As is the gas & simulator code for the v850.  */

#include "sysdep.h"

#include "bfd.h"

#include "bfdlink.h"

#include "libbfd.h"

#include "elf-bfd.h"

#include "elf/v850.h"

#include "libiberty.h"

#include "elf32-v850.h"

/* Sign-extend a 17-bit number.  */

#define SEXT17(x) ((((x) & 0x1ffff) ^ 0x10000) - 0x10000)

/* Sign-extend a 22-bit number.  */

#define SEXT22(x) ((((x) & 0x3fffff) ^ 0x200000) - 0x200000)

static reloc_howto_type v850_elf_howto_table[];

/* Look through the relocs for a section during the first phase, and

   allocate space in the global offset table or procedure linkage

   table.  */

static bool

v850_elf_check_relocs (bfd *abfd,

           struct bfd_link_info *info,

           asection *sec,

           const Elf_Internal_Rela *relocs)

{

  bool ret = true;

  Elf_Internal_Shdr *symtab_hdr;

  struct elf_link_hash_entry **sym_hashes;

  const Elf_Internal_Rela *rel;

  const Elf_Internal_Rela *rel_end;

  unsigned int r_type;

  int other = 0;

  const char *common = NULL;

  if (bfd_link_relocatable (info))

    return true;

#ifdef DEBUG

  _bfd_error_handler ("v850_elf_check_relocs called for section %pA in %pB",

          sec, abfd);

#endif

  symtab_hdr = &elf_tdata (abfd)->symtab_hdr;

  sym_hashes = elf_sym_hashes (abfd);

  rel_end = relocs + sec->reloc_count;

  for (rel = relocs; rel < rel_end; rel++)

    {

      unsigned long r_symndx;

      struct elf_link_hash_entry *h;

      r_symndx = ELF32_R_SYM (rel->r_info);

      if (r_symndx < symtab_hdr->sh_info)

  h = NULL;

      else

  {

    h = sym_hashes[r_symndx - symtab_hdr->sh_info];

    while (h->root.type == bfd_link_hash_indirect

     || h->root.type == bfd_link_hash_warning)

      h = (struct elf_link_hash_entry *) h->root.u.i.link;

  }

      r_type = ELF32_R_TYPE (rel->r_info);

      switch (r_type)

  {

  default:

    break;

  /* This relocation describes the C++ object vtable hierarchy.

     Reconstruct it for later use during GC.  */

  case R_V850_GNU_VTINHERIT:

    if (!bfd_elf_gc_record_vtinherit (abfd, sec, h, rel->r_offset))

      return false;

    break;

  /* This relocation describes which C++ vtable entries

     are actually used.  Record for later use during GC.  */

  case R_V850_GNU_VTENTRY:

    if (!bfd_elf_gc_record_vtentry (abfd, sec, h, rel->r_addend))

      return false;

    break;

  case R_V850_SDA_16_16_SPLIT_OFFSET:

  case R_V850_SDA_16_16_OFFSET:

  case R_V850_SDA_15_16_OFFSET:

  case R_V810_GPWLO_1:

  case R_V850_HWLO:

  case R_V850_HWLO_1:

    other = V850_OTHER_SDA;

    common = ".scommon";

    goto small_data_common;

  case R_V850_ZDA_16_16_SPLIT_OFFSET:

  case R_V850_ZDA_16_16_OFFSET:

  case R_V850_ZDA_15_16_OFFSET:

    other = V850_OTHER_ZDA;

    common = ".zcommon";

    goto small_data_common;

  case R_V850_TDA_4_4_OFFSET:

  case R_V850_TDA_4_5_OFFSET:

  case R_V850_TDA_7_7_OFFSET:

  case R_V850_TDA_6_8_OFFSET:

  case R_V850_TDA_7_8_OFFSET:

  case R_V850_TDA_16_16_OFFSET:

    other = V850_OTHER_TDA;

    common = ".tcommon";

    /* fall through */

#define V850_OTHER_MASK (V850_OTHER_TDA | V850_OTHER_SDA | V850_OTHER_ZDA)

  small_data_common:

    if (h)

      {

        /* Flag which type of relocation was used.  */

        h->other |= other;

        if ((h->other & V850_OTHER_MASK) != (other & V850_OTHER_MASK)

      && (h->other & V850_OTHER_ERROR) == 0)

    {

      const char * msg;

      char *buff;

      switch (h->other & V850_OTHER_MASK)

        {

        default:

          msg = _("variable `%s' cannot occupy in multiple small data regions");

          break;

        case V850_OTHER_SDA | V850_OTHER_ZDA | V850_OTHER_TDA:

          msg = _("variable `%s' can only be in one of the small, zero, and tiny data regions");

          break;

        case V850_OTHER_SDA | V850_OTHER_ZDA:

          msg = _("variable `%s' cannot be in both small and zero data regions simultaneously");

          break;

        case V850_OTHER_SDA | V850_OTHER_TDA:

          msg = _("variable `%s' cannot be in both small and tiny data regions simultaneously");

          break;

        case V850_OTHER_ZDA | V850_OTHER_TDA:

          msg = _("variable `%s' cannot be in both zero and tiny data regions simultaneously");

          break;

        }

      if (asprintf (&buff, msg, h->root.root.string) < 0)

        buff = NULL;

      else

        msg = buff;

      info->callbacks->warning (info, msg, h->root.root.string,

              abfd, h->root.u.def.section,

              (bfd_vma) 0);

      free (buff);

      bfd_set_error (bfd_error_bad_value);

      h->other |= V850_OTHER_ERROR;

      ret = false;

    }

      }

    if (h && h->root.type == bfd_link_hash_common

        && h->root.u.c.p

        && !strcmp (bfd_section_name (h->root.u.c.p->section), "COMMON"))

      {

        asection * section;

        section = h->root.u.c.p->section = bfd_make_section_old_way (abfd, common);

        section->flags |= SEC_IS_COMMON | SEC_SMALL_DATA;

      }

#ifdef DEBUG

    fprintf (stderr, "v850_elf_check_relocs, found %s relocation for %s%s\n",

       v850_elf_howto_table[ (int)r_type ].name,

       (h && h->root.root.string) ? h->root.root.string : "<unknown>",

       (h->root.type == bfd_link_hash_common) ? ", symbol is common" : "");

#endif

    break;

  }

    }

  return ret;

}

/* In the old version, when an entry was checked out from the table,

   it was deleted.  This produced an error if the entry was needed

   more than once, as the second attempted retry failed.

   In the current version, the entry is not deleted, instead we set

   the field 'found' to TRUE.  If a second lookup matches the same

   entry, then we know that the hi16s reloc has already been updated

   and does not need to be updated a second time.

   TODO - TOFIX: If it is possible that we need to restore 2 different

   addresses from the same table entry, where the first generates an

   overflow, whilst the second do not, then this code will fail.  */

typedef struct hi16s_location

{

  bfd_vma addend;

  bfd_byte *address;

  unsigned long counter;

  bool found;

  struct hi16s_location *next;

}

hi16s_location;

static hi16s_location * previous_hi16s;

static hi16s_location * free_hi16s;

static unsigned long    hi16s_counter;

static void

remember_hi16s_reloc (bfd *abfd, bfd_vma addend, bfd_byte *address)

{

  hi16s_location * entry = NULL;

  size_t amt = sizeof (* free_hi16s);

  /* Find a free structure.  */

  if (free_hi16s == NULL)

    free_hi16s = bfd_zalloc (abfd, amt);

  entry      = free_hi16s;

  free_hi16s = free_hi16s->next;

  entry->addend  = addend;

  entry->address = address;

  entry->counter = hi16s_counter ++;

  entry->found   = false;

  entry->next    = previous_hi16s;

  previous_hi16s = entry;

  /* Cope with wrap around of our counter.  */

  if (hi16s_counter == 0)

    {

      /* XXX: Assume that all counter entries differ only in their low 16 bits.  */

      for (entry = previous_hi16s; entry != NULL; entry = entry->next)

  entry->counter &= 0xffff;

      hi16s_counter = 0x10000;

    }

}

static bfd_byte *

find_remembered_hi16s_reloc (bfd_vma addend, bool *already_found)

{

  hi16s_location *match = NULL;

  hi16s_location *entry;

  bfd_byte *addr;

  /* Search the table.  Record the most recent entry that matches.  */

  for (entry = previous_hi16s; entry; entry = entry->next)

    {

      if (entry->addend == addend

    && (match == NULL || match->counter < entry->counter))

  {

    match    = entry;

  }

    }

  if (match == NULL)

    return NULL;

  /* Extract the address.  */

  addr = match->address;

  /* Remember if this entry has already been used before.  */

  if (already_found)

    * already_found = match->found;

  /* Note that this entry has now been used.  */

  match->found = true;

  return addr;

}

/* Calculate the final operand value for a R_V850_LO16 or

   R_V850_LO16_SPLIT_OFFSET.  *INSN is the current operand value and

   ADDEND is the sum of the relocation symbol and offset.  Store the

   operand value in *INSN and return true on success.

   The assembler has already done some of this: If the value stored in

   the instruction has its 15th bit set, (counting from zero) then the

   assembler will have added 1 to the value stored in the associated

   HI16S reloc.  So for example, these relocations:

       movhi hi( fred ), r0, r1

       movea lo( fred ), r1, r1

   will store 0 in the value fields for the MOVHI and MOVEA instructions

   and addend will be the address of fred, but for these instructions:

       movhi hi( fred + 0x123456 ), r0, r1

       movea lo( fred + 0x123456 ), r1, r1

   the value stored in the MOVHI instruction will be 0x12 and the value

   stored in the MOVEA instruction will be 0x3456.  If however the

   instructions were:

       movhi hi( fred + 0x10ffff ), r0, r1

       movea lo( fred + 0x10ffff ), r1, r1

   then the value stored in the MOVHI instruction would be 0x11 (not

   0x10) and the value stored in the MOVEA instruction would be 0xffff.

   Thus (assuming for the moment that the addend is 0), at run time the

   MOVHI instruction loads 0x110000 into r1, then the MOVEA instruction

   adds 0xffffffff (sign extension!) producing 0x10ffff.  Similarly if

   the instructions were:

       movhi hi( fred - 1 ), r0, r1

       movea lo( fred - 1 ), r1, r1

   then 0 is stored in the MOVHI instruction and -1 is stored in the

   MOVEA instruction.

   Overflow can occur if the addition of the value stored in the

   instruction plus the addend sets the 15th bit when before it was clear.

   This is because the 15th bit will be sign extended into the high part,

   thus reducing its value by one, but since the 15th bit was originally

   clear, the assembler will not have added 1 to the previous HI16S reloc

   to compensate for this effect.  For example:

      movhi hi( fred + 0x123456 ), r0, r1

      movea lo( fred + 0x123456 ), r1, r1

   The value stored in HI16S reloc is 0x12, the value stored in the LO16

   reloc is 0x3456.  If we assume that the address of fred is 0x00007000

   then the relocations become:

     HI16S: 0x0012 + (0x00007000 >> 16)    = 0x12

     LO16:  0x3456 + (0x00007000 & 0xffff) = 0xa456

   but when the instructions are executed, the MOVEA instruction's value

   is signed extended, so the sum becomes:

  0x00120000

      + 0xffffa456

      ------------

  0x0011a456    but 'fred + 0x123456' = 0x0012a456

   Note that if the 15th bit was set in the value stored in the LO16

   reloc, then we do not have to do anything:

      movhi hi( fred + 0x10ffff ), r0, r1

      movea lo( fred + 0x10ffff ), r1, r1

      HI16S:  0x0011 + (0x00007000 >> 16)    = 0x11

      LO16:   0xffff + (0x00007000 & 0xffff) = 0x6fff

  0x00110000

      + 0x00006fff

      ------------

  0x00116fff  = fred + 0x10ffff = 0x7000 + 0x10ffff

   Overflow can also occur if the computation carries into the 16th bit

   and it also results in the 15th bit having the same value as the 15th

   bit of the original value.   What happens is that the HI16S reloc

   will have already examined the 15th bit of the original value and

   added 1 to the high part if the bit is set.  This compensates for the

   sign extension of 15th bit of the result of the computation.  But now

   there is a carry into the 16th bit, and this has not been allowed for.

   So, for example if fred is at address 0xf000:

     movhi hi( fred + 0xffff ), r0, r1    [bit 15 of the offset is set]

     movea lo( fred + 0xffff ), r1, r1

     HI16S: 0x0001 + (0x0000f000 >> 16)    = 0x0001

     LO16:  0xffff + (0x0000f000 & 0xffff) = 0xefff   (carry into bit 16 is lost)

       0x00010000

     + 0xffffefff

     ------------

       0x0000efff   but 'fred + 0xffff' = 0x0001efff

   Similarly, if the 15th bit remains clear, but overflow occurs into

   the 16th bit then (assuming the address of fred is 0xf000):

     movhi hi( fred + 0x7000 ), r0, r1    [bit 15 of the offset is clear]

     movea lo( fred + 0x7000 ), r1, r1

     HI16S: 0x0000 + (0x0000f000 >> 16)    = 0x0000

     LO16:  0x7000 + (0x0000f000 & 0xffff) = 0x6fff  (carry into bit 16 is lost)

       0x00000000

     + 0x00006fff

     ------------

       0x00006fff   but 'fred + 0x7000' = 0x00016fff

   Note - there is no need to change anything if a carry occurs, and the

   15th bit changes its value from being set to being clear, as the HI16S

   reloc will have already added in 1 to the high part for us:

     movhi hi( fred + 0xffff ), r0, r1     [bit 15 of the offset is set]

     movea lo( fred + 0xffff ), r1, r1

     HI16S: 0x0001 + (0x00007000 >> 16)

     LO16:  0xffff + (0x00007000 & 0xffff) = 0x6fff  (carry into bit 16 is lost)

       0x00010000

     + 0x00006fff   (bit 15 not set, so the top half is zero)

     ------------

       0x00016fff   which is right (assuming that fred is at 0x7000)

   but if the 15th bit goes from being clear to being set, then we must

   once again handle overflow:

     movhi hi( fred + 0x7000 ), r0, r1     [bit 15 of the offset is clear]

     movea lo( fred + 0x7000 ), r1, r1

     HI16S: 0x0000 + (0x0000ffff >> 16)

     LO16:  0x7000 + (0x0000ffff & 0xffff) = 0x6fff  (carry into bit 16)

       0x00000000

     + 0x00006fff   (bit 15 not set, so the top half is zero)

     ------------

       0x00006fff   which is wrong (assuming that fred is at 0xffff).  */

static bool

v850_elf_perform_lo16_relocation (bfd *abfd, unsigned long *insn,

          unsigned long addend)

{

#define BIT15_SET(x) ((x) & 0x8000)

#define OVERFLOWS(a,i) ((((a) & 0xffff) + (i)) > 0xffff)

  if ((BIT15_SET (*insn + addend) && ! BIT15_SET (addend))

      || (OVERFLOWS (addend, *insn)

    && ((! BIT15_SET (*insn)) || (BIT15_SET (addend)))))

    {

      bool already_updated;

      bfd_byte *hi16s_address = find_remembered_hi16s_reloc

  (addend, & already_updated);

      /* Amend the matching HI16_S relocation.  */

      if (hi16s_address != NULL)

  {

    if (! already_updated)

      {

        unsigned long hi_insn = bfd_get_16 (abfd, hi16s_address);

        hi_insn += 1;

        bfd_put_16 (abfd, hi_insn, hi16s_address);

      }

  }

      else

  {

    _bfd_error_handler (_("failed to find previous HI16 reloc"));

    return false;

  }

    }

#undef OVERFLOWS

#undef BIT15_SET

  /* Do not complain if value has top bit set, as this has been

     anticipated.  */

  *insn = (*insn + addend) & 0xffff;

  return true;

}

/* FIXME:  The code here probably ought to be removed and the code in reloc.c

   allowed to do its stuff instead.  At least for most of the relocs, anyway.  */

static bfd_reloc_status_type

v850_elf_perform_relocation (bfd *abfd,

           unsigned int r_type,

           bfd_vma addend,

           bfd_byte *address)

{

  unsigned long insn;

  unsigned long result;

  bfd_signed_vma saddend = (bfd_signed_vma) addend;

  switch (r_type)

    {

    default:

#ifdef DEBUG

      _bfd_error_handler ("%pB: unsupported relocation type %#x",

        abfd, r_type);

#endif

      return bfd_reloc_notsupported;

    case R_V850_REL32:

    case R_V850_ABS32:

    case R_V810_WORD:

    case R_V850_PC32:

      bfd_put_32 (abfd, addend, address);

      return bfd_reloc_ok;

    case R_V850_WLO23:

    case R_V850_23:

      insn  = bfd_get_32 (abfd, address);

      insn &= ~((0x7f << 4) | (0x7fff80 << (16-7)));

      insn |= ((addend & 0x7f) << 4) | ((addend & 0x7fff80) << (16-7));

      bfd_put_32 (abfd, (bfd_vma) insn, address);

      return bfd_reloc_ok;

    case R_V850_PCR22:

    case R_V850_22_PCREL:

      if (saddend > 0x1fffff || saddend < -0x200000)

  return bfd_reloc_overflow;

      if ((addend % 2) != 0)

  return bfd_reloc_dangerous;

      insn  = bfd_get_32 (abfd, address);

      insn &= ~0xfffe003f;

      insn |= (((addend & 0xfffe) << 16) | ((addend & 0x3f0000) >> 16));

      bfd_put_32 (abfd, (bfd_vma) insn, address);

      return bfd_reloc_ok;

    case R_V850_PC17:

    case R_V850_17_PCREL:

      if (saddend > 0xffff || saddend < -0x10000)

  return bfd_reloc_overflow;

      if ((addend % 2) != 0)

  return bfd_reloc_dangerous;

      insn  = bfd_get_32 (abfd, address);

      insn &= ~ 0xfffe0010;

      insn |= ((addend & 0xfffe) << 16) | ((addend & 0x10000) >> (16-4));

      break;

    case R_V850_PC16U:

    case R_V850_16_PCREL:

      if ((saddend < -0xffff) || (saddend > 0))

  return bfd_reloc_overflow;

      if ((addend % 2) != 0)

  return bfd_reloc_dangerous;

      insn  = bfd_get_16 (abfd, address);

      insn &= ~0xfffe;

      insn |= (-addend & 0xfffe);

      break;

    case R_V850_PC9:

    case R_V850_9_PCREL:

      if (saddend > 0xff || saddend < -0x100)

  return bfd_reloc_overflow;

      if ((addend % 2) != 0)

  return bfd_reloc_dangerous;

      insn  = bfd_get_16 (abfd, address);

      insn &= ~ 0xf870;

      insn |= ((addend & 0x1f0) << 7) | ((addend & 0x0e) << 3);

      break;

    case R_V810_WHI:

    case R_V850_HI16:

      addend += (bfd_get_16 (abfd, address) << 16);

      addend = (addend >> 16);

      insn = addend;

      break;

    case R_V810_WHI1:

    case R_V850_HI16_S:

      /* Remember where this relocation took place.  */

      remember_hi16s_reloc (abfd, addend, address);

      addend += (bfd_get_16 (abfd, address) << 16);

      addend = (addend >> 16) + ((addend & 0x8000) != 0);

      /* This relocation cannot overflow.  */

      if (addend > 0xffff)

  addend = 0;

      insn = addend;

      break;

    case R_V810_WLO:

    case R_V850_LO16:

      insn = bfd_get_16 (abfd, address);

      if (! v850_elf_perform_lo16_relocation (abfd, &insn, addend))

  return bfd_reloc_overflow;

      break;

    case R_V810_BYTE:

    case R_V850_8:

      addend += (char) bfd_get_8 (abfd, address);

      saddend = (bfd_signed_vma) addend;

      if (saddend > 0x7f || saddend < -0x80)

  return bfd_reloc_overflow;

      bfd_put_8 (abfd, addend, address);

      return bfd_reloc_ok;

    case R_V850_CALLT_16_16_OFFSET:

      addend += bfd_get_16 (abfd, address);

      saddend = (bfd_signed_vma) addend;

      if (saddend > 0xffff || saddend < 0)

  return bfd_reloc_overflow;

      insn = addend;

      break;

    case R_V850_CALLT_15_16_OFFSET:

      insn = bfd_get_16 (abfd, address);

      addend += insn & 0xfffe;

      saddend = (bfd_signed_vma) addend;

      if (saddend > 0xffff || saddend < 0)

  return bfd_reloc_overflow;

      insn = (0xfffe & addend)

  | (insn & ~0xfffe);

      break;

    case R_V850_CALLT_6_7_OFFSET:

      insn = bfd_get_16 (abfd, address);

      addend += ((insn & 0x3f) << 1);

      saddend = (bfd_signed_vma) addend;

      if (saddend > 0x7e || saddend < 0)

  return bfd_reloc_overflow;

      if (addend & 1)

  return bfd_reloc_dangerous;

      insn &= 0xff80;

      insn |= (addend >> 1);

      break;

    case R_V850_16:

    case R_V810_HWORD:

    case R_V850_SDA_16_16_OFFSET:

    case R_V850_ZDA_16_16_OFFSET:

    case R_V850_TDA_16_16_OFFSET:

      addend += bfd_get_16 (abfd, address);

      saddend = (bfd_signed_vma) addend;

      if (saddend > 0x7fff || saddend < -0x8000)

  return bfd_reloc_overflow;

      insn = addend;

      break;

    case R_V850_16_S1:

    case R_V850_SDA_15_16_OFFSET:

    case R_V850_ZDA_15_16_OFFSET:

    case R_V810_GPWLO_1:

      insn = bfd_get_16 (abfd, address);

      addend += (insn & 0xfffe);

      saddend = (bfd_signed_vma) addend;

      if (saddend > 0x7ffe || saddend < -0x8000)

  return bfd_reloc_overflow;

      if (addend & 1)

  return bfd_reloc_dangerous;

      insn = (addend &~ (bfd_vma) 1) | (insn & 1);

      break;

    case R_V850_TDA_6_8_OFFSET:

      insn = bfd_get_16 (abfd, address);

      addend += ((insn & 0x7e) << 1);

      saddend = (bfd_signed_vma) addend;

      if (saddend > 0xfc || saddend < 0)

  return bfd_reloc_overflow;

      if (addend & 3)

  return bfd_reloc_dangerous;

      insn &= 0xff81;

      insn |= (addend >> 1);

      break;

    case R_V850_TDA_7_8_OFFSET:

      insn = bfd_get_16 (abfd, address);

      addend += ((insn & 0x7f) << 1);

      saddend = (bfd_signed_vma) addend;

      if (saddend > 0xfe || saddend < 0)

  return bfd_reloc_overflow;

      if (addend & 1)

  return bfd_reloc_dangerous;

      insn &= 0xff80;

      insn |= (addend >> 1);

      break;

    case R_V850_TDA_7_7_OFFSET:

      insn = bfd_get_16 (abfd, address);

      addend += insn & 0x7f;

      saddend = (bfd_signed_vma) addend;

      if (saddend > 0x7f || saddend < 0)

  return bfd_reloc_overflow;

      insn &= 0xff80;

      insn |= addend;

      break;

    case R_V850_TDA_4_5_OFFSET:

      insn = bfd_get_16 (abfd, address);

      addend += ((insn & 0xf) << 1);

      saddend = (bfd_signed_vma) addend;

      if (saddend > 0x1e || saddend < 0)

  return bfd_reloc_overflow;

      if (addend & 1)

  return bfd_reloc_dangerous;

      insn &= 0xfff0;

      insn |= (addend >> 1);

      break;

    case R_V850_TDA_4_4_OFFSET:

      insn = bfd_get_16 (abfd, address);

      addend += insn & 0xf;

      saddend = (bfd_signed_vma) addend;

      if (saddend > 0xf || saddend < 0)

  return bfd_reloc_overflow;

      insn &= 0xfff0;

      insn |= addend;

      break;

    case R_V810_WLO_1:

    case R_V850_HWLO:

    case R_V850_HWLO_1:

    case R_V850_LO16_S1:

      insn = bfd_get_16 (abfd, address);

      result = insn & 0xfffe;

      if (! v850_elf_perform_lo16_relocation (abfd, &result, addend))

  return bfd_reloc_overflow;

      if (result & 1)

  return bfd_reloc_overflow;

      insn = (result & 0xfffe)

  | (insn & ~0xfffe);

  bfd_put_16 (abfd, insn, address);

      return bfd_reloc_ok;

    case R_V850_BLO:

    case R_V850_LO16_SPLIT_OFFSET:

      insn = bfd_get_32 (abfd, address);

      result = ((insn & 0xfffe0000) >> 16) | ((insn & 0x20) >> 5);

      if (! v850_elf_perform_lo16_relocation (abfd, &result, addend))

  return bfd_reloc_overflow;

      insn = (((result << 16) & 0xfffe0000)

        | ((result << 5) & 0x20)

        | (insn & ~0xfffe0020));

      bfd_put_32 (abfd, insn, address);

      return bfd_reloc_ok;

    case R_V850_16_SPLIT_OFFSET:

    case R_V850_SDA_16_16_SPLIT_OFFSET:

    case R_V850_ZDA_16_16_SPLIT_OFFSET:

      insn = bfd_get_32 (abfd, address);

      addend += ((insn & 0xfffe0000) >> 16) + ((insn & 0x20) >> 5);

      saddend = (bfd_signed_vma) addend;

      if (saddend > 0x7fff || saddend < -0x8000)

  return bfd_reloc_overflow;

      insn &= 0x0001ffdf;

      insn |= (addend & 1) << 5;

      insn |= (addend &~ (bfd_vma) 1) << 16;

      bfd_put_32 (abfd, (bfd_vma) insn, address);

      return bfd_reloc_ok;

    case R_V850_GNU_VTINHERIT:

    case R_V850_GNU_VTENTRY:

      return bfd_reloc_ok;

    }

  bfd_put_16 (abfd, (bfd_vma) insn, address);

  return bfd_reloc_ok;

}

/* Insert the addend into the instruction.  */

static bfd_reloc_status_type

v850_elf_reloc (bfd *abfd ATTRIBUTE_UNUSED,

    arelent *reloc,

    asymbol *symbol,

    void * data ATTRIBUTE_UNUSED,

    asection *isection,

    bfd *obfd,

    char **err ATTRIBUTE_UNUSED)

{

  long relocation;

  /* If there is an output BFD,

     and the symbol is not a section name (which is only defined at final link time),

     and either we are not putting the addend into the instruction

      or the addend is zero, so there is nothing to add into the instruction

     then just fixup the address and return.  */

  if (obfd != NULL

      && (symbol->flags & BSF_SECTION_SYM) == 0

      && (! reloc->howto->partial_inplace

    || reloc->addend == 0))

    {

      reloc->address += isection->output_offset;

      return bfd_reloc_ok;

    }

  /* Catch relocs involving undefined symbols.  */

  if (bfd_is_und_section (symbol->section)

      && (symbol->flags & BSF_WEAK) == 0

      && obfd == NULL)

    return bfd_reloc_undefined;

  /* We handle final linking of some relocs ourselves.  */

  /* Is the address of the relocation really within the section?  */

  if (reloc->address > bfd_get_section_limit (abfd, isection))

    return bfd_reloc_outofrange;

  /* Work out which section the relocation is targeted at and the

     initial relocation command value.  */

  if (reloc->howto->pc_relative)

    return bfd_reloc_ok;

  /* Get symbol value.  (Common symbols are special.)  */

  if (bfd_is_com_section (symbol->section))

    relocation = 0;

  else

    relocation = symbol->value;

  /* Convert input-section-relative symbol value to absolute + addend.  */

  relocation += symbol->section->output_section->vma;

  relocation += symbol->section->output_offset;

  relocation += reloc->addend;

  reloc->addend = relocation;

  return bfd_reloc_ok;

}

/* This function is used for relocs which are only used

   for relaxing, which the linker should otherwise ignore.  */

static bfd_reloc_status_type

v850_elf_ignore_reloc (bfd *abfd ATTRIBUTE_UNUSED,

           arelent *reloc_entry,

           asymbol *symbol ATTRIBUTE_UNUSED,

           void * data ATTRIBUTE_UNUSED,

           asection *input_section,

           bfd *output_bfd,

           char **error_message ATTRIBUTE_UNUSED)

{

  if (output_bfd != NULL)

    reloc_entry->address += input_section->output_offset;

  return bfd_reloc_ok;

}

/* Note: It is REQUIRED that the 'type' value of each entry

   in this array match the index of the entry in the array.

   SeeAlso: RELOC_NUBMER in include/elf/v850.h.  */

static reloc_howto_type v850_elf_howto_table[] =

{

  /* This reloc does nothing.  */

  HOWTO (R_V850_NONE,     /* Type.  */

   0,       /* Rightshift.  */

   0,       /* Size.  */

   0,       /* Bitsize.  */

   false,       /* PC_relative.  */

   0,       /* Bitpos.  */

   complain_overflow_dont,  /* Complain_on_overflow.  */

   bfd_elf_generic_reloc,   /* Special_function.  */

   "R_V850_NONE",     /* Name.  */

   false,       /* Partial_inplace.  */

   0,       /* Src_mask.  */

   0,       /* Dst_mask.  */

   false),      /* PCrel_offset.  */

  /* A PC relative 9 bit branch.  */

  HOWTO (R_V850_9_PCREL,    /* Type.  */

   0,       /* Rightshift.  */

   2,       /* Size.  */

   9,       /* Bitsize.  */

   true,        /* PC_relative.  */

   0,       /* Bitpos.  */

   complain_overflow_bitfield,  /* Complain_on_overflow.  */

   v850_elf_reloc,    /* Special_function.  */

   "R_V850_9_PCREL",    /* Name.  */

   false,       /* Partial_inplace.  */

   0x00ffffff,      /* Src_mask.  */

   0x00ffffff,      /* Dst_mask.  */

   true),       /* PCrel_offset.  */

  /* A PC relative 22 bit branch.  */

  HOWTO (R_V850_22_PCREL,   /* Type.  */

   0,       /* Rightshift.  */

   4,       /* Size.  */

   22,        /* Bitsize.  */

   true,        /* PC_relative.  */

   0,       /* Bitpos.  */

   complain_overflow_signed,  /* Complain_on_overflow.  */

   v850_elf_reloc,    /* Special_function.  */

   "R_V850_22_PCREL",   /* Name.  */

   false,       /* Partial_inplace.  */