#line 1 "elfnn-ia64.c"

/* IA-64 support for 64-bit ELF

   Copyright (C) 1998-2025 Free Software Foundation, Inc.

   Contributed by David Mosberger-Tang <davidm@hpl.hp.com>

   This file is part of BFD, the Binary File Descriptor library.

   This program is free software; you can redistribute it and/or modify

   it under the terms of the GNU General Public License as published by

   the Free Software Foundation; either version 3 of the License, or

   (at your option) any later version.

   This program is distributed in the hope that it will be useful,

   but WITHOUT ANY WARRANTY; without even the implied warranty of

   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License

   along with this program; if not, write to the Free Software

   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,

   MA 02110-1301, USA.  */

#include "sysdep.h"

#include "bfd.h"

#include "libbfd.h"

#include "elf-bfd.h"

#include "opcode/ia64.h"

#include "elf/ia64.h"

#include "objalloc.h"

#include "hashtab.h"

#include "elfxx-ia64.h"

#define ARCH_SIZE 64

#if ARCH_SIZE == 64

#define LOG_SECTION_ALIGN 3

#endif

#if ARCH_SIZE == 32

#define LOG_SECTION_ALIGN 2

#endif

#define is_ia64_elf(bfd)         \

  (bfd_get_flavour (bfd) == bfd_target_elf_flavour \

   && elf_object_id (bfd) == IA64_ELF_DATA)

typedef struct bfd_hash_entry *(*new_hash_entry_func)

  (struct bfd_hash_entry *, struct bfd_hash_table *, const char *);

/* In dynamically (linker-) created sections, we generally need to keep track

   of the place a symbol or expression got allocated to. This is done via hash

   tables that store entries of the following type.  */

struct elf64_ia64_dyn_sym_info

{

  /* The addend for which this entry is relevant.  */

  bfd_vma addend;

  bfd_vma got_offset;

  bfd_vma fptr_offset;

  bfd_vma pltoff_offset;

  bfd_vma plt_offset;

  bfd_vma plt2_offset;

  bfd_vma tprel_offset;

  bfd_vma dtpmod_offset;

  bfd_vma dtprel_offset;

  /* The symbol table entry, if any, that this was derived from.  */

  struct elf_link_hash_entry *h;

  /* Used to count non-got, non-plt relocations for delayed sizing

     of relocation sections.  */

  struct elf64_ia64_dyn_reloc_entry

  {

    struct elf64_ia64_dyn_reloc_entry *next;

    asection *srel;

    int type;

    int count;

    /* Is this reloc against readonly section? */

    bool reltext;

  } *reloc_entries;

  /* TRUE when the section contents have been updated.  */

  unsigned got_done : 1;

  unsigned fptr_done : 1;

  unsigned pltoff_done : 1;

  unsigned tprel_done : 1;

  unsigned dtpmod_done : 1;

  unsigned dtprel_done : 1;

  /* TRUE for the different kinds of linker data we want created.  */

  unsigned want_got : 1;

  unsigned want_gotx : 1;

  unsigned want_fptr : 1;

  unsigned want_ltoff_fptr : 1;

  unsigned want_plt : 1;

  unsigned want_plt2 : 1;

  unsigned want_pltoff : 1;

  unsigned want_tprel : 1;

  unsigned want_dtpmod : 1;

  unsigned want_dtprel : 1;

};

struct elf64_ia64_local_hash_entry

{

  int id;

  unsigned int r_sym;

  /* The number of elements in elf64_ia64_dyn_sym_info array.  */

  unsigned int count;

  /* The number of sorted elements in elf64_ia64_dyn_sym_info array.  */

  unsigned int sorted_count;

  /* The size of elf64_ia64_dyn_sym_info array.  */

  unsigned int size;

  /* The array of elf64_ia64_dyn_sym_info.  */

  struct elf64_ia64_dyn_sym_info *info;

  /* TRUE if this hash entry's addends was translated for

     SHF_MERGE optimization.  */

  unsigned sec_merge_done : 1;

};

struct elf64_ia64_link_hash_entry

{

  struct elf_link_hash_entry root;

  /* The number of elements in elf64_ia64_dyn_sym_info array.  */

  unsigned int count;

  /* The number of sorted elements in elf64_ia64_dyn_sym_info array.  */

  unsigned int sorted_count;

  /* The size of elf64_ia64_dyn_sym_info array.  */

  unsigned int size;

  /* The array of elf64_ia64_dyn_sym_info.  */

  struct elf64_ia64_dyn_sym_info *info;

};

struct elf64_ia64_link_hash_table

{

  /* The main hash table.  */

  struct elf_link_hash_table root;

  asection *fptr_sec;   /* Function descriptor table (or NULL).  */

  asection *rel_fptr_sec; /* Dynamic relocation section for same.  */

  asection *pltoff_sec;   /* Private descriptors for plt (or NULL).  */

  asection *rel_pltoff_sec; /* Dynamic relocation section for same.  */

  bfd_size_type minplt_entries; /* Number of minplt entries.  */

  unsigned self_dtpmod_done : 1;/* Has self DTPMOD entry been finished?  */

  bfd_vma self_dtpmod_offset; /* .got offset to self DTPMOD entry.  */

  /* There are maybe R_IA64_GPREL22 relocations, including those

     optimized from R_IA64_LTOFF22X, against non-SHF_IA_64_SHORT

     sections.  We need to record those sections so that we can choose

     a proper GP to cover all R_IA64_GPREL22 relocations.  */

  asection *max_short_sec;  /* Maximum short output section.  */

  bfd_vma max_short_offset; /* Maximum short offset.  */

  asection *min_short_sec;  /* Minimum short output section.  */

  bfd_vma min_short_offset; /* Minimum short offset.  */

  htab_t loc_hash_table;

  void *loc_hash_memory;

};

struct elf64_ia64_allocate_data

{

  struct bfd_link_info *info;

  bfd_size_type ofs;

  bool only_got;

};

#define elf64_ia64_hash_table(p) \

  ((is_elf_hash_table ((p)->hash)          \

    && elf_hash_table_id (elf_hash_table (p)) == IA64_ELF_DATA)   \

   ? (struct elf64_ia64_link_hash_table *) (p)->hash : NULL)

static struct elf64_ia64_dyn_sym_info * get_dyn_sym_info

  (struct elf64_ia64_link_hash_table *ia64_info,

   struct elf_link_hash_entry *h,

   bfd *abfd, const Elf_Internal_Rela *rel, bool create);

static bool elf64_ia64_dynamic_symbol_p

  (struct elf_link_hash_entry *h, struct bfd_link_info *info, int);

static bool elf64_ia64_choose_gp

  (bfd *abfd, struct bfd_link_info *info, bool final);

static void elf64_ia64_dyn_sym_traverse

  (struct elf64_ia64_link_hash_table *ia64_info,

   bool (*func) (struct elf64_ia64_dyn_sym_info *, void *),

   void * info);

static bool allocate_global_data_got

  (struct elf64_ia64_dyn_sym_info *dyn_i, void * data);

static bool allocate_global_fptr_got

  (struct elf64_ia64_dyn_sym_info *dyn_i, void * data);

static bool allocate_local_got

  (struct elf64_ia64_dyn_sym_info *dyn_i, void * data);

static bool elf64_ia64_hpux_vec

  (const bfd_target *vec);

static bool allocate_dynrel_entries

  (struct elf64_ia64_dyn_sym_info *dyn_i, void * data);

static asection *get_pltoff

  (bfd *abfd, struct bfd_link_info *info,

   struct elf64_ia64_link_hash_table *ia64_info);

/* ia64-specific relocation.  */

/* Given a ELF reloc, return the matching HOWTO structure.  */

static bool

elf64_ia64_info_to_howto (bfd *abfd ATTRIBUTE_UNUSED,

        arelent *bfd_reloc,

        Elf_Internal_Rela *elf_reloc)

{

  unsigned int r_type = ELF32_R_TYPE (elf_reloc->r_info);

  bfd_reloc->howto = ia64_elf_lookup_howto (r_type);

  if (bfd_reloc->howto == NULL)

    {

      /* xgettext:c-format */

      _bfd_error_handler (_("%pB: unsupported relocation type %#x"),

        abfd, r_type);

      bfd_set_error (bfd_error_bad_value);

      return false;

    }

  return true;

}

#define PLT_HEADER_SIZE   (3 * 16)

#define PLT_MIN_ENTRY_SIZE  (1 * 16)

#define PLT_FULL_ENTRY_SIZE (2 * 16)

#define PLT_RESERVED_WORDS  3

static const bfd_byte plt_header[PLT_HEADER_SIZE] =

{

  0x0b, 0x10, 0x00, 0x1c, 0x00, 0x21,  /*   [MMI] mov r2=r14;;     */

  0xe0, 0x00, 0x08, 0x00, 0x48, 0x00,  /*   addl r14=0,r2    */

  0x00, 0x00, 0x04, 0x00,        /*   nop.i 0x0;;    */

  0x0b, 0x80, 0x20, 0x1c, 0x18, 0x14,  /*   [MMI] ld8 r16=[r14],8;;  */

  0x10, 0x41, 0x38, 0x30, 0x28, 0x00,  /*   ld8 r17=[r14],8    */

  0x00, 0x00, 0x04, 0x00,        /*   nop.i 0x0;;    */

  0x11, 0x08, 0x00, 0x1c, 0x18, 0x10,  /*   [MIB] ld8 r1=[r14]     */

  0x60, 0x88, 0x04, 0x80, 0x03, 0x00,  /*   mov b6=r17     */

  0x60, 0x00, 0x80, 0x00         /*   br.few b6;;    */

};

static const bfd_byte plt_min_entry[PLT_MIN_ENTRY_SIZE] =

{

  0x11, 0x78, 0x00, 0x00, 0x00, 0x24,  /*   [MIB] mov r15=0    */

  0x00, 0x00, 0x00, 0x02, 0x00, 0x00,  /*   nop.i 0x0    */

  0x00, 0x00, 0x00, 0x40         /*   br.few 0 <PLT0>;;  */

};

static const bfd_byte plt_full_entry[PLT_FULL_ENTRY_SIZE] =

{

  0x0b, 0x78, 0x00, 0x02, 0x00, 0x24,  /*   [MMI] addl r15=0,r1;;    */

  0x00, 0x41, 0x3c, 0x70, 0x29, 0xc0,  /*   ld8.acq r16=[r15],8*/

  0x01, 0x08, 0x00, 0x84,        /*   mov r14=r1;;     */

  0x11, 0x08, 0x00, 0x1e, 0x18, 0x10,  /*   [MIB] ld8 r1=[r15]     */

  0x60, 0x80, 0x04, 0x80, 0x03, 0x00,  /*   mov b6=r16     */

  0x60, 0x00, 0x80, 0x00         /*   br.few b6;;    */

};

#define ELF_DYNAMIC_INTERPRETER "/usr/lib/ld.so.1"

static const bfd_byte oor_brl[16] =

{

  0x05, 0x00, 0x00, 0x00, 0x01, 0x00,  /*  [MLX]  nop.m 0      */

  0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  /*   brl.sptk.few tgt;; */

  0x00, 0x00, 0x00, 0xc0

};

static const bfd_byte oor_ip[48] =

{

  0x04, 0x00, 0x00, 0x00, 0x01, 0x00,  /*  [MLX]  nop.m 0      */

  0x00, 0x00, 0x00, 0x00, 0x00, 0xe0,  /*   movl r15=0     */

  0x01, 0x00, 0x00, 0x60,

  0x03, 0x00, 0x00, 0x00, 0x01, 0x00,  /*  [MII]  nop.m 0      */

  0x00, 0x01, 0x00, 0x60, 0x00, 0x00,  /*   mov r16=ip;;     */

  0xf2, 0x80, 0x00, 0x80,        /*   add r16=r15,r16;;  */

  0x11, 0x00, 0x00, 0x00, 0x01, 0x00,  /*  [MIB]  nop.m 0      */

  0x60, 0x80, 0x04, 0x80, 0x03, 0x00,  /*   mov b6=r16     */

  0x60, 0x00, 0x80, 0x00         /*   br b6;;      */

};

static size_t oor_branch_size = sizeof (oor_brl);

void

bfd_elf64_ia64_after_parse (int itanium)

{

  oor_branch_size = itanium ? sizeof (oor_ip) : sizeof (oor_brl);

}

/* Rename some of the generic section flags to better document how they

   are used here.  */

#define skip_relax_pass_0 sec_flg0

#define skip_relax_pass_1 sec_flg1

/* These functions do relaxation for IA-64 ELF.  */

static void

elf64_ia64_update_short_info (asection *sec, bfd_vma offset,

            struct elf64_ia64_link_hash_table *ia64_info)

{

  /* Skip ABS and SHF_IA_64_SHORT sections.  */

  if (sec == bfd_abs_section_ptr

      || (sec->flags & SEC_SMALL_DATA) != 0)

    return;

  if (!ia64_info->min_short_sec)

    {

      ia64_info->max_short_sec = sec;

      ia64_info->max_short_offset = offset;

      ia64_info->min_short_sec = sec;

      ia64_info->min_short_offset = offset;

    }

  else if (sec == ia64_info->max_short_sec

     && offset > ia64_info->max_short_offset)

    ia64_info->max_short_offset = offset;

  else if (sec == ia64_info->min_short_sec

     && offset < ia64_info->min_short_offset)

    ia64_info->min_short_offset = offset;

  else if (sec->output_section->vma

     > ia64_info->max_short_sec->vma)

    {

      ia64_info->max_short_sec = sec;

      ia64_info->max_short_offset = offset;

    }

  else if (sec->output_section->vma

     < ia64_info->min_short_sec->vma)

    {

      ia64_info->min_short_sec = sec;

      ia64_info->min_short_offset = offset;

    }

}

static bool

elf64_ia64_relax_section (bfd *abfd, asection *sec,

        struct bfd_link_info *link_info,

        bool *again)

{

  struct one_fixup

    {

      struct one_fixup *next;

      asection *tsec;

      bfd_vma toff;

      bfd_vma trampoff;

    };

  Elf_Internal_Shdr *symtab_hdr;

  Elf_Internal_Rela *internal_relocs;

  Elf_Internal_Rela *irel, *irelend;

  bfd_byte *contents;

  Elf_Internal_Sym *isymbuf = NULL;

  struct elf64_ia64_link_hash_table *ia64_info;

  struct one_fixup *fixups = NULL;

  bool changed_contents = false;

  bool changed_relocs = false;

  bool changed_got = false;

  bool skip_relax_pass_0 = true;

  bool skip_relax_pass_1 = true;

  bfd_vma gp = 0;

  /* Assume we're not going to change any sizes, and we'll only need

     one pass.  */

  *again = false;

  if (bfd_link_relocatable (link_info))

    link_info->callbacks->fatal

      (_("%P: --relax and -r may not be used together\n"));

  /* Don't even try to relax for non-ELF outputs.  */

  if (!is_elf_hash_table (link_info->hash))

    return false;

  /* Nothing to do if there are no relocations or there is no need for

     the current pass.  */

  if (sec->reloc_count == 0

      || (sec->flags & SEC_RELOC) == 0

      || (sec->flags & SEC_HAS_CONTENTS) == 0

      || (link_info->relax_pass == 0 && sec->skip_relax_pass_0)

      || (link_info->relax_pass == 1 && sec->skip_relax_pass_1))

    return true;

  ia64_info = elf64_ia64_hash_table (link_info);

  if (ia64_info == NULL)

    return false;

  symtab_hdr = &elf_tdata (abfd)->symtab_hdr;

  /* Load the relocations for this section.  */

  internal_relocs = (_bfd_elf_link_read_relocs

         (abfd, sec, NULL, (Elf_Internal_Rela *) NULL,

          link_info->keep_memory));

  if (internal_relocs == NULL)

    return false;

  irelend = internal_relocs + sec->reloc_count;

  /* Get the section contents.  */

  if (elf_section_data (sec)->this_hdr.contents != NULL)

    contents = elf_section_data (sec)->this_hdr.contents;

  else

    {

      if (!bfd_malloc_and_get_section (abfd, sec, &contents))

  goto error_return;

    }

  for (irel = internal_relocs; irel < irelend; irel++)

    {

      unsigned long r_type = ELF64_R_TYPE (irel->r_info);

      bfd_vma symaddr, reladdr, trampoff, toff, roff;

      asection *tsec;

      struct one_fixup *f;

      bfd_size_type amt;

      bool is_branch;

      struct elf64_ia64_dyn_sym_info *dyn_i;

      char symtype;

      switch (r_type)

  {

  case R_IA64_PCREL21B:

  case R_IA64_PCREL21BI:

  case R_IA64_PCREL21M:

  case R_IA64_PCREL21F:

    /* In pass 1, all br relaxations are done. We can skip it. */

    if (link_info->relax_pass == 1)

      continue;

    skip_relax_pass_0 = false;

    is_branch = true;

    break;

  case R_IA64_PCREL60B:

    /* We can't optimize brl to br in pass 0 since br relaxations

       will increase the code size. Defer it to pass 1.  */

    if (link_info->relax_pass == 0)

      {

        skip_relax_pass_1 = false;

        continue;

      }

    is_branch = true;

    break;

  case R_IA64_GPREL22:

    /* Update max_short_sec/min_short_sec.  */

  case R_IA64_LTOFF22X:

  case R_IA64_LDXMOV:

    /* We can't relax ldx/mov in pass 0 since br relaxations will

       increase the code size. Defer it to pass 1.  */

    if (link_info->relax_pass == 0)

      {

        skip_relax_pass_1 = false;

        continue;

      }

    is_branch = false;

    break;

  default:

    continue;

  }

      /* Get the value of the symbol referred to by the reloc.  */

      if (ELF64_R_SYM (irel->r_info) < symtab_hdr->sh_info)

  {

    /* A local symbol.  */

    Elf_Internal_Sym *isym;

    /* Read this BFD's local symbols.  */

    if (isymbuf == NULL)

      {

        isymbuf = (Elf_Internal_Sym *) symtab_hdr->contents;

        if (isymbuf == NULL)

    isymbuf = bfd_elf_get_elf_syms (abfd, symtab_hdr,

            symtab_hdr->sh_info, 0,

            NULL, NULL, NULL);

        if (isymbuf == 0)

    goto error_return;

      }

    isym = isymbuf + ELF64_R_SYM (irel->r_info);

    if (isym->st_shndx == SHN_UNDEF)

      continue; /* We can't do anything with undefined symbols.  */

    else if (isym->st_shndx == SHN_ABS)

      tsec = bfd_abs_section_ptr;

    else if (isym->st_shndx == SHN_COMMON)

      tsec = bfd_com_section_ptr;

    else if (isym->st_shndx == SHN_IA_64_ANSI_COMMON)

      tsec = bfd_com_section_ptr;

    else

      tsec = bfd_section_from_elf_index (abfd, isym->st_shndx);

    toff = isym->st_value;

    dyn_i = get_dyn_sym_info (ia64_info, NULL, abfd, irel, false);

    symtype = ELF_ST_TYPE (isym->st_info);

  }

      else

  {

    unsigned long indx;

    struct elf_link_hash_entry *h;

    indx = ELF64_R_SYM (irel->r_info) - symtab_hdr->sh_info;

    h = elf_sym_hashes (abfd)[indx];

    BFD_ASSERT (h != NULL);

    while (h->root.type == bfd_link_hash_indirect

     || h->root.type == bfd_link_hash_warning)

      h = (struct elf_link_hash_entry *) h->root.u.i.link;

    dyn_i = get_dyn_sym_info (ia64_info, h, abfd, irel, false);

    /* For branches to dynamic symbols, we're interested instead

       in a branch to the PLT entry.  */

    if (is_branch && dyn_i && dyn_i->want_plt2)

      {

        /* Internal branches shouldn't be sent to the PLT.

     Leave this for now and we'll give an error later.  */

        if (r_type != R_IA64_PCREL21B)

    continue;

        tsec = ia64_info->root.splt;

        toff = dyn_i->plt2_offset;

        BFD_ASSERT (irel->r_addend == 0);

      }

    /* Can't do anything else with dynamic symbols.  */

    else if (elf64_ia64_dynamic_symbol_p (h, link_info, r_type))

      continue;

    else

      {

        /* We can't do anything with undefined symbols.  */

        if (h->root.type == bfd_link_hash_undefined

      || h->root.type == bfd_link_hash_undefweak)

    continue;

        tsec = h->root.u.def.section;

        toff = h->root.u.def.value;

      }

    symtype = h->type;

  }

      if (tsec->sec_info_type == SEC_INFO_TYPE_MERGE)

  {

    /* At this stage in linking, no SEC_MERGE symbol has been

       adjusted, so all references to such symbols need to be

       passed through _bfd_merged_section_offset.  (Later, in

       relocate_section, all SEC_MERGE symbols *except* for

       section symbols have been adjusted.)

       gas may reduce relocations against symbols in SEC_MERGE

       sections to a relocation against the section symbol when

       the original addend was zero.  When the reloc is against

       a section symbol we should include the addend in the

       offset passed to _bfd_merged_section_offset, since the

       location of interest is the original symbol.  On the

       other hand, an access to "sym+addend" where "sym" is not

       a section symbol should not include the addend;  Such an

       access is presumed to be an offset from "sym";  The

       location of interest is just "sym".  */

     if (symtype == STT_SECTION)

       toff += irel->r_addend;

     toff = _bfd_merged_section_offset (abfd, &tsec,

                elf_section_data (tsec)->sec_info,

                toff);

     if (symtype != STT_SECTION)

       toff += irel->r_addend;

  }

      else

  toff += irel->r_addend;

      symaddr = tsec->output_section->vma + tsec->output_offset + toff;

      roff = irel->r_offset;

      if (is_branch)

  {

    bfd_signed_vma offset;

    reladdr = (sec->output_section->vma

         + sec->output_offset

         + roff) & (bfd_vma) -4;

    /* The .plt section is aligned at 32byte and the .text section

       is aligned at 64byte. The .text section is right after the

       .plt section.  After the first relaxation pass, linker may

       increase the gap between the .plt and .text sections up

       to 32byte.  We assume linker will always insert 32byte

       between the .plt and .text sections after the first

       relaxation pass.  */

    if (tsec == ia64_info->root.splt)

      offset = -0x1000000 + 32;

    else

      offset = -0x1000000;

    /* If the branch is in range, no need to do anything.  */

    if ((bfd_signed_vma) (symaddr - reladdr) >= offset

        && (bfd_signed_vma) (symaddr - reladdr) <= 0x0FFFFF0)

      {

        /* If the 60-bit branch is in 21-bit range, optimize it. */

        if (r_type == R_IA64_PCREL60B)

    {

      ia64_elf_relax_brl (contents, roff);

      irel->r_info

        = ELF64_R_INFO (ELF64_R_SYM (irel->r_info),

            R_IA64_PCREL21B);

      /* If the original relocation offset points to slot

         1, change it to slot 2.  */

      if ((irel->r_offset & 3) == 1)

        irel->r_offset += 1;

      changed_contents = true;

      changed_relocs = true;

    }

        continue;

      }

    else if (r_type == R_IA64_PCREL60B)

      continue;

    else if (ia64_elf_relax_br (contents, roff))

      {

        irel->r_info

    = ELF64_R_INFO (ELF64_R_SYM (irel->r_info),

        R_IA64_PCREL60B);

        /* Make the relocation offset point to slot 1.  */

        irel->r_offset = (irel->r_offset & ~((bfd_vma) 0x3)) + 1;

        changed_contents = true;

        changed_relocs = true;

        continue;

      }

    /* We can't put a trampoline in a .init/.fini section. Issue

       an error.  */

    if (strcmp (sec->output_section->name, ".init") == 0

        || strcmp (sec->output_section->name, ".fini") == 0)

      {

        _bfd_error_handler

    /* xgettext:c-format */

    (_("%pB: can't relax br at %#" PRIx64 " in section `%pA';"

       " please use brl or indirect branch"),

     sec->owner, (uint64_t) roff, sec);

        bfd_set_error (bfd_error_bad_value);

        goto error_return;

      }

    /* If the branch and target are in the same section, you've

       got one honking big section and we can't help you unless

       you are branching backwards.  You'll get an error message

       later.  */

    if (tsec == sec && toff > roff)

      continue;

    /* Look for an existing fixup to this address.  */

    for (f = fixups; f ; f = f->next)

      if (f->tsec == tsec && f->toff == toff)

        break;

    if (f == NULL)

      {

        /* Two alternatives: If it's a branch to a PLT entry, we can

     make a copy of the FULL_PLT entry.  Otherwise, we'll have

     to use a `brl' insn to get where we're going.  */

        size_t size;

        if (tsec == ia64_info->root.splt)

    size = sizeof (plt_full_entry);

        else

    size = oor_branch_size;

        /* Resize the current section to make room for the new branch. */

        trampoff = (sec->size + 15) & (bfd_vma) -16;

        /* If trampoline is out of range, there is nothing we

     can do.  */

        offset = trampoff - (roff & (bfd_vma) -4);

        if (offset < -0x1000000 || offset > 0x0FFFFF0)

    continue;

        amt = trampoff + size;

        contents = (bfd_byte *) bfd_realloc (contents, amt);

        if (contents == NULL)

    goto error_return;

        sec->size = amt;

        if (tsec == ia64_info->root.splt)

    {

      memcpy (contents + trampoff, plt_full_entry, size);

      /* Hijack the old relocation for use as the PLTOFF reloc.  */

      irel->r_info = ELF64_R_INFO (ELF64_R_SYM (irel->r_info),

                 R_IA64_PLTOFF22);

      irel->r_offset = trampoff;

    }

        else

    {

      if (size == sizeof (oor_ip))

        {

          memcpy (contents + trampoff, oor_ip, size);

          irel->r_info = ELF64_R_INFO (ELF64_R_SYM (irel->r_info),

               R_IA64_PCREL64I);

          irel->r_addend -= 16;

          irel->r_offset = trampoff + 2;

        }

      else

        {

          memcpy (contents + trampoff, oor_brl, size);

          irel->r_info = ELF64_R_INFO (ELF64_R_SYM (irel->r_info),

               R_IA64_PCREL60B);

          irel->r_offset = trampoff + 2;

        }

    }

        /* Record the fixup so we don't do it again this section.  */

        f = (struct one_fixup *)

    bfd_malloc ((bfd_size_type) sizeof (*f));

        f->next = fixups;

        f->tsec = tsec;

        f->toff = toff;

        f->trampoff = trampoff;

        fixups = f;

      }

    else

      {

        /* If trampoline is out of range, there is nothing we

     can do.  */

        offset = f->trampoff - (roff & (bfd_vma) -4);

        if (offset < -0x1000000 || offset > 0x0FFFFF0)

    continue;

        /* Nop out the reloc, since we're finalizing things here.  */

        irel->r_info = ELF64_R_INFO (0, R_IA64_NONE);

      }

    /* Fix up the existing branch to hit the trampoline.  */

    if (ia64_elf_install_value (contents + roff, offset, r_type)

        != bfd_reloc_ok)

      goto error_return;

    changed_contents = true;

    changed_relocs = true;

  }

      else

  {

    /* Fetch the gp.  */

    if (gp == 0)

      {

        bfd *obfd = sec->output_section->owner;

        gp = _bfd_get_gp_value (obfd);

        if (gp == 0)

    {

      if (!elf64_ia64_choose_gp (obfd, link_info, false))

        goto error_return;

      gp = _bfd_get_gp_value (obfd);

    }

      }

    /* If the data is out of range, do nothing.  */

    if ((bfd_signed_vma) (symaddr - gp) >= 0x200000

        ||(bfd_signed_vma) (symaddr - gp) < -0x200000)

      continue;

    if (r_type == R_IA64_GPREL22)

      elf64_ia64_update_short_info (tsec->output_section,

            tsec->output_offset + toff,

            ia64_info);

    else if (r_type == R_IA64_LTOFF22X)

      {

        irel->r_info = ELF64_R_INFO (ELF64_R_SYM (irel->r_info),

             R_IA64_GPREL22);

        changed_relocs = true;

        if (dyn_i->want_gotx)

    {

      dyn_i->want_gotx = 0;

      changed_got |= !dyn_i->want_got;

    }

        elf64_ia64_update_short_info (tsec->output_section,

              tsec->output_offset + toff,

              ia64_info);

      }

    else

      {

        ia64_elf_relax_ldxmov (contents, roff);

        irel->r_info = ELF64_R_INFO (0, R_IA64_NONE);

        changed_contents = true;

        changed_relocs = true;

      }

  }

    }

  /* ??? If we created fixups, this may push the code segment large

     enough that the data segment moves, which will change the GP.

     Reset the GP so that we re-calculate next round.  We need to

     do this at the _beginning_ of the next round; now will not do.  */

  /* Clean up and go home.  */

  while (fixups)

    {

      struct one_fixup *f = fixups;

      fixups = fixups->next;

      free (f);

    }

  if (isymbuf != NULL

      && symtab_hdr->contents != (unsigned char *) isymbuf)

    {

      if (! link_info->keep_memory)

  free (isymbuf);

      else

  {

    /* Cache the symbols for elf_link_input_bfd.  */

    symtab_hdr->contents = (unsigned char *) isymbuf;

  }

    }

  if (contents != NULL

      && elf_section_data (sec)->this_hdr.contents != contents)

    {

      if (!changed_contents && !link_info->keep_memory)

  free (contents);

      else

  {

    /* Cache the section contents for elf_link_input_bfd.  */

    elf_section_data (sec)->this_hdr.contents = contents;

  }

    }

  if (elf_section_data (sec)->relocs != internal_relocs)

    {

      if (!changed_relocs)

  free (internal_relocs);

      else

  elf_section_data (sec)->relocs = internal_relocs;

    }

  if (changed_got)

    {

      struct elf64_ia64_allocate_data data;

      data.info = link_info;

      data.ofs = 0;

      ia64_info->self_dtpmod_offset = (bfd_vma) -1;

      elf64_ia64_dyn_sym_traverse (ia64_info, allocate_global_data_got, &data);

      elf64_ia64_dyn_sym_traverse (ia64_info, allocate_global_fptr_got, &data);

      elf64_ia64_dyn_sym_traverse (ia64_info, allocate_local_got, &data);

      ia64_info->root.sgot->size = data.ofs;

      if (ia64_info->root.dynamic_sections_created

    && ia64_info->root.srelgot != NULL)

  {

    /* Resize .rela.got.  */

    ia64_info->root.srelgot->size = 0;

    if (bfd_link_pic (link_info)

        && ia64_info->self_dtpmod_offset != (bfd_vma) -1)

      ia64_info->root.srelgot->size += sizeof (Elf64_External_Rela);

    data.only_got = true;

    elf64_ia64_dyn_sym_traverse (ia64_info, allocate_dynrel_entries,

               &data);

  }

    }

  if (link_info->relax_pass == 0)

    {

      /* Pass 0 is only needed to relax br.  */

      sec->skip_relax_pass_0 = skip_relax_pass_0;

      sec->skip_relax_pass_1 = skip_relax_pass_1;

    }

  *again = changed_contents || changed_relocs;

  return true;

 error_return:

  if ((unsigned char *) isymbuf != symtab_hdr->contents)

    free (isymbuf);

  if (elf_section_data (sec)->this_hdr.contents != contents)

    free (contents);

  if (elf_section_data (sec)->relocs != internal_relocs)

    free (internal_relocs);

  return false;

}

#undef skip_relax_pass_0

#undef skip_relax_pass_1

/* Return TRUE if NAME is an unwind table section name.  */

static inline bool

is_unwind_section_name (bfd *abfd, const char *name)

{

  if (elf64_ia64_hpux_vec (abfd->xvec)

      && !strcmp (name, ELF_STRING_ia64_unwind_hdr))

    return false;

  return ((startswith (name, ELF_STRING_ia64_unwind)

     && ! startswith (name, ELF_STRING_ia64_unwind_info))

    || startswith (name, ELF_STRING_ia64_unwind_once));

}

/* Handle an IA-64 specific section when reading an object file.  This

   is called when bfd_section_from_shdr finds a section with an unknown

   type.  */

static bool

elf64_ia64_section_from_shdr (bfd *abfd,

            Elf_Internal_Shdr *hdr,

            const char *name,

            int shindex)

{

  /* There ought to be a place to keep ELF backend specific flags, but

     at the moment there isn't one.  We just keep track of the

     sections by their name, instead.  Fortunately, the ABI gives

     suggested names for all the MIPS specific sections, so we will

     probably get away with this.  */

  switch (hdr->sh_type)

    {

    case SHT_IA_64_UNWIND:

    case SHT_IA_64_HP_OPT_ANOT:

      break;

    case SHT_IA_64_EXT:

      if (strcmp (name, ELF_STRING_ia64_archext) != 0)

  return false;

      break;

    default:

      return false;

    }