/* mips.h.  Mips opcode list for GDB, the GNU debugger.

   Copyright (C) 1993-2025 Free Software Foundation, Inc.

   Contributed by Ralph Campbell and OSF

   Commented and modified by Ian Lance Taylor, Cygnus Support

   This file is part of GDB, GAS, and the GNU binutils.

   GDB, GAS, and the GNU binutils are free software; you can redistribute

   them and/or modify them under the terms of the GNU General Public

   License as published by the Free Software Foundation; either version 3,

   or (at your option) any later version.

   GDB, GAS, and the GNU binutils are distributed in the hope that they

   will be useful, but WITHOUT ANY WARRANTY; without even the implied

   warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See

   the GNU General Public License for more details.

   You should have received a copy of the GNU General Public License

   along with this file; see the file COPYING3.  If not, write to the Free

   Software Foundation, 51 Franklin Street - Fifth Floor, Boston,

   MA 02110-1301, USA.  */

#ifndef _MIPS_H_

#define _MIPS_H_

#include "bfd.h"

#ifdef __cplusplus

extern "C" {

#endif

/* These are bit masks and shift counts to use to access the various

   fields of an instruction.  To retrieve the X field of an

   instruction, use the expression

  (i >> OP_SH_X) & OP_MASK_X

   To set the same field (to j), use

  i = (i &~ (OP_MASK_X << OP_SH_X)) | (j << OP_SH_X)

   Make sure you use fields that are appropriate for the instruction,

   of course.

   The 'i' format uses OP, RS, RT and IMMEDIATE.

   The 'j' format uses OP and TARGET.

   The 'r' format uses OP, RS, RT, RD, SHAMT and FUNCT.

   The 'b' format uses OP, RS, RT and DELTA.

   The floating point 'i' format uses OP, RS, RT and IMMEDIATE.

   The floating point 'r' format uses OP, FMT, FT, FS, FD and FUNCT.

   A breakpoint instruction uses OP, CODE and SPEC (10 bits of the

   breakpoint instruction are not defined; Kane says the breakpoint

   code field in BREAK is 20 bits; yet MIPS assemblers and debuggers

   only use ten bits).  An optional two-operand form of break/sdbbp

   allows the lower ten bits to be set too, and MIPS32 and later

   architectures allow 20 bits to be set with a single operand for

   the sdbbp instruction (using CODE20).

   The syscall instruction uses CODE20.

   The general coprocessor instructions use COPZ.  */

#define OP_MASK_OP    0x3f

#define OP_SH_OP    26

#define OP_MASK_RS    0x1f

#define OP_SH_RS    21

#define OP_MASK_BCC   0x7

#define OP_SH_BCC   18

#define OP_MASK_RT    0x1f

#define OP_SH_RT    16

#define OP_MASK_RD    0x1f

#define OP_SH_RD    11

#define OP_MASK_IMMEDIATE 0xffff

#define OP_SH_IMMEDIATE   0

/* Values in the 'VSEL' field.  */

#define MDMX_FMTSEL_IMM_QH  0x1d

#define MDMX_FMTSEL_IMM_OB  0x1e

#define MDMX_FMTSEL_VEC_QH  0x15

#define MDMX_FMTSEL_VEC_OB  0x16

/* Enumerates the various types of MIPS operand.  */

enum mips_operand_type {

  /* Described by mips_int_operand.  */

  OP_INT,

  /* Described by mips_mapped_int_operand.  */

  OP_MAPPED_INT,

  /* Described by mips_msb_operand.  */

  OP_MSB,

  /* Described by mips_reg_operand.  */

  OP_REG,

  /* Like OP_REG, but can be omitted if the register is the same as the

     previous operand.  */

  OP_OPTIONAL_REG,

  /* Described by mips_reg_pair_operand.  */

  OP_REG_PAIR,

  /* Described by mips_pcrel_operand.  */

  OP_PCREL,

  /* A performance register.  The field is 5 bits in size, but the supported

     values are much more restricted.  */

  OP_PERF_REG,

  /* The final operand in a microMIPS ADDIUSP instruction.  It mostly acts

     as a normal 9-bit signed offset that is multiplied by four, but there

     are four special cases:

     -2 * 4 => -258 * 4

     -1 * 4 => -257 * 4

      0 * 4 =>  256 * 4

      1 * 4 =>  257 * 4.  */

  OP_ADDIUSP_INT,

  /* The target of a (D)CLO or (D)CLZ instruction.  The operand spans two

     5-bit register fields, both of which must be set to the destination

     register.  */

  OP_CLO_CLZ_DEST,

  /* A register list for a microMIPS LWM or SWM instruction.  The operand

     size determines whether the 16-bit or 32-bit encoding is required.  */

  OP_LWM_SWM_LIST,

  /* The register list for an emulated MIPS16 ENTRY or EXIT instruction.  */

  OP_ENTRY_EXIT_LIST,

  /* The register list and frame size for a MIPS16 SAVE or RESTORE

     instruction.  */

  OP_SAVE_RESTORE_LIST,

  /* A 10-bit field VVVVVNNNNN used for octobyte and quadhalf instructions:

     V      Meaning

     -----  -------

     0EEE0  8 copies of $vN[E], OB format

     0EE01  4 copies of $vN[E], QH format

     10110  all 8 elements of $vN, OB format

     10101  all 4 elements of $vN, QH format

     11110  8 copies of immediate N, OB format

     11101  4 copies of immediate N, QH format.  */

  OP_MDMX_IMM_REG,

  /* A register operand that must match the destination register.  */

  OP_REPEAT_DEST_REG,

  /* A register operand that must match the previous register.  */

  OP_REPEAT_PREV_REG,

  /* $pc, which has no encoding in the architectural instruction.  */

  OP_PC,

  /* $28, which has no encoding in the MIPS16e architectural instruction.  */

  OP_REG28,

  /* A 4-bit XYZW channel mask or 2-bit XYZW index; the size determines

     which.  */

  OP_VU0_SUFFIX,

  /* Like OP_VU0_SUFFIX, but used when the operand's value has already

     been set.  Any suffix used here must match the previous value.  */

  OP_VU0_MATCH_SUFFIX,

  /* An index selected by an integer, e.g. [1].  */

  OP_IMM_INDEX,

  /* An index selected by a register, e.g. [$2].  */

  OP_REG_INDEX,

  /* The operand spans two 5-bit register fields, both of which must be set to

     the source register.  */

  OP_SAME_RS_RT,

  /* Described by mips_prev_operand.  */

  OP_CHECK_PREV,

  /* A register operand that must not be zero.  */

  OP_NON_ZERO_REG

};

/* Enumerates the types of MIPS register.  */

enum mips_reg_operand_type {

  /* General registers $0-$31.  Software names like $at can also be used.  */

  OP_REG_GP,

  /* Floating-point registers $f0-$f31.  */

  OP_REG_FP,

  /* Coprocessor condition code registers $cc0-$cc7.  FPU condition codes

     can also be written $fcc0-$fcc7.  */

  OP_REG_CCC,

  /* FPRs used in a vector capacity.  They can be written $f0-$f31

     or $v0-$v31, although the latter form is not used for the VR5400

     vector instructions.  */

  OP_REG_VEC,

  /* DSP accumulator registers $ac0-$ac3.  */

  OP_REG_ACC,

  /* Coprocessor registers $0-$31.  Mnemonic names like c0_cause can

     also be used in some contexts.  */

  OP_REG_COPRO,

  /* Coprocessor control registers $0-$31.  Mnemonic names like c1_fcsr can

     also be used in some contexts.  */

  OP_REG_CONTROL,

  /* Hardware registers $0-$31.  Mnemonic names like hwr_cpunum can

     also be used in some contexts.  */

  OP_REG_HW,

  /* Floating-point registers $vf0-$vf31.  */

  OP_REG_VF,

  /* Integer registers $vi0-$vi31.  */

  OP_REG_VI,

  /* R5900 VU0 registers $I, $Q, $R and $ACC.  */

  OP_REG_R5900_I,

  OP_REG_R5900_Q,

  OP_REG_R5900_R,

  OP_REG_R5900_ACC,

  /* MSA registers $w0-$w31.  */

  OP_REG_MSA,

  /* MSA control registers $0-$31.  */

  OP_REG_MSA_CTRL

};

/* Base class for all operands.  */

struct mips_operand

{

  /* The type of the operand.  */

  enum mips_operand_type type;

  /* The operand occupies SIZE bits of the instruction, starting at LSB.  */

  unsigned short size;

  unsigned short lsb;

};

/* Describes an integer operand with a regular encoding pattern.  */

struct mips_int_operand

{

  struct mips_operand root;

  /* The low ROOT.SIZE bits of MAX_VAL encodes (MAX_VAL + BIAS) << SHIFT.

     The cyclically previous field value encodes 1 << SHIFT less than that,

     and so on.  E.g.

     - for { { T, 4, L }, 14, 0, 0 }, field values 0...14 encode themselves,

       but 15 encodes -1.

     - { { T, 8, L }, 127, 0, 2 } is a normal signed 8-bit operand that is

       shifted left two places.

     - { { T, 3, L }, 8, 0, 0 } is a normal unsigned 3-bit operand except

       that 0 encodes 8.

     - { { ... }, 0, 1, 3 } means that N encodes (N + 1) << 3.  */

  unsigned int max_val;

  int bias;

  unsigned int shift;

  /* True if the operand should be printed as hex rather than decimal.  */

  bool print_hex;

};

/* Uses a lookup table to describe a small integer operand.  */

struct mips_mapped_int_operand

{

  struct mips_operand root;

  /* Maps each encoding value to the integer that it represents.  */

  const int *int_map;

  /* True if the operand should be printed as hex rather than decimal.  */

  bool print_hex;

};

/* An operand that encodes the most significant bit position of a bitfield.

   Given a bitfield that spans bits [MSB, LSB], some operands of this type

   encode MSB directly while others encode MSB - LSB.  Each operand of this

   type is preceded by an integer operand that specifies LSB.

   The assembly form varies between instructions.  For some instructions,

   such as EXT, the operand is written as the bitfield size.  For others,

   such as EXTS, it is written in raw MSB - LSB form.  */

struct mips_msb_operand

{

  struct mips_operand root;

  /* The assembly-level operand encoded by a field value of 0.  */

  int bias;

  /* True if the operand encodes MSB directly, false if it encodes

     MSB - LSB.  */

  bool add_lsb;

  /* The maximum value of MSB + 1.  */

  unsigned int opsize;

};

/* Describes a single register operand.  */

struct mips_reg_operand

{

  struct mips_operand root;

  /* The type of register.  */

  enum mips_reg_operand_type reg_type;

  /* If nonnull, REG_MAP[N] gives the register associated with encoding N,

     otherwise the encoding is the same as the register number.  */

  const unsigned char *reg_map;

};

/* Describes an operand that which must match a condition based on the

   previous operand.  */

struct mips_check_prev_operand

{

  struct mips_operand root;

  bool greater_than_ok;

  bool less_than_ok;

  bool equal_ok;

  bool zero_ok;

};

/* Describes an operand that encodes a pair of registers.  */

struct mips_reg_pair_operand

{

  struct mips_operand root;

  /* The type of register.  */

  enum mips_reg_operand_type reg_type;

  /* Encoding N represents REG1_MAP[N], REG2_MAP[N].  */

  unsigned char *reg1_map;

  unsigned char *reg2_map;

};

/* Describes an operand that is calculated relative to a base PC.

   The base PC is usually the address of the following instruction,

   but the rules for MIPS16 instructions like ADDIUPC are more complicated.  */

struct mips_pcrel_operand

{

  /* Encodes the offset.  */

  struct mips_int_operand root;

  /* The low ALIGN_LOG2 bits of the base PC are cleared to give PC',

     which is then added to the offset encoded by ROOT.  */

  unsigned int align_log2 : 8;

  /* If INCLUDE_ISA_BIT, the ISA bit of the original base PC is then

     reinstated.  This is true for jumps and branches and false for

     PC-relative data instructions.  */

  unsigned int include_isa_bit : 1;

  /* If FLIP_ISA_BIT, the ISA bit of the result is inverted.

     This is true for JALX and false otherwise.  */

  unsigned int flip_isa_bit : 1;

};

/* Return true if the assembly syntax allows OPERAND to be omitted.  */

static inline bool

mips_optional_operand_p (const struct mips_operand *operand)

{

  return (operand->type == OP_OPTIONAL_REG

    || operand->type == OP_REPEAT_PREV_REG);

}

Unexecuted instantiation: mips-dis.c:mips_optional_operand_p

Unexecuted instantiation: mips-opc.c:mips_optional_operand_p

Unexecuted instantiation: mips16-opc.c:mips_optional_operand_p

Unexecuted instantiation: micromips-opc.c:mips_optional_operand_p

/* Return a version of INSN in which the field specified by OPERAND

   has value UVAL.  */

static inline unsigned int

mips_insert_operand (const struct mips_operand *operand, unsigned int insn,

         unsigned int uval)

{

  unsigned int mask;

  mask = (1 << operand->size) - 1;

  insn &= ~(mask << operand->lsb);

  insn |= (uval & mask) << operand->lsb;

  return insn;

}

Unexecuted instantiation: mips-dis.c:mips_insert_operand

Unexecuted instantiation: mips-opc.c:mips_insert_operand

Unexecuted instantiation: mips16-opc.c:mips_insert_operand

Unexecuted instantiation: micromips-opc.c:mips_insert_operand

/* Extract OPERAND from instruction INSN.  */

static inline unsigned int

mips_extract_operand (const struct mips_operand *operand, unsigned int insn)

{

  return (insn >> operand->lsb) & ((1 << operand->size) - 1);

}

mips-dis.c:mips_extract_operand

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400

10.9M

{

401

10.9M

  return (insn >> operand->lsb) & ((1 << operand->size) - 1);

402

10.9M

}

Unexecuted instantiation: mips-opc.c:mips_extract_operand

Unexecuted instantiation: mips16-opc.c:mips_extract_operand

Unexecuted instantiation: micromips-opc.c:mips_extract_operand

/* UVAL is the value encoded by OPERAND.  Return it in signed form.  */

static inline int

mips_signed_operand (const struct mips_operand *operand, unsigned int uval)

{

  unsigned int sign_bit, mask;

  mask = (1 << operand->size) - 1;

  sign_bit = 1 << (operand->size - 1);

  return ((uval + sign_bit) & mask) - sign_bit;

}

mips-dis.c:mips_signed_operand

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21.5k

{

409

21.5k

  unsigned int sign_bit, mask;

410

411

21.5k

  mask = (1 << operand->size) - 1;

412

21.5k

  sign_bit = 1 << (operand->size - 1);

413

21.5k

  return ((uval + sign_bit) & mask) - sign_bit;

414

21.5k

}

Unexecuted instantiation: mips-opc.c:mips_signed_operand

Unexecuted instantiation: mips16-opc.c:mips_signed_operand

Unexecuted instantiation: micromips-opc.c:mips_signed_operand

/* Return the integer that OPERAND encodes as UVAL.  */

static inline int

mips_decode_int_operand (const struct mips_int_operand *operand,

       unsigned int uval)

{

  uval |= (operand->max_val - uval) & -(1 << operand->root.size);

  uval += operand->bias;

  uval <<= operand->shift;

  return uval;

}

mips-dis.c:mips_decode_int_operand

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421

2.31M

{

422

2.31M

  uval |= (operand->max_val - uval) & -(1 << operand->root.size);

423

2.31M

  uval += operand->bias;

424

2.31M

  uval <<= operand->shift;

425

2.31M

  return uval;

426

2.31M

}

Unexecuted instantiation: mips-opc.c:mips_decode_int_operand

Unexecuted instantiation: mips16-opc.c:mips_decode_int_operand

Unexecuted instantiation: micromips-opc.c:mips_decode_int_operand

/* Return the maximum value that can be encoded by OPERAND.  */

static inline int

mips_int_operand_max (const struct mips_int_operand *operand)

{

  return (operand->max_val + operand->bias) << operand->shift;

}

Unexecuted instantiation: mips-dis.c:mips_int_operand_max

Unexecuted instantiation: mips-opc.c:mips_int_operand_max

Unexecuted instantiation: mips16-opc.c:mips_int_operand_max

Unexecuted instantiation: micromips-opc.c:mips_int_operand_max

/* Return the minimum value that can be encoded by OPERAND.  */

static inline int

mips_int_operand_min (const struct mips_int_operand *operand)

{

  unsigned int mask;

  mask = (1 << operand->root.size) - 1;

  return mips_int_operand_max (operand) - (mask << operand->shift);

}

Unexecuted instantiation: mips-dis.c:mips_int_operand_min

Unexecuted instantiation: mips-opc.c:mips_int_operand_min

Unexecuted instantiation: mips16-opc.c:mips_int_operand_min

Unexecuted instantiation: micromips-opc.c:mips_int_operand_min

/* Return the register that OPERAND encodes as UVAL.  */

static inline int

mips_decode_reg_operand (const struct mips_reg_operand *operand,

       unsigned int uval)

{

  if (operand->reg_map)

    uval = operand->reg_map[uval];

  return uval;

}

mips-dis.c:mips_decode_reg_operand

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452

7.05M

{

453

7.05M

  if (operand->reg_map)

454

2.25M

    uval = operand->reg_map[uval];

455

7.05M

  return uval;

456

7.05M

}

Unexecuted instantiation: mips-opc.c:mips_decode_reg_operand

Unexecuted instantiation: mips16-opc.c:mips_decode_reg_operand

Unexecuted instantiation: micromips-opc.c:mips_decode_reg_operand

/* PC-relative operand OPERAND has value UVAL and is relative to BASE_PC.

   Return the address that it encodes.  */

static inline bfd_vma

mips_decode_pcrel_operand (const struct mips_pcrel_operand *operand,

         bfd_vma base_pc, unsigned int uval)

{

  bfd_vma addr;

  addr = base_pc & -(1 << operand->align_log2);

  addr += mips_decode_int_operand (&operand->root, uval);

  if (operand->include_isa_bit)

    addr |= base_pc & 1;

  if (operand->flip_isa_bit)

    addr ^= 1;

  return addr;

}

mips-dis.c:mips_decode_pcrel_operand

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392k

{

465

392k

  bfd_vma addr;

466

467

392k

  addr = base_pc & -(1 << operand->align_log2);

468

392k

  addr += mips_decode_int_operand (&operand->root, uval);

469

392k

  if (operand->include_isa_bit)

470

339k

    addr |= base_pc & 1;

471

392k

  if (operand->flip_isa_bit)

472

35.1k

    addr ^= 1;

473

392k

  return addr;

474

392k

}

Unexecuted instantiation: mips-opc.c:mips_decode_pcrel_operand

Unexecuted instantiation: mips16-opc.c:mips_decode_pcrel_operand

Unexecuted instantiation: micromips-opc.c:mips_decode_pcrel_operand

/* This structure holds information for a particular instruction.  */

struct mips_opcode

{

  /* The name of the instruction.  */

  const char *name;

  /* A string describing the arguments for this instruction.  */

  const char *args;

  /* The basic opcode for the instruction.  When assembling, this

     opcode is modified by the arguments to produce the actual opcode

     that is used.  If pinfo is INSN_MACRO, then this is 0.  */

  unsigned long match;

  /* If pinfo is not INSN_MACRO, then this is a bit mask for the

     relevant portions of the opcode when disassembling.  If the

     actual opcode anded with the match field equals the opcode field,

     then we have found the correct instruction.  If pinfo is

     INSN_MACRO, then this field is the macro identifier.  */

  unsigned long mask;

  /* For a macro, this is INSN_MACRO.  Otherwise, it is a collection

     of bits describing the instruction, notably any relevant hazard

     information.  */

  unsigned long pinfo;

  /* A collection of additional bits describing the instruction. */

  unsigned long pinfo2;

  /* A collection of bits describing the instruction sets of which this

     instruction or macro is a member. */

  unsigned long membership;

  /* A collection of bits describing the ASE of which this instruction

     or macro is a member.  */

  unsigned long ase;

  /* A collection of bits describing the instruction sets of which this

     instruction or macro is not a member.  */

  unsigned long exclusions;

};

/* Return true if MO is an instruction that requires 32-bit encoding.  */

static inline bool

mips_opcode_32bit_p (const struct mips_opcode *mo)

{

  return mo->mask >> 16 != 0;

}

mips-dis.c:mips_opcode_32bit_p

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62.0M

{

516

62.0M

  return mo->mask >> 16 != 0;

517

62.0M

}

Unexecuted instantiation: mips-opc.c:mips_opcode_32bit_p

Unexecuted instantiation: mips16-opc.c:mips_opcode_32bit_p

Unexecuted instantiation: micromips-opc.c:mips_opcode_32bit_p

/* These are the characters which may appear in the args field of a

   regular MIPS instruction.  They appear in the order in which the fields

   appear when the instruction is used.  Commas and parentheses in the

   args string are ignored when assembling, and written into the output

   when disassembling.

   "1" 5-bit SYNC type at bit 6.

   "<" 5-bit shift amount at bit 6 (SHAMT).

   ">" Shift amount between 32 and 63, stored after subtracting 32, at bit 6

       (SHAMT).

   "a" 26-bit target address at bit 0 (TARGET).

   "+i" Likewise, but flips bit 0.

   "b" 5-bit base register at bit 21 (RS).

   "c" 10-bit breakpoint code at bit 16.

   "d" 5-bit destination register at bit 11 (RD).

   "h" 5-bit PREFX hint at bit 11.

   "i" 16-bit unsigned immediate at bit 0 (IMMEDIATE).

   "j" 16-bit signed immediate at bit 0 (DELTA).

   "k" 5-bit CACHE opcode in target register position at bit 16.

   "o" 16-bit signed offset at bit 0 (DELTA).

   "p" 16-bit PC relative branch target address at bit 0 (DELTA).

   "q" 10-bit extra breakpoint code at bit 6.

   "r" 5-bit same register used as both source and target at bit 21 (RS).

   "s" 5-bit source register at bit 21 (RS).

   "t" 5-bit target register at bit 16 (RT).

   "u" 16-bit upper 16 bits of address at bit 0 (IMMEDIATE).

   "v" 5-bit same register used as both source and destination at bit 21 (RS).

   "w" 5-bit same register used as both target and destination at bit 16 (RT).

   "U" 5-bit same destination register at both bit 11 and 16 (both RD and RT)

       (used by CLO and CLZ).

   "C" 25-bit coprocessor function code at bit 0.

   "B" 20-bit syscall/breakpoint function code at bit 6.

   "J" 19-bit WAIT function code at bit 6.

   "x" Accept and ignore register name.

   "z" Must be zero register.

   "K" 5-bit Hardware Register (RDHWR instruction) at bit 11 (RD).

   "+A" 5-bit INS/EXT/DINS/DEXT/DINSM/DEXTM position at bit 6,

  which becomes LSB (SHAMT).

  Enforces: 0 <= pos < 32.

   "+B" 5-bit INS/DINS size at bit 11, which becomes MSB.

  Requires that "+A" or "+E" occur first to set position.

  Enforces: 0 < (pos+size) <= 32.

   "+C" 5-bit EXT/DEXT size at bit 11, which becomes MSBD.

  Requires that "+A" or "+E" occur first to set position.

  Enforces: 0 < (pos+size) <= 32.

  (Also used by DEXT w/ different limits, but limits for

  that are checked by the M_DEXT macro.)

   "+E" 5-bit DINSU/DEXTU position at bit 6, which becomes LSB-32 (SHAMT).

  Enforces: 32 <= pos < 64.

   "+F" 5-bit DINSM/DINSU size at bit 11, which becomes MSB-32.

  Requires that "+A" or "+E" occur first to set position.

  Enforces: 32 < (pos+size) <= 64.

   "+G" 5-bit DEXTM size at bit 11, which becomes MSBD-32.

  Requires that "+A" or "+E" occur first to set position.

  Enforces: 32 < (pos+size) <= 64.

   "+H" 5-bit DEXTU size at bit 11, which becomes MSBD.

  Requires that "+A" or "+E" occur first to set position.

  Enforces: 32 < (pos+size) <= 64.

   Floating point instructions:

   "D" 5-bit destination register at bit 6 (FD).

   "M" 3-bit compare condition code at bit 8 (only used for mips4 and up).

   "N" 3-bit branch condition code at bit 18 (only used for mips4 and up).

   "S" 5-bit fs source 1 register at bit 11 (FS).

   "T" 5-bit ft source 2 register at bit 16 (FT).

   "R" 5-bit fr source 3 register at bit 21 (FR).

   "V" 5-bit same register used as floating source and destination at bit 11

       (FS).

   "W" 5-bit same register used as floating target and destination at bit 16

       (FT).

   Coprocessor instructions:

   "E" 5-bit target register at bit 16 (RT).

   "G" 5-bit destination register at bit 11 (RD).

   "H" 3-bit sel field for (D)MTC* and (D)MFC* at bit 0.

   "P" 5-bit performance-monitor register at bit 1.

   "e" 3-bit vector register byte specifier at bit 22.

   "g" 5-bit control destination register at bit 11 (RD).

   "%" 3-bit immediate vr5400 vector alignment operand at bit 21.

   Macro instructions:

   "A" General 32-bit expression.

   "I" 32-bit immediate (value placed in imm_expr).

   "F" 64-bit floating point constant in .rdata.

   "L" 64-bit floating point constant in .lit8.

   "f" 32-bit floating point constant.

   "l" 32-bit floating point constant in .lit4.

   MDMX and VR5400 instruction operands (note that while these use the

   FP register fields, the MDMX instructions accept both $fN and $vN names

   for the registers):

   "O" 3-bit alignment offset at bit 21.

   "Q" 10-bit vector/scalar/immediate source at bit 16.

   "X" 5-bit destination register at bit 6 (FD).

   "Y" 5-bit source register at bit 11 (FS).

   "Z" 5-bit source register at bit 16 (FT).

   R5900 VU0 Macromode instructions:

   "+5" 5-bit floating point register at bit 6 (FD).

   "+6" 5-bit floating point register at bit 11 (FS).

   "+7" 5-bit floating point register at bit 16 (FT).

   "+8" 5-bit integer register at bit 6 (FD).

   "+9" 5-bit integer register at bit 11 (FS).

   "+0" 5-bit integer register at bit 16 (FT).

   "+K" Match an existing 4-bit channel mask starting at bit 21.

   "+L" 2-bit channel index starting at bit 21.

   "+M" 2-bit channel index starting at bit 23.

   "+N" Match an existing 2-bit channel index starting at bit 0.

   "+f" 15-bit immediate for VCALLMS at bit 6.

   "+g" 5-bit signed immediate for VIADDI at bit 6.

   "+m" $ACC register (syntax only).

   "+q" $Q register (syntax only).

   "+r" $R register (syntax only).

   "+y" $I register (syntax only).

   "#+" "++" decorator in ($reg++) sequence.

   "#-" "--" decorator in (--$reg) sequence.

   DSP ASE usage:

   "2" 2-bit unsigned immediate for byte align at bit 11.

   "3" 3-bit unsigned immediate at bit 21.

   "4" 4-bit unsigned immediate at bit 21.

   "5" 8-bit unsigned immediate at bit 16.

   "6" 5-bit unsigned immediate at bit 21 (RS).

   "7" 2-bit DSP accumulator register at bit 11.

   "8" 6-bit unsigned immediate at bit 11.

   "9" 2-bit DSP accumulator register at bit 21.

   "0" 6-bit signed immediate at bit 20.

   ":" 7-bit signed immediate at bit 19.

   "'" 6-bit unsigned immediate at bit 16.

   "@" 10-bit signed immediate at bit 16.

   MT ASE usage:

   "!" 1-bit usermode flag at bit 5.

   "$" 1-bit load high flag at bit 4.

   "*" 2-bit DSP/SmartMIPS accumulator register at bit 18.

   "&" 2-bit DSP/SmartMIPS accumulator register at bit 13.

   "y" 5-bit control target register at bit 16 (RT).

   MCU ASE usage:

   "~" 12-bit offset at bit 0.

   "\" 3-bit position for ASET and ACLR at bit 12.

   VIRT ASE usage:

   "+J" 10-bit HYPCALL code at bit 11.

   UDI immediates:

   "+1" UDI immediate bits 6-10.

   "+2" UDI immediate bits 6-15.

   "+3" UDI immediate bits 6-20.

   "+4" UDI immediate bits 6-25.

   Octeon:

   "+x" Bit index field of BBITx at bit 16.

  Enforces: 0 <= index < 32.

   "+X" Bit index field of BBITx aliasing BBITx32 at bit 16.

  Matches if 32 <= index < 64, otherwise skips to next candidate.

   "+p" Position field of CINS/CINS32/EXTS/EXTS32 at bit 6.

  Enforces 0 <= pos < 32.

   "+P" Position field of CINS/EXTS aliasing CINS32/EXTS32 at bit 6.

  Matches if 32 <= pos < 64, otherwise skips to next candidate.

   "+Q" Immediate field of SEQI/SNEI at bit 6.

  Enforces -512 <= imm < 512.

   "+s" Length-minus-one field of CINS32/EXTS32 at bit 11.

  Requires MSB position of the field to be <= 31.

   "+S" Length-minus-one field of CINS/EXTS at bit 11.

  Requires MSB position of the field to be <= 63.

   Loongson-ext ASE:

   "+a" 8-bit signed offset at bit 6.

   "+b" 8-bit signed offset at bit 3.

   "+c" 9-bit signed offset at bit 6.

   "+z" 5-bit rz register at bit 0.

   "+Z" 5-bit fz register at bit 0.

   interAptiv MR2:

   "-m" Register list for SAVE/RESTORE instruction.

   Enhanced VA Scheme:

   "+j" 9-bit signed offset at bit 7.

   MSA Extension:

   "+d" 5-bit MSA register at bit 6 (FD).

   "+e" 5-bit MSA register at bit 11 (FS).

   "+h" 5-bit MSA register at bit 16 (FT).

   "+k" 5-bit GPR at bit 6.

   "+l" 5-bit MSA control register at bit 6.

   "+n" 5-bit MSA control register at bit 11.

   "+o" 4-bit vector element index at bit 16.

   "+u" 3-bit vector element index at bit 16.

   "+v" 2-bit vector element index at bit 16.

   "+w" 1-bit vector element index at bit 16.

   "+T" (-512 .. 511) << 0 at bit 16.

   "+U" (-512 .. 511) << 1 at bit 16.

   "+V" (-512 .. 511) << 2 at bit 16.

   "+W" (-512 .. 511) << 3 at bit 16.

   "+~" 2-bit LSA/DLSA shift amount from 1 to 4 at bit 6.

   "+!" 3-bit unsigned bit position at bit 16.

   "+@" 4-bit unsigned bit position at bit 16.

   "+#" 6-bit unsigned bit position at bit 16.

   "+$" 5-bit unsigned immediate at bit 16.

   "+%" 5-bit signed immediate at bit 16.

   "+^" 10-bit signed immediate at bit 11.

   "+&" 0 vector element index.

   "+*" 5-bit register vector element index at bit 16.

   "+|" 8-bit mask at bit 16.

   MIPS R6:

   "+:" 11-bit mask at bit 0.

   "+'" 26-bit PC relative branch target address at bit 0.

   "+"" 21-bit PC relative branch target address at bit 0.

   "+;" 5-bit same register at both bit 16 and 21 (both RT and RS).

   "+I" 2-bit unsigned bit position at bit 6.

   "+O" 3-bit unsigned bit position at bit 6.

   "+R" Must be program counter.

   "-a" (-262144 .. 262143) << 2 at bit 0.

   "-b" (-131072 .. 131071) << 3 at bit 0.

   "-d" Same as destination register GP.

   "-s" 5-bit source register at bit 21 (RS) not $0.

   "-t" 5-bit target register at bit 16 (RT) not $0

   "-u" 5-bit target register at bit 16 (RT) greater than RS.

   "-v" 5-bit target register at bit 16 (RT) not $0 not RS.

   "-w" 5-bit target register at bit 16 (RT) less than or equal to RS.

   "-x" 5-bit source register at bit 21 (RS) greater than RT.

   "-y" 5-bit source register at bit 21 (RS) not $0 less than RT.

   "-A" Symbolic offset (-262144 .. 262143) << 2 at bit 0.

   "-B" Symbolic offset (-131072 .. 131071) << 3 at bit 0.

   GINV ASE usage:

   "+\" 2-bit Global TLB invalidate type at bit 8.

   Other:

   "()" Parens surrounding optional value.

   ","  Separates operands.

   "+"  Start of extension sequence.

   "-"  Start of extension sequence.

   Characters used so far, for quick reference when adding more:

   "1234567890"

   "%[]<>(),+-:'@!#$*&\~"

   "ABCDEFGHIJKLMNOPQRSTUVWXYZ"

   "abcdef hijkl  opqrstuvwxyz"

   Extension character sequences used so far ("+" followed by the

   following), for quick reference when adding more:

   "1234567890"

   "~!@#$%^&*|:'";\"

   "ABC EFGHIJKLMNOPQRSTUVWX Z"

   "abcdefghijklmnopqrs uvwxyz"

   Extension character sequences used so far ("-" followed by the

   following), for quick reference when adding more:

   "AB                        "

   "ab d        m     stuvwxy "

*/

/* These are the bits which may be set in the pinfo field of an

   instructions, if it is not equal to INSN_MACRO.  */

/* Writes to operand number N.  */

#define INSN_WRITE_SHIFT            0

#define INSN_WRITE_1                0x00000001

#define INSN_WRITE_2                0x00000002

#define INSN_WRITE_ALL              0x00000003

/* Reads from operand number N.  */

#define INSN_READ_SHIFT             2

#define INSN_READ_1                 0x00000004

#define INSN_READ_2                 0x00000008

#define INSN_READ_3                 0x00000010

#define INSN_READ_4                 0x00000020

#define INSN_READ_ALL               0x0000003c

/* Modifies general purpose register 31.  */

#define INSN_WRITE_GPR_31           0x00000040

/* Modifies coprocessor condition code.  */

#define INSN_WRITE_COND_CODE        0x00000080

/* Reads coprocessor condition code.  */

#define INSN_READ_COND_CODE         0x00000100

/* TLB operation.  */

#define INSN_TLB                    0x00000200

/* Reads coprocessor register other than floating point register.  */

#define INSN_COP                    0x00000400

/* Instruction loads value from memory.  */

#define INSN_LOAD_MEMORY      0x00000800

/* Instruction loads value from coprocessor, (may require delay).  */

#define INSN_LOAD_COPROC      0x00001000

/* Instruction has unconditional branch delay slot.  */

#define INSN_UNCOND_BRANCH_DELAY    0x00002000

/* Instruction has conditional branch delay slot.  */

#define INSN_COND_BRANCH_DELAY      0x00004000

/* Conditional branch likely: if branch not taken, insn nullified.  */

#define INSN_COND_BRANCH_LIKELY     0x00008000

/* Moves to coprocessor register, (may require delay).  */

#define INSN_COPROC_MOVE            0x00010000

/* Loads coprocessor register from memory, requiring delay.  */

#define INSN_COPROC_MEMORY_DELAY    0x00020000

/* Reads the HI register.  */

#define INSN_READ_HI        0x00040000

/* Reads the LO register.  */

#define INSN_READ_LO        0x00080000

/* Modifies the HI register.  */

#define INSN_WRITE_HI       0x00100000

/* Modifies the LO register.  */

#define INSN_WRITE_LO       0x00200000

/* Not to be placed in a branch delay slot, either architecturally

   or for ease of handling (such as with instructions that take a trap).  */

#define INSN_NO_DELAY_SLOT      0x00400000

/* Instruction stores value into memory.  */

#define INSN_STORE_MEMORY     0x00800000

/* Instruction uses single precision floating point.  */

#define FP_S          0x01000000

/* Instruction uses double precision floating point.  */

#define FP_D          0x02000000

/* Instruction is part of the tx39's integer multiply family.    */

#define INSN_MULT                   0x04000000

/* Reads general purpose register 24.  */

#define INSN_READ_GPR_24            0x08000000

/* Writes to general purpose register 24.  */

#define INSN_WRITE_GPR_24           0x10000000

/* A user-defined instruction.  */

#define INSN_UDI                    0x20000000

/* Instruction is actually a macro.  It should be ignored by the

   disassembler, and requires special treatment by the assembler.  */

#define INSN_MACRO                  0xffffffff

/* These are the bits which may be set in the pinfo2 field of an

   instruction. */

/* Instruction is a simple alias (I.E. "move" for daddu/addu/or) */

#define INSN2_ALIAS       0x00000001

/* Instruction reads MDMX accumulator. */

#define INSN2_READ_MDMX_ACC     0x00000002

/* Instruction writes MDMX accumulator. */

#define INSN2_WRITE_MDMX_ACC      0x00000004

/* Macro uses single-precision floating-point instructions.  This should

   only be set for macros.  For instructions, FP_S in pinfo carries the

   same information.  */

#define INSN2_M_FP_S        0x00000008

/* Macro uses double-precision floating-point instructions.  This should

   only be set for macros.  For instructions, FP_D in pinfo carries the

   same information.  */

#define INSN2_M_FP_D        0x00000010

/* Instruction has a branch delay slot that requires a 16-bit instruction.  */

#define INSN2_BRANCH_DELAY_16BIT    0x00000020

/* Instruction has a branch delay slot that requires a 32-bit instruction.  */

#define INSN2_BRANCH_DELAY_32BIT    0x00000040

/* Writes to the stack pointer ($29).  */

#define INSN2_WRITE_SP        0x00000080

/* Reads from the stack pointer ($29).  */

#define INSN2_READ_SP       0x00000100

/* Reads the RA ($31) register.  */

#define INSN2_READ_GPR_31     0x00000200

/* Reads the program counter ($pc).  */

#define INSN2_READ_PC       0x00000400

/* Is an unconditional branch insn. */

#define INSN2_UNCOND_BRANCH     0x00000800

/* Is a conditional branch insn. */

#define INSN2_COND_BRANCH     0x00001000

/* Reads from $16.  This is true of the MIPS16 0x6500 nop.  */

#define INSN2_READ_GPR_16           0x00002000

/* Has an "\.x?y?z?w?" suffix based on mips_vu0_channel_mask.  */

#define INSN2_VU0_CHANNEL_SUFFIX    0x00004000

/* Instruction has a forbidden slot.  */

#define INSN2_FORBIDDEN_SLOT        0x00008000

/* Opcode table entry is for a short MIPS16 form only.  An extended

   encoding may still exist, but with a separate opcode table entry

   required.  In disassembly the presence of this flag in an otherwise

   successful match against an extended instruction encoding inhibits

   matching against any subsequent short table entry even if it does

   not have this flag set.  A table entry matching the full extended

   encoding is needed or otherwise the final EXTEND entry will apply,

   for the disassembly of the prefix only.  */

#define INSN2_SHORT_ONLY      0x00010000

/* Masks used to mark instructions to indicate which MIPS ISA level

   they were introduced in.  INSN_ISA_MASK masks an enumeration that

   specifies the base ISA level(s).  The remainder of a 32-bit

   word constructed using these macros is a bitmask of the remaining

   INSN_* values below, as indicated by INSN_CHIP_MASK.  */

#define INSN_ISA_MASK     0x0000001ful

/* We cannot start at zero due to ISA_UNKNOWN below.  */

#define INSN_ISA1                 1

#define INSN_ISA2                 2

#define INSN_ISA3                 3

#define INSN_ISA4                 4

#define INSN_ISA5                 5

#define INSN_ISA32                6

#define INSN_ISA32R2              7

#define INSN_ISA32R3              8

#define INSN_ISA32R5              9

#define INSN_ISA32R6              10

#define INSN_ISA64                11 

#define INSN_ISA64R2              12

#define INSN_ISA64R3              13

#define INSN_ISA64R5              14

#define INSN_ISA64R6              15

/* Below this point the INSN_* values correspond to combinations of ISAs.

   They are only for use in the opcodes table to indicate membership of

   a combination of ISAs that cannot be expressed using the usual inclusion

   ordering on the above INSN_* values.  */

#define INSN_ISA3_32              16

#define INSN_ISA3_32R2            17

#define INSN_ISA4_32              18

#define INSN_ISA4_32R2            19

#define INSN_ISA5_32R2            20

/* The R6 definitions shown below state that they support all previous ISAs.

   This is not actually true as some instructions are removed in R6.

   The problem is that the removed instructions in R6 come from different

   ISAs.  One approach to solve this would be to describe in the membership

   field of the opcode table the different ISAs an instruction belongs to.

   This would require us to create a large amount of different ISA

   combinations which is hard to manage.  A cleaner approach (which is

   implemented here) is to say that R6 is an extension of R5 and then to

   deal with the removed instructions by adding instruction exclusions

   for R6 in the opcode table.  */

/* Bit INSN_ISA<X> - 1 of INSN_UPTO<Y> is set if ISA Y includes ISA X.  */

#define ISAF(X) (1 << (INSN_ISA##X - 1))

#define INSN_UPTO1    ISAF(1)

#define INSN_UPTO2    INSN_UPTO1 | ISAF(2)

#define INSN_UPTO3    INSN_UPTO2 | ISAF(3) | ISAF(3_32) | ISAF(3_32R2)

#define INSN_UPTO4    INSN_UPTO3 | ISAF(4) | ISAF(4_32) | ISAF(4_32R2)

#define INSN_UPTO5    INSN_UPTO4 | ISAF(5) | ISAF(5_32R2)

#define INSN_UPTO32   INSN_UPTO2 | ISAF(32) | ISAF(3_32) | ISAF(4_32)

#define INSN_UPTO32R2 INSN_UPTO32 | ISAF(32R2) \

      | ISAF(3_32R2) | ISAF(4_32R2) | ISAF(5_32R2)

#define INSN_UPTO32R3 INSN_UPTO32R2 | ISAF(32R3)

#define INSN_UPTO32R5 INSN_UPTO32R3 | ISAF(32R5)

#define INSN_UPTO32R6 INSN_UPTO32R5 | ISAF(32R6)

#define INSN_UPTO64   INSN_UPTO5 | ISAF(64) | ISAF(32)

#define INSN_UPTO64R2 INSN_UPTO64 | ISAF(64R2) | ISAF(32R2)

#define INSN_UPTO64R3 INSN_UPTO64R2 | ISAF(64R3) | ISAF(32R3)

#define INSN_UPTO64R5 INSN_UPTO64R3 | ISAF(64R5) | ISAF(32R5)

#define INSN_UPTO64R6 INSN_UPTO64R5 | ISAF(64R6) | ISAF(32R6)

/* The same information in table form: bit INSN_ISA<X> - 1 of index

   INSN_UPTO<Y> - 1 is set if ISA Y includes ISA X.  */

static const unsigned int mips_isa_table[] = {

  INSN_UPTO1,

  INSN_UPTO2,

  INSN_UPTO3,

  INSN_UPTO4,

  INSN_UPTO5,

  INSN_UPTO32,

  INSN_UPTO32R2,

  INSN_UPTO32R3,

  INSN_UPTO32R5,

  INSN_UPTO32R6,

  INSN_UPTO64,

  INSN_UPTO64R2,

  INSN_UPTO64R3,

  INSN_UPTO64R5,

  INSN_UPTO64R6

};

#undef ISAF

/* Masks used for Chip specific instructions.  */

#define INSN_CHIP_MASK    0x01ffffe0

/* MIPS R4650 instruction.  */

#define INSN_4650   0x00000020

/* LSI R4010 instruction.  */

#define INSN_4010   0x00000040

/* NEC VR4100 instruction.  */

#define INSN_4100   0x00000080

/* Toshiba R3900 instruction.  */

#define INSN_3900   0x00000100

/* MIPS R10000 instruction.  */

#define INSN_10000    0x00000200

/* Broadcom SB-1 instruction.  */

#define INSN_SB1    0x00000400

/* NEC VR4111/VR4181 instruction.  */

#define INSN_4111   0x00000800

/* NEC VR4120 instruction.  */

#define INSN_4120   0x00001000

/* NEC VR5400 instruction.  */

#define INSN_5400   0x00002000

/* NEC VR5500 instruction.  */

#define INSN_5500   0x00004000

/* MIPS R5900 instruction.  */

#define INSN_5900   0x00008000

/* ST Microelectronics Loongson 2E.  */

#define INSN_LOONGSON_2E  0x00010000

/* ST Microelectronics Loongson 2F.  */

#define INSN_LOONGSON_2F  0x00020000

/* Cavium Networks Octeon instructions.  */

#define INSN_OCTEON   0x00040000

#define INSN_OCTEONP    0x00080000

#define INSN_OCTEON2    0x00100000

#define INSN_OCTEON3    0x00200000

/* RMI XLR instruction.  */

#define INSN_XLR    0x00400000

/* Imagination interAptiv MR2.  */

#define INSN_INTERAPTIV_MR2 0x00800000

/* Sony PSP Allegrex instruction.  */

#define INSN_ALLEGREX   0x01000000

/* DSP ASE */

#define ASE_DSP     0x00000001

#define ASE_DSP64   0x00000002

/* DSP R2 ASE  */

#define ASE_DSPR2   0x00000004

/* Enhanced VA Scheme */

#define ASE_EVA     0x00000008

/* MCU (MicroController) ASE */

#define ASE_MCU     0x00000010

/* MDMX ASE */

#define ASE_MDMX    0x00000020

/* MIPS-3D ASE */

#define ASE_MIPS3D    0x00000040

/* MT ASE */

#define ASE_MT      0x00000080

/* SmartMIPS ASE  */

#define ASE_SMARTMIPS   0x00000100

/* Virtualization ASE */

#define ASE_VIRT    0x00000200

#define ASE_VIRT64    0x00000400

/* MSA Extension  */

#define ASE_MSA     0x00000800

#define ASE_MSA64   0x00001000

/* eXtended Physical Address (XPA) Extension.  */

#define ASE_XPA     0x00002000

/* DSP R3 Module.  */

#define ASE_DSPR3   0x00004000

/* MIPS16e2 ASE.  */

#define ASE_MIPS16E2    0x00008000

/* MIPS16e2 MT ASE instructions.  */

#define ASE_MIPS16E2_MT   0x00010000

/* The Virtualization ASE has eXtended Physical Addressing (XPA)

   instructions which are only valid when both ASEs are enabled.  */

#define ASE_XPA_VIRT    0x00020000

/* Cyclic redundancy check (CRC) ASE.  */

#define ASE_CRC     0x00040000

#define ASE_CRC64   0x00080000