Coverage Report

Created: 2025-06-24 06:45

/src/binutils-gdb/opcodes/dlx-dis.c
Line
Count
Source (jump to first uncovered line)
1
/* Instruction printing code for the DLX Microprocessor
2
   Copyright (C) 2002-2025 Free Software Foundation, Inc.
3
   Contributed by Kuang Hwa Lin.  Written by Kuang Hwa Lin, 03/2002.
4
5
   This file is part of the GNU opcodes library.
6
7
   This library is free software; you can redistribute it and/or modify
8
   it under the terms of the GNU General Public License as published by
9
   the Free Software Foundation; either version 3, or (at your option)
10
   any later version.
11
12
   It is distributed in the hope that it will be useful, but WITHOUT
13
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
15
   License for more details.
16
17
   You should have received a copy of the GNU General Public License
18
   along with this program; if not, write to the Free Software
19
   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
20
   MA 02110-1301, USA.  */
21
22
#include "sysdep.h"
23
#include "disassemble.h"
24
#include "opcode/dlx.h"
25
26
52
#define R_ERROR     0x1
27
934
#define R_TYPE      0x2
28
2.24k
#define ILD_TYPE    0x3
29
1.72k
#define IST_TYPE    0x4
30
4.49k
#define IAL_TYPE    0x5
31
4.42k
#define IBR_TYPE    0x6
32
5.56k
#define IJ_TYPE     0x7
33
5.95k
#define IJR_TYPE    0x8
34
56.1k
#define NIL         0x9
35
36
227k
#define OPC(x)      ((x >> 26) & 0x3F)
37
#define FUNC(x)     (x & 0x7FF)
38
39
unsigned char opc, rs1, rs2, rd;
40
unsigned long imm26, imm16, func, current_insn_addr;
41
42
/* Print one instruction from MEMADDR on INFO->STREAM.
43
   Return the size of the instruction (always 4 on dlx).  */
44
45
static unsigned char
46
dlx_get_opcode (unsigned long opcode)
47
6.90k
{
48
6.90k
  return (unsigned char) ((opcode >> 26) & 0x3F);
49
6.90k
}
50
51
static unsigned char
52
dlx_get_rs1 (unsigned long opcode)
53
6.90k
{
54
6.90k
  return (unsigned char) ((opcode >> 21) & 0x1F);
55
6.90k
}
56
57
static unsigned char
58
dlx_get_rs2 (unsigned long opcode)
59
6.90k
{
60
6.90k
  return (unsigned char) ((opcode >> 16) & 0x1F);
61
6.90k
}
62
63
static unsigned char
64
dlx_get_rdR (unsigned long opcode)
65
6.90k
{
66
6.90k
  return (unsigned char) ((opcode >> 11) & 0x1F);
67
6.90k
}
68
69
static unsigned long
70
dlx_get_func (unsigned long opcode)
71
6.90k
{
72
6.90k
  return (unsigned char) (opcode & 0x7FF);
73
6.90k
}
74
75
static unsigned long
76
dlx_get_imm16 (unsigned long opcode)
77
6.90k
{
78
6.90k
  return (unsigned long) (opcode & 0xFFFF);
79
6.90k
}
80
81
static unsigned long
82
dlx_get_imm26 (unsigned long opcode)
83
6.90k
{
84
6.90k
  return (unsigned long) (opcode & 0x03FFFFFF);
85
6.90k
}
86
87
/* Fill the opcode to the max length.  */
88
89
static void
90
operand_deliminator (struct disassemble_info *info, char *ptr)
91
4.99k
{
92
4.99k
  int difft = 8 - (int) strlen (ptr);
93
94
27.2k
  while (difft > 0)
95
22.2k
    {
96
22.2k
      (*info->fprintf_func) (info->stream, "%c", ' ');
97
22.2k
      difft -= 1;
98
22.2k
    }
99
4.99k
}
100
101
/* Process the R-type opcode.  */
102
103
static unsigned char
104
dlx_r_type (struct disassemble_info *info)
105
6.90k
{
106
6.90k
  unsigned char r_opc[] = { OPC(ALUOP) }; /* Fix ME */
107
6.90k
  int r_opc_num = (sizeof r_opc) / (sizeof (char));
108
6.90k
  struct _r_opcode
109
6.90k
  {
110
6.90k
    unsigned long func;
111
6.90k
    char *name;
112
6.90k
  }
113
6.90k
  dlx_r_opcode[] =
114
6.90k
  {
115
6.90k
    { NOPF,     "nop"    },  /* NOP                          */
116
6.90k
    { ADDF,     "add"    },  /* Add                          */
117
6.90k
    { ADDUF,    "addu"   },  /* Add Unsigned                 */
118
6.90k
    { SUBF,     "sub"    },  /* SUB                          */
119
6.90k
    { SUBUF,    "subu"   },  /* Sub Unsigned                 */
120
6.90k
    { MULTF,    "mult"   },  /* MULTIPLY                     */
121
6.90k
    { MULTUF,   "multu"  },  /* MULTIPLY Unsigned            */
122
6.90k
    { DIVF,     "div"    },  /* DIVIDE                       */
123
6.90k
    { DIVUF,    "divu"   },  /* DIVIDE Unsigned              */
124
6.90k
    { ANDF,     "and"    },  /* AND                          */
125
6.90k
    { ORF,      "or"     },  /* OR                           */
126
6.90k
    { XORF,     "xor"    },  /* Exclusive OR                 */
127
6.90k
    { SLLF,     "sll"    },  /* SHIFT LEFT LOGICAL           */
128
6.90k
    { SRAF,     "sra"    },  /* SHIFT RIGHT ARITHMETIC       */
129
6.90k
    { SRLF,     "srl"    },  /* SHIFT RIGHT LOGICAL          */
130
6.90k
    { SEQF,     "seq"    },  /* Set if equal                 */
131
6.90k
    { SNEF,     "sne"    },  /* Set if not equal             */
132
6.90k
    { SLTF,     "slt"    },  /* Set if less                  */
133
6.90k
    { SGTF,     "sgt"    },  /* Set if greater               */
134
6.90k
    { SLEF,     "sle"    },  /* Set if less or equal         */
135
6.90k
    { SGEF,     "sge"    },  /* Set if greater or equal      */
136
6.90k
    { SEQUF,    "sequ"   },  /* Set if equal                 */
137
6.90k
    { SNEUF,    "sneu"   },  /* Set if not equal             */
138
6.90k
    { SLTUF,    "sltu"   },  /* Set if less                  */
139
6.90k
    { SGTUF,    "sgtu"   },  /* Set if greater               */
140
6.90k
    { SLEUF,    "sleu"   },  /* Set if less or equal         */
141
6.90k
    { SGEUF,    "sgeu"   },  /* Set if greater or equal      */
142
6.90k
    { MVTSF,    "mvts"   },  /* Move to special register     */
143
6.90k
    { MVFSF,    "mvfs"   },  /* Move from special register   */
144
6.90k
    { BSWAPF,   "bswap"  },  /* Byte swap ??                 */
145
6.90k
    { LUTF,     "lut"    }   /* ????????? ??                 */
146
6.90k
  };
147
6.90k
  int dlx_r_opcode_num = (sizeof dlx_r_opcode) / (sizeof dlx_r_opcode[0]);
148
6.90k
  int idx;
149
150
13.3k
  for (idx = 0; idx < r_opc_num; idx++)
151
6.90k
    {
152
6.90k
      if (r_opc[idx] != opc)
153
6.41k
  continue;
154
493
      else
155
493
  break;
156
6.90k
    }
157
158
6.90k
  if (idx == r_opc_num)
159
6.41k
    return NIL;
160
161
3.50k
  for (idx = 0 ; idx < dlx_r_opcode_num; idx++)
162
3.48k
    if (dlx_r_opcode[idx].func == func)
163
467
      {
164
467
  (*info->fprintf_func) (info->stream, "%s", dlx_r_opcode[idx].name);
165
166
467
  if (func != NOPF)
167
163
    {
168
      /* This is not a nop.  */
169
163
      operand_deliminator (info, dlx_r_opcode[idx].name);
170
163
      (*info->fprintf_func) (info->stream, "r%d,", (int)rd);
171
163
      (*info->fprintf_func) (info->stream, "r%d", (int)rs1);
172
163
      if (func != MVTSF && func != MVFSF)
173
143
        (*info->fprintf_func) (info->stream, ",r%d", (int)rs2);
174
163
    }
175
467
  return (unsigned char) R_TYPE;
176
467
      }
177
178
26
  return (unsigned char) R_ERROR;
179
493
}
180
181
/* Process the memory read opcode.  */
182
183
static unsigned char
184
dlx_load_type (struct disassemble_info* info)
185
6.41k
{
186
6.41k
  struct _load_opcode
187
6.41k
  {
188
6.41k
    unsigned long opcode;
189
6.41k
    char *name;
190
6.41k
  }
191
6.41k
  dlx_load_opcode[] =
192
6.41k
  {
193
6.41k
    { OPC(LHIOP),   "lhi" },  /* Load HI to register.           */
194
6.41k
    { OPC(LBOP),     "lb" },  /* load byte sign extended.       */
195
6.41k
    { OPC(LBUOP),   "lbu" },  /* load byte unsigned.            */
196
6.41k
    { OPC(LSBUOP),"ldstbu"},  /* load store byte unsigned.      */
197
6.41k
    { OPC(LHOP),     "lh" },  /* load halfword sign extended.   */
198
6.41k
    { OPC(LHUOP),   "lhu" },  /* load halfword unsigned.        */
199
6.41k
    { OPC(LSHUOP),"ldsthu"},  /* load store halfword unsigned.  */
200
6.41k
    { OPC(LWOP),     "lw" },  /* load word.                     */
201
6.41k
    { OPC(LSWOP), "ldstw" }   /* load store word.               */
202
6.41k
  };
203
6.41k
  int dlx_load_opcode_num =
204
6.41k
    (sizeof dlx_load_opcode) / (sizeof dlx_load_opcode[0]);
205
6.41k
  int idx;
206
207
58.0k
  for (idx = 0 ; idx < dlx_load_opcode_num; idx++)
208
52.4k
    if (dlx_load_opcode[idx].opcode == opc)
209
890
      {
210
890
  if (opc == OPC (LHIOP))
211
353
    {
212
353
      (*info->fprintf_func) (info->stream, "%s", dlx_load_opcode[idx].name);
213
353
      operand_deliminator (info, dlx_load_opcode[idx].name);
214
353
      (*info->fprintf_func) (info->stream, "r%d,", (int)rs2);
215
353
      (*info->fprintf_func) (info->stream, "0x%04x", (int)imm16);
216
353
    }
217
537
  else
218
537
    {
219
537
      (*info->fprintf_func) (info->stream, "%s", dlx_load_opcode[idx].name);
220
537
      operand_deliminator (info, dlx_load_opcode[idx].name);
221
537
      (*info->fprintf_func) (info->stream, "r%d,", (int)rs2);
222
537
      (*info->fprintf_func) (info->stream, "0x%04x[r%d]", (int)imm16, (int)rs1);
223
537
    }
224
225
890
  return (unsigned char) ILD_TYPE;
226
890
    }
227
228
5.52k
  return (unsigned char) NIL;
229
6.41k
}
230
231
/* Process the memory store opcode.  */
232
233
static unsigned char
234
dlx_store_type (struct disassemble_info* info)
235
5.52k
{
236
5.52k
  struct _store_opcode
237
5.52k
  {
238
5.52k
    unsigned long opcode;
239
5.52k
    char *name;
240
5.52k
  }
241
5.52k
  dlx_store_opcode[] =
242
5.52k
  {
243
5.52k
    { OPC(SBOP),     "sb" },  /* Store byte.      */
244
5.52k
    { OPC(SHOP),     "sh" },  /* Store halfword.  */
245
5.52k
    { OPC(SWOP),     "sw" },  /* Store word.      */
246
5.52k
  };
247
5.52k
  int dlx_store_opcode_num =
248
5.52k
    (sizeof dlx_store_opcode) / (sizeof dlx_store_opcode[0]);
249
5.52k
  int idx;
250
251
21.6k
  for (idx = 0 ; idx < dlx_store_opcode_num; idx++)
252
16.2k
    if (dlx_store_opcode[idx].opcode == opc)
253
184
      {
254
184
  (*info->fprintf_func) (info->stream, "%s", dlx_store_opcode[idx].name);
255
184
  operand_deliminator (info, dlx_store_opcode[idx].name);
256
184
  (*info->fprintf_func) (info->stream, "0x%04x[r%d],", (int)imm16, (int)rs1);
257
184
  (*info->fprintf_func) (info->stream, "r%d", (int)rs2);
258
184
  return (unsigned char) IST_TYPE;
259
184
      }
260
261
5.33k
  return (unsigned char) NIL;
262
5.52k
}
263
264
/* Process the Arithmetic and Logical I-TYPE opcode.  */
265
266
static unsigned char
267
dlx_aluI_type (struct disassemble_info* info)
268
5.33k
{
269
5.33k
  struct _aluI_opcode
270
5.33k
  {
271
5.33k
    unsigned long opcode;
272
5.33k
    char *name;
273
5.33k
  }
274
5.33k
  dlx_aluI_opcode[] =
275
5.33k
  {
276
5.33k
    { OPC(ADDIOP),   "addi"  },  /* Store byte.      */
277
5.33k
    { OPC(ADDUIOP),  "addui" },  /* Store halfword.  */
278
5.33k
    { OPC(SUBIOP),   "subi"  },  /* Store word.      */
279
5.33k
    { OPC(SUBUIOP),  "subui" },  /* Store word.      */
280
5.33k
    { OPC(ANDIOP),   "andi"  },  /* Store word.      */
281
5.33k
    { OPC(ORIOP),    "ori"   },  /* Store word.      */
282
5.33k
    { OPC(XORIOP),   "xori"  },  /* Store word.      */
283
5.33k
    { OPC(SLLIOP),   "slli"  },  /* Store word.      */
284
5.33k
    { OPC(SRAIOP),   "srai"  },  /* Store word.      */
285
5.33k
    { OPC(SRLIOP),   "srli"  },  /* Store word.      */
286
5.33k
    { OPC(SEQIOP),   "seqi"  },  /* Store word.      */
287
5.33k
    { OPC(SNEIOP),   "snei"  },  /* Store word.      */
288
5.33k
    { OPC(SLTIOP),   "slti"  },  /* Store word.      */
289
5.33k
    { OPC(SGTIOP),   "sgti"  },  /* Store word.      */
290
5.33k
    { OPC(SLEIOP),   "slei"  },  /* Store word.      */
291
5.33k
    { OPC(SGEIOP),   "sgei"  },  /* Store word.      */
292
5.33k
    { OPC(SEQUIOP),  "sequi" },  /* Store word.      */
293
5.33k
    { OPC(SNEUIOP),  "sneui" },  /* Store word.      */
294
5.33k
    { OPC(SLTUIOP),  "sltui" },  /* Store word.      */
295
5.33k
    { OPC(SGTUIOP),  "sgtui" },  /* Store word.      */
296
5.33k
    { OPC(SLEUIOP),  "sleui" },  /* Store word.      */
297
5.33k
    { OPC(SGEUIOP),  "sgeui" },  /* Store word.      */
298
#if 0
299
    { OPC(MVTSOP),   "mvts"  },  /* Store word.      */
300
    { OPC(MVFSOP),   "mvfs"  },  /* Store word.      */
301
#endif
302
5.33k
  };
303
5.33k
  int dlx_aluI_opcode_num =
304
5.33k
    (sizeof dlx_aluI_opcode) / (sizeof dlx_aluI_opcode[0]);
305
5.33k
  int idx;
306
307
102k
  for (idx = 0 ; idx < dlx_aluI_opcode_num; idx++)
308
98.9k
    if (dlx_aluI_opcode[idx].opcode == opc)
309
1.47k
      {
310
1.47k
  (*info->fprintf_func) (info->stream, "%s", dlx_aluI_opcode[idx].name);
311
1.47k
  operand_deliminator (info, dlx_aluI_opcode[idx].name);
312
1.47k
  (*info->fprintf_func) (info->stream, "r%d,", (int)rs2);
313
1.47k
  (*info->fprintf_func) (info->stream, "r%d,", (int)rs1);
314
1.47k
  (*info->fprintf_func) (info->stream, "0x%04x", (int)imm16);
315
316
1.47k
  return (unsigned char) IAL_TYPE;
317
1.47k
      }
318
319
3.85k
  return (unsigned char) NIL;
320
5.33k
}
321
322
/* Process the branch instruction.  */
323
324
static unsigned char
325
dlx_br_type (struct disassemble_info* info)
326
3.85k
{
327
3.85k
  struct _br_opcode
328
3.85k
  {
329
3.85k
    unsigned long opcode;
330
3.85k
    char *name;
331
3.85k
  }
332
3.85k
  dlx_br_opcode[] =
333
3.85k
  {
334
3.85k
    { OPC(BEQOP), "beqz" }, /* Store byte.  */
335
3.85k
    { OPC(BNEOP), "bnez" }  /* Store halfword.  */
336
3.85k
  };
337
3.85k
  int dlx_br_opcode_num =
338
3.85k
    (sizeof dlx_br_opcode) / (sizeof dlx_br_opcode[0]);
339
3.85k
  int idx;
340
341
10.2k
  for (idx = 0 ; idx < dlx_br_opcode_num; idx++)
342
7.08k
    if (dlx_br_opcode[idx].opcode == opc)
343
705
      {
344
705
  if (imm16 & 0x00008000)
345
151
    imm16 |= 0xFFFF0000;
346
347
705
  imm16 += (current_insn_addr + 4);
348
705
  (*info->fprintf_func) (info->stream, "%s", dlx_br_opcode[idx].name);
349
705
  operand_deliminator (info, dlx_br_opcode[idx].name);
350
705
  (*info->fprintf_func) (info->stream, "r%d,", (int) rs1);
351
705
  (*info->fprintf_func) (info->stream, "0x%08x", (int) imm16);
352
353
705
  return (unsigned char) IBR_TYPE;
354
705
      }
355
356
3.15k
  return (unsigned char) NIL;
357
3.85k
}
358
359
/* Process the jump instruction.  */
360
361
static unsigned char
362
dlx_jmp_type (struct disassemble_info* info)
363
3.15k
{
364
3.15k
  struct _jmp_opcode
365
3.15k
  {
366
3.15k
    unsigned long opcode;
367
3.15k
    char *name;
368
3.15k
  }
369
3.15k
  dlx_jmp_opcode[] =
370
3.15k
  {
371
3.15k
    { OPC(JOP),         "j" },  /* Store byte.      */
372
3.15k
    { OPC(JALOP),     "jal" },  /* Store halfword.  */
373
3.15k
    { OPC(BREAKOP), "break" },  /* Store halfword.  */
374
3.15k
    { OPC(TRAPOP),   "trap" },  /* Store halfword.  */
375
3.15k
    { OPC(RFEOP),     "rfe" }   /* Store halfword.  */
376
3.15k
  };
377
3.15k
  int dlx_jmp_opcode_num =
378
3.15k
    (sizeof dlx_jmp_opcode) / (sizeof dlx_jmp_opcode[0]);
379
3.15k
  int idx;
380
381
15.5k
  for (idx = 0 ; idx < dlx_jmp_opcode_num; idx++)
382
13.3k
    if (dlx_jmp_opcode[idx].opcode == opc)
383
918
      {
384
918
  if (imm26 & 0x02000000)
385
281
    imm26 |= 0xFC000000;
386
387
918
  imm26 += (current_insn_addr + 4);
388
389
918
  (*info->fprintf_func) (info->stream, "%s", dlx_jmp_opcode[idx].name);
390
918
  operand_deliminator (info, dlx_jmp_opcode[idx].name);
391
918
  (*info->fprintf_func) (info->stream, "0x%08x", (int)imm26);
392
393
918
  return (unsigned char) IJ_TYPE;
394
918
      }
395
396
2.23k
  return (unsigned char) NIL;
397
3.15k
}
398
399
/* Process the jump register instruction.  */
400
401
static unsigned char
402
dlx_jr_type (struct disassemble_info* info)
403
2.23k
{
404
2.23k
  struct _jr_opcode
405
2.23k
  {
406
2.23k
    unsigned long opcode;
407
2.23k
    char *name;
408
2.23k
  }
409
2.23k
  dlx_jr_opcode[] =
410
2.23k
  {
411
2.23k
    { OPC(JROP),   "jr"    },  /* Store byte.  */
412
2.23k
    { OPC(JALROP), "jalr"  }   /* Store halfword.  */
413
2.23k
  };
414
2.23k
  int dlx_jr_opcode_num =
415
2.23k
    (sizeof dlx_jr_opcode) / (sizeof dlx_jr_opcode[0]);
416
2.23k
  int idx;
417
418
5.85k
  for (idx = 0 ; idx < dlx_jr_opcode_num; idx++)
419
4.27k
    if (dlx_jr_opcode[idx].opcode == opc)
420
657
      {
421
657
  (*info->fprintf_func) (info->stream, "%s", dlx_jr_opcode[idx].name);
422
657
  operand_deliminator (info, dlx_jr_opcode[idx].name);
423
657
  (*info->fprintf_func) (info->stream, "r%d", (int)rs1);
424
657
  return (unsigned char) IJR_TYPE;
425
657
      }
426
427
1.57k
  return (unsigned char) NIL;
428
2.23k
}
429
430
typedef unsigned char (* dlx_insn) (struct disassemble_info *);
431
432
/* This is the main DLX insn handling routine.  */
433
434
int
435
print_insn_dlx (bfd_vma memaddr, struct disassemble_info* info)
436
6.96k
{
437
6.96k
  bfd_byte buffer[4];
438
6.96k
  int insn_idx;
439
6.96k
  unsigned long insn_word;
440
6.96k
  dlx_insn dlx_insn_type[] =
441
6.96k
  {
442
6.96k
    dlx_r_type,
443
6.96k
    dlx_load_type,
444
6.96k
    dlx_store_type,
445
6.96k
    dlx_aluI_type,
446
6.96k
    dlx_br_type,
447
6.96k
    dlx_jmp_type,
448
6.96k
    dlx_jr_type,
449
6.96k
    (dlx_insn) NULL
450
6.96k
  };
451
6.96k
  int dlx_insn_type_num = ((sizeof dlx_insn_type) / (sizeof (dlx_insn))) - 1;
452
6.96k
  int status =
453
6.96k
    (*info->read_memory_func) (memaddr, (bfd_byte *) &buffer[0], 4, info);
454
455
6.96k
  if (status != 0)
456
65
    {
457
65
      (*info->memory_error_func) (status, memaddr, info);
458
65
      return -1;
459
65
    }
460
461
  /* Now decode the insn    */
462
6.90k
  insn_word = bfd_getb32 (buffer);
463
6.90k
  opc  = dlx_get_opcode (insn_word);
464
6.90k
  rs1  = dlx_get_rs1 (insn_word);
465
6.90k
  rs2  = dlx_get_rs2 (insn_word);
466
6.90k
  rd   = dlx_get_rdR (insn_word);
467
6.90k
  func = dlx_get_func (insn_word);
468
6.90k
  imm16= dlx_get_imm16 (insn_word);
469
6.90k
  imm26= dlx_get_imm26 (insn_word);
470
471
#if 0
472
  printf ("print_insn_big_dlx: opc = 0x%02x\n"
473
    "                    rs1 = 0x%02x\n"
474
    "                    rs2 = 0x%02x\n"
475
    "                    rd  = 0x%02x\n"
476
    "                  func  = 0x%08x\n"
477
    "                 imm16  = 0x%08x\n"
478
    "                 imm26  = 0x%08x\n",
479
    opc, rs1, rs2, rd, func, imm16, imm26);
480
#endif
481
482
  /* Scan through all the insn type and print the insn out.  */
483
6.90k
  current_insn_addr = (unsigned long) memaddr;
484
485
34.9k
  for (insn_idx = 0; dlx_insn_type[insn_idx] != 0x0; insn_idx++)
486
33.4k
    switch ((dlx_insn_type[insn_idx]) (info))
487
33.4k
      {
488
  /* Found the correct opcode   */
489
467
      case R_TYPE:
490
1.35k
      case ILD_TYPE:
491
1.54k
      case IST_TYPE:
492
3.01k
      case IAL_TYPE:
493
3.72k
      case IBR_TYPE:
494
4.64k
      case IJ_TYPE:
495
5.29k
      case IJR_TYPE:
496
5.29k
  return 4;
497
498
  /* Wrong insn type check next one. */
499
0
      default:
500
28.0k
      case NIL:
501
28.0k
  continue;
502
503
  /* All rest of the return code are not recongnized, treat it as error */
504
  /* we should never get here,  I hope! */
505
26
      case R_ERROR:
506
26
  return -1;
507
33.4k
      }
508
509
1.57k
  if (insn_idx ==  dlx_insn_type_num)
510
    /* Well, does not recoganize this opcode.  */
511
1.57k
    (*info->fprintf_func) (info->stream, "<%s>", "Unrecognized Opcode");
512
513
1.57k
  return 4;
514
6.90k
}