Coverage Report

Created: 2025-06-24 06:45

/src/binutils-gdb/opcodes/m32c-opc.c
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Count
Source (jump to first uncovered line)
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/* DO NOT EDIT!  -*- buffer-read-only: t -*- vi:set ro:  */
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/* Instruction opcode table for m32c.
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4
THIS FILE IS MACHINE GENERATED WITH CGEN.
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Copyright (C) 1996-2025 Free Software Foundation, Inc.
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8
This file is part of the GNU Binutils and/or GDB, the GNU debugger.
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   This file is free software; you can redistribute it and/or modify
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   it under the terms of the GNU General Public License as published by
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   the Free Software Foundation; either version 3, or (at your option)
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   any later version.
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   It is distributed in the hope that it will be useful, but WITHOUT
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   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
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   License for more details.
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   You should have received a copy of the GNU General Public License along
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   with this program; if not, write to the Free Software Foundation, Inc.,
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   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
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24
*/
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26
#include "sysdep.h"
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#include "ansidecl.h"
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#include "bfd.h"
29
#include "symcat.h"
30
#include "m32c-desc.h"
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#include "m32c-opc.h"
32
#include "libiberty.h"
33
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/* -- opc.c */
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static unsigned int
36
m32c_asm_hash (const char *mnem)
37
0
{
38
0
  unsigned int h;
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40
  /* The length of the mnemonic for the Jcnd insns is 1.  Hash jsri.  */
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0
  if (mnem[0] == 'j' && mnem[1] != 's')
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0
    return 'j';
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44
  /* Don't hash scCND  */
45
0
  if (mnem[0] == 's' && mnem[1] == 'c')
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0
    return 's';
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48
  /* Don't hash bmCND  */
49
0
  if (mnem[0] == 'b' && mnem[1] == 'm')
50
0
    return 'b';
51
52
0
  for (h = 0; *mnem && *mnem != ' ' && *mnem != ':'; ++mnem)
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0
    h += *mnem;
54
0
  return h % CGEN_ASM_HASH_SIZE;
55
0
}
56

57
/* -- asm.c */
58
/* The hash functions are recorded here to help keep assembler code out of
59
   the disassembler and vice versa.  */
60
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static int asm_hash_insn_p        (const CGEN_INSN *);
62
static unsigned int asm_hash_insn (const char *);
63
static int dis_hash_insn_p        (const CGEN_INSN *);
64
static unsigned int dis_hash_insn (const char *, CGEN_INSN_INT);
65
66
/* Instruction formats.  */
67
68
#define F(f) & m32c_cgen_ifld_table[M32C_##f]
69
static const CGEN_IFMT ifmt_empty ATTRIBUTE_UNUSED = {
70
  0, 0, 0x0, { { 0 } }
71
};
72
73
static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
74
  32, 32, 0xffff2f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
75
};
76
77
static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
78
  32, 32, 0xffff3f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
79
};
80
81
static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
82
  32, 32, 0xffff3f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
83
};
84
85
static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
86
  32, 32, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
87
};
88
89
static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
90
  32, 32, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
91
};
92
93
static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
94
  32, 32, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
95
};
96
97
static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = {
98
  32, 32, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
99
};
100
101
static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = {
102
  32, 32, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
103
};
104
105
static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = {
106
  32, 32, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
107
};
108
109
static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
110
  32, 40, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
111
};
112
113
static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
114
  32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
115
};
116
117
static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
118
  32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
119
};
120
121
static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
122
  32, 48, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
123
};
124
125
static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
126
  32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
127
};
128
129
static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
130
  32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
131
};
132
133
static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
134
  32, 56, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
135
};
136
137
static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
138
  32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
139
};
140
141
static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
142
  32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
143
};
144
145
static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
146
  32, 40, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
147
};
148
149
static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
150
  32, 40, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
151
};
152
153
static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
154
  32, 40, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
155
};
156
157
static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
158
  32, 48, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
159
};
160
161
static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
162
  32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
163
};
164
165
static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
166
  32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
167
};
168
169
static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
170
  32, 40, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
171
};
172
173
static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
174
  32, 40, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
175
};
176
177
static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
178
  32, 40, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
179
};
180
181
static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
182
  32, 48, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
183
};
184
185
static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
186
  32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
187
};
188
189
static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
190
  32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
191
};
192
193
static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
194
  32, 48, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
195
};
196
197
static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
198
  32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
199
};
200
201
static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
202
  32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
203
};
204
205
static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
206
  32, 56, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
207
};
208
209
static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
210
  32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
211
};
212
213
static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
214
  32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
215
};
216
217
static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
218
  32, 40, 0xffff2f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
219
};
220
221
static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
222
  32, 40, 0xffff3f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
223
};
224
225
static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
226
  32, 40, 0xffff3f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
227
};
228
229
static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
230
  32, 40, 0xffff3f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
231
};
232
233
static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
234
  32, 40, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
235
};
236
237
static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
238
  32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
239
};
240
241
static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
242
  32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
243
};
244
245
static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
246
  32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
247
};
248
249
static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = {
250
  32, 40, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
251
};
252
253
static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = {
254
  32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
255
};
256
257
static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = {
258
  32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
259
};
260
261
static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = {
262
  32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
263
};
264
265
static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
266
  32, 48, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
267
};
268
269
static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
270
  32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
271
};
272
273
static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
274
  32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
275
};
276
277
static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
278
  32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
279
};
280
281
static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
282
  32, 56, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
283
};
284
285
static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
286
  32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
287
};
288
289
static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
290
  32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
291
};
292
293
static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
294
  32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
295
};
296
297
static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
298
  32, 64, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
299
};
300
301
static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
302
  32, 64, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
303
};
304
305
static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
306
  32, 64, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
307
};
308
309
static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
310
  32, 64, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
311
};
312
313
static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
314
  32, 48, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
315
};
316
317
static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
318
  32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
319
};
320
321
static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
322
  32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
323
};
324
325
static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
326
  32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
327
};
328
329
static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
330
  32, 56, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
331
};
332
333
static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
334
  32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
335
};
336
337
static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
338
  32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
339
};
340
341
static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
342
  32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
343
};
344
345
static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
346
  32, 48, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
347
};
348
349
static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
350
  32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
351
};
352
353
static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
354
  32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
355
};
356
357
static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
358
  32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
359
};
360
361
static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
362
  32, 56, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
363
};
364
365
static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
366
  32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
367
};
368
369
static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
370
  32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
371
};
372
373
static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
374
  32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
375
};
376
377
static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
378
  32, 56, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
379
};
380
381
static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
382
  32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
383
};
384
385
static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
386
  32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
387
};
388
389
static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
390
  32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
391
};
392
393
static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
394
  32, 64, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
395
};
396
397
static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
398
  32, 64, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
399
};
400
401
static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
402
  32, 64, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
403
};
404
405
static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
406
  32, 64, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
407
};
408
409
static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
410
  32, 48, 0xffff2f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
411
};
412
413
static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
414
  32, 48, 0xffff3f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
415
};
416
417
static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
418
  32, 48, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
419
};
420
421
static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
422
  32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
423
};
424
425
static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = {
426
  32, 48, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
427
};
428
429
static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = {
430
  32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
431
};
432
433
static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
434
  32, 56, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_48_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
435
};
436
437
static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
438
  32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_48_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
439
};
440
441
static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
442
  32, 64, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_48_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
443
};
444
445
static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
446
  32, 64, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_48_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
447
};
448
449
static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
450
  32, 72, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_48_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
451
};
452
453
static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
454
  32, 72, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_48_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
455
};
456
457
static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
458
  32, 56, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
459
};
460
461
static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
462
  32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
463
};
464
465
static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
466
  32, 64, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
467
};
468
469
static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
470
  32, 64, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
471
};
472
473
static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
474
  32, 56, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
475
};
476
477
static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
478
  32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
479
};
480
481
static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
482
  32, 64, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
483
};
484
485
static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
486
  32, 64, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
487
};
488
489
static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
490
  32, 64, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
491
};
492
493
static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
494
  32, 64, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
495
};
496
497
static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
498
  32, 72, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
499
};
500
501
static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
502
  32, 72, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
503
};
504
505
static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
506
  24, 24, 0xffff0f, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
507
};
508
509
static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
510
  24, 24, 0xffff2f, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
511
};
512
513
static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
514
  24, 24, 0xffff8f, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
515
};
516
517
static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
518
  24, 24, 0xffffaf, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
519
};
520
521
static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = {
522
  24, 24, 0xffff8f, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
523
};
524
525
static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = {
526
  24, 24, 0xffffaf, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
527
};
528
529
static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
530
  32, 32, 0xffff8f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
531
};
532
533
static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
534
  32, 32, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
535
};
536
537
static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
538
  32, 40, 0xffff8f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
539
};
540
541
static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
542
  32, 40, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
543
};
544
545
static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
546
  32, 48, 0xffff8f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
547
};
548
549
static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
550
  32, 48, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
551
};
552
553
static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
554
  32, 32, 0xffffcf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
555
};
556
557
static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
558
  32, 32, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
559
};
560
561
static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
562
  32, 40, 0xffffcf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
563
};
564
565
static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
566
  32, 40, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
567
};
568
569
static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
570
  32, 32, 0xffffcf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
571
};
572
573
static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
574
  32, 32, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
575
};
576
577
static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
578
  32, 40, 0xffffcf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
579
};
580
581
static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
582
  32, 40, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
583
};
584
585
static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
586
  32, 40, 0xffffcf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
587
};
588
589
static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
590
  32, 40, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
591
};
592
593
static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
594
  32, 48, 0xffffcf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
595
};
596
597
static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
598
  32, 48, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
599
};
600
601
static const CGEN_IFMT ifmt_exts32_w_16_ExtUnprefixed_dst32_Rn_direct_ExtUnprefixed_HI ATTRIBUTE_UNUSED = {
602
  16, 16, 0xffbf, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_RN_EXT_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
603
};
604
605
static const CGEN_IFMT ifmt_exts32_w_16_ExtUnprefixed_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
606
  16, 16, 0xffbf, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
607
};
608
609
static const CGEN_IFMT ifmt_exts32_w_16_ExtUnprefixed_dst32_An_indirect_ExtUnprefixed_HI ATTRIBUTE_UNUSED = {
610
  16, 16, 0xffbf, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
611
};
612
613
static const CGEN_IFMT ifmt_exts32_w_16_ExtUnprefixed_dst32_16_8_An_relative_ExtUnprefixed_HI ATTRIBUTE_UNUSED = {
614
  24, 24, 0xffbf00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
615
};
616
617
static const CGEN_IFMT ifmt_exts32_w_16_ExtUnprefixed_dst32_16_16_An_relative_ExtUnprefixed_HI ATTRIBUTE_UNUSED = {
618
  32, 32, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
619
};
620
621
static const CGEN_IFMT ifmt_exts32_w_16_ExtUnprefixed_dst32_16_24_An_relative_ExtUnprefixed_HI ATTRIBUTE_UNUSED = {
622
  32, 40, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
623
};
624
625
static const CGEN_IFMT ifmt_exts32_w_16_ExtUnprefixed_dst32_16_8_SB_relative_ExtUnprefixed_HI ATTRIBUTE_UNUSED = {
626
  24, 24, 0xffff00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
627
};
628
629
static const CGEN_IFMT ifmt_exts32_w_16_ExtUnprefixed_dst32_16_16_SB_relative_ExtUnprefixed_HI ATTRIBUTE_UNUSED = {
630
  32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
631
};
632
633
static const CGEN_IFMT ifmt_exts32_w_16_ExtUnprefixed_dst32_16_8_FB_relative_ExtUnprefixed_HI ATTRIBUTE_UNUSED = {
634
  24, 24, 0xffff00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
635
};
636
637
static const CGEN_IFMT ifmt_exts32_w_16_ExtUnprefixed_dst32_16_16_FB_relative_ExtUnprefixed_HI ATTRIBUTE_UNUSED = {
638
  32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
639
};
640
641
static const CGEN_IFMT ifmt_exts32_w_16_ExtUnprefixed_dst32_16_16_absolute_ExtUnprefixed_HI ATTRIBUTE_UNUSED = {
642
  32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
643
};
644
645
static const CGEN_IFMT ifmt_exts32_w_16_ExtUnprefixed_dst32_16_24_absolute_ExtUnprefixed_HI ATTRIBUTE_UNUSED = {
646
  32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
647
};
648
649
static const CGEN_IFMT ifmt_exts32_b_16_ExtUnprefixed_dst32_Rn_direct_ExtUnprefixed_QI ATTRIBUTE_UNUSED = {
650
  16, 16, 0xffbf, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_RN_EXT_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
651
};
652
653
static const CGEN_IFMT ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
654
  16, 16, 0xffbf, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
655
};
656
657
static const CGEN_IFMT ifmt_exts32_b_16_ExtUnprefixed_dst32_An_indirect_ExtUnprefixed_QI ATTRIBUTE_UNUSED = {
658
  16, 16, 0xffbf, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
659
};
660
661
static const CGEN_IFMT ifmt_exts32_b_16_ExtUnprefixed_dst32_16_8_An_relative_ExtUnprefixed_QI ATTRIBUTE_UNUSED = {
662
  24, 24, 0xffbf00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
663
};
664
665
static const CGEN_IFMT ifmt_exts32_b_16_ExtUnprefixed_dst32_16_16_An_relative_ExtUnprefixed_QI ATTRIBUTE_UNUSED = {
666
  32, 32, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
667
};
668
669
static const CGEN_IFMT ifmt_exts32_b_16_ExtUnprefixed_dst32_16_24_An_relative_ExtUnprefixed_QI ATTRIBUTE_UNUSED = {
670
  32, 40, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
671
};
672
673
static const CGEN_IFMT ifmt_exts32_b_16_ExtUnprefixed_dst32_16_8_SB_relative_ExtUnprefixed_QI ATTRIBUTE_UNUSED = {
674
  24, 24, 0xffff00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
675
};
676
677
static const CGEN_IFMT ifmt_exts32_b_16_ExtUnprefixed_dst32_16_16_SB_relative_ExtUnprefixed_QI ATTRIBUTE_UNUSED = {
678
  32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
679
};
680
681
static const CGEN_IFMT ifmt_exts32_b_16_ExtUnprefixed_dst32_16_8_FB_relative_ExtUnprefixed_QI ATTRIBUTE_UNUSED = {
682
  24, 24, 0xffff00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
683
};
684
685
static const CGEN_IFMT ifmt_exts32_b_16_ExtUnprefixed_dst32_16_16_FB_relative_ExtUnprefixed_QI ATTRIBUTE_UNUSED = {
686
  32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
687
};
688
689
static const CGEN_IFMT ifmt_exts32_b_16_ExtUnprefixed_dst32_16_16_absolute_ExtUnprefixed_QI ATTRIBUTE_UNUSED = {
690
  32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
691
};
692
693
static const CGEN_IFMT ifmt_exts32_b_16_ExtUnprefixed_dst32_16_24_absolute_ExtUnprefixed_QI ATTRIBUTE_UNUSED = {
694
  32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
695
};
696
697
static const CGEN_IFMT ifmt_exts16_b_16_Ext_dst16_Rn_direct_Ext_QI ATTRIBUTE_UNUSED = {
698
  16, 16, 0xfffd, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN_EXT) }, { F (F_15_1) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
699
};
700
701
static const CGEN_IFMT ifmt_exts16_b_16_Ext_dst16_An_indirect_Ext_QI ATTRIBUTE_UNUSED = {
702
  16, 16, 0xfffe, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
703
};
704
705
static const CGEN_IFMT ifmt_exts16_b_16_Ext_dst16_16_8_An_relative_Ext_QI ATTRIBUTE_UNUSED = {
706
  24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
707
};
708
709
static const CGEN_IFMT ifmt_exts16_b_16_Ext_dst16_16_16_An_relative_Ext_QI ATTRIBUTE_UNUSED = {
710
  32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
711
};
712
713
static const CGEN_IFMT ifmt_exts16_b_16_Ext_dst16_16_8_SB_relative_Ext_QI ATTRIBUTE_UNUSED = {
714
  24, 24, 0xffff00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
715
};
716
717
static const CGEN_IFMT ifmt_exts16_b_16_Ext_dst16_16_16_SB_relative_Ext_QI ATTRIBUTE_UNUSED = {
718
  32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
719
};
720
721
static const CGEN_IFMT ifmt_exts16_b_16_Ext_dst16_16_8_FB_relative_Ext_QI ATTRIBUTE_UNUSED = {
722
  24, 24, 0xffff00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
723
};
724
725
static const CGEN_IFMT ifmt_exts16_b_16_Ext_dst16_16_16_absolute_Ext_QI ATTRIBUTE_UNUSED = {
726
  32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
727
};
728
729
static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
730
  24, 24, 0xff2f00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
731
};
732
733
static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
734
  24, 24, 0xff3f00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
735
};
736
737
static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
738
  24, 24, 0xff3f00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
739
};
740
741
static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
742
  24, 24, 0xffaf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
743
};
744
745
static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
746
  24, 24, 0xffbf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
747
};
748
749
static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
750
  24, 24, 0xffbf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
751
};
752
753
static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI ATTRIBUTE_UNUSED = {
754
  24, 24, 0xffaf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
755
};
756
757
static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI ATTRIBUTE_UNUSED = {
758
  24, 24, 0xffbf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
759
};
760
761
static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI ATTRIBUTE_UNUSED = {
762
  24, 24, 0xffbf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
763
};
764
765
static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
766
  32, 32, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
767
};
768
769
static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
770
  32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
771
};
772
773
static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
774
  32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
775
};
776
777
static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
778
  32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
779
};
780
781
static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
782
  32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
783
};
784
785
static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
786
  32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
787
};
788
789
static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
790
  32, 48, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
791
};
792
793
static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
794
  32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
795
};
796
797
static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
798
  32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
799
};
800
801
static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
802
  32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
803
};
804
805
static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
806
  32, 32, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
807
};
808
809
static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
810
  32, 32, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
811
};
812
813
static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
814
  32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
815
};
816
817
static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
818
  32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
819
};
820
821
static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
822
  32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
823
};
824
825
static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
826
  32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
827
};
828
829
static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
830
  32, 32, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
831
};
832
833
static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
834
  32, 32, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
835
};
836
837
static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
838
  32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
839
};
840
841
static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
842
  32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
843
};
844
845
static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
846
  32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
847
};
848
849
static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
850
  32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
851
};
852
853
static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
854
  32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
855
};
856
857
static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
858
  32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
859
};
860
861
static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
862
  32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
863
};
864
865
static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
866
  32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
867
};
868
869
static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
870
  32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
871
};
872
873
static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
874
  32, 32, 0xff2f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
875
};
876
877
static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
878
  32, 32, 0xff3f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
879
};
880
881
static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
882
  32, 32, 0xff3f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
883
};
884
885
static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
886
  32, 32, 0xff3f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
887
};
888
889
static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
890
  32, 32, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
891
};
892
893
static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
894
  32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
895
};
896
897
static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
898
  32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
899
};
900
901
static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_An_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
902
  32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
903
};
904
905
static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI ATTRIBUTE_UNUSED = {
906
  32, 32, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
907
};
908
909
static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI ATTRIBUTE_UNUSED = {
910
  32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
911
};
912
913
static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI ATTRIBUTE_UNUSED = {
914
  32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
915
};
916
917
static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI ATTRIBUTE_UNUSED = {
918
  32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
919
};
920
921
static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
922
  32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
923
};
924
925
static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
926
  32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
927
};
928
929
static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
930
  32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
931
};
932
933
static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
934
  32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
935
};
936
937
static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
938
  32, 48, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
939
};
940
941
static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
942
  32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
943
};
944
945
static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
946
  32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
947
};
948
949
static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
950
  32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
951
};
952
953
static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
954
  32, 56, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
955
};
956
957
static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
958
  32, 56, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
959
};
960
961
static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
962
  32, 56, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
963
};
964
965
static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
966
  32, 56, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
967
};
968
969
static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
970
  32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
971
};
972
973
static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
974
  32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
975
};
976
977
static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
978
  32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
979
};
980
981
static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
982
  32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
983
};
984
985
static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
986
  32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
987
};
988
989
static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
990
  32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
991
};
992
993
static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
994
  32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
995
};
996
997
static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
998
  32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
999
};
1000
1001
static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1002
  32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1003
};
1004
1005
static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1006
  32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1007
};
1008
1009
static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1010
  32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1011
};
1012
1013
static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1014
  32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1015
};
1016
1017
static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1018
  32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1019
};
1020
1021
static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1022
  32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1023
};
1024
1025
static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1026
  32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1027
};
1028
1029
static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1030
  32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1031
};
1032
1033
static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
1034
  32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1035
};
1036
1037
static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
1038
  32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1039
};
1040
1041
static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
1042
  32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1043
};
1044
1045
static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
1046
  32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1047
};
1048
1049
static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
1050
  32, 56, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1051
};
1052
1053
static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
1054
  32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1055
};
1056
1057
static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
1058
  32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1059
};
1060
1061
static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
1062
  32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1063
};
1064
1065
static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
1066
  32, 40, 0xff2f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1067
};
1068
1069
static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
1070
  32, 40, 0xff3f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1071
};
1072
1073
static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
1074
  32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1075
};
1076
1077
static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_An_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
1078
  32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1079
};
1080
1081
static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI ATTRIBUTE_UNUSED = {
1082
  32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1083
};
1084
1085
static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI ATTRIBUTE_UNUSED = {
1086
  32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1087
};
1088
1089
static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1090
  32, 48, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1091
};
1092
1093
static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1094
  32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1095
};
1096
1097
static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1098
  32, 56, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1099
};
1100
1101
static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1102
  32, 56, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1103
};
1104
1105
static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_24_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1106
  32, 64, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1107
};
1108
1109
static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_24_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1110
  32, 64, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1111
};
1112
1113
static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1114
  32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1115
};
1116
1117
static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1118
  32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1119
};
1120
1121
static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1122
  32, 56, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1123
};
1124
1125
static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1126
  32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1127
};
1128
1129
static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1130
  32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1131
};
1132
1133
static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1134
  32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1135
};
1136
1137
static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1138
  32, 56, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1139
};
1140
1141
static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1142
  32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1143
};
1144
1145
static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
1146
  32, 56, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1147
};
1148
1149
static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
1150
  32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1151
};
1152
1153
static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_24_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
1154
  32, 64, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1155
};
1156
1157
static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_24_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
1158
  32, 64, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1159
};
1160
1161
static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
1162
  16, 16, 0xff0f, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_HI) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1163
};
1164
1165
static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
1166
  16, 16, 0xff2f, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1167
};
1168
1169
static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
1170
  16, 16, 0xff2f, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1171
};
1172
1173
static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_An_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
1174
  16, 16, 0xff8f, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_HI) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1175
};
1176
1177
static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_An_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
1178
  16, 16, 0xffaf, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1179
};
1180
1181
static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_An_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
1182
  16, 16, 0xffaf, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1183
};
1184
1185
static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI ATTRIBUTE_UNUSED = {
1186
  16, 16, 0xff8f, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_HI) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1187
};
1188
1189
static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI ATTRIBUTE_UNUSED = {
1190
  16, 16, 0xffaf, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1191
};
1192
1193
static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI ATTRIBUTE_UNUSED = {
1194
  16, 16, 0xffaf, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1195
};
1196
1197
static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1198
  24, 24, 0xff8f00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_HI) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1199
};
1200
1201
static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1202
  24, 24, 0xffaf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1203
};
1204
1205
static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1206
  24, 24, 0xffaf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1207
};
1208
1209
static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1210
  32, 32, 0xff8f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_HI) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1211
};
1212
1213
static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1214
  32, 32, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1215
};
1216
1217
static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1218
  32, 32, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1219
};
1220
1221
static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1222
  32, 40, 0xff8f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_HI) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1223
};
1224
1225
static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1226
  32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1227
};
1228
1229
static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1230
  32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1231
};
1232
1233
static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1234
  24, 24, 0xffcf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_HI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1235
};
1236
1237
static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1238
  24, 24, 0xffef00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1239
};
1240
1241
static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1242
  24, 24, 0xffef00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1243
};
1244
1245
static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1246
  32, 32, 0xffcf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_HI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1247
};
1248
1249
static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1250
  32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1251
};
1252
1253
static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1254
  32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1255
};
1256
1257
static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1258
  24, 24, 0xffcf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_HI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1259
};
1260
1261
static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1262
  24, 24, 0xffef00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1263
};
1264
1265
static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1266
  24, 24, 0xffef00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1267
};
1268
1269
static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1270
  32, 32, 0xffcf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_HI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1271
};
1272
1273
static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1274
  32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1275
};
1276
1277
static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
1278
  32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1279
};
1280
1281
static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
1282
  32, 32, 0xffcf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_HI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1283
};
1284
1285
static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
1286
  32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1287
};
1288
1289
static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
1290
  32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1291
};
1292
1293
static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
1294
  32, 40, 0xffcf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_HI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1295
};
1296
1297
static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
1298
  32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1299
};
1300
1301
static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
1302
  32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1303
};
1304
1305
static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
1306
  24, 24, 0xff2f00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1307
};
1308
1309
static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
1310
  24, 24, 0xff3f00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1311
};
1312
1313
static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
1314
  24, 24, 0xff3f00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1315
};
1316
1317
static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
1318
  24, 24, 0xffaf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1319
};
1320
1321
static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
1322
  24, 24, 0xffbf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1323
};
1324
1325
static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
1326
  24, 24, 0xffbf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1327
};
1328
1329
static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI ATTRIBUTE_UNUSED = {
1330
  24, 24, 0xffaf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1331
};
1332
1333
static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI ATTRIBUTE_UNUSED = {
1334
  24, 24, 0xffbf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1335
};
1336
1337
static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI ATTRIBUTE_UNUSED = {
1338
  24, 24, 0xffbf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1339
};
1340
1341
static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1342
  32, 32, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1343
};
1344
1345
static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1346
  32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1347
};
1348
1349
static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1350
  32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1351
};
1352
1353
static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1354
  32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1355
};
1356
1357
static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1358
  32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1359
};
1360
1361
static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1362
  32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1363
};
1364
1365
static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1366
  32, 48, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1367
};
1368
1369
static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1370
  32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1371
};
1372
1373
static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1374
  32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1375
};
1376
1377
static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1378
  32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1379
};
1380
1381
static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1382
  32, 32, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1383
};
1384
1385
static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1386
  32, 32, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1387
};
1388
1389
static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1390
  32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1391
};
1392
1393
static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1394
  32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1395
};
1396
1397
static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1398
  32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1399
};
1400
1401
static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1402
  32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1403
};
1404
1405
static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1406
  32, 32, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1407
};
1408
1409
static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1410
  32, 32, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1411
};
1412
1413
static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1414
  32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1415
};
1416
1417
static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1418
  32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1419
};
1420
1421
static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1422
  32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1423
};
1424
1425
static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
1426
  32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1427
};
1428
1429
static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
1430
  32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1431
};
1432
1433
static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
1434
  32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1435
};
1436
1437
static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
1438
  32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1439
};
1440
1441
static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
1442
  32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1443
};
1444
1445
static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
1446
  32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1447
};
1448
1449
static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
1450
  32, 32, 0xff2f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1451
};
1452
1453
static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
1454
  32, 32, 0xff3f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1455
};
1456
1457
static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
1458
  32, 32, 0xff3f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1459
};
1460
1461
static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
1462
  32, 32, 0xff3f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1463
};
1464
1465
static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
1466
  32, 32, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1467
};
1468
1469
static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
1470
  32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1471
};
1472
1473
static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
1474
  32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1475
};
1476
1477
static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
1478
  32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1479
};
1480
1481
static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI ATTRIBUTE_UNUSED = {
1482
  32, 32, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1483
};
1484
1485
static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI ATTRIBUTE_UNUSED = {
1486
  32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1487
};
1488
1489
static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI ATTRIBUTE_UNUSED = {
1490
  32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1491
};
1492
1493
static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI ATTRIBUTE_UNUSED = {
1494
  32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1495
};
1496
1497
static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1498
  32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1499
};
1500
1501
static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1502
  32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1503
};
1504
1505
static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1506
  32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1507
};
1508
1509
static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1510
  32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1511
};
1512
1513
static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1514
  32, 48, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1515
};
1516
1517
static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1518
  32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1519
};
1520
1521
static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1522
  32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1523
};
1524
1525
static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1526
  32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1527
};
1528
1529
static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1530
  32, 56, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1531
};
1532
1533
static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1534
  32, 56, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1535
};
1536
1537
static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1538
  32, 56, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1539
};
1540
1541
static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1542
  32, 56, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1543
};
1544
1545
static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1546
  32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1547
};
1548
1549
static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1550
  32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1551
};
1552
1553
static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1554
  32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1555
};
1556
1557
static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1558
  32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1559
};
1560
1561
static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1562
  32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1563
};
1564
1565
static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1566
  32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1567
};
1568
1569
static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1570
  32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1571
};
1572
1573
static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1574
  32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1575
};
1576
1577
static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1578
  32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1579
};
1580
1581
static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1582
  32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1583
};
1584
1585
static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1586
  32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1587
};
1588
1589
static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1590
  32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1591
};
1592
1593
static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1594
  32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1595
};
1596
1597
static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1598
  32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1599
};
1600
1601
static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1602
  32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1603
};
1604
1605
static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1606
  32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1607
};
1608
1609
static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
1610
  32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1611
};
1612
1613
static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
1614
  32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1615
};
1616
1617
static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
1618
  32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1619
};
1620
1621
static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
1622
  32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1623
};
1624
1625
static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
1626
  32, 56, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1627
};
1628
1629
static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
1630
  32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1631
};
1632
1633
static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
1634
  32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1635
};
1636
1637
static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
1638
  32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1639
};
1640
1641
static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
1642
  32, 40, 0xff2f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1643
};
1644
1645
static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
1646
  32, 40, 0xff3f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1647
};
1648
1649
static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
1650
  32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1651
};
1652
1653
static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
1654
  32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1655
};
1656
1657
static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI ATTRIBUTE_UNUSED = {
1658
  32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1659
};
1660
1661
static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI ATTRIBUTE_UNUSED = {
1662
  32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1663
};
1664
1665
static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1666
  32, 48, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1667
};
1668
1669
static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1670
  32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1671
};
1672
1673
static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1674
  32, 56, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1675
};
1676
1677
static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1678
  32, 56, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1679
};
1680
1681
static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1682
  32, 64, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1683
};
1684
1685
static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1686
  32, 64, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1687
};
1688
1689
static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1690
  32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1691
};
1692
1693
static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1694
  32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1695
};
1696
1697
static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1698
  32, 56, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1699
};
1700
1701
static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1702
  32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1703
};
1704
1705
static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1706
  32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1707
};
1708
1709
static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1710
  32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1711
};
1712
1713
static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1714
  32, 56, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1715
};
1716
1717
static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1718
  32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1719
};
1720
1721
static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
1722
  32, 56, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1723
};
1724
1725
static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
1726
  32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1727
};
1728
1729
static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
1730
  32, 64, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1731
};
1732
1733
static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
1734
  32, 64, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1735
};
1736
1737
static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
1738
  16, 16, 0xff0f, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1739
};
1740
1741
static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
1742
  16, 16, 0xff2f, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1743
};
1744
1745
static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
1746
  16, 16, 0xff2f, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1747
};
1748
1749
static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
1750
  16, 16, 0xff8f, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1751
};
1752
1753
static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
1754
  16, 16, 0xffaf, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1755
};
1756
1757
static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
1758
  16, 16, 0xffaf, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1759
};
1760
1761
static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI ATTRIBUTE_UNUSED = {
1762
  16, 16, 0xff8f, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1763
};
1764
1765
static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI ATTRIBUTE_UNUSED = {
1766
  16, 16, 0xffaf, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1767
};
1768
1769
static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI ATTRIBUTE_UNUSED = {
1770
  16, 16, 0xffaf, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1771
};
1772
1773
static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1774
  24, 24, 0xff8f00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1775
};
1776
1777
static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1778
  24, 24, 0xffaf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1779
};
1780
1781
static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1782
  24, 24, 0xffaf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1783
};
1784
1785
static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1786
  32, 32, 0xff8f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1787
};
1788
1789
static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1790
  32, 32, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1791
};
1792
1793
static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1794
  32, 32, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1795
};
1796
1797
static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1798
  32, 40, 0xff8f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1799
};
1800
1801
static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1802
  32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1803
};
1804
1805
static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1806
  32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1807
};
1808
1809
static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1810
  24, 24, 0xffcf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1811
};
1812
1813
static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1814
  24, 24, 0xffef00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1815
};
1816
1817
static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1818
  24, 24, 0xffef00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1819
};
1820
1821
static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1822
  32, 32, 0xffcf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1823
};
1824
1825
static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1826
  32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1827
};
1828
1829
static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1830
  32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1831
};
1832
1833
static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1834
  24, 24, 0xffcf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1835
};
1836
1837
static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1838
  24, 24, 0xffef00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1839
};
1840
1841
static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1842
  24, 24, 0xffef00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1843
};
1844
1845
static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1846
  32, 32, 0xffcf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1847
};
1848
1849
static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1850
  32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1851
};
1852
1853
static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
1854
  32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1855
};
1856
1857
static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
1858
  32, 32, 0xffcf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1859
};
1860
1861
static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
1862
  32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1863
};
1864
1865
static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
1866
  32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1867
};
1868
1869
static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
1870
  32, 40, 0xffcf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1871
};
1872
1873
static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
1874
  32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1875
};
1876
1877
static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
1878
  32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
1879
};
1880
1881
static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_Rn_direct_HI ATTRIBUTE_UNUSED = {
1882
  24, 24, 0xffec00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
1883
};
1884
1885
static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_Rn_direct_HI ATTRIBUTE_UNUSED = {
1886
  24, 24, 0xfffc00, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U8) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
1887
};
1888
1889
static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_Rn_direct_HI ATTRIBUTE_UNUSED = {
1890
  24, 24, 0xfffc00, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
1891
};
1892
1893
static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_direct_HI ATTRIBUTE_UNUSED = {
1894
  24, 24, 0xffee00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
1895
};
1896
1897
static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_direct_HI ATTRIBUTE_UNUSED = {
1898
  24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
1899
};
1900
1901
static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_direct_HI ATTRIBUTE_UNUSED = {
1902
  24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
1903
};
1904
1905
static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_indirect_HI ATTRIBUTE_UNUSED = {
1906
  24, 24, 0xffee00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
1907
};
1908
1909
static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_indirect_HI ATTRIBUTE_UNUSED = {
1910
  24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
1911
};
1912
1913
static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_indirect_HI ATTRIBUTE_UNUSED = {
1914
  24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
1915
};
1916
1917
static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_An_relative_HI ATTRIBUTE_UNUSED = {
1918
  32, 32, 0xffee0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_24_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
1919
};
1920
1921
static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_An_relative_HI ATTRIBUTE_UNUSED = {
1922
  32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_24_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
1923
};
1924
1925
static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_An_relative_HI ATTRIBUTE_UNUSED = {
1926
  32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_24_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
1927
};
1928
1929
static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_An_relative_HI ATTRIBUTE_UNUSED = {
1930
  32, 40, 0xffee0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_24_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
1931
};
1932
1933
static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_An_relative_HI ATTRIBUTE_UNUSED = {
1934
  32, 40, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_24_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
1935
};
1936
1937
static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_An_relative_HI ATTRIBUTE_UNUSED = {
1938
  32, 40, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_24_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
1939
};
1940
1941
static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_SB_relative_HI ATTRIBUTE_UNUSED = {
1942
  32, 32, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_24_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
1943
};
1944
1945
static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_SB_relative_HI ATTRIBUTE_UNUSED = {
1946
  32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U8) }, { F (F_12_4) }, { F (F_DSP_24_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
1947
};
1948
1949
static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_SB_relative_HI ATTRIBUTE_UNUSED = {
1950
  32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { F (F_12_4) }, { F (F_DSP_24_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
1951
};
1952
1953
static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_SB_relative_HI ATTRIBUTE_UNUSED = {
1954
  32, 40, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_24_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
1955
};
1956
1957
static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_SB_relative_HI ATTRIBUTE_UNUSED = {
1958
  32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U8) }, { F (F_12_4) }, { F (F_DSP_24_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
1959
};
1960
1961
static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_SB_relative_HI ATTRIBUTE_UNUSED = {
1962
  32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { F (F_12_4) }, { F (F_DSP_24_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
1963
};
1964
1965
static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_FB_relative_HI ATTRIBUTE_UNUSED = {
1966
  32, 32, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_24_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
1967
};
1968
1969
static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_FB_relative_HI ATTRIBUTE_UNUSED = {
1970
  32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U8) }, { F (F_12_4) }, { F (F_DSP_24_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
1971
};
1972
1973
static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_FB_relative_HI ATTRIBUTE_UNUSED = {
1974
  32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { F (F_12_4) }, { F (F_DSP_24_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
1975
};
1976
1977
static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_absolute_HI ATTRIBUTE_UNUSED = {
1978
  32, 40, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_24_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
1979
};
1980
1981
static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_absolute_HI ATTRIBUTE_UNUSED = {
1982
  32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U8) }, { F (F_12_4) }, { F (F_DSP_24_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
1983
};
1984
1985
static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_absolute_HI ATTRIBUTE_UNUSED = {
1986
  32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { F (F_12_4) }, { F (F_DSP_24_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
1987
};
1988
1989
static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_Rn_direct_HI ATTRIBUTE_UNUSED = {
1990
  32, 32, 0xffec0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
1991
};
1992
1993
static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_Rn_direct_HI ATTRIBUTE_UNUSED = {
1994
  32, 32, 0xfffc0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
1995
};
1996
1997
static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_Rn_direct_HI ATTRIBUTE_UNUSED = {
1998
  32, 32, 0xfffc0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
1999
};
2000
2001
static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_direct_HI ATTRIBUTE_UNUSED = {
2002
  32, 32, 0xffee0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2003
};
2004
2005
static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_direct_HI ATTRIBUTE_UNUSED = {
2006
  32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2007
};
2008
2009
static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_direct_HI ATTRIBUTE_UNUSED = {
2010
  32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2011
};
2012
2013
static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_indirect_HI ATTRIBUTE_UNUSED = {
2014
  32, 32, 0xffee0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2015
};
2016
2017
static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_indirect_HI ATTRIBUTE_UNUSED = {
2018
  32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2019
};
2020
2021
static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_indirect_HI ATTRIBUTE_UNUSED = {
2022
  32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2023
};
2024
2025
static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_An_relative_HI ATTRIBUTE_UNUSED = {
2026
  32, 40, 0xffee0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_32_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2027
};
2028
2029
static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_An_relative_HI ATTRIBUTE_UNUSED = {
2030
  32, 40, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_32_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2031
};
2032
2033
static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_An_relative_HI ATTRIBUTE_UNUSED = {
2034
  32, 40, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_32_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2035
};
2036
2037
static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_An_relative_HI ATTRIBUTE_UNUSED = {
2038
  32, 48, 0xffee0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_32_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2039
};
2040
2041
static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_An_relative_HI ATTRIBUTE_UNUSED = {
2042
  32, 48, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_32_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2043
};
2044
2045
static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_An_relative_HI ATTRIBUTE_UNUSED = {
2046
  32, 48, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_32_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2047
};
2048
2049
static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_SB_relative_HI ATTRIBUTE_UNUSED = {
2050
  32, 40, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_32_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2051
};
2052
2053
static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_SB_relative_HI ATTRIBUTE_UNUSED = {
2054
  32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_4) }, { F (F_DSP_32_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2055
};
2056
2057
static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_SB_relative_HI ATTRIBUTE_UNUSED = {
2058
  32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_4) }, { F (F_DSP_32_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2059
};
2060
2061
static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_SB_relative_HI ATTRIBUTE_UNUSED = {
2062
  32, 48, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_32_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2063
};
2064
2065
static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_SB_relative_HI ATTRIBUTE_UNUSED = {
2066
  32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_4) }, { F (F_DSP_32_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2067
};
2068
2069
static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_SB_relative_HI ATTRIBUTE_UNUSED = {
2070
  32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_4) }, { F (F_DSP_32_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2071
};
2072
2073
static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_FB_relative_HI ATTRIBUTE_UNUSED = {
2074
  32, 40, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2075
};
2076
2077
static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_FB_relative_HI ATTRIBUTE_UNUSED = {
2078
  32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2079
};
2080
2081
static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_FB_relative_HI ATTRIBUTE_UNUSED = {
2082
  32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2083
};
2084
2085
static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_absolute_HI ATTRIBUTE_UNUSED = {
2086
  32, 48, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_32_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2087
};
2088
2089
static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_absolute_HI ATTRIBUTE_UNUSED = {
2090
  32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_4) }, { F (F_DSP_32_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2091
};
2092
2093
static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_absolute_HI ATTRIBUTE_UNUSED = {
2094
  32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_4) }, { F (F_DSP_32_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2095
};
2096
2097
static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_Rn_direct_HI ATTRIBUTE_UNUSED = {
2098
  16, 16, 0xffcc, { { F (F_0_4) }, { F (F_8_2) }, { F (F_SRC16_RN) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2099
};
2100
2101
static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_Rn_direct_HI ATTRIBUTE_UNUSED = {
2102
  16, 16, 0xffec, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2103
};
2104
2105
static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_Rn_direct_HI ATTRIBUTE_UNUSED = {
2106
  16, 16, 0xffec, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2107
};
2108
2109
static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_direct_HI ATTRIBUTE_UNUSED = {
2110
  16, 16, 0xffce, { { F (F_0_4) }, { F (F_8_2) }, { F (F_SRC16_RN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2111
};
2112
2113
static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_direct_HI ATTRIBUTE_UNUSED = {
2114
  16, 16, 0xffee, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2115
};
2116
2117
static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_direct_HI ATTRIBUTE_UNUSED = {
2118
  16, 16, 0xffee, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2119
};
2120
2121
static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_indirect_HI ATTRIBUTE_UNUSED = {
2122
  16, 16, 0xffce, { { F (F_0_4) }, { F (F_8_2) }, { F (F_SRC16_RN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2123
};
2124
2125
static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_indirect_HI ATTRIBUTE_UNUSED = {
2126
  16, 16, 0xffee, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2127
};
2128
2129
static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_indirect_HI ATTRIBUTE_UNUSED = {
2130
  16, 16, 0xffee, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2131
};
2132
2133
static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_An_relative_HI ATTRIBUTE_UNUSED = {
2134
  24, 24, 0xffce00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_SRC16_RN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2135
};
2136
2137
static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_An_relative_HI ATTRIBUTE_UNUSED = {
2138
  24, 24, 0xffee00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2139
};
2140
2141
static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_An_relative_HI ATTRIBUTE_UNUSED = {
2142
  24, 24, 0xffee00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2143
};
2144
2145
static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_An_relative_HI ATTRIBUTE_UNUSED = {
2146
  32, 32, 0xffce0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_SRC16_RN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2147
};
2148
2149
static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_An_relative_HI ATTRIBUTE_UNUSED = {
2150
  32, 32, 0xffee0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2151
};
2152
2153
static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_An_relative_HI ATTRIBUTE_UNUSED = {
2154
  32, 32, 0xffee0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2155
};
2156
2157
static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_SB_relative_HI ATTRIBUTE_UNUSED = {
2158
  24, 24, 0xffcf00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_SRC16_RN) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2159
};
2160
2161
static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_SB_relative_HI ATTRIBUTE_UNUSED = {
2162
  24, 24, 0xffef00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2163
};
2164
2165
static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_SB_relative_HI ATTRIBUTE_UNUSED = {
2166
  24, 24, 0xffef00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2167
};
2168
2169
static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_SB_relative_HI ATTRIBUTE_UNUSED = {
2170
  32, 32, 0xffcf0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_SRC16_RN) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2171
};
2172
2173
static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_SB_relative_HI ATTRIBUTE_UNUSED = {
2174
  32, 32, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2175
};
2176
2177
static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_SB_relative_HI ATTRIBUTE_UNUSED = {
2178
  32, 32, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2179
};
2180
2181
static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_FB_relative_HI ATTRIBUTE_UNUSED = {
2182
  24, 24, 0xffcf00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_SRC16_RN) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2183
};
2184
2185
static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_FB_relative_HI ATTRIBUTE_UNUSED = {
2186
  24, 24, 0xffef00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2187
};
2188
2189
static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_FB_relative_HI ATTRIBUTE_UNUSED = {
2190
  24, 24, 0xffef00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2191
};
2192
2193
static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_absolute_HI ATTRIBUTE_UNUSED = {
2194
  32, 32, 0xffcf0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_SRC16_RN) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2195
};
2196
2197
static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_absolute_HI ATTRIBUTE_UNUSED = {
2198
  32, 32, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2199
};
2200
2201
static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_absolute_HI ATTRIBUTE_UNUSED = {
2202
  32, 32, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2203
};
2204
2205
static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_Rn_direct_QI ATTRIBUTE_UNUSED = {
2206
  24, 24, 0xffec00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2207
};
2208
2209
static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_Rn_direct_QI ATTRIBUTE_UNUSED = {
2210
  24, 24, 0xfffc00, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U8) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2211
};
2212
2213
static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_Rn_direct_QI ATTRIBUTE_UNUSED = {
2214
  24, 24, 0xfffc00, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2215
};
2216
2217
static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_direct_QI ATTRIBUTE_UNUSED = {
2218
  24, 24, 0xffee00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2219
};
2220
2221
static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_direct_QI ATTRIBUTE_UNUSED = {
2222
  24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2223
};
2224
2225
static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_direct_QI ATTRIBUTE_UNUSED = {
2226
  24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2227
};
2228
2229
static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_indirect_QI ATTRIBUTE_UNUSED = {
2230
  24, 24, 0xffee00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2231
};
2232
2233
static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_indirect_QI ATTRIBUTE_UNUSED = {
2234
  24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2235
};
2236
2237
static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_indirect_QI ATTRIBUTE_UNUSED = {
2238
  24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2239
};
2240
2241
static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_An_relative_QI ATTRIBUTE_UNUSED = {
2242
  32, 32, 0xffee0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_24_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2243
};
2244
2245
static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_An_relative_QI ATTRIBUTE_UNUSED = {
2246
  32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_24_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2247
};
2248
2249
static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_An_relative_QI ATTRIBUTE_UNUSED = {
2250
  32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_24_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2251
};
2252
2253
static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_An_relative_QI ATTRIBUTE_UNUSED = {
2254
  32, 40, 0xffee0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_24_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2255
};
2256
2257
static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_An_relative_QI ATTRIBUTE_UNUSED = {
2258
  32, 40, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_24_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2259
};
2260
2261
static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_An_relative_QI ATTRIBUTE_UNUSED = {
2262
  32, 40, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_24_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2263
};
2264
2265
static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_SB_relative_QI ATTRIBUTE_UNUSED = {
2266
  32, 32, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_24_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2267
};
2268
2269
static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_SB_relative_QI ATTRIBUTE_UNUSED = {
2270
  32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U8) }, { F (F_12_4) }, { F (F_DSP_24_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2271
};
2272
2273
static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_SB_relative_QI ATTRIBUTE_UNUSED = {
2274
  32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { F (F_12_4) }, { F (F_DSP_24_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2275
};
2276
2277
static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_SB_relative_QI ATTRIBUTE_UNUSED = {
2278
  32, 40, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_24_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2279
};
2280
2281
static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_SB_relative_QI ATTRIBUTE_UNUSED = {
2282
  32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U8) }, { F (F_12_4) }, { F (F_DSP_24_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2283
};
2284
2285
static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_SB_relative_QI ATTRIBUTE_UNUSED = {
2286
  32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { F (F_12_4) }, { F (F_DSP_24_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2287
};
2288
2289
static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_FB_relative_QI ATTRIBUTE_UNUSED = {
2290
  32, 32, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_24_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2291
};
2292
2293
static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_FB_relative_QI ATTRIBUTE_UNUSED = {
2294
  32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U8) }, { F (F_12_4) }, { F (F_DSP_24_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2295
};
2296
2297
static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_FB_relative_QI ATTRIBUTE_UNUSED = {
2298
  32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { F (F_12_4) }, { F (F_DSP_24_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2299
};
2300
2301
static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_absolute_QI ATTRIBUTE_UNUSED = {
2302
  32, 40, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_24_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2303
};
2304
2305
static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_absolute_QI ATTRIBUTE_UNUSED = {
2306
  32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U8) }, { F (F_12_4) }, { F (F_DSP_24_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2307
};
2308
2309
static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_absolute_QI ATTRIBUTE_UNUSED = {
2310
  32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { F (F_12_4) }, { F (F_DSP_24_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2311
};
2312
2313
static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_Rn_direct_QI ATTRIBUTE_UNUSED = {
2314
  32, 32, 0xffec0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2315
};
2316
2317
static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_Rn_direct_QI ATTRIBUTE_UNUSED = {
2318
  32, 32, 0xfffc0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2319
};
2320
2321
static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_Rn_direct_QI ATTRIBUTE_UNUSED = {
2322
  32, 32, 0xfffc0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2323
};
2324
2325
static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_direct_QI ATTRIBUTE_UNUSED = {
2326
  32, 32, 0xffee0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2327
};
2328
2329
static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_direct_QI ATTRIBUTE_UNUSED = {
2330
  32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2331
};
2332
2333
static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_direct_QI ATTRIBUTE_UNUSED = {
2334
  32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2335
};
2336
2337
static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_indirect_QI ATTRIBUTE_UNUSED = {
2338
  32, 32, 0xffee0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2339
};
2340
2341
static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_indirect_QI ATTRIBUTE_UNUSED = {
2342
  32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2343
};
2344
2345
static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_indirect_QI ATTRIBUTE_UNUSED = {
2346
  32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2347
};
2348
2349
static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_An_relative_QI ATTRIBUTE_UNUSED = {
2350
  32, 40, 0xffee0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_32_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2351
};
2352
2353
static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_An_relative_QI ATTRIBUTE_UNUSED = {
2354
  32, 40, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_32_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2355
};
2356
2357
static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_An_relative_QI ATTRIBUTE_UNUSED = {
2358
  32, 40, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_32_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2359
};
2360
2361
static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_An_relative_QI ATTRIBUTE_UNUSED = {
2362
  32, 48, 0xffee0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_32_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2363
};
2364
2365
static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_An_relative_QI ATTRIBUTE_UNUSED = {
2366
  32, 48, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_32_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2367
};
2368
2369
static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_An_relative_QI ATTRIBUTE_UNUSED = {
2370
  32, 48, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_32_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2371
};
2372
2373
static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_SB_relative_QI ATTRIBUTE_UNUSED = {
2374
  32, 40, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_32_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2375
};
2376
2377
static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_SB_relative_QI ATTRIBUTE_UNUSED = {
2378
  32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_4) }, { F (F_DSP_32_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2379
};
2380
2381
static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_SB_relative_QI ATTRIBUTE_UNUSED = {
2382
  32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_4) }, { F (F_DSP_32_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2383
};
2384
2385
static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_SB_relative_QI ATTRIBUTE_UNUSED = {
2386
  32, 48, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_32_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2387
};
2388
2389
static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_SB_relative_QI ATTRIBUTE_UNUSED = {
2390
  32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_4) }, { F (F_DSP_32_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2391
};
2392
2393
static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_SB_relative_QI ATTRIBUTE_UNUSED = {
2394
  32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_4) }, { F (F_DSP_32_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2395
};
2396
2397
static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_FB_relative_QI ATTRIBUTE_UNUSED = {
2398
  32, 40, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2399
};
2400
2401
static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_FB_relative_QI ATTRIBUTE_UNUSED = {
2402
  32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2403
};
2404
2405
static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_FB_relative_QI ATTRIBUTE_UNUSED = {
2406
  32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2407
};
2408
2409
static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_absolute_QI ATTRIBUTE_UNUSED = {
2410
  32, 48, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_32_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2411
};
2412
2413
static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_absolute_QI ATTRIBUTE_UNUSED = {
2414
  32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_4) }, { F (F_DSP_32_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2415
};
2416
2417
static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_absolute_QI ATTRIBUTE_UNUSED = {
2418
  32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_4) }, { F (F_DSP_32_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2419
};
2420
2421
static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_Rn_direct_QI ATTRIBUTE_UNUSED = {
2422
  16, 16, 0xffcc, { { F (F_0_4) }, { F (F_8_2) }, { F (F_SRC16_RN) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2423
};
2424
2425
static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_Rn_direct_QI ATTRIBUTE_UNUSED = {
2426
  16, 16, 0xffec, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2427
};
2428
2429
static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_Rn_direct_QI ATTRIBUTE_UNUSED = {
2430
  16, 16, 0xffec, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2431
};
2432
2433
static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_direct_QI ATTRIBUTE_UNUSED = {
2434
  16, 16, 0xffce, { { F (F_0_4) }, { F (F_8_2) }, { F (F_SRC16_RN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2435
};
2436
2437
static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_direct_QI ATTRIBUTE_UNUSED = {
2438
  16, 16, 0xffee, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2439
};
2440
2441
static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_direct_QI ATTRIBUTE_UNUSED = {
2442
  16, 16, 0xffee, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2443
};
2444
2445
static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_indirect_QI ATTRIBUTE_UNUSED = {
2446
  16, 16, 0xffce, { { F (F_0_4) }, { F (F_8_2) }, { F (F_SRC16_RN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2447
};
2448
2449
static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_indirect_QI ATTRIBUTE_UNUSED = {
2450
  16, 16, 0xffee, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2451
};
2452
2453
static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_indirect_QI ATTRIBUTE_UNUSED = {
2454
  16, 16, 0xffee, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2455
};
2456
2457
static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_An_relative_QI ATTRIBUTE_UNUSED = {
2458
  24, 24, 0xffce00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_SRC16_RN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2459
};
2460
2461
static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_An_relative_QI ATTRIBUTE_UNUSED = {
2462
  24, 24, 0xffee00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2463
};
2464
2465
static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_An_relative_QI ATTRIBUTE_UNUSED = {
2466
  24, 24, 0xffee00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2467
};
2468
2469
static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_An_relative_QI ATTRIBUTE_UNUSED = {
2470
  32, 32, 0xffce0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_SRC16_RN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2471
};
2472
2473
static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_An_relative_QI ATTRIBUTE_UNUSED = {
2474
  32, 32, 0xffee0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2475
};
2476
2477
static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_An_relative_QI ATTRIBUTE_UNUSED = {
2478
  32, 32, 0xffee0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2479
};
2480
2481
static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_SB_relative_QI ATTRIBUTE_UNUSED = {
2482
  24, 24, 0xffcf00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_SRC16_RN) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2483
};
2484
2485
static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_SB_relative_QI ATTRIBUTE_UNUSED = {
2486
  24, 24, 0xffef00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2487
};
2488
2489
static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_SB_relative_QI ATTRIBUTE_UNUSED = {
2490
  24, 24, 0xffef00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2491
};
2492
2493
static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_SB_relative_QI ATTRIBUTE_UNUSED = {
2494
  32, 32, 0xffcf0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_SRC16_RN) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2495
};
2496
2497
static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_SB_relative_QI ATTRIBUTE_UNUSED = {
2498
  32, 32, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2499
};
2500
2501
static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_SB_relative_QI ATTRIBUTE_UNUSED = {
2502
  32, 32, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2503
};
2504
2505
static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_FB_relative_QI ATTRIBUTE_UNUSED = {
2506
  24, 24, 0xffcf00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_SRC16_RN) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2507
};
2508
2509
static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_FB_relative_QI ATTRIBUTE_UNUSED = {
2510
  24, 24, 0xffef00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2511
};
2512
2513
static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_FB_relative_QI ATTRIBUTE_UNUSED = {
2514
  24, 24, 0xffef00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2515
};
2516
2517
static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_absolute_QI ATTRIBUTE_UNUSED = {
2518
  32, 32, 0xffcf0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_SRC16_RN) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2519
};
2520
2521
static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_absolute_QI ATTRIBUTE_UNUSED = {
2522
  32, 32, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2523
};
2524
2525
static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_absolute_QI ATTRIBUTE_UNUSED = {
2526
  32, 32, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2527
};
2528
2529
static const CGEN_IFMT ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
2530
  32, 32, 0xff3f0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_S16) }, { 0 } }
2531
};
2532
2533
static const CGEN_IFMT ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
2534
  32, 32, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_S16) }, { 0 } }
2535
};
2536
2537
static const CGEN_IFMT ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI ATTRIBUTE_UNUSED = {
2538
  32, 32, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_S16) }, { 0 } }
2539
};
2540
2541
static const CGEN_IFMT ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
2542
  32, 40, 0xffbf0000, { { F (F_0_4) }, { F (F_DSP_24_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
2543
};
2544
2545
static const CGEN_IFMT ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
2546
  32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_24_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
2547
};
2548
2549
static const CGEN_IFMT ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
2550
  32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_24_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
2551
};
2552
2553
static const CGEN_IFMT ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
2554
  32, 48, 0xffbf0000, { { F (F_0_4) }, { F (F_DSP_32_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
2555
};
2556
2557
static const CGEN_IFMT ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
2558
  32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
2559
};
2560
2561
static const CGEN_IFMT ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
2562
  32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
2563
};
2564
2565
static const CGEN_IFMT ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
2566
  32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
2567
};
2568
2569
static const CGEN_IFMT ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
2570
  32, 56, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_DSP_40_S16) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
2571
};
2572
2573
static const CGEN_IFMT ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
2574
  32, 56, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_DSP_40_S16) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
2575
};
2576
2577
static const CGEN_IFMT ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
2578
  24, 24, 0xff3f00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { 0 } }
2579
};
2580
2581
static const CGEN_IFMT ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
2582
  24, 24, 0xffbf00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { 0 } }
2583
};
2584
2585
static const CGEN_IFMT ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI ATTRIBUTE_UNUSED = {
2586
  24, 24, 0xffbf00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { 0 } }
2587
};
2588
2589
static const CGEN_IFMT ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
2590
  32, 32, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_24_S8) }, { 0 } }
2591
};
2592
2593
static const CGEN_IFMT ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
2594
  32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_24_S8) }, { 0 } }
2595
};
2596
2597
static const CGEN_IFMT ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
2598
  32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_24_S8) }, { 0 } }
2599
};
2600
2601
static const CGEN_IFMT ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
2602
  32, 40, 0xffbf0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
2603
};
2604
2605
static const CGEN_IFMT ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
2606
  32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
2607
};
2608
2609
static const CGEN_IFMT ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
2610
  32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
2611
};
2612
2613
static const CGEN_IFMT ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
2614
  32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
2615
};
2616
2617
static const CGEN_IFMT ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
2618
  32, 48, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_DSP_40_S8) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
2619
};
2620
2621
static const CGEN_IFMT ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
2622
  32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_DSP_40_S8) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
2623
};
2624
2625
static const CGEN_IFMT ifmt_xor16_w_imm_G_basic_dst16_Rn_direct_HI ATTRIBUTE_UNUSED = {
2626
  32, 32, 0xfffc0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_16_S16) }, { 0 } }
2627
};
2628
2629
static const CGEN_IFMT ifmt_xor16_w_imm_G_basic_dst16_An_direct_HI ATTRIBUTE_UNUSED = {
2630
  32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_16_S16) }, { 0 } }
2631
};
2632
2633
static const CGEN_IFMT ifmt_xor16_w_imm_G_basic_dst16_An_indirect_HI ATTRIBUTE_UNUSED = {
2634
  32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_16_S16) }, { 0 } }
2635
};
2636
2637
static const CGEN_IFMT ifmt_xor16_w_imm_G_16_8_dst16_16_8_An_relative_HI ATTRIBUTE_UNUSED = {
2638
  32, 40, 0xfffe0000, { { F (F_0_4) }, { F (F_DSP_24_S16) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
2639
};
2640
2641
static const CGEN_IFMT ifmt_xor16_w_imm_G_16_8_dst16_16_8_SB_relative_HI ATTRIBUTE_UNUSED = {
2642
  32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_24_S16) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
2643
};
2644
2645
static const CGEN_IFMT ifmt_xor16_w_imm_G_16_8_dst16_16_8_FB_relative_HI ATTRIBUTE_UNUSED = {
2646
  32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_24_S16) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
2647
};
2648
2649
static const CGEN_IFMT ifmt_xor16_w_imm_G_16_16_dst16_16_16_An_relative_HI ATTRIBUTE_UNUSED = {
2650
  32, 48, 0xfffe0000, { { F (F_0_4) }, { F (F_DSP_32_S16) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
2651
};
2652
2653
static const CGEN_IFMT ifmt_xor16_w_imm_G_16_16_dst16_16_16_SB_relative_HI ATTRIBUTE_UNUSED = {
2654
  32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S16) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
2655
};
2656
2657
static const CGEN_IFMT ifmt_xor16_w_imm_G_16_16_dst16_16_16_absolute_HI ATTRIBUTE_UNUSED = {
2658
  32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S16) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
2659
};
2660
2661
static const CGEN_IFMT ifmt_xor16_b_imm_G_basic_dst16_Rn_direct_QI ATTRIBUTE_UNUSED = {
2662
  24, 24, 0xfffc00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { 0 } }
2663
};
2664
2665
static const CGEN_IFMT ifmt_xor16_b_imm_G_basic_dst16_An_direct_QI ATTRIBUTE_UNUSED = {
2666
  24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { 0 } }
2667
};
2668
2669
static const CGEN_IFMT ifmt_xor16_b_imm_G_basic_dst16_An_indirect_QI ATTRIBUTE_UNUSED = {
2670
  24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { 0 } }
2671
};
2672
2673
static const CGEN_IFMT ifmt_xor16_b_imm_G_16_8_dst16_16_8_An_relative_QI ATTRIBUTE_UNUSED = {
2674
  32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_24_S8) }, { 0 } }
2675
};
2676
2677
static const CGEN_IFMT ifmt_xor16_b_imm_G_16_8_dst16_16_8_SB_relative_QI ATTRIBUTE_UNUSED = {
2678
  32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_24_S8) }, { 0 } }
2679
};
2680
2681
static const CGEN_IFMT ifmt_xor16_b_imm_G_16_8_dst16_16_8_FB_relative_QI ATTRIBUTE_UNUSED = {
2682
  32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_24_S8) }, { 0 } }
2683
};
2684
2685
static const CGEN_IFMT ifmt_xor16_b_imm_G_16_16_dst16_16_16_An_relative_QI ATTRIBUTE_UNUSED = {
2686
  32, 40, 0xfffe0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
2687
};
2688
2689
static const CGEN_IFMT ifmt_xor16_b_imm_G_16_16_dst16_16_16_SB_relative_QI ATTRIBUTE_UNUSED = {
2690
  32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
2691
};
2692
2693
static const CGEN_IFMT ifmt_xor16_b_imm_G_16_16_dst16_16_16_absolute_QI ATTRIBUTE_UNUSED = {
2694
  32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
2695
};
2696
2697
static const CGEN_IFMT ifmt_xchg32w_r3_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
2698
  16, 16, 0xff3f, { { F (F_0_4) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
2699
};
2700
2701
static const CGEN_IFMT ifmt_xchg32w_r3_dst32_An_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
2702
  16, 16, 0xffbf, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
2703
};
2704
2705
static const CGEN_IFMT ifmt_xchg32w_r3_dst32_An_indirect_Unprefixed_HI ATTRIBUTE_UNUSED = {
2706
  16, 16, 0xffbf, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
2707
};
2708
2709
static const CGEN_IFMT ifmt_xchg32w_r3_dst32_16_8_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
2710
  24, 24, 0xffbf00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
2711
};
2712
2713
static const CGEN_IFMT ifmt_xchg32w_r3_dst32_16_16_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
2714
  32, 32, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
2715
};
2716
2717
static const CGEN_IFMT ifmt_xchg32w_r3_dst32_16_24_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
2718
  32, 40, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
2719
};
2720
2721
static const CGEN_IFMT ifmt_xchg32w_r3_dst32_16_8_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
2722
  24, 24, 0xffff00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
2723
};
2724
2725
static const CGEN_IFMT ifmt_xchg32w_r3_dst32_16_16_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
2726
  32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
2727
};
2728
2729
static const CGEN_IFMT ifmt_xchg32w_r3_dst32_16_8_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
2730
  24, 24, 0xffff00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
2731
};
2732
2733
static const CGEN_IFMT ifmt_xchg32w_r3_dst32_16_16_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
2734
  32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
2735
};
2736
2737
static const CGEN_IFMT ifmt_xchg32w_r3_dst32_16_16_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
2738
  32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
2739
};
2740
2741
static const CGEN_IFMT ifmt_xchg32w_r3_dst32_16_24_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
2742
  32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
2743
};
2744
2745
static const CGEN_IFMT ifmt_xchg32b_r1h_dst32_Rn_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
2746
  16, 16, 0xff3f, { { F (F_0_4) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
2747
};
2748
2749
static const CGEN_IFMT ifmt_xchg32b_r1h_dst32_An_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
2750
  16, 16, 0xffbf, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
2751
};
2752
2753
static const CGEN_IFMT ifmt_xchg32b_r1h_dst32_An_indirect_Unprefixed_QI ATTRIBUTE_UNUSED = {
2754
  16, 16, 0xffbf, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
2755
};
2756
2757
static const CGEN_IFMT ifmt_xchg32b_r1h_dst32_16_8_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
2758
  24, 24, 0xffbf00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
2759
};
2760
2761
static const CGEN_IFMT ifmt_xchg32b_r1h_dst32_16_16_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
2762
  32, 32, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
2763
};
2764
2765
static const CGEN_IFMT ifmt_xchg32b_r1h_dst32_16_24_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
2766
  32, 40, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
2767
};
2768
2769
static const CGEN_IFMT ifmt_xchg32b_r1h_dst32_16_8_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
2770
  24, 24, 0xffff00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
2771
};
2772
2773
static const CGEN_IFMT ifmt_xchg32b_r1h_dst32_16_16_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
2774
  32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
2775
};
2776
2777
static const CGEN_IFMT ifmt_xchg32b_r1h_dst32_16_8_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
2778
  24, 24, 0xffff00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
2779
};
2780
2781
static const CGEN_IFMT ifmt_xchg32b_r1h_dst32_16_16_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
2782
  32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
2783
};
2784
2785
static const CGEN_IFMT ifmt_xchg32b_r1h_dst32_16_16_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
2786
  32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
2787
};
2788
2789
static const CGEN_IFMT ifmt_xchg32b_r1h_dst32_16_24_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
2790
  32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
2791
};
2792
2793
static const CGEN_IFMT ifmt_xchg16w_r3_dst16_Rn_direct_HI ATTRIBUTE_UNUSED = {
2794
  16, 16, 0xfffc, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_2) }, { F (F_10_2) }, { 0 } }
2795
};
2796
2797
static const CGEN_IFMT ifmt_xchg16w_r3_dst16_An_direct_HI ATTRIBUTE_UNUSED = {
2798
  16, 16, 0xfffe, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_2) }, { F (F_10_2) }, { 0 } }
2799
};
2800
2801
static const CGEN_IFMT ifmt_xchg16w_r3_dst16_An_indirect_HI ATTRIBUTE_UNUSED = {
2802
  16, 16, 0xfffe, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_2) }, { F (F_10_2) }, { 0 } }
2803
};
2804
2805
static const CGEN_IFMT ifmt_xchg16w_r3_dst16_16_8_An_relative_HI ATTRIBUTE_UNUSED = {
2806
  24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_2) }, { F (F_10_2) }, { 0 } }
2807
};
2808
2809
static const CGEN_IFMT ifmt_xchg16w_r3_dst16_16_16_An_relative_HI ATTRIBUTE_UNUSED = {
2810
  32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_2) }, { F (F_10_2) }, { 0 } }
2811
};
2812
2813
static const CGEN_IFMT ifmt_xchg16w_r3_dst16_16_8_SB_relative_HI ATTRIBUTE_UNUSED = {
2814
  24, 24, 0xffff00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_2) }, { F (F_10_2) }, { 0 } }
2815
};
2816
2817
static const CGEN_IFMT ifmt_xchg16w_r3_dst16_16_16_SB_relative_HI ATTRIBUTE_UNUSED = {
2818
  32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_2) }, { F (F_10_2) }, { 0 } }
2819
};
2820
2821
static const CGEN_IFMT ifmt_xchg16w_r3_dst16_16_8_FB_relative_HI ATTRIBUTE_UNUSED = {
2822
  24, 24, 0xffff00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_2) }, { F (F_10_2) }, { 0 } }
2823
};
2824
2825
static const CGEN_IFMT ifmt_xchg16w_r3_dst16_16_16_absolute_HI ATTRIBUTE_UNUSED = {
2826
  32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_2) }, { F (F_10_2) }, { 0 } }
2827
};
2828
2829
static const CGEN_IFMT ifmt_xchg16b_r1h_dst16_Rn_direct_QI ATTRIBUTE_UNUSED = {
2830
  16, 16, 0xfffc, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_2) }, { F (F_10_2) }, { 0 } }
2831
};
2832
2833
static const CGEN_IFMT ifmt_xchg16b_r1h_dst16_An_direct_QI ATTRIBUTE_UNUSED = {
2834
  16, 16, 0xfffe, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_2) }, { F (F_10_2) }, { 0 } }
2835
};
2836
2837
static const CGEN_IFMT ifmt_xchg16b_r1h_dst16_An_indirect_QI ATTRIBUTE_UNUSED = {
2838
  16, 16, 0xfffe, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_2) }, { F (F_10_2) }, { 0 } }
2839
};
2840
2841
static const CGEN_IFMT ifmt_xchg16b_r1h_dst16_16_8_An_relative_QI ATTRIBUTE_UNUSED = {
2842
  24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_2) }, { F (F_10_2) }, { 0 } }
2843
};
2844
2845
static const CGEN_IFMT ifmt_xchg16b_r1h_dst16_16_16_An_relative_QI ATTRIBUTE_UNUSED = {
2846
  32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_2) }, { F (F_10_2) }, { 0 } }
2847
};
2848
2849
static const CGEN_IFMT ifmt_xchg16b_r1h_dst16_16_8_SB_relative_QI ATTRIBUTE_UNUSED = {
2850
  24, 24, 0xffff00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_2) }, { F (F_10_2) }, { 0 } }
2851
};
2852
2853
static const CGEN_IFMT ifmt_xchg16b_r1h_dst16_16_16_SB_relative_QI ATTRIBUTE_UNUSED = {
2854
  32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_2) }, { F (F_10_2) }, { 0 } }
2855
};
2856
2857
static const CGEN_IFMT ifmt_xchg16b_r1h_dst16_16_8_FB_relative_QI ATTRIBUTE_UNUSED = {
2858
  24, 24, 0xffff00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_2) }, { F (F_10_2) }, { 0 } }
2859
};
2860
2861
static const CGEN_IFMT ifmt_xchg16b_r1h_dst16_16_16_absolute_QI ATTRIBUTE_UNUSED = {
2862
  32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_2) }, { F (F_10_2) }, { 0 } }
2863
};
2864
2865
static const CGEN_IFMT ifmt_tst32_w_imm_S_2_S_8_dst32_2_S_8_SB_relative_HI ATTRIBUTE_UNUSED = {
2866
  32, 32, 0xff000000, { { F (F_0_2) }, { F (F_2_2) }, { F (F_DSP_8_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_DSP_16_S16) }, { 0 } }
2867
};
2868
2869
static const CGEN_IFMT ifmt_tst32_w_imm_S_2_S_8_dst32_2_S_8_FB_relative_HI ATTRIBUTE_UNUSED = {
2870
  32, 32, 0xff000000, { { F (F_0_2) }, { F (F_2_2) }, { F (F_DSP_8_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_DSP_16_S16) }, { 0 } }
2871
};
2872
2873
static const CGEN_IFMT ifmt_tst32_w_imm_S_2_S_16_dst32_2_S_16_absolute_HI ATTRIBUTE_UNUSED = {
2874
  32, 40, 0xff000000, { { F (F_0_2) }, { F (F_DSP_24_S16) }, { F (F_2_2) }, { F (F_DSP_8_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
2875
};
2876
2877
static const CGEN_IFMT ifmt_tst32_w_imm_S_2_S_basic_dst32_2_S_R0_direct_HI ATTRIBUTE_UNUSED = {
2878
  24, 24, 0xff0000, { { F (F_0_2) }, { F (F_2_2) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_DSP_8_S16) }, { 0 } }
2879
};
2880
2881
static const CGEN_IFMT ifmt_tst32_b_imm_S_2_S_8_dst32_2_S_8_SB_relative_QI ATTRIBUTE_UNUSED = {
2882
  24, 24, 0xff0000, { { F (F_0_2) }, { F (F_2_2) }, { F (F_DSP_8_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_DSP_16_S8) }, { 0 } }
2883
};
2884
2885
static const CGEN_IFMT ifmt_tst32_b_imm_S_2_S_8_dst32_2_S_8_FB_relative_QI ATTRIBUTE_UNUSED = {
2886
  24, 24, 0xff0000, { { F (F_0_2) }, { F (F_2_2) }, { F (F_DSP_8_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_DSP_16_S8) }, { 0 } }
2887
};
2888
2889
static const CGEN_IFMT ifmt_tst32_b_imm_S_2_S_16_dst32_2_S_16_absolute_QI ATTRIBUTE_UNUSED = {
2890
  32, 32, 0xff000000, { { F (F_0_2) }, { F (F_2_2) }, { F (F_DSP_8_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_DSP_24_S8) }, { 0 } }
2891
};
2892
2893
static const CGEN_IFMT ifmt_tst32_b_imm_S_2_S_basic_dst32_2_S_R0l_direct_QI ATTRIBUTE_UNUSED = {
2894
  16, 16, 0xff00, { { F (F_0_2) }, { F (F_2_2) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_DSP_8_S8) }, { 0 } }
2895
};
2896
2897
static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
2898
  32, 32, 0xffff2f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
2899
};
2900
2901
static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
2902
  32, 32, 0xffff3f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
2903
};
2904
2905
static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
2906
  32, 32, 0xffff3f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
2907
};
2908
2909
static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
2910
  32, 32, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
2911
};
2912
2913
static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
2914
  32, 32, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
2915
};
2916
2917
static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
2918
  32, 32, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
2919
};
2920
2921
static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = {
2922
  32, 32, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
2923
};
2924
2925
static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = {
2926
  32, 32, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
2927
};
2928
2929
static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = {
2930
  32, 32, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
2931
};
2932
2933
static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
2934
  32, 40, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
2935
};
2936
2937
static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
2938
  32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
2939
};
2940
2941
static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
2942
  32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
2943
};
2944
2945
static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
2946
  32, 48, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
2947
};
2948
2949
static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
2950
  32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
2951
};
2952
2953
static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
2954
  32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
2955
};
2956
2957
static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
2958
  32, 56, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
2959
};
2960
2961
static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
2962
  32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
2963
};
2964
2965
static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
2966
  32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
2967
};
2968
2969
static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
2970
  32, 40, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
2971
};
2972
2973
static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
2974
  32, 40, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
2975
};
2976
2977
static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
2978
  32, 40, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
2979
};
2980
2981
static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
2982
  32, 48, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
2983
};
2984
2985
static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
2986
  32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
2987
};
2988
2989
static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
2990
  32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
2991
};
2992
2993
static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
2994
  32, 40, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
2995
};
2996
2997
static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
2998
  32, 40, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
2999
};
3000
3001
static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3002
  32, 40, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3003
};
3004
3005
static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3006
  32, 48, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3007
};
3008
3009
static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3010
  32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3011
};
3012
3013
static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3014
  32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3015
};
3016
3017
static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
3018
  32, 48, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3019
};
3020
3021
static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
3022
  32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3023
};
3024
3025
static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
3026
  32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3027
};
3028
3029
static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
3030
  32, 56, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3031
};
3032
3033
static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
3034
  32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3035
};
3036
3037
static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
3038
  32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3039
};
3040
3041
static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
3042
  32, 40, 0xffff2f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3043
};
3044
3045
static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
3046
  32, 40, 0xffff3f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3047
};
3048
3049
static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
3050
  32, 40, 0xffff3f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3051
};
3052
3053
static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
3054
  32, 40, 0xffff3f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3055
};
3056
3057
static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
3058
  32, 40, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3059
};
3060
3061
static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
3062
  32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3063
};
3064
3065
static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
3066
  32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3067
};
3068
3069
static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
3070
  32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3071
};
3072
3073
static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = {
3074
  32, 40, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3075
};
3076
3077
static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = {
3078
  32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3079
};
3080
3081
static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = {
3082
  32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3083
};
3084
3085
static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = {
3086
  32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3087
};
3088
3089
static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3090
  32, 48, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3091
};
3092
3093
static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3094
  32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3095
};
3096
3097
static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3098
  32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3099
};
3100
3101
static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3102
  32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3103
};
3104
3105
static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3106
  32, 56, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3107
};
3108
3109
static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3110
  32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3111
};
3112
3113
static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3114
  32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3115
};
3116
3117
static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3118
  32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3119
};
3120
3121
static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3122
  32, 64, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3123
};
3124
3125
static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3126
  32, 64, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3127
};
3128
3129
static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3130
  32, 64, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3131
};
3132
3133
static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3134
  32, 64, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3135
};
3136
3137
static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3138
  32, 48, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3139
};
3140
3141
static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3142
  32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3143
};
3144
3145
static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3146
  32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3147
};
3148
3149
static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3150
  32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3151
};
3152
3153
static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3154
  32, 56, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3155
};
3156
3157
static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3158
  32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3159
};
3160
3161
static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3162
  32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3163
};
3164
3165
static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3166
  32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3167
};
3168
3169
static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3170
  32, 48, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3171
};
3172
3173
static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3174
  32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3175
};
3176
3177
static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3178
  32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3179
};
3180
3181
static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3182
  32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3183
};
3184
3185
static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3186
  32, 56, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3187
};
3188
3189
static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3190
  32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3191
};
3192
3193
static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3194
  32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3195
};
3196
3197
static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3198
  32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3199
};
3200
3201
static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
3202
  32, 56, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3203
};
3204
3205
static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
3206
  32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3207
};
3208
3209
static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
3210
  32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3211
};
3212
3213
static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
3214
  32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3215
};
3216
3217
static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
3218
  32, 64, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3219
};
3220
3221
static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
3222
  32, 64, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3223
};
3224
3225
static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
3226
  32, 64, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3227
};
3228
3229
static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
3230
  32, 64, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3231
};
3232
3233
static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
3234
  32, 48, 0xffff2f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3235
};
3236
3237
static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
3238
  32, 48, 0xffff3f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3239
};
3240
3241
static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
3242
  32, 48, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3243
};
3244
3245
static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
3246
  32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3247
};
3248
3249
static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = {
3250
  32, 48, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3251
};
3252
3253
static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = {
3254
  32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3255
};
3256
3257
static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3258
  32, 56, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_48_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3259
};
3260
3261
static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3262
  32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_48_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3263
};
3264
3265
static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3266
  32, 64, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_48_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3267
};
3268
3269
static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3270
  32, 64, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_48_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3271
};
3272
3273
static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3274
  32, 72, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_48_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3275
};
3276
3277
static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3278
  32, 72, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_48_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3279
};
3280
3281
static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3282
  32, 56, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3283
};
3284
3285
static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3286
  32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3287
};
3288
3289
static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3290
  32, 64, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3291
};
3292
3293
static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3294
  32, 64, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3295
};
3296
3297
static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3298
  32, 56, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3299
};
3300
3301
static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3302
  32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3303
};
3304
3305
static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3306
  32, 64, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3307
};
3308
3309
static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3310
  32, 64, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3311
};
3312
3313
static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
3314
  32, 64, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3315
};
3316
3317
static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
3318
  32, 64, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3319
};
3320
3321
static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
3322
  32, 72, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3323
};
3324
3325
static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
3326
  32, 72, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3327
};
3328
3329
static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
3330
  24, 24, 0xffff0f, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_HI) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3331
};
3332
3333
static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
3334
  24, 24, 0xffff2f, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3335
};
3336
3337
static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
3338
  24, 24, 0xffff2f, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3339
};
3340
3341
static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
3342
  24, 24, 0xffff8f, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_HI) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3343
};
3344
3345
static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
3346
  24, 24, 0xffffaf, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3347
};
3348
3349
static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
3350
  24, 24, 0xffffaf, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3351
};
3352
3353
static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = {
3354
  24, 24, 0xffff8f, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_HI) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3355
};
3356
3357
static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = {
3358
  24, 24, 0xffffaf, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3359
};
3360
3361
static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = {
3362
  24, 24, 0xffffaf, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3363
};
3364
3365
static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3366
  32, 32, 0xffff8f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_HI) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3367
};
3368
3369
static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3370
  32, 32, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3371
};
3372
3373
static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3374
  32, 32, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3375
};
3376
3377
static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3378
  32, 40, 0xffff8f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_HI) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3379
};
3380
3381
static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3382
  32, 40, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3383
};
3384
3385
static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3386
  32, 40, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3387
};
3388
3389
static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3390
  32, 48, 0xffff8f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_HI) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3391
};
3392
3393
static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3394
  32, 48, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3395
};
3396
3397
static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3398
  32, 48, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3399
};
3400
3401
static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3402
  32, 32, 0xffffcf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_HI) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3403
};
3404
3405
static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3406
  32, 32, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3407
};
3408
3409
static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3410
  32, 32, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3411
};
3412
3413
static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3414
  32, 40, 0xffffcf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_HI) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3415
};
3416
3417
static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3418
  32, 40, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3419
};
3420
3421
static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3422
  32, 40, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3423
};
3424
3425
static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3426
  32, 32, 0xffffcf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_HI) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3427
};
3428
3429
static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3430
  32, 32, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3431
};
3432
3433
static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3434
  32, 32, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3435
};
3436
3437
static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3438
  32, 40, 0xffffcf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_HI) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3439
};
3440
3441
static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3442
  32, 40, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3443
};
3444
3445
static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
3446
  32, 40, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3447
};
3448
3449
static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
3450
  32, 40, 0xffffcf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_HI) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3451
};
3452
3453
static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
3454
  32, 40, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3455
};
3456
3457
static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
3458
  32, 40, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3459
};
3460
3461
static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
3462
  32, 48, 0xffffcf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_HI) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3463
};
3464
3465
static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
3466
  32, 48, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3467
};
3468
3469
static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
3470
  32, 48, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3471
};
3472
3473
static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI ATTRIBUTE_UNUSED = {
3474
  32, 32, 0xffff2f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_QI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3475
};
3476
3477
static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI ATTRIBUTE_UNUSED = {
3478
  32, 32, 0xffff3f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_QI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3479
};
3480
3481
static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI ATTRIBUTE_UNUSED = {
3482
  32, 32, 0xffff3f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_QI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3483
};
3484
3485
static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI ATTRIBUTE_UNUSED = {
3486
  32, 32, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3487
};
3488
3489
static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI ATTRIBUTE_UNUSED = {
3490
  32, 32, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3491
};
3492
3493
static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI ATTRIBUTE_UNUSED = {
3494
  32, 32, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3495
};
3496
3497
static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI ATTRIBUTE_UNUSED = {
3498
  32, 32, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3499
};
3500
3501
static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI ATTRIBUTE_UNUSED = {
3502
  32, 32, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3503
};
3504
3505
static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI ATTRIBUTE_UNUSED = {
3506
  32, 32, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3507
};
3508
3509
static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3510
  32, 40, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3511
};
3512
3513
static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3514
  32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3515
};
3516
3517
static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3518
  32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3519
};
3520
3521
static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3522
  32, 48, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3523
};
3524
3525
static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3526
  32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3527
};
3528
3529
static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3530
  32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3531
};
3532
3533
static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3534
  32, 56, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3535
};
3536
3537
static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3538
  32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3539
};
3540
3541
static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3542
  32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3543
};
3544
3545
static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3546
  32, 40, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3547
};
3548
3549
static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3550
  32, 40, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3551
};
3552
3553
static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3554
  32, 40, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3555
};
3556
3557
static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3558
  32, 48, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3559
};
3560
3561
static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3562
  32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3563
};
3564
3565
static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3566
  32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3567
};
3568
3569
static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3570
  32, 40, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3571
};
3572
3573
static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3574
  32, 40, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3575
};
3576
3577
static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3578
  32, 40, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3579
};
3580
3581
static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3582
  32, 48, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3583
};
3584
3585
static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3586
  32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3587
};
3588
3589
static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3590
  32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3591
};
3592
3593
static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI ATTRIBUTE_UNUSED = {
3594
  32, 48, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3595
};
3596
3597
static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI ATTRIBUTE_UNUSED = {
3598
  32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3599
};
3600
3601
static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI ATTRIBUTE_UNUSED = {
3602
  32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3603
};
3604
3605
static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI ATTRIBUTE_UNUSED = {
3606
  32, 56, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3607
};
3608
3609
static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI ATTRIBUTE_UNUSED = {
3610
  32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3611
};
3612
3613
static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI ATTRIBUTE_UNUSED = {
3614
  32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3615
};
3616
3617
static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI ATTRIBUTE_UNUSED = {
3618
  32, 40, 0xffff2f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_QI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3619
};
3620
3621
static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI ATTRIBUTE_UNUSED = {
3622
  32, 40, 0xffff3f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_QI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3623
};
3624
3625
static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI ATTRIBUTE_UNUSED = {
3626
  32, 40, 0xffff3f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_QI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3627
};
3628
3629
static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_QI ATTRIBUTE_UNUSED = {
3630
  32, 40, 0xffff3f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_QI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3631
};
3632
3633
static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI ATTRIBUTE_UNUSED = {
3634
  32, 40, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3635
};
3636
3637
static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI ATTRIBUTE_UNUSED = {
3638
  32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3639
};
3640
3641
static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI ATTRIBUTE_UNUSED = {
3642
  32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3643
};
3644
3645
static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_direct_Prefixed_QI ATTRIBUTE_UNUSED = {
3646
  32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3647
};
3648
3649
static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI ATTRIBUTE_UNUSED = {
3650
  32, 40, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3651
};
3652
3653
static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI ATTRIBUTE_UNUSED = {
3654
  32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3655
};
3656
3657
static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI ATTRIBUTE_UNUSED = {
3658
  32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3659
};
3660
3661
static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_QI ATTRIBUTE_UNUSED = {
3662
  32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3663
};
3664
3665
static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3666
  32, 48, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3667
};
3668
3669
static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3670
  32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3671
};
3672
3673
static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3674
  32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3675
};
3676
3677
static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3678
  32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3679
};
3680
3681
static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3682
  32, 56, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3683
};
3684
3685
static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3686
  32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3687
};
3688
3689
static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3690
  32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3691
};
3692
3693
static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3694
  32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3695
};
3696
3697
static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3698
  32, 64, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3699
};
3700
3701
static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3702
  32, 64, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3703
};
3704
3705
static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3706
  32, 64, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3707
};
3708
3709
static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3710
  32, 64, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3711
};
3712
3713
static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3714
  32, 48, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3715
};
3716
3717
static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3718
  32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3719
};
3720
3721
static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3722
  32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3723
};
3724
3725
static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3726
  32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3727
};
3728
3729
static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3730
  32, 56, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3731
};
3732
3733
static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3734
  32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3735
};
3736
3737
static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3738
  32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3739
};
3740
3741
static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3742
  32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3743
};
3744
3745
static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3746
  32, 48, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3747
};
3748
3749
static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3750
  32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3751
};
3752
3753
static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3754
  32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3755
};
3756
3757
static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3758
  32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3759
};
3760
3761
static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3762
  32, 56, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3763
};
3764
3765
static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3766
  32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3767
};
3768
3769
static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3770
  32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3771
};
3772
3773
static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3774
  32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3775
};
3776
3777
static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI ATTRIBUTE_UNUSED = {
3778
  32, 56, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3779
};
3780
3781
static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI ATTRIBUTE_UNUSED = {
3782
  32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3783
};
3784
3785
static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI ATTRIBUTE_UNUSED = {
3786
  32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3787
};
3788
3789
static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI ATTRIBUTE_UNUSED = {
3790
  32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3791
};
3792
3793
static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI ATTRIBUTE_UNUSED = {
3794
  32, 64, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3795
};
3796
3797
static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI ATTRIBUTE_UNUSED = {
3798
  32, 64, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3799
};
3800
3801
static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI ATTRIBUTE_UNUSED = {
3802
  32, 64, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3803
};
3804
3805
static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI ATTRIBUTE_UNUSED = {
3806
  32, 64, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3807
};
3808
3809
static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI ATTRIBUTE_UNUSED = {
3810
  32, 48, 0xffff2f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_QI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3811
};
3812
3813
static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_QI ATTRIBUTE_UNUSED = {
3814
  32, 48, 0xffff3f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_QI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3815
};
3816
3817
static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI ATTRIBUTE_UNUSED = {
3818
  32, 48, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3819
};
3820
3821
static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_direct_Prefixed_QI ATTRIBUTE_UNUSED = {
3822
  32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3823
};
3824
3825
static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI ATTRIBUTE_UNUSED = {
3826
  32, 48, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3827
};
3828
3829
static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_QI ATTRIBUTE_UNUSED = {
3830
  32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3831
};
3832
3833
static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3834
  32, 56, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_48_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3835
};
3836
3837
static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3838
  32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_48_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3839
};
3840
3841
static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3842
  32, 64, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_48_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3843
};
3844
3845
static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3846
  32, 64, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_48_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3847
};
3848
3849
static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3850
  32, 72, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_48_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3851
};
3852
3853
static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3854
  32, 72, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_48_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3855
};
3856
3857
static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3858
  32, 56, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3859
};
3860
3861
static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3862
  32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3863
};
3864
3865
static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3866
  32, 64, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3867
};
3868
3869
static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3870
  32, 64, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3871
};
3872
3873
static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3874
  32, 56, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3875
};
3876
3877
static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3878
  32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3879
};
3880
3881
static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3882
  32, 64, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3883
};
3884
3885
static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3886
  32, 64, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3887
};
3888
3889
static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_absolute_Prefixed_QI ATTRIBUTE_UNUSED = {
3890
  32, 64, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3891
};
3892
3893
static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_absolute_Prefixed_QI ATTRIBUTE_UNUSED = {
3894
  32, 64, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3895
};
3896
3897
static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_absolute_Prefixed_QI ATTRIBUTE_UNUSED = {
3898
  32, 72, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3899
};
3900
3901
static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_absolute_Prefixed_QI ATTRIBUTE_UNUSED = {
3902
  32, 72, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3903
};
3904
3905
static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_QI ATTRIBUTE_UNUSED = {
3906
  24, 24, 0xffff0f, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_QI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3907
};
3908
3909
static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_QI ATTRIBUTE_UNUSED = {
3910
  24, 24, 0xffff2f, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_QI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3911
};
3912
3913
static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_Rn_direct_Prefixed_QI ATTRIBUTE_UNUSED = {
3914
  24, 24, 0xffff2f, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_QI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3915
};
3916
3917
static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_direct_Prefixed_QI ATTRIBUTE_UNUSED = {
3918
  24, 24, 0xffff8f, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3919
};
3920
3921
static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_An_direct_Prefixed_QI ATTRIBUTE_UNUSED = {
3922
  24, 24, 0xffffaf, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3923
};
3924
3925
static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_direct_Prefixed_QI ATTRIBUTE_UNUSED = {
3926
  24, 24, 0xffffaf, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3927
};
3928
3929
static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_indirect_Prefixed_QI ATTRIBUTE_UNUSED = {
3930
  24, 24, 0xffff8f, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3931
};
3932
3933
static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_An_indirect_Prefixed_QI ATTRIBUTE_UNUSED = {
3934
  24, 24, 0xffffaf, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3935
};
3936
3937
static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_indirect_Prefixed_QI ATTRIBUTE_UNUSED = {
3938
  24, 24, 0xffffaf, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3939
};
3940
3941
static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3942
  32, 32, 0xffff8f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3943
};
3944
3945
static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3946
  32, 32, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3947
};
3948
3949
static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3950
  32, 32, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3951
};
3952
3953
static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3954
  32, 40, 0xffff8f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3955
};
3956
3957
static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3958
  32, 40, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3959
};
3960
3961
static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3962
  32, 40, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3963
};
3964
3965
static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3966
  32, 48, 0xffff8f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3967
};
3968
3969
static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3970
  32, 48, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3971
};
3972
3973
static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3974
  32, 48, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3975
};
3976
3977
static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3978
  32, 32, 0xffffcf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3979
};
3980
3981
static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3982
  32, 32, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3983
};
3984
3985
static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3986
  32, 32, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3987
};
3988
3989
static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3990
  32, 40, 0xffffcf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3991
};
3992
3993
static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3994
  32, 40, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3995
};
3996
3997
static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
3998
  32, 40, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
3999
};
4000
4001
static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
4002
  32, 32, 0xffffcf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
4003
};
4004
4005
static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
4006
  32, 32, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
4007
};
4008
4009
static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
4010
  32, 32, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
4011
};
4012
4013
static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
4014
  32, 40, 0xffffcf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
4015
};
4016
4017
static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
4018
  32, 40, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
4019
};
4020
4021
static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
4022
  32, 40, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
4023
};
4024
4025
static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI ATTRIBUTE_UNUSED = {
4026
  32, 40, 0xffffcf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
4027
};
4028
4029
static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI ATTRIBUTE_UNUSED = {
4030
  32, 40, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
4031
};
4032
4033
static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI ATTRIBUTE_UNUSED = {
4034
  32, 40, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
4035
};
4036
4037
static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI ATTRIBUTE_UNUSED = {
4038
  32, 48, 0xffffcf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
4039
};
4040
4041
static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI ATTRIBUTE_UNUSED = {
4042
  32, 48, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
4043
};
4044
4045
static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI ATTRIBUTE_UNUSED = {
4046
  32, 48, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } }
4047
};
4048
4049
static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
4050
  24, 24, 0xff2f00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4051
};
4052
4053
static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
4054
  24, 24, 0xff3f00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4055
};
4056
4057
static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
4058
  24, 24, 0xff3f00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4059
};
4060
4061
static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
4062
  24, 24, 0xffaf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4063
};
4064
4065
static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
4066
  24, 24, 0xffbf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4067
};
4068
4069
static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
4070
  24, 24, 0xffbf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4071
};
4072
4073
static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = {
4074
  24, 24, 0xffaf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4075
};
4076
4077
static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = {
4078
  24, 24, 0xffbf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4079
};
4080
4081
static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = {
4082
  24, 24, 0xffbf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4083
};
4084
4085
static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4086
  32, 32, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4087
};
4088
4089
static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4090
  32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4091
};
4092
4093
static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4094
  32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4095
};
4096
4097
static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4098
  32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4099
};
4100
4101
static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4102
  32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4103
};
4104
4105
static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4106
  32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4107
};
4108
4109
static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4110
  32, 48, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4111
};
4112
4113
static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4114
  32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4115
};
4116
4117
static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4118
  32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4119
};
4120
4121
static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4122
  32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4123
};
4124
4125
static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4126
  32, 32, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4127
};
4128
4129
static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4130
  32, 32, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4131
};
4132
4133
static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4134
  32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4135
};
4136
4137
static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4138
  32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4139
};
4140
4141
static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4142
  32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4143
};
4144
4145
static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4146
  32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4147
};
4148
4149
static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4150
  32, 32, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4151
};
4152
4153
static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4154
  32, 32, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4155
};
4156
4157
static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4158
  32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4159
};
4160
4161
static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4162
  32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4163
};
4164
4165
static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4166
  32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4167
};
4168
4169
static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
4170
  32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4171
};
4172
4173
static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
4174
  32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4175
};
4176
4177
static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
4178
  32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4179
};
4180
4181
static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
4182
  32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4183
};
4184
4185
static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
4186
  32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4187
};
4188
4189
static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
4190
  32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4191
};
4192
4193
static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
4194
  32, 32, 0xff2f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4195
};
4196
4197
static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
4198
  32, 32, 0xff3f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4199
};
4200
4201
static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
4202
  32, 32, 0xff3f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4203
};
4204
4205
static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
4206
  32, 32, 0xff3f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4207
};
4208
4209
static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
4210
  32, 32, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4211
};
4212
4213
static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
4214
  32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4215
};
4216
4217
static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
4218
  32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4219
};
4220
4221
static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
4222
  32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4223
};
4224
4225
static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = {
4226
  32, 32, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4227
};
4228
4229
static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = {
4230
  32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4231
};
4232
4233
static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = {
4234
  32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4235
};
4236
4237
static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = {
4238
  32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4239
};
4240
4241
static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4242
  32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4243
};
4244
4245
static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4246
  32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4247
};
4248
4249
static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4250
  32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4251
};
4252
4253
static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4254
  32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4255
};
4256
4257
static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4258
  32, 48, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4259
};
4260
4261
static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4262
  32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4263
};
4264
4265
static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4266
  32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4267
};
4268
4269
static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4270
  32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4271
};
4272
4273
static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4274
  32, 56, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4275
};
4276
4277
static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4278
  32, 56, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4279
};
4280
4281
static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4282
  32, 56, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4283
};
4284
4285
static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4286
  32, 56, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4287
};
4288
4289
static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4290
  32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4291
};
4292
4293
static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4294
  32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4295
};
4296
4297
static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4298
  32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4299
};
4300
4301
static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4302
  32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4303
};
4304
4305
static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4306
  32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4307
};
4308
4309
static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4310
  32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4311
};
4312
4313
static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4314
  32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4315
};
4316
4317
static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4318
  32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4319
};
4320
4321
static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4322
  32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4323
};
4324
4325
static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4326
  32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4327
};
4328
4329
static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4330
  32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4331
};
4332
4333
static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4334
  32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4335
};
4336
4337
static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4338
  32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4339
};
4340
4341
static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4342
  32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4343
};
4344
4345
static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4346
  32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4347
};
4348
4349
static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4350
  32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4351
};
4352
4353
static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
4354
  32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4355
};
4356
4357
static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
4358
  32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4359
};
4360
4361
static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
4362
  32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4363
};
4364
4365
static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
4366
  32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4367
};
4368
4369
static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
4370
  32, 56, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4371
};
4372
4373
static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
4374
  32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4375
};
4376
4377
static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
4378
  32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4379
};
4380
4381
static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
4382
  32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4383
};
4384
4385
static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
4386
  32, 40, 0xff2f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4387
};
4388
4389
static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
4390
  32, 40, 0xff3f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4391
};
4392
4393
static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
4394
  32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4395
};
4396
4397
static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
4398
  32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4399
};
4400
4401
static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = {
4402
  32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4403
};
4404
4405
static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = {
4406
  32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4407
};
4408
4409
static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4410
  32, 48, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4411
};
4412
4413
static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4414
  32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4415
};
4416
4417
static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4418
  32, 56, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4419
};
4420
4421
static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4422
  32, 56, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4423
};
4424
4425
static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4426
  32, 64, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4427
};
4428
4429
static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4430
  32, 64, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4431
};
4432
4433
static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4434
  32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4435
};
4436
4437
static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4438
  32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4439
};
4440
4441
static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4442
  32, 56, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4443
};
4444
4445
static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4446
  32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4447
};
4448
4449
static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4450
  32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4451
};
4452
4453
static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4454
  32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4455
};
4456
4457
static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4458
  32, 56, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4459
};
4460
4461
static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4462
  32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4463
};
4464
4465
static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
4466
  32, 56, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4467
};
4468
4469
static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
4470
  32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4471
};
4472
4473
static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
4474
  32, 64, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4475
};
4476
4477
static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
4478
  32, 64, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4479
};
4480
4481
static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
4482
  16, 16, 0xff0f, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4483
};
4484
4485
static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
4486
  16, 16, 0xff2f, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4487
};
4488
4489
static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
4490
  16, 16, 0xff2f, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4491
};
4492
4493
static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
4494
  16, 16, 0xff8f, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4495
};
4496
4497
static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
4498
  16, 16, 0xffaf, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4499
};
4500
4501
static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
4502
  16, 16, 0xffaf, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4503
};
4504
4505
static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = {
4506
  16, 16, 0xff8f, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4507
};
4508
4509
static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = {
4510
  16, 16, 0xffaf, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4511
};
4512
4513
static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = {
4514
  16, 16, 0xffaf, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4515
};
4516
4517
static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4518
  24, 24, 0xff8f00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4519
};
4520
4521
static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4522
  24, 24, 0xffaf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4523
};
4524
4525
static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4526
  24, 24, 0xffaf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4527
};
4528
4529
static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4530
  32, 32, 0xff8f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4531
};
4532
4533
static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4534
  32, 32, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4535
};
4536
4537
static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4538
  32, 32, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4539
};
4540
4541
static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4542
  32, 40, 0xff8f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4543
};
4544
4545
static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4546
  32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4547
};
4548
4549
static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4550
  32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4551
};
4552
4553
static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4554
  24, 24, 0xffcf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4555
};
4556
4557
static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4558
  24, 24, 0xffef00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4559
};
4560
4561
static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4562
  24, 24, 0xffef00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4563
};
4564
4565
static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4566
  32, 32, 0xffcf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4567
};
4568
4569
static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4570
  32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4571
};
4572
4573
static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4574
  32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4575
};
4576
4577
static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4578
  24, 24, 0xffcf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4579
};
4580
4581
static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4582
  24, 24, 0xffef00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4583
};
4584
4585
static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4586
  24, 24, 0xffef00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4587
};
4588
4589
static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4590
  32, 32, 0xffcf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4591
};
4592
4593
static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4594
  32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4595
};
4596
4597
static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4598
  32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4599
};
4600
4601
static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
4602
  32, 32, 0xffcf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4603
};
4604
4605
static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
4606
  32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4607
};
4608
4609
static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
4610
  32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4611
};
4612
4613
static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
4614
  32, 40, 0xffcf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4615
};
4616
4617
static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
4618
  32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4619
};
4620
4621
static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
4622
  32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
4623
};
4624
4625
static const CGEN_IFMT ifmt_subx32_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
4626
  24, 24, 0xff3f00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { 0 } }
4627
};
4628
4629
static const CGEN_IFMT ifmt_subx32_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
4630
  24, 24, 0xffbf00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { 0 } }
4631
};
4632
4633
static const CGEN_IFMT ifmt_subx32_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = {
4634
  24, 24, 0xffbf00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { 0 } }
4635
};
4636
4637
static const CGEN_IFMT ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4638
  32, 32, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_24_S8) }, { 0 } }
4639
};
4640
4641
static const CGEN_IFMT ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4642
  32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_24_S8) }, { 0 } }
4643
};
4644
4645
static const CGEN_IFMT ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4646
  32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_24_S8) }, { 0 } }
4647
};
4648
4649
static const CGEN_IFMT ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4650
  32, 40, 0xffbf0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4651
};
4652
4653
static const CGEN_IFMT ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4654
  32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4655
};
4656
4657
static const CGEN_IFMT ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4658
  32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4659
};
4660
4661
static const CGEN_IFMT ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
4662
  32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4663
};
4664
4665
static const CGEN_IFMT ifmt_subx32_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4666
  32, 48, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_DSP_40_S8) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4667
};
4668
4669
static const CGEN_IFMT ifmt_subx32_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
4670
  32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_DSP_40_S8) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4671
};
4672
4673
static const CGEN_IFMT ifmt_stzx32_w_Imm_16_HI_Imm_32_HI_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
4674
  32, 48, 0xff3f0000, { { F (F_0_4) }, { F (F_DSP_32_S16) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_S16) }, { 0 } }
4675
};
4676
4677
static const CGEN_IFMT ifmt_stzx32_w_Imm_16_HI_Imm_32_HI_basic_Unprefixed_dst32_An_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
4678
  32, 48, 0xffbf0000, { { F (F_0_4) }, { F (F_DSP_32_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_S16) }, { 0 } }
4679
};
4680
4681
static const CGEN_IFMT ifmt_stzx32_w_Imm_16_HI_Imm_32_HI_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI ATTRIBUTE_UNUSED = {
4682
  32, 48, 0xffbf0000, { { F (F_0_4) }, { F (F_DSP_32_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_S16) }, { 0 } }
4683
};
4684
4685
static const CGEN_IFMT ifmt_stzx32_w_Imm_24_HI_Imm_40_HI_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
4686
  32, 56, 0xffbf0000, { { F (F_0_4) }, { F (F_DSP_24_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_DSP_40_S16) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4687
};
4688
4689
static const CGEN_IFMT ifmt_stzx32_w_Imm_24_HI_Imm_40_HI_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
4690
  32, 56, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_24_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_DSP_40_S16) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4691
};
4692
4693
static const CGEN_IFMT ifmt_stzx32_w_Imm_24_HI_Imm_40_HI_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
4694
  32, 56, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_24_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_DSP_40_S16) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4695
};
4696
4697
static const CGEN_IFMT ifmt_stzx32_w_Imm_32_HI_Imm_48_HI_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
4698
  32, 64, 0xffbf0000, { { F (F_0_4) }, { F (F_DSP_32_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_48_S16) }, { 0 } }
4699
};
4700
4701
static const CGEN_IFMT ifmt_stzx32_w_Imm_32_HI_Imm_48_HI_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
4702
  32, 64, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_48_S16) }, { 0 } }
4703
};
4704
4705
static const CGEN_IFMT ifmt_stzx32_w_Imm_32_HI_Imm_48_HI_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
4706
  32, 64, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_48_S16) }, { 0 } }
4707
};
4708
4709
static const CGEN_IFMT ifmt_stzx32_w_Imm_32_HI_Imm_48_HI_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
4710
  32, 64, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_48_S16) }, { 0 } }
4711
};
4712
4713
static const CGEN_IFMT ifmt_stzx32_w_Imm_40_HI_Imm_56_HI_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
4714
  32, 72, 0xffbf0000, { { F (F_0_4) }, { F (F_DSP_56_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_DSP_40_S16) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4715
};
4716
4717
static const CGEN_IFMT ifmt_stzx32_w_Imm_40_HI_Imm_56_HI_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
4718
  32, 72, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_56_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_DSP_40_S16) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4719
};
4720
4721
static const CGEN_IFMT ifmt_stzx32_b_Imm_16_QI_Imm_24_QI_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
4722
  32, 32, 0xff3f0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_DSP_24_S8) }, { 0 } }
4723
};
4724
4725
static const CGEN_IFMT ifmt_stzx32_b_Imm_16_QI_Imm_24_QI_basic_Unprefixed_dst32_An_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
4726
  32, 32, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_DSP_24_S8) }, { 0 } }
4727
};
4728
4729
static const CGEN_IFMT ifmt_stzx32_b_Imm_16_QI_Imm_24_QI_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI ATTRIBUTE_UNUSED = {
4730
  32, 32, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_DSP_24_S8) }, { 0 } }
4731
};
4732
4733
static const CGEN_IFMT ifmt_stzx32_b_Imm_24_QI_Imm_32_QI_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
4734
  32, 40, 0xffbf0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_24_S8) }, { 0 } }
4735
};
4736
4737
static const CGEN_IFMT ifmt_stzx32_b_Imm_24_QI_Imm_32_QI_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
4738
  32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_24_S8) }, { 0 } }
4739
};
4740
4741
static const CGEN_IFMT ifmt_stzx32_b_Imm_24_QI_Imm_32_QI_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
4742
  32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_24_S8) }, { 0 } }
4743
};
4744
4745
static const CGEN_IFMT ifmt_stzx32_b_Imm_32_QI_Imm_40_QI_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
4746
  32, 48, 0xffbf0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_DSP_40_S8) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4747
};
4748
4749
static const CGEN_IFMT ifmt_stzx32_b_Imm_32_QI_Imm_40_QI_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
4750
  32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_DSP_40_S8) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4751
};
4752
4753
static const CGEN_IFMT ifmt_stzx32_b_Imm_32_QI_Imm_40_QI_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
4754
  32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_DSP_40_S8) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4755
};
4756
4757
static const CGEN_IFMT ifmt_stzx32_b_Imm_32_QI_Imm_40_QI_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
4758
  32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_DSP_40_S8) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4759
};
4760
4761
static const CGEN_IFMT ifmt_stzx32_b_Imm_40_QI_Imm_48_QI_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
4762
  32, 56, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_DSP_40_S8) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_48_S8) }, { 0 } }
4763
};
4764
4765
static const CGEN_IFMT ifmt_stzx32_b_Imm_40_QI_Imm_48_QI_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
4766
  32, 56, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_DSP_40_S8) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_48_S8) }, { 0 } }
4767
};
4768
4769
static const CGEN_IFMT ifmt_stz16_b_S_imm8_dst3_dst16_3_S_R0l_direct_QI ATTRIBUTE_UNUSED = {
4770
  16, 16, 0xff00, { { F (F_0_4) }, { F (F_5_3) }, { F (F_4_1) }, { F (F_DSP_8_S8) }, { 0 } }
4771
};
4772
4773
static const CGEN_IFMT ifmt_stz16_b_S_imm8_dst3_dst16_3_S_R0h_direct_QI ATTRIBUTE_UNUSED = {
4774
  16, 16, 0xff00, { { F (F_0_4) }, { F (F_5_3) }, { F (F_4_1) }, { F (F_DSP_8_S8) }, { 0 } }
4775
};
4776
4777
static const CGEN_IFMT ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_8_SB_relative_QI ATTRIBUTE_UNUSED = {
4778
  24, 24, 0xff0000, { { F (F_0_4) }, { F (F_5_3) }, { F (F_DSP_16_U8) }, { F (F_4_1) }, { F (F_DSP_8_S8) }, { 0 } }
4779
};
4780
4781
static const CGEN_IFMT ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_8_FB_relative_QI ATTRIBUTE_UNUSED = {
4782
  24, 24, 0xff0000, { { F (F_0_4) }, { F (F_5_3) }, { F (F_DSP_16_S8) }, { F (F_4_1) }, { F (F_DSP_8_S8) }, { 0 } }
4783
};
4784
4785
static const CGEN_IFMT ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_16_absolute_QI ATTRIBUTE_UNUSED = {
4786
  32, 32, 0xff000000, { { F (F_0_4) }, { F (F_5_3) }, { F (F_DSP_16_U16) }, { F (F_4_1) }, { F (F_DSP_8_S8) }, { 0 } }
4787
};
4788
4789
static const CGEN_IFMT ifmt_shl32_l_dst_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
4790
  16, 16, 0xff3f, { { F (F_0_4) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4791
};
4792
4793
static const CGEN_IFMT ifmt_shl32_l_dst_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = {
4794
  16, 16, 0xffbf, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4795
};
4796
4797
static const CGEN_IFMT ifmt_shl32_l_dst_dst32_16_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4798
  24, 24, 0xffbf00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4799
};
4800
4801
static const CGEN_IFMT ifmt_shl32_l_dst_dst32_16_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4802
  32, 32, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4803
};
4804
4805
static const CGEN_IFMT ifmt_shl32_l_dst_dst32_16_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4806
  32, 40, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4807
};
4808
4809
static const CGEN_IFMT ifmt_shl32_l_dst_dst32_16_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4810
  24, 24, 0xffff00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4811
};
4812
4813
static const CGEN_IFMT ifmt_shl32_l_dst_dst32_16_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4814
  32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4815
};
4816
4817
static const CGEN_IFMT ifmt_shl32_l_dst_dst32_16_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4818
  24, 24, 0xffff00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4819
};
4820
4821
static const CGEN_IFMT ifmt_shl32_l_dst_dst32_16_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
4822
  32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4823
};
4824
4825
static const CGEN_IFMT ifmt_shl32_l_dst_dst32_16_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
4826
  32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4827
};
4828
4829
static const CGEN_IFMT ifmt_shl32_l_dst_dst32_16_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
4830
  32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4831
};
4832
4833
static const CGEN_IFMT ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
4834
  16, 16, 0xff3f, { { F (F_0_4) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4835
};
4836
4837
static const CGEN_IFMT ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI ATTRIBUTE_UNUSED = {
4838
  16, 16, 0xffbf, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4839
};
4840
4841
static const CGEN_IFMT ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
4842
  24, 24, 0xffbf00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4843
};
4844
4845
static const CGEN_IFMT ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
4846
  32, 32, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4847
};
4848
4849
static const CGEN_IFMT ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
4850
  32, 40, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4851
};
4852
4853
static const CGEN_IFMT ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
4854
  24, 24, 0xffff00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4855
};
4856
4857
static const CGEN_IFMT ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
4858
  32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4859
};
4860
4861
static const CGEN_IFMT ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
4862
  24, 24, 0xffff00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4863
};
4864
4865
static const CGEN_IFMT ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
4866
  32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4867
};
4868
4869
static const CGEN_IFMT ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
4870
  32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4871
};
4872
4873
static const CGEN_IFMT ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
4874
  32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4875
};
4876
4877
static const CGEN_IFMT ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
4878
  16, 16, 0xff3f, { { F (F_0_4) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4879
};
4880
4881
static const CGEN_IFMT ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
4882
  16, 16, 0xffbf, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4883
};
4884
4885
static const CGEN_IFMT ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI ATTRIBUTE_UNUSED = {
4886
  16, 16, 0xffbf, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4887
};
4888
4889
static const CGEN_IFMT ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
4890
  24, 24, 0xffbf00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4891
};
4892
4893
static const CGEN_IFMT ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
4894
  32, 32, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4895
};
4896
4897
static const CGEN_IFMT ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
4898
  32, 40, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4899
};
4900
4901
static const CGEN_IFMT ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
4902
  24, 24, 0xffff00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4903
};
4904
4905
static const CGEN_IFMT ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
4906
  32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4907
};
4908
4909
static const CGEN_IFMT ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
4910
  24, 24, 0xffff00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4911
};
4912
4913
static const CGEN_IFMT ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
4914
  32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4915
};
4916
4917
static const CGEN_IFMT ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
4918
  32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4919
};
4920
4921
static const CGEN_IFMT ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
4922
  32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
4923
};
4924
4925
static const CGEN_IFMT ifmt_shl16_w_dst_dst16_Rn_direct_HI ATTRIBUTE_UNUSED = {
4926
  16, 16, 0xfffc, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
4927
};
4928
4929
static const CGEN_IFMT ifmt_shl16_w_dst_dst16_An_direct_HI ATTRIBUTE_UNUSED = {
4930
  16, 16, 0xfffe, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
4931
};
4932
4933
static const CGEN_IFMT ifmt_shl16_w_dst_dst16_An_indirect_HI ATTRIBUTE_UNUSED = {
4934
  16, 16, 0xfffe, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
4935
};
4936
4937
static const CGEN_IFMT ifmt_shl16_w_dst_dst16_16_8_An_relative_HI ATTRIBUTE_UNUSED = {
4938
  24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
4939
};
4940
4941
static const CGEN_IFMT ifmt_shl16_w_dst_dst16_16_16_An_relative_HI ATTRIBUTE_UNUSED = {
4942
  32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
4943
};
4944
4945
static const CGEN_IFMT ifmt_shl16_w_dst_dst16_16_8_SB_relative_HI ATTRIBUTE_UNUSED = {
4946
  24, 24, 0xffff00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
4947
};
4948
4949
static const CGEN_IFMT ifmt_shl16_w_dst_dst16_16_16_SB_relative_HI ATTRIBUTE_UNUSED = {
4950
  32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
4951
};
4952
4953
static const CGEN_IFMT ifmt_shl16_w_dst_dst16_16_8_FB_relative_HI ATTRIBUTE_UNUSED = {
4954
  24, 24, 0xffff00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
4955
};
4956
4957
static const CGEN_IFMT ifmt_shl16_w_dst_dst16_16_16_absolute_HI ATTRIBUTE_UNUSED = {
4958
  32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
4959
};
4960
4961
static const CGEN_IFMT ifmt_shl16_b_dst_dst16_Rn_direct_QI ATTRIBUTE_UNUSED = {
4962
  16, 16, 0xfffc, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
4963
};
4964
4965
static const CGEN_IFMT ifmt_shl16_b_dst_dst16_An_direct_QI ATTRIBUTE_UNUSED = {
4966
  16, 16, 0xfffe, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
4967
};
4968
4969
static const CGEN_IFMT ifmt_shl16_b_dst_dst16_An_indirect_QI ATTRIBUTE_UNUSED = {
4970
  16, 16, 0xfffe, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
4971
};
4972
4973
static const CGEN_IFMT ifmt_shl16_b_dst_dst16_16_8_An_relative_QI ATTRIBUTE_UNUSED = {
4974
  24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
4975
};
4976
4977
static const CGEN_IFMT ifmt_shl16_b_dst_dst16_16_16_An_relative_QI ATTRIBUTE_UNUSED = {
4978
  32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
4979
};
4980
4981
static const CGEN_IFMT ifmt_shl16_b_dst_dst16_16_8_SB_relative_QI ATTRIBUTE_UNUSED = {
4982
  24, 24, 0xffff00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
4983
};
4984
4985
static const CGEN_IFMT ifmt_shl16_b_dst_dst16_16_16_SB_relative_QI ATTRIBUTE_UNUSED = {
4986
  32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
4987
};
4988
4989
static const CGEN_IFMT ifmt_shl16_b_dst_dst16_16_8_FB_relative_QI ATTRIBUTE_UNUSED = {
4990
  24, 24, 0xffff00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
4991
};
4992
4993
static const CGEN_IFMT ifmt_shl16_b_dst_dst16_16_16_absolute_QI ATTRIBUTE_UNUSED = {
4994
  32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
4995
};
4996
4997
static const CGEN_IFMT ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
4998
  16, 16, 0xff30, { { F (F_0_3) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
4999
};
5000
5001
static const CGEN_IFMT ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_An_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
5002
  16, 16, 0xffb0, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
5003
};
5004
5005
static const CGEN_IFMT ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_An_indirect_Unprefixed_HI ATTRIBUTE_UNUSED = {
5006
  16, 16, 0xffb0, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
5007
};
5008
5009
static const CGEN_IFMT ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
5010
  24, 24, 0xffb000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
5011
};
5012
5013
static const CGEN_IFMT ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
5014
  32, 32, 0xffb00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
5015
};
5016
5017
static const CGEN_IFMT ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
5018
  32, 40, 0xffb00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
5019
};
5020
5021
static const CGEN_IFMT ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
5022
  24, 24, 0xfff000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
5023
};
5024
5025
static const CGEN_IFMT ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
5026
  32, 32, 0xfff00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
5027
};
5028
5029
static const CGEN_IFMT ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
5030
  24, 24, 0xfff000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
5031
};
5032
5033
static const CGEN_IFMT ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
5034
  32, 32, 0xfff00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
5035
};
5036
5037
static const CGEN_IFMT ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
5038
  32, 32, 0xfff00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
5039
};
5040
5041
static const CGEN_IFMT ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_24_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
5042
  32, 40, 0xfff00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
5043
};
5044
5045
static const CGEN_IFMT ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_Rn_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
5046
  16, 16, 0xff30, { { F (F_0_3) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
5047
};
5048
5049
static const CGEN_IFMT ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_An_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
5050
  16, 16, 0xffb0, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
5051
};
5052
5053
static const CGEN_IFMT ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_An_indirect_Unprefixed_QI ATTRIBUTE_UNUSED = {
5054
  16, 16, 0xffb0, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
5055
};
5056
5057
static const CGEN_IFMT ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
5058
  24, 24, 0xffb000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
5059
};
5060
5061
static const CGEN_IFMT ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
5062
  32, 32, 0xffb00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
5063
};
5064
5065
static const CGEN_IFMT ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
5066
  32, 40, 0xffb00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
5067
};
5068
5069
static const CGEN_IFMT ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
5070
  24, 24, 0xfff000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
5071
};
5072
5073
static const CGEN_IFMT ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
5074
  32, 32, 0xfff00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
5075
};
5076
5077
static const CGEN_IFMT ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
5078
  24, 24, 0xfff000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
5079
};
5080
5081
static const CGEN_IFMT ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
5082
  32, 32, 0xfff00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
5083
};
5084
5085
static const CGEN_IFMT ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
5086
  32, 32, 0xfff00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
5087
};
5088
5089
static const CGEN_IFMT ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_24_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
5090
  32, 40, 0xfff00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
5091
};
5092
5093
static const CGEN_IFMT ifmt_shl16_w_imm4_Q_16_dst16_Rn_direct_HI ATTRIBUTE_UNUSED = {
5094
  16, 16, 0xff0c, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
5095
};
5096
5097
static const CGEN_IFMT ifmt_shl16_w_imm4_Q_16_dst16_An_direct_HI ATTRIBUTE_UNUSED = {
5098
  16, 16, 0xff0e, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
5099
};
5100
5101
static const CGEN_IFMT ifmt_shl16_w_imm4_Q_16_dst16_An_indirect_HI ATTRIBUTE_UNUSED = {
5102
  16, 16, 0xff0e, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
5103
};
5104
5105
static const CGEN_IFMT ifmt_shl16_w_imm4_Q_16_dst16_16_8_An_relative_HI ATTRIBUTE_UNUSED = {
5106
  24, 24, 0xff0e00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
5107
};
5108
5109
static const CGEN_IFMT ifmt_shl16_w_imm4_Q_16_dst16_16_16_An_relative_HI ATTRIBUTE_UNUSED = {
5110
  32, 32, 0xff0e0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
5111
};
5112
5113
static const CGEN_IFMT ifmt_shl16_w_imm4_Q_16_dst16_16_8_SB_relative_HI ATTRIBUTE_UNUSED = {
5114
  24, 24, 0xff0f00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
5115
};
5116
5117
static const CGEN_IFMT ifmt_shl16_w_imm4_Q_16_dst16_16_16_SB_relative_HI ATTRIBUTE_UNUSED = {
5118
  32, 32, 0xff0f0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
5119
};
5120
5121
static const CGEN_IFMT ifmt_shl16_w_imm4_Q_16_dst16_16_8_FB_relative_HI ATTRIBUTE_UNUSED = {
5122
  24, 24, 0xff0f00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
5123
};
5124
5125
static const CGEN_IFMT ifmt_shl16_w_imm4_Q_16_dst16_16_16_absolute_HI ATTRIBUTE_UNUSED = {
5126
  32, 32, 0xff0f0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
5127
};
5128
5129
static const CGEN_IFMT ifmt_shl16_b_imm4_Q_16_dst16_Rn_direct_QI ATTRIBUTE_UNUSED = {
5130
  16, 16, 0xff0c, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
5131
};
5132
5133
static const CGEN_IFMT ifmt_shl16_b_imm4_Q_16_dst16_An_direct_QI ATTRIBUTE_UNUSED = {
5134
  16, 16, 0xff0e, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
5135
};
5136
5137
static const CGEN_IFMT ifmt_shl16_b_imm4_Q_16_dst16_An_indirect_QI ATTRIBUTE_UNUSED = {
5138
  16, 16, 0xff0e, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
5139
};
5140
5141
static const CGEN_IFMT ifmt_shl16_b_imm4_Q_16_dst16_16_8_An_relative_QI ATTRIBUTE_UNUSED = {
5142
  24, 24, 0xff0e00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
5143
};
5144
5145
static const CGEN_IFMT ifmt_shl16_b_imm4_Q_16_dst16_16_16_An_relative_QI ATTRIBUTE_UNUSED = {
5146
  32, 32, 0xff0e0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
5147
};
5148
5149
static const CGEN_IFMT ifmt_shl16_b_imm4_Q_16_dst16_16_8_SB_relative_QI ATTRIBUTE_UNUSED = {
5150
  24, 24, 0xff0f00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
5151
};
5152
5153
static const CGEN_IFMT ifmt_shl16_b_imm4_Q_16_dst16_16_16_SB_relative_QI ATTRIBUTE_UNUSED = {
5154
  32, 32, 0xff0f0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
5155
};
5156
5157
static const CGEN_IFMT ifmt_shl16_b_imm4_Q_16_dst16_16_8_FB_relative_QI ATTRIBUTE_UNUSED = {
5158
  24, 24, 0xff0f00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
5159
};
5160
5161
static const CGEN_IFMT ifmt_shl16_b_imm4_Q_16_dst16_16_16_absolute_QI ATTRIBUTE_UNUSED = {
5162
  32, 32, 0xff0f0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
5163
};
5164
5165
static const CGEN_IFMT ifmt_sccnd_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
5166
  16, 16, 0xff30, { { F (F_0_4) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_COND16) }, { 0 } }
5167
};
5168
5169
static const CGEN_IFMT ifmt_sccnd_dst32_An_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
5170
  16, 16, 0xffb0, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_COND16) }, { 0 } }
5171
};
5172
5173
static const CGEN_IFMT ifmt_sccnd_dst32_An_indirect_Unprefixed_HI ATTRIBUTE_UNUSED = {
5174
  16, 16, 0xffb0, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_COND16) }, { 0 } }
5175
};
5176
5177
static const CGEN_IFMT ifmt_sccnd_dst32_16_8_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
5178
  24, 24, 0xffb000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_COND16) }, { 0 } }
5179
};
5180
5181
static const CGEN_IFMT ifmt_sccnd_dst32_16_16_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
5182
  32, 32, 0xffb00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_COND16) }, { 0 } }
5183
};
5184
5185
static const CGEN_IFMT ifmt_sccnd_dst32_16_24_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
5186
  32, 40, 0xffb00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_COND16) }, { 0 } }
5187
};
5188
5189
static const CGEN_IFMT ifmt_sccnd_dst32_16_8_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
5190
  24, 24, 0xfff000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_COND16) }, { 0 } }
5191
};
5192
5193
static const CGEN_IFMT ifmt_sccnd_dst32_16_16_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
5194
  32, 32, 0xfff00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_COND16) }, { 0 } }
5195
};
5196
5197
static const CGEN_IFMT ifmt_sccnd_dst32_16_8_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
5198
  24, 24, 0xfff000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_COND16) }, { 0 } }
5199
};
5200
5201
static const CGEN_IFMT ifmt_sccnd_dst32_16_16_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
5202
  32, 32, 0xfff00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_COND16) }, { 0 } }
5203
};
5204
5205
static const CGEN_IFMT ifmt_sccnd_dst32_16_16_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
5206
  32, 32, 0xfff00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_COND16) }, { 0 } }
5207
};
5208
5209
static const CGEN_IFMT ifmt_sccnd_dst32_16_24_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
5210
  32, 40, 0xfff00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_COND16) }, { 0 } }
5211
};
5212
5213
static const CGEN_IFMT ifmt_sbjnz32_w_imm4_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
5214
  32, 32, 0xffb00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { F (F_LAB_24_8) }, { 0 } }
5215
};
5216
5217
static const CGEN_IFMT ifmt_sbjnz32_w_imm4_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
5218
  32, 32, 0xfff00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { F (F_LAB_24_8) }, { 0 } }
5219
};
5220
5221
static const CGEN_IFMT ifmt_sbjnz32_w_imm4_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
5222
  32, 32, 0xfff00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { F (F_LAB_24_8) }, { 0 } }
5223
};
5224
5225
static const CGEN_IFMT ifmt_sbjnz32_w_imm4_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
5226
  32, 40, 0xffb00000, { { F (F_0_4) }, { F (F_LAB_32_8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
5227
};
5228
5229
static const CGEN_IFMT ifmt_sbjnz32_w_imm4_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
5230
  32, 40, 0xfff00000, { { F (F_0_4) }, { F (F_LAB_32_8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
5231
};
5232
5233
static const CGEN_IFMT ifmt_sbjnz32_w_imm4_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
5234
  32, 40, 0xfff00000, { { F (F_0_4) }, { F (F_LAB_32_8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
5235
};
5236
5237
static const CGEN_IFMT ifmt_sbjnz32_w_imm4_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
5238
  32, 40, 0xfff00000, { { F (F_0_4) }, { F (F_LAB_32_8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
5239
};
5240
5241
static const CGEN_IFMT ifmt_sbjnz32_w_imm4_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
5242
  32, 48, 0xffb00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_LAB_40_8) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
5243
};
5244
5245
static const CGEN_IFMT ifmt_sbjnz32_w_imm4_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
5246
  32, 48, 0xfff00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_LAB_40_8) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
5247
};
5248
5249
static const CGEN_IFMT ifmt_sbjnz32_w_imm4_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
5250
  24, 24, 0xff3000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { F (F_LAB_16_8) }, { 0 } }
5251
};
5252
5253
static const CGEN_IFMT ifmt_sbjnz32_w_imm4_basic_Unprefixed_dst32_An_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
5254
  24, 24, 0xffb000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { F (F_LAB_16_8) }, { 0 } }
5255
};
5256
5257
static const CGEN_IFMT ifmt_sbjnz32_w_imm4_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI ATTRIBUTE_UNUSED = {
5258
  24, 24, 0xffb000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { F (F_LAB_16_8) }, { 0 } }
5259
};
5260
5261
static const CGEN_IFMT ifmt_sbjnz32_b_imm4_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
5262
  32, 32, 0xffb00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { F (F_LAB_24_8) }, { 0 } }
5263
};
5264
5265
static const CGEN_IFMT ifmt_sbjnz32_b_imm4_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
5266
  32, 32, 0xfff00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { F (F_LAB_24_8) }, { 0 } }
5267
};
5268
5269
static const CGEN_IFMT ifmt_sbjnz32_b_imm4_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
5270
  32, 32, 0xfff00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { F (F_LAB_24_8) }, { 0 } }
5271
};
5272
5273
static const CGEN_IFMT ifmt_sbjnz32_b_imm4_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
5274
  32, 40, 0xffb00000, { { F (F_0_4) }, { F (F_LAB_32_8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
5275
};
5276
5277
static const CGEN_IFMT ifmt_sbjnz32_b_imm4_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
5278
  32, 40, 0xfff00000, { { F (F_0_4) }, { F (F_LAB_32_8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
5279
};
5280
5281
static const CGEN_IFMT ifmt_sbjnz32_b_imm4_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
5282
  32, 40, 0xfff00000, { { F (F_0_4) }, { F (F_LAB_32_8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
5283
};
5284
5285
static const CGEN_IFMT ifmt_sbjnz32_b_imm4_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
5286
  32, 40, 0xfff00000, { { F (F_0_4) }, { F (F_LAB_32_8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
5287
};
5288
5289
static const CGEN_IFMT ifmt_sbjnz32_b_imm4_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
5290
  32, 48, 0xffb00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_LAB_40_8) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
5291
};
5292
5293
static const CGEN_IFMT ifmt_sbjnz32_b_imm4_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
5294
  32, 48, 0xfff00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_LAB_40_8) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
5295
};
5296
5297
static const CGEN_IFMT ifmt_sbjnz32_b_imm4_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
5298
  24, 24, 0xff3000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { F (F_LAB_16_8) }, { 0 } }
5299
};
5300
5301
static const CGEN_IFMT ifmt_sbjnz32_b_imm4_basic_Unprefixed_dst32_An_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
5302
  24, 24, 0xffb000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { F (F_LAB_16_8) }, { 0 } }
5303
};
5304
5305
static const CGEN_IFMT ifmt_sbjnz32_b_imm4_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI ATTRIBUTE_UNUSED = {
5306
  24, 24, 0xffb000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { F (F_LAB_16_8) }, { 0 } }
5307
};
5308
5309
static const CGEN_IFMT ifmt_sbjnz16_w_imm4_16_8_dst16_16_8_An_relative_HI ATTRIBUTE_UNUSED = {
5310
  32, 32, 0xff0e0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_24_8) }, { 0 } }
5311
};
5312
5313
static const CGEN_IFMT ifmt_sbjnz16_w_imm4_16_8_dst16_16_8_SB_relative_HI ATTRIBUTE_UNUSED = {
5314
  32, 32, 0xff0f0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_24_8) }, { 0 } }
5315
};
5316
5317
static const CGEN_IFMT ifmt_sbjnz16_w_imm4_16_8_dst16_16_8_FB_relative_HI ATTRIBUTE_UNUSED = {
5318
  32, 32, 0xff0f0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_24_8) }, { 0 } }
5319
};
5320
5321
static const CGEN_IFMT ifmt_sbjnz16_w_imm4_16_16_dst16_16_16_An_relative_HI ATTRIBUTE_UNUSED = {
5322
  32, 40, 0xff0e0000, { { F (F_0_4) }, { F (F_LAB_32_8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
5323
};
5324
5325
static const CGEN_IFMT ifmt_sbjnz16_w_imm4_16_16_dst16_16_16_SB_relative_HI ATTRIBUTE_UNUSED = {
5326
  32, 40, 0xff0f0000, { { F (F_0_4) }, { F (F_LAB_32_8) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
5327
};
5328
5329
static const CGEN_IFMT ifmt_sbjnz16_w_imm4_16_16_dst16_16_16_absolute_HI ATTRIBUTE_UNUSED = {
5330
  32, 40, 0xff0f0000, { { F (F_0_4) }, { F (F_LAB_32_8) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
5331
};
5332
5333
static const CGEN_IFMT ifmt_sbjnz16_w_imm4_basic_dst16_Rn_direct_HI ATTRIBUTE_UNUSED = {
5334
  24, 24, 0xff0c00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_16_8) }, { 0 } }
5335
};
5336
5337
static const CGEN_IFMT ifmt_sbjnz16_w_imm4_basic_dst16_An_direct_HI ATTRIBUTE_UNUSED = {
5338
  24, 24, 0xff0e00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_16_8) }, { 0 } }
5339
};
5340
5341
static const CGEN_IFMT ifmt_sbjnz16_w_imm4_basic_dst16_An_indirect_HI ATTRIBUTE_UNUSED = {
5342
  24, 24, 0xff0e00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_16_8) }, { 0 } }
5343
};
5344
5345
static const CGEN_IFMT ifmt_sbjnz16_b_imm4_16_8_dst16_16_8_An_relative_QI ATTRIBUTE_UNUSED = {
5346
  32, 32, 0xff0e0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_24_8) }, { 0 } }
5347
};
5348
5349
static const CGEN_IFMT ifmt_sbjnz16_b_imm4_16_8_dst16_16_8_SB_relative_QI ATTRIBUTE_UNUSED = {
5350
  32, 32, 0xff0f0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_24_8) }, { 0 } }
5351
};
5352
5353
static const CGEN_IFMT ifmt_sbjnz16_b_imm4_16_8_dst16_16_8_FB_relative_QI ATTRIBUTE_UNUSED = {
5354
  32, 32, 0xff0f0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_24_8) }, { 0 } }
5355
};
5356
5357
static const CGEN_IFMT ifmt_sbjnz16_b_imm4_16_16_dst16_16_16_An_relative_QI ATTRIBUTE_UNUSED = {
5358
  32, 40, 0xff0e0000, { { F (F_0_4) }, { F (F_LAB_32_8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
5359
};
5360
5361
static const CGEN_IFMT ifmt_sbjnz16_b_imm4_16_16_dst16_16_16_SB_relative_QI ATTRIBUTE_UNUSED = {
5362
  32, 40, 0xff0f0000, { { F (F_0_4) }, { F (F_LAB_32_8) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
5363
};
5364
5365
static const CGEN_IFMT ifmt_sbjnz16_b_imm4_16_16_dst16_16_16_absolute_QI ATTRIBUTE_UNUSED = {
5366
  32, 40, 0xff0f0000, { { F (F_0_4) }, { F (F_LAB_32_8) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
5367
};
5368
5369
static const CGEN_IFMT ifmt_sbjnz16_b_imm4_basic_dst16_Rn_direct_QI ATTRIBUTE_UNUSED = {
5370
  24, 24, 0xff0c00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_16_8) }, { 0 } }
5371
};
5372
5373
static const CGEN_IFMT ifmt_sbjnz16_b_imm4_basic_dst16_An_direct_QI ATTRIBUTE_UNUSED = {
5374
  24, 24, 0xff0e00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_16_8) }, { 0 } }
5375
};
5376
5377
static const CGEN_IFMT ifmt_sbjnz16_b_imm4_basic_dst16_An_indirect_QI ATTRIBUTE_UNUSED = {
5378
  24, 24, 0xff0e00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_16_8) }, { 0 } }
5379
};
5380
5381
static const CGEN_IFMT ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
5382
  32, 40, 0xffff3f00, { { F (F_0_4) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5383
};
5384
5385
static const CGEN_IFMT ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
5386
  32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5387
};
5388
5389
static const CGEN_IFMT ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = {
5390
  32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5391
};
5392
5393
static const CGEN_IFMT ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
5394
  32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_DSP_32_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5395
};
5396
5397
static const CGEN_IFMT ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
5398
  32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_DSP_32_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U8) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5399
};
5400
5401
static const CGEN_IFMT ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
5402
  32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_DSP_32_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S8) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5403
};
5404
5405
static const CGEN_IFMT ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
5406
  32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_40_S16) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5407
};
5408
5409
static const CGEN_IFMT ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
5410
  32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_40_S16) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5411
};
5412
5413
static const CGEN_IFMT ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
5414
  32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_40_S16) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5415
};
5416
5417
static const CGEN_IFMT ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
5418
  32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_40_S16) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5419
};
5420
5421
static const CGEN_IFMT ifmt_sbb32_w_imm_G_24_24_Prefixed_dst32_24_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
5422
  32, 64, 0xffffbf00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_DSP_48_S16) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5423
};
5424
5425
static const CGEN_IFMT ifmt_sbb32_w_imm_G_24_24_Prefixed_dst32_24_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
5426
  32, 64, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U24) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_DSP_48_S16) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5427
};
5428
5429
static const CGEN_IFMT ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_Rn_direct_Prefixed_QI ATTRIBUTE_UNUSED = {
5430
  32, 32, 0xffff3f00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_QI) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { F (F_DSP_24_S8) }, { 0 } }
5431
};
5432
5433
static const CGEN_IFMT ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_An_direct_Prefixed_QI ATTRIBUTE_UNUSED = {
5434
  32, 32, 0xffffbf00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { F (F_DSP_24_S8) }, { 0 } }
5435
};
5436
5437
static const CGEN_IFMT ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_An_indirect_Prefixed_QI ATTRIBUTE_UNUSED = {
5438
  32, 32, 0xffffbf00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { F (F_DSP_24_S8) }, { 0 } }
5439
};
5440
5441
static const CGEN_IFMT ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
5442
  32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5443
};
5444
5445
static const CGEN_IFMT ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
5446
  32, 40, 0xffffff00, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U8) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5447
};
5448
5449
static const CGEN_IFMT ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
5450
  32, 40, 0xffffff00, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S8) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5451
};
5452
5453
static const CGEN_IFMT ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
5454
  32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_40_S8) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5455
};
5456
5457
static const CGEN_IFMT ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
5458
  32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_40_S8) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5459
};
5460
5461
static const CGEN_IFMT ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
5462
  32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_40_S8) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5463
};
5464
5465
static const CGEN_IFMT ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_absolute_Prefixed_QI ATTRIBUTE_UNUSED = {
5466
  32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_40_S8) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5467
};
5468
5469
static const CGEN_IFMT ifmt_sbb32_b_imm_G_24_24_Prefixed_dst32_24_24_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
5470
  32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_DSP_48_S8) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5471
};
5472
5473
static const CGEN_IFMT ifmt_sbb32_b_imm_G_24_24_Prefixed_dst32_24_24_absolute_Prefixed_QI ATTRIBUTE_UNUSED = {
5474
  32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U24) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_DSP_48_S8) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5475
};
5476
5477
static const CGEN_IFMT ifmt_rorc16_w_16_dst16_Rn_direct_HI ATTRIBUTE_UNUSED = {
5478
  16, 16, 0xfffc, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
5479
};
5480
5481
static const CGEN_IFMT ifmt_rorc16_w_16_dst16_An_direct_HI ATTRIBUTE_UNUSED = {
5482
  16, 16, 0xfffe, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
5483
};
5484
5485
static const CGEN_IFMT ifmt_rorc16_w_16_dst16_An_indirect_HI ATTRIBUTE_UNUSED = {
5486
  16, 16, 0xfffe, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
5487
};
5488
5489
static const CGEN_IFMT ifmt_rorc16_w_16_dst16_16_8_An_relative_HI ATTRIBUTE_UNUSED = {
5490
  24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
5491
};
5492
5493
static const CGEN_IFMT ifmt_rorc16_w_16_dst16_16_16_An_relative_HI ATTRIBUTE_UNUSED = {
5494
  32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
5495
};
5496
5497
static const CGEN_IFMT ifmt_rorc16_w_16_dst16_16_8_SB_relative_HI ATTRIBUTE_UNUSED = {
5498
  24, 24, 0xffff00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
5499
};
5500
5501
static const CGEN_IFMT ifmt_rorc16_w_16_dst16_16_16_SB_relative_HI ATTRIBUTE_UNUSED = {
5502
  32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
5503
};
5504
5505
static const CGEN_IFMT ifmt_rorc16_w_16_dst16_16_8_FB_relative_HI ATTRIBUTE_UNUSED = {
5506
  24, 24, 0xffff00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
5507
};
5508
5509
static const CGEN_IFMT ifmt_rorc16_w_16_dst16_16_16_absolute_HI ATTRIBUTE_UNUSED = {
5510
  32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
5511
};
5512
5513
static const CGEN_IFMT ifmt_rorc16_b_16_dst16_Rn_direct_QI ATTRIBUTE_UNUSED = {
5514
  16, 16, 0xfffc, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
5515
};
5516
5517
static const CGEN_IFMT ifmt_rorc16_b_16_dst16_An_direct_QI ATTRIBUTE_UNUSED = {
5518
  16, 16, 0xfffe, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
5519
};
5520
5521
static const CGEN_IFMT ifmt_rorc16_b_16_dst16_An_indirect_QI ATTRIBUTE_UNUSED = {
5522
  16, 16, 0xfffe, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
5523
};
5524
5525
static const CGEN_IFMT ifmt_rorc16_b_16_dst16_16_8_An_relative_QI ATTRIBUTE_UNUSED = {
5526
  24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
5527
};
5528
5529
static const CGEN_IFMT ifmt_rorc16_b_16_dst16_16_16_An_relative_QI ATTRIBUTE_UNUSED = {
5530
  32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
5531
};
5532
5533
static const CGEN_IFMT ifmt_rorc16_b_16_dst16_16_8_SB_relative_QI ATTRIBUTE_UNUSED = {
5534
  24, 24, 0xffff00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
5535
};
5536
5537
static const CGEN_IFMT ifmt_rorc16_b_16_dst16_16_16_SB_relative_QI ATTRIBUTE_UNUSED = {
5538
  32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
5539
};
5540
5541
static const CGEN_IFMT ifmt_rorc16_b_16_dst16_16_8_FB_relative_QI ATTRIBUTE_UNUSED = {
5542
  24, 24, 0xffff00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
5543
};
5544
5545
static const CGEN_IFMT ifmt_rorc16_b_16_dst16_16_16_absolute_QI ATTRIBUTE_UNUSED = {
5546
  32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
5547
};
5548
5549
static const CGEN_IFMT ifmt_pusha32_16_Unprefixed_Mova_dst32_An_indirect_Unprefixed_Mova_SI ATTRIBUTE_UNUSED = {
5550
  16, 16, 0xffbf, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
5551
};
5552
5553
static const CGEN_IFMT ifmt_pusha32_16_Unprefixed_Mova_dst32_16_8_An_relative_Unprefixed_Mova_SI ATTRIBUTE_UNUSED = {
5554
  24, 24, 0xffbf00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
5555
};
5556
5557
static const CGEN_IFMT ifmt_pusha32_16_Unprefixed_Mova_dst32_16_16_An_relative_Unprefixed_Mova_SI ATTRIBUTE_UNUSED = {
5558
  32, 32, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
5559
};
5560
5561
static const CGEN_IFMT ifmt_pusha32_16_Unprefixed_Mova_dst32_16_24_An_relative_Unprefixed_Mova_SI ATTRIBUTE_UNUSED = {
5562
  32, 40, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
5563
};
5564
5565
static const CGEN_IFMT ifmt_pusha32_16_Unprefixed_Mova_dst32_16_8_SB_relative_Unprefixed_Mova_SI ATTRIBUTE_UNUSED = {
5566
  24, 24, 0xffff00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
5567
};
5568
5569
static const CGEN_IFMT ifmt_pusha32_16_Unprefixed_Mova_dst32_16_16_SB_relative_Unprefixed_Mova_SI ATTRIBUTE_UNUSED = {
5570
  32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
5571
};
5572
5573
static const CGEN_IFMT ifmt_pusha32_16_Unprefixed_Mova_dst32_16_8_FB_relative_Unprefixed_Mova_SI ATTRIBUTE_UNUSED = {
5574
  24, 24, 0xffff00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
5575
};
5576
5577
static const CGEN_IFMT ifmt_pusha32_16_Unprefixed_Mova_dst32_16_16_FB_relative_Unprefixed_Mova_SI ATTRIBUTE_UNUSED = {
5578
  32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
5579
};
5580
5581
static const CGEN_IFMT ifmt_pusha32_16_Unprefixed_Mova_dst32_16_16_absolute_Unprefixed_Mova_SI ATTRIBUTE_UNUSED = {
5582
  32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
5583
};
5584
5585
static const CGEN_IFMT ifmt_pusha32_16_Unprefixed_Mova_dst32_16_24_absolute_Unprefixed_Mova_SI ATTRIBUTE_UNUSED = {
5586
  32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
5587
};
5588
5589
static const CGEN_IFMT ifmt_pusha16_16_Mova_dst16_An_indirect_Mova_HI ATTRIBUTE_UNUSED = {
5590
  16, 16, 0xfffe, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
5591
};
5592
5593
static const CGEN_IFMT ifmt_pusha16_16_Mova_dst16_16_8_An_relative_Mova_HI ATTRIBUTE_UNUSED = {
5594
  24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
5595
};
5596
5597
static const CGEN_IFMT ifmt_pusha16_16_Mova_dst16_16_16_An_relative_Mova_HI ATTRIBUTE_UNUSED = {
5598
  32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
5599
};
5600
5601
static const CGEN_IFMT ifmt_pusha16_16_Mova_dst16_16_8_SB_relative_Mova_HI ATTRIBUTE_UNUSED = {
5602
  24, 24, 0xffff00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
5603
};
5604
5605
static const CGEN_IFMT ifmt_pusha16_16_Mova_dst16_16_16_SB_relative_Mova_HI ATTRIBUTE_UNUSED = {
5606
  32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
5607
};
5608
5609
static const CGEN_IFMT ifmt_pusha16_16_Mova_dst16_16_8_FB_relative_Mova_HI ATTRIBUTE_UNUSED = {
5610
  24, 24, 0xffff00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
5611
};
5612
5613
static const CGEN_IFMT ifmt_pusha16_16_Mova_dst16_16_16_absolute_Mova_HI ATTRIBUTE_UNUSED = {
5614
  32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
5615
};
5616
5617
static const CGEN_IFMT ifmt_push16_b_s_an_An16_push_S_derived ATTRIBUTE_UNUSED = {
5618
  8, 8, 0xf7, { { F (F_0_4) }, { F (F_4_1) }, { F (F_5_3) }, { 0 } }
5619
};
5620
5621
static const CGEN_IFMT ifmt_push16_b_s_rn_Rn16_push_S_derived ATTRIBUTE_UNUSED = {
5622
  8, 8, 0xf7, { { F (F_0_4) }, { F (F_4_1) }, { F (F_5_3) }, { 0 } }
5623
};
5624
5625
static const CGEN_IFMT ifmt_or16_b_S_r0l_r0h_srcdst16_r0l_r0h_S_derived ATTRIBUTE_UNUSED = {
5626
  8, 8, 0xfb, { { F (F_0_4) }, { F (F_6_2) }, { F (F_5_1) }, { F (F_4_1) }, { 0 } }
5627
};
5628
5629
static const CGEN_IFMT ifmt_or16_b_S_src2_src16_2_S_8_SB_relative_QI ATTRIBUTE_UNUSED = {
5630
  16, 16, 0xfb00, { { F (F_0_4) }, { F (F_6_2) }, { F (F_DSP_8_U8) }, { F (F_4_1) }, { F (F_DST16_RN_QI_S) }, { 0 } }
5631
};
5632
5633
static const CGEN_IFMT ifmt_or16_b_S_src2_src16_2_S_8_FB_relative_QI ATTRIBUTE_UNUSED = {
5634
  16, 16, 0xfb00, { { F (F_0_4) }, { F (F_6_2) }, { F (F_DSP_8_S8) }, { F (F_4_1) }, { F (F_DST16_RN_QI_S) }, { 0 } }
5635
};
5636
5637
static const CGEN_IFMT ifmt_or16_b_S_src2_src16_2_S_16_absolute_QI ATTRIBUTE_UNUSED = {
5638
  24, 24, 0xfb0000, { { F (F_0_4) }, { F (F_6_2) }, { F (F_DSP_8_U16) }, { F (F_4_1) }, { F (F_DST16_RN_QI_S) }, { 0 } }
5639
};
5640
5641
static const CGEN_IFMT ifmt_not16_b_s_dst16_3_S_R0l_direct_QI ATTRIBUTE_UNUSED = {
5642
  8, 8, 0xff, { { F (F_0_4) }, { F (F_5_3) }, { F (F_4_1) }, { 0 } }
5643
};
5644
5645
static const CGEN_IFMT ifmt_not16_b_s_dst16_3_S_R0h_direct_QI ATTRIBUTE_UNUSED = {
5646
  8, 8, 0xff, { { F (F_0_4) }, { F (F_5_3) }, { F (F_4_1) }, { 0 } }
5647
};
5648
5649
static const CGEN_IFMT ifmt_not16_b_s_dst16_3_S_8_8_SB_relative_QI ATTRIBUTE_UNUSED = {
5650
  16, 16, 0xff00, { { F (F_0_4) }, { F (F_5_3) }, { F (F_DSP_8_U8) }, { F (F_4_1) }, { 0 } }
5651
};
5652
5653
static const CGEN_IFMT ifmt_not16_b_s_dst16_3_S_8_8_FB_relative_QI ATTRIBUTE_UNUSED = {
5654
  16, 16, 0xff00, { { F (F_0_4) }, { F (F_5_3) }, { F (F_DSP_8_S8) }, { F (F_4_1) }, { 0 } }
5655
};
5656
5657
static const CGEN_IFMT ifmt_not16_b_s_dst16_3_S_8_16_absolute_QI ATTRIBUTE_UNUSED = {
5658
  24, 24, 0xff0000, { { F (F_0_4) }, { F (F_5_3) }, { F (F_DSP_8_U16) }, { F (F_4_1) }, { 0 } }
5659
};
5660
5661
static const CGEN_IFMT ifmt_mulex_dst32_R3_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
5662
  16, 16, 0xffff, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
5663
};
5664
5665
static const CGEN_IFMT ifmt_mulu_l_dst32_Rn_direct_Prefixed_SI ATTRIBUTE_UNUSED = {
5666
  24, 24, 0xffff3f, { { F (F_0_4) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_SI) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5667
};
5668
5669
static const CGEN_IFMT ifmt_mulu_l_dst32_An_direct_Prefixed_SI ATTRIBUTE_UNUSED = {
5670
  24, 24, 0xffffbf, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5671
};
5672
5673
static const CGEN_IFMT ifmt_mulu_l_dst32_An_indirect_Prefixed_SI ATTRIBUTE_UNUSED = {
5674
  24, 24, 0xffffbf, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5675
};
5676
5677
static const CGEN_IFMT ifmt_mulu_l_dst32_24_8_An_relative_Prefixed_SI ATTRIBUTE_UNUSED = {
5678
  32, 32, 0xffffbf00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5679
};
5680
5681
static const CGEN_IFMT ifmt_mulu_l_dst32_24_16_An_relative_Prefixed_SI ATTRIBUTE_UNUSED = {
5682
  32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5683
};
5684
5685
static const CGEN_IFMT ifmt_mulu_l_dst32_24_24_An_relative_Prefixed_SI ATTRIBUTE_UNUSED = {
5686
  32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5687
};
5688
5689
static const CGEN_IFMT ifmt_mulu_l_dst32_24_8_SB_relative_Prefixed_SI ATTRIBUTE_UNUSED = {
5690
  32, 32, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U8) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5691
};
5692
5693
static const CGEN_IFMT ifmt_mulu_l_dst32_24_16_SB_relative_Prefixed_SI ATTRIBUTE_UNUSED = {
5694
  32, 40, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5695
};
5696
5697
static const CGEN_IFMT ifmt_mulu_l_dst32_24_8_FB_relative_Prefixed_SI ATTRIBUTE_UNUSED = {
5698
  32, 32, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S8) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5699
};
5700
5701
static const CGEN_IFMT ifmt_mulu_l_dst32_24_16_FB_relative_Prefixed_SI ATTRIBUTE_UNUSED = {
5702
  32, 40, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5703
};
5704
5705
static const CGEN_IFMT ifmt_mulu_l_dst32_24_16_absolute_Prefixed_SI ATTRIBUTE_UNUSED = {
5706
  32, 40, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5707
};
5708
5709
static const CGEN_IFMT ifmt_mulu_l_dst32_24_24_absolute_Prefixed_SI ATTRIBUTE_UNUSED = {
5710
  32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U24) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5711
};
5712
5713
static const CGEN_IFMT ifmt_movhh32_src_r0l_dst32_Rn_direct_Prefixed_QI ATTRIBUTE_UNUSED = {
5714
  24, 24, 0xffff3f, { { F (F_0_4) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_QI) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5715
};
5716
5717
static const CGEN_IFMT ifmt_movhh32_src_r0l_dst32_An_direct_Prefixed_QI ATTRIBUTE_UNUSED = {
5718
  24, 24, 0xffffbf, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5719
};
5720
5721
static const CGEN_IFMT ifmt_movhh32_src_r0l_dst32_An_indirect_Prefixed_QI ATTRIBUTE_UNUSED = {
5722
  24, 24, 0xffffbf, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5723
};
5724
5725
static const CGEN_IFMT ifmt_movhh32_src_r0l_dst32_24_8_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
5726
  32, 32, 0xffffbf00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5727
};
5728
5729
static const CGEN_IFMT ifmt_movhh32_src_r0l_dst32_24_16_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
5730
  32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5731
};
5732
5733
static const CGEN_IFMT ifmt_movhh32_src_r0l_dst32_24_24_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
5734
  32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5735
};
5736
5737
static const CGEN_IFMT ifmt_movhh32_src_r0l_dst32_24_8_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
5738
  32, 32, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U8) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5739
};
5740
5741
static const CGEN_IFMT ifmt_movhh32_src_r0l_dst32_24_16_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
5742
  32, 40, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5743
};
5744
5745
static const CGEN_IFMT ifmt_movhh32_src_r0l_dst32_24_8_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
5746
  32, 32, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S8) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5747
};
5748
5749
static const CGEN_IFMT ifmt_movhh32_src_r0l_dst32_24_16_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
5750
  32, 40, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5751
};
5752
5753
static const CGEN_IFMT ifmt_movhh32_src_r0l_dst32_24_16_absolute_Prefixed_QI ATTRIBUTE_UNUSED = {
5754
  32, 40, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5755
};
5756
5757
static const CGEN_IFMT ifmt_movhh32_src_r0l_dst32_24_24_absolute_Prefixed_QI ATTRIBUTE_UNUSED = {
5758
  32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U24) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
5759
};
5760
5761
static const CGEN_IFMT ifmt_mova32_src_a1_dst32_An_indirect_Unprefixed_Mova_SI ATTRIBUTE_UNUSED = {
5762
  16, 16, 0xffbf, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
5763
};
5764
5765
static const CGEN_IFMT ifmt_mova32_src_a1_dst32_16_8_An_relative_Unprefixed_Mova_SI ATTRIBUTE_UNUSED = {
5766
  24, 24, 0xffbf00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
5767
};
5768
5769
static const CGEN_IFMT ifmt_mova32_src_a1_dst32_16_16_An_relative_Unprefixed_Mova_SI ATTRIBUTE_UNUSED = {
5770
  32, 32, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
5771
};
5772
5773
static const CGEN_IFMT ifmt_mova32_src_a1_dst32_16_24_An_relative_Unprefixed_Mova_SI ATTRIBUTE_UNUSED = {
5774
  32, 40, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
5775
};
5776
5777
static const CGEN_IFMT ifmt_mova32_src_a1_dst32_16_8_SB_relative_Unprefixed_Mova_SI ATTRIBUTE_UNUSED = {
5778
  24, 24, 0xffff00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
5779
};
5780
5781
static const CGEN_IFMT ifmt_mova32_src_a1_dst32_16_16_SB_relative_Unprefixed_Mova_SI ATTRIBUTE_UNUSED = {
5782
  32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
5783
};
5784
5785
static const CGEN_IFMT ifmt_mova32_src_a1_dst32_16_8_FB_relative_Unprefixed_Mova_SI ATTRIBUTE_UNUSED = {
5786
  24, 24, 0xffff00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
5787
};
5788
5789
static const CGEN_IFMT ifmt_mova32_src_a1_dst32_16_16_FB_relative_Unprefixed_Mova_SI ATTRIBUTE_UNUSED = {
5790
  32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
5791
};
5792
5793
static const CGEN_IFMT ifmt_mova32_src_a1_dst32_16_16_absolute_Unprefixed_Mova_SI ATTRIBUTE_UNUSED = {
5794
  32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
5795
};
5796
5797
static const CGEN_IFMT ifmt_mova32_src_a1_dst32_16_24_absolute_Unprefixed_Mova_SI ATTRIBUTE_UNUSED = {
5798
  32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
5799
};
5800
5801
static const CGEN_IFMT ifmt_mov32_w_dst_dspsp_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
5802
  32, 32, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_24_S8) }, { 0 } }
5803
};
5804
5805
static const CGEN_IFMT ifmt_mov32_w_dst_dspsp_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
5806
  32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_24_S8) }, { 0 } }
5807
};
5808
5809
static const CGEN_IFMT ifmt_mov32_w_dst_dspsp_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
5810
  32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_24_S8) }, { 0 } }
5811
};
5812
5813
static const CGEN_IFMT ifmt_mov32_w_dst_dspsp_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
5814
  32, 40, 0xffbf0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
5815
};
5816
5817
static const CGEN_IFMT ifmt_mov32_w_dst_dspsp_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
5818
  32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
5819
};
5820
5821
static const CGEN_IFMT ifmt_mov32_w_dst_dspsp_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
5822
  32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
5823
};
5824
5825
static const CGEN_IFMT ifmt_mov32_w_dst_dspsp_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
5826
  32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
5827
};
5828
5829
static const CGEN_IFMT ifmt_mov32_w_dst_dspsp_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
5830
  32, 48, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_DSP_40_S8) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
5831
};
5832
5833
static const CGEN_IFMT ifmt_mov32_w_dst_dspsp_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
5834
  32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_DSP_40_S8) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
5835
};
5836
5837
static const CGEN_IFMT ifmt_mov32_w_dst_dspsp_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
5838
  24, 24, 0xff3f00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { 0 } }
5839
};
5840
5841
static const CGEN_IFMT ifmt_mov32_w_dst_dspsp_basic_Unprefixed_dst32_An_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
5842
  24, 24, 0xffbf00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { 0 } }
5843
};
5844
5845
static const CGEN_IFMT ifmt_mov32_w_dst_dspsp_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI ATTRIBUTE_UNUSED = {
5846
  24, 24, 0xffbf00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { 0 } }
5847
};
5848
5849
static const CGEN_IFMT ifmt_mov32_b_dst_dspsp_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
5850
  32, 32, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_24_S8) }, { 0 } }
5851
};
5852
5853
static const CGEN_IFMT ifmt_mov32_b_dst_dspsp_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
5854
  32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_24_S8) }, { 0 } }
5855
};
5856
5857
static const CGEN_IFMT ifmt_mov32_b_dst_dspsp_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
5858
  32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_24_S8) }, { 0 } }
5859
};
5860
5861
static const CGEN_IFMT ifmt_mov32_b_dst_dspsp_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
5862
  32, 40, 0xffbf0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
5863
};
5864
5865
static const CGEN_IFMT ifmt_mov32_b_dst_dspsp_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
5866
  32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
5867
};
5868
5869
static const CGEN_IFMT ifmt_mov32_b_dst_dspsp_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
5870
  32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
5871
};
5872
5873
static const CGEN_IFMT ifmt_mov32_b_dst_dspsp_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
5874
  32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
5875
};
5876
5877
static const CGEN_IFMT ifmt_mov32_b_dst_dspsp_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
5878
  32, 48, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_DSP_40_S8) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
5879
};
5880
5881
static const CGEN_IFMT ifmt_mov32_b_dst_dspsp_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
5882
  32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_DSP_40_S8) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
5883
};
5884
5885
static const CGEN_IFMT ifmt_mov32_b_dst_dspsp_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
5886
  24, 24, 0xff3f00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { 0 } }
5887
};
5888
5889
static const CGEN_IFMT ifmt_mov32_b_dst_dspsp_basic_Unprefixed_dst32_An_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
5890
  24, 24, 0xffbf00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { 0 } }
5891
};
5892
5893
static const CGEN_IFMT ifmt_mov32_b_dst_dspsp_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI ATTRIBUTE_UNUSED = {
5894
  24, 24, 0xffbf00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { 0 } }
5895
};
5896
5897
static const CGEN_IFMT ifmt_mov16_w_dst_dspsp_16_8_dst16_16_8_An_relative_HI ATTRIBUTE_UNUSED = {
5898
  32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_24_S8) }, { 0 } }
5899
};
5900
5901
static const CGEN_IFMT ifmt_mov16_w_dst_dspsp_16_8_dst16_16_8_SB_relative_HI ATTRIBUTE_UNUSED = {
5902
  32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_24_S8) }, { 0 } }
5903
};
5904
5905
static const CGEN_IFMT ifmt_mov16_w_dst_dspsp_16_8_dst16_16_8_FB_relative_HI ATTRIBUTE_UNUSED = {
5906
  32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_24_S8) }, { 0 } }
5907
};
5908
5909
static const CGEN_IFMT ifmt_mov16_w_dst_dspsp_16_16_dst16_16_16_An_relative_HI ATTRIBUTE_UNUSED = {
5910
  32, 40, 0xfffe0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
5911
};
5912
5913
static const CGEN_IFMT ifmt_mov16_w_dst_dspsp_16_16_dst16_16_16_SB_relative_HI ATTRIBUTE_UNUSED = {
5914
  32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
5915
};
5916
5917
static const CGEN_IFMT ifmt_mov16_w_dst_dspsp_16_16_dst16_16_16_absolute_HI ATTRIBUTE_UNUSED = {
5918
  32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
5919
};
5920
5921
static const CGEN_IFMT ifmt_mov16_w_dst_dspsp_basic_dst16_Rn_direct_HI ATTRIBUTE_UNUSED = {
5922
  24, 24, 0xfffc00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { 0 } }
5923
};
5924
5925
static const CGEN_IFMT ifmt_mov16_w_dst_dspsp_basic_dst16_An_direct_HI ATTRIBUTE_UNUSED = {
5926
  24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { 0 } }
5927
};
5928
5929
static const CGEN_IFMT ifmt_mov16_w_dst_dspsp_basic_dst16_An_indirect_HI ATTRIBUTE_UNUSED = {
5930
  24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { 0 } }
5931
};
5932
5933
static const CGEN_IFMT ifmt_mov16_b_dst_dspsp_16_8_dst16_16_8_An_relative_QI ATTRIBUTE_UNUSED = {
5934
  32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_24_S8) }, { 0 } }
5935
};
5936
5937
static const CGEN_IFMT ifmt_mov16_b_dst_dspsp_16_8_dst16_16_8_SB_relative_QI ATTRIBUTE_UNUSED = {
5938
  32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_24_S8) }, { 0 } }
5939
};
5940
5941
static const CGEN_IFMT ifmt_mov16_b_dst_dspsp_16_8_dst16_16_8_FB_relative_QI ATTRIBUTE_UNUSED = {
5942
  32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_24_S8) }, { 0 } }
5943
};
5944
5945
static const CGEN_IFMT ifmt_mov16_b_dst_dspsp_16_16_dst16_16_16_An_relative_QI ATTRIBUTE_UNUSED = {
5946
  32, 40, 0xfffe0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
5947
};
5948
5949
static const CGEN_IFMT ifmt_mov16_b_dst_dspsp_16_16_dst16_16_16_SB_relative_QI ATTRIBUTE_UNUSED = {
5950
  32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
5951
};
5952
5953
static const CGEN_IFMT ifmt_mov16_b_dst_dspsp_16_16_dst16_16_16_absolute_QI ATTRIBUTE_UNUSED = {
5954
  32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
5955
};
5956
5957
static const CGEN_IFMT ifmt_mov16_b_dst_dspsp_basic_dst16_Rn_direct_QI ATTRIBUTE_UNUSED = {
5958
  24, 24, 0xfffc00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { 0 } }
5959
};
5960
5961
static const CGEN_IFMT ifmt_mov16_b_dst_dspsp_basic_dst16_An_direct_QI ATTRIBUTE_UNUSED = {
5962
  24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { 0 } }
5963
};
5964
5965
static const CGEN_IFMT ifmt_mov16_b_dst_dspsp_basic_dst16_An_indirect_QI ATTRIBUTE_UNUSED = {
5966
  24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { 0 } }
5967
};
5968
5969
static const CGEN_IFMT ifmt_mov32_sz_dst32_2_S_8_a1_dst32_2_S_8_SB_relative_SI ATTRIBUTE_UNUSED = {
5970
  16, 16, 0xff00, { { F (F_0_2) }, { F (F_2_2) }, { F (F_DSP_8_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
5971
};
5972
5973
static const CGEN_IFMT ifmt_mov32_sz_dst32_2_S_8_a1_dst32_2_S_8_FB_relative_SI ATTRIBUTE_UNUSED = {
5974
  16, 16, 0xff00, { { F (F_0_2) }, { F (F_2_2) }, { F (F_DSP_8_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
5975
};
5976
5977
static const CGEN_IFMT ifmt_mov32_sz_dst32_2_S_16_a1_dst32_2_S_16_absolute_SI ATTRIBUTE_UNUSED = {
5978
  24, 24, 0xff0000, { { F (F_0_2) }, { F (F_2_2) }, { F (F_DSP_8_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
5979
};
5980
5981
static const CGEN_IFMT ifmt_mov32_w_r0_dst32_2_S_8_dst32_2_S_8_SB_relative_HI ATTRIBUTE_UNUSED = {
5982
  16, 16, 0xff00, { { F (F_0_2) }, { F (F_2_2) }, { F (F_DSP_8_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
5983
};
5984
5985
static const CGEN_IFMT ifmt_mov32_w_r0_dst32_2_S_8_dst32_2_S_8_FB_relative_HI ATTRIBUTE_UNUSED = {
5986
  16, 16, 0xff00, { { F (F_0_2) }, { F (F_2_2) }, { F (F_DSP_8_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
5987
};
5988
5989
static const CGEN_IFMT ifmt_mov32_b_r0l_dst32_2_S_8_dst32_2_S_8_SB_relative_QI ATTRIBUTE_UNUSED = {
5990
  16, 16, 0xff00, { { F (F_0_2) }, { F (F_2_2) }, { F (F_DSP_8_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
5991
};
5992
5993
static const CGEN_IFMT ifmt_mov32_b_r0l_dst32_2_S_8_dst32_2_S_8_FB_relative_QI ATTRIBUTE_UNUSED = {
5994
  16, 16, 0xff00, { { F (F_0_2) }, { F (F_2_2) }, { F (F_DSP_8_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
5995
};
5996
5997
static const CGEN_IFMT ifmt_mov32_w_r0_dst32_2_S_16_dst32_2_S_16_absolute_HI ATTRIBUTE_UNUSED = {
5998
  24, 24, 0xff0000, { { F (F_0_2) }, { F (F_2_2) }, { F (F_DSP_8_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
5999
};
6000
6001
static const CGEN_IFMT ifmt_mov32_b_r0l_dst32_2_S_16_dst32_2_S_16_absolute_QI ATTRIBUTE_UNUSED = {
6002
  24, 24, 0xff0000, { { F (F_0_2) }, { F (F_2_2) }, { F (F_DSP_8_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
6003
};
6004
6005
static const CGEN_IFMT ifmt_mov32_w_dst32_2_S_basic_r1_dst32_2_S_R0_direct_HI ATTRIBUTE_UNUSED = {
6006
  8, 8, 0xff, { { F (F_0_2) }, { F (F_2_2) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
6007
};
6008
6009
static const CGEN_IFMT ifmt_mov32_b_dst32_2_S_basic_r1l_dst32_2_S_R0l_direct_QI ATTRIBUTE_UNUSED = {
6010
  8, 8, 0xff, { { F (F_0_2) }, { F (F_2_2) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
6011
};
6012
6013
static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
6014
  24, 24, 0xff2f00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6015
};
6016
6017
static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
6018
  24, 24, 0xff3f00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6019
};
6020
6021
static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
6022
  24, 24, 0xff3f00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6023
};
6024
6025
static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
6026
  24, 24, 0xffaf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6027
};
6028
6029
static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
6030
  24, 24, 0xffbf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6031
};
6032
6033
static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
6034
  24, 24, 0xffbf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6035
};
6036
6037
static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = {
6038
  24, 24, 0xffaf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6039
};
6040
6041
static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = {
6042
  24, 24, 0xffbf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6043
};
6044
6045
static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = {
6046
  24, 24, 0xffbf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6047
};
6048
6049
static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6050
  32, 32, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6051
};
6052
6053
static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6054
  32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6055
};
6056
6057
static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6058
  32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6059
};
6060
6061
static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6062
  32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6063
};
6064
6065
static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6066
  32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6067
};
6068
6069
static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6070
  32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6071
};
6072
6073
static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6074
  32, 48, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6075
};
6076
6077
static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6078
  32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6079
};
6080
6081
static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6082
  32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6083
};
6084
6085
static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6086
  32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6087
};
6088
6089
static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6090
  32, 32, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6091
};
6092
6093
static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6094
  32, 32, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6095
};
6096
6097
static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6098
  32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6099
};
6100
6101
static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6102
  32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6103
};
6104
6105
static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6106
  32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6107
};
6108
6109
static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6110
  32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6111
};
6112
6113
static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6114
  32, 32, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6115
};
6116
6117
static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6118
  32, 32, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6119
};
6120
6121
static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6122
  32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6123
};
6124
6125
static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6126
  32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6127
};
6128
6129
static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6130
  32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6131
};
6132
6133
static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
6134
  32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6135
};
6136
6137
static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
6138
  32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6139
};
6140
6141
static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
6142
  32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6143
};
6144
6145
static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
6146
  32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6147
};
6148
6149
static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
6150
  32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6151
};
6152
6153
static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
6154
  32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6155
};
6156
6157
static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
6158
  32, 32, 0xff2f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6159
};
6160
6161
static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
6162
  32, 32, 0xff3f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6163
};
6164
6165
static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
6166
  32, 32, 0xff3f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6167
};
6168
6169
static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
6170
  32, 32, 0xff3f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6171
};
6172
6173
static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
6174
  32, 32, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6175
};
6176
6177
static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
6178
  32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6179
};
6180
6181
static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
6182
  32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6183
};
6184
6185
static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
6186
  32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6187
};
6188
6189
static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = {
6190
  32, 32, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6191
};
6192
6193
static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = {
6194
  32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6195
};
6196
6197
static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = {
6198
  32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6199
};
6200
6201
static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = {
6202
  32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6203
};
6204
6205
static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6206
  32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6207
};
6208
6209
static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6210
  32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6211
};
6212
6213
static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6214
  32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6215
};
6216
6217
static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6218
  32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6219
};
6220
6221
static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6222
  32, 48, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6223
};
6224
6225
static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6226
  32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6227
};
6228
6229
static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6230
  32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6231
};
6232
6233
static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6234
  32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6235
};
6236
6237
static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6238
  32, 56, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6239
};
6240
6241
static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6242
  32, 56, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6243
};
6244
6245
static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6246
  32, 56, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6247
};
6248
6249
static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6250
  32, 56, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6251
};
6252
6253
static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6254
  32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6255
};
6256
6257
static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6258
  32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6259
};
6260
6261
static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6262
  32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6263
};
6264
6265
static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6266
  32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6267
};
6268
6269
static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6270
  32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6271
};
6272
6273
static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6274
  32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6275
};
6276
6277
static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6278
  32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6279
};
6280
6281
static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6282
  32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6283
};
6284
6285
static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6286
  32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6287
};
6288
6289
static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6290
  32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6291
};
6292
6293
static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6294
  32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6295
};
6296
6297
static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6298
  32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6299
};
6300
6301
static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6302
  32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6303
};
6304
6305
static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6306
  32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6307
};
6308
6309
static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6310
  32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6311
};
6312
6313
static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6314
  32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6315
};
6316
6317
static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
6318
  32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6319
};
6320
6321
static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
6322
  32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6323
};
6324
6325
static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
6326
  32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6327
};
6328
6329
static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
6330
  32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6331
};
6332
6333
static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
6334
  32, 56, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6335
};
6336
6337
static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
6338
  32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6339
};
6340
6341
static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
6342
  32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6343
};
6344
6345
static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
6346
  32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6347
};
6348
6349
static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
6350
  32, 40, 0xff2f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6351
};
6352
6353
static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
6354
  32, 40, 0xff3f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6355
};
6356
6357
static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
6358
  32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6359
};
6360
6361
static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
6362
  32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6363
};
6364
6365
static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = {
6366
  32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6367
};
6368
6369
static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = {
6370
  32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6371
};
6372
6373
static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6374
  32, 48, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6375
};
6376
6377
static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6378
  32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6379
};
6380
6381
static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6382
  32, 56, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6383
};
6384
6385
static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6386
  32, 56, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6387
};
6388
6389
static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6390
  32, 64, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6391
};
6392
6393
static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6394
  32, 64, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6395
};
6396
6397
static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6398
  32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6399
};
6400
6401
static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6402
  32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6403
};
6404
6405
static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6406
  32, 56, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6407
};
6408
6409
static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6410
  32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6411
};
6412
6413
static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6414
  32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6415
};
6416
6417
static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6418
  32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6419
};
6420
6421
static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6422
  32, 56, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6423
};
6424
6425
static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6426
  32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6427
};
6428
6429
static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
6430
  32, 56, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6431
};
6432
6433
static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
6434
  32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6435
};
6436
6437
static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
6438
  32, 64, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6439
};
6440
6441
static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
6442
  32, 64, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6443
};
6444
6445
static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
6446
  16, 16, 0xff0f, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_SI) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6447
};
6448
6449
static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
6450
  16, 16, 0xff2f, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6451
};
6452
6453
static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
6454
  16, 16, 0xff2f, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6455
};
6456
6457
static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
6458
  16, 16, 0xff8f, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_SI) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6459
};
6460
6461
static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
6462
  16, 16, 0xffaf, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6463
};
6464
6465
static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
6466
  16, 16, 0xffaf, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6467
};
6468
6469
static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = {
6470
  16, 16, 0xff8f, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_SI) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6471
};
6472
6473
static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = {
6474
  16, 16, 0xffaf, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6475
};
6476
6477
static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = {
6478
  16, 16, 0xffaf, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6479
};
6480
6481
static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6482
  24, 24, 0xff8f00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_SI) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6483
};
6484
6485
static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6486
  24, 24, 0xffaf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6487
};
6488
6489
static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6490
  24, 24, 0xffaf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6491
};
6492
6493
static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6494
  32, 32, 0xff8f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_SI) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6495
};
6496
6497
static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6498
  32, 32, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6499
};
6500
6501
static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6502
  32, 32, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6503
};
6504
6505
static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6506
  32, 40, 0xff8f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_SI) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6507
};
6508
6509
static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6510
  32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6511
};
6512
6513
static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6514
  32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6515
};
6516
6517
static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6518
  24, 24, 0xffcf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_SI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6519
};
6520
6521
static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6522
  24, 24, 0xffef00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6523
};
6524
6525
static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6526
  24, 24, 0xffef00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6527
};
6528
6529
static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6530
  32, 32, 0xffcf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_SI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6531
};
6532
6533
static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6534
  32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6535
};
6536
6537
static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6538
  32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6539
};
6540
6541
static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6542
  24, 24, 0xffcf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_SI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6543
};
6544
6545
static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6546
  24, 24, 0xffef00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6547
};
6548
6549
static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6550
  24, 24, 0xffef00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6551
};
6552
6553
static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6554
  32, 32, 0xffcf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_SI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6555
};
6556
6557
static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6558
  32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6559
};
6560
6561
static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6562
  32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6563
};
6564
6565
static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
6566
  32, 32, 0xffcf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_SI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6567
};
6568
6569
static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
6570
  32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6571
};
6572
6573
static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
6574
  32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6575
};
6576
6577
static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
6578
  32, 40, 0xffcf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_SI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6579
};
6580
6581
static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
6582
  32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6583
};
6584
6585
static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
6586
  32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } }
6587
};
6588
6589
static const CGEN_IFMT ifmt_mov16_b_S_An_src16_2_S_8_SB_relative_QI ATTRIBUTE_UNUSED = {
6590
  16, 16, 0xfb00, { { F (F_0_4) }, { F (F_6_2) }, { F (F_DSP_8_U8) }, { F (F_4_1) }, { F (F_DST16_RN_QI_S) }, { 0 } }
6591
};
6592
6593
static const CGEN_IFMT ifmt_mov16_b_S_An_src16_2_S_8_FB_relative_QI ATTRIBUTE_UNUSED = {
6594
  16, 16, 0xfb00, { { F (F_0_4) }, { F (F_6_2) }, { F (F_DSP_8_S8) }, { F (F_4_1) }, { F (F_DST16_RN_QI_S) }, { 0 } }
6595
};
6596
6597
static const CGEN_IFMT ifmt_mov16_b_S_An_src16_2_S_16_absolute_QI ATTRIBUTE_UNUSED = {
6598
  24, 24, 0xfb0000, { { F (F_0_4) }, { F (F_6_2) }, { F (F_DSP_8_U16) }, { F (F_4_1) }, { F (F_DST16_RN_QI_S) }, { 0 } }
6599
};
6600
6601
static const CGEN_IFMT ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
6602
  16, 16, 0xff30, { { F (F_0_3) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
6603
};
6604
6605
static const CGEN_IFMT ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_An_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
6606
  16, 16, 0xffb0, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
6607
};
6608
6609
static const CGEN_IFMT ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_An_indirect_Unprefixed_HI ATTRIBUTE_UNUSED = {
6610
  16, 16, 0xffb0, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
6611
};
6612
6613
static const CGEN_IFMT ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
6614
  24, 24, 0xffb000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
6615
};
6616
6617
static const CGEN_IFMT ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
6618
  32, 32, 0xffb00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
6619
};
6620
6621
static const CGEN_IFMT ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
6622
  32, 40, 0xffb00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
6623
};
6624
6625
static const CGEN_IFMT ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
6626
  24, 24, 0xfff000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
6627
};
6628
6629
static const CGEN_IFMT ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
6630
  32, 32, 0xfff00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
6631
};
6632
6633
static const CGEN_IFMT ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
6634
  24, 24, 0xfff000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
6635
};
6636
6637
static const CGEN_IFMT ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
6638
  32, 32, 0xfff00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
6639
};
6640
6641
static const CGEN_IFMT ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
6642
  32, 32, 0xfff00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
6643
};
6644
6645
static const CGEN_IFMT ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_24_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
6646
  32, 40, 0xfff00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
6647
};
6648
6649
static const CGEN_IFMT ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_Rn_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
6650
  16, 16, 0xff30, { { F (F_0_3) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
6651
};
6652
6653
static const CGEN_IFMT ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_An_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
6654
  16, 16, 0xffb0, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
6655
};
6656
6657
static const CGEN_IFMT ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_An_indirect_Unprefixed_QI ATTRIBUTE_UNUSED = {
6658
  16, 16, 0xffb0, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
6659
};
6660
6661
static const CGEN_IFMT ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
6662
  24, 24, 0xffb000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
6663
};
6664
6665
static const CGEN_IFMT ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
6666
  32, 32, 0xffb00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
6667
};
6668
6669
static const CGEN_IFMT ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
6670
  32, 40, 0xffb00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
6671
};
6672
6673
static const CGEN_IFMT ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
6674
  24, 24, 0xfff000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
6675
};
6676
6677
static const CGEN_IFMT ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
6678
  32, 32, 0xfff00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
6679
};
6680
6681
static const CGEN_IFMT ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
6682
  24, 24, 0xfff000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
6683
};
6684
6685
static const CGEN_IFMT ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
6686
  32, 32, 0xfff00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
6687
};
6688
6689
static const CGEN_IFMT ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
6690
  32, 32, 0xfff00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
6691
};
6692
6693
static const CGEN_IFMT ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_24_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
6694
  32, 40, 0xfff00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
6695
};
6696
6697
static const CGEN_IFMT ifmt_mov16_w_imm4_Q_16_dst16_Rn_direct_HI ATTRIBUTE_UNUSED = {
6698
  16, 16, 0xff0c, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
6699
};
6700
6701
static const CGEN_IFMT ifmt_mov16_w_imm4_Q_16_dst16_An_direct_HI ATTRIBUTE_UNUSED = {
6702
  16, 16, 0xff0e, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
6703
};
6704
6705
static const CGEN_IFMT ifmt_mov16_w_imm4_Q_16_dst16_An_indirect_HI ATTRIBUTE_UNUSED = {
6706
  16, 16, 0xff0e, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
6707
};
6708
6709
static const CGEN_IFMT ifmt_mov16_w_imm4_Q_16_dst16_16_8_An_relative_HI ATTRIBUTE_UNUSED = {
6710
  24, 24, 0xff0e00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
6711
};
6712
6713
static const CGEN_IFMT ifmt_mov16_w_imm4_Q_16_dst16_16_16_An_relative_HI ATTRIBUTE_UNUSED = {
6714
  32, 32, 0xff0e0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
6715
};
6716
6717
static const CGEN_IFMT ifmt_mov16_w_imm4_Q_16_dst16_16_8_SB_relative_HI ATTRIBUTE_UNUSED = {
6718
  24, 24, 0xff0f00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
6719
};
6720
6721
static const CGEN_IFMT ifmt_mov16_w_imm4_Q_16_dst16_16_16_SB_relative_HI ATTRIBUTE_UNUSED = {
6722
  32, 32, 0xff0f0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
6723
};
6724
6725
static const CGEN_IFMT ifmt_mov16_w_imm4_Q_16_dst16_16_8_FB_relative_HI ATTRIBUTE_UNUSED = {
6726
  24, 24, 0xff0f00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
6727
};
6728
6729
static const CGEN_IFMT ifmt_mov16_w_imm4_Q_16_dst16_16_16_absolute_HI ATTRIBUTE_UNUSED = {
6730
  32, 32, 0xff0f0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
6731
};
6732
6733
static const CGEN_IFMT ifmt_mov16_b_imm4_Q_16_dst16_Rn_direct_QI ATTRIBUTE_UNUSED = {
6734
  16, 16, 0xff0c, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
6735
};
6736
6737
static const CGEN_IFMT ifmt_mov16_b_imm4_Q_16_dst16_An_direct_QI ATTRIBUTE_UNUSED = {
6738
  16, 16, 0xff0e, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
6739
};
6740
6741
static const CGEN_IFMT ifmt_mov16_b_imm4_Q_16_dst16_An_indirect_QI ATTRIBUTE_UNUSED = {
6742
  16, 16, 0xff0e, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
6743
};
6744
6745
static const CGEN_IFMT ifmt_mov16_b_imm4_Q_16_dst16_16_8_An_relative_QI ATTRIBUTE_UNUSED = {
6746
  24, 24, 0xff0e00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
6747
};
6748
6749
static const CGEN_IFMT ifmt_mov16_b_imm4_Q_16_dst16_16_16_An_relative_QI ATTRIBUTE_UNUSED = {
6750
  32, 32, 0xff0e0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
6751
};
6752
6753
static const CGEN_IFMT ifmt_mov16_b_imm4_Q_16_dst16_16_8_SB_relative_QI ATTRIBUTE_UNUSED = {
6754
  24, 24, 0xff0f00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
6755
};
6756
6757
static const CGEN_IFMT ifmt_mov16_b_imm4_Q_16_dst16_16_16_SB_relative_QI ATTRIBUTE_UNUSED = {
6758
  32, 32, 0xff0f0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
6759
};
6760
6761
static const CGEN_IFMT ifmt_mov16_b_imm4_Q_16_dst16_16_8_FB_relative_QI ATTRIBUTE_UNUSED = {
6762
  24, 24, 0xff0f00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
6763
};
6764
6765
static const CGEN_IFMT ifmt_mov16_b_imm4_Q_16_dst16_16_16_absolute_QI ATTRIBUTE_UNUSED = {
6766
  32, 32, 0xff0f0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
6767
};
6768
6769
static const CGEN_IFMT ifmt_mov32_l_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
6770
  32, 48, 0xff3f0000, { { F (F_0_4) }, { F (F_DSP_16_S32) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
6771
};
6772
6773
static const CGEN_IFMT ifmt_mov32_l_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
6774
  32, 48, 0xffbf0000, { { F (F_0_4) }, { F (F_DSP_16_S32) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
6775
};
6776
6777
static const CGEN_IFMT ifmt_mov32_l_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = {
6778
  32, 48, 0xffbf0000, { { F (F_0_4) }, { F (F_DSP_16_S32) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
6779
};
6780
6781
static const CGEN_IFMT ifmt_mov32_l_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6782
  32, 56, 0xffbf0000, { { F (F_0_4) }, { F (F_DSP_24_S32) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
6783
};
6784
6785
static const CGEN_IFMT ifmt_mov32_l_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6786
  32, 56, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_24_S32) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
6787
};
6788
6789
static const CGEN_IFMT ifmt_mov32_l_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6790
  32, 56, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_24_S32) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
6791
};
6792
6793
static const CGEN_IFMT ifmt_mov32_l_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6794
  32, 64, 0xffbf0000, { { F (F_0_4) }, { F (F_DSP_32_S32) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
6795
};
6796
6797
static const CGEN_IFMT ifmt_mov32_l_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6798
  32, 64, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S32) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
6799
};
6800
6801
static const CGEN_IFMT ifmt_mov32_l_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6802
  32, 64, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S32) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
6803
};
6804
6805
static const CGEN_IFMT ifmt_mov32_l_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
6806
  32, 64, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S32) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
6807
};
6808
6809
static const CGEN_IFMT ifmt_mov32_l_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6810
  32, 72, 0xffbf0000, { { F (F_0_4) }, { F (F_DSP_40_S32) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
6811
};
6812
6813
static const CGEN_IFMT ifmt_mov32_l_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
6814
  32, 72, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_40_S32) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } }
6815
};
6816
6817
static const CGEN_IFMT ifmt_ste_w_16_16_u20a0_dst16_16_16_An_relative_HI ATTRIBUTE_UNUSED = {
6818
  32, 56, 0xfffe0000, { { F (F_0_4) }, { F (F_DSP_32_U24) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
6819
};
6820
6821
static const CGEN_IFMT ifmt_ste_w_16_16_u20a0_dst16_16_16_SB_relative_HI ATTRIBUTE_UNUSED = {
6822
  32, 56, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_U24) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
6823
};
6824
6825
static const CGEN_IFMT ifmt_ste_w_16_16_u20a0_dst16_16_16_absolute_HI ATTRIBUTE_UNUSED = {
6826
  32, 56, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_U24) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
6827
};
6828
6829
static const CGEN_IFMT ifmt_ste_w_16_8_u20a0_dst16_16_8_An_relative_HI ATTRIBUTE_UNUSED = {
6830
  32, 48, 0xfffe0000, { { F (F_0_4) }, { F (F_DSP_24_U24) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
6831
};
6832
6833
static const CGEN_IFMT ifmt_ste_w_16_8_u20a0_dst16_16_8_SB_relative_HI ATTRIBUTE_UNUSED = {
6834
  32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_24_U24) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
6835
};
6836
6837
static const CGEN_IFMT ifmt_ste_w_16_8_u20a0_dst16_16_8_FB_relative_HI ATTRIBUTE_UNUSED = {
6838
  32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_24_U24) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
6839
};
6840
6841
static const CGEN_IFMT ifmt_ste_w_basic_u20a0_dst16_Rn_direct_HI ATTRIBUTE_UNUSED = {
6842
  32, 40, 0xfffc0000, { { F (F_0_4) }, { F (F_DSP_16_U24) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
6843
};
6844
6845
static const CGEN_IFMT ifmt_ste_w_basic_u20a0_dst16_An_direct_HI ATTRIBUTE_UNUSED = {
6846
  32, 40, 0xfffe0000, { { F (F_0_4) }, { F (F_DSP_16_U24) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
6847
};
6848
6849
static const CGEN_IFMT ifmt_ste_w_basic_u20a0_dst16_An_indirect_HI ATTRIBUTE_UNUSED = {
6850
  32, 40, 0xfffe0000, { { F (F_0_4) }, { F (F_DSP_16_U24) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
6851
};
6852
6853
static const CGEN_IFMT ifmt_ste_b_16_16_u20a0_dst16_16_16_An_relative_QI ATTRIBUTE_UNUSED = {
6854
  32, 56, 0xfffe0000, { { F (F_0_4) }, { F (F_DSP_32_U24) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
6855
};
6856
6857
static const CGEN_IFMT ifmt_ste_b_16_16_u20a0_dst16_16_16_SB_relative_QI ATTRIBUTE_UNUSED = {
6858
  32, 56, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_U24) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
6859
};
6860
6861
static const CGEN_IFMT ifmt_ste_b_16_16_u20a0_dst16_16_16_absolute_QI ATTRIBUTE_UNUSED = {
6862
  32, 56, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_U24) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
6863
};
6864
6865
static const CGEN_IFMT ifmt_ste_b_16_8_u20a0_dst16_16_8_An_relative_QI ATTRIBUTE_UNUSED = {
6866
  32, 48, 0xfffe0000, { { F (F_0_4) }, { F (F_DSP_24_U24) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
6867
};
6868
6869
static const CGEN_IFMT ifmt_ste_b_16_8_u20a0_dst16_16_8_SB_relative_QI ATTRIBUTE_UNUSED = {
6870
  32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_24_U24) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
6871
};
6872
6873
static const CGEN_IFMT ifmt_ste_b_16_8_u20a0_dst16_16_8_FB_relative_QI ATTRIBUTE_UNUSED = {
6874
  32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_24_U24) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
6875
};
6876
6877
static const CGEN_IFMT ifmt_ste_b_basic_u20a0_dst16_Rn_direct_QI ATTRIBUTE_UNUSED = {
6878
  32, 40, 0xfffc0000, { { F (F_0_4) }, { F (F_DSP_16_U24) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
6879
};
6880
6881
static const CGEN_IFMT ifmt_ste_b_basic_u20a0_dst16_An_direct_QI ATTRIBUTE_UNUSED = {
6882
  32, 40, 0xfffe0000, { { F (F_0_4) }, { F (F_DSP_16_U24) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
6883
};
6884
6885
static const CGEN_IFMT ifmt_ste_b_basic_u20a0_dst16_An_indirect_QI ATTRIBUTE_UNUSED = {
6886
  32, 40, 0xfffe0000, { { F (F_0_4) }, { F (F_DSP_16_U24) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } }
6887
};
6888
6889
static const CGEN_IFMT ifmt_stc32_src_cr3_dst32_Rn_direct_Prefixed_SI ATTRIBUTE_UNUSED = {
6890
  24, 24, 0xffff38, { { F (F_0_4) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_SI) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } }
6891
};
6892
6893
static const CGEN_IFMT ifmt_stc32_src_cr3_dst32_An_direct_Prefixed_SI ATTRIBUTE_UNUSED = {
6894
  24, 24, 0xffffb8, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } }
6895
};
6896
6897
static const CGEN_IFMT ifmt_stc32_src_cr3_dst32_An_indirect_Prefixed_SI ATTRIBUTE_UNUSED = {
6898
  24, 24, 0xffffb8, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } }
6899
};
6900
6901
static const CGEN_IFMT ifmt_stc32_src_cr3_dst32_24_8_An_relative_Prefixed_SI ATTRIBUTE_UNUSED = {
6902
  32, 32, 0xffffb800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } }
6903
};
6904
6905
static const CGEN_IFMT ifmt_stc32_src_cr3_dst32_24_16_An_relative_Prefixed_SI ATTRIBUTE_UNUSED = {
6906
  32, 40, 0xffffb800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } }
6907
};
6908
6909
static const CGEN_IFMT ifmt_stc32_src_cr3_dst32_24_24_An_relative_Prefixed_SI ATTRIBUTE_UNUSED = {
6910
  32, 48, 0xffffb800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } }
6911
};
6912
6913
static const CGEN_IFMT ifmt_stc32_src_cr3_dst32_24_8_SB_relative_Prefixed_SI ATTRIBUTE_UNUSED = {
6914
  32, 32, 0xfffff800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U8) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } }
6915
};
6916
6917
static const CGEN_IFMT ifmt_stc32_src_cr3_dst32_24_16_SB_relative_Prefixed_SI ATTRIBUTE_UNUSED = {
6918
  32, 40, 0xfffff800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } }
6919
};
6920
6921
static const CGEN_IFMT ifmt_stc32_src_cr3_dst32_24_8_FB_relative_Prefixed_SI ATTRIBUTE_UNUSED = {
6922
  32, 32, 0xfffff800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S8) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } }
6923
};
6924
6925
static const CGEN_IFMT ifmt_stc32_src_cr3_dst32_24_16_FB_relative_Prefixed_SI ATTRIBUTE_UNUSED = {
6926
  32, 40, 0xfffff800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } }
6927
};
6928
6929
static const CGEN_IFMT ifmt_stc32_src_cr3_dst32_24_16_absolute_Prefixed_SI ATTRIBUTE_UNUSED = {
6930
  32, 40, 0xfffff800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } }
6931
};
6932
6933
static const CGEN_IFMT ifmt_stc32_src_cr3_dst32_24_24_absolute_Prefixed_SI ATTRIBUTE_UNUSED = {
6934
  32, 48, 0xfffff800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U24) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } }
6935
};
6936
6937
static const CGEN_IFMT ifmt_stc32_src_cr2_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
6938
  16, 16, 0xff38, { { F (F_0_4) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
6939
};
6940
6941
static const CGEN_IFMT ifmt_stc32_src_cr2_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
6942
  16, 16, 0xffb8, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
6943
};
6944
6945
static const CGEN_IFMT ifmt_stc32_src_cr2_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = {
6946
  16, 16, 0xffb8, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
6947
};
6948
6949
static const CGEN_IFMT ifmt_stc32_src_cr2_dst32_16_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6950
  24, 24, 0xffb800, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
6951
};
6952
6953
static const CGEN_IFMT ifmt_stc32_src_cr2_dst32_16_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6954
  32, 32, 0xffb80000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
6955
};
6956
6957
static const CGEN_IFMT ifmt_stc32_src_cr2_dst32_16_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6958
  32, 40, 0xffb80000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
6959
};
6960
6961
static const CGEN_IFMT ifmt_stc32_src_cr2_dst32_16_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6962
  24, 24, 0xfff800, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
6963
};
6964
6965
static const CGEN_IFMT ifmt_stc32_src_cr2_dst32_16_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6966
  32, 32, 0xfff80000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
6967
};
6968
6969
static const CGEN_IFMT ifmt_stc32_src_cr2_dst32_16_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6970
  24, 24, 0xfff800, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
6971
};
6972
6973
static const CGEN_IFMT ifmt_stc32_src_cr2_dst32_16_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
6974
  32, 32, 0xfff80000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
6975
};
6976
6977
static const CGEN_IFMT ifmt_stc32_src_cr2_dst32_16_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
6978
  32, 32, 0xfff80000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
6979
};
6980
6981
static const CGEN_IFMT ifmt_stc32_src_cr2_dst32_16_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
6982
  32, 40, 0xfff80000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
6983
};
6984
6985
static const CGEN_IFMT ifmt_stc32_src_cr1_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
6986
  24, 24, 0xffff38, { { F (F_0_4) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } }
6987
};
6988
6989
static const CGEN_IFMT ifmt_stc32_src_cr1_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
6990
  24, 24, 0xffffb8, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } }
6991
};
6992
6993
static const CGEN_IFMT ifmt_stc32_src_cr1_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = {
6994
  24, 24, 0xffffb8, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } }
6995
};
6996
6997
static const CGEN_IFMT ifmt_stc32_src_cr1_dst32_24_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
6998
  32, 32, 0xffffb800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } }
6999
};
7000
7001
static const CGEN_IFMT ifmt_stc32_src_cr1_dst32_24_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
7002
  32, 40, 0xffffb800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } }
7003
};
7004
7005
static const CGEN_IFMT ifmt_stc32_src_cr1_dst32_24_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
7006
  32, 48, 0xffffb800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } }
7007
};
7008
7009
static const CGEN_IFMT ifmt_stc32_src_cr1_dst32_24_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
7010
  32, 32, 0xfffff800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U8) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } }
7011
};
7012
7013
static const CGEN_IFMT ifmt_stc32_src_cr1_dst32_24_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
7014
  32, 40, 0xfffff800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } }
7015
};
7016
7017
static const CGEN_IFMT ifmt_stc32_src_cr1_dst32_24_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
7018
  32, 32, 0xfffff800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S8) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } }
7019
};
7020
7021
static const CGEN_IFMT ifmt_stc32_src_cr1_dst32_24_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
7022
  32, 40, 0xfffff800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } }
7023
};
7024
7025
static const CGEN_IFMT ifmt_stc32_src_cr1_dst32_24_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
7026
  32, 40, 0xfffff800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } }
7027
};
7028
7029
static const CGEN_IFMT ifmt_stc32_src_cr1_dst32_24_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
7030
  32, 48, 0xfffff800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U24) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } }
7031
};
7032
7033
static const CGEN_IFMT ifmt_stc16_src_dst16_Rn_direct_HI ATTRIBUTE_UNUSED = {
7034
  16, 16, 0xff8c, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_9_3) }, { 0 } }
7035
};
7036
7037
static const CGEN_IFMT ifmt_stc16_src_dst16_An_direct_HI ATTRIBUTE_UNUSED = {
7038
  16, 16, 0xff8e, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_9_3) }, { 0 } }
7039
};
7040
7041
static const CGEN_IFMT ifmt_stc16_src_dst16_An_indirect_HI ATTRIBUTE_UNUSED = {
7042
  16, 16, 0xff8e, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_9_3) }, { 0 } }
7043
};
7044
7045
static const CGEN_IFMT ifmt_stc16_src_dst16_16_8_An_relative_HI ATTRIBUTE_UNUSED = {
7046
  24, 24, 0xff8e00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_9_3) }, { 0 } }
7047
};
7048
7049
static const CGEN_IFMT ifmt_stc16_src_dst16_16_16_An_relative_HI ATTRIBUTE_UNUSED = {
7050
  32, 32, 0xff8e0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_9_3) }, { 0 } }
7051
};
7052
7053
static const CGEN_IFMT ifmt_stc16_src_dst16_16_8_SB_relative_HI ATTRIBUTE_UNUSED = {
7054
  24, 24, 0xff8f00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_9_3) }, { 0 } }
7055
};
7056
7057
static const CGEN_IFMT ifmt_stc16_src_dst16_16_16_SB_relative_HI ATTRIBUTE_UNUSED = {
7058
  32, 32, 0xff8f0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_9_3) }, { 0 } }
7059
};
7060
7061
static const CGEN_IFMT ifmt_stc16_src_dst16_16_8_FB_relative_HI ATTRIBUTE_UNUSED = {
7062
  24, 24, 0xff8f00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_9_3) }, { 0 } }
7063
};
7064
7065
static const CGEN_IFMT ifmt_stc16_src_dst16_16_16_absolute_HI ATTRIBUTE_UNUSED = {
7066
  32, 32, 0xff8f0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_9_3) }, { 0 } }
7067
};
7068
7069
static const CGEN_IFMT ifmt_jsri16a_dst16_basic_SI_dst16_Rn_direct_SI ATTRIBUTE_UNUSED = {
7070
  16, 16, 0xfffc, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
7071
};
7072
7073
static const CGEN_IFMT ifmt_jsri16a_dst16_basic_SI_dst16_An_direct_SI ATTRIBUTE_UNUSED = {
7074
  16, 16, 0xfffe, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
7075
};
7076
7077
static const CGEN_IFMT ifmt_jsri16a_dst16_basic_SI_dst16_An_indirect_SI ATTRIBUTE_UNUSED = {
7078
  16, 16, 0xfffe, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
7079
};
7080
7081
static const CGEN_IFMT ifmt_jsri16a_dst16_16_16sa_SI_dst16_16_16_SB_relative_SI ATTRIBUTE_UNUSED = {
7082
  32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
7083
};
7084
7085
static const CGEN_IFMT ifmt_jsri16a_dst16_16_16sa_SI_dst16_16_16_absolute_SI ATTRIBUTE_UNUSED = {
7086
  32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
7087
};
7088
7089
static const CGEN_IFMT ifmt_jsri16a_dst16_16_8_SI_dst16_16_8_An_relative_SI ATTRIBUTE_UNUSED = {
7090
  24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
7091
};
7092
7093
static const CGEN_IFMT ifmt_jsri16a_dst16_16_8_SI_dst16_16_8_SB_relative_SI ATTRIBUTE_UNUSED = {
7094
  24, 24, 0xffff00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
7095
};
7096
7097
static const CGEN_IFMT ifmt_jsri16a_dst16_16_8_SI_dst16_16_8_FB_relative_SI ATTRIBUTE_UNUSED = {
7098
  24, 24, 0xffff00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
7099
};
7100
7101
static const CGEN_IFMT ifmt_jsri16a_dst16_16_20ar_SI_dst16_16_20_An_relative_SI ATTRIBUTE_UNUSED = {
7102
  32, 40, 0xfffe0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U24) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
7103
};
7104
7105
static const CGEN_IFMT ifmt_jsri16w_dst16_16_20ar_HI_dst16_16_20_An_relative_HI ATTRIBUTE_UNUSED = {
7106
  32, 40, 0xfffe0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U24) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
7107
};
7108
7109
static const CGEN_IFMT ifmt_jmpi16_a_16_dst16_16_16_An_relative_SI ATTRIBUTE_UNUSED = {
7110
  32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
7111
};
7112
7113
static const CGEN_IFMT ifmt_cmp32_w_S_src2_r0_HI_src32_2_S_8_SB_relative_HI ATTRIBUTE_UNUSED = {
7114
  16, 16, 0xff00, { { F (F_0_2) }, { F (F_2_2) }, { F (F_DSP_8_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
7115
};
7116
7117
static const CGEN_IFMT ifmt_cmp32_w_S_src2_r0_HI_src32_2_S_8_FB_relative_HI ATTRIBUTE_UNUSED = {
7118
  16, 16, 0xff00, { { F (F_0_2) }, { F (F_2_2) }, { F (F_DSP_8_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
7119
};
7120
7121
static const CGEN_IFMT ifmt_cmp32_w_S_src2_r0_HI_src32_2_S_16_absolute_HI ATTRIBUTE_UNUSED = {
7122
  24, 24, 0xff0000, { { F (F_0_2) }, { F (F_2_2) }, { F (F_DSP_8_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
7123
};
7124
7125
static const CGEN_IFMT ifmt_cmp32_b_S_src2_r0_QI_src32_2_S_8_SB_relative_QI ATTRIBUTE_UNUSED = {
7126
  16, 16, 0xff00, { { F (F_0_2) }, { F (F_2_2) }, { F (F_DSP_8_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
7127
};
7128
7129
static const CGEN_IFMT ifmt_cmp32_b_S_src2_r0_QI_src32_2_S_8_FB_relative_QI ATTRIBUTE_UNUSED = {
7130
  16, 16, 0xff00, { { F (F_0_2) }, { F (F_2_2) }, { F (F_DSP_8_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
7131
};
7132
7133
static const CGEN_IFMT ifmt_cmp32_b_S_src2_r0_QI_src32_2_S_16_absolute_QI ATTRIBUTE_UNUSED = {
7134
  24, 24, 0xff0000, { { F (F_0_2) }, { F (F_2_2) }, { F (F_DSP_8_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } }
7135
};
7136
7137
static const CGEN_IFMT ifmt_clip32_w_Imm_24_HI_Imm_40_HI_basic_Prefixed_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
7138
  32, 56, 0xffff3f00, { { F (F_0_4) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_40_S16) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
7139
};
7140
7141
static const CGEN_IFMT ifmt_clip32_w_Imm_24_HI_Imm_40_HI_basic_Prefixed_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = {
7142
  32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_40_S16) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
7143
};
7144
7145
static const CGEN_IFMT ifmt_clip32_w_Imm_24_HI_Imm_40_HI_basic_Prefixed_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = {
7146
  32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_40_S16) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
7147
};
7148
7149
static const CGEN_IFMT ifmt_clip32_w_Imm_32_HI_Imm_48_HI_24_8_Prefixed_dst32_24_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
7150
  32, 64, 0xffffbf00, { { F (F_0_4) }, { F (F_DSP_32_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_DSP_48_S16) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
7151
};
7152
7153
static const CGEN_IFMT ifmt_clip32_w_Imm_32_HI_Imm_48_HI_24_8_Prefixed_dst32_24_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
7154
  32, 64, 0xffffff00, { { F (F_0_4) }, { F (F_DSP_32_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U8) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_DSP_48_S16) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
7155
};
7156
7157
static const CGEN_IFMT ifmt_clip32_w_Imm_32_HI_Imm_48_HI_24_8_Prefixed_dst32_24_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
7158
  32, 64, 0xffffff00, { { F (F_0_4) }, { F (F_DSP_32_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S8) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_DSP_48_S16) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
7159
};
7160
7161
static const CGEN_IFMT ifmt_clip32_w_Imm_40_HI_Imm_56_HI_24_16_Prefixed_dst32_24_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
7162
  32, 72, 0xffffbf00, { { F (F_0_4) }, { F (F_DSP_56_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_40_S16) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
7163
};
7164
7165
static const CGEN_IFMT ifmt_clip32_w_Imm_40_HI_Imm_56_HI_24_16_Prefixed_dst32_24_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
7166
  32, 72, 0xffffff00, { { F (F_0_4) }, { F (F_DSP_56_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_40_S16) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
7167
};
7168
7169
static const CGEN_IFMT ifmt_clip32_w_Imm_40_HI_Imm_56_HI_24_16_Prefixed_dst32_24_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
7170
  32, 72, 0xffffff00, { { F (F_0_4) }, { F (F_DSP_56_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_40_S16) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
7171
};
7172
7173
static const CGEN_IFMT ifmt_clip32_w_Imm_40_HI_Imm_56_HI_24_16_Prefixed_dst32_24_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
7174
  32, 72, 0xffffff00, { { F (F_0_4) }, { F (F_DSP_56_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_40_S16) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
7175
};
7176
7177
static const CGEN_IFMT ifmt_clip32_w_Imm_48_HI_Imm_64_HI_24_24_Prefixed_dst32_24_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = {
7178
  32, 80, 0xffffbf00, { { F (F_0_4) }, { F (F_DSP_64_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_DSP_48_S16) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
7179
};
7180
7181
static const CGEN_IFMT ifmt_clip32_w_Imm_48_HI_Imm_64_HI_24_24_Prefixed_dst32_24_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = {
7182
  32, 80, 0xffffff00, { { F (F_0_4) }, { F (F_DSP_64_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U24) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_DSP_48_S16) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
7183
};
7184
7185
static const CGEN_IFMT ifmt_clip32_b_Imm_24_QI_Imm_32_QI_basic_Prefixed_dst32_Rn_direct_Prefixed_QI ATTRIBUTE_UNUSED = {
7186
  32, 40, 0xffff3f00, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_QI) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { F (F_DSP_24_S8) }, { 0 } }
7187
};
7188
7189
static const CGEN_IFMT ifmt_clip32_b_Imm_24_QI_Imm_32_QI_basic_Prefixed_dst32_An_direct_Prefixed_QI ATTRIBUTE_UNUSED = {
7190
  32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { F (F_DSP_24_S8) }, { 0 } }
7191
};
7192
7193
static const CGEN_IFMT ifmt_clip32_b_Imm_24_QI_Imm_32_QI_basic_Prefixed_dst32_An_indirect_Prefixed_QI ATTRIBUTE_UNUSED = {
7194
  32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { F (F_DSP_24_S8) }, { 0 } }
7195
};
7196
7197
static const CGEN_IFMT ifmt_clip32_b_Imm_32_QI_Imm_40_QI_24_8_Prefixed_dst32_24_8_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
7198
  32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_40_S8) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
7199
};
7200
7201
static const CGEN_IFMT ifmt_clip32_b_Imm_32_QI_Imm_40_QI_24_8_Prefixed_dst32_24_8_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
7202
  32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U8) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_40_S8) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
7203
};
7204
7205
static const CGEN_IFMT ifmt_clip32_b_Imm_32_QI_Imm_40_QI_24_8_Prefixed_dst32_24_8_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
7206
  32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S8) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_40_S8) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
7207
};
7208
7209
static const CGEN_IFMT ifmt_clip32_b_Imm_40_QI_Imm_48_QI_24_16_Prefixed_dst32_24_16_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
7210
  32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_40_S8) }, { F (F_15_1) }, { F (F_DSP_48_S8) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
7211
};
7212
7213
static const CGEN_IFMT ifmt_clip32_b_Imm_40_QI_Imm_48_QI_24_16_Prefixed_dst32_24_16_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
7214
  32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_40_S8) }, { F (F_15_1) }, { F (F_DSP_48_S8) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
7215
};
7216
7217
static const CGEN_IFMT ifmt_clip32_b_Imm_40_QI_Imm_48_QI_24_16_Prefixed_dst32_24_16_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
7218
  32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_40_S8) }, { F (F_15_1) }, { F (F_DSP_48_S8) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
7219
};
7220
7221
static const CGEN_IFMT ifmt_clip32_b_Imm_40_QI_Imm_48_QI_24_16_Prefixed_dst32_24_16_absolute_Prefixed_QI ATTRIBUTE_UNUSED = {
7222
  32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_40_S8) }, { F (F_15_1) }, { F (F_DSP_48_S8) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } }
7223
};
7224
7225
static const CGEN_IFMT ifmt_clip32_b_Imm_48_QI_Imm_56_QI_24_24_Prefixed_dst32_24_24_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = {
7226
  32, 64, 0xffffbf00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_DSP_48_S8) }, { F (F_18_2) }, { F (F_20_4) }, { F (F_DSP_56_S8) }, { 0 } }
7227
};
7228
7229
static const CGEN_IFMT ifmt_clip32_b_Imm_48_QI_Imm_56_QI_24_24_Prefixed_dst32_24_24_absolute_Prefixed_QI ATTRIBUTE_UNUSED = {
7230
  32, 64, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U24) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_DSP_48_S8) }, { F (F_18_2) }, { F (F_20_4) }, { F (F_DSP_56_S8) }, { 0 } }
7231
};
7232
7233
static const CGEN_IFMT ifmt_bxor32_X_bit32_24_Prefixed_bit32_Rn_direct_Prefixed ATTRIBUTE_UNUSED = {
7234
  24, 24, 0xffff38, { { F (F_0_4) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_QI) }, { F (F_BITNO32_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_3) }, { 0 } }
7235
};
7236
7237
static const CGEN_IFMT ifmt_bxor32_X_bit32_24_Prefixed_bit32_An_direct_Prefixed ATTRIBUTE_UNUSED = {
7238
  24, 24, 0xffffb8, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_BITNO32_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_3) }, { 0 } }
7239
};
7240
7241
static const CGEN_IFMT ifmt_bxor32_X_bit32_24_Prefixed_bit32_An_indirect_Prefixed ATTRIBUTE_UNUSED = {
7242
  24, 24, 0xffffb8, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_BITNO32_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_3) }, { 0 } }
7243
};
7244
7245
static const CGEN_IFMT ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_An_relative_Prefixed ATTRIBUTE_UNUSED = {
7246
  32, 32, 0xffffb800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_BITBASE32_24_U11_PREFIXED) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_3) }, { 0 } }
7247
};
7248
7249
static const CGEN_IFMT ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_An_relative_Prefixed ATTRIBUTE_UNUSED = {
7250
  32, 40, 0xffffb800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_BITBASE32_24_U19_PREFIXED) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_3) }, { 0 } }
7251
};
7252
7253
static const CGEN_IFMT ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_27_An_relative_Prefixed ATTRIBUTE_UNUSED = {
7254
  32, 48, 0xffffb800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_BITBASE32_24_U27_PREFIXED) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_3) }, { 0 } }
7255
};
7256
7257
static const CGEN_IFMT ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_SB_relative_Prefixed ATTRIBUTE_UNUSED = {
7258
  32, 32, 0xfffff800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_BITBASE32_24_U11_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_3) }, { 0 } }
7259
};
7260
7261
static const CGEN_IFMT ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_SB_relative_Prefixed ATTRIBUTE_UNUSED = {
7262
  32, 40, 0xfffff800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_BITBASE32_24_U19_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_3) }, { 0 } }
7263
};
7264
7265
static const CGEN_IFMT ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_FB_relative_Prefixed ATTRIBUTE_UNUSED = {
7266
  32, 32, 0xfffff800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_BITBASE32_24_S11_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_3) }, { 0 } }
7267
};
7268
7269
static const CGEN_IFMT ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_FB_relative_Prefixed ATTRIBUTE_UNUSED = {
7270
  32, 40, 0xfffff800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_BITBASE32_24_S19_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_3) }, { 0 } }
7271
};
7272
7273
static const CGEN_IFMT ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_absolute_Prefixed ATTRIBUTE_UNUSED = {
7274
  32, 40, 0xfffff800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_BITBASE32_24_U19_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_3) }, { 0 } }
7275
};
7276
7277
static const CGEN_IFMT ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_27_absolute_Prefixed ATTRIBUTE_UNUSED = {
7278
  32, 48, 0xfffff800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_BITBASE32_24_U27_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_3) }, { 0 } }
7279
};
7280
7281
static const CGEN_IFMT ifmt_bxor16_X_bit16_16_bit16_Rn_direct ATTRIBUTE_UNUSED = {
7282
  24, 24, 0xfffc00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_DSP_16_U8) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
7283
};
7284
7285
static const CGEN_IFMT ifmt_bxor16_X_bit16_16_bit16_An_direct ATTRIBUTE_UNUSED = {
7286
  24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_DSP_16_U8) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
7287
};
7288
7289
static const CGEN_IFMT ifmt_bxor16_X_bit16_16_bit16_An_indirect ATTRIBUTE_UNUSED = {
7290
  16, 16, 0xfffe, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
7291
};
7292
7293
static const CGEN_IFMT ifmt_bxor16_X_bit16_16_bit16_16_8_An_relative ATTRIBUTE_UNUSED = {
7294
  24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
7295
};
7296
7297
static const CGEN_IFMT ifmt_bxor16_X_bit16_16_bit16_16_16_An_relative ATTRIBUTE_UNUSED = {
7298
  32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
7299
};
7300
7301
static const CGEN_IFMT ifmt_bxor16_X_bit16_16_bit16_16_8_SB_relative ATTRIBUTE_UNUSED = {
7302
  24, 24, 0xffff00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
7303
};
7304
7305
static const CGEN_IFMT ifmt_bxor16_X_bit16_16_bit16_16_16_SB_relative ATTRIBUTE_UNUSED = {
7306
  32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
7307
};
7308
7309
static const CGEN_IFMT ifmt_bxor16_X_bit16_16_bit16_16_8_FB_relative ATTRIBUTE_UNUSED = {
7310
  24, 24, 0xffff00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
7311
};
7312
7313
static const CGEN_IFMT ifmt_bxor16_X_bit16_16_bit16_16_16_absolute ATTRIBUTE_UNUSED = {
7314
  32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
7315
};
7316
7317
static const CGEN_IFMT ifmt_btsts32_X_bit32_16_Unprefixed_bit32_Rn_direct_Unprefixed ATTRIBUTE_UNUSED = {
7318
  16, 16, 0xff38, { { F (F_0_4) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_BITNO32_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_3) }, { 0 } }
7319
};
7320
7321
static const CGEN_IFMT ifmt_btsts32_X_bit32_16_Unprefixed_bit32_An_direct_Unprefixed ATTRIBUTE_UNUSED = {
7322
  16, 16, 0xffb8, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_BITNO32_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_3) }, { 0 } }
7323
};
7324
7325
static const CGEN_IFMT ifmt_btsts32_X_bit32_16_Unprefixed_bit32_An_indirect_Unprefixed ATTRIBUTE_UNUSED = {
7326
  16, 16, 0xffb8, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_BITNO32_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_3) }, { 0 } }
7327
};
7328
7329
static const CGEN_IFMT ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_11_An_relative_Unprefixed ATTRIBUTE_UNUSED = {
7330
  24, 24, 0xffb800, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_BITBASE32_16_U11_UNPREFIXED) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_3) }, { 0 } }
7331
};
7332
7333
static const CGEN_IFMT ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_An_relative_Unprefixed ATTRIBUTE_UNUSED = {
7334
  32, 32, 0xffb80000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_BITBASE32_16_U19_UNPREFIXED) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_3) }, { 0 } }
7335
};
7336
7337
static const CGEN_IFMT ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_27_An_relative_Unprefixed ATTRIBUTE_UNUSED = {
7338
  32, 40, 0xffb80000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_BITBASE32_16_U27_UNPREFIXED) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_3) }, { 0 } }
7339
};
7340
7341
static const CGEN_IFMT ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_11_SB_relative_Unprefixed ATTRIBUTE_UNUSED = {
7342
  24, 24, 0xfff800, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_BITBASE32_16_U11_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_3) }, { 0 } }
7343
};
7344
7345
static const CGEN_IFMT ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_SB_relative_Unprefixed ATTRIBUTE_UNUSED = {
7346
  32, 32, 0xfff80000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_BITBASE32_16_U19_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_3) }, { 0 } }
7347
};
7348
7349
static const CGEN_IFMT ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_11_FB_relative_Unprefixed ATTRIBUTE_UNUSED = {
7350
  24, 24, 0xfff800, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_BITBASE32_16_S11_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_3) }, { 0 } }
7351
};
7352
7353
static const CGEN_IFMT ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_FB_relative_Unprefixed ATTRIBUTE_UNUSED = {
7354
  32, 32, 0xfff80000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_BITBASE32_16_S19_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_3) }, { 0 } }
7355
};
7356
7357
static const CGEN_IFMT ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_absolute_Unprefixed ATTRIBUTE_UNUSED = {
7358
  32, 32, 0xfff80000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_BITBASE32_16_U19_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_3) }, { 0 } }
7359
};
7360
7361
static const CGEN_IFMT ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_27_absolute_Unprefixed ATTRIBUTE_UNUSED = {
7362
  32, 40, 0xfff80000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_BITBASE32_16_U27_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_3) }, { 0 } }
7363
};
7364
7365
static const CGEN_IFMT ifmt_btst16_S_bit16_11_S_bit16_11_SB_relative_S ATTRIBUTE_UNUSED = {
7366
  16, 16, 0xf800, { { F (F_0_2) }, { F (F_BITBASE16_U11_S) }, { F (F_2_2) }, { F (F_4_1) }, { 0 } }
7367
};
7368
7369
static const CGEN_IFMT ifmt_bm32_bit32_basic_Unprefixed_cond32_16_bit32_Rn_direct_Unprefixed ATTRIBUTE_UNUSED = {
7370
  24, 24, 0xff3800, { { F (F_0_4) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_BITNO32_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_3) }, { F (F_DSP_16_U8) }, { 0 } }
7371
};
7372
7373
static const CGEN_IFMT ifmt_bm32_bit32_basic_Unprefixed_cond32_16_bit32_An_direct_Unprefixed ATTRIBUTE_UNUSED = {
7374
  24, 24, 0xffb800, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_BITNO32_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_3) }, { F (F_DSP_16_U8) }, { 0 } }
7375
};
7376
7377
static const CGEN_IFMT ifmt_bm32_bit32_basic_Unprefixed_cond32_16_bit32_An_indirect_Unprefixed ATTRIBUTE_UNUSED = {
7378
  24, 24, 0xffb800, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_BITNO32_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_3) }, { F (F_DSP_16_U8) }, { 0 } }
7379
};
7380
7381
static const CGEN_IFMT ifmt_bm32_bit32_16_8_Unprefixed_cond32_24_bit32_16_11_An_relative_Unprefixed ATTRIBUTE_UNUSED = {
7382
  32, 32, 0xffb80000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_BITBASE32_16_U11_UNPREFIXED) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_3) }, { F (F_DSP_24_U8) }, { 0 } }
7383
};
7384
7385
static const CGEN_IFMT ifmt_bm32_bit32_16_8_Unprefixed_cond32_24_bit32_16_11_SB_relative_Unprefixed ATTRIBUTE_UNUSED = {
7386
  32, 32, 0xfff80000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_BITBASE32_16_U11_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_3) }, { F (F_DSP_24_U8) }, { 0 } }
7387
};
7388
7389
static const CGEN_IFMT ifmt_bm32_bit32_16_8_Unprefixed_cond32_24_bit32_16_11_FB_relative_Unprefixed ATTRIBUTE_UNUSED = {
7390
  32, 32, 0xfff80000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_BITBASE32_16_S11_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_3) }, { F (F_DSP_24_U8) }, { 0 } }
7391
};
7392
7393
static const CGEN_IFMT ifmt_bm32_bit32_16_16_Unprefixed_cond32_32_bit32_16_19_An_relative_Unprefixed ATTRIBUTE_UNUSED = {
7394
  32, 40, 0xffb80000, { { F (F_0_4) }, { F (F_DSP_32_U8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_BITBASE32_16_U19_UNPREFIXED) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_3) }, { 0 } }
7395
};
7396
7397
static const CGEN_IFMT ifmt_bm32_bit32_16_16_Unprefixed_cond32_32_bit32_16_19_SB_relative_Unprefixed ATTRIBUTE_UNUSED = {
7398
  32, 40, 0xfff80000, { { F (F_0_4) }, { F (F_DSP_32_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_BITBASE32_16_U19_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_3) }, { 0 } }
7399
};
7400
7401
static const CGEN_IFMT ifmt_bm32_bit32_16_16_Unprefixed_cond32_32_bit32_16_19_FB_relative_Unprefixed ATTRIBUTE_UNUSED = {
7402
  32, 40, 0xfff80000, { { F (F_0_4) }, { F (F_DSP_32_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_BITBASE32_16_S19_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_3) }, { 0 } }
7403
};
7404
7405
static const CGEN_IFMT ifmt_bm32_bit32_16_16_Unprefixed_cond32_32_bit32_16_19_absolute_Unprefixed ATTRIBUTE_UNUSED = {
7406
  32, 40, 0xfff80000, { { F (F_0_4) }, { F (F_DSP_32_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_BITBASE32_16_U19_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_3) }, { 0 } }
7407
};
7408
7409
static const CGEN_IFMT ifmt_bm32_bit32_16_24_Unprefixed_cond32_40_bit32_16_27_An_relative_Unprefixed ATTRIBUTE_UNUSED = {
7410
  32, 48, 0xffb80000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_BITBASE32_16_U27_UNPREFIXED) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_DSP_40_U8) }, { F (F_10_3) }, { 0 } }
7411
};
7412
7413
static const CGEN_IFMT ifmt_bm32_bit32_16_24_Unprefixed_cond32_40_bit32_16_27_absolute_Unprefixed ATTRIBUTE_UNUSED = {
7414
  32, 48, 0xfff80000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_BITBASE32_16_U27_UNPREFIXED) }, { F (F_7_1) }, { F (F_DSP_40_U8) }, { F (F_10_3) }, { 0 } }
7415
};
7416
7417
static const CGEN_IFMT ifmt_bm16_bit16_16_8_cond16_24_bit16_Rn_direct ATTRIBUTE_UNUSED = {
7418
  32, 32, 0xfffc0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_DSP_16_U8) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_24_U8) }, { 0 } }
7419
};
7420
7421
static const CGEN_IFMT ifmt_bm16_bit16_16_8_cond16_24_bit16_An_direct ATTRIBUTE_UNUSED = {
7422
  32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_DSP_16_U8) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_24_U8) }, { 0 } }
7423
};
7424
7425
static const CGEN_IFMT ifmt_bm16_bit16_16_8_cond16_24_bit16_16_8_An_relative ATTRIBUTE_UNUSED = {
7426
  32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_24_U8) }, { 0 } }
7427
};
7428
7429
static const CGEN_IFMT ifmt_bm16_bit16_16_8_cond16_24_bit16_16_8_SB_relative ATTRIBUTE_UNUSED = {
7430
  32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_24_U8) }, { 0 } }
7431
};
7432
7433
static const CGEN_IFMT ifmt_bm16_bit16_16_8_cond16_24_bit16_16_8_FB_relative ATTRIBUTE_UNUSED = {
7434
  32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_24_U8) }, { 0 } }
7435
};
7436
7437
static const CGEN_IFMT ifmt_bm16_bit16_16_16_cond16_32_bit16_16_16_An_relative ATTRIBUTE_UNUSED = {
7438
  32, 40, 0xfffe0000, { { F (F_0_4) }, { F (F_DSP_32_U8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
7439
};
7440
7441
static const CGEN_IFMT ifmt_bm16_bit16_16_16_cond16_32_bit16_16_16_SB_relative ATTRIBUTE_UNUSED = {
7442
  32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_U8) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
7443
};
7444
7445
static const CGEN_IFMT ifmt_bm16_bit16_16_16_cond16_32_bit16_16_16_absolute ATTRIBUTE_UNUSED = {
7446
  32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_U8) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } }
7447
};
7448
7449
static const CGEN_IFMT ifmt_bm16_bit16_16_basic_cond16_16_bit16_An_indirect ATTRIBUTE_UNUSED = {
7450
  24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_16_U8) }, { 0 } }
7451
};
7452
7453
static const CGEN_IFMT ifmt_adjnz32_w_imm4_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
7454
  32, 32, 0xffb00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { F (F_LAB_24_8) }, { 0 } }
7455
};
7456
7457
static const CGEN_IFMT ifmt_adjnz32_w_imm4_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
7458
  32, 32, 0xfff00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { F (F_LAB_24_8) }, { 0 } }
7459
};
7460
7461
static const CGEN_IFMT ifmt_adjnz32_w_imm4_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
7462
  32, 32, 0xfff00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { F (F_LAB_24_8) }, { 0 } }
7463
};
7464
7465
static const CGEN_IFMT ifmt_adjnz32_w_imm4_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
7466
  32, 40, 0xffb00000, { { F (F_0_4) }, { F (F_LAB_32_8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
7467
};
7468
7469
static const CGEN_IFMT ifmt_adjnz32_w_imm4_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
7470
  32, 40, 0xfff00000, { { F (F_0_4) }, { F (F_LAB_32_8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
7471
};
7472
7473
static const CGEN_IFMT ifmt_adjnz32_w_imm4_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
7474
  32, 40, 0xfff00000, { { F (F_0_4) }, { F (F_LAB_32_8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
7475
};
7476
7477
static const CGEN_IFMT ifmt_adjnz32_w_imm4_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
7478
  32, 40, 0xfff00000, { { F (F_0_4) }, { F (F_LAB_32_8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
7479
};
7480
7481
static const CGEN_IFMT ifmt_adjnz32_w_imm4_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = {
7482
  32, 48, 0xffb00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_LAB_40_8) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
7483
};
7484
7485
static const CGEN_IFMT ifmt_adjnz32_w_imm4_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = {
7486
  32, 48, 0xfff00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_LAB_40_8) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
7487
};
7488
7489
static const CGEN_IFMT ifmt_adjnz32_w_imm4_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
7490
  24, 24, 0xff3000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { F (F_LAB_16_8) }, { 0 } }
7491
};
7492
7493
static const CGEN_IFMT ifmt_adjnz32_w_imm4_basic_Unprefixed_dst32_An_direct_Unprefixed_HI ATTRIBUTE_UNUSED = {
7494
  24, 24, 0xffb000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { F (F_LAB_16_8) }, { 0 } }
7495
};
7496
7497
static const CGEN_IFMT ifmt_adjnz32_w_imm4_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI ATTRIBUTE_UNUSED = {
7498
  24, 24, 0xffb000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { F (F_LAB_16_8) }, { 0 } }
7499
};
7500
7501
static const CGEN_IFMT ifmt_adjnz32_b_imm4_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
7502
  32, 32, 0xffb00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { F (F_LAB_24_8) }, { 0 } }
7503
};
7504
7505
static const CGEN_IFMT ifmt_adjnz32_b_imm4_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
7506
  32, 32, 0xfff00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { F (F_LAB_24_8) }, { 0 } }
7507
};
7508
7509
static const CGEN_IFMT ifmt_adjnz32_b_imm4_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
7510
  32, 32, 0xfff00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { F (F_LAB_24_8) }, { 0 } }
7511
};
7512
7513
static const CGEN_IFMT ifmt_adjnz32_b_imm4_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
7514
  32, 40, 0xffb00000, { { F (F_0_4) }, { F (F_LAB_32_8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
7515
};
7516
7517
static const CGEN_IFMT ifmt_adjnz32_b_imm4_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
7518
  32, 40, 0xfff00000, { { F (F_0_4) }, { F (F_LAB_32_8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
7519
};
7520
7521
static const CGEN_IFMT ifmt_adjnz32_b_imm4_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
7522
  32, 40, 0xfff00000, { { F (F_0_4) }, { F (F_LAB_32_8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
7523
};
7524
7525
static const CGEN_IFMT ifmt_adjnz32_b_imm4_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
7526
  32, 40, 0xfff00000, { { F (F_0_4) }, { F (F_LAB_32_8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
7527
};
7528
7529
static const CGEN_IFMT ifmt_adjnz32_b_imm4_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = {
7530
  32, 48, 0xffb00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_LAB_40_8) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
7531
};
7532
7533
static const CGEN_IFMT ifmt_adjnz32_b_imm4_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = {
7534
  32, 48, 0xfff00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_LAB_40_8) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
7535
};
7536
7537
static const CGEN_IFMT ifmt_adjnz32_b_imm4_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
7538
  24, 24, 0xff3000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { F (F_LAB_16_8) }, { 0 } }
7539
};
7540
7541
static const CGEN_IFMT ifmt_adjnz32_b_imm4_basic_Unprefixed_dst32_An_direct_Unprefixed_QI ATTRIBUTE_UNUSED = {
7542
  24, 24, 0xffb000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { F (F_LAB_16_8) }, { 0 } }
7543
};
7544
7545
static const CGEN_IFMT ifmt_adjnz32_b_imm4_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI ATTRIBUTE_UNUSED = {
7546
  24, 24, 0xffb000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { F (F_LAB_16_8) }, { 0 } }
7547
};
7548
7549
static const CGEN_IFMT ifmt_adjnz16_w_imm4_16_8_dst16_16_8_An_relative_HI ATTRIBUTE_UNUSED = {
7550
  32, 32, 0xff0e0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_24_8) }, { 0 } }
7551
};
7552
7553
static const CGEN_IFMT ifmt_adjnz16_w_imm4_16_8_dst16_16_8_SB_relative_HI ATTRIBUTE_UNUSED = {
7554
  32, 32, 0xff0f0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_24_8) }, { 0 } }
7555
};
7556
7557
static const CGEN_IFMT ifmt_adjnz16_w_imm4_16_8_dst16_16_8_FB_relative_HI ATTRIBUTE_UNUSED = {
7558
  32, 32, 0xff0f0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_24_8) }, { 0 } }
7559
};
7560
7561
static const CGEN_IFMT ifmt_adjnz16_w_imm4_16_16_dst16_16_16_An_relative_HI ATTRIBUTE_UNUSED = {
7562
  32, 40, 0xff0e0000, { { F (F_0_4) }, { F (F_LAB_32_8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
7563
};
7564
7565
static const CGEN_IFMT ifmt_adjnz16_w_imm4_16_16_dst16_16_16_SB_relative_HI ATTRIBUTE_UNUSED = {
7566
  32, 40, 0xff0f0000, { { F (F_0_4) }, { F (F_LAB_32_8) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
7567
};
7568
7569
static const CGEN_IFMT ifmt_adjnz16_w_imm4_16_16_dst16_16_16_absolute_HI ATTRIBUTE_UNUSED = {
7570
  32, 40, 0xff0f0000, { { F (F_0_4) }, { F (F_LAB_32_8) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
7571
};
7572
7573
static const CGEN_IFMT ifmt_adjnz16_w_imm4_basic_dst16_Rn_direct_HI ATTRIBUTE_UNUSED = {
7574
  24, 24, 0xff0c00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_16_8) }, { 0 } }
7575
};
7576
7577
static const CGEN_IFMT ifmt_adjnz16_w_imm4_basic_dst16_An_direct_HI ATTRIBUTE_UNUSED = {
7578
  24, 24, 0xff0e00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_16_8) }, { 0 } }
7579
};
7580
7581
static const CGEN_IFMT ifmt_adjnz16_w_imm4_basic_dst16_An_indirect_HI ATTRIBUTE_UNUSED = {
7582
  24, 24, 0xff0e00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_16_8) }, { 0 } }
7583
};
7584
7585
static const CGEN_IFMT ifmt_adjnz16_b_imm4_16_8_dst16_16_8_An_relative_QI ATTRIBUTE_UNUSED = {
7586
  32, 32, 0xff0e0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_24_8) }, { 0 } }
7587
};
7588
7589
static const CGEN_IFMT ifmt_adjnz16_b_imm4_16_8_dst16_16_8_SB_relative_QI ATTRIBUTE_UNUSED = {
7590
  32, 32, 0xff0f0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_24_8) }, { 0 } }
7591
};
7592
7593
static const CGEN_IFMT ifmt_adjnz16_b_imm4_16_8_dst16_16_8_FB_relative_QI ATTRIBUTE_UNUSED = {
7594
  32, 32, 0xff0f0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_24_8) }, { 0 } }
7595
};
7596
7597
static const CGEN_IFMT ifmt_adjnz16_b_imm4_16_16_dst16_16_16_An_relative_QI ATTRIBUTE_UNUSED = {
7598
  32, 40, 0xff0e0000, { { F (F_0_4) }, { F (F_LAB_32_8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
7599
};
7600
7601
static const CGEN_IFMT ifmt_adjnz16_b_imm4_16_16_dst16_16_16_SB_relative_QI ATTRIBUTE_UNUSED = {
7602
  32, 40, 0xff0f0000, { { F (F_0_4) }, { F (F_LAB_32_8) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
7603
};
7604
7605
static const CGEN_IFMT ifmt_adjnz16_b_imm4_16_16_dst16_16_16_absolute_QI ATTRIBUTE_UNUSED = {
7606
  32, 40, 0xff0f0000, { { F (F_0_4) }, { F (F_LAB_32_8) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } }
7607
};
7608
7609
static const CGEN_IFMT ifmt_adjnz16_b_imm4_basic_dst16_Rn_direct_QI ATTRIBUTE_UNUSED = {
7610
  24, 24, 0xff0c00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_16_8) }, { 0 } }
7611
};
7612
7613
static const CGEN_IFMT ifmt_adjnz16_b_imm4_basic_dst16_An_direct_QI ATTRIBUTE_UNUSED = {
7614
  24, 24, 0xff0e00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_16_8) }, { 0 } }
7615
};
7616
7617
static const CGEN_IFMT ifmt_adjnz16_b_imm4_basic_dst16_An_indirect_QI ATTRIBUTE_UNUSED = {
7618
  24, 24, 0xff0e00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_16_8) }, { 0 } }
7619
};
7620
7621
static const CGEN_IFMT ifmt_add32_l_s_imm1_S_an_dst32_1_S_A0_direct_HI ATTRIBUTE_UNUSED = {
7622
  8, 8, 0xdf, { { F (F_0_2) }, { F (F_7_1) }, { F (F_IMM1_S) }, { F (F_3_4) }, { 0 } }
7623
};
7624
7625
static const CGEN_IFMT ifmt_add32_l_s_imm1_S_an_dst32_1_S_A1_direct_HI ATTRIBUTE_UNUSED = {
7626
  8, 8, 0xdf, { { F (F_0_2) }, { F (F_7_1) }, { F (F_IMM1_S) }, { F (F_3_4) }, { 0 } }
7627
};
7628
7629
static const CGEN_IFMT ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
7630
  16, 16, 0xff30, { { F (F_0_3) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
7631
};
7632
7633
static const CGEN_IFMT ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = {
7634
  16, 16, 0xffb0, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
7635
};
7636
7637
static const CGEN_IFMT ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = {
7638
  16, 16, 0xffb0, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
7639
};
7640
7641
static const CGEN_IFMT ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_16_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
7642
  24, 24, 0xffb000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
7643
};
7644
7645
static const CGEN_IFMT ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
7646
  32, 32, 0xffb00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
7647
};
7648
7649
static const CGEN_IFMT ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_16_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
7650
  32, 40, 0xffb00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
7651
};
7652
7653
static const CGEN_IFMT ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_16_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
7654
  24, 24, 0xfff000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
7655
};
7656
7657
static const CGEN_IFMT ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
7658
  32, 32, 0xfff00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
7659
};
7660
7661
static const CGEN_IFMT ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_16_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
7662
  24, 24, 0xfff000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
7663
};
7664
7665
static const CGEN_IFMT ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = {
7666
  32, 32, 0xfff00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
7667
};
7668
7669
static const CGEN_IFMT ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_16_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
7670
  32, 32, 0xfff00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
7671
};
7672
7673
static const CGEN_IFMT ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_16_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = {
7674
  32, 40, 0xfff00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } }
7675
};
7676
7677
static const CGEN_IFMT ifmt_add16_wQ_sp ATTRIBUTE_UNUSED = {
7678
  16, 16, 0xfff0, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_IMM_12_S4) }, { 0 } }
7679
};
7680
7681
static const CGEN_IFMT ifmt_add16_b_G_sp ATTRIBUTE_UNUSED = {
7682
  24, 24, 0xffff00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { 0 } }
7683
};
7684
7685
static const CGEN_IFMT ifmt_add16_w_G_sp ATTRIBUTE_UNUSED = {
7686
  32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_12_4) }, { F (F_DSP_16_S16) }, { 0 } }
7687
};
7688
7689
static const CGEN_IFMT ifmt_add32_l_imm3_Q ATTRIBUTE_UNUSED = {
7690
  8, 8, 0xce, { { F (F_0_2) }, { F (F_IMM3_S) }, { F (F_4_3) }, { 0 } }
7691
};
7692
7693
static const CGEN_IFMT ifmt_add32_l_imm8_S ATTRIBUTE_UNUSED = {
7694
  24, 24, 0xffff00, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { 0 } }
7695
};
7696
7697
static const CGEN_IFMT ifmt_add32_l_imm16_G ATTRIBUTE_UNUSED = {
7698
  32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_12_4) }, { F (F_DSP_16_S16) }, { 0 } }
7699
};
7700
7701
static const CGEN_IFMT ifmt_dadc16_b_r0h_r0l ATTRIBUTE_UNUSED = {
7702
  16, 16, 0xffff, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_12_4) }, { 0 } }
7703
};
7704
7705
static const CGEN_IFMT ifmt_bm16_c ATTRIBUTE_UNUSED = {
7706
  16, 16, 0xfff0, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_COND16) }, { 0 } }
7707
};
7708
7709
static const CGEN_IFMT ifmt_bm32_c ATTRIBUTE_UNUSED = {
7710
  16, 16, 0xffb8, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_COND32) }, { F (F_10_3) }, { 0 } }
7711
};
7712
7713
static const CGEN_IFMT ifmt_brk16 ATTRIBUTE_UNUSED = {
7714
  8, 8, 0xff, { { F (F_0_4) }, { F (F_4_4) }, { 0 } }
7715
};
7716
7717
static const CGEN_IFMT ifmt_btst_s ATTRIBUTE_UNUSED = {
7718
  24, 24, 0xce0000, { { F (F_0_2) }, { F (F_IMM3_S) }, { F (F_4_3) }, { F (F_DSP_8_U16) }, { 0 } }
7719
};
7720
7721
static const CGEN_IFMT ifmt_dec16_w ATTRIBUTE_UNUSED = {
7722
  8, 8, 0xf7, { { F (F_0_4) }, { F (F_DST16_AN_S) }, { F (F_5_3) }, { 0 } }
7723
};
7724
7725
static const CGEN_IFMT ifmt_div32_b_Imm_16_QI ATTRIBUTE_UNUSED = {
7726
  24, 24, 0xffff00, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_3) }, { F (F_11_1) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { 0 } }
7727
};
7728
7729
static const CGEN_IFMT ifmt_div32_w_Imm_16_HI ATTRIBUTE_UNUSED = {
7730
  32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_3) }, { F (F_11_1) }, { F (F_12_4) }, { F (F_DSP_16_S16) }, { 0 } }
7731
};
7732
7733
static const CGEN_IFMT ifmt_enter16 ATTRIBUTE_UNUSED = {
7734
  24, 24, 0xffff00, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { 0 } }
7735
};
7736
7737
static const CGEN_IFMT ifmt_enter32 ATTRIBUTE_UNUSED = {
7738
  16, 16, 0xff00, { { F (F_0_4) }, { F (F_4_4) }, { F (F_DSP_8_U8) }, { 0 } }
7739
};
7740
7741
static const CGEN_IFMT ifmt_fclr16 ATTRIBUTE_UNUSED = {
7742
  16, 16, 0xff8f, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_9_3) }, { F (F_12_4) }, { 0 } }
7743
};
7744
7745
static const CGEN_IFMT ifmt_fclr ATTRIBUTE_UNUSED = {
7746
  16, 16, 0xfff8, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
7747
};
7748
7749
static const CGEN_IFMT ifmt_int16 ATTRIBUTE_UNUSED = {
7750
  16, 16, 0xffc0, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_2) }, { F (F_DSP_10_U6) }, { 0 } }
7751
};
7752
7753
static const CGEN_IFMT ifmt_int32 ATTRIBUTE_UNUSED = {
7754
  16, 16, 0xff03, { { F (F_0_4) }, { F (F_4_4) }, { F (F_DSP_8_U6) }, { F (F_14_2) }, { 0 } }
7755
};
7756
7757
static const CGEN_IFMT ifmt_jcnd16_5 ATTRIBUTE_UNUSED = {
7758
  16, 16, 0xf800, { { F (F_0_4) }, { F (F_4_1) }, { F (F_COND16J_5) }, { F (F_LAB_8_8) }, { 0 } }
7759
};
7760
7761
static const CGEN_IFMT ifmt_jcnd16 ATTRIBUTE_UNUSED = {
7762
  24, 24, 0xfff000, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_COND16) }, { F (F_LAB_16_8) }, { 0 } }
7763
};
7764
7765
static const CGEN_IFMT ifmt_jcnd32 ATTRIBUTE_UNUSED = {
7766
  16, 16, 0x8e00, { { F (F_0_1) }, { F (F_COND32J) }, { F (F_4_3) }, { F (F_LAB_8_8) }, { 0 } }
7767
};
7768
7769
static const CGEN_IFMT ifmt_jmp16_s ATTRIBUTE_UNUSED = {
7770
  8, 8, 0xf8, { { F (F_0_4) }, { F (F_4_1) }, { F (F_LAB_5_3) }, { 0 } }
7771
};
7772
7773
static const CGEN_IFMT ifmt_jmp16_b ATTRIBUTE_UNUSED = {
7774
  16, 16, 0xff00, { { F (F_0_4) }, { F (F_4_4) }, { F (F_LAB_8_8) }, { 0 } }
7775
};
7776
7777
static const CGEN_IFMT ifmt_jmp16_w ATTRIBUTE_UNUSED = {
7778
  24, 24, 0xff0000, { { F (F_0_4) }, { F (F_4_4) }, { F (F_LAB_8_16) }, { 0 } }
7779
};
7780
7781
static const CGEN_IFMT ifmt_jmp16_a ATTRIBUTE_UNUSED = {
7782
  32, 32, 0xff000000, { { F (F_0_4) }, { F (F_4_4) }, { F (F_LAB_8_24) }, { 0 } }
7783
};
7784
7785
static const CGEN_IFMT ifmt_jmps16 ATTRIBUTE_UNUSED = {
7786
  16, 16, 0xff00, { { F (F_0_4) }, { F (F_4_4) }, { F (F_DSP_8_S8) }, { 0 } }
7787
};
7788
7789
static const CGEN_IFMT ifmt_jmp32_s ATTRIBUTE_UNUSED = {
7790
  8, 8, 0xce, { { F (F_0_2) }, { F (F_LAB32_JMP_S) }, { F (F_4_3) }, { 0 } }
7791
};
7792
7793
static const CGEN_IFMT ifmt_ldc16_imm16 ATTRIBUTE_UNUSED = {
7794
  32, 32, 0xff8f0000, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_9_3) }, { F (F_12_4) }, { F (F_DSP_16_S16) }, { 0 } }
7795
};
7796
7797
static const CGEN_IFMT ifmt_ldc32_imm16_cr1 ATTRIBUTE_UNUSED = {
7798
  32, 32, 0xfff80000, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_12_1) }, { F (F_13_3) }, { F (F_DSP_16_S16) }, { 0 } }
7799
};
7800
7801
static const CGEN_IFMT ifmt_ldc32_imm16_cr2 ATTRIBUTE_UNUSED = {
7802
  32, 40, 0xfff80000, { { F (F_0_4) }, { F (F_DSP_16_U24) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
7803
};
7804
7805
static const CGEN_IFMT ifmt_ldc32_imm16_cr3 ATTRIBUTE_UNUSED = {
7806
  32, 40, 0xfff80000, { { F (F_0_4) }, { F (F_DSP_16_U24) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
7807
};
7808
7809
static const CGEN_IFMT ifmt_ldctx16 ATTRIBUTE_UNUSED = {
7810
  32, 56, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_U24) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { 0 } }
7811
};
7812
7813
static const CGEN_IFMT ifmt_ldipl16_imm ATTRIBUTE_UNUSED = {
7814
  16, 16, 0xfff8, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_12_1) }, { F (F_IMM_13_U3) }, { 0 } }
7815
};
7816
7817
static const CGEN_IFMT ifmt_mov16_w_S_imm_a0 ATTRIBUTE_UNUSED = {
7818
  24, 24, 0xff0000, { { F (F_0_4) }, { F (F_4_4) }, { F (F_DSP_8_S16) }, { 0 } }
7819
};
7820
7821
static const CGEN_IFMT ifmt_mov32_l_a0 ATTRIBUTE_UNUSED = {
7822
  32, 32, 0xff000000, { { F (F_0_4) }, { F (F_4_4) }, { F (F_DSP_8_S24) }, { 0 } }
7823
};
7824
7825
static const CGEN_IFMT ifmt_popc16_imm16 ATTRIBUTE_UNUSED = {
7826
  16, 16, 0xff8f, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_9_3) }, { F (F_12_4) }, { 0 } }
7827
};
7828
7829
static const CGEN_IFMT ifmt_popc32_imm16_cr1 ATTRIBUTE_UNUSED = {
7830
  16, 16, 0xfff8, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
7831
};
7832
7833
static const CGEN_IFMT ifmt_popc32_imm16_cr2 ATTRIBUTE_UNUSED = {
7834
  16, 16, 0xfff8, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } }
7835
};
7836
7837
static const CGEN_IFMT ifmt_popm16 ATTRIBUTE_UNUSED = {
7838
  16, 16, 0xff00, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_8) }, { 0 } }
7839
};
7840
7841
static const CGEN_IFMT ifmt_pushm16 ATTRIBUTE_UNUSED = {
7842
  16, 16, 0xff00, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_8) }, { 0 } }
7843
};
7844
7845
static const CGEN_IFMT ifmt_push32_l_imm ATTRIBUTE_UNUSED = {
7846
  32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_16_S32) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_12_4) }, { 0 } }
7847
};
7848
7849
static const CGEN_IFMT ifmt_sha16_L_imm_r2r0 ATTRIBUTE_UNUSED = {
7850
  16, 16, 0xfff0, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_IMM_12_S4) }, { 0 } }
7851
};
7852
7853
static const CGEN_IFMT ifmt_stzx16_imm8_imm8_r0h ATTRIBUTE_UNUSED = {
7854
  24, 24, 0xff0000, { { F (F_0_4) }, { F (F_4_4) }, { F (F_DSP_8_S8) }, { F (F_DSP_16_S8) }, { 0 } }
7855
};
7856
7857
static const CGEN_IFMT ifmt_stzx16_imm8_imm8_dsp8sb ATTRIBUTE_UNUSED = {
7858
  32, 32, 0xff000000, { { F (F_0_4) }, { F (F_4_4) }, { F (F_DSP_8_S8) }, { F (F_DSP_16_U8) }, { F (F_DSP_24_S8) }, { 0 } }
7859
};
7860
7861
static const CGEN_IFMT ifmt_stzx16_imm8_imm8_dsp8fb ATTRIBUTE_UNUSED = {
7862
  32, 32, 0xff000000, { { F (F_0_4) }, { F (F_4_4) }, { F (F_DSP_8_S8) }, { F (F_DSP_16_S8) }, { F (F_DSP_24_S8) }, { 0 } }
7863
};
7864
7865
static const CGEN_IFMT ifmt_stzx16_imm8_imm8_abs16 ATTRIBUTE_UNUSED = {
7866
  32, 40, 0xff000000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_4) }, { F (F_DSP_8_S8) }, { F (F_DSP_16_U16) }, { 0 } }
7867
};
7868
7869
#undef F
7870
7871
#define A(a) (1 << CGEN_INSN_##a)
7872
#define OPERAND(op) M32C_OPERAND_##op
7873
#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
7874
#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
7875
7876
/* The instruction table.  */
7877
7878
static const CGEN_OPCODE m32c_cgen_insn_opcode_table[MAX_INSNS] =
7879
{
7880
  /* Special null first entry.
7881
     A `num' value of zero is thus invalid.
7882
     Also, the special `invalid' insn resides here.  */
7883
  { { 0, 0, 0, 0 }, {{0}}, 0, {0}},
7884
/* extz ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
7885
  {
7886
    { 0, 0, 0, 0 },
7887
    { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
7888
    & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_HI, { 0x1980b00 }
7889
  },
7890
/* extz ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
7891
  {
7892
    { 0, 0, 0, 0 },
7893
    { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
7894
    & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_HI, { 0x1982b00 }
7895
  },
7896
/* extz ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
7897
  {
7898
    { 0, 0, 0, 0 },
7899
    { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
7900
    & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_HI, { 0x1983b00 }
7901
  },
7902
/* extz ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
7903
  {
7904
    { 0, 0, 0, 0 },
7905
    { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
7906
    & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_HI, { 0x1908b00 }
7907
  },
7908
/* extz ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
7909
  {
7910
    { 0, 0, 0, 0 },
7911
    { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
7912
    & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_HI, { 0x190ab00 }
7913
  },
7914
/* extz ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
7915
  {
7916
    { 0, 0, 0, 0 },
7917
    { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
7918
    & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_HI, { 0x190bb00 }
7919
  },
7920
/* extz ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
7921
  {
7922
    { 0, 0, 0, 0 },
7923
    { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
7924
    & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_HI, { 0x1900b00 }
7925
  },
7926
/* extz ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
7927
  {
7928
    { 0, 0, 0, 0 },
7929
    { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
7930
    & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_HI, { 0x1902b00 }
7931
  },
7932
/* extz ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
7933
  {
7934
    { 0, 0, 0, 0 },
7935
    { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
7936
    & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_HI, { 0x1903b00 }
7937
  },
7938
/* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
7939
  {
7940
    { 0, 0, 0, 0 },
7941
    { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
7942
    & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_HI, { 0x1920b00 }
7943
  },
7944
/* extz ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
7945
  {
7946
    { 0, 0, 0, 0 },
7947
    { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
7948
    & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_HI, { 0x1922b00 }
7949
  },
7950
/* extz ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
7951
  {
7952
    { 0, 0, 0, 0 },
7953
    { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
7954
    & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_HI, { 0x1923b00 }
7955
  },
7956
/* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
7957
  {
7958
    { 0, 0, 0, 0 },
7959
    { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
7960
    & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_HI, { 0x1940b00 }
7961
  },
7962
/* extz ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
7963
  {
7964
    { 0, 0, 0, 0 },
7965
    { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
7966
    & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_HI, { 0x1942b00 }
7967
  },
7968
/* extz ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
7969
  {
7970
    { 0, 0, 0, 0 },
7971
    { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
7972
    & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_HI, { 0x1943b00 }
7973
  },
7974
/* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
7975
  {
7976
    { 0, 0, 0, 0 },
7977
    { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
7978
    & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_HI, { 0x1960b00 }
7979
  },
7980
/* extz ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
7981
  {
7982
    { 0, 0, 0, 0 },
7983
    { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
7984
    & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_HI, { 0x1962b00 }
7985
  },
7986
/* extz ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
7987
  {
7988
    { 0, 0, 0, 0 },
7989
    { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
7990
    & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_HI, { 0x1963b00 }
7991
  },
7992
/* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
7993
  {
7994
    { 0, 0, 0, 0 },
7995
    { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
7996
    & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_HI, { 0x1928b00 }
7997
  },
7998
/* extz ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
7999
  {
8000
    { 0, 0, 0, 0 },
8001
    { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
8002
    & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_HI, { 0x192ab00 }
8003
  },
8004
/* extz ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
8005
  {
8006
    { 0, 0, 0, 0 },
8007
    { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
8008
    & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_HI, { 0x192bb00 }
8009
  },
8010
/* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
8011
  {
8012
    { 0, 0, 0, 0 },
8013
    { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
8014
    & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_HI, { 0x1948b00 }
8015
  },
8016
/* extz ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
8017
  {
8018
    { 0, 0, 0, 0 },
8019
    { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
8020
    & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_HI, { 0x194ab00 }
8021
  },
8022
/* extz ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
8023
  {
8024
    { 0, 0, 0, 0 },
8025
    { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
8026
    & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_HI, { 0x194bb00 }
8027
  },
8028
/* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
8029
  {
8030
    { 0, 0, 0, 0 },
8031
    { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
8032
    & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_HI, { 0x192cb00 }
8033
  },
8034
/* extz ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
8035
  {
8036
    { 0, 0, 0, 0 },
8037
    { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
8038
    & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_HI, { 0x192eb00 }
8039
  },
8040
/* extz ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
8041
  {
8042
    { 0, 0, 0, 0 },
8043
    { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
8044
    & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_HI, { 0x192fb00 }
8045
  },
8046
/* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
8047
  {
8048
    { 0, 0, 0, 0 },
8049
    { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
8050
    & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_HI, { 0x194cb00 }
8051
  },
8052
/* extz ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
8053
  {
8054
    { 0, 0, 0, 0 },
8055
    { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
8056
    & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_HI, { 0x194eb00 }
8057
  },
8058
/* extz ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
8059
  {
8060
    { 0, 0, 0, 0 },
8061
    { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
8062
    & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_HI, { 0x194fb00 }
8063
  },
8064
/* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
8065
  {
8066
    { 0, 0, 0, 0 },
8067
    { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
8068
    & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_HI, { 0x196cb00 }
8069
  },
8070
/* extz ${Dsp-24-u8}[sb],${Dsp-32-u16} */
8071
  {
8072
    { 0, 0, 0, 0 },
8073
    { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
8074
    & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_HI, { 0x196eb00 }
8075
  },
8076
/* extz ${Dsp-24-s8}[fb],${Dsp-32-u16} */
8077
  {
8078
    { 0, 0, 0, 0 },
8079
    { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
8080
    & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_HI, { 0x196fb00 }
8081
  },
8082
/* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
8083
  {
8084
    { 0, 0, 0, 0 },
8085
    { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
8086
    & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_HI, { 0x1968b00 }
8087
  },
8088
/* extz ${Dsp-24-u8}[sb],${Dsp-32-u24} */
8089
  {
8090
    { 0, 0, 0, 0 },
8091
    { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
8092
    & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_HI, { 0x196ab00 }
8093
  },
8094
/* extz ${Dsp-24-s8}[fb],${Dsp-32-u24} */
8095
  {
8096
    { 0, 0, 0, 0 },
8097
    { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
8098
    & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_HI, { 0x196bb00 }
8099
  },
8100
/* extz ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
8101
  {
8102
    { 0, 0, 0, 0 },
8103
    { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
8104
    & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_HI, { 0x1a80b00 }
8105
  },
8106
/* extz ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
8107
  {
8108
    { 0, 0, 0, 0 },
8109
    { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
8110
    & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_HI, { 0x1a82b00 }
8111
  },
8112
/* extz ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
8113
  {
8114
    { 0, 0, 0, 0 },
8115
    { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
8116
    & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_HI, { 0x1a83b00 }
8117
  },
8118
/* extz ${Dsp-24-u16},$Dst32RnPrefixedHI */
8119
  {
8120
    { 0, 0, 0, 0 },
8121
    { { MNEM, ' ', OP (DSP_24_U16), ',', OP (DST32RNPREFIXEDHI), 0 } },
8122
    & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_HI, { 0x1b83b00 }
8123
  },
8124
/* extz ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
8125
  {
8126
    { 0, 0, 0, 0 },
8127
    { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
8128
    & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_HI, { 0x1a08b00 }
8129
  },
8130
/* extz ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
8131
  {
8132
    { 0, 0, 0, 0 },
8133
    { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
8134
    & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_HI, { 0x1a0ab00 }
8135
  },
8136
/* extz ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
8137
  {
8138
    { 0, 0, 0, 0 },
8139
    { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
8140
    & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_HI, { 0x1a0bb00 }
8141
  },
8142
/* extz ${Dsp-24-u16},$Dst32AnPrefixedHI */
8143
  {
8144
    { 0, 0, 0, 0 },
8145
    { { MNEM, ' ', OP (DSP_24_U16), ',', OP (DST32ANPREFIXEDHI), 0 } },
8146
    & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_direct_Prefixed_HI, { 0x1b0bb00 }
8147
  },
8148
/* extz ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
8149
  {
8150
    { 0, 0, 0, 0 },
8151
    { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
8152
    & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_HI, { 0x1a00b00 }
8153
  },
8154
/* extz ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
8155
  {
8156
    { 0, 0, 0, 0 },
8157
    { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
8158
    & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_HI, { 0x1a02b00 }
8159
  },
8160
/* extz ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
8161
  {
8162
    { 0, 0, 0, 0 },
8163
    { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
8164
    & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_HI, { 0x1a03b00 }
8165
  },
8166
/* extz ${Dsp-24-u16},[$Dst32AnPrefixed] */
8167
  {
8168
    { 0, 0, 0, 0 },
8169
    { { MNEM, ' ', OP (DSP_24_U16), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
8170
    & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_HI, { 0x1b03b00 }
8171
  },
8172
/* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
8173
  {
8174
    { 0, 0, 0, 0 },
8175
    { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
8176
    & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a20b00 }
8177
  },
8178
/* extz ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
8179
  {
8180
    { 0, 0, 0, 0 },
8181
    { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
8182
    & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a22b00 }
8183
  },
8184
/* extz ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
8185
  {
8186
    { 0, 0, 0, 0 },
8187
    { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
8188
    & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a23b00 }
8189
  },
8190
/* extz ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
8191
  {
8192
    { 0, 0, 0, 0 },
8193
    { { MNEM, ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
8194
    & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_An_relative_Prefixed_HI, { 0x1b23b00 }
8195
  },
8196
/* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
8197
  {
8198
    { 0, 0, 0, 0 },
8199
    { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
8200
    & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a40b00 }
8201
  },
8202
/* extz ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
8203
  {
8204
    { 0, 0, 0, 0 },
8205
    { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
8206
    & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a42b00 }
8207
  },
8208
/* extz ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
8209
  {
8210
    { 0, 0, 0, 0 },
8211
    { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
8212
    & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a43b00 }
8213
  },
8214
/* extz ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
8215
  {
8216
    { 0, 0, 0, 0 },
8217
    { { MNEM, ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
8218
    & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_An_relative_Prefixed_HI, { 0x1b43b00 }
8219
  },
8220
/* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
8221
  {
8222
    { 0, 0, 0, 0 },
8223
    { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
8224
    & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a60b00 }
8225
  },
8226
/* extz ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
8227
  {
8228
    { 0, 0, 0, 0 },
8229
    { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
8230
    & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a62b00 }
8231
  },
8232
/* extz ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
8233
  {
8234
    { 0, 0, 0, 0 },
8235
    { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
8236
    & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a63b00 }
8237
  },
8238
/* extz ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
8239
  {
8240
    { 0, 0, 0, 0 },
8241
    { { MNEM, ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
8242
    & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_An_relative_Prefixed_HI, { 0x1b63b00 }
8243
  },
8244
/* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
8245
  {
8246
    { 0, 0, 0, 0 },
8247
    { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
8248
    & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a28b00 }
8249
  },
8250
/* extz ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
8251
  {
8252
    { 0, 0, 0, 0 },
8253
    { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
8254
    & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a2ab00 }
8255
  },
8256
/* extz ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
8257
  {
8258
    { 0, 0, 0, 0 },
8259
    { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
8260
    & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a2bb00 }
8261
  },
8262
/* extz ${Dsp-24-u16},${Dsp-40-u8}[sb] */
8263
  {
8264
    { 0, 0, 0, 0 },
8265
    { { MNEM, ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
8266
    & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1b2bb00 }
8267
  },
8268
/* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
8269
  {
8270
    { 0, 0, 0, 0 },
8271
    { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
8272
    & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a48b00 }
8273
  },
8274
/* extz ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
8275
  {
8276
    { 0, 0, 0, 0 },
8277
    { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
8278
    & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a4ab00 }
8279
  },
8280
/* extz ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
8281
  {
8282
    { 0, 0, 0, 0 },
8283
    { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
8284
    & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a4bb00 }
8285
  },
8286
/* extz ${Dsp-24-u16},${Dsp-40-u16}[sb] */
8287
  {
8288
    { 0, 0, 0, 0 },
8289
    { { MNEM, ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
8290
    & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1b4bb00 }
8291
  },
8292
/* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
8293
  {
8294
    { 0, 0, 0, 0 },
8295
    { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
8296
    & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a2cb00 }
8297
  },
8298
/* extz ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
8299
  {
8300
    { 0, 0, 0, 0 },
8301
    { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
8302
    & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a2eb00 }
8303
  },
8304
/* extz ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
8305
  {
8306
    { 0, 0, 0, 0 },
8307
    { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
8308
    & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a2fb00 }
8309
  },
8310
/* extz ${Dsp-24-u16},${Dsp-40-s8}[fb] */
8311
  {
8312
    { 0, 0, 0, 0 },
8313
    { { MNEM, ' ', OP (DSP_24_U16), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
8314
    & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1b2fb00 }
8315
  },
8316
/* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
8317
  {
8318
    { 0, 0, 0, 0 },
8319
    { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
8320
    & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a4cb00 }
8321
  },
8322
/* extz ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
8323
  {
8324
    { 0, 0, 0, 0 },
8325
    { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
8326
    & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a4eb00 }
8327
  },
8328
/* extz ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
8329
  {
8330
    { 0, 0, 0, 0 },
8331
    { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
8332
    & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a4fb00 }
8333
  },
8334
/* extz ${Dsp-24-u16},${Dsp-40-s16}[fb] */
8335
  {
8336
    { 0, 0, 0, 0 },
8337
    { { MNEM, ' ', OP (DSP_24_U16), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
8338
    & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1b4fb00 }
8339
  },
8340
/* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
8341
  {
8342
    { 0, 0, 0, 0 },
8343
    { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
8344
    & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_HI, { 0x1a6cb00 }
8345
  },
8346
/* extz ${Dsp-24-u16}[sb],${Dsp-40-u16} */
8347
  {
8348
    { 0, 0, 0, 0 },
8349
    { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), 0 } },
8350
    & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_HI, { 0x1a6eb00 }
8351
  },
8352
/* extz ${Dsp-24-s16}[fb],${Dsp-40-u16} */
8353
  {
8354
    { 0, 0, 0, 0 },
8355
    { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), 0 } },
8356
    & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_HI, { 0x1a6fb00 }
8357
  },
8358
/* extz ${Dsp-24-u16},${Dsp-40-u16} */
8359
  {
8360
    { 0, 0, 0, 0 },
8361
    { { MNEM, ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), 0 } },
8362
    & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_absolute_Prefixed_HI, { 0x1b6fb00 }
8363
  },
8364
/* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
8365
  {
8366
    { 0, 0, 0, 0 },
8367
    { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
8368
    & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_HI, { 0x1a68b00 }
8369
  },
8370
/* extz ${Dsp-24-u16}[sb],${Dsp-40-u24} */
8371
  {
8372
    { 0, 0, 0, 0 },
8373
    { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), 0 } },
8374
    & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_HI, { 0x1a6ab00 }
8375
  },
8376
/* extz ${Dsp-24-s16}[fb],${Dsp-40-u24} */
8377
  {
8378
    { 0, 0, 0, 0 },
8379
    { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), 0 } },
8380
    & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_HI, { 0x1a6bb00 }
8381
  },
8382
/* extz ${Dsp-24-u16},${Dsp-40-u24} */
8383
  {
8384
    { 0, 0, 0, 0 },
8385
    { { MNEM, ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), 0 } },
8386
    & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_absolute_Prefixed_HI, { 0x1b6bb00 }
8387
  },
8388
/* extz ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
8389
  {
8390
    { 0, 0, 0, 0 },
8391
    { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
8392
    & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_HI, { 0x1b80b00 }
8393
  },
8394
/* extz ${Dsp-24-u24},$Dst32RnPrefixedHI */
8395
  {
8396
    { 0, 0, 0, 0 },
8397
    { { MNEM, ' ', OP (DSP_24_U24), ',', OP (DST32RNPREFIXEDHI), 0 } },
8398
    & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_HI, { 0x1b82b00 }
8399
  },
8400
/* extz ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
8401
  {
8402
    { 0, 0, 0, 0 },
8403
    { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
8404
    & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_HI, { 0x1b08b00 }
8405
  },
8406
/* extz ${Dsp-24-u24},$Dst32AnPrefixedHI */
8407
  {
8408
    { 0, 0, 0, 0 },
8409
    { { MNEM, ' ', OP (DSP_24_U24), ',', OP (DST32ANPREFIXEDHI), 0 } },
8410
    & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_direct_Prefixed_HI, { 0x1b0ab00 }
8411
  },
8412
/* extz ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
8413
  {
8414
    { 0, 0, 0, 0 },
8415
    { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
8416
    & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_HI, { 0x1b00b00 }
8417
  },
8418
/* extz ${Dsp-24-u24},[$Dst32AnPrefixed] */
8419
  {
8420
    { 0, 0, 0, 0 },
8421
    { { MNEM, ' ', OP (DSP_24_U24), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
8422
    & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_HI, { 0x1b02b00 }
8423
  },
8424
/* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
8425
  {
8426
    { 0, 0, 0, 0 },
8427
    { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
8428
    & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b20b00 }
8429
  },
8430
/* extz ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
8431
  {
8432
    { 0, 0, 0, 0 },
8433
    { { MNEM, ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
8434
    & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b22b00 }
8435
  },
8436
/* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
8437
  {
8438
    { 0, 0, 0, 0 },
8439
    { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
8440
    & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b40b00 }
8441
  },
8442
/* extz ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
8443
  {
8444
    { 0, 0, 0, 0 },
8445
    { { MNEM, ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
8446
    & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b42b00 }
8447
  },
8448
/* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
8449
  {
8450
    { 0, 0, 0, 0 },
8451
    { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
8452
    & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b60b00 }
8453
  },
8454
/* extz ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
8455
  {
8456
    { 0, 0, 0, 0 },
8457
    { { MNEM, ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
8458
    & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b62b00 }
8459
  },
8460
/* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
8461
  {
8462
    { 0, 0, 0, 0 },
8463
    { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
8464
    & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b28b00 }
8465
  },
8466
/* extz ${Dsp-24-u24},${Dsp-48-u8}[sb] */
8467
  {
8468
    { 0, 0, 0, 0 },
8469
    { { MNEM, ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
8470
    & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b2ab00 }
8471
  },
8472
/* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
8473
  {
8474
    { 0, 0, 0, 0 },
8475
    { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
8476
    & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b48b00 }
8477
  },
8478
/* extz ${Dsp-24-u24},${Dsp-48-u16}[sb] */
8479
  {
8480
    { 0, 0, 0, 0 },
8481
    { { MNEM, ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
8482
    & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b4ab00 }
8483
  },
8484
/* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
8485
  {
8486
    { 0, 0, 0, 0 },
8487
    { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
8488
    & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b2cb00 }
8489
  },
8490
/* extz ${Dsp-24-u24},${Dsp-48-s8}[fb] */
8491
  {
8492
    { 0, 0, 0, 0 },
8493
    { { MNEM, ' ', OP (DSP_24_U24), ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
8494
    & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b2eb00 }
8495
  },
8496
/* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
8497
  {
8498
    { 0, 0, 0, 0 },
8499
    { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
8500
    & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b4cb00 }
8501
  },
8502
/* extz ${Dsp-24-u24},${Dsp-48-s16}[fb] */
8503
  {
8504
    { 0, 0, 0, 0 },
8505
    { { MNEM, ' ', OP (DSP_24_U24), ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
8506
    & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b4eb00 }
8507
  },
8508
/* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
8509
  {
8510
    { 0, 0, 0, 0 },
8511
    { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), 0 } },
8512
    & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_absolute_Prefixed_HI, { 0x1b6cb00 }
8513
  },
8514
/* extz ${Dsp-24-u24},${Dsp-48-u16} */
8515
  {
8516
    { 0, 0, 0, 0 },
8517
    { { MNEM, ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), 0 } },
8518
    & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_absolute_Prefixed_HI, { 0x1b6eb00 }
8519
  },
8520
/* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
8521
  {
8522
    { 0, 0, 0, 0 },
8523
    { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), 0 } },
8524
    & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_absolute_Prefixed_HI, { 0x1b68b00 }
8525
  },
8526
/* extz ${Dsp-24-u24},${Dsp-48-u24} */
8527
  {
8528
    { 0, 0, 0, 0 },
8529
    { { MNEM, ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), 0 } },
8530
    & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_absolute_Prefixed_HI, { 0x1b6ab00 }
8531
  },
8532
/* extz $Src32RnPrefixedQI,$Dst32RnPrefixedHI */
8533
  {
8534
    { 0, 0, 0, 0 },
8535
    { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32RNPREFIXEDHI), 0 } },
8536
    & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_HI, { 0x1c80b }
8537
  },
8538
/* extz [$Src32AnPrefixed],$Dst32RnPrefixedHI */
8539
  {
8540
    { 0, 0, 0, 0 },
8541
    { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
8542
    & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_Rn_direct_Prefixed_HI, { 0x1880b }
8543
  },
8544
/* extz $Src32RnPrefixedQI,$Dst32AnPrefixedHI */
8545
  {
8546
    { 0, 0, 0, 0 },
8547
    { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32ANPREFIXEDHI), 0 } },
8548
    & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_direct_Prefixed_HI, { 0x1c08b }
8549
  },
8550
/* extz [$Src32AnPrefixed],$Dst32AnPrefixedHI */
8551
  {
8552
    { 0, 0, 0, 0 },
8553
    { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
8554
    & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_direct_Prefixed_HI, { 0x1808b }
8555
  },
8556
/* extz $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
8557
  {
8558
    { 0, 0, 0, 0 },
8559
    { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
8560
    & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_indirect_Prefixed_HI, { 0x1c00b }
8561
  },
8562
/* extz [$Src32AnPrefixed],[$Dst32AnPrefixed] */
8563
  {
8564
    { 0, 0, 0, 0 },
8565
    { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
8566
    & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_indirect_Prefixed_HI, { 0x1800b }
8567
  },
8568
/* extz $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
8569
  {
8570
    { 0, 0, 0, 0 },
8571
    { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
8572
    & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_HI, { 0x1c20b00 }
8573
  },
8574
/* extz [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
8575
  {
8576
    { 0, 0, 0, 0 },
8577
    { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
8578
    & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_An_relative_Prefixed_HI, { 0x1820b00 }
8579
  },
8580
/* extz $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
8581
  {
8582
    { 0, 0, 0, 0 },
8583
    { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
8584
    & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_HI, { 0x1c40b00 }
8585
  },
8586
/* extz [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
8587
  {
8588
    { 0, 0, 0, 0 },
8589
    { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
8590
    & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_An_relative_Prefixed_HI, { 0x1840b00 }
8591
  },
8592
/* extz $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
8593
  {
8594
    { 0, 0, 0, 0 },
8595
    { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
8596
    & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_HI, { 0x1c60b00 }
8597
  },
8598
/* extz [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
8599
  {
8600
    { 0, 0, 0, 0 },
8601
    { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
8602
    & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_An_relative_Prefixed_HI, { 0x1860b00 }
8603
  },
8604
/* extz $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
8605
  {
8606
    { 0, 0, 0, 0 },
8607
    { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
8608
    & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1c28b00 }
8609
  },
8610
/* extz [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
8611
  {
8612
    { 0, 0, 0, 0 },
8613
    { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
8614
    & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1828b00 }
8615
  },
8616
/* extz $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
8617
  {
8618
    { 0, 0, 0, 0 },
8619
    { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
8620
    & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1c48b00 }
8621
  },
8622
/* extz [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
8623
  {
8624
    { 0, 0, 0, 0 },
8625
    { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
8626
    & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1848b00 }
8627
  },
8628
/* extz $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
8629
  {
8630
    { 0, 0, 0, 0 },
8631
    { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
8632
    & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_HI, { 0x1c2cb00 }
8633
  },
8634
/* extz [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
8635
  {
8636
    { 0, 0, 0, 0 },
8637
    { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
8638
    & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_HI, { 0x182cb00 }
8639
  },
8640
/* extz $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
8641
  {
8642
    { 0, 0, 0, 0 },
8643
    { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
8644
    & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_HI, { 0x1c4cb00 }
8645
  },
8646
/* extz [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
8647
  {
8648
    { 0, 0, 0, 0 },
8649
    { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
8650
    & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_HI, { 0x184cb00 }
8651
  },
8652
/* extz $Src32RnPrefixedQI,${Dsp-24-u16} */
8653
  {
8654
    { 0, 0, 0, 0 },
8655
    { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), 0 } },
8656
    & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_HI, { 0x1c6cb00 }
8657
  },
8658
/* extz [$Src32AnPrefixed],${Dsp-24-u16} */
8659
  {
8660
    { 0, 0, 0, 0 },
8661
    { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
8662
    & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_absolute_Prefixed_HI, { 0x186cb00 }
8663
  },
8664
/* extz $Src32RnPrefixedQI,${Dsp-24-u24} */
8665
  {
8666
    { 0, 0, 0, 0 },
8667
    { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), 0 } },
8668
    & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_HI, { 0x1c68b00 }
8669
  },
8670
/* extz [$Src32AnPrefixed],${Dsp-24-u24} */
8671
  {
8672
    { 0, 0, 0, 0 },
8673
    { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
8674
    & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_absolute_Prefixed_HI, { 0x1868b00 }
8675
  },
8676
/* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
8677
  {
8678
    { 0, 0, 0, 0 },
8679
    { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
8680
    & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_HI, { 0x1980700 }
8681
  },
8682
/* exts.b ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
8683
  {
8684
    { 0, 0, 0, 0 },
8685
    { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
8686
    & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_HI, { 0x1982700 }
8687
  },
8688
/* exts.b ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
8689
  {
8690
    { 0, 0, 0, 0 },
8691
    { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
8692
    & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_HI, { 0x1983700 }
8693
  },
8694
/* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
8695
  {
8696
    { 0, 0, 0, 0 },
8697
    { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
8698
    & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_HI, { 0x1908700 }
8699
  },
8700
/* exts.b ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
8701
  {
8702
    { 0, 0, 0, 0 },
8703
    { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
8704
    & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_HI, { 0x190a700 }
8705
  },
8706
/* exts.b ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
8707
  {
8708
    { 0, 0, 0, 0 },
8709
    { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
8710
    & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_HI, { 0x190b700 }
8711
  },
8712
/* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
8713
  {
8714
    { 0, 0, 0, 0 },
8715
    { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
8716
    & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_HI, { 0x1900700 }
8717
  },
8718
/* exts.b ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
8719
  {
8720
    { 0, 0, 0, 0 },
8721
    { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
8722
    & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_HI, { 0x1902700 }
8723
  },
8724
/* exts.b ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
8725
  {
8726
    { 0, 0, 0, 0 },
8727
    { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
8728
    & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_HI, { 0x1903700 }
8729
  },
8730
/* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
8731
  {
8732
    { 0, 0, 0, 0 },
8733
    { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
8734
    & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_HI, { 0x1920700 }
8735
  },
8736
/* exts.b ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
8737
  {
8738
    { 0, 0, 0, 0 },
8739
    { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
8740
    & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_HI, { 0x1922700 }
8741
  },
8742
/* exts.b ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
8743
  {
8744
    { 0, 0, 0, 0 },
8745
    { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
8746
    & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_HI, { 0x1923700 }
8747
  },
8748
/* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
8749
  {
8750
    { 0, 0, 0, 0 },
8751
    { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
8752
    & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_HI, { 0x1940700 }
8753
  },
8754
/* exts.b ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
8755
  {
8756
    { 0, 0, 0, 0 },
8757
    { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
8758
    & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_HI, { 0x1942700 }
8759
  },
8760
/* exts.b ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
8761
  {
8762
    { 0, 0, 0, 0 },
8763
    { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
8764
    & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_HI, { 0x1943700 }
8765
  },
8766
/* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
8767
  {
8768
    { 0, 0, 0, 0 },
8769
    { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
8770
    & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_HI, { 0x1960700 }
8771
  },
8772
/* exts.b ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
8773
  {
8774
    { 0, 0, 0, 0 },
8775
    { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
8776
    & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_HI, { 0x1962700 }
8777
  },
8778
/* exts.b ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
8779
  {
8780
    { 0, 0, 0, 0 },
8781
    { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
8782
    & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_HI, { 0x1963700 }
8783
  },
8784
/* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
8785
  {
8786
    { 0, 0, 0, 0 },
8787
    { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
8788
    & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_HI, { 0x1928700 }
8789
  },
8790
/* exts.b ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
8791
  {
8792
    { 0, 0, 0, 0 },
8793
    { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
8794
    & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_HI, { 0x192a700 }
8795
  },
8796
/* exts.b ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
8797
  {
8798
    { 0, 0, 0, 0 },
8799
    { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
8800
    & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_HI, { 0x192b700 }
8801
  },
8802
/* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
8803
  {
8804
    { 0, 0, 0, 0 },
8805
    { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
8806
    & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_HI, { 0x1948700 }
8807
  },
8808
/* exts.b ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
8809
  {
8810
    { 0, 0, 0, 0 },
8811
    { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
8812
    & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_HI, { 0x194a700 }
8813
  },
8814
/* exts.b ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
8815
  {
8816
    { 0, 0, 0, 0 },
8817
    { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
8818
    & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_HI, { 0x194b700 }
8819
  },
8820
/* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
8821
  {
8822
    { 0, 0, 0, 0 },
8823
    { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
8824
    & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_HI, { 0x192c700 }
8825
  },
8826
/* exts.b ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
8827
  {
8828
    { 0, 0, 0, 0 },
8829
    { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
8830
    & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_HI, { 0x192e700 }
8831
  },
8832
/* exts.b ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
8833
  {
8834
    { 0, 0, 0, 0 },
8835
    { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
8836
    & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_HI, { 0x192f700 }
8837
  },
8838
/* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
8839
  {
8840
    { 0, 0, 0, 0 },
8841
    { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
8842
    & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_HI, { 0x194c700 }
8843
  },
8844
/* exts.b ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
8845
  {
8846
    { 0, 0, 0, 0 },
8847
    { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
8848
    & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_HI, { 0x194e700 }
8849
  },
8850
/* exts.b ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
8851
  {
8852
    { 0, 0, 0, 0 },
8853
    { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
8854
    & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_HI, { 0x194f700 }
8855
  },
8856
/* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
8857
  {
8858
    { 0, 0, 0, 0 },
8859
    { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
8860
    & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_HI, { 0x196c700 }
8861
  },
8862
/* exts.b ${Dsp-24-u8}[sb],${Dsp-32-u16} */
8863
  {
8864
    { 0, 0, 0, 0 },
8865
    { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
8866
    & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_HI, { 0x196e700 }
8867
  },
8868
/* exts.b ${Dsp-24-s8}[fb],${Dsp-32-u16} */
8869
  {
8870
    { 0, 0, 0, 0 },
8871
    { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
8872
    & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_HI, { 0x196f700 }
8873
  },
8874
/* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
8875
  {
8876
    { 0, 0, 0, 0 },
8877
    { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
8878
    & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_HI, { 0x1968700 }
8879
  },
8880
/* exts.b ${Dsp-24-u8}[sb],${Dsp-32-u24} */
8881
  {
8882
    { 0, 0, 0, 0 },
8883
    { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
8884
    & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_HI, { 0x196a700 }
8885
  },
8886
/* exts.b ${Dsp-24-s8}[fb],${Dsp-32-u24} */
8887
  {
8888
    { 0, 0, 0, 0 },
8889
    { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
8890
    & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_HI, { 0x196b700 }
8891
  },
8892
/* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
8893
  {
8894
    { 0, 0, 0, 0 },
8895
    { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
8896
    & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_HI, { 0x1a80700 }
8897
  },
8898
/* exts.b ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
8899
  {
8900
    { 0, 0, 0, 0 },
8901
    { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
8902
    & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_HI, { 0x1a82700 }
8903
  },
8904
/* exts.b ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
8905
  {
8906
    { 0, 0, 0, 0 },
8907
    { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
8908
    & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_HI, { 0x1a83700 }
8909
  },
8910
/* exts.b ${Dsp-24-u16},$Dst32RnPrefixedHI */
8911
  {
8912
    { 0, 0, 0, 0 },
8913
    { { MNEM, ' ', OP (DSP_24_U16), ',', OP (DST32RNPREFIXEDHI), 0 } },
8914
    & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_HI, { 0x1b83700 }
8915
  },
8916
/* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
8917
  {
8918
    { 0, 0, 0, 0 },
8919
    { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
8920
    & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_HI, { 0x1a08700 }
8921
  },
8922
/* exts.b ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
8923
  {
8924
    { 0, 0, 0, 0 },
8925
    { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
8926
    & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_HI, { 0x1a0a700 }
8927
  },
8928
/* exts.b ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
8929
  {
8930
    { 0, 0, 0, 0 },
8931
    { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
8932
    & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_HI, { 0x1a0b700 }
8933
  },
8934
/* exts.b ${Dsp-24-u16},$Dst32AnPrefixedHI */
8935
  {
8936
    { 0, 0, 0, 0 },
8937
    { { MNEM, ' ', OP (DSP_24_U16), ',', OP (DST32ANPREFIXEDHI), 0 } },
8938
    & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_direct_Prefixed_HI, { 0x1b0b700 }
8939
  },
8940
/* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
8941
  {
8942
    { 0, 0, 0, 0 },
8943
    { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
8944
    & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_HI, { 0x1a00700 }
8945
  },
8946
/* exts.b ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
8947
  {
8948
    { 0, 0, 0, 0 },
8949
    { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
8950
    & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_HI, { 0x1a02700 }
8951
  },
8952
/* exts.b ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
8953
  {
8954
    { 0, 0, 0, 0 },
8955
    { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
8956
    & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_HI, { 0x1a03700 }
8957
  },
8958
/* exts.b ${Dsp-24-u16},[$Dst32AnPrefixed] */
8959
  {
8960
    { 0, 0, 0, 0 },
8961
    { { MNEM, ' ', OP (DSP_24_U16), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
8962
    & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_HI, { 0x1b03700 }
8963
  },
8964
/* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
8965
  {
8966
    { 0, 0, 0, 0 },
8967
    { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
8968
    & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a20700 }
8969
  },
8970
/* exts.b ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
8971
  {
8972
    { 0, 0, 0, 0 },
8973
    { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
8974
    & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a22700 }
8975
  },
8976
/* exts.b ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
8977
  {
8978
    { 0, 0, 0, 0 },
8979
    { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
8980
    & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a23700 }
8981
  },
8982
/* exts.b ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
8983
  {
8984
    { 0, 0, 0, 0 },
8985
    { { MNEM, ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
8986
    & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_An_relative_Prefixed_HI, { 0x1b23700 }
8987
  },
8988
/* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
8989
  {
8990
    { 0, 0, 0, 0 },
8991
    { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
8992
    & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a40700 }
8993
  },
8994
/* exts.b ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
8995
  {
8996
    { 0, 0, 0, 0 },
8997
    { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
8998
    & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a42700 }
8999
  },
9000
/* exts.b ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
9001
  {
9002
    { 0, 0, 0, 0 },
9003
    { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
9004
    & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a43700 }
9005
  },
9006
/* exts.b ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
9007
  {
9008
    { 0, 0, 0, 0 },
9009
    { { MNEM, ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
9010
    & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_An_relative_Prefixed_HI, { 0x1b43700 }
9011
  },
9012
/* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
9013
  {
9014
    { 0, 0, 0, 0 },
9015
    { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
9016
    & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a60700 }
9017
  },
9018
/* exts.b ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
9019
  {
9020
    { 0, 0, 0, 0 },
9021
    { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
9022
    & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a62700 }
9023
  },
9024
/* exts.b ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
9025
  {
9026
    { 0, 0, 0, 0 },
9027
    { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
9028
    & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a63700 }
9029
  },
9030
/* exts.b ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
9031
  {
9032
    { 0, 0, 0, 0 },
9033
    { { MNEM, ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
9034
    & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_An_relative_Prefixed_HI, { 0x1b63700 }
9035
  },
9036
/* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
9037
  {
9038
    { 0, 0, 0, 0 },
9039
    { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
9040
    & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a28700 }
9041
  },
9042
/* exts.b ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
9043
  {
9044
    { 0, 0, 0, 0 },
9045
    { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
9046
    & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a2a700 }
9047
  },
9048
/* exts.b ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
9049
  {
9050
    { 0, 0, 0, 0 },
9051
    { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
9052
    & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a2b700 }
9053
  },
9054
/* exts.b ${Dsp-24-u16},${Dsp-40-u8}[sb] */
9055
  {
9056
    { 0, 0, 0, 0 },
9057
    { { MNEM, ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
9058
    & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1b2b700 }
9059
  },
9060
/* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
9061
  {
9062
    { 0, 0, 0, 0 },
9063
    { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
9064
    & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a48700 }
9065
  },
9066
/* exts.b ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
9067
  {
9068
    { 0, 0, 0, 0 },
9069
    { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
9070
    & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a4a700 }
9071
  },
9072
/* exts.b ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
9073
  {
9074
    { 0, 0, 0, 0 },
9075
    { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
9076
    & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a4b700 }
9077
  },
9078
/* exts.b ${Dsp-24-u16},${Dsp-40-u16}[sb] */
9079
  {
9080
    { 0, 0, 0, 0 },
9081
    { { MNEM, ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
9082
    & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1b4b700 }
9083
  },
9084
/* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
9085
  {
9086
    { 0, 0, 0, 0 },
9087
    { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
9088
    & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a2c700 }
9089
  },
9090
/* exts.b ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
9091
  {
9092
    { 0, 0, 0, 0 },
9093
    { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
9094
    & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a2e700 }
9095
  },
9096
/* exts.b ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
9097
  {
9098
    { 0, 0, 0, 0 },
9099
    { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
9100
    & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a2f700 }
9101
  },
9102
/* exts.b ${Dsp-24-u16},${Dsp-40-s8}[fb] */
9103
  {
9104
    { 0, 0, 0, 0 },
9105
    { { MNEM, ' ', OP (DSP_24_U16), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
9106
    & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1b2f700 }
9107
  },
9108
/* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
9109
  {
9110
    { 0, 0, 0, 0 },
9111
    { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
9112
    & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a4c700 }
9113
  },
9114
/* exts.b ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
9115
  {
9116
    { 0, 0, 0, 0 },
9117
    { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
9118
    & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a4e700 }
9119
  },
9120
/* exts.b ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
9121
  {
9122
    { 0, 0, 0, 0 },
9123
    { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
9124
    & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a4f700 }
9125
  },
9126
/* exts.b ${Dsp-24-u16},${Dsp-40-s16}[fb] */
9127
  {
9128
    { 0, 0, 0, 0 },
9129
    { { MNEM, ' ', OP (DSP_24_U16), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
9130
    & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1b4f700 }
9131
  },
9132
/* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
9133
  {
9134
    { 0, 0, 0, 0 },
9135
    { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
9136
    & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_HI, { 0x1a6c700 }
9137
  },
9138
/* exts.b ${Dsp-24-u16}[sb],${Dsp-40-u16} */
9139
  {
9140
    { 0, 0, 0, 0 },
9141
    { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), 0 } },
9142
    & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_HI, { 0x1a6e700 }
9143
  },
9144
/* exts.b ${Dsp-24-s16}[fb],${Dsp-40-u16} */
9145
  {
9146
    { 0, 0, 0, 0 },
9147
    { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), 0 } },
9148
    & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_HI, { 0x1a6f700 }
9149
  },
9150
/* exts.b ${Dsp-24-u16},${Dsp-40-u16} */
9151
  {
9152
    { 0, 0, 0, 0 },
9153
    { { MNEM, ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), 0 } },
9154
    & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_absolute_Prefixed_HI, { 0x1b6f700 }
9155
  },
9156
/* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
9157
  {
9158
    { 0, 0, 0, 0 },
9159
    { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
9160
    & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_HI, { 0x1a68700 }
9161
  },
9162
/* exts.b ${Dsp-24-u16}[sb],${Dsp-40-u24} */
9163
  {
9164
    { 0, 0, 0, 0 },
9165
    { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), 0 } },
9166
    & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_HI, { 0x1a6a700 }
9167
  },
9168
/* exts.b ${Dsp-24-s16}[fb],${Dsp-40-u24} */
9169
  {
9170
    { 0, 0, 0, 0 },
9171
    { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), 0 } },
9172
    & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_HI, { 0x1a6b700 }
9173
  },
9174
/* exts.b ${Dsp-24-u16},${Dsp-40-u24} */
9175
  {
9176
    { 0, 0, 0, 0 },
9177
    { { MNEM, ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), 0 } },
9178
    & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_absolute_Prefixed_HI, { 0x1b6b700 }
9179
  },
9180
/* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
9181
  {
9182
    { 0, 0, 0, 0 },
9183
    { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
9184
    & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_HI, { 0x1b80700 }
9185
  },
9186
/* exts.b ${Dsp-24-u24},$Dst32RnPrefixedHI */
9187
  {
9188
    { 0, 0, 0, 0 },
9189
    { { MNEM, ' ', OP (DSP_24_U24), ',', OP (DST32RNPREFIXEDHI), 0 } },
9190
    & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_HI, { 0x1b82700 }
9191
  },
9192
/* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
9193
  {
9194
    { 0, 0, 0, 0 },
9195
    { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
9196
    & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_HI, { 0x1b08700 }
9197
  },
9198
/* exts.b ${Dsp-24-u24},$Dst32AnPrefixedHI */
9199
  {
9200
    { 0, 0, 0, 0 },
9201
    { { MNEM, ' ', OP (DSP_24_U24), ',', OP (DST32ANPREFIXEDHI), 0 } },
9202
    & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_direct_Prefixed_HI, { 0x1b0a700 }
9203
  },
9204
/* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
9205
  {
9206
    { 0, 0, 0, 0 },
9207
    { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
9208
    & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_HI, { 0x1b00700 }
9209
  },
9210
/* exts.b ${Dsp-24-u24},[$Dst32AnPrefixed] */
9211
  {
9212
    { 0, 0, 0, 0 },
9213
    { { MNEM, ' ', OP (DSP_24_U24), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
9214
    & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_HI, { 0x1b02700 }
9215
  },
9216
/* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
9217
  {
9218
    { 0, 0, 0, 0 },
9219
    { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
9220
    & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b20700 }
9221
  },
9222
/* exts.b ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
9223
  {
9224
    { 0, 0, 0, 0 },
9225
    { { MNEM, ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
9226
    & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b22700 }
9227
  },
9228
/* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
9229
  {
9230
    { 0, 0, 0, 0 },
9231
    { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
9232
    & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b40700 }
9233
  },
9234
/* exts.b ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
9235
  {
9236
    { 0, 0, 0, 0 },
9237
    { { MNEM, ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
9238
    & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b42700 }
9239
  },
9240
/* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
9241
  {
9242
    { 0, 0, 0, 0 },
9243
    { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
9244
    & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b60700 }
9245
  },
9246
/* exts.b ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
9247
  {
9248
    { 0, 0, 0, 0 },
9249
    { { MNEM, ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
9250
    & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b62700 }
9251
  },
9252
/* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
9253
  {
9254
    { 0, 0, 0, 0 },
9255
    { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
9256
    & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b28700 }
9257
  },
9258
/* exts.b ${Dsp-24-u24},${Dsp-48-u8}[sb] */
9259
  {
9260
    { 0, 0, 0, 0 },
9261
    { { MNEM, ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
9262
    & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b2a700 }
9263
  },
9264
/* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
9265
  {
9266
    { 0, 0, 0, 0 },
9267
    { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
9268
    & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b48700 }
9269
  },
9270
/* exts.b ${Dsp-24-u24},${Dsp-48-u16}[sb] */
9271
  {
9272
    { 0, 0, 0, 0 },
9273
    { { MNEM, ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
9274
    & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b4a700 }
9275
  },
9276
/* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
9277
  {
9278
    { 0, 0, 0, 0 },
9279
    { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
9280
    & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b2c700 }
9281
  },
9282
/* exts.b ${Dsp-24-u24},${Dsp-48-s8}[fb] */
9283
  {
9284
    { 0, 0, 0, 0 },
9285
    { { MNEM, ' ', OP (DSP_24_U24), ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
9286
    & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b2e700 }
9287
  },
9288
/* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
9289
  {
9290
    { 0, 0, 0, 0 },
9291
    { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
9292
    & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b4c700 }
9293
  },
9294
/* exts.b ${Dsp-24-u24},${Dsp-48-s16}[fb] */
9295
  {
9296
    { 0, 0, 0, 0 },
9297
    { { MNEM, ' ', OP (DSP_24_U24), ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
9298
    & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b4e700 }
9299
  },
9300
/* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
9301
  {
9302
    { 0, 0, 0, 0 },
9303
    { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), 0 } },
9304
    & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_absolute_Prefixed_HI, { 0x1b6c700 }
9305
  },
9306
/* exts.b ${Dsp-24-u24},${Dsp-48-u16} */
9307
  {
9308
    { 0, 0, 0, 0 },
9309
    { { MNEM, ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), 0 } },
9310
    & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_absolute_Prefixed_HI, { 0x1b6e700 }
9311
  },
9312
/* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
9313
  {
9314
    { 0, 0, 0, 0 },
9315
    { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), 0 } },
9316
    & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_absolute_Prefixed_HI, { 0x1b68700 }
9317
  },
9318
/* exts.b ${Dsp-24-u24},${Dsp-48-u24} */
9319
  {
9320
    { 0, 0, 0, 0 },
9321
    { { MNEM, ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), 0 } },
9322
    & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_absolute_Prefixed_HI, { 0x1b6a700 }
9323
  },
9324
/* exts.b $Src32RnPrefixedQI,$Dst32RnPrefixedHI */
9325
  {
9326
    { 0, 0, 0, 0 },
9327
    { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32RNPREFIXEDHI), 0 } },
9328
    & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_HI, { 0x1c807 }
9329
  },
9330
/* exts.b [$Src32AnPrefixed],$Dst32RnPrefixedHI */
9331
  {
9332
    { 0, 0, 0, 0 },
9333
    { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
9334
    & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_Rn_direct_Prefixed_HI, { 0x18807 }
9335
  },
9336
/* exts.b $Src32RnPrefixedQI,$Dst32AnPrefixedHI */
9337
  {
9338
    { 0, 0, 0, 0 },
9339
    { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32ANPREFIXEDHI), 0 } },
9340
    & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_direct_Prefixed_HI, { 0x1c087 }
9341
  },
9342
/* exts.b [$Src32AnPrefixed],$Dst32AnPrefixedHI */
9343
  {
9344
    { 0, 0, 0, 0 },
9345
    { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
9346
    & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_direct_Prefixed_HI, { 0x18087 }
9347
  },
9348
/* exts.b $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
9349
  {
9350
    { 0, 0, 0, 0 },
9351
    { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
9352
    & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_indirect_Prefixed_HI, { 0x1c007 }
9353
  },
9354
/* exts.b [$Src32AnPrefixed],[$Dst32AnPrefixed] */
9355
  {
9356
    { 0, 0, 0, 0 },
9357
    { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
9358
    & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_indirect_Prefixed_HI, { 0x18007 }
9359
  },
9360
/* exts.b $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
9361
  {
9362
    { 0, 0, 0, 0 },
9363
    { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
9364
    & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_HI, { 0x1c20700 }
9365
  },
9366
/* exts.b [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
9367
  {
9368
    { 0, 0, 0, 0 },
9369
    { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
9370
    & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_An_relative_Prefixed_HI, { 0x1820700 }
9371
  },
9372
/* exts.b $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
9373
  {
9374
    { 0, 0, 0, 0 },
9375
    { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
9376
    & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_HI, { 0x1c40700 }
9377
  },
9378
/* exts.b [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
9379
  {
9380
    { 0, 0, 0, 0 },
9381
    { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
9382
    & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_An_relative_Prefixed_HI, { 0x1840700 }
9383
  },
9384
/* exts.b $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
9385
  {
9386
    { 0, 0, 0, 0 },
9387
    { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
9388
    & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_HI, { 0x1c60700 }
9389
  },
9390
/* exts.b [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
9391
  {
9392
    { 0, 0, 0, 0 },
9393
    { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
9394
    & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_An_relative_Prefixed_HI, { 0x1860700 }
9395
  },
9396
/* exts.b $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
9397
  {
9398
    { 0, 0, 0, 0 },
9399
    { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
9400
    & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1c28700 }
9401
  },
9402
/* exts.b [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
9403
  {
9404
    { 0, 0, 0, 0 },
9405
    { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
9406
    & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1828700 }
9407
  },
9408
/* exts.b $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
9409
  {
9410
    { 0, 0, 0, 0 },
9411
    { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
9412
    & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1c48700 }
9413
  },
9414
/* exts.b [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
9415
  {
9416
    { 0, 0, 0, 0 },
9417
    { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
9418
    & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1848700 }
9419
  },
9420
/* exts.b $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
9421
  {
9422
    { 0, 0, 0, 0 },
9423
    { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
9424
    & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_HI, { 0x1c2c700 }
9425
  },
9426
/* exts.b [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
9427
  {
9428
    { 0, 0, 0, 0 },
9429
    { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
9430
    & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_HI, { 0x182c700 }
9431
  },
9432
/* exts.b $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
9433
  {
9434
    { 0, 0, 0, 0 },
9435
    { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
9436
    & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_HI, { 0x1c4c700 }
9437
  },
9438
/* exts.b [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
9439
  {
9440
    { 0, 0, 0, 0 },
9441
    { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
9442
    & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_HI, { 0x184c700 }
9443
  },
9444
/* exts.b $Src32RnPrefixedQI,${Dsp-24-u16} */
9445
  {
9446
    { 0, 0, 0, 0 },
9447
    { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), 0 } },
9448
    & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_HI, { 0x1c6c700 }
9449
  },
9450
/* exts.b [$Src32AnPrefixed],${Dsp-24-u16} */
9451
  {
9452
    { 0, 0, 0, 0 },
9453
    { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
9454
    & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_absolute_Prefixed_HI, { 0x186c700 }
9455
  },
9456
/* exts.b $Src32RnPrefixedQI,${Dsp-24-u24} */
9457
  {
9458
    { 0, 0, 0, 0 },
9459
    { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), 0 } },
9460
    & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_HI, { 0x1c68700 }
9461
  },
9462
/* exts.b [$Src32AnPrefixed],${Dsp-24-u24} */
9463
  {
9464
    { 0, 0, 0, 0 },
9465
    { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
9466
    & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_absolute_Prefixed_HI, { 0x1868700 }
9467
  },
9468
/* exts.w $Dst32RnExtUnprefixedHI */
9469
  {
9470
    { 0, 0, 0, 0 },
9471
    { { MNEM, ' ', OP (DST32RNEXTUNPREFIXEDHI), 0 } },
9472
    & ifmt_exts32_w_16_ExtUnprefixed_dst32_Rn_direct_ExtUnprefixed_HI, { 0xc99e }
9473
  },
9474
/* exts.w $Dst32AnUnprefixedSI */
9475
  {
9476
    { 0, 0, 0, 0 },
9477
    { { MNEM, ' ', OP (DST32ANUNPREFIXEDSI), 0 } },
9478
    & ifmt_exts32_w_16_ExtUnprefixed_dst32_An_direct_Unprefixed_SI, { 0xc19e }
9479
  },
9480
/* exts.w [$Dst32AnExtUnprefixed] */
9481
  {
9482
    { 0, 0, 0, 0 },
9483
    { { MNEM, ' ', '[', OP (DST32ANEXTUNPREFIXED), ']', 0 } },
9484
    & ifmt_exts32_w_16_ExtUnprefixed_dst32_An_indirect_ExtUnprefixed_HI, { 0xc11e }
9485
  },
9486
/* exts.w ${Dsp-16-u8}[$Dst32AnExtUnprefixed] */
9487
  {
9488
    { 0, 0, 0, 0 },
9489
    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANEXTUNPREFIXED), ']', 0 } },
9490
    & ifmt_exts32_w_16_ExtUnprefixed_dst32_16_8_An_relative_ExtUnprefixed_HI, { 0xc31e00 }
9491
  },
9492
/* exts.w ${Dsp-16-u16}[$Dst32AnExtUnprefixed] */
9493
  {
9494
    { 0, 0, 0, 0 },
9495
    { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANEXTUNPREFIXED), ']', 0 } },
9496
    & ifmt_exts32_w_16_ExtUnprefixed_dst32_16_16_An_relative_ExtUnprefixed_HI, { 0xc51e0000 }
9497
  },
9498
/* exts.w ${Dsp-16-u24}[$Dst32AnExtUnprefixed] */
9499
  {
9500
    { 0, 0, 0, 0 },
9501
    { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANEXTUNPREFIXED), ']', 0 } },
9502
    & ifmt_exts32_w_16_ExtUnprefixed_dst32_16_24_An_relative_ExtUnprefixed_HI, { 0xc71e0000 }
9503
  },
9504
/* exts.w ${Dsp-16-u8}[sb] */
9505
  {
9506
    { 0, 0, 0, 0 },
9507
    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
9508
    & ifmt_exts32_w_16_ExtUnprefixed_dst32_16_8_SB_relative_ExtUnprefixed_HI, { 0xc39e00 }
9509
  },
9510
/* exts.w ${Dsp-16-u16}[sb] */
9511
  {
9512
    { 0, 0, 0, 0 },
9513
    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
9514
    & ifmt_exts32_w_16_ExtUnprefixed_dst32_16_16_SB_relative_ExtUnprefixed_HI, { 0xc59e0000 }
9515
  },
9516
/* exts.w ${Dsp-16-s8}[fb] */
9517
  {
9518
    { 0, 0, 0, 0 },
9519
    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
9520
    & ifmt_exts32_w_16_ExtUnprefixed_dst32_16_8_FB_relative_ExtUnprefixed_HI, { 0xc3de00 }
9521
  },
9522
/* exts.w ${Dsp-16-s16}[fb] */
9523
  {
9524
    { 0, 0, 0, 0 },
9525
    { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
9526
    & ifmt_exts32_w_16_ExtUnprefixed_dst32_16_16_FB_relative_ExtUnprefixed_HI, { 0xc5de0000 }
9527
  },
9528
/* exts.w ${Dsp-16-u16} */
9529
  {
9530
    { 0, 0, 0, 0 },
9531
    { { MNEM, ' ', OP (DSP_16_U16), 0 } },
9532
    & ifmt_exts32_w_16_ExtUnprefixed_dst32_16_16_absolute_ExtUnprefixed_HI, { 0xc7de0000 }
9533
  },
9534
/* exts.w ${Dsp-16-u24} */
9535
  {
9536
    { 0, 0, 0, 0 },
9537
    { { MNEM, ' ', OP (DSP_16_U24), 0 } },
9538
    & ifmt_exts32_w_16_ExtUnprefixed_dst32_16_24_absolute_ExtUnprefixed_HI, { 0xc79e0000 }
9539
  },
9540
/* exts.b $Dst32RnExtUnprefixedQI */
9541
  {
9542
    { 0, 0, 0, 0 },
9543
    { { MNEM, ' ', OP (DST32RNEXTUNPREFIXEDQI), 0 } },
9544
    & ifmt_exts32_b_16_ExtUnprefixed_dst32_Rn_direct_ExtUnprefixed_QI, { 0xc89e }
9545
  },
9546
/* exts.b $Dst32AnUnprefixedHI */
9547
  {
9548
    { 0, 0, 0, 0 },
9549
    { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } },
9550
    & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xc09e }
9551
  },
9552
/* exts.b [$Dst32AnExtUnprefixed] */
9553
  {
9554
    { 0, 0, 0, 0 },
9555
    { { MNEM, ' ', '[', OP (DST32ANEXTUNPREFIXED), ']', 0 } },
9556
    & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_indirect_ExtUnprefixed_QI, { 0xc01e }
9557
  },
9558
/* exts.b ${Dsp-16-u8}[$Dst32AnExtUnprefixed] */
9559
  {
9560
    { 0, 0, 0, 0 },
9561
    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANEXTUNPREFIXED), ']', 0 } },
9562
    & ifmt_exts32_b_16_ExtUnprefixed_dst32_16_8_An_relative_ExtUnprefixed_QI, { 0xc21e00 }
9563
  },
9564
/* exts.b ${Dsp-16-u16}[$Dst32AnExtUnprefixed] */
9565
  {
9566
    { 0, 0, 0, 0 },
9567
    { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANEXTUNPREFIXED), ']', 0 } },
9568
    & ifmt_exts32_b_16_ExtUnprefixed_dst32_16_16_An_relative_ExtUnprefixed_QI, { 0xc41e0000 }
9569
  },
9570
/* exts.b ${Dsp-16-u24}[$Dst32AnExtUnprefixed] */
9571
  {
9572
    { 0, 0, 0, 0 },
9573
    { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANEXTUNPREFIXED), ']', 0 } },
9574
    & ifmt_exts32_b_16_ExtUnprefixed_dst32_16_24_An_relative_ExtUnprefixed_QI, { 0xc61e0000 }
9575
  },
9576
/* exts.b ${Dsp-16-u8}[sb] */
9577
  {
9578
    { 0, 0, 0, 0 },
9579
    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
9580
    & ifmt_exts32_b_16_ExtUnprefixed_dst32_16_8_SB_relative_ExtUnprefixed_QI, { 0xc29e00 }
9581
  },
9582
/* exts.b ${Dsp-16-u16}[sb] */
9583
  {
9584
    { 0, 0, 0, 0 },
9585
    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
9586
    & ifmt_exts32_b_16_ExtUnprefixed_dst32_16_16_SB_relative_ExtUnprefixed_QI, { 0xc49e0000 }
9587
  },
9588
/* exts.b ${Dsp-16-s8}[fb] */
9589
  {
9590
    { 0, 0, 0, 0 },
9591
    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
9592
    & ifmt_exts32_b_16_ExtUnprefixed_dst32_16_8_FB_relative_ExtUnprefixed_QI, { 0xc2de00 }
9593
  },
9594
/* exts.b ${Dsp-16-s16}[fb] */
9595
  {
9596
    { 0, 0, 0, 0 },
9597
    { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
9598
    & ifmt_exts32_b_16_ExtUnprefixed_dst32_16_16_FB_relative_ExtUnprefixed_QI, { 0xc4de0000 }
9599
  },
9600
/* exts.b ${Dsp-16-u16} */
9601
  {
9602
    { 0, 0, 0, 0 },
9603
    { { MNEM, ' ', OP (DSP_16_U16), 0 } },
9604
    & ifmt_exts32_b_16_ExtUnprefixed_dst32_16_16_absolute_ExtUnprefixed_QI, { 0xc6de0000 }
9605
  },
9606
/* exts.b ${Dsp-16-u24} */
9607
  {
9608
    { 0, 0, 0, 0 },
9609
    { { MNEM, ' ', OP (DSP_16_U24), 0 } },
9610
    & ifmt_exts32_b_16_ExtUnprefixed_dst32_16_24_absolute_ExtUnprefixed_QI, { 0xc69e0000 }
9611
  },
9612
/* exts.b $Dst16RnExtQI */
9613
  {
9614
    { 0, 0, 0, 0 },
9615
    { { MNEM, ' ', OP (DST16RNEXTQI), 0 } },
9616
    & ifmt_exts16_b_16_Ext_dst16_Rn_direct_Ext_QI, { 0x7c60 }
9617
  },
9618
/* exts.b [$Dst16An] */
9619
  {
9620
    { 0, 0, 0, 0 },
9621
    { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } },
9622
    & ifmt_exts16_b_16_Ext_dst16_An_indirect_Ext_QI, { 0x7c66 }
9623
  },
9624
/* exts.b ${Dsp-16-u8}[$Dst16An] */
9625
  {
9626
    { 0, 0, 0, 0 },
9627
    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
9628
    & ifmt_exts16_b_16_Ext_dst16_16_8_An_relative_Ext_QI, { 0x7c6800 }
9629
  },
9630
/* exts.b ${Dsp-16-u16}[$Dst16An] */
9631
  {
9632
    { 0, 0, 0, 0 },
9633
    { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
9634
    & ifmt_exts16_b_16_Ext_dst16_16_16_An_relative_Ext_QI, { 0x7c6c0000 }
9635
  },
9636
/* exts.b ${Dsp-16-u8}[sb] */
9637
  {
9638
    { 0, 0, 0, 0 },
9639
    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
9640
    & ifmt_exts16_b_16_Ext_dst16_16_8_SB_relative_Ext_QI, { 0x7c6a00 }
9641
  },
9642
/* exts.b ${Dsp-16-u16}[sb] */
9643
  {
9644
    { 0, 0, 0, 0 },
9645
    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
9646
    & ifmt_exts16_b_16_Ext_dst16_16_16_SB_relative_Ext_QI, { 0x7c6e0000 }
9647
  },
9648
/* exts.b ${Dsp-16-s8}[fb] */
9649
  {
9650
    { 0, 0, 0, 0 },
9651
    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
9652
    & ifmt_exts16_b_16_Ext_dst16_16_8_FB_relative_Ext_QI, { 0x7c6b00 }
9653
  },
9654
/* exts.b ${Dsp-16-u16} */
9655
  {
9656
    { 0, 0, 0, 0 },
9657
    { { MNEM, ' ', OP (DSP_16_U16), 0 } },
9658
    & ifmt_exts16_b_16_Ext_dst16_16_16_absolute_Ext_QI, { 0x7c6f0000 }
9659
  },
9660
/* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
9661
  {
9662
    { 0, 0, 0, 0 },
9663
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
9664
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x990900 }
9665
  },
9666
/* xor.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */
9667
  {
9668
    { 0, 0, 0, 0 },
9669
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
9670
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x992900 }
9671
  },
9672
/* xor.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */
9673
  {
9674
    { 0, 0, 0, 0 },
9675
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
9676
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x993900 }
9677
  },
9678
/* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
9679
  {
9680
    { 0, 0, 0, 0 },
9681
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
9682
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x918900 }
9683
  },
9684
/* xor.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */
9685
  {
9686
    { 0, 0, 0, 0 },
9687
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
9688
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x91a900 }
9689
  },
9690
/* xor.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */
9691
  {
9692
    { 0, 0, 0, 0 },
9693
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
9694
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x91b900 }
9695
  },
9696
/* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
9697
  {
9698
    { 0, 0, 0, 0 },
9699
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
9700
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x910900 }
9701
  },
9702
/* xor.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
9703
  {
9704
    { 0, 0, 0, 0 },
9705
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
9706
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x912900 }
9707
  },
9708
/* xor.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
9709
  {
9710
    { 0, 0, 0, 0 },
9711
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
9712
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x913900 }
9713
  },
9714
/* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
9715
  {
9716
    { 0, 0, 0, 0 },
9717
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
9718
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x93090000 }
9719
  },
9720
/* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
9721
  {
9722
    { 0, 0, 0, 0 },
9723
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
9724
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x93290000 }
9725
  },
9726
/* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
9727
  {
9728
    { 0, 0, 0, 0 },
9729
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
9730
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x93390000 }
9731
  },
9732
/* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
9733
  {
9734
    { 0, 0, 0, 0 },
9735
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
9736
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x95090000 }
9737
  },
9738
/* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
9739
  {
9740
    { 0, 0, 0, 0 },
9741
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
9742
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x95290000 }
9743
  },
9744
/* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
9745
  {
9746
    { 0, 0, 0, 0 },
9747
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
9748
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x95390000 }
9749
  },
9750
/* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
9751
  {
9752
    { 0, 0, 0, 0 },
9753
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
9754
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x97090000 }
9755
  },
9756
/* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
9757
  {
9758
    { 0, 0, 0, 0 },
9759
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
9760
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x97290000 }
9761
  },
9762
/* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
9763
  {
9764
    { 0, 0, 0, 0 },
9765
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
9766
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x97390000 }
9767
  },
9768
/* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
9769
  {
9770
    { 0, 0, 0, 0 },
9771
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
9772
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93890000 }
9773
  },
9774
/* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
9775
  {
9776
    { 0, 0, 0, 0 },
9777
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
9778
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93a90000 }
9779
  },
9780
/* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
9781
  {
9782
    { 0, 0, 0, 0 },
9783
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
9784
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93b90000 }
9785
  },
9786
/* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
9787
  {
9788
    { 0, 0, 0, 0 },
9789
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
9790
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95890000 }
9791
  },
9792
/* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
9793
  {
9794
    { 0, 0, 0, 0 },
9795
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
9796
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95a90000 }
9797
  },
9798
/* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
9799
  {
9800
    { 0, 0, 0, 0 },
9801
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
9802
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95b90000 }
9803
  },
9804
/* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
9805
  {
9806
    { 0, 0, 0, 0 },
9807
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
9808
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93c90000 }
9809
  },
9810
/* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
9811
  {
9812
    { 0, 0, 0, 0 },
9813
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
9814
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93e90000 }
9815
  },
9816
/* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
9817
  {
9818
    { 0, 0, 0, 0 },
9819
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
9820
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93f90000 }
9821
  },
9822
/* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
9823
  {
9824
    { 0, 0, 0, 0 },
9825
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
9826
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95c90000 }
9827
  },
9828
/* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
9829
  {
9830
    { 0, 0, 0, 0 },
9831
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
9832
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95e90000 }
9833
  },
9834
/* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
9835
  {
9836
    { 0, 0, 0, 0 },
9837
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
9838
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95f90000 }
9839
  },
9840
/* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
9841
  {
9842
    { 0, 0, 0, 0 },
9843
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
9844
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97c90000 }
9845
  },
9846
/* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
9847
  {
9848
    { 0, 0, 0, 0 },
9849
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
9850
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97e90000 }
9851
  },
9852
/* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
9853
  {
9854
    { 0, 0, 0, 0 },
9855
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
9856
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97f90000 }
9857
  },
9858
/* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
9859
  {
9860
    { 0, 0, 0, 0 },
9861
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
9862
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97890000 }
9863
  },
9864
/* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
9865
  {
9866
    { 0, 0, 0, 0 },
9867
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } },
9868
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97a90000 }
9869
  },
9870
/* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
9871
  {
9872
    { 0, 0, 0, 0 },
9873
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } },
9874
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97b90000 }
9875
  },
9876
/* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
9877
  {
9878
    { 0, 0, 0, 0 },
9879
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
9880
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa9090000 }
9881
  },
9882
/* xor.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */
9883
  {
9884
    { 0, 0, 0, 0 },
9885
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
9886
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa9290000 }
9887
  },
9888
/* xor.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */
9889
  {
9890
    { 0, 0, 0, 0 },
9891
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
9892
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa9390000 }
9893
  },
9894
/* xor.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */
9895
  {
9896
    { 0, 0, 0, 0 },
9897
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
9898
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb9390000 }
9899
  },
9900
/* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
9901
  {
9902
    { 0, 0, 0, 0 },
9903
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
9904
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1890000 }
9905
  },
9906
/* xor.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */
9907
  {
9908
    { 0, 0, 0, 0 },
9909
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
9910
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1a90000 }
9911
  },
9912
/* xor.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */
9913
  {
9914
    { 0, 0, 0, 0 },
9915
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
9916
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1b90000 }
9917
  },
9918
/* xor.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */
9919
  {
9920
    { 0, 0, 0, 0 },
9921
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
9922
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1b90000 }
9923
  },
9924
/* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
9925
  {
9926
    { 0, 0, 0, 0 },
9927
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
9928
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa1090000 }
9929
  },
9930
/* xor.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
9931
  {
9932
    { 0, 0, 0, 0 },
9933
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
9934
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa1290000 }
9935
  },
9936
/* xor.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
9937
  {
9938
    { 0, 0, 0, 0 },
9939
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
9940
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa1390000 }
9941
  },
9942
/* xor.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
9943
  {
9944
    { 0, 0, 0, 0 },
9945
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
9946
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb1390000 }
9947
  },
9948
/* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
9949
  {
9950
    { 0, 0, 0, 0 },
9951
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
9952
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa3090000 }
9953
  },
9954
/* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
9955
  {
9956
    { 0, 0, 0, 0 },
9957
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
9958
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa3290000 }
9959
  },
9960
/* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
9961
  {
9962
    { 0, 0, 0, 0 },
9963
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
9964
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa3390000 }
9965
  },
9966
/* xor.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
9967
  {
9968
    { 0, 0, 0, 0 },
9969
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
9970
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xb3390000 }
9971
  },
9972
/* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
9973
  {
9974
    { 0, 0, 0, 0 },
9975
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
9976
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa5090000 }
9977
  },
9978
/* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
9979
  {
9980
    { 0, 0, 0, 0 },
9981
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
9982
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa5290000 }
9983
  },
9984
/* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
9985
  {
9986
    { 0, 0, 0, 0 },
9987
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
9988
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa5390000 }
9989
  },
9990
/* xor.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
9991
  {
9992
    { 0, 0, 0, 0 },
9993
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
9994
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xb5390000 }
9995
  },
9996
/* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
9997
  {
9998
    { 0, 0, 0, 0 },
9999
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10000
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa7090000 }
10001
  },
10002
/* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
10003
  {
10004
    { 0, 0, 0, 0 },
10005
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10006
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa7290000 }
10007
  },
10008
/* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
10009
  {
10010
    { 0, 0, 0, 0 },
10011
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10012
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa7390000 }
10013
  },
10014
/* xor.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
10015
  {
10016
    { 0, 0, 0, 0 },
10017
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10018
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xb7390000 }
10019
  },
10020
/* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
10021
  {
10022
    { 0, 0, 0, 0 },
10023
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
10024
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3890000 }
10025
  },
10026
/* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
10027
  {
10028
    { 0, 0, 0, 0 },
10029
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
10030
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3a90000 }
10031
  },
10032
/* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
10033
  {
10034
    { 0, 0, 0, 0 },
10035
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
10036
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3b90000 }
10037
  },
10038
/* xor.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
10039
  {
10040
    { 0, 0, 0, 0 },
10041
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
10042
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xb3b90000 }
10043
  },
10044
/* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
10045
  {
10046
    { 0, 0, 0, 0 },
10047
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
10048
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5890000 }
10049
  },
10050
/* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
10051
  {
10052
    { 0, 0, 0, 0 },
10053
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
10054
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5a90000 }
10055
  },
10056
/* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
10057
  {
10058
    { 0, 0, 0, 0 },
10059
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
10060
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5b90000 }
10061
  },
10062
/* xor.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
10063
  {
10064
    { 0, 0, 0, 0 },
10065
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
10066
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xb5b90000 }
10067
  },
10068
/* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
10069
  {
10070
    { 0, 0, 0, 0 },
10071
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
10072
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3c90000 }
10073
  },
10074
/* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
10075
  {
10076
    { 0, 0, 0, 0 },
10077
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
10078
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3e90000 }
10079
  },
10080
/* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
10081
  {
10082
    { 0, 0, 0, 0 },
10083
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
10084
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3f90000 }
10085
  },
10086
/* xor.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
10087
  {
10088
    { 0, 0, 0, 0 },
10089
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
10090
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xb3f90000 }
10091
  },
10092
/* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
10093
  {
10094
    { 0, 0, 0, 0 },
10095
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
10096
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5c90000 }
10097
  },
10098
/* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
10099
  {
10100
    { 0, 0, 0, 0 },
10101
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
10102
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5e90000 }
10103
  },
10104
/* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
10105
  {
10106
    { 0, 0, 0, 0 },
10107
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
10108
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5f90000 }
10109
  },
10110
/* xor.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
10111
  {
10112
    { 0, 0, 0, 0 },
10113
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
10114
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xb5f90000 }
10115
  },
10116
/* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
10117
  {
10118
    { 0, 0, 0, 0 },
10119
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
10120
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7c90000 }
10121
  },
10122
/* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
10123
  {
10124
    { 0, 0, 0, 0 },
10125
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
10126
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7e90000 }
10127
  },
10128
/* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
10129
  {
10130
    { 0, 0, 0, 0 },
10131
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
10132
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7f90000 }
10133
  },
10134
/* xor.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
10135
  {
10136
    { 0, 0, 0, 0 },
10137
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
10138
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xb7f90000 }
10139
  },
10140
/* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
10141
  {
10142
    { 0, 0, 0, 0 },
10143
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
10144
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7890000 }
10145
  },
10146
/* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
10147
  {
10148
    { 0, 0, 0, 0 },
10149
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
10150
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7a90000 }
10151
  },
10152
/* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
10153
  {
10154
    { 0, 0, 0, 0 },
10155
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
10156
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7b90000 }
10157
  },
10158
/* xor.w${G} ${Dsp-16-u16},${Dsp-32-u24} */
10159
  {
10160
    { 0, 0, 0, 0 },
10161
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } },
10162
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xb7b90000 }
10163
  },
10164
/* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
10165
  {
10166
    { 0, 0, 0, 0 },
10167
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
10168
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb9090000 }
10169
  },
10170
/* xor.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */
10171
  {
10172
    { 0, 0, 0, 0 },
10173
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
10174
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb9290000 }
10175
  },
10176
/* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
10177
  {
10178
    { 0, 0, 0, 0 },
10179
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
10180
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1890000 }
10181
  },
10182
/* xor.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */
10183
  {
10184
    { 0, 0, 0, 0 },
10185
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
10186
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1a90000 }
10187
  },
10188
/* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
10189
  {
10190
    { 0, 0, 0, 0 },
10191
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10192
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb1090000 }
10193
  },
10194
/* xor.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
10195
  {
10196
    { 0, 0, 0, 0 },
10197
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10198
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb1290000 }
10199
  },
10200
/* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
10201
  {
10202
    { 0, 0, 0, 0 },
10203
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10204
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_An_relative_Unprefixed_HI, { 0xb3090000 }
10205
  },
10206
/* xor.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
10207
  {
10208
    { 0, 0, 0, 0 },
10209
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10210
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_An_relative_Unprefixed_HI, { 0xb3290000 }
10211
  },
10212
/* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
10213
  {
10214
    { 0, 0, 0, 0 },
10215
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10216
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_An_relative_Unprefixed_HI, { 0xb5090000 }
10217
  },
10218
/* xor.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
10219
  {
10220
    { 0, 0, 0, 0 },
10221
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10222
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_An_relative_Unprefixed_HI, { 0xb5290000 }
10223
  },
10224
/* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
10225
  {
10226
    { 0, 0, 0, 0 },
10227
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10228
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_24_An_relative_Unprefixed_HI, { 0xb7090000 }
10229
  },
10230
/* xor.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
10231
  {
10232
    { 0, 0, 0, 0 },
10233
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10234
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_24_An_relative_Unprefixed_HI, { 0xb7290000 }
10235
  },
10236
/* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
10237
  {
10238
    { 0, 0, 0, 0 },
10239
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
10240
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_SB_relative_Unprefixed_HI, { 0xb3890000 }
10241
  },
10242
/* xor.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
10243
  {
10244
    { 0, 0, 0, 0 },
10245
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
10246
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_SB_relative_Unprefixed_HI, { 0xb3a90000 }
10247
  },
10248
/* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
10249
  {
10250
    { 0, 0, 0, 0 },
10251
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
10252
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_SB_relative_Unprefixed_HI, { 0xb5890000 }
10253
  },
10254
/* xor.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
10255
  {
10256
    { 0, 0, 0, 0 },
10257
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
10258
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_SB_relative_Unprefixed_HI, { 0xb5a90000 }
10259
  },
10260
/* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
10261
  {
10262
    { 0, 0, 0, 0 },
10263
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
10264
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_FB_relative_Unprefixed_HI, { 0xb3c90000 }
10265
  },
10266
/* xor.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
10267
  {
10268
    { 0, 0, 0, 0 },
10269
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
10270
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_FB_relative_Unprefixed_HI, { 0xb3e90000 }
10271
  },
10272
/* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
10273
  {
10274
    { 0, 0, 0, 0 },
10275
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
10276
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_FB_relative_Unprefixed_HI, { 0xb5c90000 }
10277
  },
10278
/* xor.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
10279
  {
10280
    { 0, 0, 0, 0 },
10281
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
10282
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_FB_relative_Unprefixed_HI, { 0xb5e90000 }
10283
  },
10284
/* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
10285
  {
10286
    { 0, 0, 0, 0 },
10287
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
10288
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_absolute_Unprefixed_HI, { 0xb7c90000 }
10289
  },
10290
/* xor.w${G} ${Dsp-16-u24},${Dsp-40-u16} */
10291
  {
10292
    { 0, 0, 0, 0 },
10293
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } },
10294
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_absolute_Unprefixed_HI, { 0xb7e90000 }
10295
  },
10296
/* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
10297
  {
10298
    { 0, 0, 0, 0 },
10299
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
10300
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_24_absolute_Unprefixed_HI, { 0xb7890000 }
10301
  },
10302
/* xor.w${G} ${Dsp-16-u24},${Dsp-40-u24} */
10303
  {
10304
    { 0, 0, 0, 0 },
10305
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } },
10306
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_24_absolute_Unprefixed_HI, { 0xb7a90000 }
10307
  },
10308
/* xor.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */
10309
  {
10310
    { 0, 0, 0, 0 },
10311
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
10312
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xc909 }
10313
  },
10314
/* xor.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */
10315
  {
10316
    { 0, 0, 0, 0 },
10317
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
10318
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x8929 }
10319
  },
10320
/* xor.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
10321
  {
10322
    { 0, 0, 0, 0 },
10323
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
10324
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x8909 }
10325
  },
10326
/* xor.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */
10327
  {
10328
    { 0, 0, 0, 0 },
10329
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
10330
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xc189 }
10331
  },
10332
/* xor.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */
10333
  {
10334
    { 0, 0, 0, 0 },
10335
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
10336
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x81a9 }
10337
  },
10338
/* xor.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
10339
  {
10340
    { 0, 0, 0, 0 },
10341
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
10342
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x8189 }
10343
  },
10344
/* xor.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */
10345
  {
10346
    { 0, 0, 0, 0 },
10347
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10348
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xc109 }
10349
  },
10350
/* xor.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */
10351
  {
10352
    { 0, 0, 0, 0 },
10353
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10354
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x8129 }
10355
  },
10356
/* xor.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
10357
  {
10358
    { 0, 0, 0, 0 },
10359
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10360
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x8109 }
10361
  },
10362
/* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
10363
  {
10364
    { 0, 0, 0, 0 },
10365
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10366
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0xc30900 }
10367
  },
10368
/* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
10369
  {
10370
    { 0, 0, 0, 0 },
10371
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10372
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0x832900 }
10373
  },
10374
/* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
10375
  {
10376
    { 0, 0, 0, 0 },
10377
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10378
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0x830900 }
10379
  },
10380
/* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
10381
  {
10382
    { 0, 0, 0, 0 },
10383
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10384
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0xc5090000 }
10385
  },
10386
/* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
10387
  {
10388
    { 0, 0, 0, 0 },
10389
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10390
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0x85290000 }
10391
  },
10392
/* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
10393
  {
10394
    { 0, 0, 0, 0 },
10395
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10396
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0x85090000 }
10397
  },
10398
/* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
10399
  {
10400
    { 0, 0, 0, 0 },
10401
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10402
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0xc7090000 }
10403
  },
10404
/* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
10405
  {
10406
    { 0, 0, 0, 0 },
10407
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10408
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0x87290000 }
10409
  },
10410
/* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
10411
  {
10412
    { 0, 0, 0, 0 },
10413
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10414
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0x87090000 }
10415
  },
10416
/* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */
10417
  {
10418
    { 0, 0, 0, 0 },
10419
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
10420
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0xc38900 }
10421
  },
10422
/* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */
10423
  {
10424
    { 0, 0, 0, 0 },
10425
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
10426
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0x83a900 }
10427
  },
10428
/* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
10429
  {
10430
    { 0, 0, 0, 0 },
10431
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
10432
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0x838900 }
10433
  },
10434
/* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */
10435
  {
10436
    { 0, 0, 0, 0 },
10437
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
10438
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0xc5890000 }
10439
  },
10440
/* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */
10441
  {
10442
    { 0, 0, 0, 0 },
10443
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
10444
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0x85a90000 }
10445
  },
10446
/* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
10447
  {
10448
    { 0, 0, 0, 0 },
10449
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
10450
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0x85890000 }
10451
  },
10452
/* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */
10453
  {
10454
    { 0, 0, 0, 0 },
10455
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
10456
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0xc3c900 }
10457
  },
10458
/* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */
10459
  {
10460
    { 0, 0, 0, 0 },
10461
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
10462
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83e900 }
10463
  },
10464
/* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
10465
  {
10466
    { 0, 0, 0, 0 },
10467
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
10468
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83c900 }
10469
  },
10470
/* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */
10471
  {
10472
    { 0, 0, 0, 0 },
10473
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
10474
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0xc5c90000 }
10475
  },
10476
/* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */
10477
  {
10478
    { 0, 0, 0, 0 },
10479
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
10480
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85e90000 }
10481
  },
10482
/* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
10483
  {
10484
    { 0, 0, 0, 0 },
10485
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
10486
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85c90000 }
10487
  },
10488
/* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */
10489
  {
10490
    { 0, 0, 0, 0 },
10491
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), 0 } },
10492
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0xc7c90000 }
10493
  },
10494
/* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */
10495
  {
10496
    { 0, 0, 0, 0 },
10497
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), 0 } },
10498
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0x87e90000 }
10499
  },
10500
/* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
10501
  {
10502
    { 0, 0, 0, 0 },
10503
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } },
10504
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0x87c90000 }
10505
  },
10506
/* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */
10507
  {
10508
    { 0, 0, 0, 0 },
10509
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U24), 0 } },
10510
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0xc7890000 }
10511
  },
10512
/* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */
10513
  {
10514
    { 0, 0, 0, 0 },
10515
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U24), 0 } },
10516
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0x87a90000 }
10517
  },
10518
/* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
10519
  {
10520
    { 0, 0, 0, 0 },
10521
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } },
10522
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0x87890000 }
10523
  },
10524
/* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
10525
  {
10526
    { 0, 0, 0, 0 },
10527
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
10528
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x980900 }
10529
  },
10530
/* xor.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */
10531
  {
10532
    { 0, 0, 0, 0 },
10533
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
10534
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x982900 }
10535
  },
10536
/* xor.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */
10537
  {
10538
    { 0, 0, 0, 0 },
10539
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
10540
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x983900 }
10541
  },
10542
/* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
10543
  {
10544
    { 0, 0, 0, 0 },
10545
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
10546
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x908900 }
10547
  },
10548
/* xor.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */
10549
  {
10550
    { 0, 0, 0, 0 },
10551
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
10552
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x90a900 }
10553
  },
10554
/* xor.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */
10555
  {
10556
    { 0, 0, 0, 0 },
10557
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
10558
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x90b900 }
10559
  },
10560
/* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
10561
  {
10562
    { 0, 0, 0, 0 },
10563
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10564
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x900900 }
10565
  },
10566
/* xor.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
10567
  {
10568
    { 0, 0, 0, 0 },
10569
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10570
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x902900 }
10571
  },
10572
/* xor.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
10573
  {
10574
    { 0, 0, 0, 0 },
10575
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10576
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x903900 }
10577
  },
10578
/* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
10579
  {
10580
    { 0, 0, 0, 0 },
10581
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10582
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x92090000 }
10583
  },
10584
/* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
10585
  {
10586
    { 0, 0, 0, 0 },
10587
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10588
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x92290000 }
10589
  },
10590
/* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
10591
  {
10592
    { 0, 0, 0, 0 },
10593
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10594
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x92390000 }
10595
  },
10596
/* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
10597
  {
10598
    { 0, 0, 0, 0 },
10599
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10600
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x94090000 }
10601
  },
10602
/* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
10603
  {
10604
    { 0, 0, 0, 0 },
10605
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10606
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x94290000 }
10607
  },
10608
/* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
10609
  {
10610
    { 0, 0, 0, 0 },
10611
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10612
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x94390000 }
10613
  },
10614
/* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
10615
  {
10616
    { 0, 0, 0, 0 },
10617
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10618
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x96090000 }
10619
  },
10620
/* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
10621
  {
10622
    { 0, 0, 0, 0 },
10623
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10624
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x96290000 }
10625
  },
10626
/* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
10627
  {
10628
    { 0, 0, 0, 0 },
10629
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10630
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x96390000 }
10631
  },
10632
/* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
10633
  {
10634
    { 0, 0, 0, 0 },
10635
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
10636
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92890000 }
10637
  },
10638
/* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
10639
  {
10640
    { 0, 0, 0, 0 },
10641
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
10642
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92a90000 }
10643
  },
10644
/* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
10645
  {
10646
    { 0, 0, 0, 0 },
10647
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
10648
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92b90000 }
10649
  },
10650
/* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
10651
  {
10652
    { 0, 0, 0, 0 },
10653
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
10654
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94890000 }
10655
  },
10656
/* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
10657
  {
10658
    { 0, 0, 0, 0 },
10659
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
10660
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94a90000 }
10661
  },
10662
/* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
10663
  {
10664
    { 0, 0, 0, 0 },
10665
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
10666
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94b90000 }
10667
  },
10668
/* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
10669
  {
10670
    { 0, 0, 0, 0 },
10671
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
10672
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92c90000 }
10673
  },
10674
/* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
10675
  {
10676
    { 0, 0, 0, 0 },
10677
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
10678
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92e90000 }
10679
  },
10680
/* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
10681
  {
10682
    { 0, 0, 0, 0 },
10683
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
10684
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92f90000 }
10685
  },
10686
/* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
10687
  {
10688
    { 0, 0, 0, 0 },
10689
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
10690
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94c90000 }
10691
  },
10692
/* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
10693
  {
10694
    { 0, 0, 0, 0 },
10695
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
10696
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94e90000 }
10697
  },
10698
/* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
10699
  {
10700
    { 0, 0, 0, 0 },
10701
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
10702
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94f90000 }
10703
  },
10704
/* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
10705
  {
10706
    { 0, 0, 0, 0 },
10707
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
10708
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96c90000 }
10709
  },
10710
/* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
10711
  {
10712
    { 0, 0, 0, 0 },
10713
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
10714
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96e90000 }
10715
  },
10716
/* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
10717
  {
10718
    { 0, 0, 0, 0 },
10719
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
10720
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96f90000 }
10721
  },
10722
/* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
10723
  {
10724
    { 0, 0, 0, 0 },
10725
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
10726
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96890000 }
10727
  },
10728
/* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
10729
  {
10730
    { 0, 0, 0, 0 },
10731
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } },
10732
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96a90000 }
10733
  },
10734
/* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
10735
  {
10736
    { 0, 0, 0, 0 },
10737
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } },
10738
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96b90000 }
10739
  },
10740
/* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
10741
  {
10742
    { 0, 0, 0, 0 },
10743
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
10744
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa8090000 }
10745
  },
10746
/* xor.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */
10747
  {
10748
    { 0, 0, 0, 0 },
10749
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
10750
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa8290000 }
10751
  },
10752
/* xor.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */
10753
  {
10754
    { 0, 0, 0, 0 },
10755
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
10756
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa8390000 }
10757
  },
10758
/* xor.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */
10759
  {
10760
    { 0, 0, 0, 0 },
10761
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
10762
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb8390000 }
10763
  },
10764
/* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
10765
  {
10766
    { 0, 0, 0, 0 },
10767
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
10768
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0890000 }
10769
  },
10770
/* xor.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */
10771
  {
10772
    { 0, 0, 0, 0 },
10773
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
10774
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0a90000 }
10775
  },
10776
/* xor.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */
10777
  {
10778
    { 0, 0, 0, 0 },
10779
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
10780
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0b90000 }
10781
  },
10782
/* xor.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */
10783
  {
10784
    { 0, 0, 0, 0 },
10785
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
10786
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0b90000 }
10787
  },
10788
/* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
10789
  {
10790
    { 0, 0, 0, 0 },
10791
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10792
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa0090000 }
10793
  },
10794
/* xor.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
10795
  {
10796
    { 0, 0, 0, 0 },
10797
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10798
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa0290000 }
10799
  },
10800
/* xor.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
10801
  {
10802
    { 0, 0, 0, 0 },
10803
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10804
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa0390000 }
10805
  },
10806
/* xor.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
10807
  {
10808
    { 0, 0, 0, 0 },
10809
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10810
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb0390000 }
10811
  },
10812
/* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
10813
  {
10814
    { 0, 0, 0, 0 },
10815
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10816
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa2090000 }
10817
  },
10818
/* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
10819
  {
10820
    { 0, 0, 0, 0 },
10821
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10822
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa2290000 }
10823
  },
10824
/* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
10825
  {
10826
    { 0, 0, 0, 0 },
10827
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10828
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa2390000 }
10829
  },
10830
/* xor.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
10831
  {
10832
    { 0, 0, 0, 0 },
10833
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10834
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xb2390000 }
10835
  },
10836
/* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
10837
  {
10838
    { 0, 0, 0, 0 },
10839
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10840
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa4090000 }
10841
  },
10842
/* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
10843
  {
10844
    { 0, 0, 0, 0 },
10845
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10846
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa4290000 }
10847
  },
10848
/* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
10849
  {
10850
    { 0, 0, 0, 0 },
10851
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10852
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa4390000 }
10853
  },
10854
/* xor.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
10855
  {
10856
    { 0, 0, 0, 0 },
10857
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10858
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xb4390000 }
10859
  },
10860
/* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
10861
  {
10862
    { 0, 0, 0, 0 },
10863
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10864
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa6090000 }
10865
  },
10866
/* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
10867
  {
10868
    { 0, 0, 0, 0 },
10869
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10870
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa6290000 }
10871
  },
10872
/* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
10873
  {
10874
    { 0, 0, 0, 0 },
10875
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10876
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa6390000 }
10877
  },
10878
/* xor.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
10879
  {
10880
    { 0, 0, 0, 0 },
10881
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
10882
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xb6390000 }
10883
  },
10884
/* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
10885
  {
10886
    { 0, 0, 0, 0 },
10887
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
10888
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2890000 }
10889
  },
10890
/* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
10891
  {
10892
    { 0, 0, 0, 0 },
10893
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
10894
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2a90000 }
10895
  },
10896
/* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
10897
  {
10898
    { 0, 0, 0, 0 },
10899
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
10900
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2b90000 }
10901
  },
10902
/* xor.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
10903
  {
10904
    { 0, 0, 0, 0 },
10905
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
10906
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xb2b90000 }
10907
  },
10908
/* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
10909
  {
10910
    { 0, 0, 0, 0 },
10911
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
10912
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4890000 }
10913
  },
10914
/* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
10915
  {
10916
    { 0, 0, 0, 0 },
10917
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
10918
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4a90000 }
10919
  },
10920
/* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
10921
  {
10922
    { 0, 0, 0, 0 },
10923
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
10924
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4b90000 }
10925
  },
10926
/* xor.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
10927
  {
10928
    { 0, 0, 0, 0 },
10929
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
10930
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xb4b90000 }
10931
  },
10932
/* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
10933
  {
10934
    { 0, 0, 0, 0 },
10935
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
10936
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2c90000 }
10937
  },
10938
/* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
10939
  {
10940
    { 0, 0, 0, 0 },
10941
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
10942
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2e90000 }
10943
  },
10944
/* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
10945
  {
10946
    { 0, 0, 0, 0 },
10947
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
10948
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2f90000 }
10949
  },
10950
/* xor.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
10951
  {
10952
    { 0, 0, 0, 0 },
10953
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
10954
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xb2f90000 }
10955
  },
10956
/* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
10957
  {
10958
    { 0, 0, 0, 0 },
10959
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
10960
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4c90000 }
10961
  },
10962
/* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
10963
  {
10964
    { 0, 0, 0, 0 },
10965
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
10966
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4e90000 }
10967
  },
10968
/* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
10969
  {
10970
    { 0, 0, 0, 0 },
10971
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
10972
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4f90000 }
10973
  },
10974
/* xor.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
10975
  {
10976
    { 0, 0, 0, 0 },
10977
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
10978
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xb4f90000 }
10979
  },
10980
/* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
10981
  {
10982
    { 0, 0, 0, 0 },
10983
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
10984
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6c90000 }
10985
  },
10986
/* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
10987
  {
10988
    { 0, 0, 0, 0 },
10989
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
10990
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6e90000 }
10991
  },
10992
/* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
10993
  {
10994
    { 0, 0, 0, 0 },
10995
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
10996
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6f90000 }
10997
  },
10998
/* xor.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
10999
  {
11000
    { 0, 0, 0, 0 },
11001
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
11002
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xb6f90000 }
11003
  },
11004
/* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
11005
  {
11006
    { 0, 0, 0, 0 },
11007
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
11008
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6890000 }
11009
  },
11010
/* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
11011
  {
11012
    { 0, 0, 0, 0 },
11013
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
11014
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6a90000 }
11015
  },
11016
/* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
11017
  {
11018
    { 0, 0, 0, 0 },
11019
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
11020
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6b90000 }
11021
  },
11022
/* xor.b${G} ${Dsp-16-u16},${Dsp-32-u24} */
11023
  {
11024
    { 0, 0, 0, 0 },
11025
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } },
11026
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xb6b90000 }
11027
  },
11028
/* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
11029
  {
11030
    { 0, 0, 0, 0 },
11031
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
11032
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb8090000 }
11033
  },
11034
/* xor.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */
11035
  {
11036
    { 0, 0, 0, 0 },
11037
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
11038
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb8290000 }
11039
  },
11040
/* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
11041
  {
11042
    { 0, 0, 0, 0 },
11043
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
11044
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0890000 }
11045
  },
11046
/* xor.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */
11047
  {
11048
    { 0, 0, 0, 0 },
11049
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
11050
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0a90000 }
11051
  },
11052
/* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
11053
  {
11054
    { 0, 0, 0, 0 },
11055
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
11056
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb0090000 }
11057
  },
11058
/* xor.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
11059
  {
11060
    { 0, 0, 0, 0 },
11061
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
11062
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb0290000 }
11063
  },
11064
/* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
11065
  {
11066
    { 0, 0, 0, 0 },
11067
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
11068
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_QI, { 0xb2090000 }
11069
  },
11070
/* xor.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
11071
  {
11072
    { 0, 0, 0, 0 },
11073
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
11074
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_QI, { 0xb2290000 }
11075
  },
11076
/* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
11077
  {
11078
    { 0, 0, 0, 0 },
11079
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
11080
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_QI, { 0xb4090000 }
11081
  },
11082
/* xor.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
11083
  {
11084
    { 0, 0, 0, 0 },
11085
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
11086
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_QI, { 0xb4290000 }
11087
  },
11088
/* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
11089
  {
11090
    { 0, 0, 0, 0 },
11091
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
11092
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_QI, { 0xb6090000 }
11093
  },
11094
/* xor.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
11095
  {
11096
    { 0, 0, 0, 0 },
11097
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
11098
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_QI, { 0xb6290000 }
11099
  },
11100
/* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
11101
  {
11102
    { 0, 0, 0, 0 },
11103
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
11104
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_QI, { 0xb2890000 }
11105
  },
11106
/* xor.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
11107
  {
11108
    { 0, 0, 0, 0 },
11109
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
11110
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_QI, { 0xb2a90000 }
11111
  },
11112
/* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
11113
  {
11114
    { 0, 0, 0, 0 },
11115
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
11116
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_QI, { 0xb4890000 }
11117
  },
11118
/* xor.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
11119
  {
11120
    { 0, 0, 0, 0 },
11121
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
11122
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_QI, { 0xb4a90000 }
11123
  },
11124
/* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
11125
  {
11126
    { 0, 0, 0, 0 },
11127
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
11128
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_QI, { 0xb2c90000 }
11129
  },
11130
/* xor.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
11131
  {
11132
    { 0, 0, 0, 0 },
11133
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
11134
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_QI, { 0xb2e90000 }
11135
  },
11136
/* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
11137
  {
11138
    { 0, 0, 0, 0 },
11139
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
11140
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_QI, { 0xb4c90000 }
11141
  },
11142
/* xor.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
11143
  {
11144
    { 0, 0, 0, 0 },
11145
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
11146
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_QI, { 0xb4e90000 }
11147
  },
11148
/* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
11149
  {
11150
    { 0, 0, 0, 0 },
11151
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
11152
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_QI, { 0xb6c90000 }
11153
  },
11154
/* xor.b${G} ${Dsp-16-u24},${Dsp-40-u16} */
11155
  {
11156
    { 0, 0, 0, 0 },
11157
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } },
11158
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_QI, { 0xb6e90000 }
11159
  },
11160
/* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
11161
  {
11162
    { 0, 0, 0, 0 },
11163
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
11164
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_QI, { 0xb6890000 }
11165
  },
11166
/* xor.b${G} ${Dsp-16-u24},${Dsp-40-u24} */
11167
  {
11168
    { 0, 0, 0, 0 },
11169
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } },
11170
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_QI, { 0xb6a90000 }
11171
  },
11172
/* xor.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */
11173
  {
11174
    { 0, 0, 0, 0 },
11175
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
11176
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xc809 }
11177
  },
11178
/* xor.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */
11179
  {
11180
    { 0, 0, 0, 0 },
11181
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
11182
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x8829 }
11183
  },
11184
/* xor.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
11185
  {
11186
    { 0, 0, 0, 0 },
11187
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
11188
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x8809 }
11189
  },
11190
/* xor.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */
11191
  {
11192
    { 0, 0, 0, 0 },
11193
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
11194
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xc089 }
11195
  },
11196
/* xor.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */
11197
  {
11198
    { 0, 0, 0, 0 },
11199
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
11200
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x80a9 }
11201
  },
11202
/* xor.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
11203
  {
11204
    { 0, 0, 0, 0 },
11205
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
11206
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x8089 }
11207
  },
11208
/* xor.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */
11209
  {
11210
    { 0, 0, 0, 0 },
11211
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
11212
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xc009 }
11213
  },
11214
/* xor.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */
11215
  {
11216
    { 0, 0, 0, 0 },
11217
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
11218
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x8029 }
11219
  },
11220
/* xor.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
11221
  {
11222
    { 0, 0, 0, 0 },
11223
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
11224
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x8009 }
11225
  },
11226
/* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
11227
  {
11228
    { 0, 0, 0, 0 },
11229
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
11230
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0xc20900 }
11231
  },
11232
/* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
11233
  {
11234
    { 0, 0, 0, 0 },
11235
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
11236
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0x822900 }
11237
  },
11238
/* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
11239
  {
11240
    { 0, 0, 0, 0 },
11241
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
11242
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0x820900 }
11243
  },
11244
/* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
11245
  {
11246
    { 0, 0, 0, 0 },
11247
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
11248
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0xc4090000 }
11249
  },
11250
/* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
11251
  {
11252
    { 0, 0, 0, 0 },
11253
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
11254
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0x84290000 }
11255
  },
11256
/* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
11257
  {
11258
    { 0, 0, 0, 0 },
11259
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
11260
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0x84090000 }
11261
  },
11262
/* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
11263
  {
11264
    { 0, 0, 0, 0 },
11265
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
11266
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0xc6090000 }
11267
  },
11268
/* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
11269
  {
11270
    { 0, 0, 0, 0 },
11271
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
11272
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0x86290000 }
11273
  },
11274
/* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
11275
  {
11276
    { 0, 0, 0, 0 },
11277
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
11278
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0x86090000 }
11279
  },
11280
/* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */
11281
  {
11282
    { 0, 0, 0, 0 },
11283
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
11284
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0xc28900 }
11285
  },
11286
/* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */
11287
  {
11288
    { 0, 0, 0, 0 },
11289
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
11290
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0x82a900 }
11291
  },
11292
/* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
11293
  {
11294
    { 0, 0, 0, 0 },
11295
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
11296
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0x828900 }
11297
  },
11298
/* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */
11299
  {
11300
    { 0, 0, 0, 0 },
11301
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
11302
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0xc4890000 }
11303
  },
11304
/* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */
11305
  {
11306
    { 0, 0, 0, 0 },
11307
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
11308
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0x84a90000 }
11309
  },
11310
/* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
11311
  {
11312
    { 0, 0, 0, 0 },
11313
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
11314
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0x84890000 }
11315
  },
11316
/* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */
11317
  {
11318
    { 0, 0, 0, 0 },
11319
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
11320
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0xc2c900 }
11321
  },
11322
/* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */
11323
  {
11324
    { 0, 0, 0, 0 },
11325
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
11326
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82e900 }
11327
  },
11328
/* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
11329
  {
11330
    { 0, 0, 0, 0 },
11331
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
11332
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82c900 }
11333
  },
11334
/* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */
11335
  {
11336
    { 0, 0, 0, 0 },
11337
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
11338
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0xc4c90000 }
11339
  },
11340
/* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */
11341
  {
11342
    { 0, 0, 0, 0 },
11343
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
11344
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84e90000 }
11345
  },
11346
/* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
11347
  {
11348
    { 0, 0, 0, 0 },
11349
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
11350
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84c90000 }
11351
  },
11352
/* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */
11353
  {
11354
    { 0, 0, 0, 0 },
11355
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), 0 } },
11356
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0xc6c90000 }
11357
  },
11358
/* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */
11359
  {
11360
    { 0, 0, 0, 0 },
11361
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), 0 } },
11362
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0x86e90000 }
11363
  },
11364
/* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
11365
  {
11366
    { 0, 0, 0, 0 },
11367
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } },
11368
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0x86c90000 }
11369
  },
11370
/* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */
11371
  {
11372
    { 0, 0, 0, 0 },
11373
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U24), 0 } },
11374
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0xc6890000 }
11375
  },
11376
/* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */
11377
  {
11378
    { 0, 0, 0, 0 },
11379
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U24), 0 } },
11380
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0x86a90000 }
11381
  },
11382
/* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
11383
  {
11384
    { 0, 0, 0, 0 },
11385
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } },
11386
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0x86890000 }
11387
  },
11388
/* xor.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
11389
  {
11390
    { 0, 0, 0, 0 },
11391
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } },
11392
    & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_Rn_direct_HI, { 0x898000 }
11393
  },
11394
/* xor.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */
11395
  {
11396
    { 0, 0, 0, 0 },
11397
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } },
11398
    & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_Rn_direct_HI, { 0x89a000 }
11399
  },
11400
/* xor.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */
11401
  {
11402
    { 0, 0, 0, 0 },
11403
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNHI), 0 } },
11404
    & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_Rn_direct_HI, { 0x89b000 }
11405
  },
11406
/* xor.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
11407
  {
11408
    { 0, 0, 0, 0 },
11409
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } },
11410
    & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_direct_HI, { 0x898400 }
11411
  },
11412
/* xor.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */
11413
  {
11414
    { 0, 0, 0, 0 },
11415
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } },
11416
    & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_direct_HI, { 0x89a400 }
11417
  },
11418
/* xor.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */
11419
  {
11420
    { 0, 0, 0, 0 },
11421
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANHI), 0 } },
11422
    & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_direct_HI, { 0x89b400 }
11423
  },
11424
/* xor.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
11425
  {
11426
    { 0, 0, 0, 0 },
11427
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
11428
    & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_indirect_HI, { 0x898600 }
11429
  },
11430
/* xor.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */
11431
  {
11432
    { 0, 0, 0, 0 },
11433
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
11434
    & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_indirect_HI, { 0x89a600 }
11435
  },
11436
/* xor.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */
11437
  {
11438
    { 0, 0, 0, 0 },
11439
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
11440
    & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_indirect_HI, { 0x89b600 }
11441
  },
11442
/* xor.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
11443
  {
11444
    { 0, 0, 0, 0 },
11445
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
11446
    & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_An_relative_HI, { 0x89880000 }
11447
  },
11448
/* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
11449
  {
11450
    { 0, 0, 0, 0 },
11451
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
11452
    & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_An_relative_HI, { 0x89a80000 }
11453
  },
11454
/* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
11455
  {
11456
    { 0, 0, 0, 0 },
11457
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
11458
    & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_An_relative_HI, { 0x89b80000 }
11459
  },
11460
/* xor.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
11461
  {
11462
    { 0, 0, 0, 0 },
11463
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
11464
    & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_An_relative_HI, { 0x898c0000 }
11465
  },
11466
/* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
11467
  {
11468
    { 0, 0, 0, 0 },
11469
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
11470
    & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_An_relative_HI, { 0x89ac0000 }
11471
  },
11472
/* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
11473
  {
11474
    { 0, 0, 0, 0 },
11475
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
11476
    & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_An_relative_HI, { 0x89bc0000 }
11477
  },
11478
/* xor.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
11479
  {
11480
    { 0, 0, 0, 0 },
11481
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
11482
    & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_SB_relative_HI, { 0x898a0000 }
11483
  },
11484
/* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
11485
  {
11486
    { 0, 0, 0, 0 },
11487
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
11488
    & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_SB_relative_HI, { 0x89aa0000 }
11489
  },
11490
/* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
11491
  {
11492
    { 0, 0, 0, 0 },
11493
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
11494
    & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_SB_relative_HI, { 0x89ba0000 }
11495
  },
11496
/* xor.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
11497
  {
11498
    { 0, 0, 0, 0 },
11499
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
11500
    & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_SB_relative_HI, { 0x898e0000 }
11501
  },
11502
/* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
11503
  {
11504
    { 0, 0, 0, 0 },
11505
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
11506
    & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_SB_relative_HI, { 0x89ae0000 }
11507
  },
11508
/* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
11509
  {
11510
    { 0, 0, 0, 0 },
11511
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
11512
    & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_SB_relative_HI, { 0x89be0000 }
11513
  },
11514
/* xor.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
11515
  {
11516
    { 0, 0, 0, 0 },
11517
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
11518
    & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_FB_relative_HI, { 0x898b0000 }
11519
  },
11520
/* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
11521
  {
11522
    { 0, 0, 0, 0 },
11523
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
11524
    & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_FB_relative_HI, { 0x89ab0000 }
11525
  },
11526
/* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
11527
  {
11528
    { 0, 0, 0, 0 },
11529
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
11530
    & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_FB_relative_HI, { 0x89bb0000 }
11531
  },
11532
/* xor.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
11533
  {
11534
    { 0, 0, 0, 0 },
11535
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } },
11536
    & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_absolute_HI, { 0x898f0000 }
11537
  },
11538
/* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
11539
  {
11540
    { 0, 0, 0, 0 },
11541
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
11542
    & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_absolute_HI, { 0x89af0000 }
11543
  },
11544
/* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
11545
  {
11546
    { 0, 0, 0, 0 },
11547
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
11548
    & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_absolute_HI, { 0x89bf0000 }
11549
  },
11550
/* xor.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
11551
  {
11552
    { 0, 0, 0, 0 },
11553
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } },
11554
    & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_Rn_direct_HI, { 0x89c00000 }
11555
  },
11556
/* xor.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */
11557
  {
11558
    { 0, 0, 0, 0 },
11559
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } },
11560
    & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_Rn_direct_HI, { 0x89e00000 }
11561
  },
11562
/* xor.w${G} ${Dsp-16-u16},$Dst16RnHI */
11563
  {
11564
    { 0, 0, 0, 0 },
11565
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16RNHI), 0 } },
11566
    & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_Rn_direct_HI, { 0x89f00000 }
11567
  },
11568
/* xor.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
11569
  {
11570
    { 0, 0, 0, 0 },
11571
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } },
11572
    & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_direct_HI, { 0x89c40000 }
11573
  },
11574
/* xor.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */
11575
  {
11576
    { 0, 0, 0, 0 },
11577
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } },
11578
    & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_direct_HI, { 0x89e40000 }
11579
  },
11580
/* xor.w${G} ${Dsp-16-u16},$Dst16AnHI */
11581
  {
11582
    { 0, 0, 0, 0 },
11583
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16ANHI), 0 } },
11584
    & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_direct_HI, { 0x89f40000 }
11585
  },
11586
/* xor.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
11587
  {
11588
    { 0, 0, 0, 0 },
11589
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
11590
    & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_indirect_HI, { 0x89c60000 }
11591
  },
11592
/* xor.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */
11593
  {
11594
    { 0, 0, 0, 0 },
11595
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
11596
    & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_indirect_HI, { 0x89e60000 }
11597
  },
11598
/* xor.w${G} ${Dsp-16-u16},[$Dst16An] */
11599
  {
11600
    { 0, 0, 0, 0 },
11601
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } },
11602
    & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_indirect_HI, { 0x89f60000 }
11603
  },
11604
/* xor.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
11605
  {
11606
    { 0, 0, 0, 0 },
11607
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
11608
    & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_An_relative_HI, { 0x89c80000 }
11609
  },
11610
/* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
11611
  {
11612
    { 0, 0, 0, 0 },
11613
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
11614
    & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_An_relative_HI, { 0x89e80000 }
11615
  },
11616
/* xor.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
11617
  {
11618
    { 0, 0, 0, 0 },
11619
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
11620
    & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_An_relative_HI, { 0x89f80000 }
11621
  },
11622
/* xor.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
11623
  {
11624
    { 0, 0, 0, 0 },
11625
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
11626
    & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_An_relative_HI, { 0x89cc0000 }
11627
  },
11628
/* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
11629
  {
11630
    { 0, 0, 0, 0 },
11631
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
11632
    & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_An_relative_HI, { 0x89ec0000 }
11633
  },
11634
/* xor.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
11635
  {
11636
    { 0, 0, 0, 0 },
11637
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
11638
    & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_An_relative_HI, { 0x89fc0000 }
11639
  },
11640
/* xor.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
11641
  {
11642
    { 0, 0, 0, 0 },
11643
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
11644
    & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_SB_relative_HI, { 0x89ca0000 }
11645
  },
11646
/* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
11647
  {
11648
    { 0, 0, 0, 0 },
11649
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
11650
    & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_SB_relative_HI, { 0x89ea0000 }
11651
  },
11652
/* xor.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
11653
  {
11654
    { 0, 0, 0, 0 },
11655
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
11656
    & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_SB_relative_HI, { 0x89fa0000 }
11657
  },
11658
/* xor.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
11659
  {
11660
    { 0, 0, 0, 0 },
11661
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
11662
    & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_SB_relative_HI, { 0x89ce0000 }
11663
  },
11664
/* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
11665
  {
11666
    { 0, 0, 0, 0 },
11667
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
11668
    & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_SB_relative_HI, { 0x89ee0000 }
11669
  },
11670
/* xor.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
11671
  {
11672
    { 0, 0, 0, 0 },
11673
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
11674
    & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_SB_relative_HI, { 0x89fe0000 }
11675
  },
11676
/* xor.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
11677
  {
11678
    { 0, 0, 0, 0 },
11679
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
11680
    & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_FB_relative_HI, { 0x89cb0000 }
11681
  },
11682
/* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
11683
  {
11684
    { 0, 0, 0, 0 },
11685
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
11686
    & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_FB_relative_HI, { 0x89eb0000 }
11687
  },
11688
/* xor.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
11689
  {
11690
    { 0, 0, 0, 0 },
11691
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
11692
    & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_FB_relative_HI, { 0x89fb0000 }
11693
  },
11694
/* xor.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
11695
  {
11696
    { 0, 0, 0, 0 },
11697
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } },
11698
    & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_absolute_HI, { 0x89cf0000 }
11699
  },
11700
/* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
11701
  {
11702
    { 0, 0, 0, 0 },
11703
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
11704
    & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_absolute_HI, { 0x89ef0000 }
11705
  },
11706
/* xor.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
11707
  {
11708
    { 0, 0, 0, 0 },
11709
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
11710
    & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_absolute_HI, { 0x89ff0000 }
11711
  },
11712
/* xor.w${G} $Src16RnHI,$Dst16RnHI */
11713
  {
11714
    { 0, 0, 0, 0 },
11715
    { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DST16RNHI), 0 } },
11716
    & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_Rn_direct_HI, { 0x8900 }
11717
  },
11718
/* xor.w${G} $Src16AnHI,$Dst16RnHI */
11719
  {
11720
    { 0, 0, 0, 0 },
11721
    { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DST16RNHI), 0 } },
11722
    & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_Rn_direct_HI, { 0x8940 }
11723
  },
11724
/* xor.w${G} [$Src16An],$Dst16RnHI */
11725
  {
11726
    { 0, 0, 0, 0 },
11727
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } },
11728
    & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_Rn_direct_HI, { 0x8960 }
11729
  },
11730
/* xor.w${G} $Src16RnHI,$Dst16AnHI */
11731
  {
11732
    { 0, 0, 0, 0 },
11733
    { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DST16ANHI), 0 } },
11734
    & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_direct_HI, { 0x8904 }
11735
  },
11736
/* xor.w${G} $Src16AnHI,$Dst16AnHI */
11737
  {
11738
    { 0, 0, 0, 0 },
11739
    { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DST16ANHI), 0 } },
11740
    & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_direct_HI, { 0x8944 }
11741
  },
11742
/* xor.w${G} [$Src16An],$Dst16AnHI */
11743
  {
11744
    { 0, 0, 0, 0 },
11745
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } },
11746
    & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_direct_HI, { 0x8964 }
11747
  },
11748
/* xor.w${G} $Src16RnHI,[$Dst16An] */
11749
  {
11750
    { 0, 0, 0, 0 },
11751
    { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', '[', OP (DST16AN), ']', 0 } },
11752
    & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_indirect_HI, { 0x8906 }
11753
  },
11754
/* xor.w${G} $Src16AnHI,[$Dst16An] */
11755
  {
11756
    { 0, 0, 0, 0 },
11757
    { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', '[', OP (DST16AN), ']', 0 } },
11758
    & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_indirect_HI, { 0x8946 }
11759
  },
11760
/* xor.w${G} [$Src16An],[$Dst16An] */
11761
  {
11762
    { 0, 0, 0, 0 },
11763
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
11764
    & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_indirect_HI, { 0x8966 }
11765
  },
11766
/* xor.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
11767
  {
11768
    { 0, 0, 0, 0 },
11769
    { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
11770
    & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_An_relative_HI, { 0x890800 }
11771
  },
11772
/* xor.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
11773
  {
11774
    { 0, 0, 0, 0 },
11775
    { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
11776
    & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_An_relative_HI, { 0x894800 }
11777
  },
11778
/* xor.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
11779
  {
11780
    { 0, 0, 0, 0 },
11781
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
11782
    & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_An_relative_HI, { 0x896800 }
11783
  },
11784
/* xor.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
11785
  {
11786
    { 0, 0, 0, 0 },
11787
    { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
11788
    & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_An_relative_HI, { 0x890c0000 }
11789
  },
11790
/* xor.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
11791
  {
11792
    { 0, 0, 0, 0 },
11793
    { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
11794
    & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_An_relative_HI, { 0x894c0000 }
11795
  },
11796
/* xor.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
11797
  {
11798
    { 0, 0, 0, 0 },
11799
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
11800
    & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_An_relative_HI, { 0x896c0000 }
11801
  },
11802
/* xor.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */
11803
  {
11804
    { 0, 0, 0, 0 },
11805
    { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
11806
    & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_SB_relative_HI, { 0x890a00 }
11807
  },
11808
/* xor.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */
11809
  {
11810
    { 0, 0, 0, 0 },
11811
    { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
11812
    & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_SB_relative_HI, { 0x894a00 }
11813
  },
11814
/* xor.w${G} [$Src16An],${Dsp-16-u8}[sb] */
11815
  {
11816
    { 0, 0, 0, 0 },
11817
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
11818
    & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_SB_relative_HI, { 0x896a00 }
11819
  },
11820
/* xor.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */
11821
  {
11822
    { 0, 0, 0, 0 },
11823
    { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
11824
    & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_SB_relative_HI, { 0x890e0000 }
11825
  },
11826
/* xor.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */
11827
  {
11828
    { 0, 0, 0, 0 },
11829
    { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
11830
    & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_SB_relative_HI, { 0x894e0000 }
11831
  },
11832
/* xor.w${G} [$Src16An],${Dsp-16-u16}[sb] */
11833
  {
11834
    { 0, 0, 0, 0 },
11835
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
11836
    & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_SB_relative_HI, { 0x896e0000 }
11837
  },
11838
/* xor.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */
11839
  {
11840
    { 0, 0, 0, 0 },
11841
    { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
11842
    & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_FB_relative_HI, { 0x890b00 }
11843
  },
11844
/* xor.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */
11845
  {
11846
    { 0, 0, 0, 0 },
11847
    { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
11848
    & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_FB_relative_HI, { 0x894b00 }
11849
  },
11850
/* xor.w${G} [$Src16An],${Dsp-16-s8}[fb] */
11851
  {
11852
    { 0, 0, 0, 0 },
11853
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
11854
    & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_FB_relative_HI, { 0x896b00 }
11855
  },
11856
/* xor.w${G} $Src16RnHI,${Dsp-16-u16} */
11857
  {
11858
    { 0, 0, 0, 0 },
11859
    { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), 0 } },
11860
    & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_absolute_HI, { 0x890f0000 }
11861
  },
11862
/* xor.w${G} $Src16AnHI,${Dsp-16-u16} */
11863
  {
11864
    { 0, 0, 0, 0 },
11865
    { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), 0 } },
11866
    & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_absolute_HI, { 0x894f0000 }
11867
  },
11868
/* xor.w${G} [$Src16An],${Dsp-16-u16} */
11869
  {
11870
    { 0, 0, 0, 0 },
11871
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } },
11872
    & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_absolute_HI, { 0x896f0000 }
11873
  },
11874
/* xor.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
11875
  {
11876
    { 0, 0, 0, 0 },
11877
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } },
11878
    & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_Rn_direct_QI, { 0x888000 }
11879
  },
11880
/* xor.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */
11881
  {
11882
    { 0, 0, 0, 0 },
11883
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } },
11884
    & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_Rn_direct_QI, { 0x88a000 }
11885
  },
11886
/* xor.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */
11887
  {
11888
    { 0, 0, 0, 0 },
11889
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNQI), 0 } },
11890
    & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_Rn_direct_QI, { 0x88b000 }
11891
  },
11892
/* xor.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
11893
  {
11894
    { 0, 0, 0, 0 },
11895
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } },
11896
    & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_direct_QI, { 0x888400 }
11897
  },
11898
/* xor.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */
11899
  {
11900
    { 0, 0, 0, 0 },
11901
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } },
11902
    & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_direct_QI, { 0x88a400 }
11903
  },
11904
/* xor.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */
11905
  {
11906
    { 0, 0, 0, 0 },
11907
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANQI), 0 } },
11908
    & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_direct_QI, { 0x88b400 }
11909
  },
11910
/* xor.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
11911
  {
11912
    { 0, 0, 0, 0 },
11913
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
11914
    & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_indirect_QI, { 0x888600 }
11915
  },
11916
/* xor.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */
11917
  {
11918
    { 0, 0, 0, 0 },
11919
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
11920
    & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_indirect_QI, { 0x88a600 }
11921
  },
11922
/* xor.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */
11923
  {
11924
    { 0, 0, 0, 0 },
11925
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
11926
    & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_indirect_QI, { 0x88b600 }
11927
  },
11928
/* xor.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
11929
  {
11930
    { 0, 0, 0, 0 },
11931
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
11932
    & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_An_relative_QI, { 0x88880000 }
11933
  },
11934
/* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
11935
  {
11936
    { 0, 0, 0, 0 },
11937
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
11938
    & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_An_relative_QI, { 0x88a80000 }
11939
  },
11940
/* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
11941
  {
11942
    { 0, 0, 0, 0 },
11943
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
11944
    & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_An_relative_QI, { 0x88b80000 }
11945
  },
11946
/* xor.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
11947
  {
11948
    { 0, 0, 0, 0 },
11949
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
11950
    & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_An_relative_QI, { 0x888c0000 }
11951
  },
11952
/* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
11953
  {
11954
    { 0, 0, 0, 0 },
11955
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
11956
    & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_An_relative_QI, { 0x88ac0000 }
11957
  },
11958
/* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
11959
  {
11960
    { 0, 0, 0, 0 },
11961
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
11962
    & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_An_relative_QI, { 0x88bc0000 }
11963
  },
11964
/* xor.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
11965
  {
11966
    { 0, 0, 0, 0 },
11967
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
11968
    & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_SB_relative_QI, { 0x888a0000 }
11969
  },
11970
/* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
11971
  {
11972
    { 0, 0, 0, 0 },
11973
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
11974
    & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_SB_relative_QI, { 0x88aa0000 }
11975
  },
11976
/* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
11977
  {
11978
    { 0, 0, 0, 0 },
11979
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
11980
    & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_SB_relative_QI, { 0x88ba0000 }
11981
  },
11982
/* xor.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
11983
  {
11984
    { 0, 0, 0, 0 },
11985
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
11986
    & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_SB_relative_QI, { 0x888e0000 }
11987
  },
11988
/* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
11989
  {
11990
    { 0, 0, 0, 0 },
11991
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
11992
    & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_SB_relative_QI, { 0x88ae0000 }
11993
  },
11994
/* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
11995
  {
11996
    { 0, 0, 0, 0 },
11997
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
11998
    & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_SB_relative_QI, { 0x88be0000 }
11999
  },
12000
/* xor.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
12001
  {
12002
    { 0, 0, 0, 0 },
12003
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
12004
    & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_FB_relative_QI, { 0x888b0000 }
12005
  },
12006
/* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
12007
  {
12008
    { 0, 0, 0, 0 },
12009
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
12010
    & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_FB_relative_QI, { 0x88ab0000 }
12011
  },
12012
/* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
12013
  {
12014
    { 0, 0, 0, 0 },
12015
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
12016
    & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_FB_relative_QI, { 0x88bb0000 }
12017
  },
12018
/* xor.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
12019
  {
12020
    { 0, 0, 0, 0 },
12021
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } },
12022
    & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_absolute_QI, { 0x888f0000 }
12023
  },
12024
/* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
12025
  {
12026
    { 0, 0, 0, 0 },
12027
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
12028
    & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_absolute_QI, { 0x88af0000 }
12029
  },
12030
/* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
12031
  {
12032
    { 0, 0, 0, 0 },
12033
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
12034
    & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_absolute_QI, { 0x88bf0000 }
12035
  },
12036
/* xor.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
12037
  {
12038
    { 0, 0, 0, 0 },
12039
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } },
12040
    & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_Rn_direct_QI, { 0x88c00000 }
12041
  },
12042
/* xor.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */
12043
  {
12044
    { 0, 0, 0, 0 },
12045
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } },
12046
    & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_Rn_direct_QI, { 0x88e00000 }
12047
  },
12048
/* xor.b${G} ${Dsp-16-u16},$Dst16RnQI */
12049
  {
12050
    { 0, 0, 0, 0 },
12051
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16RNQI), 0 } },
12052
    & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_Rn_direct_QI, { 0x88f00000 }
12053
  },
12054
/* xor.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
12055
  {
12056
    { 0, 0, 0, 0 },
12057
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } },
12058
    & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_direct_QI, { 0x88c40000 }
12059
  },
12060
/* xor.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */
12061
  {
12062
    { 0, 0, 0, 0 },
12063
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } },
12064
    & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_direct_QI, { 0x88e40000 }
12065
  },
12066
/* xor.b${G} ${Dsp-16-u16},$Dst16AnQI */
12067
  {
12068
    { 0, 0, 0, 0 },
12069
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16ANQI), 0 } },
12070
    & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_direct_QI, { 0x88f40000 }
12071
  },
12072
/* xor.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
12073
  {
12074
    { 0, 0, 0, 0 },
12075
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
12076
    & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_indirect_QI, { 0x88c60000 }
12077
  },
12078
/* xor.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */
12079
  {
12080
    { 0, 0, 0, 0 },
12081
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
12082
    & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_indirect_QI, { 0x88e60000 }
12083
  },
12084
/* xor.b${G} ${Dsp-16-u16},[$Dst16An] */
12085
  {
12086
    { 0, 0, 0, 0 },
12087
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } },
12088
    & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_indirect_QI, { 0x88f60000 }
12089
  },
12090
/* xor.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
12091
  {
12092
    { 0, 0, 0, 0 },
12093
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
12094
    & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_An_relative_QI, { 0x88c80000 }
12095
  },
12096
/* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
12097
  {
12098
    { 0, 0, 0, 0 },
12099
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
12100
    & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_An_relative_QI, { 0x88e80000 }
12101
  },
12102
/* xor.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
12103
  {
12104
    { 0, 0, 0, 0 },
12105
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
12106
    & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_An_relative_QI, { 0x88f80000 }
12107
  },
12108
/* xor.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
12109
  {
12110
    { 0, 0, 0, 0 },
12111
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
12112
    & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_An_relative_QI, { 0x88cc0000 }
12113
  },
12114
/* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
12115
  {
12116
    { 0, 0, 0, 0 },
12117
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
12118
    & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_An_relative_QI, { 0x88ec0000 }
12119
  },
12120
/* xor.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
12121
  {
12122
    { 0, 0, 0, 0 },
12123
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
12124
    & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_An_relative_QI, { 0x88fc0000 }
12125
  },
12126
/* xor.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
12127
  {
12128
    { 0, 0, 0, 0 },
12129
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
12130
    & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_SB_relative_QI, { 0x88ca0000 }
12131
  },
12132
/* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
12133
  {
12134
    { 0, 0, 0, 0 },
12135
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
12136
    & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_SB_relative_QI, { 0x88ea0000 }
12137
  },
12138
/* xor.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
12139
  {
12140
    { 0, 0, 0, 0 },
12141
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
12142
    & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_SB_relative_QI, { 0x88fa0000 }
12143
  },
12144
/* xor.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
12145
  {
12146
    { 0, 0, 0, 0 },
12147
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
12148
    & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_SB_relative_QI, { 0x88ce0000 }
12149
  },
12150
/* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
12151
  {
12152
    { 0, 0, 0, 0 },
12153
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
12154
    & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_SB_relative_QI, { 0x88ee0000 }
12155
  },
12156
/* xor.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
12157
  {
12158
    { 0, 0, 0, 0 },
12159
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
12160
    & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_SB_relative_QI, { 0x88fe0000 }
12161
  },
12162
/* xor.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
12163
  {
12164
    { 0, 0, 0, 0 },
12165
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
12166
    & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_FB_relative_QI, { 0x88cb0000 }
12167
  },
12168
/* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
12169
  {
12170
    { 0, 0, 0, 0 },
12171
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
12172
    & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_FB_relative_QI, { 0x88eb0000 }
12173
  },
12174
/* xor.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
12175
  {
12176
    { 0, 0, 0, 0 },
12177
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
12178
    & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_FB_relative_QI, { 0x88fb0000 }
12179
  },
12180
/* xor.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
12181
  {
12182
    { 0, 0, 0, 0 },
12183
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } },
12184
    & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_absolute_QI, { 0x88cf0000 }
12185
  },
12186
/* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
12187
  {
12188
    { 0, 0, 0, 0 },
12189
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
12190
    & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_absolute_QI, { 0x88ef0000 }
12191
  },
12192
/* xor.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
12193
  {
12194
    { 0, 0, 0, 0 },
12195
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
12196
    & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_absolute_QI, { 0x88ff0000 }
12197
  },
12198
/* xor.b${G} $Src16RnQI,$Dst16RnQI */
12199
  {
12200
    { 0, 0, 0, 0 },
12201
    { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DST16RNQI), 0 } },
12202
    & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_Rn_direct_QI, { 0x8800 }
12203
  },
12204
/* xor.b${G} $Src16AnQI,$Dst16RnQI */
12205
  {
12206
    { 0, 0, 0, 0 },
12207
    { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DST16RNQI), 0 } },
12208
    & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_Rn_direct_QI, { 0x8840 }
12209
  },
12210
/* xor.b${G} [$Src16An],$Dst16RnQI */
12211
  {
12212
    { 0, 0, 0, 0 },
12213
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } },
12214
    & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_Rn_direct_QI, { 0x8860 }
12215
  },
12216
/* xor.b${G} $Src16RnQI,$Dst16AnQI */
12217
  {
12218
    { 0, 0, 0, 0 },
12219
    { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DST16ANQI), 0 } },
12220
    & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_direct_QI, { 0x8804 }
12221
  },
12222
/* xor.b${G} $Src16AnQI,$Dst16AnQI */
12223
  {
12224
    { 0, 0, 0, 0 },
12225
    { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DST16ANQI), 0 } },
12226
    & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_direct_QI, { 0x8844 }
12227
  },
12228
/* xor.b${G} [$Src16An],$Dst16AnQI */
12229
  {
12230
    { 0, 0, 0, 0 },
12231
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } },
12232
    & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_direct_QI, { 0x8864 }
12233
  },
12234
/* xor.b${G} $Src16RnQI,[$Dst16An] */
12235
  {
12236
    { 0, 0, 0, 0 },
12237
    { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', '[', OP (DST16AN), ']', 0 } },
12238
    & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_indirect_QI, { 0x8806 }
12239
  },
12240
/* xor.b${G} $Src16AnQI,[$Dst16An] */
12241
  {
12242
    { 0, 0, 0, 0 },
12243
    { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', '[', OP (DST16AN), ']', 0 } },
12244
    & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_indirect_QI, { 0x8846 }
12245
  },
12246
/* xor.b${G} [$Src16An],[$Dst16An] */
12247
  {
12248
    { 0, 0, 0, 0 },
12249
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
12250
    & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_indirect_QI, { 0x8866 }
12251
  },
12252
/* xor.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
12253
  {
12254
    { 0, 0, 0, 0 },
12255
    { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
12256
    & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_An_relative_QI, { 0x880800 }
12257
  },
12258
/* xor.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
12259
  {
12260
    { 0, 0, 0, 0 },
12261
    { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
12262
    & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_An_relative_QI, { 0x884800 }
12263
  },
12264
/* xor.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
12265
  {
12266
    { 0, 0, 0, 0 },
12267
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
12268
    & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_An_relative_QI, { 0x886800 }
12269
  },
12270
/* xor.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
12271
  {
12272
    { 0, 0, 0, 0 },
12273
    { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
12274
    & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_An_relative_QI, { 0x880c0000 }
12275
  },
12276
/* xor.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
12277
  {
12278
    { 0, 0, 0, 0 },
12279
    { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
12280
    & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_An_relative_QI, { 0x884c0000 }
12281
  },
12282
/* xor.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
12283
  {
12284
    { 0, 0, 0, 0 },
12285
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
12286
    & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_An_relative_QI, { 0x886c0000 }
12287
  },
12288
/* xor.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */
12289
  {
12290
    { 0, 0, 0, 0 },
12291
    { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
12292
    & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_SB_relative_QI, { 0x880a00 }
12293
  },
12294
/* xor.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */
12295
  {
12296
    { 0, 0, 0, 0 },
12297
    { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
12298
    & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_SB_relative_QI, { 0x884a00 }
12299
  },
12300
/* xor.b${G} [$Src16An],${Dsp-16-u8}[sb] */
12301
  {
12302
    { 0, 0, 0, 0 },
12303
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
12304
    & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_SB_relative_QI, { 0x886a00 }
12305
  },
12306
/* xor.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */
12307
  {
12308
    { 0, 0, 0, 0 },
12309
    { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
12310
    & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_SB_relative_QI, { 0x880e0000 }
12311
  },
12312
/* xor.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */
12313
  {
12314
    { 0, 0, 0, 0 },
12315
    { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
12316
    & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_SB_relative_QI, { 0x884e0000 }
12317
  },
12318
/* xor.b${G} [$Src16An],${Dsp-16-u16}[sb] */
12319
  {
12320
    { 0, 0, 0, 0 },
12321
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
12322
    & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_SB_relative_QI, { 0x886e0000 }
12323
  },
12324
/* xor.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */
12325
  {
12326
    { 0, 0, 0, 0 },
12327
    { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
12328
    & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_FB_relative_QI, { 0x880b00 }
12329
  },
12330
/* xor.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */
12331
  {
12332
    { 0, 0, 0, 0 },
12333
    { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
12334
    & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_FB_relative_QI, { 0x884b00 }
12335
  },
12336
/* xor.b${G} [$Src16An],${Dsp-16-s8}[fb] */
12337
  {
12338
    { 0, 0, 0, 0 },
12339
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
12340
    & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_FB_relative_QI, { 0x886b00 }
12341
  },
12342
/* xor.b${G} $Src16RnQI,${Dsp-16-u16} */
12343
  {
12344
    { 0, 0, 0, 0 },
12345
    { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), 0 } },
12346
    & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_absolute_QI, { 0x880f0000 }
12347
  },
12348
/* xor.b${G} $Src16AnQI,${Dsp-16-u16} */
12349
  {
12350
    { 0, 0, 0, 0 },
12351
    { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), 0 } },
12352
    & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_absolute_QI, { 0x884f0000 }
12353
  },
12354
/* xor.b${G} [$Src16An],${Dsp-16-u16} */
12355
  {
12356
    { 0, 0, 0, 0 },
12357
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } },
12358
    & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_absolute_QI, { 0x886f0000 }
12359
  },
12360
/* xor.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */
12361
  {
12362
    { 0, 0, 0, 0 },
12363
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
12364
    & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0x990e0000 }
12365
  },
12366
/* xor.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */
12367
  {
12368
    { 0, 0, 0, 0 },
12369
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
12370
    & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0x918e0000 }
12371
  },
12372
/* xor.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */
12373
  {
12374
    { 0, 0, 0, 0 },
12375
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
12376
    & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0x910e0000 }
12377
  },
12378
/* xor.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
12379
  {
12380
    { 0, 0, 0, 0 },
12381
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
12382
    & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0x930e0000 }
12383
  },
12384
/* xor.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
12385
  {
12386
    { 0, 0, 0, 0 },
12387
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
12388
    & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0x938e0000 }
12389
  },
12390
/* xor.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
12391
  {
12392
    { 0, 0, 0, 0 },
12393
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
12394
    & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0x93ce0000 }
12395
  },
12396
/* xor.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
12397
  {
12398
    { 0, 0, 0, 0 },
12399
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
12400
    & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0x950e0000 }
12401
  },
12402
/* xor.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
12403
  {
12404
    { 0, 0, 0, 0 },
12405
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
12406
    & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0x958e0000 }
12407
  },
12408
/* xor.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */
12409
  {
12410
    { 0, 0, 0, 0 },
12411
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
12412
    & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0x95ce0000 }
12413
  },
12414
/* xor.w${G} #${Imm-32-HI},${Dsp-16-u16} */
12415
  {
12416
    { 0, 0, 0, 0 },
12417
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } },
12418
    & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0x97ce0000 }
12419
  },
12420
/* xor.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
12421
  {
12422
    { 0, 0, 0, 0 },
12423
    { { MNEM, OP (G), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
12424
    & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0x970e0000 }
12425
  },
12426
/* xor.w${G} #${Imm-40-HI},${Dsp-16-u24} */
12427
  {
12428
    { 0, 0, 0, 0 },
12429
    { { MNEM, OP (G), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), 0 } },
12430
    & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0x978e0000 }
12431
  },
12432
/* xor.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */
12433
  {
12434
    { 0, 0, 0, 0 },
12435
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
12436
    & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0x980e00 }
12437
  },
12438
/* xor.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */
12439
  {
12440
    { 0, 0, 0, 0 },
12441
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
12442
    & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0x908e00 }
12443
  },
12444
/* xor.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */
12445
  {
12446
    { 0, 0, 0, 0 },
12447
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
12448
    & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0x900e00 }
12449
  },
12450
/* xor.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
12451
  {
12452
    { 0, 0, 0, 0 },
12453
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
12454
    & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0x920e0000 }
12455
  },
12456
/* xor.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
12457
  {
12458
    { 0, 0, 0, 0 },
12459
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
12460
    & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0x928e0000 }
12461
  },
12462
/* xor.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
12463
  {
12464
    { 0, 0, 0, 0 },
12465
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
12466
    & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0x92ce0000 }
12467
  },
12468
/* xor.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
12469
  {
12470
    { 0, 0, 0, 0 },
12471
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
12472
    & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0x940e0000 }
12473
  },
12474
/* xor.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
12475
  {
12476
    { 0, 0, 0, 0 },
12477
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
12478
    & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0x948e0000 }
12479
  },
12480
/* xor.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */
12481
  {
12482
    { 0, 0, 0, 0 },
12483
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
12484
    & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0x94ce0000 }
12485
  },
12486
/* xor.b${G} #${Imm-32-QI},${Dsp-16-u16} */
12487
  {
12488
    { 0, 0, 0, 0 },
12489
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } },
12490
    & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0x96ce0000 }
12491
  },
12492
/* xor.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
12493
  {
12494
    { 0, 0, 0, 0 },
12495
    { { MNEM, OP (G), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
12496
    & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0x960e0000 }
12497
  },
12498
/* xor.b${G} #${Imm-40-QI},${Dsp-16-u24} */
12499
  {
12500
    { 0, 0, 0, 0 },
12501
    { { MNEM, OP (G), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), 0 } },
12502
    & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0x968e0000 }
12503
  },
12504
/* xor.w${G} #${Imm-16-HI},$Dst16RnHI */
12505
  {
12506
    { 0, 0, 0, 0 },
12507
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST16RNHI), 0 } },
12508
    & ifmt_xor16_w_imm_G_basic_dst16_Rn_direct_HI, { 0x77100000 }
12509
  },
12510
/* xor.w${G} #${Imm-16-HI},$Dst16AnHI */
12511
  {
12512
    { 0, 0, 0, 0 },
12513
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST16ANHI), 0 } },
12514
    & ifmt_xor16_w_imm_G_basic_dst16_An_direct_HI, { 0x77140000 }
12515
  },
12516
/* xor.w${G} #${Imm-16-HI},[$Dst16An] */
12517
  {
12518
    { 0, 0, 0, 0 },
12519
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST16AN), ']', 0 } },
12520
    & ifmt_xor16_w_imm_G_basic_dst16_An_indirect_HI, { 0x77160000 }
12521
  },
12522
/* xor.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
12523
  {
12524
    { 0, 0, 0, 0 },
12525
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
12526
    & ifmt_xor16_w_imm_G_16_8_dst16_16_8_An_relative_HI, { 0x77180000 }
12527
  },
12528
/* xor.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
12529
  {
12530
    { 0, 0, 0, 0 },
12531
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
12532
    & ifmt_xor16_w_imm_G_16_8_dst16_16_8_SB_relative_HI, { 0x771a0000 }
12533
  },
12534
/* xor.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
12535
  {
12536
    { 0, 0, 0, 0 },
12537
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
12538
    & ifmt_xor16_w_imm_G_16_8_dst16_16_8_FB_relative_HI, { 0x771b0000 }
12539
  },
12540
/* xor.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
12541
  {
12542
    { 0, 0, 0, 0 },
12543
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
12544
    & ifmt_xor16_w_imm_G_16_16_dst16_16_16_An_relative_HI, { 0x771c0000 }
12545
  },
12546
/* xor.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
12547
  {
12548
    { 0, 0, 0, 0 },
12549
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
12550
    & ifmt_xor16_w_imm_G_16_16_dst16_16_16_SB_relative_HI, { 0x771e0000 }
12551
  },
12552
/* xor.w${G} #${Imm-32-HI},${Dsp-16-u16} */
12553
  {
12554
    { 0, 0, 0, 0 },
12555
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } },
12556
    & ifmt_xor16_w_imm_G_16_16_dst16_16_16_absolute_HI, { 0x771f0000 }
12557
  },
12558
/* xor.b${G} #${Imm-16-QI},$Dst16RnQI */
12559
  {
12560
    { 0, 0, 0, 0 },
12561
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST16RNQI), 0 } },
12562
    & ifmt_xor16_b_imm_G_basic_dst16_Rn_direct_QI, { 0x761000 }
12563
  },
12564
/* xor.b${G} #${Imm-16-QI},$Dst16AnQI */
12565
  {
12566
    { 0, 0, 0, 0 },
12567
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST16ANQI), 0 } },
12568
    & ifmt_xor16_b_imm_G_basic_dst16_An_direct_QI, { 0x761400 }
12569
  },
12570
/* xor.b${G} #${Imm-16-QI},[$Dst16An] */
12571
  {
12572
    { 0, 0, 0, 0 },
12573
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST16AN), ']', 0 } },
12574
    & ifmt_xor16_b_imm_G_basic_dst16_An_indirect_QI, { 0x761600 }
12575
  },
12576
/* xor.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
12577
  {
12578
    { 0, 0, 0, 0 },
12579
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
12580
    & ifmt_xor16_b_imm_G_16_8_dst16_16_8_An_relative_QI, { 0x76180000 }
12581
  },
12582
/* xor.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
12583
  {
12584
    { 0, 0, 0, 0 },
12585
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
12586
    & ifmt_xor16_b_imm_G_16_8_dst16_16_8_SB_relative_QI, { 0x761a0000 }
12587
  },
12588
/* xor.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
12589
  {
12590
    { 0, 0, 0, 0 },
12591
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
12592
    & ifmt_xor16_b_imm_G_16_8_dst16_16_8_FB_relative_QI, { 0x761b0000 }
12593
  },
12594
/* xor.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
12595
  {
12596
    { 0, 0, 0, 0 },
12597
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
12598
    & ifmt_xor16_b_imm_G_16_16_dst16_16_16_An_relative_QI, { 0x761c0000 }
12599
  },
12600
/* xor.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
12601
  {
12602
    { 0, 0, 0, 0 },
12603
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
12604
    & ifmt_xor16_b_imm_G_16_16_dst16_16_16_SB_relative_QI, { 0x761e0000 }
12605
  },
12606
/* xor.b${G} #${Imm-32-QI},${Dsp-16-u16} */
12607
  {
12608
    { 0, 0, 0, 0 },
12609
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } },
12610
    & ifmt_xor16_b_imm_G_16_16_dst16_16_16_absolute_QI, { 0x761f0000 }
12611
  },
12612
/* xchg.w r3,$Dst32RnUnprefixedHI */
12613
  {
12614
    { 0, 0, 0, 0 },
12615
    { { MNEM, ' ', 'r', '3', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
12616
    & ifmt_xchg32w_r3_dst32_Rn_direct_Unprefixed_HI, { 0xd90d }
12617
  },
12618
/* xchg.w r3,$Dst32AnUnprefixedHI */
12619
  {
12620
    { 0, 0, 0, 0 },
12621
    { { MNEM, ' ', 'r', '3', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
12622
    & ifmt_xchg32w_r3_dst32_An_direct_Unprefixed_HI, { 0xd18d }
12623
  },
12624
/* xchg.w r3,[$Dst32AnUnprefixed] */
12625
  {
12626
    { 0, 0, 0, 0 },
12627
    { { MNEM, ' ', 'r', '3', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
12628
    & ifmt_xchg32w_r3_dst32_An_indirect_Unprefixed_HI, { 0xd10d }
12629
  },
12630
/* xchg.w r3,${Dsp-16-u8}[$Dst32AnUnprefixed] */
12631
  {
12632
    { 0, 0, 0, 0 },
12633
    { { MNEM, ' ', 'r', '3', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
12634
    & ifmt_xchg32w_r3_dst32_16_8_An_relative_Unprefixed_HI, { 0xd30d00 }
12635
  },
12636
/* xchg.w r3,${Dsp-16-u16}[$Dst32AnUnprefixed] */
12637
  {
12638
    { 0, 0, 0, 0 },
12639
    { { MNEM, ' ', 'r', '3', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
12640
    & ifmt_xchg32w_r3_dst32_16_16_An_relative_Unprefixed_HI, { 0xd50d0000 }
12641
  },
12642
/* xchg.w r3,${Dsp-16-u24}[$Dst32AnUnprefixed] */
12643
  {
12644
    { 0, 0, 0, 0 },
12645
    { { MNEM, ' ', 'r', '3', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
12646
    & ifmt_xchg32w_r3_dst32_16_24_An_relative_Unprefixed_HI, { 0xd70d0000 }
12647
  },
12648
/* xchg.w r3,${Dsp-16-u8}[sb] */
12649
  {
12650
    { 0, 0, 0, 0 },
12651
    { { MNEM, ' ', 'r', '3', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
12652
    & ifmt_xchg32w_r3_dst32_16_8_SB_relative_Unprefixed_HI, { 0xd38d00 }
12653
  },
12654
/* xchg.w r3,${Dsp-16-u16}[sb] */
12655
  {
12656
    { 0, 0, 0, 0 },
12657
    { { MNEM, ' ', 'r', '3', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
12658
    & ifmt_xchg32w_r3_dst32_16_16_SB_relative_Unprefixed_HI, { 0xd58d0000 }
12659
  },
12660
/* xchg.w r3,${Dsp-16-s8}[fb] */
12661
  {
12662
    { 0, 0, 0, 0 },
12663
    { { MNEM, ' ', 'r', '3', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
12664
    & ifmt_xchg32w_r3_dst32_16_8_FB_relative_Unprefixed_HI, { 0xd3cd00 }
12665
  },
12666
/* xchg.w r3,${Dsp-16-s16}[fb] */
12667
  {
12668
    { 0, 0, 0, 0 },
12669
    { { MNEM, ' ', 'r', '3', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
12670
    & ifmt_xchg32w_r3_dst32_16_16_FB_relative_Unprefixed_HI, { 0xd5cd0000 }
12671
  },
12672
/* xchg.w r3,${Dsp-16-u16} */
12673
  {
12674
    { 0, 0, 0, 0 },
12675
    { { MNEM, ' ', 'r', '3', ',', OP (DSP_16_U16), 0 } },
12676
    & ifmt_xchg32w_r3_dst32_16_16_absolute_Unprefixed_HI, { 0xd7cd0000 }
12677
  },
12678
/* xchg.w r3,${Dsp-16-u24} */
12679
  {
12680
    { 0, 0, 0, 0 },
12681
    { { MNEM, ' ', 'r', '3', ',', OP (DSP_16_U24), 0 } },
12682
    & ifmt_xchg32w_r3_dst32_16_24_absolute_Unprefixed_HI, { 0xd78d0000 }
12683
  },
12684
/* xchg.w r2,$Dst32RnUnprefixedHI */
12685
  {
12686
    { 0, 0, 0, 0 },
12687
    { { MNEM, ' ', 'r', '2', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
12688
    & ifmt_xchg32w_r3_dst32_Rn_direct_Unprefixed_HI, { 0xd90c }
12689
  },
12690
/* xchg.w r2,$Dst32AnUnprefixedHI */
12691
  {
12692
    { 0, 0, 0, 0 },
12693
    { { MNEM, ' ', 'r', '2', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
12694
    & ifmt_xchg32w_r3_dst32_An_direct_Unprefixed_HI, { 0xd18c }
12695
  },
12696
/* xchg.w r2,[$Dst32AnUnprefixed] */
12697
  {
12698
    { 0, 0, 0, 0 },
12699
    { { MNEM, ' ', 'r', '2', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
12700
    & ifmt_xchg32w_r3_dst32_An_indirect_Unprefixed_HI, { 0xd10c }
12701
  },
12702
/* xchg.w r2,${Dsp-16-u8}[$Dst32AnUnprefixed] */
12703
  {
12704
    { 0, 0, 0, 0 },
12705
    { { MNEM, ' ', 'r', '2', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
12706
    & ifmt_xchg32w_r3_dst32_16_8_An_relative_Unprefixed_HI, { 0xd30c00 }
12707
  },
12708
/* xchg.w r2,${Dsp-16-u16}[$Dst32AnUnprefixed] */
12709
  {
12710
    { 0, 0, 0, 0 },
12711
    { { MNEM, ' ', 'r', '2', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
12712
    & ifmt_xchg32w_r3_dst32_16_16_An_relative_Unprefixed_HI, { 0xd50c0000 }
12713
  },
12714
/* xchg.w r2,${Dsp-16-u24}[$Dst32AnUnprefixed] */
12715
  {
12716
    { 0, 0, 0, 0 },
12717
    { { MNEM, ' ', 'r', '2', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
12718
    & ifmt_xchg32w_r3_dst32_16_24_An_relative_Unprefixed_HI, { 0xd70c0000 }
12719
  },
12720
/* xchg.w r2,${Dsp-16-u8}[sb] */
12721
  {
12722
    { 0, 0, 0, 0 },
12723
    { { MNEM, ' ', 'r', '2', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
12724
    & ifmt_xchg32w_r3_dst32_16_8_SB_relative_Unprefixed_HI, { 0xd38c00 }
12725
  },
12726
/* xchg.w r2,${Dsp-16-u16}[sb] */
12727
  {
12728
    { 0, 0, 0, 0 },
12729
    { { MNEM, ' ', 'r', '2', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
12730
    & ifmt_xchg32w_r3_dst32_16_16_SB_relative_Unprefixed_HI, { 0xd58c0000 }
12731
  },
12732
/* xchg.w r2,${Dsp-16-s8}[fb] */
12733
  {
12734
    { 0, 0, 0, 0 },
12735
    { { MNEM, ' ', 'r', '2', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
12736
    & ifmt_xchg32w_r3_dst32_16_8_FB_relative_Unprefixed_HI, { 0xd3cc00 }
12737
  },
12738
/* xchg.w r2,${Dsp-16-s16}[fb] */
12739
  {
12740
    { 0, 0, 0, 0 },
12741
    { { MNEM, ' ', 'r', '2', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
12742
    & ifmt_xchg32w_r3_dst32_16_16_FB_relative_Unprefixed_HI, { 0xd5cc0000 }
12743
  },
12744
/* xchg.w r2,${Dsp-16-u16} */
12745
  {
12746
    { 0, 0, 0, 0 },
12747
    { { MNEM, ' ', 'r', '2', ',', OP (DSP_16_U16), 0 } },
12748
    & ifmt_xchg32w_r3_dst32_16_16_absolute_Unprefixed_HI, { 0xd7cc0000 }
12749
  },
12750
/* xchg.w r2,${Dsp-16-u24} */
12751
  {
12752
    { 0, 0, 0, 0 },
12753
    { { MNEM, ' ', 'r', '2', ',', OP (DSP_16_U24), 0 } },
12754
    & ifmt_xchg32w_r3_dst32_16_24_absolute_Unprefixed_HI, { 0xd78c0000 }
12755
  },
12756
/* xchg.w a1,$Dst32RnUnprefixedHI */
12757
  {
12758
    { 0, 0, 0, 0 },
12759
    { { MNEM, ' ', 'a', '1', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
12760
    & ifmt_xchg32w_r3_dst32_Rn_direct_Unprefixed_HI, { 0xd90b }
12761
  },
12762
/* xchg.w a1,$Dst32AnUnprefixedHI */
12763
  {
12764
    { 0, 0, 0, 0 },
12765
    { { MNEM, ' ', 'a', '1', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
12766
    & ifmt_xchg32w_r3_dst32_An_direct_Unprefixed_HI, { 0xd18b }
12767
  },
12768
/* xchg.w a1,[$Dst32AnUnprefixed] */
12769
  {
12770
    { 0, 0, 0, 0 },
12771
    { { MNEM, ' ', 'a', '1', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
12772
    & ifmt_xchg32w_r3_dst32_An_indirect_Unprefixed_HI, { 0xd10b }
12773
  },
12774
/* xchg.w a1,${Dsp-16-u8}[$Dst32AnUnprefixed] */
12775
  {
12776
    { 0, 0, 0, 0 },
12777
    { { MNEM, ' ', 'a', '1', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
12778
    & ifmt_xchg32w_r3_dst32_16_8_An_relative_Unprefixed_HI, { 0xd30b00 }
12779
  },
12780
/* xchg.w a1,${Dsp-16-u16}[$Dst32AnUnprefixed] */
12781
  {
12782
    { 0, 0, 0, 0 },
12783
    { { MNEM, ' ', 'a', '1', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
12784
    & ifmt_xchg32w_r3_dst32_16_16_An_relative_Unprefixed_HI, { 0xd50b0000 }
12785
  },
12786
/* xchg.w a1,${Dsp-16-u24}[$Dst32AnUnprefixed] */
12787
  {
12788
    { 0, 0, 0, 0 },
12789
    { { MNEM, ' ', 'a', '1', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
12790
    & ifmt_xchg32w_r3_dst32_16_24_An_relative_Unprefixed_HI, { 0xd70b0000 }
12791
  },
12792
/* xchg.w a1,${Dsp-16-u8}[sb] */
12793
  {
12794
    { 0, 0, 0, 0 },
12795
    { { MNEM, ' ', 'a', '1', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
12796
    & ifmt_xchg32w_r3_dst32_16_8_SB_relative_Unprefixed_HI, { 0xd38b00 }
12797
  },
12798
/* xchg.w a1,${Dsp-16-u16}[sb] */
12799
  {
12800
    { 0, 0, 0, 0 },
12801
    { { MNEM, ' ', 'a', '1', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
12802
    & ifmt_xchg32w_r3_dst32_16_16_SB_relative_Unprefixed_HI, { 0xd58b0000 }
12803
  },
12804
/* xchg.w a1,${Dsp-16-s8}[fb] */
12805
  {
12806
    { 0, 0, 0, 0 },
12807
    { { MNEM, ' ', 'a', '1', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
12808
    & ifmt_xchg32w_r3_dst32_16_8_FB_relative_Unprefixed_HI, { 0xd3cb00 }
12809
  },
12810
/* xchg.w a1,${Dsp-16-s16}[fb] */
12811
  {
12812
    { 0, 0, 0, 0 },
12813
    { { MNEM, ' ', 'a', '1', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
12814
    & ifmt_xchg32w_r3_dst32_16_16_FB_relative_Unprefixed_HI, { 0xd5cb0000 }
12815
  },
12816
/* xchg.w a1,${Dsp-16-u16} */
12817
  {
12818
    { 0, 0, 0, 0 },
12819
    { { MNEM, ' ', 'a', '1', ',', OP (DSP_16_U16), 0 } },
12820
    & ifmt_xchg32w_r3_dst32_16_16_absolute_Unprefixed_HI, { 0xd7cb0000 }
12821
  },
12822
/* xchg.w a1,${Dsp-16-u24} */
12823
  {
12824
    { 0, 0, 0, 0 },
12825
    { { MNEM, ' ', 'a', '1', ',', OP (DSP_16_U24), 0 } },
12826
    & ifmt_xchg32w_r3_dst32_16_24_absolute_Unprefixed_HI, { 0xd78b0000 }
12827
  },
12828
/* xchg.w a0,$Dst32RnUnprefixedHI */
12829
  {
12830
    { 0, 0, 0, 0 },
12831
    { { MNEM, ' ', 'a', '0', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
12832
    & ifmt_xchg32w_r3_dst32_Rn_direct_Unprefixed_HI, { 0xd90a }
12833
  },
12834
/* xchg.w a0,$Dst32AnUnprefixedHI */
12835
  {
12836
    { 0, 0, 0, 0 },
12837
    { { MNEM, ' ', 'a', '0', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
12838
    & ifmt_xchg32w_r3_dst32_An_direct_Unprefixed_HI, { 0xd18a }
12839
  },
12840
/* xchg.w a0,[$Dst32AnUnprefixed] */
12841
  {
12842
    { 0, 0, 0, 0 },
12843
    { { MNEM, ' ', 'a', '0', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
12844
    & ifmt_xchg32w_r3_dst32_An_indirect_Unprefixed_HI, { 0xd10a }
12845
  },
12846
/* xchg.w a0,${Dsp-16-u8}[$Dst32AnUnprefixed] */
12847
  {
12848
    { 0, 0, 0, 0 },
12849
    { { MNEM, ' ', 'a', '0', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
12850
    & ifmt_xchg32w_r3_dst32_16_8_An_relative_Unprefixed_HI, { 0xd30a00 }
12851
  },
12852
/* xchg.w a0,${Dsp-16-u16}[$Dst32AnUnprefixed] */
12853
  {
12854
    { 0, 0, 0, 0 },
12855
    { { MNEM, ' ', 'a', '0', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
12856
    & ifmt_xchg32w_r3_dst32_16_16_An_relative_Unprefixed_HI, { 0xd50a0000 }
12857
  },
12858
/* xchg.w a0,${Dsp-16-u24}[$Dst32AnUnprefixed] */
12859
  {
12860
    { 0, 0, 0, 0 },
12861
    { { MNEM, ' ', 'a', '0', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
12862
    & ifmt_xchg32w_r3_dst32_16_24_An_relative_Unprefixed_HI, { 0xd70a0000 }
12863
  },
12864
/* xchg.w a0,${Dsp-16-u8}[sb] */
12865
  {
12866
    { 0, 0, 0, 0 },
12867
    { { MNEM, ' ', 'a', '0', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
12868
    & ifmt_xchg32w_r3_dst32_16_8_SB_relative_Unprefixed_HI, { 0xd38a00 }
12869
  },
12870
/* xchg.w a0,${Dsp-16-u16}[sb] */
12871
  {
12872
    { 0, 0, 0, 0 },
12873
    { { MNEM, ' ', 'a', '0', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
12874
    & ifmt_xchg32w_r3_dst32_16_16_SB_relative_Unprefixed_HI, { 0xd58a0000 }
12875
  },
12876
/* xchg.w a0,${Dsp-16-s8}[fb] */
12877
  {
12878
    { 0, 0, 0, 0 },
12879
    { { MNEM, ' ', 'a', '0', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
12880
    & ifmt_xchg32w_r3_dst32_16_8_FB_relative_Unprefixed_HI, { 0xd3ca00 }
12881
  },
12882
/* xchg.w a0,${Dsp-16-s16}[fb] */
12883
  {
12884
    { 0, 0, 0, 0 },
12885
    { { MNEM, ' ', 'a', '0', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
12886
    & ifmt_xchg32w_r3_dst32_16_16_FB_relative_Unprefixed_HI, { 0xd5ca0000 }
12887
  },
12888
/* xchg.w a0,${Dsp-16-u16} */
12889
  {
12890
    { 0, 0, 0, 0 },
12891
    { { MNEM, ' ', 'a', '0', ',', OP (DSP_16_U16), 0 } },
12892
    & ifmt_xchg32w_r3_dst32_16_16_absolute_Unprefixed_HI, { 0xd7ca0000 }
12893
  },
12894
/* xchg.w a0,${Dsp-16-u24} */
12895
  {
12896
    { 0, 0, 0, 0 },
12897
    { { MNEM, ' ', 'a', '0', ',', OP (DSP_16_U24), 0 } },
12898
    & ifmt_xchg32w_r3_dst32_16_24_absolute_Unprefixed_HI, { 0xd78a0000 }
12899
  },
12900
/* xchg.w r1,$Dst32RnUnprefixedHI */
12901
  {
12902
    { 0, 0, 0, 0 },
12903
    { { MNEM, ' ', 'r', '1', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
12904
    & ifmt_xchg32w_r3_dst32_Rn_direct_Unprefixed_HI, { 0xd909 }
12905
  },
12906
/* xchg.w r1,$Dst32AnUnprefixedHI */
12907
  {
12908
    { 0, 0, 0, 0 },
12909
    { { MNEM, ' ', 'r', '1', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
12910
    & ifmt_xchg32w_r3_dst32_An_direct_Unprefixed_HI, { 0xd189 }
12911
  },
12912
/* xchg.w r1,[$Dst32AnUnprefixed] */
12913
  {
12914
    { 0, 0, 0, 0 },
12915
    { { MNEM, ' ', 'r', '1', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
12916
    & ifmt_xchg32w_r3_dst32_An_indirect_Unprefixed_HI, { 0xd109 }
12917
  },
12918
/* xchg.w r1,${Dsp-16-u8}[$Dst32AnUnprefixed] */
12919
  {
12920
    { 0, 0, 0, 0 },
12921
    { { MNEM, ' ', 'r', '1', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
12922
    & ifmt_xchg32w_r3_dst32_16_8_An_relative_Unprefixed_HI, { 0xd30900 }
12923
  },
12924
/* xchg.w r1,${Dsp-16-u16}[$Dst32AnUnprefixed] */
12925
  {
12926
    { 0, 0, 0, 0 },
12927
    { { MNEM, ' ', 'r', '1', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
12928
    & ifmt_xchg32w_r3_dst32_16_16_An_relative_Unprefixed_HI, { 0xd5090000 }
12929
  },
12930
/* xchg.w r1,${Dsp-16-u24}[$Dst32AnUnprefixed] */
12931
  {
12932
    { 0, 0, 0, 0 },
12933
    { { MNEM, ' ', 'r', '1', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
12934
    & ifmt_xchg32w_r3_dst32_16_24_An_relative_Unprefixed_HI, { 0xd7090000 }
12935
  },
12936
/* xchg.w r1,${Dsp-16-u8}[sb] */
12937
  {
12938
    { 0, 0, 0, 0 },
12939
    { { MNEM, ' ', 'r', '1', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
12940
    & ifmt_xchg32w_r3_dst32_16_8_SB_relative_Unprefixed_HI, { 0xd38900 }
12941
  },
12942
/* xchg.w r1,${Dsp-16-u16}[sb] */
12943
  {
12944
    { 0, 0, 0, 0 },
12945
    { { MNEM, ' ', 'r', '1', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
12946
    & ifmt_xchg32w_r3_dst32_16_16_SB_relative_Unprefixed_HI, { 0xd5890000 }
12947
  },
12948
/* xchg.w r1,${Dsp-16-s8}[fb] */
12949
  {
12950
    { 0, 0, 0, 0 },
12951
    { { MNEM, ' ', 'r', '1', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
12952
    & ifmt_xchg32w_r3_dst32_16_8_FB_relative_Unprefixed_HI, { 0xd3c900 }
12953
  },
12954
/* xchg.w r1,${Dsp-16-s16}[fb] */
12955
  {
12956
    { 0, 0, 0, 0 },
12957
    { { MNEM, ' ', 'r', '1', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
12958
    & ifmt_xchg32w_r3_dst32_16_16_FB_relative_Unprefixed_HI, { 0xd5c90000 }
12959
  },
12960
/* xchg.w r1,${Dsp-16-u16} */
12961
  {
12962
    { 0, 0, 0, 0 },
12963
    { { MNEM, ' ', 'r', '1', ',', OP (DSP_16_U16), 0 } },
12964
    & ifmt_xchg32w_r3_dst32_16_16_absolute_Unprefixed_HI, { 0xd7c90000 }
12965
  },
12966
/* xchg.w r1,${Dsp-16-u24} */
12967
  {
12968
    { 0, 0, 0, 0 },
12969
    { { MNEM, ' ', 'r', '1', ',', OP (DSP_16_U24), 0 } },
12970
    & ifmt_xchg32w_r3_dst32_16_24_absolute_Unprefixed_HI, { 0xd7890000 }
12971
  },
12972
/* xchg.w r0,$Dst32RnUnprefixedHI */
12973
  {
12974
    { 0, 0, 0, 0 },
12975
    { { MNEM, ' ', 'r', '0', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
12976
    & ifmt_xchg32w_r3_dst32_Rn_direct_Unprefixed_HI, { 0xd908 }
12977
  },
12978
/* xchg.w r0,$Dst32AnUnprefixedHI */
12979
  {
12980
    { 0, 0, 0, 0 },
12981
    { { MNEM, ' ', 'r', '0', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
12982
    & ifmt_xchg32w_r3_dst32_An_direct_Unprefixed_HI, { 0xd188 }
12983
  },
12984
/* xchg.w r0,[$Dst32AnUnprefixed] */
12985
  {
12986
    { 0, 0, 0, 0 },
12987
    { { MNEM, ' ', 'r', '0', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
12988
    & ifmt_xchg32w_r3_dst32_An_indirect_Unprefixed_HI, { 0xd108 }
12989
  },
12990
/* xchg.w r0,${Dsp-16-u8}[$Dst32AnUnprefixed] */
12991
  {
12992
    { 0, 0, 0, 0 },
12993
    { { MNEM, ' ', 'r', '0', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
12994
    & ifmt_xchg32w_r3_dst32_16_8_An_relative_Unprefixed_HI, { 0xd30800 }
12995
  },
12996
/* xchg.w r0,${Dsp-16-u16}[$Dst32AnUnprefixed] */
12997
  {
12998
    { 0, 0, 0, 0 },
12999
    { { MNEM, ' ', 'r', '0', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
13000
    & ifmt_xchg32w_r3_dst32_16_16_An_relative_Unprefixed_HI, { 0xd5080000 }
13001
  },
13002
/* xchg.w r0,${Dsp-16-u24}[$Dst32AnUnprefixed] */
13003
  {
13004
    { 0, 0, 0, 0 },
13005
    { { MNEM, ' ', 'r', '0', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
13006
    & ifmt_xchg32w_r3_dst32_16_24_An_relative_Unprefixed_HI, { 0xd7080000 }
13007
  },
13008
/* xchg.w r0,${Dsp-16-u8}[sb] */
13009
  {
13010
    { 0, 0, 0, 0 },
13011
    { { MNEM, ' ', 'r', '0', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
13012
    & ifmt_xchg32w_r3_dst32_16_8_SB_relative_Unprefixed_HI, { 0xd38800 }
13013
  },
13014
/* xchg.w r0,${Dsp-16-u16}[sb] */
13015
  {
13016
    { 0, 0, 0, 0 },
13017
    { { MNEM, ' ', 'r', '0', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
13018
    & ifmt_xchg32w_r3_dst32_16_16_SB_relative_Unprefixed_HI, { 0xd5880000 }
13019
  },
13020
/* xchg.w r0,${Dsp-16-s8}[fb] */
13021
  {
13022
    { 0, 0, 0, 0 },
13023
    { { MNEM, ' ', 'r', '0', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
13024
    & ifmt_xchg32w_r3_dst32_16_8_FB_relative_Unprefixed_HI, { 0xd3c800 }
13025
  },
13026
/* xchg.w r0,${Dsp-16-s16}[fb] */
13027
  {
13028
    { 0, 0, 0, 0 },
13029
    { { MNEM, ' ', 'r', '0', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
13030
    & ifmt_xchg32w_r3_dst32_16_16_FB_relative_Unprefixed_HI, { 0xd5c80000 }
13031
  },
13032
/* xchg.w r0,${Dsp-16-u16} */
13033
  {
13034
    { 0, 0, 0, 0 },
13035
    { { MNEM, ' ', 'r', '0', ',', OP (DSP_16_U16), 0 } },
13036
    & ifmt_xchg32w_r3_dst32_16_16_absolute_Unprefixed_HI, { 0xd7c80000 }
13037
  },
13038
/* xchg.w r0,${Dsp-16-u24} */
13039
  {
13040
    { 0, 0, 0, 0 },
13041
    { { MNEM, ' ', 'r', '0', ',', OP (DSP_16_U24), 0 } },
13042
    & ifmt_xchg32w_r3_dst32_16_24_absolute_Unprefixed_HI, { 0xd7880000 }
13043
  },
13044
/* xchg.b r1h,$Dst32RnUnprefixedQI */
13045
  {
13046
    { 0, 0, 0, 0 },
13047
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
13048
    & ifmt_xchg32b_r1h_dst32_Rn_direct_Unprefixed_QI, { 0xd80d }
13049
  },
13050
/* xchg.b r1h,$Dst32AnUnprefixedQI */
13051
  {
13052
    { 0, 0, 0, 0 },
13053
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
13054
    & ifmt_xchg32b_r1h_dst32_An_direct_Unprefixed_QI, { 0xd08d }
13055
  },
13056
/* xchg.b r1h,[$Dst32AnUnprefixed] */
13057
  {
13058
    { 0, 0, 0, 0 },
13059
    { { MNEM, ' ', 'r', '1', 'h', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
13060
    & ifmt_xchg32b_r1h_dst32_An_indirect_Unprefixed_QI, { 0xd00d }
13061
  },
13062
/* xchg.b r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */
13063
  {
13064
    { 0, 0, 0, 0 },
13065
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
13066
    & ifmt_xchg32b_r1h_dst32_16_8_An_relative_Unprefixed_QI, { 0xd20d00 }
13067
  },
13068
/* xchg.b r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */
13069
  {
13070
    { 0, 0, 0, 0 },
13071
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
13072
    & ifmt_xchg32b_r1h_dst32_16_16_An_relative_Unprefixed_QI, { 0xd40d0000 }
13073
  },
13074
/* xchg.b r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */
13075
  {
13076
    { 0, 0, 0, 0 },
13077
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
13078
    & ifmt_xchg32b_r1h_dst32_16_24_An_relative_Unprefixed_QI, { 0xd60d0000 }
13079
  },
13080
/* xchg.b r1h,${Dsp-16-u8}[sb] */
13081
  {
13082
    { 0, 0, 0, 0 },
13083
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
13084
    & ifmt_xchg32b_r1h_dst32_16_8_SB_relative_Unprefixed_QI, { 0xd28d00 }
13085
  },
13086
/* xchg.b r1h,${Dsp-16-u16}[sb] */
13087
  {
13088
    { 0, 0, 0, 0 },
13089
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
13090
    & ifmt_xchg32b_r1h_dst32_16_16_SB_relative_Unprefixed_QI, { 0xd48d0000 }
13091
  },
13092
/* xchg.b r1h,${Dsp-16-s8}[fb] */
13093
  {
13094
    { 0, 0, 0, 0 },
13095
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
13096
    & ifmt_xchg32b_r1h_dst32_16_8_FB_relative_Unprefixed_QI, { 0xd2cd00 }
13097
  },
13098
/* xchg.b r1h,${Dsp-16-s16}[fb] */
13099
  {
13100
    { 0, 0, 0, 0 },
13101
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
13102
    & ifmt_xchg32b_r1h_dst32_16_16_FB_relative_Unprefixed_QI, { 0xd4cd0000 }
13103
  },
13104
/* xchg.b r1h,${Dsp-16-u16} */
13105
  {
13106
    { 0, 0, 0, 0 },
13107
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), 0 } },
13108
    & ifmt_xchg32b_r1h_dst32_16_16_absolute_Unprefixed_QI, { 0xd6cd0000 }
13109
  },
13110
/* xchg.b r1h,${Dsp-16-u24} */
13111
  {
13112
    { 0, 0, 0, 0 },
13113
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U24), 0 } },
13114
    & ifmt_xchg32b_r1h_dst32_16_24_absolute_Unprefixed_QI, { 0xd68d0000 }
13115
  },
13116
/* xchg.b r0h,$Dst32RnUnprefixedQI */
13117
  {
13118
    { 0, 0, 0, 0 },
13119
    { { MNEM, ' ', 'r', '0', 'h', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
13120
    & ifmt_xchg32b_r1h_dst32_Rn_direct_Unprefixed_QI, { 0xd80c }
13121
  },
13122
/* xchg.b r0h,$Dst32AnUnprefixedQI */
13123
  {
13124
    { 0, 0, 0, 0 },
13125
    { { MNEM, ' ', 'r', '0', 'h', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
13126
    & ifmt_xchg32b_r1h_dst32_An_direct_Unprefixed_QI, { 0xd08c }
13127
  },
13128
/* xchg.b r0h,[$Dst32AnUnprefixed] */
13129
  {
13130
    { 0, 0, 0, 0 },
13131
    { { MNEM, ' ', 'r', '0', 'h', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
13132
    & ifmt_xchg32b_r1h_dst32_An_indirect_Unprefixed_QI, { 0xd00c }
13133
  },
13134
/* xchg.b r0h,${Dsp-16-u8}[$Dst32AnUnprefixed] */
13135
  {
13136
    { 0, 0, 0, 0 },
13137
    { { MNEM, ' ', 'r', '0', 'h', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
13138
    & ifmt_xchg32b_r1h_dst32_16_8_An_relative_Unprefixed_QI, { 0xd20c00 }
13139
  },
13140
/* xchg.b r0h,${Dsp-16-u16}[$Dst32AnUnprefixed] */
13141
  {
13142
    { 0, 0, 0, 0 },
13143
    { { MNEM, ' ', 'r', '0', 'h', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
13144
    & ifmt_xchg32b_r1h_dst32_16_16_An_relative_Unprefixed_QI, { 0xd40c0000 }
13145
  },
13146
/* xchg.b r0h,${Dsp-16-u24}[$Dst32AnUnprefixed] */
13147
  {
13148
    { 0, 0, 0, 0 },
13149
    { { MNEM, ' ', 'r', '0', 'h', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
13150
    & ifmt_xchg32b_r1h_dst32_16_24_An_relative_Unprefixed_QI, { 0xd60c0000 }
13151
  },
13152
/* xchg.b r0h,${Dsp-16-u8}[sb] */
13153
  {
13154
    { 0, 0, 0, 0 },
13155
    { { MNEM, ' ', 'r', '0', 'h', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
13156
    & ifmt_xchg32b_r1h_dst32_16_8_SB_relative_Unprefixed_QI, { 0xd28c00 }
13157
  },
13158
/* xchg.b r0h,${Dsp-16-u16}[sb] */
13159
  {
13160
    { 0, 0, 0, 0 },
13161
    { { MNEM, ' ', 'r', '0', 'h', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
13162
    & ifmt_xchg32b_r1h_dst32_16_16_SB_relative_Unprefixed_QI, { 0xd48c0000 }
13163
  },
13164
/* xchg.b r0h,${Dsp-16-s8}[fb] */
13165
  {
13166
    { 0, 0, 0, 0 },
13167
    { { MNEM, ' ', 'r', '0', 'h', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
13168
    & ifmt_xchg32b_r1h_dst32_16_8_FB_relative_Unprefixed_QI, { 0xd2cc00 }
13169
  },
13170
/* xchg.b r0h,${Dsp-16-s16}[fb] */
13171
  {
13172
    { 0, 0, 0, 0 },
13173
    { { MNEM, ' ', 'r', '0', 'h', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
13174
    & ifmt_xchg32b_r1h_dst32_16_16_FB_relative_Unprefixed_QI, { 0xd4cc0000 }
13175
  },
13176
/* xchg.b r0h,${Dsp-16-u16} */
13177
  {
13178
    { 0, 0, 0, 0 },
13179
    { { MNEM, ' ', 'r', '0', 'h', ',', OP (DSP_16_U16), 0 } },
13180
    & ifmt_xchg32b_r1h_dst32_16_16_absolute_Unprefixed_QI, { 0xd6cc0000 }
13181
  },
13182
/* xchg.b r0h,${Dsp-16-u24} */
13183
  {
13184
    { 0, 0, 0, 0 },
13185
    { { MNEM, ' ', 'r', '0', 'h', ',', OP (DSP_16_U24), 0 } },
13186
    & ifmt_xchg32b_r1h_dst32_16_24_absolute_Unprefixed_QI, { 0xd68c0000 }
13187
  },
13188
/* xchg.b a1,$Dst32RnUnprefixedQI */
13189
  {
13190
    { 0, 0, 0, 0 },
13191
    { { MNEM, ' ', 'a', '1', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
13192
    & ifmt_xchg32b_r1h_dst32_Rn_direct_Unprefixed_QI, { 0xd80b }
13193
  },
13194
/* xchg.b a1,$Dst32AnUnprefixedQI */
13195
  {
13196
    { 0, 0, 0, 0 },
13197
    { { MNEM, ' ', 'a', '1', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
13198
    & ifmt_xchg32b_r1h_dst32_An_direct_Unprefixed_QI, { 0xd08b }
13199
  },
13200
/* xchg.b a1,[$Dst32AnUnprefixed] */
13201
  {
13202
    { 0, 0, 0, 0 },
13203
    { { MNEM, ' ', 'a', '1', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
13204
    & ifmt_xchg32b_r1h_dst32_An_indirect_Unprefixed_QI, { 0xd00b }
13205
  },
13206
/* xchg.b a1,${Dsp-16-u8}[$Dst32AnUnprefixed] */
13207
  {
13208
    { 0, 0, 0, 0 },
13209
    { { MNEM, ' ', 'a', '1', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
13210
    & ifmt_xchg32b_r1h_dst32_16_8_An_relative_Unprefixed_QI, { 0xd20b00 }
13211
  },
13212
/* xchg.b a1,${Dsp-16-u16}[$Dst32AnUnprefixed] */
13213
  {
13214
    { 0, 0, 0, 0 },
13215
    { { MNEM, ' ', 'a', '1', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
13216
    & ifmt_xchg32b_r1h_dst32_16_16_An_relative_Unprefixed_QI, { 0xd40b0000 }
13217
  },
13218
/* xchg.b a1,${Dsp-16-u24}[$Dst32AnUnprefixed] */
13219
  {
13220
    { 0, 0, 0, 0 },
13221
    { { MNEM, ' ', 'a', '1', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
13222
    & ifmt_xchg32b_r1h_dst32_16_24_An_relative_Unprefixed_QI, { 0xd60b0000 }
13223
  },
13224
/* xchg.b a1,${Dsp-16-u8}[sb] */
13225
  {
13226
    { 0, 0, 0, 0 },
13227
    { { MNEM, ' ', 'a', '1', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
13228
    & ifmt_xchg32b_r1h_dst32_16_8_SB_relative_Unprefixed_QI, { 0xd28b00 }
13229
  },
13230
/* xchg.b a1,${Dsp-16-u16}[sb] */
13231
  {
13232
    { 0, 0, 0, 0 },
13233
    { { MNEM, ' ', 'a', '1', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
13234
    & ifmt_xchg32b_r1h_dst32_16_16_SB_relative_Unprefixed_QI, { 0xd48b0000 }
13235
  },
13236
/* xchg.b a1,${Dsp-16-s8}[fb] */
13237
  {
13238
    { 0, 0, 0, 0 },
13239
    { { MNEM, ' ', 'a', '1', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
13240
    & ifmt_xchg32b_r1h_dst32_16_8_FB_relative_Unprefixed_QI, { 0xd2cb00 }
13241
  },
13242
/* xchg.b a1,${Dsp-16-s16}[fb] */
13243
  {
13244
    { 0, 0, 0, 0 },
13245
    { { MNEM, ' ', 'a', '1', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
13246
    & ifmt_xchg32b_r1h_dst32_16_16_FB_relative_Unprefixed_QI, { 0xd4cb0000 }
13247
  },
13248
/* xchg.b a1,${Dsp-16-u16} */
13249
  {
13250
    { 0, 0, 0, 0 },
13251
    { { MNEM, ' ', 'a', '1', ',', OP (DSP_16_U16), 0 } },
13252
    & ifmt_xchg32b_r1h_dst32_16_16_absolute_Unprefixed_QI, { 0xd6cb0000 }
13253
  },
13254
/* xchg.b a1,${Dsp-16-u24} */
13255
  {
13256
    { 0, 0, 0, 0 },
13257
    { { MNEM, ' ', 'a', '1', ',', OP (DSP_16_U24), 0 } },
13258
    & ifmt_xchg32b_r1h_dst32_16_24_absolute_Unprefixed_QI, { 0xd68b0000 }
13259
  },
13260
/* xchg.b a0,$Dst32RnUnprefixedQI */
13261
  {
13262
    { 0, 0, 0, 0 },
13263
    { { MNEM, ' ', 'a', '0', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
13264
    & ifmt_xchg32b_r1h_dst32_Rn_direct_Unprefixed_QI, { 0xd80a }
13265
  },
13266
/* xchg.b a0,$Dst32AnUnprefixedQI */
13267
  {
13268
    { 0, 0, 0, 0 },
13269
    { { MNEM, ' ', 'a', '0', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
13270
    & ifmt_xchg32b_r1h_dst32_An_direct_Unprefixed_QI, { 0xd08a }
13271
  },
13272
/* xchg.b a0,[$Dst32AnUnprefixed] */
13273
  {
13274
    { 0, 0, 0, 0 },
13275
    { { MNEM, ' ', 'a', '0', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
13276
    & ifmt_xchg32b_r1h_dst32_An_indirect_Unprefixed_QI, { 0xd00a }
13277
  },
13278
/* xchg.b a0,${Dsp-16-u8}[$Dst32AnUnprefixed] */
13279
  {
13280
    { 0, 0, 0, 0 },
13281
    { { MNEM, ' ', 'a', '0', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
13282
    & ifmt_xchg32b_r1h_dst32_16_8_An_relative_Unprefixed_QI, { 0xd20a00 }
13283
  },
13284
/* xchg.b a0,${Dsp-16-u16}[$Dst32AnUnprefixed] */
13285
  {
13286
    { 0, 0, 0, 0 },
13287
    { { MNEM, ' ', 'a', '0', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
13288
    & ifmt_xchg32b_r1h_dst32_16_16_An_relative_Unprefixed_QI, { 0xd40a0000 }
13289
  },
13290
/* xchg.b a0,${Dsp-16-u24}[$Dst32AnUnprefixed] */
13291
  {
13292
    { 0, 0, 0, 0 },
13293
    { { MNEM, ' ', 'a', '0', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
13294
    & ifmt_xchg32b_r1h_dst32_16_24_An_relative_Unprefixed_QI, { 0xd60a0000 }
13295
  },
13296
/* xchg.b a0,${Dsp-16-u8}[sb] */
13297
  {
13298
    { 0, 0, 0, 0 },
13299
    { { MNEM, ' ', 'a', '0', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
13300
    & ifmt_xchg32b_r1h_dst32_16_8_SB_relative_Unprefixed_QI, { 0xd28a00 }
13301
  },
13302
/* xchg.b a0,${Dsp-16-u16}[sb] */
13303
  {
13304
    { 0, 0, 0, 0 },
13305
    { { MNEM, ' ', 'a', '0', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
13306
    & ifmt_xchg32b_r1h_dst32_16_16_SB_relative_Unprefixed_QI, { 0xd48a0000 }
13307
  },
13308
/* xchg.b a0,${Dsp-16-s8}[fb] */
13309
  {
13310
    { 0, 0, 0, 0 },
13311
    { { MNEM, ' ', 'a', '0', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
13312
    & ifmt_xchg32b_r1h_dst32_16_8_FB_relative_Unprefixed_QI, { 0xd2ca00 }
13313
  },
13314
/* xchg.b a0,${Dsp-16-s16}[fb] */
13315
  {
13316
    { 0, 0, 0, 0 },
13317
    { { MNEM, ' ', 'a', '0', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
13318
    & ifmt_xchg32b_r1h_dst32_16_16_FB_relative_Unprefixed_QI, { 0xd4ca0000 }
13319
  },
13320
/* xchg.b a0,${Dsp-16-u16} */
13321
  {
13322
    { 0, 0, 0, 0 },
13323
    { { MNEM, ' ', 'a', '0', ',', OP (DSP_16_U16), 0 } },
13324
    & ifmt_xchg32b_r1h_dst32_16_16_absolute_Unprefixed_QI, { 0xd6ca0000 }
13325
  },
13326
/* xchg.b a0,${Dsp-16-u24} */
13327
  {
13328
    { 0, 0, 0, 0 },
13329
    { { MNEM, ' ', 'a', '0', ',', OP (DSP_16_U24), 0 } },
13330
    & ifmt_xchg32b_r1h_dst32_16_24_absolute_Unprefixed_QI, { 0xd68a0000 }
13331
  },
13332
/* xchg.b r1l,$Dst32RnUnprefixedQI */
13333
  {
13334
    { 0, 0, 0, 0 },
13335
    { { MNEM, ' ', 'r', '1', 'l', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
13336
    & ifmt_xchg32b_r1h_dst32_Rn_direct_Unprefixed_QI, { 0xd809 }
13337
  },
13338
/* xchg.b r1l,$Dst32AnUnprefixedQI */
13339
  {
13340
    { 0, 0, 0, 0 },
13341
    { { MNEM, ' ', 'r', '1', 'l', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
13342
    & ifmt_xchg32b_r1h_dst32_An_direct_Unprefixed_QI, { 0xd089 }
13343
  },
13344
/* xchg.b r1l,[$Dst32AnUnprefixed] */
13345
  {
13346
    { 0, 0, 0, 0 },
13347
    { { MNEM, ' ', 'r', '1', 'l', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
13348
    & ifmt_xchg32b_r1h_dst32_An_indirect_Unprefixed_QI, { 0xd009 }
13349
  },
13350
/* xchg.b r1l,${Dsp-16-u8}[$Dst32AnUnprefixed] */
13351
  {
13352
    { 0, 0, 0, 0 },
13353
    { { MNEM, ' ', 'r', '1', 'l', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
13354
    & ifmt_xchg32b_r1h_dst32_16_8_An_relative_Unprefixed_QI, { 0xd20900 }
13355
  },
13356
/* xchg.b r1l,${Dsp-16-u16}[$Dst32AnUnprefixed] */
13357
  {
13358
    { 0, 0, 0, 0 },
13359
    { { MNEM, ' ', 'r', '1', 'l', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
13360
    & ifmt_xchg32b_r1h_dst32_16_16_An_relative_Unprefixed_QI, { 0xd4090000 }
13361
  },
13362
/* xchg.b r1l,${Dsp-16-u24}[$Dst32AnUnprefixed] */
13363
  {
13364
    { 0, 0, 0, 0 },
13365
    { { MNEM, ' ', 'r', '1', 'l', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
13366
    & ifmt_xchg32b_r1h_dst32_16_24_An_relative_Unprefixed_QI, { 0xd6090000 }
13367
  },
13368
/* xchg.b r1l,${Dsp-16-u8}[sb] */
13369
  {
13370
    { 0, 0, 0, 0 },
13371
    { { MNEM, ' ', 'r', '1', 'l', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
13372
    & ifmt_xchg32b_r1h_dst32_16_8_SB_relative_Unprefixed_QI, { 0xd28900 }
13373
  },
13374
/* xchg.b r1l,${Dsp-16-u16}[sb] */
13375
  {
13376
    { 0, 0, 0, 0 },
13377
    { { MNEM, ' ', 'r', '1', 'l', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
13378
    & ifmt_xchg32b_r1h_dst32_16_16_SB_relative_Unprefixed_QI, { 0xd4890000 }
13379
  },
13380
/* xchg.b r1l,${Dsp-16-s8}[fb] */
13381
  {
13382
    { 0, 0, 0, 0 },
13383
    { { MNEM, ' ', 'r', '1', 'l', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
13384
    & ifmt_xchg32b_r1h_dst32_16_8_FB_relative_Unprefixed_QI, { 0xd2c900 }
13385
  },
13386
/* xchg.b r1l,${Dsp-16-s16}[fb] */
13387
  {
13388
    { 0, 0, 0, 0 },
13389
    { { MNEM, ' ', 'r', '1', 'l', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
13390
    & ifmt_xchg32b_r1h_dst32_16_16_FB_relative_Unprefixed_QI, { 0xd4c90000 }
13391
  },
13392
/* xchg.b r1l,${Dsp-16-u16} */
13393
  {
13394
    { 0, 0, 0, 0 },
13395
    { { MNEM, ' ', 'r', '1', 'l', ',', OP (DSP_16_U16), 0 } },
13396
    & ifmt_xchg32b_r1h_dst32_16_16_absolute_Unprefixed_QI, { 0xd6c90000 }
13397
  },
13398
/* xchg.b r1l,${Dsp-16-u24} */
13399
  {
13400
    { 0, 0, 0, 0 },
13401
    { { MNEM, ' ', 'r', '1', 'l', ',', OP (DSP_16_U24), 0 } },
13402
    & ifmt_xchg32b_r1h_dst32_16_24_absolute_Unprefixed_QI, { 0xd6890000 }
13403
  },
13404
/* xchg.b r0l,$Dst32RnUnprefixedQI */
13405
  {
13406
    { 0, 0, 0, 0 },
13407
    { { MNEM, ' ', 'r', '0', 'l', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
13408
    & ifmt_xchg32b_r1h_dst32_Rn_direct_Unprefixed_QI, { 0xd808 }
13409
  },
13410
/* xchg.b r0l,$Dst32AnUnprefixedQI */
13411
  {
13412
    { 0, 0, 0, 0 },
13413
    { { MNEM, ' ', 'r', '0', 'l', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
13414
    & ifmt_xchg32b_r1h_dst32_An_direct_Unprefixed_QI, { 0xd088 }
13415
  },
13416
/* xchg.b r0l,[$Dst32AnUnprefixed] */
13417
  {
13418
    { 0, 0, 0, 0 },
13419
    { { MNEM, ' ', 'r', '0', 'l', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
13420
    & ifmt_xchg32b_r1h_dst32_An_indirect_Unprefixed_QI, { 0xd008 }
13421
  },
13422
/* xchg.b r0l,${Dsp-16-u8}[$Dst32AnUnprefixed] */
13423
  {
13424
    { 0, 0, 0, 0 },
13425
    { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
13426
    & ifmt_xchg32b_r1h_dst32_16_8_An_relative_Unprefixed_QI, { 0xd20800 }
13427
  },
13428
/* xchg.b r0l,${Dsp-16-u16}[$Dst32AnUnprefixed] */
13429
  {
13430
    { 0, 0, 0, 0 },
13431
    { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
13432
    & ifmt_xchg32b_r1h_dst32_16_16_An_relative_Unprefixed_QI, { 0xd4080000 }
13433
  },
13434
/* xchg.b r0l,${Dsp-16-u24}[$Dst32AnUnprefixed] */
13435
  {
13436
    { 0, 0, 0, 0 },
13437
    { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
13438
    & ifmt_xchg32b_r1h_dst32_16_24_An_relative_Unprefixed_QI, { 0xd6080000 }
13439
  },
13440
/* xchg.b r0l,${Dsp-16-u8}[sb] */
13441
  {
13442
    { 0, 0, 0, 0 },
13443
    { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
13444
    & ifmt_xchg32b_r1h_dst32_16_8_SB_relative_Unprefixed_QI, { 0xd28800 }
13445
  },
13446
/* xchg.b r0l,${Dsp-16-u16}[sb] */
13447
  {
13448
    { 0, 0, 0, 0 },
13449
    { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
13450
    & ifmt_xchg32b_r1h_dst32_16_16_SB_relative_Unprefixed_QI, { 0xd4880000 }
13451
  },
13452
/* xchg.b r0l,${Dsp-16-s8}[fb] */
13453
  {
13454
    { 0, 0, 0, 0 },
13455
    { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
13456
    & ifmt_xchg32b_r1h_dst32_16_8_FB_relative_Unprefixed_QI, { 0xd2c800 }
13457
  },
13458
/* xchg.b r0l,${Dsp-16-s16}[fb] */
13459
  {
13460
    { 0, 0, 0, 0 },
13461
    { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
13462
    & ifmt_xchg32b_r1h_dst32_16_16_FB_relative_Unprefixed_QI, { 0xd4c80000 }
13463
  },
13464
/* xchg.b r0l,${Dsp-16-u16} */
13465
  {
13466
    { 0, 0, 0, 0 },
13467
    { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U16), 0 } },
13468
    & ifmt_xchg32b_r1h_dst32_16_16_absolute_Unprefixed_QI, { 0xd6c80000 }
13469
  },
13470
/* xchg.b r0l,${Dsp-16-u24} */
13471
  {
13472
    { 0, 0, 0, 0 },
13473
    { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U24), 0 } },
13474
    & ifmt_xchg32b_r1h_dst32_16_24_absolute_Unprefixed_QI, { 0xd6880000 }
13475
  },
13476
/* xchg.w r3,$Dst16RnHI */
13477
  {
13478
    { 0, 0, 0, 0 },
13479
    { { MNEM, ' ', 'r', '3', ',', OP (DST16RNHI), 0 } },
13480
    & ifmt_xchg16w_r3_dst16_Rn_direct_HI, { 0x7b30 }
13481
  },
13482
/* xchg.w r3,$Dst16AnHI */
13483
  {
13484
    { 0, 0, 0, 0 },
13485
    { { MNEM, ' ', 'r', '3', ',', OP (DST16ANHI), 0 } },
13486
    & ifmt_xchg16w_r3_dst16_An_direct_HI, { 0x7b34 }
13487
  },
13488
/* xchg.w r3,[$Dst16An] */
13489
  {
13490
    { 0, 0, 0, 0 },
13491
    { { MNEM, ' ', 'r', '3', ',', '[', OP (DST16AN), ']', 0 } },
13492
    & ifmt_xchg16w_r3_dst16_An_indirect_HI, { 0x7b36 }
13493
  },
13494
/* xchg.w r3,${Dsp-16-u8}[$Dst16An] */
13495
  {
13496
    { 0, 0, 0, 0 },
13497
    { { MNEM, ' ', 'r', '3', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
13498
    & ifmt_xchg16w_r3_dst16_16_8_An_relative_HI, { 0x7b3800 }
13499
  },
13500
/* xchg.w r3,${Dsp-16-u16}[$Dst16An] */
13501
  {
13502
    { 0, 0, 0, 0 },
13503
    { { MNEM, ' ', 'r', '3', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
13504
    & ifmt_xchg16w_r3_dst16_16_16_An_relative_HI, { 0x7b3c0000 }
13505
  },
13506
/* xchg.w r3,${Dsp-16-u8}[sb] */
13507
  {
13508
    { 0, 0, 0, 0 },
13509
    { { MNEM, ' ', 'r', '3', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
13510
    & ifmt_xchg16w_r3_dst16_16_8_SB_relative_HI, { 0x7b3a00 }
13511
  },
13512
/* xchg.w r3,${Dsp-16-u16}[sb] */
13513
  {
13514
    { 0, 0, 0, 0 },
13515
    { { MNEM, ' ', 'r', '3', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
13516
    & ifmt_xchg16w_r3_dst16_16_16_SB_relative_HI, { 0x7b3e0000 }
13517
  },
13518
/* xchg.w r3,${Dsp-16-s8}[fb] */
13519
  {
13520
    { 0, 0, 0, 0 },
13521
    { { MNEM, ' ', 'r', '3', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
13522
    & ifmt_xchg16w_r3_dst16_16_8_FB_relative_HI, { 0x7b3b00 }
13523
  },
13524
/* xchg.w r3,${Dsp-16-u16} */
13525
  {
13526
    { 0, 0, 0, 0 },
13527
    { { MNEM, ' ', 'r', '3', ',', OP (DSP_16_U16), 0 } },
13528
    & ifmt_xchg16w_r3_dst16_16_16_absolute_HI, { 0x7b3f0000 }
13529
  },
13530
/* xchg.w r2,$Dst16RnHI */
13531
  {
13532
    { 0, 0, 0, 0 },
13533
    { { MNEM, ' ', 'r', '2', ',', OP (DST16RNHI), 0 } },
13534
    & ifmt_xchg16w_r3_dst16_Rn_direct_HI, { 0x7b20 }
13535
  },
13536
/* xchg.w r2,$Dst16AnHI */
13537
  {
13538
    { 0, 0, 0, 0 },
13539
    { { MNEM, ' ', 'r', '2', ',', OP (DST16ANHI), 0 } },
13540
    & ifmt_xchg16w_r3_dst16_An_direct_HI, { 0x7b24 }
13541
  },
13542
/* xchg.w r2,[$Dst16An] */
13543
  {
13544
    { 0, 0, 0, 0 },
13545
    { { MNEM, ' ', 'r', '2', ',', '[', OP (DST16AN), ']', 0 } },
13546
    & ifmt_xchg16w_r3_dst16_An_indirect_HI, { 0x7b26 }
13547
  },
13548
/* xchg.w r2,${Dsp-16-u8}[$Dst16An] */
13549
  {
13550
    { 0, 0, 0, 0 },
13551
    { { MNEM, ' ', 'r', '2', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
13552
    & ifmt_xchg16w_r3_dst16_16_8_An_relative_HI, { 0x7b2800 }
13553
  },
13554
/* xchg.w r2,${Dsp-16-u16}[$Dst16An] */
13555
  {
13556
    { 0, 0, 0, 0 },
13557
    { { MNEM, ' ', 'r', '2', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
13558
    & ifmt_xchg16w_r3_dst16_16_16_An_relative_HI, { 0x7b2c0000 }
13559
  },
13560
/* xchg.w r2,${Dsp-16-u8}[sb] */
13561
  {
13562
    { 0, 0, 0, 0 },
13563
    { { MNEM, ' ', 'r', '2', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
13564
    & ifmt_xchg16w_r3_dst16_16_8_SB_relative_HI, { 0x7b2a00 }
13565
  },
13566
/* xchg.w r2,${Dsp-16-u16}[sb] */
13567
  {
13568
    { 0, 0, 0, 0 },
13569
    { { MNEM, ' ', 'r', '2', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
13570
    & ifmt_xchg16w_r3_dst16_16_16_SB_relative_HI, { 0x7b2e0000 }
13571
  },
13572
/* xchg.w r2,${Dsp-16-s8}[fb] */
13573
  {
13574
    { 0, 0, 0, 0 },
13575
    { { MNEM, ' ', 'r', '2', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
13576
    & ifmt_xchg16w_r3_dst16_16_8_FB_relative_HI, { 0x7b2b00 }
13577
  },
13578
/* xchg.w r2,${Dsp-16-u16} */
13579
  {
13580
    { 0, 0, 0, 0 },
13581
    { { MNEM, ' ', 'r', '2', ',', OP (DSP_16_U16), 0 } },
13582
    & ifmt_xchg16w_r3_dst16_16_16_absolute_HI, { 0x7b2f0000 }
13583
  },
13584
/* xchg.w r1,$Dst16RnHI */
13585
  {
13586
    { 0, 0, 0, 0 },
13587
    { { MNEM, ' ', 'r', '1', ',', OP (DST16RNHI), 0 } },
13588
    & ifmt_xchg16w_r3_dst16_Rn_direct_HI, { 0x7b10 }
13589
  },
13590
/* xchg.w r1,$Dst16AnHI */
13591
  {
13592
    { 0, 0, 0, 0 },
13593
    { { MNEM, ' ', 'r', '1', ',', OP (DST16ANHI), 0 } },
13594
    & ifmt_xchg16w_r3_dst16_An_direct_HI, { 0x7b14 }
13595
  },
13596
/* xchg.w r1,[$Dst16An] */
13597
  {
13598
    { 0, 0, 0, 0 },
13599
    { { MNEM, ' ', 'r', '1', ',', '[', OP (DST16AN), ']', 0 } },
13600
    & ifmt_xchg16w_r3_dst16_An_indirect_HI, { 0x7b16 }
13601
  },
13602
/* xchg.w r1,${Dsp-16-u8}[$Dst16An] */
13603
  {
13604
    { 0, 0, 0, 0 },
13605
    { { MNEM, ' ', 'r', '1', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
13606
    & ifmt_xchg16w_r3_dst16_16_8_An_relative_HI, { 0x7b1800 }
13607
  },
13608
/* xchg.w r1,${Dsp-16-u16}[$Dst16An] */
13609
  {
13610
    { 0, 0, 0, 0 },
13611
    { { MNEM, ' ', 'r', '1', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
13612
    & ifmt_xchg16w_r3_dst16_16_16_An_relative_HI, { 0x7b1c0000 }
13613
  },
13614
/* xchg.w r1,${Dsp-16-u8}[sb] */
13615
  {
13616
    { 0, 0, 0, 0 },
13617
    { { MNEM, ' ', 'r', '1', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
13618
    & ifmt_xchg16w_r3_dst16_16_8_SB_relative_HI, { 0x7b1a00 }
13619
  },
13620
/* xchg.w r1,${Dsp-16-u16}[sb] */
13621
  {
13622
    { 0, 0, 0, 0 },
13623
    { { MNEM, ' ', 'r', '1', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
13624
    & ifmt_xchg16w_r3_dst16_16_16_SB_relative_HI, { 0x7b1e0000 }
13625
  },
13626
/* xchg.w r1,${Dsp-16-s8}[fb] */
13627
  {
13628
    { 0, 0, 0, 0 },
13629
    { { MNEM, ' ', 'r', '1', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
13630
    & ifmt_xchg16w_r3_dst16_16_8_FB_relative_HI, { 0x7b1b00 }
13631
  },
13632
/* xchg.w r1,${Dsp-16-u16} */
13633
  {
13634
    { 0, 0, 0, 0 },
13635
    { { MNEM, ' ', 'r', '1', ',', OP (DSP_16_U16), 0 } },
13636
    & ifmt_xchg16w_r3_dst16_16_16_absolute_HI, { 0x7b1f0000 }
13637
  },
13638
/* xchg.w r0,$Dst16RnHI */
13639
  {
13640
    { 0, 0, 0, 0 },
13641
    { { MNEM, ' ', 'r', '0', ',', OP (DST16RNHI), 0 } },
13642
    & ifmt_xchg16w_r3_dst16_Rn_direct_HI, { 0x7b00 }
13643
  },
13644
/* xchg.w r0,$Dst16AnHI */
13645
  {
13646
    { 0, 0, 0, 0 },
13647
    { { MNEM, ' ', 'r', '0', ',', OP (DST16ANHI), 0 } },
13648
    & ifmt_xchg16w_r3_dst16_An_direct_HI, { 0x7b04 }
13649
  },
13650
/* xchg.w r0,[$Dst16An] */
13651
  {
13652
    { 0, 0, 0, 0 },
13653
    { { MNEM, ' ', 'r', '0', ',', '[', OP (DST16AN), ']', 0 } },
13654
    & ifmt_xchg16w_r3_dst16_An_indirect_HI, { 0x7b06 }
13655
  },
13656
/* xchg.w r0,${Dsp-16-u8}[$Dst16An] */
13657
  {
13658
    { 0, 0, 0, 0 },
13659
    { { MNEM, ' ', 'r', '0', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
13660
    & ifmt_xchg16w_r3_dst16_16_8_An_relative_HI, { 0x7b0800 }
13661
  },
13662
/* xchg.w r0,${Dsp-16-u16}[$Dst16An] */
13663
  {
13664
    { 0, 0, 0, 0 },
13665
    { { MNEM, ' ', 'r', '0', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
13666
    & ifmt_xchg16w_r3_dst16_16_16_An_relative_HI, { 0x7b0c0000 }
13667
  },
13668
/* xchg.w r0,${Dsp-16-u8}[sb] */
13669
  {
13670
    { 0, 0, 0, 0 },
13671
    { { MNEM, ' ', 'r', '0', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
13672
    & ifmt_xchg16w_r3_dst16_16_8_SB_relative_HI, { 0x7b0a00 }
13673
  },
13674
/* xchg.w r0,${Dsp-16-u16}[sb] */
13675
  {
13676
    { 0, 0, 0, 0 },
13677
    { { MNEM, ' ', 'r', '0', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
13678
    & ifmt_xchg16w_r3_dst16_16_16_SB_relative_HI, { 0x7b0e0000 }
13679
  },
13680
/* xchg.w r0,${Dsp-16-s8}[fb] */
13681
  {
13682
    { 0, 0, 0, 0 },
13683
    { { MNEM, ' ', 'r', '0', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
13684
    & ifmt_xchg16w_r3_dst16_16_8_FB_relative_HI, { 0x7b0b00 }
13685
  },
13686
/* xchg.w r0,${Dsp-16-u16} */
13687
  {
13688
    { 0, 0, 0, 0 },
13689
    { { MNEM, ' ', 'r', '0', ',', OP (DSP_16_U16), 0 } },
13690
    & ifmt_xchg16w_r3_dst16_16_16_absolute_HI, { 0x7b0f0000 }
13691
  },
13692
/* xchg.b r1h,$Dst16RnQI */
13693
  {
13694
    { 0, 0, 0, 0 },
13695
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST16RNQI), 0 } },
13696
    & ifmt_xchg16b_r1h_dst16_Rn_direct_QI, { 0x7a30 }
13697
  },
13698
/* xchg.b r1h,$Dst16AnQI */
13699
  {
13700
    { 0, 0, 0, 0 },
13701
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST16ANQI), 0 } },
13702
    & ifmt_xchg16b_r1h_dst16_An_direct_QI, { 0x7a34 }
13703
  },
13704
/* xchg.b r1h,[$Dst16An] */
13705
  {
13706
    { 0, 0, 0, 0 },
13707
    { { MNEM, ' ', 'r', '1', 'h', ',', '[', OP (DST16AN), ']', 0 } },
13708
    & ifmt_xchg16b_r1h_dst16_An_indirect_QI, { 0x7a36 }
13709
  },
13710
/* xchg.b r1h,${Dsp-16-u8}[$Dst16An] */
13711
  {
13712
    { 0, 0, 0, 0 },
13713
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
13714
    & ifmt_xchg16b_r1h_dst16_16_8_An_relative_QI, { 0x7a3800 }
13715
  },
13716
/* xchg.b r1h,${Dsp-16-u16}[$Dst16An] */
13717
  {
13718
    { 0, 0, 0, 0 },
13719
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
13720
    & ifmt_xchg16b_r1h_dst16_16_16_An_relative_QI, { 0x7a3c0000 }
13721
  },
13722
/* xchg.b r1h,${Dsp-16-u8}[sb] */
13723
  {
13724
    { 0, 0, 0, 0 },
13725
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
13726
    & ifmt_xchg16b_r1h_dst16_16_8_SB_relative_QI, { 0x7a3a00 }
13727
  },
13728
/* xchg.b r1h,${Dsp-16-u16}[sb] */
13729
  {
13730
    { 0, 0, 0, 0 },
13731
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
13732
    & ifmt_xchg16b_r1h_dst16_16_16_SB_relative_QI, { 0x7a3e0000 }
13733
  },
13734
/* xchg.b r1h,${Dsp-16-s8}[fb] */
13735
  {
13736
    { 0, 0, 0, 0 },
13737
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
13738
    & ifmt_xchg16b_r1h_dst16_16_8_FB_relative_QI, { 0x7a3b00 }
13739
  },
13740
/* xchg.b r1h,${Dsp-16-u16} */
13741
  {
13742
    { 0, 0, 0, 0 },
13743
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), 0 } },
13744
    & ifmt_xchg16b_r1h_dst16_16_16_absolute_QI, { 0x7a3f0000 }
13745
  },
13746
/* xchg.b r1l,$Dst16RnQI */
13747
  {
13748
    { 0, 0, 0, 0 },
13749
    { { MNEM, ' ', 'r', '1', 'l', ',', OP (DST16RNQI), 0 } },
13750
    & ifmt_xchg16b_r1h_dst16_Rn_direct_QI, { 0x7a20 }
13751
  },
13752
/* xchg.b r1l,$Dst16AnQI */
13753
  {
13754
    { 0, 0, 0, 0 },
13755
    { { MNEM, ' ', 'r', '1', 'l', ',', OP (DST16ANQI), 0 } },
13756
    & ifmt_xchg16b_r1h_dst16_An_direct_QI, { 0x7a24 }
13757
  },
13758
/* xchg.b r1l,[$Dst16An] */
13759
  {
13760
    { 0, 0, 0, 0 },
13761
    { { MNEM, ' ', 'r', '1', 'l', ',', '[', OP (DST16AN), ']', 0 } },
13762
    & ifmt_xchg16b_r1h_dst16_An_indirect_QI, { 0x7a26 }
13763
  },
13764
/* xchg.b r1l,${Dsp-16-u8}[$Dst16An] */
13765
  {
13766
    { 0, 0, 0, 0 },
13767
    { { MNEM, ' ', 'r', '1', 'l', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
13768
    & ifmt_xchg16b_r1h_dst16_16_8_An_relative_QI, { 0x7a2800 }
13769
  },
13770
/* xchg.b r1l,${Dsp-16-u16}[$Dst16An] */
13771
  {
13772
    { 0, 0, 0, 0 },
13773
    { { MNEM, ' ', 'r', '1', 'l', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
13774
    & ifmt_xchg16b_r1h_dst16_16_16_An_relative_QI, { 0x7a2c0000 }
13775
  },
13776
/* xchg.b r1l,${Dsp-16-u8}[sb] */
13777
  {
13778
    { 0, 0, 0, 0 },
13779
    { { MNEM, ' ', 'r', '1', 'l', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
13780
    & ifmt_xchg16b_r1h_dst16_16_8_SB_relative_QI, { 0x7a2a00 }
13781
  },
13782
/* xchg.b r1l,${Dsp-16-u16}[sb] */
13783
  {
13784
    { 0, 0, 0, 0 },
13785
    { { MNEM, ' ', 'r', '1', 'l', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
13786
    & ifmt_xchg16b_r1h_dst16_16_16_SB_relative_QI, { 0x7a2e0000 }
13787
  },
13788
/* xchg.b r1l,${Dsp-16-s8}[fb] */
13789
  {
13790
    { 0, 0, 0, 0 },
13791
    { { MNEM, ' ', 'r', '1', 'l', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
13792
    & ifmt_xchg16b_r1h_dst16_16_8_FB_relative_QI, { 0x7a2b00 }
13793
  },
13794
/* xchg.b r1l,${Dsp-16-u16} */
13795
  {
13796
    { 0, 0, 0, 0 },
13797
    { { MNEM, ' ', 'r', '1', 'l', ',', OP (DSP_16_U16), 0 } },
13798
    & ifmt_xchg16b_r1h_dst16_16_16_absolute_QI, { 0x7a2f0000 }
13799
  },
13800
/* xchg.b r0h,$Dst16RnQI */
13801
  {
13802
    { 0, 0, 0, 0 },
13803
    { { MNEM, ' ', 'r', '0', 'h', ',', OP (DST16RNQI), 0 } },
13804
    & ifmt_xchg16b_r1h_dst16_Rn_direct_QI, { 0x7a10 }
13805
  },
13806
/* xchg.b r0h,$Dst16AnQI */
13807
  {
13808
    { 0, 0, 0, 0 },
13809
    { { MNEM, ' ', 'r', '0', 'h', ',', OP (DST16ANQI), 0 } },
13810
    & ifmt_xchg16b_r1h_dst16_An_direct_QI, { 0x7a14 }
13811
  },
13812
/* xchg.b r0h,[$Dst16An] */
13813
  {
13814
    { 0, 0, 0, 0 },
13815
    { { MNEM, ' ', 'r', '0', 'h', ',', '[', OP (DST16AN), ']', 0 } },
13816
    & ifmt_xchg16b_r1h_dst16_An_indirect_QI, { 0x7a16 }
13817
  },
13818
/* xchg.b r0h,${Dsp-16-u8}[$Dst16An] */
13819
  {
13820
    { 0, 0, 0, 0 },
13821
    { { MNEM, ' ', 'r', '0', 'h', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
13822
    & ifmt_xchg16b_r1h_dst16_16_8_An_relative_QI, { 0x7a1800 }
13823
  },
13824
/* xchg.b r0h,${Dsp-16-u16}[$Dst16An] */
13825
  {
13826
    { 0, 0, 0, 0 },
13827
    { { MNEM, ' ', 'r', '0', 'h', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
13828
    & ifmt_xchg16b_r1h_dst16_16_16_An_relative_QI, { 0x7a1c0000 }
13829
  },
13830
/* xchg.b r0h,${Dsp-16-u8}[sb] */
13831
  {
13832
    { 0, 0, 0, 0 },
13833
    { { MNEM, ' ', 'r', '0', 'h', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
13834
    & ifmt_xchg16b_r1h_dst16_16_8_SB_relative_QI, { 0x7a1a00 }
13835
  },
13836
/* xchg.b r0h,${Dsp-16-u16}[sb] */
13837
  {
13838
    { 0, 0, 0, 0 },
13839
    { { MNEM, ' ', 'r', '0', 'h', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
13840
    & ifmt_xchg16b_r1h_dst16_16_16_SB_relative_QI, { 0x7a1e0000 }
13841
  },
13842
/* xchg.b r0h,${Dsp-16-s8}[fb] */
13843
  {
13844
    { 0, 0, 0, 0 },
13845
    { { MNEM, ' ', 'r', '0', 'h', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
13846
    & ifmt_xchg16b_r1h_dst16_16_8_FB_relative_QI, { 0x7a1b00 }
13847
  },
13848
/* xchg.b r0h,${Dsp-16-u16} */
13849
  {
13850
    { 0, 0, 0, 0 },
13851
    { { MNEM, ' ', 'r', '0', 'h', ',', OP (DSP_16_U16), 0 } },
13852
    & ifmt_xchg16b_r1h_dst16_16_16_absolute_QI, { 0x7a1f0000 }
13853
  },
13854
/* xchg.b r0l,$Dst16RnQI */
13855
  {
13856
    { 0, 0, 0, 0 },
13857
    { { MNEM, ' ', 'r', '0', 'l', ',', OP (DST16RNQI), 0 } },
13858
    & ifmt_xchg16b_r1h_dst16_Rn_direct_QI, { 0x7a00 }
13859
  },
13860
/* xchg.b r0l,$Dst16AnQI */
13861
  {
13862
    { 0, 0, 0, 0 },
13863
    { { MNEM, ' ', 'r', '0', 'l', ',', OP (DST16ANQI), 0 } },
13864
    & ifmt_xchg16b_r1h_dst16_An_direct_QI, { 0x7a04 }
13865
  },
13866
/* xchg.b r0l,[$Dst16An] */
13867
  {
13868
    { 0, 0, 0, 0 },
13869
    { { MNEM, ' ', 'r', '0', 'l', ',', '[', OP (DST16AN), ']', 0 } },
13870
    & ifmt_xchg16b_r1h_dst16_An_indirect_QI, { 0x7a06 }
13871
  },
13872
/* xchg.b r0l,${Dsp-16-u8}[$Dst16An] */
13873
  {
13874
    { 0, 0, 0, 0 },
13875
    { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
13876
    & ifmt_xchg16b_r1h_dst16_16_8_An_relative_QI, { 0x7a0800 }
13877
  },
13878
/* xchg.b r0l,${Dsp-16-u16}[$Dst16An] */
13879
  {
13880
    { 0, 0, 0, 0 },
13881
    { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
13882
    & ifmt_xchg16b_r1h_dst16_16_16_An_relative_QI, { 0x7a0c0000 }
13883
  },
13884
/* xchg.b r0l,${Dsp-16-u8}[sb] */
13885
  {
13886
    { 0, 0, 0, 0 },
13887
    { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
13888
    & ifmt_xchg16b_r1h_dst16_16_8_SB_relative_QI, { 0x7a0a00 }
13889
  },
13890
/* xchg.b r0l,${Dsp-16-u16}[sb] */
13891
  {
13892
    { 0, 0, 0, 0 },
13893
    { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
13894
    & ifmt_xchg16b_r1h_dst16_16_16_SB_relative_QI, { 0x7a0e0000 }
13895
  },
13896
/* xchg.b r0l,${Dsp-16-s8}[fb] */
13897
  {
13898
    { 0, 0, 0, 0 },
13899
    { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
13900
    & ifmt_xchg16b_r1h_dst16_16_8_FB_relative_QI, { 0x7a0b00 }
13901
  },
13902
/* xchg.b r0l,${Dsp-16-u16} */
13903
  {
13904
    { 0, 0, 0, 0 },
13905
    { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U16), 0 } },
13906
    & ifmt_xchg16b_r1h_dst16_16_16_absolute_QI, { 0x7a0f0000 }
13907
  },
13908
/* tst.w${S} #${Imm-16-HI},${Dsp-8-u8}[sb] */
13909
  {
13910
    { 0, 0, 0, 0 },
13911
    { { MNEM, OP (S), ' ', '#', OP (IMM_16_HI), ',', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } },
13912
    & ifmt_tst32_w_imm_S_2_S_8_dst32_2_S_8_SB_relative_HI, { 0x2d000000 }
13913
  },
13914
/* tst.w${S} #${Imm-16-HI},${Dsp-8-s8}[fb] */
13915
  {
13916
    { 0, 0, 0, 0 },
13917
    { { MNEM, OP (S), ' ', '#', OP (IMM_16_HI), ',', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } },
13918
    & ifmt_tst32_w_imm_S_2_S_8_dst32_2_S_8_FB_relative_HI, { 0x3d000000 }
13919
  },
13920
/* tst.w${S} #${Imm-24-HI},${Dsp-8-u16} */
13921
  {
13922
    { 0, 0, 0, 0 },
13923
    { { MNEM, OP (S), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_8_U16), 0 } },
13924
    & ifmt_tst32_w_imm_S_2_S_16_dst32_2_S_16_absolute_HI, { 0x1d000000 }
13925
  },
13926
/* tst.w${S} #${Imm-8-HI},r0 */
13927
  {
13928
    { 0, 0, 0, 0 },
13929
    { { MNEM, OP (S), ' ', '#', OP (IMM_8_HI), ',', 'r', '0', 0 } },
13930
    & ifmt_tst32_w_imm_S_2_S_basic_dst32_2_S_R0_direct_HI, { 0xd0000 }
13931
  },
13932
/* tst.b${S} #${Imm-16-QI},${Dsp-8-u8}[sb] */
13933
  {
13934
    { 0, 0, 0, 0 },
13935
    { { MNEM, OP (S), ' ', '#', OP (IMM_16_QI), ',', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } },
13936
    & ifmt_tst32_b_imm_S_2_S_8_dst32_2_S_8_SB_relative_QI, { 0x2c0000 }
13937
  },
13938
/* tst.b${S} #${Imm-16-QI},${Dsp-8-s8}[fb] */
13939
  {
13940
    { 0, 0, 0, 0 },
13941
    { { MNEM, OP (S), ' ', '#', OP (IMM_16_QI), ',', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } },
13942
    & ifmt_tst32_b_imm_S_2_S_8_dst32_2_S_8_FB_relative_QI, { 0x3c0000 }
13943
  },
13944
/* tst.b${S} #${Imm-24-QI},${Dsp-8-u16} */
13945
  {
13946
    { 0, 0, 0, 0 },
13947
    { { MNEM, OP (S), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_8_U16), 0 } },
13948
    & ifmt_tst32_b_imm_S_2_S_16_dst32_2_S_16_absolute_QI, { 0x1c000000 }
13949
  },
13950
/* tst.b${S} #${Imm-8-QI},r0l */
13951
  {
13952
    { 0, 0, 0, 0 },
13953
    { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'l', 0 } },
13954
    & ifmt_tst32_b_imm_S_2_S_basic_dst32_2_S_R0l_direct_QI, { 0xc00 }
13955
  },
13956
/* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
13957
  {
13958
    { 0, 0, 0, 0 },
13959
    { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
13960
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1990900 }
13961
  },
13962
/* tst.w${G} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
13963
  {
13964
    { 0, 0, 0, 0 },
13965
    { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
13966
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1992900 }
13967
  },
13968
/* tst.w${G} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
13969
  {
13970
    { 0, 0, 0, 0 },
13971
    { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
13972
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1993900 }
13973
  },
13974
/* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
13975
  {
13976
    { 0, 0, 0, 0 },
13977
    { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
13978
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1918900 }
13979
  },
13980
/* tst.w${G} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
13981
  {
13982
    { 0, 0, 0, 0 },
13983
    { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
13984
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x191a900 }
13985
  },
13986
/* tst.w${G} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
13987
  {
13988
    { 0, 0, 0, 0 },
13989
    { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
13990
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x191b900 }
13991
  },
13992
/* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
13993
  {
13994
    { 0, 0, 0, 0 },
13995
    { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
13996
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1910900 }
13997
  },
13998
/* tst.w${G} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
13999
  {
14000
    { 0, 0, 0, 0 },
14001
    { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
14002
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1912900 }
14003
  },
14004
/* tst.w${G} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
14005
  {
14006
    { 0, 0, 0, 0 },
14007
    { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
14008
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1913900 }
14009
  },
14010
/* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
14011
  {
14012
    { 0, 0, 0, 0 },
14013
    { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
14014
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1930900 }
14015
  },
14016
/* tst.w${G} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
14017
  {
14018
    { 0, 0, 0, 0 },
14019
    { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
14020
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1932900 }
14021
  },
14022
/* tst.w${G} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
14023
  {
14024
    { 0, 0, 0, 0 },
14025
    { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
14026
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1933900 }
14027
  },
14028
/* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
14029
  {
14030
    { 0, 0, 0, 0 },
14031
    { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
14032
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1950900 }
14033
  },
14034
/* tst.w${G} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
14035
  {
14036
    { 0, 0, 0, 0 },
14037
    { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
14038
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1952900 }
14039
  },
14040
/* tst.w${G} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
14041
  {
14042
    { 0, 0, 0, 0 },
14043
    { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
14044
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1953900 }
14045
  },
14046
/* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
14047
  {
14048
    { 0, 0, 0, 0 },
14049
    { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
14050
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1970900 }
14051
  },
14052
/* tst.w${G} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
14053
  {
14054
    { 0, 0, 0, 0 },
14055
    { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
14056
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1972900 }
14057
  },
14058
/* tst.w${G} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
14059
  {
14060
    { 0, 0, 0, 0 },
14061
    { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
14062
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1973900 }
14063
  },
14064
/* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
14065
  {
14066
    { 0, 0, 0, 0 },
14067
    { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
14068
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x1938900 }
14069
  },
14070
/* tst.w${G} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
14071
  {
14072
    { 0, 0, 0, 0 },
14073
    { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
14074
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x193a900 }
14075
  },
14076
/* tst.w${G} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
14077
  {
14078
    { 0, 0, 0, 0 },
14079
    { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
14080
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x193b900 }
14081
  },
14082
/* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
14083
  {
14084
    { 0, 0, 0, 0 },
14085
    { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
14086
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x1958900 }
14087
  },
14088
/* tst.w${G} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
14089
  {
14090
    { 0, 0, 0, 0 },
14091
    { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
14092
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x195a900 }
14093
  },
14094
/* tst.w${G} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
14095
  {
14096
    { 0, 0, 0, 0 },
14097
    { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
14098
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x195b900 }
14099
  },
14100
/* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
14101
  {
14102
    { 0, 0, 0, 0 },
14103
    { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
14104
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193c900 }
14105
  },
14106
/* tst.w${G} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
14107
  {
14108
    { 0, 0, 0, 0 },
14109
    { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
14110
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193e900 }
14111
  },
14112
/* tst.w${G} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
14113
  {
14114
    { 0, 0, 0, 0 },
14115
    { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
14116
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193f900 }
14117
  },
14118
/* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
14119
  {
14120
    { 0, 0, 0, 0 },
14121
    { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
14122
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195c900 }
14123
  },
14124
/* tst.w${G} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
14125
  {
14126
    { 0, 0, 0, 0 },
14127
    { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
14128
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195e900 }
14129
  },
14130
/* tst.w${G} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
14131
  {
14132
    { 0, 0, 0, 0 },
14133
    { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
14134
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195f900 }
14135
  },
14136
/* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
14137
  {
14138
    { 0, 0, 0, 0 },
14139
    { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
14140
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197c900 }
14141
  },
14142
/* tst.w${G} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
14143
  {
14144
    { 0, 0, 0, 0 },
14145
    { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
14146
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197e900 }
14147
  },
14148
/* tst.w${G} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
14149
  {
14150
    { 0, 0, 0, 0 },
14151
    { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
14152
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197f900 }
14153
  },
14154
/* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
14155
  {
14156
    { 0, 0, 0, 0 },
14157
    { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
14158
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x1978900 }
14159
  },
14160
/* tst.w${G} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
14161
  {
14162
    { 0, 0, 0, 0 },
14163
    { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
14164
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x197a900 }
14165
  },
14166
/* tst.w${G} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
14167
  {
14168
    { 0, 0, 0, 0 },
14169
    { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
14170
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x197b900 }
14171
  },
14172
/* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
14173
  {
14174
    { 0, 0, 0, 0 },
14175
    { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
14176
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a90900 }
14177
  },
14178
/* tst.w${G} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
14179
  {
14180
    { 0, 0, 0, 0 },
14181
    { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
14182
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a92900 }
14183
  },
14184
/* tst.w${G} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
14185
  {
14186
    { 0, 0, 0, 0 },
14187
    { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
14188
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a93900 }
14189
  },
14190
/* tst.w${G} ${Dsp-24-u16},$Dst32RnPrefixedHI */
14191
  {
14192
    { 0, 0, 0, 0 },
14193
    { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', OP (DST32RNPREFIXEDHI), 0 } },
14194
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b93900 }
14195
  },
14196
/* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
14197
  {
14198
    { 0, 0, 0, 0 },
14199
    { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
14200
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a18900 }
14201
  },
14202
/* tst.w${G} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
14203
  {
14204
    { 0, 0, 0, 0 },
14205
    { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
14206
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a1a900 }
14207
  },
14208
/* tst.w${G} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
14209
  {
14210
    { 0, 0, 0, 0 },
14211
    { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
14212
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a1b900 }
14213
  },
14214
/* tst.w${G} ${Dsp-24-u16},$Dst32AnPrefixedHI */
14215
  {
14216
    { 0, 0, 0, 0 },
14217
    { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', OP (DST32ANPREFIXEDHI), 0 } },
14218
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b1b900 }
14219
  },
14220
/* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
14221
  {
14222
    { 0, 0, 0, 0 },
14223
    { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
14224
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a10900 }
14225
  },
14226
/* tst.w${G} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
14227
  {
14228
    { 0, 0, 0, 0 },
14229
    { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
14230
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a12900 }
14231
  },
14232
/* tst.w${G} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
14233
  {
14234
    { 0, 0, 0, 0 },
14235
    { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
14236
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a13900 }
14237
  },
14238
/* tst.w${G} ${Dsp-24-u16},[$Dst32AnPrefixed] */
14239
  {
14240
    { 0, 0, 0, 0 },
14241
    { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
14242
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b13900 }
14243
  },
14244
/* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
14245
  {
14246
    { 0, 0, 0, 0 },
14247
    { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
14248
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a30900 }
14249
  },
14250
/* tst.w${G} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
14251
  {
14252
    { 0, 0, 0, 0 },
14253
    { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
14254
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a32900 }
14255
  },
14256
/* tst.w${G} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
14257
  {
14258
    { 0, 0, 0, 0 },
14259
    { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
14260
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a33900 }
14261
  },
14262
/* tst.w${G} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
14263
  {
14264
    { 0, 0, 0, 0 },
14265
    { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
14266
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1b33900 }
14267
  },
14268
/* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
14269
  {
14270
    { 0, 0, 0, 0 },
14271
    { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
14272
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a50900 }
14273
  },
14274
/* tst.w${G} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
14275
  {
14276
    { 0, 0, 0, 0 },
14277
    { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
14278
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a52900 }
14279
  },
14280
/* tst.w${G} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
14281
  {
14282
    { 0, 0, 0, 0 },
14283
    { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
14284
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a53900 }
14285
  },
14286
/* tst.w${G} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
14287
  {
14288
    { 0, 0, 0, 0 },
14289
    { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
14290
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1b53900 }
14291
  },
14292
/* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
14293
  {
14294
    { 0, 0, 0, 0 },
14295
    { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
14296
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a70900 }
14297
  },
14298
/* tst.w${G} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
14299
  {
14300
    { 0, 0, 0, 0 },
14301
    { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
14302
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a72900 }
14303
  },
14304
/* tst.w${G} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
14305
  {
14306
    { 0, 0, 0, 0 },
14307
    { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
14308
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a73900 }
14309
  },
14310
/* tst.w${G} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
14311
  {
14312
    { 0, 0, 0, 0 },
14313
    { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
14314
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1b73900 }
14315
  },
14316
/* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
14317
  {
14318
    { 0, 0, 0, 0 },
14319
    { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
14320
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a38900 }
14321
  },
14322
/* tst.w${G} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
14323
  {
14324
    { 0, 0, 0, 0 },
14325
    { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
14326
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a3a900 }
14327
  },
14328
/* tst.w${G} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
14329
  {
14330
    { 0, 0, 0, 0 },
14331
    { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
14332
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a3b900 }
14333
  },
14334
/* tst.w${G} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
14335
  {
14336
    { 0, 0, 0, 0 },
14337
    { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
14338
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1b3b900 }
14339
  },
14340
/* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
14341
  {
14342
    { 0, 0, 0, 0 },
14343
    { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
14344
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a58900 }
14345
  },
14346
/* tst.w${G} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
14347
  {
14348
    { 0, 0, 0, 0 },
14349
    { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
14350
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a5a900 }
14351
  },
14352
/* tst.w${G} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
14353
  {
14354
    { 0, 0, 0, 0 },
14355
    { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
14356
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a5b900 }
14357
  },
14358
/* tst.w${G} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
14359
  {
14360
    { 0, 0, 0, 0 },
14361
    { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
14362
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1b5b900 }
14363
  },
14364
/* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
14365
  {
14366
    { 0, 0, 0, 0 },
14367
    { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
14368
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3c900 }
14369
  },
14370
/* tst.w${G} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
14371
  {
14372
    { 0, 0, 0, 0 },
14373
    { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
14374
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3e900 }
14375
  },
14376
/* tst.w${G} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
14377
  {
14378
    { 0, 0, 0, 0 },
14379
    { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
14380
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3f900 }
14381
  },
14382
/* tst.w${G} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
14383
  {
14384
    { 0, 0, 0, 0 },
14385
    { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
14386
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1b3f900 }
14387
  },
14388
/* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
14389
  {
14390
    { 0, 0, 0, 0 },
14391
    { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
14392
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5c900 }
14393
  },
14394
/* tst.w${G} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
14395
  {
14396
    { 0, 0, 0, 0 },
14397
    { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
14398
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5e900 }
14399
  },
14400
/* tst.w${G} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
14401
  {
14402
    { 0, 0, 0, 0 },
14403
    { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
14404
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5f900 }
14405
  },
14406
/* tst.w${G} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
14407
  {
14408
    { 0, 0, 0, 0 },
14409
    { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
14410
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1b5f900 }
14411
  },
14412
/* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
14413
  {
14414
    { 0, 0, 0, 0 },
14415
    { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
14416
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7c900 }
14417
  },
14418
/* tst.w${G} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
14419
  {
14420
    { 0, 0, 0, 0 },
14421
    { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), 0 } },
14422
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7e900 }
14423
  },
14424
/* tst.w${G} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
14425
  {
14426
    { 0, 0, 0, 0 },
14427
    { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), 0 } },
14428
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7f900 }
14429
  },
14430
/* tst.w${G} ${Dsp-24-u16},${Dsp-40-u16} */
14431
  {
14432
    { 0, 0, 0, 0 },
14433
    { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), 0 } },
14434
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1b7f900 }
14435
  },
14436
/* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
14437
  {
14438
    { 0, 0, 0, 0 },
14439
    { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
14440
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a78900 }
14441
  },
14442
/* tst.w${G} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
14443
  {
14444
    { 0, 0, 0, 0 },
14445
    { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), 0 } },
14446
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a7a900 }
14447
  },
14448
/* tst.w${G} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
14449
  {
14450
    { 0, 0, 0, 0 },
14451
    { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), 0 } },
14452
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a7b900 }
14453
  },
14454
/* tst.w${G} ${Dsp-24-u16},${Dsp-40-u24} */
14455
  {
14456
    { 0, 0, 0, 0 },
14457
    { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), 0 } },
14458
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1b7b900 }
14459
  },
14460
/* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
14461
  {
14462
    { 0, 0, 0, 0 },
14463
    { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
14464
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b90900 }
14465
  },
14466
/* tst.w${G} ${Dsp-24-u24},$Dst32RnPrefixedHI */
14467
  {
14468
    { 0, 0, 0, 0 },
14469
    { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', OP (DST32RNPREFIXEDHI), 0 } },
14470
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b92900 }
14471
  },
14472
/* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
14473
  {
14474
    { 0, 0, 0, 0 },
14475
    { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
14476
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b18900 }
14477
  },
14478
/* tst.w${G} ${Dsp-24-u24},$Dst32AnPrefixedHI */
14479
  {
14480
    { 0, 0, 0, 0 },
14481
    { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', OP (DST32ANPREFIXEDHI), 0 } },
14482
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b1a900 }
14483
  },
14484
/* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
14485
  {
14486
    { 0, 0, 0, 0 },
14487
    { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
14488
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b10900 }
14489
  },
14490
/* tst.w${G} ${Dsp-24-u24},[$Dst32AnPrefixed] */
14491
  {
14492
    { 0, 0, 0, 0 },
14493
    { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
14494
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b12900 }
14495
  },
14496
/* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
14497
  {
14498
    { 0, 0, 0, 0 },
14499
    { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
14500
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b30900 }
14501
  },
14502
/* tst.w${G} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
14503
  {
14504
    { 0, 0, 0, 0 },
14505
    { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
14506
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b32900 }
14507
  },
14508
/* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
14509
  {
14510
    { 0, 0, 0, 0 },
14511
    { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
14512
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b50900 }
14513
  },
14514
/* tst.w${G} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
14515
  {
14516
    { 0, 0, 0, 0 },
14517
    { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
14518
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b52900 }
14519
  },
14520
/* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
14521
  {
14522
    { 0, 0, 0, 0 },
14523
    { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
14524
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b70900 }
14525
  },
14526
/* tst.w${G} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
14527
  {
14528
    { 0, 0, 0, 0 },
14529
    { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
14530
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b72900 }
14531
  },
14532
/* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
14533
  {
14534
    { 0, 0, 0, 0 },
14535
    { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
14536
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b38900 }
14537
  },
14538
/* tst.w${G} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
14539
  {
14540
    { 0, 0, 0, 0 },
14541
    { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
14542
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b3a900 }
14543
  },
14544
/* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
14545
  {
14546
    { 0, 0, 0, 0 },
14547
    { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
14548
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b58900 }
14549
  },
14550
/* tst.w${G} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
14551
  {
14552
    { 0, 0, 0, 0 },
14553
    { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
14554
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b5a900 }
14555
  },
14556
/* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
14557
  {
14558
    { 0, 0, 0, 0 },
14559
    { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
14560
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b3c900 }
14561
  },
14562
/* tst.w${G} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
14563
  {
14564
    { 0, 0, 0, 0 },
14565
    { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
14566
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b3e900 }
14567
  },
14568
/* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
14569
  {
14570
    { 0, 0, 0, 0 },
14571
    { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
14572
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b5c900 }
14573
  },
14574
/* tst.w${G} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
14575
  {
14576
    { 0, 0, 0, 0 },
14577
    { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
14578
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b5e900 }
14579
  },
14580
/* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
14581
  {
14582
    { 0, 0, 0, 0 },
14583
    { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), 0 } },
14584
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_absolute_Prefixed_HI, { 0x1b7c900 }
14585
  },
14586
/* tst.w${G} ${Dsp-24-u24},${Dsp-48-u16} */
14587
  {
14588
    { 0, 0, 0, 0 },
14589
    { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), 0 } },
14590
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_absolute_Prefixed_HI, { 0x1b7e900 }
14591
  },
14592
/* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
14593
  {
14594
    { 0, 0, 0, 0 },
14595
    { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), 0 } },
14596
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_24_absolute_Prefixed_HI, { 0x1b78900 }
14597
  },
14598
/* tst.w${G} ${Dsp-24-u24},${Dsp-48-u24} */
14599
  {
14600
    { 0, 0, 0, 0 },
14601
    { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), 0 } },
14602
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_24_absolute_Prefixed_HI, { 0x1b7a900 }
14603
  },
14604
/* tst.w${G} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */
14605
  {
14606
    { 0, 0, 0, 0 },
14607
    { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DST32RNPREFIXEDHI), 0 } },
14608
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1c909 }
14609
  },
14610
/* tst.w${G} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */
14611
  {
14612
    { 0, 0, 0, 0 },
14613
    { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DST32RNPREFIXEDHI), 0 } },
14614
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x18929 }
14615
  },
14616
/* tst.w${G} [$Src32AnPrefixed],$Dst32RnPrefixedHI */
14617
  {
14618
    { 0, 0, 0, 0 },
14619
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
14620
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x18909 }
14621
  },
14622
/* tst.w${G} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */
14623
  {
14624
    { 0, 0, 0, 0 },
14625
    { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DST32ANPREFIXEDHI), 0 } },
14626
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1c189 }
14627
  },
14628
/* tst.w${G} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */
14629
  {
14630
    { 0, 0, 0, 0 },
14631
    { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DST32ANPREFIXEDHI), 0 } },
14632
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x181a9 }
14633
  },
14634
/* tst.w${G} [$Src32AnPrefixed],$Dst32AnPrefixedHI */
14635
  {
14636
    { 0, 0, 0, 0 },
14637
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
14638
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x18189 }
14639
  },
14640
/* tst.w${G} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */
14641
  {
14642
    { 0, 0, 0, 0 },
14643
    { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDHI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
14644
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1c109 }
14645
  },
14646
/* tst.w${G} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */
14647
  {
14648
    { 0, 0, 0, 0 },
14649
    { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDHI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
14650
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x18129 }
14651
  },
14652
/* tst.w${G} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
14653
  {
14654
    { 0, 0, 0, 0 },
14655
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
14656
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x18109 }
14657
  },
14658
/* tst.w${G} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
14659
  {
14660
    { 0, 0, 0, 0 },
14661
    { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
14662
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1c30900 }
14663
  },
14664
/* tst.w${G} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
14665
  {
14666
    { 0, 0, 0, 0 },
14667
    { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
14668
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1832900 }
14669
  },
14670
/* tst.w${G} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
14671
  {
14672
    { 0, 0, 0, 0 },
14673
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
14674
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1830900 }
14675
  },
14676
/* tst.w${G} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
14677
  {
14678
    { 0, 0, 0, 0 },
14679
    { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
14680
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1c50900 }
14681
  },
14682
/* tst.w${G} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
14683
  {
14684
    { 0, 0, 0, 0 },
14685
    { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
14686
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1852900 }
14687
  },
14688
/* tst.w${G} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
14689
  {
14690
    { 0, 0, 0, 0 },
14691
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
14692
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1850900 }
14693
  },
14694
/* tst.w${G} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
14695
  {
14696
    { 0, 0, 0, 0 },
14697
    { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
14698
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1c70900 }
14699
  },
14700
/* tst.w${G} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
14701
  {
14702
    { 0, 0, 0, 0 },
14703
    { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
14704
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1872900 }
14705
  },
14706
/* tst.w${G} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
14707
  {
14708
    { 0, 0, 0, 0 },
14709
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
14710
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1870900 }
14711
  },
14712
/* tst.w${G} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */
14713
  {
14714
    { 0, 0, 0, 0 },
14715
    { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
14716
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1c38900 }
14717
  },
14718
/* tst.w${G} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */
14719
  {
14720
    { 0, 0, 0, 0 },
14721
    { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
14722
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x183a900 }
14723
  },
14724
/* tst.w${G} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
14725
  {
14726
    { 0, 0, 0, 0 },
14727
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
14728
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1838900 }
14729
  },
14730
/* tst.w${G} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */
14731
  {
14732
    { 0, 0, 0, 0 },
14733
    { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
14734
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1c58900 }
14735
  },
14736
/* tst.w${G} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */
14737
  {
14738
    { 0, 0, 0, 0 },
14739
    { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
14740
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x185a900 }
14741
  },
14742
/* tst.w${G} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
14743
  {
14744
    { 0, 0, 0, 0 },
14745
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
14746
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1858900 }
14747
  },
14748
/* tst.w${G} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */
14749
  {
14750
    { 0, 0, 0, 0 },
14751
    { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
14752
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x1c3c900 }
14753
  },
14754
/* tst.w${G} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */
14755
  {
14756
    { 0, 0, 0, 0 },
14757
    { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
14758
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x183e900 }
14759
  },
14760
/* tst.w${G} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
14761
  {
14762
    { 0, 0, 0, 0 },
14763
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
14764
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x183c900 }
14765
  },
14766
/* tst.w${G} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */
14767
  {
14768
    { 0, 0, 0, 0 },
14769
    { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
14770
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x1c5c900 }
14771
  },
14772
/* tst.w${G} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */
14773
  {
14774
    { 0, 0, 0, 0 },
14775
    { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
14776
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x185e900 }
14777
  },
14778
/* tst.w${G} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
14779
  {
14780
    { 0, 0, 0, 0 },
14781
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
14782
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x185c900 }
14783
  },
14784
/* tst.w${G} $Src32RnPrefixedHI,${Dsp-24-u16} */
14785
  {
14786
    { 0, 0, 0, 0 },
14787
    { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), 0 } },
14788
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x1c7c900 }
14789
  },
14790
/* tst.w${G} $Src32AnPrefixedHI,${Dsp-24-u16} */
14791
  {
14792
    { 0, 0, 0, 0 },
14793
    { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), 0 } },
14794
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x187e900 }
14795
  },
14796
/* tst.w${G} [$Src32AnPrefixed],${Dsp-24-u16} */
14797
  {
14798
    { 0, 0, 0, 0 },
14799
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
14800
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x187c900 }
14801
  },
14802
/* tst.w${G} $Src32RnPrefixedHI,${Dsp-24-u24} */
14803
  {
14804
    { 0, 0, 0, 0 },
14805
    { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U24), 0 } },
14806
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x1c78900 }
14807
  },
14808
/* tst.w${G} $Src32AnPrefixedHI,${Dsp-24-u24} */
14809
  {
14810
    { 0, 0, 0, 0 },
14811
    { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U24), 0 } },
14812
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x187a900 }
14813
  },
14814
/* tst.w${G} [$Src32AnPrefixed],${Dsp-24-u24} */
14815
  {
14816
    { 0, 0, 0, 0 },
14817
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
14818
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x1878900 }
14819
  },
14820
/* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
14821
  {
14822
    { 0, 0, 0, 0 },
14823
    { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
14824
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1980900 }
14825
  },
14826
/* tst.b${G} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */
14827
  {
14828
    { 0, 0, 0, 0 },
14829
    { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
14830
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1982900 }
14831
  },
14832
/* tst.b${G} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */
14833
  {
14834
    { 0, 0, 0, 0 },
14835
    { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
14836
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1983900 }
14837
  },
14838
/* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
14839
  {
14840
    { 0, 0, 0, 0 },
14841
    { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
14842
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1908900 }
14843
  },
14844
/* tst.b${G} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */
14845
  {
14846
    { 0, 0, 0, 0 },
14847
    { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
14848
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x190a900 }
14849
  },
14850
/* tst.b${G} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */
14851
  {
14852
    { 0, 0, 0, 0 },
14853
    { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
14854
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x190b900 }
14855
  },
14856
/* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
14857
  {
14858
    { 0, 0, 0, 0 },
14859
    { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
14860
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1900900 }
14861
  },
14862
/* tst.b${G} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
14863
  {
14864
    { 0, 0, 0, 0 },
14865
    { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
14866
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1902900 }
14867
  },
14868
/* tst.b${G} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
14869
  {
14870
    { 0, 0, 0, 0 },
14871
    { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
14872
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1903900 }
14873
  },
14874
/* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
14875
  {
14876
    { 0, 0, 0, 0 },
14877
    { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
14878
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1920900 }
14879
  },
14880
/* tst.b${G} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
14881
  {
14882
    { 0, 0, 0, 0 },
14883
    { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
14884
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1922900 }
14885
  },
14886
/* tst.b${G} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
14887
  {
14888
    { 0, 0, 0, 0 },
14889
    { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
14890
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1923900 }
14891
  },
14892
/* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
14893
  {
14894
    { 0, 0, 0, 0 },
14895
    { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
14896
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1940900 }
14897
  },
14898
/* tst.b${G} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
14899
  {
14900
    { 0, 0, 0, 0 },
14901
    { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
14902
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1942900 }
14903
  },
14904
/* tst.b${G} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
14905
  {
14906
    { 0, 0, 0, 0 },
14907
    { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
14908
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1943900 }
14909
  },
14910
/* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
14911
  {
14912
    { 0, 0, 0, 0 },
14913
    { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
14914
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1960900 }
14915
  },
14916
/* tst.b${G} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
14917
  {
14918
    { 0, 0, 0, 0 },
14919
    { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
14920
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1962900 }
14921
  },
14922
/* tst.b${G} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
14923
  {
14924
    { 0, 0, 0, 0 },
14925
    { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
14926
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1963900 }
14927
  },
14928
/* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
14929
  {
14930
    { 0, 0, 0, 0 },
14931
    { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
14932
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x1928900 }
14933
  },
14934
/* tst.b${G} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
14935
  {
14936
    { 0, 0, 0, 0 },
14937
    { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
14938
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x192a900 }
14939
  },
14940
/* tst.b${G} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
14941
  {
14942
    { 0, 0, 0, 0 },
14943
    { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
14944
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x192b900 }
14945
  },
14946
/* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
14947
  {
14948
    { 0, 0, 0, 0 },
14949
    { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
14950
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x1948900 }
14951
  },
14952
/* tst.b${G} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
14953
  {
14954
    { 0, 0, 0, 0 },
14955
    { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
14956
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x194a900 }
14957
  },
14958
/* tst.b${G} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
14959
  {
14960
    { 0, 0, 0, 0 },
14961
    { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
14962
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x194b900 }
14963
  },
14964
/* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
14965
  {
14966
    { 0, 0, 0, 0 },
14967
    { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
14968
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192c900 }
14969
  },
14970
/* tst.b${G} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
14971
  {
14972
    { 0, 0, 0, 0 },
14973
    { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
14974
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192e900 }
14975
  },
14976
/* tst.b${G} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
14977
  {
14978
    { 0, 0, 0, 0 },
14979
    { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
14980
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192f900 }
14981
  },
14982
/* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
14983
  {
14984
    { 0, 0, 0, 0 },
14985
    { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
14986
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194c900 }
14987
  },
14988
/* tst.b${G} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
14989
  {
14990
    { 0, 0, 0, 0 },
14991
    { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
14992
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194e900 }
14993
  },
14994
/* tst.b${G} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
14995
  {
14996
    { 0, 0, 0, 0 },
14997
    { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
14998
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194f900 }
14999
  },
15000
/* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
15001
  {
15002
    { 0, 0, 0, 0 },
15003
    { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
15004
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196c900 }
15005
  },
15006
/* tst.b${G} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
15007
  {
15008
    { 0, 0, 0, 0 },
15009
    { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
15010
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196e900 }
15011
  },
15012
/* tst.b${G} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
15013
  {
15014
    { 0, 0, 0, 0 },
15015
    { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
15016
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196f900 }
15017
  },
15018
/* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
15019
  {
15020
    { 0, 0, 0, 0 },
15021
    { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
15022
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x1968900 }
15023
  },
15024
/* tst.b${G} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
15025
  {
15026
    { 0, 0, 0, 0 },
15027
    { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
15028
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x196a900 }
15029
  },
15030
/* tst.b${G} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
15031
  {
15032
    { 0, 0, 0, 0 },
15033
    { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
15034
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x196b900 }
15035
  },
15036
/* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
15037
  {
15038
    { 0, 0, 0, 0 },
15039
    { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
15040
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a80900 }
15041
  },
15042
/* tst.b${G} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */
15043
  {
15044
    { 0, 0, 0, 0 },
15045
    { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
15046
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a82900 }
15047
  },
15048
/* tst.b${G} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */
15049
  {
15050
    { 0, 0, 0, 0 },
15051
    { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
15052
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a83900 }
15053
  },
15054
/* tst.b${G} ${Dsp-24-u16},$Dst32RnPrefixedQI */
15055
  {
15056
    { 0, 0, 0, 0 },
15057
    { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', OP (DST32RNPREFIXEDQI), 0 } },
15058
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b83900 }
15059
  },
15060
/* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
15061
  {
15062
    { 0, 0, 0, 0 },
15063
    { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
15064
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a08900 }
15065
  },
15066
/* tst.b${G} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */
15067
  {
15068
    { 0, 0, 0, 0 },
15069
    { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
15070
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a0a900 }
15071
  },
15072
/* tst.b${G} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */
15073
  {
15074
    { 0, 0, 0, 0 },
15075
    { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
15076
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a0b900 }
15077
  },
15078
/* tst.b${G} ${Dsp-24-u16},$Dst32AnPrefixedQI */
15079
  {
15080
    { 0, 0, 0, 0 },
15081
    { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', OP (DST32ANPREFIXEDQI), 0 } },
15082
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b0b900 }
15083
  },
15084
/* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
15085
  {
15086
    { 0, 0, 0, 0 },
15087
    { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
15088
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a00900 }
15089
  },
15090
/* tst.b${G} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
15091
  {
15092
    { 0, 0, 0, 0 },
15093
    { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
15094
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a02900 }
15095
  },
15096
/* tst.b${G} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
15097
  {
15098
    { 0, 0, 0, 0 },
15099
    { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
15100
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a03900 }
15101
  },
15102
/* tst.b${G} ${Dsp-24-u16},[$Dst32AnPrefixed] */
15103
  {
15104
    { 0, 0, 0, 0 },
15105
    { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
15106
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b03900 }
15107
  },
15108
/* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
15109
  {
15110
    { 0, 0, 0, 0 },
15111
    { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
15112
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a20900 }
15113
  },
15114
/* tst.b${G} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
15115
  {
15116
    { 0, 0, 0, 0 },
15117
    { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
15118
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a22900 }
15119
  },
15120
/* tst.b${G} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
15121
  {
15122
    { 0, 0, 0, 0 },
15123
    { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
15124
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a23900 }
15125
  },
15126
/* tst.b${G} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
15127
  {
15128
    { 0, 0, 0, 0 },
15129
    { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
15130
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1b23900 }
15131
  },
15132
/* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
15133
  {
15134
    { 0, 0, 0, 0 },
15135
    { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
15136
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a40900 }
15137
  },
15138
/* tst.b${G} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
15139
  {
15140
    { 0, 0, 0, 0 },
15141
    { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
15142
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a42900 }
15143
  },
15144
/* tst.b${G} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
15145
  {
15146
    { 0, 0, 0, 0 },
15147
    { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
15148
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a43900 }
15149
  },
15150
/* tst.b${G} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
15151
  {
15152
    { 0, 0, 0, 0 },
15153
    { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
15154
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1b43900 }
15155
  },
15156
/* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
15157
  {
15158
    { 0, 0, 0, 0 },
15159
    { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
15160
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a60900 }
15161
  },
15162
/* tst.b${G} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
15163
  {
15164
    { 0, 0, 0, 0 },
15165
    { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
15166
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a62900 }
15167
  },
15168
/* tst.b${G} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
15169
  {
15170
    { 0, 0, 0, 0 },
15171
    { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
15172
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a63900 }
15173
  },
15174
/* tst.b${G} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
15175
  {
15176
    { 0, 0, 0, 0 },
15177
    { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
15178
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1b63900 }
15179
  },
15180
/* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
15181
  {
15182
    { 0, 0, 0, 0 },
15183
    { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
15184
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a28900 }
15185
  },
15186
/* tst.b${G} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
15187
  {
15188
    { 0, 0, 0, 0 },
15189
    { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
15190
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a2a900 }
15191
  },
15192
/* tst.b${G} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
15193
  {
15194
    { 0, 0, 0, 0 },
15195
    { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
15196
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a2b900 }
15197
  },
15198
/* tst.b${G} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
15199
  {
15200
    { 0, 0, 0, 0 },
15201
    { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
15202
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1b2b900 }
15203
  },
15204
/* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
15205
  {
15206
    { 0, 0, 0, 0 },
15207
    { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
15208
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a48900 }
15209
  },
15210
/* tst.b${G} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
15211
  {
15212
    { 0, 0, 0, 0 },
15213
    { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
15214
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a4a900 }
15215
  },
15216
/* tst.b${G} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
15217
  {
15218
    { 0, 0, 0, 0 },
15219
    { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
15220
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a4b900 }
15221
  },
15222
/* tst.b${G} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
15223
  {
15224
    { 0, 0, 0, 0 },
15225
    { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
15226
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1b4b900 }
15227
  },
15228
/* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
15229
  {
15230
    { 0, 0, 0, 0 },
15231
    { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
15232
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2c900 }
15233
  },
15234
/* tst.b${G} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
15235
  {
15236
    { 0, 0, 0, 0 },
15237
    { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
15238
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2e900 }
15239
  },
15240
/* tst.b${G} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
15241
  {
15242
    { 0, 0, 0, 0 },
15243
    { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
15244
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2f900 }
15245
  },
15246
/* tst.b${G} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
15247
  {
15248
    { 0, 0, 0, 0 },
15249
    { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
15250
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1b2f900 }
15251
  },
15252
/* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
15253
  {
15254
    { 0, 0, 0, 0 },
15255
    { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
15256
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4c900 }
15257
  },
15258
/* tst.b${G} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
15259
  {
15260
    { 0, 0, 0, 0 },
15261
    { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
15262
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4e900 }
15263
  },
15264
/* tst.b${G} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
15265
  {
15266
    { 0, 0, 0, 0 },
15267
    { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
15268
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4f900 }
15269
  },
15270
/* tst.b${G} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
15271
  {
15272
    { 0, 0, 0, 0 },
15273
    { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
15274
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1b4f900 }
15275
  },
15276
/* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
15277
  {
15278
    { 0, 0, 0, 0 },
15279
    { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
15280
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6c900 }
15281
  },
15282
/* tst.b${G} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
15283
  {
15284
    { 0, 0, 0, 0 },
15285
    { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), 0 } },
15286
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6e900 }
15287
  },
15288
/* tst.b${G} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
15289
  {
15290
    { 0, 0, 0, 0 },
15291
    { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), 0 } },
15292
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6f900 }
15293
  },
15294
/* tst.b${G} ${Dsp-24-u16},${Dsp-40-u16} */
15295
  {
15296
    { 0, 0, 0, 0 },
15297
    { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), 0 } },
15298
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1b6f900 }
15299
  },
15300
/* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
15301
  {
15302
    { 0, 0, 0, 0 },
15303
    { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
15304
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a68900 }
15305
  },
15306
/* tst.b${G} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
15307
  {
15308
    { 0, 0, 0, 0 },
15309
    { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), 0 } },
15310
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a6a900 }
15311
  },
15312
/* tst.b${G} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
15313
  {
15314
    { 0, 0, 0, 0 },
15315
    { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), 0 } },
15316
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a6b900 }
15317
  },
15318
/* tst.b${G} ${Dsp-24-u16},${Dsp-40-u24} */
15319
  {
15320
    { 0, 0, 0, 0 },
15321
    { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), 0 } },
15322
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1b6b900 }
15323
  },
15324
/* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
15325
  {
15326
    { 0, 0, 0, 0 },
15327
    { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
15328
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b80900 }
15329
  },
15330
/* tst.b${G} ${Dsp-24-u24},$Dst32RnPrefixedQI */
15331
  {
15332
    { 0, 0, 0, 0 },
15333
    { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', OP (DST32RNPREFIXEDQI), 0 } },
15334
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b82900 }
15335
  },
15336
/* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
15337
  {
15338
    { 0, 0, 0, 0 },
15339
    { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
15340
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b08900 }
15341
  },
15342
/* tst.b${G} ${Dsp-24-u24},$Dst32AnPrefixedQI */
15343
  {
15344
    { 0, 0, 0, 0 },
15345
    { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', OP (DST32ANPREFIXEDQI), 0 } },
15346
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b0a900 }
15347
  },
15348
/* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
15349
  {
15350
    { 0, 0, 0, 0 },
15351
    { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
15352
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b00900 }
15353
  },
15354
/* tst.b${G} ${Dsp-24-u24},[$Dst32AnPrefixed] */
15355
  {
15356
    { 0, 0, 0, 0 },
15357
    { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
15358
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b02900 }
15359
  },
15360
/* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
15361
  {
15362
    { 0, 0, 0, 0 },
15363
    { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
15364
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_An_relative_Prefixed_QI, { 0x1b20900 }
15365
  },
15366
/* tst.b${G} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
15367
  {
15368
    { 0, 0, 0, 0 },
15369
    { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
15370
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_An_relative_Prefixed_QI, { 0x1b22900 }
15371
  },
15372
/* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
15373
  {
15374
    { 0, 0, 0, 0 },
15375
    { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
15376
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_An_relative_Prefixed_QI, { 0x1b40900 }
15377
  },
15378
/* tst.b${G} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
15379
  {
15380
    { 0, 0, 0, 0 },
15381
    { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
15382
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_An_relative_Prefixed_QI, { 0x1b42900 }
15383
  },
15384
/* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
15385
  {
15386
    { 0, 0, 0, 0 },
15387
    { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
15388
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_An_relative_Prefixed_QI, { 0x1b60900 }
15389
  },
15390
/* tst.b${G} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
15391
  {
15392
    { 0, 0, 0, 0 },
15393
    { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
15394
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_An_relative_Prefixed_QI, { 0x1b62900 }
15395
  },
15396
/* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
15397
  {
15398
    { 0, 0, 0, 0 },
15399
    { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
15400
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_QI, { 0x1b28900 }
15401
  },
15402
/* tst.b${G} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
15403
  {
15404
    { 0, 0, 0, 0 },
15405
    { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
15406
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_QI, { 0x1b2a900 }
15407
  },
15408
/* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
15409
  {
15410
    { 0, 0, 0, 0 },
15411
    { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
15412
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_QI, { 0x1b48900 }
15413
  },
15414
/* tst.b${G} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
15415
  {
15416
    { 0, 0, 0, 0 },
15417
    { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
15418
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_QI, { 0x1b4a900 }
15419
  },
15420
/* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
15421
  {
15422
    { 0, 0, 0, 0 },
15423
    { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
15424
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_QI, { 0x1b2c900 }
15425
  },
15426
/* tst.b${G} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
15427
  {
15428
    { 0, 0, 0, 0 },
15429
    { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
15430
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_QI, { 0x1b2e900 }
15431
  },
15432
/* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
15433
  {
15434
    { 0, 0, 0, 0 },
15435
    { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
15436
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_QI, { 0x1b4c900 }
15437
  },
15438
/* tst.b${G} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
15439
  {
15440
    { 0, 0, 0, 0 },
15441
    { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
15442
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_QI, { 0x1b4e900 }
15443
  },
15444
/* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
15445
  {
15446
    { 0, 0, 0, 0 },
15447
    { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), 0 } },
15448
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_absolute_Prefixed_QI, { 0x1b6c900 }
15449
  },
15450
/* tst.b${G} ${Dsp-24-u24},${Dsp-48-u16} */
15451
  {
15452
    { 0, 0, 0, 0 },
15453
    { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), 0 } },
15454
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_absolute_Prefixed_QI, { 0x1b6e900 }
15455
  },
15456
/* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
15457
  {
15458
    { 0, 0, 0, 0 },
15459
    { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), 0 } },
15460
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_absolute_Prefixed_QI, { 0x1b68900 }
15461
  },
15462
/* tst.b${G} ${Dsp-24-u24},${Dsp-48-u24} */
15463
  {
15464
    { 0, 0, 0, 0 },
15465
    { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), 0 } },
15466
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_absolute_Prefixed_QI, { 0x1b6a900 }
15467
  },
15468
/* tst.b${G} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */
15469
  {
15470
    { 0, 0, 0, 0 },
15471
    { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32RNPREFIXEDQI), 0 } },
15472
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1c809 }
15473
  },
15474
/* tst.b${G} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */
15475
  {
15476
    { 0, 0, 0, 0 },
15477
    { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DST32RNPREFIXEDQI), 0 } },
15478
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x18829 }
15479
  },
15480
/* tst.b${G} [$Src32AnPrefixed],$Dst32RnPrefixedQI */
15481
  {
15482
    { 0, 0, 0, 0 },
15483
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
15484
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x18809 }
15485
  },
15486
/* tst.b${G} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */
15487
  {
15488
    { 0, 0, 0, 0 },
15489
    { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32ANPREFIXEDQI), 0 } },
15490
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1c089 }
15491
  },
15492
/* tst.b${G} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */
15493
  {
15494
    { 0, 0, 0, 0 },
15495
    { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DST32ANPREFIXEDQI), 0 } },
15496
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x180a9 }
15497
  },
15498
/* tst.b${G} [$Src32AnPrefixed],$Dst32AnPrefixedQI */
15499
  {
15500
    { 0, 0, 0, 0 },
15501
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
15502
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x18089 }
15503
  },
15504
/* tst.b${G} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
15505
  {
15506
    { 0, 0, 0, 0 },
15507
    { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDQI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
15508
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1c009 }
15509
  },
15510
/* tst.b${G} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */
15511
  {
15512
    { 0, 0, 0, 0 },
15513
    { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDQI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
15514
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x18029 }
15515
  },
15516
/* tst.b${G} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
15517
  {
15518
    { 0, 0, 0, 0 },
15519
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
15520
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x18009 }
15521
  },
15522
/* tst.b${G} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
15523
  {
15524
    { 0, 0, 0, 0 },
15525
    { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
15526
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1c20900 }
15527
  },
15528
/* tst.b${G} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
15529
  {
15530
    { 0, 0, 0, 0 },
15531
    { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
15532
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1822900 }
15533
  },
15534
/* tst.b${G} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
15535
  {
15536
    { 0, 0, 0, 0 },
15537
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
15538
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1820900 }
15539
  },
15540
/* tst.b${G} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
15541
  {
15542
    { 0, 0, 0, 0 },
15543
    { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
15544
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1c40900 }
15545
  },
15546
/* tst.b${G} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
15547
  {
15548
    { 0, 0, 0, 0 },
15549
    { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
15550
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1842900 }
15551
  },
15552
/* tst.b${G} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
15553
  {
15554
    { 0, 0, 0, 0 },
15555
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
15556
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1840900 }
15557
  },
15558
/* tst.b${G} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
15559
  {
15560
    { 0, 0, 0, 0 },
15561
    { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
15562
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1c60900 }
15563
  },
15564
/* tst.b${G} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
15565
  {
15566
    { 0, 0, 0, 0 },
15567
    { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
15568
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1862900 }
15569
  },
15570
/* tst.b${G} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
15571
  {
15572
    { 0, 0, 0, 0 },
15573
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
15574
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1860900 }
15575
  },
15576
/* tst.b${G} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
15577
  {
15578
    { 0, 0, 0, 0 },
15579
    { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
15580
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x1c28900 }
15581
  },
15582
/* tst.b${G} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */
15583
  {
15584
    { 0, 0, 0, 0 },
15585
    { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
15586
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x182a900 }
15587
  },
15588
/* tst.b${G} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
15589
  {
15590
    { 0, 0, 0, 0 },
15591
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
15592
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x1828900 }
15593
  },
15594
/* tst.b${G} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
15595
  {
15596
    { 0, 0, 0, 0 },
15597
    { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
15598
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x1c48900 }
15599
  },
15600
/* tst.b${G} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */
15601
  {
15602
    { 0, 0, 0, 0 },
15603
    { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
15604
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x184a900 }
15605
  },
15606
/* tst.b${G} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
15607
  {
15608
    { 0, 0, 0, 0 },
15609
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
15610
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x1848900 }
15611
  },
15612
/* tst.b${G} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
15613
  {
15614
    { 0, 0, 0, 0 },
15615
    { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
15616
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x1c2c900 }
15617
  },
15618
/* tst.b${G} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */
15619
  {
15620
    { 0, 0, 0, 0 },
15621
    { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
15622
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x182e900 }
15623
  },
15624
/* tst.b${G} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
15625
  {
15626
    { 0, 0, 0, 0 },
15627
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
15628
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x182c900 }
15629
  },
15630
/* tst.b${G} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
15631
  {
15632
    { 0, 0, 0, 0 },
15633
    { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
15634
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x1c4c900 }
15635
  },
15636
/* tst.b${G} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */
15637
  {
15638
    { 0, 0, 0, 0 },
15639
    { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
15640
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x184e900 }
15641
  },
15642
/* tst.b${G} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
15643
  {
15644
    { 0, 0, 0, 0 },
15645
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
15646
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x184c900 }
15647
  },
15648
/* tst.b${G} $Src32RnPrefixedQI,${Dsp-24-u16} */
15649
  {
15650
    { 0, 0, 0, 0 },
15651
    { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), 0 } },
15652
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x1c6c900 }
15653
  },
15654
/* tst.b${G} $Src32AnPrefixedQI,${Dsp-24-u16} */
15655
  {
15656
    { 0, 0, 0, 0 },
15657
    { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), 0 } },
15658
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x186e900 }
15659
  },
15660
/* tst.b${G} [$Src32AnPrefixed],${Dsp-24-u16} */
15661
  {
15662
    { 0, 0, 0, 0 },
15663
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
15664
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x186c900 }
15665
  },
15666
/* tst.b${G} $Src32RnPrefixedQI,${Dsp-24-u24} */
15667
  {
15668
    { 0, 0, 0, 0 },
15669
    { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), 0 } },
15670
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x1c68900 }
15671
  },
15672
/* tst.b${G} $Src32AnPrefixedQI,${Dsp-24-u24} */
15673
  {
15674
    { 0, 0, 0, 0 },
15675
    { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U24), 0 } },
15676
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x186a900 }
15677
  },
15678
/* tst.b${G} [$Src32AnPrefixed],${Dsp-24-u24} */
15679
  {
15680
    { 0, 0, 0, 0 },
15681
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
15682
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x1868900 }
15683
  },
15684
/* tst.w${X} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
15685
  {
15686
    { 0, 0, 0, 0 },
15687
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } },
15688
    & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_Rn_direct_HI, { 0x818000 }
15689
  },
15690
/* tst.w${X} ${Dsp-16-u8}[sb],$Dst16RnHI */
15691
  {
15692
    { 0, 0, 0, 0 },
15693
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } },
15694
    & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_Rn_direct_HI, { 0x81a000 }
15695
  },
15696
/* tst.w${X} ${Dsp-16-s8}[fb],$Dst16RnHI */
15697
  {
15698
    { 0, 0, 0, 0 },
15699
    { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNHI), 0 } },
15700
    & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_Rn_direct_HI, { 0x81b000 }
15701
  },
15702
/* tst.w${X} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
15703
  {
15704
    { 0, 0, 0, 0 },
15705
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } },
15706
    & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_direct_HI, { 0x818400 }
15707
  },
15708
/* tst.w${X} ${Dsp-16-u8}[sb],$Dst16AnHI */
15709
  {
15710
    { 0, 0, 0, 0 },
15711
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } },
15712
    & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_direct_HI, { 0x81a400 }
15713
  },
15714
/* tst.w${X} ${Dsp-16-s8}[fb],$Dst16AnHI */
15715
  {
15716
    { 0, 0, 0, 0 },
15717
    { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANHI), 0 } },
15718
    & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_direct_HI, { 0x81b400 }
15719
  },
15720
/* tst.w${X} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
15721
  {
15722
    { 0, 0, 0, 0 },
15723
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
15724
    & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_indirect_HI, { 0x818600 }
15725
  },
15726
/* tst.w${X} ${Dsp-16-u8}[sb],[$Dst16An] */
15727
  {
15728
    { 0, 0, 0, 0 },
15729
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
15730
    & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_indirect_HI, { 0x81a600 }
15731
  },
15732
/* tst.w${X} ${Dsp-16-s8}[fb],[$Dst16An] */
15733
  {
15734
    { 0, 0, 0, 0 },
15735
    { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
15736
    & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_indirect_HI, { 0x81b600 }
15737
  },
15738
/* tst.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
15739
  {
15740
    { 0, 0, 0, 0 },
15741
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
15742
    & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_An_relative_HI, { 0x81880000 }
15743
  },
15744
/* tst.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
15745
  {
15746
    { 0, 0, 0, 0 },
15747
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
15748
    & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_An_relative_HI, { 0x81a80000 }
15749
  },
15750
/* tst.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
15751
  {
15752
    { 0, 0, 0, 0 },
15753
    { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
15754
    & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_An_relative_HI, { 0x81b80000 }
15755
  },
15756
/* tst.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
15757
  {
15758
    { 0, 0, 0, 0 },
15759
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
15760
    & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_An_relative_HI, { 0x818c0000 }
15761
  },
15762
/* tst.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
15763
  {
15764
    { 0, 0, 0, 0 },
15765
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
15766
    & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_An_relative_HI, { 0x81ac0000 }
15767
  },
15768
/* tst.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
15769
  {
15770
    { 0, 0, 0, 0 },
15771
    { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
15772
    & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_An_relative_HI, { 0x81bc0000 }
15773
  },
15774
/* tst.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
15775
  {
15776
    { 0, 0, 0, 0 },
15777
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
15778
    & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_SB_relative_HI, { 0x818a0000 }
15779
  },
15780
/* tst.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
15781
  {
15782
    { 0, 0, 0, 0 },
15783
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
15784
    & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_SB_relative_HI, { 0x81aa0000 }
15785
  },
15786
/* tst.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
15787
  {
15788
    { 0, 0, 0, 0 },
15789
    { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
15790
    & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_SB_relative_HI, { 0x81ba0000 }
15791
  },
15792
/* tst.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
15793
  {
15794
    { 0, 0, 0, 0 },
15795
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
15796
    & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_SB_relative_HI, { 0x818e0000 }
15797
  },
15798
/* tst.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
15799
  {
15800
    { 0, 0, 0, 0 },
15801
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
15802
    & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_SB_relative_HI, { 0x81ae0000 }
15803
  },
15804
/* tst.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
15805
  {
15806
    { 0, 0, 0, 0 },
15807
    { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
15808
    & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_SB_relative_HI, { 0x81be0000 }
15809
  },
15810
/* tst.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
15811
  {
15812
    { 0, 0, 0, 0 },
15813
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
15814
    & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_FB_relative_HI, { 0x818b0000 }
15815
  },
15816
/* tst.w${X} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
15817
  {
15818
    { 0, 0, 0, 0 },
15819
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
15820
    & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_FB_relative_HI, { 0x81ab0000 }
15821
  },
15822
/* tst.w${X} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
15823
  {
15824
    { 0, 0, 0, 0 },
15825
    { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
15826
    & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_FB_relative_HI, { 0x81bb0000 }
15827
  },
15828
/* tst.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
15829
  {
15830
    { 0, 0, 0, 0 },
15831
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } },
15832
    & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_absolute_HI, { 0x818f0000 }
15833
  },
15834
/* tst.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
15835
  {
15836
    { 0, 0, 0, 0 },
15837
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
15838
    & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_absolute_HI, { 0x81af0000 }
15839
  },
15840
/* tst.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
15841
  {
15842
    { 0, 0, 0, 0 },
15843
    { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
15844
    & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_absolute_HI, { 0x81bf0000 }
15845
  },
15846
/* tst.w${X} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
15847
  {
15848
    { 0, 0, 0, 0 },
15849
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } },
15850
    & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_Rn_direct_HI, { 0x81c00000 }
15851
  },
15852
/* tst.w${X} ${Dsp-16-u16}[sb],$Dst16RnHI */
15853
  {
15854
    { 0, 0, 0, 0 },
15855
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } },
15856
    & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_Rn_direct_HI, { 0x81e00000 }
15857
  },
15858
/* tst.w${X} ${Dsp-16-u16},$Dst16RnHI */
15859
  {
15860
    { 0, 0, 0, 0 },
15861
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DST16RNHI), 0 } },
15862
    & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_Rn_direct_HI, { 0x81f00000 }
15863
  },
15864
/* tst.w${X} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
15865
  {
15866
    { 0, 0, 0, 0 },
15867
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } },
15868
    & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_direct_HI, { 0x81c40000 }
15869
  },
15870
/* tst.w${X} ${Dsp-16-u16}[sb],$Dst16AnHI */
15871
  {
15872
    { 0, 0, 0, 0 },
15873
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } },
15874
    & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_direct_HI, { 0x81e40000 }
15875
  },
15876
/* tst.w${X} ${Dsp-16-u16},$Dst16AnHI */
15877
  {
15878
    { 0, 0, 0, 0 },
15879
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DST16ANHI), 0 } },
15880
    & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_direct_HI, { 0x81f40000 }
15881
  },
15882
/* tst.w${X} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
15883
  {
15884
    { 0, 0, 0, 0 },
15885
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
15886
    & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_indirect_HI, { 0x81c60000 }
15887
  },
15888
/* tst.w${X} ${Dsp-16-u16}[sb],[$Dst16An] */
15889
  {
15890
    { 0, 0, 0, 0 },
15891
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
15892
    & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_indirect_HI, { 0x81e60000 }
15893
  },
15894
/* tst.w${X} ${Dsp-16-u16},[$Dst16An] */
15895
  {
15896
    { 0, 0, 0, 0 },
15897
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } },
15898
    & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_indirect_HI, { 0x81f60000 }
15899
  },
15900
/* tst.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
15901
  {
15902
    { 0, 0, 0, 0 },
15903
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
15904
    & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_An_relative_HI, { 0x81c80000 }
15905
  },
15906
/* tst.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
15907
  {
15908
    { 0, 0, 0, 0 },
15909
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
15910
    & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_An_relative_HI, { 0x81e80000 }
15911
  },
15912
/* tst.w${X} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
15913
  {
15914
    { 0, 0, 0, 0 },
15915
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
15916
    & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_An_relative_HI, { 0x81f80000 }
15917
  },
15918
/* tst.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
15919
  {
15920
    { 0, 0, 0, 0 },
15921
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
15922
    & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_An_relative_HI, { 0x81cc0000 }
15923
  },
15924
/* tst.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
15925
  {
15926
    { 0, 0, 0, 0 },
15927
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
15928
    & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_An_relative_HI, { 0x81ec0000 }
15929
  },
15930
/* tst.w${X} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
15931
  {
15932
    { 0, 0, 0, 0 },
15933
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
15934
    & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_An_relative_HI, { 0x81fc0000 }
15935
  },
15936
/* tst.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
15937
  {
15938
    { 0, 0, 0, 0 },
15939
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
15940
    & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_SB_relative_HI, { 0x81ca0000 }
15941
  },
15942
/* tst.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
15943
  {
15944
    { 0, 0, 0, 0 },
15945
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
15946
    & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_SB_relative_HI, { 0x81ea0000 }
15947
  },
15948
/* tst.w${X} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
15949
  {
15950
    { 0, 0, 0, 0 },
15951
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
15952
    & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_SB_relative_HI, { 0x81fa0000 }
15953
  },
15954
/* tst.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
15955
  {
15956
    { 0, 0, 0, 0 },
15957
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
15958
    & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_SB_relative_HI, { 0x81ce0000 }
15959
  },
15960
/* tst.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
15961
  {
15962
    { 0, 0, 0, 0 },
15963
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
15964
    & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_SB_relative_HI, { 0x81ee0000 }
15965
  },
15966
/* tst.w${X} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
15967
  {
15968
    { 0, 0, 0, 0 },
15969
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
15970
    & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_SB_relative_HI, { 0x81fe0000 }
15971
  },
15972
/* tst.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
15973
  {
15974
    { 0, 0, 0, 0 },
15975
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
15976
    & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_FB_relative_HI, { 0x81cb0000 }
15977
  },
15978
/* tst.w${X} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
15979
  {
15980
    { 0, 0, 0, 0 },
15981
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
15982
    & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_FB_relative_HI, { 0x81eb0000 }
15983
  },
15984
/* tst.w${X} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
15985
  {
15986
    { 0, 0, 0, 0 },
15987
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
15988
    & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_FB_relative_HI, { 0x81fb0000 }
15989
  },
15990
/* tst.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
15991
  {
15992
    { 0, 0, 0, 0 },
15993
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } },
15994
    & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_absolute_HI, { 0x81cf0000 }
15995
  },
15996
/* tst.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
15997
  {
15998
    { 0, 0, 0, 0 },
15999
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
16000
    & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_absolute_HI, { 0x81ef0000 }
16001
  },
16002
/* tst.w${X} ${Dsp-16-u16},${Dsp-32-u16} */
16003
  {
16004
    { 0, 0, 0, 0 },
16005
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
16006
    & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_absolute_HI, { 0x81ff0000 }
16007
  },
16008
/* tst.w${X} $Src16RnHI,$Dst16RnHI */
16009
  {
16010
    { 0, 0, 0, 0 },
16011
    { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DST16RNHI), 0 } },
16012
    & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_Rn_direct_HI, { 0x8100 }
16013
  },
16014
/* tst.w${X} $Src16AnHI,$Dst16RnHI */
16015
  {
16016
    { 0, 0, 0, 0 },
16017
    { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DST16RNHI), 0 } },
16018
    & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_Rn_direct_HI, { 0x8140 }
16019
  },
16020
/* tst.w${X} [$Src16An],$Dst16RnHI */
16021
  {
16022
    { 0, 0, 0, 0 },
16023
    { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } },
16024
    & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_Rn_direct_HI, { 0x8160 }
16025
  },
16026
/* tst.w${X} $Src16RnHI,$Dst16AnHI */
16027
  {
16028
    { 0, 0, 0, 0 },
16029
    { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DST16ANHI), 0 } },
16030
    & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_direct_HI, { 0x8104 }
16031
  },
16032
/* tst.w${X} $Src16AnHI,$Dst16AnHI */
16033
  {
16034
    { 0, 0, 0, 0 },
16035
    { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DST16ANHI), 0 } },
16036
    & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_direct_HI, { 0x8144 }
16037
  },
16038
/* tst.w${X} [$Src16An],$Dst16AnHI */
16039
  {
16040
    { 0, 0, 0, 0 },
16041
    { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } },
16042
    & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_direct_HI, { 0x8164 }
16043
  },
16044
/* tst.w${X} $Src16RnHI,[$Dst16An] */
16045
  {
16046
    { 0, 0, 0, 0 },
16047
    { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', '[', OP (DST16AN), ']', 0 } },
16048
    & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_indirect_HI, { 0x8106 }
16049
  },
16050
/* tst.w${X} $Src16AnHI,[$Dst16An] */
16051
  {
16052
    { 0, 0, 0, 0 },
16053
    { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', '[', OP (DST16AN), ']', 0 } },
16054
    & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_indirect_HI, { 0x8146 }
16055
  },
16056
/* tst.w${X} [$Src16An],[$Dst16An] */
16057
  {
16058
    { 0, 0, 0, 0 },
16059
    { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
16060
    & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_indirect_HI, { 0x8166 }
16061
  },
16062
/* tst.w${X} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
16063
  {
16064
    { 0, 0, 0, 0 },
16065
    { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
16066
    & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_An_relative_HI, { 0x810800 }
16067
  },
16068
/* tst.w${X} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
16069
  {
16070
    { 0, 0, 0, 0 },
16071
    { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
16072
    & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_An_relative_HI, { 0x814800 }
16073
  },
16074
/* tst.w${X} [$Src16An],${Dsp-16-u8}[$Dst16An] */
16075
  {
16076
    { 0, 0, 0, 0 },
16077
    { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
16078
    & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_An_relative_HI, { 0x816800 }
16079
  },
16080
/* tst.w${X} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
16081
  {
16082
    { 0, 0, 0, 0 },
16083
    { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
16084
    & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_An_relative_HI, { 0x810c0000 }
16085
  },
16086
/* tst.w${X} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
16087
  {
16088
    { 0, 0, 0, 0 },
16089
    { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
16090
    & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_An_relative_HI, { 0x814c0000 }
16091
  },
16092
/* tst.w${X} [$Src16An],${Dsp-16-u16}[$Dst16An] */
16093
  {
16094
    { 0, 0, 0, 0 },
16095
    { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
16096
    & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_An_relative_HI, { 0x816c0000 }
16097
  },
16098
/* tst.w${X} $Src16RnHI,${Dsp-16-u8}[sb] */
16099
  {
16100
    { 0, 0, 0, 0 },
16101
    { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
16102
    & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_SB_relative_HI, { 0x810a00 }
16103
  },
16104
/* tst.w${X} $Src16AnHI,${Dsp-16-u8}[sb] */
16105
  {
16106
    { 0, 0, 0, 0 },
16107
    { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
16108
    & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_SB_relative_HI, { 0x814a00 }
16109
  },
16110
/* tst.w${X} [$Src16An],${Dsp-16-u8}[sb] */
16111
  {
16112
    { 0, 0, 0, 0 },
16113
    { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
16114
    & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_SB_relative_HI, { 0x816a00 }
16115
  },
16116
/* tst.w${X} $Src16RnHI,${Dsp-16-u16}[sb] */
16117
  {
16118
    { 0, 0, 0, 0 },
16119
    { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
16120
    & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_SB_relative_HI, { 0x810e0000 }
16121
  },
16122
/* tst.w${X} $Src16AnHI,${Dsp-16-u16}[sb] */
16123
  {
16124
    { 0, 0, 0, 0 },
16125
    { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
16126
    & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_SB_relative_HI, { 0x814e0000 }
16127
  },
16128
/* tst.w${X} [$Src16An],${Dsp-16-u16}[sb] */
16129
  {
16130
    { 0, 0, 0, 0 },
16131
    { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
16132
    & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_SB_relative_HI, { 0x816e0000 }
16133
  },
16134
/* tst.w${X} $Src16RnHI,${Dsp-16-s8}[fb] */
16135
  {
16136
    { 0, 0, 0, 0 },
16137
    { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
16138
    & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_FB_relative_HI, { 0x810b00 }
16139
  },
16140
/* tst.w${X} $Src16AnHI,${Dsp-16-s8}[fb] */
16141
  {
16142
    { 0, 0, 0, 0 },
16143
    { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
16144
    & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_FB_relative_HI, { 0x814b00 }
16145
  },
16146
/* tst.w${X} [$Src16An],${Dsp-16-s8}[fb] */
16147
  {
16148
    { 0, 0, 0, 0 },
16149
    { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
16150
    & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_FB_relative_HI, { 0x816b00 }
16151
  },
16152
/* tst.w${X} $Src16RnHI,${Dsp-16-u16} */
16153
  {
16154
    { 0, 0, 0, 0 },
16155
    { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), 0 } },
16156
    & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_absolute_HI, { 0x810f0000 }
16157
  },
16158
/* tst.w${X} $Src16AnHI,${Dsp-16-u16} */
16159
  {
16160
    { 0, 0, 0, 0 },
16161
    { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), 0 } },
16162
    & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_absolute_HI, { 0x814f0000 }
16163
  },
16164
/* tst.w${X} [$Src16An],${Dsp-16-u16} */
16165
  {
16166
    { 0, 0, 0, 0 },
16167
    { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } },
16168
    & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_absolute_HI, { 0x816f0000 }
16169
  },
16170
/* tst.b${X} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
16171
  {
16172
    { 0, 0, 0, 0 },
16173
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } },
16174
    & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_Rn_direct_QI, { 0x808000 }
16175
  },
16176
/* tst.b${X} ${Dsp-16-u8}[sb],$Dst16RnQI */
16177
  {
16178
    { 0, 0, 0, 0 },
16179
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } },
16180
    & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_Rn_direct_QI, { 0x80a000 }
16181
  },
16182
/* tst.b${X} ${Dsp-16-s8}[fb],$Dst16RnQI */
16183
  {
16184
    { 0, 0, 0, 0 },
16185
    { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNQI), 0 } },
16186
    & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_Rn_direct_QI, { 0x80b000 }
16187
  },
16188
/* tst.b${X} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
16189
  {
16190
    { 0, 0, 0, 0 },
16191
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } },
16192
    & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_direct_QI, { 0x808400 }
16193
  },
16194
/* tst.b${X} ${Dsp-16-u8}[sb],$Dst16AnQI */
16195
  {
16196
    { 0, 0, 0, 0 },
16197
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } },
16198
    & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_direct_QI, { 0x80a400 }
16199
  },
16200
/* tst.b${X} ${Dsp-16-s8}[fb],$Dst16AnQI */
16201
  {
16202
    { 0, 0, 0, 0 },
16203
    { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANQI), 0 } },
16204
    & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_direct_QI, { 0x80b400 }
16205
  },
16206
/* tst.b${X} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
16207
  {
16208
    { 0, 0, 0, 0 },
16209
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
16210
    & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_indirect_QI, { 0x808600 }
16211
  },
16212
/* tst.b${X} ${Dsp-16-u8}[sb],[$Dst16An] */
16213
  {
16214
    { 0, 0, 0, 0 },
16215
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
16216
    & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_indirect_QI, { 0x80a600 }
16217
  },
16218
/* tst.b${X} ${Dsp-16-s8}[fb],[$Dst16An] */
16219
  {
16220
    { 0, 0, 0, 0 },
16221
    { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
16222
    & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_indirect_QI, { 0x80b600 }
16223
  },
16224
/* tst.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
16225
  {
16226
    { 0, 0, 0, 0 },
16227
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
16228
    & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_An_relative_QI, { 0x80880000 }
16229
  },
16230
/* tst.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
16231
  {
16232
    { 0, 0, 0, 0 },
16233
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
16234
    & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_An_relative_QI, { 0x80a80000 }
16235
  },
16236
/* tst.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
16237
  {
16238
    { 0, 0, 0, 0 },
16239
    { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
16240
    & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_An_relative_QI, { 0x80b80000 }
16241
  },
16242
/* tst.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
16243
  {
16244
    { 0, 0, 0, 0 },
16245
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
16246
    & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_An_relative_QI, { 0x808c0000 }
16247
  },
16248
/* tst.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
16249
  {
16250
    { 0, 0, 0, 0 },
16251
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
16252
    & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_An_relative_QI, { 0x80ac0000 }
16253
  },
16254
/* tst.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
16255
  {
16256
    { 0, 0, 0, 0 },
16257
    { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
16258
    & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_An_relative_QI, { 0x80bc0000 }
16259
  },
16260
/* tst.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
16261
  {
16262
    { 0, 0, 0, 0 },
16263
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
16264
    & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_SB_relative_QI, { 0x808a0000 }
16265
  },
16266
/* tst.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
16267
  {
16268
    { 0, 0, 0, 0 },
16269
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
16270
    & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_SB_relative_QI, { 0x80aa0000 }
16271
  },
16272
/* tst.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
16273
  {
16274
    { 0, 0, 0, 0 },
16275
    { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
16276
    & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_SB_relative_QI, { 0x80ba0000 }
16277
  },
16278
/* tst.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
16279
  {
16280
    { 0, 0, 0, 0 },
16281
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
16282
    & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_SB_relative_QI, { 0x808e0000 }
16283
  },
16284
/* tst.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
16285
  {
16286
    { 0, 0, 0, 0 },
16287
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
16288
    & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_SB_relative_QI, { 0x80ae0000 }
16289
  },
16290
/* tst.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
16291
  {
16292
    { 0, 0, 0, 0 },
16293
    { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
16294
    & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_SB_relative_QI, { 0x80be0000 }
16295
  },
16296
/* tst.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
16297
  {
16298
    { 0, 0, 0, 0 },
16299
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
16300
    & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_FB_relative_QI, { 0x808b0000 }
16301
  },
16302
/* tst.b${X} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
16303
  {
16304
    { 0, 0, 0, 0 },
16305
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
16306
    & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_FB_relative_QI, { 0x80ab0000 }
16307
  },
16308
/* tst.b${X} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
16309
  {
16310
    { 0, 0, 0, 0 },
16311
    { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
16312
    & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_FB_relative_QI, { 0x80bb0000 }
16313
  },
16314
/* tst.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
16315
  {
16316
    { 0, 0, 0, 0 },
16317
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } },
16318
    & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_absolute_QI, { 0x808f0000 }
16319
  },
16320
/* tst.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
16321
  {
16322
    { 0, 0, 0, 0 },
16323
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
16324
    & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_absolute_QI, { 0x80af0000 }
16325
  },
16326
/* tst.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
16327
  {
16328
    { 0, 0, 0, 0 },
16329
    { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
16330
    & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_absolute_QI, { 0x80bf0000 }
16331
  },
16332
/* tst.b${X} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
16333
  {
16334
    { 0, 0, 0, 0 },
16335
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } },
16336
    & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_Rn_direct_QI, { 0x80c00000 }
16337
  },
16338
/* tst.b${X} ${Dsp-16-u16}[sb],$Dst16RnQI */
16339
  {
16340
    { 0, 0, 0, 0 },
16341
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } },
16342
    & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_Rn_direct_QI, { 0x80e00000 }
16343
  },
16344
/* tst.b${X} ${Dsp-16-u16},$Dst16RnQI */
16345
  {
16346
    { 0, 0, 0, 0 },
16347
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DST16RNQI), 0 } },
16348
    & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_Rn_direct_QI, { 0x80f00000 }
16349
  },
16350
/* tst.b${X} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
16351
  {
16352
    { 0, 0, 0, 0 },
16353
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } },
16354
    & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_direct_QI, { 0x80c40000 }
16355
  },
16356
/* tst.b${X} ${Dsp-16-u16}[sb],$Dst16AnQI */
16357
  {
16358
    { 0, 0, 0, 0 },
16359
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } },
16360
    & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_direct_QI, { 0x80e40000 }
16361
  },
16362
/* tst.b${X} ${Dsp-16-u16},$Dst16AnQI */
16363
  {
16364
    { 0, 0, 0, 0 },
16365
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DST16ANQI), 0 } },
16366
    & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_direct_QI, { 0x80f40000 }
16367
  },
16368
/* tst.b${X} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
16369
  {
16370
    { 0, 0, 0, 0 },
16371
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
16372
    & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_indirect_QI, { 0x80c60000 }
16373
  },
16374
/* tst.b${X} ${Dsp-16-u16}[sb],[$Dst16An] */
16375
  {
16376
    { 0, 0, 0, 0 },
16377
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
16378
    & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_indirect_QI, { 0x80e60000 }
16379
  },
16380
/* tst.b${X} ${Dsp-16-u16},[$Dst16An] */
16381
  {
16382
    { 0, 0, 0, 0 },
16383
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } },
16384
    & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_indirect_QI, { 0x80f60000 }
16385
  },
16386
/* tst.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
16387
  {
16388
    { 0, 0, 0, 0 },
16389
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
16390
    & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_An_relative_QI, { 0x80c80000 }
16391
  },
16392
/* tst.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
16393
  {
16394
    { 0, 0, 0, 0 },
16395
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
16396
    & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_An_relative_QI, { 0x80e80000 }
16397
  },
16398
/* tst.b${X} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
16399
  {
16400
    { 0, 0, 0, 0 },
16401
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
16402
    & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_An_relative_QI, { 0x80f80000 }
16403
  },
16404
/* tst.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
16405
  {
16406
    { 0, 0, 0, 0 },
16407
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
16408
    & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_An_relative_QI, { 0x80cc0000 }
16409
  },
16410
/* tst.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
16411
  {
16412
    { 0, 0, 0, 0 },
16413
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
16414
    & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_An_relative_QI, { 0x80ec0000 }
16415
  },
16416
/* tst.b${X} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
16417
  {
16418
    { 0, 0, 0, 0 },
16419
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
16420
    & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_An_relative_QI, { 0x80fc0000 }
16421
  },
16422
/* tst.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
16423
  {
16424
    { 0, 0, 0, 0 },
16425
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
16426
    & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_SB_relative_QI, { 0x80ca0000 }
16427
  },
16428
/* tst.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
16429
  {
16430
    { 0, 0, 0, 0 },
16431
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
16432
    & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_SB_relative_QI, { 0x80ea0000 }
16433
  },
16434
/* tst.b${X} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
16435
  {
16436
    { 0, 0, 0, 0 },
16437
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
16438
    & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_SB_relative_QI, { 0x80fa0000 }
16439
  },
16440
/* tst.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
16441
  {
16442
    { 0, 0, 0, 0 },
16443
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
16444
    & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_SB_relative_QI, { 0x80ce0000 }
16445
  },
16446
/* tst.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
16447
  {
16448
    { 0, 0, 0, 0 },
16449
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
16450
    & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_SB_relative_QI, { 0x80ee0000 }
16451
  },
16452
/* tst.b${X} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
16453
  {
16454
    { 0, 0, 0, 0 },
16455
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
16456
    & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_SB_relative_QI, { 0x80fe0000 }
16457
  },
16458
/* tst.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
16459
  {
16460
    { 0, 0, 0, 0 },
16461
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
16462
    & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_FB_relative_QI, { 0x80cb0000 }
16463
  },
16464
/* tst.b${X} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
16465
  {
16466
    { 0, 0, 0, 0 },
16467
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
16468
    & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_FB_relative_QI, { 0x80eb0000 }
16469
  },
16470
/* tst.b${X} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
16471
  {
16472
    { 0, 0, 0, 0 },
16473
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
16474
    & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_FB_relative_QI, { 0x80fb0000 }
16475
  },
16476
/* tst.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
16477
  {
16478
    { 0, 0, 0, 0 },
16479
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } },
16480
    & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_absolute_QI, { 0x80cf0000 }
16481
  },
16482
/* tst.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
16483
  {
16484
    { 0, 0, 0, 0 },
16485
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
16486
    & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_absolute_QI, { 0x80ef0000 }
16487
  },
16488
/* tst.b${X} ${Dsp-16-u16},${Dsp-32-u16} */
16489
  {
16490
    { 0, 0, 0, 0 },
16491
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
16492
    & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_absolute_QI, { 0x80ff0000 }
16493
  },
16494
/* tst.b${X} $Src16RnQI,$Dst16RnQI */
16495
  {
16496
    { 0, 0, 0, 0 },
16497
    { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DST16RNQI), 0 } },
16498
    & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_Rn_direct_QI, { 0x8000 }
16499
  },
16500
/* tst.b${X} $Src16AnQI,$Dst16RnQI */
16501
  {
16502
    { 0, 0, 0, 0 },
16503
    { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DST16RNQI), 0 } },
16504
    & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_Rn_direct_QI, { 0x8040 }
16505
  },
16506
/* tst.b${X} [$Src16An],$Dst16RnQI */
16507
  {
16508
    { 0, 0, 0, 0 },
16509
    { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } },
16510
    & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_Rn_direct_QI, { 0x8060 }
16511
  },
16512
/* tst.b${X} $Src16RnQI,$Dst16AnQI */
16513
  {
16514
    { 0, 0, 0, 0 },
16515
    { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DST16ANQI), 0 } },
16516
    & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_direct_QI, { 0x8004 }
16517
  },
16518
/* tst.b${X} $Src16AnQI,$Dst16AnQI */
16519
  {
16520
    { 0, 0, 0, 0 },
16521
    { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DST16ANQI), 0 } },
16522
    & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_direct_QI, { 0x8044 }
16523
  },
16524
/* tst.b${X} [$Src16An],$Dst16AnQI */
16525
  {
16526
    { 0, 0, 0, 0 },
16527
    { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } },
16528
    & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_direct_QI, { 0x8064 }
16529
  },
16530
/* tst.b${X} $Src16RnQI,[$Dst16An] */
16531
  {
16532
    { 0, 0, 0, 0 },
16533
    { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', '[', OP (DST16AN), ']', 0 } },
16534
    & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_indirect_QI, { 0x8006 }
16535
  },
16536
/* tst.b${X} $Src16AnQI,[$Dst16An] */
16537
  {
16538
    { 0, 0, 0, 0 },
16539
    { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', '[', OP (DST16AN), ']', 0 } },
16540
    & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_indirect_QI, { 0x8046 }
16541
  },
16542
/* tst.b${X} [$Src16An],[$Dst16An] */
16543
  {
16544
    { 0, 0, 0, 0 },
16545
    { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
16546
    & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_indirect_QI, { 0x8066 }
16547
  },
16548
/* tst.b${X} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
16549
  {
16550
    { 0, 0, 0, 0 },
16551
    { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
16552
    & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_An_relative_QI, { 0x800800 }
16553
  },
16554
/* tst.b${X} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
16555
  {
16556
    { 0, 0, 0, 0 },
16557
    { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
16558
    & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_An_relative_QI, { 0x804800 }
16559
  },
16560
/* tst.b${X} [$Src16An],${Dsp-16-u8}[$Dst16An] */
16561
  {
16562
    { 0, 0, 0, 0 },
16563
    { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
16564
    & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_An_relative_QI, { 0x806800 }
16565
  },
16566
/* tst.b${X} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
16567
  {
16568
    { 0, 0, 0, 0 },
16569
    { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
16570
    & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_An_relative_QI, { 0x800c0000 }
16571
  },
16572
/* tst.b${X} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
16573
  {
16574
    { 0, 0, 0, 0 },
16575
    { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
16576
    & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_An_relative_QI, { 0x804c0000 }
16577
  },
16578
/* tst.b${X} [$Src16An],${Dsp-16-u16}[$Dst16An] */
16579
  {
16580
    { 0, 0, 0, 0 },
16581
    { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
16582
    & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_An_relative_QI, { 0x806c0000 }
16583
  },
16584
/* tst.b${X} $Src16RnQI,${Dsp-16-u8}[sb] */
16585
  {
16586
    { 0, 0, 0, 0 },
16587
    { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
16588
    & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_SB_relative_QI, { 0x800a00 }
16589
  },
16590
/* tst.b${X} $Src16AnQI,${Dsp-16-u8}[sb] */
16591
  {
16592
    { 0, 0, 0, 0 },
16593
    { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
16594
    & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_SB_relative_QI, { 0x804a00 }
16595
  },
16596
/* tst.b${X} [$Src16An],${Dsp-16-u8}[sb] */
16597
  {
16598
    { 0, 0, 0, 0 },
16599
    { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
16600
    & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_SB_relative_QI, { 0x806a00 }
16601
  },
16602
/* tst.b${X} $Src16RnQI,${Dsp-16-u16}[sb] */
16603
  {
16604
    { 0, 0, 0, 0 },
16605
    { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
16606
    & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_SB_relative_QI, { 0x800e0000 }
16607
  },
16608
/* tst.b${X} $Src16AnQI,${Dsp-16-u16}[sb] */
16609
  {
16610
    { 0, 0, 0, 0 },
16611
    { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
16612
    & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_SB_relative_QI, { 0x804e0000 }
16613
  },
16614
/* tst.b${X} [$Src16An],${Dsp-16-u16}[sb] */
16615
  {
16616
    { 0, 0, 0, 0 },
16617
    { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
16618
    & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_SB_relative_QI, { 0x806e0000 }
16619
  },
16620
/* tst.b${X} $Src16RnQI,${Dsp-16-s8}[fb] */
16621
  {
16622
    { 0, 0, 0, 0 },
16623
    { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
16624
    & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_FB_relative_QI, { 0x800b00 }
16625
  },
16626
/* tst.b${X} $Src16AnQI,${Dsp-16-s8}[fb] */
16627
  {
16628
    { 0, 0, 0, 0 },
16629
    { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
16630
    & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_FB_relative_QI, { 0x804b00 }
16631
  },
16632
/* tst.b${X} [$Src16An],${Dsp-16-s8}[fb] */
16633
  {
16634
    { 0, 0, 0, 0 },
16635
    { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
16636
    & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_FB_relative_QI, { 0x806b00 }
16637
  },
16638
/* tst.b${X} $Src16RnQI,${Dsp-16-u16} */
16639
  {
16640
    { 0, 0, 0, 0 },
16641
    { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), 0 } },
16642
    & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_absolute_QI, { 0x800f0000 }
16643
  },
16644
/* tst.b${X} $Src16AnQI,${Dsp-16-u16} */
16645
  {
16646
    { 0, 0, 0, 0 },
16647
    { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), 0 } },
16648
    & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_absolute_QI, { 0x804f0000 }
16649
  },
16650
/* tst.b${X} [$Src16An],${Dsp-16-u16} */
16651
  {
16652
    { 0, 0, 0, 0 },
16653
    { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } },
16654
    & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_absolute_QI, { 0x806f0000 }
16655
  },
16656
/* tst.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */
16657
  {
16658
    { 0, 0, 0, 0 },
16659
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
16660
    & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0x993e0000 }
16661
  },
16662
/* tst.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */
16663
  {
16664
    { 0, 0, 0, 0 },
16665
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
16666
    & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0x91be0000 }
16667
  },
16668
/* tst.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */
16669
  {
16670
    { 0, 0, 0, 0 },
16671
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
16672
    & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0x913e0000 }
16673
  },
16674
/* tst.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
16675
  {
16676
    { 0, 0, 0, 0 },
16677
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
16678
    & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0x933e0000 }
16679
  },
16680
/* tst.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
16681
  {
16682
    { 0, 0, 0, 0 },
16683
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
16684
    & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0x93be0000 }
16685
  },
16686
/* tst.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
16687
  {
16688
    { 0, 0, 0, 0 },
16689
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
16690
    & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0x93fe0000 }
16691
  },
16692
/* tst.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
16693
  {
16694
    { 0, 0, 0, 0 },
16695
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
16696
    & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0x953e0000 }
16697
  },
16698
/* tst.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
16699
  {
16700
    { 0, 0, 0, 0 },
16701
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
16702
    & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0x95be0000 }
16703
  },
16704
/* tst.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */
16705
  {
16706
    { 0, 0, 0, 0 },
16707
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
16708
    & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0x95fe0000 }
16709
  },
16710
/* tst.w${G} #${Imm-32-HI},${Dsp-16-u16} */
16711
  {
16712
    { 0, 0, 0, 0 },
16713
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } },
16714
    & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0x97fe0000 }
16715
  },
16716
/* tst.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
16717
  {
16718
    { 0, 0, 0, 0 },
16719
    { { MNEM, OP (G), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
16720
    & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0x973e0000 }
16721
  },
16722
/* tst.w${G} #${Imm-40-HI},${Dsp-16-u24} */
16723
  {
16724
    { 0, 0, 0, 0 },
16725
    { { MNEM, OP (G), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), 0 } },
16726
    & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0x97be0000 }
16727
  },
16728
/* tst.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */
16729
  {
16730
    { 0, 0, 0, 0 },
16731
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
16732
    & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0x983e00 }
16733
  },
16734
/* tst.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */
16735
  {
16736
    { 0, 0, 0, 0 },
16737
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
16738
    & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0x90be00 }
16739
  },
16740
/* tst.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */
16741
  {
16742
    { 0, 0, 0, 0 },
16743
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
16744
    & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0x903e00 }
16745
  },
16746
/* tst.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
16747
  {
16748
    { 0, 0, 0, 0 },
16749
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
16750
    & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0x923e0000 }
16751
  },
16752
/* tst.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
16753
  {
16754
    { 0, 0, 0, 0 },
16755
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
16756
    & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0x92be0000 }
16757
  },
16758
/* tst.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
16759
  {
16760
    { 0, 0, 0, 0 },
16761
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
16762
    & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0x92fe0000 }
16763
  },
16764
/* tst.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
16765
  {
16766
    { 0, 0, 0, 0 },
16767
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
16768
    & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0x943e0000 }
16769
  },
16770
/* tst.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
16771
  {
16772
    { 0, 0, 0, 0 },
16773
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
16774
    & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0x94be0000 }
16775
  },
16776
/* tst.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */
16777
  {
16778
    { 0, 0, 0, 0 },
16779
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
16780
    & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0x94fe0000 }
16781
  },
16782
/* tst.b${G} #${Imm-32-QI},${Dsp-16-u16} */
16783
  {
16784
    { 0, 0, 0, 0 },
16785
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } },
16786
    & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0x96fe0000 }
16787
  },
16788
/* tst.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
16789
  {
16790
    { 0, 0, 0, 0 },
16791
    { { MNEM, OP (G), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
16792
    & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0x963e0000 }
16793
  },
16794
/* tst.b${G} #${Imm-40-QI},${Dsp-16-u24} */
16795
  {
16796
    { 0, 0, 0, 0 },
16797
    { { MNEM, OP (G), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), 0 } },
16798
    & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0x96be0000 }
16799
  },
16800
/* tst.w${G} #${Imm-16-HI},$Dst16RnHI */
16801
  {
16802
    { 0, 0, 0, 0 },
16803
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST16RNHI), 0 } },
16804
    & ifmt_xor16_w_imm_G_basic_dst16_Rn_direct_HI, { 0x77000000 }
16805
  },
16806
/* tst.w${G} #${Imm-16-HI},$Dst16AnHI */
16807
  {
16808
    { 0, 0, 0, 0 },
16809
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST16ANHI), 0 } },
16810
    & ifmt_xor16_w_imm_G_basic_dst16_An_direct_HI, { 0x77040000 }
16811
  },
16812
/* tst.w${G} #${Imm-16-HI},[$Dst16An] */
16813
  {
16814
    { 0, 0, 0, 0 },
16815
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST16AN), ']', 0 } },
16816
    & ifmt_xor16_w_imm_G_basic_dst16_An_indirect_HI, { 0x77060000 }
16817
  },
16818
/* tst.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
16819
  {
16820
    { 0, 0, 0, 0 },
16821
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
16822
    & ifmt_xor16_w_imm_G_16_8_dst16_16_8_An_relative_HI, { 0x77080000 }
16823
  },
16824
/* tst.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
16825
  {
16826
    { 0, 0, 0, 0 },
16827
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
16828
    & ifmt_xor16_w_imm_G_16_8_dst16_16_8_SB_relative_HI, { 0x770a0000 }
16829
  },
16830
/* tst.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
16831
  {
16832
    { 0, 0, 0, 0 },
16833
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
16834
    & ifmt_xor16_w_imm_G_16_8_dst16_16_8_FB_relative_HI, { 0x770b0000 }
16835
  },
16836
/* tst.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
16837
  {
16838
    { 0, 0, 0, 0 },
16839
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
16840
    & ifmt_xor16_w_imm_G_16_16_dst16_16_16_An_relative_HI, { 0x770c0000 }
16841
  },
16842
/* tst.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
16843
  {
16844
    { 0, 0, 0, 0 },
16845
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
16846
    & ifmt_xor16_w_imm_G_16_16_dst16_16_16_SB_relative_HI, { 0x770e0000 }
16847
  },
16848
/* tst.w${G} #${Imm-32-HI},${Dsp-16-u16} */
16849
  {
16850
    { 0, 0, 0, 0 },
16851
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } },
16852
    & ifmt_xor16_w_imm_G_16_16_dst16_16_16_absolute_HI, { 0x770f0000 }
16853
  },
16854
/* tst.b${G} #${Imm-16-QI},$Dst16RnQI */
16855
  {
16856
    { 0, 0, 0, 0 },
16857
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST16RNQI), 0 } },
16858
    & ifmt_xor16_b_imm_G_basic_dst16_Rn_direct_QI, { 0x760000 }
16859
  },
16860
/* tst.b${G} #${Imm-16-QI},$Dst16AnQI */
16861
  {
16862
    { 0, 0, 0, 0 },
16863
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST16ANQI), 0 } },
16864
    & ifmt_xor16_b_imm_G_basic_dst16_An_direct_QI, { 0x760400 }
16865
  },
16866
/* tst.b${G} #${Imm-16-QI},[$Dst16An] */
16867
  {
16868
    { 0, 0, 0, 0 },
16869
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST16AN), ']', 0 } },
16870
    & ifmt_xor16_b_imm_G_basic_dst16_An_indirect_QI, { 0x760600 }
16871
  },
16872
/* tst.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
16873
  {
16874
    { 0, 0, 0, 0 },
16875
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
16876
    & ifmt_xor16_b_imm_G_16_8_dst16_16_8_An_relative_QI, { 0x76080000 }
16877
  },
16878
/* tst.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
16879
  {
16880
    { 0, 0, 0, 0 },
16881
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
16882
    & ifmt_xor16_b_imm_G_16_8_dst16_16_8_SB_relative_QI, { 0x760a0000 }
16883
  },
16884
/* tst.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
16885
  {
16886
    { 0, 0, 0, 0 },
16887
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
16888
    & ifmt_xor16_b_imm_G_16_8_dst16_16_8_FB_relative_QI, { 0x760b0000 }
16889
  },
16890
/* tst.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
16891
  {
16892
    { 0, 0, 0, 0 },
16893
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
16894
    & ifmt_xor16_b_imm_G_16_16_dst16_16_16_An_relative_QI, { 0x760c0000 }
16895
  },
16896
/* tst.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
16897
  {
16898
    { 0, 0, 0, 0 },
16899
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
16900
    & ifmt_xor16_b_imm_G_16_16_dst16_16_16_SB_relative_QI, { 0x760e0000 }
16901
  },
16902
/* tst.b${G} #${Imm-32-QI},${Dsp-16-u16} */
16903
  {
16904
    { 0, 0, 0, 0 },
16905
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } },
16906
    & ifmt_xor16_b_imm_G_16_16_dst16_16_16_absolute_QI, { 0x760f0000 }
16907
  },
16908
/* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
16909
  {
16910
    { 0, 0, 0, 0 },
16911
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
16912
    & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0x980000 }
16913
  },
16914
/* subx${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedSI */
16915
  {
16916
    { 0, 0, 0, 0 },
16917
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
16918
    & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0x982000 }
16919
  },
16920
/* subx${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedSI */
16921
  {
16922
    { 0, 0, 0, 0 },
16923
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
16924
    & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0x983000 }
16925
  },
16926
/* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
16927
  {
16928
    { 0, 0, 0, 0 },
16929
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
16930
    & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0x908000 }
16931
  },
16932
/* subx${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedSI */
16933
  {
16934
    { 0, 0, 0, 0 },
16935
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
16936
    & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0x90a000 }
16937
  },
16938
/* subx${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedSI */
16939
  {
16940
    { 0, 0, 0, 0 },
16941
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
16942
    & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0x90b000 }
16943
  },
16944
/* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
16945
  {
16946
    { 0, 0, 0, 0 },
16947
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
16948
    & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0x900000 }
16949
  },
16950
/* subx${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
16951
  {
16952
    { 0, 0, 0, 0 },
16953
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
16954
    & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0x902000 }
16955
  },
16956
/* subx${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
16957
  {
16958
    { 0, 0, 0, 0 },
16959
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
16960
    & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0x903000 }
16961
  },
16962
/* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
16963
  {
16964
    { 0, 0, 0, 0 },
16965
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
16966
    & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_SI, { 0x92000000 }
16967
  },
16968
/* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
16969
  {
16970
    { 0, 0, 0, 0 },
16971
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
16972
    & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_SI, { 0x92200000 }
16973
  },
16974
/* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
16975
  {
16976
    { 0, 0, 0, 0 },
16977
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
16978
    & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_SI, { 0x92300000 }
16979
  },
16980
/* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
16981
  {
16982
    { 0, 0, 0, 0 },
16983
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
16984
    & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_SI, { 0x94000000 }
16985
  },
16986
/* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
16987
  {
16988
    { 0, 0, 0, 0 },
16989
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
16990
    & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_SI, { 0x94200000 }
16991
  },
16992
/* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
16993
  {
16994
    { 0, 0, 0, 0 },
16995
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
16996
    & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_SI, { 0x94300000 }
16997
  },
16998
/* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
16999
  {
17000
    { 0, 0, 0, 0 },
17001
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17002
    & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_SI, { 0x96000000 }
17003
  },
17004
/* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
17005
  {
17006
    { 0, 0, 0, 0 },
17007
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17008
    & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_SI, { 0x96200000 }
17009
  },
17010
/* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
17011
  {
17012
    { 0, 0, 0, 0 },
17013
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17014
    & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_SI, { 0x96300000 }
17015
  },
17016
/* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
17017
  {
17018
    { 0, 0, 0, 0 },
17019
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
17020
    & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_SI, { 0x92800000 }
17021
  },
17022
/* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
17023
  {
17024
    { 0, 0, 0, 0 },
17025
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
17026
    & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_SI, { 0x92a00000 }
17027
  },
17028
/* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
17029
  {
17030
    { 0, 0, 0, 0 },
17031
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
17032
    & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_SI, { 0x92b00000 }
17033
  },
17034
/* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
17035
  {
17036
    { 0, 0, 0, 0 },
17037
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
17038
    & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_SI, { 0x94800000 }
17039
  },
17040
/* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
17041
  {
17042
    { 0, 0, 0, 0 },
17043
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
17044
    & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_SI, { 0x94a00000 }
17045
  },
17046
/* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
17047
  {
17048
    { 0, 0, 0, 0 },
17049
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
17050
    & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_SI, { 0x94b00000 }
17051
  },
17052
/* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
17053
  {
17054
    { 0, 0, 0, 0 },
17055
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
17056
    & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_SI, { 0x92c00000 }
17057
  },
17058
/* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
17059
  {
17060
    { 0, 0, 0, 0 },
17061
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
17062
    & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_SI, { 0x92e00000 }
17063
  },
17064
/* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
17065
  {
17066
    { 0, 0, 0, 0 },
17067
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
17068
    & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_SI, { 0x92f00000 }
17069
  },
17070
/* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
17071
  {
17072
    { 0, 0, 0, 0 },
17073
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
17074
    & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_SI, { 0x94c00000 }
17075
  },
17076
/* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
17077
  {
17078
    { 0, 0, 0, 0 },
17079
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
17080
    & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_SI, { 0x94e00000 }
17081
  },
17082
/* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
17083
  {
17084
    { 0, 0, 0, 0 },
17085
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
17086
    & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_SI, { 0x94f00000 }
17087
  },
17088
/* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
17089
  {
17090
    { 0, 0, 0, 0 },
17091
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
17092
    & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_SI, { 0x96c00000 }
17093
  },
17094
/* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
17095
  {
17096
    { 0, 0, 0, 0 },
17097
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
17098
    & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_SI, { 0x96e00000 }
17099
  },
17100
/* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
17101
  {
17102
    { 0, 0, 0, 0 },
17103
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
17104
    & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_SI, { 0x96f00000 }
17105
  },
17106
/* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
17107
  {
17108
    { 0, 0, 0, 0 },
17109
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
17110
    & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_SI, { 0x96800000 }
17111
  },
17112
/* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
17113
  {
17114
    { 0, 0, 0, 0 },
17115
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } },
17116
    & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_SI, { 0x96a00000 }
17117
  },
17118
/* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
17119
  {
17120
    { 0, 0, 0, 0 },
17121
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } },
17122
    & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_SI, { 0x96b00000 }
17123
  },
17124
/* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
17125
  {
17126
    { 0, 0, 0, 0 },
17127
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
17128
    & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0xa8000000 }
17129
  },
17130
/* subx${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedSI */
17131
  {
17132
    { 0, 0, 0, 0 },
17133
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
17134
    & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0xa8200000 }
17135
  },
17136
/* subx${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedSI */
17137
  {
17138
    { 0, 0, 0, 0 },
17139
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
17140
    & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0xa8300000 }
17141
  },
17142
/* subx${G} ${Dsp-16-u16},$Dst32RnUnprefixedSI */
17143
  {
17144
    { 0, 0, 0, 0 },
17145
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
17146
    & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0xb8300000 }
17147
  },
17148
/* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
17149
  {
17150
    { 0, 0, 0, 0 },
17151
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
17152
    & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0xa0800000 }
17153
  },
17154
/* subx${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedSI */
17155
  {
17156
    { 0, 0, 0, 0 },
17157
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
17158
    & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0xa0a00000 }
17159
  },
17160
/* subx${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedSI */
17161
  {
17162
    { 0, 0, 0, 0 },
17163
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
17164
    & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0xa0b00000 }
17165
  },
17166
/* subx${G} ${Dsp-16-u16},$Dst32AnUnprefixedSI */
17167
  {
17168
    { 0, 0, 0, 0 },
17169
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
17170
    & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0xb0b00000 }
17171
  },
17172
/* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
17173
  {
17174
    { 0, 0, 0, 0 },
17175
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17176
    & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0xa0000000 }
17177
  },
17178
/* subx${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
17179
  {
17180
    { 0, 0, 0, 0 },
17181
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17182
    & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0xa0200000 }
17183
  },
17184
/* subx${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
17185
  {
17186
    { 0, 0, 0, 0 },
17187
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17188
    & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0xa0300000 }
17189
  },
17190
/* subx${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
17191
  {
17192
    { 0, 0, 0, 0 },
17193
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17194
    & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0xb0300000 }
17195
  },
17196
/* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
17197
  {
17198
    { 0, 0, 0, 0 },
17199
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17200
    & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_SI, { 0xa2000000 }
17201
  },
17202
/* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
17203
  {
17204
    { 0, 0, 0, 0 },
17205
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17206
    & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_SI, { 0xa2200000 }
17207
  },
17208
/* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
17209
  {
17210
    { 0, 0, 0, 0 },
17211
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17212
    & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_SI, { 0xa2300000 }
17213
  },
17214
/* subx${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
17215
  {
17216
    { 0, 0, 0, 0 },
17217
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17218
    & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_SI, { 0xb2300000 }
17219
  },
17220
/* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
17221
  {
17222
    { 0, 0, 0, 0 },
17223
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17224
    & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_SI, { 0xa4000000 }
17225
  },
17226
/* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
17227
  {
17228
    { 0, 0, 0, 0 },
17229
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17230
    & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_SI, { 0xa4200000 }
17231
  },
17232
/* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
17233
  {
17234
    { 0, 0, 0, 0 },
17235
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17236
    & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_SI, { 0xa4300000 }
17237
  },
17238
/* subx${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
17239
  {
17240
    { 0, 0, 0, 0 },
17241
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17242
    & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_SI, { 0xb4300000 }
17243
  },
17244
/* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
17245
  {
17246
    { 0, 0, 0, 0 },
17247
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17248
    & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_SI, { 0xa6000000 }
17249
  },
17250
/* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
17251
  {
17252
    { 0, 0, 0, 0 },
17253
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17254
    & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_SI, { 0xa6200000 }
17255
  },
17256
/* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
17257
  {
17258
    { 0, 0, 0, 0 },
17259
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17260
    & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_SI, { 0xa6300000 }
17261
  },
17262
/* subx${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
17263
  {
17264
    { 0, 0, 0, 0 },
17265
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17266
    & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_SI, { 0xb6300000 }
17267
  },
17268
/* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
17269
  {
17270
    { 0, 0, 0, 0 },
17271
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
17272
    & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xa2800000 }
17273
  },
17274
/* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
17275
  {
17276
    { 0, 0, 0, 0 },
17277
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
17278
    & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xa2a00000 }
17279
  },
17280
/* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
17281
  {
17282
    { 0, 0, 0, 0 },
17283
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
17284
    & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xa2b00000 }
17285
  },
17286
/* subx${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
17287
  {
17288
    { 0, 0, 0, 0 },
17289
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
17290
    & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xb2b00000 }
17291
  },
17292
/* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
17293
  {
17294
    { 0, 0, 0, 0 },
17295
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
17296
    & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xa4800000 }
17297
  },
17298
/* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
17299
  {
17300
    { 0, 0, 0, 0 },
17301
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
17302
    & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xa4a00000 }
17303
  },
17304
/* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
17305
  {
17306
    { 0, 0, 0, 0 },
17307
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
17308
    & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xa4b00000 }
17309
  },
17310
/* subx${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
17311
  {
17312
    { 0, 0, 0, 0 },
17313
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
17314
    & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xb4b00000 }
17315
  },
17316
/* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
17317
  {
17318
    { 0, 0, 0, 0 },
17319
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
17320
    & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xa2c00000 }
17321
  },
17322
/* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
17323
  {
17324
    { 0, 0, 0, 0 },
17325
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
17326
    & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xa2e00000 }
17327
  },
17328
/* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
17329
  {
17330
    { 0, 0, 0, 0 },
17331
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
17332
    & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xa2f00000 }
17333
  },
17334
/* subx${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
17335
  {
17336
    { 0, 0, 0, 0 },
17337
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
17338
    & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xb2f00000 }
17339
  },
17340
/* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
17341
  {
17342
    { 0, 0, 0, 0 },
17343
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
17344
    & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xa4c00000 }
17345
  },
17346
/* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
17347
  {
17348
    { 0, 0, 0, 0 },
17349
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
17350
    & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xa4e00000 }
17351
  },
17352
/* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
17353
  {
17354
    { 0, 0, 0, 0 },
17355
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
17356
    & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xa4f00000 }
17357
  },
17358
/* subx${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
17359
  {
17360
    { 0, 0, 0, 0 },
17361
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
17362
    & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xb4f00000 }
17363
  },
17364
/* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
17365
  {
17366
    { 0, 0, 0, 0 },
17367
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
17368
    & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_SI, { 0xa6c00000 }
17369
  },
17370
/* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
17371
  {
17372
    { 0, 0, 0, 0 },
17373
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
17374
    & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_SI, { 0xa6e00000 }
17375
  },
17376
/* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
17377
  {
17378
    { 0, 0, 0, 0 },
17379
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
17380
    & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_SI, { 0xa6f00000 }
17381
  },
17382
/* subx${G} ${Dsp-16-u16},${Dsp-32-u16} */
17383
  {
17384
    { 0, 0, 0, 0 },
17385
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
17386
    & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_SI, { 0xb6f00000 }
17387
  },
17388
/* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
17389
  {
17390
    { 0, 0, 0, 0 },
17391
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
17392
    & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_SI, { 0xa6800000 }
17393
  },
17394
/* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
17395
  {
17396
    { 0, 0, 0, 0 },
17397
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
17398
    & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_SI, { 0xa6a00000 }
17399
  },
17400
/* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
17401
  {
17402
    { 0, 0, 0, 0 },
17403
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
17404
    & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_SI, { 0xa6b00000 }
17405
  },
17406
/* subx${G} ${Dsp-16-u16},${Dsp-32-u24} */
17407
  {
17408
    { 0, 0, 0, 0 },
17409
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } },
17410
    & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_SI, { 0xb6b00000 }
17411
  },
17412
/* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
17413
  {
17414
    { 0, 0, 0, 0 },
17415
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
17416
    & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0xb8000000 }
17417
  },
17418
/* subx${G} ${Dsp-16-u24},$Dst32RnUnprefixedSI */
17419
  {
17420
    { 0, 0, 0, 0 },
17421
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
17422
    & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0xb8200000 }
17423
  },
17424
/* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
17425
  {
17426
    { 0, 0, 0, 0 },
17427
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
17428
    & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0xb0800000 }
17429
  },
17430
/* subx${G} ${Dsp-16-u24},$Dst32AnUnprefixedSI */
17431
  {
17432
    { 0, 0, 0, 0 },
17433
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
17434
    & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0xb0a00000 }
17435
  },
17436
/* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
17437
  {
17438
    { 0, 0, 0, 0 },
17439
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17440
    & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0xb0000000 }
17441
  },
17442
/* subx${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
17443
  {
17444
    { 0, 0, 0, 0 },
17445
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17446
    & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0xb0200000 }
17447
  },
17448
/* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
17449
  {
17450
    { 0, 0, 0, 0 },
17451
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17452
    & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_SI, { 0xb2000000 }
17453
  },
17454
/* subx${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
17455
  {
17456
    { 0, 0, 0, 0 },
17457
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17458
    & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_SI, { 0xb2200000 }
17459
  },
17460
/* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
17461
  {
17462
    { 0, 0, 0, 0 },
17463
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17464
    & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_SI, { 0xb4000000 }
17465
  },
17466
/* subx${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
17467
  {
17468
    { 0, 0, 0, 0 },
17469
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17470
    & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_SI, { 0xb4200000 }
17471
  },
17472
/* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
17473
  {
17474
    { 0, 0, 0, 0 },
17475
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17476
    & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_SI, { 0xb6000000 }
17477
  },
17478
/* subx${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
17479
  {
17480
    { 0, 0, 0, 0 },
17481
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17482
    & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_SI, { 0xb6200000 }
17483
  },
17484
/* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
17485
  {
17486
    { 0, 0, 0, 0 },
17487
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
17488
    & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_SI, { 0xb2800000 }
17489
  },
17490
/* subx${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
17491
  {
17492
    { 0, 0, 0, 0 },
17493
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
17494
    & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_SI, { 0xb2a00000 }
17495
  },
17496
/* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
17497
  {
17498
    { 0, 0, 0, 0 },
17499
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
17500
    & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_SI, { 0xb4800000 }
17501
  },
17502
/* subx${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
17503
  {
17504
    { 0, 0, 0, 0 },
17505
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
17506
    & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_SI, { 0xb4a00000 }
17507
  },
17508
/* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
17509
  {
17510
    { 0, 0, 0, 0 },
17511
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
17512
    & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_SI, { 0xb2c00000 }
17513
  },
17514
/* subx${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
17515
  {
17516
    { 0, 0, 0, 0 },
17517
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
17518
    & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_SI, { 0xb2e00000 }
17519
  },
17520
/* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
17521
  {
17522
    { 0, 0, 0, 0 },
17523
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
17524
    & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_SI, { 0xb4c00000 }
17525
  },
17526
/* subx${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
17527
  {
17528
    { 0, 0, 0, 0 },
17529
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
17530
    & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_SI, { 0xb4e00000 }
17531
  },
17532
/* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
17533
  {
17534
    { 0, 0, 0, 0 },
17535
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
17536
    & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_SI, { 0xb6c00000 }
17537
  },
17538
/* subx${G} ${Dsp-16-u24},${Dsp-40-u16} */
17539
  {
17540
    { 0, 0, 0, 0 },
17541
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } },
17542
    & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_SI, { 0xb6e00000 }
17543
  },
17544
/* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
17545
  {
17546
    { 0, 0, 0, 0 },
17547
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
17548
    & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_SI, { 0xb6800000 }
17549
  },
17550
/* subx${G} ${Dsp-16-u24},${Dsp-40-u24} */
17551
  {
17552
    { 0, 0, 0, 0 },
17553
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } },
17554
    & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_SI, { 0xb6a00000 }
17555
  },
17556
/* subx${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedSI */
17557
  {
17558
    { 0, 0, 0, 0 },
17559
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
17560
    & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0xc800 }
17561
  },
17562
/* subx${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedSI */
17563
  {
17564
    { 0, 0, 0, 0 },
17565
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
17566
    & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0x8820 }
17567
  },
17568
/* subx${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
17569
  {
17570
    { 0, 0, 0, 0 },
17571
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
17572
    & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0x8800 }
17573
  },
17574
/* subx${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedSI */
17575
  {
17576
    { 0, 0, 0, 0 },
17577
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
17578
    & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0xc080 }
17579
  },
17580
/* subx${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedSI */
17581
  {
17582
    { 0, 0, 0, 0 },
17583
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
17584
    & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0x80a0 }
17585
  },
17586
/* subx${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
17587
  {
17588
    { 0, 0, 0, 0 },
17589
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
17590
    & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0x8080 }
17591
  },
17592
/* subx${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */
17593
  {
17594
    { 0, 0, 0, 0 },
17595
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17596
    & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0xc000 }
17597
  },
17598
/* subx${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */
17599
  {
17600
    { 0, 0, 0, 0 },
17601
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17602
    & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0x8020 }
17603
  },
17604
/* subx${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
17605
  {
17606
    { 0, 0, 0, 0 },
17607
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17608
    & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0x8000 }
17609
  },
17610
/* subx${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
17611
  {
17612
    { 0, 0, 0, 0 },
17613
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17614
    & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_SI, { 0xc20000 }
17615
  },
17616
/* subx${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
17617
  {
17618
    { 0, 0, 0, 0 },
17619
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17620
    & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_SI, { 0x822000 }
17621
  },
17622
/* subx${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
17623
  {
17624
    { 0, 0, 0, 0 },
17625
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17626
    & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_SI, { 0x820000 }
17627
  },
17628
/* subx${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
17629
  {
17630
    { 0, 0, 0, 0 },
17631
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17632
    & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_SI, { 0xc4000000 }
17633
  },
17634
/* subx${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
17635
  {
17636
    { 0, 0, 0, 0 },
17637
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17638
    & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_SI, { 0x84200000 }
17639
  },
17640
/* subx${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
17641
  {
17642
    { 0, 0, 0, 0 },
17643
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17644
    & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_SI, { 0x84000000 }
17645
  },
17646
/* subx${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
17647
  {
17648
    { 0, 0, 0, 0 },
17649
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17650
    & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_SI, { 0xc6000000 }
17651
  },
17652
/* subx${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
17653
  {
17654
    { 0, 0, 0, 0 },
17655
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17656
    & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_SI, { 0x86200000 }
17657
  },
17658
/* subx${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
17659
  {
17660
    { 0, 0, 0, 0 },
17661
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17662
    & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_SI, { 0x86000000 }
17663
  },
17664
/* subx${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */
17665
  {
17666
    { 0, 0, 0, 0 },
17667
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
17668
    & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_SI, { 0xc28000 }
17669
  },
17670
/* subx${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */
17671
  {
17672
    { 0, 0, 0, 0 },
17673
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
17674
    & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_SI, { 0x82a000 }
17675
  },
17676
/* subx${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
17677
  {
17678
    { 0, 0, 0, 0 },
17679
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
17680
    & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_SI, { 0x828000 }
17681
  },
17682
/* subx${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */
17683
  {
17684
    { 0, 0, 0, 0 },
17685
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
17686
    & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_SI, { 0xc4800000 }
17687
  },
17688
/* subx${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */
17689
  {
17690
    { 0, 0, 0, 0 },
17691
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
17692
    & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_SI, { 0x84a00000 }
17693
  },
17694
/* subx${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
17695
  {
17696
    { 0, 0, 0, 0 },
17697
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
17698
    & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_SI, { 0x84800000 }
17699
  },
17700
/* subx${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */
17701
  {
17702
    { 0, 0, 0, 0 },
17703
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
17704
    & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_SI, { 0xc2c000 }
17705
  },
17706
/* subx${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */
17707
  {
17708
    { 0, 0, 0, 0 },
17709
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
17710
    & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_SI, { 0x82e000 }
17711
  },
17712
/* subx${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
17713
  {
17714
    { 0, 0, 0, 0 },
17715
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
17716
    & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_SI, { 0x82c000 }
17717
  },
17718
/* subx${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */
17719
  {
17720
    { 0, 0, 0, 0 },
17721
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
17722
    & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_SI, { 0xc4c00000 }
17723
  },
17724
/* subx${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */
17725
  {
17726
    { 0, 0, 0, 0 },
17727
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
17728
    & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_SI, { 0x84e00000 }
17729
  },
17730
/* subx${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
17731
  {
17732
    { 0, 0, 0, 0 },
17733
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
17734
    & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_SI, { 0x84c00000 }
17735
  },
17736
/* subx${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */
17737
  {
17738
    { 0, 0, 0, 0 },
17739
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), 0 } },
17740
    & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_SI, { 0xc6c00000 }
17741
  },
17742
/* subx${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */
17743
  {
17744
    { 0, 0, 0, 0 },
17745
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), 0 } },
17746
    & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_SI, { 0x86e00000 }
17747
  },
17748
/* subx${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
17749
  {
17750
    { 0, 0, 0, 0 },
17751
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } },
17752
    & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_SI, { 0x86c00000 }
17753
  },
17754
/* subx${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */
17755
  {
17756
    { 0, 0, 0, 0 },
17757
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U24), 0 } },
17758
    & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_SI, { 0xc6800000 }
17759
  },
17760
/* subx${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */
17761
  {
17762
    { 0, 0, 0, 0 },
17763
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U24), 0 } },
17764
    & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_SI, { 0x86a00000 }
17765
  },
17766
/* subx${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
17767
  {
17768
    { 0, 0, 0, 0 },
17769
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } },
17770
    & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_SI, { 0x86800000 }
17771
  },
17772
/* subx${G} #${Imm-16-QI},$Dst32RnUnprefixedSI */
17773
  {
17774
    { 0, 0, 0, 0 },
17775
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
17776
    & ifmt_subx32_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_SI, { 0x981100 }
17777
  },
17778
/* subx${G} #${Imm-16-QI},$Dst32AnUnprefixedSI */
17779
  {
17780
    { 0, 0, 0, 0 },
17781
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
17782
    & ifmt_subx32_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_SI, { 0x909100 }
17783
  },
17784
/* subx${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */
17785
  {
17786
    { 0, 0, 0, 0 },
17787
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17788
    & ifmt_subx32_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_SI, { 0x901100 }
17789
  },
17790
/* subx${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
17791
  {
17792
    { 0, 0, 0, 0 },
17793
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17794
    & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_SI, { 0x92110000 }
17795
  },
17796
/* subx${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
17797
  {
17798
    { 0, 0, 0, 0 },
17799
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
17800
    & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_SI, { 0x92910000 }
17801
  },
17802
/* subx${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
17803
  {
17804
    { 0, 0, 0, 0 },
17805
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
17806
    & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_SI, { 0x92d10000 }
17807
  },
17808
/* subx${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
17809
  {
17810
    { 0, 0, 0, 0 },
17811
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17812
    & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_SI, { 0x94110000 }
17813
  },
17814
/* subx${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
17815
  {
17816
    { 0, 0, 0, 0 },
17817
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
17818
    & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_SI, { 0x94910000 }
17819
  },
17820
/* subx${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */
17821
  {
17822
    { 0, 0, 0, 0 },
17823
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
17824
    & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_SI, { 0x94d10000 }
17825
  },
17826
/* subx${G} #${Imm-32-QI},${Dsp-16-u16} */
17827
  {
17828
    { 0, 0, 0, 0 },
17829
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } },
17830
    & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_SI, { 0x96d10000 }
17831
  },
17832
/* subx${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
17833
  {
17834
    { 0, 0, 0, 0 },
17835
    { { MNEM, OP (G), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17836
    & ifmt_subx32_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_SI, { 0x96110000 }
17837
  },
17838
/* subx${G} #${Imm-40-QI},${Dsp-16-u24} */
17839
  {
17840
    { 0, 0, 0, 0 },
17841
    { { MNEM, OP (G), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), 0 } },
17842
    & ifmt_subx32_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_SI, { 0x96910000 }
17843
  },
17844
/* stzx.w #${Imm-16-HI},#${Imm-32-HI},$Dst32RnUnprefixedHI */
17845
  {
17846
    { 0, 0, 0, 0 },
17847
    { { MNEM, ' ', '#', OP (IMM_16_HI), ',', '#', OP (IMM_32_HI), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
17848
    & ifmt_stzx32_w_Imm_16_HI_Imm_32_HI_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0x993f0000 }
17849
  },
17850
/* stzx.w #${Imm-16-HI},#${Imm-32-HI},$Dst32AnUnprefixedHI */
17851
  {
17852
    { 0, 0, 0, 0 },
17853
    { { MNEM, ' ', '#', OP (IMM_16_HI), ',', '#', OP (IMM_32_HI), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
17854
    & ifmt_stzx32_w_Imm_16_HI_Imm_32_HI_basic_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0x91bf0000 }
17855
  },
17856
/* stzx.w #${Imm-16-HI},#${Imm-32-HI},[$Dst32AnUnprefixed] */
17857
  {
17858
    { 0, 0, 0, 0 },
17859
    { { MNEM, ' ', '#', OP (IMM_16_HI), ',', '#', OP (IMM_32_HI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17860
    & ifmt_stzx32_w_Imm_16_HI_Imm_32_HI_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0x913f0000 }
17861
  },
17862
/* stzx.w #${Imm-24-HI},#${Imm-40-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
17863
  {
17864
    { 0, 0, 0, 0 },
17865
    { { MNEM, ' ', '#', OP (IMM_24_HI), ',', '#', OP (IMM_40_HI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17866
    & ifmt_stzx32_w_Imm_24_HI_Imm_40_HI_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0x933f0000 }
17867
  },
17868
/* stzx.w #${Imm-24-HI},#${Imm-40-HI},${Dsp-16-u8}[sb] */
17869
  {
17870
    { 0, 0, 0, 0 },
17871
    { { MNEM, ' ', '#', OP (IMM_24_HI), ',', '#', OP (IMM_40_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
17872
    & ifmt_stzx32_w_Imm_24_HI_Imm_40_HI_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0x93bf0000 }
17873
  },
17874
/* stzx.w #${Imm-24-HI},#${Imm-40-HI},${Dsp-16-s8}[fb] */
17875
  {
17876
    { 0, 0, 0, 0 },
17877
    { { MNEM, ' ', '#', OP (IMM_24_HI), ',', '#', OP (IMM_40_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
17878
    & ifmt_stzx32_w_Imm_24_HI_Imm_40_HI_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0x93ff0000 }
17879
  },
17880
/* stzx.w #${Imm-32-HI},#${Imm-48-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
17881
  {
17882
    { 0, 0, 0, 0 },
17883
    { { MNEM, ' ', '#', OP (IMM_32_HI), ',', '#', OP (IMM_48_HI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17884
    & ifmt_stzx32_w_Imm_32_HI_Imm_48_HI_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0x953f0000 }
17885
  },
17886
/* stzx.w #${Imm-32-HI},#${Imm-48-HI},${Dsp-16-u16}[sb] */
17887
  {
17888
    { 0, 0, 0, 0 },
17889
    { { MNEM, ' ', '#', OP (IMM_32_HI), ',', '#', OP (IMM_48_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
17890
    & ifmt_stzx32_w_Imm_32_HI_Imm_48_HI_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0x95bf0000 }
17891
  },
17892
/* stzx.w #${Imm-32-HI},#${Imm-48-HI},${Dsp-16-s16}[fb] */
17893
  {
17894
    { 0, 0, 0, 0 },
17895
    { { MNEM, ' ', '#', OP (IMM_32_HI), ',', '#', OP (IMM_48_HI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
17896
    & ifmt_stzx32_w_Imm_32_HI_Imm_48_HI_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0x95ff0000 }
17897
  },
17898
/* stzx.w #${Imm-32-HI},#${Imm-48-HI},${Dsp-16-u16} */
17899
  {
17900
    { 0, 0, 0, 0 },
17901
    { { MNEM, ' ', '#', OP (IMM_32_HI), ',', '#', OP (IMM_48_HI), ',', OP (DSP_16_U16), 0 } },
17902
    & ifmt_stzx32_w_Imm_32_HI_Imm_48_HI_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0x97ff0000 }
17903
  },
17904
/* stzx.w #${Imm-40-HI},#${Imm-56-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
17905
  {
17906
    { 0, 0, 0, 0 },
17907
    { { MNEM, ' ', '#', OP (IMM_40_HI), ',', '#', OP (IMM_56_HI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17908
    & ifmt_stzx32_w_Imm_40_HI_Imm_56_HI_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0x973f0000 }
17909
  },
17910
/* stzx.w #${Imm-40-HI},#${Imm-56-HI},${Dsp-16-u24} */
17911
  {
17912
    { 0, 0, 0, 0 },
17913
    { { MNEM, ' ', '#', OP (IMM_40_HI), ',', '#', OP (IMM_56_HI), ',', OP (DSP_16_U24), 0 } },
17914
    & ifmt_stzx32_w_Imm_40_HI_Imm_56_HI_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0x97bf0000 }
17915
  },
17916
/* stzx.b #${Imm-16-QI},#${Imm-24-QI},$Dst32RnUnprefixedQI */
17917
  {
17918
    { 0, 0, 0, 0 },
17919
    { { MNEM, ' ', '#', OP (IMM_16_QI), ',', '#', OP (IMM_24_QI), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
17920
    & ifmt_stzx32_b_Imm_16_QI_Imm_24_QI_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0x983f0000 }
17921
  },
17922
/* stzx.b #${Imm-16-QI},#${Imm-24-QI},$Dst32AnUnprefixedQI */
17923
  {
17924
    { 0, 0, 0, 0 },
17925
    { { MNEM, ' ', '#', OP (IMM_16_QI), ',', '#', OP (IMM_24_QI), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
17926
    & ifmt_stzx32_b_Imm_16_QI_Imm_24_QI_basic_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0x90bf0000 }
17927
  },
17928
/* stzx.b #${Imm-16-QI},#${Imm-24-QI},[$Dst32AnUnprefixed] */
17929
  {
17930
    { 0, 0, 0, 0 },
17931
    { { MNEM, ' ', '#', OP (IMM_16_QI), ',', '#', OP (IMM_24_QI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17932
    & ifmt_stzx32_b_Imm_16_QI_Imm_24_QI_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0x903f0000 }
17933
  },
17934
/* stzx.b #${Imm-24-QI},#${Imm-32-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
17935
  {
17936
    { 0, 0, 0, 0 },
17937
    { { MNEM, ' ', '#', OP (IMM_24_QI), ',', '#', OP (IMM_32_QI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17938
    & ifmt_stzx32_b_Imm_24_QI_Imm_32_QI_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0x923f0000 }
17939
  },
17940
/* stzx.b #${Imm-24-QI},#${Imm-32-QI},${Dsp-16-u8}[sb] */
17941
  {
17942
    { 0, 0, 0, 0 },
17943
    { { MNEM, ' ', '#', OP (IMM_24_QI), ',', '#', OP (IMM_32_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
17944
    & ifmt_stzx32_b_Imm_24_QI_Imm_32_QI_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0x92bf0000 }
17945
  },
17946
/* stzx.b #${Imm-24-QI},#${Imm-32-QI},${Dsp-16-s8}[fb] */
17947
  {
17948
    { 0, 0, 0, 0 },
17949
    { { MNEM, ' ', '#', OP (IMM_24_QI), ',', '#', OP (IMM_32_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
17950
    & ifmt_stzx32_b_Imm_24_QI_Imm_32_QI_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0x92ff0000 }
17951
  },
17952
/* stzx.b #${Imm-32-QI},#${Imm-40-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
17953
  {
17954
    { 0, 0, 0, 0 },
17955
    { { MNEM, ' ', '#', OP (IMM_32_QI), ',', '#', OP (IMM_40_QI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17956
    & ifmt_stzx32_b_Imm_32_QI_Imm_40_QI_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0x943f0000 }
17957
  },
17958
/* stzx.b #${Imm-32-QI},#${Imm-40-QI},${Dsp-16-u16}[sb] */
17959
  {
17960
    { 0, 0, 0, 0 },
17961
    { { MNEM, ' ', '#', OP (IMM_32_QI), ',', '#', OP (IMM_40_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
17962
    & ifmt_stzx32_b_Imm_32_QI_Imm_40_QI_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0x94bf0000 }
17963
  },
17964
/* stzx.b #${Imm-32-QI},#${Imm-40-QI},${Dsp-16-s16}[fb] */
17965
  {
17966
    { 0, 0, 0, 0 },
17967
    { { MNEM, ' ', '#', OP (IMM_32_QI), ',', '#', OP (IMM_40_QI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
17968
    & ifmt_stzx32_b_Imm_32_QI_Imm_40_QI_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0x94ff0000 }
17969
  },
17970
/* stzx.b #${Imm-32-QI},#${Imm-40-QI},${Dsp-16-u16} */
17971
  {
17972
    { 0, 0, 0, 0 },
17973
    { { MNEM, ' ', '#', OP (IMM_32_QI), ',', '#', OP (IMM_40_QI), ',', OP (DSP_16_U16), 0 } },
17974
    & ifmt_stzx32_b_Imm_32_QI_Imm_40_QI_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0x96ff0000 }
17975
  },
17976
/* stzx.b #${Imm-40-QI},#${Imm-48-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
17977
  {
17978
    { 0, 0, 0, 0 },
17979
    { { MNEM, ' ', '#', OP (IMM_40_QI), ',', '#', OP (IMM_48_QI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
17980
    & ifmt_stzx32_b_Imm_40_QI_Imm_48_QI_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0x963f0000 }
17981
  },
17982
/* stzx.b #${Imm-40-QI},#${Imm-48-QI},${Dsp-16-u24} */
17983
  {
17984
    { 0, 0, 0, 0 },
17985
    { { MNEM, ' ', '#', OP (IMM_40_QI), ',', '#', OP (IMM_48_QI), ',', OP (DSP_16_U24), 0 } },
17986
    & ifmt_stzx32_b_Imm_40_QI_Imm_48_QI_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0x96bf0000 }
17987
  },
17988
/* stz.w${X} #${Imm-16-HI},$Dst32RnUnprefixedHI */
17989
  {
17990
    { 0, 0, 0, 0 },
17991
    { { MNEM, OP (X), ' ', '#', OP (IMM_16_HI), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
17992
    & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0x990f0000 }
17993
  },
17994
/* stz.w${X} #${Imm-16-HI},$Dst32AnUnprefixedHI */
17995
  {
17996
    { 0, 0, 0, 0 },
17997
    { { MNEM, OP (X), ' ', '#', OP (IMM_16_HI), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
17998
    & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0x918f0000 }
17999
  },
18000
/* stz.w${X} #${Imm-16-HI},[$Dst32AnUnprefixed] */
18001
  {
18002
    { 0, 0, 0, 0 },
18003
    { { MNEM, OP (X), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18004
    & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0x910f0000 }
18005
  },
18006
/* stz.w${X} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
18007
  {
18008
    { 0, 0, 0, 0 },
18009
    { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18010
    & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0x930f0000 }
18011
  },
18012
/* stz.w${X} #${Imm-24-HI},${Dsp-16-u8}[sb] */
18013
  {
18014
    { 0, 0, 0, 0 },
18015
    { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
18016
    & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0x938f0000 }
18017
  },
18018
/* stz.w${X} #${Imm-24-HI},${Dsp-16-s8}[fb] */
18019
  {
18020
    { 0, 0, 0, 0 },
18021
    { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
18022
    & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0x93cf0000 }
18023
  },
18024
/* stz.w${X} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
18025
  {
18026
    { 0, 0, 0, 0 },
18027
    { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18028
    & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0x950f0000 }
18029
  },
18030
/* stz.w${X} #${Imm-32-HI},${Dsp-16-u16}[sb] */
18031
  {
18032
    { 0, 0, 0, 0 },
18033
    { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
18034
    & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0x958f0000 }
18035
  },
18036
/* stz.w${X} #${Imm-32-HI},${Dsp-16-s16}[fb] */
18037
  {
18038
    { 0, 0, 0, 0 },
18039
    { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
18040
    & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0x95cf0000 }
18041
  },
18042
/* stz.w${X} #${Imm-32-HI},${Dsp-16-u16} */
18043
  {
18044
    { 0, 0, 0, 0 },
18045
    { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } },
18046
    & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0x97cf0000 }
18047
  },
18048
/* stz.w${X} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
18049
  {
18050
    { 0, 0, 0, 0 },
18051
    { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18052
    & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0x970f0000 }
18053
  },
18054
/* stz.w${X} #${Imm-40-HI},${Dsp-16-u24} */
18055
  {
18056
    { 0, 0, 0, 0 },
18057
    { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), 0 } },
18058
    & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0x978f0000 }
18059
  },
18060
/* stz.b${X} #${Imm-16-QI},$Dst32RnUnprefixedQI */
18061
  {
18062
    { 0, 0, 0, 0 },
18063
    { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
18064
    & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0x980f00 }
18065
  },
18066
/* stz.b${X} #${Imm-16-QI},$Dst32AnUnprefixedQI */
18067
  {
18068
    { 0, 0, 0, 0 },
18069
    { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
18070
    & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0x908f00 }
18071
  },
18072
/* stz.b${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */
18073
  {
18074
    { 0, 0, 0, 0 },
18075
    { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18076
    & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0x900f00 }
18077
  },
18078
/* stz.b${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
18079
  {
18080
    { 0, 0, 0, 0 },
18081
    { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18082
    & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0x920f0000 }
18083
  },
18084
/* stz.b${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
18085
  {
18086
    { 0, 0, 0, 0 },
18087
    { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
18088
    & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0x928f0000 }
18089
  },
18090
/* stz.b${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
18091
  {
18092
    { 0, 0, 0, 0 },
18093
    { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
18094
    & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0x92cf0000 }
18095
  },
18096
/* stz.b${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
18097
  {
18098
    { 0, 0, 0, 0 },
18099
    { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18100
    & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0x940f0000 }
18101
  },
18102
/* stz.b${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
18103
  {
18104
    { 0, 0, 0, 0 },
18105
    { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
18106
    & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0x948f0000 }
18107
  },
18108
/* stz.b${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */
18109
  {
18110
    { 0, 0, 0, 0 },
18111
    { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
18112
    & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0x94cf0000 }
18113
  },
18114
/* stz.b${X} #${Imm-32-QI},${Dsp-16-u16} */
18115
  {
18116
    { 0, 0, 0, 0 },
18117
    { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } },
18118
    & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0x96cf0000 }
18119
  },
18120
/* stz.b${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
18121
  {
18122
    { 0, 0, 0, 0 },
18123
    { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18124
    & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0x960f0000 }
18125
  },
18126
/* stz.b${X} #${Imm-40-QI},${Dsp-16-u24} */
18127
  {
18128
    { 0, 0, 0, 0 },
18129
    { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), 0 } },
18130
    & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0x968f0000 }
18131
  },
18132
/* stz${S} #${Imm-8-QI},r0l */
18133
  {
18134
    { 0, 0, 0, 0 },
18135
    { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'l', 0 } },
18136
    & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_R0l_direct_QI, { 0xcc00 }
18137
  },
18138
/* stz${S} #${Imm-8-QI},r0h */
18139
  {
18140
    { 0, 0, 0, 0 },
18141
    { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'h', 0 } },
18142
    & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_R0h_direct_QI, { 0xcb00 }
18143
  },
18144
/* stz${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */
18145
  {
18146
    { 0, 0, 0, 0 },
18147
    { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
18148
    & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_8_SB_relative_QI, { 0xcd0000 }
18149
  },
18150
/* stz${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */
18151
  {
18152
    { 0, 0, 0, 0 },
18153
    { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
18154
    & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_8_FB_relative_QI, { 0xce0000 }
18155
  },
18156
/* stz${S} #${Imm-8-QI},${Dsp-16-u16} */
18157
  {
18158
    { 0, 0, 0, 0 },
18159
    { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_U16), 0 } },
18160
    & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_16_absolute_QI, { 0xcf000000 }
18161
  },
18162
/* stnz.w${X} #${Imm-16-HI},$Dst32RnUnprefixedHI */
18163
  {
18164
    { 0, 0, 0, 0 },
18165
    { { MNEM, OP (X), ' ', '#', OP (IMM_16_HI), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
18166
    & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0x991f0000 }
18167
  },
18168
/* stnz.w${X} #${Imm-16-HI},$Dst32AnUnprefixedHI */
18169
  {
18170
    { 0, 0, 0, 0 },
18171
    { { MNEM, OP (X), ' ', '#', OP (IMM_16_HI), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
18172
    & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0x919f0000 }
18173
  },
18174
/* stnz.w${X} #${Imm-16-HI},[$Dst32AnUnprefixed] */
18175
  {
18176
    { 0, 0, 0, 0 },
18177
    { { MNEM, OP (X), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18178
    & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0x911f0000 }
18179
  },
18180
/* stnz.w${X} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
18181
  {
18182
    { 0, 0, 0, 0 },
18183
    { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18184
    & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0x931f0000 }
18185
  },
18186
/* stnz.w${X} #${Imm-24-HI},${Dsp-16-u8}[sb] */
18187
  {
18188
    { 0, 0, 0, 0 },
18189
    { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
18190
    & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0x939f0000 }
18191
  },
18192
/* stnz.w${X} #${Imm-24-HI},${Dsp-16-s8}[fb] */
18193
  {
18194
    { 0, 0, 0, 0 },
18195
    { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
18196
    & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0x93df0000 }
18197
  },
18198
/* stnz.w${X} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
18199
  {
18200
    { 0, 0, 0, 0 },
18201
    { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18202
    & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0x951f0000 }
18203
  },
18204
/* stnz.w${X} #${Imm-32-HI},${Dsp-16-u16}[sb] */
18205
  {
18206
    { 0, 0, 0, 0 },
18207
    { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
18208
    & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0x959f0000 }
18209
  },
18210
/* stnz.w${X} #${Imm-32-HI},${Dsp-16-s16}[fb] */
18211
  {
18212
    { 0, 0, 0, 0 },
18213
    { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
18214
    & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0x95df0000 }
18215
  },
18216
/* stnz.w${X} #${Imm-32-HI},${Dsp-16-u16} */
18217
  {
18218
    { 0, 0, 0, 0 },
18219
    { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } },
18220
    & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0x97df0000 }
18221
  },
18222
/* stnz.w${X} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
18223
  {
18224
    { 0, 0, 0, 0 },
18225
    { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18226
    & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0x971f0000 }
18227
  },
18228
/* stnz.w${X} #${Imm-40-HI},${Dsp-16-u24} */
18229
  {
18230
    { 0, 0, 0, 0 },
18231
    { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), 0 } },
18232
    & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0x979f0000 }
18233
  },
18234
/* stnz.b${X} #${Imm-16-QI},$Dst32RnUnprefixedQI */
18235
  {
18236
    { 0, 0, 0, 0 },
18237
    { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
18238
    & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0x981f00 }
18239
  },
18240
/* stnz.b${X} #${Imm-16-QI},$Dst32AnUnprefixedQI */
18241
  {
18242
    { 0, 0, 0, 0 },
18243
    { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
18244
    & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0x909f00 }
18245
  },
18246
/* stnz.b${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */
18247
  {
18248
    { 0, 0, 0, 0 },
18249
    { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18250
    & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0x901f00 }
18251
  },
18252
/* stnz.b${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
18253
  {
18254
    { 0, 0, 0, 0 },
18255
    { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18256
    & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0x921f0000 }
18257
  },
18258
/* stnz.b${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
18259
  {
18260
    { 0, 0, 0, 0 },
18261
    { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
18262
    & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0x929f0000 }
18263
  },
18264
/* stnz.b${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
18265
  {
18266
    { 0, 0, 0, 0 },
18267
    { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
18268
    & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0x92df0000 }
18269
  },
18270
/* stnz.b${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
18271
  {
18272
    { 0, 0, 0, 0 },
18273
    { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18274
    & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0x941f0000 }
18275
  },
18276
/* stnz.b${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
18277
  {
18278
    { 0, 0, 0, 0 },
18279
    { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
18280
    & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0x949f0000 }
18281
  },
18282
/* stnz.b${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */
18283
  {
18284
    { 0, 0, 0, 0 },
18285
    { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
18286
    & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0x94df0000 }
18287
  },
18288
/* stnz.b${X} #${Imm-32-QI},${Dsp-16-u16} */
18289
  {
18290
    { 0, 0, 0, 0 },
18291
    { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } },
18292
    & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0x96df0000 }
18293
  },
18294
/* stnz.b${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
18295
  {
18296
    { 0, 0, 0, 0 },
18297
    { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18298
    & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0x961f0000 }
18299
  },
18300
/* stnz.b${X} #${Imm-40-QI},${Dsp-16-u24} */
18301
  {
18302
    { 0, 0, 0, 0 },
18303
    { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), 0 } },
18304
    & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0x969f0000 }
18305
  },
18306
/* stnz${S} #${Imm-8-QI},r0l */
18307
  {
18308
    { 0, 0, 0, 0 },
18309
    { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'l', 0 } },
18310
    & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_R0l_direct_QI, { 0xd400 }
18311
  },
18312
/* stnz${S} #${Imm-8-QI},r0h */
18313
  {
18314
    { 0, 0, 0, 0 },
18315
    { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'h', 0 } },
18316
    & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_R0h_direct_QI, { 0xd300 }
18317
  },
18318
/* stnz${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */
18319
  {
18320
    { 0, 0, 0, 0 },
18321
    { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
18322
    & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_8_SB_relative_QI, { 0xd50000 }
18323
  },
18324
/* stnz${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */
18325
  {
18326
    { 0, 0, 0, 0 },
18327
    { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
18328
    & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_8_FB_relative_QI, { 0xd60000 }
18329
  },
18330
/* stnz${S} #${Imm-8-QI},${Dsp-16-u16} */
18331
  {
18332
    { 0, 0, 0, 0 },
18333
    { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_U16), 0 } },
18334
    & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_16_absolute_QI, { 0xd7000000 }
18335
  },
18336
/* shlnc.l${X} #${Imm-16-QI},$Dst32RnUnprefixedSI */
18337
  {
18338
    { 0, 0, 0, 0 },
18339
    { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
18340
    & ifmt_subx32_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_SI, { 0x882100 }
18341
  },
18342
/* shlnc.l${X} #${Imm-16-QI},$Dst32AnUnprefixedSI */
18343
  {
18344
    { 0, 0, 0, 0 },
18345
    { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
18346
    & ifmt_subx32_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_SI, { 0x80a100 }
18347
  },
18348
/* shlnc.l${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */
18349
  {
18350
    { 0, 0, 0, 0 },
18351
    { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18352
    & ifmt_subx32_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_SI, { 0x802100 }
18353
  },
18354
/* shlnc.l${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
18355
  {
18356
    { 0, 0, 0, 0 },
18357
    { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18358
    & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_SI, { 0x82210000 }
18359
  },
18360
/* shlnc.l${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
18361
  {
18362
    { 0, 0, 0, 0 },
18363
    { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
18364
    & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_SI, { 0x82a10000 }
18365
  },
18366
/* shlnc.l${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
18367
  {
18368
    { 0, 0, 0, 0 },
18369
    { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
18370
    & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_SI, { 0x82e10000 }
18371
  },
18372
/* shlnc.l${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
18373
  {
18374
    { 0, 0, 0, 0 },
18375
    { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18376
    & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_SI, { 0x84210000 }
18377
  },
18378
/* shlnc.l${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
18379
  {
18380
    { 0, 0, 0, 0 },
18381
    { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
18382
    & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_SI, { 0x84a10000 }
18383
  },
18384
/* shlnc.l${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */
18385
  {
18386
    { 0, 0, 0, 0 },
18387
    { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
18388
    & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_SI, { 0x84e10000 }
18389
  },
18390
/* shlnc.l${X} #${Imm-32-QI},${Dsp-16-u16} */
18391
  {
18392
    { 0, 0, 0, 0 },
18393
    { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } },
18394
    & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_SI, { 0x86e10000 }
18395
  },
18396
/* shlnc.l${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
18397
  {
18398
    { 0, 0, 0, 0 },
18399
    { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18400
    & ifmt_subx32_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_SI, { 0x86210000 }
18401
  },
18402
/* shlnc.l${X} #${Imm-40-QI},${Dsp-16-u24} */
18403
  {
18404
    { 0, 0, 0, 0 },
18405
    { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), 0 } },
18406
    & ifmt_subx32_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_SI, { 0x86a10000 }
18407
  },
18408
/* shl.l r1h,$Dst32RnUnprefixedSI */
18409
  {
18410
    { 0, 0, 0, 0 },
18411
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
18412
    & ifmt_shl32_l_dst_dst32_Rn_direct_Unprefixed_SI, { 0xc801 }
18413
  },
18414
/* shl.l r1h,$Dst32AnUnprefixedSI */
18415
  {
18416
    { 0, 0, 0, 0 },
18417
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
18418
    & ifmt_exts32_w_16_ExtUnprefixed_dst32_An_direct_Unprefixed_SI, { 0xc081 }
18419
  },
18420
/* shl.l r1h,[$Dst32AnUnprefixed] */
18421
  {
18422
    { 0, 0, 0, 0 },
18423
    { { MNEM, ' ', 'r', '1', 'h', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18424
    & ifmt_shl32_l_dst_dst32_An_indirect_Unprefixed_SI, { 0xc001 }
18425
  },
18426
/* shl.l r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */
18427
  {
18428
    { 0, 0, 0, 0 },
18429
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18430
    & ifmt_shl32_l_dst_dst32_16_8_An_relative_Unprefixed_SI, { 0xc20100 }
18431
  },
18432
/* shl.l r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */
18433
  {
18434
    { 0, 0, 0, 0 },
18435
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18436
    & ifmt_shl32_l_dst_dst32_16_16_An_relative_Unprefixed_SI, { 0xc4010000 }
18437
  },
18438
/* shl.l r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */
18439
  {
18440
    { 0, 0, 0, 0 },
18441
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18442
    & ifmt_shl32_l_dst_dst32_16_24_An_relative_Unprefixed_SI, { 0xc6010000 }
18443
  },
18444
/* shl.l r1h,${Dsp-16-u8}[sb] */
18445
  {
18446
    { 0, 0, 0, 0 },
18447
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
18448
    & ifmt_shl32_l_dst_dst32_16_8_SB_relative_Unprefixed_SI, { 0xc28100 }
18449
  },
18450
/* shl.l r1h,${Dsp-16-u16}[sb] */
18451
  {
18452
    { 0, 0, 0, 0 },
18453
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
18454
    & ifmt_shl32_l_dst_dst32_16_16_SB_relative_Unprefixed_SI, { 0xc4810000 }
18455
  },
18456
/* shl.l r1h,${Dsp-16-s8}[fb] */
18457
  {
18458
    { 0, 0, 0, 0 },
18459
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
18460
    & ifmt_shl32_l_dst_dst32_16_8_FB_relative_Unprefixed_SI, { 0xc2c100 }
18461
  },
18462
/* shl.l r1h,${Dsp-16-s16}[fb] */
18463
  {
18464
    { 0, 0, 0, 0 },
18465
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
18466
    & ifmt_shl32_l_dst_dst32_16_16_FB_relative_Unprefixed_SI, { 0xc4c10000 }
18467
  },
18468
/* shl.l r1h,${Dsp-16-u16} */
18469
  {
18470
    { 0, 0, 0, 0 },
18471
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), 0 } },
18472
    & ifmt_shl32_l_dst_dst32_16_16_absolute_Unprefixed_SI, { 0xc6c10000 }
18473
  },
18474
/* shl.l r1h,${Dsp-16-u24} */
18475
  {
18476
    { 0, 0, 0, 0 },
18477
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U24), 0 } },
18478
    & ifmt_shl32_l_dst_dst32_16_24_absolute_Unprefixed_SI, { 0xc6810000 }
18479
  },
18480
/* shl.l${X} #${Imm-16-QI},$Dst32RnUnprefixedSI */
18481
  {
18482
    { 0, 0, 0, 0 },
18483
    { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
18484
    & ifmt_subx32_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_SI, { 0x982100 }
18485
  },
18486
/* shl.l${X} #${Imm-16-QI},$Dst32AnUnprefixedSI */
18487
  {
18488
    { 0, 0, 0, 0 },
18489
    { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
18490
    & ifmt_subx32_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_SI, { 0x90a100 }
18491
  },
18492
/* shl.l${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */
18493
  {
18494
    { 0, 0, 0, 0 },
18495
    { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18496
    & ifmt_subx32_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_SI, { 0x902100 }
18497
  },
18498
/* shl.l${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
18499
  {
18500
    { 0, 0, 0, 0 },
18501
    { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18502
    & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_SI, { 0x92210000 }
18503
  },
18504
/* shl.l${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
18505
  {
18506
    { 0, 0, 0, 0 },
18507
    { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
18508
    & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_SI, { 0x92a10000 }
18509
  },
18510
/* shl.l${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
18511
  {
18512
    { 0, 0, 0, 0 },
18513
    { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
18514
    & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_SI, { 0x92e10000 }
18515
  },
18516
/* shl.l${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
18517
  {
18518
    { 0, 0, 0, 0 },
18519
    { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18520
    & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_SI, { 0x94210000 }
18521
  },
18522
/* shl.l${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
18523
  {
18524
    { 0, 0, 0, 0 },
18525
    { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
18526
    & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_SI, { 0x94a10000 }
18527
  },
18528
/* shl.l${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */
18529
  {
18530
    { 0, 0, 0, 0 },
18531
    { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
18532
    & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_SI, { 0x94e10000 }
18533
  },
18534
/* shl.l${X} #${Imm-32-QI},${Dsp-16-u16} */
18535
  {
18536
    { 0, 0, 0, 0 },
18537
    { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } },
18538
    & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_SI, { 0x96e10000 }
18539
  },
18540
/* shl.l${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
18541
  {
18542
    { 0, 0, 0, 0 },
18543
    { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18544
    & ifmt_subx32_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_SI, { 0x96210000 }
18545
  },
18546
/* shl.l${X} #${Imm-40-QI},${Dsp-16-u24} */
18547
  {
18548
    { 0, 0, 0, 0 },
18549
    { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), 0 } },
18550
    & ifmt_subx32_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_SI, { 0x96a10000 }
18551
  },
18552
/* shl.w r1h,$Dst32RnUnprefixedHI */
18553
  {
18554
    { 0, 0, 0, 0 },
18555
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
18556
    & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xa93e }
18557
  },
18558
/* shl.w r1h,$Dst32AnUnprefixedHI */
18559
  {
18560
    { 0, 0, 0, 0 },
18561
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
18562
    & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xa1be }
18563
  },
18564
/* shl.w r1h,[$Dst32AnUnprefixed] */
18565
  {
18566
    { 0, 0, 0, 0 },
18567
    { { MNEM, ' ', 'r', '1', 'h', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18568
    & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xa13e }
18569
  },
18570
/* shl.w r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */
18571
  {
18572
    { 0, 0, 0, 0 },
18573
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18574
    & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xa33e00 }
18575
  },
18576
/* shl.w r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */
18577
  {
18578
    { 0, 0, 0, 0 },
18579
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18580
    & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xa53e0000 }
18581
  },
18582
/* shl.w r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */
18583
  {
18584
    { 0, 0, 0, 0 },
18585
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18586
    & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xa73e0000 }
18587
  },
18588
/* shl.w r1h,${Dsp-16-u8}[sb] */
18589
  {
18590
    { 0, 0, 0, 0 },
18591
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
18592
    & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xa3be00 }
18593
  },
18594
/* shl.w r1h,${Dsp-16-u16}[sb] */
18595
  {
18596
    { 0, 0, 0, 0 },
18597
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
18598
    & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xa5be0000 }
18599
  },
18600
/* shl.w r1h,${Dsp-16-s8}[fb] */
18601
  {
18602
    { 0, 0, 0, 0 },
18603
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
18604
    & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xa3fe00 }
18605
  },
18606
/* shl.w r1h,${Dsp-16-s16}[fb] */
18607
  {
18608
    { 0, 0, 0, 0 },
18609
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
18610
    & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xa5fe0000 }
18611
  },
18612
/* shl.w r1h,${Dsp-16-u16} */
18613
  {
18614
    { 0, 0, 0, 0 },
18615
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), 0 } },
18616
    & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xa7fe0000 }
18617
  },
18618
/* shl.w r1h,${Dsp-16-u24} */
18619
  {
18620
    { 0, 0, 0, 0 },
18621
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U24), 0 } },
18622
    & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xa7be0000 }
18623
  },
18624
/* shl.b r1h,$Dst32RnUnprefixedQI */
18625
  {
18626
    { 0, 0, 0, 0 },
18627
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
18628
    & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0xa83e }
18629
  },
18630
/* shl.b r1h,$Dst32AnUnprefixedQI */
18631
  {
18632
    { 0, 0, 0, 0 },
18633
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
18634
    & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0xa0be }
18635
  },
18636
/* shl.b r1h,[$Dst32AnUnprefixed] */
18637
  {
18638
    { 0, 0, 0, 0 },
18639
    { { MNEM, ' ', 'r', '1', 'h', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18640
    & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0xa03e }
18641
  },
18642
/* shl.b r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */
18643
  {
18644
    { 0, 0, 0, 0 },
18645
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18646
    & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0xa23e00 }
18647
  },
18648
/* shl.b r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */
18649
  {
18650
    { 0, 0, 0, 0 },
18651
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18652
    & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0xa43e0000 }
18653
  },
18654
/* shl.b r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */
18655
  {
18656
    { 0, 0, 0, 0 },
18657
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18658
    & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0xa63e0000 }
18659
  },
18660
/* shl.b r1h,${Dsp-16-u8}[sb] */
18661
  {
18662
    { 0, 0, 0, 0 },
18663
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
18664
    & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0xa2be00 }
18665
  },
18666
/* shl.b r1h,${Dsp-16-u16}[sb] */
18667
  {
18668
    { 0, 0, 0, 0 },
18669
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
18670
    & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0xa4be0000 }
18671
  },
18672
/* shl.b r1h,${Dsp-16-s8}[fb] */
18673
  {
18674
    { 0, 0, 0, 0 },
18675
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
18676
    & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0xa2fe00 }
18677
  },
18678
/* shl.b r1h,${Dsp-16-s16}[fb] */
18679
  {
18680
    { 0, 0, 0, 0 },
18681
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
18682
    & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0xa4fe0000 }
18683
  },
18684
/* shl.b r1h,${Dsp-16-u16} */
18685
  {
18686
    { 0, 0, 0, 0 },
18687
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), 0 } },
18688
    & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0xa6fe0000 }
18689
  },
18690
/* shl.b r1h,${Dsp-16-u24} */
18691
  {
18692
    { 0, 0, 0, 0 },
18693
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U24), 0 } },
18694
    & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0xa6be0000 }
18695
  },
18696
/* shl.w r1h,$Dst16RnHI */
18697
  {
18698
    { 0, 0, 0, 0 },
18699
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST16RNHI), 0 } },
18700
    & ifmt_shl16_w_dst_dst16_Rn_direct_HI, { 0x75e0 }
18701
  },
18702
/* shl.w r1h,$Dst16AnHI */
18703
  {
18704
    { 0, 0, 0, 0 },
18705
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST16ANHI), 0 } },
18706
    & ifmt_shl16_w_dst_dst16_An_direct_HI, { 0x75e4 }
18707
  },
18708
/* shl.w r1h,[$Dst16An] */
18709
  {
18710
    { 0, 0, 0, 0 },
18711
    { { MNEM, ' ', 'r', '1', 'h', ',', '[', OP (DST16AN), ']', 0 } },
18712
    & ifmt_shl16_w_dst_dst16_An_indirect_HI, { 0x75e6 }
18713
  },
18714
/* shl.w r1h,${Dsp-16-u8}[$Dst16An] */
18715
  {
18716
    { 0, 0, 0, 0 },
18717
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
18718
    & ifmt_shl16_w_dst_dst16_16_8_An_relative_HI, { 0x75e800 }
18719
  },
18720
/* shl.w r1h,${Dsp-16-u16}[$Dst16An] */
18721
  {
18722
    { 0, 0, 0, 0 },
18723
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
18724
    & ifmt_shl16_w_dst_dst16_16_16_An_relative_HI, { 0x75ec0000 }
18725
  },
18726
/* shl.w r1h,${Dsp-16-u8}[sb] */
18727
  {
18728
    { 0, 0, 0, 0 },
18729
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
18730
    & ifmt_shl16_w_dst_dst16_16_8_SB_relative_HI, { 0x75ea00 }
18731
  },
18732
/* shl.w r1h,${Dsp-16-u16}[sb] */
18733
  {
18734
    { 0, 0, 0, 0 },
18735
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
18736
    & ifmt_shl16_w_dst_dst16_16_16_SB_relative_HI, { 0x75ee0000 }
18737
  },
18738
/* shl.w r1h,${Dsp-16-s8}[fb] */
18739
  {
18740
    { 0, 0, 0, 0 },
18741
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
18742
    & ifmt_shl16_w_dst_dst16_16_8_FB_relative_HI, { 0x75eb00 }
18743
  },
18744
/* shl.w r1h,${Dsp-16-u16} */
18745
  {
18746
    { 0, 0, 0, 0 },
18747
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), 0 } },
18748
    & ifmt_shl16_w_dst_dst16_16_16_absolute_HI, { 0x75ef0000 }
18749
  },
18750
/* shl.b r1h,$Dst16RnQI */
18751
  {
18752
    { 0, 0, 0, 0 },
18753
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST16RNQI), 0 } },
18754
    & ifmt_shl16_b_dst_dst16_Rn_direct_QI, { 0x74e0 }
18755
  },
18756
/* shl.b r1h,$Dst16AnQI */
18757
  {
18758
    { 0, 0, 0, 0 },
18759
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST16ANQI), 0 } },
18760
    & ifmt_shl16_b_dst_dst16_An_direct_QI, { 0x74e4 }
18761
  },
18762
/* shl.b r1h,[$Dst16An] */
18763
  {
18764
    { 0, 0, 0, 0 },
18765
    { { MNEM, ' ', 'r', '1', 'h', ',', '[', OP (DST16AN), ']', 0 } },
18766
    & ifmt_shl16_b_dst_dst16_An_indirect_QI, { 0x74e6 }
18767
  },
18768
/* shl.b r1h,${Dsp-16-u8}[$Dst16An] */
18769
  {
18770
    { 0, 0, 0, 0 },
18771
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
18772
    & ifmt_shl16_b_dst_dst16_16_8_An_relative_QI, { 0x74e800 }
18773
  },
18774
/* shl.b r1h,${Dsp-16-u16}[$Dst16An] */
18775
  {
18776
    { 0, 0, 0, 0 },
18777
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
18778
    & ifmt_shl16_b_dst_dst16_16_16_An_relative_QI, { 0x74ec0000 }
18779
  },
18780
/* shl.b r1h,${Dsp-16-u8}[sb] */
18781
  {
18782
    { 0, 0, 0, 0 },
18783
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
18784
    & ifmt_shl16_b_dst_dst16_16_8_SB_relative_QI, { 0x74ea00 }
18785
  },
18786
/* shl.b r1h,${Dsp-16-u16}[sb] */
18787
  {
18788
    { 0, 0, 0, 0 },
18789
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
18790
    & ifmt_shl16_b_dst_dst16_16_16_SB_relative_QI, { 0x74ee0000 }
18791
  },
18792
/* shl.b r1h,${Dsp-16-s8}[fb] */
18793
  {
18794
    { 0, 0, 0, 0 },
18795
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
18796
    & ifmt_shl16_b_dst_dst16_16_8_FB_relative_QI, { 0x74eb00 }
18797
  },
18798
/* shl.b r1h,${Dsp-16-u16} */
18799
  {
18800
    { 0, 0, 0, 0 },
18801
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), 0 } },
18802
    & ifmt_shl16_b_dst_dst16_16_16_absolute_QI, { 0x74ef0000 }
18803
  },
18804
/* shl.w${Q} #${Imm-sh-12-s4},$Dst32RnUnprefixedHI */
18805
  {
18806
    { 0, 0, 0, 0 },
18807
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
18808
    & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0xe900 }
18809
  },
18810
/* shl.w${Q} #${Imm-sh-12-s4},$Dst32AnUnprefixedHI */
18811
  {
18812
    { 0, 0, 0, 0 },
18813
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
18814
    & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0xe180 }
18815
  },
18816
/* shl.w${Q} #${Imm-sh-12-s4},[$Dst32AnUnprefixed] */
18817
  {
18818
    { 0, 0, 0, 0 },
18819
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18820
    & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0xe100 }
18821
  },
18822
/* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
18823
  {
18824
    { 0, 0, 0, 0 },
18825
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18826
    & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0xe30000 }
18827
  },
18828
/* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
18829
  {
18830
    { 0, 0, 0, 0 },
18831
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18832
    & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0xe5000000 }
18833
  },
18834
/* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
18835
  {
18836
    { 0, 0, 0, 0 },
18837
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18838
    & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0xe7000000 }
18839
  },
18840
/* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[sb] */
18841
  {
18842
    { 0, 0, 0, 0 },
18843
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
18844
    & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0xe38000 }
18845
  },
18846
/* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[sb] */
18847
  {
18848
    { 0, 0, 0, 0 },
18849
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
18850
    & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0xe5800000 }
18851
  },
18852
/* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-s8}[fb] */
18853
  {
18854
    { 0, 0, 0, 0 },
18855
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
18856
    & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0xe3c000 }
18857
  },
18858
/* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-s16}[fb] */
18859
  {
18860
    { 0, 0, 0, 0 },
18861
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
18862
    & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0xe5c00000 }
18863
  },
18864
/* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16} */
18865
  {
18866
    { 0, 0, 0, 0 },
18867
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U16), 0 } },
18868
    & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0xe7c00000 }
18869
  },
18870
/* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-u24} */
18871
  {
18872
    { 0, 0, 0, 0 },
18873
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U24), 0 } },
18874
    & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0xe7800000 }
18875
  },
18876
/* shl.b${Q} #${Imm-sh-12-s4},$Dst32RnUnprefixedQI */
18877
  {
18878
    { 0, 0, 0, 0 },
18879
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
18880
    & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0xe800 }
18881
  },
18882
/* shl.b${Q} #${Imm-sh-12-s4},$Dst32AnUnprefixedQI */
18883
  {
18884
    { 0, 0, 0, 0 },
18885
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
18886
    & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0xe080 }
18887
  },
18888
/* shl.b${Q} #${Imm-sh-12-s4},[$Dst32AnUnprefixed] */
18889
  {
18890
    { 0, 0, 0, 0 },
18891
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18892
    & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0xe000 }
18893
  },
18894
/* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
18895
  {
18896
    { 0, 0, 0, 0 },
18897
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18898
    & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0xe20000 }
18899
  },
18900
/* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
18901
  {
18902
    { 0, 0, 0, 0 },
18903
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18904
    & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0xe4000000 }
18905
  },
18906
/* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
18907
  {
18908
    { 0, 0, 0, 0 },
18909
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
18910
    & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0xe6000000 }
18911
  },
18912
/* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[sb] */
18913
  {
18914
    { 0, 0, 0, 0 },
18915
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
18916
    & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0xe28000 }
18917
  },
18918
/* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[sb] */
18919
  {
18920
    { 0, 0, 0, 0 },
18921
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
18922
    & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0xe4800000 }
18923
  },
18924
/* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-s8}[fb] */
18925
  {
18926
    { 0, 0, 0, 0 },
18927
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
18928
    & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0xe2c000 }
18929
  },
18930
/* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-s16}[fb] */
18931
  {
18932
    { 0, 0, 0, 0 },
18933
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
18934
    & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0xe4c00000 }
18935
  },
18936
/* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16} */
18937
  {
18938
    { 0, 0, 0, 0 },
18939
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U16), 0 } },
18940
    & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0xe6c00000 }
18941
  },
18942
/* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-u24} */
18943
  {
18944
    { 0, 0, 0, 0 },
18945
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U24), 0 } },
18946
    & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0xe6800000 }
18947
  },
18948
/* shl.w${Q} #${Imm-sh-8-s4},$Dst16RnHI */
18949
  {
18950
    { 0, 0, 0, 0 },
18951
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DST16RNHI), 0 } },
18952
    & ifmt_shl16_w_imm4_Q_16_dst16_Rn_direct_HI, { 0xe900 }
18953
  },
18954
/* shl.w${Q} #${Imm-sh-8-s4},$Dst16AnHI */
18955
  {
18956
    { 0, 0, 0, 0 },
18957
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DST16ANHI), 0 } },
18958
    & ifmt_shl16_w_imm4_Q_16_dst16_An_direct_HI, { 0xe904 }
18959
  },
18960
/* shl.w${Q} #${Imm-sh-8-s4},[$Dst16An] */
18961
  {
18962
    { 0, 0, 0, 0 },
18963
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', '[', OP (DST16AN), ']', 0 } },
18964
    & ifmt_shl16_w_imm4_Q_16_dst16_An_indirect_HI, { 0xe906 }
18965
  },
18966
/* shl.w${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[$Dst16An] */
18967
  {
18968
    { 0, 0, 0, 0 },
18969
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
18970
    & ifmt_shl16_w_imm4_Q_16_dst16_16_8_An_relative_HI, { 0xe90800 }
18971
  },
18972
/* shl.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[$Dst16An] */
18973
  {
18974
    { 0, 0, 0, 0 },
18975
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
18976
    & ifmt_shl16_w_imm4_Q_16_dst16_16_16_An_relative_HI, { 0xe90c0000 }
18977
  },
18978
/* shl.w${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[sb] */
18979
  {
18980
    { 0, 0, 0, 0 },
18981
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
18982
    & ifmt_shl16_w_imm4_Q_16_dst16_16_8_SB_relative_HI, { 0xe90a00 }
18983
  },
18984
/* shl.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[sb] */
18985
  {
18986
    { 0, 0, 0, 0 },
18987
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
18988
    & ifmt_shl16_w_imm4_Q_16_dst16_16_16_SB_relative_HI, { 0xe90e0000 }
18989
  },
18990
/* shl.w${Q} #${Imm-sh-8-s4},${Dsp-16-s8}[fb] */
18991
  {
18992
    { 0, 0, 0, 0 },
18993
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
18994
    & ifmt_shl16_w_imm4_Q_16_dst16_16_8_FB_relative_HI, { 0xe90b00 }
18995
  },
18996
/* shl.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16} */
18997
  {
18998
    { 0, 0, 0, 0 },
18999
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U16), 0 } },
19000
    & ifmt_shl16_w_imm4_Q_16_dst16_16_16_absolute_HI, { 0xe90f0000 }
19001
  },
19002
/* shl.b${Q} #${Imm-sh-8-s4},$Dst16RnQI */
19003
  {
19004
    { 0, 0, 0, 0 },
19005
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DST16RNQI), 0 } },
19006
    & ifmt_shl16_b_imm4_Q_16_dst16_Rn_direct_QI, { 0xe800 }
19007
  },
19008
/* shl.b${Q} #${Imm-sh-8-s4},$Dst16AnQI */
19009
  {
19010
    { 0, 0, 0, 0 },
19011
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DST16ANQI), 0 } },
19012
    & ifmt_shl16_b_imm4_Q_16_dst16_An_direct_QI, { 0xe804 }
19013
  },
19014
/* shl.b${Q} #${Imm-sh-8-s4},[$Dst16An] */
19015
  {
19016
    { 0, 0, 0, 0 },
19017
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', '[', OP (DST16AN), ']', 0 } },
19018
    & ifmt_shl16_b_imm4_Q_16_dst16_An_indirect_QI, { 0xe806 }
19019
  },
19020
/* shl.b${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[$Dst16An] */
19021
  {
19022
    { 0, 0, 0, 0 },
19023
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
19024
    & ifmt_shl16_b_imm4_Q_16_dst16_16_8_An_relative_QI, { 0xe80800 }
19025
  },
19026
/* shl.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[$Dst16An] */
19027
  {
19028
    { 0, 0, 0, 0 },
19029
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
19030
    & ifmt_shl16_b_imm4_Q_16_dst16_16_16_An_relative_QI, { 0xe80c0000 }
19031
  },
19032
/* shl.b${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[sb] */
19033
  {
19034
    { 0, 0, 0, 0 },
19035
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
19036
    & ifmt_shl16_b_imm4_Q_16_dst16_16_8_SB_relative_QI, { 0xe80a00 }
19037
  },
19038
/* shl.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[sb] */
19039
  {
19040
    { 0, 0, 0, 0 },
19041
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
19042
    & ifmt_shl16_b_imm4_Q_16_dst16_16_16_SB_relative_QI, { 0xe80e0000 }
19043
  },
19044
/* shl.b${Q} #${Imm-sh-8-s4},${Dsp-16-s8}[fb] */
19045
  {
19046
    { 0, 0, 0, 0 },
19047
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
19048
    & ifmt_shl16_b_imm4_Q_16_dst16_16_8_FB_relative_QI, { 0xe80b00 }
19049
  },
19050
/* shl.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16} */
19051
  {
19052
    { 0, 0, 0, 0 },
19053
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U16), 0 } },
19054
    & ifmt_shl16_b_imm4_Q_16_dst16_16_16_absolute_QI, { 0xe80f0000 }
19055
  },
19056
/* shanc.l${X} #${Imm-16-QI},$Dst32RnUnprefixedSI */
19057
  {
19058
    { 0, 0, 0, 0 },
19059
    { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
19060
    & ifmt_subx32_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_SI, { 0xc82100 }
19061
  },
19062
/* shanc.l${X} #${Imm-16-QI},$Dst32AnUnprefixedSI */
19063
  {
19064
    { 0, 0, 0, 0 },
19065
    { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
19066
    & ifmt_subx32_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_SI, { 0xc0a100 }
19067
  },
19068
/* shanc.l${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */
19069
  {
19070
    { 0, 0, 0, 0 },
19071
    { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
19072
    & ifmt_subx32_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_SI, { 0xc02100 }
19073
  },
19074
/* shanc.l${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
19075
  {
19076
    { 0, 0, 0, 0 },
19077
    { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
19078
    & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_SI, { 0xc2210000 }
19079
  },
19080
/* shanc.l${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
19081
  {
19082
    { 0, 0, 0, 0 },
19083
    { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
19084
    & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_SI, { 0xc2a10000 }
19085
  },
19086
/* shanc.l${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
19087
  {
19088
    { 0, 0, 0, 0 },
19089
    { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
19090
    & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_SI, { 0xc2e10000 }
19091
  },
19092
/* shanc.l${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
19093
  {
19094
    { 0, 0, 0, 0 },
19095
    { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
19096
    & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_SI, { 0xc4210000 }
19097
  },
19098
/* shanc.l${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
19099
  {
19100
    { 0, 0, 0, 0 },
19101
    { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
19102
    & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_SI, { 0xc4a10000 }
19103
  },
19104
/* shanc.l${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */
19105
  {
19106
    { 0, 0, 0, 0 },
19107
    { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
19108
    & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_SI, { 0xc4e10000 }
19109
  },
19110
/* shanc.l${X} #${Imm-32-QI},${Dsp-16-u16} */
19111
  {
19112
    { 0, 0, 0, 0 },
19113
    { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } },
19114
    & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_SI, { 0xc6e10000 }
19115
  },
19116
/* shanc.l${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
19117
  {
19118
    { 0, 0, 0, 0 },
19119
    { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
19120
    & ifmt_subx32_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_SI, { 0xc6210000 }
19121
  },
19122
/* shanc.l${X} #${Imm-40-QI},${Dsp-16-u24} */
19123
  {
19124
    { 0, 0, 0, 0 },
19125
    { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), 0 } },
19126
    & ifmt_subx32_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_SI, { 0xc6a10000 }
19127
  },
19128
/* sha.l r1h,$Dst32RnUnprefixedSI */
19129
  {
19130
    { 0, 0, 0, 0 },
19131
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
19132
    & ifmt_shl32_l_dst_dst32_Rn_direct_Unprefixed_SI, { 0xc811 }
19133
  },
19134
/* sha.l r1h,$Dst32AnUnprefixedSI */
19135
  {
19136
    { 0, 0, 0, 0 },
19137
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
19138
    & ifmt_exts32_w_16_ExtUnprefixed_dst32_An_direct_Unprefixed_SI, { 0xc091 }
19139
  },
19140
/* sha.l r1h,[$Dst32AnUnprefixed] */
19141
  {
19142
    { 0, 0, 0, 0 },
19143
    { { MNEM, ' ', 'r', '1', 'h', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
19144
    & ifmt_shl32_l_dst_dst32_An_indirect_Unprefixed_SI, { 0xc011 }
19145
  },
19146
/* sha.l r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */
19147
  {
19148
    { 0, 0, 0, 0 },
19149
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
19150
    & ifmt_shl32_l_dst_dst32_16_8_An_relative_Unprefixed_SI, { 0xc21100 }
19151
  },
19152
/* sha.l r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */
19153
  {
19154
    { 0, 0, 0, 0 },
19155
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
19156
    & ifmt_shl32_l_dst_dst32_16_16_An_relative_Unprefixed_SI, { 0xc4110000 }
19157
  },
19158
/* sha.l r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */
19159
  {
19160
    { 0, 0, 0, 0 },
19161
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
19162
    & ifmt_shl32_l_dst_dst32_16_24_An_relative_Unprefixed_SI, { 0xc6110000 }
19163
  },
19164
/* sha.l r1h,${Dsp-16-u8}[sb] */
19165
  {
19166
    { 0, 0, 0, 0 },
19167
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
19168
    & ifmt_shl32_l_dst_dst32_16_8_SB_relative_Unprefixed_SI, { 0xc29100 }
19169
  },
19170
/* sha.l r1h,${Dsp-16-u16}[sb] */
19171
  {
19172
    { 0, 0, 0, 0 },
19173
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
19174
    & ifmt_shl32_l_dst_dst32_16_16_SB_relative_Unprefixed_SI, { 0xc4910000 }
19175
  },
19176
/* sha.l r1h,${Dsp-16-s8}[fb] */
19177
  {
19178
    { 0, 0, 0, 0 },
19179
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
19180
    & ifmt_shl32_l_dst_dst32_16_8_FB_relative_Unprefixed_SI, { 0xc2d100 }
19181
  },
19182
/* sha.l r1h,${Dsp-16-s16}[fb] */
19183
  {
19184
    { 0, 0, 0, 0 },
19185
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
19186
    & ifmt_shl32_l_dst_dst32_16_16_FB_relative_Unprefixed_SI, { 0xc4d10000 }
19187
  },
19188
/* sha.l r1h,${Dsp-16-u16} */
19189
  {
19190
    { 0, 0, 0, 0 },
19191
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), 0 } },
19192
    & ifmt_shl32_l_dst_dst32_16_16_absolute_Unprefixed_SI, { 0xc6d10000 }
19193
  },
19194
/* sha.l r1h,${Dsp-16-u24} */
19195
  {
19196
    { 0, 0, 0, 0 },
19197
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U24), 0 } },
19198
    & ifmt_shl32_l_dst_dst32_16_24_absolute_Unprefixed_SI, { 0xc6910000 }
19199
  },
19200
/* sha.l${X} #${Imm-16-QI},$Dst32RnUnprefixedSI */
19201
  {
19202
    { 0, 0, 0, 0 },
19203
    { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
19204
    & ifmt_subx32_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_SI, { 0xa82100 }
19205
  },
19206
/* sha.l${X} #${Imm-16-QI},$Dst32AnUnprefixedSI */
19207
  {
19208
    { 0, 0, 0, 0 },
19209
    { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
19210
    & ifmt_subx32_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_SI, { 0xa0a100 }
19211
  },
19212
/* sha.l${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */
19213
  {
19214
    { 0, 0, 0, 0 },
19215
    { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
19216
    & ifmt_subx32_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_SI, { 0xa02100 }
19217
  },
19218
/* sha.l${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
19219
  {
19220
    { 0, 0, 0, 0 },
19221
    { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
19222
    & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_SI, { 0xa2210000 }
19223
  },
19224
/* sha.l${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
19225
  {
19226
    { 0, 0, 0, 0 },
19227
    { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
19228
    & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_SI, { 0xa2a10000 }
19229
  },
19230
/* sha.l${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
19231
  {
19232
    { 0, 0, 0, 0 },
19233
    { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
19234
    & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_SI, { 0xa2e10000 }
19235
  },
19236
/* sha.l${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
19237
  {
19238
    { 0, 0, 0, 0 },
19239
    { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
19240
    & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_SI, { 0xa4210000 }
19241
  },
19242
/* sha.l${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
19243
  {
19244
    { 0, 0, 0, 0 },
19245
    { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
19246
    & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_SI, { 0xa4a10000 }
19247
  },
19248
/* sha.l${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */
19249
  {
19250
    { 0, 0, 0, 0 },
19251
    { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
19252
    & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_SI, { 0xa4e10000 }
19253
  },
19254
/* sha.l${X} #${Imm-32-QI},${Dsp-16-u16} */
19255
  {
19256
    { 0, 0, 0, 0 },
19257
    { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } },
19258
    & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_SI, { 0xa6e10000 }
19259
  },
19260
/* sha.l${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
19261
  {
19262
    { 0, 0, 0, 0 },
19263
    { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
19264
    & ifmt_subx32_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_SI, { 0xa6210000 }
19265
  },
19266
/* sha.l${X} #${Imm-40-QI},${Dsp-16-u24} */
19267
  {
19268
    { 0, 0, 0, 0 },
19269
    { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), 0 } },
19270
    & ifmt_subx32_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_SI, { 0xa6a10000 }
19271
  },
19272
/* sha.w r1h,$Dst32RnUnprefixedHI */
19273
  {
19274
    { 0, 0, 0, 0 },
19275
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
19276
    & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xb93e }
19277
  },
19278
/* sha.w r1h,$Dst32AnUnprefixedHI */
19279
  {
19280
    { 0, 0, 0, 0 },
19281
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
19282
    & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xb1be }
19283
  },
19284
/* sha.w r1h,[$Dst32AnUnprefixed] */
19285
  {
19286
    { 0, 0, 0, 0 },
19287
    { { MNEM, ' ', 'r', '1', 'h', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
19288
    & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xb13e }
19289
  },
19290
/* sha.w r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */
19291
  {
19292
    { 0, 0, 0, 0 },
19293
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
19294
    & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xb33e00 }
19295
  },
19296
/* sha.w r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */
19297
  {
19298
    { 0, 0, 0, 0 },
19299
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
19300
    & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xb53e0000 }
19301
  },
19302
/* sha.w r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */
19303
  {
19304
    { 0, 0, 0, 0 },
19305
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
19306
    & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xb73e0000 }
19307
  },
19308
/* sha.w r1h,${Dsp-16-u8}[sb] */
19309
  {
19310
    { 0, 0, 0, 0 },
19311
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
19312
    & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xb3be00 }
19313
  },
19314
/* sha.w r1h,${Dsp-16-u16}[sb] */
19315
  {
19316
    { 0, 0, 0, 0 },
19317
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
19318
    & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xb5be0000 }
19319
  },
19320
/* sha.w r1h,${Dsp-16-s8}[fb] */
19321
  {
19322
    { 0, 0, 0, 0 },
19323
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
19324
    & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xb3fe00 }
19325
  },
19326
/* sha.w r1h,${Dsp-16-s16}[fb] */
19327
  {
19328
    { 0, 0, 0, 0 },
19329
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
19330
    & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xb5fe0000 }
19331
  },
19332
/* sha.w r1h,${Dsp-16-u16} */
19333
  {
19334
    { 0, 0, 0, 0 },
19335
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), 0 } },
19336
    & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xb7fe0000 }
19337
  },
19338
/* sha.w r1h,${Dsp-16-u24} */
19339
  {
19340
    { 0, 0, 0, 0 },
19341
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U24), 0 } },
19342
    & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xb7be0000 }
19343
  },
19344
/* sha.b r1h,$Dst32RnUnprefixedQI */
19345
  {
19346
    { 0, 0, 0, 0 },
19347
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
19348
    & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0xb83e }
19349
  },
19350
/* sha.b r1h,$Dst32AnUnprefixedQI */
19351
  {
19352
    { 0, 0, 0, 0 },
19353
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
19354
    & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0xb0be }
19355
  },
19356
/* sha.b r1h,[$Dst32AnUnprefixed] */
19357
  {
19358
    { 0, 0, 0, 0 },
19359
    { { MNEM, ' ', 'r', '1', 'h', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
19360
    & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0xb03e }
19361
  },
19362
/* sha.b r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */
19363
  {
19364
    { 0, 0, 0, 0 },
19365
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
19366
    & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0xb23e00 }
19367
  },
19368
/* sha.b r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */
19369
  {
19370
    { 0, 0, 0, 0 },
19371
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
19372
    & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0xb43e0000 }
19373
  },
19374
/* sha.b r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */
19375
  {
19376
    { 0, 0, 0, 0 },
19377
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
19378
    & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0xb63e0000 }
19379
  },
19380
/* sha.b r1h,${Dsp-16-u8}[sb] */
19381
  {
19382
    { 0, 0, 0, 0 },
19383
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
19384
    & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0xb2be00 }
19385
  },
19386
/* sha.b r1h,${Dsp-16-u16}[sb] */
19387
  {
19388
    { 0, 0, 0, 0 },
19389
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
19390
    & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0xb4be0000 }
19391
  },
19392
/* sha.b r1h,${Dsp-16-s8}[fb] */
19393
  {
19394
    { 0, 0, 0, 0 },
19395
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
19396
    & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0xb2fe00 }
19397
  },
19398
/* sha.b r1h,${Dsp-16-s16}[fb] */
19399
  {
19400
    { 0, 0, 0, 0 },
19401
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
19402
    & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0xb4fe0000 }
19403
  },
19404
/* sha.b r1h,${Dsp-16-u16} */
19405
  {
19406
    { 0, 0, 0, 0 },
19407
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), 0 } },
19408
    & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0xb6fe0000 }
19409
  },
19410
/* sha.b r1h,${Dsp-16-u24} */
19411
  {
19412
    { 0, 0, 0, 0 },
19413
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U24), 0 } },
19414
    & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0xb6be0000 }
19415
  },
19416
/* sha.w r1h,$Dst16RnHI */
19417
  {
19418
    { 0, 0, 0, 0 },
19419
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST16RNHI), 0 } },
19420
    & ifmt_shl16_w_dst_dst16_Rn_direct_HI, { 0x75f0 }
19421
  },
19422
/* sha.w r1h,$Dst16AnHI */
19423
  {
19424
    { 0, 0, 0, 0 },
19425
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST16ANHI), 0 } },
19426
    & ifmt_shl16_w_dst_dst16_An_direct_HI, { 0x75f4 }
19427
  },
19428
/* sha.w r1h,[$Dst16An] */
19429
  {
19430
    { 0, 0, 0, 0 },
19431
    { { MNEM, ' ', 'r', '1', 'h', ',', '[', OP (DST16AN), ']', 0 } },
19432
    & ifmt_shl16_w_dst_dst16_An_indirect_HI, { 0x75f6 }
19433
  },
19434
/* sha.w r1h,${Dsp-16-u8}[$Dst16An] */
19435
  {
19436
    { 0, 0, 0, 0 },
19437
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
19438
    & ifmt_shl16_w_dst_dst16_16_8_An_relative_HI, { 0x75f800 }
19439
  },
19440
/* sha.w r1h,${Dsp-16-u16}[$Dst16An] */
19441
  {
19442
    { 0, 0, 0, 0 },
19443
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
19444
    & ifmt_shl16_w_dst_dst16_16_16_An_relative_HI, { 0x75fc0000 }
19445
  },
19446
/* sha.w r1h,${Dsp-16-u8}[sb] */
19447
  {
19448
    { 0, 0, 0, 0 },
19449
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
19450
    & ifmt_shl16_w_dst_dst16_16_8_SB_relative_HI, { 0x75fa00 }
19451
  },
19452
/* sha.w r1h,${Dsp-16-u16}[sb] */
19453
  {
19454
    { 0, 0, 0, 0 },
19455
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
19456
    & ifmt_shl16_w_dst_dst16_16_16_SB_relative_HI, { 0x75fe0000 }
19457
  },
19458
/* sha.w r1h,${Dsp-16-s8}[fb] */
19459
  {
19460
    { 0, 0, 0, 0 },
19461
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
19462
    & ifmt_shl16_w_dst_dst16_16_8_FB_relative_HI, { 0x75fb00 }
19463
  },
19464
/* sha.w r1h,${Dsp-16-u16} */
19465
  {
19466
    { 0, 0, 0, 0 },
19467
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), 0 } },
19468
    & ifmt_shl16_w_dst_dst16_16_16_absolute_HI, { 0x75ff0000 }
19469
  },
19470
/* sha.b r1h,$Dst16RnQI */
19471
  {
19472
    { 0, 0, 0, 0 },
19473
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST16RNQI), 0 } },
19474
    & ifmt_shl16_b_dst_dst16_Rn_direct_QI, { 0x74f0 }
19475
  },
19476
/* sha.b r1h,$Dst16AnQI */
19477
  {
19478
    { 0, 0, 0, 0 },
19479
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST16ANQI), 0 } },
19480
    & ifmt_shl16_b_dst_dst16_An_direct_QI, { 0x74f4 }
19481
  },
19482
/* sha.b r1h,[$Dst16An] */
19483
  {
19484
    { 0, 0, 0, 0 },
19485
    { { MNEM, ' ', 'r', '1', 'h', ',', '[', OP (DST16AN), ']', 0 } },
19486
    & ifmt_shl16_b_dst_dst16_An_indirect_QI, { 0x74f6 }
19487
  },
19488
/* sha.b r1h,${Dsp-16-u8}[$Dst16An] */
19489
  {
19490
    { 0, 0, 0, 0 },
19491
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
19492
    & ifmt_shl16_b_dst_dst16_16_8_An_relative_QI, { 0x74f800 }
19493
  },
19494
/* sha.b r1h,${Dsp-16-u16}[$Dst16An] */
19495
  {
19496
    { 0, 0, 0, 0 },
19497
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
19498
    & ifmt_shl16_b_dst_dst16_16_16_An_relative_QI, { 0x74fc0000 }
19499
  },
19500
/* sha.b r1h,${Dsp-16-u8}[sb] */
19501
  {
19502
    { 0, 0, 0, 0 },
19503
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
19504
    & ifmt_shl16_b_dst_dst16_16_8_SB_relative_QI, { 0x74fa00 }
19505
  },
19506
/* sha.b r1h,${Dsp-16-u16}[sb] */
19507
  {
19508
    { 0, 0, 0, 0 },
19509
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
19510
    & ifmt_shl16_b_dst_dst16_16_16_SB_relative_QI, { 0x74fe0000 }
19511
  },
19512
/* sha.b r1h,${Dsp-16-s8}[fb] */
19513
  {
19514
    { 0, 0, 0, 0 },
19515
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
19516
    & ifmt_shl16_b_dst_dst16_16_8_FB_relative_QI, { 0x74fb00 }
19517
  },
19518
/* sha.b r1h,${Dsp-16-u16} */
19519
  {
19520
    { 0, 0, 0, 0 },
19521
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), 0 } },
19522
    & ifmt_shl16_b_dst_dst16_16_16_absolute_QI, { 0x74ff0000 }
19523
  },
19524
/* sha.w${Q} #${Imm-sh-12-s4},$Dst32RnUnprefixedHI */
19525
  {
19526
    { 0, 0, 0, 0 },
19527
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
19528
    & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0xf900 }
19529
  },
19530
/* sha.w${Q} #${Imm-sh-12-s4},$Dst32AnUnprefixedHI */
19531
  {
19532
    { 0, 0, 0, 0 },
19533
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
19534
    & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0xf180 }
19535
  },
19536
/* sha.w${Q} #${Imm-sh-12-s4},[$Dst32AnUnprefixed] */
19537
  {
19538
    { 0, 0, 0, 0 },
19539
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
19540
    & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0xf100 }
19541
  },
19542
/* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
19543
  {
19544
    { 0, 0, 0, 0 },
19545
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
19546
    & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0xf30000 }
19547
  },
19548
/* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
19549
  {
19550
    { 0, 0, 0, 0 },
19551
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
19552
    & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0xf5000000 }
19553
  },
19554
/* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
19555
  {
19556
    { 0, 0, 0, 0 },
19557
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
19558
    & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0xf7000000 }
19559
  },
19560
/* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[sb] */
19561
  {
19562
    { 0, 0, 0, 0 },
19563
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
19564
    & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0xf38000 }
19565
  },
19566
/* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[sb] */
19567
  {
19568
    { 0, 0, 0, 0 },
19569
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
19570
    & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0xf5800000 }
19571
  },
19572
/* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-s8}[fb] */
19573
  {
19574
    { 0, 0, 0, 0 },
19575
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
19576
    & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0xf3c000 }
19577
  },
19578
/* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-s16}[fb] */
19579
  {
19580
    { 0, 0, 0, 0 },
19581
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
19582
    & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0xf5c00000 }
19583
  },
19584
/* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16} */
19585
  {
19586
    { 0, 0, 0, 0 },
19587
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U16), 0 } },
19588
    & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0xf7c00000 }
19589
  },
19590
/* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-u24} */
19591
  {
19592
    { 0, 0, 0, 0 },
19593
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U24), 0 } },
19594
    & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0xf7800000 }
19595
  },
19596
/* sha.b${Q} #${Imm-sh-12-s4},$Dst32RnUnprefixedQI */
19597
  {
19598
    { 0, 0, 0, 0 },
19599
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
19600
    & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0xf800 }
19601
  },
19602
/* sha.b${Q} #${Imm-sh-12-s4},$Dst32AnUnprefixedQI */
19603
  {
19604
    { 0, 0, 0, 0 },
19605
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
19606
    & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0xf080 }
19607
  },
19608
/* sha.b${Q} #${Imm-sh-12-s4},[$Dst32AnUnprefixed] */
19609
  {
19610
    { 0, 0, 0, 0 },
19611
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
19612
    & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0xf000 }
19613
  },
19614
/* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
19615
  {
19616
    { 0, 0, 0, 0 },
19617
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
19618
    & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0xf20000 }
19619
  },
19620
/* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
19621
  {
19622
    { 0, 0, 0, 0 },
19623
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
19624
    & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0xf4000000 }
19625
  },
19626
/* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
19627
  {
19628
    { 0, 0, 0, 0 },
19629
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
19630
    & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0xf6000000 }
19631
  },
19632
/* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[sb] */
19633
  {
19634
    { 0, 0, 0, 0 },
19635
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
19636
    & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0xf28000 }
19637
  },
19638
/* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[sb] */
19639
  {
19640
    { 0, 0, 0, 0 },
19641
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
19642
    & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0xf4800000 }
19643
  },
19644
/* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-s8}[fb] */
19645
  {
19646
    { 0, 0, 0, 0 },
19647
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
19648
    & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0xf2c000 }
19649
  },
19650
/* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-s16}[fb] */
19651
  {
19652
    { 0, 0, 0, 0 },
19653
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
19654
    & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0xf4c00000 }
19655
  },
19656
/* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16} */
19657
  {
19658
    { 0, 0, 0, 0 },
19659
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U16), 0 } },
19660
    & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0xf6c00000 }
19661
  },
19662
/* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-u24} */
19663
  {
19664
    { 0, 0, 0, 0 },
19665
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U24), 0 } },
19666
    & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0xf6800000 }
19667
  },
19668
/* sha.w${Q} #${Imm-sh-8-s4},$Dst16RnHI */
19669
  {
19670
    { 0, 0, 0, 0 },
19671
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DST16RNHI), 0 } },
19672
    & ifmt_shl16_w_imm4_Q_16_dst16_Rn_direct_HI, { 0xf100 }
19673
  },
19674
/* sha.w${Q} #${Imm-sh-8-s4},$Dst16AnHI */
19675
  {
19676
    { 0, 0, 0, 0 },
19677
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DST16ANHI), 0 } },
19678
    & ifmt_shl16_w_imm4_Q_16_dst16_An_direct_HI, { 0xf104 }
19679
  },
19680
/* sha.w${Q} #${Imm-sh-8-s4},[$Dst16An] */
19681
  {
19682
    { 0, 0, 0, 0 },
19683
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', '[', OP (DST16AN), ']', 0 } },
19684
    & ifmt_shl16_w_imm4_Q_16_dst16_An_indirect_HI, { 0xf106 }
19685
  },
19686
/* sha.w${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[$Dst16An] */
19687
  {
19688
    { 0, 0, 0, 0 },
19689
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
19690
    & ifmt_shl16_w_imm4_Q_16_dst16_16_8_An_relative_HI, { 0xf10800 }
19691
  },
19692
/* sha.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[$Dst16An] */
19693
  {
19694
    { 0, 0, 0, 0 },
19695
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
19696
    & ifmt_shl16_w_imm4_Q_16_dst16_16_16_An_relative_HI, { 0xf10c0000 }
19697
  },
19698
/* sha.w${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[sb] */
19699
  {
19700
    { 0, 0, 0, 0 },
19701
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
19702
    & ifmt_shl16_w_imm4_Q_16_dst16_16_8_SB_relative_HI, { 0xf10a00 }
19703
  },
19704
/* sha.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[sb] */
19705
  {
19706
    { 0, 0, 0, 0 },
19707
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
19708
    & ifmt_shl16_w_imm4_Q_16_dst16_16_16_SB_relative_HI, { 0xf10e0000 }
19709
  },
19710
/* sha.w${Q} #${Imm-sh-8-s4},${Dsp-16-s8}[fb] */
19711
  {
19712
    { 0, 0, 0, 0 },
19713
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
19714
    & ifmt_shl16_w_imm4_Q_16_dst16_16_8_FB_relative_HI, { 0xf10b00 }
19715
  },
19716
/* sha.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16} */
19717
  {
19718
    { 0, 0, 0, 0 },
19719
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U16), 0 } },
19720
    & ifmt_shl16_w_imm4_Q_16_dst16_16_16_absolute_HI, { 0xf10f0000 }
19721
  },
19722
/* sha.b${Q} #${Imm-sh-8-s4},$Dst16RnQI */
19723
  {
19724
    { 0, 0, 0, 0 },
19725
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DST16RNQI), 0 } },
19726
    & ifmt_shl16_b_imm4_Q_16_dst16_Rn_direct_QI, { 0xf000 }
19727
  },
19728
/* sha.b${Q} #${Imm-sh-8-s4},$Dst16AnQI */
19729
  {
19730
    { 0, 0, 0, 0 },
19731
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DST16ANQI), 0 } },
19732
    & ifmt_shl16_b_imm4_Q_16_dst16_An_direct_QI, { 0xf004 }
19733
  },
19734
/* sha.b${Q} #${Imm-sh-8-s4},[$Dst16An] */
19735
  {
19736
    { 0, 0, 0, 0 },
19737
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', '[', OP (DST16AN), ']', 0 } },
19738
    & ifmt_shl16_b_imm4_Q_16_dst16_An_indirect_QI, { 0xf006 }
19739
  },
19740
/* sha.b${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[$Dst16An] */
19741
  {
19742
    { 0, 0, 0, 0 },
19743
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
19744
    & ifmt_shl16_b_imm4_Q_16_dst16_16_8_An_relative_QI, { 0xf00800 }
19745
  },
19746
/* sha.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[$Dst16An] */
19747
  {
19748
    { 0, 0, 0, 0 },
19749
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
19750
    & ifmt_shl16_b_imm4_Q_16_dst16_16_16_An_relative_QI, { 0xf00c0000 }
19751
  },
19752
/* sha.b${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[sb] */
19753
  {
19754
    { 0, 0, 0, 0 },
19755
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
19756
    & ifmt_shl16_b_imm4_Q_16_dst16_16_8_SB_relative_QI, { 0xf00a00 }
19757
  },
19758
/* sha.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[sb] */
19759
  {
19760
    { 0, 0, 0, 0 },
19761
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
19762
    & ifmt_shl16_b_imm4_Q_16_dst16_16_16_SB_relative_QI, { 0xf00e0000 }
19763
  },
19764
/* sha.b${Q} #${Imm-sh-8-s4},${Dsp-16-s8}[fb] */
19765
  {
19766
    { 0, 0, 0, 0 },
19767
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
19768
    & ifmt_shl16_b_imm4_Q_16_dst16_16_8_FB_relative_QI, { 0xf00b00 }
19769
  },
19770
/* sha.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16} */
19771
  {
19772
    { 0, 0, 0, 0 },
19773
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U16), 0 } },
19774
    & ifmt_shl16_b_imm4_Q_16_dst16_16_16_absolute_QI, { 0xf00f0000 }
19775
  },
19776
/* sc${sccond32} $Dst32RnUnprefixedHI */
19777
  {
19778
    { 0, 0, 0, 0 },
19779
    { { MNEM, OP (SCCOND32), ' ', OP (DST32RNUNPREFIXEDHI), 0 } },
19780
    & ifmt_sccnd_dst32_Rn_direct_Unprefixed_HI, { 0xd930 }
19781
  },
19782
/* sc${sccond32} $Dst32AnUnprefixedHI */
19783
  {
19784
    { 0, 0, 0, 0 },
19785
    { { MNEM, OP (SCCOND32), ' ', OP (DST32ANUNPREFIXEDHI), 0 } },
19786
    & ifmt_sccnd_dst32_An_direct_Unprefixed_HI, { 0xd1b0 }
19787
  },
19788
/* sc${sccond32} [$Dst32AnUnprefixed] */
19789
  {
19790
    { 0, 0, 0, 0 },
19791
    { { MNEM, OP (SCCOND32), ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
19792
    & ifmt_sccnd_dst32_An_indirect_Unprefixed_HI, { 0xd130 }
19793
  },
19794
/* sc${sccond32} ${Dsp-16-u8}[$Dst32AnUnprefixed] */
19795
  {
19796
    { 0, 0, 0, 0 },
19797
    { { MNEM, OP (SCCOND32), ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
19798
    & ifmt_sccnd_dst32_16_8_An_relative_Unprefixed_HI, { 0xd33000 }
19799
  },
19800
/* sc${sccond32} ${Dsp-16-u16}[$Dst32AnUnprefixed] */
19801
  {
19802
    { 0, 0, 0, 0 },
19803
    { { MNEM, OP (SCCOND32), ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
19804
    & ifmt_sccnd_dst32_16_16_An_relative_Unprefixed_HI, { 0xd5300000 }
19805
  },
19806
/* sc${sccond32} ${Dsp-16-u24}[$Dst32AnUnprefixed] */
19807
  {
19808
    { 0, 0, 0, 0 },
19809
    { { MNEM, OP (SCCOND32), ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
19810
    & ifmt_sccnd_dst32_16_24_An_relative_Unprefixed_HI, { 0xd7300000 }
19811
  },
19812
/* sc${sccond32} ${Dsp-16-u8}[sb] */
19813
  {
19814
    { 0, 0, 0, 0 },
19815
    { { MNEM, OP (SCCOND32), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
19816
    & ifmt_sccnd_dst32_16_8_SB_relative_Unprefixed_HI, { 0xd3b000 }
19817
  },
19818
/* sc${sccond32} ${Dsp-16-u16}[sb] */
19819
  {
19820
    { 0, 0, 0, 0 },
19821
    { { MNEM, OP (SCCOND32), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
19822
    & ifmt_sccnd_dst32_16_16_SB_relative_Unprefixed_HI, { 0xd5b00000 }
19823
  },
19824
/* sc${sccond32} ${Dsp-16-s8}[fb] */
19825
  {
19826
    { 0, 0, 0, 0 },
19827
    { { MNEM, OP (SCCOND32), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
19828
    & ifmt_sccnd_dst32_16_8_FB_relative_Unprefixed_HI, { 0xd3f000 }
19829
  },
19830
/* sc${sccond32} ${Dsp-16-s16}[fb] */
19831
  {
19832
    { 0, 0, 0, 0 },
19833
    { { MNEM, OP (SCCOND32), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
19834
    & ifmt_sccnd_dst32_16_16_FB_relative_Unprefixed_HI, { 0xd5f00000 }
19835
  },
19836
/* sc${sccond32} ${Dsp-16-u16} */
19837
  {
19838
    { 0, 0, 0, 0 },
19839
    { { MNEM, OP (SCCOND32), ' ', OP (DSP_16_U16), 0 } },
19840
    & ifmt_sccnd_dst32_16_16_absolute_Unprefixed_HI, { 0xd7f00000 }
19841
  },
19842
/* sc${sccond32} ${Dsp-16-u24} */
19843
  {
19844
    { 0, 0, 0, 0 },
19845
    { { MNEM, OP (SCCOND32), ' ', OP (DSP_16_U24), 0 } },
19846
    & ifmt_sccnd_dst32_16_24_absolute_Unprefixed_HI, { 0xd7b00000 }
19847
  },
19848
/* sbjnz.w #${Imm-12-s4n},${Dsp-16-u8}[$Dst32AnUnprefixed],${Lab-24-8} */
19849
  {
19850
    { 0, 0, 0, 0 },
19851
    { { MNEM, ' ', '#', OP (IMM_12_S4N), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (LAB_24_8), 0 } },
19852
    & ifmt_sbjnz32_w_imm4_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0xf3100000 }
19853
  },
19854
/* sbjnz.w #${Imm-12-s4n},${Dsp-16-u8}[sb],${Lab-24-8} */
19855
  {
19856
    { 0, 0, 0, 0 },
19857
    { { MNEM, ' ', '#', OP (IMM_12_S4N), ',', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (LAB_24_8), 0 } },
19858
    & ifmt_sbjnz32_w_imm4_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0xf3900000 }
19859
  },
19860
/* sbjnz.w #${Imm-12-s4n},${Dsp-16-s8}[fb],${Lab-24-8} */
19861
  {
19862
    { 0, 0, 0, 0 },
19863
    { { MNEM, ' ', '#', OP (IMM_12_S4N), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (LAB_24_8), 0 } },
19864
    & ifmt_sbjnz32_w_imm4_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0xf3d00000 }
19865
  },
19866
/* sbjnz.w #${Imm-12-s4n},${Dsp-16-u16}[$Dst32AnUnprefixed],${Lab-32-8} */
19867
  {
19868
    { 0, 0, 0, 0 },
19869
    { { MNEM, ' ', '#', OP (IMM_12_S4N), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (LAB_32_8), 0 } },
19870
    & ifmt_sbjnz32_w_imm4_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0xf5100000 }
19871
  },
19872
/* sbjnz.w #${Imm-12-s4n},${Dsp-16-u16}[sb],${Lab-32-8} */
19873
  {
19874
    { 0, 0, 0, 0 },
19875
    { { MNEM, ' ', '#', OP (IMM_12_S4N), ',', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (LAB_32_8), 0 } },
19876
    & ifmt_sbjnz32_w_imm4_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0xf5900000 }
19877
  },
19878
/* sbjnz.w #${Imm-12-s4n},${Dsp-16-s16}[fb],${Lab-32-8} */
19879
  {
19880
    { 0, 0, 0, 0 },
19881
    { { MNEM, ' ', '#', OP (IMM_12_S4N), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (LAB_32_8), 0 } },
19882
    & ifmt_sbjnz32_w_imm4_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0xf5d00000 }
19883
  },
19884
/* sbjnz.w #${Imm-12-s4n},${Dsp-16-u16},${Lab-32-8} */
19885
  {
19886
    { 0, 0, 0, 0 },
19887
    { { MNEM, ' ', '#', OP (IMM_12_S4N), ',', OP (DSP_16_U16), ',', OP (LAB_32_8), 0 } },
19888
    & ifmt_sbjnz32_w_imm4_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0xf7d00000 }
19889
  },
19890
/* sbjnz.w #${Imm-12-s4n},${Dsp-16-u24}[$Dst32AnUnprefixed],${Lab-40-8} */
19891
  {
19892
    { 0, 0, 0, 0 },
19893
    { { MNEM, ' ', '#', OP (IMM_12_S4N), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (LAB_40_8), 0 } },
19894
    & ifmt_sbjnz32_w_imm4_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0xf7100000 }
19895
  },
19896
/* sbjnz.w #${Imm-12-s4n},${Dsp-16-u24},${Lab-40-8} */
19897
  {
19898
    { 0, 0, 0, 0 },
19899
    { { MNEM, ' ', '#', OP (IMM_12_S4N), ',', OP (DSP_16_U24), ',', OP (LAB_40_8), 0 } },
19900
    & ifmt_sbjnz32_w_imm4_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0xf7900000 }
19901
  },
19902
/* sbjnz.w #${Imm-12-s4n},$Dst32RnUnprefixedHI,${Lab-16-8} */
19903
  {
19904
    { 0, 0, 0, 0 },
19905
    { { MNEM, ' ', '#', OP (IMM_12_S4N), ',', OP (DST32RNUNPREFIXEDHI), ',', OP (LAB_16_8), 0 } },
19906
    & ifmt_sbjnz32_w_imm4_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0xf91000 }
19907
  },
19908
/* sbjnz.w #${Imm-12-s4n},$Dst32AnUnprefixedHI,${Lab-16-8} */
19909
  {
19910
    { 0, 0, 0, 0 },
19911
    { { MNEM, ' ', '#', OP (IMM_12_S4N), ',', OP (DST32ANUNPREFIXEDHI), ',', OP (LAB_16_8), 0 } },
19912
    & ifmt_sbjnz32_w_imm4_basic_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0xf19000 }
19913
  },
19914
/* sbjnz.w #${Imm-12-s4n},[$Dst32AnUnprefixed],${Lab-16-8} */
19915
  {
19916
    { 0, 0, 0, 0 },
19917
    { { MNEM, ' ', '#', OP (IMM_12_S4N), ',', '[', OP (DST32ANUNPREFIXED), ']', ',', OP (LAB_16_8), 0 } },
19918
    & ifmt_sbjnz32_w_imm4_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0xf11000 }
19919
  },
19920
/* sbjnz.b #${Imm-12-s4n},${Dsp-16-u8}[$Dst32AnUnprefixed],${Lab-24-8} */
19921
  {
19922
    { 0, 0, 0, 0 },
19923
    { { MNEM, ' ', '#', OP (IMM_12_S4N), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (LAB_24_8), 0 } },
19924
    & ifmt_sbjnz32_b_imm4_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0xf2100000 }
19925
  },
19926
/* sbjnz.b #${Imm-12-s4n},${Dsp-16-u8}[sb],${Lab-24-8} */
19927
  {
19928
    { 0, 0, 0, 0 },
19929
    { { MNEM, ' ', '#', OP (IMM_12_S4N), ',', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (LAB_24_8), 0 } },
19930
    & ifmt_sbjnz32_b_imm4_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0xf2900000 }
19931
  },
19932
/* sbjnz.b #${Imm-12-s4n},${Dsp-16-s8}[fb],${Lab-24-8} */
19933
  {
19934
    { 0, 0, 0, 0 },
19935
    { { MNEM, ' ', '#', OP (IMM_12_S4N), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (LAB_24_8), 0 } },
19936
    & ifmt_sbjnz32_b_imm4_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0xf2d00000 }
19937
  },
19938
/* sbjnz.b #${Imm-12-s4n},${Dsp-16-u16}[$Dst32AnUnprefixed],${Lab-32-8} */
19939
  {
19940
    { 0, 0, 0, 0 },
19941
    { { MNEM, ' ', '#', OP (IMM_12_S4N), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (LAB_32_8), 0 } },
19942
    & ifmt_sbjnz32_b_imm4_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0xf4100000 }
19943
  },
19944
/* sbjnz.b #${Imm-12-s4n},${Dsp-16-u16}[sb],${Lab-32-8} */
19945
  {
19946
    { 0, 0, 0, 0 },
19947
    { { MNEM, ' ', '#', OP (IMM_12_S4N), ',', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (LAB_32_8), 0 } },
19948
    & ifmt_sbjnz32_b_imm4_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0xf4900000 }
19949
  },
19950
/* sbjnz.b #${Imm-12-s4n},${Dsp-16-s16}[fb],${Lab-32-8} */
19951
  {
19952
    { 0, 0, 0, 0 },
19953
    { { MNEM, ' ', '#', OP (IMM_12_S4N), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (LAB_32_8), 0 } },
19954
    & ifmt_sbjnz32_b_imm4_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0xf4d00000 }
19955
  },
19956
/* sbjnz.b #${Imm-12-s4n},${Dsp-16-u16},${Lab-32-8} */
19957
  {
19958
    { 0, 0, 0, 0 },
19959
    { { MNEM, ' ', '#', OP (IMM_12_S4N), ',', OP (DSP_16_U16), ',', OP (LAB_32_8), 0 } },
19960
    & ifmt_sbjnz32_b_imm4_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0xf6d00000 }
19961
  },
19962
/* sbjnz.b #${Imm-12-s4n},${Dsp-16-u24}[$Dst32AnUnprefixed],${Lab-40-8} */
19963
  {
19964
    { 0, 0, 0, 0 },
19965
    { { MNEM, ' ', '#', OP (IMM_12_S4N), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (LAB_40_8), 0 } },
19966
    & ifmt_sbjnz32_b_imm4_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0xf6100000 }
19967
  },
19968
/* sbjnz.b #${Imm-12-s4n},${Dsp-16-u24},${Lab-40-8} */
19969
  {
19970
    { 0, 0, 0, 0 },
19971
    { { MNEM, ' ', '#', OP (IMM_12_S4N), ',', OP (DSP_16_U24), ',', OP (LAB_40_8), 0 } },
19972
    & ifmt_sbjnz32_b_imm4_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0xf6900000 }
19973
  },
19974
/* sbjnz.b #${Imm-12-s4n},$Dst32RnUnprefixedQI,${Lab-16-8} */
19975
  {
19976
    { 0, 0, 0, 0 },
19977
    { { MNEM, ' ', '#', OP (IMM_12_S4N), ',', OP (DST32RNUNPREFIXEDQI), ',', OP (LAB_16_8), 0 } },
19978
    & ifmt_sbjnz32_b_imm4_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0xf81000 }
19979
  },
19980
/* sbjnz.b #${Imm-12-s4n},$Dst32AnUnprefixedQI,${Lab-16-8} */
19981
  {
19982
    { 0, 0, 0, 0 },
19983
    { { MNEM, ' ', '#', OP (IMM_12_S4N), ',', OP (DST32ANUNPREFIXEDQI), ',', OP (LAB_16_8), 0 } },
19984
    & ifmt_sbjnz32_b_imm4_basic_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0xf09000 }
19985
  },
19986
/* sbjnz.b #${Imm-12-s4n},[$Dst32AnUnprefixed],${Lab-16-8} */
19987
  {
19988
    { 0, 0, 0, 0 },
19989
    { { MNEM, ' ', '#', OP (IMM_12_S4N), ',', '[', OP (DST32ANUNPREFIXED), ']', ',', OP (LAB_16_8), 0 } },
19990
    & ifmt_sbjnz32_b_imm4_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0xf01000 }
19991
  },
19992
/* sbjnz.w #${Imm-8-s4n},${Dsp-16-u8}[$Dst16An],${Lab-24-8} */
19993
  {
19994
    { 0, 0, 0, 0 },
19995
    { { MNEM, ' ', '#', OP (IMM_8_S4N), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', OP (LAB_24_8), 0 } },
19996
    & ifmt_sbjnz16_w_imm4_16_8_dst16_16_8_An_relative_HI, { 0xf9080000 }
19997
  },
19998
/* sbjnz.w #${Imm-8-s4n},${Dsp-16-u8}[sb],${Lab-24-8} */
19999
  {
20000
    { 0, 0, 0, 0 },
20001
    { { MNEM, ' ', '#', OP (IMM_8_S4N), ',', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (LAB_24_8), 0 } },
20002
    & ifmt_sbjnz16_w_imm4_16_8_dst16_16_8_SB_relative_HI, { 0xf90a0000 }
20003
  },
20004
/* sbjnz.w #${Imm-8-s4n},${Dsp-16-s8}[fb],${Lab-24-8} */
20005
  {
20006
    { 0, 0, 0, 0 },
20007
    { { MNEM, ' ', '#', OP (IMM_8_S4N), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (LAB_24_8), 0 } },
20008
    & ifmt_sbjnz16_w_imm4_16_8_dst16_16_8_FB_relative_HI, { 0xf90b0000 }
20009
  },
20010
/* sbjnz.w #${Imm-8-s4n},${Dsp-16-u16}[$Dst16An],${Lab-32-8} */
20011
  {
20012
    { 0, 0, 0, 0 },
20013
    { { MNEM, ' ', '#', OP (IMM_8_S4N), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', OP (LAB_32_8), 0 } },
20014
    & ifmt_sbjnz16_w_imm4_16_16_dst16_16_16_An_relative_HI, { 0xf90c0000 }
20015
  },
20016
/* sbjnz.w #${Imm-8-s4n},${Dsp-16-u16}[sb],${Lab-32-8} */
20017
  {
20018
    { 0, 0, 0, 0 },
20019
    { { MNEM, ' ', '#', OP (IMM_8_S4N), ',', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (LAB_32_8), 0 } },
20020
    & ifmt_sbjnz16_w_imm4_16_16_dst16_16_16_SB_relative_HI, { 0xf90e0000 }
20021
  },
20022
/* sbjnz.w #${Imm-8-s4n},${Dsp-16-u16},${Lab-32-8} */
20023
  {
20024
    { 0, 0, 0, 0 },
20025
    { { MNEM, ' ', '#', OP (IMM_8_S4N), ',', OP (DSP_16_U16), ',', OP (LAB_32_8), 0 } },
20026
    & ifmt_sbjnz16_w_imm4_16_16_dst16_16_16_absolute_HI, { 0xf90f0000 }
20027
  },
20028
/* sbjnz.w #${Imm-8-s4n},$Dst16RnHI,${Lab-16-8} */
20029
  {
20030
    { 0, 0, 0, 0 },
20031
    { { MNEM, ' ', '#', OP (IMM_8_S4N), ',', OP (DST16RNHI), ',', OP (LAB_16_8), 0 } },
20032
    & ifmt_sbjnz16_w_imm4_basic_dst16_Rn_direct_HI, { 0xf90000 }
20033
  },
20034
/* sbjnz.w #${Imm-8-s4n},$Dst16AnHI,${Lab-16-8} */
20035
  {
20036
    { 0, 0, 0, 0 },
20037
    { { MNEM, ' ', '#', OP (IMM_8_S4N), ',', OP (DST16ANHI), ',', OP (LAB_16_8), 0 } },
20038
    & ifmt_sbjnz16_w_imm4_basic_dst16_An_direct_HI, { 0xf90400 }
20039
  },
20040
/* sbjnz.w #${Imm-8-s4n},[$Dst16An],${Lab-16-8} */
20041
  {
20042
    { 0, 0, 0, 0 },
20043
    { { MNEM, ' ', '#', OP (IMM_8_S4N), ',', '[', OP (DST16AN), ']', ',', OP (LAB_16_8), 0 } },
20044
    & ifmt_sbjnz16_w_imm4_basic_dst16_An_indirect_HI, { 0xf90600 }
20045
  },
20046
/* sbjnz.b #${Imm-8-s4n},${Dsp-16-u8}[$Dst16An],${Lab-24-8} */
20047
  {
20048
    { 0, 0, 0, 0 },
20049
    { { MNEM, ' ', '#', OP (IMM_8_S4N), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', OP (LAB_24_8), 0 } },
20050
    & ifmt_sbjnz16_b_imm4_16_8_dst16_16_8_An_relative_QI, { 0xf8080000 }
20051
  },
20052
/* sbjnz.b #${Imm-8-s4n},${Dsp-16-u8}[sb],${Lab-24-8} */
20053
  {
20054
    { 0, 0, 0, 0 },
20055
    { { MNEM, ' ', '#', OP (IMM_8_S4N), ',', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (LAB_24_8), 0 } },
20056
    & ifmt_sbjnz16_b_imm4_16_8_dst16_16_8_SB_relative_QI, { 0xf80a0000 }
20057
  },
20058
/* sbjnz.b #${Imm-8-s4n},${Dsp-16-s8}[fb],${Lab-24-8} */
20059
  {
20060
    { 0, 0, 0, 0 },
20061
    { { MNEM, ' ', '#', OP (IMM_8_S4N), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (LAB_24_8), 0 } },
20062
    & ifmt_sbjnz16_b_imm4_16_8_dst16_16_8_FB_relative_QI, { 0xf80b0000 }
20063
  },
20064
/* sbjnz.b #${Imm-8-s4n},${Dsp-16-u16}[$Dst16An],${Lab-32-8} */
20065
  {
20066
    { 0, 0, 0, 0 },
20067
    { { MNEM, ' ', '#', OP (IMM_8_S4N), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', OP (LAB_32_8), 0 } },
20068
    & ifmt_sbjnz16_b_imm4_16_16_dst16_16_16_An_relative_QI, { 0xf80c0000 }
20069
  },
20070
/* sbjnz.b #${Imm-8-s4n},${Dsp-16-u16}[sb],${Lab-32-8} */
20071
  {
20072
    { 0, 0, 0, 0 },
20073
    { { MNEM, ' ', '#', OP (IMM_8_S4N), ',', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (LAB_32_8), 0 } },
20074
    & ifmt_sbjnz16_b_imm4_16_16_dst16_16_16_SB_relative_QI, { 0xf80e0000 }
20075
  },
20076
/* sbjnz.b #${Imm-8-s4n},${Dsp-16-u16},${Lab-32-8} */
20077
  {
20078
    { 0, 0, 0, 0 },
20079
    { { MNEM, ' ', '#', OP (IMM_8_S4N), ',', OP (DSP_16_U16), ',', OP (LAB_32_8), 0 } },
20080
    & ifmt_sbjnz16_b_imm4_16_16_dst16_16_16_absolute_QI, { 0xf80f0000 }
20081
  },
20082
/* sbjnz.b #${Imm-8-s4n},$Dst16RnQI,${Lab-16-8} */
20083
  {
20084
    { 0, 0, 0, 0 },
20085
    { { MNEM, ' ', '#', OP (IMM_8_S4N), ',', OP (DST16RNQI), ',', OP (LAB_16_8), 0 } },
20086
    & ifmt_sbjnz16_b_imm4_basic_dst16_Rn_direct_QI, { 0xf80000 }
20087
  },
20088
/* sbjnz.b #${Imm-8-s4n},$Dst16AnQI,${Lab-16-8} */
20089
  {
20090
    { 0, 0, 0, 0 },
20091
    { { MNEM, ' ', '#', OP (IMM_8_S4N), ',', OP (DST16ANQI), ',', OP (LAB_16_8), 0 } },
20092
    & ifmt_sbjnz16_b_imm4_basic_dst16_An_direct_QI, { 0xf80400 }
20093
  },
20094
/* sbjnz.b #${Imm-8-s4n},[$Dst16An],${Lab-16-8} */
20095
  {
20096
    { 0, 0, 0, 0 },
20097
    { { MNEM, ' ', '#', OP (IMM_8_S4N), ',', '[', OP (DST16AN), ']', ',', OP (LAB_16_8), 0 } },
20098
    & ifmt_sbjnz16_b_imm4_basic_dst16_An_indirect_QI, { 0xf80600 }
20099
  },
20100
/* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
20101
  {
20102
    { 0, 0, 0, 0 },
20103
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
20104
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1990600 }
20105
  },
20106
/* sbb.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
20107
  {
20108
    { 0, 0, 0, 0 },
20109
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
20110
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1992600 }
20111
  },
20112
/* sbb.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
20113
  {
20114
    { 0, 0, 0, 0 },
20115
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
20116
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1993600 }
20117
  },
20118
/* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
20119
  {
20120
    { 0, 0, 0, 0 },
20121
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
20122
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1918600 }
20123
  },
20124
/* sbb.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
20125
  {
20126
    { 0, 0, 0, 0 },
20127
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
20128
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x191a600 }
20129
  },
20130
/* sbb.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
20131
  {
20132
    { 0, 0, 0, 0 },
20133
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
20134
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x191b600 }
20135
  },
20136
/* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
20137
  {
20138
    { 0, 0, 0, 0 },
20139
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
20140
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1910600 }
20141
  },
20142
/* sbb.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
20143
  {
20144
    { 0, 0, 0, 0 },
20145
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
20146
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1912600 }
20147
  },
20148
/* sbb.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
20149
  {
20150
    { 0, 0, 0, 0 },
20151
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
20152
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1913600 }
20153
  },
20154
/* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
20155
  {
20156
    { 0, 0, 0, 0 },
20157
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
20158
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1930600 }
20159
  },
20160
/* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
20161
  {
20162
    { 0, 0, 0, 0 },
20163
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
20164
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1932600 }
20165
  },
20166
/* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
20167
  {
20168
    { 0, 0, 0, 0 },
20169
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
20170
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1933600 }
20171
  },
20172
/* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
20173
  {
20174
    { 0, 0, 0, 0 },
20175
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
20176
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1950600 }
20177
  },
20178
/* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
20179
  {
20180
    { 0, 0, 0, 0 },
20181
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
20182
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1952600 }
20183
  },
20184
/* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
20185
  {
20186
    { 0, 0, 0, 0 },
20187
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
20188
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1953600 }
20189
  },
20190
/* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
20191
  {
20192
    { 0, 0, 0, 0 },
20193
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
20194
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1970600 }
20195
  },
20196
/* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
20197
  {
20198
    { 0, 0, 0, 0 },
20199
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
20200
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1972600 }
20201
  },
20202
/* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
20203
  {
20204
    { 0, 0, 0, 0 },
20205
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
20206
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1973600 }
20207
  },
20208
/* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
20209
  {
20210
    { 0, 0, 0, 0 },
20211
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
20212
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x1938600 }
20213
  },
20214
/* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
20215
  {
20216
    { 0, 0, 0, 0 },
20217
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
20218
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x193a600 }
20219
  },
20220
/* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
20221
  {
20222
    { 0, 0, 0, 0 },
20223
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
20224
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x193b600 }
20225
  },
20226
/* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
20227
  {
20228
    { 0, 0, 0, 0 },
20229
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
20230
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x1958600 }
20231
  },
20232
/* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
20233
  {
20234
    { 0, 0, 0, 0 },
20235
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
20236
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x195a600 }
20237
  },
20238
/* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
20239
  {
20240
    { 0, 0, 0, 0 },
20241
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
20242
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x195b600 }
20243
  },
20244
/* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
20245
  {
20246
    { 0, 0, 0, 0 },
20247
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
20248
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193c600 }
20249
  },
20250
/* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
20251
  {
20252
    { 0, 0, 0, 0 },
20253
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
20254
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193e600 }
20255
  },
20256
/* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
20257
  {
20258
    { 0, 0, 0, 0 },
20259
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
20260
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193f600 }
20261
  },
20262
/* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
20263
  {
20264
    { 0, 0, 0, 0 },
20265
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
20266
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195c600 }
20267
  },
20268
/* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
20269
  {
20270
    { 0, 0, 0, 0 },
20271
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
20272
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195e600 }
20273
  },
20274
/* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
20275
  {
20276
    { 0, 0, 0, 0 },
20277
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
20278
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195f600 }
20279
  },
20280
/* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
20281
  {
20282
    { 0, 0, 0, 0 },
20283
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
20284
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197c600 }
20285
  },
20286
/* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
20287
  {
20288
    { 0, 0, 0, 0 },
20289
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
20290
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197e600 }
20291
  },
20292
/* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
20293
  {
20294
    { 0, 0, 0, 0 },
20295
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
20296
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197f600 }
20297
  },
20298
/* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
20299
  {
20300
    { 0, 0, 0, 0 },
20301
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
20302
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x1978600 }
20303
  },
20304
/* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
20305
  {
20306
    { 0, 0, 0, 0 },
20307
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
20308
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x197a600 }
20309
  },
20310
/* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
20311
  {
20312
    { 0, 0, 0, 0 },
20313
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
20314
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x197b600 }
20315
  },
20316
/* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
20317
  {
20318
    { 0, 0, 0, 0 },
20319
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
20320
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a90600 }
20321
  },
20322
/* sbb.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
20323
  {
20324
    { 0, 0, 0, 0 },
20325
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
20326
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a92600 }
20327
  },
20328
/* sbb.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
20329
  {
20330
    { 0, 0, 0, 0 },
20331
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
20332
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a93600 }
20333
  },
20334
/* sbb.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */
20335
  {
20336
    { 0, 0, 0, 0 },
20337
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32RNPREFIXEDHI), 0 } },
20338
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b93600 }
20339
  },
20340
/* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
20341
  {
20342
    { 0, 0, 0, 0 },
20343
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
20344
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a18600 }
20345
  },
20346
/* sbb.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
20347
  {
20348
    { 0, 0, 0, 0 },
20349
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
20350
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a1a600 }
20351
  },
20352
/* sbb.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
20353
  {
20354
    { 0, 0, 0, 0 },
20355
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
20356
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a1b600 }
20357
  },
20358
/* sbb.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */
20359
  {
20360
    { 0, 0, 0, 0 },
20361
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32ANPREFIXEDHI), 0 } },
20362
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b1b600 }
20363
  },
20364
/* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
20365
  {
20366
    { 0, 0, 0, 0 },
20367
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
20368
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a10600 }
20369
  },
20370
/* sbb.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
20371
  {
20372
    { 0, 0, 0, 0 },
20373
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
20374
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a12600 }
20375
  },
20376
/* sbb.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
20377
  {
20378
    { 0, 0, 0, 0 },
20379
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
20380
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a13600 }
20381
  },
20382
/* sbb.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
20383
  {
20384
    { 0, 0, 0, 0 },
20385
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
20386
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b13600 }
20387
  },
20388
/* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
20389
  {
20390
    { 0, 0, 0, 0 },
20391
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
20392
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a30600 }
20393
  },
20394
/* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
20395
  {
20396
    { 0, 0, 0, 0 },
20397
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
20398
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a32600 }
20399
  },
20400
/* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
20401
  {
20402
    { 0, 0, 0, 0 },
20403
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
20404
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a33600 }
20405
  },
20406
/* sbb.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
20407
  {
20408
    { 0, 0, 0, 0 },
20409
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
20410
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1b33600 }
20411
  },
20412
/* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
20413
  {
20414
    { 0, 0, 0, 0 },
20415
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
20416
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a50600 }
20417
  },
20418
/* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
20419
  {
20420
    { 0, 0, 0, 0 },
20421
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
20422
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a52600 }
20423
  },
20424
/* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
20425
  {
20426
    { 0, 0, 0, 0 },
20427
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
20428
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a53600 }
20429
  },
20430
/* sbb.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
20431
  {
20432
    { 0, 0, 0, 0 },
20433
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
20434
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1b53600 }
20435
  },
20436
/* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
20437
  {
20438
    { 0, 0, 0, 0 },
20439
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
20440
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a70600 }
20441
  },
20442
/* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
20443
  {
20444
    { 0, 0, 0, 0 },
20445
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
20446
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a72600 }
20447
  },
20448
/* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
20449
  {
20450
    { 0, 0, 0, 0 },
20451
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
20452
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a73600 }
20453
  },
20454
/* sbb.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
20455
  {
20456
    { 0, 0, 0, 0 },
20457
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
20458
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1b73600 }
20459
  },
20460
/* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
20461
  {
20462
    { 0, 0, 0, 0 },
20463
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
20464
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a38600 }
20465
  },
20466
/* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
20467
  {
20468
    { 0, 0, 0, 0 },
20469
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
20470
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a3a600 }
20471
  },
20472
/* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
20473
  {
20474
    { 0, 0, 0, 0 },
20475
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
20476
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a3b600 }
20477
  },
20478
/* sbb.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
20479
  {
20480
    { 0, 0, 0, 0 },
20481
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
20482
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1b3b600 }
20483
  },
20484
/* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
20485
  {
20486
    { 0, 0, 0, 0 },
20487
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
20488
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a58600 }
20489
  },
20490
/* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
20491
  {
20492
    { 0, 0, 0, 0 },
20493
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
20494
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a5a600 }
20495
  },
20496
/* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
20497
  {
20498
    { 0, 0, 0, 0 },
20499
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
20500
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a5b600 }
20501
  },
20502
/* sbb.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
20503
  {
20504
    { 0, 0, 0, 0 },
20505
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
20506
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1b5b600 }
20507
  },
20508
/* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
20509
  {
20510
    { 0, 0, 0, 0 },
20511
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
20512
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3c600 }
20513
  },
20514
/* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
20515
  {
20516
    { 0, 0, 0, 0 },
20517
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
20518
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3e600 }
20519
  },
20520
/* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
20521
  {
20522
    { 0, 0, 0, 0 },
20523
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
20524
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3f600 }
20525
  },
20526
/* sbb.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
20527
  {
20528
    { 0, 0, 0, 0 },
20529
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
20530
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1b3f600 }
20531
  },
20532
/* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
20533
  {
20534
    { 0, 0, 0, 0 },
20535
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
20536
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5c600 }
20537
  },
20538
/* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
20539
  {
20540
    { 0, 0, 0, 0 },
20541
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
20542
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5e600 }
20543
  },
20544
/* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
20545
  {
20546
    { 0, 0, 0, 0 },
20547
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
20548
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5f600 }
20549
  },
20550
/* sbb.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
20551
  {
20552
    { 0, 0, 0, 0 },
20553
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
20554
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1b5f600 }
20555
  },
20556
/* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
20557
  {
20558
    { 0, 0, 0, 0 },
20559
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
20560
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7c600 }
20561
  },
20562
/* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
20563
  {
20564
    { 0, 0, 0, 0 },
20565
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), 0 } },
20566
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7e600 }
20567
  },
20568
/* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
20569
  {
20570
    { 0, 0, 0, 0 },
20571
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), 0 } },
20572
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7f600 }
20573
  },
20574
/* sbb.w${X} ${Dsp-24-u16},${Dsp-40-u16} */
20575
  {
20576
    { 0, 0, 0, 0 },
20577
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), 0 } },
20578
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1b7f600 }
20579
  },
20580
/* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
20581
  {
20582
    { 0, 0, 0, 0 },
20583
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
20584
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a78600 }
20585
  },
20586
/* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
20587
  {
20588
    { 0, 0, 0, 0 },
20589
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), 0 } },
20590
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a7a600 }
20591
  },
20592
/* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
20593
  {
20594
    { 0, 0, 0, 0 },
20595
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), 0 } },
20596
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a7b600 }
20597
  },
20598
/* sbb.w${X} ${Dsp-24-u16},${Dsp-40-u24} */
20599
  {
20600
    { 0, 0, 0, 0 },
20601
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), 0 } },
20602
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1b7b600 }
20603
  },
20604
/* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
20605
  {
20606
    { 0, 0, 0, 0 },
20607
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
20608
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b90600 }
20609
  },
20610
/* sbb.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */
20611
  {
20612
    { 0, 0, 0, 0 },
20613
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32RNPREFIXEDHI), 0 } },
20614
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b92600 }
20615
  },
20616
/* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
20617
  {
20618
    { 0, 0, 0, 0 },
20619
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
20620
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b18600 }
20621
  },
20622
/* sbb.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */
20623
  {
20624
    { 0, 0, 0, 0 },
20625
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32ANPREFIXEDHI), 0 } },
20626
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b1a600 }
20627
  },
20628
/* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
20629
  {
20630
    { 0, 0, 0, 0 },
20631
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
20632
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b10600 }
20633
  },
20634
/* sbb.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
20635
  {
20636
    { 0, 0, 0, 0 },
20637
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
20638
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b12600 }
20639
  },
20640
/* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
20641
  {
20642
    { 0, 0, 0, 0 },
20643
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
20644
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b30600 }
20645
  },
20646
/* sbb.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
20647
  {
20648
    { 0, 0, 0, 0 },
20649
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
20650
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b32600 }
20651
  },
20652
/* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
20653
  {
20654
    { 0, 0, 0, 0 },
20655
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
20656
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b50600 }
20657
  },
20658
/* sbb.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
20659
  {
20660
    { 0, 0, 0, 0 },
20661
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
20662
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b52600 }
20663
  },
20664
/* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
20665
  {
20666
    { 0, 0, 0, 0 },
20667
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
20668
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b70600 }
20669
  },
20670
/* sbb.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
20671
  {
20672
    { 0, 0, 0, 0 },
20673
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
20674
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b72600 }
20675
  },
20676
/* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
20677
  {
20678
    { 0, 0, 0, 0 },
20679
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
20680
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b38600 }
20681
  },
20682
/* sbb.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
20683
  {
20684
    { 0, 0, 0, 0 },
20685
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
20686
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b3a600 }
20687
  },
20688
/* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
20689
  {
20690
    { 0, 0, 0, 0 },
20691
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
20692
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b58600 }
20693
  },
20694
/* sbb.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
20695
  {
20696
    { 0, 0, 0, 0 },
20697
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
20698
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b5a600 }
20699
  },
20700
/* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
20701
  {
20702
    { 0, 0, 0, 0 },
20703
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
20704
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b3c600 }
20705
  },
20706
/* sbb.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
20707
  {
20708
    { 0, 0, 0, 0 },
20709
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
20710
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b3e600 }
20711
  },
20712
/* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
20713
  {
20714
    { 0, 0, 0, 0 },
20715
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
20716
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b5c600 }
20717
  },
20718
/* sbb.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
20719
  {
20720
    { 0, 0, 0, 0 },
20721
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
20722
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b5e600 }
20723
  },
20724
/* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
20725
  {
20726
    { 0, 0, 0, 0 },
20727
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), 0 } },
20728
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_absolute_Prefixed_HI, { 0x1b7c600 }
20729
  },
20730
/* sbb.w${X} ${Dsp-24-u24},${Dsp-48-u16} */
20731
  {
20732
    { 0, 0, 0, 0 },
20733
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), 0 } },
20734
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_absolute_Prefixed_HI, { 0x1b7e600 }
20735
  },
20736
/* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
20737
  {
20738
    { 0, 0, 0, 0 },
20739
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), 0 } },
20740
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_24_absolute_Prefixed_HI, { 0x1b78600 }
20741
  },
20742
/* sbb.w${X} ${Dsp-24-u24},${Dsp-48-u24} */
20743
  {
20744
    { 0, 0, 0, 0 },
20745
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), 0 } },
20746
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_24_absolute_Prefixed_HI, { 0x1b7a600 }
20747
  },
20748
/* sbb.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */
20749
  {
20750
    { 0, 0, 0, 0 },
20751
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DST32RNPREFIXEDHI), 0 } },
20752
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1c906 }
20753
  },
20754
/* sbb.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */
20755
  {
20756
    { 0, 0, 0, 0 },
20757
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DST32RNPREFIXEDHI), 0 } },
20758
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x18926 }
20759
  },
20760
/* sbb.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */
20761
  {
20762
    { 0, 0, 0, 0 },
20763
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
20764
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x18906 }
20765
  },
20766
/* sbb.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */
20767
  {
20768
    { 0, 0, 0, 0 },
20769
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DST32ANPREFIXEDHI), 0 } },
20770
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1c186 }
20771
  },
20772
/* sbb.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */
20773
  {
20774
    { 0, 0, 0, 0 },
20775
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DST32ANPREFIXEDHI), 0 } },
20776
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x181a6 }
20777
  },
20778
/* sbb.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */
20779
  {
20780
    { 0, 0, 0, 0 },
20781
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
20782
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x18186 }
20783
  },
20784
/* sbb.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */
20785
  {
20786
    { 0, 0, 0, 0 },
20787
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
20788
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1c106 }
20789
  },
20790
/* sbb.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */
20791
  {
20792
    { 0, 0, 0, 0 },
20793
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
20794
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x18126 }
20795
  },
20796
/* sbb.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
20797
  {
20798
    { 0, 0, 0, 0 },
20799
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
20800
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x18106 }
20801
  },
20802
/* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
20803
  {
20804
    { 0, 0, 0, 0 },
20805
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
20806
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1c30600 }
20807
  },
20808
/* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
20809
  {
20810
    { 0, 0, 0, 0 },
20811
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
20812
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1832600 }
20813
  },
20814
/* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
20815
  {
20816
    { 0, 0, 0, 0 },
20817
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
20818
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1830600 }
20819
  },
20820
/* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
20821
  {
20822
    { 0, 0, 0, 0 },
20823
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
20824
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1c50600 }
20825
  },
20826
/* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
20827
  {
20828
    { 0, 0, 0, 0 },
20829
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
20830
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1852600 }
20831
  },
20832
/* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
20833
  {
20834
    { 0, 0, 0, 0 },
20835
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
20836
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1850600 }
20837
  },
20838
/* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
20839
  {
20840
    { 0, 0, 0, 0 },
20841
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
20842
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1c70600 }
20843
  },
20844
/* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
20845
  {
20846
    { 0, 0, 0, 0 },
20847
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
20848
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1872600 }
20849
  },
20850
/* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
20851
  {
20852
    { 0, 0, 0, 0 },
20853
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
20854
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1870600 }
20855
  },
20856
/* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */
20857
  {
20858
    { 0, 0, 0, 0 },
20859
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
20860
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1c38600 }
20861
  },
20862
/* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */
20863
  {
20864
    { 0, 0, 0, 0 },
20865
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
20866
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x183a600 }
20867
  },
20868
/* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
20869
  {
20870
    { 0, 0, 0, 0 },
20871
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
20872
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1838600 }
20873
  },
20874
/* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */
20875
  {
20876
    { 0, 0, 0, 0 },
20877
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
20878
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1c58600 }
20879
  },
20880
/* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */
20881
  {
20882
    { 0, 0, 0, 0 },
20883
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
20884
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x185a600 }
20885
  },
20886
/* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
20887
  {
20888
    { 0, 0, 0, 0 },
20889
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
20890
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1858600 }
20891
  },
20892
/* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */
20893
  {
20894
    { 0, 0, 0, 0 },
20895
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
20896
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x1c3c600 }
20897
  },
20898
/* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */
20899
  {
20900
    { 0, 0, 0, 0 },
20901
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
20902
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x183e600 }
20903
  },
20904
/* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
20905
  {
20906
    { 0, 0, 0, 0 },
20907
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
20908
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x183c600 }
20909
  },
20910
/* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */
20911
  {
20912
    { 0, 0, 0, 0 },
20913
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
20914
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x1c5c600 }
20915
  },
20916
/* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */
20917
  {
20918
    { 0, 0, 0, 0 },
20919
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
20920
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x185e600 }
20921
  },
20922
/* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
20923
  {
20924
    { 0, 0, 0, 0 },
20925
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
20926
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x185c600 }
20927
  },
20928
/* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */
20929
  {
20930
    { 0, 0, 0, 0 },
20931
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), 0 } },
20932
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x1c7c600 }
20933
  },
20934
/* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */
20935
  {
20936
    { 0, 0, 0, 0 },
20937
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), 0 } },
20938
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x187e600 }
20939
  },
20940
/* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */
20941
  {
20942
    { 0, 0, 0, 0 },
20943
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
20944
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x187c600 }
20945
  },
20946
/* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */
20947
  {
20948
    { 0, 0, 0, 0 },
20949
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U24), 0 } },
20950
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x1c78600 }
20951
  },
20952
/* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */
20953
  {
20954
    { 0, 0, 0, 0 },
20955
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U24), 0 } },
20956
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x187a600 }
20957
  },
20958
/* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */
20959
  {
20960
    { 0, 0, 0, 0 },
20961
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
20962
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x1878600 }
20963
  },
20964
/* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
20965
  {
20966
    { 0, 0, 0, 0 },
20967
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
20968
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1980600 }
20969
  },
20970
/* sbb.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */
20971
  {
20972
    { 0, 0, 0, 0 },
20973
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
20974
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1982600 }
20975
  },
20976
/* sbb.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */
20977
  {
20978
    { 0, 0, 0, 0 },
20979
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
20980
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1983600 }
20981
  },
20982
/* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
20983
  {
20984
    { 0, 0, 0, 0 },
20985
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
20986
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1908600 }
20987
  },
20988
/* sbb.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */
20989
  {
20990
    { 0, 0, 0, 0 },
20991
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
20992
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x190a600 }
20993
  },
20994
/* sbb.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */
20995
  {
20996
    { 0, 0, 0, 0 },
20997
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
20998
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x190b600 }
20999
  },
21000
/* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
21001
  {
21002
    { 0, 0, 0, 0 },
21003
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
21004
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1900600 }
21005
  },
21006
/* sbb.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
21007
  {
21008
    { 0, 0, 0, 0 },
21009
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
21010
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1902600 }
21011
  },
21012
/* sbb.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
21013
  {
21014
    { 0, 0, 0, 0 },
21015
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
21016
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1903600 }
21017
  },
21018
/* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
21019
  {
21020
    { 0, 0, 0, 0 },
21021
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
21022
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1920600 }
21023
  },
21024
/* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
21025
  {
21026
    { 0, 0, 0, 0 },
21027
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
21028
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1922600 }
21029
  },
21030
/* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
21031
  {
21032
    { 0, 0, 0, 0 },
21033
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
21034
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1923600 }
21035
  },
21036
/* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
21037
  {
21038
    { 0, 0, 0, 0 },
21039
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
21040
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1940600 }
21041
  },
21042
/* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
21043
  {
21044
    { 0, 0, 0, 0 },
21045
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
21046
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1942600 }
21047
  },
21048
/* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
21049
  {
21050
    { 0, 0, 0, 0 },
21051
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
21052
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1943600 }
21053
  },
21054
/* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
21055
  {
21056
    { 0, 0, 0, 0 },
21057
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
21058
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1960600 }
21059
  },
21060
/* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
21061
  {
21062
    { 0, 0, 0, 0 },
21063
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
21064
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1962600 }
21065
  },
21066
/* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
21067
  {
21068
    { 0, 0, 0, 0 },
21069
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
21070
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1963600 }
21071
  },
21072
/* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
21073
  {
21074
    { 0, 0, 0, 0 },
21075
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
21076
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x1928600 }
21077
  },
21078
/* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
21079
  {
21080
    { 0, 0, 0, 0 },
21081
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
21082
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x192a600 }
21083
  },
21084
/* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
21085
  {
21086
    { 0, 0, 0, 0 },
21087
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
21088
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x192b600 }
21089
  },
21090
/* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
21091
  {
21092
    { 0, 0, 0, 0 },
21093
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
21094
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x1948600 }
21095
  },
21096
/* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
21097
  {
21098
    { 0, 0, 0, 0 },
21099
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
21100
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x194a600 }
21101
  },
21102
/* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
21103
  {
21104
    { 0, 0, 0, 0 },
21105
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
21106
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x194b600 }
21107
  },
21108
/* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
21109
  {
21110
    { 0, 0, 0, 0 },
21111
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
21112
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192c600 }
21113
  },
21114
/* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
21115
  {
21116
    { 0, 0, 0, 0 },
21117
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
21118
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192e600 }
21119
  },
21120
/* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
21121
  {
21122
    { 0, 0, 0, 0 },
21123
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
21124
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192f600 }
21125
  },
21126
/* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
21127
  {
21128
    { 0, 0, 0, 0 },
21129
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
21130
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194c600 }
21131
  },
21132
/* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
21133
  {
21134
    { 0, 0, 0, 0 },
21135
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
21136
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194e600 }
21137
  },
21138
/* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
21139
  {
21140
    { 0, 0, 0, 0 },
21141
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
21142
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194f600 }
21143
  },
21144
/* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
21145
  {
21146
    { 0, 0, 0, 0 },
21147
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
21148
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196c600 }
21149
  },
21150
/* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
21151
  {
21152
    { 0, 0, 0, 0 },
21153
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
21154
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196e600 }
21155
  },
21156
/* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
21157
  {
21158
    { 0, 0, 0, 0 },
21159
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
21160
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196f600 }
21161
  },
21162
/* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
21163
  {
21164
    { 0, 0, 0, 0 },
21165
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
21166
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x1968600 }
21167
  },
21168
/* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
21169
  {
21170
    { 0, 0, 0, 0 },
21171
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
21172
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x196a600 }
21173
  },
21174
/* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
21175
  {
21176
    { 0, 0, 0, 0 },
21177
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
21178
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x196b600 }
21179
  },
21180
/* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
21181
  {
21182
    { 0, 0, 0, 0 },
21183
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
21184
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a80600 }
21185
  },
21186
/* sbb.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */
21187
  {
21188
    { 0, 0, 0, 0 },
21189
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
21190
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a82600 }
21191
  },
21192
/* sbb.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */
21193
  {
21194
    { 0, 0, 0, 0 },
21195
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
21196
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a83600 }
21197
  },
21198
/* sbb.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */
21199
  {
21200
    { 0, 0, 0, 0 },
21201
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32RNPREFIXEDQI), 0 } },
21202
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b83600 }
21203
  },
21204
/* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
21205
  {
21206
    { 0, 0, 0, 0 },
21207
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
21208
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a08600 }
21209
  },
21210
/* sbb.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */
21211
  {
21212
    { 0, 0, 0, 0 },
21213
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
21214
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a0a600 }
21215
  },
21216
/* sbb.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */
21217
  {
21218
    { 0, 0, 0, 0 },
21219
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
21220
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a0b600 }
21221
  },
21222
/* sbb.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */
21223
  {
21224
    { 0, 0, 0, 0 },
21225
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32ANPREFIXEDQI), 0 } },
21226
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b0b600 }
21227
  },
21228
/* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
21229
  {
21230
    { 0, 0, 0, 0 },
21231
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
21232
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a00600 }
21233
  },
21234
/* sbb.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
21235
  {
21236
    { 0, 0, 0, 0 },
21237
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
21238
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a02600 }
21239
  },
21240
/* sbb.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
21241
  {
21242
    { 0, 0, 0, 0 },
21243
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
21244
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a03600 }
21245
  },
21246
/* sbb.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
21247
  {
21248
    { 0, 0, 0, 0 },
21249
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
21250
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b03600 }
21251
  },
21252
/* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
21253
  {
21254
    { 0, 0, 0, 0 },
21255
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
21256
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a20600 }
21257
  },
21258
/* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
21259
  {
21260
    { 0, 0, 0, 0 },
21261
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
21262
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a22600 }
21263
  },
21264
/* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
21265
  {
21266
    { 0, 0, 0, 0 },
21267
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
21268
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a23600 }
21269
  },
21270
/* sbb.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
21271
  {
21272
    { 0, 0, 0, 0 },
21273
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
21274
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1b23600 }
21275
  },
21276
/* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
21277
  {
21278
    { 0, 0, 0, 0 },
21279
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
21280
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a40600 }
21281
  },
21282
/* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
21283
  {
21284
    { 0, 0, 0, 0 },
21285
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
21286
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a42600 }
21287
  },
21288
/* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
21289
  {
21290
    { 0, 0, 0, 0 },
21291
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
21292
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a43600 }
21293
  },
21294
/* sbb.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
21295
  {
21296
    { 0, 0, 0, 0 },
21297
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
21298
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1b43600 }
21299
  },
21300
/* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
21301
  {
21302
    { 0, 0, 0, 0 },
21303
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
21304
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a60600 }
21305
  },
21306
/* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
21307
  {
21308
    { 0, 0, 0, 0 },
21309
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
21310
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a62600 }
21311
  },
21312
/* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
21313
  {
21314
    { 0, 0, 0, 0 },
21315
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
21316
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a63600 }
21317
  },
21318
/* sbb.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
21319
  {
21320
    { 0, 0, 0, 0 },
21321
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
21322
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1b63600 }
21323
  },
21324
/* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
21325
  {
21326
    { 0, 0, 0, 0 },
21327
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
21328
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a28600 }
21329
  },
21330
/* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
21331
  {
21332
    { 0, 0, 0, 0 },
21333
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
21334
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a2a600 }
21335
  },
21336
/* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
21337
  {
21338
    { 0, 0, 0, 0 },
21339
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
21340
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a2b600 }
21341
  },
21342
/* sbb.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
21343
  {
21344
    { 0, 0, 0, 0 },
21345
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
21346
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1b2b600 }
21347
  },
21348
/* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
21349
  {
21350
    { 0, 0, 0, 0 },
21351
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
21352
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a48600 }
21353
  },
21354
/* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
21355
  {
21356
    { 0, 0, 0, 0 },
21357
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
21358
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a4a600 }
21359
  },
21360
/* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
21361
  {
21362
    { 0, 0, 0, 0 },
21363
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
21364
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a4b600 }
21365
  },
21366
/* sbb.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
21367
  {
21368
    { 0, 0, 0, 0 },
21369
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
21370
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1b4b600 }
21371
  },
21372
/* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
21373
  {
21374
    { 0, 0, 0, 0 },
21375
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
21376
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2c600 }
21377
  },
21378
/* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
21379
  {
21380
    { 0, 0, 0, 0 },
21381
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
21382
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2e600 }
21383
  },
21384
/* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
21385
  {
21386
    { 0, 0, 0, 0 },
21387
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
21388
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2f600 }
21389
  },
21390
/* sbb.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
21391
  {
21392
    { 0, 0, 0, 0 },
21393
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
21394
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1b2f600 }
21395
  },
21396
/* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
21397
  {
21398
    { 0, 0, 0, 0 },
21399
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
21400
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4c600 }
21401
  },
21402
/* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
21403
  {
21404
    { 0, 0, 0, 0 },
21405
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
21406
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4e600 }
21407
  },
21408
/* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
21409
  {
21410
    { 0, 0, 0, 0 },
21411
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
21412
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4f600 }
21413
  },
21414
/* sbb.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
21415
  {
21416
    { 0, 0, 0, 0 },
21417
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
21418
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1b4f600 }
21419
  },
21420
/* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
21421
  {
21422
    { 0, 0, 0, 0 },
21423
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
21424
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6c600 }
21425
  },
21426
/* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
21427
  {
21428
    { 0, 0, 0, 0 },
21429
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), 0 } },
21430
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6e600 }
21431
  },
21432
/* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
21433
  {
21434
    { 0, 0, 0, 0 },
21435
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), 0 } },
21436
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6f600 }
21437
  },
21438
/* sbb.b${X} ${Dsp-24-u16},${Dsp-40-u16} */
21439
  {
21440
    { 0, 0, 0, 0 },
21441
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), 0 } },
21442
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1b6f600 }
21443
  },
21444
/* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
21445
  {
21446
    { 0, 0, 0, 0 },
21447
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
21448
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a68600 }
21449
  },
21450
/* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
21451
  {
21452
    { 0, 0, 0, 0 },
21453
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), 0 } },
21454
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a6a600 }
21455
  },
21456
/* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
21457
  {
21458
    { 0, 0, 0, 0 },
21459
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), 0 } },
21460
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a6b600 }
21461
  },
21462
/* sbb.b${X} ${Dsp-24-u16},${Dsp-40-u24} */
21463
  {
21464
    { 0, 0, 0, 0 },
21465
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), 0 } },
21466
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1b6b600 }
21467
  },
21468
/* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
21469
  {
21470
    { 0, 0, 0, 0 },
21471
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
21472
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b80600 }
21473
  },
21474
/* sbb.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */
21475
  {
21476
    { 0, 0, 0, 0 },
21477
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32RNPREFIXEDQI), 0 } },
21478
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b82600 }
21479
  },
21480
/* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
21481
  {
21482
    { 0, 0, 0, 0 },
21483
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
21484
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b08600 }
21485
  },
21486
/* sbb.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */
21487
  {
21488
    { 0, 0, 0, 0 },
21489
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32ANPREFIXEDQI), 0 } },
21490
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b0a600 }
21491
  },
21492
/* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
21493
  {
21494
    { 0, 0, 0, 0 },
21495
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
21496
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b00600 }
21497
  },
21498
/* sbb.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
21499
  {
21500
    { 0, 0, 0, 0 },
21501
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
21502
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b02600 }
21503
  },
21504
/* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
21505
  {
21506
    { 0, 0, 0, 0 },
21507
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
21508
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_An_relative_Prefixed_QI, { 0x1b20600 }
21509
  },
21510
/* sbb.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
21511
  {
21512
    { 0, 0, 0, 0 },
21513
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
21514
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_An_relative_Prefixed_QI, { 0x1b22600 }
21515
  },
21516
/* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
21517
  {
21518
    { 0, 0, 0, 0 },
21519
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
21520
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_An_relative_Prefixed_QI, { 0x1b40600 }
21521
  },
21522
/* sbb.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
21523
  {
21524
    { 0, 0, 0, 0 },
21525
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
21526
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_An_relative_Prefixed_QI, { 0x1b42600 }
21527
  },
21528
/* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
21529
  {
21530
    { 0, 0, 0, 0 },
21531
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
21532
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_An_relative_Prefixed_QI, { 0x1b60600 }
21533
  },
21534
/* sbb.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
21535
  {
21536
    { 0, 0, 0, 0 },
21537
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
21538
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_An_relative_Prefixed_QI, { 0x1b62600 }
21539
  },
21540
/* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
21541
  {
21542
    { 0, 0, 0, 0 },
21543
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
21544
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_QI, { 0x1b28600 }
21545
  },
21546
/* sbb.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
21547
  {
21548
    { 0, 0, 0, 0 },
21549
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
21550
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_QI, { 0x1b2a600 }
21551
  },
21552
/* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
21553
  {
21554
    { 0, 0, 0, 0 },
21555
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
21556
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_QI, { 0x1b48600 }
21557
  },
21558
/* sbb.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
21559
  {
21560
    { 0, 0, 0, 0 },
21561
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
21562
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_QI, { 0x1b4a600 }
21563
  },
21564
/* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
21565
  {
21566
    { 0, 0, 0, 0 },
21567
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
21568
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_QI, { 0x1b2c600 }
21569
  },
21570
/* sbb.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
21571
  {
21572
    { 0, 0, 0, 0 },
21573
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
21574
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_QI, { 0x1b2e600 }
21575
  },
21576
/* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
21577
  {
21578
    { 0, 0, 0, 0 },
21579
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
21580
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_QI, { 0x1b4c600 }
21581
  },
21582
/* sbb.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
21583
  {
21584
    { 0, 0, 0, 0 },
21585
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
21586
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_QI, { 0x1b4e600 }
21587
  },
21588
/* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
21589
  {
21590
    { 0, 0, 0, 0 },
21591
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), 0 } },
21592
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_absolute_Prefixed_QI, { 0x1b6c600 }
21593
  },
21594
/* sbb.b${X} ${Dsp-24-u24},${Dsp-48-u16} */
21595
  {
21596
    { 0, 0, 0, 0 },
21597
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), 0 } },
21598
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_absolute_Prefixed_QI, { 0x1b6e600 }
21599
  },
21600
/* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
21601
  {
21602
    { 0, 0, 0, 0 },
21603
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), 0 } },
21604
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_absolute_Prefixed_QI, { 0x1b68600 }
21605
  },
21606
/* sbb.b${X} ${Dsp-24-u24},${Dsp-48-u24} */
21607
  {
21608
    { 0, 0, 0, 0 },
21609
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), 0 } },
21610
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_absolute_Prefixed_QI, { 0x1b6a600 }
21611
  },
21612
/* sbb.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */
21613
  {
21614
    { 0, 0, 0, 0 },
21615
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32RNPREFIXEDQI), 0 } },
21616
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1c806 }
21617
  },
21618
/* sbb.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */
21619
  {
21620
    { 0, 0, 0, 0 },
21621
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DST32RNPREFIXEDQI), 0 } },
21622
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x18826 }
21623
  },
21624
/* sbb.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */
21625
  {
21626
    { 0, 0, 0, 0 },
21627
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
21628
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x18806 }
21629
  },
21630
/* sbb.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */
21631
  {
21632
    { 0, 0, 0, 0 },
21633
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32ANPREFIXEDQI), 0 } },
21634
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1c086 }
21635
  },
21636
/* sbb.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */
21637
  {
21638
    { 0, 0, 0, 0 },
21639
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DST32ANPREFIXEDQI), 0 } },
21640
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x180a6 }
21641
  },
21642
/* sbb.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */
21643
  {
21644
    { 0, 0, 0, 0 },
21645
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
21646
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x18086 }
21647
  },
21648
/* sbb.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
21649
  {
21650
    { 0, 0, 0, 0 },
21651
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
21652
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1c006 }
21653
  },
21654
/* sbb.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */
21655
  {
21656
    { 0, 0, 0, 0 },
21657
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
21658
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x18026 }
21659
  },
21660
/* sbb.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
21661
  {
21662
    { 0, 0, 0, 0 },
21663
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
21664
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x18006 }
21665
  },
21666
/* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
21667
  {
21668
    { 0, 0, 0, 0 },
21669
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
21670
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1c20600 }
21671
  },
21672
/* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
21673
  {
21674
    { 0, 0, 0, 0 },
21675
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
21676
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1822600 }
21677
  },
21678
/* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
21679
  {
21680
    { 0, 0, 0, 0 },
21681
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
21682
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1820600 }
21683
  },
21684
/* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
21685
  {
21686
    { 0, 0, 0, 0 },
21687
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
21688
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1c40600 }
21689
  },
21690
/* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
21691
  {
21692
    { 0, 0, 0, 0 },
21693
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
21694
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1842600 }
21695
  },
21696
/* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
21697
  {
21698
    { 0, 0, 0, 0 },
21699
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
21700
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1840600 }
21701
  },
21702
/* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
21703
  {
21704
    { 0, 0, 0, 0 },
21705
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
21706
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1c60600 }
21707
  },
21708
/* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
21709
  {
21710
    { 0, 0, 0, 0 },
21711
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
21712
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1862600 }
21713
  },
21714
/* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
21715
  {
21716
    { 0, 0, 0, 0 },
21717
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
21718
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1860600 }
21719
  },
21720
/* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
21721
  {
21722
    { 0, 0, 0, 0 },
21723
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
21724
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x1c28600 }
21725
  },
21726
/* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */
21727
  {
21728
    { 0, 0, 0, 0 },
21729
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
21730
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x182a600 }
21731
  },
21732
/* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
21733
  {
21734
    { 0, 0, 0, 0 },
21735
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
21736
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x1828600 }
21737
  },
21738
/* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
21739
  {
21740
    { 0, 0, 0, 0 },
21741
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
21742
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x1c48600 }
21743
  },
21744
/* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */
21745
  {
21746
    { 0, 0, 0, 0 },
21747
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
21748
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x184a600 }
21749
  },
21750
/* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
21751
  {
21752
    { 0, 0, 0, 0 },
21753
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
21754
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x1848600 }
21755
  },
21756
/* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
21757
  {
21758
    { 0, 0, 0, 0 },
21759
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
21760
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x1c2c600 }
21761
  },
21762
/* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */
21763
  {
21764
    { 0, 0, 0, 0 },
21765
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
21766
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x182e600 }
21767
  },
21768
/* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
21769
  {
21770
    { 0, 0, 0, 0 },
21771
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
21772
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x182c600 }
21773
  },
21774
/* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
21775
  {
21776
    { 0, 0, 0, 0 },
21777
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
21778
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x1c4c600 }
21779
  },
21780
/* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */
21781
  {
21782
    { 0, 0, 0, 0 },
21783
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
21784
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x184e600 }
21785
  },
21786
/* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
21787
  {
21788
    { 0, 0, 0, 0 },
21789
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
21790
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x184c600 }
21791
  },
21792
/* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */
21793
  {
21794
    { 0, 0, 0, 0 },
21795
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), 0 } },
21796
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x1c6c600 }
21797
  },
21798
/* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */
21799
  {
21800
    { 0, 0, 0, 0 },
21801
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), 0 } },
21802
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x186e600 }
21803
  },
21804
/* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */
21805
  {
21806
    { 0, 0, 0, 0 },
21807
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
21808
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x186c600 }
21809
  },
21810
/* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */
21811
  {
21812
    { 0, 0, 0, 0 },
21813
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), 0 } },
21814
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x1c68600 }
21815
  },
21816
/* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */
21817
  {
21818
    { 0, 0, 0, 0 },
21819
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U24), 0 } },
21820
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x186a600 }
21821
  },
21822
/* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */
21823
  {
21824
    { 0, 0, 0, 0 },
21825
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
21826
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x1868600 }
21827
  },
21828
/* sbb.w${X} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
21829
  {
21830
    { 0, 0, 0, 0 },
21831
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } },
21832
    & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_Rn_direct_HI, { 0xb98000 }
21833
  },
21834
/* sbb.w${X} ${Dsp-16-u8}[sb],$Dst16RnHI */
21835
  {
21836
    { 0, 0, 0, 0 },
21837
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } },
21838
    & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_Rn_direct_HI, { 0xb9a000 }
21839
  },
21840
/* sbb.w${X} ${Dsp-16-s8}[fb],$Dst16RnHI */
21841
  {
21842
    { 0, 0, 0, 0 },
21843
    { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNHI), 0 } },
21844
    & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_Rn_direct_HI, { 0xb9b000 }
21845
  },
21846
/* sbb.w${X} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
21847
  {
21848
    { 0, 0, 0, 0 },
21849
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } },
21850
    & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_direct_HI, { 0xb98400 }
21851
  },
21852
/* sbb.w${X} ${Dsp-16-u8}[sb],$Dst16AnHI */
21853
  {
21854
    { 0, 0, 0, 0 },
21855
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } },
21856
    & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_direct_HI, { 0xb9a400 }
21857
  },
21858
/* sbb.w${X} ${Dsp-16-s8}[fb],$Dst16AnHI */
21859
  {
21860
    { 0, 0, 0, 0 },
21861
    { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANHI), 0 } },
21862
    & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_direct_HI, { 0xb9b400 }
21863
  },
21864
/* sbb.w${X} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
21865
  {
21866
    { 0, 0, 0, 0 },
21867
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
21868
    & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_indirect_HI, { 0xb98600 }
21869
  },
21870
/* sbb.w${X} ${Dsp-16-u8}[sb],[$Dst16An] */
21871
  {
21872
    { 0, 0, 0, 0 },
21873
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
21874
    & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_indirect_HI, { 0xb9a600 }
21875
  },
21876
/* sbb.w${X} ${Dsp-16-s8}[fb],[$Dst16An] */
21877
  {
21878
    { 0, 0, 0, 0 },
21879
    { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
21880
    & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_indirect_HI, { 0xb9b600 }
21881
  },
21882
/* sbb.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
21883
  {
21884
    { 0, 0, 0, 0 },
21885
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
21886
    & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_An_relative_HI, { 0xb9880000 }
21887
  },
21888
/* sbb.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
21889
  {
21890
    { 0, 0, 0, 0 },
21891
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
21892
    & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_An_relative_HI, { 0xb9a80000 }
21893
  },
21894
/* sbb.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
21895
  {
21896
    { 0, 0, 0, 0 },
21897
    { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
21898
    & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_An_relative_HI, { 0xb9b80000 }
21899
  },
21900
/* sbb.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
21901
  {
21902
    { 0, 0, 0, 0 },
21903
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
21904
    & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_An_relative_HI, { 0xb98c0000 }
21905
  },
21906
/* sbb.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
21907
  {
21908
    { 0, 0, 0, 0 },
21909
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
21910
    & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_An_relative_HI, { 0xb9ac0000 }
21911
  },
21912
/* sbb.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
21913
  {
21914
    { 0, 0, 0, 0 },
21915
    { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
21916
    & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_An_relative_HI, { 0xb9bc0000 }
21917
  },
21918
/* sbb.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
21919
  {
21920
    { 0, 0, 0, 0 },
21921
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
21922
    & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_SB_relative_HI, { 0xb98a0000 }
21923
  },
21924
/* sbb.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
21925
  {
21926
    { 0, 0, 0, 0 },
21927
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
21928
    & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_SB_relative_HI, { 0xb9aa0000 }
21929
  },
21930
/* sbb.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
21931
  {
21932
    { 0, 0, 0, 0 },
21933
    { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
21934
    & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_SB_relative_HI, { 0xb9ba0000 }
21935
  },
21936
/* sbb.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
21937
  {
21938
    { 0, 0, 0, 0 },
21939
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
21940
    & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_SB_relative_HI, { 0xb98e0000 }
21941
  },
21942
/* sbb.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
21943
  {
21944
    { 0, 0, 0, 0 },
21945
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
21946
    & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_SB_relative_HI, { 0xb9ae0000 }
21947
  },
21948
/* sbb.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
21949
  {
21950
    { 0, 0, 0, 0 },
21951
    { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
21952
    & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_SB_relative_HI, { 0xb9be0000 }
21953
  },
21954
/* sbb.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
21955
  {
21956
    { 0, 0, 0, 0 },
21957
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
21958
    & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_FB_relative_HI, { 0xb98b0000 }
21959
  },
21960
/* sbb.w${X} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
21961
  {
21962
    { 0, 0, 0, 0 },
21963
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
21964
    & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_FB_relative_HI, { 0xb9ab0000 }
21965
  },
21966
/* sbb.w${X} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
21967
  {
21968
    { 0, 0, 0, 0 },
21969
    { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
21970
    & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_FB_relative_HI, { 0xb9bb0000 }
21971
  },
21972
/* sbb.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
21973
  {
21974
    { 0, 0, 0, 0 },
21975
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } },
21976
    & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_absolute_HI, { 0xb98f0000 }
21977
  },
21978
/* sbb.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
21979
  {
21980
    { 0, 0, 0, 0 },
21981
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
21982
    & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_absolute_HI, { 0xb9af0000 }
21983
  },
21984
/* sbb.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
21985
  {
21986
    { 0, 0, 0, 0 },
21987
    { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
21988
    & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_absolute_HI, { 0xb9bf0000 }
21989
  },
21990
/* sbb.w${X} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
21991
  {
21992
    { 0, 0, 0, 0 },
21993
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } },
21994
    & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_Rn_direct_HI, { 0xb9c00000 }
21995
  },
21996
/* sbb.w${X} ${Dsp-16-u16}[sb],$Dst16RnHI */
21997
  {
21998
    { 0, 0, 0, 0 },
21999
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } },
22000
    & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_Rn_direct_HI, { 0xb9e00000 }
22001
  },
22002
/* sbb.w${X} ${Dsp-16-u16},$Dst16RnHI */
22003
  {
22004
    { 0, 0, 0, 0 },
22005
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DST16RNHI), 0 } },
22006
    & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_Rn_direct_HI, { 0xb9f00000 }
22007
  },
22008
/* sbb.w${X} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
22009
  {
22010
    { 0, 0, 0, 0 },
22011
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } },
22012
    & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_direct_HI, { 0xb9c40000 }
22013
  },
22014
/* sbb.w${X} ${Dsp-16-u16}[sb],$Dst16AnHI */
22015
  {
22016
    { 0, 0, 0, 0 },
22017
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } },
22018
    & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_direct_HI, { 0xb9e40000 }
22019
  },
22020
/* sbb.w${X} ${Dsp-16-u16},$Dst16AnHI */
22021
  {
22022
    { 0, 0, 0, 0 },
22023
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DST16ANHI), 0 } },
22024
    & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_direct_HI, { 0xb9f40000 }
22025
  },
22026
/* sbb.w${X} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
22027
  {
22028
    { 0, 0, 0, 0 },
22029
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
22030
    & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_indirect_HI, { 0xb9c60000 }
22031
  },
22032
/* sbb.w${X} ${Dsp-16-u16}[sb],[$Dst16An] */
22033
  {
22034
    { 0, 0, 0, 0 },
22035
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
22036
    & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_indirect_HI, { 0xb9e60000 }
22037
  },
22038
/* sbb.w${X} ${Dsp-16-u16},[$Dst16An] */
22039
  {
22040
    { 0, 0, 0, 0 },
22041
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } },
22042
    & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_indirect_HI, { 0xb9f60000 }
22043
  },
22044
/* sbb.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
22045
  {
22046
    { 0, 0, 0, 0 },
22047
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
22048
    & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_An_relative_HI, { 0xb9c80000 }
22049
  },
22050
/* sbb.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
22051
  {
22052
    { 0, 0, 0, 0 },
22053
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
22054
    & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_An_relative_HI, { 0xb9e80000 }
22055
  },
22056
/* sbb.w${X} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
22057
  {
22058
    { 0, 0, 0, 0 },
22059
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
22060
    & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_An_relative_HI, { 0xb9f80000 }
22061
  },
22062
/* sbb.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
22063
  {
22064
    { 0, 0, 0, 0 },
22065
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
22066
    & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_An_relative_HI, { 0xb9cc0000 }
22067
  },
22068
/* sbb.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
22069
  {
22070
    { 0, 0, 0, 0 },
22071
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
22072
    & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_An_relative_HI, { 0xb9ec0000 }
22073
  },
22074
/* sbb.w${X} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
22075
  {
22076
    { 0, 0, 0, 0 },
22077
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
22078
    & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_An_relative_HI, { 0xb9fc0000 }
22079
  },
22080
/* sbb.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
22081
  {
22082
    { 0, 0, 0, 0 },
22083
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
22084
    & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_SB_relative_HI, { 0xb9ca0000 }
22085
  },
22086
/* sbb.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
22087
  {
22088
    { 0, 0, 0, 0 },
22089
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
22090
    & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_SB_relative_HI, { 0xb9ea0000 }
22091
  },
22092
/* sbb.w${X} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
22093
  {
22094
    { 0, 0, 0, 0 },
22095
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
22096
    & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_SB_relative_HI, { 0xb9fa0000 }
22097
  },
22098
/* sbb.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
22099
  {
22100
    { 0, 0, 0, 0 },
22101
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
22102
    & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_SB_relative_HI, { 0xb9ce0000 }
22103
  },
22104
/* sbb.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
22105
  {
22106
    { 0, 0, 0, 0 },
22107
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
22108
    & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_SB_relative_HI, { 0xb9ee0000 }
22109
  },
22110
/* sbb.w${X} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
22111
  {
22112
    { 0, 0, 0, 0 },
22113
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
22114
    & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_SB_relative_HI, { 0xb9fe0000 }
22115
  },
22116
/* sbb.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
22117
  {
22118
    { 0, 0, 0, 0 },
22119
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
22120
    & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_FB_relative_HI, { 0xb9cb0000 }
22121
  },
22122
/* sbb.w${X} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
22123
  {
22124
    { 0, 0, 0, 0 },
22125
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
22126
    & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_FB_relative_HI, { 0xb9eb0000 }
22127
  },
22128
/* sbb.w${X} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
22129
  {
22130
    { 0, 0, 0, 0 },
22131
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
22132
    & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_FB_relative_HI, { 0xb9fb0000 }
22133
  },
22134
/* sbb.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
22135
  {
22136
    { 0, 0, 0, 0 },
22137
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } },
22138
    & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_absolute_HI, { 0xb9cf0000 }
22139
  },
22140
/* sbb.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
22141
  {
22142
    { 0, 0, 0, 0 },
22143
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
22144
    & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_absolute_HI, { 0xb9ef0000 }
22145
  },
22146
/* sbb.w${X} ${Dsp-16-u16},${Dsp-32-u16} */
22147
  {
22148
    { 0, 0, 0, 0 },
22149
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
22150
    & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_absolute_HI, { 0xb9ff0000 }
22151
  },
22152
/* sbb.w${X} $Src16RnHI,$Dst16RnHI */
22153
  {
22154
    { 0, 0, 0, 0 },
22155
    { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DST16RNHI), 0 } },
22156
    & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_Rn_direct_HI, { 0xb900 }
22157
  },
22158
/* sbb.w${X} $Src16AnHI,$Dst16RnHI */
22159
  {
22160
    { 0, 0, 0, 0 },
22161
    { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DST16RNHI), 0 } },
22162
    & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_Rn_direct_HI, { 0xb940 }
22163
  },
22164
/* sbb.w${X} [$Src16An],$Dst16RnHI */
22165
  {
22166
    { 0, 0, 0, 0 },
22167
    { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } },
22168
    & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_Rn_direct_HI, { 0xb960 }
22169
  },
22170
/* sbb.w${X} $Src16RnHI,$Dst16AnHI */
22171
  {
22172
    { 0, 0, 0, 0 },
22173
    { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DST16ANHI), 0 } },
22174
    & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_direct_HI, { 0xb904 }
22175
  },
22176
/* sbb.w${X} $Src16AnHI,$Dst16AnHI */
22177
  {
22178
    { 0, 0, 0, 0 },
22179
    { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DST16ANHI), 0 } },
22180
    & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_direct_HI, { 0xb944 }
22181
  },
22182
/* sbb.w${X} [$Src16An],$Dst16AnHI */
22183
  {
22184
    { 0, 0, 0, 0 },
22185
    { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } },
22186
    & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_direct_HI, { 0xb964 }
22187
  },
22188
/* sbb.w${X} $Src16RnHI,[$Dst16An] */
22189
  {
22190
    { 0, 0, 0, 0 },
22191
    { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', '[', OP (DST16AN), ']', 0 } },
22192
    & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_indirect_HI, { 0xb906 }
22193
  },
22194
/* sbb.w${X} $Src16AnHI,[$Dst16An] */
22195
  {
22196
    { 0, 0, 0, 0 },
22197
    { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', '[', OP (DST16AN), ']', 0 } },
22198
    & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_indirect_HI, { 0xb946 }
22199
  },
22200
/* sbb.w${X} [$Src16An],[$Dst16An] */
22201
  {
22202
    { 0, 0, 0, 0 },
22203
    { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
22204
    & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_indirect_HI, { 0xb966 }
22205
  },
22206
/* sbb.w${X} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
22207
  {
22208
    { 0, 0, 0, 0 },
22209
    { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
22210
    & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_An_relative_HI, { 0xb90800 }
22211
  },
22212
/* sbb.w${X} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
22213
  {
22214
    { 0, 0, 0, 0 },
22215
    { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
22216
    & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_An_relative_HI, { 0xb94800 }
22217
  },
22218
/* sbb.w${X} [$Src16An],${Dsp-16-u8}[$Dst16An] */
22219
  {
22220
    { 0, 0, 0, 0 },
22221
    { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
22222
    & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_An_relative_HI, { 0xb96800 }
22223
  },
22224
/* sbb.w${X} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
22225
  {
22226
    { 0, 0, 0, 0 },
22227
    { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
22228
    & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_An_relative_HI, { 0xb90c0000 }
22229
  },
22230
/* sbb.w${X} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
22231
  {
22232
    { 0, 0, 0, 0 },
22233
    { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
22234
    & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_An_relative_HI, { 0xb94c0000 }
22235
  },
22236
/* sbb.w${X} [$Src16An],${Dsp-16-u16}[$Dst16An] */
22237
  {
22238
    { 0, 0, 0, 0 },
22239
    { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
22240
    & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_An_relative_HI, { 0xb96c0000 }
22241
  },
22242
/* sbb.w${X} $Src16RnHI,${Dsp-16-u8}[sb] */
22243
  {
22244
    { 0, 0, 0, 0 },
22245
    { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
22246
    & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_SB_relative_HI, { 0xb90a00 }
22247
  },
22248
/* sbb.w${X} $Src16AnHI,${Dsp-16-u8}[sb] */
22249
  {
22250
    { 0, 0, 0, 0 },
22251
    { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
22252
    & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_SB_relative_HI, { 0xb94a00 }
22253
  },
22254
/* sbb.w${X} [$Src16An],${Dsp-16-u8}[sb] */
22255
  {
22256
    { 0, 0, 0, 0 },
22257
    { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
22258
    & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_SB_relative_HI, { 0xb96a00 }
22259
  },
22260
/* sbb.w${X} $Src16RnHI,${Dsp-16-u16}[sb] */
22261
  {
22262
    { 0, 0, 0, 0 },
22263
    { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
22264
    & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_SB_relative_HI, { 0xb90e0000 }
22265
  },
22266
/* sbb.w${X} $Src16AnHI,${Dsp-16-u16}[sb] */
22267
  {
22268
    { 0, 0, 0, 0 },
22269
    { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
22270
    & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_SB_relative_HI, { 0xb94e0000 }
22271
  },
22272
/* sbb.w${X} [$Src16An],${Dsp-16-u16}[sb] */
22273
  {
22274
    { 0, 0, 0, 0 },
22275
    { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
22276
    & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_SB_relative_HI, { 0xb96e0000 }
22277
  },
22278
/* sbb.w${X} $Src16RnHI,${Dsp-16-s8}[fb] */
22279
  {
22280
    { 0, 0, 0, 0 },
22281
    { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
22282
    & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_FB_relative_HI, { 0xb90b00 }
22283
  },
22284
/* sbb.w${X} $Src16AnHI,${Dsp-16-s8}[fb] */
22285
  {
22286
    { 0, 0, 0, 0 },
22287
    { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
22288
    & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_FB_relative_HI, { 0xb94b00 }
22289
  },
22290
/* sbb.w${X} [$Src16An],${Dsp-16-s8}[fb] */
22291
  {
22292
    { 0, 0, 0, 0 },
22293
    { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
22294
    & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_FB_relative_HI, { 0xb96b00 }
22295
  },
22296
/* sbb.w${X} $Src16RnHI,${Dsp-16-u16} */
22297
  {
22298
    { 0, 0, 0, 0 },
22299
    { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), 0 } },
22300
    & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_absolute_HI, { 0xb90f0000 }
22301
  },
22302
/* sbb.w${X} $Src16AnHI,${Dsp-16-u16} */
22303
  {
22304
    { 0, 0, 0, 0 },
22305
    { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), 0 } },
22306
    & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_absolute_HI, { 0xb94f0000 }
22307
  },
22308
/* sbb.w${X} [$Src16An],${Dsp-16-u16} */
22309
  {
22310
    { 0, 0, 0, 0 },
22311
    { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } },
22312
    & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_absolute_HI, { 0xb96f0000 }
22313
  },
22314
/* sbb.b${X} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
22315
  {
22316
    { 0, 0, 0, 0 },
22317
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } },
22318
    & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_Rn_direct_QI, { 0xb88000 }
22319
  },
22320
/* sbb.b${X} ${Dsp-16-u8}[sb],$Dst16RnQI */
22321
  {
22322
    { 0, 0, 0, 0 },
22323
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } },
22324
    & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_Rn_direct_QI, { 0xb8a000 }
22325
  },
22326
/* sbb.b${X} ${Dsp-16-s8}[fb],$Dst16RnQI */
22327
  {
22328
    { 0, 0, 0, 0 },
22329
    { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNQI), 0 } },
22330
    & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_Rn_direct_QI, { 0xb8b000 }
22331
  },
22332
/* sbb.b${X} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
22333
  {
22334
    { 0, 0, 0, 0 },
22335
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } },
22336
    & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_direct_QI, { 0xb88400 }
22337
  },
22338
/* sbb.b${X} ${Dsp-16-u8}[sb],$Dst16AnQI */
22339
  {
22340
    { 0, 0, 0, 0 },
22341
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } },
22342
    & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_direct_QI, { 0xb8a400 }
22343
  },
22344
/* sbb.b${X} ${Dsp-16-s8}[fb],$Dst16AnQI */
22345
  {
22346
    { 0, 0, 0, 0 },
22347
    { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANQI), 0 } },
22348
    & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_direct_QI, { 0xb8b400 }
22349
  },
22350
/* sbb.b${X} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
22351
  {
22352
    { 0, 0, 0, 0 },
22353
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
22354
    & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_indirect_QI, { 0xb88600 }
22355
  },
22356
/* sbb.b${X} ${Dsp-16-u8}[sb],[$Dst16An] */
22357
  {
22358
    { 0, 0, 0, 0 },
22359
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
22360
    & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_indirect_QI, { 0xb8a600 }
22361
  },
22362
/* sbb.b${X} ${Dsp-16-s8}[fb],[$Dst16An] */
22363
  {
22364
    { 0, 0, 0, 0 },
22365
    { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
22366
    & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_indirect_QI, { 0xb8b600 }
22367
  },
22368
/* sbb.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
22369
  {
22370
    { 0, 0, 0, 0 },
22371
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
22372
    & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_An_relative_QI, { 0xb8880000 }
22373
  },
22374
/* sbb.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
22375
  {
22376
    { 0, 0, 0, 0 },
22377
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
22378
    & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_An_relative_QI, { 0xb8a80000 }
22379
  },
22380
/* sbb.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
22381
  {
22382
    { 0, 0, 0, 0 },
22383
    { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
22384
    & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_An_relative_QI, { 0xb8b80000 }
22385
  },
22386
/* sbb.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
22387
  {
22388
    { 0, 0, 0, 0 },
22389
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
22390
    & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_An_relative_QI, { 0xb88c0000 }
22391
  },
22392
/* sbb.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
22393
  {
22394
    { 0, 0, 0, 0 },
22395
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
22396
    & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_An_relative_QI, { 0xb8ac0000 }
22397
  },
22398
/* sbb.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
22399
  {
22400
    { 0, 0, 0, 0 },
22401
    { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
22402
    & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_An_relative_QI, { 0xb8bc0000 }
22403
  },
22404
/* sbb.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
22405
  {
22406
    { 0, 0, 0, 0 },
22407
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
22408
    & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_SB_relative_QI, { 0xb88a0000 }
22409
  },
22410
/* sbb.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
22411
  {
22412
    { 0, 0, 0, 0 },
22413
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
22414
    & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_SB_relative_QI, { 0xb8aa0000 }
22415
  },
22416
/* sbb.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
22417
  {
22418
    { 0, 0, 0, 0 },
22419
    { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
22420
    & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_SB_relative_QI, { 0xb8ba0000 }
22421
  },
22422
/* sbb.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
22423
  {
22424
    { 0, 0, 0, 0 },
22425
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
22426
    & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_SB_relative_QI, { 0xb88e0000 }
22427
  },
22428
/* sbb.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
22429
  {
22430
    { 0, 0, 0, 0 },
22431
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
22432
    & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_SB_relative_QI, { 0xb8ae0000 }
22433
  },
22434
/* sbb.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
22435
  {
22436
    { 0, 0, 0, 0 },
22437
    { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
22438
    & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_SB_relative_QI, { 0xb8be0000 }
22439
  },
22440
/* sbb.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
22441
  {
22442
    { 0, 0, 0, 0 },
22443
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
22444
    & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_FB_relative_QI, { 0xb88b0000 }
22445
  },
22446
/* sbb.b${X} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
22447
  {
22448
    { 0, 0, 0, 0 },
22449
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
22450
    & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_FB_relative_QI, { 0xb8ab0000 }
22451
  },
22452
/* sbb.b${X} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
22453
  {
22454
    { 0, 0, 0, 0 },
22455
    { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
22456
    & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_FB_relative_QI, { 0xb8bb0000 }
22457
  },
22458
/* sbb.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
22459
  {
22460
    { 0, 0, 0, 0 },
22461
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } },
22462
    & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_absolute_QI, { 0xb88f0000 }
22463
  },
22464
/* sbb.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
22465
  {
22466
    { 0, 0, 0, 0 },
22467
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
22468
    & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_absolute_QI, { 0xb8af0000 }
22469
  },
22470
/* sbb.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
22471
  {
22472
    { 0, 0, 0, 0 },
22473
    { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
22474
    & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_absolute_QI, { 0xb8bf0000 }
22475
  },
22476
/* sbb.b${X} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
22477
  {
22478
    { 0, 0, 0, 0 },
22479
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } },
22480
    & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_Rn_direct_QI, { 0xb8c00000 }
22481
  },
22482
/* sbb.b${X} ${Dsp-16-u16}[sb],$Dst16RnQI */
22483
  {
22484
    { 0, 0, 0, 0 },
22485
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } },
22486
    & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_Rn_direct_QI, { 0xb8e00000 }
22487
  },
22488
/* sbb.b${X} ${Dsp-16-u16},$Dst16RnQI */
22489
  {
22490
    { 0, 0, 0, 0 },
22491
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DST16RNQI), 0 } },
22492
    & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_Rn_direct_QI, { 0xb8f00000 }
22493
  },
22494
/* sbb.b${X} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
22495
  {
22496
    { 0, 0, 0, 0 },
22497
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } },
22498
    & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_direct_QI, { 0xb8c40000 }
22499
  },
22500
/* sbb.b${X} ${Dsp-16-u16}[sb],$Dst16AnQI */
22501
  {
22502
    { 0, 0, 0, 0 },
22503
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } },
22504
    & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_direct_QI, { 0xb8e40000 }
22505
  },
22506
/* sbb.b${X} ${Dsp-16-u16},$Dst16AnQI */
22507
  {
22508
    { 0, 0, 0, 0 },
22509
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DST16ANQI), 0 } },
22510
    & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_direct_QI, { 0xb8f40000 }
22511
  },
22512
/* sbb.b${X} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
22513
  {
22514
    { 0, 0, 0, 0 },
22515
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
22516
    & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_indirect_QI, { 0xb8c60000 }
22517
  },
22518
/* sbb.b${X} ${Dsp-16-u16}[sb],[$Dst16An] */
22519
  {
22520
    { 0, 0, 0, 0 },
22521
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
22522
    & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_indirect_QI, { 0xb8e60000 }
22523
  },
22524
/* sbb.b${X} ${Dsp-16-u16},[$Dst16An] */
22525
  {
22526
    { 0, 0, 0, 0 },
22527
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } },
22528
    & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_indirect_QI, { 0xb8f60000 }
22529
  },
22530
/* sbb.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
22531
  {
22532
    { 0, 0, 0, 0 },
22533
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
22534
    & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_An_relative_QI, { 0xb8c80000 }
22535
  },
22536
/* sbb.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
22537
  {
22538
    { 0, 0, 0, 0 },
22539
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
22540
    & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_An_relative_QI, { 0xb8e80000 }
22541
  },
22542
/* sbb.b${X} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
22543
  {
22544
    { 0, 0, 0, 0 },
22545
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
22546
    & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_An_relative_QI, { 0xb8f80000 }
22547
  },
22548
/* sbb.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
22549
  {
22550
    { 0, 0, 0, 0 },
22551
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
22552
    & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_An_relative_QI, { 0xb8cc0000 }
22553
  },
22554
/* sbb.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
22555
  {
22556
    { 0, 0, 0, 0 },
22557
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
22558
    & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_An_relative_QI, { 0xb8ec0000 }
22559
  },
22560
/* sbb.b${X} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
22561
  {
22562
    { 0, 0, 0, 0 },
22563
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
22564
    & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_An_relative_QI, { 0xb8fc0000 }
22565
  },
22566
/* sbb.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
22567
  {
22568
    { 0, 0, 0, 0 },
22569
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
22570
    & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_SB_relative_QI, { 0xb8ca0000 }
22571
  },
22572
/* sbb.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
22573
  {
22574
    { 0, 0, 0, 0 },
22575
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
22576
    & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_SB_relative_QI, { 0xb8ea0000 }
22577
  },
22578
/* sbb.b${X} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
22579
  {
22580
    { 0, 0, 0, 0 },
22581
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
22582
    & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_SB_relative_QI, { 0xb8fa0000 }
22583
  },
22584
/* sbb.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
22585
  {
22586
    { 0, 0, 0, 0 },
22587
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
22588
    & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_SB_relative_QI, { 0xb8ce0000 }
22589
  },
22590
/* sbb.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
22591
  {
22592
    { 0, 0, 0, 0 },
22593
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
22594
    & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_SB_relative_QI, { 0xb8ee0000 }
22595
  },
22596
/* sbb.b${X} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
22597
  {
22598
    { 0, 0, 0, 0 },
22599
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
22600
    & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_SB_relative_QI, { 0xb8fe0000 }
22601
  },
22602
/* sbb.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
22603
  {
22604
    { 0, 0, 0, 0 },
22605
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
22606
    & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_FB_relative_QI, { 0xb8cb0000 }
22607
  },
22608
/* sbb.b${X} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
22609
  {
22610
    { 0, 0, 0, 0 },
22611
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
22612
    & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_FB_relative_QI, { 0xb8eb0000 }
22613
  },
22614
/* sbb.b${X} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
22615
  {
22616
    { 0, 0, 0, 0 },
22617
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
22618
    & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_FB_relative_QI, { 0xb8fb0000 }
22619
  },
22620
/* sbb.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
22621
  {
22622
    { 0, 0, 0, 0 },
22623
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } },
22624
    & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_absolute_QI, { 0xb8cf0000 }
22625
  },
22626
/* sbb.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
22627
  {
22628
    { 0, 0, 0, 0 },
22629
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
22630
    & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_absolute_QI, { 0xb8ef0000 }
22631
  },
22632
/* sbb.b${X} ${Dsp-16-u16},${Dsp-32-u16} */
22633
  {
22634
    { 0, 0, 0, 0 },
22635
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
22636
    & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_absolute_QI, { 0xb8ff0000 }
22637
  },
22638
/* sbb.b${X} $Src16RnQI,$Dst16RnQI */
22639
  {
22640
    { 0, 0, 0, 0 },
22641
    { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DST16RNQI), 0 } },
22642
    & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_Rn_direct_QI, { 0xb800 }
22643
  },
22644
/* sbb.b${X} $Src16AnQI,$Dst16RnQI */
22645
  {
22646
    { 0, 0, 0, 0 },
22647
    { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DST16RNQI), 0 } },
22648
    & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_Rn_direct_QI, { 0xb840 }
22649
  },
22650
/* sbb.b${X} [$Src16An],$Dst16RnQI */
22651
  {
22652
    { 0, 0, 0, 0 },
22653
    { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } },
22654
    & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_Rn_direct_QI, { 0xb860 }
22655
  },
22656
/* sbb.b${X} $Src16RnQI,$Dst16AnQI */
22657
  {
22658
    { 0, 0, 0, 0 },
22659
    { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DST16ANQI), 0 } },
22660
    & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_direct_QI, { 0xb804 }
22661
  },
22662
/* sbb.b${X} $Src16AnQI,$Dst16AnQI */
22663
  {
22664
    { 0, 0, 0, 0 },
22665
    { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DST16ANQI), 0 } },
22666
    & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_direct_QI, { 0xb844 }
22667
  },
22668
/* sbb.b${X} [$Src16An],$Dst16AnQI */
22669
  {
22670
    { 0, 0, 0, 0 },
22671
    { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } },
22672
    & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_direct_QI, { 0xb864 }
22673
  },
22674
/* sbb.b${X} $Src16RnQI,[$Dst16An] */
22675
  {
22676
    { 0, 0, 0, 0 },
22677
    { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', '[', OP (DST16AN), ']', 0 } },
22678
    & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_indirect_QI, { 0xb806 }
22679
  },
22680
/* sbb.b${X} $Src16AnQI,[$Dst16An] */
22681
  {
22682
    { 0, 0, 0, 0 },
22683
    { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', '[', OP (DST16AN), ']', 0 } },
22684
    & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_indirect_QI, { 0xb846 }
22685
  },
22686
/* sbb.b${X} [$Src16An],[$Dst16An] */
22687
  {
22688
    { 0, 0, 0, 0 },
22689
    { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
22690
    & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_indirect_QI, { 0xb866 }
22691
  },
22692
/* sbb.b${X} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
22693
  {
22694
    { 0, 0, 0, 0 },
22695
    { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
22696
    & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_An_relative_QI, { 0xb80800 }
22697
  },
22698
/* sbb.b${X} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
22699
  {
22700
    { 0, 0, 0, 0 },
22701
    { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
22702
    & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_An_relative_QI, { 0xb84800 }
22703
  },
22704
/* sbb.b${X} [$Src16An],${Dsp-16-u8}[$Dst16An] */
22705
  {
22706
    { 0, 0, 0, 0 },
22707
    { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
22708
    & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_An_relative_QI, { 0xb86800 }
22709
  },
22710
/* sbb.b${X} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
22711
  {
22712
    { 0, 0, 0, 0 },
22713
    { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
22714
    & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_An_relative_QI, { 0xb80c0000 }
22715
  },
22716
/* sbb.b${X} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
22717
  {
22718
    { 0, 0, 0, 0 },
22719
    { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
22720
    & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_An_relative_QI, { 0xb84c0000 }
22721
  },
22722
/* sbb.b${X} [$Src16An],${Dsp-16-u16}[$Dst16An] */
22723
  {
22724
    { 0, 0, 0, 0 },
22725
    { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
22726
    & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_An_relative_QI, { 0xb86c0000 }
22727
  },
22728
/* sbb.b${X} $Src16RnQI,${Dsp-16-u8}[sb] */
22729
  {
22730
    { 0, 0, 0, 0 },
22731
    { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
22732
    & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_SB_relative_QI, { 0xb80a00 }
22733
  },
22734
/* sbb.b${X} $Src16AnQI,${Dsp-16-u8}[sb] */
22735
  {
22736
    { 0, 0, 0, 0 },
22737
    { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
22738
    & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_SB_relative_QI, { 0xb84a00 }
22739
  },
22740
/* sbb.b${X} [$Src16An],${Dsp-16-u8}[sb] */
22741
  {
22742
    { 0, 0, 0, 0 },
22743
    { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
22744
    & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_SB_relative_QI, { 0xb86a00 }
22745
  },
22746
/* sbb.b${X} $Src16RnQI,${Dsp-16-u16}[sb] */
22747
  {
22748
    { 0, 0, 0, 0 },
22749
    { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
22750
    & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_SB_relative_QI, { 0xb80e0000 }
22751
  },
22752
/* sbb.b${X} $Src16AnQI,${Dsp-16-u16}[sb] */
22753
  {
22754
    { 0, 0, 0, 0 },
22755
    { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
22756
    & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_SB_relative_QI, { 0xb84e0000 }
22757
  },
22758
/* sbb.b${X} [$Src16An],${Dsp-16-u16}[sb] */
22759
  {
22760
    { 0, 0, 0, 0 },
22761
    { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
22762
    & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_SB_relative_QI, { 0xb86e0000 }
22763
  },
22764
/* sbb.b${X} $Src16RnQI,${Dsp-16-s8}[fb] */
22765
  {
22766
    { 0, 0, 0, 0 },
22767
    { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
22768
    & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_FB_relative_QI, { 0xb80b00 }
22769
  },
22770
/* sbb.b${X} $Src16AnQI,${Dsp-16-s8}[fb] */
22771
  {
22772
    { 0, 0, 0, 0 },
22773
    { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
22774
    & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_FB_relative_QI, { 0xb84b00 }
22775
  },
22776
/* sbb.b${X} [$Src16An],${Dsp-16-s8}[fb] */
22777
  {
22778
    { 0, 0, 0, 0 },
22779
    { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
22780
    & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_FB_relative_QI, { 0xb86b00 }
22781
  },
22782
/* sbb.b${X} $Src16RnQI,${Dsp-16-u16} */
22783
  {
22784
    { 0, 0, 0, 0 },
22785
    { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), 0 } },
22786
    & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_absolute_QI, { 0xb80f0000 }
22787
  },
22788
/* sbb.b${X} $Src16AnQI,${Dsp-16-u16} */
22789
  {
22790
    { 0, 0, 0, 0 },
22791
    { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), 0 } },
22792
    & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_absolute_QI, { 0xb84f0000 }
22793
  },
22794
/* sbb.b${X} [$Src16An],${Dsp-16-u16} */
22795
  {
22796
    { 0, 0, 0, 0 },
22797
    { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } },
22798
    & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_absolute_QI, { 0xb86f0000 }
22799
  },
22800
/* sbb.w${X} #${Imm-24-HI},$Dst32RnPrefixedHI */
22801
  {
22802
    { 0, 0, 0, 0 },
22803
    { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DST32RNPREFIXEDHI), 0 } },
22804
    & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_Rn_direct_Prefixed_HI, { 0x1992e00 }
22805
  },
22806
/* sbb.w${X} #${Imm-24-HI},$Dst32AnPrefixedHI */
22807
  {
22808
    { 0, 0, 0, 0 },
22809
    { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DST32ANPREFIXEDHI), 0 } },
22810
    & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_An_direct_Prefixed_HI, { 0x191ae00 }
22811
  },
22812
/* sbb.w${X} #${Imm-24-HI},[$Dst32AnPrefixed] */
22813
  {
22814
    { 0, 0, 0, 0 },
22815
    { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
22816
    & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_An_indirect_Prefixed_HI, { 0x1912e00 }
22817
  },
22818
/* sbb.w${X} #${Imm-32-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */
22819
  {
22820
    { 0, 0, 0, 0 },
22821
    { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
22822
    & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_An_relative_Prefixed_HI, { 0x1932e00 }
22823
  },
22824
/* sbb.w${X} #${Imm-32-HI},${Dsp-24-u8}[sb] */
22825
  {
22826
    { 0, 0, 0, 0 },
22827
    { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
22828
    & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_SB_relative_Prefixed_HI, { 0x193ae00 }
22829
  },
22830
/* sbb.w${X} #${Imm-32-HI},${Dsp-24-s8}[fb] */
22831
  {
22832
    { 0, 0, 0, 0 },
22833
    { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
22834
    & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_FB_relative_Prefixed_HI, { 0x193ee00 }
22835
  },
22836
/* sbb.w${X} #${Imm-40-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */
22837
  {
22838
    { 0, 0, 0, 0 },
22839
    { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
22840
    & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_An_relative_Prefixed_HI, { 0x1952e00 }
22841
  },
22842
/* sbb.w${X} #${Imm-40-HI},${Dsp-24-u16}[sb] */
22843
  {
22844
    { 0, 0, 0, 0 },
22845
    { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
22846
    & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_SB_relative_Prefixed_HI, { 0x195ae00 }
22847
  },
22848
/* sbb.w${X} #${Imm-40-HI},${Dsp-24-s16}[fb] */
22849
  {
22850
    { 0, 0, 0, 0 },
22851
    { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
22852
    & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_FB_relative_Prefixed_HI, { 0x195ee00 }
22853
  },
22854
/* sbb.w${X} #${Imm-40-HI},${Dsp-24-u16} */
22855
  {
22856
    { 0, 0, 0, 0 },
22857
    { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), 0 } },
22858
    & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_absolute_Prefixed_HI, { 0x197ee00 }
22859
  },
22860
/* sbb.w${X} #${Imm-48-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */
22861
  {
22862
    { 0, 0, 0, 0 },
22863
    { { MNEM, OP (X), ' ', '#', OP (IMM_48_HI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
22864
    & ifmt_sbb32_w_imm_G_24_24_Prefixed_dst32_24_24_An_relative_Prefixed_HI, { 0x1972e00 }
22865
  },
22866
/* sbb.w${X} #${Imm-48-HI},${Dsp-24-u24} */
22867
  {
22868
    { 0, 0, 0, 0 },
22869
    { { MNEM, OP (X), ' ', '#', OP (IMM_48_HI), ',', OP (DSP_24_U24), 0 } },
22870
    & ifmt_sbb32_w_imm_G_24_24_Prefixed_dst32_24_24_absolute_Prefixed_HI, { 0x197ae00 }
22871
  },
22872
/* sbb.b${X} #${Imm-24-QI},$Dst32RnPrefixedQI */
22873
  {
22874
    { 0, 0, 0, 0 },
22875
    { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DST32RNPREFIXEDQI), 0 } },
22876
    & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_Rn_direct_Prefixed_QI, { 0x1982e00 }
22877
  },
22878
/* sbb.b${X} #${Imm-24-QI},$Dst32AnPrefixedQI */
22879
  {
22880
    { 0, 0, 0, 0 },
22881
    { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DST32ANPREFIXEDQI), 0 } },
22882
    & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_An_direct_Prefixed_QI, { 0x190ae00 }
22883
  },
22884
/* sbb.b${X} #${Imm-24-QI},[$Dst32AnPrefixed] */
22885
  {
22886
    { 0, 0, 0, 0 },
22887
    { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
22888
    & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_An_indirect_Prefixed_QI, { 0x1902e00 }
22889
  },
22890
/* sbb.b${X} #${Imm-32-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */
22891
  {
22892
    { 0, 0, 0, 0 },
22893
    { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
22894
    & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_An_relative_Prefixed_QI, { 0x1922e00 }
22895
  },
22896
/* sbb.b${X} #${Imm-32-QI},${Dsp-24-u8}[sb] */
22897
  {
22898
    { 0, 0, 0, 0 },
22899
    { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
22900
    & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_SB_relative_Prefixed_QI, { 0x192ae00 }
22901
  },
22902
/* sbb.b${X} #${Imm-32-QI},${Dsp-24-s8}[fb] */
22903
  {
22904
    { 0, 0, 0, 0 },
22905
    { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
22906
    & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_FB_relative_Prefixed_QI, { 0x192ee00 }
22907
  },
22908
/* sbb.b${X} #${Imm-40-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */
22909
  {
22910
    { 0, 0, 0, 0 },
22911
    { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
22912
    & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_An_relative_Prefixed_QI, { 0x1942e00 }
22913
  },
22914
/* sbb.b${X} #${Imm-40-QI},${Dsp-24-u16}[sb] */
22915
  {
22916
    { 0, 0, 0, 0 },
22917
    { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
22918
    & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_SB_relative_Prefixed_QI, { 0x194ae00 }
22919
  },
22920
/* sbb.b${X} #${Imm-40-QI},${Dsp-24-s16}[fb] */
22921
  {
22922
    { 0, 0, 0, 0 },
22923
    { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
22924
    & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_FB_relative_Prefixed_QI, { 0x194ee00 }
22925
  },
22926
/* sbb.b${X} #${Imm-40-QI},${Dsp-24-u16} */
22927
  {
22928
    { 0, 0, 0, 0 },
22929
    { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), 0 } },
22930
    & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_absolute_Prefixed_QI, { 0x196ee00 }
22931
  },
22932
/* sbb.b${X} #${Imm-48-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */
22933
  {
22934
    { 0, 0, 0, 0 },
22935
    { { MNEM, OP (X), ' ', '#', OP (IMM_48_QI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
22936
    & ifmt_sbb32_b_imm_G_24_24_Prefixed_dst32_24_24_An_relative_Prefixed_QI, { 0x1962e00 }
22937
  },
22938
/* sbb.b${X} #${Imm-48-QI},${Dsp-24-u24} */
22939
  {
22940
    { 0, 0, 0, 0 },
22941
    { { MNEM, OP (X), ' ', '#', OP (IMM_48_QI), ',', OP (DSP_24_U24), 0 } },
22942
    & ifmt_sbb32_b_imm_G_24_24_Prefixed_dst32_24_24_absolute_Prefixed_QI, { 0x196ae00 }
22943
  },
22944
/* sbb.w${X} #${Imm-16-HI},$Dst16RnHI */
22945
  {
22946
    { 0, 0, 0, 0 },
22947
    { { MNEM, OP (X), ' ', '#', OP (IMM_16_HI), ',', OP (DST16RNHI), 0 } },
22948
    & ifmt_xor16_w_imm_G_basic_dst16_Rn_direct_HI, { 0x77700000 }
22949
  },
22950
/* sbb.w${X} #${Imm-16-HI},$Dst16AnHI */
22951
  {
22952
    { 0, 0, 0, 0 },
22953
    { { MNEM, OP (X), ' ', '#', OP (IMM_16_HI), ',', OP (DST16ANHI), 0 } },
22954
    & ifmt_xor16_w_imm_G_basic_dst16_An_direct_HI, { 0x77740000 }
22955
  },
22956
/* sbb.w${X} #${Imm-16-HI},[$Dst16An] */
22957
  {
22958
    { 0, 0, 0, 0 },
22959
    { { MNEM, OP (X), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST16AN), ']', 0 } },
22960
    & ifmt_xor16_w_imm_G_basic_dst16_An_indirect_HI, { 0x77760000 }
22961
  },
22962
/* sbb.w${X} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
22963
  {
22964
    { 0, 0, 0, 0 },
22965
    { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
22966
    & ifmt_xor16_w_imm_G_16_8_dst16_16_8_An_relative_HI, { 0x77780000 }
22967
  },
22968
/* sbb.w${X} #${Imm-24-HI},${Dsp-16-u8}[sb] */
22969
  {
22970
    { 0, 0, 0, 0 },
22971
    { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
22972
    & ifmt_xor16_w_imm_G_16_8_dst16_16_8_SB_relative_HI, { 0x777a0000 }
22973
  },
22974
/* sbb.w${X} #${Imm-24-HI},${Dsp-16-s8}[fb] */
22975
  {
22976
    { 0, 0, 0, 0 },
22977
    { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
22978
    & ifmt_xor16_w_imm_G_16_8_dst16_16_8_FB_relative_HI, { 0x777b0000 }
22979
  },
22980
/* sbb.w${X} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
22981
  {
22982
    { 0, 0, 0, 0 },
22983
    { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
22984
    & ifmt_xor16_w_imm_G_16_16_dst16_16_16_An_relative_HI, { 0x777c0000 }
22985
  },
22986
/* sbb.w${X} #${Imm-32-HI},${Dsp-16-u16}[sb] */
22987
  {
22988
    { 0, 0, 0, 0 },
22989
    { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
22990
    & ifmt_xor16_w_imm_G_16_16_dst16_16_16_SB_relative_HI, { 0x777e0000 }
22991
  },
22992
/* sbb.w${X} #${Imm-32-HI},${Dsp-16-u16} */
22993
  {
22994
    { 0, 0, 0, 0 },
22995
    { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } },
22996
    & ifmt_xor16_w_imm_G_16_16_dst16_16_16_absolute_HI, { 0x777f0000 }
22997
  },
22998
/* sbb.b${X} #${Imm-16-QI},$Dst16RnQI */
22999
  {
23000
    { 0, 0, 0, 0 },
23001
    { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST16RNQI), 0 } },
23002
    & ifmt_xor16_b_imm_G_basic_dst16_Rn_direct_QI, { 0x767000 }
23003
  },
23004
/* sbb.b${X} #${Imm-16-QI},$Dst16AnQI */
23005
  {
23006
    { 0, 0, 0, 0 },
23007
    { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST16ANQI), 0 } },
23008
    & ifmt_xor16_b_imm_G_basic_dst16_An_direct_QI, { 0x767400 }
23009
  },
23010
/* sbb.b${X} #${Imm-16-QI},[$Dst16An] */
23011
  {
23012
    { 0, 0, 0, 0 },
23013
    { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST16AN), ']', 0 } },
23014
    & ifmt_xor16_b_imm_G_basic_dst16_An_indirect_QI, { 0x767600 }
23015
  },
23016
/* sbb.b${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
23017
  {
23018
    { 0, 0, 0, 0 },
23019
    { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
23020
    & ifmt_xor16_b_imm_G_16_8_dst16_16_8_An_relative_QI, { 0x76780000 }
23021
  },
23022
/* sbb.b${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
23023
  {
23024
    { 0, 0, 0, 0 },
23025
    { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
23026
    & ifmt_xor16_b_imm_G_16_8_dst16_16_8_SB_relative_QI, { 0x767a0000 }
23027
  },
23028
/* sbb.b${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
23029
  {
23030
    { 0, 0, 0, 0 },
23031
    { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
23032
    & ifmt_xor16_b_imm_G_16_8_dst16_16_8_FB_relative_QI, { 0x767b0000 }
23033
  },
23034
/* sbb.b${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
23035
  {
23036
    { 0, 0, 0, 0 },
23037
    { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
23038
    & ifmt_xor16_b_imm_G_16_16_dst16_16_16_An_relative_QI, { 0x767c0000 }
23039
  },
23040
/* sbb.b${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
23041
  {
23042
    { 0, 0, 0, 0 },
23043
    { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
23044
    & ifmt_xor16_b_imm_G_16_16_dst16_16_16_SB_relative_QI, { 0x767e0000 }
23045
  },
23046
/* sbb.b${X} #${Imm-32-QI},${Dsp-16-u16} */
23047
  {
23048
    { 0, 0, 0, 0 },
23049
    { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } },
23050
    & ifmt_xor16_b_imm_G_16_16_dst16_16_16_absolute_QI, { 0x767f0000 }
23051
  },
23052
/* rot.w r1h,$Dst32RnUnprefixedHI */
23053
  {
23054
    { 0, 0, 0, 0 },
23055
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
23056
    & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xa93f }
23057
  },
23058
/* rot.w r1h,$Dst32AnUnprefixedHI */
23059
  {
23060
    { 0, 0, 0, 0 },
23061
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
23062
    & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xa1bf }
23063
  },
23064
/* rot.w r1h,[$Dst32AnUnprefixed] */
23065
  {
23066
    { 0, 0, 0, 0 },
23067
    { { MNEM, ' ', 'r', '1', 'h', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
23068
    & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xa13f }
23069
  },
23070
/* rot.w r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */
23071
  {
23072
    { 0, 0, 0, 0 },
23073
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
23074
    & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xa33f00 }
23075
  },
23076
/* rot.w r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */
23077
  {
23078
    { 0, 0, 0, 0 },
23079
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
23080
    & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xa53f0000 }
23081
  },
23082
/* rot.w r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */
23083
  {
23084
    { 0, 0, 0, 0 },
23085
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
23086
    & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xa73f0000 }
23087
  },
23088
/* rot.w r1h,${Dsp-16-u8}[sb] */
23089
  {
23090
    { 0, 0, 0, 0 },
23091
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
23092
    & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xa3bf00 }
23093
  },
23094
/* rot.w r1h,${Dsp-16-u16}[sb] */
23095
  {
23096
    { 0, 0, 0, 0 },
23097
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
23098
    & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xa5bf0000 }
23099
  },
23100
/* rot.w r1h,${Dsp-16-s8}[fb] */
23101
  {
23102
    { 0, 0, 0, 0 },
23103
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
23104
    & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xa3ff00 }
23105
  },
23106
/* rot.w r1h,${Dsp-16-s16}[fb] */
23107
  {
23108
    { 0, 0, 0, 0 },
23109
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
23110
    & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xa5ff0000 }
23111
  },
23112
/* rot.w r1h,${Dsp-16-u16} */
23113
  {
23114
    { 0, 0, 0, 0 },
23115
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), 0 } },
23116
    & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xa7ff0000 }
23117
  },
23118
/* rot.w r1h,${Dsp-16-u24} */
23119
  {
23120
    { 0, 0, 0, 0 },
23121
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U24), 0 } },
23122
    & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xa7bf0000 }
23123
  },
23124
/* rot.b r1h,$Dst32RnUnprefixedQI */
23125
  {
23126
    { 0, 0, 0, 0 },
23127
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
23128
    & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0xa83f }
23129
  },
23130
/* rot.b r1h,$Dst32AnUnprefixedQI */
23131
  {
23132
    { 0, 0, 0, 0 },
23133
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
23134
    & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0xa0bf }
23135
  },
23136
/* rot.b r1h,[$Dst32AnUnprefixed] */
23137
  {
23138
    { 0, 0, 0, 0 },
23139
    { { MNEM, ' ', 'r', '1', 'h', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
23140
    & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0xa03f }
23141
  },
23142
/* rot.b r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */
23143
  {
23144
    { 0, 0, 0, 0 },
23145
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
23146
    & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0xa23f00 }
23147
  },
23148
/* rot.b r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */
23149
  {
23150
    { 0, 0, 0, 0 },
23151
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
23152
    & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0xa43f0000 }
23153
  },
23154
/* rot.b r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */
23155
  {
23156
    { 0, 0, 0, 0 },
23157
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
23158
    & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0xa63f0000 }
23159
  },
23160
/* rot.b r1h,${Dsp-16-u8}[sb] */
23161
  {
23162
    { 0, 0, 0, 0 },
23163
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
23164
    & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0xa2bf00 }
23165
  },
23166
/* rot.b r1h,${Dsp-16-u16}[sb] */
23167
  {
23168
    { 0, 0, 0, 0 },
23169
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
23170
    & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0xa4bf0000 }
23171
  },
23172
/* rot.b r1h,${Dsp-16-s8}[fb] */
23173
  {
23174
    { 0, 0, 0, 0 },
23175
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
23176
    & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0xa2ff00 }
23177
  },
23178
/* rot.b r1h,${Dsp-16-s16}[fb] */
23179
  {
23180
    { 0, 0, 0, 0 },
23181
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
23182
    & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0xa4ff0000 }
23183
  },
23184
/* rot.b r1h,${Dsp-16-u16} */
23185
  {
23186
    { 0, 0, 0, 0 },
23187
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), 0 } },
23188
    & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0xa6ff0000 }
23189
  },
23190
/* rot.b r1h,${Dsp-16-u24} */
23191
  {
23192
    { 0, 0, 0, 0 },
23193
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U24), 0 } },
23194
    & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0xa6bf0000 }
23195
  },
23196
/* rot.w r1h,$Dst16RnHI */
23197
  {
23198
    { 0, 0, 0, 0 },
23199
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST16RNHI), 0 } },
23200
    & ifmt_shl16_w_dst_dst16_Rn_direct_HI, { 0x7560 }
23201
  },
23202
/* rot.w r1h,$Dst16AnHI */
23203
  {
23204
    { 0, 0, 0, 0 },
23205
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST16ANHI), 0 } },
23206
    & ifmt_shl16_w_dst_dst16_An_direct_HI, { 0x7564 }
23207
  },
23208
/* rot.w r1h,[$Dst16An] */
23209
  {
23210
    { 0, 0, 0, 0 },
23211
    { { MNEM, ' ', 'r', '1', 'h', ',', '[', OP (DST16AN), ']', 0 } },
23212
    & ifmt_shl16_w_dst_dst16_An_indirect_HI, { 0x7566 }
23213
  },
23214
/* rot.w r1h,${Dsp-16-u8}[$Dst16An] */
23215
  {
23216
    { 0, 0, 0, 0 },
23217
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
23218
    & ifmt_shl16_w_dst_dst16_16_8_An_relative_HI, { 0x756800 }
23219
  },
23220
/* rot.w r1h,${Dsp-16-u16}[$Dst16An] */
23221
  {
23222
    { 0, 0, 0, 0 },
23223
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
23224
    & ifmt_shl16_w_dst_dst16_16_16_An_relative_HI, { 0x756c0000 }
23225
  },
23226
/* rot.w r1h,${Dsp-16-u8}[sb] */
23227
  {
23228
    { 0, 0, 0, 0 },
23229
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
23230
    & ifmt_shl16_w_dst_dst16_16_8_SB_relative_HI, { 0x756a00 }
23231
  },
23232
/* rot.w r1h,${Dsp-16-u16}[sb] */
23233
  {
23234
    { 0, 0, 0, 0 },
23235
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
23236
    & ifmt_shl16_w_dst_dst16_16_16_SB_relative_HI, { 0x756e0000 }
23237
  },
23238
/* rot.w r1h,${Dsp-16-s8}[fb] */
23239
  {
23240
    { 0, 0, 0, 0 },
23241
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
23242
    & ifmt_shl16_w_dst_dst16_16_8_FB_relative_HI, { 0x756b00 }
23243
  },
23244
/* rot.w r1h,${Dsp-16-u16} */
23245
  {
23246
    { 0, 0, 0, 0 },
23247
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), 0 } },
23248
    & ifmt_shl16_w_dst_dst16_16_16_absolute_HI, { 0x756f0000 }
23249
  },
23250
/* rot.b r1h,$Dst16RnQI */
23251
  {
23252
    { 0, 0, 0, 0 },
23253
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST16RNQI), 0 } },
23254
    & ifmt_shl16_b_dst_dst16_Rn_direct_QI, { 0x7460 }
23255
  },
23256
/* rot.b r1h,$Dst16AnQI */
23257
  {
23258
    { 0, 0, 0, 0 },
23259
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST16ANQI), 0 } },
23260
    & ifmt_shl16_b_dst_dst16_An_direct_QI, { 0x7464 }
23261
  },
23262
/* rot.b r1h,[$Dst16An] */
23263
  {
23264
    { 0, 0, 0, 0 },
23265
    { { MNEM, ' ', 'r', '1', 'h', ',', '[', OP (DST16AN), ']', 0 } },
23266
    & ifmt_shl16_b_dst_dst16_An_indirect_QI, { 0x7466 }
23267
  },
23268
/* rot.b r1h,${Dsp-16-u8}[$Dst16An] */
23269
  {
23270
    { 0, 0, 0, 0 },
23271
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
23272
    & ifmt_shl16_b_dst_dst16_16_8_An_relative_QI, { 0x746800 }
23273
  },
23274
/* rot.b r1h,${Dsp-16-u16}[$Dst16An] */
23275
  {
23276
    { 0, 0, 0, 0 },
23277
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
23278
    & ifmt_shl16_b_dst_dst16_16_16_An_relative_QI, { 0x746c0000 }
23279
  },
23280
/* rot.b r1h,${Dsp-16-u8}[sb] */
23281
  {
23282
    { 0, 0, 0, 0 },
23283
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
23284
    & ifmt_shl16_b_dst_dst16_16_8_SB_relative_QI, { 0x746a00 }
23285
  },
23286
/* rot.b r1h,${Dsp-16-u16}[sb] */
23287
  {
23288
    { 0, 0, 0, 0 },
23289
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
23290
    & ifmt_shl16_b_dst_dst16_16_16_SB_relative_QI, { 0x746e0000 }
23291
  },
23292
/* rot.b r1h,${Dsp-16-s8}[fb] */
23293
  {
23294
    { 0, 0, 0, 0 },
23295
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
23296
    & ifmt_shl16_b_dst_dst16_16_8_FB_relative_QI, { 0x746b00 }
23297
  },
23298
/* rot.b r1h,${Dsp-16-u16} */
23299
  {
23300
    { 0, 0, 0, 0 },
23301
    { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), 0 } },
23302
    & ifmt_shl16_b_dst_dst16_16_16_absolute_QI, { 0x746f0000 }
23303
  },
23304
/* rot.w${Q} #${Imm-sh-12-s4},$Dst32RnUnprefixedHI */
23305
  {
23306
    { 0, 0, 0, 0 },
23307
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
23308
    & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0xe920 }
23309
  },
23310
/* rot.w${Q} #${Imm-sh-12-s4},$Dst32AnUnprefixedHI */
23311
  {
23312
    { 0, 0, 0, 0 },
23313
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
23314
    & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0xe1a0 }
23315
  },
23316
/* rot.w${Q} #${Imm-sh-12-s4},[$Dst32AnUnprefixed] */
23317
  {
23318
    { 0, 0, 0, 0 },
23319
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
23320
    & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0xe120 }
23321
  },
23322
/* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
23323
  {
23324
    { 0, 0, 0, 0 },
23325
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
23326
    & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0xe32000 }
23327
  },
23328
/* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
23329
  {
23330
    { 0, 0, 0, 0 },
23331
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
23332
    & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0xe5200000 }
23333
  },
23334
/* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
23335
  {
23336
    { 0, 0, 0, 0 },
23337
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
23338
    & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0xe7200000 }
23339
  },
23340
/* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[sb] */
23341
  {
23342
    { 0, 0, 0, 0 },
23343
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
23344
    & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0xe3a000 }
23345
  },
23346
/* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[sb] */
23347
  {
23348
    { 0, 0, 0, 0 },
23349
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
23350
    & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0xe5a00000 }
23351
  },
23352
/* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-s8}[fb] */
23353
  {
23354
    { 0, 0, 0, 0 },
23355
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
23356
    & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0xe3e000 }
23357
  },
23358
/* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-s16}[fb] */
23359
  {
23360
    { 0, 0, 0, 0 },
23361
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
23362
    & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0xe5e00000 }
23363
  },
23364
/* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16} */
23365
  {
23366
    { 0, 0, 0, 0 },
23367
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U16), 0 } },
23368
    & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0xe7e00000 }
23369
  },
23370
/* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-u24} */
23371
  {
23372
    { 0, 0, 0, 0 },
23373
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U24), 0 } },
23374
    & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0xe7a00000 }
23375
  },
23376
/* rot.b${Q} #${Imm-sh-12-s4},$Dst32RnUnprefixedQI */
23377
  {
23378
    { 0, 0, 0, 0 },
23379
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
23380
    & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0xe820 }
23381
  },
23382
/* rot.b${Q} #${Imm-sh-12-s4},$Dst32AnUnprefixedQI */
23383
  {
23384
    { 0, 0, 0, 0 },
23385
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
23386
    & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0xe0a0 }
23387
  },
23388
/* rot.b${Q} #${Imm-sh-12-s4},[$Dst32AnUnprefixed] */
23389
  {
23390
    { 0, 0, 0, 0 },
23391
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
23392
    & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0xe020 }
23393
  },
23394
/* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
23395
  {
23396
    { 0, 0, 0, 0 },
23397
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
23398
    & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0xe22000 }
23399
  },
23400
/* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
23401
  {
23402
    { 0, 0, 0, 0 },
23403
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
23404
    & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0xe4200000 }
23405
  },
23406
/* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
23407
  {
23408
    { 0, 0, 0, 0 },
23409
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
23410
    & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0xe6200000 }
23411
  },
23412
/* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[sb] */
23413
  {
23414
    { 0, 0, 0, 0 },
23415
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
23416
    & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0xe2a000 }
23417
  },
23418
/* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[sb] */
23419
  {
23420
    { 0, 0, 0, 0 },
23421
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
23422
    & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0xe4a00000 }
23423
  },
23424
/* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-s8}[fb] */
23425
  {
23426
    { 0, 0, 0, 0 },
23427
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
23428
    & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0xe2e000 }
23429
  },
23430
/* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-s16}[fb] */
23431
  {
23432
    { 0, 0, 0, 0 },
23433
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
23434
    & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0xe4e00000 }
23435
  },
23436
/* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16} */
23437
  {
23438
    { 0, 0, 0, 0 },
23439
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U16), 0 } },
23440
    & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0xe6e00000 }
23441
  },
23442
/* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-u24} */
23443
  {
23444
    { 0, 0, 0, 0 },
23445
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U24), 0 } },
23446
    & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0xe6a00000 }
23447
  },
23448
/* rot.w${Q} #${Imm-sh-8-s4},$Dst16RnHI */
23449
  {
23450
    { 0, 0, 0, 0 },
23451
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DST16RNHI), 0 } },
23452
    & ifmt_shl16_w_imm4_Q_16_dst16_Rn_direct_HI, { 0xe100 }
23453
  },
23454
/* rot.w${Q} #${Imm-sh-8-s4},$Dst16AnHI */
23455
  {
23456
    { 0, 0, 0, 0 },
23457
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DST16ANHI), 0 } },
23458
    & ifmt_shl16_w_imm4_Q_16_dst16_An_direct_HI, { 0xe104 }
23459
  },
23460
/* rot.w${Q} #${Imm-sh-8-s4},[$Dst16An] */
23461
  {
23462
    { 0, 0, 0, 0 },
23463
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', '[', OP (DST16AN), ']', 0 } },
23464
    & ifmt_shl16_w_imm4_Q_16_dst16_An_indirect_HI, { 0xe106 }
23465
  },
23466
/* rot.w${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[$Dst16An] */
23467
  {
23468
    { 0, 0, 0, 0 },
23469
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
23470
    & ifmt_shl16_w_imm4_Q_16_dst16_16_8_An_relative_HI, { 0xe10800 }
23471
  },
23472
/* rot.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[$Dst16An] */
23473
  {
23474
    { 0, 0, 0, 0 },
23475
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
23476
    & ifmt_shl16_w_imm4_Q_16_dst16_16_16_An_relative_HI, { 0xe10c0000 }
23477
  },
23478
/* rot.w${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[sb] */
23479
  {
23480
    { 0, 0, 0, 0 },
23481
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
23482
    & ifmt_shl16_w_imm4_Q_16_dst16_16_8_SB_relative_HI, { 0xe10a00 }
23483
  },
23484
/* rot.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[sb] */
23485
  {
23486
    { 0, 0, 0, 0 },
23487
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
23488
    & ifmt_shl16_w_imm4_Q_16_dst16_16_16_SB_relative_HI, { 0xe10e0000 }
23489
  },
23490
/* rot.w${Q} #${Imm-sh-8-s4},${Dsp-16-s8}[fb] */
23491
  {
23492
    { 0, 0, 0, 0 },
23493
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
23494
    & ifmt_shl16_w_imm4_Q_16_dst16_16_8_FB_relative_HI, { 0xe10b00 }
23495
  },
23496
/* rot.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16} */
23497
  {
23498
    { 0, 0, 0, 0 },
23499
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U16), 0 } },
23500
    & ifmt_shl16_w_imm4_Q_16_dst16_16_16_absolute_HI, { 0xe10f0000 }
23501
  },
23502
/* rot.b${Q} #${Imm-sh-8-s4},$Dst16RnQI */
23503
  {
23504
    { 0, 0, 0, 0 },
23505
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DST16RNQI), 0 } },
23506
    & ifmt_shl16_b_imm4_Q_16_dst16_Rn_direct_QI, { 0xe000 }
23507
  },
23508
/* rot.b${Q} #${Imm-sh-8-s4},$Dst16AnQI */
23509
  {
23510
    { 0, 0, 0, 0 },
23511
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DST16ANQI), 0 } },
23512
    & ifmt_shl16_b_imm4_Q_16_dst16_An_direct_QI, { 0xe004 }
23513
  },
23514
/* rot.b${Q} #${Imm-sh-8-s4},[$Dst16An] */
23515
  {
23516
    { 0, 0, 0, 0 },
23517
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', '[', OP (DST16AN), ']', 0 } },
23518
    & ifmt_shl16_b_imm4_Q_16_dst16_An_indirect_QI, { 0xe006 }
23519
  },
23520
/* rot.b${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[$Dst16An] */
23521
  {
23522
    { 0, 0, 0, 0 },
23523
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
23524
    & ifmt_shl16_b_imm4_Q_16_dst16_16_8_An_relative_QI, { 0xe00800 }
23525
  },
23526
/* rot.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[$Dst16An] */
23527
  {
23528
    { 0, 0, 0, 0 },
23529
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
23530
    & ifmt_shl16_b_imm4_Q_16_dst16_16_16_An_relative_QI, { 0xe00c0000 }
23531
  },
23532
/* rot.b${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[sb] */
23533
  {
23534
    { 0, 0, 0, 0 },
23535
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
23536
    & ifmt_shl16_b_imm4_Q_16_dst16_16_8_SB_relative_QI, { 0xe00a00 }
23537
  },
23538
/* rot.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[sb] */
23539
  {
23540
    { 0, 0, 0, 0 },
23541
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
23542
    & ifmt_shl16_b_imm4_Q_16_dst16_16_16_SB_relative_QI, { 0xe00e0000 }
23543
  },
23544
/* rot.b${Q} #${Imm-sh-8-s4},${Dsp-16-s8}[fb] */
23545
  {
23546
    { 0, 0, 0, 0 },
23547
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
23548
    & ifmt_shl16_b_imm4_Q_16_dst16_16_8_FB_relative_QI, { 0xe00b00 }
23549
  },
23550
/* rot.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16} */
23551
  {
23552
    { 0, 0, 0, 0 },
23553
    { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U16), 0 } },
23554
    & ifmt_shl16_b_imm4_Q_16_dst16_16_16_absolute_QI, { 0xe00f0000 }
23555
  },
23556
/* rorc.w $Dst32RnUnprefixedHI */
23557
  {
23558
    { 0, 0, 0, 0 },
23559
    { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } },
23560
    & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xa92e }
23561
  },
23562
/* rorc.w $Dst32AnUnprefixedHI */
23563
  {
23564
    { 0, 0, 0, 0 },
23565
    { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } },
23566
    & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xa1ae }
23567
  },
23568
/* rorc.w [$Dst32AnUnprefixed] */
23569
  {
23570
    { 0, 0, 0, 0 },
23571
    { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
23572
    & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xa12e }
23573
  },
23574
/* rorc.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
23575
  {
23576
    { 0, 0, 0, 0 },
23577
    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
23578
    & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xa32e00 }
23579
  },
23580
/* rorc.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
23581
  {
23582
    { 0, 0, 0, 0 },
23583
    { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
23584
    & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xa52e0000 }
23585
  },
23586
/* rorc.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
23587
  {
23588
    { 0, 0, 0, 0 },
23589
    { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
23590
    & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xa72e0000 }
23591
  },
23592
/* rorc.w ${Dsp-16-u8}[sb] */
23593
  {
23594
    { 0, 0, 0, 0 },
23595
    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
23596
    & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xa3ae00 }
23597
  },
23598
/* rorc.w ${Dsp-16-u16}[sb] */
23599
  {
23600
    { 0, 0, 0, 0 },
23601
    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
23602
    & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xa5ae0000 }
23603
  },
23604
/* rorc.w ${Dsp-16-s8}[fb] */
23605
  {
23606
    { 0, 0, 0, 0 },
23607
    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
23608
    & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xa3ee00 }
23609
  },
23610
/* rorc.w ${Dsp-16-s16}[fb] */
23611
  {
23612
    { 0, 0, 0, 0 },
23613
    { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
23614
    & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xa5ee0000 }
23615
  },
23616
/* rorc.w ${Dsp-16-u16} */
23617
  {
23618
    { 0, 0, 0, 0 },
23619
    { { MNEM, ' ', OP (DSP_16_U16), 0 } },
23620
    & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xa7ee0000 }
23621
  },
23622
/* rorc.w ${Dsp-16-u24} */
23623
  {
23624
    { 0, 0, 0, 0 },
23625
    { { MNEM, ' ', OP (DSP_16_U24), 0 } },
23626
    & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xa7ae0000 }
23627
  },
23628
/* rorc.b $Dst32RnUnprefixedQI */
23629
  {
23630
    { 0, 0, 0, 0 },
23631
    { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } },
23632
    & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0xa82e }
23633
  },
23634
/* rorc.b $Dst32AnUnprefixedQI */
23635
  {
23636
    { 0, 0, 0, 0 },
23637
    { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } },
23638
    & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0xa0ae }
23639
  },
23640
/* rorc.b [$Dst32AnUnprefixed] */
23641
  {
23642
    { 0, 0, 0, 0 },
23643
    { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
23644
    & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0xa02e }
23645
  },
23646
/* rorc.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
23647
  {
23648
    { 0, 0, 0, 0 },
23649
    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
23650
    & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0xa22e00 }
23651
  },
23652
/* rorc.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
23653
  {
23654
    { 0, 0, 0, 0 },
23655
    { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
23656
    & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0xa42e0000 }
23657
  },
23658
/* rorc.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
23659
  {
23660
    { 0, 0, 0, 0 },
23661
    { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
23662
    & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0xa62e0000 }
23663
  },
23664
/* rorc.b ${Dsp-16-u8}[sb] */
23665
  {
23666
    { 0, 0, 0, 0 },
23667
    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
23668
    & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0xa2ae00 }
23669
  },
23670
/* rorc.b ${Dsp-16-u16}[sb] */
23671
  {
23672
    { 0, 0, 0, 0 },
23673
    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
23674
    & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0xa4ae0000 }
23675
  },
23676
/* rorc.b ${Dsp-16-s8}[fb] */
23677
  {
23678
    { 0, 0, 0, 0 },
23679
    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
23680
    & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0xa2ee00 }
23681
  },
23682
/* rorc.b ${Dsp-16-s16}[fb] */
23683
  {
23684
    { 0, 0, 0, 0 },
23685
    { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
23686
    & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0xa4ee0000 }
23687
  },
23688
/* rorc.b ${Dsp-16-u16} */
23689
  {
23690
    { 0, 0, 0, 0 },
23691
    { { MNEM, ' ', OP (DSP_16_U16), 0 } },
23692
    & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0xa6ee0000 }
23693
  },
23694
/* rorc.b ${Dsp-16-u24} */
23695
  {
23696
    { 0, 0, 0, 0 },
23697
    { { MNEM, ' ', OP (DSP_16_U24), 0 } },
23698
    & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0xa6ae0000 }
23699
  },
23700
/* rorc.w $Dst16RnHI */
23701
  {
23702
    { 0, 0, 0, 0 },
23703
    { { MNEM, ' ', OP (DST16RNHI), 0 } },
23704
    & ifmt_rorc16_w_16_dst16_Rn_direct_HI, { 0x77b0 }
23705
  },
23706
/* rorc.w $Dst16AnHI */
23707
  {
23708
    { 0, 0, 0, 0 },
23709
    { { MNEM, ' ', OP (DST16ANHI), 0 } },
23710
    & ifmt_rorc16_w_16_dst16_An_direct_HI, { 0x77b4 }
23711
  },
23712
/* rorc.w [$Dst16An] */
23713
  {
23714
    { 0, 0, 0, 0 },
23715
    { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } },
23716
    & ifmt_rorc16_w_16_dst16_An_indirect_HI, { 0x77b6 }
23717
  },
23718
/* rorc.w ${Dsp-16-u8}[$Dst16An] */
23719
  {
23720
    { 0, 0, 0, 0 },
23721
    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
23722
    & ifmt_rorc16_w_16_dst16_16_8_An_relative_HI, { 0x77b800 }
23723
  },
23724
/* rorc.w ${Dsp-16-u16}[$Dst16An] */
23725
  {
23726
    { 0, 0, 0, 0 },
23727
    { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
23728
    & ifmt_rorc16_w_16_dst16_16_16_An_relative_HI, { 0x77bc0000 }
23729
  },
23730
/* rorc.w ${Dsp-16-u8}[sb] */
23731
  {
23732
    { 0, 0, 0, 0 },
23733
    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
23734
    & ifmt_rorc16_w_16_dst16_16_8_SB_relative_HI, { 0x77ba00 }
23735
  },
23736
/* rorc.w ${Dsp-16-u16}[sb] */
23737
  {
23738
    { 0, 0, 0, 0 },
23739
    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
23740
    & ifmt_rorc16_w_16_dst16_16_16_SB_relative_HI, { 0x77be0000 }
23741
  },
23742
/* rorc.w ${Dsp-16-s8}[fb] */
23743
  {
23744
    { 0, 0, 0, 0 },
23745
    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
23746
    & ifmt_rorc16_w_16_dst16_16_8_FB_relative_HI, { 0x77bb00 }
23747
  },
23748
/* rorc.w ${Dsp-16-u16} */
23749
  {
23750
    { 0, 0, 0, 0 },
23751
    { { MNEM, ' ', OP (DSP_16_U16), 0 } },
23752
    & ifmt_rorc16_w_16_dst16_16_16_absolute_HI, { 0x77bf0000 }
23753
  },
23754
/* rorc.b $Dst16RnQI */
23755
  {
23756
    { 0, 0, 0, 0 },
23757
    { { MNEM, ' ', OP (DST16RNQI), 0 } },
23758
    & ifmt_rorc16_b_16_dst16_Rn_direct_QI, { 0x76b0 }
23759
  },
23760
/* rorc.b $Dst16AnQI */
23761
  {
23762
    { 0, 0, 0, 0 },
23763
    { { MNEM, ' ', OP (DST16ANQI), 0 } },
23764
    & ifmt_rorc16_b_16_dst16_An_direct_QI, { 0x76b4 }
23765
  },
23766
/* rorc.b [$Dst16An] */
23767
  {
23768
    { 0, 0, 0, 0 },
23769
    { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } },
23770
    & ifmt_rorc16_b_16_dst16_An_indirect_QI, { 0x76b6 }
23771
  },
23772
/* rorc.b ${Dsp-16-u8}[$Dst16An] */
23773
  {
23774
    { 0, 0, 0, 0 },
23775
    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
23776
    & ifmt_rorc16_b_16_dst16_16_8_An_relative_QI, { 0x76b800 }
23777
  },
23778
/* rorc.b ${Dsp-16-u16}[$Dst16An] */
23779
  {
23780
    { 0, 0, 0, 0 },
23781
    { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
23782
    & ifmt_rorc16_b_16_dst16_16_16_An_relative_QI, { 0x76bc0000 }
23783
  },
23784
/* rorc.b ${Dsp-16-u8}[sb] */
23785
  {
23786
    { 0, 0, 0, 0 },
23787
    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
23788
    & ifmt_rorc16_b_16_dst16_16_8_SB_relative_QI, { 0x76ba00 }
23789
  },
23790
/* rorc.b ${Dsp-16-u16}[sb] */
23791
  {
23792
    { 0, 0, 0, 0 },
23793
    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
23794
    & ifmt_rorc16_b_16_dst16_16_16_SB_relative_QI, { 0x76be0000 }
23795
  },
23796
/* rorc.b ${Dsp-16-s8}[fb] */
23797
  {
23798
    { 0, 0, 0, 0 },
23799
    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
23800
    & ifmt_rorc16_b_16_dst16_16_8_FB_relative_QI, { 0x76bb00 }
23801
  },
23802
/* rorc.b ${Dsp-16-u16} */
23803
  {
23804
    { 0, 0, 0, 0 },
23805
    { { MNEM, ' ', OP (DSP_16_U16), 0 } },
23806
    & ifmt_rorc16_b_16_dst16_16_16_absolute_QI, { 0x76bf0000 }
23807
  },
23808
/* rolc.w $Dst32RnUnprefixedHI */
23809
  {
23810
    { 0, 0, 0, 0 },
23811
    { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } },
23812
    & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xb92e }
23813
  },
23814
/* rolc.w $Dst32AnUnprefixedHI */
23815
  {
23816
    { 0, 0, 0, 0 },
23817
    { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } },
23818
    & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xb1ae }
23819
  },
23820
/* rolc.w [$Dst32AnUnprefixed] */
23821
  {
23822
    { 0, 0, 0, 0 },
23823
    { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
23824
    & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xb12e }
23825
  },
23826
/* rolc.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
23827
  {
23828
    { 0, 0, 0, 0 },
23829
    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
23830
    & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xb32e00 }
23831
  },
23832
/* rolc.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
23833
  {
23834
    { 0, 0, 0, 0 },
23835
    { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
23836
    & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xb52e0000 }
23837
  },
23838
/* rolc.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
23839
  {
23840
    { 0, 0, 0, 0 },
23841
    { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
23842
    & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xb72e0000 }
23843
  },
23844
/* rolc.w ${Dsp-16-u8}[sb] */
23845
  {
23846
    { 0, 0, 0, 0 },
23847
    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
23848
    & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xb3ae00 }
23849
  },
23850
/* rolc.w ${Dsp-16-u16}[sb] */
23851
  {
23852
    { 0, 0, 0, 0 },
23853
    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
23854
    & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xb5ae0000 }
23855
  },
23856
/* rolc.w ${Dsp-16-s8}[fb] */
23857
  {
23858
    { 0, 0, 0, 0 },
23859
    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
23860
    & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xb3ee00 }
23861
  },
23862
/* rolc.w ${Dsp-16-s16}[fb] */
23863
  {
23864
    { 0, 0, 0, 0 },
23865
    { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
23866
    & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xb5ee0000 }
23867
  },
23868
/* rolc.w ${Dsp-16-u16} */
23869
  {
23870
    { 0, 0, 0, 0 },
23871
    { { MNEM, ' ', OP (DSP_16_U16), 0 } },
23872
    & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xb7ee0000 }
23873
  },
23874
/* rolc.w ${Dsp-16-u24} */
23875
  {
23876
    { 0, 0, 0, 0 },
23877
    { { MNEM, ' ', OP (DSP_16_U24), 0 } },
23878
    & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xb7ae0000 }
23879
  },
23880
/* rolc.b $Dst32RnUnprefixedQI */
23881
  {
23882
    { 0, 0, 0, 0 },
23883
    { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } },
23884
    & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0xb82e }
23885
  },
23886
/* rolc.b $Dst32AnUnprefixedQI */
23887
  {
23888
    { 0, 0, 0, 0 },
23889
    { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } },
23890
    & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0xb0ae }
23891
  },
23892
/* rolc.b [$Dst32AnUnprefixed] */
23893
  {
23894
    { 0, 0, 0, 0 },
23895
    { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
23896
    & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0xb02e }
23897
  },
23898
/* rolc.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
23899
  {
23900
    { 0, 0, 0, 0 },
23901
    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
23902
    & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0xb22e00 }
23903
  },
23904
/* rolc.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
23905
  {
23906
    { 0, 0, 0, 0 },
23907
    { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
23908
    & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0xb42e0000 }
23909
  },
23910
/* rolc.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
23911
  {
23912
    { 0, 0, 0, 0 },
23913
    { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
23914
    & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0xb62e0000 }
23915
  },
23916
/* rolc.b ${Dsp-16-u8}[sb] */
23917
  {
23918
    { 0, 0, 0, 0 },
23919
    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
23920
    & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0xb2ae00 }
23921
  },
23922
/* rolc.b ${Dsp-16-u16}[sb] */
23923
  {
23924
    { 0, 0, 0, 0 },
23925
    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
23926
    & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0xb4ae0000 }
23927
  },
23928
/* rolc.b ${Dsp-16-s8}[fb] */
23929
  {
23930
    { 0, 0, 0, 0 },
23931
    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
23932
    & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0xb2ee00 }
23933
  },
23934
/* rolc.b ${Dsp-16-s16}[fb] */
23935
  {
23936
    { 0, 0, 0, 0 },
23937
    { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
23938
    & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0xb4ee0000 }
23939
  },
23940
/* rolc.b ${Dsp-16-u16} */
23941
  {
23942
    { 0, 0, 0, 0 },
23943
    { { MNEM, ' ', OP (DSP_16_U16), 0 } },
23944
    & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0xb6ee0000 }
23945
  },
23946
/* rolc.b ${Dsp-16-u24} */
23947
  {
23948
    { 0, 0, 0, 0 },
23949
    { { MNEM, ' ', OP (DSP_16_U24), 0 } },
23950
    & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0xb6ae0000 }
23951
  },
23952
/* rolc.w $Dst16RnHI */
23953
  {
23954
    { 0, 0, 0, 0 },
23955
    { { MNEM, ' ', OP (DST16RNHI), 0 } },
23956
    & ifmt_rorc16_w_16_dst16_Rn_direct_HI, { 0x77a0 }
23957
  },
23958
/* rolc.w $Dst16AnHI */
23959
  {
23960
    { 0, 0, 0, 0 },
23961
    { { MNEM, ' ', OP (DST16ANHI), 0 } },
23962
    & ifmt_rorc16_w_16_dst16_An_direct_HI, { 0x77a4 }
23963
  },
23964
/* rolc.w [$Dst16An] */
23965
  {
23966
    { 0, 0, 0, 0 },
23967
    { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } },
23968
    & ifmt_rorc16_w_16_dst16_An_indirect_HI, { 0x77a6 }
23969
  },
23970
/* rolc.w ${Dsp-16-u8}[$Dst16An] */
23971
  {
23972
    { 0, 0, 0, 0 },
23973
    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
23974
    & ifmt_rorc16_w_16_dst16_16_8_An_relative_HI, { 0x77a800 }
23975
  },
23976
/* rolc.w ${Dsp-16-u16}[$Dst16An] */
23977
  {
23978
    { 0, 0, 0, 0 },
23979
    { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
23980
    & ifmt_rorc16_w_16_dst16_16_16_An_relative_HI, { 0x77ac0000 }
23981
  },
23982
/* rolc.w ${Dsp-16-u8}[sb] */
23983
  {
23984
    { 0, 0, 0, 0 },
23985
    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
23986
    & ifmt_rorc16_w_16_dst16_16_8_SB_relative_HI, { 0x77aa00 }
23987
  },
23988
/* rolc.w ${Dsp-16-u16}[sb] */
23989
  {
23990
    { 0, 0, 0, 0 },
23991
    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
23992
    & ifmt_rorc16_w_16_dst16_16_16_SB_relative_HI, { 0x77ae0000 }
23993
  },
23994
/* rolc.w ${Dsp-16-s8}[fb] */
23995
  {
23996
    { 0, 0, 0, 0 },
23997
    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
23998
    & ifmt_rorc16_w_16_dst16_16_8_FB_relative_HI, { 0x77ab00 }
23999
  },
24000
/* rolc.w ${Dsp-16-u16} */
24001
  {
24002
    { 0, 0, 0, 0 },
24003
    { { MNEM, ' ', OP (DSP_16_U16), 0 } },
24004
    & ifmt_rorc16_w_16_dst16_16_16_absolute_HI, { 0x77af0000 }
24005
  },
24006
/* rolc.b $Dst16RnQI */
24007
  {
24008
    { 0, 0, 0, 0 },
24009
    { { MNEM, ' ', OP (DST16RNQI), 0 } },
24010
    & ifmt_rorc16_b_16_dst16_Rn_direct_QI, { 0x76a0 }
24011
  },
24012
/* rolc.b $Dst16AnQI */
24013
  {
24014
    { 0, 0, 0, 0 },
24015
    { { MNEM, ' ', OP (DST16ANQI), 0 } },
24016
    & ifmt_rorc16_b_16_dst16_An_direct_QI, { 0x76a4 }
24017
  },
24018
/* rolc.b [$Dst16An] */
24019
  {
24020
    { 0, 0, 0, 0 },
24021
    { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } },
24022
    & ifmt_rorc16_b_16_dst16_An_indirect_QI, { 0x76a6 }
24023
  },
24024
/* rolc.b ${Dsp-16-u8}[$Dst16An] */
24025
  {
24026
    { 0, 0, 0, 0 },
24027
    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
24028
    & ifmt_rorc16_b_16_dst16_16_8_An_relative_QI, { 0x76a800 }
24029
  },
24030
/* rolc.b ${Dsp-16-u16}[$Dst16An] */
24031
  {
24032
    { 0, 0, 0, 0 },
24033
    { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
24034
    & ifmt_rorc16_b_16_dst16_16_16_An_relative_QI, { 0x76ac0000 }
24035
  },
24036
/* rolc.b ${Dsp-16-u8}[sb] */
24037
  {
24038
    { 0, 0, 0, 0 },
24039
    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
24040
    & ifmt_rorc16_b_16_dst16_16_8_SB_relative_QI, { 0x76aa00 }
24041
  },
24042
/* rolc.b ${Dsp-16-u16}[sb] */
24043
  {
24044
    { 0, 0, 0, 0 },
24045
    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
24046
    & ifmt_rorc16_b_16_dst16_16_16_SB_relative_QI, { 0x76ae0000 }
24047
  },
24048
/* rolc.b ${Dsp-16-s8}[fb] */
24049
  {
24050
    { 0, 0, 0, 0 },
24051
    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
24052
    & ifmt_rorc16_b_16_dst16_16_8_FB_relative_QI, { 0x76ab00 }
24053
  },
24054
/* rolc.b ${Dsp-16-u16} */
24055
  {
24056
    { 0, 0, 0, 0 },
24057
    { { MNEM, ' ', OP (DSP_16_U16), 0 } },
24058
    & ifmt_rorc16_b_16_dst16_16_16_absolute_QI, { 0x76af0000 }
24059
  },
24060
/* pusha [$Dst32AnUnprefixed] */
24061
  {
24062
    { 0, 0, 0, 0 },
24063
    { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24064
    & ifmt_pusha32_16_Unprefixed_Mova_dst32_An_indirect_Unprefixed_Mova_SI, { 0xb001 }
24065
  },
24066
/* pusha ${Dsp-16-u8}[$Dst32AnUnprefixed] */
24067
  {
24068
    { 0, 0, 0, 0 },
24069
    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24070
    & ifmt_pusha32_16_Unprefixed_Mova_dst32_16_8_An_relative_Unprefixed_Mova_SI, { 0xb20100 }
24071
  },
24072
/* pusha ${Dsp-16-u16}[$Dst32AnUnprefixed] */
24073
  {
24074
    { 0, 0, 0, 0 },
24075
    { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24076
    & ifmt_pusha32_16_Unprefixed_Mova_dst32_16_16_An_relative_Unprefixed_Mova_SI, { 0xb4010000 }
24077
  },
24078
/* pusha ${Dsp-16-u24}[$Dst32AnUnprefixed] */
24079
  {
24080
    { 0, 0, 0, 0 },
24081
    { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24082
    & ifmt_pusha32_16_Unprefixed_Mova_dst32_16_24_An_relative_Unprefixed_Mova_SI, { 0xb6010000 }
24083
  },
24084
/* pusha ${Dsp-16-u8}[sb] */
24085
  {
24086
    { 0, 0, 0, 0 },
24087
    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
24088
    & ifmt_pusha32_16_Unprefixed_Mova_dst32_16_8_SB_relative_Unprefixed_Mova_SI, { 0xb28100 }
24089
  },
24090
/* pusha ${Dsp-16-u16}[sb] */
24091
  {
24092
    { 0, 0, 0, 0 },
24093
    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
24094
    & ifmt_pusha32_16_Unprefixed_Mova_dst32_16_16_SB_relative_Unprefixed_Mova_SI, { 0xb4810000 }
24095
  },
24096
/* pusha ${Dsp-16-s8}[fb] */
24097
  {
24098
    { 0, 0, 0, 0 },
24099
    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
24100
    & ifmt_pusha32_16_Unprefixed_Mova_dst32_16_8_FB_relative_Unprefixed_Mova_SI, { 0xb2c100 }
24101
  },
24102
/* pusha ${Dsp-16-s16}[fb] */
24103
  {
24104
    { 0, 0, 0, 0 },
24105
    { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
24106
    & ifmt_pusha32_16_Unprefixed_Mova_dst32_16_16_FB_relative_Unprefixed_Mova_SI, { 0xb4c10000 }
24107
  },
24108
/* pusha ${Dsp-16-u16} */
24109
  {
24110
    { 0, 0, 0, 0 },
24111
    { { MNEM, ' ', OP (DSP_16_U16), 0 } },
24112
    & ifmt_pusha32_16_Unprefixed_Mova_dst32_16_16_absolute_Unprefixed_Mova_SI, { 0xb6c10000 }
24113
  },
24114
/* pusha ${Dsp-16-u24} */
24115
  {
24116
    { 0, 0, 0, 0 },
24117
    { { MNEM, ' ', OP (DSP_16_U24), 0 } },
24118
    & ifmt_pusha32_16_Unprefixed_Mova_dst32_16_24_absolute_Unprefixed_Mova_SI, { 0xb6810000 }
24119
  },
24120
/* pusha [$Dst16An] */
24121
  {
24122
    { 0, 0, 0, 0 },
24123
    { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } },
24124
    & ifmt_pusha16_16_Mova_dst16_An_indirect_Mova_HI, { 0x7d96 }
24125
  },
24126
/* pusha ${Dsp-16-u8}[$Dst16An] */
24127
  {
24128
    { 0, 0, 0, 0 },
24129
    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
24130
    & ifmt_pusha16_16_Mova_dst16_16_8_An_relative_Mova_HI, { 0x7d9800 }
24131
  },
24132
/* pusha ${Dsp-16-u16}[$Dst16An] */
24133
  {
24134
    { 0, 0, 0, 0 },
24135
    { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
24136
    & ifmt_pusha16_16_Mova_dst16_16_16_An_relative_Mova_HI, { 0x7d9c0000 }
24137
  },
24138
/* pusha ${Dsp-16-u8}[sb] */
24139
  {
24140
    { 0, 0, 0, 0 },
24141
    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
24142
    & ifmt_pusha16_16_Mova_dst16_16_8_SB_relative_Mova_HI, { 0x7d9a00 }
24143
  },
24144
/* pusha ${Dsp-16-u16}[sb] */
24145
  {
24146
    { 0, 0, 0, 0 },
24147
    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
24148
    & ifmt_pusha16_16_Mova_dst16_16_16_SB_relative_Mova_HI, { 0x7d9e0000 }
24149
  },
24150
/* pusha ${Dsp-16-s8}[fb] */
24151
  {
24152
    { 0, 0, 0, 0 },
24153
    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
24154
    & ifmt_pusha16_16_Mova_dst16_16_8_FB_relative_Mova_HI, { 0x7d9b00 }
24155
  },
24156
/* pusha ${Dsp-16-u16} */
24157
  {
24158
    { 0, 0, 0, 0 },
24159
    { { MNEM, ' ', OP (DSP_16_U16), 0 } },
24160
    & ifmt_pusha16_16_Mova_dst16_16_16_absolute_Mova_HI, { 0x7d9f0000 }
24161
  },
24162
/* push.l $Dst32RnUnprefixedSI */
24163
  {
24164
    { 0, 0, 0, 0 },
24165
    { { MNEM, ' ', OP (DST32RNUNPREFIXEDSI), 0 } },
24166
    & ifmt_shl32_l_dst_dst32_Rn_direct_Unprefixed_SI, { 0xa801 }
24167
  },
24168
/* push.l $Dst32AnUnprefixedSI */
24169
  {
24170
    { 0, 0, 0, 0 },
24171
    { { MNEM, ' ', OP (DST32ANUNPREFIXEDSI), 0 } },
24172
    & ifmt_exts32_w_16_ExtUnprefixed_dst32_An_direct_Unprefixed_SI, { 0xa081 }
24173
  },
24174
/* push.l [$Dst32AnUnprefixed] */
24175
  {
24176
    { 0, 0, 0, 0 },
24177
    { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24178
    & ifmt_shl32_l_dst_dst32_An_indirect_Unprefixed_SI, { 0xa001 }
24179
  },
24180
/* push.l ${Dsp-16-u8}[$Dst32AnUnprefixed] */
24181
  {
24182
    { 0, 0, 0, 0 },
24183
    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24184
    & ifmt_shl32_l_dst_dst32_16_8_An_relative_Unprefixed_SI, { 0xa20100 }
24185
  },
24186
/* push.l ${Dsp-16-u16}[$Dst32AnUnprefixed] */
24187
  {
24188
    { 0, 0, 0, 0 },
24189
    { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24190
    & ifmt_shl32_l_dst_dst32_16_16_An_relative_Unprefixed_SI, { 0xa4010000 }
24191
  },
24192
/* push.l ${Dsp-16-u24}[$Dst32AnUnprefixed] */
24193
  {
24194
    { 0, 0, 0, 0 },
24195
    { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24196
    & ifmt_shl32_l_dst_dst32_16_24_An_relative_Unprefixed_SI, { 0xa6010000 }
24197
  },
24198
/* push.l ${Dsp-16-u8}[sb] */
24199
  {
24200
    { 0, 0, 0, 0 },
24201
    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
24202
    & ifmt_shl32_l_dst_dst32_16_8_SB_relative_Unprefixed_SI, { 0xa28100 }
24203
  },
24204
/* push.l ${Dsp-16-u16}[sb] */
24205
  {
24206
    { 0, 0, 0, 0 },
24207
    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
24208
    & ifmt_shl32_l_dst_dst32_16_16_SB_relative_Unprefixed_SI, { 0xa4810000 }
24209
  },
24210
/* push.l ${Dsp-16-s8}[fb] */
24211
  {
24212
    { 0, 0, 0, 0 },
24213
    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
24214
    & ifmt_shl32_l_dst_dst32_16_8_FB_relative_Unprefixed_SI, { 0xa2c100 }
24215
  },
24216
/* push.l ${Dsp-16-s16}[fb] */
24217
  {
24218
    { 0, 0, 0, 0 },
24219
    { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
24220
    & ifmt_shl32_l_dst_dst32_16_16_FB_relative_Unprefixed_SI, { 0xa4c10000 }
24221
  },
24222
/* push.l ${Dsp-16-u16} */
24223
  {
24224
    { 0, 0, 0, 0 },
24225
    { { MNEM, ' ', OP (DSP_16_U16), 0 } },
24226
    & ifmt_shl32_l_dst_dst32_16_16_absolute_Unprefixed_SI, { 0xa6c10000 }
24227
  },
24228
/* push.l ${Dsp-16-u24} */
24229
  {
24230
    { 0, 0, 0, 0 },
24231
    { { MNEM, ' ', OP (DSP_16_U24), 0 } },
24232
    & ifmt_shl32_l_dst_dst32_16_24_absolute_Unprefixed_SI, { 0xa6810000 }
24233
  },
24234
/* push.w${S} ${An16-push-S} */
24235
  {
24236
    { 0, 0, 0, 0 },
24237
    { { MNEM, OP (S), ' ', OP (AN16_PUSH_S), 0 } },
24238
    & ifmt_push16_b_s_an_An16_push_S_derived, { 0xc2 }
24239
  },
24240
/* push.b${S} ${Rn16-push-S} */
24241
  {
24242
    { 0, 0, 0, 0 },
24243
    { { MNEM, OP (S), ' ', OP (RN16_PUSH_S), 0 } },
24244
    & ifmt_push16_b_s_rn_Rn16_push_S_derived, { 0x82 }
24245
  },
24246
/* push.w $Dst32RnUnprefixedHI */
24247
  {
24248
    { 0, 0, 0, 0 },
24249
    { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } },
24250
    & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xc90e }
24251
  },
24252
/* push.w $Dst32AnUnprefixedHI */
24253
  {
24254
    { 0, 0, 0, 0 },
24255
    { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } },
24256
    & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xc18e }
24257
  },
24258
/* push.w [$Dst32AnUnprefixed] */
24259
  {
24260
    { 0, 0, 0, 0 },
24261
    { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24262
    & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xc10e }
24263
  },
24264
/* push.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
24265
  {
24266
    { 0, 0, 0, 0 },
24267
    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24268
    & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xc30e00 }
24269
  },
24270
/* push.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
24271
  {
24272
    { 0, 0, 0, 0 },
24273
    { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24274
    & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xc50e0000 }
24275
  },
24276
/* push.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
24277
  {
24278
    { 0, 0, 0, 0 },
24279
    { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24280
    & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xc70e0000 }
24281
  },
24282
/* push.w ${Dsp-16-u8}[sb] */
24283
  {
24284
    { 0, 0, 0, 0 },
24285
    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
24286
    & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xc38e00 }
24287
  },
24288
/* push.w ${Dsp-16-u16}[sb] */
24289
  {
24290
    { 0, 0, 0, 0 },
24291
    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
24292
    & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xc58e0000 }
24293
  },
24294
/* push.w ${Dsp-16-s8}[fb] */
24295
  {
24296
    { 0, 0, 0, 0 },
24297
    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
24298
    & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xc3ce00 }
24299
  },
24300
/* push.w ${Dsp-16-s16}[fb] */
24301
  {
24302
    { 0, 0, 0, 0 },
24303
    { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
24304
    & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xc5ce0000 }
24305
  },
24306
/* push.w ${Dsp-16-u16} */
24307
  {
24308
    { 0, 0, 0, 0 },
24309
    { { MNEM, ' ', OP (DSP_16_U16), 0 } },
24310
    & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xc7ce0000 }
24311
  },
24312
/* push.w ${Dsp-16-u24} */
24313
  {
24314
    { 0, 0, 0, 0 },
24315
    { { MNEM, ' ', OP (DSP_16_U24), 0 } },
24316
    & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xc78e0000 }
24317
  },
24318
/* push.b $Dst32RnUnprefixedQI */
24319
  {
24320
    { 0, 0, 0, 0 },
24321
    { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } },
24322
    & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0xc80e }
24323
  },
24324
/* push.b $Dst32AnUnprefixedQI */
24325
  {
24326
    { 0, 0, 0, 0 },
24327
    { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } },
24328
    & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0xc08e }
24329
  },
24330
/* push.b [$Dst32AnUnprefixed] */
24331
  {
24332
    { 0, 0, 0, 0 },
24333
    { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24334
    & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0xc00e }
24335
  },
24336
/* push.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
24337
  {
24338
    { 0, 0, 0, 0 },
24339
    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24340
    & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0xc20e00 }
24341
  },
24342
/* push.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
24343
  {
24344
    { 0, 0, 0, 0 },
24345
    { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24346
    & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0xc40e0000 }
24347
  },
24348
/* push.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
24349
  {
24350
    { 0, 0, 0, 0 },
24351
    { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24352
    & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0xc60e0000 }
24353
  },
24354
/* push.b ${Dsp-16-u8}[sb] */
24355
  {
24356
    { 0, 0, 0, 0 },
24357
    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
24358
    & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0xc28e00 }
24359
  },
24360
/* push.b ${Dsp-16-u16}[sb] */
24361
  {
24362
    { 0, 0, 0, 0 },
24363
    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
24364
    & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0xc48e0000 }
24365
  },
24366
/* push.b ${Dsp-16-s8}[fb] */
24367
  {
24368
    { 0, 0, 0, 0 },
24369
    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
24370
    & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0xc2ce00 }
24371
  },
24372
/* push.b ${Dsp-16-s16}[fb] */
24373
  {
24374
    { 0, 0, 0, 0 },
24375
    { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
24376
    & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0xc4ce0000 }
24377
  },
24378
/* push.b ${Dsp-16-u16} */
24379
  {
24380
    { 0, 0, 0, 0 },
24381
    { { MNEM, ' ', OP (DSP_16_U16), 0 } },
24382
    & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0xc6ce0000 }
24383
  },
24384
/* push.b ${Dsp-16-u24} */
24385
  {
24386
    { 0, 0, 0, 0 },
24387
    { { MNEM, ' ', OP (DSP_16_U24), 0 } },
24388
    & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0xc68e0000 }
24389
  },
24390
/* push.w${G} $Dst16RnHI */
24391
  {
24392
    { 0, 0, 0, 0 },
24393
    { { MNEM, OP (G), ' ', OP (DST16RNHI), 0 } },
24394
    & ifmt_rorc16_w_16_dst16_Rn_direct_HI, { 0x7540 }
24395
  },
24396
/* push.w${G} $Dst16AnHI */
24397
  {
24398
    { 0, 0, 0, 0 },
24399
    { { MNEM, OP (G), ' ', OP (DST16ANHI), 0 } },
24400
    & ifmt_rorc16_w_16_dst16_An_direct_HI, { 0x7544 }
24401
  },
24402
/* push.w${G} [$Dst16An] */
24403
  {
24404
    { 0, 0, 0, 0 },
24405
    { { MNEM, OP (G), ' ', '[', OP (DST16AN), ']', 0 } },
24406
    & ifmt_rorc16_w_16_dst16_An_indirect_HI, { 0x7546 }
24407
  },
24408
/* push.w${G} ${Dsp-16-u8}[$Dst16An] */
24409
  {
24410
    { 0, 0, 0, 0 },
24411
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
24412
    & ifmt_rorc16_w_16_dst16_16_8_An_relative_HI, { 0x754800 }
24413
  },
24414
/* push.w${G} ${Dsp-16-u16}[$Dst16An] */
24415
  {
24416
    { 0, 0, 0, 0 },
24417
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
24418
    & ifmt_rorc16_w_16_dst16_16_16_An_relative_HI, { 0x754c0000 }
24419
  },
24420
/* push.w${G} ${Dsp-16-u8}[sb] */
24421
  {
24422
    { 0, 0, 0, 0 },
24423
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
24424
    & ifmt_rorc16_w_16_dst16_16_8_SB_relative_HI, { 0x754a00 }
24425
  },
24426
/* push.w${G} ${Dsp-16-u16}[sb] */
24427
  {
24428
    { 0, 0, 0, 0 },
24429
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
24430
    & ifmt_rorc16_w_16_dst16_16_16_SB_relative_HI, { 0x754e0000 }
24431
  },
24432
/* push.w${G} ${Dsp-16-s8}[fb] */
24433
  {
24434
    { 0, 0, 0, 0 },
24435
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
24436
    & ifmt_rorc16_w_16_dst16_16_8_FB_relative_HI, { 0x754b00 }
24437
  },
24438
/* push.w${G} ${Dsp-16-u16} */
24439
  {
24440
    { 0, 0, 0, 0 },
24441
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), 0 } },
24442
    & ifmt_rorc16_w_16_dst16_16_16_absolute_HI, { 0x754f0000 }
24443
  },
24444
/* push.b${G} $Dst16RnQI */
24445
  {
24446
    { 0, 0, 0, 0 },
24447
    { { MNEM, OP (G), ' ', OP (DST16RNQI), 0 } },
24448
    & ifmt_rorc16_b_16_dst16_Rn_direct_QI, { 0x7440 }
24449
  },
24450
/* push.b${G} $Dst16AnQI */
24451
  {
24452
    { 0, 0, 0, 0 },
24453
    { { MNEM, OP (G), ' ', OP (DST16ANQI), 0 } },
24454
    & ifmt_rorc16_b_16_dst16_An_direct_QI, { 0x7444 }
24455
  },
24456
/* push.b${G} [$Dst16An] */
24457
  {
24458
    { 0, 0, 0, 0 },
24459
    { { MNEM, OP (G), ' ', '[', OP (DST16AN), ']', 0 } },
24460
    & ifmt_rorc16_b_16_dst16_An_indirect_QI, { 0x7446 }
24461
  },
24462
/* push.b${G} ${Dsp-16-u8}[$Dst16An] */
24463
  {
24464
    { 0, 0, 0, 0 },
24465
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
24466
    & ifmt_rorc16_b_16_dst16_16_8_An_relative_QI, { 0x744800 }
24467
  },
24468
/* push.b${G} ${Dsp-16-u16}[$Dst16An] */
24469
  {
24470
    { 0, 0, 0, 0 },
24471
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
24472
    & ifmt_rorc16_b_16_dst16_16_16_An_relative_QI, { 0x744c0000 }
24473
  },
24474
/* push.b${G} ${Dsp-16-u8}[sb] */
24475
  {
24476
    { 0, 0, 0, 0 },
24477
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
24478
    & ifmt_rorc16_b_16_dst16_16_8_SB_relative_QI, { 0x744a00 }
24479
  },
24480
/* push.b${G} ${Dsp-16-u16}[sb] */
24481
  {
24482
    { 0, 0, 0, 0 },
24483
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
24484
    & ifmt_rorc16_b_16_dst16_16_16_SB_relative_QI, { 0x744e0000 }
24485
  },
24486
/* push.b${G} ${Dsp-16-s8}[fb] */
24487
  {
24488
    { 0, 0, 0, 0 },
24489
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
24490
    & ifmt_rorc16_b_16_dst16_16_8_FB_relative_QI, { 0x744b00 }
24491
  },
24492
/* push.b${G} ${Dsp-16-u16} */
24493
  {
24494
    { 0, 0, 0, 0 },
24495
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), 0 } },
24496
    & ifmt_rorc16_b_16_dst16_16_16_absolute_QI, { 0x744f0000 }
24497
  },
24498
/* pop.w${S} ${An16-push-S} */
24499
  {
24500
    { 0, 0, 0, 0 },
24501
    { { MNEM, OP (S), ' ', OP (AN16_PUSH_S), 0 } },
24502
    & ifmt_push16_b_s_an_An16_push_S_derived, { 0xd2 }
24503
  },
24504
/* pop.b${S} ${Rn16-push-S} */
24505
  {
24506
    { 0, 0, 0, 0 },
24507
    { { MNEM, OP (S), ' ', OP (RN16_PUSH_S), 0 } },
24508
    & ifmt_push16_b_s_rn_Rn16_push_S_derived, { 0x92 }
24509
  },
24510
/* pop.w $Dst32RnUnprefixedHI */
24511
  {
24512
    { 0, 0, 0, 0 },
24513
    { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } },
24514
    & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xb92f }
24515
  },
24516
/* pop.w $Dst32AnUnprefixedHI */
24517
  {
24518
    { 0, 0, 0, 0 },
24519
    { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } },
24520
    & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xb1af }
24521
  },
24522
/* pop.w [$Dst32AnUnprefixed] */
24523
  {
24524
    { 0, 0, 0, 0 },
24525
    { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24526
    & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xb12f }
24527
  },
24528
/* pop.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
24529
  {
24530
    { 0, 0, 0, 0 },
24531
    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24532
    & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xb32f00 }
24533
  },
24534
/* pop.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
24535
  {
24536
    { 0, 0, 0, 0 },
24537
    { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24538
    & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xb52f0000 }
24539
  },
24540
/* pop.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
24541
  {
24542
    { 0, 0, 0, 0 },
24543
    { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24544
    & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xb72f0000 }
24545
  },
24546
/* pop.w ${Dsp-16-u8}[sb] */
24547
  {
24548
    { 0, 0, 0, 0 },
24549
    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
24550
    & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xb3af00 }
24551
  },
24552
/* pop.w ${Dsp-16-u16}[sb] */
24553
  {
24554
    { 0, 0, 0, 0 },
24555
    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
24556
    & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xb5af0000 }
24557
  },
24558
/* pop.w ${Dsp-16-s8}[fb] */
24559
  {
24560
    { 0, 0, 0, 0 },
24561
    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
24562
    & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xb3ef00 }
24563
  },
24564
/* pop.w ${Dsp-16-s16}[fb] */
24565
  {
24566
    { 0, 0, 0, 0 },
24567
    { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
24568
    & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xb5ef0000 }
24569
  },
24570
/* pop.w ${Dsp-16-u16} */
24571
  {
24572
    { 0, 0, 0, 0 },
24573
    { { MNEM, ' ', OP (DSP_16_U16), 0 } },
24574
    & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xb7ef0000 }
24575
  },
24576
/* pop.w ${Dsp-16-u24} */
24577
  {
24578
    { 0, 0, 0, 0 },
24579
    { { MNEM, ' ', OP (DSP_16_U24), 0 } },
24580
    & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xb7af0000 }
24581
  },
24582
/* pop.b $Dst32RnUnprefixedQI */
24583
  {
24584
    { 0, 0, 0, 0 },
24585
    { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } },
24586
    & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0xb82f }
24587
  },
24588
/* pop.b $Dst32AnUnprefixedQI */
24589
  {
24590
    { 0, 0, 0, 0 },
24591
    { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } },
24592
    & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0xb0af }
24593
  },
24594
/* pop.b [$Dst32AnUnprefixed] */
24595
  {
24596
    { 0, 0, 0, 0 },
24597
    { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24598
    & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0xb02f }
24599
  },
24600
/* pop.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
24601
  {
24602
    { 0, 0, 0, 0 },
24603
    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24604
    & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0xb22f00 }
24605
  },
24606
/* pop.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
24607
  {
24608
    { 0, 0, 0, 0 },
24609
    { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24610
    & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0xb42f0000 }
24611
  },
24612
/* pop.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
24613
  {
24614
    { 0, 0, 0, 0 },
24615
    { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24616
    & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0xb62f0000 }
24617
  },
24618
/* pop.b ${Dsp-16-u8}[sb] */
24619
  {
24620
    { 0, 0, 0, 0 },
24621
    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
24622
    & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0xb2af00 }
24623
  },
24624
/* pop.b ${Dsp-16-u16}[sb] */
24625
  {
24626
    { 0, 0, 0, 0 },
24627
    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
24628
    & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0xb4af0000 }
24629
  },
24630
/* pop.b ${Dsp-16-s8}[fb] */
24631
  {
24632
    { 0, 0, 0, 0 },
24633
    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
24634
    & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0xb2ef00 }
24635
  },
24636
/* pop.b ${Dsp-16-s16}[fb] */
24637
  {
24638
    { 0, 0, 0, 0 },
24639
    { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
24640
    & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0xb4ef0000 }
24641
  },
24642
/* pop.b ${Dsp-16-u16} */
24643
  {
24644
    { 0, 0, 0, 0 },
24645
    { { MNEM, ' ', OP (DSP_16_U16), 0 } },
24646
    & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0xb6ef0000 }
24647
  },
24648
/* pop.b ${Dsp-16-u24} */
24649
  {
24650
    { 0, 0, 0, 0 },
24651
    { { MNEM, ' ', OP (DSP_16_U24), 0 } },
24652
    & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0xb6af0000 }
24653
  },
24654
/* pop.w${G} $Dst16RnHI */
24655
  {
24656
    { 0, 0, 0, 0 },
24657
    { { MNEM, OP (G), ' ', OP (DST16RNHI), 0 } },
24658
    & ifmt_rorc16_w_16_dst16_Rn_direct_HI, { 0x75d0 }
24659
  },
24660
/* pop.w${G} $Dst16AnHI */
24661
  {
24662
    { 0, 0, 0, 0 },
24663
    { { MNEM, OP (G), ' ', OP (DST16ANHI), 0 } },
24664
    & ifmt_rorc16_w_16_dst16_An_direct_HI, { 0x75d4 }
24665
  },
24666
/* pop.w${G} [$Dst16An] */
24667
  {
24668
    { 0, 0, 0, 0 },
24669
    { { MNEM, OP (G), ' ', '[', OP (DST16AN), ']', 0 } },
24670
    & ifmt_rorc16_w_16_dst16_An_indirect_HI, { 0x75d6 }
24671
  },
24672
/* pop.w${G} ${Dsp-16-u8}[$Dst16An] */
24673
  {
24674
    { 0, 0, 0, 0 },
24675
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
24676
    & ifmt_rorc16_w_16_dst16_16_8_An_relative_HI, { 0x75d800 }
24677
  },
24678
/* pop.w${G} ${Dsp-16-u16}[$Dst16An] */
24679
  {
24680
    { 0, 0, 0, 0 },
24681
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
24682
    & ifmt_rorc16_w_16_dst16_16_16_An_relative_HI, { 0x75dc0000 }
24683
  },
24684
/* pop.w${G} ${Dsp-16-u8}[sb] */
24685
  {
24686
    { 0, 0, 0, 0 },
24687
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
24688
    & ifmt_rorc16_w_16_dst16_16_8_SB_relative_HI, { 0x75da00 }
24689
  },
24690
/* pop.w${G} ${Dsp-16-u16}[sb] */
24691
  {
24692
    { 0, 0, 0, 0 },
24693
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
24694
    & ifmt_rorc16_w_16_dst16_16_16_SB_relative_HI, { 0x75de0000 }
24695
  },
24696
/* pop.w${G} ${Dsp-16-s8}[fb] */
24697
  {
24698
    { 0, 0, 0, 0 },
24699
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
24700
    & ifmt_rorc16_w_16_dst16_16_8_FB_relative_HI, { 0x75db00 }
24701
  },
24702
/* pop.w${G} ${Dsp-16-u16} */
24703
  {
24704
    { 0, 0, 0, 0 },
24705
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), 0 } },
24706
    & ifmt_rorc16_w_16_dst16_16_16_absolute_HI, { 0x75df0000 }
24707
  },
24708
/* pop.b${G} $Dst16RnQI */
24709
  {
24710
    { 0, 0, 0, 0 },
24711
    { { MNEM, OP (G), ' ', OP (DST16RNQI), 0 } },
24712
    & ifmt_rorc16_b_16_dst16_Rn_direct_QI, { 0x74d0 }
24713
  },
24714
/* pop.b${G} $Dst16AnQI */
24715
  {
24716
    { 0, 0, 0, 0 },
24717
    { { MNEM, OP (G), ' ', OP (DST16ANQI), 0 } },
24718
    & ifmt_rorc16_b_16_dst16_An_direct_QI, { 0x74d4 }
24719
  },
24720
/* pop.b${G} [$Dst16An] */
24721
  {
24722
    { 0, 0, 0, 0 },
24723
    { { MNEM, OP (G), ' ', '[', OP (DST16AN), ']', 0 } },
24724
    & ifmt_rorc16_b_16_dst16_An_indirect_QI, { 0x74d6 }
24725
  },
24726
/* pop.b${G} ${Dsp-16-u8}[$Dst16An] */
24727
  {
24728
    { 0, 0, 0, 0 },
24729
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
24730
    & ifmt_rorc16_b_16_dst16_16_8_An_relative_QI, { 0x74d800 }
24731
  },
24732
/* pop.b${G} ${Dsp-16-u16}[$Dst16An] */
24733
  {
24734
    { 0, 0, 0, 0 },
24735
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
24736
    & ifmt_rorc16_b_16_dst16_16_16_An_relative_QI, { 0x74dc0000 }
24737
  },
24738
/* pop.b${G} ${Dsp-16-u8}[sb] */
24739
  {
24740
    { 0, 0, 0, 0 },
24741
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
24742
    & ifmt_rorc16_b_16_dst16_16_8_SB_relative_QI, { 0x74da00 }
24743
  },
24744
/* pop.b${G} ${Dsp-16-u16}[sb] */
24745
  {
24746
    { 0, 0, 0, 0 },
24747
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
24748
    & ifmt_rorc16_b_16_dst16_16_16_SB_relative_QI, { 0x74de0000 }
24749
  },
24750
/* pop.b${G} ${Dsp-16-s8}[fb] */
24751
  {
24752
    { 0, 0, 0, 0 },
24753
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
24754
    & ifmt_rorc16_b_16_dst16_16_8_FB_relative_QI, { 0x74db00 }
24755
  },
24756
/* pop.b${G} ${Dsp-16-u16} */
24757
  {
24758
    { 0, 0, 0, 0 },
24759
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), 0 } },
24760
    & ifmt_rorc16_b_16_dst16_16_16_absolute_QI, { 0x74df0000 }
24761
  },
24762
/* or.b${S} ${SrcDst16-r0l-r0h-S-normal} */
24763
  {
24764
    { 0, 0, 0, 0 },
24765
    { { MNEM, OP (S), ' ', OP (SRCDST16_R0L_R0H_S_NORMAL), 0 } },
24766
    & ifmt_or16_b_S_r0l_r0h_srcdst16_r0l_r0h_S_derived, { 0x18 }
24767
  },
24768
/* or.b${S} ${Dsp-8-u8}[sb],${Dst16RnQI-S} */
24769
  {
24770
    { 0, 0, 0, 0 },
24771
    { { MNEM, OP (S), ' ', OP (DSP_8_U8), '[', 's', 'b', ']', ',', OP (DST16RNQI_S), 0 } },
24772
    & ifmt_or16_b_S_src2_src16_2_S_8_SB_relative_QI, { 0x1900 }
24773
  },
24774
/* or.b${S} ${Dsp-8-s8}[fb],${Dst16RnQI-S} */
24775
  {
24776
    { 0, 0, 0, 0 },
24777
    { { MNEM, OP (S), ' ', OP (DSP_8_S8), '[', 'f', 'b', ']', ',', OP (DST16RNQI_S), 0 } },
24778
    & ifmt_or16_b_S_src2_src16_2_S_8_FB_relative_QI, { 0x1a00 }
24779
  },
24780
/* or.b${S} ${Dsp-8-u16},${Dst16RnQI-S} */
24781
  {
24782
    { 0, 0, 0, 0 },
24783
    { { MNEM, OP (S), ' ', OP (DSP_8_U16), ',', OP (DST16RNQI_S), 0 } },
24784
    & ifmt_or16_b_S_src2_src16_2_S_16_absolute_QI, { 0x1b0000 }
24785
  },
24786
/* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
24787
  {
24788
    { 0, 0, 0, 0 },
24789
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
24790
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x990500 }
24791
  },
24792
/* or.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */
24793
  {
24794
    { 0, 0, 0, 0 },
24795
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
24796
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x992500 }
24797
  },
24798
/* or.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */
24799
  {
24800
    { 0, 0, 0, 0 },
24801
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
24802
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x993500 }
24803
  },
24804
/* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
24805
  {
24806
    { 0, 0, 0, 0 },
24807
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
24808
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x918500 }
24809
  },
24810
/* or.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */
24811
  {
24812
    { 0, 0, 0, 0 },
24813
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
24814
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x91a500 }
24815
  },
24816
/* or.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */
24817
  {
24818
    { 0, 0, 0, 0 },
24819
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
24820
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x91b500 }
24821
  },
24822
/* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
24823
  {
24824
    { 0, 0, 0, 0 },
24825
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24826
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x910500 }
24827
  },
24828
/* or.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
24829
  {
24830
    { 0, 0, 0, 0 },
24831
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24832
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x912500 }
24833
  },
24834
/* or.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
24835
  {
24836
    { 0, 0, 0, 0 },
24837
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24838
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x913500 }
24839
  },
24840
/* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
24841
  {
24842
    { 0, 0, 0, 0 },
24843
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24844
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x93050000 }
24845
  },
24846
/* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
24847
  {
24848
    { 0, 0, 0, 0 },
24849
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24850
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x93250000 }
24851
  },
24852
/* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
24853
  {
24854
    { 0, 0, 0, 0 },
24855
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24856
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x93350000 }
24857
  },
24858
/* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
24859
  {
24860
    { 0, 0, 0, 0 },
24861
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24862
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x95050000 }
24863
  },
24864
/* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
24865
  {
24866
    { 0, 0, 0, 0 },
24867
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24868
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x95250000 }
24869
  },
24870
/* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
24871
  {
24872
    { 0, 0, 0, 0 },
24873
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24874
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x95350000 }
24875
  },
24876
/* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
24877
  {
24878
    { 0, 0, 0, 0 },
24879
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24880
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x97050000 }
24881
  },
24882
/* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
24883
  {
24884
    { 0, 0, 0, 0 },
24885
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24886
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x97250000 }
24887
  },
24888
/* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
24889
  {
24890
    { 0, 0, 0, 0 },
24891
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
24892
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x97350000 }
24893
  },
24894
/* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
24895
  {
24896
    { 0, 0, 0, 0 },
24897
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
24898
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93850000 }
24899
  },
24900
/* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
24901
  {
24902
    { 0, 0, 0, 0 },
24903
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
24904
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93a50000 }
24905
  },
24906
/* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
24907
  {
24908
    { 0, 0, 0, 0 },
24909
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
24910
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93b50000 }
24911
  },
24912
/* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
24913
  {
24914
    { 0, 0, 0, 0 },
24915
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
24916
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95850000 }
24917
  },
24918
/* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
24919
  {
24920
    { 0, 0, 0, 0 },
24921
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
24922
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95a50000 }
24923
  },
24924
/* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
24925
  {
24926
    { 0, 0, 0, 0 },
24927
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
24928
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95b50000 }
24929
  },
24930
/* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
24931
  {
24932
    { 0, 0, 0, 0 },
24933
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
24934
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93c50000 }
24935
  },
24936
/* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
24937
  {
24938
    { 0, 0, 0, 0 },
24939
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
24940
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93e50000 }
24941
  },
24942
/* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
24943
  {
24944
    { 0, 0, 0, 0 },
24945
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
24946
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93f50000 }
24947
  },
24948
/* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
24949
  {
24950
    { 0, 0, 0, 0 },
24951
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
24952
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95c50000 }
24953
  },
24954
/* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
24955
  {
24956
    { 0, 0, 0, 0 },
24957
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
24958
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95e50000 }
24959
  },
24960
/* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
24961
  {
24962
    { 0, 0, 0, 0 },
24963
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
24964
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95f50000 }
24965
  },
24966
/* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
24967
  {
24968
    { 0, 0, 0, 0 },
24969
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
24970
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97c50000 }
24971
  },
24972
/* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
24973
  {
24974
    { 0, 0, 0, 0 },
24975
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
24976
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97e50000 }
24977
  },
24978
/* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
24979
  {
24980
    { 0, 0, 0, 0 },
24981
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
24982
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97f50000 }
24983
  },
24984
/* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
24985
  {
24986
    { 0, 0, 0, 0 },
24987
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
24988
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97850000 }
24989
  },
24990
/* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
24991
  {
24992
    { 0, 0, 0, 0 },
24993
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } },
24994
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97a50000 }
24995
  },
24996
/* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
24997
  {
24998
    { 0, 0, 0, 0 },
24999
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } },
25000
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97b50000 }
25001
  },
25002
/* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
25003
  {
25004
    { 0, 0, 0, 0 },
25005
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
25006
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa9050000 }
25007
  },
25008
/* or.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */
25009
  {
25010
    { 0, 0, 0, 0 },
25011
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
25012
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa9250000 }
25013
  },
25014
/* or.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */
25015
  {
25016
    { 0, 0, 0, 0 },
25017
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
25018
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa9350000 }
25019
  },
25020
/* or.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */
25021
  {
25022
    { 0, 0, 0, 0 },
25023
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
25024
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb9350000 }
25025
  },
25026
/* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
25027
  {
25028
    { 0, 0, 0, 0 },
25029
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
25030
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1850000 }
25031
  },
25032
/* or.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */
25033
  {
25034
    { 0, 0, 0, 0 },
25035
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
25036
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1a50000 }
25037
  },
25038
/* or.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */
25039
  {
25040
    { 0, 0, 0, 0 },
25041
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
25042
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1b50000 }
25043
  },
25044
/* or.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */
25045
  {
25046
    { 0, 0, 0, 0 },
25047
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
25048
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1b50000 }
25049
  },
25050
/* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
25051
  {
25052
    { 0, 0, 0, 0 },
25053
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25054
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa1050000 }
25055
  },
25056
/* or.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
25057
  {
25058
    { 0, 0, 0, 0 },
25059
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25060
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa1250000 }
25061
  },
25062
/* or.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
25063
  {
25064
    { 0, 0, 0, 0 },
25065
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25066
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa1350000 }
25067
  },
25068
/* or.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
25069
  {
25070
    { 0, 0, 0, 0 },
25071
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25072
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb1350000 }
25073
  },
25074
/* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
25075
  {
25076
    { 0, 0, 0, 0 },
25077
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25078
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa3050000 }
25079
  },
25080
/* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
25081
  {
25082
    { 0, 0, 0, 0 },
25083
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25084
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa3250000 }
25085
  },
25086
/* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
25087
  {
25088
    { 0, 0, 0, 0 },
25089
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25090
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa3350000 }
25091
  },
25092
/* or.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
25093
  {
25094
    { 0, 0, 0, 0 },
25095
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25096
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xb3350000 }
25097
  },
25098
/* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
25099
  {
25100
    { 0, 0, 0, 0 },
25101
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25102
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa5050000 }
25103
  },
25104
/* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
25105
  {
25106
    { 0, 0, 0, 0 },
25107
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25108
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa5250000 }
25109
  },
25110
/* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
25111
  {
25112
    { 0, 0, 0, 0 },
25113
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25114
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa5350000 }
25115
  },
25116
/* or.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
25117
  {
25118
    { 0, 0, 0, 0 },
25119
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25120
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xb5350000 }
25121
  },
25122
/* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
25123
  {
25124
    { 0, 0, 0, 0 },
25125
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25126
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa7050000 }
25127
  },
25128
/* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
25129
  {
25130
    { 0, 0, 0, 0 },
25131
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25132
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa7250000 }
25133
  },
25134
/* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
25135
  {
25136
    { 0, 0, 0, 0 },
25137
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25138
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa7350000 }
25139
  },
25140
/* or.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
25141
  {
25142
    { 0, 0, 0, 0 },
25143
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25144
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xb7350000 }
25145
  },
25146
/* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
25147
  {
25148
    { 0, 0, 0, 0 },
25149
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
25150
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3850000 }
25151
  },
25152
/* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
25153
  {
25154
    { 0, 0, 0, 0 },
25155
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
25156
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3a50000 }
25157
  },
25158
/* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
25159
  {
25160
    { 0, 0, 0, 0 },
25161
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
25162
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3b50000 }
25163
  },
25164
/* or.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
25165
  {
25166
    { 0, 0, 0, 0 },
25167
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
25168
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xb3b50000 }
25169
  },
25170
/* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
25171
  {
25172
    { 0, 0, 0, 0 },
25173
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
25174
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5850000 }
25175
  },
25176
/* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
25177
  {
25178
    { 0, 0, 0, 0 },
25179
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
25180
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5a50000 }
25181
  },
25182
/* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
25183
  {
25184
    { 0, 0, 0, 0 },
25185
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
25186
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5b50000 }
25187
  },
25188
/* or.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
25189
  {
25190
    { 0, 0, 0, 0 },
25191
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
25192
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xb5b50000 }
25193
  },
25194
/* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
25195
  {
25196
    { 0, 0, 0, 0 },
25197
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
25198
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3c50000 }
25199
  },
25200
/* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
25201
  {
25202
    { 0, 0, 0, 0 },
25203
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
25204
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3e50000 }
25205
  },
25206
/* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
25207
  {
25208
    { 0, 0, 0, 0 },
25209
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
25210
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3f50000 }
25211
  },
25212
/* or.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
25213
  {
25214
    { 0, 0, 0, 0 },
25215
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
25216
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xb3f50000 }
25217
  },
25218
/* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
25219
  {
25220
    { 0, 0, 0, 0 },
25221
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
25222
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5c50000 }
25223
  },
25224
/* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
25225
  {
25226
    { 0, 0, 0, 0 },
25227
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
25228
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5e50000 }
25229
  },
25230
/* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
25231
  {
25232
    { 0, 0, 0, 0 },
25233
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
25234
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5f50000 }
25235
  },
25236
/* or.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
25237
  {
25238
    { 0, 0, 0, 0 },
25239
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
25240
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xb5f50000 }
25241
  },
25242
/* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
25243
  {
25244
    { 0, 0, 0, 0 },
25245
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
25246
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7c50000 }
25247
  },
25248
/* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
25249
  {
25250
    { 0, 0, 0, 0 },
25251
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
25252
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7e50000 }
25253
  },
25254
/* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
25255
  {
25256
    { 0, 0, 0, 0 },
25257
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
25258
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7f50000 }
25259
  },
25260
/* or.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
25261
  {
25262
    { 0, 0, 0, 0 },
25263
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
25264
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xb7f50000 }
25265
  },
25266
/* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
25267
  {
25268
    { 0, 0, 0, 0 },
25269
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
25270
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7850000 }
25271
  },
25272
/* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
25273
  {
25274
    { 0, 0, 0, 0 },
25275
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
25276
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7a50000 }
25277
  },
25278
/* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
25279
  {
25280
    { 0, 0, 0, 0 },
25281
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
25282
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7b50000 }
25283
  },
25284
/* or.w${G} ${Dsp-16-u16},${Dsp-32-u24} */
25285
  {
25286
    { 0, 0, 0, 0 },
25287
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } },
25288
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xb7b50000 }
25289
  },
25290
/* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
25291
  {
25292
    { 0, 0, 0, 0 },
25293
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
25294
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb9050000 }
25295
  },
25296
/* or.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */
25297
  {
25298
    { 0, 0, 0, 0 },
25299
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
25300
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb9250000 }
25301
  },
25302
/* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
25303
  {
25304
    { 0, 0, 0, 0 },
25305
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
25306
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1850000 }
25307
  },
25308
/* or.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */
25309
  {
25310
    { 0, 0, 0, 0 },
25311
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
25312
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1a50000 }
25313
  },
25314
/* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
25315
  {
25316
    { 0, 0, 0, 0 },
25317
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25318
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb1050000 }
25319
  },
25320
/* or.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
25321
  {
25322
    { 0, 0, 0, 0 },
25323
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25324
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb1250000 }
25325
  },
25326
/* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
25327
  {
25328
    { 0, 0, 0, 0 },
25329
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25330
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_An_relative_Unprefixed_HI, { 0xb3050000 }
25331
  },
25332
/* or.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
25333
  {
25334
    { 0, 0, 0, 0 },
25335
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25336
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_An_relative_Unprefixed_HI, { 0xb3250000 }
25337
  },
25338
/* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
25339
  {
25340
    { 0, 0, 0, 0 },
25341
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25342
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_An_relative_Unprefixed_HI, { 0xb5050000 }
25343
  },
25344
/* or.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
25345
  {
25346
    { 0, 0, 0, 0 },
25347
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25348
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_An_relative_Unprefixed_HI, { 0xb5250000 }
25349
  },
25350
/* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
25351
  {
25352
    { 0, 0, 0, 0 },
25353
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25354
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_24_An_relative_Unprefixed_HI, { 0xb7050000 }
25355
  },
25356
/* or.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
25357
  {
25358
    { 0, 0, 0, 0 },
25359
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25360
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_24_An_relative_Unprefixed_HI, { 0xb7250000 }
25361
  },
25362
/* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
25363
  {
25364
    { 0, 0, 0, 0 },
25365
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
25366
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_SB_relative_Unprefixed_HI, { 0xb3850000 }
25367
  },
25368
/* or.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
25369
  {
25370
    { 0, 0, 0, 0 },
25371
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
25372
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_SB_relative_Unprefixed_HI, { 0xb3a50000 }
25373
  },
25374
/* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
25375
  {
25376
    { 0, 0, 0, 0 },
25377
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
25378
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_SB_relative_Unprefixed_HI, { 0xb5850000 }
25379
  },
25380
/* or.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
25381
  {
25382
    { 0, 0, 0, 0 },
25383
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
25384
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_SB_relative_Unprefixed_HI, { 0xb5a50000 }
25385
  },
25386
/* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
25387
  {
25388
    { 0, 0, 0, 0 },
25389
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
25390
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_FB_relative_Unprefixed_HI, { 0xb3c50000 }
25391
  },
25392
/* or.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
25393
  {
25394
    { 0, 0, 0, 0 },
25395
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
25396
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_FB_relative_Unprefixed_HI, { 0xb3e50000 }
25397
  },
25398
/* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
25399
  {
25400
    { 0, 0, 0, 0 },
25401
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
25402
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_FB_relative_Unprefixed_HI, { 0xb5c50000 }
25403
  },
25404
/* or.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
25405
  {
25406
    { 0, 0, 0, 0 },
25407
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
25408
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_FB_relative_Unprefixed_HI, { 0xb5e50000 }
25409
  },
25410
/* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
25411
  {
25412
    { 0, 0, 0, 0 },
25413
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
25414
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_absolute_Unprefixed_HI, { 0xb7c50000 }
25415
  },
25416
/* or.w${G} ${Dsp-16-u24},${Dsp-40-u16} */
25417
  {
25418
    { 0, 0, 0, 0 },
25419
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } },
25420
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_absolute_Unprefixed_HI, { 0xb7e50000 }
25421
  },
25422
/* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
25423
  {
25424
    { 0, 0, 0, 0 },
25425
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
25426
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_24_absolute_Unprefixed_HI, { 0xb7850000 }
25427
  },
25428
/* or.w${G} ${Dsp-16-u24},${Dsp-40-u24} */
25429
  {
25430
    { 0, 0, 0, 0 },
25431
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } },
25432
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_24_absolute_Unprefixed_HI, { 0xb7a50000 }
25433
  },
25434
/* or.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */
25435
  {
25436
    { 0, 0, 0, 0 },
25437
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
25438
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xc905 }
25439
  },
25440
/* or.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */
25441
  {
25442
    { 0, 0, 0, 0 },
25443
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
25444
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x8925 }
25445
  },
25446
/* or.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
25447
  {
25448
    { 0, 0, 0, 0 },
25449
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
25450
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x8905 }
25451
  },
25452
/* or.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */
25453
  {
25454
    { 0, 0, 0, 0 },
25455
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
25456
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xc185 }
25457
  },
25458
/* or.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */
25459
  {
25460
    { 0, 0, 0, 0 },
25461
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
25462
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x81a5 }
25463
  },
25464
/* or.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
25465
  {
25466
    { 0, 0, 0, 0 },
25467
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
25468
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x8185 }
25469
  },
25470
/* or.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */
25471
  {
25472
    { 0, 0, 0, 0 },
25473
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25474
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xc105 }
25475
  },
25476
/* or.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */
25477
  {
25478
    { 0, 0, 0, 0 },
25479
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25480
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x8125 }
25481
  },
25482
/* or.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
25483
  {
25484
    { 0, 0, 0, 0 },
25485
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25486
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x8105 }
25487
  },
25488
/* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
25489
  {
25490
    { 0, 0, 0, 0 },
25491
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25492
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0xc30500 }
25493
  },
25494
/* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
25495
  {
25496
    { 0, 0, 0, 0 },
25497
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25498
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0x832500 }
25499
  },
25500
/* or.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
25501
  {
25502
    { 0, 0, 0, 0 },
25503
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25504
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0x830500 }
25505
  },
25506
/* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
25507
  {
25508
    { 0, 0, 0, 0 },
25509
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25510
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0xc5050000 }
25511
  },
25512
/* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
25513
  {
25514
    { 0, 0, 0, 0 },
25515
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25516
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0x85250000 }
25517
  },
25518
/* or.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
25519
  {
25520
    { 0, 0, 0, 0 },
25521
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25522
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0x85050000 }
25523
  },
25524
/* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
25525
  {
25526
    { 0, 0, 0, 0 },
25527
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25528
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0xc7050000 }
25529
  },
25530
/* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
25531
  {
25532
    { 0, 0, 0, 0 },
25533
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25534
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0x87250000 }
25535
  },
25536
/* or.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
25537
  {
25538
    { 0, 0, 0, 0 },
25539
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25540
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0x87050000 }
25541
  },
25542
/* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */
25543
  {
25544
    { 0, 0, 0, 0 },
25545
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
25546
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0xc38500 }
25547
  },
25548
/* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */
25549
  {
25550
    { 0, 0, 0, 0 },
25551
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
25552
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0x83a500 }
25553
  },
25554
/* or.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
25555
  {
25556
    { 0, 0, 0, 0 },
25557
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
25558
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0x838500 }
25559
  },
25560
/* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */
25561
  {
25562
    { 0, 0, 0, 0 },
25563
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
25564
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0xc5850000 }
25565
  },
25566
/* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */
25567
  {
25568
    { 0, 0, 0, 0 },
25569
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
25570
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0x85a50000 }
25571
  },
25572
/* or.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
25573
  {
25574
    { 0, 0, 0, 0 },
25575
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
25576
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0x85850000 }
25577
  },
25578
/* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */
25579
  {
25580
    { 0, 0, 0, 0 },
25581
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
25582
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0xc3c500 }
25583
  },
25584
/* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */
25585
  {
25586
    { 0, 0, 0, 0 },
25587
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
25588
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83e500 }
25589
  },
25590
/* or.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
25591
  {
25592
    { 0, 0, 0, 0 },
25593
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
25594
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83c500 }
25595
  },
25596
/* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */
25597
  {
25598
    { 0, 0, 0, 0 },
25599
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
25600
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0xc5c50000 }
25601
  },
25602
/* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */
25603
  {
25604
    { 0, 0, 0, 0 },
25605
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
25606
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85e50000 }
25607
  },
25608
/* or.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
25609
  {
25610
    { 0, 0, 0, 0 },
25611
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
25612
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85c50000 }
25613
  },
25614
/* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */
25615
  {
25616
    { 0, 0, 0, 0 },
25617
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), 0 } },
25618
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0xc7c50000 }
25619
  },
25620
/* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */
25621
  {
25622
    { 0, 0, 0, 0 },
25623
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), 0 } },
25624
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0x87e50000 }
25625
  },
25626
/* or.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
25627
  {
25628
    { 0, 0, 0, 0 },
25629
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } },
25630
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0x87c50000 }
25631
  },
25632
/* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */
25633
  {
25634
    { 0, 0, 0, 0 },
25635
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U24), 0 } },
25636
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0xc7850000 }
25637
  },
25638
/* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */
25639
  {
25640
    { 0, 0, 0, 0 },
25641
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U24), 0 } },
25642
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0x87a50000 }
25643
  },
25644
/* or.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
25645
  {
25646
    { 0, 0, 0, 0 },
25647
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } },
25648
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0x87850000 }
25649
  },
25650
/* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
25651
  {
25652
    { 0, 0, 0, 0 },
25653
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
25654
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x980500 }
25655
  },
25656
/* or.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */
25657
  {
25658
    { 0, 0, 0, 0 },
25659
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
25660
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x982500 }
25661
  },
25662
/* or.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */
25663
  {
25664
    { 0, 0, 0, 0 },
25665
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
25666
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x983500 }
25667
  },
25668
/* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
25669
  {
25670
    { 0, 0, 0, 0 },
25671
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
25672
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x908500 }
25673
  },
25674
/* or.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */
25675
  {
25676
    { 0, 0, 0, 0 },
25677
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
25678
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x90a500 }
25679
  },
25680
/* or.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */
25681
  {
25682
    { 0, 0, 0, 0 },
25683
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
25684
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x90b500 }
25685
  },
25686
/* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
25687
  {
25688
    { 0, 0, 0, 0 },
25689
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25690
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x900500 }
25691
  },
25692
/* or.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
25693
  {
25694
    { 0, 0, 0, 0 },
25695
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25696
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x902500 }
25697
  },
25698
/* or.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
25699
  {
25700
    { 0, 0, 0, 0 },
25701
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25702
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x903500 }
25703
  },
25704
/* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
25705
  {
25706
    { 0, 0, 0, 0 },
25707
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25708
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x92050000 }
25709
  },
25710
/* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
25711
  {
25712
    { 0, 0, 0, 0 },
25713
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25714
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x92250000 }
25715
  },
25716
/* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
25717
  {
25718
    { 0, 0, 0, 0 },
25719
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25720
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x92350000 }
25721
  },
25722
/* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
25723
  {
25724
    { 0, 0, 0, 0 },
25725
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25726
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x94050000 }
25727
  },
25728
/* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
25729
  {
25730
    { 0, 0, 0, 0 },
25731
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25732
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x94250000 }
25733
  },
25734
/* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
25735
  {
25736
    { 0, 0, 0, 0 },
25737
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25738
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x94350000 }
25739
  },
25740
/* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
25741
  {
25742
    { 0, 0, 0, 0 },
25743
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25744
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x96050000 }
25745
  },
25746
/* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
25747
  {
25748
    { 0, 0, 0, 0 },
25749
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25750
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x96250000 }
25751
  },
25752
/* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
25753
  {
25754
    { 0, 0, 0, 0 },
25755
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25756
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x96350000 }
25757
  },
25758
/* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
25759
  {
25760
    { 0, 0, 0, 0 },
25761
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
25762
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92850000 }
25763
  },
25764
/* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
25765
  {
25766
    { 0, 0, 0, 0 },
25767
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
25768
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92a50000 }
25769
  },
25770
/* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
25771
  {
25772
    { 0, 0, 0, 0 },
25773
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
25774
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92b50000 }
25775
  },
25776
/* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
25777
  {
25778
    { 0, 0, 0, 0 },
25779
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
25780
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94850000 }
25781
  },
25782
/* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
25783
  {
25784
    { 0, 0, 0, 0 },
25785
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
25786
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94a50000 }
25787
  },
25788
/* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
25789
  {
25790
    { 0, 0, 0, 0 },
25791
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
25792
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94b50000 }
25793
  },
25794
/* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
25795
  {
25796
    { 0, 0, 0, 0 },
25797
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
25798
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92c50000 }
25799
  },
25800
/* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
25801
  {
25802
    { 0, 0, 0, 0 },
25803
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
25804
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92e50000 }
25805
  },
25806
/* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
25807
  {
25808
    { 0, 0, 0, 0 },
25809
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
25810
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92f50000 }
25811
  },
25812
/* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
25813
  {
25814
    { 0, 0, 0, 0 },
25815
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
25816
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94c50000 }
25817
  },
25818
/* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
25819
  {
25820
    { 0, 0, 0, 0 },
25821
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
25822
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94e50000 }
25823
  },
25824
/* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
25825
  {
25826
    { 0, 0, 0, 0 },
25827
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
25828
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94f50000 }
25829
  },
25830
/* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
25831
  {
25832
    { 0, 0, 0, 0 },
25833
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
25834
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96c50000 }
25835
  },
25836
/* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
25837
  {
25838
    { 0, 0, 0, 0 },
25839
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
25840
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96e50000 }
25841
  },
25842
/* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
25843
  {
25844
    { 0, 0, 0, 0 },
25845
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
25846
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96f50000 }
25847
  },
25848
/* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
25849
  {
25850
    { 0, 0, 0, 0 },
25851
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
25852
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96850000 }
25853
  },
25854
/* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
25855
  {
25856
    { 0, 0, 0, 0 },
25857
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } },
25858
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96a50000 }
25859
  },
25860
/* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
25861
  {
25862
    { 0, 0, 0, 0 },
25863
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } },
25864
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96b50000 }
25865
  },
25866
/* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
25867
  {
25868
    { 0, 0, 0, 0 },
25869
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
25870
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa8050000 }
25871
  },
25872
/* or.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */
25873
  {
25874
    { 0, 0, 0, 0 },
25875
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
25876
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa8250000 }
25877
  },
25878
/* or.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */
25879
  {
25880
    { 0, 0, 0, 0 },
25881
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
25882
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa8350000 }
25883
  },
25884
/* or.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */
25885
  {
25886
    { 0, 0, 0, 0 },
25887
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
25888
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb8350000 }
25889
  },
25890
/* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
25891
  {
25892
    { 0, 0, 0, 0 },
25893
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
25894
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0850000 }
25895
  },
25896
/* or.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */
25897
  {
25898
    { 0, 0, 0, 0 },
25899
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
25900
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0a50000 }
25901
  },
25902
/* or.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */
25903
  {
25904
    { 0, 0, 0, 0 },
25905
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
25906
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0b50000 }
25907
  },
25908
/* or.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */
25909
  {
25910
    { 0, 0, 0, 0 },
25911
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
25912
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0b50000 }
25913
  },
25914
/* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
25915
  {
25916
    { 0, 0, 0, 0 },
25917
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25918
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa0050000 }
25919
  },
25920
/* or.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
25921
  {
25922
    { 0, 0, 0, 0 },
25923
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25924
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa0250000 }
25925
  },
25926
/* or.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
25927
  {
25928
    { 0, 0, 0, 0 },
25929
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25930
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa0350000 }
25931
  },
25932
/* or.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
25933
  {
25934
    { 0, 0, 0, 0 },
25935
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25936
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb0350000 }
25937
  },
25938
/* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
25939
  {
25940
    { 0, 0, 0, 0 },
25941
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25942
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa2050000 }
25943
  },
25944
/* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
25945
  {
25946
    { 0, 0, 0, 0 },
25947
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25948
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa2250000 }
25949
  },
25950
/* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
25951
  {
25952
    { 0, 0, 0, 0 },
25953
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25954
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa2350000 }
25955
  },
25956
/* or.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
25957
  {
25958
    { 0, 0, 0, 0 },
25959
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25960
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xb2350000 }
25961
  },
25962
/* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
25963
  {
25964
    { 0, 0, 0, 0 },
25965
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25966
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa4050000 }
25967
  },
25968
/* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
25969
  {
25970
    { 0, 0, 0, 0 },
25971
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25972
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa4250000 }
25973
  },
25974
/* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
25975
  {
25976
    { 0, 0, 0, 0 },
25977
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25978
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa4350000 }
25979
  },
25980
/* or.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
25981
  {
25982
    { 0, 0, 0, 0 },
25983
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25984
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xb4350000 }
25985
  },
25986
/* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
25987
  {
25988
    { 0, 0, 0, 0 },
25989
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25990
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa6050000 }
25991
  },
25992
/* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
25993
  {
25994
    { 0, 0, 0, 0 },
25995
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
25996
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa6250000 }
25997
  },
25998
/* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
25999
  {
26000
    { 0, 0, 0, 0 },
26001
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
26002
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa6350000 }
26003
  },
26004
/* or.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
26005
  {
26006
    { 0, 0, 0, 0 },
26007
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
26008
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xb6350000 }
26009
  },
26010
/* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
26011
  {
26012
    { 0, 0, 0, 0 },
26013
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
26014
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2850000 }
26015
  },
26016
/* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
26017
  {
26018
    { 0, 0, 0, 0 },
26019
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
26020
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2a50000 }
26021
  },
26022
/* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
26023
  {
26024
    { 0, 0, 0, 0 },
26025
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
26026
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2b50000 }
26027
  },
26028
/* or.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
26029
  {
26030
    { 0, 0, 0, 0 },
26031
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
26032
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xb2b50000 }
26033
  },
26034
/* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
26035
  {
26036
    { 0, 0, 0, 0 },
26037
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
26038
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4850000 }
26039
  },
26040
/* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
26041
  {
26042
    { 0, 0, 0, 0 },
26043
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
26044
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4a50000 }
26045
  },
26046
/* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
26047
  {
26048
    { 0, 0, 0, 0 },
26049
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
26050
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4b50000 }
26051
  },
26052
/* or.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
26053
  {
26054
    { 0, 0, 0, 0 },
26055
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
26056
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xb4b50000 }
26057
  },
26058
/* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
26059
  {
26060
    { 0, 0, 0, 0 },
26061
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
26062
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2c50000 }
26063
  },
26064
/* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
26065
  {
26066
    { 0, 0, 0, 0 },
26067
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
26068
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2e50000 }
26069
  },
26070
/* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
26071
  {
26072
    { 0, 0, 0, 0 },
26073
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
26074
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2f50000 }
26075
  },
26076
/* or.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
26077
  {
26078
    { 0, 0, 0, 0 },
26079
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
26080
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xb2f50000 }
26081
  },
26082
/* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
26083
  {
26084
    { 0, 0, 0, 0 },
26085
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
26086
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4c50000 }
26087
  },
26088
/* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
26089
  {
26090
    { 0, 0, 0, 0 },
26091
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
26092
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4e50000 }
26093
  },
26094
/* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
26095
  {
26096
    { 0, 0, 0, 0 },
26097
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
26098
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4f50000 }
26099
  },
26100
/* or.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
26101
  {
26102
    { 0, 0, 0, 0 },
26103
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
26104
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xb4f50000 }
26105
  },
26106
/* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
26107
  {
26108
    { 0, 0, 0, 0 },
26109
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
26110
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6c50000 }
26111
  },
26112
/* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
26113
  {
26114
    { 0, 0, 0, 0 },
26115
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
26116
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6e50000 }
26117
  },
26118
/* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
26119
  {
26120
    { 0, 0, 0, 0 },
26121
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
26122
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6f50000 }
26123
  },
26124
/* or.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
26125
  {
26126
    { 0, 0, 0, 0 },
26127
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
26128
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xb6f50000 }
26129
  },
26130
/* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
26131
  {
26132
    { 0, 0, 0, 0 },
26133
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
26134
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6850000 }
26135
  },
26136
/* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
26137
  {
26138
    { 0, 0, 0, 0 },
26139
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
26140
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6a50000 }
26141
  },
26142
/* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
26143
  {
26144
    { 0, 0, 0, 0 },
26145
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
26146
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6b50000 }
26147
  },
26148
/* or.b${G} ${Dsp-16-u16},${Dsp-32-u24} */
26149
  {
26150
    { 0, 0, 0, 0 },
26151
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } },
26152
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xb6b50000 }
26153
  },
26154
/* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
26155
  {
26156
    { 0, 0, 0, 0 },
26157
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
26158
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb8050000 }
26159
  },
26160
/* or.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */
26161
  {
26162
    { 0, 0, 0, 0 },
26163
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
26164
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb8250000 }
26165
  },
26166
/* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
26167
  {
26168
    { 0, 0, 0, 0 },
26169
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
26170
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0850000 }
26171
  },
26172
/* or.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */
26173
  {
26174
    { 0, 0, 0, 0 },
26175
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
26176
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0a50000 }
26177
  },
26178
/* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
26179
  {
26180
    { 0, 0, 0, 0 },
26181
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
26182
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb0050000 }
26183
  },
26184
/* or.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
26185
  {
26186
    { 0, 0, 0, 0 },
26187
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
26188
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb0250000 }
26189
  },
26190
/* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
26191
  {
26192
    { 0, 0, 0, 0 },
26193
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
26194
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_QI, { 0xb2050000 }
26195
  },
26196
/* or.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
26197
  {
26198
    { 0, 0, 0, 0 },
26199
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
26200
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_QI, { 0xb2250000 }
26201
  },
26202
/* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
26203
  {
26204
    { 0, 0, 0, 0 },
26205
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
26206
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_QI, { 0xb4050000 }
26207
  },
26208
/* or.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
26209
  {
26210
    { 0, 0, 0, 0 },
26211
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
26212
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_QI, { 0xb4250000 }
26213
  },
26214
/* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
26215
  {
26216
    { 0, 0, 0, 0 },
26217
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
26218
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_QI, { 0xb6050000 }
26219
  },
26220
/* or.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
26221
  {
26222
    { 0, 0, 0, 0 },
26223
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
26224
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_QI, { 0xb6250000 }
26225
  },
26226
/* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
26227
  {
26228
    { 0, 0, 0, 0 },
26229
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
26230
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_QI, { 0xb2850000 }
26231
  },
26232
/* or.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
26233
  {
26234
    { 0, 0, 0, 0 },
26235
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
26236
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_QI, { 0xb2a50000 }
26237
  },
26238
/* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
26239
  {
26240
    { 0, 0, 0, 0 },
26241
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
26242
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_QI, { 0xb4850000 }
26243
  },
26244
/* or.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
26245
  {
26246
    { 0, 0, 0, 0 },
26247
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
26248
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_QI, { 0xb4a50000 }
26249
  },
26250
/* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
26251
  {
26252
    { 0, 0, 0, 0 },
26253
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
26254
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_QI, { 0xb2c50000 }
26255
  },
26256
/* or.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
26257
  {
26258
    { 0, 0, 0, 0 },
26259
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
26260
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_QI, { 0xb2e50000 }
26261
  },
26262
/* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
26263
  {
26264
    { 0, 0, 0, 0 },
26265
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
26266
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_QI, { 0xb4c50000 }
26267
  },
26268
/* or.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
26269
  {
26270
    { 0, 0, 0, 0 },
26271
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
26272
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_QI, { 0xb4e50000 }
26273
  },
26274
/* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
26275
  {
26276
    { 0, 0, 0, 0 },
26277
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
26278
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_QI, { 0xb6c50000 }
26279
  },
26280
/* or.b${G} ${Dsp-16-u24},${Dsp-40-u16} */
26281
  {
26282
    { 0, 0, 0, 0 },
26283
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } },
26284
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_QI, { 0xb6e50000 }
26285
  },
26286
/* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
26287
  {
26288
    { 0, 0, 0, 0 },
26289
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
26290
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_QI, { 0xb6850000 }
26291
  },
26292
/* or.b${G} ${Dsp-16-u24},${Dsp-40-u24} */
26293
  {
26294
    { 0, 0, 0, 0 },
26295
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } },
26296
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_QI, { 0xb6a50000 }
26297
  },
26298
/* or.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */
26299
  {
26300
    { 0, 0, 0, 0 },
26301
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
26302
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xc805 }
26303
  },
26304
/* or.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */
26305
  {
26306
    { 0, 0, 0, 0 },
26307
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
26308
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x8825 }
26309
  },
26310
/* or.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
26311
  {
26312
    { 0, 0, 0, 0 },
26313
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
26314
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x8805 }
26315
  },
26316
/* or.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */
26317
  {
26318
    { 0, 0, 0, 0 },
26319
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
26320
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xc085 }
26321
  },
26322
/* or.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */
26323
  {
26324
    { 0, 0, 0, 0 },
26325
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
26326
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x80a5 }
26327
  },
26328
/* or.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
26329
  {
26330
    { 0, 0, 0, 0 },
26331
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
26332
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x8085 }
26333
  },
26334
/* or.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */
26335
  {
26336
    { 0, 0, 0, 0 },
26337
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
26338
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xc005 }
26339
  },
26340
/* or.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */
26341
  {
26342
    { 0, 0, 0, 0 },
26343
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
26344
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x8025 }
26345
  },
26346
/* or.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
26347
  {
26348
    { 0, 0, 0, 0 },
26349
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
26350
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x8005 }
26351
  },
26352
/* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
26353
  {
26354
    { 0, 0, 0, 0 },
26355
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
26356
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0xc20500 }
26357
  },
26358
/* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
26359
  {
26360
    { 0, 0, 0, 0 },
26361
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
26362
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0x822500 }
26363
  },
26364
/* or.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
26365
  {
26366
    { 0, 0, 0, 0 },
26367
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
26368
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0x820500 }
26369
  },
26370
/* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
26371
  {
26372
    { 0, 0, 0, 0 },
26373
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
26374
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0xc4050000 }
26375
  },
26376
/* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
26377
  {
26378
    { 0, 0, 0, 0 },
26379
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
26380
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0x84250000 }
26381
  },
26382
/* or.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
26383
  {
26384
    { 0, 0, 0, 0 },
26385
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
26386
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0x84050000 }
26387
  },
26388
/* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
26389
  {
26390
    { 0, 0, 0, 0 },
26391
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
26392
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0xc6050000 }
26393
  },
26394
/* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
26395
  {
26396
    { 0, 0, 0, 0 },
26397
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
26398
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0x86250000 }
26399
  },
26400
/* or.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
26401
  {
26402
    { 0, 0, 0, 0 },
26403
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
26404
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0x86050000 }
26405
  },
26406
/* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */
26407
  {
26408
    { 0, 0, 0, 0 },
26409
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
26410
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0xc28500 }
26411
  },
26412
/* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */
26413
  {
26414
    { 0, 0, 0, 0 },
26415
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
26416
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0x82a500 }
26417
  },
26418
/* or.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
26419
  {
26420
    { 0, 0, 0, 0 },
26421
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
26422
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0x828500 }
26423
  },
26424
/* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */
26425
  {
26426
    { 0, 0, 0, 0 },
26427
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
26428
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0xc4850000 }
26429
  },
26430
/* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */
26431
  {
26432
    { 0, 0, 0, 0 },
26433
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
26434
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0x84a50000 }
26435
  },
26436
/* or.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
26437
  {
26438
    { 0, 0, 0, 0 },
26439
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
26440
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0x84850000 }
26441
  },
26442
/* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */
26443
  {
26444
    { 0, 0, 0, 0 },
26445
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
26446
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0xc2c500 }
26447
  },
26448
/* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */
26449
  {
26450
    { 0, 0, 0, 0 },
26451
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
26452
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82e500 }
26453
  },
26454
/* or.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
26455
  {
26456
    { 0, 0, 0, 0 },
26457
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
26458
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82c500 }
26459
  },
26460
/* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */
26461
  {
26462
    { 0, 0, 0, 0 },
26463
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
26464
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0xc4c50000 }
26465
  },
26466
/* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */
26467
  {
26468
    { 0, 0, 0, 0 },
26469
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
26470
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84e50000 }
26471
  },
26472
/* or.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
26473
  {
26474
    { 0, 0, 0, 0 },
26475
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
26476
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84c50000 }
26477
  },
26478
/* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */
26479
  {
26480
    { 0, 0, 0, 0 },
26481
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), 0 } },
26482
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0xc6c50000 }
26483
  },
26484
/* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */
26485
  {
26486
    { 0, 0, 0, 0 },
26487
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), 0 } },
26488
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0x86e50000 }
26489
  },
26490
/* or.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
26491
  {
26492
    { 0, 0, 0, 0 },
26493
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } },
26494
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0x86c50000 }
26495
  },
26496
/* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */
26497
  {
26498
    { 0, 0, 0, 0 },
26499
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U24), 0 } },
26500
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0xc6850000 }
26501
  },
26502
/* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */
26503
  {
26504
    { 0, 0, 0, 0 },
26505
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U24), 0 } },
26506
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0x86a50000 }
26507
  },
26508
/* or.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
26509
  {
26510
    { 0, 0, 0, 0 },
26511
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } },
26512
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0x86850000 }
26513
  },
26514
/* or.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
26515
  {
26516
    { 0, 0, 0, 0 },
26517
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } },
26518
    & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_Rn_direct_HI, { 0x998000 }
26519
  },
26520
/* or.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */
26521
  {
26522
    { 0, 0, 0, 0 },
26523
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } },
26524
    & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_Rn_direct_HI, { 0x99a000 }
26525
  },
26526
/* or.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */
26527
  {
26528
    { 0, 0, 0, 0 },
26529
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNHI), 0 } },
26530
    & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_Rn_direct_HI, { 0x99b000 }
26531
  },
26532
/* or.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
26533
  {
26534
    { 0, 0, 0, 0 },
26535
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } },
26536
    & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_direct_HI, { 0x998400 }
26537
  },
26538
/* or.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */
26539
  {
26540
    { 0, 0, 0, 0 },
26541
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } },
26542
    & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_direct_HI, { 0x99a400 }
26543
  },
26544
/* or.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */
26545
  {
26546
    { 0, 0, 0, 0 },
26547
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANHI), 0 } },
26548
    & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_direct_HI, { 0x99b400 }
26549
  },
26550
/* or.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
26551
  {
26552
    { 0, 0, 0, 0 },
26553
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
26554
    & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_indirect_HI, { 0x998600 }
26555
  },
26556
/* or.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */
26557
  {
26558
    { 0, 0, 0, 0 },
26559
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
26560
    & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_indirect_HI, { 0x99a600 }
26561
  },
26562
/* or.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */
26563
  {
26564
    { 0, 0, 0, 0 },
26565
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
26566
    & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_indirect_HI, { 0x99b600 }
26567
  },
26568
/* or.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
26569
  {
26570
    { 0, 0, 0, 0 },
26571
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
26572
    & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_An_relative_HI, { 0x99880000 }
26573
  },
26574
/* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
26575
  {
26576
    { 0, 0, 0, 0 },
26577
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
26578
    & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_An_relative_HI, { 0x99a80000 }
26579
  },
26580
/* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
26581
  {
26582
    { 0, 0, 0, 0 },
26583
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
26584
    & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_An_relative_HI, { 0x99b80000 }
26585
  },
26586
/* or.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
26587
  {
26588
    { 0, 0, 0, 0 },
26589
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
26590
    & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_An_relative_HI, { 0x998c0000 }
26591
  },
26592
/* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
26593
  {
26594
    { 0, 0, 0, 0 },
26595
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
26596
    & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_An_relative_HI, { 0x99ac0000 }
26597
  },
26598
/* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
26599
  {
26600
    { 0, 0, 0, 0 },
26601
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
26602
    & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_An_relative_HI, { 0x99bc0000 }
26603
  },
26604
/* or.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
26605
  {
26606
    { 0, 0, 0, 0 },
26607
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
26608
    & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_SB_relative_HI, { 0x998a0000 }
26609
  },
26610
/* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
26611
  {
26612
    { 0, 0, 0, 0 },
26613
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
26614
    & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_SB_relative_HI, { 0x99aa0000 }
26615
  },
26616
/* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
26617
  {
26618
    { 0, 0, 0, 0 },
26619
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
26620
    & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_SB_relative_HI, { 0x99ba0000 }
26621
  },
26622
/* or.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
26623
  {
26624
    { 0, 0, 0, 0 },
26625
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
26626
    & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_SB_relative_HI, { 0x998e0000 }
26627
  },
26628
/* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
26629
  {
26630
    { 0, 0, 0, 0 },
26631
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
26632
    & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_SB_relative_HI, { 0x99ae0000 }
26633
  },
26634
/* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
26635
  {
26636
    { 0, 0, 0, 0 },
26637
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
26638
    & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_SB_relative_HI, { 0x99be0000 }
26639
  },
26640
/* or.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
26641
  {
26642
    { 0, 0, 0, 0 },
26643
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
26644
    & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_FB_relative_HI, { 0x998b0000 }
26645
  },
26646
/* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
26647
  {
26648
    { 0, 0, 0, 0 },
26649
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
26650
    & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_FB_relative_HI, { 0x99ab0000 }
26651
  },
26652
/* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
26653
  {
26654
    { 0, 0, 0, 0 },
26655
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
26656
    & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_FB_relative_HI, { 0x99bb0000 }
26657
  },
26658
/* or.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
26659
  {
26660
    { 0, 0, 0, 0 },
26661
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } },
26662
    & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_absolute_HI, { 0x998f0000 }
26663
  },
26664
/* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
26665
  {
26666
    { 0, 0, 0, 0 },
26667
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
26668
    & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_absolute_HI, { 0x99af0000 }
26669
  },
26670
/* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
26671
  {
26672
    { 0, 0, 0, 0 },
26673
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
26674
    & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_absolute_HI, { 0x99bf0000 }
26675
  },
26676
/* or.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
26677
  {
26678
    { 0, 0, 0, 0 },
26679
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } },
26680
    & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_Rn_direct_HI, { 0x99c00000 }
26681
  },
26682
/* or.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */
26683
  {
26684
    { 0, 0, 0, 0 },
26685
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } },
26686
    & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_Rn_direct_HI, { 0x99e00000 }
26687
  },
26688
/* or.w${G} ${Dsp-16-u16},$Dst16RnHI */
26689
  {
26690
    { 0, 0, 0, 0 },
26691
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16RNHI), 0 } },
26692
    & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_Rn_direct_HI, { 0x99f00000 }
26693
  },
26694
/* or.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
26695
  {
26696
    { 0, 0, 0, 0 },
26697
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } },
26698
    & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_direct_HI, { 0x99c40000 }
26699
  },
26700
/* or.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */
26701
  {
26702
    { 0, 0, 0, 0 },
26703
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } },
26704
    & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_direct_HI, { 0x99e40000 }
26705
  },
26706
/* or.w${G} ${Dsp-16-u16},$Dst16AnHI */
26707
  {
26708
    { 0, 0, 0, 0 },
26709
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16ANHI), 0 } },
26710
    & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_direct_HI, { 0x99f40000 }
26711
  },
26712
/* or.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
26713
  {
26714
    { 0, 0, 0, 0 },
26715
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
26716
    & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_indirect_HI, { 0x99c60000 }
26717
  },
26718
/* or.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */
26719
  {
26720
    { 0, 0, 0, 0 },
26721
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
26722
    & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_indirect_HI, { 0x99e60000 }
26723
  },
26724
/* or.w${G} ${Dsp-16-u16},[$Dst16An] */
26725
  {
26726
    { 0, 0, 0, 0 },
26727
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } },
26728
    & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_indirect_HI, { 0x99f60000 }
26729
  },
26730
/* or.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
26731
  {
26732
    { 0, 0, 0, 0 },
26733
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
26734
    & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_An_relative_HI, { 0x99c80000 }
26735
  },
26736
/* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
26737
  {
26738
    { 0, 0, 0, 0 },
26739
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
26740
    & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_An_relative_HI, { 0x99e80000 }
26741
  },
26742
/* or.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
26743
  {
26744
    { 0, 0, 0, 0 },
26745
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
26746
    & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_An_relative_HI, { 0x99f80000 }
26747
  },
26748
/* or.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
26749
  {
26750
    { 0, 0, 0, 0 },
26751
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
26752
    & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_An_relative_HI, { 0x99cc0000 }
26753
  },
26754
/* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
26755
  {
26756
    { 0, 0, 0, 0 },
26757
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
26758
    & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_An_relative_HI, { 0x99ec0000 }
26759
  },
26760
/* or.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
26761
  {
26762
    { 0, 0, 0, 0 },
26763
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
26764
    & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_An_relative_HI, { 0x99fc0000 }
26765
  },
26766
/* or.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
26767
  {
26768
    { 0, 0, 0, 0 },
26769
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
26770
    & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_SB_relative_HI, { 0x99ca0000 }
26771
  },
26772
/* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
26773
  {
26774
    { 0, 0, 0, 0 },
26775
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
26776
    & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_SB_relative_HI, { 0x99ea0000 }
26777
  },
26778
/* or.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
26779
  {
26780
    { 0, 0, 0, 0 },
26781
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
26782
    & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_SB_relative_HI, { 0x99fa0000 }
26783
  },
26784
/* or.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
26785
  {
26786
    { 0, 0, 0, 0 },
26787
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
26788
    & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_SB_relative_HI, { 0x99ce0000 }
26789
  },
26790
/* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
26791
  {
26792
    { 0, 0, 0, 0 },
26793
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
26794
    & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_SB_relative_HI, { 0x99ee0000 }
26795
  },
26796
/* or.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
26797
  {
26798
    { 0, 0, 0, 0 },
26799
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
26800
    & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_SB_relative_HI, { 0x99fe0000 }
26801
  },
26802
/* or.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
26803
  {
26804
    { 0, 0, 0, 0 },
26805
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
26806
    & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_FB_relative_HI, { 0x99cb0000 }
26807
  },
26808
/* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
26809
  {
26810
    { 0, 0, 0, 0 },
26811
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
26812
    & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_FB_relative_HI, { 0x99eb0000 }
26813
  },
26814
/* or.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
26815
  {
26816
    { 0, 0, 0, 0 },
26817
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
26818
    & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_FB_relative_HI, { 0x99fb0000 }
26819
  },
26820
/* or.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
26821
  {
26822
    { 0, 0, 0, 0 },
26823
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } },
26824
    & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_absolute_HI, { 0x99cf0000 }
26825
  },
26826
/* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
26827
  {
26828
    { 0, 0, 0, 0 },
26829
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
26830
    & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_absolute_HI, { 0x99ef0000 }
26831
  },
26832
/* or.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
26833
  {
26834
    { 0, 0, 0, 0 },
26835
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
26836
    & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_absolute_HI, { 0x99ff0000 }
26837
  },
26838
/* or.w${G} $Src16RnHI,$Dst16RnHI */
26839
  {
26840
    { 0, 0, 0, 0 },
26841
    { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DST16RNHI), 0 } },
26842
    & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_Rn_direct_HI, { 0x9900 }
26843
  },
26844
/* or.w${G} $Src16AnHI,$Dst16RnHI */
26845
  {
26846
    { 0, 0, 0, 0 },
26847
    { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DST16RNHI), 0 } },
26848
    & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_Rn_direct_HI, { 0x9940 }
26849
  },
26850
/* or.w${G} [$Src16An],$Dst16RnHI */
26851
  {
26852
    { 0, 0, 0, 0 },
26853
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } },
26854
    & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_Rn_direct_HI, { 0x9960 }
26855
  },
26856
/* or.w${G} $Src16RnHI,$Dst16AnHI */
26857
  {
26858
    { 0, 0, 0, 0 },
26859
    { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DST16ANHI), 0 } },
26860
    & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_direct_HI, { 0x9904 }
26861
  },
26862
/* or.w${G} $Src16AnHI,$Dst16AnHI */
26863
  {
26864
    { 0, 0, 0, 0 },
26865
    { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DST16ANHI), 0 } },
26866
    & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_direct_HI, { 0x9944 }
26867
  },
26868
/* or.w${G} [$Src16An],$Dst16AnHI */
26869
  {
26870
    { 0, 0, 0, 0 },
26871
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } },
26872
    & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_direct_HI, { 0x9964 }
26873
  },
26874
/* or.w${G} $Src16RnHI,[$Dst16An] */
26875
  {
26876
    { 0, 0, 0, 0 },
26877
    { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', '[', OP (DST16AN), ']', 0 } },
26878
    & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_indirect_HI, { 0x9906 }
26879
  },
26880
/* or.w${G} $Src16AnHI,[$Dst16An] */
26881
  {
26882
    { 0, 0, 0, 0 },
26883
    { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', '[', OP (DST16AN), ']', 0 } },
26884
    & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_indirect_HI, { 0x9946 }
26885
  },
26886
/* or.w${G} [$Src16An],[$Dst16An] */
26887
  {
26888
    { 0, 0, 0, 0 },
26889
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
26890
    & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_indirect_HI, { 0x9966 }
26891
  },
26892
/* or.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
26893
  {
26894
    { 0, 0, 0, 0 },
26895
    { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
26896
    & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_An_relative_HI, { 0x990800 }
26897
  },
26898
/* or.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
26899
  {
26900
    { 0, 0, 0, 0 },
26901
    { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
26902
    & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_An_relative_HI, { 0x994800 }
26903
  },
26904
/* or.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
26905
  {
26906
    { 0, 0, 0, 0 },
26907
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
26908
    & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_An_relative_HI, { 0x996800 }
26909
  },
26910
/* or.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
26911
  {
26912
    { 0, 0, 0, 0 },
26913
    { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
26914
    & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_An_relative_HI, { 0x990c0000 }
26915
  },
26916
/* or.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
26917
  {
26918
    { 0, 0, 0, 0 },
26919
    { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
26920
    & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_An_relative_HI, { 0x994c0000 }
26921
  },
26922
/* or.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
26923
  {
26924
    { 0, 0, 0, 0 },
26925
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
26926
    & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_An_relative_HI, { 0x996c0000 }
26927
  },
26928
/* or.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */
26929
  {
26930
    { 0, 0, 0, 0 },
26931
    { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
26932
    & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_SB_relative_HI, { 0x990a00 }
26933
  },
26934
/* or.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */
26935
  {
26936
    { 0, 0, 0, 0 },
26937
    { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
26938
    & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_SB_relative_HI, { 0x994a00 }
26939
  },
26940
/* or.w${G} [$Src16An],${Dsp-16-u8}[sb] */
26941
  {
26942
    { 0, 0, 0, 0 },
26943
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
26944
    & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_SB_relative_HI, { 0x996a00 }
26945
  },
26946
/* or.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */
26947
  {
26948
    { 0, 0, 0, 0 },
26949
    { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
26950
    & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_SB_relative_HI, { 0x990e0000 }
26951
  },
26952
/* or.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */
26953
  {
26954
    { 0, 0, 0, 0 },
26955
    { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
26956
    & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_SB_relative_HI, { 0x994e0000 }
26957
  },
26958
/* or.w${G} [$Src16An],${Dsp-16-u16}[sb] */
26959
  {
26960
    { 0, 0, 0, 0 },
26961
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
26962
    & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_SB_relative_HI, { 0x996e0000 }
26963
  },
26964
/* or.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */
26965
  {
26966
    { 0, 0, 0, 0 },
26967
    { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
26968
    & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_FB_relative_HI, { 0x990b00 }
26969
  },
26970
/* or.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */
26971
  {
26972
    { 0, 0, 0, 0 },
26973
    { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
26974
    & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_FB_relative_HI, { 0x994b00 }
26975
  },
26976
/* or.w${G} [$Src16An],${Dsp-16-s8}[fb] */
26977
  {
26978
    { 0, 0, 0, 0 },
26979
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
26980
    & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_FB_relative_HI, { 0x996b00 }
26981
  },
26982
/* or.w${G} $Src16RnHI,${Dsp-16-u16} */
26983
  {
26984
    { 0, 0, 0, 0 },
26985
    { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), 0 } },
26986
    & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_absolute_HI, { 0x990f0000 }
26987
  },
26988
/* or.w${G} $Src16AnHI,${Dsp-16-u16} */
26989
  {
26990
    { 0, 0, 0, 0 },
26991
    { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), 0 } },
26992
    & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_absolute_HI, { 0x994f0000 }
26993
  },
26994
/* or.w${G} [$Src16An],${Dsp-16-u16} */
26995
  {
26996
    { 0, 0, 0, 0 },
26997
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } },
26998
    & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_absolute_HI, { 0x996f0000 }
26999
  },
27000
/* or.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
27001
  {
27002
    { 0, 0, 0, 0 },
27003
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } },
27004
    & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_Rn_direct_QI, { 0x988000 }
27005
  },
27006
/* or.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */
27007
  {
27008
    { 0, 0, 0, 0 },
27009
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } },
27010
    & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_Rn_direct_QI, { 0x98a000 }
27011
  },
27012
/* or.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */
27013
  {
27014
    { 0, 0, 0, 0 },
27015
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNQI), 0 } },
27016
    & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_Rn_direct_QI, { 0x98b000 }
27017
  },
27018
/* or.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
27019
  {
27020
    { 0, 0, 0, 0 },
27021
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } },
27022
    & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_direct_QI, { 0x988400 }
27023
  },
27024
/* or.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */
27025
  {
27026
    { 0, 0, 0, 0 },
27027
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } },
27028
    & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_direct_QI, { 0x98a400 }
27029
  },
27030
/* or.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */
27031
  {
27032
    { 0, 0, 0, 0 },
27033
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANQI), 0 } },
27034
    & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_direct_QI, { 0x98b400 }
27035
  },
27036
/* or.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
27037
  {
27038
    { 0, 0, 0, 0 },
27039
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
27040
    & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_indirect_QI, { 0x988600 }
27041
  },
27042
/* or.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */
27043
  {
27044
    { 0, 0, 0, 0 },
27045
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
27046
    & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_indirect_QI, { 0x98a600 }
27047
  },
27048
/* or.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */
27049
  {
27050
    { 0, 0, 0, 0 },
27051
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
27052
    & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_indirect_QI, { 0x98b600 }
27053
  },
27054
/* or.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
27055
  {
27056
    { 0, 0, 0, 0 },
27057
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
27058
    & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_An_relative_QI, { 0x98880000 }
27059
  },
27060
/* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
27061
  {
27062
    { 0, 0, 0, 0 },
27063
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
27064
    & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_An_relative_QI, { 0x98a80000 }
27065
  },
27066
/* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
27067
  {
27068
    { 0, 0, 0, 0 },
27069
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
27070
    & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_An_relative_QI, { 0x98b80000 }
27071
  },
27072
/* or.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
27073
  {
27074
    { 0, 0, 0, 0 },
27075
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
27076
    & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_An_relative_QI, { 0x988c0000 }
27077
  },
27078
/* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
27079
  {
27080
    { 0, 0, 0, 0 },
27081
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
27082
    & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_An_relative_QI, { 0x98ac0000 }
27083
  },
27084
/* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
27085
  {
27086
    { 0, 0, 0, 0 },
27087
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
27088
    & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_An_relative_QI, { 0x98bc0000 }
27089
  },
27090
/* or.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
27091
  {
27092
    { 0, 0, 0, 0 },
27093
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
27094
    & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_SB_relative_QI, { 0x988a0000 }
27095
  },
27096
/* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
27097
  {
27098
    { 0, 0, 0, 0 },
27099
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
27100
    & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_SB_relative_QI, { 0x98aa0000 }
27101
  },
27102
/* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
27103
  {
27104
    { 0, 0, 0, 0 },
27105
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
27106
    & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_SB_relative_QI, { 0x98ba0000 }
27107
  },
27108
/* or.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
27109
  {
27110
    { 0, 0, 0, 0 },
27111
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
27112
    & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_SB_relative_QI, { 0x988e0000 }
27113
  },
27114
/* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
27115
  {
27116
    { 0, 0, 0, 0 },
27117
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
27118
    & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_SB_relative_QI, { 0x98ae0000 }
27119
  },
27120
/* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
27121
  {
27122
    { 0, 0, 0, 0 },
27123
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
27124
    & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_SB_relative_QI, { 0x98be0000 }
27125
  },
27126
/* or.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
27127
  {
27128
    { 0, 0, 0, 0 },
27129
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
27130
    & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_FB_relative_QI, { 0x988b0000 }
27131
  },
27132
/* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
27133
  {
27134
    { 0, 0, 0, 0 },
27135
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
27136
    & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_FB_relative_QI, { 0x98ab0000 }
27137
  },
27138
/* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
27139
  {
27140
    { 0, 0, 0, 0 },
27141
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
27142
    & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_FB_relative_QI, { 0x98bb0000 }
27143
  },
27144
/* or.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
27145
  {
27146
    { 0, 0, 0, 0 },
27147
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } },
27148
    & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_absolute_QI, { 0x988f0000 }
27149
  },
27150
/* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
27151
  {
27152
    { 0, 0, 0, 0 },
27153
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
27154
    & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_absolute_QI, { 0x98af0000 }
27155
  },
27156
/* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
27157
  {
27158
    { 0, 0, 0, 0 },
27159
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
27160
    & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_absolute_QI, { 0x98bf0000 }
27161
  },
27162
/* or.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
27163
  {
27164
    { 0, 0, 0, 0 },
27165
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } },
27166
    & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_Rn_direct_QI, { 0x98c00000 }
27167
  },
27168
/* or.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */
27169
  {
27170
    { 0, 0, 0, 0 },
27171
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } },
27172
    & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_Rn_direct_QI, { 0x98e00000 }
27173
  },
27174
/* or.b${G} ${Dsp-16-u16},$Dst16RnQI */
27175
  {
27176
    { 0, 0, 0, 0 },
27177
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16RNQI), 0 } },
27178
    & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_Rn_direct_QI, { 0x98f00000 }
27179
  },
27180
/* or.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
27181
  {
27182
    { 0, 0, 0, 0 },
27183
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } },
27184
    & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_direct_QI, { 0x98c40000 }
27185
  },
27186
/* or.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */
27187
  {
27188
    { 0, 0, 0, 0 },
27189
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } },
27190
    & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_direct_QI, { 0x98e40000 }
27191
  },
27192
/* or.b${G} ${Dsp-16-u16},$Dst16AnQI */
27193
  {
27194
    { 0, 0, 0, 0 },
27195
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16ANQI), 0 } },
27196
    & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_direct_QI, { 0x98f40000 }
27197
  },
27198
/* or.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
27199
  {
27200
    { 0, 0, 0, 0 },
27201
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
27202
    & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_indirect_QI, { 0x98c60000 }
27203
  },
27204
/* or.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */
27205
  {
27206
    { 0, 0, 0, 0 },
27207
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
27208
    & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_indirect_QI, { 0x98e60000 }
27209
  },
27210
/* or.b${G} ${Dsp-16-u16},[$Dst16An] */
27211
  {
27212
    { 0, 0, 0, 0 },
27213
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } },
27214
    & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_indirect_QI, { 0x98f60000 }
27215
  },
27216
/* or.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
27217
  {
27218
    { 0, 0, 0, 0 },
27219
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
27220
    & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_An_relative_QI, { 0x98c80000 }
27221
  },
27222
/* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
27223
  {
27224
    { 0, 0, 0, 0 },
27225
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
27226
    & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_An_relative_QI, { 0x98e80000 }
27227
  },
27228
/* or.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
27229
  {
27230
    { 0, 0, 0, 0 },
27231
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
27232
    & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_An_relative_QI, { 0x98f80000 }
27233
  },
27234
/* or.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
27235
  {
27236
    { 0, 0, 0, 0 },
27237
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
27238
    & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_An_relative_QI, { 0x98cc0000 }
27239
  },
27240
/* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
27241
  {
27242
    { 0, 0, 0, 0 },
27243
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
27244
    & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_An_relative_QI, { 0x98ec0000 }
27245
  },
27246
/* or.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
27247
  {
27248
    { 0, 0, 0, 0 },
27249
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
27250
    & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_An_relative_QI, { 0x98fc0000 }
27251
  },
27252
/* or.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
27253
  {
27254
    { 0, 0, 0, 0 },
27255
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
27256
    & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_SB_relative_QI, { 0x98ca0000 }
27257
  },
27258
/* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
27259
  {
27260
    { 0, 0, 0, 0 },
27261
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
27262
    & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_SB_relative_QI, { 0x98ea0000 }
27263
  },
27264
/* or.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
27265
  {
27266
    { 0, 0, 0, 0 },
27267
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
27268
    & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_SB_relative_QI, { 0x98fa0000 }
27269
  },
27270
/* or.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
27271
  {
27272
    { 0, 0, 0, 0 },
27273
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
27274
    & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_SB_relative_QI, { 0x98ce0000 }
27275
  },
27276
/* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
27277
  {
27278
    { 0, 0, 0, 0 },
27279
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
27280
    & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_SB_relative_QI, { 0x98ee0000 }
27281
  },
27282
/* or.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
27283
  {
27284
    { 0, 0, 0, 0 },
27285
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
27286
    & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_SB_relative_QI, { 0x98fe0000 }
27287
  },
27288
/* or.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
27289
  {
27290
    { 0, 0, 0, 0 },
27291
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
27292
    & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_FB_relative_QI, { 0x98cb0000 }
27293
  },
27294
/* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
27295
  {
27296
    { 0, 0, 0, 0 },
27297
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
27298
    & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_FB_relative_QI, { 0x98eb0000 }
27299
  },
27300
/* or.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
27301
  {
27302
    { 0, 0, 0, 0 },
27303
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
27304
    & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_FB_relative_QI, { 0x98fb0000 }
27305
  },
27306
/* or.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
27307
  {
27308
    { 0, 0, 0, 0 },
27309
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } },
27310
    & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_absolute_QI, { 0x98cf0000 }
27311
  },
27312
/* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
27313
  {
27314
    { 0, 0, 0, 0 },
27315
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
27316
    & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_absolute_QI, { 0x98ef0000 }
27317
  },
27318
/* or.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
27319
  {
27320
    { 0, 0, 0, 0 },
27321
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
27322
    & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_absolute_QI, { 0x98ff0000 }
27323
  },
27324
/* or.b${G} $Src16RnQI,$Dst16RnQI */
27325
  {
27326
    { 0, 0, 0, 0 },
27327
    { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DST16RNQI), 0 } },
27328
    & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_Rn_direct_QI, { 0x9800 }
27329
  },
27330
/* or.b${G} $Src16AnQI,$Dst16RnQI */
27331
  {
27332
    { 0, 0, 0, 0 },
27333
    { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DST16RNQI), 0 } },
27334
    & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_Rn_direct_QI, { 0x9840 }
27335
  },
27336
/* or.b${G} [$Src16An],$Dst16RnQI */
27337
  {
27338
    { 0, 0, 0, 0 },
27339
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } },
27340
    & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_Rn_direct_QI, { 0x9860 }
27341
  },
27342
/* or.b${G} $Src16RnQI,$Dst16AnQI */
27343
  {
27344
    { 0, 0, 0, 0 },
27345
    { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DST16ANQI), 0 } },
27346
    & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_direct_QI, { 0x9804 }
27347
  },
27348
/* or.b${G} $Src16AnQI,$Dst16AnQI */
27349
  {
27350
    { 0, 0, 0, 0 },
27351
    { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DST16ANQI), 0 } },
27352
    & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_direct_QI, { 0x9844 }
27353
  },
27354
/* or.b${G} [$Src16An],$Dst16AnQI */
27355
  {
27356
    { 0, 0, 0, 0 },
27357
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } },
27358
    & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_direct_QI, { 0x9864 }
27359
  },
27360
/* or.b${G} $Src16RnQI,[$Dst16An] */
27361
  {
27362
    { 0, 0, 0, 0 },
27363
    { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', '[', OP (DST16AN), ']', 0 } },
27364
    & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_indirect_QI, { 0x9806 }
27365
  },
27366
/* or.b${G} $Src16AnQI,[$Dst16An] */
27367
  {
27368
    { 0, 0, 0, 0 },
27369
    { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', '[', OP (DST16AN), ']', 0 } },
27370
    & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_indirect_QI, { 0x9846 }
27371
  },
27372
/* or.b${G} [$Src16An],[$Dst16An] */
27373
  {
27374
    { 0, 0, 0, 0 },
27375
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
27376
    & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_indirect_QI, { 0x9866 }
27377
  },
27378
/* or.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
27379
  {
27380
    { 0, 0, 0, 0 },
27381
    { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
27382
    & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_An_relative_QI, { 0x980800 }
27383
  },
27384
/* or.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
27385
  {
27386
    { 0, 0, 0, 0 },
27387
    { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
27388
    & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_An_relative_QI, { 0x984800 }
27389
  },
27390
/* or.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
27391
  {
27392
    { 0, 0, 0, 0 },
27393
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
27394
    & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_An_relative_QI, { 0x986800 }
27395
  },
27396
/* or.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
27397
  {
27398
    { 0, 0, 0, 0 },
27399
    { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
27400
    & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_An_relative_QI, { 0x980c0000 }
27401
  },
27402
/* or.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
27403
  {
27404
    { 0, 0, 0, 0 },
27405
    { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
27406
    & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_An_relative_QI, { 0x984c0000 }
27407
  },
27408
/* or.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
27409
  {
27410
    { 0, 0, 0, 0 },
27411
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
27412
    & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_An_relative_QI, { 0x986c0000 }
27413
  },
27414
/* or.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */
27415
  {
27416
    { 0, 0, 0, 0 },
27417
    { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
27418
    & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_SB_relative_QI, { 0x980a00 }
27419
  },
27420
/* or.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */
27421
  {
27422
    { 0, 0, 0, 0 },
27423
    { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
27424
    & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_SB_relative_QI, { 0x984a00 }
27425
  },
27426
/* or.b${G} [$Src16An],${Dsp-16-u8}[sb] */
27427
  {
27428
    { 0, 0, 0, 0 },
27429
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
27430
    & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_SB_relative_QI, { 0x986a00 }
27431
  },
27432
/* or.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */
27433
  {
27434
    { 0, 0, 0, 0 },
27435
    { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
27436
    & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_SB_relative_QI, { 0x980e0000 }
27437
  },
27438
/* or.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */
27439
  {
27440
    { 0, 0, 0, 0 },
27441
    { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
27442
    & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_SB_relative_QI, { 0x984e0000 }
27443
  },
27444
/* or.b${G} [$Src16An],${Dsp-16-u16}[sb] */
27445
  {
27446
    { 0, 0, 0, 0 },
27447
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
27448
    & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_SB_relative_QI, { 0x986e0000 }
27449
  },
27450
/* or.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */
27451
  {
27452
    { 0, 0, 0, 0 },
27453
    { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
27454
    & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_FB_relative_QI, { 0x980b00 }
27455
  },
27456
/* or.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */
27457
  {
27458
    { 0, 0, 0, 0 },
27459
    { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
27460
    & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_FB_relative_QI, { 0x984b00 }
27461
  },
27462
/* or.b${G} [$Src16An],${Dsp-16-s8}[fb] */
27463
  {
27464
    { 0, 0, 0, 0 },
27465
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
27466
    & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_FB_relative_QI, { 0x986b00 }
27467
  },
27468
/* or.b${G} $Src16RnQI,${Dsp-16-u16} */
27469
  {
27470
    { 0, 0, 0, 0 },
27471
    { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), 0 } },
27472
    & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_absolute_QI, { 0x980f0000 }
27473
  },
27474
/* or.b${G} $Src16AnQI,${Dsp-16-u16} */
27475
  {
27476
    { 0, 0, 0, 0 },
27477
    { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), 0 } },
27478
    & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_absolute_QI, { 0x984f0000 }
27479
  },
27480
/* or.b${G} [$Src16An],${Dsp-16-u16} */
27481
  {
27482
    { 0, 0, 0, 0 },
27483
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } },
27484
    & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_absolute_QI, { 0x986f0000 }
27485
  },
27486
/* or.w${S} #${Imm-16-HI},${Dsp-8-u8}[sb] */
27487
  {
27488
    { 0, 0, 0, 0 },
27489
    { { MNEM, OP (S), ' ', '#', OP (IMM_16_HI), ',', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } },
27490
    & ifmt_tst32_w_imm_S_2_S_8_dst32_2_S_8_SB_relative_HI, { 0x65000000 }
27491
  },
27492
/* or.w${S} #${Imm-16-HI},${Dsp-8-s8}[fb] */
27493
  {
27494
    { 0, 0, 0, 0 },
27495
    { { MNEM, OP (S), ' ', '#', OP (IMM_16_HI), ',', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } },
27496
    & ifmt_tst32_w_imm_S_2_S_8_dst32_2_S_8_FB_relative_HI, { 0x75000000 }
27497
  },
27498
/* or.w${S} #${Imm-24-HI},${Dsp-8-u16} */
27499
  {
27500
    { 0, 0, 0, 0 },
27501
    { { MNEM, OP (S), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_8_U16), 0 } },
27502
    & ifmt_tst32_w_imm_S_2_S_16_dst32_2_S_16_absolute_HI, { 0x55000000 }
27503
  },
27504
/* or.w${S} #${Imm-8-HI},r0 */
27505
  {
27506
    { 0, 0, 0, 0 },
27507
    { { MNEM, OP (S), ' ', '#', OP (IMM_8_HI), ',', 'r', '0', 0 } },
27508
    & ifmt_tst32_w_imm_S_2_S_basic_dst32_2_S_R0_direct_HI, { 0x450000 }
27509
  },
27510
/* or.b${S} #${Imm-16-QI},${Dsp-8-u8}[sb] */
27511
  {
27512
    { 0, 0, 0, 0 },
27513
    { { MNEM, OP (S), ' ', '#', OP (IMM_16_QI), ',', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } },
27514
    & ifmt_tst32_b_imm_S_2_S_8_dst32_2_S_8_SB_relative_QI, { 0x640000 }
27515
  },
27516
/* or.b${S} #${Imm-16-QI},${Dsp-8-s8}[fb] */
27517
  {
27518
    { 0, 0, 0, 0 },
27519
    { { MNEM, OP (S), ' ', '#', OP (IMM_16_QI), ',', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } },
27520
    & ifmt_tst32_b_imm_S_2_S_8_dst32_2_S_8_FB_relative_QI, { 0x740000 }
27521
  },
27522
/* or.b${S} #${Imm-24-QI},${Dsp-8-u16} */
27523
  {
27524
    { 0, 0, 0, 0 },
27525
    { { MNEM, OP (S), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_8_U16), 0 } },
27526
    & ifmt_tst32_b_imm_S_2_S_16_dst32_2_S_16_absolute_QI, { 0x54000000 }
27527
  },
27528
/* or.b${S} #${Imm-8-QI},r0l */
27529
  {
27530
    { 0, 0, 0, 0 },
27531
    { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'l', 0 } },
27532
    & ifmt_tst32_b_imm_S_2_S_basic_dst32_2_S_R0l_direct_QI, { 0x4400 }
27533
  },
27534
/* or.b${S} #${Imm-8-QI},r0l */
27535
  {
27536
    { 0, 0, 0, 0 },
27537
    { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'l', 0 } },
27538
    & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_R0l_direct_QI, { 0x9c00 }
27539
  },
27540
/* or.b${S} #${Imm-8-QI},r0h */
27541
  {
27542
    { 0, 0, 0, 0 },
27543
    { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'h', 0 } },
27544
    & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_R0h_direct_QI, { 0x9b00 }
27545
  },
27546
/* or.b${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */
27547
  {
27548
    { 0, 0, 0, 0 },
27549
    { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
27550
    & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_8_SB_relative_QI, { 0x9d0000 }
27551
  },
27552
/* or.b${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */
27553
  {
27554
    { 0, 0, 0, 0 },
27555
    { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
27556
    & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_8_FB_relative_QI, { 0x9e0000 }
27557
  },
27558
/* or.b${S} #${Imm-8-QI},${Dsp-16-u16} */
27559
  {
27560
    { 0, 0, 0, 0 },
27561
    { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_U16), 0 } },
27562
    & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_16_absolute_QI, { 0x9f000000 }
27563
  },
27564
/* or.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */
27565
  {
27566
    { 0, 0, 0, 0 },
27567
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
27568
    & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0x892f0000 }
27569
  },
27570
/* or.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */
27571
  {
27572
    { 0, 0, 0, 0 },
27573
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
27574
    & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0x81af0000 }
27575
  },
27576
/* or.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */
27577
  {
27578
    { 0, 0, 0, 0 },
27579
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
27580
    & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0x812f0000 }
27581
  },
27582
/* or.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
27583
  {
27584
    { 0, 0, 0, 0 },
27585
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
27586
    & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0x832f0000 }
27587
  },
27588
/* or.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
27589
  {
27590
    { 0, 0, 0, 0 },
27591
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
27592
    & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0x83af0000 }
27593
  },
27594
/* or.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
27595
  {
27596
    { 0, 0, 0, 0 },
27597
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
27598
    & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83ef0000 }
27599
  },
27600
/* or.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
27601
  {
27602
    { 0, 0, 0, 0 },
27603
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
27604
    & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0x852f0000 }
27605
  },
27606
/* or.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
27607
  {
27608
    { 0, 0, 0, 0 },
27609
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
27610
    & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0x85af0000 }
27611
  },
27612
/* or.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */
27613
  {
27614
    { 0, 0, 0, 0 },
27615
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
27616
    & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85ef0000 }
27617
  },
27618
/* or.w${G} #${Imm-32-HI},${Dsp-16-u16} */
27619
  {
27620
    { 0, 0, 0, 0 },
27621
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } },
27622
    & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0x87ef0000 }
27623
  },
27624
/* or.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
27625
  {
27626
    { 0, 0, 0, 0 },
27627
    { { MNEM, OP (G), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
27628
    & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0x872f0000 }
27629
  },
27630
/* or.w${G} #${Imm-40-HI},${Dsp-16-u24} */
27631
  {
27632
    { 0, 0, 0, 0 },
27633
    { { MNEM, OP (G), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), 0 } },
27634
    & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0x87af0000 }
27635
  },
27636
/* or.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */
27637
  {
27638
    { 0, 0, 0, 0 },
27639
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
27640
    & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0x882f00 }
27641
  },
27642
/* or.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */
27643
  {
27644
    { 0, 0, 0, 0 },
27645
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
27646
    & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0x80af00 }
27647
  },
27648
/* or.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */
27649
  {
27650
    { 0, 0, 0, 0 },
27651
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
27652
    & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0x802f00 }
27653
  },
27654
/* or.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
27655
  {
27656
    { 0, 0, 0, 0 },
27657
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
27658
    & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0x822f0000 }
27659
  },
27660
/* or.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
27661
  {
27662
    { 0, 0, 0, 0 },
27663
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
27664
    & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0x82af0000 }
27665
  },
27666
/* or.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
27667
  {
27668
    { 0, 0, 0, 0 },
27669
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
27670
    & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82ef0000 }
27671
  },
27672
/* or.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
27673
  {
27674
    { 0, 0, 0, 0 },
27675
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
27676
    & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0x842f0000 }
27677
  },
27678
/* or.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
27679
  {
27680
    { 0, 0, 0, 0 },
27681
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
27682
    & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0x84af0000 }
27683
  },
27684
/* or.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */
27685
  {
27686
    { 0, 0, 0, 0 },
27687
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
27688
    & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84ef0000 }
27689
  },
27690
/* or.b${G} #${Imm-32-QI},${Dsp-16-u16} */
27691
  {
27692
    { 0, 0, 0, 0 },
27693
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } },
27694
    & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0x86ef0000 }
27695
  },
27696
/* or.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
27697
  {
27698
    { 0, 0, 0, 0 },
27699
    { { MNEM, OP (G), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
27700
    & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0x862f0000 }
27701
  },
27702
/* or.b${G} #${Imm-40-QI},${Dsp-16-u24} */
27703
  {
27704
    { 0, 0, 0, 0 },
27705
    { { MNEM, OP (G), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), 0 } },
27706
    & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0x86af0000 }
27707
  },
27708
/* or.w${G} #${Imm-16-HI},$Dst16RnHI */
27709
  {
27710
    { 0, 0, 0, 0 },
27711
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST16RNHI), 0 } },
27712
    & ifmt_xor16_w_imm_G_basic_dst16_Rn_direct_HI, { 0x77300000 }
27713
  },
27714
/* or.w${G} #${Imm-16-HI},$Dst16AnHI */
27715
  {
27716
    { 0, 0, 0, 0 },
27717
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST16ANHI), 0 } },
27718
    & ifmt_xor16_w_imm_G_basic_dst16_An_direct_HI, { 0x77340000 }
27719
  },
27720
/* or.w${G} #${Imm-16-HI},[$Dst16An] */
27721
  {
27722
    { 0, 0, 0, 0 },
27723
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST16AN), ']', 0 } },
27724
    & ifmt_xor16_w_imm_G_basic_dst16_An_indirect_HI, { 0x77360000 }
27725
  },
27726
/* or.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
27727
  {
27728
    { 0, 0, 0, 0 },
27729
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
27730
    & ifmt_xor16_w_imm_G_16_8_dst16_16_8_An_relative_HI, { 0x77380000 }
27731
  },
27732
/* or.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
27733
  {
27734
    { 0, 0, 0, 0 },
27735
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
27736
    & ifmt_xor16_w_imm_G_16_8_dst16_16_8_SB_relative_HI, { 0x773a0000 }
27737
  },
27738
/* or.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
27739
  {
27740
    { 0, 0, 0, 0 },
27741
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
27742
    & ifmt_xor16_w_imm_G_16_8_dst16_16_8_FB_relative_HI, { 0x773b0000 }
27743
  },
27744
/* or.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
27745
  {
27746
    { 0, 0, 0, 0 },
27747
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
27748
    & ifmt_xor16_w_imm_G_16_16_dst16_16_16_An_relative_HI, { 0x773c0000 }
27749
  },
27750
/* or.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
27751
  {
27752
    { 0, 0, 0, 0 },
27753
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
27754
    & ifmt_xor16_w_imm_G_16_16_dst16_16_16_SB_relative_HI, { 0x773e0000 }
27755
  },
27756
/* or.w${G} #${Imm-32-HI},${Dsp-16-u16} */
27757
  {
27758
    { 0, 0, 0, 0 },
27759
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } },
27760
    & ifmt_xor16_w_imm_G_16_16_dst16_16_16_absolute_HI, { 0x773f0000 }
27761
  },
27762
/* or.b${G} #${Imm-16-QI},$Dst16RnQI */
27763
  {
27764
    { 0, 0, 0, 0 },
27765
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST16RNQI), 0 } },
27766
    & ifmt_xor16_b_imm_G_basic_dst16_Rn_direct_QI, { 0x763000 }
27767
  },
27768
/* or.b${G} #${Imm-16-QI},$Dst16AnQI */
27769
  {
27770
    { 0, 0, 0, 0 },
27771
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST16ANQI), 0 } },
27772
    & ifmt_xor16_b_imm_G_basic_dst16_An_direct_QI, { 0x763400 }
27773
  },
27774
/* or.b${G} #${Imm-16-QI},[$Dst16An] */
27775
  {
27776
    { 0, 0, 0, 0 },
27777
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST16AN), ']', 0 } },
27778
    & ifmt_xor16_b_imm_G_basic_dst16_An_indirect_QI, { 0x763600 }
27779
  },
27780
/* or.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
27781
  {
27782
    { 0, 0, 0, 0 },
27783
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
27784
    & ifmt_xor16_b_imm_G_16_8_dst16_16_8_An_relative_QI, { 0x76380000 }
27785
  },
27786
/* or.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
27787
  {
27788
    { 0, 0, 0, 0 },
27789
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
27790
    & ifmt_xor16_b_imm_G_16_8_dst16_16_8_SB_relative_QI, { 0x763a0000 }
27791
  },
27792
/* or.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
27793
  {
27794
    { 0, 0, 0, 0 },
27795
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
27796
    & ifmt_xor16_b_imm_G_16_8_dst16_16_8_FB_relative_QI, { 0x763b0000 }
27797
  },
27798
/* or.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
27799
  {
27800
    { 0, 0, 0, 0 },
27801
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
27802
    & ifmt_xor16_b_imm_G_16_16_dst16_16_16_An_relative_QI, { 0x763c0000 }
27803
  },
27804
/* or.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
27805
  {
27806
    { 0, 0, 0, 0 },
27807
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
27808
    & ifmt_xor16_b_imm_G_16_16_dst16_16_16_SB_relative_QI, { 0x763e0000 }
27809
  },
27810
/* or.b${G} #${Imm-32-QI},${Dsp-16-u16} */
27811
  {
27812
    { 0, 0, 0, 0 },
27813
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } },
27814
    & ifmt_xor16_b_imm_G_16_16_dst16_16_16_absolute_QI, { 0x763f0000 }
27815
  },
27816
/* not.b:s r0l */
27817
  {
27818
    { 0, 0, 0, 0 },
27819
    { { MNEM, ' ', 'r', '0', 'l', 0 } },
27820
    & ifmt_not16_b_s_dst16_3_S_R0l_direct_QI, { 0xbc }
27821
  },
27822
/* not.b:s r0h */
27823
  {
27824
    { 0, 0, 0, 0 },
27825
    { { MNEM, ' ', 'r', '0', 'h', 0 } },
27826
    & ifmt_not16_b_s_dst16_3_S_R0h_direct_QI, { 0xbb }
27827
  },
27828
/* not.b:s ${Dsp-8-u8}[sb] */
27829
  {
27830
    { 0, 0, 0, 0 },
27831
    { { MNEM, ' ', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } },
27832
    & ifmt_not16_b_s_dst16_3_S_8_8_SB_relative_QI, { 0xbd00 }
27833
  },
27834
/* not.b:s ${Dsp-8-s8}[fb] */
27835
  {
27836
    { 0, 0, 0, 0 },
27837
    { { MNEM, ' ', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } },
27838
    & ifmt_not16_b_s_dst16_3_S_8_8_FB_relative_QI, { 0xbe00 }
27839
  },
27840
/* not.b:s ${Dsp-8-u16} */
27841
  {
27842
    { 0, 0, 0, 0 },
27843
    { { MNEM, ' ', OP (DSP_8_U16), 0 } },
27844
    & ifmt_not16_b_s_dst16_3_S_8_16_absolute_QI, { 0xbf0000 }
27845
  },
27846
/* not.w${G} $Dst32RnUnprefixedHI */
27847
  {
27848
    { 0, 0, 0, 0 },
27849
    { { MNEM, OP (G), ' ', OP (DST32RNUNPREFIXEDHI), 0 } },
27850
    & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xa91e }
27851
  },
27852
/* not.w${G} $Dst32AnUnprefixedHI */
27853
  {
27854
    { 0, 0, 0, 0 },
27855
    { { MNEM, OP (G), ' ', OP (DST32ANUNPREFIXEDHI), 0 } },
27856
    & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xa19e }
27857
  },
27858
/* not.w${G} [$Dst32AnUnprefixed] */
27859
  {
27860
    { 0, 0, 0, 0 },
27861
    { { MNEM, OP (G), ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
27862
    & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xa11e }
27863
  },
27864
/* not.w${G} ${Dsp-16-u8}[$Dst32AnUnprefixed] */
27865
  {
27866
    { 0, 0, 0, 0 },
27867
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
27868
    & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xa31e00 }
27869
  },
27870
/* not.w${G} ${Dsp-16-u16}[$Dst32AnUnprefixed] */
27871
  {
27872
    { 0, 0, 0, 0 },
27873
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
27874
    & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xa51e0000 }
27875
  },
27876
/* not.w${G} ${Dsp-16-u24}[$Dst32AnUnprefixed] */
27877
  {
27878
    { 0, 0, 0, 0 },
27879
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
27880
    & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xa71e0000 }
27881
  },
27882
/* not.w${G} ${Dsp-16-u8}[sb] */
27883
  {
27884
    { 0, 0, 0, 0 },
27885
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
27886
    & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xa39e00 }
27887
  },
27888
/* not.w${G} ${Dsp-16-u16}[sb] */
27889
  {
27890
    { 0, 0, 0, 0 },
27891
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
27892
    & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xa59e0000 }
27893
  },
27894
/* not.w${G} ${Dsp-16-s8}[fb] */
27895
  {
27896
    { 0, 0, 0, 0 },
27897
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
27898
    & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xa3de00 }
27899
  },
27900
/* not.w${G} ${Dsp-16-s16}[fb] */
27901
  {
27902
    { 0, 0, 0, 0 },
27903
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
27904
    & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xa5de0000 }
27905
  },
27906
/* not.w${G} ${Dsp-16-u16} */
27907
  {
27908
    { 0, 0, 0, 0 },
27909
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), 0 } },
27910
    & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xa7de0000 }
27911
  },
27912
/* not.w${G} ${Dsp-16-u24} */
27913
  {
27914
    { 0, 0, 0, 0 },
27915
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), 0 } },
27916
    & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xa79e0000 }
27917
  },
27918
/* not.b${G} $Dst32RnUnprefixedQI */
27919
  {
27920
    { 0, 0, 0, 0 },
27921
    { { MNEM, OP (G), ' ', OP (DST32RNUNPREFIXEDQI), 0 } },
27922
    & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0xa81e }
27923
  },
27924
/* not.b${G} $Dst32AnUnprefixedQI */
27925
  {
27926
    { 0, 0, 0, 0 },
27927
    { { MNEM, OP (G), ' ', OP (DST32ANUNPREFIXEDQI), 0 } },
27928
    & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0xa09e }
27929
  },
27930
/* not.b${G} [$Dst32AnUnprefixed] */
27931
  {
27932
    { 0, 0, 0, 0 },
27933
    { { MNEM, OP (G), ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
27934
    & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0xa01e }
27935
  },
27936
/* not.b${G} ${Dsp-16-u8}[$Dst32AnUnprefixed] */
27937
  {
27938
    { 0, 0, 0, 0 },
27939
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
27940
    & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0xa21e00 }
27941
  },
27942
/* not.b${G} ${Dsp-16-u16}[$Dst32AnUnprefixed] */
27943
  {
27944
    { 0, 0, 0, 0 },
27945
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
27946
    & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0xa41e0000 }
27947
  },
27948
/* not.b${G} ${Dsp-16-u24}[$Dst32AnUnprefixed] */
27949
  {
27950
    { 0, 0, 0, 0 },
27951
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
27952
    & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0xa61e0000 }
27953
  },
27954
/* not.b${G} ${Dsp-16-u8}[sb] */
27955
  {
27956
    { 0, 0, 0, 0 },
27957
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
27958
    & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0xa29e00 }
27959
  },
27960
/* not.b${G} ${Dsp-16-u16}[sb] */
27961
  {
27962
    { 0, 0, 0, 0 },
27963
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
27964
    & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0xa49e0000 }
27965
  },
27966
/* not.b${G} ${Dsp-16-s8}[fb] */
27967
  {
27968
    { 0, 0, 0, 0 },
27969
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
27970
    & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0xa2de00 }
27971
  },
27972
/* not.b${G} ${Dsp-16-s16}[fb] */
27973
  {
27974
    { 0, 0, 0, 0 },
27975
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
27976
    & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0xa4de0000 }
27977
  },
27978
/* not.b${G} ${Dsp-16-u16} */
27979
  {
27980
    { 0, 0, 0, 0 },
27981
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), 0 } },
27982
    & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0xa6de0000 }
27983
  },
27984
/* not.b${G} ${Dsp-16-u24} */
27985
  {
27986
    { 0, 0, 0, 0 },
27987
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), 0 } },
27988
    & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0xa69e0000 }
27989
  },
27990
/* not.w${G} $Dst16RnHI */
27991
  {
27992
    { 0, 0, 0, 0 },
27993
    { { MNEM, OP (G), ' ', OP (DST16RNHI), 0 } },
27994
    & ifmt_rorc16_w_16_dst16_Rn_direct_HI, { 0x7570 }
27995
  },
27996
/* not.w${G} $Dst16AnHI */
27997
  {
27998
    { 0, 0, 0, 0 },
27999
    { { MNEM, OP (G), ' ', OP (DST16ANHI), 0 } },
28000
    & ifmt_rorc16_w_16_dst16_An_direct_HI, { 0x7574 }
28001
  },
28002
/* not.w${G} [$Dst16An] */
28003
  {
28004
    { 0, 0, 0, 0 },
28005
    { { MNEM, OP (G), ' ', '[', OP (DST16AN), ']', 0 } },
28006
    & ifmt_rorc16_w_16_dst16_An_indirect_HI, { 0x7576 }
28007
  },
28008
/* not.w${G} ${Dsp-16-u8}[$Dst16An] */
28009
  {
28010
    { 0, 0, 0, 0 },
28011
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
28012
    & ifmt_rorc16_w_16_dst16_16_8_An_relative_HI, { 0x757800 }
28013
  },
28014
/* not.w${G} ${Dsp-16-u16}[$Dst16An] */
28015
  {
28016
    { 0, 0, 0, 0 },
28017
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
28018
    & ifmt_rorc16_w_16_dst16_16_16_An_relative_HI, { 0x757c0000 }
28019
  },
28020
/* not.w${G} ${Dsp-16-u8}[sb] */
28021
  {
28022
    { 0, 0, 0, 0 },
28023
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
28024
    & ifmt_rorc16_w_16_dst16_16_8_SB_relative_HI, { 0x757a00 }
28025
  },
28026
/* not.w${G} ${Dsp-16-u16}[sb] */
28027
  {
28028
    { 0, 0, 0, 0 },
28029
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
28030
    & ifmt_rorc16_w_16_dst16_16_16_SB_relative_HI, { 0x757e0000 }
28031
  },
28032
/* not.w${G} ${Dsp-16-s8}[fb] */
28033
  {
28034
    { 0, 0, 0, 0 },
28035
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
28036
    & ifmt_rorc16_w_16_dst16_16_8_FB_relative_HI, { 0x757b00 }
28037
  },
28038
/* not.w${G} ${Dsp-16-u16} */
28039
  {
28040
    { 0, 0, 0, 0 },
28041
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), 0 } },
28042
    & ifmt_rorc16_w_16_dst16_16_16_absolute_HI, { 0x757f0000 }
28043
  },
28044
/* not.b${G} $Dst16RnQI */
28045
  {
28046
    { 0, 0, 0, 0 },
28047
    { { MNEM, OP (G), ' ', OP (DST16RNQI), 0 } },
28048
    & ifmt_rorc16_b_16_dst16_Rn_direct_QI, { 0x7470 }
28049
  },
28050
/* not.b${G} $Dst16AnQI */
28051
  {
28052
    { 0, 0, 0, 0 },
28053
    { { MNEM, OP (G), ' ', OP (DST16ANQI), 0 } },
28054
    & ifmt_rorc16_b_16_dst16_An_direct_QI, { 0x7474 }
28055
  },
28056
/* not.b${G} [$Dst16An] */
28057
  {
28058
    { 0, 0, 0, 0 },
28059
    { { MNEM, OP (G), ' ', '[', OP (DST16AN), ']', 0 } },
28060
    & ifmt_rorc16_b_16_dst16_An_indirect_QI, { 0x7476 }
28061
  },
28062
/* not.b${G} ${Dsp-16-u8}[$Dst16An] */
28063
  {
28064
    { 0, 0, 0, 0 },
28065
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
28066
    & ifmt_rorc16_b_16_dst16_16_8_An_relative_QI, { 0x747800 }
28067
  },
28068
/* not.b${G} ${Dsp-16-u16}[$Dst16An] */
28069
  {
28070
    { 0, 0, 0, 0 },
28071
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
28072
    & ifmt_rorc16_b_16_dst16_16_16_An_relative_QI, { 0x747c0000 }
28073
  },
28074
/* not.b${G} ${Dsp-16-u8}[sb] */
28075
  {
28076
    { 0, 0, 0, 0 },
28077
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
28078
    & ifmt_rorc16_b_16_dst16_16_8_SB_relative_QI, { 0x747a00 }
28079
  },
28080
/* not.b${G} ${Dsp-16-u16}[sb] */
28081
  {
28082
    { 0, 0, 0, 0 },
28083
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
28084
    & ifmt_rorc16_b_16_dst16_16_16_SB_relative_QI, { 0x747e0000 }
28085
  },
28086
/* not.b${G} ${Dsp-16-s8}[fb] */
28087
  {
28088
    { 0, 0, 0, 0 },
28089
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
28090
    & ifmt_rorc16_b_16_dst16_16_8_FB_relative_QI, { 0x747b00 }
28091
  },
28092
/* not.b${G} ${Dsp-16-u16} */
28093
  {
28094
    { 0, 0, 0, 0 },
28095
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), 0 } },
28096
    & ifmt_rorc16_b_16_dst16_16_16_absolute_QI, { 0x747f0000 }
28097
  },
28098
/* neg.w $Dst32RnUnprefixedHI */
28099
  {
28100
    { 0, 0, 0, 0 },
28101
    { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } },
28102
    & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xa92f }
28103
  },
28104
/* neg.w $Dst32AnUnprefixedHI */
28105
  {
28106
    { 0, 0, 0, 0 },
28107
    { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } },
28108
    & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xa1af }
28109
  },
28110
/* neg.w [$Dst32AnUnprefixed] */
28111
  {
28112
    { 0, 0, 0, 0 },
28113
    { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28114
    & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xa12f }
28115
  },
28116
/* neg.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
28117
  {
28118
    { 0, 0, 0, 0 },
28119
    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28120
    & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xa32f00 }
28121
  },
28122
/* neg.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
28123
  {
28124
    { 0, 0, 0, 0 },
28125
    { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28126
    & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xa52f0000 }
28127
  },
28128
/* neg.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
28129
  {
28130
    { 0, 0, 0, 0 },
28131
    { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28132
    & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xa72f0000 }
28133
  },
28134
/* neg.w ${Dsp-16-u8}[sb] */
28135
  {
28136
    { 0, 0, 0, 0 },
28137
    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
28138
    & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xa3af00 }
28139
  },
28140
/* neg.w ${Dsp-16-u16}[sb] */
28141
  {
28142
    { 0, 0, 0, 0 },
28143
    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
28144
    & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xa5af0000 }
28145
  },
28146
/* neg.w ${Dsp-16-s8}[fb] */
28147
  {
28148
    { 0, 0, 0, 0 },
28149
    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
28150
    & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xa3ef00 }
28151
  },
28152
/* neg.w ${Dsp-16-s16}[fb] */
28153
  {
28154
    { 0, 0, 0, 0 },
28155
    { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
28156
    & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xa5ef0000 }
28157
  },
28158
/* neg.w ${Dsp-16-u16} */
28159
  {
28160
    { 0, 0, 0, 0 },
28161
    { { MNEM, ' ', OP (DSP_16_U16), 0 } },
28162
    & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xa7ef0000 }
28163
  },
28164
/* neg.w ${Dsp-16-u24} */
28165
  {
28166
    { 0, 0, 0, 0 },
28167
    { { MNEM, ' ', OP (DSP_16_U24), 0 } },
28168
    & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xa7af0000 }
28169
  },
28170
/* neg.b $Dst32RnUnprefixedQI */
28171
  {
28172
    { 0, 0, 0, 0 },
28173
    { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } },
28174
    & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0xa82f }
28175
  },
28176
/* neg.b $Dst32AnUnprefixedQI */
28177
  {
28178
    { 0, 0, 0, 0 },
28179
    { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } },
28180
    & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0xa0af }
28181
  },
28182
/* neg.b [$Dst32AnUnprefixed] */
28183
  {
28184
    { 0, 0, 0, 0 },
28185
    { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28186
    & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0xa02f }
28187
  },
28188
/* neg.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
28189
  {
28190
    { 0, 0, 0, 0 },
28191
    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28192
    & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0xa22f00 }
28193
  },
28194
/* neg.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
28195
  {
28196
    { 0, 0, 0, 0 },
28197
    { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28198
    & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0xa42f0000 }
28199
  },
28200
/* neg.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
28201
  {
28202
    { 0, 0, 0, 0 },
28203
    { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28204
    & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0xa62f0000 }
28205
  },
28206
/* neg.b ${Dsp-16-u8}[sb] */
28207
  {
28208
    { 0, 0, 0, 0 },
28209
    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
28210
    & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0xa2af00 }
28211
  },
28212
/* neg.b ${Dsp-16-u16}[sb] */
28213
  {
28214
    { 0, 0, 0, 0 },
28215
    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
28216
    & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0xa4af0000 }
28217
  },
28218
/* neg.b ${Dsp-16-s8}[fb] */
28219
  {
28220
    { 0, 0, 0, 0 },
28221
    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
28222
    & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0xa2ef00 }
28223
  },
28224
/* neg.b ${Dsp-16-s16}[fb] */
28225
  {
28226
    { 0, 0, 0, 0 },
28227
    { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
28228
    & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0xa4ef0000 }
28229
  },
28230
/* neg.b ${Dsp-16-u16} */
28231
  {
28232
    { 0, 0, 0, 0 },
28233
    { { MNEM, ' ', OP (DSP_16_U16), 0 } },
28234
    & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0xa6ef0000 }
28235
  },
28236
/* neg.b ${Dsp-16-u24} */
28237
  {
28238
    { 0, 0, 0, 0 },
28239
    { { MNEM, ' ', OP (DSP_16_U24), 0 } },
28240
    & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0xa6af0000 }
28241
  },
28242
/* neg.w $Dst16RnHI */
28243
  {
28244
    { 0, 0, 0, 0 },
28245
    { { MNEM, ' ', OP (DST16RNHI), 0 } },
28246
    & ifmt_rorc16_w_16_dst16_Rn_direct_HI, { 0x7550 }
28247
  },
28248
/* neg.w $Dst16AnHI */
28249
  {
28250
    { 0, 0, 0, 0 },
28251
    { { MNEM, ' ', OP (DST16ANHI), 0 } },
28252
    & ifmt_rorc16_w_16_dst16_An_direct_HI, { 0x7554 }
28253
  },
28254
/* neg.w [$Dst16An] */
28255
  {
28256
    { 0, 0, 0, 0 },
28257
    { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } },
28258
    & ifmt_rorc16_w_16_dst16_An_indirect_HI, { 0x7556 }
28259
  },
28260
/* neg.w ${Dsp-16-u8}[$Dst16An] */
28261
  {
28262
    { 0, 0, 0, 0 },
28263
    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
28264
    & ifmt_rorc16_w_16_dst16_16_8_An_relative_HI, { 0x755800 }
28265
  },
28266
/* neg.w ${Dsp-16-u16}[$Dst16An] */
28267
  {
28268
    { 0, 0, 0, 0 },
28269
    { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
28270
    & ifmt_rorc16_w_16_dst16_16_16_An_relative_HI, { 0x755c0000 }
28271
  },
28272
/* neg.w ${Dsp-16-u8}[sb] */
28273
  {
28274
    { 0, 0, 0, 0 },
28275
    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
28276
    & ifmt_rorc16_w_16_dst16_16_8_SB_relative_HI, { 0x755a00 }
28277
  },
28278
/* neg.w ${Dsp-16-u16}[sb] */
28279
  {
28280
    { 0, 0, 0, 0 },
28281
    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
28282
    & ifmt_rorc16_w_16_dst16_16_16_SB_relative_HI, { 0x755e0000 }
28283
  },
28284
/* neg.w ${Dsp-16-s8}[fb] */
28285
  {
28286
    { 0, 0, 0, 0 },
28287
    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
28288
    & ifmt_rorc16_w_16_dst16_16_8_FB_relative_HI, { 0x755b00 }
28289
  },
28290
/* neg.w ${Dsp-16-u16} */
28291
  {
28292
    { 0, 0, 0, 0 },
28293
    { { MNEM, ' ', OP (DSP_16_U16), 0 } },
28294
    & ifmt_rorc16_w_16_dst16_16_16_absolute_HI, { 0x755f0000 }
28295
  },
28296
/* neg.b $Dst16RnQI */
28297
  {
28298
    { 0, 0, 0, 0 },
28299
    { { MNEM, ' ', OP (DST16RNQI), 0 } },
28300
    & ifmt_rorc16_b_16_dst16_Rn_direct_QI, { 0x7450 }
28301
  },
28302
/* neg.b $Dst16AnQI */
28303
  {
28304
    { 0, 0, 0, 0 },
28305
    { { MNEM, ' ', OP (DST16ANQI), 0 } },
28306
    & ifmt_rorc16_b_16_dst16_An_direct_QI, { 0x7454 }
28307
  },
28308
/* neg.b [$Dst16An] */
28309
  {
28310
    { 0, 0, 0, 0 },
28311
    { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } },
28312
    & ifmt_rorc16_b_16_dst16_An_indirect_QI, { 0x7456 }
28313
  },
28314
/* neg.b ${Dsp-16-u8}[$Dst16An] */
28315
  {
28316
    { 0, 0, 0, 0 },
28317
    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
28318
    & ifmt_rorc16_b_16_dst16_16_8_An_relative_QI, { 0x745800 }
28319
  },
28320
/* neg.b ${Dsp-16-u16}[$Dst16An] */
28321
  {
28322
    { 0, 0, 0, 0 },
28323
    { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
28324
    & ifmt_rorc16_b_16_dst16_16_16_An_relative_QI, { 0x745c0000 }
28325
  },
28326
/* neg.b ${Dsp-16-u8}[sb] */
28327
  {
28328
    { 0, 0, 0, 0 },
28329
    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
28330
    & ifmt_rorc16_b_16_dst16_16_8_SB_relative_QI, { 0x745a00 }
28331
  },
28332
/* neg.b ${Dsp-16-u16}[sb] */
28333
  {
28334
    { 0, 0, 0, 0 },
28335
    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
28336
    & ifmt_rorc16_b_16_dst16_16_16_SB_relative_QI, { 0x745e0000 }
28337
  },
28338
/* neg.b ${Dsp-16-s8}[fb] */
28339
  {
28340
    { 0, 0, 0, 0 },
28341
    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
28342
    & ifmt_rorc16_b_16_dst16_16_8_FB_relative_QI, { 0x745b00 }
28343
  },
28344
/* neg.b ${Dsp-16-u16} */
28345
  {
28346
    { 0, 0, 0, 0 },
28347
    { { MNEM, ' ', OP (DSP_16_U16), 0 } },
28348
    & ifmt_rorc16_b_16_dst16_16_16_absolute_QI, { 0x745f0000 }
28349
  },
28350
/* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
28351
  {
28352
    { 0, 0, 0, 0 },
28353
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
28354
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x990400 }
28355
  },
28356
/* mulu.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */
28357
  {
28358
    { 0, 0, 0, 0 },
28359
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
28360
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x992400 }
28361
  },
28362
/* mulu.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */
28363
  {
28364
    { 0, 0, 0, 0 },
28365
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
28366
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x993400 }
28367
  },
28368
/* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
28369
  {
28370
    { 0, 0, 0, 0 },
28371
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
28372
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x918400 }
28373
  },
28374
/* mulu.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */
28375
  {
28376
    { 0, 0, 0, 0 },
28377
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
28378
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x91a400 }
28379
  },
28380
/* mulu.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */
28381
  {
28382
    { 0, 0, 0, 0 },
28383
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
28384
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x91b400 }
28385
  },
28386
/* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
28387
  {
28388
    { 0, 0, 0, 0 },
28389
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28390
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x910400 }
28391
  },
28392
/* mulu.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
28393
  {
28394
    { 0, 0, 0, 0 },
28395
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28396
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x912400 }
28397
  },
28398
/* mulu.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
28399
  {
28400
    { 0, 0, 0, 0 },
28401
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28402
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x913400 }
28403
  },
28404
/* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
28405
  {
28406
    { 0, 0, 0, 0 },
28407
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28408
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x93040000 }
28409
  },
28410
/* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
28411
  {
28412
    { 0, 0, 0, 0 },
28413
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28414
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x93240000 }
28415
  },
28416
/* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
28417
  {
28418
    { 0, 0, 0, 0 },
28419
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28420
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x93340000 }
28421
  },
28422
/* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
28423
  {
28424
    { 0, 0, 0, 0 },
28425
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28426
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x95040000 }
28427
  },
28428
/* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
28429
  {
28430
    { 0, 0, 0, 0 },
28431
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28432
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x95240000 }
28433
  },
28434
/* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
28435
  {
28436
    { 0, 0, 0, 0 },
28437
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28438
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x95340000 }
28439
  },
28440
/* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
28441
  {
28442
    { 0, 0, 0, 0 },
28443
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28444
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x97040000 }
28445
  },
28446
/* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
28447
  {
28448
    { 0, 0, 0, 0 },
28449
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28450
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x97240000 }
28451
  },
28452
/* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
28453
  {
28454
    { 0, 0, 0, 0 },
28455
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28456
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x97340000 }
28457
  },
28458
/* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
28459
  {
28460
    { 0, 0, 0, 0 },
28461
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
28462
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93840000 }
28463
  },
28464
/* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
28465
  {
28466
    { 0, 0, 0, 0 },
28467
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
28468
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93a40000 }
28469
  },
28470
/* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
28471
  {
28472
    { 0, 0, 0, 0 },
28473
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
28474
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93b40000 }
28475
  },
28476
/* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
28477
  {
28478
    { 0, 0, 0, 0 },
28479
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
28480
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95840000 }
28481
  },
28482
/* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
28483
  {
28484
    { 0, 0, 0, 0 },
28485
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
28486
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95a40000 }
28487
  },
28488
/* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
28489
  {
28490
    { 0, 0, 0, 0 },
28491
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
28492
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95b40000 }
28493
  },
28494
/* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
28495
  {
28496
    { 0, 0, 0, 0 },
28497
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
28498
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93c40000 }
28499
  },
28500
/* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
28501
  {
28502
    { 0, 0, 0, 0 },
28503
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
28504
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93e40000 }
28505
  },
28506
/* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
28507
  {
28508
    { 0, 0, 0, 0 },
28509
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
28510
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93f40000 }
28511
  },
28512
/* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
28513
  {
28514
    { 0, 0, 0, 0 },
28515
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
28516
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95c40000 }
28517
  },
28518
/* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
28519
  {
28520
    { 0, 0, 0, 0 },
28521
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
28522
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95e40000 }
28523
  },
28524
/* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
28525
  {
28526
    { 0, 0, 0, 0 },
28527
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
28528
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95f40000 }
28529
  },
28530
/* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
28531
  {
28532
    { 0, 0, 0, 0 },
28533
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
28534
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97c40000 }
28535
  },
28536
/* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
28537
  {
28538
    { 0, 0, 0, 0 },
28539
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
28540
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97e40000 }
28541
  },
28542
/* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
28543
  {
28544
    { 0, 0, 0, 0 },
28545
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
28546
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97f40000 }
28547
  },
28548
/* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
28549
  {
28550
    { 0, 0, 0, 0 },
28551
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
28552
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97840000 }
28553
  },
28554
/* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
28555
  {
28556
    { 0, 0, 0, 0 },
28557
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } },
28558
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97a40000 }
28559
  },
28560
/* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
28561
  {
28562
    { 0, 0, 0, 0 },
28563
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } },
28564
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97b40000 }
28565
  },
28566
/* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
28567
  {
28568
    { 0, 0, 0, 0 },
28569
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
28570
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa9040000 }
28571
  },
28572
/* mulu.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */
28573
  {
28574
    { 0, 0, 0, 0 },
28575
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
28576
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa9240000 }
28577
  },
28578
/* mulu.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */
28579
  {
28580
    { 0, 0, 0, 0 },
28581
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
28582
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa9340000 }
28583
  },
28584
/* mulu.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */
28585
  {
28586
    { 0, 0, 0, 0 },
28587
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
28588
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb9340000 }
28589
  },
28590
/* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
28591
  {
28592
    { 0, 0, 0, 0 },
28593
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
28594
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1840000 }
28595
  },
28596
/* mulu.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */
28597
  {
28598
    { 0, 0, 0, 0 },
28599
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
28600
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1a40000 }
28601
  },
28602
/* mulu.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */
28603
  {
28604
    { 0, 0, 0, 0 },
28605
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
28606
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1b40000 }
28607
  },
28608
/* mulu.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */
28609
  {
28610
    { 0, 0, 0, 0 },
28611
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
28612
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1b40000 }
28613
  },
28614
/* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
28615
  {
28616
    { 0, 0, 0, 0 },
28617
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28618
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa1040000 }
28619
  },
28620
/* mulu.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
28621
  {
28622
    { 0, 0, 0, 0 },
28623
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28624
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa1240000 }
28625
  },
28626
/* mulu.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
28627
  {
28628
    { 0, 0, 0, 0 },
28629
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28630
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa1340000 }
28631
  },
28632
/* mulu.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
28633
  {
28634
    { 0, 0, 0, 0 },
28635
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28636
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb1340000 }
28637
  },
28638
/* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
28639
  {
28640
    { 0, 0, 0, 0 },
28641
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28642
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa3040000 }
28643
  },
28644
/* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
28645
  {
28646
    { 0, 0, 0, 0 },
28647
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28648
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa3240000 }
28649
  },
28650
/* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
28651
  {
28652
    { 0, 0, 0, 0 },
28653
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28654
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa3340000 }
28655
  },
28656
/* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
28657
  {
28658
    { 0, 0, 0, 0 },
28659
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28660
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xb3340000 }
28661
  },
28662
/* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
28663
  {
28664
    { 0, 0, 0, 0 },
28665
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28666
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa5040000 }
28667
  },
28668
/* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
28669
  {
28670
    { 0, 0, 0, 0 },
28671
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28672
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa5240000 }
28673
  },
28674
/* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
28675
  {
28676
    { 0, 0, 0, 0 },
28677
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28678
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa5340000 }
28679
  },
28680
/* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
28681
  {
28682
    { 0, 0, 0, 0 },
28683
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28684
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xb5340000 }
28685
  },
28686
/* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
28687
  {
28688
    { 0, 0, 0, 0 },
28689
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28690
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa7040000 }
28691
  },
28692
/* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
28693
  {
28694
    { 0, 0, 0, 0 },
28695
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28696
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa7240000 }
28697
  },
28698
/* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
28699
  {
28700
    { 0, 0, 0, 0 },
28701
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28702
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa7340000 }
28703
  },
28704
/* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
28705
  {
28706
    { 0, 0, 0, 0 },
28707
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28708
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xb7340000 }
28709
  },
28710
/* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
28711
  {
28712
    { 0, 0, 0, 0 },
28713
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
28714
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3840000 }
28715
  },
28716
/* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
28717
  {
28718
    { 0, 0, 0, 0 },
28719
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
28720
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3a40000 }
28721
  },
28722
/* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
28723
  {
28724
    { 0, 0, 0, 0 },
28725
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
28726
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3b40000 }
28727
  },
28728
/* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
28729
  {
28730
    { 0, 0, 0, 0 },
28731
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
28732
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xb3b40000 }
28733
  },
28734
/* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
28735
  {
28736
    { 0, 0, 0, 0 },
28737
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
28738
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5840000 }
28739
  },
28740
/* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
28741
  {
28742
    { 0, 0, 0, 0 },
28743
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
28744
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5a40000 }
28745
  },
28746
/* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
28747
  {
28748
    { 0, 0, 0, 0 },
28749
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
28750
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5b40000 }
28751
  },
28752
/* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
28753
  {
28754
    { 0, 0, 0, 0 },
28755
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
28756
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xb5b40000 }
28757
  },
28758
/* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
28759
  {
28760
    { 0, 0, 0, 0 },
28761
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
28762
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3c40000 }
28763
  },
28764
/* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
28765
  {
28766
    { 0, 0, 0, 0 },
28767
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
28768
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3e40000 }
28769
  },
28770
/* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
28771
  {
28772
    { 0, 0, 0, 0 },
28773
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
28774
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3f40000 }
28775
  },
28776
/* mulu.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
28777
  {
28778
    { 0, 0, 0, 0 },
28779
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
28780
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xb3f40000 }
28781
  },
28782
/* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
28783
  {
28784
    { 0, 0, 0, 0 },
28785
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
28786
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5c40000 }
28787
  },
28788
/* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
28789
  {
28790
    { 0, 0, 0, 0 },
28791
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
28792
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5e40000 }
28793
  },
28794
/* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
28795
  {
28796
    { 0, 0, 0, 0 },
28797
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
28798
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5f40000 }
28799
  },
28800
/* mulu.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
28801
  {
28802
    { 0, 0, 0, 0 },
28803
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
28804
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xb5f40000 }
28805
  },
28806
/* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
28807
  {
28808
    { 0, 0, 0, 0 },
28809
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
28810
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7c40000 }
28811
  },
28812
/* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
28813
  {
28814
    { 0, 0, 0, 0 },
28815
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
28816
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7e40000 }
28817
  },
28818
/* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
28819
  {
28820
    { 0, 0, 0, 0 },
28821
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
28822
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7f40000 }
28823
  },
28824
/* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
28825
  {
28826
    { 0, 0, 0, 0 },
28827
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
28828
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xb7f40000 }
28829
  },
28830
/* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
28831
  {
28832
    { 0, 0, 0, 0 },
28833
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
28834
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7840000 }
28835
  },
28836
/* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
28837
  {
28838
    { 0, 0, 0, 0 },
28839
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
28840
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7a40000 }
28841
  },
28842
/* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
28843
  {
28844
    { 0, 0, 0, 0 },
28845
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
28846
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7b40000 }
28847
  },
28848
/* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u24} */
28849
  {
28850
    { 0, 0, 0, 0 },
28851
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } },
28852
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xb7b40000 }
28853
  },
28854
/* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
28855
  {
28856
    { 0, 0, 0, 0 },
28857
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
28858
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb9040000 }
28859
  },
28860
/* mulu.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */
28861
  {
28862
    { 0, 0, 0, 0 },
28863
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
28864
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb9240000 }
28865
  },
28866
/* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
28867
  {
28868
    { 0, 0, 0, 0 },
28869
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
28870
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1840000 }
28871
  },
28872
/* mulu.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */
28873
  {
28874
    { 0, 0, 0, 0 },
28875
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
28876
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1a40000 }
28877
  },
28878
/* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
28879
  {
28880
    { 0, 0, 0, 0 },
28881
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28882
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb1040000 }
28883
  },
28884
/* mulu.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
28885
  {
28886
    { 0, 0, 0, 0 },
28887
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28888
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb1240000 }
28889
  },
28890
/* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
28891
  {
28892
    { 0, 0, 0, 0 },
28893
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28894
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_An_relative_Unprefixed_HI, { 0xb3040000 }
28895
  },
28896
/* mulu.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
28897
  {
28898
    { 0, 0, 0, 0 },
28899
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28900
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_An_relative_Unprefixed_HI, { 0xb3240000 }
28901
  },
28902
/* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
28903
  {
28904
    { 0, 0, 0, 0 },
28905
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28906
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_An_relative_Unprefixed_HI, { 0xb5040000 }
28907
  },
28908
/* mulu.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
28909
  {
28910
    { 0, 0, 0, 0 },
28911
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28912
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_An_relative_Unprefixed_HI, { 0xb5240000 }
28913
  },
28914
/* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
28915
  {
28916
    { 0, 0, 0, 0 },
28917
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28918
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_24_An_relative_Unprefixed_HI, { 0xb7040000 }
28919
  },
28920
/* mulu.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
28921
  {
28922
    { 0, 0, 0, 0 },
28923
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
28924
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_24_An_relative_Unprefixed_HI, { 0xb7240000 }
28925
  },
28926
/* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
28927
  {
28928
    { 0, 0, 0, 0 },
28929
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
28930
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_SB_relative_Unprefixed_HI, { 0xb3840000 }
28931
  },
28932
/* mulu.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
28933
  {
28934
    { 0, 0, 0, 0 },
28935
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
28936
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_SB_relative_Unprefixed_HI, { 0xb3a40000 }
28937
  },
28938
/* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
28939
  {
28940
    { 0, 0, 0, 0 },
28941
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
28942
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_SB_relative_Unprefixed_HI, { 0xb5840000 }
28943
  },
28944
/* mulu.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
28945
  {
28946
    { 0, 0, 0, 0 },
28947
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
28948
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_SB_relative_Unprefixed_HI, { 0xb5a40000 }
28949
  },
28950
/* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
28951
  {
28952
    { 0, 0, 0, 0 },
28953
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
28954
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_FB_relative_Unprefixed_HI, { 0xb3c40000 }
28955
  },
28956
/* mulu.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
28957
  {
28958
    { 0, 0, 0, 0 },
28959
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
28960
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_FB_relative_Unprefixed_HI, { 0xb3e40000 }
28961
  },
28962
/* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
28963
  {
28964
    { 0, 0, 0, 0 },
28965
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
28966
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_FB_relative_Unprefixed_HI, { 0xb5c40000 }
28967
  },
28968
/* mulu.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
28969
  {
28970
    { 0, 0, 0, 0 },
28971
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
28972
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_FB_relative_Unprefixed_HI, { 0xb5e40000 }
28973
  },
28974
/* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
28975
  {
28976
    { 0, 0, 0, 0 },
28977
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
28978
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_absolute_Unprefixed_HI, { 0xb7c40000 }
28979
  },
28980
/* mulu.w${G} ${Dsp-16-u24},${Dsp-40-u16} */
28981
  {
28982
    { 0, 0, 0, 0 },
28983
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } },
28984
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_absolute_Unprefixed_HI, { 0xb7e40000 }
28985
  },
28986
/* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
28987
  {
28988
    { 0, 0, 0, 0 },
28989
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
28990
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_24_absolute_Unprefixed_HI, { 0xb7840000 }
28991
  },
28992
/* mulu.w${G} ${Dsp-16-u24},${Dsp-40-u24} */
28993
  {
28994
    { 0, 0, 0, 0 },
28995
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } },
28996
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_24_absolute_Unprefixed_HI, { 0xb7a40000 }
28997
  },
28998
/* mulu.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */
28999
  {
29000
    { 0, 0, 0, 0 },
29001
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
29002
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xc904 }
29003
  },
29004
/* mulu.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */
29005
  {
29006
    { 0, 0, 0, 0 },
29007
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
29008
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x8924 }
29009
  },
29010
/* mulu.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
29011
  {
29012
    { 0, 0, 0, 0 },
29013
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
29014
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x8904 }
29015
  },
29016
/* mulu.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */
29017
  {
29018
    { 0, 0, 0, 0 },
29019
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
29020
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xc184 }
29021
  },
29022
/* mulu.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */
29023
  {
29024
    { 0, 0, 0, 0 },
29025
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
29026
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x81a4 }
29027
  },
29028
/* mulu.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
29029
  {
29030
    { 0, 0, 0, 0 },
29031
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
29032
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x8184 }
29033
  },
29034
/* mulu.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */
29035
  {
29036
    { 0, 0, 0, 0 },
29037
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29038
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xc104 }
29039
  },
29040
/* mulu.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */
29041
  {
29042
    { 0, 0, 0, 0 },
29043
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29044
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x8124 }
29045
  },
29046
/* mulu.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
29047
  {
29048
    { 0, 0, 0, 0 },
29049
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29050
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x8104 }
29051
  },
29052
/* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
29053
  {
29054
    { 0, 0, 0, 0 },
29055
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29056
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0xc30400 }
29057
  },
29058
/* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
29059
  {
29060
    { 0, 0, 0, 0 },
29061
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29062
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0x832400 }
29063
  },
29064
/* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
29065
  {
29066
    { 0, 0, 0, 0 },
29067
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29068
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0x830400 }
29069
  },
29070
/* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
29071
  {
29072
    { 0, 0, 0, 0 },
29073
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29074
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0xc5040000 }
29075
  },
29076
/* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
29077
  {
29078
    { 0, 0, 0, 0 },
29079
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29080
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0x85240000 }
29081
  },
29082
/* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
29083
  {
29084
    { 0, 0, 0, 0 },
29085
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29086
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0x85040000 }
29087
  },
29088
/* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
29089
  {
29090
    { 0, 0, 0, 0 },
29091
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29092
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0xc7040000 }
29093
  },
29094
/* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
29095
  {
29096
    { 0, 0, 0, 0 },
29097
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29098
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0x87240000 }
29099
  },
29100
/* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
29101
  {
29102
    { 0, 0, 0, 0 },
29103
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29104
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0x87040000 }
29105
  },
29106
/* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */
29107
  {
29108
    { 0, 0, 0, 0 },
29109
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
29110
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0xc38400 }
29111
  },
29112
/* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */
29113
  {
29114
    { 0, 0, 0, 0 },
29115
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
29116
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0x83a400 }
29117
  },
29118
/* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
29119
  {
29120
    { 0, 0, 0, 0 },
29121
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
29122
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0x838400 }
29123
  },
29124
/* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */
29125
  {
29126
    { 0, 0, 0, 0 },
29127
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
29128
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0xc5840000 }
29129
  },
29130
/* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */
29131
  {
29132
    { 0, 0, 0, 0 },
29133
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
29134
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0x85a40000 }
29135
  },
29136
/* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
29137
  {
29138
    { 0, 0, 0, 0 },
29139
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
29140
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0x85840000 }
29141
  },
29142
/* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */
29143
  {
29144
    { 0, 0, 0, 0 },
29145
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
29146
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0xc3c400 }
29147
  },
29148
/* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */
29149
  {
29150
    { 0, 0, 0, 0 },
29151
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
29152
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83e400 }
29153
  },
29154
/* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
29155
  {
29156
    { 0, 0, 0, 0 },
29157
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
29158
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83c400 }
29159
  },
29160
/* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */
29161
  {
29162
    { 0, 0, 0, 0 },
29163
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
29164
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0xc5c40000 }
29165
  },
29166
/* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */
29167
  {
29168
    { 0, 0, 0, 0 },
29169
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
29170
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85e40000 }
29171
  },
29172
/* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
29173
  {
29174
    { 0, 0, 0, 0 },
29175
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
29176
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85c40000 }
29177
  },
29178
/* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */
29179
  {
29180
    { 0, 0, 0, 0 },
29181
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), 0 } },
29182
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0xc7c40000 }
29183
  },
29184
/* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */
29185
  {
29186
    { 0, 0, 0, 0 },
29187
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), 0 } },
29188
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0x87e40000 }
29189
  },
29190
/* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
29191
  {
29192
    { 0, 0, 0, 0 },
29193
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } },
29194
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0x87c40000 }
29195
  },
29196
/* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */
29197
  {
29198
    { 0, 0, 0, 0 },
29199
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U24), 0 } },
29200
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0xc7840000 }
29201
  },
29202
/* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */
29203
  {
29204
    { 0, 0, 0, 0 },
29205
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U24), 0 } },
29206
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0x87a40000 }
29207
  },
29208
/* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
29209
  {
29210
    { 0, 0, 0, 0 },
29211
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } },
29212
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0x87840000 }
29213
  },
29214
/* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
29215
  {
29216
    { 0, 0, 0, 0 },
29217
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
29218
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x980400 }
29219
  },
29220
/* mulu.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */
29221
  {
29222
    { 0, 0, 0, 0 },
29223
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
29224
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x982400 }
29225
  },
29226
/* mulu.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */
29227
  {
29228
    { 0, 0, 0, 0 },
29229
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
29230
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x983400 }
29231
  },
29232
/* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
29233
  {
29234
    { 0, 0, 0, 0 },
29235
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
29236
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x908400 }
29237
  },
29238
/* mulu.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */
29239
  {
29240
    { 0, 0, 0, 0 },
29241
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
29242
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x90a400 }
29243
  },
29244
/* mulu.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */
29245
  {
29246
    { 0, 0, 0, 0 },
29247
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
29248
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x90b400 }
29249
  },
29250
/* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
29251
  {
29252
    { 0, 0, 0, 0 },
29253
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29254
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x900400 }
29255
  },
29256
/* mulu.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
29257
  {
29258
    { 0, 0, 0, 0 },
29259
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29260
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x902400 }
29261
  },
29262
/* mulu.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
29263
  {
29264
    { 0, 0, 0, 0 },
29265
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29266
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x903400 }
29267
  },
29268
/* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
29269
  {
29270
    { 0, 0, 0, 0 },
29271
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29272
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x92040000 }
29273
  },
29274
/* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
29275
  {
29276
    { 0, 0, 0, 0 },
29277
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29278
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x92240000 }
29279
  },
29280
/* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
29281
  {
29282
    { 0, 0, 0, 0 },
29283
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29284
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x92340000 }
29285
  },
29286
/* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
29287
  {
29288
    { 0, 0, 0, 0 },
29289
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29290
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x94040000 }
29291
  },
29292
/* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
29293
  {
29294
    { 0, 0, 0, 0 },
29295
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29296
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x94240000 }
29297
  },
29298
/* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
29299
  {
29300
    { 0, 0, 0, 0 },
29301
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29302
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x94340000 }
29303
  },
29304
/* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
29305
  {
29306
    { 0, 0, 0, 0 },
29307
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29308
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x96040000 }
29309
  },
29310
/* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
29311
  {
29312
    { 0, 0, 0, 0 },
29313
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29314
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x96240000 }
29315
  },
29316
/* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
29317
  {
29318
    { 0, 0, 0, 0 },
29319
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29320
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x96340000 }
29321
  },
29322
/* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
29323
  {
29324
    { 0, 0, 0, 0 },
29325
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
29326
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92840000 }
29327
  },
29328
/* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
29329
  {
29330
    { 0, 0, 0, 0 },
29331
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
29332
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92a40000 }
29333
  },
29334
/* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
29335
  {
29336
    { 0, 0, 0, 0 },
29337
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
29338
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92b40000 }
29339
  },
29340
/* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
29341
  {
29342
    { 0, 0, 0, 0 },
29343
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
29344
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94840000 }
29345
  },
29346
/* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
29347
  {
29348
    { 0, 0, 0, 0 },
29349
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
29350
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94a40000 }
29351
  },
29352
/* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
29353
  {
29354
    { 0, 0, 0, 0 },
29355
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
29356
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94b40000 }
29357
  },
29358
/* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
29359
  {
29360
    { 0, 0, 0, 0 },
29361
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
29362
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92c40000 }
29363
  },
29364
/* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
29365
  {
29366
    { 0, 0, 0, 0 },
29367
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
29368
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92e40000 }
29369
  },
29370
/* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
29371
  {
29372
    { 0, 0, 0, 0 },
29373
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
29374
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92f40000 }
29375
  },
29376
/* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
29377
  {
29378
    { 0, 0, 0, 0 },
29379
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
29380
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94c40000 }
29381
  },
29382
/* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
29383
  {
29384
    { 0, 0, 0, 0 },
29385
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
29386
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94e40000 }
29387
  },
29388
/* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
29389
  {
29390
    { 0, 0, 0, 0 },
29391
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
29392
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94f40000 }
29393
  },
29394
/* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
29395
  {
29396
    { 0, 0, 0, 0 },
29397
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
29398
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96c40000 }
29399
  },
29400
/* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
29401
  {
29402
    { 0, 0, 0, 0 },
29403
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
29404
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96e40000 }
29405
  },
29406
/* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
29407
  {
29408
    { 0, 0, 0, 0 },
29409
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
29410
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96f40000 }
29411
  },
29412
/* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
29413
  {
29414
    { 0, 0, 0, 0 },
29415
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
29416
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96840000 }
29417
  },
29418
/* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
29419
  {
29420
    { 0, 0, 0, 0 },
29421
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } },
29422
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96a40000 }
29423
  },
29424
/* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
29425
  {
29426
    { 0, 0, 0, 0 },
29427
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } },
29428
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96b40000 }
29429
  },
29430
/* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
29431
  {
29432
    { 0, 0, 0, 0 },
29433
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
29434
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa8040000 }
29435
  },
29436
/* mulu.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */
29437
  {
29438
    { 0, 0, 0, 0 },
29439
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
29440
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa8240000 }
29441
  },
29442
/* mulu.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */
29443
  {
29444
    { 0, 0, 0, 0 },
29445
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
29446
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa8340000 }
29447
  },
29448
/* mulu.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */
29449
  {
29450
    { 0, 0, 0, 0 },
29451
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
29452
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb8340000 }
29453
  },
29454
/* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
29455
  {
29456
    { 0, 0, 0, 0 },
29457
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
29458
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0840000 }
29459
  },
29460
/* mulu.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */
29461
  {
29462
    { 0, 0, 0, 0 },
29463
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
29464
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0a40000 }
29465
  },
29466
/* mulu.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */
29467
  {
29468
    { 0, 0, 0, 0 },
29469
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
29470
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0b40000 }
29471
  },
29472
/* mulu.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */
29473
  {
29474
    { 0, 0, 0, 0 },
29475
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
29476
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0b40000 }
29477
  },
29478
/* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
29479
  {
29480
    { 0, 0, 0, 0 },
29481
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29482
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa0040000 }
29483
  },
29484
/* mulu.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
29485
  {
29486
    { 0, 0, 0, 0 },
29487
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29488
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa0240000 }
29489
  },
29490
/* mulu.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
29491
  {
29492
    { 0, 0, 0, 0 },
29493
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29494
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa0340000 }
29495
  },
29496
/* mulu.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
29497
  {
29498
    { 0, 0, 0, 0 },
29499
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29500
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb0340000 }
29501
  },
29502
/* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
29503
  {
29504
    { 0, 0, 0, 0 },
29505
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29506
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa2040000 }
29507
  },
29508
/* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
29509
  {
29510
    { 0, 0, 0, 0 },
29511
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29512
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa2240000 }
29513
  },
29514
/* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
29515
  {
29516
    { 0, 0, 0, 0 },
29517
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29518
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa2340000 }
29519
  },
29520
/* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
29521
  {
29522
    { 0, 0, 0, 0 },
29523
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29524
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xb2340000 }
29525
  },
29526
/* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
29527
  {
29528
    { 0, 0, 0, 0 },
29529
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29530
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa4040000 }
29531
  },
29532
/* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
29533
  {
29534
    { 0, 0, 0, 0 },
29535
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29536
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa4240000 }
29537
  },
29538
/* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
29539
  {
29540
    { 0, 0, 0, 0 },
29541
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29542
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa4340000 }
29543
  },
29544
/* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
29545
  {
29546
    { 0, 0, 0, 0 },
29547
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29548
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xb4340000 }
29549
  },
29550
/* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
29551
  {
29552
    { 0, 0, 0, 0 },
29553
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29554
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa6040000 }
29555
  },
29556
/* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
29557
  {
29558
    { 0, 0, 0, 0 },
29559
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29560
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa6240000 }
29561
  },
29562
/* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
29563
  {
29564
    { 0, 0, 0, 0 },
29565
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29566
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa6340000 }
29567
  },
29568
/* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
29569
  {
29570
    { 0, 0, 0, 0 },
29571
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29572
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xb6340000 }
29573
  },
29574
/* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
29575
  {
29576
    { 0, 0, 0, 0 },
29577
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
29578
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2840000 }
29579
  },
29580
/* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
29581
  {
29582
    { 0, 0, 0, 0 },
29583
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
29584
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2a40000 }
29585
  },
29586
/* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
29587
  {
29588
    { 0, 0, 0, 0 },
29589
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
29590
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2b40000 }
29591
  },
29592
/* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
29593
  {
29594
    { 0, 0, 0, 0 },
29595
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
29596
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xb2b40000 }
29597
  },
29598
/* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
29599
  {
29600
    { 0, 0, 0, 0 },
29601
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
29602
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4840000 }
29603
  },
29604
/* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
29605
  {
29606
    { 0, 0, 0, 0 },
29607
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
29608
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4a40000 }
29609
  },
29610
/* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
29611
  {
29612
    { 0, 0, 0, 0 },
29613
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
29614
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4b40000 }
29615
  },
29616
/* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
29617
  {
29618
    { 0, 0, 0, 0 },
29619
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
29620
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xb4b40000 }
29621
  },
29622
/* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
29623
  {
29624
    { 0, 0, 0, 0 },
29625
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
29626
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2c40000 }
29627
  },
29628
/* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
29629
  {
29630
    { 0, 0, 0, 0 },
29631
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
29632
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2e40000 }
29633
  },
29634
/* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
29635
  {
29636
    { 0, 0, 0, 0 },
29637
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
29638
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2f40000 }
29639
  },
29640
/* mulu.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
29641
  {
29642
    { 0, 0, 0, 0 },
29643
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
29644
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xb2f40000 }
29645
  },
29646
/* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
29647
  {
29648
    { 0, 0, 0, 0 },
29649
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
29650
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4c40000 }
29651
  },
29652
/* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
29653
  {
29654
    { 0, 0, 0, 0 },
29655
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
29656
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4e40000 }
29657
  },
29658
/* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
29659
  {
29660
    { 0, 0, 0, 0 },
29661
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
29662
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4f40000 }
29663
  },
29664
/* mulu.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
29665
  {
29666
    { 0, 0, 0, 0 },
29667
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
29668
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xb4f40000 }
29669
  },
29670
/* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
29671
  {
29672
    { 0, 0, 0, 0 },
29673
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
29674
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6c40000 }
29675
  },
29676
/* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
29677
  {
29678
    { 0, 0, 0, 0 },
29679
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
29680
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6e40000 }
29681
  },
29682
/* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
29683
  {
29684
    { 0, 0, 0, 0 },
29685
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
29686
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6f40000 }
29687
  },
29688
/* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
29689
  {
29690
    { 0, 0, 0, 0 },
29691
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
29692
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xb6f40000 }
29693
  },
29694
/* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
29695
  {
29696
    { 0, 0, 0, 0 },
29697
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
29698
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6840000 }
29699
  },
29700
/* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
29701
  {
29702
    { 0, 0, 0, 0 },
29703
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
29704
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6a40000 }
29705
  },
29706
/* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
29707
  {
29708
    { 0, 0, 0, 0 },
29709
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
29710
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6b40000 }
29711
  },
29712
/* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u24} */
29713
  {
29714
    { 0, 0, 0, 0 },
29715
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } },
29716
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xb6b40000 }
29717
  },
29718
/* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
29719
  {
29720
    { 0, 0, 0, 0 },
29721
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
29722
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb8040000 }
29723
  },
29724
/* mulu.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */
29725
  {
29726
    { 0, 0, 0, 0 },
29727
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
29728
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb8240000 }
29729
  },
29730
/* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
29731
  {
29732
    { 0, 0, 0, 0 },
29733
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
29734
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0840000 }
29735
  },
29736
/* mulu.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */
29737
  {
29738
    { 0, 0, 0, 0 },
29739
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
29740
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0a40000 }
29741
  },
29742
/* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
29743
  {
29744
    { 0, 0, 0, 0 },
29745
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29746
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb0040000 }
29747
  },
29748
/* mulu.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
29749
  {
29750
    { 0, 0, 0, 0 },
29751
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29752
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb0240000 }
29753
  },
29754
/* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
29755
  {
29756
    { 0, 0, 0, 0 },
29757
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29758
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_QI, { 0xb2040000 }
29759
  },
29760
/* mulu.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
29761
  {
29762
    { 0, 0, 0, 0 },
29763
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29764
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_QI, { 0xb2240000 }
29765
  },
29766
/* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
29767
  {
29768
    { 0, 0, 0, 0 },
29769
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29770
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_QI, { 0xb4040000 }
29771
  },
29772
/* mulu.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
29773
  {
29774
    { 0, 0, 0, 0 },
29775
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29776
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_QI, { 0xb4240000 }
29777
  },
29778
/* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
29779
  {
29780
    { 0, 0, 0, 0 },
29781
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29782
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_QI, { 0xb6040000 }
29783
  },
29784
/* mulu.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
29785
  {
29786
    { 0, 0, 0, 0 },
29787
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29788
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_QI, { 0xb6240000 }
29789
  },
29790
/* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
29791
  {
29792
    { 0, 0, 0, 0 },
29793
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
29794
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_QI, { 0xb2840000 }
29795
  },
29796
/* mulu.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
29797
  {
29798
    { 0, 0, 0, 0 },
29799
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
29800
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_QI, { 0xb2a40000 }
29801
  },
29802
/* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
29803
  {
29804
    { 0, 0, 0, 0 },
29805
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
29806
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_QI, { 0xb4840000 }
29807
  },
29808
/* mulu.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
29809
  {
29810
    { 0, 0, 0, 0 },
29811
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
29812
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_QI, { 0xb4a40000 }
29813
  },
29814
/* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
29815
  {
29816
    { 0, 0, 0, 0 },
29817
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
29818
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_QI, { 0xb2c40000 }
29819
  },
29820
/* mulu.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
29821
  {
29822
    { 0, 0, 0, 0 },
29823
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
29824
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_QI, { 0xb2e40000 }
29825
  },
29826
/* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
29827
  {
29828
    { 0, 0, 0, 0 },
29829
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
29830
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_QI, { 0xb4c40000 }
29831
  },
29832
/* mulu.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
29833
  {
29834
    { 0, 0, 0, 0 },
29835
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
29836
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_QI, { 0xb4e40000 }
29837
  },
29838
/* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
29839
  {
29840
    { 0, 0, 0, 0 },
29841
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
29842
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_QI, { 0xb6c40000 }
29843
  },
29844
/* mulu.b${G} ${Dsp-16-u24},${Dsp-40-u16} */
29845
  {
29846
    { 0, 0, 0, 0 },
29847
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } },
29848
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_QI, { 0xb6e40000 }
29849
  },
29850
/* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
29851
  {
29852
    { 0, 0, 0, 0 },
29853
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
29854
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_QI, { 0xb6840000 }
29855
  },
29856
/* mulu.b${G} ${Dsp-16-u24},${Dsp-40-u24} */
29857
  {
29858
    { 0, 0, 0, 0 },
29859
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } },
29860
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_QI, { 0xb6a40000 }
29861
  },
29862
/* mulu.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */
29863
  {
29864
    { 0, 0, 0, 0 },
29865
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
29866
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xc804 }
29867
  },
29868
/* mulu.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */
29869
  {
29870
    { 0, 0, 0, 0 },
29871
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
29872
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x8824 }
29873
  },
29874
/* mulu.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
29875
  {
29876
    { 0, 0, 0, 0 },
29877
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
29878
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x8804 }
29879
  },
29880
/* mulu.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */
29881
  {
29882
    { 0, 0, 0, 0 },
29883
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
29884
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xc084 }
29885
  },
29886
/* mulu.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */
29887
  {
29888
    { 0, 0, 0, 0 },
29889
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
29890
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x80a4 }
29891
  },
29892
/* mulu.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
29893
  {
29894
    { 0, 0, 0, 0 },
29895
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
29896
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x8084 }
29897
  },
29898
/* mulu.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */
29899
  {
29900
    { 0, 0, 0, 0 },
29901
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29902
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xc004 }
29903
  },
29904
/* mulu.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */
29905
  {
29906
    { 0, 0, 0, 0 },
29907
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29908
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x8024 }
29909
  },
29910
/* mulu.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
29911
  {
29912
    { 0, 0, 0, 0 },
29913
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29914
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x8004 }
29915
  },
29916
/* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
29917
  {
29918
    { 0, 0, 0, 0 },
29919
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29920
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0xc20400 }
29921
  },
29922
/* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
29923
  {
29924
    { 0, 0, 0, 0 },
29925
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29926
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0x822400 }
29927
  },
29928
/* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
29929
  {
29930
    { 0, 0, 0, 0 },
29931
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29932
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0x820400 }
29933
  },
29934
/* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
29935
  {
29936
    { 0, 0, 0, 0 },
29937
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29938
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0xc4040000 }
29939
  },
29940
/* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
29941
  {
29942
    { 0, 0, 0, 0 },
29943
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29944
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0x84240000 }
29945
  },
29946
/* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
29947
  {
29948
    { 0, 0, 0, 0 },
29949
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29950
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0x84040000 }
29951
  },
29952
/* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
29953
  {
29954
    { 0, 0, 0, 0 },
29955
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29956
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0xc6040000 }
29957
  },
29958
/* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
29959
  {
29960
    { 0, 0, 0, 0 },
29961
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29962
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0x86240000 }
29963
  },
29964
/* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
29965
  {
29966
    { 0, 0, 0, 0 },
29967
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
29968
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0x86040000 }
29969
  },
29970
/* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */
29971
  {
29972
    { 0, 0, 0, 0 },
29973
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
29974
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0xc28400 }
29975
  },
29976
/* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */
29977
  {
29978
    { 0, 0, 0, 0 },
29979
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
29980
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0x82a400 }
29981
  },
29982
/* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
29983
  {
29984
    { 0, 0, 0, 0 },
29985
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
29986
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0x828400 }
29987
  },
29988
/* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */
29989
  {
29990
    { 0, 0, 0, 0 },
29991
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
29992
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0xc4840000 }
29993
  },
29994
/* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */
29995
  {
29996
    { 0, 0, 0, 0 },
29997
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
29998
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0x84a40000 }
29999
  },
30000
/* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
30001
  {
30002
    { 0, 0, 0, 0 },
30003
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
30004
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0x84840000 }
30005
  },
30006
/* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */
30007
  {
30008
    { 0, 0, 0, 0 },
30009
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
30010
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0xc2c400 }
30011
  },
30012
/* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */
30013
  {
30014
    { 0, 0, 0, 0 },
30015
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
30016
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82e400 }
30017
  },
30018
/* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
30019
  {
30020
    { 0, 0, 0, 0 },
30021
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
30022
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82c400 }
30023
  },
30024
/* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */
30025
  {
30026
    { 0, 0, 0, 0 },
30027
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
30028
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0xc4c40000 }
30029
  },
30030
/* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */
30031
  {
30032
    { 0, 0, 0, 0 },
30033
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
30034
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84e40000 }
30035
  },
30036
/* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
30037
  {
30038
    { 0, 0, 0, 0 },
30039
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
30040
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84c40000 }
30041
  },
30042
/* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */
30043
  {
30044
    { 0, 0, 0, 0 },
30045
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), 0 } },
30046
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0xc6c40000 }
30047
  },
30048
/* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */
30049
  {
30050
    { 0, 0, 0, 0 },
30051
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), 0 } },
30052
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0x86e40000 }
30053
  },
30054
/* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
30055
  {
30056
    { 0, 0, 0, 0 },
30057
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } },
30058
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0x86c40000 }
30059
  },
30060
/* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */
30061
  {
30062
    { 0, 0, 0, 0 },
30063
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U24), 0 } },
30064
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0xc6840000 }
30065
  },
30066
/* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */
30067
  {
30068
    { 0, 0, 0, 0 },
30069
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U24), 0 } },
30070
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0x86a40000 }
30071
  },
30072
/* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
30073
  {
30074
    { 0, 0, 0, 0 },
30075
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } },
30076
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0x86840000 }
30077
  },
30078
/* mulu.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
30079
  {
30080
    { 0, 0, 0, 0 },
30081
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } },
30082
    & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_Rn_direct_HI, { 0x718000 }
30083
  },
30084
/* mulu.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */
30085
  {
30086
    { 0, 0, 0, 0 },
30087
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } },
30088
    & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_Rn_direct_HI, { 0x71a000 }
30089
  },
30090
/* mulu.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */
30091
  {
30092
    { 0, 0, 0, 0 },
30093
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNHI), 0 } },
30094
    & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_Rn_direct_HI, { 0x71b000 }
30095
  },
30096
/* mulu.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
30097
  {
30098
    { 0, 0, 0, 0 },
30099
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } },
30100
    & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_direct_HI, { 0x718400 }
30101
  },
30102
/* mulu.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */
30103
  {
30104
    { 0, 0, 0, 0 },
30105
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } },
30106
    & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_direct_HI, { 0x71a400 }
30107
  },
30108
/* mulu.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */
30109
  {
30110
    { 0, 0, 0, 0 },
30111
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANHI), 0 } },
30112
    & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_direct_HI, { 0x71b400 }
30113
  },
30114
/* mulu.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
30115
  {
30116
    { 0, 0, 0, 0 },
30117
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
30118
    & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_indirect_HI, { 0x718600 }
30119
  },
30120
/* mulu.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */
30121
  {
30122
    { 0, 0, 0, 0 },
30123
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
30124
    & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_indirect_HI, { 0x71a600 }
30125
  },
30126
/* mulu.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */
30127
  {
30128
    { 0, 0, 0, 0 },
30129
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
30130
    & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_indirect_HI, { 0x71b600 }
30131
  },
30132
/* mulu.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
30133
  {
30134
    { 0, 0, 0, 0 },
30135
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
30136
    & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_An_relative_HI, { 0x71880000 }
30137
  },
30138
/* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
30139
  {
30140
    { 0, 0, 0, 0 },
30141
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
30142
    & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_An_relative_HI, { 0x71a80000 }
30143
  },
30144
/* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
30145
  {
30146
    { 0, 0, 0, 0 },
30147
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
30148
    & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_An_relative_HI, { 0x71b80000 }
30149
  },
30150
/* mulu.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
30151
  {
30152
    { 0, 0, 0, 0 },
30153
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
30154
    & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_An_relative_HI, { 0x718c0000 }
30155
  },
30156
/* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
30157
  {
30158
    { 0, 0, 0, 0 },
30159
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
30160
    & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_An_relative_HI, { 0x71ac0000 }
30161
  },
30162
/* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
30163
  {
30164
    { 0, 0, 0, 0 },
30165
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
30166
    & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_An_relative_HI, { 0x71bc0000 }
30167
  },
30168
/* mulu.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
30169
  {
30170
    { 0, 0, 0, 0 },
30171
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
30172
    & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_SB_relative_HI, { 0x718a0000 }
30173
  },
30174
/* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
30175
  {
30176
    { 0, 0, 0, 0 },
30177
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
30178
    & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_SB_relative_HI, { 0x71aa0000 }
30179
  },
30180
/* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
30181
  {
30182
    { 0, 0, 0, 0 },
30183
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
30184
    & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_SB_relative_HI, { 0x71ba0000 }
30185
  },
30186
/* mulu.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
30187
  {
30188
    { 0, 0, 0, 0 },
30189
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
30190
    & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_SB_relative_HI, { 0x718e0000 }
30191
  },
30192
/* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
30193
  {
30194
    { 0, 0, 0, 0 },
30195
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
30196
    & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_SB_relative_HI, { 0x71ae0000 }
30197
  },
30198
/* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
30199
  {
30200
    { 0, 0, 0, 0 },
30201
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
30202
    & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_SB_relative_HI, { 0x71be0000 }
30203
  },
30204
/* mulu.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
30205
  {
30206
    { 0, 0, 0, 0 },
30207
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
30208
    & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_FB_relative_HI, { 0x718b0000 }
30209
  },
30210
/* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
30211
  {
30212
    { 0, 0, 0, 0 },
30213
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
30214
    & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_FB_relative_HI, { 0x71ab0000 }
30215
  },
30216
/* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
30217
  {
30218
    { 0, 0, 0, 0 },
30219
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
30220
    & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_FB_relative_HI, { 0x71bb0000 }
30221
  },
30222
/* mulu.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
30223
  {
30224
    { 0, 0, 0, 0 },
30225
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } },
30226
    & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_absolute_HI, { 0x718f0000 }
30227
  },
30228
/* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
30229
  {
30230
    { 0, 0, 0, 0 },
30231
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
30232
    & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_absolute_HI, { 0x71af0000 }
30233
  },
30234
/* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
30235
  {
30236
    { 0, 0, 0, 0 },
30237
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
30238
    & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_absolute_HI, { 0x71bf0000 }
30239
  },
30240
/* mulu.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
30241
  {
30242
    { 0, 0, 0, 0 },
30243
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } },
30244
    & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_Rn_direct_HI, { 0x71c00000 }
30245
  },
30246
/* mulu.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */
30247
  {
30248
    { 0, 0, 0, 0 },
30249
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } },
30250
    & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_Rn_direct_HI, { 0x71e00000 }
30251
  },
30252
/* mulu.w${G} ${Dsp-16-u16},$Dst16RnHI */
30253
  {
30254
    { 0, 0, 0, 0 },
30255
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16RNHI), 0 } },
30256
    & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_Rn_direct_HI, { 0x71f00000 }
30257
  },
30258
/* mulu.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
30259
  {
30260
    { 0, 0, 0, 0 },
30261
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } },
30262
    & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_direct_HI, { 0x71c40000 }
30263
  },
30264
/* mulu.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */
30265
  {
30266
    { 0, 0, 0, 0 },
30267
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } },
30268
    & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_direct_HI, { 0x71e40000 }
30269
  },
30270
/* mulu.w${G} ${Dsp-16-u16},$Dst16AnHI */
30271
  {
30272
    { 0, 0, 0, 0 },
30273
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16ANHI), 0 } },
30274
    & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_direct_HI, { 0x71f40000 }
30275
  },
30276
/* mulu.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
30277
  {
30278
    { 0, 0, 0, 0 },
30279
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
30280
    & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_indirect_HI, { 0x71c60000 }
30281
  },
30282
/* mulu.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */
30283
  {
30284
    { 0, 0, 0, 0 },
30285
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
30286
    & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_indirect_HI, { 0x71e60000 }
30287
  },
30288
/* mulu.w${G} ${Dsp-16-u16},[$Dst16An] */
30289
  {
30290
    { 0, 0, 0, 0 },
30291
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } },
30292
    & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_indirect_HI, { 0x71f60000 }
30293
  },
30294
/* mulu.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
30295
  {
30296
    { 0, 0, 0, 0 },
30297
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
30298
    & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_An_relative_HI, { 0x71c80000 }
30299
  },
30300
/* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
30301
  {
30302
    { 0, 0, 0, 0 },
30303
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
30304
    & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_An_relative_HI, { 0x71e80000 }
30305
  },
30306
/* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
30307
  {
30308
    { 0, 0, 0, 0 },
30309
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
30310
    & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_An_relative_HI, { 0x71f80000 }
30311
  },
30312
/* mulu.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
30313
  {
30314
    { 0, 0, 0, 0 },
30315
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
30316
    & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_An_relative_HI, { 0x71cc0000 }
30317
  },
30318
/* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
30319
  {
30320
    { 0, 0, 0, 0 },
30321
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
30322
    & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_An_relative_HI, { 0x71ec0000 }
30323
  },
30324
/* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
30325
  {
30326
    { 0, 0, 0, 0 },
30327
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
30328
    & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_An_relative_HI, { 0x71fc0000 }
30329
  },
30330
/* mulu.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
30331
  {
30332
    { 0, 0, 0, 0 },
30333
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
30334
    & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_SB_relative_HI, { 0x71ca0000 }
30335
  },
30336
/* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
30337
  {
30338
    { 0, 0, 0, 0 },
30339
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
30340
    & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_SB_relative_HI, { 0x71ea0000 }
30341
  },
30342
/* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
30343
  {
30344
    { 0, 0, 0, 0 },
30345
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
30346
    & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_SB_relative_HI, { 0x71fa0000 }
30347
  },
30348
/* mulu.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
30349
  {
30350
    { 0, 0, 0, 0 },
30351
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
30352
    & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_SB_relative_HI, { 0x71ce0000 }
30353
  },
30354
/* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
30355
  {
30356
    { 0, 0, 0, 0 },
30357
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
30358
    & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_SB_relative_HI, { 0x71ee0000 }
30359
  },
30360
/* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
30361
  {
30362
    { 0, 0, 0, 0 },
30363
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
30364
    & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_SB_relative_HI, { 0x71fe0000 }
30365
  },
30366
/* mulu.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
30367
  {
30368
    { 0, 0, 0, 0 },
30369
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
30370
    & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_FB_relative_HI, { 0x71cb0000 }
30371
  },
30372
/* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
30373
  {
30374
    { 0, 0, 0, 0 },
30375
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
30376
    & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_FB_relative_HI, { 0x71eb0000 }
30377
  },
30378
/* mulu.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
30379
  {
30380
    { 0, 0, 0, 0 },
30381
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
30382
    & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_FB_relative_HI, { 0x71fb0000 }
30383
  },
30384
/* mulu.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
30385
  {
30386
    { 0, 0, 0, 0 },
30387
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } },
30388
    & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_absolute_HI, { 0x71cf0000 }
30389
  },
30390
/* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
30391
  {
30392
    { 0, 0, 0, 0 },
30393
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
30394
    & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_absolute_HI, { 0x71ef0000 }
30395
  },
30396
/* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
30397
  {
30398
    { 0, 0, 0, 0 },
30399
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
30400
    & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_absolute_HI, { 0x71ff0000 }
30401
  },
30402
/* mulu.w${G} $Src16RnHI,$Dst16RnHI */
30403
  {
30404
    { 0, 0, 0, 0 },
30405
    { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DST16RNHI), 0 } },
30406
    & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_Rn_direct_HI, { 0x7100 }
30407
  },
30408
/* mulu.w${G} $Src16AnHI,$Dst16RnHI */
30409
  {
30410
    { 0, 0, 0, 0 },
30411
    { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DST16RNHI), 0 } },
30412
    & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_Rn_direct_HI, { 0x7140 }
30413
  },
30414
/* mulu.w${G} [$Src16An],$Dst16RnHI */
30415
  {
30416
    { 0, 0, 0, 0 },
30417
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } },
30418
    & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_Rn_direct_HI, { 0x7160 }
30419
  },
30420
/* mulu.w${G} $Src16RnHI,$Dst16AnHI */
30421
  {
30422
    { 0, 0, 0, 0 },
30423
    { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DST16ANHI), 0 } },
30424
    & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_direct_HI, { 0x7104 }
30425
  },
30426
/* mulu.w${G} $Src16AnHI,$Dst16AnHI */
30427
  {
30428
    { 0, 0, 0, 0 },
30429
    { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DST16ANHI), 0 } },
30430
    & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_direct_HI, { 0x7144 }
30431
  },
30432
/* mulu.w${G} [$Src16An],$Dst16AnHI */
30433
  {
30434
    { 0, 0, 0, 0 },
30435
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } },
30436
    & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_direct_HI, { 0x7164 }
30437
  },
30438
/* mulu.w${G} $Src16RnHI,[$Dst16An] */
30439
  {
30440
    { 0, 0, 0, 0 },
30441
    { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', '[', OP (DST16AN), ']', 0 } },
30442
    & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_indirect_HI, { 0x7106 }
30443
  },
30444
/* mulu.w${G} $Src16AnHI,[$Dst16An] */
30445
  {
30446
    { 0, 0, 0, 0 },
30447
    { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', '[', OP (DST16AN), ']', 0 } },
30448
    & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_indirect_HI, { 0x7146 }
30449
  },
30450
/* mulu.w${G} [$Src16An],[$Dst16An] */
30451
  {
30452
    { 0, 0, 0, 0 },
30453
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
30454
    & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_indirect_HI, { 0x7166 }
30455
  },
30456
/* mulu.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
30457
  {
30458
    { 0, 0, 0, 0 },
30459
    { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
30460
    & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_An_relative_HI, { 0x710800 }
30461
  },
30462
/* mulu.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
30463
  {
30464
    { 0, 0, 0, 0 },
30465
    { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
30466
    & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_An_relative_HI, { 0x714800 }
30467
  },
30468
/* mulu.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
30469
  {
30470
    { 0, 0, 0, 0 },
30471
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
30472
    & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_An_relative_HI, { 0x716800 }
30473
  },
30474
/* mulu.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
30475
  {
30476
    { 0, 0, 0, 0 },
30477
    { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
30478
    & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_An_relative_HI, { 0x710c0000 }
30479
  },
30480
/* mulu.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
30481
  {
30482
    { 0, 0, 0, 0 },
30483
    { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
30484
    & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_An_relative_HI, { 0x714c0000 }
30485
  },
30486
/* mulu.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
30487
  {
30488
    { 0, 0, 0, 0 },
30489
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
30490
    & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_An_relative_HI, { 0x716c0000 }
30491
  },
30492
/* mulu.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */
30493
  {
30494
    { 0, 0, 0, 0 },
30495
    { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
30496
    & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_SB_relative_HI, { 0x710a00 }
30497
  },
30498
/* mulu.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */
30499
  {
30500
    { 0, 0, 0, 0 },
30501
    { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
30502
    & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_SB_relative_HI, { 0x714a00 }
30503
  },
30504
/* mulu.w${G} [$Src16An],${Dsp-16-u8}[sb] */
30505
  {
30506
    { 0, 0, 0, 0 },
30507
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
30508
    & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_SB_relative_HI, { 0x716a00 }
30509
  },
30510
/* mulu.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */
30511
  {
30512
    { 0, 0, 0, 0 },
30513
    { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
30514
    & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_SB_relative_HI, { 0x710e0000 }
30515
  },
30516
/* mulu.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */
30517
  {
30518
    { 0, 0, 0, 0 },
30519
    { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
30520
    & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_SB_relative_HI, { 0x714e0000 }
30521
  },
30522
/* mulu.w${G} [$Src16An],${Dsp-16-u16}[sb] */
30523
  {
30524
    { 0, 0, 0, 0 },
30525
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
30526
    & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_SB_relative_HI, { 0x716e0000 }
30527
  },
30528
/* mulu.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */
30529
  {
30530
    { 0, 0, 0, 0 },
30531
    { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
30532
    & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_FB_relative_HI, { 0x710b00 }
30533
  },
30534
/* mulu.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */
30535
  {
30536
    { 0, 0, 0, 0 },
30537
    { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
30538
    & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_FB_relative_HI, { 0x714b00 }
30539
  },
30540
/* mulu.w${G} [$Src16An],${Dsp-16-s8}[fb] */
30541
  {
30542
    { 0, 0, 0, 0 },
30543
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
30544
    & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_FB_relative_HI, { 0x716b00 }
30545
  },
30546
/* mulu.w${G} $Src16RnHI,${Dsp-16-u16} */
30547
  {
30548
    { 0, 0, 0, 0 },
30549
    { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), 0 } },
30550
    & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_absolute_HI, { 0x710f0000 }
30551
  },
30552
/* mulu.w${G} $Src16AnHI,${Dsp-16-u16} */
30553
  {
30554
    { 0, 0, 0, 0 },
30555
    { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), 0 } },
30556
    & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_absolute_HI, { 0x714f0000 }
30557
  },
30558
/* mulu.w${G} [$Src16An],${Dsp-16-u16} */
30559
  {
30560
    { 0, 0, 0, 0 },
30561
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } },
30562
    & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_absolute_HI, { 0x716f0000 }
30563
  },
30564
/* mulu.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
30565
  {
30566
    { 0, 0, 0, 0 },
30567
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } },
30568
    & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_Rn_direct_QI, { 0x708000 }
30569
  },
30570
/* mulu.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */
30571
  {
30572
    { 0, 0, 0, 0 },
30573
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } },
30574
    & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_Rn_direct_QI, { 0x70a000 }
30575
  },
30576
/* mulu.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */
30577
  {
30578
    { 0, 0, 0, 0 },
30579
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNQI), 0 } },
30580
    & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_Rn_direct_QI, { 0x70b000 }
30581
  },
30582
/* mulu.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
30583
  {
30584
    { 0, 0, 0, 0 },
30585
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } },
30586
    & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_direct_QI, { 0x708400 }
30587
  },
30588
/* mulu.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */
30589
  {
30590
    { 0, 0, 0, 0 },
30591
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } },
30592
    & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_direct_QI, { 0x70a400 }
30593
  },
30594
/* mulu.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */
30595
  {
30596
    { 0, 0, 0, 0 },
30597
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANQI), 0 } },
30598
    & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_direct_QI, { 0x70b400 }
30599
  },
30600
/* mulu.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
30601
  {
30602
    { 0, 0, 0, 0 },
30603
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
30604
    & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_indirect_QI, { 0x708600 }
30605
  },
30606
/* mulu.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */
30607
  {
30608
    { 0, 0, 0, 0 },
30609
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
30610
    & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_indirect_QI, { 0x70a600 }
30611
  },
30612
/* mulu.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */
30613
  {
30614
    { 0, 0, 0, 0 },
30615
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
30616
    & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_indirect_QI, { 0x70b600 }
30617
  },
30618
/* mulu.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
30619
  {
30620
    { 0, 0, 0, 0 },
30621
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
30622
    & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_An_relative_QI, { 0x70880000 }
30623
  },
30624
/* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
30625
  {
30626
    { 0, 0, 0, 0 },
30627
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
30628
    & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_An_relative_QI, { 0x70a80000 }
30629
  },
30630
/* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
30631
  {
30632
    { 0, 0, 0, 0 },
30633
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
30634
    & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_An_relative_QI, { 0x70b80000 }
30635
  },
30636
/* mulu.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
30637
  {
30638
    { 0, 0, 0, 0 },
30639
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
30640
    & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_An_relative_QI, { 0x708c0000 }
30641
  },
30642
/* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
30643
  {
30644
    { 0, 0, 0, 0 },
30645
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
30646
    & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_An_relative_QI, { 0x70ac0000 }
30647
  },
30648
/* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
30649
  {
30650
    { 0, 0, 0, 0 },
30651
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
30652
    & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_An_relative_QI, { 0x70bc0000 }
30653
  },
30654
/* mulu.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
30655
  {
30656
    { 0, 0, 0, 0 },
30657
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
30658
    & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_SB_relative_QI, { 0x708a0000 }
30659
  },
30660
/* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
30661
  {
30662
    { 0, 0, 0, 0 },
30663
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
30664
    & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_SB_relative_QI, { 0x70aa0000 }
30665
  },
30666
/* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
30667
  {
30668
    { 0, 0, 0, 0 },
30669
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
30670
    & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_SB_relative_QI, { 0x70ba0000 }
30671
  },
30672
/* mulu.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
30673
  {
30674
    { 0, 0, 0, 0 },
30675
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
30676
    & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_SB_relative_QI, { 0x708e0000 }
30677
  },
30678
/* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
30679
  {
30680
    { 0, 0, 0, 0 },
30681
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
30682
    & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_SB_relative_QI, { 0x70ae0000 }
30683
  },
30684
/* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
30685
  {
30686
    { 0, 0, 0, 0 },
30687
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
30688
    & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_SB_relative_QI, { 0x70be0000 }
30689
  },
30690
/* mulu.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
30691
  {
30692
    { 0, 0, 0, 0 },
30693
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
30694
    & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_FB_relative_QI, { 0x708b0000 }
30695
  },
30696
/* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
30697
  {
30698
    { 0, 0, 0, 0 },
30699
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
30700
    & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_FB_relative_QI, { 0x70ab0000 }
30701
  },
30702
/* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
30703
  {
30704
    { 0, 0, 0, 0 },
30705
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
30706
    & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_FB_relative_QI, { 0x70bb0000 }
30707
  },
30708
/* mulu.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
30709
  {
30710
    { 0, 0, 0, 0 },
30711
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } },
30712
    & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_absolute_QI, { 0x708f0000 }
30713
  },
30714
/* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
30715
  {
30716
    { 0, 0, 0, 0 },
30717
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
30718
    & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_absolute_QI, { 0x70af0000 }
30719
  },
30720
/* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
30721
  {
30722
    { 0, 0, 0, 0 },
30723
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
30724
    & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_absolute_QI, { 0x70bf0000 }
30725
  },
30726
/* mulu.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
30727
  {
30728
    { 0, 0, 0, 0 },
30729
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } },
30730
    & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_Rn_direct_QI, { 0x70c00000 }
30731
  },
30732
/* mulu.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */
30733
  {
30734
    { 0, 0, 0, 0 },
30735
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } },
30736
    & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_Rn_direct_QI, { 0x70e00000 }
30737
  },
30738
/* mulu.b${G} ${Dsp-16-u16},$Dst16RnQI */
30739
  {
30740
    { 0, 0, 0, 0 },
30741
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16RNQI), 0 } },
30742
    & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_Rn_direct_QI, { 0x70f00000 }
30743
  },
30744
/* mulu.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
30745
  {
30746
    { 0, 0, 0, 0 },
30747
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } },
30748
    & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_direct_QI, { 0x70c40000 }
30749
  },
30750
/* mulu.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */
30751
  {
30752
    { 0, 0, 0, 0 },
30753
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } },
30754
    & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_direct_QI, { 0x70e40000 }
30755
  },
30756
/* mulu.b${G} ${Dsp-16-u16},$Dst16AnQI */
30757
  {
30758
    { 0, 0, 0, 0 },
30759
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16ANQI), 0 } },
30760
    & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_direct_QI, { 0x70f40000 }
30761
  },
30762
/* mulu.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
30763
  {
30764
    { 0, 0, 0, 0 },
30765
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
30766
    & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_indirect_QI, { 0x70c60000 }
30767
  },
30768
/* mulu.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */
30769
  {
30770
    { 0, 0, 0, 0 },
30771
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
30772
    & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_indirect_QI, { 0x70e60000 }
30773
  },
30774
/* mulu.b${G} ${Dsp-16-u16},[$Dst16An] */
30775
  {
30776
    { 0, 0, 0, 0 },
30777
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } },
30778
    & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_indirect_QI, { 0x70f60000 }
30779
  },
30780
/* mulu.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
30781
  {
30782
    { 0, 0, 0, 0 },
30783
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
30784
    & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_An_relative_QI, { 0x70c80000 }
30785
  },
30786
/* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
30787
  {
30788
    { 0, 0, 0, 0 },
30789
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
30790
    & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_An_relative_QI, { 0x70e80000 }
30791
  },
30792
/* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
30793
  {
30794
    { 0, 0, 0, 0 },
30795
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
30796
    & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_An_relative_QI, { 0x70f80000 }
30797
  },
30798
/* mulu.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
30799
  {
30800
    { 0, 0, 0, 0 },
30801
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
30802
    & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_An_relative_QI, { 0x70cc0000 }
30803
  },
30804
/* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
30805
  {
30806
    { 0, 0, 0, 0 },
30807
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
30808
    & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_An_relative_QI, { 0x70ec0000 }
30809
  },
30810
/* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
30811
  {
30812
    { 0, 0, 0, 0 },
30813
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
30814
    & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_An_relative_QI, { 0x70fc0000 }
30815
  },
30816
/* mulu.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
30817
  {
30818
    { 0, 0, 0, 0 },
30819
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
30820
    & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_SB_relative_QI, { 0x70ca0000 }
30821
  },
30822
/* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
30823
  {
30824
    { 0, 0, 0, 0 },
30825
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
30826
    & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_SB_relative_QI, { 0x70ea0000 }
30827
  },
30828
/* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
30829
  {
30830
    { 0, 0, 0, 0 },
30831
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
30832
    & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_SB_relative_QI, { 0x70fa0000 }
30833
  },
30834
/* mulu.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
30835
  {
30836
    { 0, 0, 0, 0 },
30837
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
30838
    & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_SB_relative_QI, { 0x70ce0000 }
30839
  },
30840
/* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
30841
  {
30842
    { 0, 0, 0, 0 },
30843
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
30844
    & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_SB_relative_QI, { 0x70ee0000 }
30845
  },
30846
/* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
30847
  {
30848
    { 0, 0, 0, 0 },
30849
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
30850
    & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_SB_relative_QI, { 0x70fe0000 }
30851
  },
30852
/* mulu.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
30853
  {
30854
    { 0, 0, 0, 0 },
30855
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
30856
    & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_FB_relative_QI, { 0x70cb0000 }
30857
  },
30858
/* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
30859
  {
30860
    { 0, 0, 0, 0 },
30861
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
30862
    & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_FB_relative_QI, { 0x70eb0000 }
30863
  },
30864
/* mulu.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
30865
  {
30866
    { 0, 0, 0, 0 },
30867
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
30868
    & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_FB_relative_QI, { 0x70fb0000 }
30869
  },
30870
/* mulu.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
30871
  {
30872
    { 0, 0, 0, 0 },
30873
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } },
30874
    & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_absolute_QI, { 0x70cf0000 }
30875
  },
30876
/* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
30877
  {
30878
    { 0, 0, 0, 0 },
30879
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
30880
    & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_absolute_QI, { 0x70ef0000 }
30881
  },
30882
/* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
30883
  {
30884
    { 0, 0, 0, 0 },
30885
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
30886
    & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_absolute_QI, { 0x70ff0000 }
30887
  },
30888
/* mulu.b${G} $Src16RnQI,$Dst16RnQI */
30889
  {
30890
    { 0, 0, 0, 0 },
30891
    { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DST16RNQI), 0 } },
30892
    & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_Rn_direct_QI, { 0x7000 }
30893
  },
30894
/* mulu.b${G} $Src16AnQI,$Dst16RnQI */
30895
  {
30896
    { 0, 0, 0, 0 },
30897
    { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DST16RNQI), 0 } },
30898
    & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_Rn_direct_QI, { 0x7040 }
30899
  },
30900
/* mulu.b${G} [$Src16An],$Dst16RnQI */
30901
  {
30902
    { 0, 0, 0, 0 },
30903
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } },
30904
    & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_Rn_direct_QI, { 0x7060 }
30905
  },
30906
/* mulu.b${G} $Src16RnQI,$Dst16AnQI */
30907
  {
30908
    { 0, 0, 0, 0 },
30909
    { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DST16ANQI), 0 } },
30910
    & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_direct_QI, { 0x7004 }
30911
  },
30912
/* mulu.b${G} $Src16AnQI,$Dst16AnQI */
30913
  {
30914
    { 0, 0, 0, 0 },
30915
    { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DST16ANQI), 0 } },
30916
    & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_direct_QI, { 0x7044 }
30917
  },
30918
/* mulu.b${G} [$Src16An],$Dst16AnQI */
30919
  {
30920
    { 0, 0, 0, 0 },
30921
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } },
30922
    & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_direct_QI, { 0x7064 }
30923
  },
30924
/* mulu.b${G} $Src16RnQI,[$Dst16An] */
30925
  {
30926
    { 0, 0, 0, 0 },
30927
    { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', '[', OP (DST16AN), ']', 0 } },
30928
    & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_indirect_QI, { 0x7006 }
30929
  },
30930
/* mulu.b${G} $Src16AnQI,[$Dst16An] */
30931
  {
30932
    { 0, 0, 0, 0 },
30933
    { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', '[', OP (DST16AN), ']', 0 } },
30934
    & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_indirect_QI, { 0x7046 }
30935
  },
30936
/* mulu.b${G} [$Src16An],[$Dst16An] */
30937
  {
30938
    { 0, 0, 0, 0 },
30939
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
30940
    & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_indirect_QI, { 0x7066 }
30941
  },
30942
/* mulu.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
30943
  {
30944
    { 0, 0, 0, 0 },
30945
    { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
30946
    & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_An_relative_QI, { 0x700800 }
30947
  },
30948
/* mulu.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
30949
  {
30950
    { 0, 0, 0, 0 },
30951
    { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
30952
    & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_An_relative_QI, { 0x704800 }
30953
  },
30954
/* mulu.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
30955
  {
30956
    { 0, 0, 0, 0 },
30957
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
30958
    & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_An_relative_QI, { 0x706800 }
30959
  },
30960
/* mulu.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
30961
  {
30962
    { 0, 0, 0, 0 },
30963
    { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
30964
    & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_An_relative_QI, { 0x700c0000 }
30965
  },
30966
/* mulu.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
30967
  {
30968
    { 0, 0, 0, 0 },
30969
    { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
30970
    & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_An_relative_QI, { 0x704c0000 }
30971
  },
30972
/* mulu.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
30973
  {
30974
    { 0, 0, 0, 0 },
30975
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
30976
    & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_An_relative_QI, { 0x706c0000 }
30977
  },
30978
/* mulu.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */
30979
  {
30980
    { 0, 0, 0, 0 },
30981
    { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
30982
    & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_SB_relative_QI, { 0x700a00 }
30983
  },
30984
/* mulu.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */
30985
  {
30986
    { 0, 0, 0, 0 },
30987
    { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
30988
    & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_SB_relative_QI, { 0x704a00 }
30989
  },
30990
/* mulu.b${G} [$Src16An],${Dsp-16-u8}[sb] */
30991
  {
30992
    { 0, 0, 0, 0 },
30993
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
30994
    & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_SB_relative_QI, { 0x706a00 }
30995
  },
30996
/* mulu.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */
30997
  {
30998
    { 0, 0, 0, 0 },
30999
    { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
31000
    & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_SB_relative_QI, { 0x700e0000 }
31001
  },
31002
/* mulu.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */
31003
  {
31004
    { 0, 0, 0, 0 },
31005
    { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
31006
    & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_SB_relative_QI, { 0x704e0000 }
31007
  },
31008
/* mulu.b${G} [$Src16An],${Dsp-16-u16}[sb] */
31009
  {
31010
    { 0, 0, 0, 0 },
31011
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
31012
    & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_SB_relative_QI, { 0x706e0000 }
31013
  },
31014
/* mulu.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */
31015
  {
31016
    { 0, 0, 0, 0 },
31017
    { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
31018
    & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_FB_relative_QI, { 0x700b00 }
31019
  },
31020
/* mulu.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */
31021
  {
31022
    { 0, 0, 0, 0 },
31023
    { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
31024
    & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_FB_relative_QI, { 0x704b00 }
31025
  },
31026
/* mulu.b${G} [$Src16An],${Dsp-16-s8}[fb] */
31027
  {
31028
    { 0, 0, 0, 0 },
31029
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
31030
    & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_FB_relative_QI, { 0x706b00 }
31031
  },
31032
/* mulu.b${G} $Src16RnQI,${Dsp-16-u16} */
31033
  {
31034
    { 0, 0, 0, 0 },
31035
    { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), 0 } },
31036
    & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_absolute_QI, { 0x700f0000 }
31037
  },
31038
/* mulu.b${G} $Src16AnQI,${Dsp-16-u16} */
31039
  {
31040
    { 0, 0, 0, 0 },
31041
    { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), 0 } },
31042
    & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_absolute_QI, { 0x704f0000 }
31043
  },
31044
/* mulu.b${G} [$Src16An],${Dsp-16-u16} */
31045
  {
31046
    { 0, 0, 0, 0 },
31047
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } },
31048
    & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_absolute_QI, { 0x706f0000 }
31049
  },
31050
/* mulu.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */
31051
  {
31052
    { 0, 0, 0, 0 },
31053
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
31054
    & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0x890f0000 }
31055
  },
31056
/* mulu.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */
31057
  {
31058
    { 0, 0, 0, 0 },
31059
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
31060
    & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0x818f0000 }
31061
  },
31062
/* mulu.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */
31063
  {
31064
    { 0, 0, 0, 0 },
31065
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31066
    & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0x810f0000 }
31067
  },
31068
/* mulu.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
31069
  {
31070
    { 0, 0, 0, 0 },
31071
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31072
    & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0x830f0000 }
31073
  },
31074
/* mulu.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
31075
  {
31076
    { 0, 0, 0, 0 },
31077
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
31078
    & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0x838f0000 }
31079
  },
31080
/* mulu.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
31081
  {
31082
    { 0, 0, 0, 0 },
31083
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
31084
    & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83cf0000 }
31085
  },
31086
/* mulu.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
31087
  {
31088
    { 0, 0, 0, 0 },
31089
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31090
    & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0x850f0000 }
31091
  },
31092
/* mulu.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
31093
  {
31094
    { 0, 0, 0, 0 },
31095
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
31096
    & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0x858f0000 }
31097
  },
31098
/* mulu.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */
31099
  {
31100
    { 0, 0, 0, 0 },
31101
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
31102
    & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85cf0000 }
31103
  },
31104
/* mulu.w${G} #${Imm-32-HI},${Dsp-16-u16} */
31105
  {
31106
    { 0, 0, 0, 0 },
31107
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } },
31108
    & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0x87cf0000 }
31109
  },
31110
/* mulu.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
31111
  {
31112
    { 0, 0, 0, 0 },
31113
    { { MNEM, OP (G), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31114
    & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0x870f0000 }
31115
  },
31116
/* mulu.w${G} #${Imm-40-HI},${Dsp-16-u24} */
31117
  {
31118
    { 0, 0, 0, 0 },
31119
    { { MNEM, OP (G), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), 0 } },
31120
    & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0x878f0000 }
31121
  },
31122
/* mulu.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */
31123
  {
31124
    { 0, 0, 0, 0 },
31125
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
31126
    & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0x880f00 }
31127
  },
31128
/* mulu.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */
31129
  {
31130
    { 0, 0, 0, 0 },
31131
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
31132
    & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0x808f00 }
31133
  },
31134
/* mulu.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */
31135
  {
31136
    { 0, 0, 0, 0 },
31137
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31138
    & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0x800f00 }
31139
  },
31140
/* mulu.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
31141
  {
31142
    { 0, 0, 0, 0 },
31143
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31144
    & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0x820f0000 }
31145
  },
31146
/* mulu.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
31147
  {
31148
    { 0, 0, 0, 0 },
31149
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
31150
    & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0x828f0000 }
31151
  },
31152
/* mulu.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
31153
  {
31154
    { 0, 0, 0, 0 },
31155
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
31156
    & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82cf0000 }
31157
  },
31158
/* mulu.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
31159
  {
31160
    { 0, 0, 0, 0 },
31161
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31162
    & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0x840f0000 }
31163
  },
31164
/* mulu.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
31165
  {
31166
    { 0, 0, 0, 0 },
31167
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
31168
    & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0x848f0000 }
31169
  },
31170
/* mulu.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */
31171
  {
31172
    { 0, 0, 0, 0 },
31173
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
31174
    & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84cf0000 }
31175
  },
31176
/* mulu.b${G} #${Imm-32-QI},${Dsp-16-u16} */
31177
  {
31178
    { 0, 0, 0, 0 },
31179
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } },
31180
    & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0x86cf0000 }
31181
  },
31182
/* mulu.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
31183
  {
31184
    { 0, 0, 0, 0 },
31185
    { { MNEM, OP (G), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31186
    & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0x860f0000 }
31187
  },
31188
/* mulu.b${G} #${Imm-40-QI},${Dsp-16-u24} */
31189
  {
31190
    { 0, 0, 0, 0 },
31191
    { { MNEM, OP (G), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), 0 } },
31192
    & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0x868f0000 }
31193
  },
31194
/* mulu.w${G} #${Imm-16-HI},$Dst16RnHI */
31195
  {
31196
    { 0, 0, 0, 0 },
31197
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST16RNHI), 0 } },
31198
    & ifmt_xor16_w_imm_G_basic_dst16_Rn_direct_HI, { 0x7d400000 }
31199
  },
31200
/* mulu.w${G} #${Imm-16-HI},$Dst16AnHI */
31201
  {
31202
    { 0, 0, 0, 0 },
31203
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST16ANHI), 0 } },
31204
    & ifmt_xor16_w_imm_G_basic_dst16_An_direct_HI, { 0x7d440000 }
31205
  },
31206
/* mulu.w${G} #${Imm-16-HI},[$Dst16An] */
31207
  {
31208
    { 0, 0, 0, 0 },
31209
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST16AN), ']', 0 } },
31210
    & ifmt_xor16_w_imm_G_basic_dst16_An_indirect_HI, { 0x7d460000 }
31211
  },
31212
/* mulu.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
31213
  {
31214
    { 0, 0, 0, 0 },
31215
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
31216
    & ifmt_xor16_w_imm_G_16_8_dst16_16_8_An_relative_HI, { 0x7d480000 }
31217
  },
31218
/* mulu.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
31219
  {
31220
    { 0, 0, 0, 0 },
31221
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
31222
    & ifmt_xor16_w_imm_G_16_8_dst16_16_8_SB_relative_HI, { 0x7d4a0000 }
31223
  },
31224
/* mulu.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
31225
  {
31226
    { 0, 0, 0, 0 },
31227
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
31228
    & ifmt_xor16_w_imm_G_16_8_dst16_16_8_FB_relative_HI, { 0x7d4b0000 }
31229
  },
31230
/* mulu.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
31231
  {
31232
    { 0, 0, 0, 0 },
31233
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
31234
    & ifmt_xor16_w_imm_G_16_16_dst16_16_16_An_relative_HI, { 0x7d4c0000 }
31235
  },
31236
/* mulu.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
31237
  {
31238
    { 0, 0, 0, 0 },
31239
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
31240
    & ifmt_xor16_w_imm_G_16_16_dst16_16_16_SB_relative_HI, { 0x7d4e0000 }
31241
  },
31242
/* mulu.w${G} #${Imm-32-HI},${Dsp-16-u16} */
31243
  {
31244
    { 0, 0, 0, 0 },
31245
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } },
31246
    & ifmt_xor16_w_imm_G_16_16_dst16_16_16_absolute_HI, { 0x7d4f0000 }
31247
  },
31248
/* mulu.b${G} #${Imm-16-QI},$Dst16RnQI */
31249
  {
31250
    { 0, 0, 0, 0 },
31251
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST16RNQI), 0 } },
31252
    & ifmt_xor16_b_imm_G_basic_dst16_Rn_direct_QI, { 0x7c4000 }
31253
  },
31254
/* mulu.b${G} #${Imm-16-QI},$Dst16AnQI */
31255
  {
31256
    { 0, 0, 0, 0 },
31257
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST16ANQI), 0 } },
31258
    & ifmt_xor16_b_imm_G_basic_dst16_An_direct_QI, { 0x7c4400 }
31259
  },
31260
/* mulu.b${G} #${Imm-16-QI},[$Dst16An] */
31261
  {
31262
    { 0, 0, 0, 0 },
31263
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST16AN), ']', 0 } },
31264
    & ifmt_xor16_b_imm_G_basic_dst16_An_indirect_QI, { 0x7c4600 }
31265
  },
31266
/* mulu.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
31267
  {
31268
    { 0, 0, 0, 0 },
31269
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
31270
    & ifmt_xor16_b_imm_G_16_8_dst16_16_8_An_relative_QI, { 0x7c480000 }
31271
  },
31272
/* mulu.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
31273
  {
31274
    { 0, 0, 0, 0 },
31275
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
31276
    & ifmt_xor16_b_imm_G_16_8_dst16_16_8_SB_relative_QI, { 0x7c4a0000 }
31277
  },
31278
/* mulu.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
31279
  {
31280
    { 0, 0, 0, 0 },
31281
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
31282
    & ifmt_xor16_b_imm_G_16_8_dst16_16_8_FB_relative_QI, { 0x7c4b0000 }
31283
  },
31284
/* mulu.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
31285
  {
31286
    { 0, 0, 0, 0 },
31287
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
31288
    & ifmt_xor16_b_imm_G_16_16_dst16_16_16_An_relative_QI, { 0x7c4c0000 }
31289
  },
31290
/* mulu.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
31291
  {
31292
    { 0, 0, 0, 0 },
31293
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
31294
    & ifmt_xor16_b_imm_G_16_16_dst16_16_16_SB_relative_QI, { 0x7c4e0000 }
31295
  },
31296
/* mulu.b${G} #${Imm-32-QI},${Dsp-16-u16} */
31297
  {
31298
    { 0, 0, 0, 0 },
31299
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } },
31300
    & ifmt_xor16_b_imm_G_16_16_dst16_16_16_absolute_QI, { 0x7c4f0000 }
31301
  },
31302
/* mulex $R3 */
31303
  {
31304
    { 0, 0, 0, 0 },
31305
    { { MNEM, ' ', OP (R3), 0 } },
31306
    & ifmt_mulex_dst32_R3_direct_Unprefixed_HI, { 0xc97e }
31307
  },
31308
/* mulex $Dst32AnUnprefixedHI */
31309
  {
31310
    { 0, 0, 0, 0 },
31311
    { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } },
31312
    & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xc1be }
31313
  },
31314
/* mulex [$Dst32AnUnprefixed] */
31315
  {
31316
    { 0, 0, 0, 0 },
31317
    { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31318
    & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xc13e }
31319
  },
31320
/* mulex ${Dsp-16-u8}[$Dst32AnUnprefixed] */
31321
  {
31322
    { 0, 0, 0, 0 },
31323
    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31324
    & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xc33e00 }
31325
  },
31326
/* mulex ${Dsp-16-u16}[$Dst32AnUnprefixed] */
31327
  {
31328
    { 0, 0, 0, 0 },
31329
    { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31330
    & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xc53e0000 }
31331
  },
31332
/* mulex ${Dsp-16-u24}[$Dst32AnUnprefixed] */
31333
  {
31334
    { 0, 0, 0, 0 },
31335
    { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31336
    & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xc73e0000 }
31337
  },
31338
/* mulex ${Dsp-16-u8}[sb] */
31339
  {
31340
    { 0, 0, 0, 0 },
31341
    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
31342
    & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xc3be00 }
31343
  },
31344
/* mulex ${Dsp-16-u16}[sb] */
31345
  {
31346
    { 0, 0, 0, 0 },
31347
    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
31348
    & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xc5be0000 }
31349
  },
31350
/* mulex ${Dsp-16-s8}[fb] */
31351
  {
31352
    { 0, 0, 0, 0 },
31353
    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
31354
    & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xc3fe00 }
31355
  },
31356
/* mulex ${Dsp-16-s16}[fb] */
31357
  {
31358
    { 0, 0, 0, 0 },
31359
    { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
31360
    & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xc5fe0000 }
31361
  },
31362
/* mulex ${Dsp-16-u16} */
31363
  {
31364
    { 0, 0, 0, 0 },
31365
    { { MNEM, ' ', OP (DSP_16_U16), 0 } },
31366
    & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xc7fe0000 }
31367
  },
31368
/* mulex ${Dsp-16-u24} */
31369
  {
31370
    { 0, 0, 0, 0 },
31371
    { { MNEM, ' ', OP (DSP_16_U24), 0 } },
31372
    & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xc7be0000 }
31373
  },
31374
/* mulu.l $Dst32RnPrefixedSI,r2r0 */
31375
  {
31376
    { 0, 0, 0, 0 },
31377
    { { MNEM, ' ', OP (DST32RNPREFIXEDSI), ',', 'r', '2', 'r', '0', 0 } },
31378
    & ifmt_mulu_l_dst32_Rn_direct_Prefixed_SI, { 0x1890f }
31379
  },
31380
/* mulu.l $Dst32AnPrefixedSI,r2r0 */
31381
  {
31382
    { 0, 0, 0, 0 },
31383
    { { MNEM, ' ', OP (DST32ANPREFIXEDSI), ',', 'r', '2', 'r', '0', 0 } },
31384
    & ifmt_mulu_l_dst32_An_direct_Prefixed_SI, { 0x1818f }
31385
  },
31386
/* mulu.l [$Dst32AnPrefixed],r2r0 */
31387
  {
31388
    { 0, 0, 0, 0 },
31389
    { { MNEM, ' ', '[', OP (DST32ANPREFIXED), ']', ',', 'r', '2', 'r', '0', 0 } },
31390
    & ifmt_mulu_l_dst32_An_indirect_Prefixed_SI, { 0x1810f }
31391
  },
31392
/* mulu.l ${Dsp-24-u8}[$Dst32AnPrefixed],r2r0 */
31393
  {
31394
    { 0, 0, 0, 0 },
31395
    { { MNEM, ' ', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', ',', 'r', '2', 'r', '0', 0 } },
31396
    & ifmt_mulu_l_dst32_24_8_An_relative_Prefixed_SI, { 0x1830f00 }
31397
  },
31398
/* mulu.l ${Dsp-24-u16}[$Dst32AnPrefixed],r2r0 */
31399
  {
31400
    { 0, 0, 0, 0 },
31401
    { { MNEM, ' ', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', ',', 'r', '2', 'r', '0', 0 } },
31402
    & ifmt_mulu_l_dst32_24_16_An_relative_Prefixed_SI, { 0x1850f00 }
31403
  },
31404
/* mulu.l ${Dsp-24-u24}[$Dst32AnPrefixed],r2r0 */
31405
  {
31406
    { 0, 0, 0, 0 },
31407
    { { MNEM, ' ', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', ',', 'r', '2', 'r', '0', 0 } },
31408
    & ifmt_mulu_l_dst32_24_24_An_relative_Prefixed_SI, { 0x1870f00 }
31409
  },
31410
/* mulu.l ${Dsp-24-u8}[sb],r2r0 */
31411
  {
31412
    { 0, 0, 0, 0 },
31413
    { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', 'r', '2', 'r', '0', 0 } },
31414
    & ifmt_mulu_l_dst32_24_8_SB_relative_Prefixed_SI, { 0x1838f00 }
31415
  },
31416
/* mulu.l ${Dsp-24-u16}[sb],r2r0 */
31417
  {
31418
    { 0, 0, 0, 0 },
31419
    { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', 'r', '2', 'r', '0', 0 } },
31420
    & ifmt_mulu_l_dst32_24_16_SB_relative_Prefixed_SI, { 0x1858f00 }
31421
  },
31422
/* mulu.l ${Dsp-24-s8}[fb],r2r0 */
31423
  {
31424
    { 0, 0, 0, 0 },
31425
    { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', 'r', '2', 'r', '0', 0 } },
31426
    & ifmt_mulu_l_dst32_24_8_FB_relative_Prefixed_SI, { 0x183cf00 }
31427
  },
31428
/* mulu.l ${Dsp-24-s16}[fb],r2r0 */
31429
  {
31430
    { 0, 0, 0, 0 },
31431
    { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', 'r', '2', 'r', '0', 0 } },
31432
    & ifmt_mulu_l_dst32_24_16_FB_relative_Prefixed_SI, { 0x185cf00 }
31433
  },
31434
/* mulu.l ${Dsp-24-u16},r2r0 */
31435
  {
31436
    { 0, 0, 0, 0 },
31437
    { { MNEM, ' ', OP (DSP_24_U16), ',', 'r', '2', 'r', '0', 0 } },
31438
    & ifmt_mulu_l_dst32_24_16_absolute_Prefixed_SI, { 0x187cf00 }
31439
  },
31440
/* mulu.l ${Dsp-24-u24},r2r0 */
31441
  {
31442
    { 0, 0, 0, 0 },
31443
    { { MNEM, ' ', OP (DSP_24_U24), ',', 'r', '2', 'r', '0', 0 } },
31444
    & ifmt_mulu_l_dst32_24_24_absolute_Prefixed_SI, { 0x1878f00 }
31445
  },
31446
/* mul.l $Dst32RnPrefixedSI,r2r0 */
31447
  {
31448
    { 0, 0, 0, 0 },
31449
    { { MNEM, ' ', OP (DST32RNPREFIXEDSI), ',', 'r', '2', 'r', '0', 0 } },
31450
    & ifmt_mulu_l_dst32_Rn_direct_Prefixed_SI, { 0x1891f }
31451
  },
31452
/* mul.l $Dst32AnPrefixedSI,r2r0 */
31453
  {
31454
    { 0, 0, 0, 0 },
31455
    { { MNEM, ' ', OP (DST32ANPREFIXEDSI), ',', 'r', '2', 'r', '0', 0 } },
31456
    & ifmt_mulu_l_dst32_An_direct_Prefixed_SI, { 0x1819f }
31457
  },
31458
/* mul.l [$Dst32AnPrefixed],r2r0 */
31459
  {
31460
    { 0, 0, 0, 0 },
31461
    { { MNEM, ' ', '[', OP (DST32ANPREFIXED), ']', ',', 'r', '2', 'r', '0', 0 } },
31462
    & ifmt_mulu_l_dst32_An_indirect_Prefixed_SI, { 0x1811f }
31463
  },
31464
/* mul.l ${Dsp-24-u8}[$Dst32AnPrefixed],r2r0 */
31465
  {
31466
    { 0, 0, 0, 0 },
31467
    { { MNEM, ' ', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', ',', 'r', '2', 'r', '0', 0 } },
31468
    & ifmt_mulu_l_dst32_24_8_An_relative_Prefixed_SI, { 0x1831f00 }
31469
  },
31470
/* mul.l ${Dsp-24-u16}[$Dst32AnPrefixed],r2r0 */
31471
  {
31472
    { 0, 0, 0, 0 },
31473
    { { MNEM, ' ', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', ',', 'r', '2', 'r', '0', 0 } },
31474
    & ifmt_mulu_l_dst32_24_16_An_relative_Prefixed_SI, { 0x1851f00 }
31475
  },
31476
/* mul.l ${Dsp-24-u24}[$Dst32AnPrefixed],r2r0 */
31477
  {
31478
    { 0, 0, 0, 0 },
31479
    { { MNEM, ' ', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', ',', 'r', '2', 'r', '0', 0 } },
31480
    & ifmt_mulu_l_dst32_24_24_An_relative_Prefixed_SI, { 0x1871f00 }
31481
  },
31482
/* mul.l ${Dsp-24-u8}[sb],r2r0 */
31483
  {
31484
    { 0, 0, 0, 0 },
31485
    { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', 'r', '2', 'r', '0', 0 } },
31486
    & ifmt_mulu_l_dst32_24_8_SB_relative_Prefixed_SI, { 0x1839f00 }
31487
  },
31488
/* mul.l ${Dsp-24-u16}[sb],r2r0 */
31489
  {
31490
    { 0, 0, 0, 0 },
31491
    { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', 'r', '2', 'r', '0', 0 } },
31492
    & ifmt_mulu_l_dst32_24_16_SB_relative_Prefixed_SI, { 0x1859f00 }
31493
  },
31494
/* mul.l ${Dsp-24-s8}[fb],r2r0 */
31495
  {
31496
    { 0, 0, 0, 0 },
31497
    { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', 'r', '2', 'r', '0', 0 } },
31498
    & ifmt_mulu_l_dst32_24_8_FB_relative_Prefixed_SI, { 0x183df00 }
31499
  },
31500
/* mul.l ${Dsp-24-s16}[fb],r2r0 */
31501
  {
31502
    { 0, 0, 0, 0 },
31503
    { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', 'r', '2', 'r', '0', 0 } },
31504
    & ifmt_mulu_l_dst32_24_16_FB_relative_Prefixed_SI, { 0x185df00 }
31505
  },
31506
/* mul.l ${Dsp-24-u16},r2r0 */
31507
  {
31508
    { 0, 0, 0, 0 },
31509
    { { MNEM, ' ', OP (DSP_24_U16), ',', 'r', '2', 'r', '0', 0 } },
31510
    & ifmt_mulu_l_dst32_24_16_absolute_Prefixed_SI, { 0x187df00 }
31511
  },
31512
/* mul.l ${Dsp-24-u24},r2r0 */
31513
  {
31514
    { 0, 0, 0, 0 },
31515
    { { MNEM, ' ', OP (DSP_24_U24), ',', 'r', '2', 'r', '0', 0 } },
31516
    & ifmt_mulu_l_dst32_24_24_absolute_Prefixed_SI, { 0x1879f00 }
31517
  },
31518
/* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
31519
  {
31520
    { 0, 0, 0, 0 },
31521
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
31522
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x990c00 }
31523
  },
31524
/* mul.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */
31525
  {
31526
    { 0, 0, 0, 0 },
31527
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
31528
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x992c00 }
31529
  },
31530
/* mul.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */
31531
  {
31532
    { 0, 0, 0, 0 },
31533
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
31534
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x993c00 }
31535
  },
31536
/* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
31537
  {
31538
    { 0, 0, 0, 0 },
31539
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
31540
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x918c00 }
31541
  },
31542
/* mul.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */
31543
  {
31544
    { 0, 0, 0, 0 },
31545
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
31546
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x91ac00 }
31547
  },
31548
/* mul.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */
31549
  {
31550
    { 0, 0, 0, 0 },
31551
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
31552
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x91bc00 }
31553
  },
31554
/* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
31555
  {
31556
    { 0, 0, 0, 0 },
31557
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31558
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x910c00 }
31559
  },
31560
/* mul.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
31561
  {
31562
    { 0, 0, 0, 0 },
31563
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31564
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x912c00 }
31565
  },
31566
/* mul.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
31567
  {
31568
    { 0, 0, 0, 0 },
31569
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31570
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x913c00 }
31571
  },
31572
/* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
31573
  {
31574
    { 0, 0, 0, 0 },
31575
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31576
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x930c0000 }
31577
  },
31578
/* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
31579
  {
31580
    { 0, 0, 0, 0 },
31581
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31582
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x932c0000 }
31583
  },
31584
/* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
31585
  {
31586
    { 0, 0, 0, 0 },
31587
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31588
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x933c0000 }
31589
  },
31590
/* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
31591
  {
31592
    { 0, 0, 0, 0 },
31593
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31594
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x950c0000 }
31595
  },
31596
/* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
31597
  {
31598
    { 0, 0, 0, 0 },
31599
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31600
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x952c0000 }
31601
  },
31602
/* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
31603
  {
31604
    { 0, 0, 0, 0 },
31605
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31606
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x953c0000 }
31607
  },
31608
/* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
31609
  {
31610
    { 0, 0, 0, 0 },
31611
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31612
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x970c0000 }
31613
  },
31614
/* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
31615
  {
31616
    { 0, 0, 0, 0 },
31617
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31618
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x972c0000 }
31619
  },
31620
/* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
31621
  {
31622
    { 0, 0, 0, 0 },
31623
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31624
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x973c0000 }
31625
  },
31626
/* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
31627
  {
31628
    { 0, 0, 0, 0 },
31629
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
31630
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x938c0000 }
31631
  },
31632
/* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
31633
  {
31634
    { 0, 0, 0, 0 },
31635
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
31636
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93ac0000 }
31637
  },
31638
/* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
31639
  {
31640
    { 0, 0, 0, 0 },
31641
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
31642
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93bc0000 }
31643
  },
31644
/* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
31645
  {
31646
    { 0, 0, 0, 0 },
31647
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
31648
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x958c0000 }
31649
  },
31650
/* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
31651
  {
31652
    { 0, 0, 0, 0 },
31653
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
31654
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95ac0000 }
31655
  },
31656
/* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
31657
  {
31658
    { 0, 0, 0, 0 },
31659
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
31660
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95bc0000 }
31661
  },
31662
/* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
31663
  {
31664
    { 0, 0, 0, 0 },
31665
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
31666
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93cc0000 }
31667
  },
31668
/* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
31669
  {
31670
    { 0, 0, 0, 0 },
31671
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
31672
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93ec0000 }
31673
  },
31674
/* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
31675
  {
31676
    { 0, 0, 0, 0 },
31677
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
31678
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93fc0000 }
31679
  },
31680
/* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
31681
  {
31682
    { 0, 0, 0, 0 },
31683
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
31684
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95cc0000 }
31685
  },
31686
/* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
31687
  {
31688
    { 0, 0, 0, 0 },
31689
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
31690
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95ec0000 }
31691
  },
31692
/* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
31693
  {
31694
    { 0, 0, 0, 0 },
31695
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
31696
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95fc0000 }
31697
  },
31698
/* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
31699
  {
31700
    { 0, 0, 0, 0 },
31701
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
31702
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97cc0000 }
31703
  },
31704
/* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
31705
  {
31706
    { 0, 0, 0, 0 },
31707
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
31708
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97ec0000 }
31709
  },
31710
/* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
31711
  {
31712
    { 0, 0, 0, 0 },
31713
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
31714
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97fc0000 }
31715
  },
31716
/* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
31717
  {
31718
    { 0, 0, 0, 0 },
31719
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
31720
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x978c0000 }
31721
  },
31722
/* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
31723
  {
31724
    { 0, 0, 0, 0 },
31725
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } },
31726
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97ac0000 }
31727
  },
31728
/* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
31729
  {
31730
    { 0, 0, 0, 0 },
31731
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } },
31732
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97bc0000 }
31733
  },
31734
/* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
31735
  {
31736
    { 0, 0, 0, 0 },
31737
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
31738
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa90c0000 }
31739
  },
31740
/* mul.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */
31741
  {
31742
    { 0, 0, 0, 0 },
31743
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
31744
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa92c0000 }
31745
  },
31746
/* mul.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */
31747
  {
31748
    { 0, 0, 0, 0 },
31749
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
31750
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa93c0000 }
31751
  },
31752
/* mul.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */
31753
  {
31754
    { 0, 0, 0, 0 },
31755
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
31756
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb93c0000 }
31757
  },
31758
/* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
31759
  {
31760
    { 0, 0, 0, 0 },
31761
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
31762
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa18c0000 }
31763
  },
31764
/* mul.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */
31765
  {
31766
    { 0, 0, 0, 0 },
31767
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
31768
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1ac0000 }
31769
  },
31770
/* mul.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */
31771
  {
31772
    { 0, 0, 0, 0 },
31773
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
31774
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1bc0000 }
31775
  },
31776
/* mul.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */
31777
  {
31778
    { 0, 0, 0, 0 },
31779
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
31780
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1bc0000 }
31781
  },
31782
/* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
31783
  {
31784
    { 0, 0, 0, 0 },
31785
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31786
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa10c0000 }
31787
  },
31788
/* mul.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
31789
  {
31790
    { 0, 0, 0, 0 },
31791
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31792
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa12c0000 }
31793
  },
31794
/* mul.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
31795
  {
31796
    { 0, 0, 0, 0 },
31797
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31798
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa13c0000 }
31799
  },
31800
/* mul.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
31801
  {
31802
    { 0, 0, 0, 0 },
31803
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31804
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb13c0000 }
31805
  },
31806
/* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
31807
  {
31808
    { 0, 0, 0, 0 },
31809
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31810
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa30c0000 }
31811
  },
31812
/* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
31813
  {
31814
    { 0, 0, 0, 0 },
31815
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31816
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa32c0000 }
31817
  },
31818
/* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
31819
  {
31820
    { 0, 0, 0, 0 },
31821
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31822
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa33c0000 }
31823
  },
31824
/* mul.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
31825
  {
31826
    { 0, 0, 0, 0 },
31827
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31828
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xb33c0000 }
31829
  },
31830
/* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
31831
  {
31832
    { 0, 0, 0, 0 },
31833
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31834
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa50c0000 }
31835
  },
31836
/* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
31837
  {
31838
    { 0, 0, 0, 0 },
31839
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31840
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa52c0000 }
31841
  },
31842
/* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
31843
  {
31844
    { 0, 0, 0, 0 },
31845
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31846
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa53c0000 }
31847
  },
31848
/* mul.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
31849
  {
31850
    { 0, 0, 0, 0 },
31851
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31852
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xb53c0000 }
31853
  },
31854
/* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
31855
  {
31856
    { 0, 0, 0, 0 },
31857
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31858
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa70c0000 }
31859
  },
31860
/* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
31861
  {
31862
    { 0, 0, 0, 0 },
31863
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31864
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa72c0000 }
31865
  },
31866
/* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
31867
  {
31868
    { 0, 0, 0, 0 },
31869
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31870
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa73c0000 }
31871
  },
31872
/* mul.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
31873
  {
31874
    { 0, 0, 0, 0 },
31875
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
31876
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xb73c0000 }
31877
  },
31878
/* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
31879
  {
31880
    { 0, 0, 0, 0 },
31881
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
31882
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa38c0000 }
31883
  },
31884
/* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
31885
  {
31886
    { 0, 0, 0, 0 },
31887
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
31888
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3ac0000 }
31889
  },
31890
/* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
31891
  {
31892
    { 0, 0, 0, 0 },
31893
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
31894
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3bc0000 }
31895
  },
31896
/* mul.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
31897
  {
31898
    { 0, 0, 0, 0 },
31899
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
31900
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xb3bc0000 }
31901
  },
31902
/* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
31903
  {
31904
    { 0, 0, 0, 0 },
31905
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
31906
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa58c0000 }
31907
  },
31908
/* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
31909
  {
31910
    { 0, 0, 0, 0 },
31911
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
31912
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5ac0000 }
31913
  },
31914
/* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
31915
  {
31916
    { 0, 0, 0, 0 },
31917
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
31918
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5bc0000 }
31919
  },
31920
/* mul.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
31921
  {
31922
    { 0, 0, 0, 0 },
31923
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
31924
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xb5bc0000 }
31925
  },
31926
/* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
31927
  {
31928
    { 0, 0, 0, 0 },
31929
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
31930
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3cc0000 }
31931
  },
31932
/* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
31933
  {
31934
    { 0, 0, 0, 0 },
31935
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
31936
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3ec0000 }
31937
  },
31938
/* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
31939
  {
31940
    { 0, 0, 0, 0 },
31941
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
31942
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3fc0000 }
31943
  },
31944
/* mul.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
31945
  {
31946
    { 0, 0, 0, 0 },
31947
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
31948
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xb3fc0000 }
31949
  },
31950
/* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
31951
  {
31952
    { 0, 0, 0, 0 },
31953
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
31954
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5cc0000 }
31955
  },
31956
/* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
31957
  {
31958
    { 0, 0, 0, 0 },
31959
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
31960
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5ec0000 }
31961
  },
31962
/* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
31963
  {
31964
    { 0, 0, 0, 0 },
31965
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
31966
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5fc0000 }
31967
  },
31968
/* mul.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
31969
  {
31970
    { 0, 0, 0, 0 },
31971
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
31972
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xb5fc0000 }
31973
  },
31974
/* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
31975
  {
31976
    { 0, 0, 0, 0 },
31977
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
31978
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7cc0000 }
31979
  },
31980
/* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
31981
  {
31982
    { 0, 0, 0, 0 },
31983
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
31984
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7ec0000 }
31985
  },
31986
/* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
31987
  {
31988
    { 0, 0, 0, 0 },
31989
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
31990
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7fc0000 }
31991
  },
31992
/* mul.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
31993
  {
31994
    { 0, 0, 0, 0 },
31995
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
31996
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xb7fc0000 }
31997
  },
31998
/* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
31999
  {
32000
    { 0, 0, 0, 0 },
32001
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
32002
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa78c0000 }
32003
  },
32004
/* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
32005
  {
32006
    { 0, 0, 0, 0 },
32007
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
32008
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7ac0000 }
32009
  },
32010
/* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
32011
  {
32012
    { 0, 0, 0, 0 },
32013
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
32014
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7bc0000 }
32015
  },
32016
/* mul.w${G} ${Dsp-16-u16},${Dsp-32-u24} */
32017
  {
32018
    { 0, 0, 0, 0 },
32019
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } },
32020
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xb7bc0000 }
32021
  },
32022
/* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
32023
  {
32024
    { 0, 0, 0, 0 },
32025
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
32026
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb90c0000 }
32027
  },
32028
/* mul.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */
32029
  {
32030
    { 0, 0, 0, 0 },
32031
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
32032
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb92c0000 }
32033
  },
32034
/* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
32035
  {
32036
    { 0, 0, 0, 0 },
32037
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
32038
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb18c0000 }
32039
  },
32040
/* mul.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */
32041
  {
32042
    { 0, 0, 0, 0 },
32043
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
32044
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1ac0000 }
32045
  },
32046
/* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
32047
  {
32048
    { 0, 0, 0, 0 },
32049
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32050
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb10c0000 }
32051
  },
32052
/* mul.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
32053
  {
32054
    { 0, 0, 0, 0 },
32055
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32056
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb12c0000 }
32057
  },
32058
/* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
32059
  {
32060
    { 0, 0, 0, 0 },
32061
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32062
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_An_relative_Unprefixed_HI, { 0xb30c0000 }
32063
  },
32064
/* mul.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
32065
  {
32066
    { 0, 0, 0, 0 },
32067
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32068
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_An_relative_Unprefixed_HI, { 0xb32c0000 }
32069
  },
32070
/* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
32071
  {
32072
    { 0, 0, 0, 0 },
32073
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32074
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_An_relative_Unprefixed_HI, { 0xb50c0000 }
32075
  },
32076
/* mul.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
32077
  {
32078
    { 0, 0, 0, 0 },
32079
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32080
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_An_relative_Unprefixed_HI, { 0xb52c0000 }
32081
  },
32082
/* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
32083
  {
32084
    { 0, 0, 0, 0 },
32085
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32086
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_24_An_relative_Unprefixed_HI, { 0xb70c0000 }
32087
  },
32088
/* mul.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
32089
  {
32090
    { 0, 0, 0, 0 },
32091
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32092
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_24_An_relative_Unprefixed_HI, { 0xb72c0000 }
32093
  },
32094
/* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
32095
  {
32096
    { 0, 0, 0, 0 },
32097
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
32098
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_SB_relative_Unprefixed_HI, { 0xb38c0000 }
32099
  },
32100
/* mul.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
32101
  {
32102
    { 0, 0, 0, 0 },
32103
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
32104
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_SB_relative_Unprefixed_HI, { 0xb3ac0000 }
32105
  },
32106
/* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
32107
  {
32108
    { 0, 0, 0, 0 },
32109
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
32110
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_SB_relative_Unprefixed_HI, { 0xb58c0000 }
32111
  },
32112
/* mul.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
32113
  {
32114
    { 0, 0, 0, 0 },
32115
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
32116
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_SB_relative_Unprefixed_HI, { 0xb5ac0000 }
32117
  },
32118
/* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
32119
  {
32120
    { 0, 0, 0, 0 },
32121
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
32122
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_FB_relative_Unprefixed_HI, { 0xb3cc0000 }
32123
  },
32124
/* mul.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
32125
  {
32126
    { 0, 0, 0, 0 },
32127
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
32128
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_FB_relative_Unprefixed_HI, { 0xb3ec0000 }
32129
  },
32130
/* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
32131
  {
32132
    { 0, 0, 0, 0 },
32133
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
32134
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_FB_relative_Unprefixed_HI, { 0xb5cc0000 }
32135
  },
32136
/* mul.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
32137
  {
32138
    { 0, 0, 0, 0 },
32139
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
32140
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_FB_relative_Unprefixed_HI, { 0xb5ec0000 }
32141
  },
32142
/* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
32143
  {
32144
    { 0, 0, 0, 0 },
32145
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
32146
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_absolute_Unprefixed_HI, { 0xb7cc0000 }
32147
  },
32148
/* mul.w${G} ${Dsp-16-u24},${Dsp-40-u16} */
32149
  {
32150
    { 0, 0, 0, 0 },
32151
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } },
32152
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_absolute_Unprefixed_HI, { 0xb7ec0000 }
32153
  },
32154
/* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
32155
  {
32156
    { 0, 0, 0, 0 },
32157
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
32158
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_24_absolute_Unprefixed_HI, { 0xb78c0000 }
32159
  },
32160
/* mul.w${G} ${Dsp-16-u24},${Dsp-40-u24} */
32161
  {
32162
    { 0, 0, 0, 0 },
32163
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } },
32164
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_24_absolute_Unprefixed_HI, { 0xb7ac0000 }
32165
  },
32166
/* mul.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */
32167
  {
32168
    { 0, 0, 0, 0 },
32169
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
32170
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xc90c }
32171
  },
32172
/* mul.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */
32173
  {
32174
    { 0, 0, 0, 0 },
32175
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
32176
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x892c }
32177
  },
32178
/* mul.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
32179
  {
32180
    { 0, 0, 0, 0 },
32181
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
32182
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x890c }
32183
  },
32184
/* mul.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */
32185
  {
32186
    { 0, 0, 0, 0 },
32187
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
32188
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xc18c }
32189
  },
32190
/* mul.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */
32191
  {
32192
    { 0, 0, 0, 0 },
32193
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
32194
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x81ac }
32195
  },
32196
/* mul.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
32197
  {
32198
    { 0, 0, 0, 0 },
32199
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
32200
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x818c }
32201
  },
32202
/* mul.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */
32203
  {
32204
    { 0, 0, 0, 0 },
32205
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32206
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xc10c }
32207
  },
32208
/* mul.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */
32209
  {
32210
    { 0, 0, 0, 0 },
32211
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32212
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x812c }
32213
  },
32214
/* mul.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
32215
  {
32216
    { 0, 0, 0, 0 },
32217
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32218
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x810c }
32219
  },
32220
/* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
32221
  {
32222
    { 0, 0, 0, 0 },
32223
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32224
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0xc30c00 }
32225
  },
32226
/* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
32227
  {
32228
    { 0, 0, 0, 0 },
32229
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32230
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0x832c00 }
32231
  },
32232
/* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
32233
  {
32234
    { 0, 0, 0, 0 },
32235
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32236
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0x830c00 }
32237
  },
32238
/* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
32239
  {
32240
    { 0, 0, 0, 0 },
32241
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32242
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0xc50c0000 }
32243
  },
32244
/* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
32245
  {
32246
    { 0, 0, 0, 0 },
32247
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32248
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0x852c0000 }
32249
  },
32250
/* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
32251
  {
32252
    { 0, 0, 0, 0 },
32253
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32254
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0x850c0000 }
32255
  },
32256
/* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
32257
  {
32258
    { 0, 0, 0, 0 },
32259
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32260
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0xc70c0000 }
32261
  },
32262
/* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
32263
  {
32264
    { 0, 0, 0, 0 },
32265
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32266
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0x872c0000 }
32267
  },
32268
/* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
32269
  {
32270
    { 0, 0, 0, 0 },
32271
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32272
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0x870c0000 }
32273
  },
32274
/* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */
32275
  {
32276
    { 0, 0, 0, 0 },
32277
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
32278
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0xc38c00 }
32279
  },
32280
/* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */
32281
  {
32282
    { 0, 0, 0, 0 },
32283
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
32284
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0x83ac00 }
32285
  },
32286
/* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
32287
  {
32288
    { 0, 0, 0, 0 },
32289
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
32290
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0x838c00 }
32291
  },
32292
/* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */
32293
  {
32294
    { 0, 0, 0, 0 },
32295
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
32296
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0xc58c0000 }
32297
  },
32298
/* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */
32299
  {
32300
    { 0, 0, 0, 0 },
32301
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
32302
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0x85ac0000 }
32303
  },
32304
/* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
32305
  {
32306
    { 0, 0, 0, 0 },
32307
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
32308
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0x858c0000 }
32309
  },
32310
/* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */
32311
  {
32312
    { 0, 0, 0, 0 },
32313
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
32314
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0xc3cc00 }
32315
  },
32316
/* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */
32317
  {
32318
    { 0, 0, 0, 0 },
32319
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
32320
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83ec00 }
32321
  },
32322
/* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
32323
  {
32324
    { 0, 0, 0, 0 },
32325
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
32326
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83cc00 }
32327
  },
32328
/* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */
32329
  {
32330
    { 0, 0, 0, 0 },
32331
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
32332
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0xc5cc0000 }
32333
  },
32334
/* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */
32335
  {
32336
    { 0, 0, 0, 0 },
32337
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
32338
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85ec0000 }
32339
  },
32340
/* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
32341
  {
32342
    { 0, 0, 0, 0 },
32343
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
32344
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85cc0000 }
32345
  },
32346
/* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */
32347
  {
32348
    { 0, 0, 0, 0 },
32349
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), 0 } },
32350
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0xc7cc0000 }
32351
  },
32352
/* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */
32353
  {
32354
    { 0, 0, 0, 0 },
32355
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), 0 } },
32356
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0x87ec0000 }
32357
  },
32358
/* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
32359
  {
32360
    { 0, 0, 0, 0 },
32361
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } },
32362
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0x87cc0000 }
32363
  },
32364
/* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */
32365
  {
32366
    { 0, 0, 0, 0 },
32367
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U24), 0 } },
32368
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0xc78c0000 }
32369
  },
32370
/* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */
32371
  {
32372
    { 0, 0, 0, 0 },
32373
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U24), 0 } },
32374
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0x87ac0000 }
32375
  },
32376
/* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
32377
  {
32378
    { 0, 0, 0, 0 },
32379
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } },
32380
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0x878c0000 }
32381
  },
32382
/* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
32383
  {
32384
    { 0, 0, 0, 0 },
32385
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
32386
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x980c00 }
32387
  },
32388
/* mul.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */
32389
  {
32390
    { 0, 0, 0, 0 },
32391
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
32392
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x982c00 }
32393
  },
32394
/* mul.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */
32395
  {
32396
    { 0, 0, 0, 0 },
32397
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
32398
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x983c00 }
32399
  },
32400
/* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
32401
  {
32402
    { 0, 0, 0, 0 },
32403
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
32404
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x908c00 }
32405
  },
32406
/* mul.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */
32407
  {
32408
    { 0, 0, 0, 0 },
32409
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
32410
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x90ac00 }
32411
  },
32412
/* mul.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */
32413
  {
32414
    { 0, 0, 0, 0 },
32415
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
32416
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x90bc00 }
32417
  },
32418
/* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
32419
  {
32420
    { 0, 0, 0, 0 },
32421
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32422
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x900c00 }
32423
  },
32424
/* mul.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
32425
  {
32426
    { 0, 0, 0, 0 },
32427
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32428
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x902c00 }
32429
  },
32430
/* mul.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
32431
  {
32432
    { 0, 0, 0, 0 },
32433
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32434
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x903c00 }
32435
  },
32436
/* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
32437
  {
32438
    { 0, 0, 0, 0 },
32439
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32440
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x920c0000 }
32441
  },
32442
/* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
32443
  {
32444
    { 0, 0, 0, 0 },
32445
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32446
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x922c0000 }
32447
  },
32448
/* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
32449
  {
32450
    { 0, 0, 0, 0 },
32451
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32452
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x923c0000 }
32453
  },
32454
/* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
32455
  {
32456
    { 0, 0, 0, 0 },
32457
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32458
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x940c0000 }
32459
  },
32460
/* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
32461
  {
32462
    { 0, 0, 0, 0 },
32463
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32464
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x942c0000 }
32465
  },
32466
/* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
32467
  {
32468
    { 0, 0, 0, 0 },
32469
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32470
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x943c0000 }
32471
  },
32472
/* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
32473
  {
32474
    { 0, 0, 0, 0 },
32475
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32476
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x960c0000 }
32477
  },
32478
/* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
32479
  {
32480
    { 0, 0, 0, 0 },
32481
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32482
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x962c0000 }
32483
  },
32484
/* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
32485
  {
32486
    { 0, 0, 0, 0 },
32487
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32488
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x963c0000 }
32489
  },
32490
/* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
32491
  {
32492
    { 0, 0, 0, 0 },
32493
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
32494
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x928c0000 }
32495
  },
32496
/* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
32497
  {
32498
    { 0, 0, 0, 0 },
32499
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
32500
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92ac0000 }
32501
  },
32502
/* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
32503
  {
32504
    { 0, 0, 0, 0 },
32505
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
32506
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92bc0000 }
32507
  },
32508
/* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
32509
  {
32510
    { 0, 0, 0, 0 },
32511
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
32512
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x948c0000 }
32513
  },
32514
/* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
32515
  {
32516
    { 0, 0, 0, 0 },
32517
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
32518
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94ac0000 }
32519
  },
32520
/* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
32521
  {
32522
    { 0, 0, 0, 0 },
32523
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
32524
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94bc0000 }
32525
  },
32526
/* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
32527
  {
32528
    { 0, 0, 0, 0 },
32529
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
32530
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92cc0000 }
32531
  },
32532
/* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
32533
  {
32534
    { 0, 0, 0, 0 },
32535
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
32536
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92ec0000 }
32537
  },
32538
/* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
32539
  {
32540
    { 0, 0, 0, 0 },
32541
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
32542
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92fc0000 }
32543
  },
32544
/* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
32545
  {
32546
    { 0, 0, 0, 0 },
32547
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
32548
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94cc0000 }
32549
  },
32550
/* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
32551
  {
32552
    { 0, 0, 0, 0 },
32553
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
32554
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94ec0000 }
32555
  },
32556
/* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
32557
  {
32558
    { 0, 0, 0, 0 },
32559
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
32560
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94fc0000 }
32561
  },
32562
/* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
32563
  {
32564
    { 0, 0, 0, 0 },
32565
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
32566
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96cc0000 }
32567
  },
32568
/* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
32569
  {
32570
    { 0, 0, 0, 0 },
32571
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
32572
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96ec0000 }
32573
  },
32574
/* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
32575
  {
32576
    { 0, 0, 0, 0 },
32577
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
32578
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96fc0000 }
32579
  },
32580
/* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
32581
  {
32582
    { 0, 0, 0, 0 },
32583
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
32584
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x968c0000 }
32585
  },
32586
/* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
32587
  {
32588
    { 0, 0, 0, 0 },
32589
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } },
32590
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96ac0000 }
32591
  },
32592
/* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
32593
  {
32594
    { 0, 0, 0, 0 },
32595
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } },
32596
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96bc0000 }
32597
  },
32598
/* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
32599
  {
32600
    { 0, 0, 0, 0 },
32601
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
32602
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa80c0000 }
32603
  },
32604
/* mul.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */
32605
  {
32606
    { 0, 0, 0, 0 },
32607
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
32608
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa82c0000 }
32609
  },
32610
/* mul.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */
32611
  {
32612
    { 0, 0, 0, 0 },
32613
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
32614
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa83c0000 }
32615
  },
32616
/* mul.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */
32617
  {
32618
    { 0, 0, 0, 0 },
32619
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
32620
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb83c0000 }
32621
  },
32622
/* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
32623
  {
32624
    { 0, 0, 0, 0 },
32625
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
32626
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa08c0000 }
32627
  },
32628
/* mul.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */
32629
  {
32630
    { 0, 0, 0, 0 },
32631
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
32632
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0ac0000 }
32633
  },
32634
/* mul.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */
32635
  {
32636
    { 0, 0, 0, 0 },
32637
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
32638
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0bc0000 }
32639
  },
32640
/* mul.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */
32641
  {
32642
    { 0, 0, 0, 0 },
32643
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
32644
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0bc0000 }
32645
  },
32646
/* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
32647
  {
32648
    { 0, 0, 0, 0 },
32649
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32650
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa00c0000 }
32651
  },
32652
/* mul.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
32653
  {
32654
    { 0, 0, 0, 0 },
32655
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32656
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa02c0000 }
32657
  },
32658
/* mul.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
32659
  {
32660
    { 0, 0, 0, 0 },
32661
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32662
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa03c0000 }
32663
  },
32664
/* mul.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
32665
  {
32666
    { 0, 0, 0, 0 },
32667
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32668
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb03c0000 }
32669
  },
32670
/* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
32671
  {
32672
    { 0, 0, 0, 0 },
32673
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32674
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa20c0000 }
32675
  },
32676
/* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
32677
  {
32678
    { 0, 0, 0, 0 },
32679
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32680
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa22c0000 }
32681
  },
32682
/* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
32683
  {
32684
    { 0, 0, 0, 0 },
32685
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32686
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa23c0000 }
32687
  },
32688
/* mul.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
32689
  {
32690
    { 0, 0, 0, 0 },
32691
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32692
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xb23c0000 }
32693
  },
32694
/* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
32695
  {
32696
    { 0, 0, 0, 0 },
32697
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32698
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa40c0000 }
32699
  },
32700
/* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
32701
  {
32702
    { 0, 0, 0, 0 },
32703
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32704
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa42c0000 }
32705
  },
32706
/* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
32707
  {
32708
    { 0, 0, 0, 0 },
32709
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32710
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa43c0000 }
32711
  },
32712
/* mul.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
32713
  {
32714
    { 0, 0, 0, 0 },
32715
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32716
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xb43c0000 }
32717
  },
32718
/* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
32719
  {
32720
    { 0, 0, 0, 0 },
32721
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32722
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa60c0000 }
32723
  },
32724
/* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
32725
  {
32726
    { 0, 0, 0, 0 },
32727
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32728
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa62c0000 }
32729
  },
32730
/* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
32731
  {
32732
    { 0, 0, 0, 0 },
32733
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32734
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa63c0000 }
32735
  },
32736
/* mul.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
32737
  {
32738
    { 0, 0, 0, 0 },
32739
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32740
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xb63c0000 }
32741
  },
32742
/* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
32743
  {
32744
    { 0, 0, 0, 0 },
32745
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
32746
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa28c0000 }
32747
  },
32748
/* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
32749
  {
32750
    { 0, 0, 0, 0 },
32751
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
32752
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2ac0000 }
32753
  },
32754
/* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
32755
  {
32756
    { 0, 0, 0, 0 },
32757
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
32758
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2bc0000 }
32759
  },
32760
/* mul.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
32761
  {
32762
    { 0, 0, 0, 0 },
32763
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
32764
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xb2bc0000 }
32765
  },
32766
/* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
32767
  {
32768
    { 0, 0, 0, 0 },
32769
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
32770
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa48c0000 }
32771
  },
32772
/* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
32773
  {
32774
    { 0, 0, 0, 0 },
32775
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
32776
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4ac0000 }
32777
  },
32778
/* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
32779
  {
32780
    { 0, 0, 0, 0 },
32781
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
32782
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4bc0000 }
32783
  },
32784
/* mul.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
32785
  {
32786
    { 0, 0, 0, 0 },
32787
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
32788
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xb4bc0000 }
32789
  },
32790
/* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
32791
  {
32792
    { 0, 0, 0, 0 },
32793
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
32794
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2cc0000 }
32795
  },
32796
/* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
32797
  {
32798
    { 0, 0, 0, 0 },
32799
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
32800
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2ec0000 }
32801
  },
32802
/* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
32803
  {
32804
    { 0, 0, 0, 0 },
32805
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
32806
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2fc0000 }
32807
  },
32808
/* mul.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
32809
  {
32810
    { 0, 0, 0, 0 },
32811
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
32812
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xb2fc0000 }
32813
  },
32814
/* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
32815
  {
32816
    { 0, 0, 0, 0 },
32817
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
32818
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4cc0000 }
32819
  },
32820
/* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
32821
  {
32822
    { 0, 0, 0, 0 },
32823
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
32824
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4ec0000 }
32825
  },
32826
/* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
32827
  {
32828
    { 0, 0, 0, 0 },
32829
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
32830
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4fc0000 }
32831
  },
32832
/* mul.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
32833
  {
32834
    { 0, 0, 0, 0 },
32835
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
32836
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xb4fc0000 }
32837
  },
32838
/* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
32839
  {
32840
    { 0, 0, 0, 0 },
32841
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
32842
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6cc0000 }
32843
  },
32844
/* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
32845
  {
32846
    { 0, 0, 0, 0 },
32847
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
32848
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6ec0000 }
32849
  },
32850
/* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
32851
  {
32852
    { 0, 0, 0, 0 },
32853
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
32854
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6fc0000 }
32855
  },
32856
/* mul.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
32857
  {
32858
    { 0, 0, 0, 0 },
32859
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
32860
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xb6fc0000 }
32861
  },
32862
/* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
32863
  {
32864
    { 0, 0, 0, 0 },
32865
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
32866
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa68c0000 }
32867
  },
32868
/* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
32869
  {
32870
    { 0, 0, 0, 0 },
32871
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
32872
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6ac0000 }
32873
  },
32874
/* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
32875
  {
32876
    { 0, 0, 0, 0 },
32877
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
32878
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6bc0000 }
32879
  },
32880
/* mul.b${G} ${Dsp-16-u16},${Dsp-32-u24} */
32881
  {
32882
    { 0, 0, 0, 0 },
32883
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } },
32884
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xb6bc0000 }
32885
  },
32886
/* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
32887
  {
32888
    { 0, 0, 0, 0 },
32889
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
32890
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb80c0000 }
32891
  },
32892
/* mul.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */
32893
  {
32894
    { 0, 0, 0, 0 },
32895
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
32896
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb82c0000 }
32897
  },
32898
/* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
32899
  {
32900
    { 0, 0, 0, 0 },
32901
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
32902
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb08c0000 }
32903
  },
32904
/* mul.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */
32905
  {
32906
    { 0, 0, 0, 0 },
32907
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
32908
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0ac0000 }
32909
  },
32910
/* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
32911
  {
32912
    { 0, 0, 0, 0 },
32913
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32914
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb00c0000 }
32915
  },
32916
/* mul.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
32917
  {
32918
    { 0, 0, 0, 0 },
32919
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32920
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb02c0000 }
32921
  },
32922
/* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
32923
  {
32924
    { 0, 0, 0, 0 },
32925
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32926
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_QI, { 0xb20c0000 }
32927
  },
32928
/* mul.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
32929
  {
32930
    { 0, 0, 0, 0 },
32931
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32932
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_QI, { 0xb22c0000 }
32933
  },
32934
/* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
32935
  {
32936
    { 0, 0, 0, 0 },
32937
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32938
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_QI, { 0xb40c0000 }
32939
  },
32940
/* mul.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
32941
  {
32942
    { 0, 0, 0, 0 },
32943
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32944
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_QI, { 0xb42c0000 }
32945
  },
32946
/* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
32947
  {
32948
    { 0, 0, 0, 0 },
32949
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32950
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_QI, { 0xb60c0000 }
32951
  },
32952
/* mul.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
32953
  {
32954
    { 0, 0, 0, 0 },
32955
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
32956
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_QI, { 0xb62c0000 }
32957
  },
32958
/* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
32959
  {
32960
    { 0, 0, 0, 0 },
32961
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
32962
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_QI, { 0xb28c0000 }
32963
  },
32964
/* mul.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
32965
  {
32966
    { 0, 0, 0, 0 },
32967
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
32968
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_QI, { 0xb2ac0000 }
32969
  },
32970
/* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
32971
  {
32972
    { 0, 0, 0, 0 },
32973
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
32974
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_QI, { 0xb48c0000 }
32975
  },
32976
/* mul.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
32977
  {
32978
    { 0, 0, 0, 0 },
32979
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
32980
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_QI, { 0xb4ac0000 }
32981
  },
32982
/* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
32983
  {
32984
    { 0, 0, 0, 0 },
32985
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
32986
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_QI, { 0xb2cc0000 }
32987
  },
32988
/* mul.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
32989
  {
32990
    { 0, 0, 0, 0 },
32991
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
32992
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_QI, { 0xb2ec0000 }
32993
  },
32994
/* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
32995
  {
32996
    { 0, 0, 0, 0 },
32997
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
32998
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_QI, { 0xb4cc0000 }
32999
  },
33000
/* mul.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
33001
  {
33002
    { 0, 0, 0, 0 },
33003
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
33004
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_QI, { 0xb4ec0000 }
33005
  },
33006
/* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
33007
  {
33008
    { 0, 0, 0, 0 },
33009
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
33010
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_QI, { 0xb6cc0000 }
33011
  },
33012
/* mul.b${G} ${Dsp-16-u24},${Dsp-40-u16} */
33013
  {
33014
    { 0, 0, 0, 0 },
33015
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } },
33016
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_QI, { 0xb6ec0000 }
33017
  },
33018
/* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
33019
  {
33020
    { 0, 0, 0, 0 },
33021
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
33022
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_QI, { 0xb68c0000 }
33023
  },
33024
/* mul.b${G} ${Dsp-16-u24},${Dsp-40-u24} */
33025
  {
33026
    { 0, 0, 0, 0 },
33027
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } },
33028
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_QI, { 0xb6ac0000 }
33029
  },
33030
/* mul.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */
33031
  {
33032
    { 0, 0, 0, 0 },
33033
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
33034
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xc80c }
33035
  },
33036
/* mul.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */
33037
  {
33038
    { 0, 0, 0, 0 },
33039
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
33040
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x882c }
33041
  },
33042
/* mul.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
33043
  {
33044
    { 0, 0, 0, 0 },
33045
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
33046
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x880c }
33047
  },
33048
/* mul.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */
33049
  {
33050
    { 0, 0, 0, 0 },
33051
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
33052
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xc08c }
33053
  },
33054
/* mul.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */
33055
  {
33056
    { 0, 0, 0, 0 },
33057
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
33058
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x80ac }
33059
  },
33060
/* mul.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
33061
  {
33062
    { 0, 0, 0, 0 },
33063
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
33064
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x808c }
33065
  },
33066
/* mul.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */
33067
  {
33068
    { 0, 0, 0, 0 },
33069
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
33070
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xc00c }
33071
  },
33072
/* mul.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */
33073
  {
33074
    { 0, 0, 0, 0 },
33075
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
33076
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x802c }
33077
  },
33078
/* mul.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
33079
  {
33080
    { 0, 0, 0, 0 },
33081
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
33082
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x800c }
33083
  },
33084
/* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
33085
  {
33086
    { 0, 0, 0, 0 },
33087
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
33088
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0xc20c00 }
33089
  },
33090
/* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
33091
  {
33092
    { 0, 0, 0, 0 },
33093
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
33094
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0x822c00 }
33095
  },
33096
/* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
33097
  {
33098
    { 0, 0, 0, 0 },
33099
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
33100
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0x820c00 }
33101
  },
33102
/* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
33103
  {
33104
    { 0, 0, 0, 0 },
33105
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
33106
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0xc40c0000 }
33107
  },
33108
/* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
33109
  {
33110
    { 0, 0, 0, 0 },
33111
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
33112
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0x842c0000 }
33113
  },
33114
/* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
33115
  {
33116
    { 0, 0, 0, 0 },
33117
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
33118
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0x840c0000 }
33119
  },
33120
/* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
33121
  {
33122
    { 0, 0, 0, 0 },
33123
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
33124
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0xc60c0000 }
33125
  },
33126
/* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
33127
  {
33128
    { 0, 0, 0, 0 },
33129
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
33130
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0x862c0000 }
33131
  },
33132
/* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
33133
  {
33134
    { 0, 0, 0, 0 },
33135
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
33136
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0x860c0000 }
33137
  },
33138
/* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */
33139
  {
33140
    { 0, 0, 0, 0 },
33141
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
33142
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0xc28c00 }
33143
  },
33144
/* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */
33145
  {
33146
    { 0, 0, 0, 0 },
33147
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
33148
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0x82ac00 }
33149
  },
33150
/* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
33151
  {
33152
    { 0, 0, 0, 0 },
33153
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
33154
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0x828c00 }
33155
  },
33156
/* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */
33157
  {
33158
    { 0, 0, 0, 0 },
33159
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
33160
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0xc48c0000 }
33161
  },
33162
/* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */
33163
  {
33164
    { 0, 0, 0, 0 },
33165
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
33166
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0x84ac0000 }
33167
  },
33168
/* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
33169
  {
33170
    { 0, 0, 0, 0 },
33171
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
33172
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0x848c0000 }
33173
  },
33174
/* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */
33175
  {
33176
    { 0, 0, 0, 0 },
33177
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
33178
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0xc2cc00 }
33179
  },
33180
/* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */
33181
  {
33182
    { 0, 0, 0, 0 },
33183
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
33184
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82ec00 }
33185
  },
33186
/* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
33187
  {
33188
    { 0, 0, 0, 0 },
33189
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
33190
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82cc00 }
33191
  },
33192
/* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */
33193
  {
33194
    { 0, 0, 0, 0 },
33195
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
33196
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0xc4cc0000 }
33197
  },
33198
/* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */
33199
  {
33200
    { 0, 0, 0, 0 },
33201
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
33202
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84ec0000 }
33203
  },
33204
/* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
33205
  {
33206
    { 0, 0, 0, 0 },
33207
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
33208
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84cc0000 }
33209
  },
33210
/* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */
33211
  {
33212
    { 0, 0, 0, 0 },
33213
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), 0 } },
33214
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0xc6cc0000 }
33215
  },
33216
/* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */
33217
  {
33218
    { 0, 0, 0, 0 },
33219
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), 0 } },
33220
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0x86ec0000 }
33221
  },
33222
/* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
33223
  {
33224
    { 0, 0, 0, 0 },
33225
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } },
33226
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0x86cc0000 }
33227
  },
33228
/* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */
33229
  {
33230
    { 0, 0, 0, 0 },
33231
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U24), 0 } },
33232
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0xc68c0000 }
33233
  },
33234
/* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */
33235
  {
33236
    { 0, 0, 0, 0 },
33237
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U24), 0 } },
33238
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0x86ac0000 }
33239
  },
33240
/* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
33241
  {
33242
    { 0, 0, 0, 0 },
33243
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } },
33244
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0x868c0000 }
33245
  },
33246
/* mul.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
33247
  {
33248
    { 0, 0, 0, 0 },
33249
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } },
33250
    & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_Rn_direct_HI, { 0x798000 }
33251
  },
33252
/* mul.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */
33253
  {
33254
    { 0, 0, 0, 0 },
33255
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } },
33256
    & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_Rn_direct_HI, { 0x79a000 }
33257
  },
33258
/* mul.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */
33259
  {
33260
    { 0, 0, 0, 0 },
33261
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNHI), 0 } },
33262
    & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_Rn_direct_HI, { 0x79b000 }
33263
  },
33264
/* mul.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
33265
  {
33266
    { 0, 0, 0, 0 },
33267
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } },
33268
    & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_direct_HI, { 0x798400 }
33269
  },
33270
/* mul.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */
33271
  {
33272
    { 0, 0, 0, 0 },
33273
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } },
33274
    & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_direct_HI, { 0x79a400 }
33275
  },
33276
/* mul.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */
33277
  {
33278
    { 0, 0, 0, 0 },
33279
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANHI), 0 } },
33280
    & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_direct_HI, { 0x79b400 }
33281
  },
33282
/* mul.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
33283
  {
33284
    { 0, 0, 0, 0 },
33285
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
33286
    & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_indirect_HI, { 0x798600 }
33287
  },
33288
/* mul.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */
33289
  {
33290
    { 0, 0, 0, 0 },
33291
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
33292
    & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_indirect_HI, { 0x79a600 }
33293
  },
33294
/* mul.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */
33295
  {
33296
    { 0, 0, 0, 0 },
33297
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
33298
    & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_indirect_HI, { 0x79b600 }
33299
  },
33300
/* mul.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
33301
  {
33302
    { 0, 0, 0, 0 },
33303
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
33304
    & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_An_relative_HI, { 0x79880000 }
33305
  },
33306
/* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
33307
  {
33308
    { 0, 0, 0, 0 },
33309
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
33310
    & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_An_relative_HI, { 0x79a80000 }
33311
  },
33312
/* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
33313
  {
33314
    { 0, 0, 0, 0 },
33315
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
33316
    & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_An_relative_HI, { 0x79b80000 }
33317
  },
33318
/* mul.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
33319
  {
33320
    { 0, 0, 0, 0 },
33321
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
33322
    & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_An_relative_HI, { 0x798c0000 }
33323
  },
33324
/* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
33325
  {
33326
    { 0, 0, 0, 0 },
33327
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
33328
    & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_An_relative_HI, { 0x79ac0000 }
33329
  },
33330
/* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
33331
  {
33332
    { 0, 0, 0, 0 },
33333
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
33334
    & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_An_relative_HI, { 0x79bc0000 }
33335
  },
33336
/* mul.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
33337
  {
33338
    { 0, 0, 0, 0 },
33339
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
33340
    & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_SB_relative_HI, { 0x798a0000 }
33341
  },
33342
/* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
33343
  {
33344
    { 0, 0, 0, 0 },
33345
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
33346
    & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_SB_relative_HI, { 0x79aa0000 }
33347
  },
33348
/* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
33349
  {
33350
    { 0, 0, 0, 0 },
33351
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
33352
    & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_SB_relative_HI, { 0x79ba0000 }
33353
  },
33354
/* mul.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
33355
  {
33356
    { 0, 0, 0, 0 },
33357
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
33358
    & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_SB_relative_HI, { 0x798e0000 }
33359
  },
33360
/* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
33361
  {
33362
    { 0, 0, 0, 0 },
33363
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
33364
    & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_SB_relative_HI, { 0x79ae0000 }
33365
  },
33366
/* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
33367
  {
33368
    { 0, 0, 0, 0 },
33369
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
33370
    & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_SB_relative_HI, { 0x79be0000 }
33371
  },
33372
/* mul.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
33373
  {
33374
    { 0, 0, 0, 0 },
33375
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
33376
    & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_FB_relative_HI, { 0x798b0000 }
33377
  },
33378
/* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
33379
  {
33380
    { 0, 0, 0, 0 },
33381
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
33382
    & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_FB_relative_HI, { 0x79ab0000 }
33383
  },
33384
/* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
33385
  {
33386
    { 0, 0, 0, 0 },
33387
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
33388
    & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_FB_relative_HI, { 0x79bb0000 }
33389
  },
33390
/* mul.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
33391
  {
33392
    { 0, 0, 0, 0 },
33393
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } },
33394
    & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_absolute_HI, { 0x798f0000 }
33395
  },
33396
/* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
33397
  {
33398
    { 0, 0, 0, 0 },
33399
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
33400
    & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_absolute_HI, { 0x79af0000 }
33401
  },
33402
/* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
33403
  {
33404
    { 0, 0, 0, 0 },
33405
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
33406
    & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_absolute_HI, { 0x79bf0000 }
33407
  },
33408
/* mul.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
33409
  {
33410
    { 0, 0, 0, 0 },
33411
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } },
33412
    & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_Rn_direct_HI, { 0x79c00000 }
33413
  },
33414
/* mul.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */
33415
  {
33416
    { 0, 0, 0, 0 },
33417
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } },
33418
    & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_Rn_direct_HI, { 0x79e00000 }
33419
  },
33420
/* mul.w${G} ${Dsp-16-u16},$Dst16RnHI */
33421
  {
33422
    { 0, 0, 0, 0 },
33423
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16RNHI), 0 } },
33424
    & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_Rn_direct_HI, { 0x79f00000 }
33425
  },
33426
/* mul.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
33427
  {
33428
    { 0, 0, 0, 0 },
33429
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } },
33430
    & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_direct_HI, { 0x79c40000 }
33431
  },
33432
/* mul.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */
33433
  {
33434
    { 0, 0, 0, 0 },
33435
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } },
33436
    & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_direct_HI, { 0x79e40000 }
33437
  },
33438
/* mul.w${G} ${Dsp-16-u16},$Dst16AnHI */
33439
  {
33440
    { 0, 0, 0, 0 },
33441
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16ANHI), 0 } },
33442
    & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_direct_HI, { 0x79f40000 }
33443
  },
33444
/* mul.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
33445
  {
33446
    { 0, 0, 0, 0 },
33447
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
33448
    & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_indirect_HI, { 0x79c60000 }
33449
  },
33450
/* mul.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */
33451
  {
33452
    { 0, 0, 0, 0 },
33453
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
33454
    & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_indirect_HI, { 0x79e60000 }
33455
  },
33456
/* mul.w${G} ${Dsp-16-u16},[$Dst16An] */
33457
  {
33458
    { 0, 0, 0, 0 },
33459
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } },
33460
    & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_indirect_HI, { 0x79f60000 }
33461
  },
33462
/* mul.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
33463
  {
33464
    { 0, 0, 0, 0 },
33465
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
33466
    & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_An_relative_HI, { 0x79c80000 }
33467
  },
33468
/* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
33469
  {
33470
    { 0, 0, 0, 0 },
33471
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
33472
    & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_An_relative_HI, { 0x79e80000 }
33473
  },
33474
/* mul.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
33475
  {
33476
    { 0, 0, 0, 0 },
33477
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
33478
    & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_An_relative_HI, { 0x79f80000 }
33479
  },
33480
/* mul.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
33481
  {
33482
    { 0, 0, 0, 0 },
33483
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
33484
    & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_An_relative_HI, { 0x79cc0000 }
33485
  },
33486
/* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
33487
  {
33488
    { 0, 0, 0, 0 },
33489
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
33490
    & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_An_relative_HI, { 0x79ec0000 }
33491
  },
33492
/* mul.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
33493
  {
33494
    { 0, 0, 0, 0 },
33495
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
33496
    & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_An_relative_HI, { 0x79fc0000 }
33497
  },
33498
/* mul.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
33499
  {
33500
    { 0, 0, 0, 0 },
33501
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
33502
    & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_SB_relative_HI, { 0x79ca0000 }
33503
  },
33504
/* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
33505
  {
33506
    { 0, 0, 0, 0 },
33507
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
33508
    & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_SB_relative_HI, { 0x79ea0000 }
33509
  },
33510
/* mul.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
33511
  {
33512
    { 0, 0, 0, 0 },
33513
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
33514
    & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_SB_relative_HI, { 0x79fa0000 }
33515
  },
33516
/* mul.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
33517
  {
33518
    { 0, 0, 0, 0 },
33519
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
33520
    & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_SB_relative_HI, { 0x79ce0000 }
33521
  },
33522
/* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
33523
  {
33524
    { 0, 0, 0, 0 },
33525
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
33526
    & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_SB_relative_HI, { 0x79ee0000 }
33527
  },
33528
/* mul.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
33529
  {
33530
    { 0, 0, 0, 0 },
33531
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
33532
    & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_SB_relative_HI, { 0x79fe0000 }
33533
  },
33534
/* mul.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
33535
  {
33536
    { 0, 0, 0, 0 },
33537
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
33538
    & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_FB_relative_HI, { 0x79cb0000 }
33539
  },
33540
/* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
33541
  {
33542
    { 0, 0, 0, 0 },
33543
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
33544
    & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_FB_relative_HI, { 0x79eb0000 }
33545
  },
33546
/* mul.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
33547
  {
33548
    { 0, 0, 0, 0 },
33549
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
33550
    & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_FB_relative_HI, { 0x79fb0000 }
33551
  },
33552
/* mul.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
33553
  {
33554
    { 0, 0, 0, 0 },
33555
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } },
33556
    & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_absolute_HI, { 0x79cf0000 }
33557
  },
33558
/* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
33559
  {
33560
    { 0, 0, 0, 0 },
33561
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
33562
    & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_absolute_HI, { 0x79ef0000 }
33563
  },
33564
/* mul.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
33565
  {
33566
    { 0, 0, 0, 0 },
33567
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
33568
    & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_absolute_HI, { 0x79ff0000 }
33569
  },
33570
/* mul.w${G} $Src16RnHI,$Dst16RnHI */
33571
  {
33572
    { 0, 0, 0, 0 },
33573
    { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DST16RNHI), 0 } },
33574
    & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_Rn_direct_HI, { 0x7900 }
33575
  },
33576
/* mul.w${G} $Src16AnHI,$Dst16RnHI */
33577
  {
33578
    { 0, 0, 0, 0 },
33579
    { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DST16RNHI), 0 } },
33580
    & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_Rn_direct_HI, { 0x7940 }
33581
  },
33582
/* mul.w${G} [$Src16An],$Dst16RnHI */
33583
  {
33584
    { 0, 0, 0, 0 },
33585
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } },
33586
    & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_Rn_direct_HI, { 0x7960 }
33587
  },
33588
/* mul.w${G} $Src16RnHI,$Dst16AnHI */
33589
  {
33590
    { 0, 0, 0, 0 },
33591
    { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DST16ANHI), 0 } },
33592
    & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_direct_HI, { 0x7904 }
33593
  },
33594
/* mul.w${G} $Src16AnHI,$Dst16AnHI */
33595
  {
33596
    { 0, 0, 0, 0 },
33597
    { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DST16ANHI), 0 } },
33598
    & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_direct_HI, { 0x7944 }
33599
  },
33600
/* mul.w${G} [$Src16An],$Dst16AnHI */
33601
  {
33602
    { 0, 0, 0, 0 },
33603
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } },
33604
    & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_direct_HI, { 0x7964 }
33605
  },
33606
/* mul.w${G} $Src16RnHI,[$Dst16An] */
33607
  {
33608
    { 0, 0, 0, 0 },
33609
    { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', '[', OP (DST16AN), ']', 0 } },
33610
    & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_indirect_HI, { 0x7906 }
33611
  },
33612
/* mul.w${G} $Src16AnHI,[$Dst16An] */
33613
  {
33614
    { 0, 0, 0, 0 },
33615
    { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', '[', OP (DST16AN), ']', 0 } },
33616
    & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_indirect_HI, { 0x7946 }
33617
  },
33618
/* mul.w${G} [$Src16An],[$Dst16An] */
33619
  {
33620
    { 0, 0, 0, 0 },
33621
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
33622
    & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_indirect_HI, { 0x7966 }
33623
  },
33624
/* mul.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
33625
  {
33626
    { 0, 0, 0, 0 },
33627
    { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
33628
    & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_An_relative_HI, { 0x790800 }
33629
  },
33630
/* mul.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
33631
  {
33632
    { 0, 0, 0, 0 },
33633
    { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
33634
    & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_An_relative_HI, { 0x794800 }
33635
  },
33636
/* mul.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
33637
  {
33638
    { 0, 0, 0, 0 },
33639
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
33640
    & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_An_relative_HI, { 0x796800 }
33641
  },
33642
/* mul.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
33643
  {
33644
    { 0, 0, 0, 0 },
33645
    { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
33646
    & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_An_relative_HI, { 0x790c0000 }
33647
  },
33648
/* mul.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
33649
  {
33650
    { 0, 0, 0, 0 },
33651
    { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
33652
    & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_An_relative_HI, { 0x794c0000 }
33653
  },
33654
/* mul.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
33655
  {
33656
    { 0, 0, 0, 0 },
33657
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
33658
    & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_An_relative_HI, { 0x796c0000 }
33659
  },
33660
/* mul.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */
33661
  {
33662
    { 0, 0, 0, 0 },
33663
    { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
33664
    & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_SB_relative_HI, { 0x790a00 }
33665
  },
33666
/* mul.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */
33667
  {
33668
    { 0, 0, 0, 0 },
33669
    { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
33670
    & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_SB_relative_HI, { 0x794a00 }
33671
  },
33672
/* mul.w${G} [$Src16An],${Dsp-16-u8}[sb] */
33673
  {
33674
    { 0, 0, 0, 0 },
33675
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
33676
    & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_SB_relative_HI, { 0x796a00 }
33677
  },
33678
/* mul.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */
33679
  {
33680
    { 0, 0, 0, 0 },
33681
    { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
33682
    & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_SB_relative_HI, { 0x790e0000 }
33683
  },
33684
/* mul.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */
33685
  {
33686
    { 0, 0, 0, 0 },
33687
    { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
33688
    & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_SB_relative_HI, { 0x794e0000 }
33689
  },
33690
/* mul.w${G} [$Src16An],${Dsp-16-u16}[sb] */
33691
  {
33692
    { 0, 0, 0, 0 },
33693
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
33694
    & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_SB_relative_HI, { 0x796e0000 }
33695
  },
33696
/* mul.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */
33697
  {
33698
    { 0, 0, 0, 0 },
33699
    { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
33700
    & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_FB_relative_HI, { 0x790b00 }
33701
  },
33702
/* mul.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */
33703
  {
33704
    { 0, 0, 0, 0 },
33705
    { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
33706
    & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_FB_relative_HI, { 0x794b00 }
33707
  },
33708
/* mul.w${G} [$Src16An],${Dsp-16-s8}[fb] */
33709
  {
33710
    { 0, 0, 0, 0 },
33711
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
33712
    & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_FB_relative_HI, { 0x796b00 }
33713
  },
33714
/* mul.w${G} $Src16RnHI,${Dsp-16-u16} */
33715
  {
33716
    { 0, 0, 0, 0 },
33717
    { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), 0 } },
33718
    & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_absolute_HI, { 0x790f0000 }
33719
  },
33720
/* mul.w${G} $Src16AnHI,${Dsp-16-u16} */
33721
  {
33722
    { 0, 0, 0, 0 },
33723
    { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), 0 } },
33724
    & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_absolute_HI, { 0x794f0000 }
33725
  },
33726
/* mul.w${G} [$Src16An],${Dsp-16-u16} */
33727
  {
33728
    { 0, 0, 0, 0 },
33729
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } },
33730
    & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_absolute_HI, { 0x796f0000 }
33731
  },
33732
/* mul.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
33733
  {
33734
    { 0, 0, 0, 0 },
33735
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } },
33736
    & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_Rn_direct_QI, { 0x788000 }
33737
  },
33738
/* mul.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */
33739
  {
33740
    { 0, 0, 0, 0 },
33741
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } },
33742
    & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_Rn_direct_QI, { 0x78a000 }
33743
  },
33744
/* mul.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */
33745
  {
33746
    { 0, 0, 0, 0 },
33747
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNQI), 0 } },
33748
    & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_Rn_direct_QI, { 0x78b000 }
33749
  },
33750
/* mul.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
33751
  {
33752
    { 0, 0, 0, 0 },
33753
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } },
33754
    & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_direct_QI, { 0x788400 }
33755
  },
33756
/* mul.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */
33757
  {
33758
    { 0, 0, 0, 0 },
33759
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } },
33760
    & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_direct_QI, { 0x78a400 }
33761
  },
33762
/* mul.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */
33763
  {
33764
    { 0, 0, 0, 0 },
33765
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANQI), 0 } },
33766
    & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_direct_QI, { 0x78b400 }
33767
  },
33768
/* mul.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
33769
  {
33770
    { 0, 0, 0, 0 },
33771
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
33772
    & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_indirect_QI, { 0x788600 }
33773
  },
33774
/* mul.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */
33775
  {
33776
    { 0, 0, 0, 0 },
33777
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
33778
    & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_indirect_QI, { 0x78a600 }
33779
  },
33780
/* mul.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */
33781
  {
33782
    { 0, 0, 0, 0 },
33783
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
33784
    & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_indirect_QI, { 0x78b600 }
33785
  },
33786
/* mul.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
33787
  {
33788
    { 0, 0, 0, 0 },
33789
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
33790
    & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_An_relative_QI, { 0x78880000 }
33791
  },
33792
/* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
33793
  {
33794
    { 0, 0, 0, 0 },
33795
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
33796
    & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_An_relative_QI, { 0x78a80000 }
33797
  },
33798
/* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
33799
  {
33800
    { 0, 0, 0, 0 },
33801
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
33802
    & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_An_relative_QI, { 0x78b80000 }
33803
  },
33804
/* mul.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
33805
  {
33806
    { 0, 0, 0, 0 },
33807
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
33808
    & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_An_relative_QI, { 0x788c0000 }
33809
  },
33810
/* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
33811
  {
33812
    { 0, 0, 0, 0 },
33813
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
33814
    & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_An_relative_QI, { 0x78ac0000 }
33815
  },
33816
/* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
33817
  {
33818
    { 0, 0, 0, 0 },
33819
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
33820
    & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_An_relative_QI, { 0x78bc0000 }
33821
  },
33822
/* mul.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
33823
  {
33824
    { 0, 0, 0, 0 },
33825
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
33826
    & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_SB_relative_QI, { 0x788a0000 }
33827
  },
33828
/* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
33829
  {
33830
    { 0, 0, 0, 0 },
33831
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
33832
    & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_SB_relative_QI, { 0x78aa0000 }
33833
  },
33834
/* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
33835
  {
33836
    { 0, 0, 0, 0 },
33837
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
33838
    & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_SB_relative_QI, { 0x78ba0000 }
33839
  },
33840
/* mul.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
33841
  {
33842
    { 0, 0, 0, 0 },
33843
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
33844
    & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_SB_relative_QI, { 0x788e0000 }
33845
  },
33846
/* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
33847
  {
33848
    { 0, 0, 0, 0 },
33849
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
33850
    & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_SB_relative_QI, { 0x78ae0000 }
33851
  },
33852
/* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
33853
  {
33854
    { 0, 0, 0, 0 },
33855
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
33856
    & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_SB_relative_QI, { 0x78be0000 }
33857
  },
33858
/* mul.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
33859
  {
33860
    { 0, 0, 0, 0 },
33861
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
33862
    & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_FB_relative_QI, { 0x788b0000 }
33863
  },
33864
/* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
33865
  {
33866
    { 0, 0, 0, 0 },
33867
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
33868
    & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_FB_relative_QI, { 0x78ab0000 }
33869
  },
33870
/* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
33871
  {
33872
    { 0, 0, 0, 0 },
33873
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
33874
    & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_FB_relative_QI, { 0x78bb0000 }
33875
  },
33876
/* mul.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
33877
  {
33878
    { 0, 0, 0, 0 },
33879
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } },
33880
    & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_absolute_QI, { 0x788f0000 }
33881
  },
33882
/* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
33883
  {
33884
    { 0, 0, 0, 0 },
33885
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
33886
    & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_absolute_QI, { 0x78af0000 }
33887
  },
33888
/* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
33889
  {
33890
    { 0, 0, 0, 0 },
33891
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
33892
    & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_absolute_QI, { 0x78bf0000 }
33893
  },
33894
/* mul.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
33895
  {
33896
    { 0, 0, 0, 0 },
33897
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } },
33898
    & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_Rn_direct_QI, { 0x78c00000 }
33899
  },
33900
/* mul.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */
33901
  {
33902
    { 0, 0, 0, 0 },
33903
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } },
33904
    & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_Rn_direct_QI, { 0x78e00000 }
33905
  },
33906
/* mul.b${G} ${Dsp-16-u16},$Dst16RnQI */
33907
  {
33908
    { 0, 0, 0, 0 },
33909
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16RNQI), 0 } },
33910
    & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_Rn_direct_QI, { 0x78f00000 }
33911
  },
33912
/* mul.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
33913
  {
33914
    { 0, 0, 0, 0 },
33915
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } },
33916
    & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_direct_QI, { 0x78c40000 }
33917
  },
33918
/* mul.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */
33919
  {
33920
    { 0, 0, 0, 0 },
33921
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } },
33922
    & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_direct_QI, { 0x78e40000 }
33923
  },
33924
/* mul.b${G} ${Dsp-16-u16},$Dst16AnQI */
33925
  {
33926
    { 0, 0, 0, 0 },
33927
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16ANQI), 0 } },
33928
    & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_direct_QI, { 0x78f40000 }
33929
  },
33930
/* mul.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
33931
  {
33932
    { 0, 0, 0, 0 },
33933
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
33934
    & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_indirect_QI, { 0x78c60000 }
33935
  },
33936
/* mul.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */
33937
  {
33938
    { 0, 0, 0, 0 },
33939
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
33940
    & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_indirect_QI, { 0x78e60000 }
33941
  },
33942
/* mul.b${G} ${Dsp-16-u16},[$Dst16An] */
33943
  {
33944
    { 0, 0, 0, 0 },
33945
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } },
33946
    & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_indirect_QI, { 0x78f60000 }
33947
  },
33948
/* mul.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
33949
  {
33950
    { 0, 0, 0, 0 },
33951
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
33952
    & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_An_relative_QI, { 0x78c80000 }
33953
  },
33954
/* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
33955
  {
33956
    { 0, 0, 0, 0 },
33957
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
33958
    & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_An_relative_QI, { 0x78e80000 }
33959
  },
33960
/* mul.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
33961
  {
33962
    { 0, 0, 0, 0 },
33963
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
33964
    & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_An_relative_QI, { 0x78f80000 }
33965
  },
33966
/* mul.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
33967
  {
33968
    { 0, 0, 0, 0 },
33969
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
33970
    & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_An_relative_QI, { 0x78cc0000 }
33971
  },
33972
/* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
33973
  {
33974
    { 0, 0, 0, 0 },
33975
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
33976
    & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_An_relative_QI, { 0x78ec0000 }
33977
  },
33978
/* mul.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
33979
  {
33980
    { 0, 0, 0, 0 },
33981
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
33982
    & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_An_relative_QI, { 0x78fc0000 }
33983
  },
33984
/* mul.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
33985
  {
33986
    { 0, 0, 0, 0 },
33987
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
33988
    & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_SB_relative_QI, { 0x78ca0000 }
33989
  },
33990
/* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
33991
  {
33992
    { 0, 0, 0, 0 },
33993
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
33994
    & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_SB_relative_QI, { 0x78ea0000 }
33995
  },
33996
/* mul.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
33997
  {
33998
    { 0, 0, 0, 0 },
33999
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
34000
    & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_SB_relative_QI, { 0x78fa0000 }
34001
  },
34002
/* mul.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
34003
  {
34004
    { 0, 0, 0, 0 },
34005
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
34006
    & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_SB_relative_QI, { 0x78ce0000 }
34007
  },
34008
/* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
34009
  {
34010
    { 0, 0, 0, 0 },
34011
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
34012
    & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_SB_relative_QI, { 0x78ee0000 }
34013
  },
34014
/* mul.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
34015
  {
34016
    { 0, 0, 0, 0 },
34017
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
34018
    & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_SB_relative_QI, { 0x78fe0000 }
34019
  },
34020
/* mul.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
34021
  {
34022
    { 0, 0, 0, 0 },
34023
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
34024
    & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_FB_relative_QI, { 0x78cb0000 }
34025
  },
34026
/* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
34027
  {
34028
    { 0, 0, 0, 0 },
34029
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
34030
    & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_FB_relative_QI, { 0x78eb0000 }
34031
  },
34032
/* mul.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
34033
  {
34034
    { 0, 0, 0, 0 },
34035
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
34036
    & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_FB_relative_QI, { 0x78fb0000 }
34037
  },
34038
/* mul.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
34039
  {
34040
    { 0, 0, 0, 0 },
34041
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } },
34042
    & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_absolute_QI, { 0x78cf0000 }
34043
  },
34044
/* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
34045
  {
34046
    { 0, 0, 0, 0 },
34047
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
34048
    & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_absolute_QI, { 0x78ef0000 }
34049
  },
34050
/* mul.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
34051
  {
34052
    { 0, 0, 0, 0 },
34053
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
34054
    & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_absolute_QI, { 0x78ff0000 }
34055
  },
34056
/* mul.b${G} $Src16RnQI,$Dst16RnQI */
34057
  {
34058
    { 0, 0, 0, 0 },
34059
    { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DST16RNQI), 0 } },
34060
    & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_Rn_direct_QI, { 0x7800 }
34061
  },
34062
/* mul.b${G} $Src16AnQI,$Dst16RnQI */
34063
  {
34064
    { 0, 0, 0, 0 },
34065
    { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DST16RNQI), 0 } },
34066
    & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_Rn_direct_QI, { 0x7840 }
34067
  },
34068
/* mul.b${G} [$Src16An],$Dst16RnQI */
34069
  {
34070
    { 0, 0, 0, 0 },
34071
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } },
34072
    & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_Rn_direct_QI, { 0x7860 }
34073
  },
34074
/* mul.b${G} $Src16RnQI,$Dst16AnQI */
34075
  {
34076
    { 0, 0, 0, 0 },
34077
    { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DST16ANQI), 0 } },
34078
    & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_direct_QI, { 0x7804 }
34079
  },
34080
/* mul.b${G} $Src16AnQI,$Dst16AnQI */
34081
  {
34082
    { 0, 0, 0, 0 },
34083
    { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DST16ANQI), 0 } },
34084
    & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_direct_QI, { 0x7844 }
34085
  },
34086
/* mul.b${G} [$Src16An],$Dst16AnQI */
34087
  {
34088
    { 0, 0, 0, 0 },
34089
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } },
34090
    & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_direct_QI, { 0x7864 }
34091
  },
34092
/* mul.b${G} $Src16RnQI,[$Dst16An] */
34093
  {
34094
    { 0, 0, 0, 0 },
34095
    { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', '[', OP (DST16AN), ']', 0 } },
34096
    & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_indirect_QI, { 0x7806 }
34097
  },
34098
/* mul.b${G} $Src16AnQI,[$Dst16An] */
34099
  {
34100
    { 0, 0, 0, 0 },
34101
    { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', '[', OP (DST16AN), ']', 0 } },
34102
    & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_indirect_QI, { 0x7846 }
34103
  },
34104
/* mul.b${G} [$Src16An],[$Dst16An] */
34105
  {
34106
    { 0, 0, 0, 0 },
34107
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
34108
    & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_indirect_QI, { 0x7866 }
34109
  },
34110
/* mul.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
34111
  {
34112
    { 0, 0, 0, 0 },
34113
    { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
34114
    & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_An_relative_QI, { 0x780800 }
34115
  },
34116
/* mul.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
34117
  {
34118
    { 0, 0, 0, 0 },
34119
    { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
34120
    & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_An_relative_QI, { 0x784800 }
34121
  },
34122
/* mul.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
34123
  {
34124
    { 0, 0, 0, 0 },
34125
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
34126
    & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_An_relative_QI, { 0x786800 }
34127
  },
34128
/* mul.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
34129
  {
34130
    { 0, 0, 0, 0 },
34131
    { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
34132
    & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_An_relative_QI, { 0x780c0000 }
34133
  },
34134
/* mul.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
34135
  {
34136
    { 0, 0, 0, 0 },
34137
    { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
34138
    & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_An_relative_QI, { 0x784c0000 }
34139
  },
34140
/* mul.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
34141
  {
34142
    { 0, 0, 0, 0 },
34143
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
34144
    & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_An_relative_QI, { 0x786c0000 }
34145
  },
34146
/* mul.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */
34147
  {
34148
    { 0, 0, 0, 0 },
34149
    { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
34150
    & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_SB_relative_QI, { 0x780a00 }
34151
  },
34152
/* mul.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */
34153
  {
34154
    { 0, 0, 0, 0 },
34155
    { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
34156
    & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_SB_relative_QI, { 0x784a00 }
34157
  },
34158
/* mul.b${G} [$Src16An],${Dsp-16-u8}[sb] */
34159
  {
34160
    { 0, 0, 0, 0 },
34161
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
34162
    & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_SB_relative_QI, { 0x786a00 }
34163
  },
34164
/* mul.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */
34165
  {
34166
    { 0, 0, 0, 0 },
34167
    { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
34168
    & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_SB_relative_QI, { 0x780e0000 }
34169
  },
34170
/* mul.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */
34171
  {
34172
    { 0, 0, 0, 0 },
34173
    { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
34174
    & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_SB_relative_QI, { 0x784e0000 }
34175
  },
34176
/* mul.b${G} [$Src16An],${Dsp-16-u16}[sb] */
34177
  {
34178
    { 0, 0, 0, 0 },
34179
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
34180
    & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_SB_relative_QI, { 0x786e0000 }
34181
  },
34182
/* mul.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */
34183
  {
34184
    { 0, 0, 0, 0 },
34185
    { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
34186
    & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_FB_relative_QI, { 0x780b00 }
34187
  },
34188
/* mul.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */
34189
  {
34190
    { 0, 0, 0, 0 },
34191
    { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
34192
    & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_FB_relative_QI, { 0x784b00 }
34193
  },
34194
/* mul.b${G} [$Src16An],${Dsp-16-s8}[fb] */
34195
  {
34196
    { 0, 0, 0, 0 },
34197
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
34198
    & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_FB_relative_QI, { 0x786b00 }
34199
  },
34200
/* mul.b${G} $Src16RnQI,${Dsp-16-u16} */
34201
  {
34202
    { 0, 0, 0, 0 },
34203
    { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), 0 } },
34204
    & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_absolute_QI, { 0x780f0000 }
34205
  },
34206
/* mul.b${G} $Src16AnQI,${Dsp-16-u16} */
34207
  {
34208
    { 0, 0, 0, 0 },
34209
    { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), 0 } },
34210
    & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_absolute_QI, { 0x784f0000 }
34211
  },
34212
/* mul.b${G} [$Src16An],${Dsp-16-u16} */
34213
  {
34214
    { 0, 0, 0, 0 },
34215
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } },
34216
    & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_absolute_QI, { 0x786f0000 }
34217
  },
34218
/* mul.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */
34219
  {
34220
    { 0, 0, 0, 0 },
34221
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
34222
    & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0x891f0000 }
34223
  },
34224
/* mul.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */
34225
  {
34226
    { 0, 0, 0, 0 },
34227
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
34228
    & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0x819f0000 }
34229
  },
34230
/* mul.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */
34231
  {
34232
    { 0, 0, 0, 0 },
34233
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
34234
    & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0x811f0000 }
34235
  },
34236
/* mul.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
34237
  {
34238
    { 0, 0, 0, 0 },
34239
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
34240
    & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0x831f0000 }
34241
  },
34242
/* mul.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
34243
  {
34244
    { 0, 0, 0, 0 },
34245
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
34246
    & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0x839f0000 }
34247
  },
34248
/* mul.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
34249
  {
34250
    { 0, 0, 0, 0 },
34251
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
34252
    & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83df0000 }
34253
  },
34254
/* mul.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
34255
  {
34256
    { 0, 0, 0, 0 },
34257
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
34258
    & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0x851f0000 }
34259
  },
34260
/* mul.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
34261
  {
34262
    { 0, 0, 0, 0 },
34263
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
34264
    & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0x859f0000 }
34265
  },
34266
/* mul.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */
34267
  {
34268
    { 0, 0, 0, 0 },
34269
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
34270
    & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85df0000 }
34271
  },
34272
/* mul.w${G} #${Imm-32-HI},${Dsp-16-u16} */
34273
  {
34274
    { 0, 0, 0, 0 },
34275
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } },
34276
    & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0x87df0000 }
34277
  },
34278
/* mul.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
34279
  {
34280
    { 0, 0, 0, 0 },
34281
    { { MNEM, OP (G), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
34282
    & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0x871f0000 }
34283
  },
34284
/* mul.w${G} #${Imm-40-HI},${Dsp-16-u24} */
34285
  {
34286
    { 0, 0, 0, 0 },
34287
    { { MNEM, OP (G), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), 0 } },
34288
    & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0x879f0000 }
34289
  },
34290
/* mul.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */
34291
  {
34292
    { 0, 0, 0, 0 },
34293
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
34294
    & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0x881f00 }
34295
  },
34296
/* mul.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */
34297
  {
34298
    { 0, 0, 0, 0 },
34299
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
34300
    & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0x809f00 }
34301
  },
34302
/* mul.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */
34303
  {
34304
    { 0, 0, 0, 0 },
34305
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
34306
    & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0x801f00 }
34307
  },
34308
/* mul.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
34309
  {
34310
    { 0, 0, 0, 0 },
34311
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
34312
    & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0x821f0000 }
34313
  },
34314
/* mul.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
34315
  {
34316
    { 0, 0, 0, 0 },
34317
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
34318
    & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0x829f0000 }
34319
  },
34320
/* mul.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
34321
  {
34322
    { 0, 0, 0, 0 },
34323
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
34324
    & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82df0000 }
34325
  },
34326
/* mul.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
34327
  {
34328
    { 0, 0, 0, 0 },
34329
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
34330
    & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0x841f0000 }
34331
  },
34332
/* mul.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
34333
  {
34334
    { 0, 0, 0, 0 },
34335
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
34336
    & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0x849f0000 }
34337
  },
34338
/* mul.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */
34339
  {
34340
    { 0, 0, 0, 0 },
34341
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
34342
    & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84df0000 }
34343
  },
34344
/* mul.b${G} #${Imm-32-QI},${Dsp-16-u16} */
34345
  {
34346
    { 0, 0, 0, 0 },
34347
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } },
34348
    & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0x86df0000 }
34349
  },
34350
/* mul.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
34351
  {
34352
    { 0, 0, 0, 0 },
34353
    { { MNEM, OP (G), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
34354
    & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0x861f0000 }
34355
  },
34356
/* mul.b${G} #${Imm-40-QI},${Dsp-16-u24} */
34357
  {
34358
    { 0, 0, 0, 0 },
34359
    { { MNEM, OP (G), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), 0 } },
34360
    & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0x869f0000 }
34361
  },
34362
/* mul.w${G} #${Imm-16-HI},$Dst16RnHI */
34363
  {
34364
    { 0, 0, 0, 0 },
34365
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST16RNHI), 0 } },
34366
    & ifmt_xor16_w_imm_G_basic_dst16_Rn_direct_HI, { 0x7d500000 }
34367
  },
34368
/* mul.w${G} #${Imm-16-HI},$Dst16AnHI */
34369
  {
34370
    { 0, 0, 0, 0 },
34371
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST16ANHI), 0 } },
34372
    & ifmt_xor16_w_imm_G_basic_dst16_An_direct_HI, { 0x7d540000 }
34373
  },
34374
/* mul.w${G} #${Imm-16-HI},[$Dst16An] */
34375
  {
34376
    { 0, 0, 0, 0 },
34377
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST16AN), ']', 0 } },
34378
    & ifmt_xor16_w_imm_G_basic_dst16_An_indirect_HI, { 0x7d560000 }
34379
  },
34380
/* mul.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
34381
  {
34382
    { 0, 0, 0, 0 },
34383
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
34384
    & ifmt_xor16_w_imm_G_16_8_dst16_16_8_An_relative_HI, { 0x7d580000 }
34385
  },
34386
/* mul.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
34387
  {
34388
    { 0, 0, 0, 0 },
34389
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
34390
    & ifmt_xor16_w_imm_G_16_8_dst16_16_8_SB_relative_HI, { 0x7d5a0000 }
34391
  },
34392
/* mul.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
34393
  {
34394
    { 0, 0, 0, 0 },
34395
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
34396
    & ifmt_xor16_w_imm_G_16_8_dst16_16_8_FB_relative_HI, { 0x7d5b0000 }
34397
  },
34398
/* mul.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
34399
  {
34400
    { 0, 0, 0, 0 },
34401
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
34402
    & ifmt_xor16_w_imm_G_16_16_dst16_16_16_An_relative_HI, { 0x7d5c0000 }
34403
  },
34404
/* mul.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
34405
  {
34406
    { 0, 0, 0, 0 },
34407
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
34408
    & ifmt_xor16_w_imm_G_16_16_dst16_16_16_SB_relative_HI, { 0x7d5e0000 }
34409
  },
34410
/* mul.w${G} #${Imm-32-HI},${Dsp-16-u16} */
34411
  {
34412
    { 0, 0, 0, 0 },
34413
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } },
34414
    & ifmt_xor16_w_imm_G_16_16_dst16_16_16_absolute_HI, { 0x7d5f0000 }
34415
  },
34416
/* mul.b${G} #${Imm-16-QI},$Dst16RnQI */
34417
  {
34418
    { 0, 0, 0, 0 },
34419
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST16RNQI), 0 } },
34420
    & ifmt_xor16_b_imm_G_basic_dst16_Rn_direct_QI, { 0x7c5000 }
34421
  },
34422
/* mul.b${G} #${Imm-16-QI},$Dst16AnQI */
34423
  {
34424
    { 0, 0, 0, 0 },
34425
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST16ANQI), 0 } },
34426
    & ifmt_xor16_b_imm_G_basic_dst16_An_direct_QI, { 0x7c5400 }
34427
  },
34428
/* mul.b${G} #${Imm-16-QI},[$Dst16An] */
34429
  {
34430
    { 0, 0, 0, 0 },
34431
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST16AN), ']', 0 } },
34432
    & ifmt_xor16_b_imm_G_basic_dst16_An_indirect_QI, { 0x7c5600 }
34433
  },
34434
/* mul.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
34435
  {
34436
    { 0, 0, 0, 0 },
34437
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
34438
    & ifmt_xor16_b_imm_G_16_8_dst16_16_8_An_relative_QI, { 0x7c580000 }
34439
  },
34440
/* mul.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
34441
  {
34442
    { 0, 0, 0, 0 },
34443
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
34444
    & ifmt_xor16_b_imm_G_16_8_dst16_16_8_SB_relative_QI, { 0x7c5a0000 }
34445
  },
34446
/* mul.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
34447
  {
34448
    { 0, 0, 0, 0 },
34449
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
34450
    & ifmt_xor16_b_imm_G_16_8_dst16_16_8_FB_relative_QI, { 0x7c5b0000 }
34451
  },
34452
/* mul.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
34453
  {
34454
    { 0, 0, 0, 0 },
34455
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
34456
    & ifmt_xor16_b_imm_G_16_16_dst16_16_16_An_relative_QI, { 0x7c5c0000 }
34457
  },
34458
/* mul.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
34459
  {
34460
    { 0, 0, 0, 0 },
34461
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
34462
    & ifmt_xor16_b_imm_G_16_16_dst16_16_16_SB_relative_QI, { 0x7c5e0000 }
34463
  },
34464
/* mul.b${G} #${Imm-32-QI},${Dsp-16-u16} */
34465
  {
34466
    { 0, 0, 0, 0 },
34467
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } },
34468
    & ifmt_xor16_b_imm_G_16_16_dst16_16_16_absolute_QI, { 0x7c5f0000 }
34469
  },
34470
/* movx${X} #${Imm-16-QI},$Dst32RnUnprefixedSI */
34471
  {
34472
    { 0, 0, 0, 0 },
34473
    { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
34474
    & ifmt_subx32_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_SI, { 0xb81100 }
34475
  },
34476
/* movx${X} #${Imm-16-QI},$Dst32AnUnprefixedSI */
34477
  {
34478
    { 0, 0, 0, 0 },
34479
    { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
34480
    & ifmt_subx32_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_SI, { 0xb09100 }
34481
  },
34482
/* movx${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */
34483
  {
34484
    { 0, 0, 0, 0 },
34485
    { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
34486
    & ifmt_subx32_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_SI, { 0xb01100 }
34487
  },
34488
/* movx${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
34489
  {
34490
    { 0, 0, 0, 0 },
34491
    { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
34492
    & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_SI, { 0xb2110000 }
34493
  },
34494
/* movx${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
34495
  {
34496
    { 0, 0, 0, 0 },
34497
    { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
34498
    & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_SI, { 0xb2910000 }
34499
  },
34500
/* movx${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
34501
  {
34502
    { 0, 0, 0, 0 },
34503
    { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
34504
    & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_SI, { 0xb2d10000 }
34505
  },
34506
/* movx${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
34507
  {
34508
    { 0, 0, 0, 0 },
34509
    { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
34510
    & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_SI, { 0xb4110000 }
34511
  },
34512
/* movx${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
34513
  {
34514
    { 0, 0, 0, 0 },
34515
    { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
34516
    & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_SI, { 0xb4910000 }
34517
  },
34518
/* movx${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */
34519
  {
34520
    { 0, 0, 0, 0 },
34521
    { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
34522
    & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_SI, { 0xb4d10000 }
34523
  },
34524
/* movx${X} #${Imm-32-QI},${Dsp-16-u16} */
34525
  {
34526
    { 0, 0, 0, 0 },
34527
    { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } },
34528
    & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_SI, { 0xb6d10000 }
34529
  },
34530
/* movx${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
34531
  {
34532
    { 0, 0, 0, 0 },
34533
    { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
34534
    & ifmt_subx32_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_SI, { 0xb6110000 }
34535
  },
34536
/* movx${X} #${Imm-40-QI},${Dsp-16-u24} */
34537
  {
34538
    { 0, 0, 0, 0 },
34539
    { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), 0 } },
34540
    & ifmt_subx32_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_SI, { 0xb6910000 }
34541
  },
34542
/* movhh $Dst32RnPrefixedQI,r0l */
34543
  {
34544
    { 0, 0, 0, 0 },
34545
    { { MNEM, ' ', OP (DST32RNPREFIXEDQI), ',', 'r', '0', 'l', 0 } },
34546
    & ifmt_movhh32_src_r0l_dst32_Rn_direct_Prefixed_QI, { 0x1a83e }
34547
  },
34548
/* movhh $Dst32AnPrefixedQI,r0l */
34549
  {
34550
    { 0, 0, 0, 0 },
34551
    { { MNEM, ' ', OP (DST32ANPREFIXEDQI), ',', 'r', '0', 'l', 0 } },
34552
    & ifmt_movhh32_src_r0l_dst32_An_direct_Prefixed_QI, { 0x1a0be }
34553
  },
34554
/* movhh [$Dst32AnPrefixed],r0l */
34555
  {
34556
    { 0, 0, 0, 0 },
34557
    { { MNEM, ' ', '[', OP (DST32ANPREFIXED), ']', ',', 'r', '0', 'l', 0 } },
34558
    & ifmt_movhh32_src_r0l_dst32_An_indirect_Prefixed_QI, { 0x1a03e }
34559
  },
34560
/* movhh ${Dsp-24-u8}[$Dst32AnPrefixed],r0l */
34561
  {
34562
    { 0, 0, 0, 0 },
34563
    { { MNEM, ' ', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', ',', 'r', '0', 'l', 0 } },
34564
    & ifmt_movhh32_src_r0l_dst32_24_8_An_relative_Prefixed_QI, { 0x1a23e00 }
34565
  },
34566
/* movhh ${Dsp-24-u16}[$Dst32AnPrefixed],r0l */
34567
  {
34568
    { 0, 0, 0, 0 },
34569
    { { MNEM, ' ', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', ',', 'r', '0', 'l', 0 } },
34570
    & ifmt_movhh32_src_r0l_dst32_24_16_An_relative_Prefixed_QI, { 0x1a43e00 }
34571
  },
34572
/* movhh ${Dsp-24-u24}[$Dst32AnPrefixed],r0l */
34573
  {
34574
    { 0, 0, 0, 0 },
34575
    { { MNEM, ' ', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', ',', 'r', '0', 'l', 0 } },
34576
    & ifmt_movhh32_src_r0l_dst32_24_24_An_relative_Prefixed_QI, { 0x1a63e00 }
34577
  },
34578
/* movhh ${Dsp-24-u8}[sb],r0l */
34579
  {
34580
    { 0, 0, 0, 0 },
34581
    { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', 'r', '0', 'l', 0 } },
34582
    & ifmt_movhh32_src_r0l_dst32_24_8_SB_relative_Prefixed_QI, { 0x1a2be00 }
34583
  },
34584
/* movhh ${Dsp-24-u16}[sb],r0l */
34585
  {
34586
    { 0, 0, 0, 0 },
34587
    { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', 'r', '0', 'l', 0 } },
34588
    & ifmt_movhh32_src_r0l_dst32_24_16_SB_relative_Prefixed_QI, { 0x1a4be00 }
34589
  },
34590
/* movhh ${Dsp-24-s8}[fb],r0l */
34591
  {
34592
    { 0, 0, 0, 0 },
34593
    { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', 'r', '0', 'l', 0 } },
34594
    & ifmt_movhh32_src_r0l_dst32_24_8_FB_relative_Prefixed_QI, { 0x1a2fe00 }
34595
  },
34596
/* movhh ${Dsp-24-s16}[fb],r0l */
34597
  {
34598
    { 0, 0, 0, 0 },
34599
    { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', 'r', '0', 'l', 0 } },
34600
    & ifmt_movhh32_src_r0l_dst32_24_16_FB_relative_Prefixed_QI, { 0x1a4fe00 }
34601
  },
34602
/* movhh ${Dsp-24-u16},r0l */
34603
  {
34604
    { 0, 0, 0, 0 },
34605
    { { MNEM, ' ', OP (DSP_24_U16), ',', 'r', '0', 'l', 0 } },
34606
    & ifmt_movhh32_src_r0l_dst32_24_16_absolute_Prefixed_QI, { 0x1a6fe00 }
34607
  },
34608
/* movhh ${Dsp-24-u24},r0l */
34609
  {
34610
    { 0, 0, 0, 0 },
34611
    { { MNEM, ' ', OP (DSP_24_U24), ',', 'r', '0', 'l', 0 } },
34612
    & ifmt_movhh32_src_r0l_dst32_24_24_absolute_Prefixed_QI, { 0x1a6be00 }
34613
  },
34614
/* movhl $Dst32RnPrefixedQI,r0l */
34615
  {
34616
    { 0, 0, 0, 0 },
34617
    { { MNEM, ' ', OP (DST32RNPREFIXEDQI), ',', 'r', '0', 'l', 0 } },
34618
    & ifmt_movhh32_src_r0l_dst32_Rn_direct_Prefixed_QI, { 0x1a82e }
34619
  },
34620
/* movhl $Dst32AnPrefixedQI,r0l */
34621
  {
34622
    { 0, 0, 0, 0 },
34623
    { { MNEM, ' ', OP (DST32ANPREFIXEDQI), ',', 'r', '0', 'l', 0 } },
34624
    & ifmt_movhh32_src_r0l_dst32_An_direct_Prefixed_QI, { 0x1a0ae }
34625
  },
34626
/* movhl [$Dst32AnPrefixed],r0l */
34627
  {
34628
    { 0, 0, 0, 0 },
34629
    { { MNEM, ' ', '[', OP (DST32ANPREFIXED), ']', ',', 'r', '0', 'l', 0 } },
34630
    & ifmt_movhh32_src_r0l_dst32_An_indirect_Prefixed_QI, { 0x1a02e }
34631
  },
34632
/* movhl ${Dsp-24-u8}[$Dst32AnPrefixed],r0l */
34633
  {
34634
    { 0, 0, 0, 0 },
34635
    { { MNEM, ' ', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', ',', 'r', '0', 'l', 0 } },
34636
    & ifmt_movhh32_src_r0l_dst32_24_8_An_relative_Prefixed_QI, { 0x1a22e00 }
34637
  },
34638
/* movhl ${Dsp-24-u16}[$Dst32AnPrefixed],r0l */
34639
  {
34640
    { 0, 0, 0, 0 },
34641
    { { MNEM, ' ', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', ',', 'r', '0', 'l', 0 } },
34642
    & ifmt_movhh32_src_r0l_dst32_24_16_An_relative_Prefixed_QI, { 0x1a42e00 }
34643
  },
34644
/* movhl ${Dsp-24-u24}[$Dst32AnPrefixed],r0l */
34645
  {
34646
    { 0, 0, 0, 0 },
34647
    { { MNEM, ' ', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', ',', 'r', '0', 'l', 0 } },
34648
    & ifmt_movhh32_src_r0l_dst32_24_24_An_relative_Prefixed_QI, { 0x1a62e00 }
34649
  },
34650
/* movhl ${Dsp-24-u8}[sb],r0l */
34651
  {
34652
    { 0, 0, 0, 0 },
34653
    { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', 'r', '0', 'l', 0 } },
34654
    & ifmt_movhh32_src_r0l_dst32_24_8_SB_relative_Prefixed_QI, { 0x1a2ae00 }
34655
  },
34656
/* movhl ${Dsp-24-u16}[sb],r0l */
34657
  {
34658
    { 0, 0, 0, 0 },
34659
    { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', 'r', '0', 'l', 0 } },
34660
    & ifmt_movhh32_src_r0l_dst32_24_16_SB_relative_Prefixed_QI, { 0x1a4ae00 }
34661
  },
34662
/* movhl ${Dsp-24-s8}[fb],r0l */
34663
  {
34664
    { 0, 0, 0, 0 },
34665
    { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', 'r', '0', 'l', 0 } },
34666
    & ifmt_movhh32_src_r0l_dst32_24_8_FB_relative_Prefixed_QI, { 0x1a2ee00 }
34667
  },
34668
/* movhl ${Dsp-24-s16}[fb],r0l */
34669
  {
34670
    { 0, 0, 0, 0 },
34671
    { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', 'r', '0', 'l', 0 } },
34672
    & ifmt_movhh32_src_r0l_dst32_24_16_FB_relative_Prefixed_QI, { 0x1a4ee00 }
34673
  },
34674
/* movhl ${Dsp-24-u16},r0l */
34675
  {
34676
    { 0, 0, 0, 0 },
34677
    { { MNEM, ' ', OP (DSP_24_U16), ',', 'r', '0', 'l', 0 } },
34678
    & ifmt_movhh32_src_r0l_dst32_24_16_absolute_Prefixed_QI, { 0x1a6ee00 }
34679
  },
34680
/* movhl ${Dsp-24-u24},r0l */
34681
  {
34682
    { 0, 0, 0, 0 },
34683
    { { MNEM, ' ', OP (DSP_24_U24), ',', 'r', '0', 'l', 0 } },
34684
    & ifmt_movhh32_src_r0l_dst32_24_24_absolute_Prefixed_QI, { 0x1a6ae00 }
34685
  },
34686
/* movlh $Dst32RnPrefixedQI,r0l */
34687
  {
34688
    { 0, 0, 0, 0 },
34689
    { { MNEM, ' ', OP (DST32RNPREFIXEDQI), ',', 'r', '0', 'l', 0 } },
34690
    & ifmt_movhh32_src_r0l_dst32_Rn_direct_Prefixed_QI, { 0x1a81e }
34691
  },
34692
/* movlh $Dst32AnPrefixedQI,r0l */
34693
  {
34694
    { 0, 0, 0, 0 },
34695
    { { MNEM, ' ', OP (DST32ANPREFIXEDQI), ',', 'r', '0', 'l', 0 } },
34696
    & ifmt_movhh32_src_r0l_dst32_An_direct_Prefixed_QI, { 0x1a09e }
34697
  },
34698
/* movlh [$Dst32AnPrefixed],r0l */
34699
  {
34700
    { 0, 0, 0, 0 },
34701
    { { MNEM, ' ', '[', OP (DST32ANPREFIXED), ']', ',', 'r', '0', 'l', 0 } },
34702
    & ifmt_movhh32_src_r0l_dst32_An_indirect_Prefixed_QI, { 0x1a01e }
34703
  },
34704
/* movlh ${Dsp-24-u8}[$Dst32AnPrefixed],r0l */
34705
  {
34706
    { 0, 0, 0, 0 },
34707
    { { MNEM, ' ', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', ',', 'r', '0', 'l', 0 } },
34708
    & ifmt_movhh32_src_r0l_dst32_24_8_An_relative_Prefixed_QI, { 0x1a21e00 }
34709
  },
34710
/* movlh ${Dsp-24-u16}[$Dst32AnPrefixed],r0l */
34711
  {
34712
    { 0, 0, 0, 0 },
34713
    { { MNEM, ' ', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', ',', 'r', '0', 'l', 0 } },
34714
    & ifmt_movhh32_src_r0l_dst32_24_16_An_relative_Prefixed_QI, { 0x1a41e00 }
34715
  },
34716
/* movlh ${Dsp-24-u24}[$Dst32AnPrefixed],r0l */
34717
  {
34718
    { 0, 0, 0, 0 },
34719
    { { MNEM, ' ', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', ',', 'r', '0', 'l', 0 } },
34720
    & ifmt_movhh32_src_r0l_dst32_24_24_An_relative_Prefixed_QI, { 0x1a61e00 }
34721
  },
34722
/* movlh ${Dsp-24-u8}[sb],r0l */
34723
  {
34724
    { 0, 0, 0, 0 },
34725
    { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', 'r', '0', 'l', 0 } },
34726
    & ifmt_movhh32_src_r0l_dst32_24_8_SB_relative_Prefixed_QI, { 0x1a29e00 }
34727
  },
34728
/* movlh ${Dsp-24-u16}[sb],r0l */
34729
  {
34730
    { 0, 0, 0, 0 },
34731
    { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', 'r', '0', 'l', 0 } },
34732
    & ifmt_movhh32_src_r0l_dst32_24_16_SB_relative_Prefixed_QI, { 0x1a49e00 }
34733
  },
34734
/* movlh ${Dsp-24-s8}[fb],r0l */
34735
  {
34736
    { 0, 0, 0, 0 },
34737
    { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', 'r', '0', 'l', 0 } },
34738
    & ifmt_movhh32_src_r0l_dst32_24_8_FB_relative_Prefixed_QI, { 0x1a2de00 }
34739
  },
34740
/* movlh ${Dsp-24-s16}[fb],r0l */
34741
  {
34742
    { 0, 0, 0, 0 },
34743
    { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', 'r', '0', 'l', 0 } },
34744
    & ifmt_movhh32_src_r0l_dst32_24_16_FB_relative_Prefixed_QI, { 0x1a4de00 }
34745
  },
34746
/* movlh ${Dsp-24-u16},r0l */
34747
  {
34748
    { 0, 0, 0, 0 },
34749
    { { MNEM, ' ', OP (DSP_24_U16), ',', 'r', '0', 'l', 0 } },
34750
    & ifmt_movhh32_src_r0l_dst32_24_16_absolute_Prefixed_QI, { 0x1a6de00 }
34751
  },
34752
/* movlh ${Dsp-24-u24},r0l */
34753
  {
34754
    { 0, 0, 0, 0 },
34755
    { { MNEM, ' ', OP (DSP_24_U24), ',', 'r', '0', 'l', 0 } },
34756
    & ifmt_movhh32_src_r0l_dst32_24_24_absolute_Prefixed_QI, { 0x1a69e00 }
34757
  },
34758
/* movll $Dst32RnPrefixedQI,r0l */
34759
  {
34760
    { 0, 0, 0, 0 },
34761
    { { MNEM, ' ', OP (DST32RNPREFIXEDQI), ',', 'r', '0', 'l', 0 } },
34762
    & ifmt_movhh32_src_r0l_dst32_Rn_direct_Prefixed_QI, { 0x1a80e }
34763
  },
34764
/* movll $Dst32AnPrefixedQI,r0l */
34765
  {
34766
    { 0, 0, 0, 0 },
34767
    { { MNEM, ' ', OP (DST32ANPREFIXEDQI), ',', 'r', '0', 'l', 0 } },
34768
    & ifmt_movhh32_src_r0l_dst32_An_direct_Prefixed_QI, { 0x1a08e }
34769
  },
34770
/* movll [$Dst32AnPrefixed],r0l */
34771
  {
34772
    { 0, 0, 0, 0 },
34773
    { { MNEM, ' ', '[', OP (DST32ANPREFIXED), ']', ',', 'r', '0', 'l', 0 } },
34774
    & ifmt_movhh32_src_r0l_dst32_An_indirect_Prefixed_QI, { 0x1a00e }
34775
  },
34776
/* movll ${Dsp-24-u8}[$Dst32AnPrefixed],r0l */
34777
  {
34778
    { 0, 0, 0, 0 },
34779
    { { MNEM, ' ', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', ',', 'r', '0', 'l', 0 } },
34780
    & ifmt_movhh32_src_r0l_dst32_24_8_An_relative_Prefixed_QI, { 0x1a20e00 }
34781
  },
34782
/* movll ${Dsp-24-u16}[$Dst32AnPrefixed],r0l */
34783
  {
34784
    { 0, 0, 0, 0 },
34785
    { { MNEM, ' ', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', ',', 'r', '0', 'l', 0 } },
34786
    & ifmt_movhh32_src_r0l_dst32_24_16_An_relative_Prefixed_QI, { 0x1a40e00 }
34787
  },
34788
/* movll ${Dsp-24-u24}[$Dst32AnPrefixed],r0l */
34789
  {
34790
    { 0, 0, 0, 0 },
34791
    { { MNEM, ' ', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', ',', 'r', '0', 'l', 0 } },
34792
    & ifmt_movhh32_src_r0l_dst32_24_24_An_relative_Prefixed_QI, { 0x1a60e00 }
34793
  },
34794
/* movll ${Dsp-24-u8}[sb],r0l */
34795
  {
34796
    { 0, 0, 0, 0 },
34797
    { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', 'r', '0', 'l', 0 } },
34798
    & ifmt_movhh32_src_r0l_dst32_24_8_SB_relative_Prefixed_QI, { 0x1a28e00 }
34799
  },
34800
/* movll ${Dsp-24-u16}[sb],r0l */
34801
  {
34802
    { 0, 0, 0, 0 },
34803
    { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', 'r', '0', 'l', 0 } },
34804
    & ifmt_movhh32_src_r0l_dst32_24_16_SB_relative_Prefixed_QI, { 0x1a48e00 }
34805
  },
34806
/* movll ${Dsp-24-s8}[fb],r0l */
34807
  {
34808
    { 0, 0, 0, 0 },
34809
    { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', 'r', '0', 'l', 0 } },
34810
    & ifmt_movhh32_src_r0l_dst32_24_8_FB_relative_Prefixed_QI, { 0x1a2ce00 }
34811
  },
34812
/* movll ${Dsp-24-s16}[fb],r0l */
34813
  {
34814
    { 0, 0, 0, 0 },
34815
    { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', 'r', '0', 'l', 0 } },
34816
    & ifmt_movhh32_src_r0l_dst32_24_16_FB_relative_Prefixed_QI, { 0x1a4ce00 }
34817
  },
34818
/* movll ${Dsp-24-u16},r0l */
34819
  {
34820
    { 0, 0, 0, 0 },
34821
    { { MNEM, ' ', OP (DSP_24_U16), ',', 'r', '0', 'l', 0 } },
34822
    & ifmt_movhh32_src_r0l_dst32_24_16_absolute_Prefixed_QI, { 0x1a6ce00 }
34823
  },
34824
/* movll ${Dsp-24-u24},r0l */
34825
  {
34826
    { 0, 0, 0, 0 },
34827
    { { MNEM, ' ', OP (DSP_24_U24), ',', 'r', '0', 'l', 0 } },
34828
    & ifmt_movhh32_src_r0l_dst32_24_24_absolute_Prefixed_QI, { 0x1a68e00 }
34829
  },
34830
/* movhh r0l,$Dst32RnPrefixedQI */
34831
  {
34832
    { 0, 0, 0, 0 },
34833
    { { MNEM, ' ', 'r', '0', 'l', ',', OP (DST32RNPREFIXEDQI), 0 } },
34834
    & ifmt_movhh32_src_r0l_dst32_Rn_direct_Prefixed_QI, { 0x1b83e }
34835
  },
34836
/* movhh r0l,$Dst32AnPrefixedQI */
34837
  {
34838
    { 0, 0, 0, 0 },
34839
    { { MNEM, ' ', 'r', '0', 'l', ',', OP (DST32ANPREFIXEDQI), 0 } },
34840
    & ifmt_movhh32_src_r0l_dst32_An_direct_Prefixed_QI, { 0x1b0be }
34841
  },
34842
/* movhh r0l,[$Dst32AnPrefixed] */
34843
  {
34844
    { 0, 0, 0, 0 },
34845
    { { MNEM, ' ', 'r', '0', 'l', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
34846
    & ifmt_movhh32_src_r0l_dst32_An_indirect_Prefixed_QI, { 0x1b03e }
34847
  },
34848
/* movhh r0l,${Dsp-24-u8}[$Dst32AnPrefixed] */
34849
  {
34850
    { 0, 0, 0, 0 },
34851
    { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
34852
    & ifmt_movhh32_src_r0l_dst32_24_8_An_relative_Prefixed_QI, { 0x1b23e00 }
34853
  },
34854
/* movhh r0l,${Dsp-24-u16}[$Dst32AnPrefixed] */
34855
  {
34856
    { 0, 0, 0, 0 },
34857
    { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
34858
    & ifmt_movhh32_src_r0l_dst32_24_16_An_relative_Prefixed_QI, { 0x1b43e00 }
34859
  },
34860
/* movhh r0l,${Dsp-24-u24}[$Dst32AnPrefixed] */
34861
  {
34862
    { 0, 0, 0, 0 },
34863
    { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
34864
    & ifmt_movhh32_src_r0l_dst32_24_24_An_relative_Prefixed_QI, { 0x1b63e00 }
34865
  },
34866
/* movhh r0l,${Dsp-24-u8}[sb] */
34867
  {
34868
    { 0, 0, 0, 0 },
34869
    { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
34870
    & ifmt_movhh32_src_r0l_dst32_24_8_SB_relative_Prefixed_QI, { 0x1b2be00 }
34871
  },
34872
/* movhh r0l,${Dsp-24-u16}[sb] */
34873
  {
34874
    { 0, 0, 0, 0 },
34875
    { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
34876
    & ifmt_movhh32_src_r0l_dst32_24_16_SB_relative_Prefixed_QI, { 0x1b4be00 }
34877
  },
34878
/* movhh r0l,${Dsp-24-s8}[fb] */
34879
  {
34880
    { 0, 0, 0, 0 },
34881
    { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
34882
    & ifmt_movhh32_src_r0l_dst32_24_8_FB_relative_Prefixed_QI, { 0x1b2fe00 }
34883
  },
34884
/* movhh r0l,${Dsp-24-s16}[fb] */
34885
  {
34886
    { 0, 0, 0, 0 },
34887
    { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
34888
    & ifmt_movhh32_src_r0l_dst32_24_16_FB_relative_Prefixed_QI, { 0x1b4fe00 }
34889
  },
34890
/* movhh r0l,${Dsp-24-u16} */
34891
  {
34892
    { 0, 0, 0, 0 },
34893
    { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U16), 0 } },
34894
    & ifmt_movhh32_src_r0l_dst32_24_16_absolute_Prefixed_QI, { 0x1b6fe00 }
34895
  },
34896
/* movhh r0l,${Dsp-24-u24} */
34897
  {
34898
    { 0, 0, 0, 0 },
34899
    { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U24), 0 } },
34900
    & ifmt_movhh32_src_r0l_dst32_24_24_absolute_Prefixed_QI, { 0x1b6be00 }
34901
  },
34902
/* movhl r0l,$Dst32RnPrefixedQI */
34903
  {
34904
    { 0, 0, 0, 0 },
34905
    { { MNEM, ' ', 'r', '0', 'l', ',', OP (DST32RNPREFIXEDQI), 0 } },
34906
    & ifmt_movhh32_src_r0l_dst32_Rn_direct_Prefixed_QI, { 0x1b82e }
34907
  },
34908
/* movhl r0l,$Dst32AnPrefixedQI */
34909
  {
34910
    { 0, 0, 0, 0 },
34911
    { { MNEM, ' ', 'r', '0', 'l', ',', OP (DST32ANPREFIXEDQI), 0 } },
34912
    & ifmt_movhh32_src_r0l_dst32_An_direct_Prefixed_QI, { 0x1b0ae }
34913
  },
34914
/* movhl r0l,[$Dst32AnPrefixed] */
34915
  {
34916
    { 0, 0, 0, 0 },
34917
    { { MNEM, ' ', 'r', '0', 'l', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
34918
    & ifmt_movhh32_src_r0l_dst32_An_indirect_Prefixed_QI, { 0x1b02e }
34919
  },
34920
/* movhl r0l,${Dsp-24-u8}[$Dst32AnPrefixed] */
34921
  {
34922
    { 0, 0, 0, 0 },
34923
    { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
34924
    & ifmt_movhh32_src_r0l_dst32_24_8_An_relative_Prefixed_QI, { 0x1b22e00 }
34925
  },
34926
/* movhl r0l,${Dsp-24-u16}[$Dst32AnPrefixed] */
34927
  {
34928
    { 0, 0, 0, 0 },
34929
    { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
34930
    & ifmt_movhh32_src_r0l_dst32_24_16_An_relative_Prefixed_QI, { 0x1b42e00 }
34931
  },
34932
/* movhl r0l,${Dsp-24-u24}[$Dst32AnPrefixed] */
34933
  {
34934
    { 0, 0, 0, 0 },
34935
    { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
34936
    & ifmt_movhh32_src_r0l_dst32_24_24_An_relative_Prefixed_QI, { 0x1b62e00 }
34937
  },
34938
/* movhl r0l,${Dsp-24-u8}[sb] */
34939
  {
34940
    { 0, 0, 0, 0 },
34941
    { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
34942
    & ifmt_movhh32_src_r0l_dst32_24_8_SB_relative_Prefixed_QI, { 0x1b2ae00 }
34943
  },
34944
/* movhl r0l,${Dsp-24-u16}[sb] */
34945
  {
34946
    { 0, 0, 0, 0 },
34947
    { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
34948
    & ifmt_movhh32_src_r0l_dst32_24_16_SB_relative_Prefixed_QI, { 0x1b4ae00 }
34949
  },
34950
/* movhl r0l,${Dsp-24-s8}[fb] */
34951
  {
34952
    { 0, 0, 0, 0 },
34953
    { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
34954
    & ifmt_movhh32_src_r0l_dst32_24_8_FB_relative_Prefixed_QI, { 0x1b2ee00 }
34955
  },
34956
/* movhl r0l,${Dsp-24-s16}[fb] */
34957
  {
34958
    { 0, 0, 0, 0 },
34959
    { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
34960
    & ifmt_movhh32_src_r0l_dst32_24_16_FB_relative_Prefixed_QI, { 0x1b4ee00 }
34961
  },
34962
/* movhl r0l,${Dsp-24-u16} */
34963
  {
34964
    { 0, 0, 0, 0 },
34965
    { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U16), 0 } },
34966
    & ifmt_movhh32_src_r0l_dst32_24_16_absolute_Prefixed_QI, { 0x1b6ee00 }
34967
  },
34968
/* movhl r0l,${Dsp-24-u24} */
34969
  {
34970
    { 0, 0, 0, 0 },
34971
    { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U24), 0 } },
34972
    & ifmt_movhh32_src_r0l_dst32_24_24_absolute_Prefixed_QI, { 0x1b6ae00 }
34973
  },
34974
/* movlh r0l,$Dst32RnPrefixedQI */
34975
  {
34976
    { 0, 0, 0, 0 },
34977
    { { MNEM, ' ', 'r', '0', 'l', ',', OP (DST32RNPREFIXEDQI), 0 } },
34978
    & ifmt_movhh32_src_r0l_dst32_Rn_direct_Prefixed_QI, { 0x1b81e }
34979
  },
34980
/* movlh r0l,$Dst32AnPrefixedQI */
34981
  {
34982
    { 0, 0, 0, 0 },
34983
    { { MNEM, ' ', 'r', '0', 'l', ',', OP (DST32ANPREFIXEDQI), 0 } },
34984
    & ifmt_movhh32_src_r0l_dst32_An_direct_Prefixed_QI, { 0x1b09e }
34985
  },
34986
/* movlh r0l,[$Dst32AnPrefixed] */
34987
  {
34988
    { 0, 0, 0, 0 },
34989
    { { MNEM, ' ', 'r', '0', 'l', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
34990
    & ifmt_movhh32_src_r0l_dst32_An_indirect_Prefixed_QI, { 0x1b01e }
34991
  },
34992
/* movlh r0l,${Dsp-24-u8}[$Dst32AnPrefixed] */
34993
  {
34994
    { 0, 0, 0, 0 },
34995
    { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
34996
    & ifmt_movhh32_src_r0l_dst32_24_8_An_relative_Prefixed_QI, { 0x1b21e00 }
34997
  },
34998
/* movlh r0l,${Dsp-24-u16}[$Dst32AnPrefixed] */
34999
  {
35000
    { 0, 0, 0, 0 },
35001
    { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
35002
    & ifmt_movhh32_src_r0l_dst32_24_16_An_relative_Prefixed_QI, { 0x1b41e00 }
35003
  },
35004
/* movlh r0l,${Dsp-24-u24}[$Dst32AnPrefixed] */
35005
  {
35006
    { 0, 0, 0, 0 },
35007
    { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
35008
    & ifmt_movhh32_src_r0l_dst32_24_24_An_relative_Prefixed_QI, { 0x1b61e00 }
35009
  },
35010
/* movlh r0l,${Dsp-24-u8}[sb] */
35011
  {
35012
    { 0, 0, 0, 0 },
35013
    { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
35014
    & ifmt_movhh32_src_r0l_dst32_24_8_SB_relative_Prefixed_QI, { 0x1b29e00 }
35015
  },
35016
/* movlh r0l,${Dsp-24-u16}[sb] */
35017
  {
35018
    { 0, 0, 0, 0 },
35019
    { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
35020
    & ifmt_movhh32_src_r0l_dst32_24_16_SB_relative_Prefixed_QI, { 0x1b49e00 }
35021
  },
35022
/* movlh r0l,${Dsp-24-s8}[fb] */
35023
  {
35024
    { 0, 0, 0, 0 },
35025
    { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
35026
    & ifmt_movhh32_src_r0l_dst32_24_8_FB_relative_Prefixed_QI, { 0x1b2de00 }
35027
  },
35028
/* movlh r0l,${Dsp-24-s16}[fb] */
35029
  {
35030
    { 0, 0, 0, 0 },
35031
    { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
35032
    & ifmt_movhh32_src_r0l_dst32_24_16_FB_relative_Prefixed_QI, { 0x1b4de00 }
35033
  },
35034
/* movlh r0l,${Dsp-24-u16} */
35035
  {
35036
    { 0, 0, 0, 0 },
35037
    { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U16), 0 } },
35038
    & ifmt_movhh32_src_r0l_dst32_24_16_absolute_Prefixed_QI, { 0x1b6de00 }
35039
  },
35040
/* movlh r0l,${Dsp-24-u24} */
35041
  {
35042
    { 0, 0, 0, 0 },
35043
    { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U24), 0 } },
35044
    & ifmt_movhh32_src_r0l_dst32_24_24_absolute_Prefixed_QI, { 0x1b69e00 }
35045
  },
35046
/* movll r0l,$Dst32RnPrefixedQI */
35047
  {
35048
    { 0, 0, 0, 0 },
35049
    { { MNEM, ' ', 'r', '0', 'l', ',', OP (DST32RNPREFIXEDQI), 0 } },
35050
    & ifmt_movhh32_src_r0l_dst32_Rn_direct_Prefixed_QI, { 0x1b80e }
35051
  },
35052
/* movll r0l,$Dst32AnPrefixedQI */
35053
  {
35054
    { 0, 0, 0, 0 },
35055
    { { MNEM, ' ', 'r', '0', 'l', ',', OP (DST32ANPREFIXEDQI), 0 } },
35056
    & ifmt_movhh32_src_r0l_dst32_An_direct_Prefixed_QI, { 0x1b08e }
35057
  },
35058
/* movll r0l,[$Dst32AnPrefixed] */
35059
  {
35060
    { 0, 0, 0, 0 },
35061
    { { MNEM, ' ', 'r', '0', 'l', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
35062
    & ifmt_movhh32_src_r0l_dst32_An_indirect_Prefixed_QI, { 0x1b00e }
35063
  },
35064
/* movll r0l,${Dsp-24-u8}[$Dst32AnPrefixed] */
35065
  {
35066
    { 0, 0, 0, 0 },
35067
    { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
35068
    & ifmt_movhh32_src_r0l_dst32_24_8_An_relative_Prefixed_QI, { 0x1b20e00 }
35069
  },
35070
/* movll r0l,${Dsp-24-u16}[$Dst32AnPrefixed] */
35071
  {
35072
    { 0, 0, 0, 0 },
35073
    { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
35074
    & ifmt_movhh32_src_r0l_dst32_24_16_An_relative_Prefixed_QI, { 0x1b40e00 }
35075
  },
35076
/* movll r0l,${Dsp-24-u24}[$Dst32AnPrefixed] */
35077
  {
35078
    { 0, 0, 0, 0 },
35079
    { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
35080
    & ifmt_movhh32_src_r0l_dst32_24_24_An_relative_Prefixed_QI, { 0x1b60e00 }
35081
  },
35082
/* movll r0l,${Dsp-24-u8}[sb] */
35083
  {
35084
    { 0, 0, 0, 0 },
35085
    { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
35086
    & ifmt_movhh32_src_r0l_dst32_24_8_SB_relative_Prefixed_QI, { 0x1b28e00 }
35087
  },
35088
/* movll r0l,${Dsp-24-u16}[sb] */
35089
  {
35090
    { 0, 0, 0, 0 },
35091
    { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
35092
    & ifmt_movhh32_src_r0l_dst32_24_16_SB_relative_Prefixed_QI, { 0x1b48e00 }
35093
  },
35094
/* movll r0l,${Dsp-24-s8}[fb] */
35095
  {
35096
    { 0, 0, 0, 0 },
35097
    { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
35098
    & ifmt_movhh32_src_r0l_dst32_24_8_FB_relative_Prefixed_QI, { 0x1b2ce00 }
35099
  },
35100
/* movll r0l,${Dsp-24-s16}[fb] */
35101
  {
35102
    { 0, 0, 0, 0 },
35103
    { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
35104
    & ifmt_movhh32_src_r0l_dst32_24_16_FB_relative_Prefixed_QI, { 0x1b4ce00 }
35105
  },
35106
/* movll r0l,${Dsp-24-u16} */
35107
  {
35108
    { 0, 0, 0, 0 },
35109
    { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U16), 0 } },
35110
    & ifmt_movhh32_src_r0l_dst32_24_16_absolute_Prefixed_QI, { 0x1b6ce00 }
35111
  },
35112
/* movll r0l,${Dsp-24-u24} */
35113
  {
35114
    { 0, 0, 0, 0 },
35115
    { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U24), 0 } },
35116
    & ifmt_movhh32_src_r0l_dst32_24_24_absolute_Prefixed_QI, { 0x1b68e00 }
35117
  },
35118
/* movhh $Dst16RnQI,r0l */
35119
  {
35120
    { 0, 0, 0, 0 },
35121
    { { MNEM, ' ', OP (DST16RNQI), ',', 'r', '0', 'l', 0 } },
35122
    & ifmt_shl16_b_dst_dst16_Rn_direct_QI, { 0x7c30 }
35123
  },
35124
/* movhh $Dst16AnQI,r0l */
35125
  {
35126
    { 0, 0, 0, 0 },
35127
    { { MNEM, ' ', OP (DST16ANQI), ',', 'r', '0', 'l', 0 } },
35128
    & ifmt_shl16_b_dst_dst16_An_direct_QI, { 0x7c34 }
35129
  },
35130
/* movhh [$Dst16An],r0l */
35131
  {
35132
    { 0, 0, 0, 0 },
35133
    { { MNEM, ' ', '[', OP (DST16AN), ']', ',', 'r', '0', 'l', 0 } },
35134
    & ifmt_shl16_b_dst_dst16_An_indirect_QI, { 0x7c36 }
35135
  },
35136
/* movhh ${Dsp-16-u8}[$Dst16An],r0l */
35137
  {
35138
    { 0, 0, 0, 0 },
35139
    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', 'r', '0', 'l', 0 } },
35140
    & ifmt_shl16_b_dst_dst16_16_8_An_relative_QI, { 0x7c3800 }
35141
  },
35142
/* movhh ${Dsp-16-u16}[$Dst16An],r0l */
35143
  {
35144
    { 0, 0, 0, 0 },
35145
    { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', 'r', '0', 'l', 0 } },
35146
    & ifmt_shl16_b_dst_dst16_16_16_An_relative_QI, { 0x7c3c0000 }
35147
  },
35148
/* movhh ${Dsp-16-u8}[sb],r0l */
35149
  {
35150
    { 0, 0, 0, 0 },
35151
    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', 'r', '0', 'l', 0 } },
35152
    & ifmt_shl16_b_dst_dst16_16_8_SB_relative_QI, { 0x7c3a00 }
35153
  },
35154
/* movhh ${Dsp-16-u16}[sb],r0l */
35155
  {
35156
    { 0, 0, 0, 0 },
35157
    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', 'r', '0', 'l', 0 } },
35158
    & ifmt_shl16_b_dst_dst16_16_16_SB_relative_QI, { 0x7c3e0000 }
35159
  },
35160
/* movhh ${Dsp-16-s8}[fb],r0l */
35161
  {
35162
    { 0, 0, 0, 0 },
35163
    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', 'r', '0', 'l', 0 } },
35164
    & ifmt_shl16_b_dst_dst16_16_8_FB_relative_QI, { 0x7c3b00 }
35165
  },
35166
/* movhh ${Dsp-16-u16},r0l */
35167
  {
35168
    { 0, 0, 0, 0 },
35169
    { { MNEM, ' ', OP (DSP_16_U16), ',', 'r', '0', 'l', 0 } },
35170
    & ifmt_shl16_b_dst_dst16_16_16_absolute_QI, { 0x7c3f0000 }
35171
  },
35172
/* movhl $Dst16RnQI,r0l */
35173
  {
35174
    { 0, 0, 0, 0 },
35175
    { { MNEM, ' ', OP (DST16RNQI), ',', 'r', '0', 'l', 0 } },
35176
    & ifmt_shl16_b_dst_dst16_Rn_direct_QI, { 0x7c10 }
35177
  },
35178
/* movhl $Dst16AnQI,r0l */
35179
  {
35180
    { 0, 0, 0, 0 },
35181
    { { MNEM, ' ', OP (DST16ANQI), ',', 'r', '0', 'l', 0 } },
35182
    & ifmt_shl16_b_dst_dst16_An_direct_QI, { 0x7c14 }
35183
  },
35184
/* movhl [$Dst16An],r0l */
35185
  {
35186
    { 0, 0, 0, 0 },
35187
    { { MNEM, ' ', '[', OP (DST16AN), ']', ',', 'r', '0', 'l', 0 } },
35188
    & ifmt_shl16_b_dst_dst16_An_indirect_QI, { 0x7c16 }
35189
  },
35190
/* movhl ${Dsp-16-u8}[$Dst16An],r0l */
35191
  {
35192
    { 0, 0, 0, 0 },
35193
    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', 'r', '0', 'l', 0 } },
35194
    & ifmt_shl16_b_dst_dst16_16_8_An_relative_QI, { 0x7c1800 }
35195
  },
35196
/* movhl ${Dsp-16-u16}[$Dst16An],r0l */
35197
  {
35198
    { 0, 0, 0, 0 },
35199
    { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', 'r', '0', 'l', 0 } },
35200
    & ifmt_shl16_b_dst_dst16_16_16_An_relative_QI, { 0x7c1c0000 }
35201
  },
35202
/* movhl ${Dsp-16-u8}[sb],r0l */
35203
  {
35204
    { 0, 0, 0, 0 },
35205
    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', 'r', '0', 'l', 0 } },
35206
    & ifmt_shl16_b_dst_dst16_16_8_SB_relative_QI, { 0x7c1a00 }
35207
  },
35208
/* movhl ${Dsp-16-u16}[sb],r0l */
35209
  {
35210
    { 0, 0, 0, 0 },
35211
    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', 'r', '0', 'l', 0 } },
35212
    & ifmt_shl16_b_dst_dst16_16_16_SB_relative_QI, { 0x7c1e0000 }
35213
  },
35214
/* movhl ${Dsp-16-s8}[fb],r0l */
35215
  {
35216
    { 0, 0, 0, 0 },
35217
    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', 'r', '0', 'l', 0 } },
35218
    & ifmt_shl16_b_dst_dst16_16_8_FB_relative_QI, { 0x7c1b00 }
35219
  },
35220
/* movhl ${Dsp-16-u16},r0l */
35221
  {
35222
    { 0, 0, 0, 0 },
35223
    { { MNEM, ' ', OP (DSP_16_U16), ',', 'r', '0', 'l', 0 } },
35224
    & ifmt_shl16_b_dst_dst16_16_16_absolute_QI, { 0x7c1f0000 }
35225
  },
35226
/* movlh $Dst16RnQI,r0l */
35227
  {
35228
    { 0, 0, 0, 0 },
35229
    { { MNEM, ' ', OP (DST16RNQI), ',', 'r', '0', 'l', 0 } },
35230
    & ifmt_shl16_b_dst_dst16_Rn_direct_QI, { 0x7c20 }
35231
  },
35232
/* movlh $Dst16AnQI,r0l */
35233
  {
35234
    { 0, 0, 0, 0 },
35235
    { { MNEM, ' ', OP (DST16ANQI), ',', 'r', '0', 'l', 0 } },
35236
    & ifmt_shl16_b_dst_dst16_An_direct_QI, { 0x7c24 }
35237
  },
35238
/* movlh [$Dst16An],r0l */
35239
  {
35240
    { 0, 0, 0, 0 },
35241
    { { MNEM, ' ', '[', OP (DST16AN), ']', ',', 'r', '0', 'l', 0 } },
35242
    & ifmt_shl16_b_dst_dst16_An_indirect_QI, { 0x7c26 }
35243
  },
35244
/* movlh ${Dsp-16-u8}[$Dst16An],r0l */
35245
  {
35246
    { 0, 0, 0, 0 },
35247
    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', 'r', '0', 'l', 0 } },
35248
    & ifmt_shl16_b_dst_dst16_16_8_An_relative_QI, { 0x7c2800 }
35249
  },
35250
/* movlh ${Dsp-16-u16}[$Dst16An],r0l */
35251
  {
35252
    { 0, 0, 0, 0 },
35253
    { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', 'r', '0', 'l', 0 } },
35254
    & ifmt_shl16_b_dst_dst16_16_16_An_relative_QI, { 0x7c2c0000 }
35255
  },
35256
/* movlh ${Dsp-16-u8}[sb],r0l */
35257
  {
35258
    { 0, 0, 0, 0 },
35259
    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', 'r', '0', 'l', 0 } },
35260
    & ifmt_shl16_b_dst_dst16_16_8_SB_relative_QI, { 0x7c2a00 }
35261
  },
35262
/* movlh ${Dsp-16-u16}[sb],r0l */
35263
  {
35264
    { 0, 0, 0, 0 },
35265
    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', 'r', '0', 'l', 0 } },
35266
    & ifmt_shl16_b_dst_dst16_16_16_SB_relative_QI, { 0x7c2e0000 }
35267
  },
35268
/* movlh ${Dsp-16-s8}[fb],r0l */
35269
  {
35270
    { 0, 0, 0, 0 },
35271
    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', 'r', '0', 'l', 0 } },
35272
    & ifmt_shl16_b_dst_dst16_16_8_FB_relative_QI, { 0x7c2b00 }
35273
  },
35274
/* movlh ${Dsp-16-u16},r0l */
35275
  {
35276
    { 0, 0, 0, 0 },
35277
    { { MNEM, ' ', OP (DSP_16_U16), ',', 'r', '0', 'l', 0 } },
35278
    & ifmt_shl16_b_dst_dst16_16_16_absolute_QI, { 0x7c2f0000 }
35279
  },
35280
/* movll $Dst16RnQI,r0l */
35281
  {
35282
    { 0, 0, 0, 0 },
35283
    { { MNEM, ' ', OP (DST16RNQI), ',', 'r', '0', 'l', 0 } },
35284
    & ifmt_shl16_b_dst_dst16_Rn_direct_QI, { 0x7c00 }
35285
  },
35286
/* movll $Dst16AnQI,r0l */
35287
  {
35288
    { 0, 0, 0, 0 },
35289
    { { MNEM, ' ', OP (DST16ANQI), ',', 'r', '0', 'l', 0 } },
35290
    & ifmt_shl16_b_dst_dst16_An_direct_QI, { 0x7c04 }
35291
  },
35292
/* movll [$Dst16An],r0l */
35293
  {
35294
    { 0, 0, 0, 0 },
35295
    { { MNEM, ' ', '[', OP (DST16AN), ']', ',', 'r', '0', 'l', 0 } },
35296
    & ifmt_shl16_b_dst_dst16_An_indirect_QI, { 0x7c06 }
35297
  },
35298
/* movll ${Dsp-16-u8}[$Dst16An],r0l */
35299
  {
35300
    { 0, 0, 0, 0 },
35301
    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', 'r', '0', 'l', 0 } },
35302
    & ifmt_shl16_b_dst_dst16_16_8_An_relative_QI, { 0x7c0800 }
35303
  },
35304
/* movll ${Dsp-16-u16}[$Dst16An],r0l */
35305
  {
35306
    { 0, 0, 0, 0 },
35307
    { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', 'r', '0', 'l', 0 } },
35308
    & ifmt_shl16_b_dst_dst16_16_16_An_relative_QI, { 0x7c0c0000 }
35309
  },
35310
/* movll ${Dsp-16-u8}[sb],r0l */
35311
  {
35312
    { 0, 0, 0, 0 },
35313
    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', 'r', '0', 'l', 0 } },
35314
    & ifmt_shl16_b_dst_dst16_16_8_SB_relative_QI, { 0x7c0a00 }
35315
  },
35316
/* movll ${Dsp-16-u16}[sb],r0l */
35317
  {
35318
    { 0, 0, 0, 0 },
35319
    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', 'r', '0', 'l', 0 } },
35320
    & ifmt_shl16_b_dst_dst16_16_16_SB_relative_QI, { 0x7c0e0000 }
35321
  },
35322
/* movll ${Dsp-16-s8}[fb],r0l */
35323
  {
35324
    { 0, 0, 0, 0 },
35325
    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', 'r', '0', 'l', 0 } },
35326
    & ifmt_shl16_b_dst_dst16_16_8_FB_relative_QI, { 0x7c0b00 }
35327
  },
35328
/* movll ${Dsp-16-u16},r0l */
35329
  {
35330
    { 0, 0, 0, 0 },
35331
    { { MNEM, ' ', OP (DSP_16_U16), ',', 'r', '0', 'l', 0 } },
35332
    & ifmt_shl16_b_dst_dst16_16_16_absolute_QI, { 0x7c0f0000 }
35333
  },
35334
/* movhh r0l,$Dst16RnQI */
35335
  {
35336
    { 0, 0, 0, 0 },
35337
    { { MNEM, ' ', 'r', '0', 'l', ',', OP (DST16RNQI), 0 } },
35338
    & ifmt_shl16_b_dst_dst16_Rn_direct_QI, { 0x7cb0 }
35339
  },
35340
/* movhh r0l,$Dst16AnQI */
35341
  {
35342
    { 0, 0, 0, 0 },
35343
    { { MNEM, ' ', 'r', '0', 'l', ',', OP (DST16ANQI), 0 } },
35344
    & ifmt_shl16_b_dst_dst16_An_direct_QI, { 0x7cb4 }
35345
  },
35346
/* movhh r0l,[$Dst16An] */
35347
  {
35348
    { 0, 0, 0, 0 },
35349
    { { MNEM, ' ', 'r', '0', 'l', ',', '[', OP (DST16AN), ']', 0 } },
35350
    & ifmt_shl16_b_dst_dst16_An_indirect_QI, { 0x7cb6 }
35351
  },
35352
/* movhh r0l,${Dsp-16-u8}[$Dst16An] */
35353
  {
35354
    { 0, 0, 0, 0 },
35355
    { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
35356
    & ifmt_shl16_b_dst_dst16_16_8_An_relative_QI, { 0x7cb800 }
35357
  },
35358
/* movhh r0l,${Dsp-16-u16}[$Dst16An] */
35359
  {
35360
    { 0, 0, 0, 0 },
35361
    { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
35362
    & ifmt_shl16_b_dst_dst16_16_16_An_relative_QI, { 0x7cbc0000 }
35363
  },
35364
/* movhh r0l,${Dsp-16-u8}[sb] */
35365
  {
35366
    { 0, 0, 0, 0 },
35367
    { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
35368
    & ifmt_shl16_b_dst_dst16_16_8_SB_relative_QI, { 0x7cba00 }
35369
  },
35370
/* movhh r0l,${Dsp-16-u16}[sb] */
35371
  {
35372
    { 0, 0, 0, 0 },
35373
    { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
35374
    & ifmt_shl16_b_dst_dst16_16_16_SB_relative_QI, { 0x7cbe0000 }
35375
  },
35376
/* movhh r0l,${Dsp-16-s8}[fb] */
35377
  {
35378
    { 0, 0, 0, 0 },
35379
    { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
35380
    & ifmt_shl16_b_dst_dst16_16_8_FB_relative_QI, { 0x7cbb00 }
35381
  },
35382
/* movhh r0l,${Dsp-16-u16} */
35383
  {
35384
    { 0, 0, 0, 0 },
35385
    { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U16), 0 } },
35386
    & ifmt_shl16_b_dst_dst16_16_16_absolute_QI, { 0x7cbf0000 }
35387
  },
35388
/* movhl r0l,$Dst16RnQI */
35389
  {
35390
    { 0, 0, 0, 0 },
35391
    { { MNEM, ' ', 'r', '0', 'l', ',', OP (DST16RNQI), 0 } },
35392
    & ifmt_shl16_b_dst_dst16_Rn_direct_QI, { 0x7c90 }
35393
  },
35394
/* movhl r0l,$Dst16AnQI */
35395
  {
35396
    { 0, 0, 0, 0 },
35397
    { { MNEM, ' ', 'r', '0', 'l', ',', OP (DST16ANQI), 0 } },
35398
    & ifmt_shl16_b_dst_dst16_An_direct_QI, { 0x7c94 }
35399
  },
35400
/* movhl r0l,[$Dst16An] */
35401
  {
35402
    { 0, 0, 0, 0 },
35403
    { { MNEM, ' ', 'r', '0', 'l', ',', '[', OP (DST16AN), ']', 0 } },
35404
    & ifmt_shl16_b_dst_dst16_An_indirect_QI, { 0x7c96 }
35405
  },
35406
/* movhl r0l,${Dsp-16-u8}[$Dst16An] */
35407
  {
35408
    { 0, 0, 0, 0 },
35409
    { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
35410
    & ifmt_shl16_b_dst_dst16_16_8_An_relative_QI, { 0x7c9800 }
35411
  },
35412
/* movhl r0l,${Dsp-16-u16}[$Dst16An] */
35413
  {
35414
    { 0, 0, 0, 0 },
35415
    { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
35416
    & ifmt_shl16_b_dst_dst16_16_16_An_relative_QI, { 0x7c9c0000 }
35417
  },
35418
/* movhl r0l,${Dsp-16-u8}[sb] */
35419
  {
35420
    { 0, 0, 0, 0 },
35421
    { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
35422
    & ifmt_shl16_b_dst_dst16_16_8_SB_relative_QI, { 0x7c9a00 }
35423
  },
35424
/* movhl r0l,${Dsp-16-u16}[sb] */
35425
  {
35426
    { 0, 0, 0, 0 },
35427
    { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
35428
    & ifmt_shl16_b_dst_dst16_16_16_SB_relative_QI, { 0x7c9e0000 }
35429
  },
35430
/* movhl r0l,${Dsp-16-s8}[fb] */
35431
  {
35432
    { 0, 0, 0, 0 },
35433
    { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
35434
    & ifmt_shl16_b_dst_dst16_16_8_FB_relative_QI, { 0x7c9b00 }
35435
  },
35436
/* movhl r0l,${Dsp-16-u16} */
35437
  {
35438
    { 0, 0, 0, 0 },
35439
    { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U16), 0 } },
35440
    & ifmt_shl16_b_dst_dst16_16_16_absolute_QI, { 0x7c9f0000 }
35441
  },
35442
/* movlh r0l,$Dst16RnQI */
35443
  {
35444
    { 0, 0, 0, 0 },
35445
    { { MNEM, ' ', 'r', '0', 'l', ',', OP (DST16RNQI), 0 } },
35446
    & ifmt_shl16_b_dst_dst16_Rn_direct_QI, { 0x7ca0 }
35447
  },
35448
/* movlh r0l,$Dst16AnQI */
35449
  {
35450
    { 0, 0, 0, 0 },
35451
    { { MNEM, ' ', 'r', '0', 'l', ',', OP (DST16ANQI), 0 } },
35452
    & ifmt_shl16_b_dst_dst16_An_direct_QI, { 0x7ca4 }
35453
  },
35454
/* movlh r0l,[$Dst16An] */
35455
  {
35456
    { 0, 0, 0, 0 },
35457
    { { MNEM, ' ', 'r', '0', 'l', ',', '[', OP (DST16AN), ']', 0 } },
35458
    & ifmt_shl16_b_dst_dst16_An_indirect_QI, { 0x7ca6 }
35459
  },
35460
/* movlh r0l,${Dsp-16-u8}[$Dst16An] */
35461
  {
35462
    { 0, 0, 0, 0 },
35463
    { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
35464
    & ifmt_shl16_b_dst_dst16_16_8_An_relative_QI, { 0x7ca800 }
35465
  },
35466
/* movlh r0l,${Dsp-16-u16}[$Dst16An] */
35467
  {
35468
    { 0, 0, 0, 0 },
35469
    { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
35470
    & ifmt_shl16_b_dst_dst16_16_16_An_relative_QI, { 0x7cac0000 }
35471
  },
35472
/* movlh r0l,${Dsp-16-u8}[sb] */
35473
  {
35474
    { 0, 0, 0, 0 },
35475
    { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
35476
    & ifmt_shl16_b_dst_dst16_16_8_SB_relative_QI, { 0x7caa00 }
35477
  },
35478
/* movlh r0l,${Dsp-16-u16}[sb] */
35479
  {
35480
    { 0, 0, 0, 0 },
35481
    { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
35482
    & ifmt_shl16_b_dst_dst16_16_16_SB_relative_QI, { 0x7cae0000 }
35483
  },
35484
/* movlh r0l,${Dsp-16-s8}[fb] */
35485
  {
35486
    { 0, 0, 0, 0 },
35487
    { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
35488
    & ifmt_shl16_b_dst_dst16_16_8_FB_relative_QI, { 0x7cab00 }
35489
  },
35490
/* movlh r0l,${Dsp-16-u16} */
35491
  {
35492
    { 0, 0, 0, 0 },
35493
    { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U16), 0 } },
35494
    & ifmt_shl16_b_dst_dst16_16_16_absolute_QI, { 0x7caf0000 }
35495
  },
35496
/* movll r0l,$Dst16RnQI */
35497
  {
35498
    { 0, 0, 0, 0 },
35499
    { { MNEM, ' ', 'r', '0', 'l', ',', OP (DST16RNQI), 0 } },
35500
    & ifmt_shl16_b_dst_dst16_Rn_direct_QI, { 0x7c80 }
35501
  },
35502
/* movll r0l,$Dst16AnQI */
35503
  {
35504
    { 0, 0, 0, 0 },
35505
    { { MNEM, ' ', 'r', '0', 'l', ',', OP (DST16ANQI), 0 } },
35506
    & ifmt_shl16_b_dst_dst16_An_direct_QI, { 0x7c84 }
35507
  },
35508
/* movll r0l,[$Dst16An] */
35509
  {
35510
    { 0, 0, 0, 0 },
35511
    { { MNEM, ' ', 'r', '0', 'l', ',', '[', OP (DST16AN), ']', 0 } },
35512
    & ifmt_shl16_b_dst_dst16_An_indirect_QI, { 0x7c86 }
35513
  },
35514
/* movll r0l,${Dsp-16-u8}[$Dst16An] */
35515
  {
35516
    { 0, 0, 0, 0 },
35517
    { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
35518
    & ifmt_shl16_b_dst_dst16_16_8_An_relative_QI, { 0x7c8800 }
35519
  },
35520
/* movll r0l,${Dsp-16-u16}[$Dst16An] */
35521
  {
35522
    { 0, 0, 0, 0 },
35523
    { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
35524
    & ifmt_shl16_b_dst_dst16_16_16_An_relative_QI, { 0x7c8c0000 }
35525
  },
35526
/* movll r0l,${Dsp-16-u8}[sb] */
35527
  {
35528
    { 0, 0, 0, 0 },
35529
    { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
35530
    & ifmt_shl16_b_dst_dst16_16_8_SB_relative_QI, { 0x7c8a00 }
35531
  },
35532
/* movll r0l,${Dsp-16-u16}[sb] */
35533
  {
35534
    { 0, 0, 0, 0 },
35535
    { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
35536
    & ifmt_shl16_b_dst_dst16_16_16_SB_relative_QI, { 0x7c8e0000 }
35537
  },
35538
/* movll r0l,${Dsp-16-s8}[fb] */
35539
  {
35540
    { 0, 0, 0, 0 },
35541
    { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
35542
    & ifmt_shl16_b_dst_dst16_16_8_FB_relative_QI, { 0x7c8b00 }
35543
  },
35544
/* movll r0l,${Dsp-16-u16} */
35545
  {
35546
    { 0, 0, 0, 0 },
35547
    { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U16), 0 } },
35548
    & ifmt_shl16_b_dst_dst16_16_16_absolute_QI, { 0x7c8f0000 }
35549
  },
35550
/* mova [$Dst32AnUnprefixed],a1 */
35551
  {
35552
    { 0, 0, 0, 0 },
35553
    { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', ',', 'a', '1', 0 } },
35554
    & ifmt_mova32_src_a1_dst32_An_indirect_Unprefixed_Mova_SI, { 0xd11b }
35555
  },
35556
/* mova ${Dsp-16-u8}[$Dst32AnUnprefixed],a1 */
35557
  {
35558
    { 0, 0, 0, 0 },
35559
    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', ',', 'a', '1', 0 } },
35560
    & ifmt_mova32_src_a1_dst32_16_8_An_relative_Unprefixed_Mova_SI, { 0xd31b00 }
35561
  },
35562
/* mova ${Dsp-16-u16}[$Dst32AnUnprefixed],a1 */
35563
  {
35564
    { 0, 0, 0, 0 },
35565
    { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', ',', 'a', '1', 0 } },
35566
    & ifmt_mova32_src_a1_dst32_16_16_An_relative_Unprefixed_Mova_SI, { 0xd51b0000 }
35567
  },
35568
/* mova ${Dsp-16-u24}[$Dst32AnUnprefixed],a1 */
35569
  {
35570
    { 0, 0, 0, 0 },
35571
    { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', ',', 'a', '1', 0 } },
35572
    & ifmt_mova32_src_a1_dst32_16_24_An_relative_Unprefixed_Mova_SI, { 0xd71b0000 }
35573
  },
35574
/* mova ${Dsp-16-u8}[sb],a1 */
35575
  {
35576
    { 0, 0, 0, 0 },
35577
    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', 'a', '1', 0 } },
35578
    & ifmt_mova32_src_a1_dst32_16_8_SB_relative_Unprefixed_Mova_SI, { 0xd39b00 }
35579
  },
35580
/* mova ${Dsp-16-u16}[sb],a1 */
35581
  {
35582
    { 0, 0, 0, 0 },
35583
    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', 'a', '1', 0 } },
35584
    & ifmt_mova32_src_a1_dst32_16_16_SB_relative_Unprefixed_Mova_SI, { 0xd59b0000 }
35585
  },
35586
/* mova ${Dsp-16-s8}[fb],a1 */
35587
  {
35588
    { 0, 0, 0, 0 },
35589
    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', 'a', '1', 0 } },
35590
    & ifmt_mova32_src_a1_dst32_16_8_FB_relative_Unprefixed_Mova_SI, { 0xd3db00 }
35591
  },
35592
/* mova ${Dsp-16-s16}[fb],a1 */
35593
  {
35594
    { 0, 0, 0, 0 },
35595
    { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', 'a', '1', 0 } },
35596
    & ifmt_mova32_src_a1_dst32_16_16_FB_relative_Unprefixed_Mova_SI, { 0xd5db0000 }
35597
  },
35598
/* mova ${Dsp-16-u16},a1 */
35599
  {
35600
    { 0, 0, 0, 0 },
35601
    { { MNEM, ' ', OP (DSP_16_U16), ',', 'a', '1', 0 } },
35602
    & ifmt_mova32_src_a1_dst32_16_16_absolute_Unprefixed_Mova_SI, { 0xd7db0000 }
35603
  },
35604
/* mova ${Dsp-16-u24},a1 */
35605
  {
35606
    { 0, 0, 0, 0 },
35607
    { { MNEM, ' ', OP (DSP_16_U24), ',', 'a', '1', 0 } },
35608
    & ifmt_mova32_src_a1_dst32_16_24_absolute_Unprefixed_Mova_SI, { 0xd79b0000 }
35609
  },
35610
/* mova [$Dst32AnUnprefixed],a0 */
35611
  {
35612
    { 0, 0, 0, 0 },
35613
    { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', ',', 'a', '0', 0 } },
35614
    & ifmt_mova32_src_a1_dst32_An_indirect_Unprefixed_Mova_SI, { 0xd11a }
35615
  },
35616
/* mova ${Dsp-16-u8}[$Dst32AnUnprefixed],a0 */
35617
  {
35618
    { 0, 0, 0, 0 },
35619
    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', ',', 'a', '0', 0 } },
35620
    & ifmt_mova32_src_a1_dst32_16_8_An_relative_Unprefixed_Mova_SI, { 0xd31a00 }
35621
  },
35622
/* mova ${Dsp-16-u16}[$Dst32AnUnprefixed],a0 */
35623
  {
35624
    { 0, 0, 0, 0 },
35625
    { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', ',', 'a', '0', 0 } },
35626
    & ifmt_mova32_src_a1_dst32_16_16_An_relative_Unprefixed_Mova_SI, { 0xd51a0000 }
35627
  },
35628
/* mova ${Dsp-16-u24}[$Dst32AnUnprefixed],a0 */
35629
  {
35630
    { 0, 0, 0, 0 },
35631
    { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', ',', 'a', '0', 0 } },
35632
    & ifmt_mova32_src_a1_dst32_16_24_An_relative_Unprefixed_Mova_SI, { 0xd71a0000 }
35633
  },
35634
/* mova ${Dsp-16-u8}[sb],a0 */
35635
  {
35636
    { 0, 0, 0, 0 },
35637
    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', 'a', '0', 0 } },
35638
    & ifmt_mova32_src_a1_dst32_16_8_SB_relative_Unprefixed_Mova_SI, { 0xd39a00 }
35639
  },
35640
/* mova ${Dsp-16-u16}[sb],a0 */
35641
  {
35642
    { 0, 0, 0, 0 },
35643
    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', 'a', '0', 0 } },
35644
    & ifmt_mova32_src_a1_dst32_16_16_SB_relative_Unprefixed_Mova_SI, { 0xd59a0000 }
35645
  },
35646
/* mova ${Dsp-16-s8}[fb],a0 */
35647
  {
35648
    { 0, 0, 0, 0 },
35649
    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', 'a', '0', 0 } },
35650
    & ifmt_mova32_src_a1_dst32_16_8_FB_relative_Unprefixed_Mova_SI, { 0xd3da00 }
35651
  },
35652
/* mova ${Dsp-16-s16}[fb],a0 */
35653
  {
35654
    { 0, 0, 0, 0 },
35655
    { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', 'a', '0', 0 } },
35656
    & ifmt_mova32_src_a1_dst32_16_16_FB_relative_Unprefixed_Mova_SI, { 0xd5da0000 }
35657
  },
35658
/* mova ${Dsp-16-u16},a0 */
35659
  {
35660
    { 0, 0, 0, 0 },
35661
    { { MNEM, ' ', OP (DSP_16_U16), ',', 'a', '0', 0 } },
35662
    & ifmt_mova32_src_a1_dst32_16_16_absolute_Unprefixed_Mova_SI, { 0xd7da0000 }
35663
  },
35664
/* mova ${Dsp-16-u24},a0 */
35665
  {
35666
    { 0, 0, 0, 0 },
35667
    { { MNEM, ' ', OP (DSP_16_U24), ',', 'a', '0', 0 } },
35668
    & ifmt_mova32_src_a1_dst32_16_24_absolute_Unprefixed_Mova_SI, { 0xd79a0000 }
35669
  },
35670
/* mova [$Dst32AnUnprefixed],r3r1 */
35671
  {
35672
    { 0, 0, 0, 0 },
35673
    { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', ',', 'r', '3', 'r', '1', 0 } },
35674
    & ifmt_mova32_src_a1_dst32_An_indirect_Unprefixed_Mova_SI, { 0xd119 }
35675
  },
35676
/* mova ${Dsp-16-u8}[$Dst32AnUnprefixed],r3r1 */
35677
  {
35678
    { 0, 0, 0, 0 },
35679
    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', ',', 'r', '3', 'r', '1', 0 } },
35680
    & ifmt_mova32_src_a1_dst32_16_8_An_relative_Unprefixed_Mova_SI, { 0xd31900 }
35681
  },
35682
/* mova ${Dsp-16-u16}[$Dst32AnUnprefixed],r3r1 */
35683
  {
35684
    { 0, 0, 0, 0 },
35685
    { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', ',', 'r', '3', 'r', '1', 0 } },
35686
    & ifmt_mova32_src_a1_dst32_16_16_An_relative_Unprefixed_Mova_SI, { 0xd5190000 }
35687
  },
35688
/* mova ${Dsp-16-u24}[$Dst32AnUnprefixed],r3r1 */
35689
  {
35690
    { 0, 0, 0, 0 },
35691
    { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', ',', 'r', '3', 'r', '1', 0 } },
35692
    & ifmt_mova32_src_a1_dst32_16_24_An_relative_Unprefixed_Mova_SI, { 0xd7190000 }
35693
  },
35694
/* mova ${Dsp-16-u8}[sb],r3r1 */
35695
  {
35696
    { 0, 0, 0, 0 },
35697
    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', 'r', '3', 'r', '1', 0 } },
35698
    & ifmt_mova32_src_a1_dst32_16_8_SB_relative_Unprefixed_Mova_SI, { 0xd39900 }
35699
  },
35700
/* mova ${Dsp-16-u16}[sb],r3r1 */
35701
  {
35702
    { 0, 0, 0, 0 },
35703
    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', 'r', '3', 'r', '1', 0 } },
35704
    & ifmt_mova32_src_a1_dst32_16_16_SB_relative_Unprefixed_Mova_SI, { 0xd5990000 }
35705
  },
35706
/* mova ${Dsp-16-s8}[fb],r3r1 */
35707
  {
35708
    { 0, 0, 0, 0 },
35709
    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', 'r', '3', 'r', '1', 0 } },
35710
    & ifmt_mova32_src_a1_dst32_16_8_FB_relative_Unprefixed_Mova_SI, { 0xd3d900 }
35711
  },
35712
/* mova ${Dsp-16-s16}[fb],r3r1 */
35713
  {
35714
    { 0, 0, 0, 0 },
35715
    { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', 'r', '3', 'r', '1', 0 } },
35716
    & ifmt_mova32_src_a1_dst32_16_16_FB_relative_Unprefixed_Mova_SI, { 0xd5d90000 }
35717
  },
35718
/* mova ${Dsp-16-u16},r3r1 */
35719
  {
35720
    { 0, 0, 0, 0 },
35721
    { { MNEM, ' ', OP (DSP_16_U16), ',', 'r', '3', 'r', '1', 0 } },
35722
    & ifmt_mova32_src_a1_dst32_16_16_absolute_Unprefixed_Mova_SI, { 0xd7d90000 }
35723
  },
35724
/* mova ${Dsp-16-u24},r3r1 */
35725
  {
35726
    { 0, 0, 0, 0 },
35727
    { { MNEM, ' ', OP (DSP_16_U24), ',', 'r', '3', 'r', '1', 0 } },
35728
    & ifmt_mova32_src_a1_dst32_16_24_absolute_Unprefixed_Mova_SI, { 0xd7990000 }
35729
  },
35730
/* mova [$Dst32AnUnprefixed],r2r0 */
35731
  {
35732
    { 0, 0, 0, 0 },
35733
    { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', ',', 'r', '2', 'r', '0', 0 } },
35734
    & ifmt_mova32_src_a1_dst32_An_indirect_Unprefixed_Mova_SI, { 0xd118 }
35735
  },
35736
/* mova ${Dsp-16-u8}[$Dst32AnUnprefixed],r2r0 */
35737
  {
35738
    { 0, 0, 0, 0 },
35739
    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', ',', 'r', '2', 'r', '0', 0 } },
35740
    & ifmt_mova32_src_a1_dst32_16_8_An_relative_Unprefixed_Mova_SI, { 0xd31800 }
35741
  },
35742
/* mova ${Dsp-16-u16}[$Dst32AnUnprefixed],r2r0 */
35743
  {
35744
    { 0, 0, 0, 0 },
35745
    { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', ',', 'r', '2', 'r', '0', 0 } },
35746
    & ifmt_mova32_src_a1_dst32_16_16_An_relative_Unprefixed_Mova_SI, { 0xd5180000 }
35747
  },
35748
/* mova ${Dsp-16-u24}[$Dst32AnUnprefixed],r2r0 */
35749
  {
35750
    { 0, 0, 0, 0 },
35751
    { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', ',', 'r', '2', 'r', '0', 0 } },
35752
    & ifmt_mova32_src_a1_dst32_16_24_An_relative_Unprefixed_Mova_SI, { 0xd7180000 }
35753
  },
35754
/* mova ${Dsp-16-u8}[sb],r2r0 */
35755
  {
35756
    { 0, 0, 0, 0 },
35757
    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', 'r', '2', 'r', '0', 0 } },
35758
    & ifmt_mova32_src_a1_dst32_16_8_SB_relative_Unprefixed_Mova_SI, { 0xd39800 }
35759
  },
35760
/* mova ${Dsp-16-u16}[sb],r2r0 */
35761
  {
35762
    { 0, 0, 0, 0 },
35763
    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', 'r', '2', 'r', '0', 0 } },
35764
    & ifmt_mova32_src_a1_dst32_16_16_SB_relative_Unprefixed_Mova_SI, { 0xd5980000 }
35765
  },
35766
/* mova ${Dsp-16-s8}[fb],r2r0 */
35767
  {
35768
    { 0, 0, 0, 0 },
35769
    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', 'r', '2', 'r', '0', 0 } },
35770
    & ifmt_mova32_src_a1_dst32_16_8_FB_relative_Unprefixed_Mova_SI, { 0xd3d800 }
35771
  },
35772
/* mova ${Dsp-16-s16}[fb],r2r0 */
35773
  {
35774
    { 0, 0, 0, 0 },
35775
    { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', 'r', '2', 'r', '0', 0 } },
35776
    & ifmt_mova32_src_a1_dst32_16_16_FB_relative_Unprefixed_Mova_SI, { 0xd5d80000 }
35777
  },
35778
/* mova ${Dsp-16-u16},r2r0 */
35779
  {
35780
    { 0, 0, 0, 0 },
35781
    { { MNEM, ' ', OP (DSP_16_U16), ',', 'r', '2', 'r', '0', 0 } },
35782
    & ifmt_mova32_src_a1_dst32_16_16_absolute_Unprefixed_Mova_SI, { 0xd7d80000 }
35783
  },
35784
/* mova ${Dsp-16-u24},r2r0 */
35785
  {
35786
    { 0, 0, 0, 0 },
35787
    { { MNEM, ' ', OP (DSP_16_U24), ',', 'r', '2', 'r', '0', 0 } },
35788
    & ifmt_mova32_src_a1_dst32_16_24_absolute_Unprefixed_Mova_SI, { 0xd7980000 }
35789
  },
35790
/* mova [$Dst16An],a1 */
35791
  {
35792
    { 0, 0, 0, 0 },
35793
    { { MNEM, ' ', '[', OP (DST16AN), ']', ',', 'a', '1', 0 } },
35794
    & ifmt_pusha16_16_Mova_dst16_An_indirect_Mova_HI, { 0xeb56 }
35795
  },
35796
/* mova ${Dsp-16-u8}[$Dst16An],a1 */
35797
  {
35798
    { 0, 0, 0, 0 },
35799
    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', 'a', '1', 0 } },
35800
    & ifmt_pusha16_16_Mova_dst16_16_8_An_relative_Mova_HI, { 0xeb5800 }
35801
  },
35802
/* mova ${Dsp-16-u16}[$Dst16An],a1 */
35803
  {
35804
    { 0, 0, 0, 0 },
35805
    { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', 'a', '1', 0 } },
35806
    & ifmt_pusha16_16_Mova_dst16_16_16_An_relative_Mova_HI, { 0xeb5c0000 }
35807
  },
35808
/* mova ${Dsp-16-u8}[sb],a1 */
35809
  {
35810
    { 0, 0, 0, 0 },
35811
    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', 'a', '1', 0 } },
35812
    & ifmt_pusha16_16_Mova_dst16_16_8_SB_relative_Mova_HI, { 0xeb5a00 }
35813
  },
35814
/* mova ${Dsp-16-u16}[sb],a1 */
35815
  {
35816
    { 0, 0, 0, 0 },
35817
    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', 'a', '1', 0 } },
35818
    & ifmt_pusha16_16_Mova_dst16_16_16_SB_relative_Mova_HI, { 0xeb5e0000 }
35819
  },
35820
/* mova ${Dsp-16-s8}[fb],a1 */
35821
  {
35822
    { 0, 0, 0, 0 },
35823
    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', 'a', '1', 0 } },
35824
    & ifmt_pusha16_16_Mova_dst16_16_8_FB_relative_Mova_HI, { 0xeb5b00 }
35825
  },
35826
/* mova ${Dsp-16-u16},a1 */
35827
  {
35828
    { 0, 0, 0, 0 },
35829
    { { MNEM, ' ', OP (DSP_16_U16), ',', 'a', '1', 0 } },
35830
    & ifmt_pusha16_16_Mova_dst16_16_16_absolute_Mova_HI, { 0xeb5f0000 }
35831
  },
35832
/* mova [$Dst16An],a0 */
35833
  {
35834
    { 0, 0, 0, 0 },
35835
    { { MNEM, ' ', '[', OP (DST16AN), ']', ',', 'a', '0', 0 } },
35836
    & ifmt_pusha16_16_Mova_dst16_An_indirect_Mova_HI, { 0xeb46 }
35837
  },
35838
/* mova ${Dsp-16-u8}[$Dst16An],a0 */
35839
  {
35840
    { 0, 0, 0, 0 },
35841
    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', 'a', '0', 0 } },
35842
    & ifmt_pusha16_16_Mova_dst16_16_8_An_relative_Mova_HI, { 0xeb4800 }
35843
  },
35844
/* mova ${Dsp-16-u16}[$Dst16An],a0 */
35845
  {
35846
    { 0, 0, 0, 0 },
35847
    { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', 'a', '0', 0 } },
35848
    & ifmt_pusha16_16_Mova_dst16_16_16_An_relative_Mova_HI, { 0xeb4c0000 }
35849
  },
35850
/* mova ${Dsp-16-u8}[sb],a0 */
35851
  {
35852
    { 0, 0, 0, 0 },
35853
    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', 'a', '0', 0 } },
35854
    & ifmt_pusha16_16_Mova_dst16_16_8_SB_relative_Mova_HI, { 0xeb4a00 }
35855
  },
35856
/* mova ${Dsp-16-u16}[sb],a0 */
35857
  {
35858
    { 0, 0, 0, 0 },
35859
    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', 'a', '0', 0 } },
35860
    & ifmt_pusha16_16_Mova_dst16_16_16_SB_relative_Mova_HI, { 0xeb4e0000 }
35861
  },
35862
/* mova ${Dsp-16-s8}[fb],a0 */
35863
  {
35864
    { 0, 0, 0, 0 },
35865
    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', 'a', '0', 0 } },
35866
    & ifmt_pusha16_16_Mova_dst16_16_8_FB_relative_Mova_HI, { 0xeb4b00 }
35867
  },
35868
/* mova ${Dsp-16-u16},a0 */
35869
  {
35870
    { 0, 0, 0, 0 },
35871
    { { MNEM, ' ', OP (DSP_16_U16), ',', 'a', '0', 0 } },
35872
    & ifmt_pusha16_16_Mova_dst16_16_16_absolute_Mova_HI, { 0xeb4f0000 }
35873
  },
35874
/* mova [$Dst16An],r3 */
35875
  {
35876
    { 0, 0, 0, 0 },
35877
    { { MNEM, ' ', '[', OP (DST16AN), ']', ',', 'r', '3', 0 } },
35878
    & ifmt_pusha16_16_Mova_dst16_An_indirect_Mova_HI, { 0xeb36 }
35879
  },
35880
/* mova ${Dsp-16-u8}[$Dst16An],r3 */
35881
  {
35882
    { 0, 0, 0, 0 },
35883
    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', 'r', '3', 0 } },
35884
    & ifmt_pusha16_16_Mova_dst16_16_8_An_relative_Mova_HI, { 0xeb3800 }
35885
  },
35886
/* mova ${Dsp-16-u16}[$Dst16An],r3 */
35887
  {
35888
    { 0, 0, 0, 0 },
35889
    { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', 'r', '3', 0 } },
35890
    & ifmt_pusha16_16_Mova_dst16_16_16_An_relative_Mova_HI, { 0xeb3c0000 }
35891
  },
35892
/* mova ${Dsp-16-u8}[sb],r3 */
35893
  {
35894
    { 0, 0, 0, 0 },
35895
    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', 'r', '3', 0 } },
35896
    & ifmt_pusha16_16_Mova_dst16_16_8_SB_relative_Mova_HI, { 0xeb3a00 }
35897
  },
35898
/* mova ${Dsp-16-u16}[sb],r3 */
35899
  {
35900
    { 0, 0, 0, 0 },
35901
    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', 'r', '3', 0 } },
35902
    & ifmt_pusha16_16_Mova_dst16_16_16_SB_relative_Mova_HI, { 0xeb3e0000 }
35903
  },
35904
/* mova ${Dsp-16-s8}[fb],r3 */
35905
  {
35906
    { 0, 0, 0, 0 },
35907
    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', 'r', '3', 0 } },
35908
    & ifmt_pusha16_16_Mova_dst16_16_8_FB_relative_Mova_HI, { 0xeb3b00 }
35909
  },
35910
/* mova ${Dsp-16-u16},r3 */
35911
  {
35912
    { 0, 0, 0, 0 },
35913
    { { MNEM, ' ', OP (DSP_16_U16), ',', 'r', '3', 0 } },
35914
    & ifmt_pusha16_16_Mova_dst16_16_16_absolute_Mova_HI, { 0xeb3f0000 }
35915
  },
35916
/* mova [$Dst16An],r2 */
35917
  {
35918
    { 0, 0, 0, 0 },
35919
    { { MNEM, ' ', '[', OP (DST16AN), ']', ',', 'r', '2', 0 } },
35920
    & ifmt_pusha16_16_Mova_dst16_An_indirect_Mova_HI, { 0xeb26 }
35921
  },
35922
/* mova ${Dsp-16-u8}[$Dst16An],r2 */
35923
  {
35924
    { 0, 0, 0, 0 },
35925
    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', 'r', '2', 0 } },
35926
    & ifmt_pusha16_16_Mova_dst16_16_8_An_relative_Mova_HI, { 0xeb2800 }
35927
  },
35928
/* mova ${Dsp-16-u16}[$Dst16An],r2 */
35929
  {
35930
    { 0, 0, 0, 0 },
35931
    { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', 'r', '2', 0 } },
35932
    & ifmt_pusha16_16_Mova_dst16_16_16_An_relative_Mova_HI, { 0xeb2c0000 }
35933
  },
35934
/* mova ${Dsp-16-u8}[sb],r2 */
35935
  {
35936
    { 0, 0, 0, 0 },
35937
    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', 'r', '2', 0 } },
35938
    & ifmt_pusha16_16_Mova_dst16_16_8_SB_relative_Mova_HI, { 0xeb2a00 }
35939
  },
35940
/* mova ${Dsp-16-u16}[sb],r2 */
35941
  {
35942
    { 0, 0, 0, 0 },
35943
    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', 'r', '2', 0 } },
35944
    & ifmt_pusha16_16_Mova_dst16_16_16_SB_relative_Mova_HI, { 0xeb2e0000 }
35945
  },
35946
/* mova ${Dsp-16-s8}[fb],r2 */
35947
  {
35948
    { 0, 0, 0, 0 },
35949
    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', 'r', '2', 0 } },
35950
    & ifmt_pusha16_16_Mova_dst16_16_8_FB_relative_Mova_HI, { 0xeb2b00 }
35951
  },
35952
/* mova ${Dsp-16-u16},r2 */
35953
  {
35954
    { 0, 0, 0, 0 },
35955
    { { MNEM, ' ', OP (DSP_16_U16), ',', 'r', '2', 0 } },
35956
    & ifmt_pusha16_16_Mova_dst16_16_16_absolute_Mova_HI, { 0xeb2f0000 }
35957
  },
35958
/* mova [$Dst16An],r1 */
35959
  {
35960
    { 0, 0, 0, 0 },
35961
    { { MNEM, ' ', '[', OP (DST16AN), ']', ',', 'r', '1', 0 } },
35962
    & ifmt_pusha16_16_Mova_dst16_An_indirect_Mova_HI, { 0xeb16 }
35963
  },
35964
/* mova ${Dsp-16-u8}[$Dst16An],r1 */
35965
  {
35966
    { 0, 0, 0, 0 },
35967
    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', 'r', '1', 0 } },
35968
    & ifmt_pusha16_16_Mova_dst16_16_8_An_relative_Mova_HI, { 0xeb1800 }
35969
  },
35970
/* mova ${Dsp-16-u16}[$Dst16An],r1 */
35971
  {
35972
    { 0, 0, 0, 0 },
35973
    { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', 'r', '1', 0 } },
35974
    & ifmt_pusha16_16_Mova_dst16_16_16_An_relative_Mova_HI, { 0xeb1c0000 }
35975
  },
35976
/* mova ${Dsp-16-u8}[sb],r1 */
35977
  {
35978
    { 0, 0, 0, 0 },
35979
    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', 'r', '1', 0 } },
35980
    & ifmt_pusha16_16_Mova_dst16_16_8_SB_relative_Mova_HI, { 0xeb1a00 }
35981
  },
35982
/* mova ${Dsp-16-u16}[sb],r1 */
35983
  {
35984
    { 0, 0, 0, 0 },
35985
    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', 'r', '1', 0 } },
35986
    & ifmt_pusha16_16_Mova_dst16_16_16_SB_relative_Mova_HI, { 0xeb1e0000 }
35987
  },
35988
/* mova ${Dsp-16-s8}[fb],r1 */
35989
  {
35990
    { 0, 0, 0, 0 },
35991
    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', 'r', '1', 0 } },
35992
    & ifmt_pusha16_16_Mova_dst16_16_8_FB_relative_Mova_HI, { 0xeb1b00 }
35993
  },
35994
/* mova ${Dsp-16-u16},r1 */
35995
  {
35996
    { 0, 0, 0, 0 },
35997
    { { MNEM, ' ', OP (DSP_16_U16), ',', 'r', '1', 0 } },
35998
    & ifmt_pusha16_16_Mova_dst16_16_16_absolute_Mova_HI, { 0xeb1f0000 }
35999
  },
36000
/* mova [$Dst16An],r0 */
36001
  {
36002
    { 0, 0, 0, 0 },
36003
    { { MNEM, ' ', '[', OP (DST16AN), ']', ',', 'r', '0', 0 } },
36004
    & ifmt_pusha16_16_Mova_dst16_An_indirect_Mova_HI, { 0xeb06 }
36005
  },
36006
/* mova ${Dsp-16-u8}[$Dst16An],r0 */
36007
  {
36008
    { 0, 0, 0, 0 },
36009
    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', 'r', '0', 0 } },
36010
    & ifmt_pusha16_16_Mova_dst16_16_8_An_relative_Mova_HI, { 0xeb0800 }
36011
  },
36012
/* mova ${Dsp-16-u16}[$Dst16An],r0 */
36013
  {
36014
    { 0, 0, 0, 0 },
36015
    { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', 'r', '0', 0 } },
36016
    & ifmt_pusha16_16_Mova_dst16_16_16_An_relative_Mova_HI, { 0xeb0c0000 }
36017
  },
36018
/* mova ${Dsp-16-u8}[sb],r0 */
36019
  {
36020
    { 0, 0, 0, 0 },
36021
    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', 'r', '0', 0 } },
36022
    & ifmt_pusha16_16_Mova_dst16_16_8_SB_relative_Mova_HI, { 0xeb0a00 }
36023
  },
36024
/* mova ${Dsp-16-u16}[sb],r0 */
36025
  {
36026
    { 0, 0, 0, 0 },
36027
    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', 'r', '0', 0 } },
36028
    & ifmt_pusha16_16_Mova_dst16_16_16_SB_relative_Mova_HI, { 0xeb0e0000 }
36029
  },
36030
/* mova ${Dsp-16-s8}[fb],r0 */
36031
  {
36032
    { 0, 0, 0, 0 },
36033
    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', 'r', '0', 0 } },
36034
    & ifmt_pusha16_16_Mova_dst16_16_8_FB_relative_Mova_HI, { 0xeb0b00 }
36035
  },
36036
/* mova ${Dsp-16-u16},r0 */
36037
  {
36038
    { 0, 0, 0, 0 },
36039
    { { MNEM, ' ', OP (DSP_16_U16), ',', 'r', '0', 0 } },
36040
    & ifmt_pusha16_16_Mova_dst16_16_16_absolute_Mova_HI, { 0xeb0f0000 }
36041
  },
36042
/* mov.w${G} ${Dsp-16-u8}[$Dst32AnUnprefixed],${Dsp-24-s8}[sp] */
36043
  {
36044
    { 0, 0, 0, 0 },
36045
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 's', 'p', ']', 0 } },
36046
    & ifmt_mov32_w_dst_dspsp_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0xa30f0000 }
36047
  },
36048
/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[sp] */
36049
  {
36050
    { 0, 0, 0, 0 },
36051
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 's', 'p', ']', 0 } },
36052
    & ifmt_mov32_w_dst_dspsp_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0xa38f0000 }
36053
  },
36054
/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[sp] */
36055
  {
36056
    { 0, 0, 0, 0 },
36057
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 's', 'p', ']', 0 } },
36058
    & ifmt_mov32_w_dst_dspsp_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0xa3cf0000 }
36059
  },
36060
/* mov.w${G} ${Dsp-16-u16}[$Dst32AnUnprefixed],${Dsp-32-s8}[sp] */
36061
  {
36062
    { 0, 0, 0, 0 },
36063
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 's', 'p', ']', 0 } },
36064
    & ifmt_mov32_w_dst_dspsp_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0xa50f0000 }
36065
  },
36066
/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[sp] */
36067
  {
36068
    { 0, 0, 0, 0 },
36069
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 's', 'p', ']', 0 } },
36070
    & ifmt_mov32_w_dst_dspsp_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0xa58f0000 }
36071
  },
36072
/* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[sp] */
36073
  {
36074
    { 0, 0, 0, 0 },
36075
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 's', 'p', ']', 0 } },
36076
    & ifmt_mov32_w_dst_dspsp_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0xa5cf0000 }
36077
  },
36078
/* mov.w${G} ${Dsp-16-u16},${Dsp-32-s8}[sp] */
36079
  {
36080
    { 0, 0, 0, 0 },
36081
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 's', 'p', ']', 0 } },
36082
    & ifmt_mov32_w_dst_dspsp_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0xa7cf0000 }
36083
  },
36084
/* mov.w${G} ${Dsp-16-u24}[$Dst32AnUnprefixed],${Dsp-40-s8}[sp] */
36085
  {
36086
    { 0, 0, 0, 0 },
36087
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 's', 'p', ']', 0 } },
36088
    & ifmt_mov32_w_dst_dspsp_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0xa70f0000 }
36089
  },
36090
/* mov.w${G} ${Dsp-16-u24},${Dsp-40-s8}[sp] */
36091
  {
36092
    { 0, 0, 0, 0 },
36093
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 's', 'p', ']', 0 } },
36094
    & ifmt_mov32_w_dst_dspsp_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0xa78f0000 }
36095
  },
36096
/* mov.w${G} $Dst32RnUnprefixedHI,${Dsp-16-s8}[sp] */
36097
  {
36098
    { 0, 0, 0, 0 },
36099
    { { MNEM, OP (G), ' ', OP (DST32RNUNPREFIXEDHI), ',', OP (DSP_16_S8), '[', 's', 'p', ']', 0 } },
36100
    & ifmt_mov32_w_dst_dspsp_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0xa90f00 }
36101
  },
36102
/* mov.w${G} $Dst32AnUnprefixedHI,${Dsp-16-s8}[sp] */
36103
  {
36104
    { 0, 0, 0, 0 },
36105
    { { MNEM, OP (G), ' ', OP (DST32ANUNPREFIXEDHI), ',', OP (DSP_16_S8), '[', 's', 'p', ']', 0 } },
36106
    & ifmt_mov32_w_dst_dspsp_basic_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0xa18f00 }
36107
  },
36108
/* mov.w${G} [$Dst32AnUnprefixed],${Dsp-16-s8}[sp] */
36109
  {
36110
    { 0, 0, 0, 0 },
36111
    { { MNEM, OP (G), ' ', '[', OP (DST32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 's', 'p', ']', 0 } },
36112
    & ifmt_mov32_w_dst_dspsp_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0xa10f00 }
36113
  },
36114
/* mov.b${G} ${Dsp-16-u8}[$Dst32AnUnprefixed],${Dsp-24-s8}[sp] */
36115
  {
36116
    { 0, 0, 0, 0 },
36117
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 's', 'p', ']', 0 } },
36118
    & ifmt_mov32_b_dst_dspsp_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0xa20f0000 }
36119
  },
36120
/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[sp] */
36121
  {
36122
    { 0, 0, 0, 0 },
36123
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 's', 'p', ']', 0 } },
36124
    & ifmt_mov32_b_dst_dspsp_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0xa28f0000 }
36125
  },
36126
/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[sp] */
36127
  {
36128
    { 0, 0, 0, 0 },
36129
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 's', 'p', ']', 0 } },
36130
    & ifmt_mov32_b_dst_dspsp_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0xa2cf0000 }
36131
  },
36132
/* mov.b${G} ${Dsp-16-u16}[$Dst32AnUnprefixed],${Dsp-32-s8}[sp] */
36133
  {
36134
    { 0, 0, 0, 0 },
36135
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 's', 'p', ']', 0 } },
36136
    & ifmt_mov32_b_dst_dspsp_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0xa40f0000 }
36137
  },
36138
/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[sp] */
36139
  {
36140
    { 0, 0, 0, 0 },
36141
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 's', 'p', ']', 0 } },
36142
    & ifmt_mov32_b_dst_dspsp_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0xa48f0000 }
36143
  },
36144
/* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[sp] */
36145
  {
36146
    { 0, 0, 0, 0 },
36147
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 's', 'p', ']', 0 } },
36148
    & ifmt_mov32_b_dst_dspsp_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0xa4cf0000 }
36149
  },
36150
/* mov.b${G} ${Dsp-16-u16},${Dsp-32-s8}[sp] */
36151
  {
36152
    { 0, 0, 0, 0 },
36153
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 's', 'p', ']', 0 } },
36154
    & ifmt_mov32_b_dst_dspsp_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0xa6cf0000 }
36155
  },
36156
/* mov.b${G} ${Dsp-16-u24}[$Dst32AnUnprefixed],${Dsp-40-s8}[sp] */
36157
  {
36158
    { 0, 0, 0, 0 },
36159
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 's', 'p', ']', 0 } },
36160
    & ifmt_mov32_b_dst_dspsp_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0xa60f0000 }
36161
  },
36162
/* mov.b${G} ${Dsp-16-u24},${Dsp-40-s8}[sp] */
36163
  {
36164
    { 0, 0, 0, 0 },
36165
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 's', 'p', ']', 0 } },
36166
    & ifmt_mov32_b_dst_dspsp_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0xa68f0000 }
36167
  },
36168
/* mov.b${G} $Dst32RnUnprefixedQI,${Dsp-16-s8}[sp] */
36169
  {
36170
    { 0, 0, 0, 0 },
36171
    { { MNEM, OP (G), ' ', OP (DST32RNUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 's', 'p', ']', 0 } },
36172
    & ifmt_mov32_b_dst_dspsp_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0xa80f00 }
36173
  },
36174
/* mov.b${G} $Dst32AnUnprefixedQI,${Dsp-16-s8}[sp] */
36175
  {
36176
    { 0, 0, 0, 0 },
36177
    { { MNEM, OP (G), ' ', OP (DST32ANUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 's', 'p', ']', 0 } },
36178
    & ifmt_mov32_b_dst_dspsp_basic_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0xa08f00 }
36179
  },
36180
/* mov.b${G} [$Dst32AnUnprefixed],${Dsp-16-s8}[sp] */
36181
  {
36182
    { 0, 0, 0, 0 },
36183
    { { MNEM, OP (G), ' ', '[', OP (DST32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 's', 'p', ']', 0 } },
36184
    & ifmt_mov32_b_dst_dspsp_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0xa00f00 }
36185
  },
36186
/* mov.w${G} ${Dsp-16-u8}[$Dst16An],${Dsp-24-s8}[sp] */
36187
  {
36188
    { 0, 0, 0, 0 },
36189
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', OP (DSP_24_S8), '[', 's', 'p', ']', 0 } },
36190
    & ifmt_mov16_w_dst_dspsp_16_8_dst16_16_8_An_relative_HI, { 0x75380000 }
36191
  },
36192
/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[sp] */
36193
  {
36194
    { 0, 0, 0, 0 },
36195
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 's', 'p', ']', 0 } },
36196
    & ifmt_mov16_w_dst_dspsp_16_8_dst16_16_8_SB_relative_HI, { 0x753a0000 }
36197
  },
36198
/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[sp] */
36199
  {
36200
    { 0, 0, 0, 0 },
36201
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 's', 'p', ']', 0 } },
36202
    & ifmt_mov16_w_dst_dspsp_16_8_dst16_16_8_FB_relative_HI, { 0x753b0000 }
36203
  },
36204
/* mov.w${G} ${Dsp-16-u16}[$Dst16An],${Dsp-32-s8}[sp] */
36205
  {
36206
    { 0, 0, 0, 0 },
36207
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', OP (DSP_32_S8), '[', 's', 'p', ']', 0 } },
36208
    & ifmt_mov16_w_dst_dspsp_16_16_dst16_16_16_An_relative_HI, { 0x753c0000 }
36209
  },
36210
/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[sp] */
36211
  {
36212
    { 0, 0, 0, 0 },
36213
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 's', 'p', ']', 0 } },
36214
    & ifmt_mov16_w_dst_dspsp_16_16_dst16_16_16_SB_relative_HI, { 0x753e0000 }
36215
  },
36216
/* mov.w${G} ${Dsp-16-u16},${Dsp-32-s8}[sp] */
36217
  {
36218
    { 0, 0, 0, 0 },
36219
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 's', 'p', ']', 0 } },
36220
    & ifmt_mov16_w_dst_dspsp_16_16_dst16_16_16_absolute_HI, { 0x753f0000 }
36221
  },
36222
/* mov.w${G} $Dst16RnHI,${Dsp-16-s8}[sp] */
36223
  {
36224
    { 0, 0, 0, 0 },
36225
    { { MNEM, OP (G), ' ', OP (DST16RNHI), ',', OP (DSP_16_S8), '[', 's', 'p', ']', 0 } },
36226
    & ifmt_mov16_w_dst_dspsp_basic_dst16_Rn_direct_HI, { 0x753000 }
36227
  },
36228
/* mov.w${G} $Dst16AnHI,${Dsp-16-s8}[sp] */
36229
  {
36230
    { 0, 0, 0, 0 },
36231
    { { MNEM, OP (G), ' ', OP (DST16ANHI), ',', OP (DSP_16_S8), '[', 's', 'p', ']', 0 } },
36232
    & ifmt_mov16_w_dst_dspsp_basic_dst16_An_direct_HI, { 0x753400 }
36233
  },
36234
/* mov.w${G} [$Dst16An],${Dsp-16-s8}[sp] */
36235
  {
36236
    { 0, 0, 0, 0 },
36237
    { { MNEM, OP (G), ' ', '[', OP (DST16AN), ']', ',', OP (DSP_16_S8), '[', 's', 'p', ']', 0 } },
36238
    & ifmt_mov16_w_dst_dspsp_basic_dst16_An_indirect_HI, { 0x753600 }
36239
  },
36240
/* mov.b${G} ${Dsp-16-u8}[$Dst16An],${Dsp-24-s8}[sp] */
36241
  {
36242
    { 0, 0, 0, 0 },
36243
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', OP (DSP_24_S8), '[', 's', 'p', ']', 0 } },
36244
    & ifmt_mov16_b_dst_dspsp_16_8_dst16_16_8_An_relative_QI, { 0x74380000 }
36245
  },
36246
/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[sp] */
36247
  {
36248
    { 0, 0, 0, 0 },
36249
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 's', 'p', ']', 0 } },
36250
    & ifmt_mov16_b_dst_dspsp_16_8_dst16_16_8_SB_relative_QI, { 0x743a0000 }
36251
  },
36252
/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[sp] */
36253
  {
36254
    { 0, 0, 0, 0 },
36255
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 's', 'p', ']', 0 } },
36256
    & ifmt_mov16_b_dst_dspsp_16_8_dst16_16_8_FB_relative_QI, { 0x743b0000 }
36257
  },
36258
/* mov.b${G} ${Dsp-16-u16}[$Dst16An],${Dsp-32-s8}[sp] */
36259
  {
36260
    { 0, 0, 0, 0 },
36261
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', OP (DSP_32_S8), '[', 's', 'p', ']', 0 } },
36262
    & ifmt_mov16_b_dst_dspsp_16_16_dst16_16_16_An_relative_QI, { 0x743c0000 }
36263
  },
36264
/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[sp] */
36265
  {
36266
    { 0, 0, 0, 0 },
36267
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 's', 'p', ']', 0 } },
36268
    & ifmt_mov16_b_dst_dspsp_16_16_dst16_16_16_SB_relative_QI, { 0x743e0000 }
36269
  },
36270
/* mov.b${G} ${Dsp-16-u16},${Dsp-32-s8}[sp] */
36271
  {
36272
    { 0, 0, 0, 0 },
36273
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 's', 'p', ']', 0 } },
36274
    & ifmt_mov16_b_dst_dspsp_16_16_dst16_16_16_absolute_QI, { 0x743f0000 }
36275
  },
36276
/* mov.b${G} $Dst16RnQI,${Dsp-16-s8}[sp] */
36277
  {
36278
    { 0, 0, 0, 0 },
36279
    { { MNEM, OP (G), ' ', OP (DST16RNQI), ',', OP (DSP_16_S8), '[', 's', 'p', ']', 0 } },
36280
    & ifmt_mov16_b_dst_dspsp_basic_dst16_Rn_direct_QI, { 0x743000 }
36281
  },
36282
/* mov.b${G} $Dst16AnQI,${Dsp-16-s8}[sp] */
36283
  {
36284
    { 0, 0, 0, 0 },
36285
    { { MNEM, OP (G), ' ', OP (DST16ANQI), ',', OP (DSP_16_S8), '[', 's', 'p', ']', 0 } },
36286
    & ifmt_mov16_b_dst_dspsp_basic_dst16_An_direct_QI, { 0x743400 }
36287
  },
36288
/* mov.b${G} [$Dst16An],${Dsp-16-s8}[sp] */
36289
  {
36290
    { 0, 0, 0, 0 },
36291
    { { MNEM, OP (G), ' ', '[', OP (DST16AN), ']', ',', OP (DSP_16_S8), '[', 's', 'p', ']', 0 } },
36292
    & ifmt_mov16_b_dst_dspsp_basic_dst16_An_indirect_QI, { 0x743600 }
36293
  },
36294
/* mov.w${G} ${Dsp-24-s8}[sp],${Dsp-16-u8}[$Dst32AnUnprefixed] */
36295
  {
36296
    { 0, 0, 0, 0 },
36297
    { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
36298
    & ifmt_mov32_w_dst_dspsp_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0xb30f0000 }
36299
  },
36300
/* mov.w${G} ${Dsp-24-s8}[sp],${Dsp-16-u8}[sb] */
36301
  {
36302
    { 0, 0, 0, 0 },
36303
    { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
36304
    & ifmt_mov32_w_dst_dspsp_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0xb38f0000 }
36305
  },
36306
/* mov.w${G} ${Dsp-24-s8}[sp],${Dsp-16-s8}[fb] */
36307
  {
36308
    { 0, 0, 0, 0 },
36309
    { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 's', 'p', ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
36310
    & ifmt_mov32_w_dst_dspsp_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0xb3cf0000 }
36311
  },
36312
/* mov.w${G} ${Dsp-32-s8}[sp],${Dsp-16-u16}[$Dst32AnUnprefixed] */
36313
  {
36314
    { 0, 0, 0, 0 },
36315
    { { MNEM, OP (G), ' ', OP (DSP_32_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
36316
    & ifmt_mov32_w_dst_dspsp_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0xb50f0000 }
36317
  },
36318
/* mov.w${G} ${Dsp-32-s8}[sp],${Dsp-16-u16}[sb] */
36319
  {
36320
    { 0, 0, 0, 0 },
36321
    { { MNEM, OP (G), ' ', OP (DSP_32_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
36322
    & ifmt_mov32_w_dst_dspsp_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0xb58f0000 }
36323
  },
36324
/* mov.w${G} ${Dsp-32-s8}[sp],${Dsp-16-s16}[fb] */
36325
  {
36326
    { 0, 0, 0, 0 },
36327
    { { MNEM, OP (G), ' ', OP (DSP_32_S8), '[', 's', 'p', ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
36328
    & ifmt_mov32_w_dst_dspsp_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0xb5cf0000 }
36329
  },
36330
/* mov.w${G} ${Dsp-32-s8}[sp],${Dsp-16-u16} */
36331
  {
36332
    { 0, 0, 0, 0 },
36333
    { { MNEM, OP (G), ' ', OP (DSP_32_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U16), 0 } },
36334
    & ifmt_mov32_w_dst_dspsp_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0xb7cf0000 }
36335
  },
36336
/* mov.w${G} ${Dsp-40-s8}[sp],${Dsp-16-u24}[$Dst32AnUnprefixed] */
36337
  {
36338
    { 0, 0, 0, 0 },
36339
    { { MNEM, OP (G), ' ', OP (DSP_40_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
36340
    & ifmt_mov32_w_dst_dspsp_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0xb70f0000 }
36341
  },
36342
/* mov.w${G} ${Dsp-40-s8}[sp],${Dsp-16-u24} */
36343
  {
36344
    { 0, 0, 0, 0 },
36345
    { { MNEM, OP (G), ' ', OP (DSP_40_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U24), 0 } },
36346
    & ifmt_mov32_w_dst_dspsp_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0xb78f0000 }
36347
  },
36348
/* mov.w${G} ${Dsp-16-s8}[sp],$Dst32RnUnprefixedHI */
36349
  {
36350
    { 0, 0, 0, 0 },
36351
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 's', 'p', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
36352
    & ifmt_mov32_w_dst_dspsp_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0xb90f00 }
36353
  },
36354
/* mov.w${G} ${Dsp-16-s8}[sp],$Dst32AnUnprefixedHI */
36355
  {
36356
    { 0, 0, 0, 0 },
36357
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 's', 'p', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
36358
    & ifmt_mov32_w_dst_dspsp_basic_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0xb18f00 }
36359
  },
36360
/* mov.w${G} ${Dsp-16-s8}[sp],[$Dst32AnUnprefixed] */
36361
  {
36362
    { 0, 0, 0, 0 },
36363
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 's', 'p', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
36364
    & ifmt_mov32_w_dst_dspsp_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0xb10f00 }
36365
  },
36366
/* mov.b${G} ${Dsp-24-s8}[sp],${Dsp-16-u8}[$Dst32AnUnprefixed] */
36367
  {
36368
    { 0, 0, 0, 0 },
36369
    { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
36370
    & ifmt_mov32_b_dst_dspsp_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0xb20f0000 }
36371
  },
36372
/* mov.b${G} ${Dsp-24-s8}[sp],${Dsp-16-u8}[sb] */
36373
  {
36374
    { 0, 0, 0, 0 },
36375
    { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
36376
    & ifmt_mov32_b_dst_dspsp_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0xb28f0000 }
36377
  },
36378
/* mov.b${G} ${Dsp-24-s8}[sp],${Dsp-16-s8}[fb] */
36379
  {
36380
    { 0, 0, 0, 0 },
36381
    { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 's', 'p', ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
36382
    & ifmt_mov32_b_dst_dspsp_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0xb2cf0000 }
36383
  },
36384
/* mov.b${G} ${Dsp-32-s8}[sp],${Dsp-16-u16}[$Dst32AnUnprefixed] */
36385
  {
36386
    { 0, 0, 0, 0 },
36387
    { { MNEM, OP (G), ' ', OP (DSP_32_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
36388
    & ifmt_mov32_b_dst_dspsp_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0xb40f0000 }
36389
  },
36390
/* mov.b${G} ${Dsp-32-s8}[sp],${Dsp-16-u16}[sb] */
36391
  {
36392
    { 0, 0, 0, 0 },
36393
    { { MNEM, OP (G), ' ', OP (DSP_32_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
36394
    & ifmt_mov32_b_dst_dspsp_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0xb48f0000 }
36395
  },
36396
/* mov.b${G} ${Dsp-32-s8}[sp],${Dsp-16-s16}[fb] */
36397
  {
36398
    { 0, 0, 0, 0 },
36399
    { { MNEM, OP (G), ' ', OP (DSP_32_S8), '[', 's', 'p', ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
36400
    & ifmt_mov32_b_dst_dspsp_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0xb4cf0000 }
36401
  },
36402
/* mov.b${G} ${Dsp-32-s8}[sp],${Dsp-16-u16} */
36403
  {
36404
    { 0, 0, 0, 0 },
36405
    { { MNEM, OP (G), ' ', OP (DSP_32_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U16), 0 } },
36406
    & ifmt_mov32_b_dst_dspsp_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0xb6cf0000 }
36407
  },
36408
/* mov.b${G} ${Dsp-40-s8}[sp],${Dsp-16-u24}[$Dst32AnUnprefixed] */
36409
  {
36410
    { 0, 0, 0, 0 },
36411
    { { MNEM, OP (G), ' ', OP (DSP_40_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
36412
    & ifmt_mov32_b_dst_dspsp_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0xb60f0000 }
36413
  },
36414
/* mov.b${G} ${Dsp-40-s8}[sp],${Dsp-16-u24} */
36415
  {
36416
    { 0, 0, 0, 0 },
36417
    { { MNEM, OP (G), ' ', OP (DSP_40_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U24), 0 } },
36418
    & ifmt_mov32_b_dst_dspsp_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0xb68f0000 }
36419
  },
36420
/* mov.b${G} ${Dsp-16-s8}[sp],$Dst32RnUnprefixedQI */
36421
  {
36422
    { 0, 0, 0, 0 },
36423
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 's', 'p', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
36424
    & ifmt_mov32_b_dst_dspsp_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0xb80f00 }
36425
  },
36426
/* mov.b${G} ${Dsp-16-s8}[sp],$Dst32AnUnprefixedQI */
36427
  {
36428
    { 0, 0, 0, 0 },
36429
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 's', 'p', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
36430
    & ifmt_mov32_b_dst_dspsp_basic_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0xb08f00 }
36431
  },
36432
/* mov.b${G} ${Dsp-16-s8}[sp],[$Dst32AnUnprefixed] */
36433
  {
36434
    { 0, 0, 0, 0 },
36435
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 's', 'p', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
36436
    & ifmt_mov32_b_dst_dspsp_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0xb00f00 }
36437
  },
36438
/* mov.w${G} ${Dsp-24-s8}[sp],${Dsp-16-u8}[$Dst16An] */
36439
  {
36440
    { 0, 0, 0, 0 },
36441
    { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
36442
    & ifmt_mov16_w_dst_dspsp_16_8_dst16_16_8_An_relative_HI, { 0x75b80000 }
36443
  },
36444
/* mov.w${G} ${Dsp-24-s8}[sp],${Dsp-16-u8}[sb] */
36445
  {
36446
    { 0, 0, 0, 0 },
36447
    { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
36448
    & ifmt_mov16_w_dst_dspsp_16_8_dst16_16_8_SB_relative_HI, { 0x75ba0000 }
36449
  },
36450
/* mov.w${G} ${Dsp-24-s8}[sp],${Dsp-16-s8}[fb] */
36451
  {
36452
    { 0, 0, 0, 0 },
36453
    { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 's', 'p', ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
36454
    & ifmt_mov16_w_dst_dspsp_16_8_dst16_16_8_FB_relative_HI, { 0x75bb0000 }
36455
  },
36456
/* mov.w${G} ${Dsp-32-s8}[sp],${Dsp-16-u16}[$Dst16An] */
36457
  {
36458
    { 0, 0, 0, 0 },
36459
    { { MNEM, OP (G), ' ', OP (DSP_32_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
36460
    & ifmt_mov16_w_dst_dspsp_16_16_dst16_16_16_An_relative_HI, { 0x75bc0000 }
36461
  },
36462
/* mov.w${G} ${Dsp-32-s8}[sp],${Dsp-16-u16}[sb] */
36463
  {
36464
    { 0, 0, 0, 0 },
36465
    { { MNEM, OP (G), ' ', OP (DSP_32_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
36466
    & ifmt_mov16_w_dst_dspsp_16_16_dst16_16_16_SB_relative_HI, { 0x75be0000 }
36467
  },
36468
/* mov.w${G} ${Dsp-32-s8}[sp],${Dsp-16-u16} */
36469
  {
36470
    { 0, 0, 0, 0 },
36471
    { { MNEM, OP (G), ' ', OP (DSP_32_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U16), 0 } },
36472
    & ifmt_mov16_w_dst_dspsp_16_16_dst16_16_16_absolute_HI, { 0x75bf0000 }
36473
  },
36474
/* mov.w${G} ${Dsp-16-s8}[sp],$Dst16RnHI */
36475
  {
36476
    { 0, 0, 0, 0 },
36477
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 's', 'p', ']', ',', OP (DST16RNHI), 0 } },
36478
    & ifmt_mov16_w_dst_dspsp_basic_dst16_Rn_direct_HI, { 0x75b000 }
36479
  },
36480
/* mov.w${G} ${Dsp-16-s8}[sp],$Dst16AnHI */
36481
  {
36482
    { 0, 0, 0, 0 },
36483
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 's', 'p', ']', ',', OP (DST16ANHI), 0 } },
36484
    & ifmt_mov16_w_dst_dspsp_basic_dst16_An_direct_HI, { 0x75b400 }
36485
  },
36486
/* mov.w${G} ${Dsp-16-s8}[sp],[$Dst16An] */
36487
  {
36488
    { 0, 0, 0, 0 },
36489
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 's', 'p', ']', ',', '[', OP (DST16AN), ']', 0 } },
36490
    & ifmt_mov16_w_dst_dspsp_basic_dst16_An_indirect_HI, { 0x75b600 }
36491
  },
36492
/* mov.b${G} ${Dsp-24-s8}[sp],${Dsp-16-u8}[$Dst16An] */
36493
  {
36494
    { 0, 0, 0, 0 },
36495
    { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
36496
    & ifmt_mov16_b_dst_dspsp_16_8_dst16_16_8_An_relative_QI, { 0x74b80000 }
36497
  },
36498
/* mov.b${G} ${Dsp-24-s8}[sp],${Dsp-16-u8}[sb] */
36499
  {
36500
    { 0, 0, 0, 0 },
36501
    { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
36502
    & ifmt_mov16_b_dst_dspsp_16_8_dst16_16_8_SB_relative_QI, { 0x74ba0000 }
36503
  },
36504
/* mov.b${G} ${Dsp-24-s8}[sp],${Dsp-16-s8}[fb] */
36505
  {
36506
    { 0, 0, 0, 0 },
36507
    { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 's', 'p', ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
36508
    & ifmt_mov16_b_dst_dspsp_16_8_dst16_16_8_FB_relative_QI, { 0x74bb0000 }
36509
  },
36510
/* mov.b${G} ${Dsp-32-s8}[sp],${Dsp-16-u16}[$Dst16An] */
36511
  {
36512
    { 0, 0, 0, 0 },
36513
    { { MNEM, OP (G), ' ', OP (DSP_32_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
36514
    & ifmt_mov16_b_dst_dspsp_16_16_dst16_16_16_An_relative_QI, { 0x74bc0000 }
36515
  },
36516
/* mov.b${G} ${Dsp-32-s8}[sp],${Dsp-16-u16}[sb] */
36517
  {
36518
    { 0, 0, 0, 0 },
36519
    { { MNEM, OP (G), ' ', OP (DSP_32_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
36520
    & ifmt_mov16_b_dst_dspsp_16_16_dst16_16_16_SB_relative_QI, { 0x74be0000 }
36521
  },
36522
/* mov.b${G} ${Dsp-32-s8}[sp],${Dsp-16-u16} */
36523
  {
36524
    { 0, 0, 0, 0 },
36525
    { { MNEM, OP (G), ' ', OP (DSP_32_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U16), 0 } },
36526
    & ifmt_mov16_b_dst_dspsp_16_16_dst16_16_16_absolute_QI, { 0x74bf0000 }
36527
  },
36528
/* mov.b${G} ${Dsp-16-s8}[sp],$Dst16RnQI */
36529
  {
36530
    { 0, 0, 0, 0 },
36531
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 's', 'p', ']', ',', OP (DST16RNQI), 0 } },
36532
    & ifmt_mov16_b_dst_dspsp_basic_dst16_Rn_direct_QI, { 0x74b000 }
36533
  },
36534
/* mov.b${G} ${Dsp-16-s8}[sp],$Dst16AnQI */
36535
  {
36536
    { 0, 0, 0, 0 },
36537
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 's', 'p', ']', ',', OP (DST16ANQI), 0 } },
36538
    & ifmt_mov16_b_dst_dspsp_basic_dst16_An_direct_QI, { 0x74b400 }
36539
  },
36540
/* mov.b${G} ${Dsp-16-s8}[sp],[$Dst16An] */
36541
  {
36542
    { 0, 0, 0, 0 },
36543
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 's', 'p', ']', ',', '[', OP (DST16AN), ']', 0 } },
36544
    & ifmt_mov16_b_dst_dspsp_basic_dst16_An_indirect_QI, { 0x74b600 }
36545
  },
36546
/* mov.l${S} ${Dsp-8-u8}[sb],a1 */
36547
  {
36548
    { 0, 0, 0, 0 },
36549
    { { MNEM, OP (S), ' ', OP (DSP_8_U8), '[', 's', 'b', ']', ',', 'a', '1', 0 } },
36550
    & ifmt_mov32_sz_dst32_2_S_8_a1_dst32_2_S_8_SB_relative_SI, { 0x6900 }
36551
  },
36552
/* mov.l${S} ${Dsp-8-s8}[fb],a1 */
36553
  {
36554
    { 0, 0, 0, 0 },
36555
    { { MNEM, OP (S), ' ', OP (DSP_8_S8), '[', 'f', 'b', ']', ',', 'a', '1', 0 } },
36556
    & ifmt_mov32_sz_dst32_2_S_8_a1_dst32_2_S_8_FB_relative_SI, { 0x7900 }
36557
  },
36558
/* mov.l${S} ${Dsp-8-u8}[sb],a0 */
36559
  {
36560
    { 0, 0, 0, 0 },
36561
    { { MNEM, OP (S), ' ', OP (DSP_8_U8), '[', 's', 'b', ']', ',', 'a', '0', 0 } },
36562
    & ifmt_mov32_sz_dst32_2_S_8_a1_dst32_2_S_8_SB_relative_SI, { 0x6800 }
36563
  },
36564
/* mov.l${S} ${Dsp-8-s8}[fb],a0 */
36565
  {
36566
    { 0, 0, 0, 0 },
36567
    { { MNEM, OP (S), ' ', OP (DSP_8_S8), '[', 'f', 'b', ']', ',', 'a', '0', 0 } },
36568
    & ifmt_mov32_sz_dst32_2_S_8_a1_dst32_2_S_8_FB_relative_SI, { 0x7800 }
36569
  },
36570
/* mov.l${S} ${Dsp-8-u16},a1 */
36571
  {
36572
    { 0, 0, 0, 0 },
36573
    { { MNEM, OP (S), ' ', OP (DSP_8_U16), ',', 'a', '1', 0 } },
36574
    & ifmt_mov32_sz_dst32_2_S_16_a1_dst32_2_S_16_absolute_SI, { 0x590000 }
36575
  },
36576
/* mov.l${S} ${Dsp-8-u16},a0 */
36577
  {
36578
    { 0, 0, 0, 0 },
36579
    { { MNEM, OP (S), ' ', OP (DSP_8_U16), ',', 'a', '0', 0 } },
36580
    & ifmt_mov32_sz_dst32_2_S_16_a1_dst32_2_S_16_absolute_SI, { 0x580000 }
36581
  },
36582
/* mov.w${S} r0,${Dsp-8-u8}[sb] */
36583
  {
36584
    { 0, 0, 0, 0 },
36585
    { { MNEM, OP (S), ' ', 'r', '0', ',', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } },
36586
    & ifmt_mov32_w_r0_dst32_2_S_8_dst32_2_S_8_SB_relative_HI, { 0x2100 }
36587
  },
36588
/* mov.w${S} r0,${Dsp-8-s8}[fb] */
36589
  {
36590
    { 0, 0, 0, 0 },
36591
    { { MNEM, OP (S), ' ', 'r', '0', ',', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } },
36592
    & ifmt_mov32_w_r0_dst32_2_S_8_dst32_2_S_8_FB_relative_HI, { 0x3100 }
36593
  },
36594
/* mov.b${S} r0l,${Dsp-8-u8}[sb] */
36595
  {
36596
    { 0, 0, 0, 0 },
36597
    { { MNEM, OP (S), ' ', 'r', '0', 'l', ',', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } },
36598
    & ifmt_mov32_b_r0l_dst32_2_S_8_dst32_2_S_8_SB_relative_QI, { 0x2000 }
36599
  },
36600
/* mov.b${S} r0l,${Dsp-8-s8}[fb] */
36601
  {
36602
    { 0, 0, 0, 0 },
36603
    { { MNEM, OP (S), ' ', 'r', '0', 'l', ',', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } },
36604
    & ifmt_mov32_b_r0l_dst32_2_S_8_dst32_2_S_8_FB_relative_QI, { 0x3000 }
36605
  },
36606
/* mov.w${S} r0,${Dsp-8-u16} */
36607
  {
36608
    { 0, 0, 0, 0 },
36609
    { { MNEM, OP (S), ' ', 'r', '0', ',', OP (DSP_8_U16), 0 } },
36610
    & ifmt_mov32_w_r0_dst32_2_S_16_dst32_2_S_16_absolute_HI, { 0x110000 }
36611
  },
36612
/* mov.b${S} r0l,${Dsp-8-u16} */
36613
  {
36614
    { 0, 0, 0, 0 },
36615
    { { MNEM, OP (S), ' ', 'r', '0', 'l', ',', OP (DSP_8_U16), 0 } },
36616
    & ifmt_mov32_b_r0l_dst32_2_S_16_dst32_2_S_16_absolute_QI, { 0x100000 }
36617
  },
36618
/* mov.w${S} ${Dsp-8-u8}[sb],r1 */
36619
  {
36620
    { 0, 0, 0, 0 },
36621
    { { MNEM, OP (S), ' ', OP (DSP_8_U8), '[', 's', 'b', ']', ',', 'r', '1', 0 } },
36622
    & ifmt_mov32_w_r0_dst32_2_S_8_dst32_2_S_8_SB_relative_HI, { 0x6f00 }
36623
  },
36624
/* mov.w${S} ${Dsp-8-s8}[fb],r1 */
36625
  {
36626
    { 0, 0, 0, 0 },
36627
    { { MNEM, OP (S), ' ', OP (DSP_8_S8), '[', 'f', 'b', ']', ',', 'r', '1', 0 } },
36628
    & ifmt_mov32_w_r0_dst32_2_S_8_dst32_2_S_8_FB_relative_HI, { 0x7f00 }
36629
  },
36630
/* mov.b${S} ${Dsp-8-u8}[sb],r1l */
36631
  {
36632
    { 0, 0, 0, 0 },
36633
    { { MNEM, OP (S), ' ', OP (DSP_8_U8), '[', 's', 'b', ']', ',', 'r', '1', 'l', 0 } },
36634
    & ifmt_mov32_b_r0l_dst32_2_S_8_dst32_2_S_8_SB_relative_QI, { 0x6e00 }
36635
  },
36636
/* mov.b${S} ${Dsp-8-s8}[fb],r1l */
36637
  {
36638
    { 0, 0, 0, 0 },
36639
    { { MNEM, OP (S), ' ', OP (DSP_8_S8), '[', 'f', 'b', ']', ',', 'r', '1', 'l', 0 } },
36640
    & ifmt_mov32_b_r0l_dst32_2_S_8_dst32_2_S_8_FB_relative_QI, { 0x7e00 }
36641
  },
36642
/* mov.w${S} ${Dsp-8-u16},r1 */
36643
  {
36644
    { 0, 0, 0, 0 },
36645
    { { MNEM, OP (S), ' ', OP (DSP_8_U16), ',', 'r', '1', 0 } },
36646
    & ifmt_mov32_w_r0_dst32_2_S_16_dst32_2_S_16_absolute_HI, { 0x5f0000 }
36647
  },
36648
/* mov.b${S} ${Dsp-8-u16},r1l */
36649
  {
36650
    { 0, 0, 0, 0 },
36651
    { { MNEM, OP (S), ' ', OP (DSP_8_U16), ',', 'r', '1', 'l', 0 } },
36652
    & ifmt_mov32_b_r0l_dst32_2_S_16_dst32_2_S_16_absolute_QI, { 0x5e0000 }
36653
  },
36654
/* mov.w${S} r0,r1 */
36655
  {
36656
    { 0, 0, 0, 0 },
36657
    { { MNEM, OP (S), ' ', 'r', '0', ',', 'r', '1', 0 } },
36658
    & ifmt_mov32_w_dst32_2_S_basic_r1_dst32_2_S_R0_direct_HI, { 0x4f }
36659
  },
36660
/* mov.b${S} r0l,r1l */
36661
  {
36662
    { 0, 0, 0, 0 },
36663
    { { MNEM, OP (S), ' ', 'r', '0', 'l', ',', 'r', '1', 'l', 0 } },
36664
    & ifmt_mov32_b_dst32_2_S_basic_r1l_dst32_2_S_R0l_direct_QI, { 0x4e }
36665
  },
36666
/* mov.w${S} ${Dsp-8-u8}[sb],r0 */
36667
  {
36668
    { 0, 0, 0, 0 },
36669
    { { MNEM, OP (S), ' ', OP (DSP_8_U8), '[', 's', 'b', ']', ',', 'r', '0', 0 } },
36670
    & ifmt_mov32_w_r0_dst32_2_S_8_dst32_2_S_8_SB_relative_HI, { 0x2900 }
36671
  },
36672
/* mov.w${S} ${Dsp-8-s8}[fb],r0 */
36673
  {
36674
    { 0, 0, 0, 0 },
36675
    { { MNEM, OP (S), ' ', OP (DSP_8_S8), '[', 'f', 'b', ']', ',', 'r', '0', 0 } },
36676
    & ifmt_mov32_w_r0_dst32_2_S_8_dst32_2_S_8_FB_relative_HI, { 0x3900 }
36677
  },
36678
/* mov.b${S} ${Dsp-8-u8}[sb],r0l */
36679
  {
36680
    { 0, 0, 0, 0 },
36681
    { { MNEM, OP (S), ' ', OP (DSP_8_U8), '[', 's', 'b', ']', ',', 'r', '0', 'l', 0 } },
36682
    & ifmt_mov32_b_r0l_dst32_2_S_8_dst32_2_S_8_SB_relative_QI, { 0x2800 }
36683
  },
36684
/* mov.b${S} ${Dsp-8-s8}[fb],r0l */
36685
  {
36686
    { 0, 0, 0, 0 },
36687
    { { MNEM, OP (S), ' ', OP (DSP_8_S8), '[', 'f', 'b', ']', ',', 'r', '0', 'l', 0 } },
36688
    & ifmt_mov32_b_r0l_dst32_2_S_8_dst32_2_S_8_FB_relative_QI, { 0x3800 }
36689
  },
36690
/* mov.w${S} ${Dsp-8-u16},r0 */
36691
  {
36692
    { 0, 0, 0, 0 },
36693
    { { MNEM, OP (S), ' ', OP (DSP_8_U16), ',', 'r', '0', 0 } },
36694
    & ifmt_mov32_w_r0_dst32_2_S_16_dst32_2_S_16_absolute_HI, { 0x190000 }
36695
  },
36696
/* mov.b${S} ${Dsp-8-u16},r0l */
36697
  {
36698
    { 0, 0, 0, 0 },
36699
    { { MNEM, OP (S), ' ', OP (DSP_8_U16), ',', 'r', '0', 'l', 0 } },
36700
    & ifmt_mov32_b_r0l_dst32_2_S_16_dst32_2_S_16_absolute_QI, { 0x180000 }
36701
  },
36702
/* mov.b${S} ${SrcDst16-r0l-r0h-S-normal} */
36703
  {
36704
    { 0, 0, 0, 0 },
36705
    { { MNEM, OP (S), ' ', OP (SRCDST16_R0L_R0H_S_NORMAL), 0 } },
36706
    & ifmt_or16_b_S_r0l_r0h_srcdst16_r0l_r0h_S_derived, { 0x8 }
36707
  },
36708
/* mov.b${S} ${Dsp-8-u8}[sb],${Dst16RnQI-S} */
36709
  {
36710
    { 0, 0, 0, 0 },
36711
    { { MNEM, OP (S), ' ', OP (DSP_8_U8), '[', 's', 'b', ']', ',', OP (DST16RNQI_S), 0 } },
36712
    & ifmt_or16_b_S_src2_src16_2_S_8_SB_relative_QI, { 0x900 }
36713
  },
36714
/* mov.b${S} ${Dsp-8-s8}[fb],${Dst16RnQI-S} */
36715
  {
36716
    { 0, 0, 0, 0 },
36717
    { { MNEM, OP (S), ' ', OP (DSP_8_S8), '[', 'f', 'b', ']', ',', OP (DST16RNQI_S), 0 } },
36718
    & ifmt_or16_b_S_src2_src16_2_S_8_FB_relative_QI, { 0xa00 }
36719
  },
36720
/* mov.b${S} ${Dsp-8-u16},${Dst16RnQI-S} */
36721
  {
36722
    { 0, 0, 0, 0 },
36723
    { { MNEM, OP (S), ' ', OP (DSP_8_U16), ',', OP (DST16RNQI_S), 0 } },
36724
    & ifmt_or16_b_S_src2_src16_2_S_16_absolute_QI, { 0xb0000 }
36725
  },
36726
/* mov.b${S} ${Dst16RnQI-S},${Dsp-8-u8}[sb] */
36727
  {
36728
    { 0, 0, 0, 0 },
36729
    { { MNEM, OP (S), ' ', OP (DST16RNQI_S), ',', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } },
36730
    & ifmt_or16_b_S_src2_src16_2_S_8_SB_relative_QI, { 0x100 }
36731
  },
36732
/* mov.b${S} ${Dst16RnQI-S},${Dsp-8-s8}[fb] */
36733
  {
36734
    { 0, 0, 0, 0 },
36735
    { { MNEM, OP (S), ' ', OP (DST16RNQI_S), ',', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } },
36736
    & ifmt_or16_b_S_src2_src16_2_S_8_FB_relative_QI, { 0x200 }
36737
  },
36738
/* mov.b${S} ${Dst16RnQI-S},${Dsp-8-u16} */
36739
  {
36740
    { 0, 0, 0, 0 },
36741
    { { MNEM, OP (S), ' ', OP (DST16RNQI_S), ',', OP (DSP_8_U16), 0 } },
36742
    & ifmt_or16_b_S_src2_src16_2_S_16_absolute_QI, { 0x30000 }
36743
  },
36744
/* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
36745
  {
36746
    { 0, 0, 0, 0 },
36747
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
36748
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0x990300 }
36749
  },
36750
/* mov.l${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedSI */
36751
  {
36752
    { 0, 0, 0, 0 },
36753
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
36754
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0x992300 }
36755
  },
36756
/* mov.l${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedSI */
36757
  {
36758
    { 0, 0, 0, 0 },
36759
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
36760
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0x993300 }
36761
  },
36762
/* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
36763
  {
36764
    { 0, 0, 0, 0 },
36765
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
36766
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0x918300 }
36767
  },
36768
/* mov.l${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedSI */
36769
  {
36770
    { 0, 0, 0, 0 },
36771
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
36772
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0x91a300 }
36773
  },
36774
/* mov.l${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedSI */
36775
  {
36776
    { 0, 0, 0, 0 },
36777
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
36778
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0x91b300 }
36779
  },
36780
/* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
36781
  {
36782
    { 0, 0, 0, 0 },
36783
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
36784
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0x910300 }
36785
  },
36786
/* mov.l${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
36787
  {
36788
    { 0, 0, 0, 0 },
36789
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
36790
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0x912300 }
36791
  },
36792
/* mov.l${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
36793
  {
36794
    { 0, 0, 0, 0 },
36795
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
36796
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0x913300 }
36797
  },
36798
/* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
36799
  {
36800
    { 0, 0, 0, 0 },
36801
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
36802
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_8_An_relative_Unprefixed_SI, { 0x93030000 }
36803
  },
36804
/* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
36805
  {
36806
    { 0, 0, 0, 0 },
36807
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
36808
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_8_An_relative_Unprefixed_SI, { 0x93230000 }
36809
  },
36810
/* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
36811
  {
36812
    { 0, 0, 0, 0 },
36813
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
36814
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_8_An_relative_Unprefixed_SI, { 0x93330000 }
36815
  },
36816
/* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
36817
  {
36818
    { 0, 0, 0, 0 },
36819
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
36820
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_16_An_relative_Unprefixed_SI, { 0x95030000 }
36821
  },
36822
/* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
36823
  {
36824
    { 0, 0, 0, 0 },
36825
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
36826
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_16_An_relative_Unprefixed_SI, { 0x95230000 }
36827
  },
36828
/* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
36829
  {
36830
    { 0, 0, 0, 0 },
36831
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
36832
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_16_An_relative_Unprefixed_SI, { 0x95330000 }
36833
  },
36834
/* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
36835
  {
36836
    { 0, 0, 0, 0 },
36837
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
36838
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_24_An_relative_Unprefixed_SI, { 0x97030000 }
36839
  },
36840
/* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
36841
  {
36842
    { 0, 0, 0, 0 },
36843
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
36844
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_24_An_relative_Unprefixed_SI, { 0x97230000 }
36845
  },
36846
/* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
36847
  {
36848
    { 0, 0, 0, 0 },
36849
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
36850
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_24_An_relative_Unprefixed_SI, { 0x97330000 }
36851
  },
36852
/* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
36853
  {
36854
    { 0, 0, 0, 0 },
36855
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
36856
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_8_SB_relative_Unprefixed_SI, { 0x93830000 }
36857
  },
36858
/* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
36859
  {
36860
    { 0, 0, 0, 0 },
36861
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
36862
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_8_SB_relative_Unprefixed_SI, { 0x93a30000 }
36863
  },
36864
/* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
36865
  {
36866
    { 0, 0, 0, 0 },
36867
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
36868
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_8_SB_relative_Unprefixed_SI, { 0x93b30000 }
36869
  },
36870
/* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
36871
  {
36872
    { 0, 0, 0, 0 },
36873
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
36874
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_16_SB_relative_Unprefixed_SI, { 0x95830000 }
36875
  },
36876
/* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
36877
  {
36878
    { 0, 0, 0, 0 },
36879
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
36880
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_16_SB_relative_Unprefixed_SI, { 0x95a30000 }
36881
  },
36882
/* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
36883
  {
36884
    { 0, 0, 0, 0 },
36885
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
36886
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_16_SB_relative_Unprefixed_SI, { 0x95b30000 }
36887
  },
36888
/* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
36889
  {
36890
    { 0, 0, 0, 0 },
36891
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
36892
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_8_FB_relative_Unprefixed_SI, { 0x93c30000 }
36893
  },
36894
/* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
36895
  {
36896
    { 0, 0, 0, 0 },
36897
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
36898
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_8_FB_relative_Unprefixed_SI, { 0x93e30000 }
36899
  },
36900
/* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
36901
  {
36902
    { 0, 0, 0, 0 },
36903
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
36904
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_8_FB_relative_Unprefixed_SI, { 0x93f30000 }
36905
  },
36906
/* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
36907
  {
36908
    { 0, 0, 0, 0 },
36909
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
36910
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_16_FB_relative_Unprefixed_SI, { 0x95c30000 }
36911
  },
36912
/* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
36913
  {
36914
    { 0, 0, 0, 0 },
36915
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
36916
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_16_FB_relative_Unprefixed_SI, { 0x95e30000 }
36917
  },
36918
/* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
36919
  {
36920
    { 0, 0, 0, 0 },
36921
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
36922
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_16_FB_relative_Unprefixed_SI, { 0x95f30000 }
36923
  },
36924
/* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
36925
  {
36926
    { 0, 0, 0, 0 },
36927
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
36928
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_16_absolute_Unprefixed_SI, { 0x97c30000 }
36929
  },
36930
/* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
36931
  {
36932
    { 0, 0, 0, 0 },
36933
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
36934
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_16_absolute_Unprefixed_SI, { 0x97e30000 }
36935
  },
36936
/* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
36937
  {
36938
    { 0, 0, 0, 0 },
36939
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
36940
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_16_absolute_Unprefixed_SI, { 0x97f30000 }
36941
  },
36942
/* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
36943
  {
36944
    { 0, 0, 0, 0 },
36945
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
36946
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_24_absolute_Unprefixed_SI, { 0x97830000 }
36947
  },
36948
/* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
36949
  {
36950
    { 0, 0, 0, 0 },
36951
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } },
36952
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_24_absolute_Unprefixed_SI, { 0x97a30000 }
36953
  },
36954
/* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
36955
  {
36956
    { 0, 0, 0, 0 },
36957
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } },
36958
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_24_absolute_Unprefixed_SI, { 0x97b30000 }
36959
  },
36960
/* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
36961
  {
36962
    { 0, 0, 0, 0 },
36963
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
36964
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xa9030000 }
36965
  },
36966
/* mov.l${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedSI */
36967
  {
36968
    { 0, 0, 0, 0 },
36969
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
36970
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xa9230000 }
36971
  },
36972
/* mov.l${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedSI */
36973
  {
36974
    { 0, 0, 0, 0 },
36975
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
36976
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xa9330000 }
36977
  },
36978
/* mov.l${G} ${Dsp-16-u16},$Dst32RnUnprefixedSI */
36979
  {
36980
    { 0, 0, 0, 0 },
36981
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
36982
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xb9330000 }
36983
  },
36984
/* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
36985
  {
36986
    { 0, 0, 0, 0 },
36987
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
36988
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xa1830000 }
36989
  },
36990
/* mov.l${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedSI */
36991
  {
36992
    { 0, 0, 0, 0 },
36993
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
36994
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xa1a30000 }
36995
  },
36996
/* mov.l${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedSI */
36997
  {
36998
    { 0, 0, 0, 0 },
36999
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
37000
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xa1b30000 }
37001
  },
37002
/* mov.l${G} ${Dsp-16-u16},$Dst32AnUnprefixedSI */
37003
  {
37004
    { 0, 0, 0, 0 },
37005
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
37006
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xb1b30000 }
37007
  },
37008
/* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
37009
  {
37010
    { 0, 0, 0, 0 },
37011
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37012
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xa1030000 }
37013
  },
37014
/* mov.l${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
37015
  {
37016
    { 0, 0, 0, 0 },
37017
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37018
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xa1230000 }
37019
  },
37020
/* mov.l${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
37021
  {
37022
    { 0, 0, 0, 0 },
37023
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37024
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xa1330000 }
37025
  },
37026
/* mov.l${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
37027
  {
37028
    { 0, 0, 0, 0 },
37029
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37030
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xb1330000 }
37031
  },
37032
/* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
37033
  {
37034
    { 0, 0, 0, 0 },
37035
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37036
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_8_An_relative_Unprefixed_SI, { 0xa3030000 }
37037
  },
37038
/* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
37039
  {
37040
    { 0, 0, 0, 0 },
37041
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37042
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_8_An_relative_Unprefixed_SI, { 0xa3230000 }
37043
  },
37044
/* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
37045
  {
37046
    { 0, 0, 0, 0 },
37047
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37048
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_8_An_relative_Unprefixed_SI, { 0xa3330000 }
37049
  },
37050
/* mov.l${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
37051
  {
37052
    { 0, 0, 0, 0 },
37053
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37054
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_8_An_relative_Unprefixed_SI, { 0xb3330000 }
37055
  },
37056
/* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
37057
  {
37058
    { 0, 0, 0, 0 },
37059
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37060
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_16_An_relative_Unprefixed_SI, { 0xa5030000 }
37061
  },
37062
/* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
37063
  {
37064
    { 0, 0, 0, 0 },
37065
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37066
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_16_An_relative_Unprefixed_SI, { 0xa5230000 }
37067
  },
37068
/* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
37069
  {
37070
    { 0, 0, 0, 0 },
37071
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37072
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_16_An_relative_Unprefixed_SI, { 0xa5330000 }
37073
  },
37074
/* mov.l${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
37075
  {
37076
    { 0, 0, 0, 0 },
37077
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37078
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_16_An_relative_Unprefixed_SI, { 0xb5330000 }
37079
  },
37080
/* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
37081
  {
37082
    { 0, 0, 0, 0 },
37083
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37084
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_24_An_relative_Unprefixed_SI, { 0xa7030000 }
37085
  },
37086
/* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
37087
  {
37088
    { 0, 0, 0, 0 },
37089
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37090
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_24_An_relative_Unprefixed_SI, { 0xa7230000 }
37091
  },
37092
/* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
37093
  {
37094
    { 0, 0, 0, 0 },
37095
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37096
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_24_An_relative_Unprefixed_SI, { 0xa7330000 }
37097
  },
37098
/* mov.l${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
37099
  {
37100
    { 0, 0, 0, 0 },
37101
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37102
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_24_An_relative_Unprefixed_SI, { 0xb7330000 }
37103
  },
37104
/* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
37105
  {
37106
    { 0, 0, 0, 0 },
37107
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
37108
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xa3830000 }
37109
  },
37110
/* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
37111
  {
37112
    { 0, 0, 0, 0 },
37113
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
37114
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xa3a30000 }
37115
  },
37116
/* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
37117
  {
37118
    { 0, 0, 0, 0 },
37119
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
37120
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xa3b30000 }
37121
  },
37122
/* mov.l${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
37123
  {
37124
    { 0, 0, 0, 0 },
37125
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
37126
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xb3b30000 }
37127
  },
37128
/* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
37129
  {
37130
    { 0, 0, 0, 0 },
37131
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
37132
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xa5830000 }
37133
  },
37134
/* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
37135
  {
37136
    { 0, 0, 0, 0 },
37137
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
37138
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xa5a30000 }
37139
  },
37140
/* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
37141
  {
37142
    { 0, 0, 0, 0 },
37143
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
37144
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xa5b30000 }
37145
  },
37146
/* mov.l${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
37147
  {
37148
    { 0, 0, 0, 0 },
37149
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
37150
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xb5b30000 }
37151
  },
37152
/* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
37153
  {
37154
    { 0, 0, 0, 0 },
37155
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
37156
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xa3c30000 }
37157
  },
37158
/* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
37159
  {
37160
    { 0, 0, 0, 0 },
37161
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
37162
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xa3e30000 }
37163
  },
37164
/* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
37165
  {
37166
    { 0, 0, 0, 0 },
37167
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
37168
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xa3f30000 }
37169
  },
37170
/* mov.l${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
37171
  {
37172
    { 0, 0, 0, 0 },
37173
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
37174
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xb3f30000 }
37175
  },
37176
/* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
37177
  {
37178
    { 0, 0, 0, 0 },
37179
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
37180
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xa5c30000 }
37181
  },
37182
/* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
37183
  {
37184
    { 0, 0, 0, 0 },
37185
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
37186
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xa5e30000 }
37187
  },
37188
/* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
37189
  {
37190
    { 0, 0, 0, 0 },
37191
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
37192
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xa5f30000 }
37193
  },
37194
/* mov.l${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
37195
  {
37196
    { 0, 0, 0, 0 },
37197
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
37198
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xb5f30000 }
37199
  },
37200
/* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
37201
  {
37202
    { 0, 0, 0, 0 },
37203
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
37204
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_16_absolute_Unprefixed_SI, { 0xa7c30000 }
37205
  },
37206
/* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
37207
  {
37208
    { 0, 0, 0, 0 },
37209
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
37210
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_16_absolute_Unprefixed_SI, { 0xa7e30000 }
37211
  },
37212
/* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
37213
  {
37214
    { 0, 0, 0, 0 },
37215
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
37216
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_16_absolute_Unprefixed_SI, { 0xa7f30000 }
37217
  },
37218
/* mov.l${G} ${Dsp-16-u16},${Dsp-32-u16} */
37219
  {
37220
    { 0, 0, 0, 0 },
37221
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
37222
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_16_absolute_Unprefixed_SI, { 0xb7f30000 }
37223
  },
37224
/* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
37225
  {
37226
    { 0, 0, 0, 0 },
37227
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
37228
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_24_absolute_Unprefixed_SI, { 0xa7830000 }
37229
  },
37230
/* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
37231
  {
37232
    { 0, 0, 0, 0 },
37233
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
37234
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_24_absolute_Unprefixed_SI, { 0xa7a30000 }
37235
  },
37236
/* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
37237
  {
37238
    { 0, 0, 0, 0 },
37239
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
37240
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_24_absolute_Unprefixed_SI, { 0xa7b30000 }
37241
  },
37242
/* mov.l${G} ${Dsp-16-u16},${Dsp-32-u24} */
37243
  {
37244
    { 0, 0, 0, 0 },
37245
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } },
37246
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_24_absolute_Unprefixed_SI, { 0xb7b30000 }
37247
  },
37248
/* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
37249
  {
37250
    { 0, 0, 0, 0 },
37251
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
37252
    & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xb9030000 }
37253
  },
37254
/* mov.l${G} ${Dsp-16-u24},$Dst32RnUnprefixedSI */
37255
  {
37256
    { 0, 0, 0, 0 },
37257
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
37258
    & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xb9230000 }
37259
  },
37260
/* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
37261
  {
37262
    { 0, 0, 0, 0 },
37263
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
37264
    & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xb1830000 }
37265
  },
37266
/* mov.l${G} ${Dsp-16-u24},$Dst32AnUnprefixedSI */
37267
  {
37268
    { 0, 0, 0, 0 },
37269
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
37270
    & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xb1a30000 }
37271
  },
37272
/* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
37273
  {
37274
    { 0, 0, 0, 0 },
37275
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37276
    & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xb1030000 }
37277
  },
37278
/* mov.l${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
37279
  {
37280
    { 0, 0, 0, 0 },
37281
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37282
    & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xb1230000 }
37283
  },
37284
/* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
37285
  {
37286
    { 0, 0, 0, 0 },
37287
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37288
    & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_8_An_relative_Unprefixed_SI, { 0xb3030000 }
37289
  },
37290
/* mov.l${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
37291
  {
37292
    { 0, 0, 0, 0 },
37293
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37294
    & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_8_An_relative_Unprefixed_SI, { 0xb3230000 }
37295
  },
37296
/* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
37297
  {
37298
    { 0, 0, 0, 0 },
37299
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37300
    & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_16_An_relative_Unprefixed_SI, { 0xb5030000 }
37301
  },
37302
/* mov.l${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
37303
  {
37304
    { 0, 0, 0, 0 },
37305
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37306
    & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_16_An_relative_Unprefixed_SI, { 0xb5230000 }
37307
  },
37308
/* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
37309
  {
37310
    { 0, 0, 0, 0 },
37311
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37312
    & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_24_An_relative_Unprefixed_SI, { 0xb7030000 }
37313
  },
37314
/* mov.l${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
37315
  {
37316
    { 0, 0, 0, 0 },
37317
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37318
    & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_24_An_relative_Unprefixed_SI, { 0xb7230000 }
37319
  },
37320
/* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
37321
  {
37322
    { 0, 0, 0, 0 },
37323
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
37324
    & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_8_SB_relative_Unprefixed_SI, { 0xb3830000 }
37325
  },
37326
/* mov.l${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
37327
  {
37328
    { 0, 0, 0, 0 },
37329
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
37330
    & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_8_SB_relative_Unprefixed_SI, { 0xb3a30000 }
37331
  },
37332
/* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
37333
  {
37334
    { 0, 0, 0, 0 },
37335
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
37336
    & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_16_SB_relative_Unprefixed_SI, { 0xb5830000 }
37337
  },
37338
/* mov.l${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
37339
  {
37340
    { 0, 0, 0, 0 },
37341
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
37342
    & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_16_SB_relative_Unprefixed_SI, { 0xb5a30000 }
37343
  },
37344
/* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
37345
  {
37346
    { 0, 0, 0, 0 },
37347
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
37348
    & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_8_FB_relative_Unprefixed_SI, { 0xb3c30000 }
37349
  },
37350
/* mov.l${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
37351
  {
37352
    { 0, 0, 0, 0 },
37353
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
37354
    & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_8_FB_relative_Unprefixed_SI, { 0xb3e30000 }
37355
  },
37356
/* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
37357
  {
37358
    { 0, 0, 0, 0 },
37359
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
37360
    & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_16_FB_relative_Unprefixed_SI, { 0xb5c30000 }
37361
  },
37362
/* mov.l${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
37363
  {
37364
    { 0, 0, 0, 0 },
37365
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
37366
    & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_16_FB_relative_Unprefixed_SI, { 0xb5e30000 }
37367
  },
37368
/* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
37369
  {
37370
    { 0, 0, 0, 0 },
37371
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
37372
    & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_16_absolute_Unprefixed_SI, { 0xb7c30000 }
37373
  },
37374
/* mov.l${G} ${Dsp-16-u24},${Dsp-40-u16} */
37375
  {
37376
    { 0, 0, 0, 0 },
37377
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } },
37378
    & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_16_absolute_Unprefixed_SI, { 0xb7e30000 }
37379
  },
37380
/* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
37381
  {
37382
    { 0, 0, 0, 0 },
37383
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
37384
    & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_24_absolute_Unprefixed_SI, { 0xb7830000 }
37385
  },
37386
/* mov.l${G} ${Dsp-16-u24},${Dsp-40-u24} */
37387
  {
37388
    { 0, 0, 0, 0 },
37389
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } },
37390
    & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_24_absolute_Unprefixed_SI, { 0xb7a30000 }
37391
  },
37392
/* mov.l${G} $Src32RnUnprefixedSI,$Dst32RnUnprefixedSI */
37393
  {
37394
    { 0, 0, 0, 0 },
37395
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
37396
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xc903 }
37397
  },
37398
/* mov.l${G} $Src32AnUnprefixedSI,$Dst32RnUnprefixedSI */
37399
  {
37400
    { 0, 0, 0, 0 },
37401
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
37402
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0x8923 }
37403
  },
37404
/* mov.l${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
37405
  {
37406
    { 0, 0, 0, 0 },
37407
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
37408
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0x8903 }
37409
  },
37410
/* mov.l${G} $Src32RnUnprefixedSI,$Dst32AnUnprefixedSI */
37411
  {
37412
    { 0, 0, 0, 0 },
37413
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
37414
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xc183 }
37415
  },
37416
/* mov.l${G} $Src32AnUnprefixedSI,$Dst32AnUnprefixedSI */
37417
  {
37418
    { 0, 0, 0, 0 },
37419
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
37420
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0x81a3 }
37421
  },
37422
/* mov.l${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
37423
  {
37424
    { 0, 0, 0, 0 },
37425
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
37426
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0x8183 }
37427
  },
37428
/* mov.l${G} $Src32RnUnprefixedSI,[$Dst32AnUnprefixed] */
37429
  {
37430
    { 0, 0, 0, 0 },
37431
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37432
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xc103 }
37433
  },
37434
/* mov.l${G} $Src32AnUnprefixedSI,[$Dst32AnUnprefixed] */
37435
  {
37436
    { 0, 0, 0, 0 },
37437
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37438
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0x8123 }
37439
  },
37440
/* mov.l${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
37441
  {
37442
    { 0, 0, 0, 0 },
37443
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37444
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0x8103 }
37445
  },
37446
/* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
37447
  {
37448
    { 0, 0, 0, 0 },
37449
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37450
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_8_An_relative_Unprefixed_SI, { 0xc30300 }
37451
  },
37452
/* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
37453
  {
37454
    { 0, 0, 0, 0 },
37455
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37456
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_8_An_relative_Unprefixed_SI, { 0x832300 }
37457
  },
37458
/* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
37459
  {
37460
    { 0, 0, 0, 0 },
37461
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37462
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_8_An_relative_Unprefixed_SI, { 0x830300 }
37463
  },
37464
/* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
37465
  {
37466
    { 0, 0, 0, 0 },
37467
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37468
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_16_An_relative_Unprefixed_SI, { 0xc5030000 }
37469
  },
37470
/* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
37471
  {
37472
    { 0, 0, 0, 0 },
37473
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37474
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_16_An_relative_Unprefixed_SI, { 0x85230000 }
37475
  },
37476
/* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
37477
  {
37478
    { 0, 0, 0, 0 },
37479
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37480
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_16_An_relative_Unprefixed_SI, { 0x85030000 }
37481
  },
37482
/* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
37483
  {
37484
    { 0, 0, 0, 0 },
37485
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37486
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_24_An_relative_Unprefixed_SI, { 0xc7030000 }
37487
  },
37488
/* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
37489
  {
37490
    { 0, 0, 0, 0 },
37491
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37492
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_24_An_relative_Unprefixed_SI, { 0x87230000 }
37493
  },
37494
/* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
37495
  {
37496
    { 0, 0, 0, 0 },
37497
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37498
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_24_An_relative_Unprefixed_SI, { 0x87030000 }
37499
  },
37500
/* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-u8}[sb] */
37501
  {
37502
    { 0, 0, 0, 0 },
37503
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
37504
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_8_SB_relative_Unprefixed_SI, { 0xc38300 }
37505
  },
37506
/* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-u8}[sb] */
37507
  {
37508
    { 0, 0, 0, 0 },
37509
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
37510
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_8_SB_relative_Unprefixed_SI, { 0x83a300 }
37511
  },
37512
/* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
37513
  {
37514
    { 0, 0, 0, 0 },
37515
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
37516
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_8_SB_relative_Unprefixed_SI, { 0x838300 }
37517
  },
37518
/* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16}[sb] */
37519
  {
37520
    { 0, 0, 0, 0 },
37521
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
37522
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_16_SB_relative_Unprefixed_SI, { 0xc5830000 }
37523
  },
37524
/* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16}[sb] */
37525
  {
37526
    { 0, 0, 0, 0 },
37527
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
37528
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_16_SB_relative_Unprefixed_SI, { 0x85a30000 }
37529
  },
37530
/* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
37531
  {
37532
    { 0, 0, 0, 0 },
37533
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
37534
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_16_SB_relative_Unprefixed_SI, { 0x85830000 }
37535
  },
37536
/* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-s8}[fb] */
37537
  {
37538
    { 0, 0, 0, 0 },
37539
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
37540
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_8_FB_relative_Unprefixed_SI, { 0xc3c300 }
37541
  },
37542
/* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-s8}[fb] */
37543
  {
37544
    { 0, 0, 0, 0 },
37545
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
37546
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_8_FB_relative_Unprefixed_SI, { 0x83e300 }
37547
  },
37548
/* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
37549
  {
37550
    { 0, 0, 0, 0 },
37551
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
37552
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_8_FB_relative_Unprefixed_SI, { 0x83c300 }
37553
  },
37554
/* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-s16}[fb] */
37555
  {
37556
    { 0, 0, 0, 0 },
37557
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
37558
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_16_FB_relative_Unprefixed_SI, { 0xc5c30000 }
37559
  },
37560
/* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-s16}[fb] */
37561
  {
37562
    { 0, 0, 0, 0 },
37563
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
37564
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_16_FB_relative_Unprefixed_SI, { 0x85e30000 }
37565
  },
37566
/* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
37567
  {
37568
    { 0, 0, 0, 0 },
37569
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
37570
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_16_FB_relative_Unprefixed_SI, { 0x85c30000 }
37571
  },
37572
/* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16} */
37573
  {
37574
    { 0, 0, 0, 0 },
37575
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U16), 0 } },
37576
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_16_absolute_Unprefixed_SI, { 0xc7c30000 }
37577
  },
37578
/* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16} */
37579
  {
37580
    { 0, 0, 0, 0 },
37581
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U16), 0 } },
37582
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_16_absolute_Unprefixed_SI, { 0x87e30000 }
37583
  },
37584
/* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
37585
  {
37586
    { 0, 0, 0, 0 },
37587
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } },
37588
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_16_absolute_Unprefixed_SI, { 0x87c30000 }
37589
  },
37590
/* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-u24} */
37591
  {
37592
    { 0, 0, 0, 0 },
37593
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U24), 0 } },
37594
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_24_absolute_Unprefixed_SI, { 0xc7830000 }
37595
  },
37596
/* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-u24} */
37597
  {
37598
    { 0, 0, 0, 0 },
37599
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U24), 0 } },
37600
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_24_absolute_Unprefixed_SI, { 0x87a30000 }
37601
  },
37602
/* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
37603
  {
37604
    { 0, 0, 0, 0 },
37605
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } },
37606
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_24_absolute_Unprefixed_SI, { 0x87830000 }
37607
  },
37608
/* mov.b${S} ${Dsp-8-u8}[sb],${Dst16AnQI-S} */
37609
  {
37610
    { 0, 0, 0, 0 },
37611
    { { MNEM, OP (S), ' ', OP (DSP_8_U8), '[', 's', 'b', ']', ',', OP (DST16ANQI_S), 0 } },
37612
    & ifmt_mov16_b_S_An_src16_2_S_8_SB_relative_QI, { 0x3100 }
37613
  },
37614
/* mov.b${S} ${Dsp-8-s8}[fb],${Dst16AnQI-S} */
37615
  {
37616
    { 0, 0, 0, 0 },
37617
    { { MNEM, OP (S), ' ', OP (DSP_8_S8), '[', 'f', 'b', ']', ',', OP (DST16ANQI_S), 0 } },
37618
    & ifmt_mov16_b_S_An_src16_2_S_8_FB_relative_QI, { 0x3200 }
37619
  },
37620
/* mov.b${S} ${Dsp-8-u16},${Dst16AnQI-S} */
37621
  {
37622
    { 0, 0, 0, 0 },
37623
    { { MNEM, OP (S), ' ', OP (DSP_8_U16), ',', OP (DST16ANQI_S), 0 } },
37624
    & ifmt_mov16_b_S_An_src16_2_S_16_absolute_QI, { 0x330000 }
37625
  },
37626
/* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
37627
  {
37628
    { 0, 0, 0, 0 },
37629
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
37630
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x990b00 }
37631
  },
37632
/* mov.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */
37633
  {
37634
    { 0, 0, 0, 0 },
37635
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
37636
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x992b00 }
37637
  },
37638
/* mov.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */
37639
  {
37640
    { 0, 0, 0, 0 },
37641
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
37642
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x993b00 }
37643
  },
37644
/* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
37645
  {
37646
    { 0, 0, 0, 0 },
37647
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
37648
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x918b00 }
37649
  },
37650
/* mov.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */
37651
  {
37652
    { 0, 0, 0, 0 },
37653
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
37654
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x91ab00 }
37655
  },
37656
/* mov.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */
37657
  {
37658
    { 0, 0, 0, 0 },
37659
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
37660
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x91bb00 }
37661
  },
37662
/* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
37663
  {
37664
    { 0, 0, 0, 0 },
37665
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37666
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x910b00 }
37667
  },
37668
/* mov.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
37669
  {
37670
    { 0, 0, 0, 0 },
37671
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37672
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x912b00 }
37673
  },
37674
/* mov.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
37675
  {
37676
    { 0, 0, 0, 0 },
37677
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37678
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x913b00 }
37679
  },
37680
/* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
37681
  {
37682
    { 0, 0, 0, 0 },
37683
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37684
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x930b0000 }
37685
  },
37686
/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
37687
  {
37688
    { 0, 0, 0, 0 },
37689
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37690
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x932b0000 }
37691
  },
37692
/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
37693
  {
37694
    { 0, 0, 0, 0 },
37695
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37696
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x933b0000 }
37697
  },
37698
/* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
37699
  {
37700
    { 0, 0, 0, 0 },
37701
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37702
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x950b0000 }
37703
  },
37704
/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
37705
  {
37706
    { 0, 0, 0, 0 },
37707
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37708
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x952b0000 }
37709
  },
37710
/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
37711
  {
37712
    { 0, 0, 0, 0 },
37713
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37714
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x953b0000 }
37715
  },
37716
/* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
37717
  {
37718
    { 0, 0, 0, 0 },
37719
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37720
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x970b0000 }
37721
  },
37722
/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
37723
  {
37724
    { 0, 0, 0, 0 },
37725
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37726
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x972b0000 }
37727
  },
37728
/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
37729
  {
37730
    { 0, 0, 0, 0 },
37731
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37732
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x973b0000 }
37733
  },
37734
/* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
37735
  {
37736
    { 0, 0, 0, 0 },
37737
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
37738
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x938b0000 }
37739
  },
37740
/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
37741
  {
37742
    { 0, 0, 0, 0 },
37743
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
37744
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93ab0000 }
37745
  },
37746
/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
37747
  {
37748
    { 0, 0, 0, 0 },
37749
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
37750
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93bb0000 }
37751
  },
37752
/* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
37753
  {
37754
    { 0, 0, 0, 0 },
37755
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
37756
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x958b0000 }
37757
  },
37758
/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
37759
  {
37760
    { 0, 0, 0, 0 },
37761
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
37762
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95ab0000 }
37763
  },
37764
/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
37765
  {
37766
    { 0, 0, 0, 0 },
37767
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
37768
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95bb0000 }
37769
  },
37770
/* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
37771
  {
37772
    { 0, 0, 0, 0 },
37773
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
37774
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93cb0000 }
37775
  },
37776
/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
37777
  {
37778
    { 0, 0, 0, 0 },
37779
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
37780
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93eb0000 }
37781
  },
37782
/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
37783
  {
37784
    { 0, 0, 0, 0 },
37785
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
37786
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93fb0000 }
37787
  },
37788
/* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
37789
  {
37790
    { 0, 0, 0, 0 },
37791
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
37792
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95cb0000 }
37793
  },
37794
/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
37795
  {
37796
    { 0, 0, 0, 0 },
37797
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
37798
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95eb0000 }
37799
  },
37800
/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
37801
  {
37802
    { 0, 0, 0, 0 },
37803
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
37804
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95fb0000 }
37805
  },
37806
/* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
37807
  {
37808
    { 0, 0, 0, 0 },
37809
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
37810
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97cb0000 }
37811
  },
37812
/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
37813
  {
37814
    { 0, 0, 0, 0 },
37815
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
37816
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97eb0000 }
37817
  },
37818
/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
37819
  {
37820
    { 0, 0, 0, 0 },
37821
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
37822
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97fb0000 }
37823
  },
37824
/* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
37825
  {
37826
    { 0, 0, 0, 0 },
37827
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
37828
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x978b0000 }
37829
  },
37830
/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
37831
  {
37832
    { 0, 0, 0, 0 },
37833
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } },
37834
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97ab0000 }
37835
  },
37836
/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
37837
  {
37838
    { 0, 0, 0, 0 },
37839
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } },
37840
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97bb0000 }
37841
  },
37842
/* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
37843
  {
37844
    { 0, 0, 0, 0 },
37845
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
37846
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa90b0000 }
37847
  },
37848
/* mov.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */
37849
  {
37850
    { 0, 0, 0, 0 },
37851
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
37852
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa92b0000 }
37853
  },
37854
/* mov.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */
37855
  {
37856
    { 0, 0, 0, 0 },
37857
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
37858
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa93b0000 }
37859
  },
37860
/* mov.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */
37861
  {
37862
    { 0, 0, 0, 0 },
37863
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
37864
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb93b0000 }
37865
  },
37866
/* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
37867
  {
37868
    { 0, 0, 0, 0 },
37869
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
37870
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa18b0000 }
37871
  },
37872
/* mov.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */
37873
  {
37874
    { 0, 0, 0, 0 },
37875
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
37876
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1ab0000 }
37877
  },
37878
/* mov.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */
37879
  {
37880
    { 0, 0, 0, 0 },
37881
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
37882
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1bb0000 }
37883
  },
37884
/* mov.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */
37885
  {
37886
    { 0, 0, 0, 0 },
37887
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
37888
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1bb0000 }
37889
  },
37890
/* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
37891
  {
37892
    { 0, 0, 0, 0 },
37893
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37894
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa10b0000 }
37895
  },
37896
/* mov.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
37897
  {
37898
    { 0, 0, 0, 0 },
37899
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37900
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa12b0000 }
37901
  },
37902
/* mov.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
37903
  {
37904
    { 0, 0, 0, 0 },
37905
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37906
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa13b0000 }
37907
  },
37908
/* mov.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
37909
  {
37910
    { 0, 0, 0, 0 },
37911
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37912
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb13b0000 }
37913
  },
37914
/* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
37915
  {
37916
    { 0, 0, 0, 0 },
37917
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37918
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa30b0000 }
37919
  },
37920
/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
37921
  {
37922
    { 0, 0, 0, 0 },
37923
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37924
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa32b0000 }
37925
  },
37926
/* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
37927
  {
37928
    { 0, 0, 0, 0 },
37929
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37930
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa33b0000 }
37931
  },
37932
/* mov.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
37933
  {
37934
    { 0, 0, 0, 0 },
37935
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37936
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xb33b0000 }
37937
  },
37938
/* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
37939
  {
37940
    { 0, 0, 0, 0 },
37941
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37942
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa50b0000 }
37943
  },
37944
/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
37945
  {
37946
    { 0, 0, 0, 0 },
37947
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37948
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa52b0000 }
37949
  },
37950
/* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
37951
  {
37952
    { 0, 0, 0, 0 },
37953
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37954
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa53b0000 }
37955
  },
37956
/* mov.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
37957
  {
37958
    { 0, 0, 0, 0 },
37959
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37960
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xb53b0000 }
37961
  },
37962
/* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
37963
  {
37964
    { 0, 0, 0, 0 },
37965
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37966
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa70b0000 }
37967
  },
37968
/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
37969
  {
37970
    { 0, 0, 0, 0 },
37971
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37972
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa72b0000 }
37973
  },
37974
/* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
37975
  {
37976
    { 0, 0, 0, 0 },
37977
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37978
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa73b0000 }
37979
  },
37980
/* mov.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
37981
  {
37982
    { 0, 0, 0, 0 },
37983
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
37984
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xb73b0000 }
37985
  },
37986
/* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
37987
  {
37988
    { 0, 0, 0, 0 },
37989
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
37990
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa38b0000 }
37991
  },
37992
/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
37993
  {
37994
    { 0, 0, 0, 0 },
37995
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
37996
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3ab0000 }
37997
  },
37998
/* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
37999
  {
38000
    { 0, 0, 0, 0 },
38001
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
38002
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3bb0000 }
38003
  },
38004
/* mov.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
38005
  {
38006
    { 0, 0, 0, 0 },
38007
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
38008
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xb3bb0000 }
38009
  },
38010
/* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
38011
  {
38012
    { 0, 0, 0, 0 },
38013
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
38014
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa58b0000 }
38015
  },
38016
/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
38017
  {
38018
    { 0, 0, 0, 0 },
38019
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
38020
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5ab0000 }
38021
  },
38022
/* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
38023
  {
38024
    { 0, 0, 0, 0 },
38025
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
38026
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5bb0000 }
38027
  },
38028
/* mov.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
38029
  {
38030
    { 0, 0, 0, 0 },
38031
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
38032
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xb5bb0000 }
38033
  },
38034
/* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
38035
  {
38036
    { 0, 0, 0, 0 },
38037
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
38038
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3cb0000 }
38039
  },
38040
/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
38041
  {
38042
    { 0, 0, 0, 0 },
38043
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
38044
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3eb0000 }
38045
  },
38046
/* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
38047
  {
38048
    { 0, 0, 0, 0 },
38049
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
38050
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3fb0000 }
38051
  },
38052
/* mov.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
38053
  {
38054
    { 0, 0, 0, 0 },
38055
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
38056
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xb3fb0000 }
38057
  },
38058
/* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
38059
  {
38060
    { 0, 0, 0, 0 },
38061
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
38062
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5cb0000 }
38063
  },
38064
/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
38065
  {
38066
    { 0, 0, 0, 0 },
38067
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
38068
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5eb0000 }
38069
  },
38070
/* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
38071
  {
38072
    { 0, 0, 0, 0 },
38073
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
38074
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5fb0000 }
38075
  },
38076
/* mov.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
38077
  {
38078
    { 0, 0, 0, 0 },
38079
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
38080
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xb5fb0000 }
38081
  },
38082
/* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
38083
  {
38084
    { 0, 0, 0, 0 },
38085
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
38086
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7cb0000 }
38087
  },
38088
/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
38089
  {
38090
    { 0, 0, 0, 0 },
38091
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
38092
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7eb0000 }
38093
  },
38094
/* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
38095
  {
38096
    { 0, 0, 0, 0 },
38097
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
38098
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7fb0000 }
38099
  },
38100
/* mov.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
38101
  {
38102
    { 0, 0, 0, 0 },
38103
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
38104
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xb7fb0000 }
38105
  },
38106
/* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
38107
  {
38108
    { 0, 0, 0, 0 },
38109
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
38110
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa78b0000 }
38111
  },
38112
/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
38113
  {
38114
    { 0, 0, 0, 0 },
38115
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
38116
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7ab0000 }
38117
  },
38118
/* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
38119
  {
38120
    { 0, 0, 0, 0 },
38121
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
38122
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7bb0000 }
38123
  },
38124
/* mov.w${G} ${Dsp-16-u16},${Dsp-32-u24} */
38125
  {
38126
    { 0, 0, 0, 0 },
38127
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } },
38128
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xb7bb0000 }
38129
  },
38130
/* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
38131
  {
38132
    { 0, 0, 0, 0 },
38133
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
38134
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb90b0000 }
38135
  },
38136
/* mov.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */
38137
  {
38138
    { 0, 0, 0, 0 },
38139
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
38140
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb92b0000 }
38141
  },
38142
/* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
38143
  {
38144
    { 0, 0, 0, 0 },
38145
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
38146
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb18b0000 }
38147
  },
38148
/* mov.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */
38149
  {
38150
    { 0, 0, 0, 0 },
38151
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
38152
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1ab0000 }
38153
  },
38154
/* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
38155
  {
38156
    { 0, 0, 0, 0 },
38157
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38158
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb10b0000 }
38159
  },
38160
/* mov.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
38161
  {
38162
    { 0, 0, 0, 0 },
38163
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38164
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb12b0000 }
38165
  },
38166
/* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
38167
  {
38168
    { 0, 0, 0, 0 },
38169
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38170
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_An_relative_Unprefixed_HI, { 0xb30b0000 }
38171
  },
38172
/* mov.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
38173
  {
38174
    { 0, 0, 0, 0 },
38175
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38176
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_An_relative_Unprefixed_HI, { 0xb32b0000 }
38177
  },
38178
/* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
38179
  {
38180
    { 0, 0, 0, 0 },
38181
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38182
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_An_relative_Unprefixed_HI, { 0xb50b0000 }
38183
  },
38184
/* mov.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
38185
  {
38186
    { 0, 0, 0, 0 },
38187
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38188
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_An_relative_Unprefixed_HI, { 0xb52b0000 }
38189
  },
38190
/* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
38191
  {
38192
    { 0, 0, 0, 0 },
38193
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38194
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_24_An_relative_Unprefixed_HI, { 0xb70b0000 }
38195
  },
38196
/* mov.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
38197
  {
38198
    { 0, 0, 0, 0 },
38199
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38200
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_24_An_relative_Unprefixed_HI, { 0xb72b0000 }
38201
  },
38202
/* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
38203
  {
38204
    { 0, 0, 0, 0 },
38205
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
38206
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_SB_relative_Unprefixed_HI, { 0xb38b0000 }
38207
  },
38208
/* mov.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
38209
  {
38210
    { 0, 0, 0, 0 },
38211
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
38212
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_SB_relative_Unprefixed_HI, { 0xb3ab0000 }
38213
  },
38214
/* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
38215
  {
38216
    { 0, 0, 0, 0 },
38217
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
38218
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_SB_relative_Unprefixed_HI, { 0xb58b0000 }
38219
  },
38220
/* mov.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
38221
  {
38222
    { 0, 0, 0, 0 },
38223
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
38224
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_SB_relative_Unprefixed_HI, { 0xb5ab0000 }
38225
  },
38226
/* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
38227
  {
38228
    { 0, 0, 0, 0 },
38229
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
38230
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_FB_relative_Unprefixed_HI, { 0xb3cb0000 }
38231
  },
38232
/* mov.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
38233
  {
38234
    { 0, 0, 0, 0 },
38235
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
38236
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_FB_relative_Unprefixed_HI, { 0xb3eb0000 }
38237
  },
38238
/* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
38239
  {
38240
    { 0, 0, 0, 0 },
38241
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
38242
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_FB_relative_Unprefixed_HI, { 0xb5cb0000 }
38243
  },
38244
/* mov.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
38245
  {
38246
    { 0, 0, 0, 0 },
38247
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
38248
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_FB_relative_Unprefixed_HI, { 0xb5eb0000 }
38249
  },
38250
/* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
38251
  {
38252
    { 0, 0, 0, 0 },
38253
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
38254
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_absolute_Unprefixed_HI, { 0xb7cb0000 }
38255
  },
38256
/* mov.w${G} ${Dsp-16-u24},${Dsp-40-u16} */
38257
  {
38258
    { 0, 0, 0, 0 },
38259
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } },
38260
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_absolute_Unprefixed_HI, { 0xb7eb0000 }
38261
  },
38262
/* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
38263
  {
38264
    { 0, 0, 0, 0 },
38265
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
38266
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_24_absolute_Unprefixed_HI, { 0xb78b0000 }
38267
  },
38268
/* mov.w${G} ${Dsp-16-u24},${Dsp-40-u24} */
38269
  {
38270
    { 0, 0, 0, 0 },
38271
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } },
38272
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_24_absolute_Unprefixed_HI, { 0xb7ab0000 }
38273
  },
38274
/* mov.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */
38275
  {
38276
    { 0, 0, 0, 0 },
38277
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
38278
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xc90b }
38279
  },
38280
/* mov.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */
38281
  {
38282
    { 0, 0, 0, 0 },
38283
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
38284
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x892b }
38285
  },
38286
/* mov.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
38287
  {
38288
    { 0, 0, 0, 0 },
38289
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
38290
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x890b }
38291
  },
38292
/* mov.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */
38293
  {
38294
    { 0, 0, 0, 0 },
38295
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
38296
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xc18b }
38297
  },
38298
/* mov.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */
38299
  {
38300
    { 0, 0, 0, 0 },
38301
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
38302
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x81ab }
38303
  },
38304
/* mov.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
38305
  {
38306
    { 0, 0, 0, 0 },
38307
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
38308
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x818b }
38309
  },
38310
/* mov.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */
38311
  {
38312
    { 0, 0, 0, 0 },
38313
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38314
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xc10b }
38315
  },
38316
/* mov.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */
38317
  {
38318
    { 0, 0, 0, 0 },
38319
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38320
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x812b }
38321
  },
38322
/* mov.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
38323
  {
38324
    { 0, 0, 0, 0 },
38325
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38326
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x810b }
38327
  },
38328
/* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
38329
  {
38330
    { 0, 0, 0, 0 },
38331
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38332
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0xc30b00 }
38333
  },
38334
/* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
38335
  {
38336
    { 0, 0, 0, 0 },
38337
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38338
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0x832b00 }
38339
  },
38340
/* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
38341
  {
38342
    { 0, 0, 0, 0 },
38343
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38344
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0x830b00 }
38345
  },
38346
/* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
38347
  {
38348
    { 0, 0, 0, 0 },
38349
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38350
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0xc50b0000 }
38351
  },
38352
/* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
38353
  {
38354
    { 0, 0, 0, 0 },
38355
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38356
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0x852b0000 }
38357
  },
38358
/* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
38359
  {
38360
    { 0, 0, 0, 0 },
38361
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38362
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0x850b0000 }
38363
  },
38364
/* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
38365
  {
38366
    { 0, 0, 0, 0 },
38367
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38368
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0xc70b0000 }
38369
  },
38370
/* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
38371
  {
38372
    { 0, 0, 0, 0 },
38373
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38374
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0x872b0000 }
38375
  },
38376
/* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
38377
  {
38378
    { 0, 0, 0, 0 },
38379
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38380
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0x870b0000 }
38381
  },
38382
/* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */
38383
  {
38384
    { 0, 0, 0, 0 },
38385
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
38386
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0xc38b00 }
38387
  },
38388
/* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */
38389
  {
38390
    { 0, 0, 0, 0 },
38391
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
38392
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0x83ab00 }
38393
  },
38394
/* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
38395
  {
38396
    { 0, 0, 0, 0 },
38397
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
38398
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0x838b00 }
38399
  },
38400
/* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */
38401
  {
38402
    { 0, 0, 0, 0 },
38403
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
38404
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0xc58b0000 }
38405
  },
38406
/* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */
38407
  {
38408
    { 0, 0, 0, 0 },
38409
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
38410
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0x85ab0000 }
38411
  },
38412
/* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
38413
  {
38414
    { 0, 0, 0, 0 },
38415
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
38416
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0x858b0000 }
38417
  },
38418
/* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */
38419
  {
38420
    { 0, 0, 0, 0 },
38421
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
38422
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0xc3cb00 }
38423
  },
38424
/* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */
38425
  {
38426
    { 0, 0, 0, 0 },
38427
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
38428
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83eb00 }
38429
  },
38430
/* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
38431
  {
38432
    { 0, 0, 0, 0 },
38433
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
38434
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83cb00 }
38435
  },
38436
/* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */
38437
  {
38438
    { 0, 0, 0, 0 },
38439
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
38440
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0xc5cb0000 }
38441
  },
38442
/* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */
38443
  {
38444
    { 0, 0, 0, 0 },
38445
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
38446
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85eb0000 }
38447
  },
38448
/* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
38449
  {
38450
    { 0, 0, 0, 0 },
38451
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
38452
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85cb0000 }
38453
  },
38454
/* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */
38455
  {
38456
    { 0, 0, 0, 0 },
38457
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), 0 } },
38458
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0xc7cb0000 }
38459
  },
38460
/* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */
38461
  {
38462
    { 0, 0, 0, 0 },
38463
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), 0 } },
38464
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0x87eb0000 }
38465
  },
38466
/* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
38467
  {
38468
    { 0, 0, 0, 0 },
38469
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } },
38470
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0x87cb0000 }
38471
  },
38472
/* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */
38473
  {
38474
    { 0, 0, 0, 0 },
38475
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U24), 0 } },
38476
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0xc78b0000 }
38477
  },
38478
/* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */
38479
  {
38480
    { 0, 0, 0, 0 },
38481
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U24), 0 } },
38482
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0x87ab0000 }
38483
  },
38484
/* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
38485
  {
38486
    { 0, 0, 0, 0 },
38487
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } },
38488
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0x878b0000 }
38489
  },
38490
/* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
38491
  {
38492
    { 0, 0, 0, 0 },
38493
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
38494
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x980b00 }
38495
  },
38496
/* mov.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */
38497
  {
38498
    { 0, 0, 0, 0 },
38499
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
38500
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x982b00 }
38501
  },
38502
/* mov.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */
38503
  {
38504
    { 0, 0, 0, 0 },
38505
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
38506
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x983b00 }
38507
  },
38508
/* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
38509
  {
38510
    { 0, 0, 0, 0 },
38511
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
38512
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x908b00 }
38513
  },
38514
/* mov.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */
38515
  {
38516
    { 0, 0, 0, 0 },
38517
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
38518
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x90ab00 }
38519
  },
38520
/* mov.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */
38521
  {
38522
    { 0, 0, 0, 0 },
38523
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
38524
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x90bb00 }
38525
  },
38526
/* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
38527
  {
38528
    { 0, 0, 0, 0 },
38529
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38530
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x900b00 }
38531
  },
38532
/* mov.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
38533
  {
38534
    { 0, 0, 0, 0 },
38535
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38536
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x902b00 }
38537
  },
38538
/* mov.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
38539
  {
38540
    { 0, 0, 0, 0 },
38541
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38542
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x903b00 }
38543
  },
38544
/* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
38545
  {
38546
    { 0, 0, 0, 0 },
38547
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38548
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x920b0000 }
38549
  },
38550
/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
38551
  {
38552
    { 0, 0, 0, 0 },
38553
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38554
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x922b0000 }
38555
  },
38556
/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
38557
  {
38558
    { 0, 0, 0, 0 },
38559
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38560
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x923b0000 }
38561
  },
38562
/* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
38563
  {
38564
    { 0, 0, 0, 0 },
38565
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38566
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x940b0000 }
38567
  },
38568
/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
38569
  {
38570
    { 0, 0, 0, 0 },
38571
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38572
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x942b0000 }
38573
  },
38574
/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
38575
  {
38576
    { 0, 0, 0, 0 },
38577
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38578
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x943b0000 }
38579
  },
38580
/* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
38581
  {
38582
    { 0, 0, 0, 0 },
38583
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38584
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x960b0000 }
38585
  },
38586
/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
38587
  {
38588
    { 0, 0, 0, 0 },
38589
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38590
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x962b0000 }
38591
  },
38592
/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
38593
  {
38594
    { 0, 0, 0, 0 },
38595
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38596
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x963b0000 }
38597
  },
38598
/* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
38599
  {
38600
    { 0, 0, 0, 0 },
38601
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
38602
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x928b0000 }
38603
  },
38604
/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
38605
  {
38606
    { 0, 0, 0, 0 },
38607
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
38608
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92ab0000 }
38609
  },
38610
/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
38611
  {
38612
    { 0, 0, 0, 0 },
38613
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
38614
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92bb0000 }
38615
  },
38616
/* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
38617
  {
38618
    { 0, 0, 0, 0 },
38619
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
38620
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x948b0000 }
38621
  },
38622
/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
38623
  {
38624
    { 0, 0, 0, 0 },
38625
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
38626
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94ab0000 }
38627
  },
38628
/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
38629
  {
38630
    { 0, 0, 0, 0 },
38631
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
38632
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94bb0000 }
38633
  },
38634
/* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
38635
  {
38636
    { 0, 0, 0, 0 },
38637
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
38638
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92cb0000 }
38639
  },
38640
/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
38641
  {
38642
    { 0, 0, 0, 0 },
38643
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
38644
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92eb0000 }
38645
  },
38646
/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
38647
  {
38648
    { 0, 0, 0, 0 },
38649
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
38650
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92fb0000 }
38651
  },
38652
/* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
38653
  {
38654
    { 0, 0, 0, 0 },
38655
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
38656
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94cb0000 }
38657
  },
38658
/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
38659
  {
38660
    { 0, 0, 0, 0 },
38661
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
38662
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94eb0000 }
38663
  },
38664
/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
38665
  {
38666
    { 0, 0, 0, 0 },
38667
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
38668
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94fb0000 }
38669
  },
38670
/* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
38671
  {
38672
    { 0, 0, 0, 0 },
38673
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
38674
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96cb0000 }
38675
  },
38676
/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
38677
  {
38678
    { 0, 0, 0, 0 },
38679
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
38680
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96eb0000 }
38681
  },
38682
/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
38683
  {
38684
    { 0, 0, 0, 0 },
38685
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
38686
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96fb0000 }
38687
  },
38688
/* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
38689
  {
38690
    { 0, 0, 0, 0 },
38691
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
38692
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x968b0000 }
38693
  },
38694
/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
38695
  {
38696
    { 0, 0, 0, 0 },
38697
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } },
38698
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96ab0000 }
38699
  },
38700
/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
38701
  {
38702
    { 0, 0, 0, 0 },
38703
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } },
38704
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96bb0000 }
38705
  },
38706
/* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
38707
  {
38708
    { 0, 0, 0, 0 },
38709
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
38710
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa80b0000 }
38711
  },
38712
/* mov.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */
38713
  {
38714
    { 0, 0, 0, 0 },
38715
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
38716
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa82b0000 }
38717
  },
38718
/* mov.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */
38719
  {
38720
    { 0, 0, 0, 0 },
38721
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
38722
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa83b0000 }
38723
  },
38724
/* mov.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */
38725
  {
38726
    { 0, 0, 0, 0 },
38727
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
38728
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb83b0000 }
38729
  },
38730
/* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
38731
  {
38732
    { 0, 0, 0, 0 },
38733
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
38734
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa08b0000 }
38735
  },
38736
/* mov.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */
38737
  {
38738
    { 0, 0, 0, 0 },
38739
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
38740
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0ab0000 }
38741
  },
38742
/* mov.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */
38743
  {
38744
    { 0, 0, 0, 0 },
38745
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
38746
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0bb0000 }
38747
  },
38748
/* mov.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */
38749
  {
38750
    { 0, 0, 0, 0 },
38751
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
38752
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0bb0000 }
38753
  },
38754
/* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
38755
  {
38756
    { 0, 0, 0, 0 },
38757
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38758
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa00b0000 }
38759
  },
38760
/* mov.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
38761
  {
38762
    { 0, 0, 0, 0 },
38763
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38764
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa02b0000 }
38765
  },
38766
/* mov.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
38767
  {
38768
    { 0, 0, 0, 0 },
38769
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38770
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa03b0000 }
38771
  },
38772
/* mov.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
38773
  {
38774
    { 0, 0, 0, 0 },
38775
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38776
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb03b0000 }
38777
  },
38778
/* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
38779
  {
38780
    { 0, 0, 0, 0 },
38781
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38782
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa20b0000 }
38783
  },
38784
/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
38785
  {
38786
    { 0, 0, 0, 0 },
38787
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38788
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa22b0000 }
38789
  },
38790
/* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
38791
  {
38792
    { 0, 0, 0, 0 },
38793
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38794
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa23b0000 }
38795
  },
38796
/* mov.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
38797
  {
38798
    { 0, 0, 0, 0 },
38799
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38800
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xb23b0000 }
38801
  },
38802
/* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
38803
  {
38804
    { 0, 0, 0, 0 },
38805
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38806
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa40b0000 }
38807
  },
38808
/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
38809
  {
38810
    { 0, 0, 0, 0 },
38811
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38812
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa42b0000 }
38813
  },
38814
/* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
38815
  {
38816
    { 0, 0, 0, 0 },
38817
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38818
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa43b0000 }
38819
  },
38820
/* mov.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
38821
  {
38822
    { 0, 0, 0, 0 },
38823
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38824
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xb43b0000 }
38825
  },
38826
/* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
38827
  {
38828
    { 0, 0, 0, 0 },
38829
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38830
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa60b0000 }
38831
  },
38832
/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
38833
  {
38834
    { 0, 0, 0, 0 },
38835
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38836
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa62b0000 }
38837
  },
38838
/* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
38839
  {
38840
    { 0, 0, 0, 0 },
38841
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38842
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa63b0000 }
38843
  },
38844
/* mov.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
38845
  {
38846
    { 0, 0, 0, 0 },
38847
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
38848
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xb63b0000 }
38849
  },
38850
/* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
38851
  {
38852
    { 0, 0, 0, 0 },
38853
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
38854
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa28b0000 }
38855
  },
38856
/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
38857
  {
38858
    { 0, 0, 0, 0 },
38859
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
38860
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2ab0000 }
38861
  },
38862
/* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
38863
  {
38864
    { 0, 0, 0, 0 },
38865
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
38866
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2bb0000 }
38867
  },
38868
/* mov.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
38869
  {
38870
    { 0, 0, 0, 0 },
38871
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
38872
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xb2bb0000 }
38873
  },
38874
/* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
38875
  {
38876
    { 0, 0, 0, 0 },
38877
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
38878
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa48b0000 }
38879
  },
38880
/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
38881
  {
38882
    { 0, 0, 0, 0 },
38883
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
38884
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4ab0000 }
38885
  },
38886
/* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
38887
  {
38888
    { 0, 0, 0, 0 },
38889
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
38890
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4bb0000 }
38891
  },
38892
/* mov.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
38893
  {
38894
    { 0, 0, 0, 0 },
38895
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
38896
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xb4bb0000 }
38897
  },
38898
/* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
38899
  {
38900
    { 0, 0, 0, 0 },
38901
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
38902
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2cb0000 }
38903
  },
38904
/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
38905
  {
38906
    { 0, 0, 0, 0 },
38907
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
38908
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2eb0000 }
38909
  },
38910
/* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
38911
  {
38912
    { 0, 0, 0, 0 },
38913
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
38914
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2fb0000 }
38915
  },
38916
/* mov.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
38917
  {
38918
    { 0, 0, 0, 0 },
38919
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
38920
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xb2fb0000 }
38921
  },
38922
/* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
38923
  {
38924
    { 0, 0, 0, 0 },
38925
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
38926
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4cb0000 }
38927
  },
38928
/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
38929
  {
38930
    { 0, 0, 0, 0 },
38931
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
38932
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4eb0000 }
38933
  },
38934
/* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
38935
  {
38936
    { 0, 0, 0, 0 },
38937
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
38938
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4fb0000 }
38939
  },
38940
/* mov.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
38941
  {
38942
    { 0, 0, 0, 0 },
38943
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
38944
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xb4fb0000 }
38945
  },
38946
/* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
38947
  {
38948
    { 0, 0, 0, 0 },
38949
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
38950
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6cb0000 }
38951
  },
38952
/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
38953
  {
38954
    { 0, 0, 0, 0 },
38955
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
38956
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6eb0000 }
38957
  },
38958
/* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
38959
  {
38960
    { 0, 0, 0, 0 },
38961
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
38962
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6fb0000 }
38963
  },
38964
/* mov.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
38965
  {
38966
    { 0, 0, 0, 0 },
38967
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
38968
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xb6fb0000 }
38969
  },
38970
/* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
38971
  {
38972
    { 0, 0, 0, 0 },
38973
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
38974
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa68b0000 }
38975
  },
38976
/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
38977
  {
38978
    { 0, 0, 0, 0 },
38979
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
38980
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6ab0000 }
38981
  },
38982
/* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
38983
  {
38984
    { 0, 0, 0, 0 },
38985
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
38986
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6bb0000 }
38987
  },
38988
/* mov.b${G} ${Dsp-16-u16},${Dsp-32-u24} */
38989
  {
38990
    { 0, 0, 0, 0 },
38991
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } },
38992
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xb6bb0000 }
38993
  },
38994
/* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
38995
  {
38996
    { 0, 0, 0, 0 },
38997
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
38998
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb80b0000 }
38999
  },
39000
/* mov.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */
39001
  {
39002
    { 0, 0, 0, 0 },
39003
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
39004
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb82b0000 }
39005
  },
39006
/* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
39007
  {
39008
    { 0, 0, 0, 0 },
39009
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
39010
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb08b0000 }
39011
  },
39012
/* mov.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */
39013
  {
39014
    { 0, 0, 0, 0 },
39015
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
39016
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0ab0000 }
39017
  },
39018
/* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
39019
  {
39020
    { 0, 0, 0, 0 },
39021
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
39022
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb00b0000 }
39023
  },
39024
/* mov.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
39025
  {
39026
    { 0, 0, 0, 0 },
39027
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
39028
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb02b0000 }
39029
  },
39030
/* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
39031
  {
39032
    { 0, 0, 0, 0 },
39033
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
39034
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_QI, { 0xb20b0000 }
39035
  },
39036
/* mov.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
39037
  {
39038
    { 0, 0, 0, 0 },
39039
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
39040
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_QI, { 0xb22b0000 }
39041
  },
39042
/* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
39043
  {
39044
    { 0, 0, 0, 0 },
39045
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
39046
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_QI, { 0xb40b0000 }
39047
  },
39048
/* mov.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
39049
  {
39050
    { 0, 0, 0, 0 },
39051
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
39052
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_QI, { 0xb42b0000 }
39053
  },
39054
/* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
39055
  {
39056
    { 0, 0, 0, 0 },
39057
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
39058
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_QI, { 0xb60b0000 }
39059
  },
39060
/* mov.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
39061
  {
39062
    { 0, 0, 0, 0 },
39063
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
39064
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_QI, { 0xb62b0000 }
39065
  },
39066
/* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
39067
  {
39068
    { 0, 0, 0, 0 },
39069
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
39070
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_QI, { 0xb28b0000 }
39071
  },
39072
/* mov.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
39073
  {
39074
    { 0, 0, 0, 0 },
39075
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
39076
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_QI, { 0xb2ab0000 }
39077
  },
39078
/* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
39079
  {
39080
    { 0, 0, 0, 0 },
39081
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
39082
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_QI, { 0xb48b0000 }
39083
  },
39084
/* mov.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
39085
  {
39086
    { 0, 0, 0, 0 },
39087
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
39088
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_QI, { 0xb4ab0000 }
39089
  },
39090
/* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
39091
  {
39092
    { 0, 0, 0, 0 },
39093
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
39094
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_QI, { 0xb2cb0000 }
39095
  },
39096
/* mov.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
39097
  {
39098
    { 0, 0, 0, 0 },
39099
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
39100
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_QI, { 0xb2eb0000 }
39101
  },
39102
/* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
39103
  {
39104
    { 0, 0, 0, 0 },
39105
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
39106
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_QI, { 0xb4cb0000 }
39107
  },
39108
/* mov.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
39109
  {
39110
    { 0, 0, 0, 0 },
39111
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
39112
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_QI, { 0xb4eb0000 }
39113
  },
39114
/* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
39115
  {
39116
    { 0, 0, 0, 0 },
39117
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
39118
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_QI, { 0xb6cb0000 }
39119
  },
39120
/* mov.b${G} ${Dsp-16-u24},${Dsp-40-u16} */
39121
  {
39122
    { 0, 0, 0, 0 },
39123
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } },
39124
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_QI, { 0xb6eb0000 }
39125
  },
39126
/* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
39127
  {
39128
    { 0, 0, 0, 0 },
39129
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
39130
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_QI, { 0xb68b0000 }
39131
  },
39132
/* mov.b${G} ${Dsp-16-u24},${Dsp-40-u24} */
39133
  {
39134
    { 0, 0, 0, 0 },
39135
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } },
39136
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_QI, { 0xb6ab0000 }
39137
  },
39138
/* mov.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */
39139
  {
39140
    { 0, 0, 0, 0 },
39141
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
39142
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xc80b }
39143
  },
39144
/* mov.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */
39145
  {
39146
    { 0, 0, 0, 0 },
39147
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
39148
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x882b }
39149
  },
39150
/* mov.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
39151
  {
39152
    { 0, 0, 0, 0 },
39153
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
39154
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x880b }
39155
  },
39156
/* mov.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */
39157
  {
39158
    { 0, 0, 0, 0 },
39159
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
39160
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xc08b }
39161
  },
39162
/* mov.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */
39163
  {
39164
    { 0, 0, 0, 0 },
39165
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
39166
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x80ab }
39167
  },
39168
/* mov.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
39169
  {
39170
    { 0, 0, 0, 0 },
39171
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
39172
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x808b }
39173
  },
39174
/* mov.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */
39175
  {
39176
    { 0, 0, 0, 0 },
39177
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
39178
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xc00b }
39179
  },
39180
/* mov.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */
39181
  {
39182
    { 0, 0, 0, 0 },
39183
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
39184
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x802b }
39185
  },
39186
/* mov.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
39187
  {
39188
    { 0, 0, 0, 0 },
39189
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
39190
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x800b }
39191
  },
39192
/* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
39193
  {
39194
    { 0, 0, 0, 0 },
39195
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
39196
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0xc20b00 }
39197
  },
39198
/* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
39199
  {
39200
    { 0, 0, 0, 0 },
39201
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
39202
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0x822b00 }
39203
  },
39204
/* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
39205
  {
39206
    { 0, 0, 0, 0 },
39207
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
39208
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0x820b00 }
39209
  },
39210
/* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
39211
  {
39212
    { 0, 0, 0, 0 },
39213
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
39214
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0xc40b0000 }
39215
  },
39216
/* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
39217
  {
39218
    { 0, 0, 0, 0 },
39219
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
39220
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0x842b0000 }
39221
  },
39222
/* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
39223
  {
39224
    { 0, 0, 0, 0 },
39225
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
39226
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0x840b0000 }
39227
  },
39228
/* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
39229
  {
39230
    { 0, 0, 0, 0 },
39231
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
39232
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0xc60b0000 }
39233
  },
39234
/* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
39235
  {
39236
    { 0, 0, 0, 0 },
39237
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
39238
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0x862b0000 }
39239
  },
39240
/* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
39241
  {
39242
    { 0, 0, 0, 0 },
39243
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
39244
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0x860b0000 }
39245
  },
39246
/* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */
39247
  {
39248
    { 0, 0, 0, 0 },
39249
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
39250
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0xc28b00 }
39251
  },
39252
/* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */
39253
  {
39254
    { 0, 0, 0, 0 },
39255
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
39256
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0x82ab00 }
39257
  },
39258
/* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
39259
  {
39260
    { 0, 0, 0, 0 },
39261
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
39262
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0x828b00 }
39263
  },
39264
/* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */
39265
  {
39266
    { 0, 0, 0, 0 },
39267
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
39268
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0xc48b0000 }
39269
  },
39270
/* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */
39271
  {
39272
    { 0, 0, 0, 0 },
39273
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
39274
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0x84ab0000 }
39275
  },
39276
/* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
39277
  {
39278
    { 0, 0, 0, 0 },
39279
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
39280
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0x848b0000 }
39281
  },
39282
/* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */
39283
  {
39284
    { 0, 0, 0, 0 },
39285
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
39286
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0xc2cb00 }
39287
  },
39288
/* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */
39289
  {
39290
    { 0, 0, 0, 0 },
39291
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
39292
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82eb00 }
39293
  },
39294
/* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
39295
  {
39296
    { 0, 0, 0, 0 },
39297
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
39298
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82cb00 }
39299
  },
39300
/* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */
39301
  {
39302
    { 0, 0, 0, 0 },
39303
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
39304
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0xc4cb0000 }
39305
  },
39306
/* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */
39307
  {
39308
    { 0, 0, 0, 0 },
39309
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
39310
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84eb0000 }
39311
  },
39312
/* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
39313
  {
39314
    { 0, 0, 0, 0 },
39315
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
39316
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84cb0000 }
39317
  },
39318
/* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */
39319
  {
39320
    { 0, 0, 0, 0 },
39321
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), 0 } },
39322
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0xc6cb0000 }
39323
  },
39324
/* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */
39325
  {
39326
    { 0, 0, 0, 0 },
39327
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), 0 } },
39328
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0x86eb0000 }
39329
  },
39330
/* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
39331
  {
39332
    { 0, 0, 0, 0 },
39333
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } },
39334
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0x86cb0000 }
39335
  },
39336
/* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */
39337
  {
39338
    { 0, 0, 0, 0 },
39339
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U24), 0 } },
39340
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0xc68b0000 }
39341
  },
39342
/* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */
39343
  {
39344
    { 0, 0, 0, 0 },
39345
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U24), 0 } },
39346
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0x86ab0000 }
39347
  },
39348
/* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
39349
  {
39350
    { 0, 0, 0, 0 },
39351
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } },
39352
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0x868b0000 }
39353
  },
39354
/* mov.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
39355
  {
39356
    { 0, 0, 0, 0 },
39357
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } },
39358
    & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_Rn_direct_HI, { 0x738000 }
39359
  },
39360
/* mov.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */
39361
  {
39362
    { 0, 0, 0, 0 },
39363
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } },
39364
    & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_Rn_direct_HI, { 0x73a000 }
39365
  },
39366
/* mov.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */
39367
  {
39368
    { 0, 0, 0, 0 },
39369
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNHI), 0 } },
39370
    & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_Rn_direct_HI, { 0x73b000 }
39371
  },
39372
/* mov.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
39373
  {
39374
    { 0, 0, 0, 0 },
39375
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } },
39376
    & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_direct_HI, { 0x738400 }
39377
  },
39378
/* mov.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */
39379
  {
39380
    { 0, 0, 0, 0 },
39381
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } },
39382
    & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_direct_HI, { 0x73a400 }
39383
  },
39384
/* mov.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */
39385
  {
39386
    { 0, 0, 0, 0 },
39387
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANHI), 0 } },
39388
    & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_direct_HI, { 0x73b400 }
39389
  },
39390
/* mov.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
39391
  {
39392
    { 0, 0, 0, 0 },
39393
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
39394
    & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_indirect_HI, { 0x738600 }
39395
  },
39396
/* mov.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */
39397
  {
39398
    { 0, 0, 0, 0 },
39399
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
39400
    & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_indirect_HI, { 0x73a600 }
39401
  },
39402
/* mov.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */
39403
  {
39404
    { 0, 0, 0, 0 },
39405
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
39406
    & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_indirect_HI, { 0x73b600 }
39407
  },
39408
/* mov.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
39409
  {
39410
    { 0, 0, 0, 0 },
39411
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
39412
    & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_An_relative_HI, { 0x73880000 }
39413
  },
39414
/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
39415
  {
39416
    { 0, 0, 0, 0 },
39417
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
39418
    & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_An_relative_HI, { 0x73a80000 }
39419
  },
39420
/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
39421
  {
39422
    { 0, 0, 0, 0 },
39423
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
39424
    & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_An_relative_HI, { 0x73b80000 }
39425
  },
39426
/* mov.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
39427
  {
39428
    { 0, 0, 0, 0 },
39429
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
39430
    & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_An_relative_HI, { 0x738c0000 }
39431
  },
39432
/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
39433
  {
39434
    { 0, 0, 0, 0 },
39435
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
39436
    & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_An_relative_HI, { 0x73ac0000 }
39437
  },
39438
/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
39439
  {
39440
    { 0, 0, 0, 0 },
39441
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
39442
    & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_An_relative_HI, { 0x73bc0000 }
39443
  },
39444
/* mov.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
39445
  {
39446
    { 0, 0, 0, 0 },
39447
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
39448
    & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_SB_relative_HI, { 0x738a0000 }
39449
  },
39450
/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
39451
  {
39452
    { 0, 0, 0, 0 },
39453
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
39454
    & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_SB_relative_HI, { 0x73aa0000 }
39455
  },
39456
/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
39457
  {
39458
    { 0, 0, 0, 0 },
39459
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
39460
    & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_SB_relative_HI, { 0x73ba0000 }
39461
  },
39462
/* mov.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
39463
  {
39464
    { 0, 0, 0, 0 },
39465
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
39466
    & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_SB_relative_HI, { 0x738e0000 }
39467
  },
39468
/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
39469
  {
39470
    { 0, 0, 0, 0 },
39471
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
39472
    & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_SB_relative_HI, { 0x73ae0000 }
39473
  },
39474
/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
39475
  {
39476
    { 0, 0, 0, 0 },
39477
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
39478
    & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_SB_relative_HI, { 0x73be0000 }
39479
  },
39480
/* mov.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
39481
  {
39482
    { 0, 0, 0, 0 },
39483
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
39484
    & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_FB_relative_HI, { 0x738b0000 }
39485
  },
39486
/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
39487
  {
39488
    { 0, 0, 0, 0 },
39489
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
39490
    & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_FB_relative_HI, { 0x73ab0000 }
39491
  },
39492
/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
39493
  {
39494
    { 0, 0, 0, 0 },
39495
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
39496
    & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_FB_relative_HI, { 0x73bb0000 }
39497
  },
39498
/* mov.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
39499
  {
39500
    { 0, 0, 0, 0 },
39501
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } },
39502
    & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_absolute_HI, { 0x738f0000 }
39503
  },
39504
/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
39505
  {
39506
    { 0, 0, 0, 0 },
39507
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
39508
    & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_absolute_HI, { 0x73af0000 }
39509
  },
39510
/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
39511
  {
39512
    { 0, 0, 0, 0 },
39513
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
39514
    & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_absolute_HI, { 0x73bf0000 }
39515
  },
39516
/* mov.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
39517
  {
39518
    { 0, 0, 0, 0 },
39519
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } },
39520
    & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_Rn_direct_HI, { 0x73c00000 }
39521
  },
39522
/* mov.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */
39523
  {
39524
    { 0, 0, 0, 0 },
39525
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } },
39526
    & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_Rn_direct_HI, { 0x73e00000 }
39527
  },
39528
/* mov.w${G} ${Dsp-16-u16},$Dst16RnHI */
39529
  {
39530
    { 0, 0, 0, 0 },
39531
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16RNHI), 0 } },
39532
    & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_Rn_direct_HI, { 0x73f00000 }
39533
  },
39534
/* mov.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
39535
  {
39536
    { 0, 0, 0, 0 },
39537
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } },
39538
    & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_direct_HI, { 0x73c40000 }
39539
  },
39540
/* mov.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */
39541
  {
39542
    { 0, 0, 0, 0 },
39543
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } },
39544
    & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_direct_HI, { 0x73e40000 }
39545
  },
39546
/* mov.w${G} ${Dsp-16-u16},$Dst16AnHI */
39547
  {
39548
    { 0, 0, 0, 0 },
39549
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16ANHI), 0 } },
39550
    & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_direct_HI, { 0x73f40000 }
39551
  },
39552
/* mov.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
39553
  {
39554
    { 0, 0, 0, 0 },
39555
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
39556
    & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_indirect_HI, { 0x73c60000 }
39557
  },
39558
/* mov.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */
39559
  {
39560
    { 0, 0, 0, 0 },
39561
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
39562
    & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_indirect_HI, { 0x73e60000 }
39563
  },
39564
/* mov.w${G} ${Dsp-16-u16},[$Dst16An] */
39565
  {
39566
    { 0, 0, 0, 0 },
39567
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } },
39568
    & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_indirect_HI, { 0x73f60000 }
39569
  },
39570
/* mov.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
39571
  {
39572
    { 0, 0, 0, 0 },
39573
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
39574
    & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_An_relative_HI, { 0x73c80000 }
39575
  },
39576
/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
39577
  {
39578
    { 0, 0, 0, 0 },
39579
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
39580
    & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_An_relative_HI, { 0x73e80000 }
39581
  },
39582
/* mov.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
39583
  {
39584
    { 0, 0, 0, 0 },
39585
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
39586
    & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_An_relative_HI, { 0x73f80000 }
39587
  },
39588
/* mov.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
39589
  {
39590
    { 0, 0, 0, 0 },
39591
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
39592
    & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_An_relative_HI, { 0x73cc0000 }
39593
  },
39594
/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
39595
  {
39596
    { 0, 0, 0, 0 },
39597
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
39598
    & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_An_relative_HI, { 0x73ec0000 }
39599
  },
39600
/* mov.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
39601
  {
39602
    { 0, 0, 0, 0 },
39603
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
39604
    & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_An_relative_HI, { 0x73fc0000 }
39605
  },
39606
/* mov.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
39607
  {
39608
    { 0, 0, 0, 0 },
39609
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
39610
    & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_SB_relative_HI, { 0x73ca0000 }
39611
  },
39612
/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
39613
  {
39614
    { 0, 0, 0, 0 },
39615
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
39616
    & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_SB_relative_HI, { 0x73ea0000 }
39617
  },
39618
/* mov.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
39619
  {
39620
    { 0, 0, 0, 0 },
39621
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
39622
    & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_SB_relative_HI, { 0x73fa0000 }
39623
  },
39624
/* mov.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
39625
  {
39626
    { 0, 0, 0, 0 },
39627
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
39628
    & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_SB_relative_HI, { 0x73ce0000 }
39629
  },
39630
/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
39631
  {
39632
    { 0, 0, 0, 0 },
39633
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
39634
    & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_SB_relative_HI, { 0x73ee0000 }
39635
  },
39636
/* mov.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
39637
  {
39638
    { 0, 0, 0, 0 },
39639
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
39640
    & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_SB_relative_HI, { 0x73fe0000 }
39641
  },
39642
/* mov.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
39643
  {
39644
    { 0, 0, 0, 0 },
39645
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
39646
    & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_FB_relative_HI, { 0x73cb0000 }
39647
  },
39648
/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
39649
  {
39650
    { 0, 0, 0, 0 },
39651
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
39652
    & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_FB_relative_HI, { 0x73eb0000 }
39653
  },
39654
/* mov.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
39655
  {
39656
    { 0, 0, 0, 0 },
39657
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
39658
    & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_FB_relative_HI, { 0x73fb0000 }
39659
  },
39660
/* mov.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
39661
  {
39662
    { 0, 0, 0, 0 },
39663
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } },
39664
    & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_absolute_HI, { 0x73cf0000 }
39665
  },
39666
/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
39667
  {
39668
    { 0, 0, 0, 0 },
39669
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
39670
    & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_absolute_HI, { 0x73ef0000 }
39671
  },
39672
/* mov.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
39673
  {
39674
    { 0, 0, 0, 0 },
39675
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
39676
    & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_absolute_HI, { 0x73ff0000 }
39677
  },
39678
/* mov.w${G} $Src16RnHI,$Dst16RnHI */
39679
  {
39680
    { 0, 0, 0, 0 },
39681
    { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DST16RNHI), 0 } },
39682
    & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_Rn_direct_HI, { 0x7300 }
39683
  },
39684
/* mov.w${G} $Src16AnHI,$Dst16RnHI */
39685
  {
39686
    { 0, 0, 0, 0 },
39687
    { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DST16RNHI), 0 } },
39688
    & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_Rn_direct_HI, { 0x7340 }
39689
  },
39690
/* mov.w${G} [$Src16An],$Dst16RnHI */
39691
  {
39692
    { 0, 0, 0, 0 },
39693
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } },
39694
    & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_Rn_direct_HI, { 0x7360 }
39695
  },
39696
/* mov.w${G} $Src16RnHI,$Dst16AnHI */
39697
  {
39698
    { 0, 0, 0, 0 },
39699
    { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DST16ANHI), 0 } },
39700
    & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_direct_HI, { 0x7304 }
39701
  },
39702
/* mov.w${G} $Src16AnHI,$Dst16AnHI */
39703
  {
39704
    { 0, 0, 0, 0 },
39705
    { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DST16ANHI), 0 } },
39706
    & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_direct_HI, { 0x7344 }
39707
  },
39708
/* mov.w${G} [$Src16An],$Dst16AnHI */
39709
  {
39710
    { 0, 0, 0, 0 },
39711
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } },
39712
    & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_direct_HI, { 0x7364 }
39713
  },
39714
/* mov.w${G} $Src16RnHI,[$Dst16An] */
39715
  {
39716
    { 0, 0, 0, 0 },
39717
    { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', '[', OP (DST16AN), ']', 0 } },
39718
    & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_indirect_HI, { 0x7306 }
39719
  },
39720
/* mov.w${G} $Src16AnHI,[$Dst16An] */
39721
  {
39722
    { 0, 0, 0, 0 },
39723
    { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', '[', OP (DST16AN), ']', 0 } },
39724
    & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_indirect_HI, { 0x7346 }
39725
  },
39726
/* mov.w${G} [$Src16An],[$Dst16An] */
39727
  {
39728
    { 0, 0, 0, 0 },
39729
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
39730
    & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_indirect_HI, { 0x7366 }
39731
  },
39732
/* mov.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
39733
  {
39734
    { 0, 0, 0, 0 },
39735
    { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
39736
    & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_An_relative_HI, { 0x730800 }
39737
  },
39738
/* mov.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
39739
  {
39740
    { 0, 0, 0, 0 },
39741
    { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
39742
    & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_An_relative_HI, { 0x734800 }
39743
  },
39744
/* mov.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
39745
  {
39746
    { 0, 0, 0, 0 },
39747
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
39748
    & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_An_relative_HI, { 0x736800 }
39749
  },
39750
/* mov.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
39751
  {
39752
    { 0, 0, 0, 0 },
39753
    { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
39754
    & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_An_relative_HI, { 0x730c0000 }
39755
  },
39756
/* mov.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
39757
  {
39758
    { 0, 0, 0, 0 },
39759
    { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
39760
    & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_An_relative_HI, { 0x734c0000 }
39761
  },
39762
/* mov.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
39763
  {
39764
    { 0, 0, 0, 0 },
39765
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
39766
    & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_An_relative_HI, { 0x736c0000 }
39767
  },
39768
/* mov.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */
39769
  {
39770
    { 0, 0, 0, 0 },
39771
    { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
39772
    & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_SB_relative_HI, { 0x730a00 }
39773
  },
39774
/* mov.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */
39775
  {
39776
    { 0, 0, 0, 0 },
39777
    { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
39778
    & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_SB_relative_HI, { 0x734a00 }
39779
  },
39780
/* mov.w${G} [$Src16An],${Dsp-16-u8}[sb] */
39781
  {
39782
    { 0, 0, 0, 0 },
39783
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
39784
    & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_SB_relative_HI, { 0x736a00 }
39785
  },
39786
/* mov.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */
39787
  {
39788
    { 0, 0, 0, 0 },
39789
    { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
39790
    & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_SB_relative_HI, { 0x730e0000 }
39791
  },
39792
/* mov.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */
39793
  {
39794
    { 0, 0, 0, 0 },
39795
    { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
39796
    & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_SB_relative_HI, { 0x734e0000 }
39797
  },
39798
/* mov.w${G} [$Src16An],${Dsp-16-u16}[sb] */
39799
  {
39800
    { 0, 0, 0, 0 },
39801
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
39802
    & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_SB_relative_HI, { 0x736e0000 }
39803
  },
39804
/* mov.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */
39805
  {
39806
    { 0, 0, 0, 0 },
39807
    { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
39808
    & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_FB_relative_HI, { 0x730b00 }
39809
  },
39810
/* mov.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */
39811
  {
39812
    { 0, 0, 0, 0 },
39813
    { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
39814
    & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_FB_relative_HI, { 0x734b00 }
39815
  },
39816
/* mov.w${G} [$Src16An],${Dsp-16-s8}[fb] */
39817
  {
39818
    { 0, 0, 0, 0 },
39819
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
39820
    & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_FB_relative_HI, { 0x736b00 }
39821
  },
39822
/* mov.w${G} $Src16RnHI,${Dsp-16-u16} */
39823
  {
39824
    { 0, 0, 0, 0 },
39825
    { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), 0 } },
39826
    & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_absolute_HI, { 0x730f0000 }
39827
  },
39828
/* mov.w${G} $Src16AnHI,${Dsp-16-u16} */
39829
  {
39830
    { 0, 0, 0, 0 },
39831
    { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), 0 } },
39832
    & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_absolute_HI, { 0x734f0000 }
39833
  },
39834
/* mov.w${G} [$Src16An],${Dsp-16-u16} */
39835
  {
39836
    { 0, 0, 0, 0 },
39837
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } },
39838
    & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_absolute_HI, { 0x736f0000 }
39839
  },
39840
/* mov.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
39841
  {
39842
    { 0, 0, 0, 0 },
39843
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } },
39844
    & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_Rn_direct_QI, { 0x728000 }
39845
  },
39846
/* mov.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */
39847
  {
39848
    { 0, 0, 0, 0 },
39849
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } },
39850
    & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_Rn_direct_QI, { 0x72a000 }
39851
  },
39852
/* mov.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */
39853
  {
39854
    { 0, 0, 0, 0 },
39855
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNQI), 0 } },
39856
    & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_Rn_direct_QI, { 0x72b000 }
39857
  },
39858
/* mov.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
39859
  {
39860
    { 0, 0, 0, 0 },
39861
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } },
39862
    & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_direct_QI, { 0x728400 }
39863
  },
39864
/* mov.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */
39865
  {
39866
    { 0, 0, 0, 0 },
39867
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } },
39868
    & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_direct_QI, { 0x72a400 }
39869
  },
39870
/* mov.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */
39871
  {
39872
    { 0, 0, 0, 0 },
39873
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANQI), 0 } },
39874
    & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_direct_QI, { 0x72b400 }
39875
  },
39876
/* mov.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
39877
  {
39878
    { 0, 0, 0, 0 },
39879
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
39880
    & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_indirect_QI, { 0x728600 }
39881
  },
39882
/* mov.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */
39883
  {
39884
    { 0, 0, 0, 0 },
39885
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
39886
    & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_indirect_QI, { 0x72a600 }
39887
  },
39888
/* mov.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */
39889
  {
39890
    { 0, 0, 0, 0 },
39891
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
39892
    & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_indirect_QI, { 0x72b600 }
39893
  },
39894
/* mov.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
39895
  {
39896
    { 0, 0, 0, 0 },
39897
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
39898
    & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_An_relative_QI, { 0x72880000 }
39899
  },
39900
/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
39901
  {
39902
    { 0, 0, 0, 0 },
39903
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
39904
    & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_An_relative_QI, { 0x72a80000 }
39905
  },
39906
/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
39907
  {
39908
    { 0, 0, 0, 0 },
39909
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
39910
    & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_An_relative_QI, { 0x72b80000 }
39911
  },
39912
/* mov.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
39913
  {
39914
    { 0, 0, 0, 0 },
39915
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
39916
    & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_An_relative_QI, { 0x728c0000 }
39917
  },
39918
/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
39919
  {
39920
    { 0, 0, 0, 0 },
39921
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
39922
    & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_An_relative_QI, { 0x72ac0000 }
39923
  },
39924
/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
39925
  {
39926
    { 0, 0, 0, 0 },
39927
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
39928
    & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_An_relative_QI, { 0x72bc0000 }
39929
  },
39930
/* mov.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
39931
  {
39932
    { 0, 0, 0, 0 },
39933
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
39934
    & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_SB_relative_QI, { 0x728a0000 }
39935
  },
39936
/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
39937
  {
39938
    { 0, 0, 0, 0 },
39939
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
39940
    & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_SB_relative_QI, { 0x72aa0000 }
39941
  },
39942
/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
39943
  {
39944
    { 0, 0, 0, 0 },
39945
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
39946
    & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_SB_relative_QI, { 0x72ba0000 }
39947
  },
39948
/* mov.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
39949
  {
39950
    { 0, 0, 0, 0 },
39951
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
39952
    & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_SB_relative_QI, { 0x728e0000 }
39953
  },
39954
/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
39955
  {
39956
    { 0, 0, 0, 0 },
39957
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
39958
    & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_SB_relative_QI, { 0x72ae0000 }
39959
  },
39960
/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
39961
  {
39962
    { 0, 0, 0, 0 },
39963
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
39964
    & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_SB_relative_QI, { 0x72be0000 }
39965
  },
39966
/* mov.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
39967
  {
39968
    { 0, 0, 0, 0 },
39969
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
39970
    & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_FB_relative_QI, { 0x728b0000 }
39971
  },
39972
/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
39973
  {
39974
    { 0, 0, 0, 0 },
39975
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
39976
    & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_FB_relative_QI, { 0x72ab0000 }
39977
  },
39978
/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
39979
  {
39980
    { 0, 0, 0, 0 },
39981
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
39982
    & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_FB_relative_QI, { 0x72bb0000 }
39983
  },
39984
/* mov.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
39985
  {
39986
    { 0, 0, 0, 0 },
39987
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } },
39988
    & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_absolute_QI, { 0x728f0000 }
39989
  },
39990
/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
39991
  {
39992
    { 0, 0, 0, 0 },
39993
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
39994
    & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_absolute_QI, { 0x72af0000 }
39995
  },
39996
/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
39997
  {
39998
    { 0, 0, 0, 0 },
39999
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
40000
    & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_absolute_QI, { 0x72bf0000 }
40001
  },
40002
/* mov.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
40003
  {
40004
    { 0, 0, 0, 0 },
40005
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } },
40006
    & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_Rn_direct_QI, { 0x72c00000 }
40007
  },
40008
/* mov.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */
40009
  {
40010
    { 0, 0, 0, 0 },
40011
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } },
40012
    & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_Rn_direct_QI, { 0x72e00000 }
40013
  },
40014
/* mov.b${G} ${Dsp-16-u16},$Dst16RnQI */
40015
  {
40016
    { 0, 0, 0, 0 },
40017
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16RNQI), 0 } },
40018
    & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_Rn_direct_QI, { 0x72f00000 }
40019
  },
40020
/* mov.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
40021
  {
40022
    { 0, 0, 0, 0 },
40023
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } },
40024
    & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_direct_QI, { 0x72c40000 }
40025
  },
40026
/* mov.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */
40027
  {
40028
    { 0, 0, 0, 0 },
40029
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } },
40030
    & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_direct_QI, { 0x72e40000 }
40031
  },
40032
/* mov.b${G} ${Dsp-16-u16},$Dst16AnQI */
40033
  {
40034
    { 0, 0, 0, 0 },
40035
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16ANQI), 0 } },
40036
    & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_direct_QI, { 0x72f40000 }
40037
  },
40038
/* mov.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
40039
  {
40040
    { 0, 0, 0, 0 },
40041
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
40042
    & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_indirect_QI, { 0x72c60000 }
40043
  },
40044
/* mov.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */
40045
  {
40046
    { 0, 0, 0, 0 },
40047
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
40048
    & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_indirect_QI, { 0x72e60000 }
40049
  },
40050
/* mov.b${G} ${Dsp-16-u16},[$Dst16An] */
40051
  {
40052
    { 0, 0, 0, 0 },
40053
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } },
40054
    & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_indirect_QI, { 0x72f60000 }
40055
  },
40056
/* mov.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
40057
  {
40058
    { 0, 0, 0, 0 },
40059
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
40060
    & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_An_relative_QI, { 0x72c80000 }
40061
  },
40062
/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
40063
  {
40064
    { 0, 0, 0, 0 },
40065
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
40066
    & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_An_relative_QI, { 0x72e80000 }
40067
  },
40068
/* mov.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
40069
  {
40070
    { 0, 0, 0, 0 },
40071
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
40072
    & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_An_relative_QI, { 0x72f80000 }
40073
  },
40074
/* mov.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
40075
  {
40076
    { 0, 0, 0, 0 },
40077
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
40078
    & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_An_relative_QI, { 0x72cc0000 }
40079
  },
40080
/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
40081
  {
40082
    { 0, 0, 0, 0 },
40083
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
40084
    & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_An_relative_QI, { 0x72ec0000 }
40085
  },
40086
/* mov.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
40087
  {
40088
    { 0, 0, 0, 0 },
40089
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
40090
    & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_An_relative_QI, { 0x72fc0000 }
40091
  },
40092
/* mov.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
40093
  {
40094
    { 0, 0, 0, 0 },
40095
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
40096
    & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_SB_relative_QI, { 0x72ca0000 }
40097
  },
40098
/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
40099
  {
40100
    { 0, 0, 0, 0 },
40101
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
40102
    & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_SB_relative_QI, { 0x72ea0000 }
40103
  },
40104
/* mov.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
40105
  {
40106
    { 0, 0, 0, 0 },
40107
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
40108
    & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_SB_relative_QI, { 0x72fa0000 }
40109
  },
40110
/* mov.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
40111
  {
40112
    { 0, 0, 0, 0 },
40113
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
40114
    & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_SB_relative_QI, { 0x72ce0000 }
40115
  },
40116
/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
40117
  {
40118
    { 0, 0, 0, 0 },
40119
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
40120
    & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_SB_relative_QI, { 0x72ee0000 }
40121
  },
40122
/* mov.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
40123
  {
40124
    { 0, 0, 0, 0 },
40125
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
40126
    & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_SB_relative_QI, { 0x72fe0000 }
40127
  },
40128
/* mov.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
40129
  {
40130
    { 0, 0, 0, 0 },
40131
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
40132
    & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_FB_relative_QI, { 0x72cb0000 }
40133
  },
40134
/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
40135
  {
40136
    { 0, 0, 0, 0 },
40137
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
40138
    & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_FB_relative_QI, { 0x72eb0000 }
40139
  },
40140
/* mov.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
40141
  {
40142
    { 0, 0, 0, 0 },
40143
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
40144
    & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_FB_relative_QI, { 0x72fb0000 }
40145
  },
40146
/* mov.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
40147
  {
40148
    { 0, 0, 0, 0 },
40149
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } },
40150
    & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_absolute_QI, { 0x72cf0000 }
40151
  },
40152
/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
40153
  {
40154
    { 0, 0, 0, 0 },
40155
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
40156
    & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_absolute_QI, { 0x72ef0000 }
40157
  },
40158
/* mov.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
40159
  {
40160
    { 0, 0, 0, 0 },
40161
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
40162
    & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_absolute_QI, { 0x72ff0000 }
40163
  },
40164
/* mov.b${G} $Src16RnQI,$Dst16RnQI */
40165
  {
40166
    { 0, 0, 0, 0 },
40167
    { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DST16RNQI), 0 } },
40168
    & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_Rn_direct_QI, { 0x7200 }
40169
  },
40170
/* mov.b${G} $Src16AnQI,$Dst16RnQI */
40171
  {
40172
    { 0, 0, 0, 0 },
40173
    { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DST16RNQI), 0 } },
40174
    & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_Rn_direct_QI, { 0x7240 }
40175
  },
40176
/* mov.b${G} [$Src16An],$Dst16RnQI */
40177
  {
40178
    { 0, 0, 0, 0 },
40179
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } },
40180
    & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_Rn_direct_QI, { 0x7260 }
40181
  },
40182
/* mov.b${G} $Src16RnQI,$Dst16AnQI */
40183
  {
40184
    { 0, 0, 0, 0 },
40185
    { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DST16ANQI), 0 } },
40186
    & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_direct_QI, { 0x7204 }
40187
  },
40188
/* mov.b${G} $Src16AnQI,$Dst16AnQI */
40189
  {
40190
    { 0, 0, 0, 0 },
40191
    { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DST16ANQI), 0 } },
40192
    & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_direct_QI, { 0x7244 }
40193
  },
40194
/* mov.b${G} [$Src16An],$Dst16AnQI */
40195
  {
40196
    { 0, 0, 0, 0 },
40197
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } },
40198
    & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_direct_QI, { 0x7264 }
40199
  },
40200
/* mov.b${G} $Src16RnQI,[$Dst16An] */
40201
  {
40202
    { 0, 0, 0, 0 },
40203
    { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', '[', OP (DST16AN), ']', 0 } },
40204
    & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_indirect_QI, { 0x7206 }
40205
  },
40206
/* mov.b${G} $Src16AnQI,[$Dst16An] */
40207
  {
40208
    { 0, 0, 0, 0 },
40209
    { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', '[', OP (DST16AN), ']', 0 } },
40210
    & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_indirect_QI, { 0x7246 }
40211
  },
40212
/* mov.b${G} [$Src16An],[$Dst16An] */
40213
  {
40214
    { 0, 0, 0, 0 },
40215
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
40216
    & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_indirect_QI, { 0x7266 }
40217
  },
40218
/* mov.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
40219
  {
40220
    { 0, 0, 0, 0 },
40221
    { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
40222
    & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_An_relative_QI, { 0x720800 }
40223
  },
40224
/* mov.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
40225
  {
40226
    { 0, 0, 0, 0 },
40227
    { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
40228
    & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_An_relative_QI, { 0x724800 }
40229
  },
40230
/* mov.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
40231
  {
40232
    { 0, 0, 0, 0 },
40233
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
40234
    & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_An_relative_QI, { 0x726800 }
40235
  },
40236
/* mov.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
40237
  {
40238
    { 0, 0, 0, 0 },
40239
    { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
40240
    & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_An_relative_QI, { 0x720c0000 }
40241
  },
40242
/* mov.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
40243
  {
40244
    { 0, 0, 0, 0 },
40245
    { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
40246
    & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_An_relative_QI, { 0x724c0000 }
40247
  },
40248
/* mov.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
40249
  {
40250
    { 0, 0, 0, 0 },
40251
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
40252
    & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_An_relative_QI, { 0x726c0000 }
40253
  },
40254
/* mov.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */
40255
  {
40256
    { 0, 0, 0, 0 },
40257
    { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
40258
    & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_SB_relative_QI, { 0x720a00 }
40259
  },
40260
/* mov.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */
40261
  {
40262
    { 0, 0, 0, 0 },
40263
    { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
40264
    & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_SB_relative_QI, { 0x724a00 }
40265
  },
40266
/* mov.b${G} [$Src16An],${Dsp-16-u8}[sb] */
40267
  {
40268
    { 0, 0, 0, 0 },
40269
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
40270
    & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_SB_relative_QI, { 0x726a00 }
40271
  },
40272
/* mov.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */
40273
  {
40274
    { 0, 0, 0, 0 },
40275
    { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
40276
    & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_SB_relative_QI, { 0x720e0000 }
40277
  },
40278
/* mov.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */
40279
  {
40280
    { 0, 0, 0, 0 },
40281
    { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
40282
    & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_SB_relative_QI, { 0x724e0000 }
40283
  },
40284
/* mov.b${G} [$Src16An],${Dsp-16-u16}[sb] */
40285
  {
40286
    { 0, 0, 0, 0 },
40287
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
40288
    & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_SB_relative_QI, { 0x726e0000 }
40289
  },
40290
/* mov.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */
40291
  {
40292
    { 0, 0, 0, 0 },
40293
    { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
40294
    & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_FB_relative_QI, { 0x720b00 }
40295
  },
40296
/* mov.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */
40297
  {
40298
    { 0, 0, 0, 0 },
40299
    { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
40300
    & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_FB_relative_QI, { 0x724b00 }
40301
  },
40302
/* mov.b${G} [$Src16An],${Dsp-16-s8}[fb] */
40303
  {
40304
    { 0, 0, 0, 0 },
40305
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
40306
    & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_FB_relative_QI, { 0x726b00 }
40307
  },
40308
/* mov.b${G} $Src16RnQI,${Dsp-16-u16} */
40309
  {
40310
    { 0, 0, 0, 0 },
40311
    { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), 0 } },
40312
    & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_absolute_QI, { 0x720f0000 }
40313
  },
40314
/* mov.b${G} $Src16AnQI,${Dsp-16-u16} */
40315
  {
40316
    { 0, 0, 0, 0 },
40317
    { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), 0 } },
40318
    & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_absolute_QI, { 0x724f0000 }
40319
  },
40320
/* mov.b${G} [$Src16An],${Dsp-16-u16} */
40321
  {
40322
    { 0, 0, 0, 0 },
40323
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } },
40324
    & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_absolute_QI, { 0x726f0000 }
40325
  },
40326
/* mov.w${Z} #0,${Dsp-8-u8}[sb] */
40327
  {
40328
    { 0, 0, 0, 0 },
40329
    { { MNEM, OP (Z), ' ', '#', '0', ',', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } },
40330
    & ifmt_mov32_w_r0_dst32_2_S_8_dst32_2_S_8_SB_relative_HI, { 0x2300 }
40331
  },
40332
/* mov.w${Z} #0,${Dsp-8-s8}[fb] */
40333
  {
40334
    { 0, 0, 0, 0 },
40335
    { { MNEM, OP (Z), ' ', '#', '0', ',', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } },
40336
    & ifmt_mov32_w_r0_dst32_2_S_8_dst32_2_S_8_FB_relative_HI, { 0x3300 }
40337
  },
40338
/* mov.w${Z} #0,${Dsp-8-u16} */
40339
  {
40340
    { 0, 0, 0, 0 },
40341
    { { MNEM, OP (Z), ' ', '#', '0', ',', OP (DSP_8_U16), 0 } },
40342
    & ifmt_mov32_w_r0_dst32_2_S_16_dst32_2_S_16_absolute_HI, { 0x130000 }
40343
  },
40344
/* mov.w${Z} #0,r0 */
40345
  {
40346
    { 0, 0, 0, 0 },
40347
    { { MNEM, OP (Z), ' ', '#', '0', ',', 'r', '0', 0 } },
40348
    & ifmt_mov32_w_dst32_2_S_basic_r1_dst32_2_S_R0_direct_HI, { 0x3 }
40349
  },
40350
/* mov.b${Z} #0,${Dsp-8-u8}[sb] */
40351
  {
40352
    { 0, 0, 0, 0 },
40353
    { { MNEM, OP (Z), ' ', '#', '0', ',', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } },
40354
    & ifmt_mov32_b_r0l_dst32_2_S_8_dst32_2_S_8_SB_relative_QI, { 0x2200 }
40355
  },
40356
/* mov.b${Z} #0,${Dsp-8-s8}[fb] */
40357
  {
40358
    { 0, 0, 0, 0 },
40359
    { { MNEM, OP (Z), ' ', '#', '0', ',', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } },
40360
    & ifmt_mov32_b_r0l_dst32_2_S_8_dst32_2_S_8_FB_relative_QI, { 0x3200 }
40361
  },
40362
/* mov.b${Z} #0,${Dsp-8-u16} */
40363
  {
40364
    { 0, 0, 0, 0 },
40365
    { { MNEM, OP (Z), ' ', '#', '0', ',', OP (DSP_8_U16), 0 } },
40366
    & ifmt_mov32_b_r0l_dst32_2_S_16_dst32_2_S_16_absolute_QI, { 0x120000 }
40367
  },
40368
/* mov.b${Z} #0,r0l */
40369
  {
40370
    { 0, 0, 0, 0 },
40371
    { { MNEM, OP (Z), ' ', '#', '0', ',', 'r', '0', 'l', 0 } },
40372
    & ifmt_mov32_b_dst32_2_S_basic_r1l_dst32_2_S_R0l_direct_QI, { 0x2 }
40373
  },
40374
/* mov.b${Z} #0,r0l */
40375
  {
40376
    { 0, 0, 0, 0 },
40377
    { { MNEM, OP (Z), ' ', '#', '0', ',', 'r', '0', 'l', 0 } },
40378
    & ifmt_not16_b_s_dst16_3_S_R0l_direct_QI, { 0xb4 }
40379
  },
40380
/* mov.b${Z} #0,r0h */
40381
  {
40382
    { 0, 0, 0, 0 },
40383
    { { MNEM, OP (Z), ' ', '#', '0', ',', 'r', '0', 'h', 0 } },
40384
    & ifmt_not16_b_s_dst16_3_S_R0h_direct_QI, { 0xb3 }
40385
  },
40386
/* mov.b${Z} #0,${Dsp-8-u8}[sb] */
40387
  {
40388
    { 0, 0, 0, 0 },
40389
    { { MNEM, OP (Z), ' ', '#', '0', ',', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } },
40390
    & ifmt_not16_b_s_dst16_3_S_8_8_SB_relative_QI, { 0xb500 }
40391
  },
40392
/* mov.b${Z} #0,${Dsp-8-s8}[fb] */
40393
  {
40394
    { 0, 0, 0, 0 },
40395
    { { MNEM, OP (Z), ' ', '#', '0', ',', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } },
40396
    & ifmt_not16_b_s_dst16_3_S_8_8_FB_relative_QI, { 0xb600 }
40397
  },
40398
/* mov.b${Z} #0,${Dsp-8-u16} */
40399
  {
40400
    { 0, 0, 0, 0 },
40401
    { { MNEM, OP (Z), ' ', '#', '0', ',', OP (DSP_8_U16), 0 } },
40402
    & ifmt_not16_b_s_dst16_3_S_8_16_absolute_QI, { 0xb70000 }
40403
  },
40404
/* mov.w${Q} #${Imm-12-s4},$Dst32RnUnprefixedHI */
40405
  {
40406
    { 0, 0, 0, 0 },
40407
    { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
40408
    & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0xf920 }
40409
  },
40410
/* mov.w${Q} #${Imm-12-s4},$Dst32AnUnprefixedHI */
40411
  {
40412
    { 0, 0, 0, 0 },
40413
    { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
40414
    & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0xf1a0 }
40415
  },
40416
/* mov.w${Q} #${Imm-12-s4},[$Dst32AnUnprefixed] */
40417
  {
40418
    { 0, 0, 0, 0 },
40419
    { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
40420
    & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0xf120 }
40421
  },
40422
/* mov.w${Q} #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
40423
  {
40424
    { 0, 0, 0, 0 },
40425
    { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
40426
    & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0xf32000 }
40427
  },
40428
/* mov.w${Q} #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
40429
  {
40430
    { 0, 0, 0, 0 },
40431
    { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
40432
    & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0xf5200000 }
40433
  },
40434
/* mov.w${Q} #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
40435
  {
40436
    { 0, 0, 0, 0 },
40437
    { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
40438
    & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0xf7200000 }
40439
  },
40440
/* mov.w${Q} #${Imm-12-s4},${Dsp-16-u8}[sb] */
40441
  {
40442
    { 0, 0, 0, 0 },
40443
    { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
40444
    & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0xf3a000 }
40445
  },
40446
/* mov.w${Q} #${Imm-12-s4},${Dsp-16-u16}[sb] */
40447
  {
40448
    { 0, 0, 0, 0 },
40449
    { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
40450
    & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0xf5a00000 }
40451
  },
40452
/* mov.w${Q} #${Imm-12-s4},${Dsp-16-s8}[fb] */
40453
  {
40454
    { 0, 0, 0, 0 },
40455
    { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
40456
    & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0xf3e000 }
40457
  },
40458
/* mov.w${Q} #${Imm-12-s4},${Dsp-16-s16}[fb] */
40459
  {
40460
    { 0, 0, 0, 0 },
40461
    { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
40462
    & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0xf5e00000 }
40463
  },
40464
/* mov.w${Q} #${Imm-12-s4},${Dsp-16-u16} */
40465
  {
40466
    { 0, 0, 0, 0 },
40467
    { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), 0 } },
40468
    & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0xf7e00000 }
40469
  },
40470
/* mov.w${Q} #${Imm-12-s4},${Dsp-16-u24} */
40471
  {
40472
    { 0, 0, 0, 0 },
40473
    { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U24), 0 } },
40474
    & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0xf7a00000 }
40475
  },
40476
/* mov.b${Q} #${Imm-12-s4},$Dst32RnUnprefixedQI */
40477
  {
40478
    { 0, 0, 0, 0 },
40479
    { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
40480
    & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0xf820 }
40481
  },
40482
/* mov.b${Q} #${Imm-12-s4},$Dst32AnUnprefixedQI */
40483
  {
40484
    { 0, 0, 0, 0 },
40485
    { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
40486
    & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0xf0a0 }
40487
  },
40488
/* mov.b${Q} #${Imm-12-s4},[$Dst32AnUnprefixed] */
40489
  {
40490
    { 0, 0, 0, 0 },
40491
    { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
40492
    & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0xf020 }
40493
  },
40494
/* mov.b${Q} #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
40495
  {
40496
    { 0, 0, 0, 0 },
40497
    { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
40498
    & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0xf22000 }
40499
  },
40500
/* mov.b${Q} #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
40501
  {
40502
    { 0, 0, 0, 0 },
40503
    { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
40504
    & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0xf4200000 }
40505
  },
40506
/* mov.b${Q} #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
40507
  {
40508
    { 0, 0, 0, 0 },
40509
    { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
40510
    & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0xf6200000 }
40511
  },
40512
/* mov.b${Q} #${Imm-12-s4},${Dsp-16-u8}[sb] */
40513
  {
40514
    { 0, 0, 0, 0 },
40515
    { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
40516
    & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0xf2a000 }
40517
  },
40518
/* mov.b${Q} #${Imm-12-s4},${Dsp-16-u16}[sb] */
40519
  {
40520
    { 0, 0, 0, 0 },
40521
    { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
40522
    & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0xf4a00000 }
40523
  },
40524
/* mov.b${Q} #${Imm-12-s4},${Dsp-16-s8}[fb] */
40525
  {
40526
    { 0, 0, 0, 0 },
40527
    { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
40528
    & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0xf2e000 }
40529
  },
40530
/* mov.b${Q} #${Imm-12-s4},${Dsp-16-s16}[fb] */
40531
  {
40532
    { 0, 0, 0, 0 },
40533
    { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
40534
    & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0xf4e00000 }
40535
  },
40536
/* mov.b${Q} #${Imm-12-s4},${Dsp-16-u16} */
40537
  {
40538
    { 0, 0, 0, 0 },
40539
    { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), 0 } },
40540
    & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0xf6e00000 }
40541
  },
40542
/* mov.b${Q} #${Imm-12-s4},${Dsp-16-u24} */
40543
  {
40544
    { 0, 0, 0, 0 },
40545
    { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U24), 0 } },
40546
    & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0xf6a00000 }
40547
  },
40548
/* mov.w${Q} #${Imm-8-s4},$Dst16RnHI */
40549
  {
40550
    { 0, 0, 0, 0 },
40551
    { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DST16RNHI), 0 } },
40552
    & ifmt_mov16_w_imm4_Q_16_dst16_Rn_direct_HI, { 0xd900 }
40553
  },
40554
/* mov.w${Q} #${Imm-8-s4},$Dst16AnHI */
40555
  {
40556
    { 0, 0, 0, 0 },
40557
    { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DST16ANHI), 0 } },
40558
    & ifmt_mov16_w_imm4_Q_16_dst16_An_direct_HI, { 0xd904 }
40559
  },
40560
/* mov.w${Q} #${Imm-8-s4},[$Dst16An] */
40561
  {
40562
    { 0, 0, 0, 0 },
40563
    { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', '[', OP (DST16AN), ']', 0 } },
40564
    & ifmt_mov16_w_imm4_Q_16_dst16_An_indirect_HI, { 0xd906 }
40565
  },
40566
/* mov.w${Q} #${Imm-8-s4},${Dsp-16-u8}[$Dst16An] */
40567
  {
40568
    { 0, 0, 0, 0 },
40569
    { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
40570
    & ifmt_mov16_w_imm4_Q_16_dst16_16_8_An_relative_HI, { 0xd90800 }
40571
  },
40572
/* mov.w${Q} #${Imm-8-s4},${Dsp-16-u16}[$Dst16An] */
40573
  {
40574
    { 0, 0, 0, 0 },
40575
    { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
40576
    & ifmt_mov16_w_imm4_Q_16_dst16_16_16_An_relative_HI, { 0xd90c0000 }
40577
  },
40578
/* mov.w${Q} #${Imm-8-s4},${Dsp-16-u8}[sb] */
40579
  {
40580
    { 0, 0, 0, 0 },
40581
    { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
40582
    & ifmt_mov16_w_imm4_Q_16_dst16_16_8_SB_relative_HI, { 0xd90a00 }
40583
  },
40584
/* mov.w${Q} #${Imm-8-s4},${Dsp-16-u16}[sb] */
40585
  {
40586
    { 0, 0, 0, 0 },
40587
    { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
40588
    & ifmt_mov16_w_imm4_Q_16_dst16_16_16_SB_relative_HI, { 0xd90e0000 }
40589
  },
40590
/* mov.w${Q} #${Imm-8-s4},${Dsp-16-s8}[fb] */
40591
  {
40592
    { 0, 0, 0, 0 },
40593
    { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
40594
    & ifmt_mov16_w_imm4_Q_16_dst16_16_8_FB_relative_HI, { 0xd90b00 }
40595
  },
40596
/* mov.w${Q} #${Imm-8-s4},${Dsp-16-u16} */
40597
  {
40598
    { 0, 0, 0, 0 },
40599
    { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), 0 } },
40600
    & ifmt_mov16_w_imm4_Q_16_dst16_16_16_absolute_HI, { 0xd90f0000 }
40601
  },
40602
/* mov.b${Q} #${Imm-8-s4},$Dst16RnQI */
40603
  {
40604
    { 0, 0, 0, 0 },
40605
    { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DST16RNQI), 0 } },
40606
    & ifmt_mov16_b_imm4_Q_16_dst16_Rn_direct_QI, { 0xd800 }
40607
  },
40608
/* mov.b${Q} #${Imm-8-s4},$Dst16AnQI */
40609
  {
40610
    { 0, 0, 0, 0 },
40611
    { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DST16ANQI), 0 } },
40612
    & ifmt_mov16_b_imm4_Q_16_dst16_An_direct_QI, { 0xd804 }
40613
  },
40614
/* mov.b${Q} #${Imm-8-s4},[$Dst16An] */
40615
  {
40616
    { 0, 0, 0, 0 },
40617
    { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', '[', OP (DST16AN), ']', 0 } },
40618
    & ifmt_mov16_b_imm4_Q_16_dst16_An_indirect_QI, { 0xd806 }
40619
  },
40620
/* mov.b${Q} #${Imm-8-s4},${Dsp-16-u8}[$Dst16An] */
40621
  {
40622
    { 0, 0, 0, 0 },
40623
    { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
40624
    & ifmt_mov16_b_imm4_Q_16_dst16_16_8_An_relative_QI, { 0xd80800 }
40625
  },
40626
/* mov.b${Q} #${Imm-8-s4},${Dsp-16-u16}[$Dst16An] */
40627
  {
40628
    { 0, 0, 0, 0 },
40629
    { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
40630
    & ifmt_mov16_b_imm4_Q_16_dst16_16_16_An_relative_QI, { 0xd80c0000 }
40631
  },
40632
/* mov.b${Q} #${Imm-8-s4},${Dsp-16-u8}[sb] */
40633
  {
40634
    { 0, 0, 0, 0 },
40635
    { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
40636
    & ifmt_mov16_b_imm4_Q_16_dst16_16_8_SB_relative_QI, { 0xd80a00 }
40637
  },
40638
/* mov.b${Q} #${Imm-8-s4},${Dsp-16-u16}[sb] */
40639
  {
40640
    { 0, 0, 0, 0 },
40641
    { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
40642
    & ifmt_mov16_b_imm4_Q_16_dst16_16_16_SB_relative_QI, { 0xd80e0000 }
40643
  },
40644
/* mov.b${Q} #${Imm-8-s4},${Dsp-16-s8}[fb] */
40645
  {
40646
    { 0, 0, 0, 0 },
40647
    { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
40648
    & ifmt_mov16_b_imm4_Q_16_dst16_16_8_FB_relative_QI, { 0xd80b00 }
40649
  },
40650
/* mov.b${Q} #${Imm-8-s4},${Dsp-16-u16} */
40651
  {
40652
    { 0, 0, 0, 0 },
40653
    { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), 0 } },
40654
    & ifmt_mov16_b_imm4_Q_16_dst16_16_16_absolute_QI, { 0xd80f0000 }
40655
  },
40656
/* mov.b${S} #${Imm-8-QI},r0l */
40657
  {
40658
    { 0, 0, 0, 0 },
40659
    { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'l', 0 } },
40660
    & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_R0l_direct_QI, { 0xc400 }
40661
  },
40662
/* mov.b${S} #${Imm-8-QI},r0h */
40663
  {
40664
    { 0, 0, 0, 0 },
40665
    { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'h', 0 } },
40666
    & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_R0h_direct_QI, { 0xc300 }
40667
  },
40668
/* mov.b${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */
40669
  {
40670
    { 0, 0, 0, 0 },
40671
    { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
40672
    & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_8_SB_relative_QI, { 0xc50000 }
40673
  },
40674
/* mov.b${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */
40675
  {
40676
    { 0, 0, 0, 0 },
40677
    { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
40678
    & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_8_FB_relative_QI, { 0xc60000 }
40679
  },
40680
/* mov.b${S} #${Imm-8-QI},${Dsp-16-u16} */
40681
  {
40682
    { 0, 0, 0, 0 },
40683
    { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_U16), 0 } },
40684
    & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_16_absolute_QI, { 0xc7000000 }
40685
  },
40686
/* mov.w${S} #${Imm-16-HI},${Dsp-8-u8}[sb] */
40687
  {
40688
    { 0, 0, 0, 0 },
40689
    { { MNEM, OP (S), ' ', '#', OP (IMM_16_HI), ',', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } },
40690
    & ifmt_tst32_w_imm_S_2_S_8_dst32_2_S_8_SB_relative_HI, { 0x25000000 }
40691
  },
40692
/* mov.w${S} #${Imm-16-HI},${Dsp-8-s8}[fb] */
40693
  {
40694
    { 0, 0, 0, 0 },
40695
    { { MNEM, OP (S), ' ', '#', OP (IMM_16_HI), ',', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } },
40696
    & ifmt_tst32_w_imm_S_2_S_8_dst32_2_S_8_FB_relative_HI, { 0x35000000 }
40697
  },
40698
/* mov.w${S} #${Imm-24-HI},${Dsp-8-u16} */
40699
  {
40700
    { 0, 0, 0, 0 },
40701
    { { MNEM, OP (S), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_8_U16), 0 } },
40702
    & ifmt_tst32_w_imm_S_2_S_16_dst32_2_S_16_absolute_HI, { 0x15000000 }
40703
  },
40704
/* mov.w${S} #${Imm-8-HI},r0 */
40705
  {
40706
    { 0, 0, 0, 0 },
40707
    { { MNEM, OP (S), ' ', '#', OP (IMM_8_HI), ',', 'r', '0', 0 } },
40708
    & ifmt_tst32_w_imm_S_2_S_basic_dst32_2_S_R0_direct_HI, { 0x50000 }
40709
  },
40710
/* mov.b${S} #${Imm-16-QI},${Dsp-8-u8}[sb] */
40711
  {
40712
    { 0, 0, 0, 0 },
40713
    { { MNEM, OP (S), ' ', '#', OP (IMM_16_QI), ',', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } },
40714
    & ifmt_tst32_b_imm_S_2_S_8_dst32_2_S_8_SB_relative_QI, { 0x240000 }
40715
  },
40716
/* mov.b${S} #${Imm-16-QI},${Dsp-8-s8}[fb] */
40717
  {
40718
    { 0, 0, 0, 0 },
40719
    { { MNEM, OP (S), ' ', '#', OP (IMM_16_QI), ',', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } },
40720
    & ifmt_tst32_b_imm_S_2_S_8_dst32_2_S_8_FB_relative_QI, { 0x340000 }
40721
  },
40722
/* mov.b${S} #${Imm-24-QI},${Dsp-8-u16} */
40723
  {
40724
    { 0, 0, 0, 0 },
40725
    { { MNEM, OP (S), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_8_U16), 0 } },
40726
    & ifmt_tst32_b_imm_S_2_S_16_dst32_2_S_16_absolute_QI, { 0x14000000 }
40727
  },
40728
/* mov.b${S} #${Imm-8-QI},r0l */
40729
  {
40730
    { 0, 0, 0, 0 },
40731
    { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'l', 0 } },
40732
    & ifmt_tst32_b_imm_S_2_S_basic_dst32_2_S_R0l_direct_QI, { 0x400 }
40733
  },
40734
/* mov.l${G} #${Imm-16-SI},$Dst32RnUnprefixedSI */
40735
  {
40736
    { 0, 0, 0, 0 },
40737
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_SI), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
40738
    & ifmt_mov32_l_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_SI, { 0xb8310000 }
40739
  },
40740
/* mov.l${G} #${Imm-16-SI},$Dst32AnUnprefixedSI */
40741
  {
40742
    { 0, 0, 0, 0 },
40743
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_SI), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
40744
    & ifmt_mov32_l_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_SI, { 0xb0b10000 }
40745
  },
40746
/* mov.l${G} #${Imm-16-SI},[$Dst32AnUnprefixed] */
40747
  {
40748
    { 0, 0, 0, 0 },
40749
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_SI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
40750
    & ifmt_mov32_l_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_SI, { 0xb0310000 }
40751
  },
40752
/* mov.l${G} #${Imm-24-SI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
40753
  {
40754
    { 0, 0, 0, 0 },
40755
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_SI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
40756
    & ifmt_mov32_l_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_SI, { 0xb2310000 }
40757
  },
40758
/* mov.l${G} #${Imm-24-SI},${Dsp-16-u8}[sb] */
40759
  {
40760
    { 0, 0, 0, 0 },
40761
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_SI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
40762
    & ifmt_mov32_l_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_SI, { 0xb2b10000 }
40763
  },
40764
/* mov.l${G} #${Imm-24-SI},${Dsp-16-s8}[fb] */
40765
  {
40766
    { 0, 0, 0, 0 },
40767
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_SI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
40768
    & ifmt_mov32_l_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_SI, { 0xb2f10000 }
40769
  },
40770
/* mov.l${G} #${Imm-32-SI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
40771
  {
40772
    { 0, 0, 0, 0 },
40773
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_SI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
40774
    & ifmt_mov32_l_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_SI, { 0xb4310000 }
40775
  },
40776
/* mov.l${G} #${Imm-32-SI},${Dsp-16-u16}[sb] */
40777
  {
40778
    { 0, 0, 0, 0 },
40779
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_SI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
40780
    & ifmt_mov32_l_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_SI, { 0xb4b10000 }
40781
  },
40782
/* mov.l${G} #${Imm-32-SI},${Dsp-16-s16}[fb] */
40783
  {
40784
    { 0, 0, 0, 0 },
40785
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_SI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
40786
    & ifmt_mov32_l_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_SI, { 0xb4f10000 }
40787
  },
40788
/* mov.l${G} #${Imm-32-SI},${Dsp-16-u16} */
40789
  {
40790
    { 0, 0, 0, 0 },
40791
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_SI), ',', OP (DSP_16_U16), 0 } },
40792
    & ifmt_mov32_l_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_SI, { 0xb6f10000 }
40793
  },
40794
/* mov.l${G} #${Imm-40-SI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
40795
  {
40796
    { 0, 0, 0, 0 },
40797
    { { MNEM, OP (G), ' ', '#', OP (IMM_40_SI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
40798
    & ifmt_mov32_l_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_SI, { 0xb6310000 }
40799
  },
40800
/* mov.l${G} #${Imm-40-SI},${Dsp-16-u24} */
40801
  {
40802
    { 0, 0, 0, 0 },
40803
    { { MNEM, OP (G), ' ', '#', OP (IMM_40_SI), ',', OP (DSP_16_U24), 0 } },
40804
    & ifmt_mov32_l_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_SI, { 0xb6b10000 }
40805
  },
40806
/* mov.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */
40807
  {
40808
    { 0, 0, 0, 0 },
40809
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
40810
    & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0x992f0000 }
40811
  },
40812
/* mov.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */
40813
  {
40814
    { 0, 0, 0, 0 },
40815
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
40816
    & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0x91af0000 }
40817
  },
40818
/* mov.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */
40819
  {
40820
    { 0, 0, 0, 0 },
40821
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
40822
    & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0x912f0000 }
40823
  },
40824
/* mov.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
40825
  {
40826
    { 0, 0, 0, 0 },
40827
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
40828
    & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0x932f0000 }
40829
  },
40830
/* mov.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
40831
  {
40832
    { 0, 0, 0, 0 },
40833
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
40834
    & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0x93af0000 }
40835
  },
40836
/* mov.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
40837
  {
40838
    { 0, 0, 0, 0 },
40839
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
40840
    & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0x93ef0000 }
40841
  },
40842
/* mov.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
40843
  {
40844
    { 0, 0, 0, 0 },
40845
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
40846
    & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0x952f0000 }
40847
  },
40848
/* mov.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
40849
  {
40850
    { 0, 0, 0, 0 },
40851
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
40852
    & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0x95af0000 }
40853
  },
40854
/* mov.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */
40855
  {
40856
    { 0, 0, 0, 0 },
40857
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
40858
    & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0x95ef0000 }
40859
  },
40860
/* mov.w${G} #${Imm-32-HI},${Dsp-16-u16} */
40861
  {
40862
    { 0, 0, 0, 0 },
40863
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } },
40864
    & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0x97ef0000 }
40865
  },
40866
/* mov.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
40867
  {
40868
    { 0, 0, 0, 0 },
40869
    { { MNEM, OP (G), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
40870
    & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0x972f0000 }
40871
  },
40872
/* mov.w${G} #${Imm-40-HI},${Dsp-16-u24} */
40873
  {
40874
    { 0, 0, 0, 0 },
40875
    { { MNEM, OP (G), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), 0 } },
40876
    & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0x97af0000 }
40877
  },
40878
/* mov.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */
40879
  {
40880
    { 0, 0, 0, 0 },
40881
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
40882
    & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0x982f00 }
40883
  },
40884
/* mov.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */
40885
  {
40886
    { 0, 0, 0, 0 },
40887
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
40888
    & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0x90af00 }
40889
  },
40890
/* mov.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */
40891
  {
40892
    { 0, 0, 0, 0 },
40893
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
40894
    & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0x902f00 }
40895
  },
40896
/* mov.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
40897
  {
40898
    { 0, 0, 0, 0 },
40899
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
40900
    & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0x922f0000 }
40901
  },
40902
/* mov.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
40903
  {
40904
    { 0, 0, 0, 0 },
40905
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
40906
    & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0x92af0000 }
40907
  },
40908
/* mov.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
40909
  {
40910
    { 0, 0, 0, 0 },
40911
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
40912
    & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0x92ef0000 }
40913
  },
40914
/* mov.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
40915
  {
40916
    { 0, 0, 0, 0 },
40917
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
40918
    & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0x942f0000 }
40919
  },
40920
/* mov.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
40921
  {
40922
    { 0, 0, 0, 0 },
40923
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
40924
    & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0x94af0000 }
40925
  },
40926
/* mov.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */
40927
  {
40928
    { 0, 0, 0, 0 },
40929
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
40930
    & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0x94ef0000 }
40931
  },
40932
/* mov.b${G} #${Imm-32-QI},${Dsp-16-u16} */
40933
  {
40934
    { 0, 0, 0, 0 },
40935
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } },
40936
    & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0x96ef0000 }
40937
  },
40938
/* mov.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
40939
  {
40940
    { 0, 0, 0, 0 },
40941
    { { MNEM, OP (G), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
40942
    & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0x962f0000 }
40943
  },
40944
/* mov.b${G} #${Imm-40-QI},${Dsp-16-u24} */
40945
  {
40946
    { 0, 0, 0, 0 },
40947
    { { MNEM, OP (G), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), 0 } },
40948
    & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0x96af0000 }
40949
  },
40950
/* mov.w${G} #${Imm-16-HI},$Dst16RnHI */
40951
  {
40952
    { 0, 0, 0, 0 },
40953
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST16RNHI), 0 } },
40954
    & ifmt_xor16_w_imm_G_basic_dst16_Rn_direct_HI, { 0x75c00000 }
40955
  },
40956
/* mov.w${G} #${Imm-16-HI},$Dst16AnHI */
40957
  {
40958
    { 0, 0, 0, 0 },
40959
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST16ANHI), 0 } },
40960
    & ifmt_xor16_w_imm_G_basic_dst16_An_direct_HI, { 0x75c40000 }
40961
  },
40962
/* mov.w${G} #${Imm-16-HI},[$Dst16An] */
40963
  {
40964
    { 0, 0, 0, 0 },
40965
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST16AN), ']', 0 } },
40966
    & ifmt_xor16_w_imm_G_basic_dst16_An_indirect_HI, { 0x75c60000 }
40967
  },
40968
/* mov.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
40969
  {
40970
    { 0, 0, 0, 0 },
40971
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
40972
    & ifmt_xor16_w_imm_G_16_8_dst16_16_8_An_relative_HI, { 0x75c80000 }
40973
  },
40974
/* mov.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
40975
  {
40976
    { 0, 0, 0, 0 },
40977
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
40978
    & ifmt_xor16_w_imm_G_16_8_dst16_16_8_SB_relative_HI, { 0x75ca0000 }
40979
  },
40980
/* mov.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
40981
  {
40982
    { 0, 0, 0, 0 },
40983
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
40984
    & ifmt_xor16_w_imm_G_16_8_dst16_16_8_FB_relative_HI, { 0x75cb0000 }
40985
  },
40986
/* mov.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
40987
  {
40988
    { 0, 0, 0, 0 },
40989
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
40990
    & ifmt_xor16_w_imm_G_16_16_dst16_16_16_An_relative_HI, { 0x75cc0000 }
40991
  },
40992
/* mov.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
40993
  {
40994
    { 0, 0, 0, 0 },
40995
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
40996
    & ifmt_xor16_w_imm_G_16_16_dst16_16_16_SB_relative_HI, { 0x75ce0000 }
40997
  },
40998
/* mov.w${G} #${Imm-32-HI},${Dsp-16-u16} */
40999
  {
41000
    { 0, 0, 0, 0 },
41001
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } },
41002
    & ifmt_xor16_w_imm_G_16_16_dst16_16_16_absolute_HI, { 0x75cf0000 }
41003
  },
41004
/* mov.b${G} #${Imm-16-QI},$Dst16RnQI */
41005
  {
41006
    { 0, 0, 0, 0 },
41007
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST16RNQI), 0 } },
41008
    & ifmt_xor16_b_imm_G_basic_dst16_Rn_direct_QI, { 0x74c000 }
41009
  },
41010
/* mov.b${G} #${Imm-16-QI},$Dst16AnQI */
41011
  {
41012
    { 0, 0, 0, 0 },
41013
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST16ANQI), 0 } },
41014
    & ifmt_xor16_b_imm_G_basic_dst16_An_direct_QI, { 0x74c400 }
41015
  },
41016
/* mov.b${G} #${Imm-16-QI},[$Dst16An] */
41017
  {
41018
    { 0, 0, 0, 0 },
41019
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST16AN), ']', 0 } },
41020
    & ifmt_xor16_b_imm_G_basic_dst16_An_indirect_QI, { 0x74c600 }
41021
  },
41022
/* mov.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
41023
  {
41024
    { 0, 0, 0, 0 },
41025
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
41026
    & ifmt_xor16_b_imm_G_16_8_dst16_16_8_An_relative_QI, { 0x74c80000 }
41027
  },
41028
/* mov.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
41029
  {
41030
    { 0, 0, 0, 0 },
41031
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
41032
    & ifmt_xor16_b_imm_G_16_8_dst16_16_8_SB_relative_QI, { 0x74ca0000 }
41033
  },
41034
/* mov.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
41035
  {
41036
    { 0, 0, 0, 0 },
41037
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
41038
    & ifmt_xor16_b_imm_G_16_8_dst16_16_8_FB_relative_QI, { 0x74cb0000 }
41039
  },
41040
/* mov.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
41041
  {
41042
    { 0, 0, 0, 0 },
41043
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
41044
    & ifmt_xor16_b_imm_G_16_16_dst16_16_16_An_relative_QI, { 0x74cc0000 }
41045
  },
41046
/* mov.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
41047
  {
41048
    { 0, 0, 0, 0 },
41049
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
41050
    & ifmt_xor16_b_imm_G_16_16_dst16_16_16_SB_relative_QI, { 0x74ce0000 }
41051
  },
41052
/* mov.b${G} #${Imm-32-QI},${Dsp-16-u16} */
41053
  {
41054
    { 0, 0, 0, 0 },
41055
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } },
41056
    & ifmt_xor16_b_imm_G_16_16_dst16_16_16_absolute_QI, { 0x74cf0000 }
41057
  },
41058
/* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
41059
  {
41060
    { 0, 0, 0, 0 },
41061
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
41062
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1990c00 }
41063
  },
41064
/* min.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
41065
  {
41066
    { 0, 0, 0, 0 },
41067
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
41068
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1992c00 }
41069
  },
41070
/* min.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
41071
  {
41072
    { 0, 0, 0, 0 },
41073
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
41074
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1993c00 }
41075
  },
41076
/* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
41077
  {
41078
    { 0, 0, 0, 0 },
41079
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
41080
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1918c00 }
41081
  },
41082
/* min.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
41083
  {
41084
    { 0, 0, 0, 0 },
41085
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
41086
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x191ac00 }
41087
  },
41088
/* min.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
41089
  {
41090
    { 0, 0, 0, 0 },
41091
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
41092
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x191bc00 }
41093
  },
41094
/* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
41095
  {
41096
    { 0, 0, 0, 0 },
41097
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
41098
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1910c00 }
41099
  },
41100
/* min.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
41101
  {
41102
    { 0, 0, 0, 0 },
41103
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
41104
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1912c00 }
41105
  },
41106
/* min.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
41107
  {
41108
    { 0, 0, 0, 0 },
41109
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
41110
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1913c00 }
41111
  },
41112
/* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
41113
  {
41114
    { 0, 0, 0, 0 },
41115
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
41116
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1930c00 }
41117
  },
41118
/* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
41119
  {
41120
    { 0, 0, 0, 0 },
41121
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
41122
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1932c00 }
41123
  },
41124
/* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
41125
  {
41126
    { 0, 0, 0, 0 },
41127
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
41128
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1933c00 }
41129
  },
41130
/* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
41131
  {
41132
    { 0, 0, 0, 0 },
41133
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
41134
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1950c00 }
41135
  },
41136
/* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
41137
  {
41138
    { 0, 0, 0, 0 },
41139
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
41140
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1952c00 }
41141
  },
41142
/* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
41143
  {
41144
    { 0, 0, 0, 0 },
41145
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
41146
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1953c00 }
41147
  },
41148
/* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
41149
  {
41150
    { 0, 0, 0, 0 },
41151
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
41152
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1970c00 }
41153
  },
41154
/* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
41155
  {
41156
    { 0, 0, 0, 0 },
41157
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
41158
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1972c00 }
41159
  },
41160
/* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
41161
  {
41162
    { 0, 0, 0, 0 },
41163
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
41164
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1973c00 }
41165
  },
41166
/* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
41167
  {
41168
    { 0, 0, 0, 0 },
41169
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
41170
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x1938c00 }
41171
  },
41172
/* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
41173
  {
41174
    { 0, 0, 0, 0 },
41175
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
41176
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x193ac00 }
41177
  },
41178
/* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
41179
  {
41180
    { 0, 0, 0, 0 },
41181
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
41182
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x193bc00 }
41183
  },
41184
/* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
41185
  {
41186
    { 0, 0, 0, 0 },
41187
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
41188
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x1958c00 }
41189
  },
41190
/* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
41191
  {
41192
    { 0, 0, 0, 0 },
41193
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
41194
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x195ac00 }
41195
  },
41196
/* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
41197
  {
41198
    { 0, 0, 0, 0 },
41199
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
41200
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x195bc00 }
41201
  },
41202
/* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
41203
  {
41204
    { 0, 0, 0, 0 },
41205
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
41206
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193cc00 }
41207
  },
41208
/* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
41209
  {
41210
    { 0, 0, 0, 0 },
41211
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
41212
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193ec00 }
41213
  },
41214
/* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
41215
  {
41216
    { 0, 0, 0, 0 },
41217
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
41218
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193fc00 }
41219
  },
41220
/* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
41221
  {
41222
    { 0, 0, 0, 0 },
41223
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
41224
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195cc00 }
41225
  },
41226
/* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
41227
  {
41228
    { 0, 0, 0, 0 },
41229
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
41230
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195ec00 }
41231
  },
41232
/* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
41233
  {
41234
    { 0, 0, 0, 0 },
41235
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
41236
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195fc00 }
41237
  },
41238
/* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
41239
  {
41240
    { 0, 0, 0, 0 },
41241
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
41242
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197cc00 }
41243
  },
41244
/* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
41245
  {
41246
    { 0, 0, 0, 0 },
41247
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
41248
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197ec00 }
41249
  },
41250
/* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
41251
  {
41252
    { 0, 0, 0, 0 },
41253
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
41254
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197fc00 }
41255
  },
41256
/* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
41257
  {
41258
    { 0, 0, 0, 0 },
41259
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
41260
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x1978c00 }
41261
  },
41262
/* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
41263
  {
41264
    { 0, 0, 0, 0 },
41265
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
41266
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x197ac00 }
41267
  },
41268
/* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
41269
  {
41270
    { 0, 0, 0, 0 },
41271
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
41272
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x197bc00 }
41273
  },
41274
/* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
41275
  {
41276
    { 0, 0, 0, 0 },
41277
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
41278
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a90c00 }
41279
  },
41280
/* min.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
41281
  {
41282
    { 0, 0, 0, 0 },
41283
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
41284
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a92c00 }
41285
  },
41286
/* min.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
41287
  {
41288
    { 0, 0, 0, 0 },
41289
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
41290
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a93c00 }
41291
  },
41292
/* min.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */
41293
  {
41294
    { 0, 0, 0, 0 },
41295
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32RNPREFIXEDHI), 0 } },
41296
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b93c00 }
41297
  },
41298
/* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
41299
  {
41300
    { 0, 0, 0, 0 },
41301
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
41302
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a18c00 }
41303
  },
41304
/* min.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
41305
  {
41306
    { 0, 0, 0, 0 },
41307
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
41308
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a1ac00 }
41309
  },
41310
/* min.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
41311
  {
41312
    { 0, 0, 0, 0 },
41313
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
41314
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a1bc00 }
41315
  },
41316
/* min.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */
41317
  {
41318
    { 0, 0, 0, 0 },
41319
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32ANPREFIXEDHI), 0 } },
41320
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b1bc00 }
41321
  },
41322
/* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
41323
  {
41324
    { 0, 0, 0, 0 },
41325
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
41326
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a10c00 }
41327
  },
41328
/* min.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
41329
  {
41330
    { 0, 0, 0, 0 },
41331
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
41332
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a12c00 }
41333
  },
41334
/* min.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
41335
  {
41336
    { 0, 0, 0, 0 },
41337
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
41338
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a13c00 }
41339
  },
41340
/* min.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
41341
  {
41342
    { 0, 0, 0, 0 },
41343
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
41344
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b13c00 }
41345
  },
41346
/* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
41347
  {
41348
    { 0, 0, 0, 0 },
41349
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
41350
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a30c00 }
41351
  },
41352
/* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
41353
  {
41354
    { 0, 0, 0, 0 },
41355
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
41356
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a32c00 }
41357
  },
41358
/* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
41359
  {
41360
    { 0, 0, 0, 0 },
41361
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
41362
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a33c00 }
41363
  },
41364
/* min.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
41365
  {
41366
    { 0, 0, 0, 0 },
41367
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
41368
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1b33c00 }
41369
  },
41370
/* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
41371
  {
41372
    { 0, 0, 0, 0 },
41373
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
41374
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a50c00 }
41375
  },
41376
/* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
41377
  {
41378
    { 0, 0, 0, 0 },
41379
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
41380
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a52c00 }
41381
  },
41382
/* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
41383
  {
41384
    { 0, 0, 0, 0 },
41385
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
41386
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a53c00 }
41387
  },
41388
/* min.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
41389
  {
41390
    { 0, 0, 0, 0 },
41391
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
41392
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1b53c00 }
41393
  },
41394
/* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
41395
  {
41396
    { 0, 0, 0, 0 },
41397
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
41398
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a70c00 }
41399
  },
41400
/* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
41401
  {
41402
    { 0, 0, 0, 0 },
41403
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
41404
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a72c00 }
41405
  },
41406
/* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
41407
  {
41408
    { 0, 0, 0, 0 },
41409
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
41410
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a73c00 }
41411
  },
41412
/* min.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
41413
  {
41414
    { 0, 0, 0, 0 },
41415
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
41416
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1b73c00 }
41417
  },
41418
/* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
41419
  {
41420
    { 0, 0, 0, 0 },
41421
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
41422
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a38c00 }
41423
  },
41424
/* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
41425
  {
41426
    { 0, 0, 0, 0 },
41427
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
41428
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a3ac00 }
41429
  },
41430
/* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
41431
  {
41432
    { 0, 0, 0, 0 },
41433
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
41434
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a3bc00 }
41435
  },
41436
/* min.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
41437
  {
41438
    { 0, 0, 0, 0 },
41439
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
41440
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1b3bc00 }
41441
  },
41442
/* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
41443
  {
41444
    { 0, 0, 0, 0 },
41445
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
41446
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a58c00 }
41447
  },
41448
/* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
41449
  {
41450
    { 0, 0, 0, 0 },
41451
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
41452
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a5ac00 }
41453
  },
41454
/* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
41455
  {
41456
    { 0, 0, 0, 0 },
41457
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
41458
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a5bc00 }
41459
  },
41460
/* min.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
41461
  {
41462
    { 0, 0, 0, 0 },
41463
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
41464
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1b5bc00 }
41465
  },
41466
/* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
41467
  {
41468
    { 0, 0, 0, 0 },
41469
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
41470
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3cc00 }
41471
  },
41472
/* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
41473
  {
41474
    { 0, 0, 0, 0 },
41475
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
41476
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3ec00 }
41477
  },
41478
/* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
41479
  {
41480
    { 0, 0, 0, 0 },
41481
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
41482
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3fc00 }
41483
  },
41484
/* min.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
41485
  {
41486
    { 0, 0, 0, 0 },
41487
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
41488
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1b3fc00 }
41489
  },
41490
/* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
41491
  {
41492
    { 0, 0, 0, 0 },
41493
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
41494
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5cc00 }
41495
  },
41496
/* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
41497
  {
41498
    { 0, 0, 0, 0 },
41499
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
41500
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5ec00 }
41501
  },
41502
/* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
41503
  {
41504
    { 0, 0, 0, 0 },
41505
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
41506
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5fc00 }
41507
  },
41508
/* min.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
41509
  {
41510
    { 0, 0, 0, 0 },
41511
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
41512
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1b5fc00 }
41513
  },
41514
/* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
41515
  {
41516
    { 0, 0, 0, 0 },
41517
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
41518
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7cc00 }
41519
  },
41520
/* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
41521
  {
41522
    { 0, 0, 0, 0 },
41523
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), 0 } },
41524
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7ec00 }
41525
  },
41526
/* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
41527
  {
41528
    { 0, 0, 0, 0 },
41529
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), 0 } },
41530
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7fc00 }
41531
  },
41532
/* min.w${X} ${Dsp-24-u16},${Dsp-40-u16} */
41533
  {
41534
    { 0, 0, 0, 0 },
41535
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), 0 } },
41536
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1b7fc00 }
41537
  },
41538
/* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
41539
  {
41540
    { 0, 0, 0, 0 },
41541
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
41542
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a78c00 }
41543
  },
41544
/* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
41545
  {
41546
    { 0, 0, 0, 0 },
41547
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), 0 } },
41548
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a7ac00 }
41549
  },
41550
/* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
41551
  {
41552
    { 0, 0, 0, 0 },
41553
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), 0 } },
41554
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a7bc00 }
41555
  },
41556
/* min.w${X} ${Dsp-24-u16},${Dsp-40-u24} */
41557
  {
41558
    { 0, 0, 0, 0 },
41559
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), 0 } },
41560
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1b7bc00 }
41561
  },
41562
/* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
41563
  {
41564
    { 0, 0, 0, 0 },
41565
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
41566
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b90c00 }
41567
  },
41568
/* min.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */
41569
  {
41570
    { 0, 0, 0, 0 },
41571
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32RNPREFIXEDHI), 0 } },
41572
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b92c00 }
41573
  },
41574
/* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
41575
  {
41576
    { 0, 0, 0, 0 },
41577
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
41578
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b18c00 }
41579
  },
41580
/* min.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */
41581
  {
41582
    { 0, 0, 0, 0 },
41583
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32ANPREFIXEDHI), 0 } },
41584
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b1ac00 }
41585
  },
41586
/* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
41587
  {
41588
    { 0, 0, 0, 0 },
41589
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
41590
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b10c00 }
41591
  },
41592
/* min.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
41593
  {
41594
    { 0, 0, 0, 0 },
41595
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
41596
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b12c00 }
41597
  },
41598
/* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
41599
  {
41600
    { 0, 0, 0, 0 },
41601
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
41602
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b30c00 }
41603
  },
41604
/* min.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
41605
  {
41606
    { 0, 0, 0, 0 },
41607
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
41608
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b32c00 }
41609
  },
41610
/* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
41611
  {
41612
    { 0, 0, 0, 0 },
41613
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
41614
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b50c00 }
41615
  },
41616
/* min.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
41617
  {
41618
    { 0, 0, 0, 0 },
41619
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
41620
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b52c00 }
41621
  },
41622
/* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
41623
  {
41624
    { 0, 0, 0, 0 },
41625
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
41626
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b70c00 }
41627
  },
41628
/* min.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
41629
  {
41630
    { 0, 0, 0, 0 },
41631
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
41632
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b72c00 }
41633
  },
41634
/* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
41635
  {
41636
    { 0, 0, 0, 0 },
41637
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
41638
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b38c00 }
41639
  },
41640
/* min.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
41641
  {
41642
    { 0, 0, 0, 0 },
41643
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
41644
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b3ac00 }
41645
  },
41646
/* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
41647
  {
41648
    { 0, 0, 0, 0 },
41649
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
41650
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b58c00 }
41651
  },
41652
/* min.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
41653
  {
41654
    { 0, 0, 0, 0 },
41655
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
41656
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b5ac00 }
41657
  },
41658
/* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
41659
  {
41660
    { 0, 0, 0, 0 },
41661
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
41662
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b3cc00 }
41663
  },
41664
/* min.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
41665
  {
41666
    { 0, 0, 0, 0 },
41667
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
41668
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b3ec00 }
41669
  },
41670
/* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
41671
  {
41672
    { 0, 0, 0, 0 },
41673
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
41674
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b5cc00 }
41675
  },
41676
/* min.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
41677
  {
41678
    { 0, 0, 0, 0 },
41679
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
41680
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b5ec00 }
41681
  },
41682
/* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
41683
  {
41684
    { 0, 0, 0, 0 },
41685
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), 0 } },
41686
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_absolute_Prefixed_HI, { 0x1b7cc00 }
41687
  },
41688
/* min.w${X} ${Dsp-24-u24},${Dsp-48-u16} */
41689
  {
41690
    { 0, 0, 0, 0 },
41691
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), 0 } },
41692
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_absolute_Prefixed_HI, { 0x1b7ec00 }
41693
  },
41694
/* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
41695
  {
41696
    { 0, 0, 0, 0 },
41697
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), 0 } },
41698
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_24_absolute_Prefixed_HI, { 0x1b78c00 }
41699
  },
41700
/* min.w${X} ${Dsp-24-u24},${Dsp-48-u24} */
41701
  {
41702
    { 0, 0, 0, 0 },
41703
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), 0 } },
41704
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_24_absolute_Prefixed_HI, { 0x1b7ac00 }
41705
  },
41706
/* min.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */
41707
  {
41708
    { 0, 0, 0, 0 },
41709
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DST32RNPREFIXEDHI), 0 } },
41710
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1c90c }
41711
  },
41712
/* min.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */
41713
  {
41714
    { 0, 0, 0, 0 },
41715
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DST32RNPREFIXEDHI), 0 } },
41716
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1892c }
41717
  },
41718
/* min.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */
41719
  {
41720
    { 0, 0, 0, 0 },
41721
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
41722
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1890c }
41723
  },
41724
/* min.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */
41725
  {
41726
    { 0, 0, 0, 0 },
41727
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DST32ANPREFIXEDHI), 0 } },
41728
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1c18c }
41729
  },
41730
/* min.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */
41731
  {
41732
    { 0, 0, 0, 0 },
41733
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DST32ANPREFIXEDHI), 0 } },
41734
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x181ac }
41735
  },
41736
/* min.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */
41737
  {
41738
    { 0, 0, 0, 0 },
41739
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
41740
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1818c }
41741
  },
41742
/* min.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */
41743
  {
41744
    { 0, 0, 0, 0 },
41745
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
41746
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1c10c }
41747
  },
41748
/* min.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */
41749
  {
41750
    { 0, 0, 0, 0 },
41751
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
41752
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1812c }
41753
  },
41754
/* min.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
41755
  {
41756
    { 0, 0, 0, 0 },
41757
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
41758
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1810c }
41759
  },
41760
/* min.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
41761
  {
41762
    { 0, 0, 0, 0 },
41763
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
41764
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1c30c00 }
41765
  },
41766
/* min.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
41767
  {
41768
    { 0, 0, 0, 0 },
41769
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
41770
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1832c00 }
41771
  },
41772
/* min.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
41773
  {
41774
    { 0, 0, 0, 0 },
41775
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
41776
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1830c00 }
41777
  },
41778
/* min.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
41779
  {
41780
    { 0, 0, 0, 0 },
41781
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
41782
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1c50c00 }
41783
  },
41784
/* min.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
41785
  {
41786
    { 0, 0, 0, 0 },
41787
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
41788
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1852c00 }
41789
  },
41790
/* min.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
41791
  {
41792
    { 0, 0, 0, 0 },
41793
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
41794
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1850c00 }
41795
  },
41796
/* min.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
41797
  {
41798
    { 0, 0, 0, 0 },
41799
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
41800
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1c70c00 }
41801
  },
41802
/* min.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
41803
  {
41804
    { 0, 0, 0, 0 },
41805
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
41806
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1872c00 }
41807
  },
41808
/* min.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
41809
  {
41810
    { 0, 0, 0, 0 },
41811
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
41812
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1870c00 }
41813
  },
41814
/* min.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */
41815
  {
41816
    { 0, 0, 0, 0 },
41817
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
41818
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1c38c00 }
41819
  },
41820
/* min.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */
41821
  {
41822
    { 0, 0, 0, 0 },
41823
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
41824
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x183ac00 }
41825
  },
41826
/* min.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
41827
  {
41828
    { 0, 0, 0, 0 },
41829
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
41830
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1838c00 }
41831
  },
41832
/* min.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */
41833
  {
41834
    { 0, 0, 0, 0 },
41835
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
41836
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1c58c00 }
41837
  },
41838
/* min.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */
41839
  {
41840
    { 0, 0, 0, 0 },
41841
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
41842
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x185ac00 }
41843
  },
41844
/* min.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
41845
  {
41846
    { 0, 0, 0, 0 },
41847
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
41848
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1858c00 }
41849
  },
41850
/* min.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */
41851
  {
41852
    { 0, 0, 0, 0 },
41853
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
41854
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x1c3cc00 }
41855
  },
41856
/* min.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */
41857
  {
41858
    { 0, 0, 0, 0 },
41859
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
41860
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x183ec00 }
41861
  },
41862
/* min.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
41863
  {
41864
    { 0, 0, 0, 0 },
41865
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
41866
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x183cc00 }
41867
  },
41868
/* min.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */
41869
  {
41870
    { 0, 0, 0, 0 },
41871
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
41872
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x1c5cc00 }
41873
  },
41874
/* min.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */
41875
  {
41876
    { 0, 0, 0, 0 },
41877
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
41878
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x185ec00 }
41879
  },
41880
/* min.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
41881
  {
41882
    { 0, 0, 0, 0 },
41883
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
41884
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x185cc00 }
41885
  },
41886
/* min.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */
41887
  {
41888
    { 0, 0, 0, 0 },
41889
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), 0 } },
41890
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x1c7cc00 }
41891
  },
41892
/* min.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */
41893
  {
41894
    { 0, 0, 0, 0 },
41895
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), 0 } },
41896
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x187ec00 }
41897
  },
41898
/* min.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */
41899
  {
41900
    { 0, 0, 0, 0 },
41901
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
41902
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x187cc00 }
41903
  },
41904
/* min.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */
41905
  {
41906
    { 0, 0, 0, 0 },
41907
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U24), 0 } },
41908
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x1c78c00 }
41909
  },
41910
/* min.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */
41911
  {
41912
    { 0, 0, 0, 0 },
41913
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U24), 0 } },
41914
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x187ac00 }
41915
  },
41916
/* min.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */
41917
  {
41918
    { 0, 0, 0, 0 },
41919
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
41920
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x1878c00 }
41921
  },
41922
/* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
41923
  {
41924
    { 0, 0, 0, 0 },
41925
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
41926
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1980c00 }
41927
  },
41928
/* min.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */
41929
  {
41930
    { 0, 0, 0, 0 },
41931
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
41932
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1982c00 }
41933
  },
41934
/* min.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */
41935
  {
41936
    { 0, 0, 0, 0 },
41937
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
41938
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1983c00 }
41939
  },
41940
/* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
41941
  {
41942
    { 0, 0, 0, 0 },
41943
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
41944
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1908c00 }
41945
  },
41946
/* min.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */
41947
  {
41948
    { 0, 0, 0, 0 },
41949
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
41950
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x190ac00 }
41951
  },
41952
/* min.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */
41953
  {
41954
    { 0, 0, 0, 0 },
41955
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
41956
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x190bc00 }
41957
  },
41958
/* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
41959
  {
41960
    { 0, 0, 0, 0 },
41961
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
41962
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1900c00 }
41963
  },
41964
/* min.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
41965
  {
41966
    { 0, 0, 0, 0 },
41967
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
41968
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1902c00 }
41969
  },
41970
/* min.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
41971
  {
41972
    { 0, 0, 0, 0 },
41973
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
41974
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1903c00 }
41975
  },
41976
/* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
41977
  {
41978
    { 0, 0, 0, 0 },
41979
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
41980
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1920c00 }
41981
  },
41982
/* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
41983
  {
41984
    { 0, 0, 0, 0 },
41985
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
41986
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1922c00 }
41987
  },
41988
/* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
41989
  {
41990
    { 0, 0, 0, 0 },
41991
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
41992
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1923c00 }
41993
  },
41994
/* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
41995
  {
41996
    { 0, 0, 0, 0 },
41997
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
41998
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1940c00 }
41999
  },
42000
/* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
42001
  {
42002
    { 0, 0, 0, 0 },
42003
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
42004
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1942c00 }
42005
  },
42006
/* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
42007
  {
42008
    { 0, 0, 0, 0 },
42009
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
42010
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1943c00 }
42011
  },
42012
/* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
42013
  {
42014
    { 0, 0, 0, 0 },
42015
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
42016
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1960c00 }
42017
  },
42018
/* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
42019
  {
42020
    { 0, 0, 0, 0 },
42021
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
42022
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1962c00 }
42023
  },
42024
/* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
42025
  {
42026
    { 0, 0, 0, 0 },
42027
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
42028
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1963c00 }
42029
  },
42030
/* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
42031
  {
42032
    { 0, 0, 0, 0 },
42033
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
42034
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x1928c00 }
42035
  },
42036
/* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
42037
  {
42038
    { 0, 0, 0, 0 },
42039
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
42040
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x192ac00 }
42041
  },
42042
/* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
42043
  {
42044
    { 0, 0, 0, 0 },
42045
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
42046
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x192bc00 }
42047
  },
42048
/* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
42049
  {
42050
    { 0, 0, 0, 0 },
42051
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
42052
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x1948c00 }
42053
  },
42054
/* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
42055
  {
42056
    { 0, 0, 0, 0 },
42057
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
42058
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x194ac00 }
42059
  },
42060
/* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
42061
  {
42062
    { 0, 0, 0, 0 },
42063
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
42064
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x194bc00 }
42065
  },
42066
/* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
42067
  {
42068
    { 0, 0, 0, 0 },
42069
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
42070
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192cc00 }
42071
  },
42072
/* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
42073
  {
42074
    { 0, 0, 0, 0 },
42075
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
42076
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192ec00 }
42077
  },
42078
/* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
42079
  {
42080
    { 0, 0, 0, 0 },
42081
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
42082
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192fc00 }
42083
  },
42084
/* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
42085
  {
42086
    { 0, 0, 0, 0 },
42087
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
42088
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194cc00 }
42089
  },
42090
/* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
42091
  {
42092
    { 0, 0, 0, 0 },
42093
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
42094
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194ec00 }
42095
  },
42096
/* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
42097
  {
42098
    { 0, 0, 0, 0 },
42099
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
42100
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194fc00 }
42101
  },
42102
/* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
42103
  {
42104
    { 0, 0, 0, 0 },
42105
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
42106
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196cc00 }
42107
  },
42108
/* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
42109
  {
42110
    { 0, 0, 0, 0 },
42111
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
42112
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196ec00 }
42113
  },
42114
/* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
42115
  {
42116
    { 0, 0, 0, 0 },
42117
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
42118
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196fc00 }
42119
  },
42120
/* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
42121
  {
42122
    { 0, 0, 0, 0 },
42123
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
42124
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x1968c00 }
42125
  },
42126
/* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
42127
  {
42128
    { 0, 0, 0, 0 },
42129
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
42130
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x196ac00 }
42131
  },
42132
/* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
42133
  {
42134
    { 0, 0, 0, 0 },
42135
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
42136
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x196bc00 }
42137
  },
42138
/* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
42139
  {
42140
    { 0, 0, 0, 0 },
42141
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
42142
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a80c00 }
42143
  },
42144
/* min.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */
42145
  {
42146
    { 0, 0, 0, 0 },
42147
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
42148
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a82c00 }
42149
  },
42150
/* min.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */
42151
  {
42152
    { 0, 0, 0, 0 },
42153
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
42154
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a83c00 }
42155
  },
42156
/* min.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */
42157
  {
42158
    { 0, 0, 0, 0 },
42159
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32RNPREFIXEDQI), 0 } },
42160
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b83c00 }
42161
  },
42162
/* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
42163
  {
42164
    { 0, 0, 0, 0 },
42165
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
42166
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a08c00 }
42167
  },
42168
/* min.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */
42169
  {
42170
    { 0, 0, 0, 0 },
42171
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
42172
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a0ac00 }
42173
  },
42174
/* min.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */
42175
  {
42176
    { 0, 0, 0, 0 },
42177
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
42178
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a0bc00 }
42179
  },
42180
/* min.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */
42181
  {
42182
    { 0, 0, 0, 0 },
42183
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32ANPREFIXEDQI), 0 } },
42184
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b0bc00 }
42185
  },
42186
/* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
42187
  {
42188
    { 0, 0, 0, 0 },
42189
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
42190
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a00c00 }
42191
  },
42192
/* min.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
42193
  {
42194
    { 0, 0, 0, 0 },
42195
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
42196
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a02c00 }
42197
  },
42198
/* min.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
42199
  {
42200
    { 0, 0, 0, 0 },
42201
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
42202
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a03c00 }
42203
  },
42204
/* min.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
42205
  {
42206
    { 0, 0, 0, 0 },
42207
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
42208
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b03c00 }
42209
  },
42210
/* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
42211
  {
42212
    { 0, 0, 0, 0 },
42213
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
42214
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a20c00 }
42215
  },
42216
/* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
42217
  {
42218
    { 0, 0, 0, 0 },
42219
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
42220
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a22c00 }
42221
  },
42222
/* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
42223
  {
42224
    { 0, 0, 0, 0 },
42225
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
42226
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a23c00 }
42227
  },
42228
/* min.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
42229
  {
42230
    { 0, 0, 0, 0 },
42231
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
42232
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1b23c00 }
42233
  },
42234
/* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
42235
  {
42236
    { 0, 0, 0, 0 },
42237
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
42238
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a40c00 }
42239
  },
42240
/* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
42241
  {
42242
    { 0, 0, 0, 0 },
42243
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
42244
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a42c00 }
42245
  },
42246
/* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
42247
  {
42248
    { 0, 0, 0, 0 },
42249
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
42250
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a43c00 }
42251
  },
42252
/* min.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
42253
  {
42254
    { 0, 0, 0, 0 },
42255
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
42256
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1b43c00 }
42257
  },
42258
/* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
42259
  {
42260
    { 0, 0, 0, 0 },
42261
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
42262
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a60c00 }
42263
  },
42264
/* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
42265
  {
42266
    { 0, 0, 0, 0 },
42267
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
42268
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a62c00 }
42269
  },
42270
/* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
42271
  {
42272
    { 0, 0, 0, 0 },
42273
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
42274
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a63c00 }
42275
  },
42276
/* min.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
42277
  {
42278
    { 0, 0, 0, 0 },
42279
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
42280
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1b63c00 }
42281
  },
42282
/* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
42283
  {
42284
    { 0, 0, 0, 0 },
42285
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
42286
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a28c00 }
42287
  },
42288
/* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
42289
  {
42290
    { 0, 0, 0, 0 },
42291
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
42292
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a2ac00 }
42293
  },
42294
/* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
42295
  {
42296
    { 0, 0, 0, 0 },
42297
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
42298
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a2bc00 }
42299
  },
42300
/* min.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
42301
  {
42302
    { 0, 0, 0, 0 },
42303
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
42304
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1b2bc00 }
42305
  },
42306
/* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
42307
  {
42308
    { 0, 0, 0, 0 },
42309
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
42310
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a48c00 }
42311
  },
42312
/* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
42313
  {
42314
    { 0, 0, 0, 0 },
42315
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
42316
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a4ac00 }
42317
  },
42318
/* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
42319
  {
42320
    { 0, 0, 0, 0 },
42321
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
42322
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a4bc00 }
42323
  },
42324
/* min.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
42325
  {
42326
    { 0, 0, 0, 0 },
42327
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
42328
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1b4bc00 }
42329
  },
42330
/* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
42331
  {
42332
    { 0, 0, 0, 0 },
42333
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
42334
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2cc00 }
42335
  },
42336
/* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
42337
  {
42338
    { 0, 0, 0, 0 },
42339
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
42340
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2ec00 }
42341
  },
42342
/* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
42343
  {
42344
    { 0, 0, 0, 0 },
42345
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
42346
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2fc00 }
42347
  },
42348
/* min.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
42349
  {
42350
    { 0, 0, 0, 0 },
42351
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
42352
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1b2fc00 }
42353
  },
42354
/* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
42355
  {
42356
    { 0, 0, 0, 0 },
42357
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
42358
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4cc00 }
42359
  },
42360
/* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
42361
  {
42362
    { 0, 0, 0, 0 },
42363
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
42364
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4ec00 }
42365
  },
42366
/* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
42367
  {
42368
    { 0, 0, 0, 0 },
42369
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
42370
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4fc00 }
42371
  },
42372
/* min.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
42373
  {
42374
    { 0, 0, 0, 0 },
42375
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
42376
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1b4fc00 }
42377
  },
42378
/* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
42379
  {
42380
    { 0, 0, 0, 0 },
42381
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
42382
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6cc00 }
42383
  },
42384
/* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
42385
  {
42386
    { 0, 0, 0, 0 },
42387
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), 0 } },
42388
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6ec00 }
42389
  },
42390
/* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
42391
  {
42392
    { 0, 0, 0, 0 },
42393
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), 0 } },
42394
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6fc00 }
42395
  },
42396
/* min.b${X} ${Dsp-24-u16},${Dsp-40-u16} */
42397
  {
42398
    { 0, 0, 0, 0 },
42399
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), 0 } },
42400
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1b6fc00 }
42401
  },
42402
/* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
42403
  {
42404
    { 0, 0, 0, 0 },
42405
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
42406
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a68c00 }
42407
  },
42408
/* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
42409
  {
42410
    { 0, 0, 0, 0 },
42411
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), 0 } },
42412
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a6ac00 }
42413
  },
42414
/* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
42415
  {
42416
    { 0, 0, 0, 0 },
42417
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), 0 } },
42418
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a6bc00 }
42419
  },
42420
/* min.b${X} ${Dsp-24-u16},${Dsp-40-u24} */
42421
  {
42422
    { 0, 0, 0, 0 },
42423
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), 0 } },
42424
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1b6bc00 }
42425
  },
42426
/* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
42427
  {
42428
    { 0, 0, 0, 0 },
42429
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
42430
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b80c00 }
42431
  },
42432
/* min.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */
42433
  {
42434
    { 0, 0, 0, 0 },
42435
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32RNPREFIXEDQI), 0 } },
42436
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b82c00 }
42437
  },
42438
/* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
42439
  {
42440
    { 0, 0, 0, 0 },
42441
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
42442
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b08c00 }
42443
  },
42444
/* min.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */
42445
  {
42446
    { 0, 0, 0, 0 },
42447
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32ANPREFIXEDQI), 0 } },
42448
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b0ac00 }
42449
  },
42450
/* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
42451
  {
42452
    { 0, 0, 0, 0 },
42453
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
42454
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b00c00 }
42455
  },
42456
/* min.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
42457
  {
42458
    { 0, 0, 0, 0 },
42459
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
42460
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b02c00 }
42461
  },
42462
/* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
42463
  {
42464
    { 0, 0, 0, 0 },
42465
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
42466
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_An_relative_Prefixed_QI, { 0x1b20c00 }
42467
  },
42468
/* min.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
42469
  {
42470
    { 0, 0, 0, 0 },
42471
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
42472
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_An_relative_Prefixed_QI, { 0x1b22c00 }
42473
  },
42474
/* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
42475
  {
42476
    { 0, 0, 0, 0 },
42477
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
42478
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_An_relative_Prefixed_QI, { 0x1b40c00 }
42479
  },
42480
/* min.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
42481
  {
42482
    { 0, 0, 0, 0 },
42483
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
42484
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_An_relative_Prefixed_QI, { 0x1b42c00 }
42485
  },
42486
/* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
42487
  {
42488
    { 0, 0, 0, 0 },
42489
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
42490
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_An_relative_Prefixed_QI, { 0x1b60c00 }
42491
  },
42492
/* min.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
42493
  {
42494
    { 0, 0, 0, 0 },
42495
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
42496
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_An_relative_Prefixed_QI, { 0x1b62c00 }
42497
  },
42498
/* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
42499
  {
42500
    { 0, 0, 0, 0 },
42501
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
42502
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_QI, { 0x1b28c00 }
42503
  },
42504
/* min.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
42505
  {
42506
    { 0, 0, 0, 0 },
42507
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
42508
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_QI, { 0x1b2ac00 }
42509
  },
42510
/* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
42511
  {
42512
    { 0, 0, 0, 0 },
42513
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
42514
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_QI, { 0x1b48c00 }
42515
  },
42516
/* min.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
42517
  {
42518
    { 0, 0, 0, 0 },
42519
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
42520
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_QI, { 0x1b4ac00 }
42521
  },
42522
/* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
42523
  {
42524
    { 0, 0, 0, 0 },
42525
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
42526
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_QI, { 0x1b2cc00 }
42527
  },
42528
/* min.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
42529
  {
42530
    { 0, 0, 0, 0 },
42531
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
42532
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_QI, { 0x1b2ec00 }
42533
  },
42534
/* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
42535
  {
42536
    { 0, 0, 0, 0 },
42537
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
42538
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_QI, { 0x1b4cc00 }
42539
  },
42540
/* min.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
42541
  {
42542
    { 0, 0, 0, 0 },
42543
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
42544
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_QI, { 0x1b4ec00 }
42545
  },
42546
/* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
42547
  {
42548
    { 0, 0, 0, 0 },
42549
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), 0 } },
42550
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_absolute_Prefixed_QI, { 0x1b6cc00 }
42551
  },
42552
/* min.b${X} ${Dsp-24-u24},${Dsp-48-u16} */
42553
  {
42554
    { 0, 0, 0, 0 },
42555
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), 0 } },
42556
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_absolute_Prefixed_QI, { 0x1b6ec00 }
42557
  },
42558
/* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
42559
  {
42560
    { 0, 0, 0, 0 },
42561
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), 0 } },
42562
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_absolute_Prefixed_QI, { 0x1b68c00 }
42563
  },
42564
/* min.b${X} ${Dsp-24-u24},${Dsp-48-u24} */
42565
  {
42566
    { 0, 0, 0, 0 },
42567
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), 0 } },
42568
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_absolute_Prefixed_QI, { 0x1b6ac00 }
42569
  },
42570
/* min.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */
42571
  {
42572
    { 0, 0, 0, 0 },
42573
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32RNPREFIXEDQI), 0 } },
42574
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1c80c }
42575
  },
42576
/* min.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */
42577
  {
42578
    { 0, 0, 0, 0 },
42579
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DST32RNPREFIXEDQI), 0 } },
42580
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1882c }
42581
  },
42582
/* min.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */
42583
  {
42584
    { 0, 0, 0, 0 },
42585
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
42586
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1880c }
42587
  },
42588
/* min.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */
42589
  {
42590
    { 0, 0, 0, 0 },
42591
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32ANPREFIXEDQI), 0 } },
42592
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1c08c }
42593
  },
42594
/* min.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */
42595
  {
42596
    { 0, 0, 0, 0 },
42597
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DST32ANPREFIXEDQI), 0 } },
42598
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x180ac }
42599
  },
42600
/* min.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */
42601
  {
42602
    { 0, 0, 0, 0 },
42603
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
42604
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1808c }
42605
  },
42606
/* min.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
42607
  {
42608
    { 0, 0, 0, 0 },
42609
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
42610
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1c00c }
42611
  },
42612
/* min.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */
42613
  {
42614
    { 0, 0, 0, 0 },
42615
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
42616
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1802c }
42617
  },
42618
/* min.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
42619
  {
42620
    { 0, 0, 0, 0 },
42621
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
42622
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1800c }
42623
  },
42624
/* min.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
42625
  {
42626
    { 0, 0, 0, 0 },
42627
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
42628
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1c20c00 }
42629
  },
42630
/* min.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
42631
  {
42632
    { 0, 0, 0, 0 },
42633
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
42634
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1822c00 }
42635
  },
42636
/* min.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
42637
  {
42638
    { 0, 0, 0, 0 },
42639
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
42640
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1820c00 }
42641
  },
42642
/* min.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
42643
  {
42644
    { 0, 0, 0, 0 },
42645
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
42646
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1c40c00 }
42647
  },
42648
/* min.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
42649
  {
42650
    { 0, 0, 0, 0 },
42651
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
42652
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1842c00 }
42653
  },
42654
/* min.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
42655
  {
42656
    { 0, 0, 0, 0 },
42657
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
42658
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1840c00 }
42659
  },
42660
/* min.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
42661
  {
42662
    { 0, 0, 0, 0 },
42663
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
42664
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1c60c00 }
42665
  },
42666
/* min.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
42667
  {
42668
    { 0, 0, 0, 0 },
42669
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
42670
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1862c00 }
42671
  },
42672
/* min.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
42673
  {
42674
    { 0, 0, 0, 0 },
42675
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
42676
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1860c00 }
42677
  },
42678
/* min.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
42679
  {
42680
    { 0, 0, 0, 0 },
42681
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
42682
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x1c28c00 }
42683
  },
42684
/* min.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */
42685
  {
42686
    { 0, 0, 0, 0 },
42687
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
42688
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x182ac00 }
42689
  },
42690
/* min.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
42691
  {
42692
    { 0, 0, 0, 0 },
42693
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
42694
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x1828c00 }
42695
  },
42696
/* min.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
42697
  {
42698
    { 0, 0, 0, 0 },
42699
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
42700
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x1c48c00 }
42701
  },
42702
/* min.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */
42703
  {
42704
    { 0, 0, 0, 0 },
42705
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
42706
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x184ac00 }
42707
  },
42708
/* min.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
42709
  {
42710
    { 0, 0, 0, 0 },
42711
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
42712
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x1848c00 }
42713
  },
42714
/* min.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
42715
  {
42716
    { 0, 0, 0, 0 },
42717
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
42718
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x1c2cc00 }
42719
  },
42720
/* min.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */
42721
  {
42722
    { 0, 0, 0, 0 },
42723
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
42724
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x182ec00 }
42725
  },
42726
/* min.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
42727
  {
42728
    { 0, 0, 0, 0 },
42729
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
42730
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x182cc00 }
42731
  },
42732
/* min.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
42733
  {
42734
    { 0, 0, 0, 0 },
42735
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
42736
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x1c4cc00 }
42737
  },
42738
/* min.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */
42739
  {
42740
    { 0, 0, 0, 0 },
42741
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
42742
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x184ec00 }
42743
  },
42744
/* min.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
42745
  {
42746
    { 0, 0, 0, 0 },
42747
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
42748
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x184cc00 }
42749
  },
42750
/* min.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */
42751
  {
42752
    { 0, 0, 0, 0 },
42753
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), 0 } },
42754
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x1c6cc00 }
42755
  },
42756
/* min.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */
42757
  {
42758
    { 0, 0, 0, 0 },
42759
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), 0 } },
42760
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x186ec00 }
42761
  },
42762
/* min.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */
42763
  {
42764
    { 0, 0, 0, 0 },
42765
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
42766
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x186cc00 }
42767
  },
42768
/* min.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */
42769
  {
42770
    { 0, 0, 0, 0 },
42771
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), 0 } },
42772
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x1c68c00 }
42773
  },
42774
/* min.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */
42775
  {
42776
    { 0, 0, 0, 0 },
42777
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U24), 0 } },
42778
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x186ac00 }
42779
  },
42780
/* min.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */
42781
  {
42782
    { 0, 0, 0, 0 },
42783
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
42784
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x1868c00 }
42785
  },
42786
/* min.w${X} #${Imm-24-HI},$Dst32RnPrefixedHI */
42787
  {
42788
    { 0, 0, 0, 0 },
42789
    { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DST32RNPREFIXEDHI), 0 } },
42790
    & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_Rn_direct_Prefixed_HI, { 0x1892f00 }
42791
  },
42792
/* min.w${X} #${Imm-24-HI},$Dst32AnPrefixedHI */
42793
  {
42794
    { 0, 0, 0, 0 },
42795
    { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DST32ANPREFIXEDHI), 0 } },
42796
    & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_An_direct_Prefixed_HI, { 0x181af00 }
42797
  },
42798
/* min.w${X} #${Imm-24-HI},[$Dst32AnPrefixed] */
42799
  {
42800
    { 0, 0, 0, 0 },
42801
    { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
42802
    & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_An_indirect_Prefixed_HI, { 0x1812f00 }
42803
  },
42804
/* min.w${X} #${Imm-32-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */
42805
  {
42806
    { 0, 0, 0, 0 },
42807
    { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
42808
    & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_An_relative_Prefixed_HI, { 0x1832f00 }
42809
  },
42810
/* min.w${X} #${Imm-32-HI},${Dsp-24-u8}[sb] */
42811
  {
42812
    { 0, 0, 0, 0 },
42813
    { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
42814
    & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_SB_relative_Prefixed_HI, { 0x183af00 }
42815
  },
42816
/* min.w${X} #${Imm-32-HI},${Dsp-24-s8}[fb] */
42817
  {
42818
    { 0, 0, 0, 0 },
42819
    { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
42820
    & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_FB_relative_Prefixed_HI, { 0x183ef00 }
42821
  },
42822
/* min.w${X} #${Imm-40-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */
42823
  {
42824
    { 0, 0, 0, 0 },
42825
    { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
42826
    & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_An_relative_Prefixed_HI, { 0x1852f00 }
42827
  },
42828
/* min.w${X} #${Imm-40-HI},${Dsp-24-u16}[sb] */
42829
  {
42830
    { 0, 0, 0, 0 },
42831
    { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
42832
    & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_SB_relative_Prefixed_HI, { 0x185af00 }
42833
  },
42834
/* min.w${X} #${Imm-40-HI},${Dsp-24-s16}[fb] */
42835
  {
42836
    { 0, 0, 0, 0 },
42837
    { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
42838
    & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_FB_relative_Prefixed_HI, { 0x185ef00 }
42839
  },
42840
/* min.w${X} #${Imm-40-HI},${Dsp-24-u16} */
42841
  {
42842
    { 0, 0, 0, 0 },
42843
    { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), 0 } },
42844
    & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_absolute_Prefixed_HI, { 0x187ef00 }
42845
  },
42846
/* min.w${X} #${Imm-48-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */
42847
  {
42848
    { 0, 0, 0, 0 },
42849
    { { MNEM, OP (X), ' ', '#', OP (IMM_48_HI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
42850
    & ifmt_sbb32_w_imm_G_24_24_Prefixed_dst32_24_24_An_relative_Prefixed_HI, { 0x1872f00 }
42851
  },
42852
/* min.w${X} #${Imm-48-HI},${Dsp-24-u24} */
42853
  {
42854
    { 0, 0, 0, 0 },
42855
    { { MNEM, OP (X), ' ', '#', OP (IMM_48_HI), ',', OP (DSP_24_U24), 0 } },
42856
    & ifmt_sbb32_w_imm_G_24_24_Prefixed_dst32_24_24_absolute_Prefixed_HI, { 0x187af00 }
42857
  },
42858
/* min.b${X} #${Imm-24-QI},$Dst32RnPrefixedQI */
42859
  {
42860
    { 0, 0, 0, 0 },
42861
    { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DST32RNPREFIXEDQI), 0 } },
42862
    & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_Rn_direct_Prefixed_QI, { 0x1882f00 }
42863
  },
42864
/* min.b${X} #${Imm-24-QI},$Dst32AnPrefixedQI */
42865
  {
42866
    { 0, 0, 0, 0 },
42867
    { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DST32ANPREFIXEDQI), 0 } },
42868
    & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_An_direct_Prefixed_QI, { 0x180af00 }
42869
  },
42870
/* min.b${X} #${Imm-24-QI},[$Dst32AnPrefixed] */
42871
  {
42872
    { 0, 0, 0, 0 },
42873
    { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
42874
    & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_An_indirect_Prefixed_QI, { 0x1802f00 }
42875
  },
42876
/* min.b${X} #${Imm-32-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */
42877
  {
42878
    { 0, 0, 0, 0 },
42879
    { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
42880
    & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_An_relative_Prefixed_QI, { 0x1822f00 }
42881
  },
42882
/* min.b${X} #${Imm-32-QI},${Dsp-24-u8}[sb] */
42883
  {
42884
    { 0, 0, 0, 0 },
42885
    { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
42886
    & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_SB_relative_Prefixed_QI, { 0x182af00 }
42887
  },
42888
/* min.b${X} #${Imm-32-QI},${Dsp-24-s8}[fb] */
42889
  {
42890
    { 0, 0, 0, 0 },
42891
    { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
42892
    & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_FB_relative_Prefixed_QI, { 0x182ef00 }
42893
  },
42894
/* min.b${X} #${Imm-40-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */
42895
  {
42896
    { 0, 0, 0, 0 },
42897
    { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
42898
    & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_An_relative_Prefixed_QI, { 0x1842f00 }
42899
  },
42900
/* min.b${X} #${Imm-40-QI},${Dsp-24-u16}[sb] */
42901
  {
42902
    { 0, 0, 0, 0 },
42903
    { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
42904
    & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_SB_relative_Prefixed_QI, { 0x184af00 }
42905
  },
42906
/* min.b${X} #${Imm-40-QI},${Dsp-24-s16}[fb] */
42907
  {
42908
    { 0, 0, 0, 0 },
42909
    { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
42910
    & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_FB_relative_Prefixed_QI, { 0x184ef00 }
42911
  },
42912
/* min.b${X} #${Imm-40-QI},${Dsp-24-u16} */
42913
  {
42914
    { 0, 0, 0, 0 },
42915
    { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), 0 } },
42916
    & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_absolute_Prefixed_QI, { 0x186ef00 }
42917
  },
42918
/* min.b${X} #${Imm-48-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */
42919
  {
42920
    { 0, 0, 0, 0 },
42921
    { { MNEM, OP (X), ' ', '#', OP (IMM_48_QI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
42922
    & ifmt_sbb32_b_imm_G_24_24_Prefixed_dst32_24_24_An_relative_Prefixed_QI, { 0x1862f00 }
42923
  },
42924
/* min.b${X} #${Imm-48-QI},${Dsp-24-u24} */
42925
  {
42926
    { 0, 0, 0, 0 },
42927
    { { MNEM, OP (X), ' ', '#', OP (IMM_48_QI), ',', OP (DSP_24_U24), 0 } },
42928
    & ifmt_sbb32_b_imm_G_24_24_Prefixed_dst32_24_24_absolute_Prefixed_QI, { 0x186af00 }
42929
  },
42930
/* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
42931
  {
42932
    { 0, 0, 0, 0 },
42933
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
42934
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1990d00 }
42935
  },
42936
/* max.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
42937
  {
42938
    { 0, 0, 0, 0 },
42939
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
42940
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1992d00 }
42941
  },
42942
/* max.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
42943
  {
42944
    { 0, 0, 0, 0 },
42945
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
42946
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1993d00 }
42947
  },
42948
/* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
42949
  {
42950
    { 0, 0, 0, 0 },
42951
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
42952
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1918d00 }
42953
  },
42954
/* max.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
42955
  {
42956
    { 0, 0, 0, 0 },
42957
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
42958
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x191ad00 }
42959
  },
42960
/* max.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
42961
  {
42962
    { 0, 0, 0, 0 },
42963
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
42964
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x191bd00 }
42965
  },
42966
/* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
42967
  {
42968
    { 0, 0, 0, 0 },
42969
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
42970
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1910d00 }
42971
  },
42972
/* max.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
42973
  {
42974
    { 0, 0, 0, 0 },
42975
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
42976
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1912d00 }
42977
  },
42978
/* max.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
42979
  {
42980
    { 0, 0, 0, 0 },
42981
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
42982
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1913d00 }
42983
  },
42984
/* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
42985
  {
42986
    { 0, 0, 0, 0 },
42987
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
42988
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1930d00 }
42989
  },
42990
/* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
42991
  {
42992
    { 0, 0, 0, 0 },
42993
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
42994
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1932d00 }
42995
  },
42996
/* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
42997
  {
42998
    { 0, 0, 0, 0 },
42999
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
43000
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1933d00 }
43001
  },
43002
/* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
43003
  {
43004
    { 0, 0, 0, 0 },
43005
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
43006
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1950d00 }
43007
  },
43008
/* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
43009
  {
43010
    { 0, 0, 0, 0 },
43011
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
43012
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1952d00 }
43013
  },
43014
/* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
43015
  {
43016
    { 0, 0, 0, 0 },
43017
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
43018
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1953d00 }
43019
  },
43020
/* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
43021
  {
43022
    { 0, 0, 0, 0 },
43023
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
43024
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1970d00 }
43025
  },
43026
/* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
43027
  {
43028
    { 0, 0, 0, 0 },
43029
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
43030
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1972d00 }
43031
  },
43032
/* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
43033
  {
43034
    { 0, 0, 0, 0 },
43035
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
43036
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1973d00 }
43037
  },
43038
/* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
43039
  {
43040
    { 0, 0, 0, 0 },
43041
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
43042
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x1938d00 }
43043
  },
43044
/* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
43045
  {
43046
    { 0, 0, 0, 0 },
43047
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
43048
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x193ad00 }
43049
  },
43050
/* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
43051
  {
43052
    { 0, 0, 0, 0 },
43053
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
43054
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x193bd00 }
43055
  },
43056
/* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
43057
  {
43058
    { 0, 0, 0, 0 },
43059
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
43060
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x1958d00 }
43061
  },
43062
/* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
43063
  {
43064
    { 0, 0, 0, 0 },
43065
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
43066
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x195ad00 }
43067
  },
43068
/* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
43069
  {
43070
    { 0, 0, 0, 0 },
43071
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
43072
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x195bd00 }
43073
  },
43074
/* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
43075
  {
43076
    { 0, 0, 0, 0 },
43077
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
43078
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193cd00 }
43079
  },
43080
/* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
43081
  {
43082
    { 0, 0, 0, 0 },
43083
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
43084
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193ed00 }
43085
  },
43086
/* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
43087
  {
43088
    { 0, 0, 0, 0 },
43089
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
43090
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193fd00 }
43091
  },
43092
/* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
43093
  {
43094
    { 0, 0, 0, 0 },
43095
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
43096
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195cd00 }
43097
  },
43098
/* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
43099
  {
43100
    { 0, 0, 0, 0 },
43101
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
43102
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195ed00 }
43103
  },
43104
/* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
43105
  {
43106
    { 0, 0, 0, 0 },
43107
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
43108
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195fd00 }
43109
  },
43110
/* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
43111
  {
43112
    { 0, 0, 0, 0 },
43113
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
43114
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197cd00 }
43115
  },
43116
/* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
43117
  {
43118
    { 0, 0, 0, 0 },
43119
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
43120
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197ed00 }
43121
  },
43122
/* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
43123
  {
43124
    { 0, 0, 0, 0 },
43125
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
43126
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197fd00 }
43127
  },
43128
/* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
43129
  {
43130
    { 0, 0, 0, 0 },
43131
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
43132
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x1978d00 }
43133
  },
43134
/* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
43135
  {
43136
    { 0, 0, 0, 0 },
43137
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
43138
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x197ad00 }
43139
  },
43140
/* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
43141
  {
43142
    { 0, 0, 0, 0 },
43143
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
43144
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x197bd00 }
43145
  },
43146
/* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
43147
  {
43148
    { 0, 0, 0, 0 },
43149
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
43150
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a90d00 }
43151
  },
43152
/* max.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
43153
  {
43154
    { 0, 0, 0, 0 },
43155
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
43156
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a92d00 }
43157
  },
43158
/* max.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
43159
  {
43160
    { 0, 0, 0, 0 },
43161
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
43162
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a93d00 }
43163
  },
43164
/* max.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */
43165
  {
43166
    { 0, 0, 0, 0 },
43167
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32RNPREFIXEDHI), 0 } },
43168
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b93d00 }
43169
  },
43170
/* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
43171
  {
43172
    { 0, 0, 0, 0 },
43173
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
43174
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a18d00 }
43175
  },
43176
/* max.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
43177
  {
43178
    { 0, 0, 0, 0 },
43179
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
43180
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a1ad00 }
43181
  },
43182
/* max.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
43183
  {
43184
    { 0, 0, 0, 0 },
43185
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
43186
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a1bd00 }
43187
  },
43188
/* max.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */
43189
  {
43190
    { 0, 0, 0, 0 },
43191
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32ANPREFIXEDHI), 0 } },
43192
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b1bd00 }
43193
  },
43194
/* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
43195
  {
43196
    { 0, 0, 0, 0 },
43197
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
43198
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a10d00 }
43199
  },
43200
/* max.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
43201
  {
43202
    { 0, 0, 0, 0 },
43203
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
43204
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a12d00 }
43205
  },
43206
/* max.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
43207
  {
43208
    { 0, 0, 0, 0 },
43209
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
43210
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a13d00 }
43211
  },
43212
/* max.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
43213
  {
43214
    { 0, 0, 0, 0 },
43215
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
43216
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b13d00 }
43217
  },
43218
/* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
43219
  {
43220
    { 0, 0, 0, 0 },
43221
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
43222
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a30d00 }
43223
  },
43224
/* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
43225
  {
43226
    { 0, 0, 0, 0 },
43227
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
43228
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a32d00 }
43229
  },
43230
/* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
43231
  {
43232
    { 0, 0, 0, 0 },
43233
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
43234
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a33d00 }
43235
  },
43236
/* max.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
43237
  {
43238
    { 0, 0, 0, 0 },
43239
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
43240
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1b33d00 }
43241
  },
43242
/* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
43243
  {
43244
    { 0, 0, 0, 0 },
43245
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
43246
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a50d00 }
43247
  },
43248
/* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
43249
  {
43250
    { 0, 0, 0, 0 },
43251
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
43252
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a52d00 }
43253
  },
43254
/* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
43255
  {
43256
    { 0, 0, 0, 0 },
43257
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
43258
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a53d00 }
43259
  },
43260
/* max.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
43261
  {
43262
    { 0, 0, 0, 0 },
43263
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
43264
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1b53d00 }
43265
  },
43266
/* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
43267
  {
43268
    { 0, 0, 0, 0 },
43269
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
43270
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a70d00 }
43271
  },
43272
/* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
43273
  {
43274
    { 0, 0, 0, 0 },
43275
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
43276
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a72d00 }
43277
  },
43278
/* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
43279
  {
43280
    { 0, 0, 0, 0 },
43281
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
43282
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a73d00 }
43283
  },
43284
/* max.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
43285
  {
43286
    { 0, 0, 0, 0 },
43287
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
43288
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1b73d00 }
43289
  },
43290
/* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
43291
  {
43292
    { 0, 0, 0, 0 },
43293
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
43294
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a38d00 }
43295
  },
43296
/* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
43297
  {
43298
    { 0, 0, 0, 0 },
43299
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
43300
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a3ad00 }
43301
  },
43302
/* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
43303
  {
43304
    { 0, 0, 0, 0 },
43305
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
43306
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a3bd00 }
43307
  },
43308
/* max.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
43309
  {
43310
    { 0, 0, 0, 0 },
43311
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
43312
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1b3bd00 }
43313
  },
43314
/* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
43315
  {
43316
    { 0, 0, 0, 0 },
43317
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
43318
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a58d00 }
43319
  },
43320
/* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
43321
  {
43322
    { 0, 0, 0, 0 },
43323
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
43324
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a5ad00 }
43325
  },
43326
/* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
43327
  {
43328
    { 0, 0, 0, 0 },
43329
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
43330
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a5bd00 }
43331
  },
43332
/* max.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
43333
  {
43334
    { 0, 0, 0, 0 },
43335
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
43336
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1b5bd00 }
43337
  },
43338
/* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
43339
  {
43340
    { 0, 0, 0, 0 },
43341
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
43342
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3cd00 }
43343
  },
43344
/* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
43345
  {
43346
    { 0, 0, 0, 0 },
43347
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
43348
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3ed00 }
43349
  },
43350
/* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
43351
  {
43352
    { 0, 0, 0, 0 },
43353
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
43354
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3fd00 }
43355
  },
43356
/* max.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
43357
  {
43358
    { 0, 0, 0, 0 },
43359
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
43360
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1b3fd00 }
43361
  },
43362
/* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
43363
  {
43364
    { 0, 0, 0, 0 },
43365
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
43366
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5cd00 }
43367
  },
43368
/* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
43369
  {
43370
    { 0, 0, 0, 0 },
43371
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
43372
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5ed00 }
43373
  },
43374
/* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
43375
  {
43376
    { 0, 0, 0, 0 },
43377
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
43378
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5fd00 }
43379
  },
43380
/* max.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
43381
  {
43382
    { 0, 0, 0, 0 },
43383
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
43384
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1b5fd00 }
43385
  },
43386
/* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
43387
  {
43388
    { 0, 0, 0, 0 },
43389
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
43390
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7cd00 }
43391
  },
43392
/* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
43393
  {
43394
    { 0, 0, 0, 0 },
43395
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), 0 } },
43396
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7ed00 }
43397
  },
43398
/* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
43399
  {
43400
    { 0, 0, 0, 0 },
43401
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), 0 } },
43402
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7fd00 }
43403
  },
43404
/* max.w${X} ${Dsp-24-u16},${Dsp-40-u16} */
43405
  {
43406
    { 0, 0, 0, 0 },
43407
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), 0 } },
43408
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1b7fd00 }
43409
  },
43410
/* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
43411
  {
43412
    { 0, 0, 0, 0 },
43413
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
43414
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a78d00 }
43415
  },
43416
/* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
43417
  {
43418
    { 0, 0, 0, 0 },
43419
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), 0 } },
43420
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a7ad00 }
43421
  },
43422
/* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
43423
  {
43424
    { 0, 0, 0, 0 },
43425
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), 0 } },
43426
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a7bd00 }
43427
  },
43428
/* max.w${X} ${Dsp-24-u16},${Dsp-40-u24} */
43429
  {
43430
    { 0, 0, 0, 0 },
43431
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), 0 } },
43432
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1b7bd00 }
43433
  },
43434
/* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
43435
  {
43436
    { 0, 0, 0, 0 },
43437
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
43438
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b90d00 }
43439
  },
43440
/* max.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */
43441
  {
43442
    { 0, 0, 0, 0 },
43443
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32RNPREFIXEDHI), 0 } },
43444
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b92d00 }
43445
  },
43446
/* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
43447
  {
43448
    { 0, 0, 0, 0 },
43449
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
43450
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b18d00 }
43451
  },
43452
/* max.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */
43453
  {
43454
    { 0, 0, 0, 0 },
43455
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32ANPREFIXEDHI), 0 } },
43456
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b1ad00 }
43457
  },
43458
/* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
43459
  {
43460
    { 0, 0, 0, 0 },
43461
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
43462
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b10d00 }
43463
  },
43464
/* max.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
43465
  {
43466
    { 0, 0, 0, 0 },
43467
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
43468
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b12d00 }
43469
  },
43470
/* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
43471
  {
43472
    { 0, 0, 0, 0 },
43473
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
43474
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b30d00 }
43475
  },
43476
/* max.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
43477
  {
43478
    { 0, 0, 0, 0 },
43479
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
43480
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b32d00 }
43481
  },
43482
/* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
43483
  {
43484
    { 0, 0, 0, 0 },
43485
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
43486
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b50d00 }
43487
  },
43488
/* max.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
43489
  {
43490
    { 0, 0, 0, 0 },
43491
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
43492
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b52d00 }
43493
  },
43494
/* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
43495
  {
43496
    { 0, 0, 0, 0 },
43497
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
43498
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b70d00 }
43499
  },
43500
/* max.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
43501
  {
43502
    { 0, 0, 0, 0 },
43503
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
43504
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b72d00 }
43505
  },
43506
/* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
43507
  {
43508
    { 0, 0, 0, 0 },
43509
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
43510
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b38d00 }
43511
  },
43512
/* max.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
43513
  {
43514
    { 0, 0, 0, 0 },
43515
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
43516
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b3ad00 }
43517
  },
43518
/* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
43519
  {
43520
    { 0, 0, 0, 0 },
43521
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
43522
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b58d00 }
43523
  },
43524
/* max.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
43525
  {
43526
    { 0, 0, 0, 0 },
43527
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
43528
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b5ad00 }
43529
  },
43530
/* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
43531
  {
43532
    { 0, 0, 0, 0 },
43533
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
43534
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b3cd00 }
43535
  },
43536
/* max.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
43537
  {
43538
    { 0, 0, 0, 0 },
43539
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
43540
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b3ed00 }
43541
  },
43542
/* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
43543
  {
43544
    { 0, 0, 0, 0 },
43545
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
43546
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b5cd00 }
43547
  },
43548
/* max.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
43549
  {
43550
    { 0, 0, 0, 0 },
43551
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
43552
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b5ed00 }
43553
  },
43554
/* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
43555
  {
43556
    { 0, 0, 0, 0 },
43557
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), 0 } },
43558
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_absolute_Prefixed_HI, { 0x1b7cd00 }
43559
  },
43560
/* max.w${X} ${Dsp-24-u24},${Dsp-48-u16} */
43561
  {
43562
    { 0, 0, 0, 0 },
43563
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), 0 } },
43564
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_absolute_Prefixed_HI, { 0x1b7ed00 }
43565
  },
43566
/* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
43567
  {
43568
    { 0, 0, 0, 0 },
43569
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), 0 } },
43570
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_24_absolute_Prefixed_HI, { 0x1b78d00 }
43571
  },
43572
/* max.w${X} ${Dsp-24-u24},${Dsp-48-u24} */
43573
  {
43574
    { 0, 0, 0, 0 },
43575
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), 0 } },
43576
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_24_absolute_Prefixed_HI, { 0x1b7ad00 }
43577
  },
43578
/* max.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */
43579
  {
43580
    { 0, 0, 0, 0 },
43581
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DST32RNPREFIXEDHI), 0 } },
43582
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1c90d }
43583
  },
43584
/* max.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */
43585
  {
43586
    { 0, 0, 0, 0 },
43587
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DST32RNPREFIXEDHI), 0 } },
43588
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1892d }
43589
  },
43590
/* max.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */
43591
  {
43592
    { 0, 0, 0, 0 },
43593
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
43594
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1890d }
43595
  },
43596
/* max.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */
43597
  {
43598
    { 0, 0, 0, 0 },
43599
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DST32ANPREFIXEDHI), 0 } },
43600
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1c18d }
43601
  },
43602
/* max.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */
43603
  {
43604
    { 0, 0, 0, 0 },
43605
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DST32ANPREFIXEDHI), 0 } },
43606
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x181ad }
43607
  },
43608
/* max.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */
43609
  {
43610
    { 0, 0, 0, 0 },
43611
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
43612
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1818d }
43613
  },
43614
/* max.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */
43615
  {
43616
    { 0, 0, 0, 0 },
43617
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
43618
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1c10d }
43619
  },
43620
/* max.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */
43621
  {
43622
    { 0, 0, 0, 0 },
43623
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
43624
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1812d }
43625
  },
43626
/* max.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
43627
  {
43628
    { 0, 0, 0, 0 },
43629
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
43630
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1810d }
43631
  },
43632
/* max.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
43633
  {
43634
    { 0, 0, 0, 0 },
43635
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
43636
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1c30d00 }
43637
  },
43638
/* max.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
43639
  {
43640
    { 0, 0, 0, 0 },
43641
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
43642
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1832d00 }
43643
  },
43644
/* max.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
43645
  {
43646
    { 0, 0, 0, 0 },
43647
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
43648
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1830d00 }
43649
  },
43650
/* max.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
43651
  {
43652
    { 0, 0, 0, 0 },
43653
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
43654
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1c50d00 }
43655
  },
43656
/* max.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
43657
  {
43658
    { 0, 0, 0, 0 },
43659
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
43660
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1852d00 }
43661
  },
43662
/* max.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
43663
  {
43664
    { 0, 0, 0, 0 },
43665
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
43666
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1850d00 }
43667
  },
43668
/* max.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
43669
  {
43670
    { 0, 0, 0, 0 },
43671
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
43672
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1c70d00 }
43673
  },
43674
/* max.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
43675
  {
43676
    { 0, 0, 0, 0 },
43677
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
43678
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1872d00 }
43679
  },
43680
/* max.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
43681
  {
43682
    { 0, 0, 0, 0 },
43683
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
43684
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1870d00 }
43685
  },
43686
/* max.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */
43687
  {
43688
    { 0, 0, 0, 0 },
43689
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
43690
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1c38d00 }
43691
  },
43692
/* max.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */
43693
  {
43694
    { 0, 0, 0, 0 },
43695
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
43696
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x183ad00 }
43697
  },
43698
/* max.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
43699
  {
43700
    { 0, 0, 0, 0 },
43701
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
43702
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1838d00 }
43703
  },
43704
/* max.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */
43705
  {
43706
    { 0, 0, 0, 0 },
43707
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
43708
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1c58d00 }
43709
  },
43710
/* max.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */
43711
  {
43712
    { 0, 0, 0, 0 },
43713
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
43714
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x185ad00 }
43715
  },
43716
/* max.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
43717
  {
43718
    { 0, 0, 0, 0 },
43719
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
43720
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1858d00 }
43721
  },
43722
/* max.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */
43723
  {
43724
    { 0, 0, 0, 0 },
43725
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
43726
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x1c3cd00 }
43727
  },
43728
/* max.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */
43729
  {
43730
    { 0, 0, 0, 0 },
43731
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
43732
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x183ed00 }
43733
  },
43734
/* max.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
43735
  {
43736
    { 0, 0, 0, 0 },
43737
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
43738
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x183cd00 }
43739
  },
43740
/* max.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */
43741
  {
43742
    { 0, 0, 0, 0 },
43743
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
43744
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x1c5cd00 }
43745
  },
43746
/* max.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */
43747
  {
43748
    { 0, 0, 0, 0 },
43749
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
43750
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x185ed00 }
43751
  },
43752
/* max.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
43753
  {
43754
    { 0, 0, 0, 0 },
43755
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
43756
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x185cd00 }
43757
  },
43758
/* max.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */
43759
  {
43760
    { 0, 0, 0, 0 },
43761
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), 0 } },
43762
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x1c7cd00 }
43763
  },
43764
/* max.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */
43765
  {
43766
    { 0, 0, 0, 0 },
43767
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), 0 } },
43768
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x187ed00 }
43769
  },
43770
/* max.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */
43771
  {
43772
    { 0, 0, 0, 0 },
43773
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
43774
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x187cd00 }
43775
  },
43776
/* max.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */
43777
  {
43778
    { 0, 0, 0, 0 },
43779
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U24), 0 } },
43780
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x1c78d00 }
43781
  },
43782
/* max.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */
43783
  {
43784
    { 0, 0, 0, 0 },
43785
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U24), 0 } },
43786
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x187ad00 }
43787
  },
43788
/* max.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */
43789
  {
43790
    { 0, 0, 0, 0 },
43791
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
43792
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x1878d00 }
43793
  },
43794
/* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
43795
  {
43796
    { 0, 0, 0, 0 },
43797
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
43798
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1980d00 }
43799
  },
43800
/* max.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */
43801
  {
43802
    { 0, 0, 0, 0 },
43803
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
43804
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1982d00 }
43805
  },
43806
/* max.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */
43807
  {
43808
    { 0, 0, 0, 0 },
43809
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
43810
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1983d00 }
43811
  },
43812
/* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
43813
  {
43814
    { 0, 0, 0, 0 },
43815
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
43816
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1908d00 }
43817
  },
43818
/* max.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */
43819
  {
43820
    { 0, 0, 0, 0 },
43821
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
43822
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x190ad00 }
43823
  },
43824
/* max.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */
43825
  {
43826
    { 0, 0, 0, 0 },
43827
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
43828
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x190bd00 }
43829
  },
43830
/* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
43831
  {
43832
    { 0, 0, 0, 0 },
43833
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
43834
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1900d00 }
43835
  },
43836
/* max.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
43837
  {
43838
    { 0, 0, 0, 0 },
43839
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
43840
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1902d00 }
43841
  },
43842
/* max.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
43843
  {
43844
    { 0, 0, 0, 0 },
43845
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
43846
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1903d00 }
43847
  },
43848
/* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
43849
  {
43850
    { 0, 0, 0, 0 },
43851
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
43852
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1920d00 }
43853
  },
43854
/* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
43855
  {
43856
    { 0, 0, 0, 0 },
43857
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
43858
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1922d00 }
43859
  },
43860
/* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
43861
  {
43862
    { 0, 0, 0, 0 },
43863
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
43864
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1923d00 }
43865
  },
43866
/* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
43867
  {
43868
    { 0, 0, 0, 0 },
43869
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
43870
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1940d00 }
43871
  },
43872
/* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
43873
  {
43874
    { 0, 0, 0, 0 },
43875
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
43876
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1942d00 }
43877
  },
43878
/* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
43879
  {
43880
    { 0, 0, 0, 0 },
43881
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
43882
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1943d00 }
43883
  },
43884
/* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
43885
  {
43886
    { 0, 0, 0, 0 },
43887
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
43888
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1960d00 }
43889
  },
43890
/* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
43891
  {
43892
    { 0, 0, 0, 0 },
43893
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
43894
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1962d00 }
43895
  },
43896
/* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
43897
  {
43898
    { 0, 0, 0, 0 },
43899
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
43900
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1963d00 }
43901
  },
43902
/* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
43903
  {
43904
    { 0, 0, 0, 0 },
43905
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
43906
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x1928d00 }
43907
  },
43908
/* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
43909
  {
43910
    { 0, 0, 0, 0 },
43911
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
43912
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x192ad00 }
43913
  },
43914
/* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
43915
  {
43916
    { 0, 0, 0, 0 },
43917
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
43918
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x192bd00 }
43919
  },
43920
/* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
43921
  {
43922
    { 0, 0, 0, 0 },
43923
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
43924
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x1948d00 }
43925
  },
43926
/* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
43927
  {
43928
    { 0, 0, 0, 0 },
43929
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
43930
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x194ad00 }
43931
  },
43932
/* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
43933
  {
43934
    { 0, 0, 0, 0 },
43935
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
43936
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x194bd00 }
43937
  },
43938
/* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
43939
  {
43940
    { 0, 0, 0, 0 },
43941
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
43942
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192cd00 }
43943
  },
43944
/* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
43945
  {
43946
    { 0, 0, 0, 0 },
43947
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
43948
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192ed00 }
43949
  },
43950
/* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
43951
  {
43952
    { 0, 0, 0, 0 },
43953
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
43954
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192fd00 }
43955
  },
43956
/* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
43957
  {
43958
    { 0, 0, 0, 0 },
43959
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
43960
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194cd00 }
43961
  },
43962
/* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
43963
  {
43964
    { 0, 0, 0, 0 },
43965
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
43966
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194ed00 }
43967
  },
43968
/* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
43969
  {
43970
    { 0, 0, 0, 0 },
43971
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
43972
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194fd00 }
43973
  },
43974
/* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
43975
  {
43976
    { 0, 0, 0, 0 },
43977
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
43978
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196cd00 }
43979
  },
43980
/* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
43981
  {
43982
    { 0, 0, 0, 0 },
43983
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
43984
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196ed00 }
43985
  },
43986
/* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
43987
  {
43988
    { 0, 0, 0, 0 },
43989
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
43990
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196fd00 }
43991
  },
43992
/* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
43993
  {
43994
    { 0, 0, 0, 0 },
43995
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
43996
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x1968d00 }
43997
  },
43998
/* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
43999
  {
44000
    { 0, 0, 0, 0 },
44001
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
44002
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x196ad00 }
44003
  },
44004
/* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
44005
  {
44006
    { 0, 0, 0, 0 },
44007
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
44008
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x196bd00 }
44009
  },
44010
/* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
44011
  {
44012
    { 0, 0, 0, 0 },
44013
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
44014
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a80d00 }
44015
  },
44016
/* max.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */
44017
  {
44018
    { 0, 0, 0, 0 },
44019
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
44020
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a82d00 }
44021
  },
44022
/* max.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */
44023
  {
44024
    { 0, 0, 0, 0 },
44025
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
44026
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a83d00 }
44027
  },
44028
/* max.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */
44029
  {
44030
    { 0, 0, 0, 0 },
44031
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32RNPREFIXEDQI), 0 } },
44032
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b83d00 }
44033
  },
44034
/* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
44035
  {
44036
    { 0, 0, 0, 0 },
44037
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
44038
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a08d00 }
44039
  },
44040
/* max.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */
44041
  {
44042
    { 0, 0, 0, 0 },
44043
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
44044
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a0ad00 }
44045
  },
44046
/* max.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */
44047
  {
44048
    { 0, 0, 0, 0 },
44049
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
44050
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a0bd00 }
44051
  },
44052
/* max.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */
44053
  {
44054
    { 0, 0, 0, 0 },
44055
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32ANPREFIXEDQI), 0 } },
44056
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b0bd00 }
44057
  },
44058
/* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
44059
  {
44060
    { 0, 0, 0, 0 },
44061
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
44062
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a00d00 }
44063
  },
44064
/* max.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
44065
  {
44066
    { 0, 0, 0, 0 },
44067
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
44068
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a02d00 }
44069
  },
44070
/* max.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
44071
  {
44072
    { 0, 0, 0, 0 },
44073
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
44074
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a03d00 }
44075
  },
44076
/* max.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
44077
  {
44078
    { 0, 0, 0, 0 },
44079
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
44080
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b03d00 }
44081
  },
44082
/* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
44083
  {
44084
    { 0, 0, 0, 0 },
44085
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
44086
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a20d00 }
44087
  },
44088
/* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
44089
  {
44090
    { 0, 0, 0, 0 },
44091
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
44092
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a22d00 }
44093
  },
44094
/* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
44095
  {
44096
    { 0, 0, 0, 0 },
44097
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
44098
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a23d00 }
44099
  },
44100
/* max.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
44101
  {
44102
    { 0, 0, 0, 0 },
44103
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
44104
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1b23d00 }
44105
  },
44106
/* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
44107
  {
44108
    { 0, 0, 0, 0 },
44109
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
44110
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a40d00 }
44111
  },
44112
/* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
44113
  {
44114
    { 0, 0, 0, 0 },
44115
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
44116
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a42d00 }
44117
  },
44118
/* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
44119
  {
44120
    { 0, 0, 0, 0 },
44121
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
44122
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a43d00 }
44123
  },
44124
/* max.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
44125
  {
44126
    { 0, 0, 0, 0 },
44127
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
44128
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1b43d00 }
44129
  },
44130
/* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
44131
  {
44132
    { 0, 0, 0, 0 },
44133
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
44134
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a60d00 }
44135
  },
44136
/* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
44137
  {
44138
    { 0, 0, 0, 0 },
44139
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
44140
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a62d00 }
44141
  },
44142
/* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
44143
  {
44144
    { 0, 0, 0, 0 },
44145
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
44146
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a63d00 }
44147
  },
44148
/* max.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
44149
  {
44150
    { 0, 0, 0, 0 },
44151
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
44152
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1b63d00 }
44153
  },
44154
/* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
44155
  {
44156
    { 0, 0, 0, 0 },
44157
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
44158
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a28d00 }
44159
  },
44160
/* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
44161
  {
44162
    { 0, 0, 0, 0 },
44163
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
44164
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a2ad00 }
44165
  },
44166
/* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
44167
  {
44168
    { 0, 0, 0, 0 },
44169
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
44170
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a2bd00 }
44171
  },
44172
/* max.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
44173
  {
44174
    { 0, 0, 0, 0 },
44175
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
44176
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1b2bd00 }
44177
  },
44178
/* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
44179
  {
44180
    { 0, 0, 0, 0 },
44181
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
44182
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a48d00 }
44183
  },
44184
/* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
44185
  {
44186
    { 0, 0, 0, 0 },
44187
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
44188
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a4ad00 }
44189
  },
44190
/* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
44191
  {
44192
    { 0, 0, 0, 0 },
44193
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
44194
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a4bd00 }
44195
  },
44196
/* max.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
44197
  {
44198
    { 0, 0, 0, 0 },
44199
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
44200
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1b4bd00 }
44201
  },
44202
/* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
44203
  {
44204
    { 0, 0, 0, 0 },
44205
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
44206
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2cd00 }
44207
  },
44208
/* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
44209
  {
44210
    { 0, 0, 0, 0 },
44211
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
44212
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2ed00 }
44213
  },
44214
/* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
44215
  {
44216
    { 0, 0, 0, 0 },
44217
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
44218
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2fd00 }
44219
  },
44220
/* max.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
44221
  {
44222
    { 0, 0, 0, 0 },
44223
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
44224
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1b2fd00 }
44225
  },
44226
/* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
44227
  {
44228
    { 0, 0, 0, 0 },
44229
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
44230
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4cd00 }
44231
  },
44232
/* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
44233
  {
44234
    { 0, 0, 0, 0 },
44235
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
44236
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4ed00 }
44237
  },
44238
/* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
44239
  {
44240
    { 0, 0, 0, 0 },
44241
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
44242
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4fd00 }
44243
  },
44244
/* max.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
44245
  {
44246
    { 0, 0, 0, 0 },
44247
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
44248
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1b4fd00 }
44249
  },
44250
/* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
44251
  {
44252
    { 0, 0, 0, 0 },
44253
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
44254
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6cd00 }
44255
  },
44256
/* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
44257
  {
44258
    { 0, 0, 0, 0 },
44259
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), 0 } },
44260
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6ed00 }
44261
  },
44262
/* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
44263
  {
44264
    { 0, 0, 0, 0 },
44265
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), 0 } },
44266
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6fd00 }
44267
  },
44268
/* max.b${X} ${Dsp-24-u16},${Dsp-40-u16} */
44269
  {
44270
    { 0, 0, 0, 0 },
44271
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), 0 } },
44272
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1b6fd00 }
44273
  },
44274
/* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
44275
  {
44276
    { 0, 0, 0, 0 },
44277
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
44278
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a68d00 }
44279
  },
44280
/* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
44281
  {
44282
    { 0, 0, 0, 0 },
44283
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), 0 } },
44284
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a6ad00 }
44285
  },
44286
/* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
44287
  {
44288
    { 0, 0, 0, 0 },
44289
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), 0 } },
44290
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a6bd00 }
44291
  },
44292
/* max.b${X} ${Dsp-24-u16},${Dsp-40-u24} */
44293
  {
44294
    { 0, 0, 0, 0 },
44295
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), 0 } },
44296
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1b6bd00 }
44297
  },
44298
/* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
44299
  {
44300
    { 0, 0, 0, 0 },
44301
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
44302
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b80d00 }
44303
  },
44304
/* max.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */
44305
  {
44306
    { 0, 0, 0, 0 },
44307
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32RNPREFIXEDQI), 0 } },
44308
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b82d00 }
44309
  },
44310
/* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
44311
  {
44312
    { 0, 0, 0, 0 },
44313
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
44314
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b08d00 }
44315
  },
44316
/* max.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */
44317
  {
44318
    { 0, 0, 0, 0 },
44319
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32ANPREFIXEDQI), 0 } },
44320
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b0ad00 }
44321
  },
44322
/* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
44323
  {
44324
    { 0, 0, 0, 0 },
44325
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
44326
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b00d00 }
44327
  },
44328
/* max.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
44329
  {
44330
    { 0, 0, 0, 0 },
44331
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
44332
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b02d00 }
44333
  },
44334
/* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
44335
  {
44336
    { 0, 0, 0, 0 },
44337
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
44338
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_An_relative_Prefixed_QI, { 0x1b20d00 }
44339
  },
44340
/* max.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
44341
  {
44342
    { 0, 0, 0, 0 },
44343
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
44344
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_An_relative_Prefixed_QI, { 0x1b22d00 }
44345
  },
44346
/* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
44347
  {
44348
    { 0, 0, 0, 0 },
44349
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
44350
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_An_relative_Prefixed_QI, { 0x1b40d00 }
44351
  },
44352
/* max.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
44353
  {
44354
    { 0, 0, 0, 0 },
44355
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
44356
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_An_relative_Prefixed_QI, { 0x1b42d00 }
44357
  },
44358
/* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
44359
  {
44360
    { 0, 0, 0, 0 },
44361
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
44362
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_An_relative_Prefixed_QI, { 0x1b60d00 }
44363
  },
44364
/* max.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
44365
  {
44366
    { 0, 0, 0, 0 },
44367
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
44368
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_An_relative_Prefixed_QI, { 0x1b62d00 }
44369
  },
44370
/* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
44371
  {
44372
    { 0, 0, 0, 0 },
44373
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
44374
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_QI, { 0x1b28d00 }
44375
  },
44376
/* max.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
44377
  {
44378
    { 0, 0, 0, 0 },
44379
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
44380
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_QI, { 0x1b2ad00 }
44381
  },
44382
/* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
44383
  {
44384
    { 0, 0, 0, 0 },
44385
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
44386
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_QI, { 0x1b48d00 }
44387
  },
44388
/* max.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
44389
  {
44390
    { 0, 0, 0, 0 },
44391
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
44392
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_QI, { 0x1b4ad00 }
44393
  },
44394
/* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
44395
  {
44396
    { 0, 0, 0, 0 },
44397
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
44398
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_QI, { 0x1b2cd00 }
44399
  },
44400
/* max.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
44401
  {
44402
    { 0, 0, 0, 0 },
44403
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
44404
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_QI, { 0x1b2ed00 }
44405
  },
44406
/* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
44407
  {
44408
    { 0, 0, 0, 0 },
44409
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
44410
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_QI, { 0x1b4cd00 }
44411
  },
44412
/* max.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
44413
  {
44414
    { 0, 0, 0, 0 },
44415
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
44416
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_QI, { 0x1b4ed00 }
44417
  },
44418
/* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
44419
  {
44420
    { 0, 0, 0, 0 },
44421
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), 0 } },
44422
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_absolute_Prefixed_QI, { 0x1b6cd00 }
44423
  },
44424
/* max.b${X} ${Dsp-24-u24},${Dsp-48-u16} */
44425
  {
44426
    { 0, 0, 0, 0 },
44427
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), 0 } },
44428
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_absolute_Prefixed_QI, { 0x1b6ed00 }
44429
  },
44430
/* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
44431
  {
44432
    { 0, 0, 0, 0 },
44433
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), 0 } },
44434
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_absolute_Prefixed_QI, { 0x1b68d00 }
44435
  },
44436
/* max.b${X} ${Dsp-24-u24},${Dsp-48-u24} */
44437
  {
44438
    { 0, 0, 0, 0 },
44439
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), 0 } },
44440
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_absolute_Prefixed_QI, { 0x1b6ad00 }
44441
  },
44442
/* max.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */
44443
  {
44444
    { 0, 0, 0, 0 },
44445
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32RNPREFIXEDQI), 0 } },
44446
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1c80d }
44447
  },
44448
/* max.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */
44449
  {
44450
    { 0, 0, 0, 0 },
44451
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DST32RNPREFIXEDQI), 0 } },
44452
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1882d }
44453
  },
44454
/* max.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */
44455
  {
44456
    { 0, 0, 0, 0 },
44457
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
44458
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1880d }
44459
  },
44460
/* max.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */
44461
  {
44462
    { 0, 0, 0, 0 },
44463
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32ANPREFIXEDQI), 0 } },
44464
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1c08d }
44465
  },
44466
/* max.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */
44467
  {
44468
    { 0, 0, 0, 0 },
44469
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DST32ANPREFIXEDQI), 0 } },
44470
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x180ad }
44471
  },
44472
/* max.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */
44473
  {
44474
    { 0, 0, 0, 0 },
44475
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
44476
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1808d }
44477
  },
44478
/* max.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
44479
  {
44480
    { 0, 0, 0, 0 },
44481
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
44482
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1c00d }
44483
  },
44484
/* max.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */
44485
  {
44486
    { 0, 0, 0, 0 },
44487
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
44488
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1802d }
44489
  },
44490
/* max.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
44491
  {
44492
    { 0, 0, 0, 0 },
44493
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
44494
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1800d }
44495
  },
44496
/* max.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
44497
  {
44498
    { 0, 0, 0, 0 },
44499
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
44500
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1c20d00 }
44501
  },
44502
/* max.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
44503
  {
44504
    { 0, 0, 0, 0 },
44505
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
44506
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1822d00 }
44507
  },
44508
/* max.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
44509
  {
44510
    { 0, 0, 0, 0 },
44511
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
44512
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1820d00 }
44513
  },
44514
/* max.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
44515
  {
44516
    { 0, 0, 0, 0 },
44517
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
44518
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1c40d00 }
44519
  },
44520
/* max.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
44521
  {
44522
    { 0, 0, 0, 0 },
44523
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
44524
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1842d00 }
44525
  },
44526
/* max.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
44527
  {
44528
    { 0, 0, 0, 0 },
44529
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
44530
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1840d00 }
44531
  },
44532
/* max.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
44533
  {
44534
    { 0, 0, 0, 0 },
44535
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
44536
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1c60d00 }
44537
  },
44538
/* max.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
44539
  {
44540
    { 0, 0, 0, 0 },
44541
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
44542
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1862d00 }
44543
  },
44544
/* max.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
44545
  {
44546
    { 0, 0, 0, 0 },
44547
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
44548
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1860d00 }
44549
  },
44550
/* max.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
44551
  {
44552
    { 0, 0, 0, 0 },
44553
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
44554
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x1c28d00 }
44555
  },
44556
/* max.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */
44557
  {
44558
    { 0, 0, 0, 0 },
44559
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
44560
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x182ad00 }
44561
  },
44562
/* max.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
44563
  {
44564
    { 0, 0, 0, 0 },
44565
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
44566
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x1828d00 }
44567
  },
44568
/* max.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
44569
  {
44570
    { 0, 0, 0, 0 },
44571
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
44572
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x1c48d00 }
44573
  },
44574
/* max.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */
44575
  {
44576
    { 0, 0, 0, 0 },
44577
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
44578
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x184ad00 }
44579
  },
44580
/* max.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
44581
  {
44582
    { 0, 0, 0, 0 },
44583
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
44584
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x1848d00 }
44585
  },
44586
/* max.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
44587
  {
44588
    { 0, 0, 0, 0 },
44589
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
44590
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x1c2cd00 }
44591
  },
44592
/* max.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */
44593
  {
44594
    { 0, 0, 0, 0 },
44595
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
44596
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x182ed00 }
44597
  },
44598
/* max.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
44599
  {
44600
    { 0, 0, 0, 0 },
44601
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
44602
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x182cd00 }
44603
  },
44604
/* max.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
44605
  {
44606
    { 0, 0, 0, 0 },
44607
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
44608
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x1c4cd00 }
44609
  },
44610
/* max.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */
44611
  {
44612
    { 0, 0, 0, 0 },
44613
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
44614
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x184ed00 }
44615
  },
44616
/* max.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
44617
  {
44618
    { 0, 0, 0, 0 },
44619
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
44620
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x184cd00 }
44621
  },
44622
/* max.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */
44623
  {
44624
    { 0, 0, 0, 0 },
44625
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), 0 } },
44626
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x1c6cd00 }
44627
  },
44628
/* max.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */
44629
  {
44630
    { 0, 0, 0, 0 },
44631
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), 0 } },
44632
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x186ed00 }
44633
  },
44634
/* max.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */
44635
  {
44636
    { 0, 0, 0, 0 },
44637
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
44638
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x186cd00 }
44639
  },
44640
/* max.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */
44641
  {
44642
    { 0, 0, 0, 0 },
44643
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), 0 } },
44644
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x1c68d00 }
44645
  },
44646
/* max.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */
44647
  {
44648
    { 0, 0, 0, 0 },
44649
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U24), 0 } },
44650
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x186ad00 }
44651
  },
44652
/* max.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */
44653
  {
44654
    { 0, 0, 0, 0 },
44655
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
44656
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x1868d00 }
44657
  },
44658
/* max.w${X} #${Imm-24-HI},$Dst32RnPrefixedHI */
44659
  {
44660
    { 0, 0, 0, 0 },
44661
    { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DST32RNPREFIXEDHI), 0 } },
44662
    & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_Rn_direct_Prefixed_HI, { 0x1893f00 }
44663
  },
44664
/* max.w${X} #${Imm-24-HI},$Dst32AnPrefixedHI */
44665
  {
44666
    { 0, 0, 0, 0 },
44667
    { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DST32ANPREFIXEDHI), 0 } },
44668
    & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_An_direct_Prefixed_HI, { 0x181bf00 }
44669
  },
44670
/* max.w${X} #${Imm-24-HI},[$Dst32AnPrefixed] */
44671
  {
44672
    { 0, 0, 0, 0 },
44673
    { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
44674
    & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_An_indirect_Prefixed_HI, { 0x1813f00 }
44675
  },
44676
/* max.w${X} #${Imm-32-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */
44677
  {
44678
    { 0, 0, 0, 0 },
44679
    { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
44680
    & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_An_relative_Prefixed_HI, { 0x1833f00 }
44681
  },
44682
/* max.w${X} #${Imm-32-HI},${Dsp-24-u8}[sb] */
44683
  {
44684
    { 0, 0, 0, 0 },
44685
    { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
44686
    & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_SB_relative_Prefixed_HI, { 0x183bf00 }
44687
  },
44688
/* max.w${X} #${Imm-32-HI},${Dsp-24-s8}[fb] */
44689
  {
44690
    { 0, 0, 0, 0 },
44691
    { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
44692
    & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_FB_relative_Prefixed_HI, { 0x183ff00 }
44693
  },
44694
/* max.w${X} #${Imm-40-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */
44695
  {
44696
    { 0, 0, 0, 0 },
44697
    { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
44698
    & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_An_relative_Prefixed_HI, { 0x1853f00 }
44699
  },
44700
/* max.w${X} #${Imm-40-HI},${Dsp-24-u16}[sb] */
44701
  {
44702
    { 0, 0, 0, 0 },
44703
    { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
44704
    & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_SB_relative_Prefixed_HI, { 0x185bf00 }
44705
  },
44706
/* max.w${X} #${Imm-40-HI},${Dsp-24-s16}[fb] */
44707
  {
44708
    { 0, 0, 0, 0 },
44709
    { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
44710
    & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_FB_relative_Prefixed_HI, { 0x185ff00 }
44711
  },
44712
/* max.w${X} #${Imm-40-HI},${Dsp-24-u16} */
44713
  {
44714
    { 0, 0, 0, 0 },
44715
    { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), 0 } },
44716
    & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_absolute_Prefixed_HI, { 0x187ff00 }
44717
  },
44718
/* max.w${X} #${Imm-48-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */
44719
  {
44720
    { 0, 0, 0, 0 },
44721
    { { MNEM, OP (X), ' ', '#', OP (IMM_48_HI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
44722
    & ifmt_sbb32_w_imm_G_24_24_Prefixed_dst32_24_24_An_relative_Prefixed_HI, { 0x1873f00 }
44723
  },
44724
/* max.w${X} #${Imm-48-HI},${Dsp-24-u24} */
44725
  {
44726
    { 0, 0, 0, 0 },
44727
    { { MNEM, OP (X), ' ', '#', OP (IMM_48_HI), ',', OP (DSP_24_U24), 0 } },
44728
    & ifmt_sbb32_w_imm_G_24_24_Prefixed_dst32_24_24_absolute_Prefixed_HI, { 0x187bf00 }
44729
  },
44730
/* max.b${X} #${Imm-24-QI},$Dst32RnPrefixedQI */
44731
  {
44732
    { 0, 0, 0, 0 },
44733
    { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DST32RNPREFIXEDQI), 0 } },
44734
    & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_Rn_direct_Prefixed_QI, { 0x1883f00 }
44735
  },
44736
/* max.b${X} #${Imm-24-QI},$Dst32AnPrefixedQI */
44737
  {
44738
    { 0, 0, 0, 0 },
44739
    { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DST32ANPREFIXEDQI), 0 } },
44740
    & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_An_direct_Prefixed_QI, { 0x180bf00 }
44741
  },
44742
/* max.b${X} #${Imm-24-QI},[$Dst32AnPrefixed] */
44743
  {
44744
    { 0, 0, 0, 0 },
44745
    { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
44746
    & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_An_indirect_Prefixed_QI, { 0x1803f00 }
44747
  },
44748
/* max.b${X} #${Imm-32-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */
44749
  {
44750
    { 0, 0, 0, 0 },
44751
    { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
44752
    & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_An_relative_Prefixed_QI, { 0x1823f00 }
44753
  },
44754
/* max.b${X} #${Imm-32-QI},${Dsp-24-u8}[sb] */
44755
  {
44756
    { 0, 0, 0, 0 },
44757
    { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
44758
    & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_SB_relative_Prefixed_QI, { 0x182bf00 }
44759
  },
44760
/* max.b${X} #${Imm-32-QI},${Dsp-24-s8}[fb] */
44761
  {
44762
    { 0, 0, 0, 0 },
44763
    { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
44764
    & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_FB_relative_Prefixed_QI, { 0x182ff00 }
44765
  },
44766
/* max.b${X} #${Imm-40-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */
44767
  {
44768
    { 0, 0, 0, 0 },
44769
    { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
44770
    & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_An_relative_Prefixed_QI, { 0x1843f00 }
44771
  },
44772
/* max.b${X} #${Imm-40-QI},${Dsp-24-u16}[sb] */
44773
  {
44774
    { 0, 0, 0, 0 },
44775
    { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
44776
    & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_SB_relative_Prefixed_QI, { 0x184bf00 }
44777
  },
44778
/* max.b${X} #${Imm-40-QI},${Dsp-24-s16}[fb] */
44779
  {
44780
    { 0, 0, 0, 0 },
44781
    { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
44782
    & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_FB_relative_Prefixed_QI, { 0x184ff00 }
44783
  },
44784
/* max.b${X} #${Imm-40-QI},${Dsp-24-u16} */
44785
  {
44786
    { 0, 0, 0, 0 },
44787
    { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), 0 } },
44788
    & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_absolute_Prefixed_QI, { 0x186ff00 }
44789
  },
44790
/* max.b${X} #${Imm-48-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */
44791
  {
44792
    { 0, 0, 0, 0 },
44793
    { { MNEM, OP (X), ' ', '#', OP (IMM_48_QI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
44794
    & ifmt_sbb32_b_imm_G_24_24_Prefixed_dst32_24_24_An_relative_Prefixed_QI, { 0x1863f00 }
44795
  },
44796
/* max.b${X} #${Imm-48-QI},${Dsp-24-u24} */
44797
  {
44798
    { 0, 0, 0, 0 },
44799
    { { MNEM, OP (X), ' ', '#', OP (IMM_48_QI), ',', OP (DSP_24_U24), 0 } },
44800
    & ifmt_sbb32_b_imm_G_24_24_Prefixed_dst32_24_24_absolute_Prefixed_QI, { 0x186bf00 }
44801
  },
44802
/* ste.w ${Dsp-16-u16}[$Dst16An],[a1a0] */
44803
  {
44804
    { 0, 0, 0, 0 },
44805
    { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', '[', 'a', '1', 'a', '0', ']', 0 } },
44806
    & ifmt_rorc16_w_16_dst16_16_16_An_relative_HI, { 0x752c0000 }
44807
  },
44808
/* ste.w ${Dsp-16-u16}[sb],[a1a0] */
44809
  {
44810
    { 0, 0, 0, 0 },
44811
    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', 'a', '1', 'a', '0', ']', 0 } },
44812
    & ifmt_rorc16_w_16_dst16_16_16_SB_relative_HI, { 0x752e0000 }
44813
  },
44814
/* ste.w ${Dsp-16-u16},[a1a0] */
44815
  {
44816
    { 0, 0, 0, 0 },
44817
    { { MNEM, ' ', OP (DSP_16_U16), ',', '[', 'a', '1', 'a', '0', ']', 0 } },
44818
    & ifmt_rorc16_w_16_dst16_16_16_absolute_HI, { 0x752f0000 }
44819
  },
44820
/* ste.w ${Dsp-16-u16}[$Dst16An],${Dsp-32-u20}[a0] */
44821
  {
44822
    { 0, 0, 0, 0 },
44823
    { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', OP (DSP_32_U20), '[', 'a', '0', ']', 0 } },
44824
    & ifmt_ste_w_16_16_u20a0_dst16_16_16_An_relative_HI, { 0x751c0000 }
44825
  },
44826
/* ste.w ${Dsp-16-u16}[sb],${Dsp-32-u20}[a0] */
44827
  {
44828
    { 0, 0, 0, 0 },
44829
    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U20), '[', 'a', '0', ']', 0 } },
44830
    & ifmt_ste_w_16_16_u20a0_dst16_16_16_SB_relative_HI, { 0x751e0000 }
44831
  },
44832
/* ste.w ${Dsp-16-u16},${Dsp-32-u20}[a0] */
44833
  {
44834
    { 0, 0, 0, 0 },
44835
    { { MNEM, ' ', OP (DSP_16_U16), ',', OP (DSP_32_U20), '[', 'a', '0', ']', 0 } },
44836
    & ifmt_ste_w_16_16_u20a0_dst16_16_16_absolute_HI, { 0x751f0000 }
44837
  },
44838
/* ste.w ${Dsp-16-u16}[$Dst16An],${Dsp-32-u20} */
44839
  {
44840
    { 0, 0, 0, 0 },
44841
    { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', OP (DSP_32_U20), 0 } },
44842
    & ifmt_ste_w_16_16_u20a0_dst16_16_16_An_relative_HI, { 0x750c0000 }
44843
  },
44844
/* ste.w ${Dsp-16-u16}[sb],${Dsp-32-u20} */
44845
  {
44846
    { 0, 0, 0, 0 },
44847
    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U20), 0 } },
44848
    & ifmt_ste_w_16_16_u20a0_dst16_16_16_SB_relative_HI, { 0x750e0000 }
44849
  },
44850
/* ste.w ${Dsp-16-u16},${Dsp-32-u20} */
44851
  {
44852
    { 0, 0, 0, 0 },
44853
    { { MNEM, ' ', OP (DSP_16_U16), ',', OP (DSP_32_U20), 0 } },
44854
    & ifmt_ste_w_16_16_u20a0_dst16_16_16_absolute_HI, { 0x750f0000 }
44855
  },
44856
/* ste.w ${Dsp-16-u8}[$Dst16An],[a1a0] */
44857
  {
44858
    { 0, 0, 0, 0 },
44859
    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', '[', 'a', '1', 'a', '0', ']', 0 } },
44860
    & ifmt_rorc16_w_16_dst16_16_8_An_relative_HI, { 0x752800 }
44861
  },
44862
/* ste.w ${Dsp-16-u8}[sb],[a1a0] */
44863
  {
44864
    { 0, 0, 0, 0 },
44865
    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', 'a', '1', 'a', '0', ']', 0 } },
44866
    & ifmt_rorc16_w_16_dst16_16_8_SB_relative_HI, { 0x752a00 }
44867
  },
44868
/* ste.w ${Dsp-16-s8}[fb],[a1a0] */
44869
  {
44870
    { 0, 0, 0, 0 },
44871
    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', 'a', '1', 'a', '0', ']', 0 } },
44872
    & ifmt_rorc16_w_16_dst16_16_8_FB_relative_HI, { 0x752b00 }
44873
  },
44874
/* ste.w ${Dsp-16-u8}[$Dst16An],${Dsp-24-u20}[a0] */
44875
  {
44876
    { 0, 0, 0, 0 },
44877
    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', OP (DSP_24_U20), '[', 'a', '0', ']', 0 } },
44878
    & ifmt_ste_w_16_8_u20a0_dst16_16_8_An_relative_HI, { 0x75180000 }
44879
  },
44880
/* ste.w ${Dsp-16-u8}[sb],${Dsp-24-u20}[a0] */
44881
  {
44882
    { 0, 0, 0, 0 },
44883
    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U20), '[', 'a', '0', ']', 0 } },
44884
    & ifmt_ste_w_16_8_u20a0_dst16_16_8_SB_relative_HI, { 0x751a0000 }
44885
  },
44886
/* ste.w ${Dsp-16-s8}[fb],${Dsp-24-u20}[a0] */
44887
  {
44888
    { 0, 0, 0, 0 },
44889
    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U20), '[', 'a', '0', ']', 0 } },
44890
    & ifmt_ste_w_16_8_u20a0_dst16_16_8_FB_relative_HI, { 0x751b0000 }
44891
  },
44892
/* ste.w ${Dsp-16-u8}[$Dst16An],${Dsp-24-u20} */
44893
  {
44894
    { 0, 0, 0, 0 },
44895
    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', OP (DSP_24_U20), 0 } },
44896
    & ifmt_ste_w_16_8_u20a0_dst16_16_8_An_relative_HI, { 0x75080000 }
44897
  },
44898
/* ste.w ${Dsp-16-u8}[sb],${Dsp-24-u20} */
44899
  {
44900
    { 0, 0, 0, 0 },
44901
    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U20), 0 } },
44902
    & ifmt_ste_w_16_8_u20a0_dst16_16_8_SB_relative_HI, { 0x750a0000 }
44903
  },
44904
/* ste.w ${Dsp-16-s8}[fb],${Dsp-24-u20} */
44905
  {
44906
    { 0, 0, 0, 0 },
44907
    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U20), 0 } },
44908
    & ifmt_ste_w_16_8_u20a0_dst16_16_8_FB_relative_HI, { 0x750b0000 }
44909
  },
44910
/* ste.w $Dst16RnHI,[a1a0] */
44911
  {
44912
    { 0, 0, 0, 0 },
44913
    { { MNEM, ' ', OP (DST16RNHI), ',', '[', 'a', '1', 'a', '0', ']', 0 } },
44914
    & ifmt_rorc16_w_16_dst16_Rn_direct_HI, { 0x7520 }
44915
  },
44916
/* ste.w $Dst16AnHI,[a1a0] */
44917
  {
44918
    { 0, 0, 0, 0 },
44919
    { { MNEM, ' ', OP (DST16ANHI), ',', '[', 'a', '1', 'a', '0', ']', 0 } },
44920
    & ifmt_rorc16_w_16_dst16_An_direct_HI, { 0x7524 }
44921
  },
44922
/* ste.w [$Dst16An],[a1a0] */
44923
  {
44924
    { 0, 0, 0, 0 },
44925
    { { MNEM, ' ', '[', OP (DST16AN), ']', ',', '[', 'a', '1', 'a', '0', ']', 0 } },
44926
    & ifmt_rorc16_w_16_dst16_An_indirect_HI, { 0x7526 }
44927
  },
44928
/* ste.w $Dst16RnHI,${Dsp-16-u20}[a0] */
44929
  {
44930
    { 0, 0, 0, 0 },
44931
    { { MNEM, ' ', OP (DST16RNHI), ',', OP (DSP_16_U20), '[', 'a', '0', ']', 0 } },
44932
    & ifmt_ste_w_basic_u20a0_dst16_Rn_direct_HI, { 0x75100000 }
44933
  },
44934
/* ste.w $Dst16AnHI,${Dsp-16-u20}[a0] */
44935
  {
44936
    { 0, 0, 0, 0 },
44937
    { { MNEM, ' ', OP (DST16ANHI), ',', OP (DSP_16_U20), '[', 'a', '0', ']', 0 } },
44938
    & ifmt_ste_w_basic_u20a0_dst16_An_direct_HI, { 0x75140000 }
44939
  },
44940
/* ste.w [$Dst16An],${Dsp-16-u20}[a0] */
44941
  {
44942
    { 0, 0, 0, 0 },
44943
    { { MNEM, ' ', '[', OP (DST16AN), ']', ',', OP (DSP_16_U20), '[', 'a', '0', ']', 0 } },
44944
    & ifmt_ste_w_basic_u20a0_dst16_An_indirect_HI, { 0x75160000 }
44945
  },
44946
/* ste.w $Dst16RnHI,${Dsp-16-u20} */
44947
  {
44948
    { 0, 0, 0, 0 },
44949
    { { MNEM, ' ', OP (DST16RNHI), ',', OP (DSP_16_U20), 0 } },
44950
    & ifmt_ste_w_basic_u20a0_dst16_Rn_direct_HI, { 0x75000000 }
44951
  },
44952
/* ste.w $Dst16AnHI,${Dsp-16-u20} */
44953
  {
44954
    { 0, 0, 0, 0 },
44955
    { { MNEM, ' ', OP (DST16ANHI), ',', OP (DSP_16_U20), 0 } },
44956
    & ifmt_ste_w_basic_u20a0_dst16_An_direct_HI, { 0x75040000 }
44957
  },
44958
/* ste.w [$Dst16An],${Dsp-16-u20} */
44959
  {
44960
    { 0, 0, 0, 0 },
44961
    { { MNEM, ' ', '[', OP (DST16AN), ']', ',', OP (DSP_16_U20), 0 } },
44962
    & ifmt_ste_w_basic_u20a0_dst16_An_indirect_HI, { 0x75060000 }
44963
  },
44964
/* ste.b ${Dsp-16-u16}[$Dst16An],[a1a0] */
44965
  {
44966
    { 0, 0, 0, 0 },
44967
    { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', '[', 'a', '1', 'a', '0', ']', 0 } },
44968
    & ifmt_rorc16_b_16_dst16_16_16_An_relative_QI, { 0x742c0000 }
44969
  },
44970
/* ste.b ${Dsp-16-u16}[sb],[a1a0] */
44971
  {
44972
    { 0, 0, 0, 0 },
44973
    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', 'a', '1', 'a', '0', ']', 0 } },
44974
    & ifmt_rorc16_b_16_dst16_16_16_SB_relative_QI, { 0x742e0000 }
44975
  },
44976
/* ste.b ${Dsp-16-u16},[a1a0] */
44977
  {
44978
    { 0, 0, 0, 0 },
44979
    { { MNEM, ' ', OP (DSP_16_U16), ',', '[', 'a', '1', 'a', '0', ']', 0 } },
44980
    & ifmt_rorc16_b_16_dst16_16_16_absolute_QI, { 0x742f0000 }
44981
  },
44982
/* ste.b ${Dsp-16-u16}[$Dst16An],${Dsp-32-u20}[a0] */
44983
  {
44984
    { 0, 0, 0, 0 },
44985
    { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', OP (DSP_32_U20), '[', 'a', '0', ']', 0 } },
44986
    & ifmt_ste_b_16_16_u20a0_dst16_16_16_An_relative_QI, { 0x741c0000 }
44987
  },
44988
/* ste.b ${Dsp-16-u16}[sb],${Dsp-32-u20}[a0] */
44989
  {
44990
    { 0, 0, 0, 0 },
44991
    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U20), '[', 'a', '0', ']', 0 } },
44992
    & ifmt_ste_b_16_16_u20a0_dst16_16_16_SB_relative_QI, { 0x741e0000 }
44993
  },
44994
/* ste.b ${Dsp-16-u16},${Dsp-32-u20}[a0] */
44995
  {
44996
    { 0, 0, 0, 0 },
44997
    { { MNEM, ' ', OP (DSP_16_U16), ',', OP (DSP_32_U20), '[', 'a', '0', ']', 0 } },
44998
    & ifmt_ste_b_16_16_u20a0_dst16_16_16_absolute_QI, { 0x741f0000 }
44999
  },
45000
/* ste.b ${Dsp-16-u16}[$Dst16An],${Dsp-32-u20} */
45001
  {
45002
    { 0, 0, 0, 0 },
45003
    { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', OP (DSP_32_U20), 0 } },
45004
    & ifmt_ste_b_16_16_u20a0_dst16_16_16_An_relative_QI, { 0x740c0000 }
45005
  },
45006
/* ste.b ${Dsp-16-u16}[sb],${Dsp-32-u20} */
45007
  {
45008
    { 0, 0, 0, 0 },
45009
    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U20), 0 } },
45010
    & ifmt_ste_b_16_16_u20a0_dst16_16_16_SB_relative_QI, { 0x740e0000 }
45011
  },
45012
/* ste.b ${Dsp-16-u16},${Dsp-32-u20} */
45013
  {
45014
    { 0, 0, 0, 0 },
45015
    { { MNEM, ' ', OP (DSP_16_U16), ',', OP (DSP_32_U20), 0 } },
45016
    & ifmt_ste_b_16_16_u20a0_dst16_16_16_absolute_QI, { 0x740f0000 }
45017
  },
45018
/* ste.b ${Dsp-16-u8}[$Dst16An],[a1a0] */
45019
  {
45020
    { 0, 0, 0, 0 },
45021
    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', '[', 'a', '1', 'a', '0', ']', 0 } },
45022
    & ifmt_rorc16_b_16_dst16_16_8_An_relative_QI, { 0x742800 }
45023
  },
45024
/* ste.b ${Dsp-16-u8}[sb],[a1a0] */
45025
  {
45026
    { 0, 0, 0, 0 },
45027
    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', 'a', '1', 'a', '0', ']', 0 } },
45028
    & ifmt_rorc16_b_16_dst16_16_8_SB_relative_QI, { 0x742a00 }
45029
  },
45030
/* ste.b ${Dsp-16-s8}[fb],[a1a0] */
45031
  {
45032
    { 0, 0, 0, 0 },
45033
    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', 'a', '1', 'a', '0', ']', 0 } },
45034
    & ifmt_rorc16_b_16_dst16_16_8_FB_relative_QI, { 0x742b00 }
45035
  },
45036
/* ste.b ${Dsp-16-u8}[$Dst16An],${Dsp-24-u20}[a0] */
45037
  {
45038
    { 0, 0, 0, 0 },
45039
    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', OP (DSP_24_U20), '[', 'a', '0', ']', 0 } },
45040
    & ifmt_ste_b_16_8_u20a0_dst16_16_8_An_relative_QI, { 0x74180000 }
45041
  },
45042
/* ste.b ${Dsp-16-u8}[sb],${Dsp-24-u20}[a0] */
45043
  {
45044
    { 0, 0, 0, 0 },
45045
    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U20), '[', 'a', '0', ']', 0 } },
45046
    & ifmt_ste_b_16_8_u20a0_dst16_16_8_SB_relative_QI, { 0x741a0000 }
45047
  },
45048
/* ste.b ${Dsp-16-s8}[fb],${Dsp-24-u20}[a0] */
45049
  {
45050
    { 0, 0, 0, 0 },
45051
    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U20), '[', 'a', '0', ']', 0 } },
45052
    & ifmt_ste_b_16_8_u20a0_dst16_16_8_FB_relative_QI, { 0x741b0000 }
45053
  },
45054
/* ste.b ${Dsp-16-u8}[$Dst16An],${Dsp-24-u20} */
45055
  {
45056
    { 0, 0, 0, 0 },
45057
    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', OP (DSP_24_U20), 0 } },
45058
    & ifmt_ste_b_16_8_u20a0_dst16_16_8_An_relative_QI, { 0x74080000 }
45059
  },
45060
/* ste.b ${Dsp-16-u8}[sb],${Dsp-24-u20} */
45061
  {
45062
    { 0, 0, 0, 0 },
45063
    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U20), 0 } },
45064
    & ifmt_ste_b_16_8_u20a0_dst16_16_8_SB_relative_QI, { 0x740a0000 }
45065
  },
45066
/* ste.b ${Dsp-16-s8}[fb],${Dsp-24-u20} */
45067
  {
45068
    { 0, 0, 0, 0 },
45069
    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U20), 0 } },
45070
    & ifmt_ste_b_16_8_u20a0_dst16_16_8_FB_relative_QI, { 0x740b0000 }
45071
  },
45072
/* ste.b $Dst16RnQI,[a1a0] */
45073
  {
45074
    { 0, 0, 0, 0 },
45075
    { { MNEM, ' ', OP (DST16RNQI), ',', '[', 'a', '1', 'a', '0', ']', 0 } },
45076
    & ifmt_rorc16_b_16_dst16_Rn_direct_QI, { 0x7420 }
45077
  },
45078
/* ste.b $Dst16AnQI,[a1a0] */
45079
  {
45080
    { 0, 0, 0, 0 },
45081
    { { MNEM, ' ', OP (DST16ANQI), ',', '[', 'a', '1', 'a', '0', ']', 0 } },
45082
    & ifmt_rorc16_b_16_dst16_An_direct_QI, { 0x7424 }
45083
  },
45084
/* ste.b [$Dst16An],[a1a0] */
45085
  {
45086
    { 0, 0, 0, 0 },
45087
    { { MNEM, ' ', '[', OP (DST16AN), ']', ',', '[', 'a', '1', 'a', '0', ']', 0 } },
45088
    & ifmt_rorc16_b_16_dst16_An_indirect_QI, { 0x7426 }
45089
  },
45090
/* ste.b $Dst16RnQI,${Dsp-16-u20}[a0] */
45091
  {
45092
    { 0, 0, 0, 0 },
45093
    { { MNEM, ' ', OP (DST16RNQI), ',', OP (DSP_16_U20), '[', 'a', '0', ']', 0 } },
45094
    & ifmt_ste_b_basic_u20a0_dst16_Rn_direct_QI, { 0x74100000 }
45095
  },
45096
/* ste.b $Dst16AnQI,${Dsp-16-u20}[a0] */
45097
  {
45098
    { 0, 0, 0, 0 },
45099
    { { MNEM, ' ', OP (DST16ANQI), ',', OP (DSP_16_U20), '[', 'a', '0', ']', 0 } },
45100
    & ifmt_ste_b_basic_u20a0_dst16_An_direct_QI, { 0x74140000 }
45101
  },
45102
/* ste.b [$Dst16An],${Dsp-16-u20}[a0] */
45103
  {
45104
    { 0, 0, 0, 0 },
45105
    { { MNEM, ' ', '[', OP (DST16AN), ']', ',', OP (DSP_16_U20), '[', 'a', '0', ']', 0 } },
45106
    & ifmt_ste_b_basic_u20a0_dst16_An_indirect_QI, { 0x74160000 }
45107
  },
45108
/* ste.b $Dst16RnQI,${Dsp-16-u20} */
45109
  {
45110
    { 0, 0, 0, 0 },
45111
    { { MNEM, ' ', OP (DST16RNQI), ',', OP (DSP_16_U20), 0 } },
45112
    & ifmt_ste_b_basic_u20a0_dst16_Rn_direct_QI, { 0x74000000 }
45113
  },
45114
/* ste.b $Dst16AnQI,${Dsp-16-u20} */
45115
  {
45116
    { 0, 0, 0, 0 },
45117
    { { MNEM, ' ', OP (DST16ANQI), ',', OP (DSP_16_U20), 0 } },
45118
    & ifmt_ste_b_basic_u20a0_dst16_An_direct_QI, { 0x74040000 }
45119
  },
45120
/* ste.b [$Dst16An],${Dsp-16-u20} */
45121
  {
45122
    { 0, 0, 0, 0 },
45123
    { { MNEM, ' ', '[', OP (DST16AN), ']', ',', OP (DSP_16_U20), 0 } },
45124
    & ifmt_ste_b_basic_u20a0_dst16_An_indirect_QI, { 0x74060000 }
45125
  },
45126
/* lde.w [a1a0],${Dsp-16-u16}[$Dst16An] */
45127
  {
45128
    { 0, 0, 0, 0 },
45129
    { { MNEM, ' ', '[', 'a', '1', 'a', '0', ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
45130
    & ifmt_rorc16_w_16_dst16_16_16_An_relative_HI, { 0x75ac0000 }
45131
  },
45132
/* lde.w [a1a0],${Dsp-16-u16}[sb] */
45133
  {
45134
    { 0, 0, 0, 0 },
45135
    { { MNEM, ' ', '[', 'a', '1', 'a', '0', ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
45136
    & ifmt_rorc16_w_16_dst16_16_16_SB_relative_HI, { 0x75ae0000 }
45137
  },
45138
/* lde.w [a1a0],${Dsp-16-u16} */
45139
  {
45140
    { 0, 0, 0, 0 },
45141
    { { MNEM, ' ', '[', 'a', '1', 'a', '0', ']', ',', OP (DSP_16_U16), 0 } },
45142
    & ifmt_rorc16_w_16_dst16_16_16_absolute_HI, { 0x75af0000 }
45143
  },
45144
/* lde.w ${Dsp-32-u20}[a0],${Dsp-16-u16}[$Dst16An] */
45145
  {
45146
    { 0, 0, 0, 0 },
45147
    { { MNEM, ' ', OP (DSP_32_U20), '[', 'a', '0', ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
45148
    & ifmt_ste_w_16_16_u20a0_dst16_16_16_An_relative_HI, { 0x759c0000 }
45149
  },
45150
/* lde.w ${Dsp-32-u20}[a0],${Dsp-16-u16}[sb] */
45151
  {
45152
    { 0, 0, 0, 0 },
45153
    { { MNEM, ' ', OP (DSP_32_U20), '[', 'a', '0', ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
45154
    & ifmt_ste_w_16_16_u20a0_dst16_16_16_SB_relative_HI, { 0x759e0000 }
45155
  },
45156
/* lde.w ${Dsp-32-u20}[a0],${Dsp-16-u16} */
45157
  {
45158
    { 0, 0, 0, 0 },
45159
    { { MNEM, ' ', OP (DSP_32_U20), '[', 'a', '0', ']', ',', OP (DSP_16_U16), 0 } },
45160
    & ifmt_ste_w_16_16_u20a0_dst16_16_16_absolute_HI, { 0x759f0000 }
45161
  },
45162
/* lde.w ${Dsp-32-u20},${Dsp-16-u16}[$Dst16An] */
45163
  {
45164
    { 0, 0, 0, 0 },
45165
    { { MNEM, ' ', OP (DSP_32_U20), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
45166
    & ifmt_ste_w_16_16_u20a0_dst16_16_16_An_relative_HI, { 0x758c0000 }
45167
  },
45168
/* lde.w ${Dsp-32-u20},${Dsp-16-u16}[sb] */
45169
  {
45170
    { 0, 0, 0, 0 },
45171
    { { MNEM, ' ', OP (DSP_32_U20), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
45172
    & ifmt_ste_w_16_16_u20a0_dst16_16_16_SB_relative_HI, { 0x758e0000 }
45173
  },
45174
/* lde.w ${Dsp-32-u20},${Dsp-16-u16} */
45175
  {
45176
    { 0, 0, 0, 0 },
45177
    { { MNEM, ' ', OP (DSP_32_U20), ',', OP (DSP_16_U16), 0 } },
45178
    & ifmt_ste_w_16_16_u20a0_dst16_16_16_absolute_HI, { 0x758f0000 }
45179
  },
45180
/* lde.w [a1a0],${Dsp-16-u8}[$Dst16An] */
45181
  {
45182
    { 0, 0, 0, 0 },
45183
    { { MNEM, ' ', '[', 'a', '1', 'a', '0', ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
45184
    & ifmt_rorc16_w_16_dst16_16_8_An_relative_HI, { 0x75a800 }
45185
  },
45186
/* lde.w [a1a0],${Dsp-16-u8}[sb] */
45187
  {
45188
    { 0, 0, 0, 0 },
45189
    { { MNEM, ' ', '[', 'a', '1', 'a', '0', ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
45190
    & ifmt_rorc16_w_16_dst16_16_8_SB_relative_HI, { 0x75aa00 }
45191
  },
45192
/* lde.w [a1a0],${Dsp-16-s8}[fb] */
45193
  {
45194
    { 0, 0, 0, 0 },
45195
    { { MNEM, ' ', '[', 'a', '1', 'a', '0', ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
45196
    & ifmt_rorc16_w_16_dst16_16_8_FB_relative_HI, { 0x75ab00 }
45197
  },
45198
/* lde.w ${Dsp-24-u20}[a0],${Dsp-16-u8}[$Dst16An] */
45199
  {
45200
    { 0, 0, 0, 0 },
45201
    { { MNEM, ' ', OP (DSP_24_U20), '[', 'a', '0', ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
45202
    & ifmt_ste_w_16_8_u20a0_dst16_16_8_An_relative_HI, { 0x75980000 }
45203
  },
45204
/* lde.w ${Dsp-24-u20}[a0],${Dsp-16-u8}[sb] */
45205
  {
45206
    { 0, 0, 0, 0 },
45207
    { { MNEM, ' ', OP (DSP_24_U20), '[', 'a', '0', ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
45208
    & ifmt_ste_w_16_8_u20a0_dst16_16_8_SB_relative_HI, { 0x759a0000 }
45209
  },
45210
/* lde.w ${Dsp-24-u20}[a0],${Dsp-16-s8}[fb] */
45211
  {
45212
    { 0, 0, 0, 0 },
45213
    { { MNEM, ' ', OP (DSP_24_U20), '[', 'a', '0', ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
45214
    & ifmt_ste_w_16_8_u20a0_dst16_16_8_FB_relative_HI, { 0x759b0000 }
45215
  },
45216
/* lde.w ${Dsp-24-u20},${Dsp-16-u8}[$Dst16An] */
45217
  {
45218
    { 0, 0, 0, 0 },
45219
    { { MNEM, ' ', OP (DSP_24_U20), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
45220
    & ifmt_ste_w_16_8_u20a0_dst16_16_8_An_relative_HI, { 0x75880000 }
45221
  },
45222
/* lde.w ${Dsp-24-u20},${Dsp-16-u8}[sb] */
45223
  {
45224
    { 0, 0, 0, 0 },
45225
    { { MNEM, ' ', OP (DSP_24_U20), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
45226
    & ifmt_ste_w_16_8_u20a0_dst16_16_8_SB_relative_HI, { 0x758a0000 }
45227
  },
45228
/* lde.w ${Dsp-24-u20},${Dsp-16-s8}[fb] */
45229
  {
45230
    { 0, 0, 0, 0 },
45231
    { { MNEM, ' ', OP (DSP_24_U20), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
45232
    & ifmt_ste_w_16_8_u20a0_dst16_16_8_FB_relative_HI, { 0x758b0000 }
45233
  },
45234
/* lde.w [a1a0],$Dst16RnHI */
45235
  {
45236
    { 0, 0, 0, 0 },
45237
    { { MNEM, ' ', '[', 'a', '1', 'a', '0', ']', ',', OP (DST16RNHI), 0 } },
45238
    & ifmt_rorc16_w_16_dst16_Rn_direct_HI, { 0x75a0 }
45239
  },
45240
/* lde.w [a1a0],$Dst16AnHI */
45241
  {
45242
    { 0, 0, 0, 0 },
45243
    { { MNEM, ' ', '[', 'a', '1', 'a', '0', ']', ',', OP (DST16ANHI), 0 } },
45244
    & ifmt_rorc16_w_16_dst16_An_direct_HI, { 0x75a4 }
45245
  },
45246
/* lde.w [a1a0],[$Dst16An] */
45247
  {
45248
    { 0, 0, 0, 0 },
45249
    { { MNEM, ' ', '[', 'a', '1', 'a', '0', ']', ',', '[', OP (DST16AN), ']', 0 } },
45250
    & ifmt_rorc16_w_16_dst16_An_indirect_HI, { 0x75a6 }
45251
  },
45252
/* lde.w ${Dsp-16-u20}[a0],$Dst16RnHI */
45253
  {
45254
    { 0, 0, 0, 0 },
45255
    { { MNEM, ' ', OP (DSP_16_U20), '[', 'a', '0', ']', ',', OP (DST16RNHI), 0 } },
45256
    & ifmt_ste_w_basic_u20a0_dst16_Rn_direct_HI, { 0x75900000 }
45257
  },
45258
/* lde.w ${Dsp-16-u20}[a0],$Dst16AnHI */
45259
  {
45260
    { 0, 0, 0, 0 },
45261
    { { MNEM, ' ', OP (DSP_16_U20), '[', 'a', '0', ']', ',', OP (DST16ANHI), 0 } },
45262
    & ifmt_ste_w_basic_u20a0_dst16_An_direct_HI, { 0x75940000 }
45263
  },
45264
/* lde.w ${Dsp-16-u20}[a0],[$Dst16An] */
45265
  {
45266
    { 0, 0, 0, 0 },
45267
    { { MNEM, ' ', OP (DSP_16_U20), '[', 'a', '0', ']', ',', '[', OP (DST16AN), ']', 0 } },
45268
    & ifmt_ste_w_basic_u20a0_dst16_An_indirect_HI, { 0x75960000 }
45269
  },
45270
/* lde.w ${Dsp-16-u20},$Dst16RnHI */
45271
  {
45272
    { 0, 0, 0, 0 },
45273
    { { MNEM, ' ', OP (DSP_16_U20), ',', OP (DST16RNHI), 0 } },
45274
    & ifmt_ste_w_basic_u20a0_dst16_Rn_direct_HI, { 0x75800000 }
45275
  },
45276
/* lde.w ${Dsp-16-u20},$Dst16AnHI */
45277
  {
45278
    { 0, 0, 0, 0 },
45279
    { { MNEM, ' ', OP (DSP_16_U20), ',', OP (DST16ANHI), 0 } },
45280
    & ifmt_ste_w_basic_u20a0_dst16_An_direct_HI, { 0x75840000 }
45281
  },
45282
/* lde.w ${Dsp-16-u20},[$Dst16An] */
45283
  {
45284
    { 0, 0, 0, 0 },
45285
    { { MNEM, ' ', OP (DSP_16_U20), ',', '[', OP (DST16AN), ']', 0 } },
45286
    & ifmt_ste_w_basic_u20a0_dst16_An_indirect_HI, { 0x75860000 }
45287
  },
45288
/* lde.b [a1a0],${Dsp-16-u16}[$Dst16An] */
45289
  {
45290
    { 0, 0, 0, 0 },
45291
    { { MNEM, ' ', '[', 'a', '1', 'a', '0', ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
45292
    & ifmt_rorc16_b_16_dst16_16_16_An_relative_QI, { 0x74ac0000 }
45293
  },
45294
/* lde.b [a1a0],${Dsp-16-u16}[sb] */
45295
  {
45296
    { 0, 0, 0, 0 },
45297
    { { MNEM, ' ', '[', 'a', '1', 'a', '0', ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
45298
    & ifmt_rorc16_b_16_dst16_16_16_SB_relative_QI, { 0x74ae0000 }
45299
  },
45300
/* lde.b [a1a0],${Dsp-16-u16} */
45301
  {
45302
    { 0, 0, 0, 0 },
45303
    { { MNEM, ' ', '[', 'a', '1', 'a', '0', ']', ',', OP (DSP_16_U16), 0 } },
45304
    & ifmt_rorc16_b_16_dst16_16_16_absolute_QI, { 0x74af0000 }
45305
  },
45306
/* lde.b ${Dsp-32-u20}[a0],${Dsp-16-u16}[$Dst16An] */
45307
  {
45308
    { 0, 0, 0, 0 },
45309
    { { MNEM, ' ', OP (DSP_32_U20), '[', 'a', '0', ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
45310
    & ifmt_ste_b_16_16_u20a0_dst16_16_16_An_relative_QI, { 0x749c0000 }
45311
  },
45312
/* lde.b ${Dsp-32-u20}[a0],${Dsp-16-u16}[sb] */
45313
  {
45314
    { 0, 0, 0, 0 },
45315
    { { MNEM, ' ', OP (DSP_32_U20), '[', 'a', '0', ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
45316
    & ifmt_ste_b_16_16_u20a0_dst16_16_16_SB_relative_QI, { 0x749e0000 }
45317
  },
45318
/* lde.b ${Dsp-32-u20}[a0],${Dsp-16-u16} */
45319
  {
45320
    { 0, 0, 0, 0 },
45321
    { { MNEM, ' ', OP (DSP_32_U20), '[', 'a', '0', ']', ',', OP (DSP_16_U16), 0 } },
45322
    & ifmt_ste_b_16_16_u20a0_dst16_16_16_absolute_QI, { 0x749f0000 }
45323
  },
45324
/* lde.b ${Dsp-32-u20},${Dsp-16-u16}[$Dst16An] */
45325
  {
45326
    { 0, 0, 0, 0 },
45327
    { { MNEM, ' ', OP (DSP_32_U20), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
45328
    & ifmt_ste_b_16_16_u20a0_dst16_16_16_An_relative_QI, { 0x748c0000 }
45329
  },
45330
/* lde.b ${Dsp-32-u20},${Dsp-16-u16}[sb] */
45331
  {
45332
    { 0, 0, 0, 0 },
45333
    { { MNEM, ' ', OP (DSP_32_U20), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
45334
    & ifmt_ste_b_16_16_u20a0_dst16_16_16_SB_relative_QI, { 0x748e0000 }
45335
  },
45336
/* lde.b ${Dsp-32-u20},${Dsp-16-u16} */
45337
  {
45338
    { 0, 0, 0, 0 },
45339
    { { MNEM, ' ', OP (DSP_32_U20), ',', OP (DSP_16_U16), 0 } },
45340
    & ifmt_ste_b_16_16_u20a0_dst16_16_16_absolute_QI, { 0x748f0000 }
45341
  },
45342
/* lde.b [a1a0],${Dsp-16-u8}[$Dst16An] */
45343
  {
45344
    { 0, 0, 0, 0 },
45345
    { { MNEM, ' ', '[', 'a', '1', 'a', '0', ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
45346
    & ifmt_rorc16_b_16_dst16_16_8_An_relative_QI, { 0x74a800 }
45347
  },
45348
/* lde.b [a1a0],${Dsp-16-u8}[sb] */
45349
  {
45350
    { 0, 0, 0, 0 },
45351
    { { MNEM, ' ', '[', 'a', '1', 'a', '0', ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
45352
    & ifmt_rorc16_b_16_dst16_16_8_SB_relative_QI, { 0x74aa00 }
45353
  },
45354
/* lde.b [a1a0],${Dsp-16-s8}[fb] */
45355
  {
45356
    { 0, 0, 0, 0 },
45357
    { { MNEM, ' ', '[', 'a', '1', 'a', '0', ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
45358
    & ifmt_rorc16_b_16_dst16_16_8_FB_relative_QI, { 0x74ab00 }
45359
  },
45360
/* lde.b ${Dsp-24-u20}[a0],${Dsp-16-u8}[$Dst16An] */
45361
  {
45362
    { 0, 0, 0, 0 },
45363
    { { MNEM, ' ', OP (DSP_24_U20), '[', 'a', '0', ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
45364
    & ifmt_ste_b_16_8_u20a0_dst16_16_8_An_relative_QI, { 0x74980000 }
45365
  },
45366
/* lde.b ${Dsp-24-u20}[a0],${Dsp-16-u8}[sb] */
45367
  {
45368
    { 0, 0, 0, 0 },
45369
    { { MNEM, ' ', OP (DSP_24_U20), '[', 'a', '0', ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
45370
    & ifmt_ste_b_16_8_u20a0_dst16_16_8_SB_relative_QI, { 0x749a0000 }
45371
  },
45372
/* lde.b ${Dsp-24-u20}[a0],${Dsp-16-s8}[fb] */
45373
  {
45374
    { 0, 0, 0, 0 },
45375
    { { MNEM, ' ', OP (DSP_24_U20), '[', 'a', '0', ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
45376
    & ifmt_ste_b_16_8_u20a0_dst16_16_8_FB_relative_QI, { 0x749b0000 }
45377
  },
45378
/* lde.b ${Dsp-24-u20},${Dsp-16-u8}[$Dst16An] */
45379
  {
45380
    { 0, 0, 0, 0 },
45381
    { { MNEM, ' ', OP (DSP_24_U20), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
45382
    & ifmt_ste_b_16_8_u20a0_dst16_16_8_An_relative_QI, { 0x74880000 }
45383
  },
45384
/* lde.b ${Dsp-24-u20},${Dsp-16-u8}[sb] */
45385
  {
45386
    { 0, 0, 0, 0 },
45387
    { { MNEM, ' ', OP (DSP_24_U20), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
45388
    & ifmt_ste_b_16_8_u20a0_dst16_16_8_SB_relative_QI, { 0x748a0000 }
45389
  },
45390
/* lde.b ${Dsp-24-u20},${Dsp-16-s8}[fb] */
45391
  {
45392
    { 0, 0, 0, 0 },
45393
    { { MNEM, ' ', OP (DSP_24_U20), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
45394
    & ifmt_ste_b_16_8_u20a0_dst16_16_8_FB_relative_QI, { 0x748b0000 }
45395
  },
45396
/* lde.b [a1a0],$Dst16RnQI */
45397
  {
45398
    { 0, 0, 0, 0 },
45399
    { { MNEM, ' ', '[', 'a', '1', 'a', '0', ']', ',', OP (DST16RNQI), 0 } },
45400
    & ifmt_rorc16_b_16_dst16_Rn_direct_QI, { 0x74a0 }
45401
  },
45402
/* lde.b [a1a0],$Dst16AnQI */
45403
  {
45404
    { 0, 0, 0, 0 },
45405
    { { MNEM, ' ', '[', 'a', '1', 'a', '0', ']', ',', OP (DST16ANQI), 0 } },
45406
    & ifmt_rorc16_b_16_dst16_An_direct_QI, { 0x74a4 }
45407
  },
45408
/* lde.b [a1a0],[$Dst16An] */
45409
  {
45410
    { 0, 0, 0, 0 },
45411
    { { MNEM, ' ', '[', 'a', '1', 'a', '0', ']', ',', '[', OP (DST16AN), ']', 0 } },
45412
    & ifmt_rorc16_b_16_dst16_An_indirect_QI, { 0x74a6 }
45413
  },
45414
/* lde.b ${Dsp-16-u20}[a0],$Dst16RnQI */
45415
  {
45416
    { 0, 0, 0, 0 },
45417
    { { MNEM, ' ', OP (DSP_16_U20), '[', 'a', '0', ']', ',', OP (DST16RNQI), 0 } },
45418
    & ifmt_ste_b_basic_u20a0_dst16_Rn_direct_QI, { 0x74900000 }
45419
  },
45420
/* lde.b ${Dsp-16-u20}[a0],$Dst16AnQI */
45421
  {
45422
    { 0, 0, 0, 0 },
45423
    { { MNEM, ' ', OP (DSP_16_U20), '[', 'a', '0', ']', ',', OP (DST16ANQI), 0 } },
45424
    & ifmt_ste_b_basic_u20a0_dst16_An_direct_QI, { 0x74940000 }
45425
  },
45426
/* lde.b ${Dsp-16-u20}[a0],[$Dst16An] */
45427
  {
45428
    { 0, 0, 0, 0 },
45429
    { { MNEM, ' ', OP (DSP_16_U20), '[', 'a', '0', ']', ',', '[', OP (DST16AN), ']', 0 } },
45430
    & ifmt_ste_b_basic_u20a0_dst16_An_indirect_QI, { 0x74960000 }
45431
  },
45432
/* lde.b ${Dsp-16-u20},$Dst16RnQI */
45433
  {
45434
    { 0, 0, 0, 0 },
45435
    { { MNEM, ' ', OP (DSP_16_U20), ',', OP (DST16RNQI), 0 } },
45436
    & ifmt_ste_b_basic_u20a0_dst16_Rn_direct_QI, { 0x74800000 }
45437
  },
45438
/* lde.b ${Dsp-16-u20},$Dst16AnQI */
45439
  {
45440
    { 0, 0, 0, 0 },
45441
    { { MNEM, ' ', OP (DSP_16_U20), ',', OP (DST16ANQI), 0 } },
45442
    & ifmt_ste_b_basic_u20a0_dst16_An_direct_QI, { 0x74840000 }
45443
  },
45444
/* lde.b ${Dsp-16-u20},[$Dst16An] */
45445
  {
45446
    { 0, 0, 0, 0 },
45447
    { { MNEM, ' ', OP (DSP_16_U20), ',', '[', OP (DST16AN), ']', 0 } },
45448
    & ifmt_ste_b_basic_u20a0_dst16_An_indirect_QI, { 0x74860000 }
45449
  },
45450
/* stc ${cr3-Prefixed-32},$Dst32RnPrefixedSI */
45451
  {
45452
    { 0, 0, 0, 0 },
45453
    { { MNEM, ' ', OP (CR3_PREFIXED_32), ',', OP (DST32RNPREFIXEDSI), 0 } },
45454
    & ifmt_stc32_src_cr3_dst32_Rn_direct_Prefixed_SI, { 0x1d910 }
45455
  },
45456
/* stc ${cr3-Prefixed-32},$Dst32AnPrefixedSI */
45457
  {
45458
    { 0, 0, 0, 0 },
45459
    { { MNEM, ' ', OP (CR3_PREFIXED_32), ',', OP (DST32ANPREFIXEDSI), 0 } },
45460
    & ifmt_stc32_src_cr3_dst32_An_direct_Prefixed_SI, { 0x1d190 }
45461
  },
45462
/* stc ${cr3-Prefixed-32},[$Dst32AnPrefixed] */
45463
  {
45464
    { 0, 0, 0, 0 },
45465
    { { MNEM, ' ', OP (CR3_PREFIXED_32), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
45466
    & ifmt_stc32_src_cr3_dst32_An_indirect_Prefixed_SI, { 0x1d110 }
45467
  },
45468
/* stc ${cr3-Prefixed-32},${Dsp-24-u8}[$Dst32AnPrefixed] */
45469
  {
45470
    { 0, 0, 0, 0 },
45471
    { { MNEM, ' ', OP (CR3_PREFIXED_32), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
45472
    & ifmt_stc32_src_cr3_dst32_24_8_An_relative_Prefixed_SI, { 0x1d31000 }
45473
  },
45474
/* stc ${cr3-Prefixed-32},${Dsp-24-u16}[$Dst32AnPrefixed] */
45475
  {
45476
    { 0, 0, 0, 0 },
45477
    { { MNEM, ' ', OP (CR3_PREFIXED_32), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
45478
    & ifmt_stc32_src_cr3_dst32_24_16_An_relative_Prefixed_SI, { 0x1d51000 }
45479
  },
45480
/* stc ${cr3-Prefixed-32},${Dsp-24-u24}[$Dst32AnPrefixed] */
45481
  {
45482
    { 0, 0, 0, 0 },
45483
    { { MNEM, ' ', OP (CR3_PREFIXED_32), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
45484
    & ifmt_stc32_src_cr3_dst32_24_24_An_relative_Prefixed_SI, { 0x1d71000 }
45485
  },
45486
/* stc ${cr3-Prefixed-32},${Dsp-24-u8}[sb] */
45487
  {
45488
    { 0, 0, 0, 0 },
45489
    { { MNEM, ' ', OP (CR3_PREFIXED_32), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
45490
    & ifmt_stc32_src_cr3_dst32_24_8_SB_relative_Prefixed_SI, { 0x1d39000 }
45491
  },
45492
/* stc ${cr3-Prefixed-32},${Dsp-24-u16}[sb] */
45493
  {
45494
    { 0, 0, 0, 0 },
45495
    { { MNEM, ' ', OP (CR3_PREFIXED_32), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
45496
    & ifmt_stc32_src_cr3_dst32_24_16_SB_relative_Prefixed_SI, { 0x1d59000 }
45497
  },
45498
/* stc ${cr3-Prefixed-32},${Dsp-24-s8}[fb] */
45499
  {
45500
    { 0, 0, 0, 0 },
45501
    { { MNEM, ' ', OP (CR3_PREFIXED_32), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
45502
    & ifmt_stc32_src_cr3_dst32_24_8_FB_relative_Prefixed_SI, { 0x1d3d000 }
45503
  },
45504
/* stc ${cr3-Prefixed-32},${Dsp-24-s16}[fb] */
45505
  {
45506
    { 0, 0, 0, 0 },
45507
    { { MNEM, ' ', OP (CR3_PREFIXED_32), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
45508
    & ifmt_stc32_src_cr3_dst32_24_16_FB_relative_Prefixed_SI, { 0x1d5d000 }
45509
  },
45510
/* stc ${cr3-Prefixed-32},${Dsp-24-u16} */
45511
  {
45512
    { 0, 0, 0, 0 },
45513
    { { MNEM, ' ', OP (CR3_PREFIXED_32), ',', OP (DSP_24_U16), 0 } },
45514
    & ifmt_stc32_src_cr3_dst32_24_16_absolute_Prefixed_SI, { 0x1d7d000 }
45515
  },
45516
/* stc ${cr3-Prefixed-32},${Dsp-24-u24} */
45517
  {
45518
    { 0, 0, 0, 0 },
45519
    { { MNEM, ' ', OP (CR3_PREFIXED_32), ',', OP (DSP_24_U24), 0 } },
45520
    & ifmt_stc32_src_cr3_dst32_24_24_absolute_Prefixed_SI, { 0x1d79000 }
45521
  },
45522
/* stc ${cr2-32},$Dst32RnUnprefixedSI */
45523
  {
45524
    { 0, 0, 0, 0 },
45525
    { { MNEM, ' ', OP (CR2_32), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
45526
    & ifmt_stc32_src_cr2_dst32_Rn_direct_Unprefixed_SI, { 0xd910 }
45527
  },
45528
/* stc ${cr2-32},$Dst32AnUnprefixedSI */
45529
  {
45530
    { 0, 0, 0, 0 },
45531
    { { MNEM, ' ', OP (CR2_32), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
45532
    & ifmt_stc32_src_cr2_dst32_An_direct_Unprefixed_SI, { 0xd190 }
45533
  },
45534
/* stc ${cr2-32},[$Dst32AnUnprefixed] */
45535
  {
45536
    { 0, 0, 0, 0 },
45537
    { { MNEM, ' ', OP (CR2_32), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
45538
    & ifmt_stc32_src_cr2_dst32_An_indirect_Unprefixed_SI, { 0xd110 }
45539
  },
45540
/* stc ${cr2-32},${Dsp-16-u8}[$Dst32AnUnprefixed] */
45541
  {
45542
    { 0, 0, 0, 0 },
45543
    { { MNEM, ' ', OP (CR2_32), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
45544
    & ifmt_stc32_src_cr2_dst32_16_8_An_relative_Unprefixed_SI, { 0xd31000 }
45545
  },
45546
/* stc ${cr2-32},${Dsp-16-u16}[$Dst32AnUnprefixed] */
45547
  {
45548
    { 0, 0, 0, 0 },
45549
    { { MNEM, ' ', OP (CR2_32), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
45550
    & ifmt_stc32_src_cr2_dst32_16_16_An_relative_Unprefixed_SI, { 0xd5100000 }
45551
  },
45552
/* stc ${cr2-32},${Dsp-16-u24}[$Dst32AnUnprefixed] */
45553
  {
45554
    { 0, 0, 0, 0 },
45555
    { { MNEM, ' ', OP (CR2_32), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
45556
    & ifmt_stc32_src_cr2_dst32_16_24_An_relative_Unprefixed_SI, { 0xd7100000 }
45557
  },
45558
/* stc ${cr2-32},${Dsp-16-u8}[sb] */
45559
  {
45560
    { 0, 0, 0, 0 },
45561
    { { MNEM, ' ', OP (CR2_32), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
45562
    & ifmt_stc32_src_cr2_dst32_16_8_SB_relative_Unprefixed_SI, { 0xd39000 }
45563
  },
45564
/* stc ${cr2-32},${Dsp-16-u16}[sb] */
45565
  {
45566
    { 0, 0, 0, 0 },
45567
    { { MNEM, ' ', OP (CR2_32), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
45568
    & ifmt_stc32_src_cr2_dst32_16_16_SB_relative_Unprefixed_SI, { 0xd5900000 }
45569
  },
45570
/* stc ${cr2-32},${Dsp-16-s8}[fb] */
45571
  {
45572
    { 0, 0, 0, 0 },
45573
    { { MNEM, ' ', OP (CR2_32), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
45574
    & ifmt_stc32_src_cr2_dst32_16_8_FB_relative_Unprefixed_SI, { 0xd3d000 }
45575
  },
45576
/* stc ${cr2-32},${Dsp-16-s16}[fb] */
45577
  {
45578
    { 0, 0, 0, 0 },
45579
    { { MNEM, ' ', OP (CR2_32), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
45580
    & ifmt_stc32_src_cr2_dst32_16_16_FB_relative_Unprefixed_SI, { 0xd5d00000 }
45581
  },
45582
/* stc ${cr2-32},${Dsp-16-u16} */
45583
  {
45584
    { 0, 0, 0, 0 },
45585
    { { MNEM, ' ', OP (CR2_32), ',', OP (DSP_16_U16), 0 } },
45586
    & ifmt_stc32_src_cr2_dst32_16_16_absolute_Unprefixed_SI, { 0xd7d00000 }
45587
  },
45588
/* stc ${cr2-32},${Dsp-16-u24} */
45589
  {
45590
    { 0, 0, 0, 0 },
45591
    { { MNEM, ' ', OP (CR2_32), ',', OP (DSP_16_U24), 0 } },
45592
    & ifmt_stc32_src_cr2_dst32_16_24_absolute_Unprefixed_SI, { 0xd7900000 }
45593
  },
45594
/* stc ${cr1-Prefixed-32},$Dst32RnPrefixedHI */
45595
  {
45596
    { 0, 0, 0, 0 },
45597
    { { MNEM, ' ', OP (CR1_PREFIXED_32), ',', OP (DST32RNPREFIXEDHI), 0 } },
45598
    & ifmt_stc32_src_cr1_dst32_Rn_direct_Prefixed_HI, { 0x1d918 }
45599
  },
45600
/* stc ${cr1-Prefixed-32},$Dst32AnPrefixedHI */
45601
  {
45602
    { 0, 0, 0, 0 },
45603
    { { MNEM, ' ', OP (CR1_PREFIXED_32), ',', OP (DST32ANPREFIXEDHI), 0 } },
45604
    & ifmt_stc32_src_cr1_dst32_An_direct_Prefixed_HI, { 0x1d198 }
45605
  },
45606
/* stc ${cr1-Prefixed-32},[$Dst32AnPrefixed] */
45607
  {
45608
    { 0, 0, 0, 0 },
45609
    { { MNEM, ' ', OP (CR1_PREFIXED_32), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
45610
    & ifmt_stc32_src_cr1_dst32_An_indirect_Prefixed_HI, { 0x1d118 }
45611
  },
45612
/* stc ${cr1-Prefixed-32},${Dsp-24-u8}[$Dst32AnPrefixed] */
45613
  {
45614
    { 0, 0, 0, 0 },
45615
    { { MNEM, ' ', OP (CR1_PREFIXED_32), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
45616
    & ifmt_stc32_src_cr1_dst32_24_8_An_relative_Prefixed_HI, { 0x1d31800 }
45617
  },
45618
/* stc ${cr1-Prefixed-32},${Dsp-24-u16}[$Dst32AnPrefixed] */
45619
  {
45620
    { 0, 0, 0, 0 },
45621
    { { MNEM, ' ', OP (CR1_PREFIXED_32), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
45622
    & ifmt_stc32_src_cr1_dst32_24_16_An_relative_Prefixed_HI, { 0x1d51800 }
45623
  },
45624
/* stc ${cr1-Prefixed-32},${Dsp-24-u24}[$Dst32AnPrefixed] */
45625
  {
45626
    { 0, 0, 0, 0 },
45627
    { { MNEM, ' ', OP (CR1_PREFIXED_32), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
45628
    & ifmt_stc32_src_cr1_dst32_24_24_An_relative_Prefixed_HI, { 0x1d71800 }
45629
  },
45630
/* stc ${cr1-Prefixed-32},${Dsp-24-u8}[sb] */
45631
  {
45632
    { 0, 0, 0, 0 },
45633
    { { MNEM, ' ', OP (CR1_PREFIXED_32), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
45634
    & ifmt_stc32_src_cr1_dst32_24_8_SB_relative_Prefixed_HI, { 0x1d39800 }
45635
  },
45636
/* stc ${cr1-Prefixed-32},${Dsp-24-u16}[sb] */
45637
  {
45638
    { 0, 0, 0, 0 },
45639
    { { MNEM, ' ', OP (CR1_PREFIXED_32), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
45640
    & ifmt_stc32_src_cr1_dst32_24_16_SB_relative_Prefixed_HI, { 0x1d59800 }
45641
  },
45642
/* stc ${cr1-Prefixed-32},${Dsp-24-s8}[fb] */
45643
  {
45644
    { 0, 0, 0, 0 },
45645
    { { MNEM, ' ', OP (CR1_PREFIXED_32), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
45646
    & ifmt_stc32_src_cr1_dst32_24_8_FB_relative_Prefixed_HI, { 0x1d3d800 }
45647
  },
45648
/* stc ${cr1-Prefixed-32},${Dsp-24-s16}[fb] */
45649
  {
45650
    { 0, 0, 0, 0 },
45651
    { { MNEM, ' ', OP (CR1_PREFIXED_32), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
45652
    & ifmt_stc32_src_cr1_dst32_24_16_FB_relative_Prefixed_HI, { 0x1d5d800 }
45653
  },
45654
/* stc ${cr1-Prefixed-32},${Dsp-24-u16} */
45655
  {
45656
    { 0, 0, 0, 0 },
45657
    { { MNEM, ' ', OP (CR1_PREFIXED_32), ',', OP (DSP_24_U16), 0 } },
45658
    & ifmt_stc32_src_cr1_dst32_24_16_absolute_Prefixed_HI, { 0x1d7d800 }
45659
  },
45660
/* stc ${cr1-Prefixed-32},${Dsp-24-u24} */
45661
  {
45662
    { 0, 0, 0, 0 },
45663
    { { MNEM, ' ', OP (CR1_PREFIXED_32), ',', OP (DSP_24_U24), 0 } },
45664
    & ifmt_stc32_src_cr1_dst32_24_24_absolute_Prefixed_HI, { 0x1d79800 }
45665
  },
45666
/* stc pc,$Dst16RnHI */
45667
  {
45668
    { 0, 0, 0, 0 },
45669
    { { MNEM, ' ', 'p', 'c', ',', OP (DST16RNHI), 0 } },
45670
    & ifmt_shl16_w_dst_dst16_Rn_direct_HI, { 0x7cc0 }
45671
  },
45672
/* stc pc,$Dst16AnHI */
45673
  {
45674
    { 0, 0, 0, 0 },
45675
    { { MNEM, ' ', 'p', 'c', ',', OP (DST16ANHI), 0 } },
45676
    & ifmt_shl16_w_dst_dst16_An_direct_HI, { 0x7cc4 }
45677
  },
45678
/* stc pc,[$Dst16An] */
45679
  {
45680
    { 0, 0, 0, 0 },
45681
    { { MNEM, ' ', 'p', 'c', ',', '[', OP (DST16AN), ']', 0 } },
45682
    & ifmt_shl16_w_dst_dst16_An_indirect_HI, { 0x7cc6 }
45683
  },
45684
/* stc pc,${Dsp-16-u8}[$Dst16An] */
45685
  {
45686
    { 0, 0, 0, 0 },
45687
    { { MNEM, ' ', 'p', 'c', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
45688
    & ifmt_shl16_w_dst_dst16_16_8_An_relative_HI, { 0x7cc800 }
45689
  },
45690
/* stc pc,${Dsp-16-u16}[$Dst16An] */
45691
  {
45692
    { 0, 0, 0, 0 },
45693
    { { MNEM, ' ', 'p', 'c', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
45694
    & ifmt_shl16_w_dst_dst16_16_16_An_relative_HI, { 0x7ccc0000 }
45695
  },
45696
/* stc pc,${Dsp-16-u8}[sb] */
45697
  {
45698
    { 0, 0, 0, 0 },
45699
    { { MNEM, ' ', 'p', 'c', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
45700
    & ifmt_shl16_w_dst_dst16_16_8_SB_relative_HI, { 0x7cca00 }
45701
  },
45702
/* stc pc,${Dsp-16-u16}[sb] */
45703
  {
45704
    { 0, 0, 0, 0 },
45705
    { { MNEM, ' ', 'p', 'c', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
45706
    & ifmt_shl16_w_dst_dst16_16_16_SB_relative_HI, { 0x7cce0000 }
45707
  },
45708
/* stc pc,${Dsp-16-s8}[fb] */
45709
  {
45710
    { 0, 0, 0, 0 },
45711
    { { MNEM, ' ', 'p', 'c', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
45712
    & ifmt_shl16_w_dst_dst16_16_8_FB_relative_HI, { 0x7ccb00 }
45713
  },
45714
/* stc pc,${Dsp-16-u16} */
45715
  {
45716
    { 0, 0, 0, 0 },
45717
    { { MNEM, ' ', 'p', 'c', ',', OP (DSP_16_U16), 0 } },
45718
    & ifmt_shl16_w_dst_dst16_16_16_absolute_HI, { 0x7ccf0000 }
45719
  },
45720
/* stc ${cr16},$Dst16RnHI */
45721
  {
45722
    { 0, 0, 0, 0 },
45723
    { { MNEM, ' ', OP (CR16), ',', OP (DST16RNHI), 0 } },
45724
    & ifmt_stc16_src_dst16_Rn_direct_HI, { 0x7b80 }
45725
  },
45726
/* stc ${cr16},$Dst16AnHI */
45727
  {
45728
    { 0, 0, 0, 0 },
45729
    { { MNEM, ' ', OP (CR16), ',', OP (DST16ANHI), 0 } },
45730
    & ifmt_stc16_src_dst16_An_direct_HI, { 0x7b84 }
45731
  },
45732
/* stc ${cr16},[$Dst16An] */
45733
  {
45734
    { 0, 0, 0, 0 },
45735
    { { MNEM, ' ', OP (CR16), ',', '[', OP (DST16AN), ']', 0 } },
45736
    & ifmt_stc16_src_dst16_An_indirect_HI, { 0x7b86 }
45737
  },
45738
/* stc ${cr16},${Dsp-16-u8}[$Dst16An] */
45739
  {
45740
    { 0, 0, 0, 0 },
45741
    { { MNEM, ' ', OP (CR16), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
45742
    & ifmt_stc16_src_dst16_16_8_An_relative_HI, { 0x7b8800 }
45743
  },
45744
/* stc ${cr16},${Dsp-16-u16}[$Dst16An] */
45745
  {
45746
    { 0, 0, 0, 0 },
45747
    { { MNEM, ' ', OP (CR16), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
45748
    & ifmt_stc16_src_dst16_16_16_An_relative_HI, { 0x7b8c0000 }
45749
  },
45750
/* stc ${cr16},${Dsp-16-u8}[sb] */
45751
  {
45752
    { 0, 0, 0, 0 },
45753
    { { MNEM, ' ', OP (CR16), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
45754
    & ifmt_stc16_src_dst16_16_8_SB_relative_HI, { 0x7b8a00 }
45755
  },
45756
/* stc ${cr16},${Dsp-16-u16}[sb] */
45757
  {
45758
    { 0, 0, 0, 0 },
45759
    { { MNEM, ' ', OP (CR16), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
45760
    & ifmt_stc16_src_dst16_16_16_SB_relative_HI, { 0x7b8e0000 }
45761
  },
45762
/* stc ${cr16},${Dsp-16-s8}[fb] */
45763
  {
45764
    { 0, 0, 0, 0 },
45765
    { { MNEM, ' ', OP (CR16), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
45766
    & ifmt_stc16_src_dst16_16_8_FB_relative_HI, { 0x7b8b00 }
45767
  },
45768
/* stc ${cr16},${Dsp-16-u16} */
45769
  {
45770
    { 0, 0, 0, 0 },
45771
    { { MNEM, ' ', OP (CR16), ',', OP (DSP_16_U16), 0 } },
45772
    & ifmt_stc16_src_dst16_16_16_absolute_HI, { 0x7b8f0000 }
45773
  },
45774
/* ldc $Dst32RnPrefixedSI,${cr3-Prefixed-32} */
45775
  {
45776
    { 0, 0, 0, 0 },
45777
    { { MNEM, ' ', OP (DST32RNPREFIXEDSI), ',', OP (CR3_PREFIXED_32), 0 } },
45778
    & ifmt_stc32_src_cr3_dst32_Rn_direct_Prefixed_SI, { 0x1d900 }
45779
  },
45780
/* ldc $Dst32AnPrefixedSI,${cr3-Prefixed-32} */
45781
  {
45782
    { 0, 0, 0, 0 },
45783
    { { MNEM, ' ', OP (DST32ANPREFIXEDSI), ',', OP (CR3_PREFIXED_32), 0 } },
45784
    & ifmt_stc32_src_cr3_dst32_An_direct_Prefixed_SI, { 0x1d180 }
45785
  },
45786
/* ldc [$Dst32AnPrefixed],${cr3-Prefixed-32} */
45787
  {
45788
    { 0, 0, 0, 0 },
45789
    { { MNEM, ' ', '[', OP (DST32ANPREFIXED), ']', ',', OP (CR3_PREFIXED_32), 0 } },
45790
    & ifmt_stc32_src_cr3_dst32_An_indirect_Prefixed_SI, { 0x1d100 }
45791
  },
45792
/* ldc ${Dsp-24-u8}[$Dst32AnPrefixed],${cr3-Prefixed-32} */
45793
  {
45794
    { 0, 0, 0, 0 },
45795
    { { MNEM, ' ', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', ',', OP (CR3_PREFIXED_32), 0 } },
45796
    & ifmt_stc32_src_cr3_dst32_24_8_An_relative_Prefixed_SI, { 0x1d30000 }
45797
  },
45798
/* ldc ${Dsp-24-u16}[$Dst32AnPrefixed],${cr3-Prefixed-32} */
45799
  {
45800
    { 0, 0, 0, 0 },
45801
    { { MNEM, ' ', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', ',', OP (CR3_PREFIXED_32), 0 } },
45802
    & ifmt_stc32_src_cr3_dst32_24_16_An_relative_Prefixed_SI, { 0x1d50000 }
45803
  },
45804
/* ldc ${Dsp-24-u24}[$Dst32AnPrefixed],${cr3-Prefixed-32} */
45805
  {
45806
    { 0, 0, 0, 0 },
45807
    { { MNEM, ' ', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', ',', OP (CR3_PREFIXED_32), 0 } },
45808
    & ifmt_stc32_src_cr3_dst32_24_24_An_relative_Prefixed_SI, { 0x1d70000 }
45809
  },
45810
/* ldc ${Dsp-24-u8}[sb],${cr3-Prefixed-32} */
45811
  {
45812
    { 0, 0, 0, 0 },
45813
    { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (CR3_PREFIXED_32), 0 } },
45814
    & ifmt_stc32_src_cr3_dst32_24_8_SB_relative_Prefixed_SI, { 0x1d38000 }
45815
  },
45816
/* ldc ${Dsp-24-u16}[sb],${cr3-Prefixed-32} */
45817
  {
45818
    { 0, 0, 0, 0 },
45819
    { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (CR3_PREFIXED_32), 0 } },
45820
    & ifmt_stc32_src_cr3_dst32_24_16_SB_relative_Prefixed_SI, { 0x1d58000 }
45821
  },
45822
/* ldc ${Dsp-24-s8}[fb],${cr3-Prefixed-32} */
45823
  {
45824
    { 0, 0, 0, 0 },
45825
    { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (CR3_PREFIXED_32), 0 } },
45826
    & ifmt_stc32_src_cr3_dst32_24_8_FB_relative_Prefixed_SI, { 0x1d3c000 }
45827
  },
45828
/* ldc ${Dsp-24-s16}[fb],${cr3-Prefixed-32} */
45829
  {
45830
    { 0, 0, 0, 0 },
45831
    { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (CR3_PREFIXED_32), 0 } },
45832
    & ifmt_stc32_src_cr3_dst32_24_16_FB_relative_Prefixed_SI, { 0x1d5c000 }
45833
  },
45834
/* ldc ${Dsp-24-u16},${cr3-Prefixed-32} */
45835
  {
45836
    { 0, 0, 0, 0 },
45837
    { { MNEM, ' ', OP (DSP_24_U16), ',', OP (CR3_PREFIXED_32), 0 } },
45838
    & ifmt_stc32_src_cr3_dst32_24_16_absolute_Prefixed_SI, { 0x1d7c000 }
45839
  },
45840
/* ldc ${Dsp-24-u24},${cr3-Prefixed-32} */
45841
  {
45842
    { 0, 0, 0, 0 },
45843
    { { MNEM, ' ', OP (DSP_24_U24), ',', OP (CR3_PREFIXED_32), 0 } },
45844
    & ifmt_stc32_src_cr3_dst32_24_24_absolute_Prefixed_SI, { 0x1d78000 }
45845
  },
45846
/* ldc $Dst32RnUnprefixedSI,${cr2-32} */
45847
  {
45848
    { 0, 0, 0, 0 },
45849
    { { MNEM, ' ', OP (DST32RNUNPREFIXEDSI), ',', OP (CR2_32), 0 } },
45850
    & ifmt_stc32_src_cr2_dst32_Rn_direct_Unprefixed_SI, { 0xd900 }
45851
  },
45852
/* ldc $Dst32AnUnprefixedSI,${cr2-32} */
45853
  {
45854
    { 0, 0, 0, 0 },
45855
    { { MNEM, ' ', OP (DST32ANUNPREFIXEDSI), ',', OP (CR2_32), 0 } },
45856
    & ifmt_stc32_src_cr2_dst32_An_direct_Unprefixed_SI, { 0xd180 }
45857
  },
45858
/* ldc [$Dst32AnUnprefixed],${cr2-32} */
45859
  {
45860
    { 0, 0, 0, 0 },
45861
    { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', ',', OP (CR2_32), 0 } },
45862
    & ifmt_stc32_src_cr2_dst32_An_indirect_Unprefixed_SI, { 0xd100 }
45863
  },
45864
/* ldc ${Dsp-16-u8}[$Dst32AnUnprefixed],${cr2-32} */
45865
  {
45866
    { 0, 0, 0, 0 },
45867
    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (CR2_32), 0 } },
45868
    & ifmt_stc32_src_cr2_dst32_16_8_An_relative_Unprefixed_SI, { 0xd30000 }
45869
  },
45870
/* ldc ${Dsp-16-u16}[$Dst32AnUnprefixed],${cr2-32} */
45871
  {
45872
    { 0, 0, 0, 0 },
45873
    { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (CR2_32), 0 } },
45874
    & ifmt_stc32_src_cr2_dst32_16_16_An_relative_Unprefixed_SI, { 0xd5000000 }
45875
  },
45876
/* ldc ${Dsp-16-u24}[$Dst32AnUnprefixed],${cr2-32} */
45877
  {
45878
    { 0, 0, 0, 0 },
45879
    { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (CR2_32), 0 } },
45880
    & ifmt_stc32_src_cr2_dst32_16_24_An_relative_Unprefixed_SI, { 0xd7000000 }
45881
  },
45882
/* ldc ${Dsp-16-u8}[sb],${cr2-32} */
45883
  {
45884
    { 0, 0, 0, 0 },
45885
    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (CR2_32), 0 } },
45886
    & ifmt_stc32_src_cr2_dst32_16_8_SB_relative_Unprefixed_SI, { 0xd38000 }
45887
  },
45888
/* ldc ${Dsp-16-u16}[sb],${cr2-32} */
45889
  {
45890
    { 0, 0, 0, 0 },
45891
    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (CR2_32), 0 } },
45892
    & ifmt_stc32_src_cr2_dst32_16_16_SB_relative_Unprefixed_SI, { 0xd5800000 }
45893
  },
45894
/* ldc ${Dsp-16-s8}[fb],${cr2-32} */
45895
  {
45896
    { 0, 0, 0, 0 },
45897
    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (CR2_32), 0 } },
45898
    & ifmt_stc32_src_cr2_dst32_16_8_FB_relative_Unprefixed_SI, { 0xd3c000 }
45899
  },
45900
/* ldc ${Dsp-16-s16}[fb],${cr2-32} */
45901
  {
45902
    { 0, 0, 0, 0 },
45903
    { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (CR2_32), 0 } },
45904
    & ifmt_stc32_src_cr2_dst32_16_16_FB_relative_Unprefixed_SI, { 0xd5c00000 }
45905
  },
45906
/* ldc ${Dsp-16-u16},${cr2-32} */
45907
  {
45908
    { 0, 0, 0, 0 },
45909
    { { MNEM, ' ', OP (DSP_16_U16), ',', OP (CR2_32), 0 } },
45910
    & ifmt_stc32_src_cr2_dst32_16_16_absolute_Unprefixed_SI, { 0xd7c00000 }
45911
  },
45912
/* ldc ${Dsp-16-u24},${cr2-32} */
45913
  {
45914
    { 0, 0, 0, 0 },
45915
    { { MNEM, ' ', OP (DSP_16_U24), ',', OP (CR2_32), 0 } },
45916
    & ifmt_stc32_src_cr2_dst32_16_24_absolute_Unprefixed_SI, { 0xd7800000 }
45917
  },
45918
/* ldc $Dst32RnPrefixedHI,${cr1-Prefixed-32} */
45919
  {
45920
    { 0, 0, 0, 0 },
45921
    { { MNEM, ' ', OP (DST32RNPREFIXEDHI), ',', OP (CR1_PREFIXED_32), 0 } },
45922
    & ifmt_stc32_src_cr1_dst32_Rn_direct_Prefixed_HI, { 0x1d908 }
45923
  },
45924
/* ldc $Dst32AnPrefixedHI,${cr1-Prefixed-32} */
45925
  {
45926
    { 0, 0, 0, 0 },
45927
    { { MNEM, ' ', OP (DST32ANPREFIXEDHI), ',', OP (CR1_PREFIXED_32), 0 } },
45928
    & ifmt_stc32_src_cr1_dst32_An_direct_Prefixed_HI, { 0x1d188 }
45929
  },
45930
/* ldc [$Dst32AnPrefixed],${cr1-Prefixed-32} */
45931
  {
45932
    { 0, 0, 0, 0 },
45933
    { { MNEM, ' ', '[', OP (DST32ANPREFIXED), ']', ',', OP (CR1_PREFIXED_32), 0 } },
45934
    & ifmt_stc32_src_cr1_dst32_An_indirect_Prefixed_HI, { 0x1d108 }
45935
  },
45936
/* ldc ${Dsp-24-u8}[$Dst32AnPrefixed],${cr1-Prefixed-32} */
45937
  {
45938
    { 0, 0, 0, 0 },
45939
    { { MNEM, ' ', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', ',', OP (CR1_PREFIXED_32), 0 } },
45940
    & ifmt_stc32_src_cr1_dst32_24_8_An_relative_Prefixed_HI, { 0x1d30800 }
45941
  },
45942
/* ldc ${Dsp-24-u16}[$Dst32AnPrefixed],${cr1-Prefixed-32} */
45943
  {
45944
    { 0, 0, 0, 0 },
45945
    { { MNEM, ' ', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', ',', OP (CR1_PREFIXED_32), 0 } },
45946
    & ifmt_stc32_src_cr1_dst32_24_16_An_relative_Prefixed_HI, { 0x1d50800 }
45947
  },
45948
/* ldc ${Dsp-24-u24}[$Dst32AnPrefixed],${cr1-Prefixed-32} */
45949
  {
45950
    { 0, 0, 0, 0 },
45951
    { { MNEM, ' ', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', ',', OP (CR1_PREFIXED_32), 0 } },
45952
    & ifmt_stc32_src_cr1_dst32_24_24_An_relative_Prefixed_HI, { 0x1d70800 }
45953
  },
45954
/* ldc ${Dsp-24-u8}[sb],${cr1-Prefixed-32} */
45955
  {
45956
    { 0, 0, 0, 0 },
45957
    { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (CR1_PREFIXED_32), 0 } },
45958
    & ifmt_stc32_src_cr1_dst32_24_8_SB_relative_Prefixed_HI, { 0x1d38800 }
45959
  },
45960
/* ldc ${Dsp-24-u16}[sb],${cr1-Prefixed-32} */
45961
  {
45962
    { 0, 0, 0, 0 },
45963
    { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (CR1_PREFIXED_32), 0 } },
45964
    & ifmt_stc32_src_cr1_dst32_24_16_SB_relative_Prefixed_HI, { 0x1d58800 }
45965
  },
45966
/* ldc ${Dsp-24-s8}[fb],${cr1-Prefixed-32} */
45967
  {
45968
    { 0, 0, 0, 0 },
45969
    { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (CR1_PREFIXED_32), 0 } },
45970
    & ifmt_stc32_src_cr1_dst32_24_8_FB_relative_Prefixed_HI, { 0x1d3c800 }
45971
  },
45972
/* ldc ${Dsp-24-s16}[fb],${cr1-Prefixed-32} */
45973
  {
45974
    { 0, 0, 0, 0 },
45975
    { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (CR1_PREFIXED_32), 0 } },
45976
    & ifmt_stc32_src_cr1_dst32_24_16_FB_relative_Prefixed_HI, { 0x1d5c800 }
45977
  },
45978
/* ldc ${Dsp-24-u16},${cr1-Prefixed-32} */
45979
  {
45980
    { 0, 0, 0, 0 },
45981
    { { MNEM, ' ', OP (DSP_24_U16), ',', OP (CR1_PREFIXED_32), 0 } },
45982
    & ifmt_stc32_src_cr1_dst32_24_16_absolute_Prefixed_HI, { 0x1d7c800 }
45983
  },
45984
/* ldc ${Dsp-24-u24},${cr1-Prefixed-32} */
45985
  {
45986
    { 0, 0, 0, 0 },
45987
    { { MNEM, ' ', OP (DSP_24_U24), ',', OP (CR1_PREFIXED_32), 0 } },
45988
    & ifmt_stc32_src_cr1_dst32_24_24_absolute_Prefixed_HI, { 0x1d78800 }
45989
  },
45990
/* ldc $Dst16RnHI,${cr16} */
45991
  {
45992
    { 0, 0, 0, 0 },
45993
    { { MNEM, ' ', OP (DST16RNHI), ',', OP (CR16), 0 } },
45994
    & ifmt_stc16_src_dst16_Rn_direct_HI, { 0x7a80 }
45995
  },
45996
/* ldc $Dst16AnHI,${cr16} */
45997
  {
45998
    { 0, 0, 0, 0 },
45999
    { { MNEM, ' ', OP (DST16ANHI), ',', OP (CR16), 0 } },
46000
    & ifmt_stc16_src_dst16_An_direct_HI, { 0x7a84 }
46001
  },
46002
/* ldc [$Dst16An],${cr16} */
46003
  {
46004
    { 0, 0, 0, 0 },
46005
    { { MNEM, ' ', '[', OP (DST16AN), ']', ',', OP (CR16), 0 } },
46006
    & ifmt_stc16_src_dst16_An_indirect_HI, { 0x7a86 }
46007
  },
46008
/* ldc ${Dsp-16-u8}[$Dst16An],${cr16} */
46009
  {
46010
    { 0, 0, 0, 0 },
46011
    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', OP (CR16), 0 } },
46012
    & ifmt_stc16_src_dst16_16_8_An_relative_HI, { 0x7a8800 }
46013
  },
46014
/* ldc ${Dsp-16-u16}[$Dst16An],${cr16} */
46015
  {
46016
    { 0, 0, 0, 0 },
46017
    { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', OP (CR16), 0 } },
46018
    & ifmt_stc16_src_dst16_16_16_An_relative_HI, { 0x7a8c0000 }
46019
  },
46020
/* ldc ${Dsp-16-u8}[sb],${cr16} */
46021
  {
46022
    { 0, 0, 0, 0 },
46023
    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (CR16), 0 } },
46024
    & ifmt_stc16_src_dst16_16_8_SB_relative_HI, { 0x7a8a00 }
46025
  },
46026
/* ldc ${Dsp-16-u16}[sb],${cr16} */
46027
  {
46028
    { 0, 0, 0, 0 },
46029
    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (CR16), 0 } },
46030
    & ifmt_stc16_src_dst16_16_16_SB_relative_HI, { 0x7a8e0000 }
46031
  },
46032
/* ldc ${Dsp-16-s8}[fb],${cr16} */
46033
  {
46034
    { 0, 0, 0, 0 },
46035
    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (CR16), 0 } },
46036
    & ifmt_stc16_src_dst16_16_8_FB_relative_HI, { 0x7a8b00 }
46037
  },
46038
/* ldc ${Dsp-16-u16},${cr16} */
46039
  {
46040
    { 0, 0, 0, 0 },
46041
    { { MNEM, ' ', OP (DSP_16_U16), ',', OP (CR16), 0 } },
46042
    & ifmt_stc16_src_dst16_16_16_absolute_HI, { 0x7a8f0000 }
46043
  },
46044
/* jsri.a ${Dsp-16-u24}[$Dst32AnUnprefixed] */
46045
  {
46046
    { 0, 0, 0, 0 },
46047
    { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
46048
    & ifmt_shl32_l_dst_dst32_16_24_An_relative_Unprefixed_SI, { 0x96010000 }
46049
  },
46050
/* jsri.a ${Dsp-16-u24} */
46051
  {
46052
    { 0, 0, 0, 0 },
46053
    { { MNEM, ' ', OP (DSP_16_U24), 0 } },
46054
    & ifmt_shl32_l_dst_dst32_16_24_absolute_Unprefixed_SI, { 0x96810000 }
46055
  },
46056
/* jsri.a $Dst32RnUnprefixedSI */
46057
  {
46058
    { 0, 0, 0, 0 },
46059
    { { MNEM, ' ', OP (DST32RNUNPREFIXEDSI), 0 } },
46060
    & ifmt_shl32_l_dst_dst32_Rn_direct_Unprefixed_SI, { 0x9801 }
46061
  },
46062
/* jsri.a $Dst32AnUnprefixedSI */
46063
  {
46064
    { 0, 0, 0, 0 },
46065
    { { MNEM, ' ', OP (DST32ANUNPREFIXEDSI), 0 } },
46066
    & ifmt_exts32_w_16_ExtUnprefixed_dst32_An_direct_Unprefixed_SI, { 0x9081 }
46067
  },
46068
/* jsri.a [$Dst32AnUnprefixed] */
46069
  {
46070
    { 0, 0, 0, 0 },
46071
    { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
46072
    & ifmt_shl32_l_dst_dst32_An_indirect_Unprefixed_SI, { 0x9001 }
46073
  },
46074
/* jsri.a $Dst16RnSI */
46075
  {
46076
    { 0, 0, 0, 0 },
46077
    { { MNEM, ' ', OP (DST16RNSI), 0 } },
46078
    & ifmt_jsri16a_dst16_basic_SI_dst16_Rn_direct_SI, { 0x7d10 }
46079
  },
46080
/* jsri.a $Dst16AnSI */
46081
  {
46082
    { 0, 0, 0, 0 },
46083
    { { MNEM, ' ', OP (DST16ANSI), 0 } },
46084
    & ifmt_jsri16a_dst16_basic_SI_dst16_An_direct_SI, { 0x7d14 }
46085
  },
46086
/* jsri.a [$Dst16An] */
46087
  {
46088
    { 0, 0, 0, 0 },
46089
    { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } },
46090
    & ifmt_jsri16a_dst16_basic_SI_dst16_An_indirect_SI, { 0x7d16 }
46091
  },
46092
/* jsri.a ${Dsp-16-u16}[sb] */
46093
  {
46094
    { 0, 0, 0, 0 },
46095
    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
46096
    & ifmt_shl32_l_dst_dst32_16_16_SB_relative_Unprefixed_SI, { 0x94810000 }
46097
  },
46098
/* jsri.a ${Dsp-16-s16}[fb] */
46099
  {
46100
    { 0, 0, 0, 0 },
46101
    { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
46102
    & ifmt_shl32_l_dst_dst32_16_16_FB_relative_Unprefixed_SI, { 0x94c10000 }
46103
  },
46104
/* jsri.a ${Dsp-16-u16} */
46105
  {
46106
    { 0, 0, 0, 0 },
46107
    { { MNEM, ' ', OP (DSP_16_U16), 0 } },
46108
    & ifmt_shl32_l_dst_dst32_16_16_absolute_Unprefixed_SI, { 0x96c10000 }
46109
  },
46110
/* jsri.a ${Dsp-16-u16}[sb] */
46111
  {
46112
    { 0, 0, 0, 0 },
46113
    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
46114
    & ifmt_jsri16a_dst16_16_16sa_SI_dst16_16_16_SB_relative_SI, { 0x7d1e0000 }
46115
  },
46116
/* jsri.a ${Dsp-16-u16} */
46117
  {
46118
    { 0, 0, 0, 0 },
46119
    { { MNEM, ' ', OP (DSP_16_U16), 0 } },
46120
    & ifmt_jsri16a_dst16_16_16sa_SI_dst16_16_16_absolute_SI, { 0x7d1f0000 }
46121
  },
46122
/* jsri.a ${Dsp-16-u8}[$Dst32AnUnprefixed] */
46123
  {
46124
    { 0, 0, 0, 0 },
46125
    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
46126
    & ifmt_shl32_l_dst_dst32_16_8_An_relative_Unprefixed_SI, { 0x920100 }
46127
  },
46128
/* jsri.a ${Dsp-16-u8}[sb] */
46129
  {
46130
    { 0, 0, 0, 0 },
46131
    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
46132
    & ifmt_shl32_l_dst_dst32_16_8_SB_relative_Unprefixed_SI, { 0x928100 }
46133
  },
46134
/* jsri.a ${Dsp-16-s8}[fb] */
46135
  {
46136
    { 0, 0, 0, 0 },
46137
    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
46138
    & ifmt_shl32_l_dst_dst32_16_8_FB_relative_Unprefixed_SI, { 0x92c100 }
46139
  },
46140
/* jsri.a ${Dsp-16-u8}[$Dst16An] */
46141
  {
46142
    { 0, 0, 0, 0 },
46143
    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
46144
    & ifmt_jsri16a_dst16_16_8_SI_dst16_16_8_An_relative_SI, { 0x7d1800 }
46145
  },
46146
/* jsri.a ${Dsp-16-u8}[sb] */
46147
  {
46148
    { 0, 0, 0, 0 },
46149
    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
46150
    & ifmt_jsri16a_dst16_16_8_SI_dst16_16_8_SB_relative_SI, { 0x7d1a00 }
46151
  },
46152
/* jsri.a ${Dsp-16-s8}[fb] */
46153
  {
46154
    { 0, 0, 0, 0 },
46155
    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
46156
    & ifmt_jsri16a_dst16_16_8_SI_dst16_16_8_FB_relative_SI, { 0x7d1b00 }
46157
  },
46158
/* jsri.a ${Dsp-16-u24}[$Dst32AnUnprefixed] */
46159
  {
46160
    { 0, 0, 0, 0 },
46161
    { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
46162
    & ifmt_shl32_l_dst_dst32_16_24_An_relative_Unprefixed_SI, { 0x96010000 }
46163
  },
46164
/* jsri.a ${Dsp-16-u24} */
46165
  {
46166
    { 0, 0, 0, 0 },
46167
    { { MNEM, ' ', OP (DSP_16_U24), 0 } },
46168
    & ifmt_shl32_l_dst_dst32_16_24_absolute_Unprefixed_SI, { 0x96810000 }
46169
  },
46170
/* jsri.a ${Dsp-16-u20}[$Dst16An] */
46171
  {
46172
    { 0, 0, 0, 0 },
46173
    { { MNEM, ' ', OP (DSP_16_U20), '[', OP (DST16AN), ']', 0 } },
46174
    & ifmt_jsri16a_dst16_16_20ar_SI_dst16_16_20_An_relative_SI, { 0x7d1c0000 }
46175
  },
46176
/* jsri.w $Dst32RnUnprefixedHI */
46177
  {
46178
    { 0, 0, 0, 0 },
46179
    { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } },
46180
    & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xc91f }
46181
  },
46182
/* jsri.w $Dst32AnUnprefixedHI */
46183
  {
46184
    { 0, 0, 0, 0 },
46185
    { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } },
46186
    & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xc19f }
46187
  },
46188
/* jsri.w [$Dst32AnUnprefixed] */
46189
  {
46190
    { 0, 0, 0, 0 },
46191
    { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
46192
    & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xc11f }
46193
  },
46194
/* jsri.w $Dst16RnHI */
46195
  {
46196
    { 0, 0, 0, 0 },
46197
    { { MNEM, ' ', OP (DST16RNHI), 0 } },
46198
    & ifmt_shl16_w_dst_dst16_Rn_direct_HI, { 0x7d30 }
46199
  },
46200
/* jsri.w $Dst16AnHI */
46201
  {
46202
    { 0, 0, 0, 0 },
46203
    { { MNEM, ' ', OP (DST16ANHI), 0 } },
46204
    & ifmt_shl16_w_dst_dst16_An_direct_HI, { 0x7d34 }
46205
  },
46206
/* jsri.w [$Dst16An] */
46207
  {
46208
    { 0, 0, 0, 0 },
46209
    { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } },
46210
    & ifmt_shl16_w_dst_dst16_An_indirect_HI, { 0x7d36 }
46211
  },
46212
/* jsri.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
46213
  {
46214
    { 0, 0, 0, 0 },
46215
    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
46216
    & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xc31f00 }
46217
  },
46218
/* jsri.w ${Dsp-16-u8}[sb] */
46219
  {
46220
    { 0, 0, 0, 0 },
46221
    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
46222
    & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xc39f00 }
46223
  },
46224
/* jsri.w ${Dsp-16-s8}[fb] */
46225
  {
46226
    { 0, 0, 0, 0 },
46227
    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
46228
    & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xc3df00 }
46229
  },
46230
/* jsri.w ${Dsp-16-u8}[$Dst16An] */
46231
  {
46232
    { 0, 0, 0, 0 },
46233
    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
46234
    & ifmt_shl16_w_dst_dst16_16_8_An_relative_HI, { 0x7d3800 }
46235
  },
46236
/* jsri.w ${Dsp-16-u8}[sb] */
46237
  {
46238
    { 0, 0, 0, 0 },
46239
    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
46240
    & ifmt_shl16_w_dst_dst16_16_8_SB_relative_HI, { 0x7d3a00 }
46241
  },
46242
/* jsri.w ${Dsp-16-s8}[fb] */
46243
  {
46244
    { 0, 0, 0, 0 },
46245
    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
46246
    & ifmt_shl16_w_dst_dst16_16_8_FB_relative_HI, { 0x7d3b00 }
46247
  },
46248
/* jsri.w ${Dsp-16-u16}[sb] */
46249
  {
46250
    { 0, 0, 0, 0 },
46251
    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
46252
    & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xc59f0000 }
46253
  },
46254
/* jsri.w ${Dsp-16-s16}[fb] */
46255
  {
46256
    { 0, 0, 0, 0 },
46257
    { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
46258
    & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xc5df0000 }
46259
  },
46260
/* jsri.w ${Dsp-16-u16} */
46261
  {
46262
    { 0, 0, 0, 0 },
46263
    { { MNEM, ' ', OP (DSP_16_U16), 0 } },
46264
    & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xc7df0000 }
46265
  },
46266
/* jsri.w ${Dsp-16-u16}[sb] */
46267
  {
46268
    { 0, 0, 0, 0 },
46269
    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
46270
    & ifmt_shl16_w_dst_dst16_16_16_SB_relative_HI, { 0x7d3e0000 }
46271
  },
46272
/* jsri.w ${Dsp-16-u16} */
46273
  {
46274
    { 0, 0, 0, 0 },
46275
    { { MNEM, ' ', OP (DSP_16_U16), 0 } },
46276
    & ifmt_shl16_w_dst_dst16_16_16_absolute_HI, { 0x7d3f0000 }
46277
  },
46278
/* jsri.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
46279
  {
46280
    { 0, 0, 0, 0 },
46281
    { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
46282
    & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xc71f0000 }
46283
  },
46284
/* jsri.w ${Dsp-16-u24} */
46285
  {
46286
    { 0, 0, 0, 0 },
46287
    { { MNEM, ' ', OP (DSP_16_U24), 0 } },
46288
    & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xc79f0000 }
46289
  },
46290
/* jsri.w ${Dsp-16-u20}[$Dst16An] */
46291
  {
46292
    { 0, 0, 0, 0 },
46293
    { { MNEM, ' ', OP (DSP_16_U20), '[', OP (DST16AN), ']', 0 } },
46294
    & ifmt_jsri16w_dst16_16_20ar_HI_dst16_16_20_An_relative_HI, { 0x7d3c0000 }
46295
  },
46296
/* jmpi.a $Dst32RnUnprefixedSI */
46297
  {
46298
    { 0, 0, 0, 0 },
46299
    { { MNEM, ' ', OP (DST32RNUNPREFIXEDSI), 0 } },
46300
    & ifmt_shl32_l_dst_dst32_Rn_direct_Unprefixed_SI, { 0x8801 }
46301
  },
46302
/* jmpi.a $Dst32AnUnprefixedSI */
46303
  {
46304
    { 0, 0, 0, 0 },
46305
    { { MNEM, ' ', OP (DST32ANUNPREFIXEDSI), 0 } },
46306
    & ifmt_exts32_w_16_ExtUnprefixed_dst32_An_direct_Unprefixed_SI, { 0x8081 }
46307
  },
46308
/* jmpi.a [$Dst32AnUnprefixed] */
46309
  {
46310
    { 0, 0, 0, 0 },
46311
    { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
46312
    & ifmt_shl32_l_dst_dst32_An_indirect_Unprefixed_SI, { 0x8001 }
46313
  },
46314
/* jmpi.a ${Dsp-16-u8}[$Dst32AnUnprefixed] */
46315
  {
46316
    { 0, 0, 0, 0 },
46317
    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
46318
    & ifmt_shl32_l_dst_dst32_16_8_An_relative_Unprefixed_SI, { 0x820100 }
46319
  },
46320
/* jmpi.a ${Dsp-16-u16}[$Dst32AnUnprefixed] */
46321
  {
46322
    { 0, 0, 0, 0 },
46323
    { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
46324
    & ifmt_shl32_l_dst_dst32_16_16_An_relative_Unprefixed_SI, { 0x84010000 }
46325
  },
46326
/* jmpi.a ${Dsp-16-u24}[$Dst32AnUnprefixed] */
46327
  {
46328
    { 0, 0, 0, 0 },
46329
    { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
46330
    & ifmt_shl32_l_dst_dst32_16_24_An_relative_Unprefixed_SI, { 0x86010000 }
46331
  },
46332
/* jmpi.a ${Dsp-16-u8}[sb] */
46333
  {
46334
    { 0, 0, 0, 0 },
46335
    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
46336
    & ifmt_shl32_l_dst_dst32_16_8_SB_relative_Unprefixed_SI, { 0x828100 }
46337
  },
46338
/* jmpi.a ${Dsp-16-u16}[sb] */
46339
  {
46340
    { 0, 0, 0, 0 },
46341
    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
46342
    & ifmt_shl32_l_dst_dst32_16_16_SB_relative_Unprefixed_SI, { 0x84810000 }
46343
  },
46344
/* jmpi.a ${Dsp-16-s8}[fb] */
46345
  {
46346
    { 0, 0, 0, 0 },
46347
    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
46348
    & ifmt_shl32_l_dst_dst32_16_8_FB_relative_Unprefixed_SI, { 0x82c100 }
46349
  },
46350
/* jmpi.a ${Dsp-16-s16}[fb] */
46351
  {
46352
    { 0, 0, 0, 0 },
46353
    { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
46354
    & ifmt_shl32_l_dst_dst32_16_16_FB_relative_Unprefixed_SI, { 0x84c10000 }
46355
  },
46356
/* jmpi.a ${Dsp-16-u16} */
46357
  {
46358
    { 0, 0, 0, 0 },
46359
    { { MNEM, ' ', OP (DSP_16_U16), 0 } },
46360
    & ifmt_shl32_l_dst_dst32_16_16_absolute_Unprefixed_SI, { 0x86c10000 }
46361
  },
46362
/* jmpi.a ${Dsp-16-u24} */
46363
  {
46364
    { 0, 0, 0, 0 },
46365
    { { MNEM, ' ', OP (DSP_16_U24), 0 } },
46366
    & ifmt_shl32_l_dst_dst32_16_24_absolute_Unprefixed_SI, { 0x86810000 }
46367
  },
46368
/* jmpi.a $Dst16RnSI */
46369
  {
46370
    { 0, 0, 0, 0 },
46371
    { { MNEM, ' ', OP (DST16RNSI), 0 } },
46372
    & ifmt_jsri16a_dst16_basic_SI_dst16_Rn_direct_SI, { 0x7d00 }
46373
  },
46374
/* jmpi.a $Dst16AnSI */
46375
  {
46376
    { 0, 0, 0, 0 },
46377
    { { MNEM, ' ', OP (DST16ANSI), 0 } },
46378
    & ifmt_jsri16a_dst16_basic_SI_dst16_An_direct_SI, { 0x7d04 }
46379
  },
46380
/* jmpi.a [$Dst16An] */
46381
  {
46382
    { 0, 0, 0, 0 },
46383
    { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } },
46384
    & ifmt_jsri16a_dst16_basic_SI_dst16_An_indirect_SI, { 0x7d06 }
46385
  },
46386
/* jmpi.a ${Dsp-16-u8}[$Dst16An] */
46387
  {
46388
    { 0, 0, 0, 0 },
46389
    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
46390
    & ifmt_jsri16a_dst16_16_8_SI_dst16_16_8_An_relative_SI, { 0x7d0800 }
46391
  },
46392
/* jmpi.a ${Dsp-16-u16}[$Dst16An] */
46393
  {
46394
    { 0, 0, 0, 0 },
46395
    { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
46396
    & ifmt_jmpi16_a_16_dst16_16_16_An_relative_SI, { 0x7d0c0000 }
46397
  },
46398
/* jmpi.a ${Dsp-16-u8}[sb] */
46399
  {
46400
    { 0, 0, 0, 0 },
46401
    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
46402
    & ifmt_jsri16a_dst16_16_8_SI_dst16_16_8_SB_relative_SI, { 0x7d0a00 }
46403
  },
46404
/* jmpi.a ${Dsp-16-u16}[sb] */
46405
  {
46406
    { 0, 0, 0, 0 },
46407
    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
46408
    & ifmt_jsri16a_dst16_16_16sa_SI_dst16_16_16_SB_relative_SI, { 0x7d0e0000 }
46409
  },
46410
/* jmpi.a ${Dsp-16-s8}[fb] */
46411
  {
46412
    { 0, 0, 0, 0 },
46413
    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
46414
    & ifmt_jsri16a_dst16_16_8_SI_dst16_16_8_FB_relative_SI, { 0x7d0b00 }
46415
  },
46416
/* jmpi.a ${Dsp-16-u16} */
46417
  {
46418
    { 0, 0, 0, 0 },
46419
    { { MNEM, ' ', OP (DSP_16_U16), 0 } },
46420
    & ifmt_jsri16a_dst16_16_16sa_SI_dst16_16_16_absolute_SI, { 0x7d0f0000 }
46421
  },
46422
/* jmpi.w $Dst32RnUnprefixedHI */
46423
  {
46424
    { 0, 0, 0, 0 },
46425
    { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } },
46426
    & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xc90f }
46427
  },
46428
/* jmpi.w $Dst32AnUnprefixedHI */
46429
  {
46430
    { 0, 0, 0, 0 },
46431
    { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } },
46432
    & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xc18f }
46433
  },
46434
/* jmpi.w [$Dst32AnUnprefixed] */
46435
  {
46436
    { 0, 0, 0, 0 },
46437
    { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
46438
    & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xc10f }
46439
  },
46440
/* jmpi.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
46441
  {
46442
    { 0, 0, 0, 0 },
46443
    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
46444
    & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xc30f00 }
46445
  },
46446
/* jmpi.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
46447
  {
46448
    { 0, 0, 0, 0 },
46449
    { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
46450
    & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xc50f0000 }
46451
  },
46452
/* jmpi.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
46453
  {
46454
    { 0, 0, 0, 0 },
46455
    { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
46456
    & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xc70f0000 }
46457
  },
46458
/* jmpi.w ${Dsp-16-u8}[sb] */
46459
  {
46460
    { 0, 0, 0, 0 },
46461
    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
46462
    & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xc38f00 }
46463
  },
46464
/* jmpi.w ${Dsp-16-u16}[sb] */
46465
  {
46466
    { 0, 0, 0, 0 },
46467
    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
46468
    & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xc58f0000 }
46469
  },
46470
/* jmpi.w ${Dsp-16-s8}[fb] */
46471
  {
46472
    { 0, 0, 0, 0 },
46473
    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
46474
    & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xc3cf00 }
46475
  },
46476
/* jmpi.w ${Dsp-16-s16}[fb] */
46477
  {
46478
    { 0, 0, 0, 0 },
46479
    { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
46480
    & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xc5cf0000 }
46481
  },
46482
/* jmpi.w ${Dsp-16-u16} */
46483
  {
46484
    { 0, 0, 0, 0 },
46485
    { { MNEM, ' ', OP (DSP_16_U16), 0 } },
46486
    & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xc7cf0000 }
46487
  },
46488
/* jmpi.w ${Dsp-16-u24} */
46489
  {
46490
    { 0, 0, 0, 0 },
46491
    { { MNEM, ' ', OP (DSP_16_U24), 0 } },
46492
    & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xc78f0000 }
46493
  },
46494
/* jmpi.w $Dst16RnHI */
46495
  {
46496
    { 0, 0, 0, 0 },
46497
    { { MNEM, ' ', OP (DST16RNHI), 0 } },
46498
    & ifmt_shl16_w_dst_dst16_Rn_direct_HI, { 0x7d20 }
46499
  },
46500
/* jmpi.w $Dst16AnHI */
46501
  {
46502
    { 0, 0, 0, 0 },
46503
    { { MNEM, ' ', OP (DST16ANHI), 0 } },
46504
    & ifmt_shl16_w_dst_dst16_An_direct_HI, { 0x7d24 }
46505
  },
46506
/* jmpi.w [$Dst16An] */
46507
  {
46508
    { 0, 0, 0, 0 },
46509
    { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } },
46510
    & ifmt_shl16_w_dst_dst16_An_indirect_HI, { 0x7d26 }
46511
  },
46512
/* jmpi.w ${Dsp-16-u8}[$Dst16An] */
46513
  {
46514
    { 0, 0, 0, 0 },
46515
    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
46516
    & ifmt_shl16_w_dst_dst16_16_8_An_relative_HI, { 0x7d2800 }
46517
  },
46518
/* jmpi.w ${Dsp-16-u16}[$Dst16An] */
46519
  {
46520
    { 0, 0, 0, 0 },
46521
    { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
46522
    & ifmt_shl16_w_dst_dst16_16_16_An_relative_HI, { 0x7d2c0000 }
46523
  },
46524
/* jmpi.w ${Dsp-16-u8}[sb] */
46525
  {
46526
    { 0, 0, 0, 0 },
46527
    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
46528
    & ifmt_shl16_w_dst_dst16_16_8_SB_relative_HI, { 0x7d2a00 }
46529
  },
46530
/* jmpi.w ${Dsp-16-u16}[sb] */
46531
  {
46532
    { 0, 0, 0, 0 },
46533
    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
46534
    & ifmt_shl16_w_dst_dst16_16_16_SB_relative_HI, { 0x7d2e0000 }
46535
  },
46536
/* jmpi.w ${Dsp-16-s8}[fb] */
46537
  {
46538
    { 0, 0, 0, 0 },
46539
    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
46540
    & ifmt_shl16_w_dst_dst16_16_8_FB_relative_HI, { 0x7d2b00 }
46541
  },
46542
/* jmpi.w ${Dsp-16-u16} */
46543
  {
46544
    { 0, 0, 0, 0 },
46545
    { { MNEM, ' ', OP (DSP_16_U16), 0 } },
46546
    & ifmt_shl16_w_dst_dst16_16_16_absolute_HI, { 0x7d2f0000 }
46547
  },
46548
/* indexws.w $Dst32RnUnprefixedHI */
46549
  {
46550
    { 0, 0, 0, 0 },
46551
    { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } },
46552
    & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xc833 }
46553
  },
46554
/* indexws.w $Dst32AnUnprefixedHI */
46555
  {
46556
    { 0, 0, 0, 0 },
46557
    { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } },
46558
    & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xc0b3 }
46559
  },
46560
/* indexws.w [$Dst32AnUnprefixed] */
46561
  {
46562
    { 0, 0, 0, 0 },
46563
    { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
46564
    & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xc033 }
46565
  },
46566
/* indexws.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
46567
  {
46568
    { 0, 0, 0, 0 },
46569
    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
46570
    & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xc23300 }
46571
  },
46572
/* indexws.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
46573
  {
46574
    { 0, 0, 0, 0 },
46575
    { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
46576
    & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xc4330000 }
46577
  },
46578
/* indexws.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
46579
  {
46580
    { 0, 0, 0, 0 },
46581
    { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
46582
    & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xc6330000 }
46583
  },
46584
/* indexws.w ${Dsp-16-u8}[sb] */
46585
  {
46586
    { 0, 0, 0, 0 },
46587
    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
46588
    & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xc2b300 }
46589
  },
46590
/* indexws.w ${Dsp-16-u16}[sb] */
46591
  {
46592
    { 0, 0, 0, 0 },
46593
    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
46594
    & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xc4b30000 }
46595
  },
46596
/* indexws.w ${Dsp-16-s8}[fb] */
46597
  {
46598
    { 0, 0, 0, 0 },
46599
    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
46600
    & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xc2f300 }
46601
  },
46602
/* indexws.w ${Dsp-16-s16}[fb] */
46603
  {
46604
    { 0, 0, 0, 0 },
46605
    { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
46606
    & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xc4f30000 }
46607
  },
46608
/* indexws.w ${Dsp-16-u16} */
46609
  {
46610
    { 0, 0, 0, 0 },
46611
    { { MNEM, ' ', OP (DSP_16_U16), 0 } },
46612
    & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xc6f30000 }
46613
  },
46614
/* indexws.w ${Dsp-16-u24} */
46615
  {
46616
    { 0, 0, 0, 0 },
46617
    { { MNEM, ' ', OP (DSP_16_U24), 0 } },
46618
    & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xc6b30000 }
46619
  },
46620
/* indexws.b $Dst32RnUnprefixedQI */
46621
  {
46622
    { 0, 0, 0, 0 },
46623
    { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } },
46624
    & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0xc823 }
46625
  },
46626
/* indexws.b $Dst32AnUnprefixedQI */
46627
  {
46628
    { 0, 0, 0, 0 },
46629
    { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } },
46630
    & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0xc0a3 }
46631
  },
46632
/* indexws.b [$Dst32AnUnprefixed] */
46633
  {
46634
    { 0, 0, 0, 0 },
46635
    { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
46636
    & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0xc023 }
46637
  },
46638
/* indexws.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
46639
  {
46640
    { 0, 0, 0, 0 },
46641
    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
46642
    & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0xc22300 }
46643
  },
46644
/* indexws.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
46645
  {
46646
    { 0, 0, 0, 0 },
46647
    { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
46648
    & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0xc4230000 }
46649
  },
46650
/* indexws.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
46651
  {
46652
    { 0, 0, 0, 0 },
46653
    { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
46654
    & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0xc6230000 }
46655
  },
46656
/* indexws.b ${Dsp-16-u8}[sb] */
46657
  {
46658
    { 0, 0, 0, 0 },
46659
    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
46660
    & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0xc2a300 }
46661
  },
46662
/* indexws.b ${Dsp-16-u16}[sb] */
46663
  {
46664
    { 0, 0, 0, 0 },
46665
    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
46666
    & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0xc4a30000 }
46667
  },
46668
/* indexws.b ${Dsp-16-s8}[fb] */
46669
  {
46670
    { 0, 0, 0, 0 },
46671
    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
46672
    & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0xc2e300 }
46673
  },
46674
/* indexws.b ${Dsp-16-s16}[fb] */
46675
  {
46676
    { 0, 0, 0, 0 },
46677
    { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
46678
    & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0xc4e30000 }
46679
  },
46680
/* indexws.b ${Dsp-16-u16} */
46681
  {
46682
    { 0, 0, 0, 0 },
46683
    { { MNEM, ' ', OP (DSP_16_U16), 0 } },
46684
    & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0xc6e30000 }
46685
  },
46686
/* indexws.b ${Dsp-16-u24} */
46687
  {
46688
    { 0, 0, 0, 0 },
46689
    { { MNEM, ' ', OP (DSP_16_U24), 0 } },
46690
    & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0xc6a30000 }
46691
  },
46692
/* indexwd.w $Dst32RnUnprefixedHI */
46693
  {
46694
    { 0, 0, 0, 0 },
46695
    { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } },
46696
    & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xa833 }
46697
  },
46698
/* indexwd.w $Dst32AnUnprefixedHI */
46699
  {
46700
    { 0, 0, 0, 0 },
46701
    { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } },
46702
    & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xa0b3 }
46703
  },
46704
/* indexwd.w [$Dst32AnUnprefixed] */
46705
  {
46706
    { 0, 0, 0, 0 },
46707
    { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
46708
    & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xa033 }
46709
  },
46710
/* indexwd.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
46711
  {
46712
    { 0, 0, 0, 0 },
46713
    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
46714
    & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xa23300 }
46715
  },
46716
/* indexwd.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
46717
  {
46718
    { 0, 0, 0, 0 },
46719
    { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
46720
    & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xa4330000 }
46721
  },
46722
/* indexwd.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
46723
  {
46724
    { 0, 0, 0, 0 },
46725
    { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
46726
    & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xa6330000 }
46727
  },
46728
/* indexwd.w ${Dsp-16-u8}[sb] */
46729
  {
46730
    { 0, 0, 0, 0 },
46731
    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
46732
    & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xa2b300 }
46733
  },
46734
/* indexwd.w ${Dsp-16-u16}[sb] */
46735
  {
46736
    { 0, 0, 0, 0 },
46737
    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
46738
    & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xa4b30000 }
46739
  },
46740
/* indexwd.w ${Dsp-16-s8}[fb] */
46741
  {
46742
    { 0, 0, 0, 0 },
46743
    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
46744
    & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xa2f300 }
46745
  },
46746
/* indexwd.w ${Dsp-16-s16}[fb] */
46747
  {
46748
    { 0, 0, 0, 0 },
46749
    { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
46750
    & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xa4f30000 }
46751
  },
46752
/* indexwd.w ${Dsp-16-u16} */
46753
  {
46754
    { 0, 0, 0, 0 },
46755
    { { MNEM, ' ', OP (DSP_16_U16), 0 } },
46756
    & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xa6f30000 }
46757
  },
46758
/* indexwd.w ${Dsp-16-u24} */
46759
  {
46760
    { 0, 0, 0, 0 },
46761
    { { MNEM, ' ', OP (DSP_16_U24), 0 } },
46762
    & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xa6b30000 }
46763
  },
46764
/* indexwd.b $Dst32RnUnprefixedQI */
46765
  {
46766
    { 0, 0, 0, 0 },
46767
    { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } },
46768
    & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0xa823 }
46769
  },
46770
/* indexwd.b $Dst32AnUnprefixedQI */
46771
  {
46772
    { 0, 0, 0, 0 },
46773
    { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } },
46774
    & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0xa0a3 }
46775
  },
46776
/* indexwd.b [$Dst32AnUnprefixed] */
46777
  {
46778
    { 0, 0, 0, 0 },
46779
    { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
46780
    & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0xa023 }
46781
  },
46782
/* indexwd.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
46783
  {
46784
    { 0, 0, 0, 0 },
46785
    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
46786
    & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0xa22300 }
46787
  },
46788
/* indexwd.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
46789
  {
46790
    { 0, 0, 0, 0 },
46791
    { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
46792
    & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0xa4230000 }
46793
  },
46794
/* indexwd.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
46795
  {
46796
    { 0, 0, 0, 0 },
46797
    { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
46798
    & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0xa6230000 }
46799
  },
46800
/* indexwd.b ${Dsp-16-u8}[sb] */
46801
  {
46802
    { 0, 0, 0, 0 },
46803
    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
46804
    & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0xa2a300 }
46805
  },
46806
/* indexwd.b ${Dsp-16-u16}[sb] */
46807
  {
46808
    { 0, 0, 0, 0 },
46809
    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
46810
    & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0xa4a30000 }
46811
  },
46812
/* indexwd.b ${Dsp-16-s8}[fb] */
46813
  {
46814
    { 0, 0, 0, 0 },
46815
    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
46816
    & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0xa2e300 }
46817
  },
46818
/* indexwd.b ${Dsp-16-s16}[fb] */
46819
  {
46820
    { 0, 0, 0, 0 },
46821
    { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
46822
    & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0xa4e30000 }
46823
  },
46824
/* indexwd.b ${Dsp-16-u16} */
46825
  {
46826
    { 0, 0, 0, 0 },
46827
    { { MNEM, ' ', OP (DSP_16_U16), 0 } },
46828
    & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0xa6e30000 }
46829
  },
46830
/* indexwd.b ${Dsp-16-u24} */
46831
  {
46832
    { 0, 0, 0, 0 },
46833
    { { MNEM, ' ', OP (DSP_16_U24), 0 } },
46834
    & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0xa6a30000 }
46835
  },
46836
/* indexw.w $Dst32RnUnprefixedHI */
46837
  {
46838
    { 0, 0, 0, 0 },
46839
    { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } },
46840
    & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0x8833 }
46841
  },
46842
/* indexw.w $Dst32AnUnprefixedHI */
46843
  {
46844
    { 0, 0, 0, 0 },
46845
    { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } },
46846
    & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0x80b3 }
46847
  },
46848
/* indexw.w [$Dst32AnUnprefixed] */
46849
  {
46850
    { 0, 0, 0, 0 },
46851
    { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
46852
    & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0x8033 }
46853
  },
46854
/* indexw.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
46855
  {
46856
    { 0, 0, 0, 0 },
46857
    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
46858
    & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0x823300 }
46859
  },
46860
/* indexw.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
46861
  {
46862
    { 0, 0, 0, 0 },
46863
    { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
46864
    & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0x84330000 }
46865
  },
46866
/* indexw.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
46867
  {
46868
    { 0, 0, 0, 0 },
46869
    { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
46870
    & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0x86330000 }
46871
  },
46872
/* indexw.w ${Dsp-16-u8}[sb] */
46873
  {
46874
    { 0, 0, 0, 0 },
46875
    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
46876
    & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0x82b300 }
46877
  },
46878
/* indexw.w ${Dsp-16-u16}[sb] */
46879
  {
46880
    { 0, 0, 0, 0 },
46881
    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
46882
    & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0x84b30000 }
46883
  },
46884
/* indexw.w ${Dsp-16-s8}[fb] */
46885
  {
46886
    { 0, 0, 0, 0 },
46887
    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
46888
    & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0x82f300 }
46889
  },
46890
/* indexw.w ${Dsp-16-s16}[fb] */
46891
  {
46892
    { 0, 0, 0, 0 },
46893
    { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
46894
    & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0x84f30000 }
46895
  },
46896
/* indexw.w ${Dsp-16-u16} */
46897
  {
46898
    { 0, 0, 0, 0 },
46899
    { { MNEM, ' ', OP (DSP_16_U16), 0 } },
46900
    & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0x86f30000 }
46901
  },
46902
/* indexw.w ${Dsp-16-u24} */
46903
  {
46904
    { 0, 0, 0, 0 },
46905
    { { MNEM, ' ', OP (DSP_16_U24), 0 } },
46906
    & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0x86b30000 }
46907
  },
46908
/* indexw.b $Dst32RnUnprefixedQI */
46909
  {
46910
    { 0, 0, 0, 0 },
46911
    { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } },
46912
    & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0x8823 }
46913
  },
46914
/* indexw.b $Dst32AnUnprefixedQI */
46915
  {
46916
    { 0, 0, 0, 0 },
46917
    { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } },
46918
    & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0x80a3 }
46919
  },
46920
/* indexw.b [$Dst32AnUnprefixed] */
46921
  {
46922
    { 0, 0, 0, 0 },
46923
    { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
46924
    & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0x8023 }
46925
  },
46926
/* indexw.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
46927
  {
46928
    { 0, 0, 0, 0 },
46929
    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
46930
    & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0x822300 }
46931
  },
46932
/* indexw.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
46933
  {
46934
    { 0, 0, 0, 0 },
46935
    { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
46936
    & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0x84230000 }
46937
  },
46938
/* indexw.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
46939
  {
46940
    { 0, 0, 0, 0 },
46941
    { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
46942
    & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0x86230000 }
46943
  },
46944
/* indexw.b ${Dsp-16-u8}[sb] */
46945
  {
46946
    { 0, 0, 0, 0 },
46947
    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
46948
    & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0x82a300 }
46949
  },
46950
/* indexw.b ${Dsp-16-u16}[sb] */
46951
  {
46952
    { 0, 0, 0, 0 },
46953
    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
46954
    & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0x84a30000 }
46955
  },
46956
/* indexw.b ${Dsp-16-s8}[fb] */
46957
  {
46958
    { 0, 0, 0, 0 },
46959
    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
46960
    & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82e300 }
46961
  },
46962
/* indexw.b ${Dsp-16-s16}[fb] */
46963
  {
46964
    { 0, 0, 0, 0 },
46965
    { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
46966
    & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84e30000 }
46967
  },
46968
/* indexw.b ${Dsp-16-u16} */
46969
  {
46970
    { 0, 0, 0, 0 },
46971
    { { MNEM, ' ', OP (DSP_16_U16), 0 } },
46972
    & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0x86e30000 }
46973
  },
46974
/* indexw.b ${Dsp-16-u24} */
46975
  {
46976
    { 0, 0, 0, 0 },
46977
    { { MNEM, ' ', OP (DSP_16_U24), 0 } },
46978
    & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0x86a30000 }
46979
  },
46980
/* indexls.w $Dst32RnUnprefixedHI */
46981
  {
46982
    { 0, 0, 0, 0 },
46983
    { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } },
46984
    & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0x9813 }
46985
  },
46986
/* indexls.w $Dst32AnUnprefixedHI */
46987
  {
46988
    { 0, 0, 0, 0 },
46989
    { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } },
46990
    & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0x9093 }
46991
  },
46992
/* indexls.w [$Dst32AnUnprefixed] */
46993
  {
46994
    { 0, 0, 0, 0 },
46995
    { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
46996
    & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0x9013 }
46997
  },
46998
/* indexls.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
46999
  {
47000
    { 0, 0, 0, 0 },
47001
    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47002
    & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0x921300 }
47003
  },
47004
/* indexls.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
47005
  {
47006
    { 0, 0, 0, 0 },
47007
    { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47008
    & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0x94130000 }
47009
  },
47010
/* indexls.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
47011
  {
47012
    { 0, 0, 0, 0 },
47013
    { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47014
    & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0x96130000 }
47015
  },
47016
/* indexls.w ${Dsp-16-u8}[sb] */
47017
  {
47018
    { 0, 0, 0, 0 },
47019
    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
47020
    & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0x929300 }
47021
  },
47022
/* indexls.w ${Dsp-16-u16}[sb] */
47023
  {
47024
    { 0, 0, 0, 0 },
47025
    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
47026
    & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0x94930000 }
47027
  },
47028
/* indexls.w ${Dsp-16-s8}[fb] */
47029
  {
47030
    { 0, 0, 0, 0 },
47031
    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
47032
    & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0x92d300 }
47033
  },
47034
/* indexls.w ${Dsp-16-s16}[fb] */
47035
  {
47036
    { 0, 0, 0, 0 },
47037
    { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
47038
    & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0x94d30000 }
47039
  },
47040
/* indexls.w ${Dsp-16-u16} */
47041
  {
47042
    { 0, 0, 0, 0 },
47043
    { { MNEM, ' ', OP (DSP_16_U16), 0 } },
47044
    & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0x96d30000 }
47045
  },
47046
/* indexls.w ${Dsp-16-u24} */
47047
  {
47048
    { 0, 0, 0, 0 },
47049
    { { MNEM, ' ', OP (DSP_16_U24), 0 } },
47050
    & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0x96930000 }
47051
  },
47052
/* indexls.b $Dst32RnUnprefixedQI */
47053
  {
47054
    { 0, 0, 0, 0 },
47055
    { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } },
47056
    & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0x9803 }
47057
  },
47058
/* indexls.b $Dst32AnUnprefixedQI */
47059
  {
47060
    { 0, 0, 0, 0 },
47061
    { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } },
47062
    & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0x9083 }
47063
  },
47064
/* indexls.b [$Dst32AnUnprefixed] */
47065
  {
47066
    { 0, 0, 0, 0 },
47067
    { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47068
    & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0x9003 }
47069
  },
47070
/* indexls.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
47071
  {
47072
    { 0, 0, 0, 0 },
47073
    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47074
    & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0x920300 }
47075
  },
47076
/* indexls.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
47077
  {
47078
    { 0, 0, 0, 0 },
47079
    { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47080
    & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0x94030000 }
47081
  },
47082
/* indexls.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
47083
  {
47084
    { 0, 0, 0, 0 },
47085
    { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47086
    & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0x96030000 }
47087
  },
47088
/* indexls.b ${Dsp-16-u8}[sb] */
47089
  {
47090
    { 0, 0, 0, 0 },
47091
    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
47092
    & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0x928300 }
47093
  },
47094
/* indexls.b ${Dsp-16-u16}[sb] */
47095
  {
47096
    { 0, 0, 0, 0 },
47097
    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
47098
    & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0x94830000 }
47099
  },
47100
/* indexls.b ${Dsp-16-s8}[fb] */
47101
  {
47102
    { 0, 0, 0, 0 },
47103
    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
47104
    & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0x92c300 }
47105
  },
47106
/* indexls.b ${Dsp-16-s16}[fb] */
47107
  {
47108
    { 0, 0, 0, 0 },
47109
    { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
47110
    & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0x94c30000 }
47111
  },
47112
/* indexls.b ${Dsp-16-u16} */
47113
  {
47114
    { 0, 0, 0, 0 },
47115
    { { MNEM, ' ', OP (DSP_16_U16), 0 } },
47116
    & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0x96c30000 }
47117
  },
47118
/* indexls.b ${Dsp-16-u24} */
47119
  {
47120
    { 0, 0, 0, 0 },
47121
    { { MNEM, ' ', OP (DSP_16_U24), 0 } },
47122
    & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0x96830000 }
47123
  },
47124
/* indexld.w $Dst32RnUnprefixedHI */
47125
  {
47126
    { 0, 0, 0, 0 },
47127
    { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } },
47128
    & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xb833 }
47129
  },
47130
/* indexld.w $Dst32AnUnprefixedHI */
47131
  {
47132
    { 0, 0, 0, 0 },
47133
    { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } },
47134
    & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xb0b3 }
47135
  },
47136
/* indexld.w [$Dst32AnUnprefixed] */
47137
  {
47138
    { 0, 0, 0, 0 },
47139
    { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47140
    & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xb033 }
47141
  },
47142
/* indexld.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
47143
  {
47144
    { 0, 0, 0, 0 },
47145
    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47146
    & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xb23300 }
47147
  },
47148
/* indexld.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
47149
  {
47150
    { 0, 0, 0, 0 },
47151
    { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47152
    & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xb4330000 }
47153
  },
47154
/* indexld.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
47155
  {
47156
    { 0, 0, 0, 0 },
47157
    { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47158
    & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xb6330000 }
47159
  },
47160
/* indexld.w ${Dsp-16-u8}[sb] */
47161
  {
47162
    { 0, 0, 0, 0 },
47163
    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
47164
    & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xb2b300 }
47165
  },
47166
/* indexld.w ${Dsp-16-u16}[sb] */
47167
  {
47168
    { 0, 0, 0, 0 },
47169
    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
47170
    & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xb4b30000 }
47171
  },
47172
/* indexld.w ${Dsp-16-s8}[fb] */
47173
  {
47174
    { 0, 0, 0, 0 },
47175
    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
47176
    & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xb2f300 }
47177
  },
47178
/* indexld.w ${Dsp-16-s16}[fb] */
47179
  {
47180
    { 0, 0, 0, 0 },
47181
    { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
47182
    & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xb4f30000 }
47183
  },
47184
/* indexld.w ${Dsp-16-u16} */
47185
  {
47186
    { 0, 0, 0, 0 },
47187
    { { MNEM, ' ', OP (DSP_16_U16), 0 } },
47188
    & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xb6f30000 }
47189
  },
47190
/* indexld.w ${Dsp-16-u24} */
47191
  {
47192
    { 0, 0, 0, 0 },
47193
    { { MNEM, ' ', OP (DSP_16_U24), 0 } },
47194
    & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xb6b30000 }
47195
  },
47196
/* indexld.b $Dst32RnUnprefixedQI */
47197
  {
47198
    { 0, 0, 0, 0 },
47199
    { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } },
47200
    & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0xb823 }
47201
  },
47202
/* indexld.b $Dst32AnUnprefixedQI */
47203
  {
47204
    { 0, 0, 0, 0 },
47205
    { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } },
47206
    & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0xb0a3 }
47207
  },
47208
/* indexld.b [$Dst32AnUnprefixed] */
47209
  {
47210
    { 0, 0, 0, 0 },
47211
    { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47212
    & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0xb023 }
47213
  },
47214
/* indexld.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
47215
  {
47216
    { 0, 0, 0, 0 },
47217
    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47218
    & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0xb22300 }
47219
  },
47220
/* indexld.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
47221
  {
47222
    { 0, 0, 0, 0 },
47223
    { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47224
    & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0xb4230000 }
47225
  },
47226
/* indexld.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
47227
  {
47228
    { 0, 0, 0, 0 },
47229
    { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47230
    & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0xb6230000 }
47231
  },
47232
/* indexld.b ${Dsp-16-u8}[sb] */
47233
  {
47234
    { 0, 0, 0, 0 },
47235
    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
47236
    & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0xb2a300 }
47237
  },
47238
/* indexld.b ${Dsp-16-u16}[sb] */
47239
  {
47240
    { 0, 0, 0, 0 },
47241
    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
47242
    & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0xb4a30000 }
47243
  },
47244
/* indexld.b ${Dsp-16-s8}[fb] */
47245
  {
47246
    { 0, 0, 0, 0 },
47247
    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
47248
    & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0xb2e300 }
47249
  },
47250
/* indexld.b ${Dsp-16-s16}[fb] */
47251
  {
47252
    { 0, 0, 0, 0 },
47253
    { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
47254
    & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0xb4e30000 }
47255
  },
47256
/* indexld.b ${Dsp-16-u16} */
47257
  {
47258
    { 0, 0, 0, 0 },
47259
    { { MNEM, ' ', OP (DSP_16_U16), 0 } },
47260
    & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0xb6e30000 }
47261
  },
47262
/* indexld.b ${Dsp-16-u24} */
47263
  {
47264
    { 0, 0, 0, 0 },
47265
    { { MNEM, ' ', OP (DSP_16_U24), 0 } },
47266
    & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0xb6a30000 }
47267
  },
47268
/* indexl.w $Dst32RnUnprefixedHI */
47269
  {
47270
    { 0, 0, 0, 0 },
47271
    { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } },
47272
    & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0x9833 }
47273
  },
47274
/* indexl.w $Dst32AnUnprefixedHI */
47275
  {
47276
    { 0, 0, 0, 0 },
47277
    { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } },
47278
    & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0x90b3 }
47279
  },
47280
/* indexl.w [$Dst32AnUnprefixed] */
47281
  {
47282
    { 0, 0, 0, 0 },
47283
    { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47284
    & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0x9033 }
47285
  },
47286
/* indexl.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
47287
  {
47288
    { 0, 0, 0, 0 },
47289
    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47290
    & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0x923300 }
47291
  },
47292
/* indexl.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
47293
  {
47294
    { 0, 0, 0, 0 },
47295
    { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47296
    & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0x94330000 }
47297
  },
47298
/* indexl.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
47299
  {
47300
    { 0, 0, 0, 0 },
47301
    { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47302
    & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0x96330000 }
47303
  },
47304
/* indexl.w ${Dsp-16-u8}[sb] */
47305
  {
47306
    { 0, 0, 0, 0 },
47307
    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
47308
    & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0x92b300 }
47309
  },
47310
/* indexl.w ${Dsp-16-u16}[sb] */
47311
  {
47312
    { 0, 0, 0, 0 },
47313
    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
47314
    & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0x94b30000 }
47315
  },
47316
/* indexl.w ${Dsp-16-s8}[fb] */
47317
  {
47318
    { 0, 0, 0, 0 },
47319
    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
47320
    & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0x92f300 }
47321
  },
47322
/* indexl.w ${Dsp-16-s16}[fb] */
47323
  {
47324
    { 0, 0, 0, 0 },
47325
    { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
47326
    & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0x94f30000 }
47327
  },
47328
/* indexl.w ${Dsp-16-u16} */
47329
  {
47330
    { 0, 0, 0, 0 },
47331
    { { MNEM, ' ', OP (DSP_16_U16), 0 } },
47332
    & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0x96f30000 }
47333
  },
47334
/* indexl.w ${Dsp-16-u24} */
47335
  {
47336
    { 0, 0, 0, 0 },
47337
    { { MNEM, ' ', OP (DSP_16_U24), 0 } },
47338
    & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0x96b30000 }
47339
  },
47340
/* indexl.b $Dst32RnUnprefixedQI */
47341
  {
47342
    { 0, 0, 0, 0 },
47343
    { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } },
47344
    & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0x9823 }
47345
  },
47346
/* indexl.b $Dst32AnUnprefixedQI */
47347
  {
47348
    { 0, 0, 0, 0 },
47349
    { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } },
47350
    & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0x90a3 }
47351
  },
47352
/* indexl.b [$Dst32AnUnprefixed] */
47353
  {
47354
    { 0, 0, 0, 0 },
47355
    { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47356
    & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0x9023 }
47357
  },
47358
/* indexl.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
47359
  {
47360
    { 0, 0, 0, 0 },
47361
    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47362
    & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0x922300 }
47363
  },
47364
/* indexl.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
47365
  {
47366
    { 0, 0, 0, 0 },
47367
    { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47368
    & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0x94230000 }
47369
  },
47370
/* indexl.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
47371
  {
47372
    { 0, 0, 0, 0 },
47373
    { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47374
    & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0x96230000 }
47375
  },
47376
/* indexl.b ${Dsp-16-u8}[sb] */
47377
  {
47378
    { 0, 0, 0, 0 },
47379
    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
47380
    & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0x92a300 }
47381
  },
47382
/* indexl.b ${Dsp-16-u16}[sb] */
47383
  {
47384
    { 0, 0, 0, 0 },
47385
    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
47386
    & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0x94a30000 }
47387
  },
47388
/* indexl.b ${Dsp-16-s8}[fb] */
47389
  {
47390
    { 0, 0, 0, 0 },
47391
    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
47392
    & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0x92e300 }
47393
  },
47394
/* indexl.b ${Dsp-16-s16}[fb] */
47395
  {
47396
    { 0, 0, 0, 0 },
47397
    { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
47398
    & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0x94e30000 }
47399
  },
47400
/* indexl.b ${Dsp-16-u16} */
47401
  {
47402
    { 0, 0, 0, 0 },
47403
    { { MNEM, ' ', OP (DSP_16_U16), 0 } },
47404
    & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0x96e30000 }
47405
  },
47406
/* indexl.b ${Dsp-16-u24} */
47407
  {
47408
    { 0, 0, 0, 0 },
47409
    { { MNEM, ' ', OP (DSP_16_U24), 0 } },
47410
    & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0x96a30000 }
47411
  },
47412
/* indexbs.w $Dst32RnUnprefixedHI */
47413
  {
47414
    { 0, 0, 0, 0 },
47415
    { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } },
47416
    & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xc813 }
47417
  },
47418
/* indexbs.w $Dst32AnUnprefixedHI */
47419
  {
47420
    { 0, 0, 0, 0 },
47421
    { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } },
47422
    & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xc093 }
47423
  },
47424
/* indexbs.w [$Dst32AnUnprefixed] */
47425
  {
47426
    { 0, 0, 0, 0 },
47427
    { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47428
    & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xc013 }
47429
  },
47430
/* indexbs.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
47431
  {
47432
    { 0, 0, 0, 0 },
47433
    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47434
    & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xc21300 }
47435
  },
47436
/* indexbs.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
47437
  {
47438
    { 0, 0, 0, 0 },
47439
    { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47440
    & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xc4130000 }
47441
  },
47442
/* indexbs.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
47443
  {
47444
    { 0, 0, 0, 0 },
47445
    { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47446
    & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xc6130000 }
47447
  },
47448
/* indexbs.w ${Dsp-16-u8}[sb] */
47449
  {
47450
    { 0, 0, 0, 0 },
47451
    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
47452
    & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xc29300 }
47453
  },
47454
/* indexbs.w ${Dsp-16-u16}[sb] */
47455
  {
47456
    { 0, 0, 0, 0 },
47457
    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
47458
    & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xc4930000 }
47459
  },
47460
/* indexbs.w ${Dsp-16-s8}[fb] */
47461
  {
47462
    { 0, 0, 0, 0 },
47463
    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
47464
    & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xc2d300 }
47465
  },
47466
/* indexbs.w ${Dsp-16-s16}[fb] */
47467
  {
47468
    { 0, 0, 0, 0 },
47469
    { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
47470
    & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xc4d30000 }
47471
  },
47472
/* indexbs.w ${Dsp-16-u16} */
47473
  {
47474
    { 0, 0, 0, 0 },
47475
    { { MNEM, ' ', OP (DSP_16_U16), 0 } },
47476
    & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xc6d30000 }
47477
  },
47478
/* indexbs.w ${Dsp-16-u24} */
47479
  {
47480
    { 0, 0, 0, 0 },
47481
    { { MNEM, ' ', OP (DSP_16_U24), 0 } },
47482
    & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xc6930000 }
47483
  },
47484
/* indexbs.b $Dst32RnUnprefixedQI */
47485
  {
47486
    { 0, 0, 0, 0 },
47487
    { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } },
47488
    & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0xc803 }
47489
  },
47490
/* indexbs.b $Dst32AnUnprefixedQI */
47491
  {
47492
    { 0, 0, 0, 0 },
47493
    { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } },
47494
    & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0xc083 }
47495
  },
47496
/* indexbs.b [$Dst32AnUnprefixed] */
47497
  {
47498
    { 0, 0, 0, 0 },
47499
    { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47500
    & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0xc003 }
47501
  },
47502
/* indexbs.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
47503
  {
47504
    { 0, 0, 0, 0 },
47505
    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47506
    & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0xc20300 }
47507
  },
47508
/* indexbs.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
47509
  {
47510
    { 0, 0, 0, 0 },
47511
    { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47512
    & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0xc4030000 }
47513
  },
47514
/* indexbs.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
47515
  {
47516
    { 0, 0, 0, 0 },
47517
    { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47518
    & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0xc6030000 }
47519
  },
47520
/* indexbs.b ${Dsp-16-u8}[sb] */
47521
  {
47522
    { 0, 0, 0, 0 },
47523
    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
47524
    & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0xc28300 }
47525
  },
47526
/* indexbs.b ${Dsp-16-u16}[sb] */
47527
  {
47528
    { 0, 0, 0, 0 },
47529
    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
47530
    & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0xc4830000 }
47531
  },
47532
/* indexbs.b ${Dsp-16-s8}[fb] */
47533
  {
47534
    { 0, 0, 0, 0 },
47535
    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
47536
    & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0xc2c300 }
47537
  },
47538
/* indexbs.b ${Dsp-16-s16}[fb] */
47539
  {
47540
    { 0, 0, 0, 0 },
47541
    { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
47542
    & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0xc4c30000 }
47543
  },
47544
/* indexbs.b ${Dsp-16-u16} */
47545
  {
47546
    { 0, 0, 0, 0 },
47547
    { { MNEM, ' ', OP (DSP_16_U16), 0 } },
47548
    & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0xc6c30000 }
47549
  },
47550
/* indexbs.b ${Dsp-16-u24} */
47551
  {
47552
    { 0, 0, 0, 0 },
47553
    { { MNEM, ' ', OP (DSP_16_U24), 0 } },
47554
    & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0xc6830000 }
47555
  },
47556
/* indexbd.w $Dst32RnUnprefixedHI */
47557
  {
47558
    { 0, 0, 0, 0 },
47559
    { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } },
47560
    & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xa813 }
47561
  },
47562
/* indexbd.w $Dst32AnUnprefixedHI */
47563
  {
47564
    { 0, 0, 0, 0 },
47565
    { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } },
47566
    & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xa093 }
47567
  },
47568
/* indexbd.w [$Dst32AnUnprefixed] */
47569
  {
47570
    { 0, 0, 0, 0 },
47571
    { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47572
    & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xa013 }
47573
  },
47574
/* indexbd.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
47575
  {
47576
    { 0, 0, 0, 0 },
47577
    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47578
    & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xa21300 }
47579
  },
47580
/* indexbd.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
47581
  {
47582
    { 0, 0, 0, 0 },
47583
    { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47584
    & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xa4130000 }
47585
  },
47586
/* indexbd.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
47587
  {
47588
    { 0, 0, 0, 0 },
47589
    { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47590
    & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xa6130000 }
47591
  },
47592
/* indexbd.w ${Dsp-16-u8}[sb] */
47593
  {
47594
    { 0, 0, 0, 0 },
47595
    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
47596
    & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xa29300 }
47597
  },
47598
/* indexbd.w ${Dsp-16-u16}[sb] */
47599
  {
47600
    { 0, 0, 0, 0 },
47601
    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
47602
    & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xa4930000 }
47603
  },
47604
/* indexbd.w ${Dsp-16-s8}[fb] */
47605
  {
47606
    { 0, 0, 0, 0 },
47607
    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
47608
    & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xa2d300 }
47609
  },
47610
/* indexbd.w ${Dsp-16-s16}[fb] */
47611
  {
47612
    { 0, 0, 0, 0 },
47613
    { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
47614
    & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xa4d30000 }
47615
  },
47616
/* indexbd.w ${Dsp-16-u16} */
47617
  {
47618
    { 0, 0, 0, 0 },
47619
    { { MNEM, ' ', OP (DSP_16_U16), 0 } },
47620
    & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xa6d30000 }
47621
  },
47622
/* indexbd.w ${Dsp-16-u24} */
47623
  {
47624
    { 0, 0, 0, 0 },
47625
    { { MNEM, ' ', OP (DSP_16_U24), 0 } },
47626
    & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xa6930000 }
47627
  },
47628
/* indexbd.b $Dst32RnUnprefixedQI */
47629
  {
47630
    { 0, 0, 0, 0 },
47631
    { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } },
47632
    & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0xa803 }
47633
  },
47634
/* indexbd.b $Dst32AnUnprefixedQI */
47635
  {
47636
    { 0, 0, 0, 0 },
47637
    { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } },
47638
    & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0xa083 }
47639
  },
47640
/* indexbd.b [$Dst32AnUnprefixed] */
47641
  {
47642
    { 0, 0, 0, 0 },
47643
    { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47644
    & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0xa003 }
47645
  },
47646
/* indexbd.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
47647
  {
47648
    { 0, 0, 0, 0 },
47649
    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47650
    & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0xa20300 }
47651
  },
47652
/* indexbd.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
47653
  {
47654
    { 0, 0, 0, 0 },
47655
    { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47656
    & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0xa4030000 }
47657
  },
47658
/* indexbd.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
47659
  {
47660
    { 0, 0, 0, 0 },
47661
    { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47662
    & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0xa6030000 }
47663
  },
47664
/* indexbd.b ${Dsp-16-u8}[sb] */
47665
  {
47666
    { 0, 0, 0, 0 },
47667
    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
47668
    & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0xa28300 }
47669
  },
47670
/* indexbd.b ${Dsp-16-u16}[sb] */
47671
  {
47672
    { 0, 0, 0, 0 },
47673
    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
47674
    & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0xa4830000 }
47675
  },
47676
/* indexbd.b ${Dsp-16-s8}[fb] */
47677
  {
47678
    { 0, 0, 0, 0 },
47679
    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
47680
    & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0xa2c300 }
47681
  },
47682
/* indexbd.b ${Dsp-16-s16}[fb] */
47683
  {
47684
    { 0, 0, 0, 0 },
47685
    { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
47686
    & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0xa4c30000 }
47687
  },
47688
/* indexbd.b ${Dsp-16-u16} */
47689
  {
47690
    { 0, 0, 0, 0 },
47691
    { { MNEM, ' ', OP (DSP_16_U16), 0 } },
47692
    & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0xa6c30000 }
47693
  },
47694
/* indexbd.b ${Dsp-16-u24} */
47695
  {
47696
    { 0, 0, 0, 0 },
47697
    { { MNEM, ' ', OP (DSP_16_U24), 0 } },
47698
    & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0xa6830000 }
47699
  },
47700
/* indexb.w $Dst32RnUnprefixedHI */
47701
  {
47702
    { 0, 0, 0, 0 },
47703
    { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } },
47704
    & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0x8813 }
47705
  },
47706
/* indexb.w $Dst32AnUnprefixedHI */
47707
  {
47708
    { 0, 0, 0, 0 },
47709
    { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } },
47710
    & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0x8093 }
47711
  },
47712
/* indexb.w [$Dst32AnUnprefixed] */
47713
  {
47714
    { 0, 0, 0, 0 },
47715
    { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47716
    & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0x8013 }
47717
  },
47718
/* indexb.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
47719
  {
47720
    { 0, 0, 0, 0 },
47721
    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47722
    & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0x821300 }
47723
  },
47724
/* indexb.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
47725
  {
47726
    { 0, 0, 0, 0 },
47727
    { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47728
    & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0x84130000 }
47729
  },
47730
/* indexb.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
47731
  {
47732
    { 0, 0, 0, 0 },
47733
    { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47734
    & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0x86130000 }
47735
  },
47736
/* indexb.w ${Dsp-16-u8}[sb] */
47737
  {
47738
    { 0, 0, 0, 0 },
47739
    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
47740
    & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0x829300 }
47741
  },
47742
/* indexb.w ${Dsp-16-u16}[sb] */
47743
  {
47744
    { 0, 0, 0, 0 },
47745
    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
47746
    & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0x84930000 }
47747
  },
47748
/* indexb.w ${Dsp-16-s8}[fb] */
47749
  {
47750
    { 0, 0, 0, 0 },
47751
    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
47752
    & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0x82d300 }
47753
  },
47754
/* indexb.w ${Dsp-16-s16}[fb] */
47755
  {
47756
    { 0, 0, 0, 0 },
47757
    { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
47758
    & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0x84d30000 }
47759
  },
47760
/* indexb.w ${Dsp-16-u16} */
47761
  {
47762
    { 0, 0, 0, 0 },
47763
    { { MNEM, ' ', OP (DSP_16_U16), 0 } },
47764
    & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0x86d30000 }
47765
  },
47766
/* indexb.w ${Dsp-16-u24} */
47767
  {
47768
    { 0, 0, 0, 0 },
47769
    { { MNEM, ' ', OP (DSP_16_U24), 0 } },
47770
    & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0x86930000 }
47771
  },
47772
/* indexb.b $Dst32RnUnprefixedQI */
47773
  {
47774
    { 0, 0, 0, 0 },
47775
    { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } },
47776
    & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0x8803 }
47777
  },
47778
/* indexb.b $Dst32AnUnprefixedQI */
47779
  {
47780
    { 0, 0, 0, 0 },
47781
    { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } },
47782
    & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0x8083 }
47783
  },
47784
/* indexb.b [$Dst32AnUnprefixed] */
47785
  {
47786
    { 0, 0, 0, 0 },
47787
    { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47788
    & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0x8003 }
47789
  },
47790
/* indexb.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
47791
  {
47792
    { 0, 0, 0, 0 },
47793
    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47794
    & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0x820300 }
47795
  },
47796
/* indexb.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
47797
  {
47798
    { 0, 0, 0, 0 },
47799
    { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47800
    & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0x84030000 }
47801
  },
47802
/* indexb.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
47803
  {
47804
    { 0, 0, 0, 0 },
47805
    { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47806
    & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0x86030000 }
47807
  },
47808
/* indexb.b ${Dsp-16-u8}[sb] */
47809
  {
47810
    { 0, 0, 0, 0 },
47811
    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
47812
    & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0x828300 }
47813
  },
47814
/* indexb.b ${Dsp-16-u16}[sb] */
47815
  {
47816
    { 0, 0, 0, 0 },
47817
    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
47818
    & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0x84830000 }
47819
  },
47820
/* indexb.b ${Dsp-16-s8}[fb] */
47821
  {
47822
    { 0, 0, 0, 0 },
47823
    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
47824
    & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82c300 }
47825
  },
47826
/* indexb.b ${Dsp-16-s16}[fb] */
47827
  {
47828
    { 0, 0, 0, 0 },
47829
    { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
47830
    & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84c30000 }
47831
  },
47832
/* indexb.b ${Dsp-16-u16} */
47833
  {
47834
    { 0, 0, 0, 0 },
47835
    { { MNEM, ' ', OP (DSP_16_U16), 0 } },
47836
    & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0x86c30000 }
47837
  },
47838
/* indexb.b ${Dsp-16-u24} */
47839
  {
47840
    { 0, 0, 0, 0 },
47841
    { { MNEM, ' ', OP (DSP_16_U24), 0 } },
47842
    & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0x86830000 }
47843
  },
47844
/* inc.w $Dst32RnUnprefixedHI */
47845
  {
47846
    { 0, 0, 0, 0 },
47847
    { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } },
47848
    & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xa90e }
47849
  },
47850
/* inc.w $Dst32AnUnprefixedHI */
47851
  {
47852
    { 0, 0, 0, 0 },
47853
    { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } },
47854
    & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xa18e }
47855
  },
47856
/* inc.w [$Dst32AnUnprefixed] */
47857
  {
47858
    { 0, 0, 0, 0 },
47859
    { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47860
    & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xa10e }
47861
  },
47862
/* inc.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
47863
  {
47864
    { 0, 0, 0, 0 },
47865
    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47866
    & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xa30e00 }
47867
  },
47868
/* inc.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
47869
  {
47870
    { 0, 0, 0, 0 },
47871
    { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47872
    & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xa50e0000 }
47873
  },
47874
/* inc.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
47875
  {
47876
    { 0, 0, 0, 0 },
47877
    { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47878
    & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xa70e0000 }
47879
  },
47880
/* inc.w ${Dsp-16-u8}[sb] */
47881
  {
47882
    { 0, 0, 0, 0 },
47883
    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
47884
    & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xa38e00 }
47885
  },
47886
/* inc.w ${Dsp-16-u16}[sb] */
47887
  {
47888
    { 0, 0, 0, 0 },
47889
    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
47890
    & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xa58e0000 }
47891
  },
47892
/* inc.w ${Dsp-16-s8}[fb] */
47893
  {
47894
    { 0, 0, 0, 0 },
47895
    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
47896
    & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xa3ce00 }
47897
  },
47898
/* inc.w ${Dsp-16-s16}[fb] */
47899
  {
47900
    { 0, 0, 0, 0 },
47901
    { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
47902
    & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xa5ce0000 }
47903
  },
47904
/* inc.w ${Dsp-16-u16} */
47905
  {
47906
    { 0, 0, 0, 0 },
47907
    { { MNEM, ' ', OP (DSP_16_U16), 0 } },
47908
    & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xa7ce0000 }
47909
  },
47910
/* inc.w ${Dsp-16-u24} */
47911
  {
47912
    { 0, 0, 0, 0 },
47913
    { { MNEM, ' ', OP (DSP_16_U24), 0 } },
47914
    & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xa78e0000 }
47915
  },
47916
/* inc.b $Dst32RnUnprefixedQI */
47917
  {
47918
    { 0, 0, 0, 0 },
47919
    { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } },
47920
    & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0xa80e }
47921
  },
47922
/* inc.b $Dst32AnUnprefixedQI */
47923
  {
47924
    { 0, 0, 0, 0 },
47925
    { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } },
47926
    & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0xa08e }
47927
  },
47928
/* inc.b [$Dst32AnUnprefixed] */
47929
  {
47930
    { 0, 0, 0, 0 },
47931
    { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47932
    & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0xa00e }
47933
  },
47934
/* inc.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
47935
  {
47936
    { 0, 0, 0, 0 },
47937
    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47938
    & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0xa20e00 }
47939
  },
47940
/* inc.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
47941
  {
47942
    { 0, 0, 0, 0 },
47943
    { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47944
    & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0xa40e0000 }
47945
  },
47946
/* inc.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
47947
  {
47948
    { 0, 0, 0, 0 },
47949
    { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
47950
    & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0xa60e0000 }
47951
  },
47952
/* inc.b ${Dsp-16-u8}[sb] */
47953
  {
47954
    { 0, 0, 0, 0 },
47955
    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
47956
    & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0xa28e00 }
47957
  },
47958
/* inc.b ${Dsp-16-u16}[sb] */
47959
  {
47960
    { 0, 0, 0, 0 },
47961
    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
47962
    & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0xa48e0000 }
47963
  },
47964
/* inc.b ${Dsp-16-s8}[fb] */
47965
  {
47966
    { 0, 0, 0, 0 },
47967
    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
47968
    & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0xa2ce00 }
47969
  },
47970
/* inc.b ${Dsp-16-s16}[fb] */
47971
  {
47972
    { 0, 0, 0, 0 },
47973
    { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
47974
    & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0xa4ce0000 }
47975
  },
47976
/* inc.b ${Dsp-16-u16} */
47977
  {
47978
    { 0, 0, 0, 0 },
47979
    { { MNEM, ' ', OP (DSP_16_U16), 0 } },
47980
    & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0xa6ce0000 }
47981
  },
47982
/* inc.b ${Dsp-16-u24} */
47983
  {
47984
    { 0, 0, 0, 0 },
47985
    { { MNEM, ' ', OP (DSP_16_U24), 0 } },
47986
    & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0xa68e0000 }
47987
  },
47988
/* inc.b r0l */
47989
  {
47990
    { 0, 0, 0, 0 },
47991
    { { MNEM, ' ', 'r', '0', 'l', 0 } },
47992
    & ifmt_not16_b_s_dst16_3_S_R0l_direct_QI, { 0xa4 }
47993
  },
47994
/* inc.b r0h */
47995
  {
47996
    { 0, 0, 0, 0 },
47997
    { { MNEM, ' ', 'r', '0', 'h', 0 } },
47998
    & ifmt_not16_b_s_dst16_3_S_R0h_direct_QI, { 0xa3 }
47999
  },
48000
/* inc.b ${Dsp-8-u8}[sb] */
48001
  {
48002
    { 0, 0, 0, 0 },
48003
    { { MNEM, ' ', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } },
48004
    & ifmt_not16_b_s_dst16_3_S_8_8_SB_relative_QI, { 0xa500 }
48005
  },
48006
/* inc.b ${Dsp-8-s8}[fb] */
48007
  {
48008
    { 0, 0, 0, 0 },
48009
    { { MNEM, ' ', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } },
48010
    & ifmt_not16_b_s_dst16_3_S_8_8_FB_relative_QI, { 0xa600 }
48011
  },
48012
/* inc.b ${Dsp-8-u16} */
48013
  {
48014
    { 0, 0, 0, 0 },
48015
    { { MNEM, ' ', OP (DSP_8_U16), 0 } },
48016
    & ifmt_not16_b_s_dst16_3_S_8_16_absolute_QI, { 0xa70000 }
48017
  },
48018
/* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
48019
  {
48020
    { 0, 0, 0, 0 },
48021
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
48022
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0x990000 }
48023
  },
48024
/* sub.l${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedSI */
48025
  {
48026
    { 0, 0, 0, 0 },
48027
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
48028
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0x992000 }
48029
  },
48030
/* sub.l${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedSI */
48031
  {
48032
    { 0, 0, 0, 0 },
48033
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
48034
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0x993000 }
48035
  },
48036
/* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
48037
  {
48038
    { 0, 0, 0, 0 },
48039
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
48040
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0x918000 }
48041
  },
48042
/* sub.l${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedSI */
48043
  {
48044
    { 0, 0, 0, 0 },
48045
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
48046
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0x91a000 }
48047
  },
48048
/* sub.l${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedSI */
48049
  {
48050
    { 0, 0, 0, 0 },
48051
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
48052
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0x91b000 }
48053
  },
48054
/* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
48055
  {
48056
    { 0, 0, 0, 0 },
48057
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48058
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0x910000 }
48059
  },
48060
/* sub.l${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
48061
  {
48062
    { 0, 0, 0, 0 },
48063
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48064
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0x912000 }
48065
  },
48066
/* sub.l${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
48067
  {
48068
    { 0, 0, 0, 0 },
48069
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48070
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0x913000 }
48071
  },
48072
/* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
48073
  {
48074
    { 0, 0, 0, 0 },
48075
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48076
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_8_An_relative_Unprefixed_SI, { 0x93000000 }
48077
  },
48078
/* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
48079
  {
48080
    { 0, 0, 0, 0 },
48081
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48082
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_8_An_relative_Unprefixed_SI, { 0x93200000 }
48083
  },
48084
/* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
48085
  {
48086
    { 0, 0, 0, 0 },
48087
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48088
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_8_An_relative_Unprefixed_SI, { 0x93300000 }
48089
  },
48090
/* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
48091
  {
48092
    { 0, 0, 0, 0 },
48093
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48094
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_16_An_relative_Unprefixed_SI, { 0x95000000 }
48095
  },
48096
/* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
48097
  {
48098
    { 0, 0, 0, 0 },
48099
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48100
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_16_An_relative_Unprefixed_SI, { 0x95200000 }
48101
  },
48102
/* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
48103
  {
48104
    { 0, 0, 0, 0 },
48105
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48106
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_16_An_relative_Unprefixed_SI, { 0x95300000 }
48107
  },
48108
/* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
48109
  {
48110
    { 0, 0, 0, 0 },
48111
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48112
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_24_An_relative_Unprefixed_SI, { 0x97000000 }
48113
  },
48114
/* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
48115
  {
48116
    { 0, 0, 0, 0 },
48117
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48118
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_24_An_relative_Unprefixed_SI, { 0x97200000 }
48119
  },
48120
/* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
48121
  {
48122
    { 0, 0, 0, 0 },
48123
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48124
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_24_An_relative_Unprefixed_SI, { 0x97300000 }
48125
  },
48126
/* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
48127
  {
48128
    { 0, 0, 0, 0 },
48129
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
48130
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_8_SB_relative_Unprefixed_SI, { 0x93800000 }
48131
  },
48132
/* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
48133
  {
48134
    { 0, 0, 0, 0 },
48135
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
48136
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_8_SB_relative_Unprefixed_SI, { 0x93a00000 }
48137
  },
48138
/* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
48139
  {
48140
    { 0, 0, 0, 0 },
48141
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
48142
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_8_SB_relative_Unprefixed_SI, { 0x93b00000 }
48143
  },
48144
/* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
48145
  {
48146
    { 0, 0, 0, 0 },
48147
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
48148
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_16_SB_relative_Unprefixed_SI, { 0x95800000 }
48149
  },
48150
/* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
48151
  {
48152
    { 0, 0, 0, 0 },
48153
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
48154
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_16_SB_relative_Unprefixed_SI, { 0x95a00000 }
48155
  },
48156
/* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
48157
  {
48158
    { 0, 0, 0, 0 },
48159
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
48160
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_16_SB_relative_Unprefixed_SI, { 0x95b00000 }
48161
  },
48162
/* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
48163
  {
48164
    { 0, 0, 0, 0 },
48165
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
48166
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_8_FB_relative_Unprefixed_SI, { 0x93c00000 }
48167
  },
48168
/* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
48169
  {
48170
    { 0, 0, 0, 0 },
48171
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
48172
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_8_FB_relative_Unprefixed_SI, { 0x93e00000 }
48173
  },
48174
/* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
48175
  {
48176
    { 0, 0, 0, 0 },
48177
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
48178
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_8_FB_relative_Unprefixed_SI, { 0x93f00000 }
48179
  },
48180
/* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
48181
  {
48182
    { 0, 0, 0, 0 },
48183
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
48184
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_16_FB_relative_Unprefixed_SI, { 0x95c00000 }
48185
  },
48186
/* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
48187
  {
48188
    { 0, 0, 0, 0 },
48189
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
48190
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_16_FB_relative_Unprefixed_SI, { 0x95e00000 }
48191
  },
48192
/* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
48193
  {
48194
    { 0, 0, 0, 0 },
48195
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
48196
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_16_FB_relative_Unprefixed_SI, { 0x95f00000 }
48197
  },
48198
/* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
48199
  {
48200
    { 0, 0, 0, 0 },
48201
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
48202
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_16_absolute_Unprefixed_SI, { 0x97c00000 }
48203
  },
48204
/* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
48205
  {
48206
    { 0, 0, 0, 0 },
48207
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
48208
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_16_absolute_Unprefixed_SI, { 0x97e00000 }
48209
  },
48210
/* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
48211
  {
48212
    { 0, 0, 0, 0 },
48213
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
48214
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_16_absolute_Unprefixed_SI, { 0x97f00000 }
48215
  },
48216
/* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
48217
  {
48218
    { 0, 0, 0, 0 },
48219
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
48220
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_24_absolute_Unprefixed_SI, { 0x97800000 }
48221
  },
48222
/* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
48223
  {
48224
    { 0, 0, 0, 0 },
48225
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } },
48226
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_24_absolute_Unprefixed_SI, { 0x97a00000 }
48227
  },
48228
/* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
48229
  {
48230
    { 0, 0, 0, 0 },
48231
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } },
48232
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_24_absolute_Unprefixed_SI, { 0x97b00000 }
48233
  },
48234
/* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
48235
  {
48236
    { 0, 0, 0, 0 },
48237
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
48238
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xa9000000 }
48239
  },
48240
/* sub.l${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedSI */
48241
  {
48242
    { 0, 0, 0, 0 },
48243
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
48244
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xa9200000 }
48245
  },
48246
/* sub.l${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedSI */
48247
  {
48248
    { 0, 0, 0, 0 },
48249
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
48250
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xa9300000 }
48251
  },
48252
/* sub.l${G} ${Dsp-16-u16},$Dst32RnUnprefixedSI */
48253
  {
48254
    { 0, 0, 0, 0 },
48255
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
48256
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xb9300000 }
48257
  },
48258
/* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
48259
  {
48260
    { 0, 0, 0, 0 },
48261
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
48262
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xa1800000 }
48263
  },
48264
/* sub.l${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedSI */
48265
  {
48266
    { 0, 0, 0, 0 },
48267
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
48268
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xa1a00000 }
48269
  },
48270
/* sub.l${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedSI */
48271
  {
48272
    { 0, 0, 0, 0 },
48273
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
48274
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xa1b00000 }
48275
  },
48276
/* sub.l${G} ${Dsp-16-u16},$Dst32AnUnprefixedSI */
48277
  {
48278
    { 0, 0, 0, 0 },
48279
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
48280
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xb1b00000 }
48281
  },
48282
/* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
48283
  {
48284
    { 0, 0, 0, 0 },
48285
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48286
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xa1000000 }
48287
  },
48288
/* sub.l${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
48289
  {
48290
    { 0, 0, 0, 0 },
48291
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48292
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xa1200000 }
48293
  },
48294
/* sub.l${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
48295
  {
48296
    { 0, 0, 0, 0 },
48297
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48298
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xa1300000 }
48299
  },
48300
/* sub.l${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
48301
  {
48302
    { 0, 0, 0, 0 },
48303
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48304
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xb1300000 }
48305
  },
48306
/* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
48307
  {
48308
    { 0, 0, 0, 0 },
48309
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48310
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_8_An_relative_Unprefixed_SI, { 0xa3000000 }
48311
  },
48312
/* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
48313
  {
48314
    { 0, 0, 0, 0 },
48315
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48316
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_8_An_relative_Unprefixed_SI, { 0xa3200000 }
48317
  },
48318
/* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
48319
  {
48320
    { 0, 0, 0, 0 },
48321
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48322
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_8_An_relative_Unprefixed_SI, { 0xa3300000 }
48323
  },
48324
/* sub.l${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
48325
  {
48326
    { 0, 0, 0, 0 },
48327
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48328
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_8_An_relative_Unprefixed_SI, { 0xb3300000 }
48329
  },
48330
/* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
48331
  {
48332
    { 0, 0, 0, 0 },
48333
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48334
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_16_An_relative_Unprefixed_SI, { 0xa5000000 }
48335
  },
48336
/* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
48337
  {
48338
    { 0, 0, 0, 0 },
48339
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48340
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_16_An_relative_Unprefixed_SI, { 0xa5200000 }
48341
  },
48342
/* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
48343
  {
48344
    { 0, 0, 0, 0 },
48345
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48346
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_16_An_relative_Unprefixed_SI, { 0xa5300000 }
48347
  },
48348
/* sub.l${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
48349
  {
48350
    { 0, 0, 0, 0 },
48351
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48352
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_16_An_relative_Unprefixed_SI, { 0xb5300000 }
48353
  },
48354
/* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
48355
  {
48356
    { 0, 0, 0, 0 },
48357
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48358
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_24_An_relative_Unprefixed_SI, { 0xa7000000 }
48359
  },
48360
/* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
48361
  {
48362
    { 0, 0, 0, 0 },
48363
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48364
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_24_An_relative_Unprefixed_SI, { 0xa7200000 }
48365
  },
48366
/* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
48367
  {
48368
    { 0, 0, 0, 0 },
48369
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48370
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_24_An_relative_Unprefixed_SI, { 0xa7300000 }
48371
  },
48372
/* sub.l${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
48373
  {
48374
    { 0, 0, 0, 0 },
48375
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48376
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_24_An_relative_Unprefixed_SI, { 0xb7300000 }
48377
  },
48378
/* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
48379
  {
48380
    { 0, 0, 0, 0 },
48381
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
48382
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xa3800000 }
48383
  },
48384
/* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
48385
  {
48386
    { 0, 0, 0, 0 },
48387
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
48388
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xa3a00000 }
48389
  },
48390
/* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
48391
  {
48392
    { 0, 0, 0, 0 },
48393
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
48394
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xa3b00000 }
48395
  },
48396
/* sub.l${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
48397
  {
48398
    { 0, 0, 0, 0 },
48399
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
48400
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xb3b00000 }
48401
  },
48402
/* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
48403
  {
48404
    { 0, 0, 0, 0 },
48405
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
48406
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xa5800000 }
48407
  },
48408
/* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
48409
  {
48410
    { 0, 0, 0, 0 },
48411
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
48412
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xa5a00000 }
48413
  },
48414
/* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
48415
  {
48416
    { 0, 0, 0, 0 },
48417
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
48418
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xa5b00000 }
48419
  },
48420
/* sub.l${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
48421
  {
48422
    { 0, 0, 0, 0 },
48423
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
48424
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xb5b00000 }
48425
  },
48426
/* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
48427
  {
48428
    { 0, 0, 0, 0 },
48429
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
48430
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xa3c00000 }
48431
  },
48432
/* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
48433
  {
48434
    { 0, 0, 0, 0 },
48435
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
48436
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xa3e00000 }
48437
  },
48438
/* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
48439
  {
48440
    { 0, 0, 0, 0 },
48441
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
48442
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xa3f00000 }
48443
  },
48444
/* sub.l${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
48445
  {
48446
    { 0, 0, 0, 0 },
48447
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
48448
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xb3f00000 }
48449
  },
48450
/* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
48451
  {
48452
    { 0, 0, 0, 0 },
48453
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
48454
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xa5c00000 }
48455
  },
48456
/* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
48457
  {
48458
    { 0, 0, 0, 0 },
48459
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
48460
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xa5e00000 }
48461
  },
48462
/* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
48463
  {
48464
    { 0, 0, 0, 0 },
48465
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
48466
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xa5f00000 }
48467
  },
48468
/* sub.l${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
48469
  {
48470
    { 0, 0, 0, 0 },
48471
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
48472
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xb5f00000 }
48473
  },
48474
/* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
48475
  {
48476
    { 0, 0, 0, 0 },
48477
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
48478
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_16_absolute_Unprefixed_SI, { 0xa7c00000 }
48479
  },
48480
/* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
48481
  {
48482
    { 0, 0, 0, 0 },
48483
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
48484
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_16_absolute_Unprefixed_SI, { 0xa7e00000 }
48485
  },
48486
/* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
48487
  {
48488
    { 0, 0, 0, 0 },
48489
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
48490
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_16_absolute_Unprefixed_SI, { 0xa7f00000 }
48491
  },
48492
/* sub.l${G} ${Dsp-16-u16},${Dsp-32-u16} */
48493
  {
48494
    { 0, 0, 0, 0 },
48495
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
48496
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_16_absolute_Unprefixed_SI, { 0xb7f00000 }
48497
  },
48498
/* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
48499
  {
48500
    { 0, 0, 0, 0 },
48501
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
48502
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_24_absolute_Unprefixed_SI, { 0xa7800000 }
48503
  },
48504
/* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
48505
  {
48506
    { 0, 0, 0, 0 },
48507
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
48508
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_24_absolute_Unprefixed_SI, { 0xa7a00000 }
48509
  },
48510
/* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
48511
  {
48512
    { 0, 0, 0, 0 },
48513
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
48514
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_24_absolute_Unprefixed_SI, { 0xa7b00000 }
48515
  },
48516
/* sub.l${G} ${Dsp-16-u16},${Dsp-32-u24} */
48517
  {
48518
    { 0, 0, 0, 0 },
48519
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } },
48520
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_24_absolute_Unprefixed_SI, { 0xb7b00000 }
48521
  },
48522
/* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
48523
  {
48524
    { 0, 0, 0, 0 },
48525
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
48526
    & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xb9000000 }
48527
  },
48528
/* sub.l${G} ${Dsp-16-u24},$Dst32RnUnprefixedSI */
48529
  {
48530
    { 0, 0, 0, 0 },
48531
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
48532
    & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xb9200000 }
48533
  },
48534
/* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
48535
  {
48536
    { 0, 0, 0, 0 },
48537
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
48538
    & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xb1800000 }
48539
  },
48540
/* sub.l${G} ${Dsp-16-u24},$Dst32AnUnprefixedSI */
48541
  {
48542
    { 0, 0, 0, 0 },
48543
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
48544
    & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xb1a00000 }
48545
  },
48546
/* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
48547
  {
48548
    { 0, 0, 0, 0 },
48549
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48550
    & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xb1000000 }
48551
  },
48552
/* sub.l${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
48553
  {
48554
    { 0, 0, 0, 0 },
48555
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48556
    & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xb1200000 }
48557
  },
48558
/* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
48559
  {
48560
    { 0, 0, 0, 0 },
48561
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48562
    & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_8_An_relative_Unprefixed_SI, { 0xb3000000 }
48563
  },
48564
/* sub.l${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
48565
  {
48566
    { 0, 0, 0, 0 },
48567
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48568
    & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_8_An_relative_Unprefixed_SI, { 0xb3200000 }
48569
  },
48570
/* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
48571
  {
48572
    { 0, 0, 0, 0 },
48573
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48574
    & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_16_An_relative_Unprefixed_SI, { 0xb5000000 }
48575
  },
48576
/* sub.l${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
48577
  {
48578
    { 0, 0, 0, 0 },
48579
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48580
    & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_16_An_relative_Unprefixed_SI, { 0xb5200000 }
48581
  },
48582
/* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
48583
  {
48584
    { 0, 0, 0, 0 },
48585
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48586
    & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_24_An_relative_Unprefixed_SI, { 0xb7000000 }
48587
  },
48588
/* sub.l${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
48589
  {
48590
    { 0, 0, 0, 0 },
48591
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48592
    & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_24_An_relative_Unprefixed_SI, { 0xb7200000 }
48593
  },
48594
/* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
48595
  {
48596
    { 0, 0, 0, 0 },
48597
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
48598
    & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_8_SB_relative_Unprefixed_SI, { 0xb3800000 }
48599
  },
48600
/* sub.l${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
48601
  {
48602
    { 0, 0, 0, 0 },
48603
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
48604
    & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_8_SB_relative_Unprefixed_SI, { 0xb3a00000 }
48605
  },
48606
/* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
48607
  {
48608
    { 0, 0, 0, 0 },
48609
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
48610
    & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_16_SB_relative_Unprefixed_SI, { 0xb5800000 }
48611
  },
48612
/* sub.l${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
48613
  {
48614
    { 0, 0, 0, 0 },
48615
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
48616
    & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_16_SB_relative_Unprefixed_SI, { 0xb5a00000 }
48617
  },
48618
/* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
48619
  {
48620
    { 0, 0, 0, 0 },
48621
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
48622
    & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_8_FB_relative_Unprefixed_SI, { 0xb3c00000 }
48623
  },
48624
/* sub.l${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
48625
  {
48626
    { 0, 0, 0, 0 },
48627
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
48628
    & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_8_FB_relative_Unprefixed_SI, { 0xb3e00000 }
48629
  },
48630
/* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
48631
  {
48632
    { 0, 0, 0, 0 },
48633
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
48634
    & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_16_FB_relative_Unprefixed_SI, { 0xb5c00000 }
48635
  },
48636
/* sub.l${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
48637
  {
48638
    { 0, 0, 0, 0 },
48639
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
48640
    & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_16_FB_relative_Unprefixed_SI, { 0xb5e00000 }
48641
  },
48642
/* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
48643
  {
48644
    { 0, 0, 0, 0 },
48645
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
48646
    & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_16_absolute_Unprefixed_SI, { 0xb7c00000 }
48647
  },
48648
/* sub.l${G} ${Dsp-16-u24},${Dsp-40-u16} */
48649
  {
48650
    { 0, 0, 0, 0 },
48651
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } },
48652
    & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_16_absolute_Unprefixed_SI, { 0xb7e00000 }
48653
  },
48654
/* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
48655
  {
48656
    { 0, 0, 0, 0 },
48657
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
48658
    & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_24_absolute_Unprefixed_SI, { 0xb7800000 }
48659
  },
48660
/* sub.l${G} ${Dsp-16-u24},${Dsp-40-u24} */
48661
  {
48662
    { 0, 0, 0, 0 },
48663
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } },
48664
    & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_24_absolute_Unprefixed_SI, { 0xb7a00000 }
48665
  },
48666
/* sub.l${G} $Src32RnUnprefixedSI,$Dst32RnUnprefixedSI */
48667
  {
48668
    { 0, 0, 0, 0 },
48669
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
48670
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xc900 }
48671
  },
48672
/* sub.l${G} $Src32AnUnprefixedSI,$Dst32RnUnprefixedSI */
48673
  {
48674
    { 0, 0, 0, 0 },
48675
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
48676
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0x8920 }
48677
  },
48678
/* sub.l${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
48679
  {
48680
    { 0, 0, 0, 0 },
48681
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
48682
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0x8900 }
48683
  },
48684
/* sub.l${G} $Src32RnUnprefixedSI,$Dst32AnUnprefixedSI */
48685
  {
48686
    { 0, 0, 0, 0 },
48687
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
48688
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xc180 }
48689
  },
48690
/* sub.l${G} $Src32AnUnprefixedSI,$Dst32AnUnprefixedSI */
48691
  {
48692
    { 0, 0, 0, 0 },
48693
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
48694
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0x81a0 }
48695
  },
48696
/* sub.l${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
48697
  {
48698
    { 0, 0, 0, 0 },
48699
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
48700
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0x8180 }
48701
  },
48702
/* sub.l${G} $Src32RnUnprefixedSI,[$Dst32AnUnprefixed] */
48703
  {
48704
    { 0, 0, 0, 0 },
48705
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48706
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xc100 }
48707
  },
48708
/* sub.l${G} $Src32AnUnprefixedSI,[$Dst32AnUnprefixed] */
48709
  {
48710
    { 0, 0, 0, 0 },
48711
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48712
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0x8120 }
48713
  },
48714
/* sub.l${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
48715
  {
48716
    { 0, 0, 0, 0 },
48717
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48718
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0x8100 }
48719
  },
48720
/* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
48721
  {
48722
    { 0, 0, 0, 0 },
48723
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48724
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_8_An_relative_Unprefixed_SI, { 0xc30000 }
48725
  },
48726
/* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
48727
  {
48728
    { 0, 0, 0, 0 },
48729
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48730
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_8_An_relative_Unprefixed_SI, { 0x832000 }
48731
  },
48732
/* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
48733
  {
48734
    { 0, 0, 0, 0 },
48735
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48736
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_8_An_relative_Unprefixed_SI, { 0x830000 }
48737
  },
48738
/* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
48739
  {
48740
    { 0, 0, 0, 0 },
48741
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48742
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_16_An_relative_Unprefixed_SI, { 0xc5000000 }
48743
  },
48744
/* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
48745
  {
48746
    { 0, 0, 0, 0 },
48747
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48748
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_16_An_relative_Unprefixed_SI, { 0x85200000 }
48749
  },
48750
/* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
48751
  {
48752
    { 0, 0, 0, 0 },
48753
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48754
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_16_An_relative_Unprefixed_SI, { 0x85000000 }
48755
  },
48756
/* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
48757
  {
48758
    { 0, 0, 0, 0 },
48759
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48760
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_24_An_relative_Unprefixed_SI, { 0xc7000000 }
48761
  },
48762
/* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
48763
  {
48764
    { 0, 0, 0, 0 },
48765
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48766
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_24_An_relative_Unprefixed_SI, { 0x87200000 }
48767
  },
48768
/* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
48769
  {
48770
    { 0, 0, 0, 0 },
48771
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48772
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_24_An_relative_Unprefixed_SI, { 0x87000000 }
48773
  },
48774
/* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-u8}[sb] */
48775
  {
48776
    { 0, 0, 0, 0 },
48777
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
48778
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_8_SB_relative_Unprefixed_SI, { 0xc38000 }
48779
  },
48780
/* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-u8}[sb] */
48781
  {
48782
    { 0, 0, 0, 0 },
48783
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
48784
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_8_SB_relative_Unprefixed_SI, { 0x83a000 }
48785
  },
48786
/* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
48787
  {
48788
    { 0, 0, 0, 0 },
48789
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
48790
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_8_SB_relative_Unprefixed_SI, { 0x838000 }
48791
  },
48792
/* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16}[sb] */
48793
  {
48794
    { 0, 0, 0, 0 },
48795
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
48796
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_16_SB_relative_Unprefixed_SI, { 0xc5800000 }
48797
  },
48798
/* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16}[sb] */
48799
  {
48800
    { 0, 0, 0, 0 },
48801
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
48802
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_16_SB_relative_Unprefixed_SI, { 0x85a00000 }
48803
  },
48804
/* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
48805
  {
48806
    { 0, 0, 0, 0 },
48807
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
48808
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_16_SB_relative_Unprefixed_SI, { 0x85800000 }
48809
  },
48810
/* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-s8}[fb] */
48811
  {
48812
    { 0, 0, 0, 0 },
48813
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
48814
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_8_FB_relative_Unprefixed_SI, { 0xc3c000 }
48815
  },
48816
/* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-s8}[fb] */
48817
  {
48818
    { 0, 0, 0, 0 },
48819
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
48820
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_8_FB_relative_Unprefixed_SI, { 0x83e000 }
48821
  },
48822
/* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
48823
  {
48824
    { 0, 0, 0, 0 },
48825
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
48826
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_8_FB_relative_Unprefixed_SI, { 0x83c000 }
48827
  },
48828
/* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-s16}[fb] */
48829
  {
48830
    { 0, 0, 0, 0 },
48831
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
48832
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_16_FB_relative_Unprefixed_SI, { 0xc5c00000 }
48833
  },
48834
/* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-s16}[fb] */
48835
  {
48836
    { 0, 0, 0, 0 },
48837
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
48838
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_16_FB_relative_Unprefixed_SI, { 0x85e00000 }
48839
  },
48840
/* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
48841
  {
48842
    { 0, 0, 0, 0 },
48843
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
48844
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_16_FB_relative_Unprefixed_SI, { 0x85c00000 }
48845
  },
48846
/* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16} */
48847
  {
48848
    { 0, 0, 0, 0 },
48849
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U16), 0 } },
48850
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_16_absolute_Unprefixed_SI, { 0xc7c00000 }
48851
  },
48852
/* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16} */
48853
  {
48854
    { 0, 0, 0, 0 },
48855
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U16), 0 } },
48856
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_16_absolute_Unprefixed_SI, { 0x87e00000 }
48857
  },
48858
/* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
48859
  {
48860
    { 0, 0, 0, 0 },
48861
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } },
48862
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_16_absolute_Unprefixed_SI, { 0x87c00000 }
48863
  },
48864
/* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-u24} */
48865
  {
48866
    { 0, 0, 0, 0 },
48867
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U24), 0 } },
48868
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_24_absolute_Unprefixed_SI, { 0xc7800000 }
48869
  },
48870
/* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-u24} */
48871
  {
48872
    { 0, 0, 0, 0 },
48873
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U24), 0 } },
48874
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_24_absolute_Unprefixed_SI, { 0x87a00000 }
48875
  },
48876
/* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
48877
  {
48878
    { 0, 0, 0, 0 },
48879
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } },
48880
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_24_absolute_Unprefixed_SI, { 0x87800000 }
48881
  },
48882
/* sub.w${S} #${Imm-16-HI},${Dsp-8-u8}[sb] */
48883
  {
48884
    { 0, 0, 0, 0 },
48885
    { { MNEM, OP (S), ' ', '#', OP (IMM_16_HI), ',', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } },
48886
    & ifmt_tst32_w_imm_S_2_S_8_dst32_2_S_8_SB_relative_HI, { 0x2f000000 }
48887
  },
48888
/* sub.w${S} #${Imm-16-HI},${Dsp-8-s8}[fb] */
48889
  {
48890
    { 0, 0, 0, 0 },
48891
    { { MNEM, OP (S), ' ', '#', OP (IMM_16_HI), ',', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } },
48892
    & ifmt_tst32_w_imm_S_2_S_8_dst32_2_S_8_FB_relative_HI, { 0x3f000000 }
48893
  },
48894
/* sub.w${S} #${Imm-24-HI},${Dsp-8-u16} */
48895
  {
48896
    { 0, 0, 0, 0 },
48897
    { { MNEM, OP (S), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_8_U16), 0 } },
48898
    & ifmt_tst32_w_imm_S_2_S_16_dst32_2_S_16_absolute_HI, { 0x1f000000 }
48899
  },
48900
/* sub.w${S} #${Imm-8-HI},r0 */
48901
  {
48902
    { 0, 0, 0, 0 },
48903
    { { MNEM, OP (S), ' ', '#', OP (IMM_8_HI), ',', 'r', '0', 0 } },
48904
    & ifmt_tst32_w_imm_S_2_S_basic_dst32_2_S_R0_direct_HI, { 0xf0000 }
48905
  },
48906
/* sub.b${S} #${Imm-16-QI},${Dsp-8-u8}[sb] */
48907
  {
48908
    { 0, 0, 0, 0 },
48909
    { { MNEM, OP (S), ' ', '#', OP (IMM_16_QI), ',', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } },
48910
    & ifmt_tst32_b_imm_S_2_S_8_dst32_2_S_8_SB_relative_QI, { 0x2e0000 }
48911
  },
48912
/* sub.b${S} #${Imm-16-QI},${Dsp-8-s8}[fb] */
48913
  {
48914
    { 0, 0, 0, 0 },
48915
    { { MNEM, OP (S), ' ', '#', OP (IMM_16_QI), ',', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } },
48916
    & ifmt_tst32_b_imm_S_2_S_8_dst32_2_S_8_FB_relative_QI, { 0x3e0000 }
48917
  },
48918
/* sub.b${S} #${Imm-24-QI},${Dsp-8-u16} */
48919
  {
48920
    { 0, 0, 0, 0 },
48921
    { { MNEM, OP (S), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_8_U16), 0 } },
48922
    & ifmt_tst32_b_imm_S_2_S_16_dst32_2_S_16_absolute_QI, { 0x1e000000 }
48923
  },
48924
/* sub.b${S} #${Imm-8-QI},r0l */
48925
  {
48926
    { 0, 0, 0, 0 },
48927
    { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'l', 0 } },
48928
    & ifmt_tst32_b_imm_S_2_S_basic_dst32_2_S_R0l_direct_QI, { 0xe00 }
48929
  },
48930
/* sub.l${G} #${Imm-16-SI},$Dst32RnUnprefixedSI */
48931
  {
48932
    { 0, 0, 0, 0 },
48933
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_SI), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
48934
    & ifmt_mov32_l_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_SI, { 0x98310000 }
48935
  },
48936
/* sub.l${G} #${Imm-16-SI},$Dst32AnUnprefixedSI */
48937
  {
48938
    { 0, 0, 0, 0 },
48939
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_SI), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
48940
    & ifmt_mov32_l_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_SI, { 0x90b10000 }
48941
  },
48942
/* sub.l${G} #${Imm-16-SI},[$Dst32AnUnprefixed] */
48943
  {
48944
    { 0, 0, 0, 0 },
48945
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_SI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48946
    & ifmt_mov32_l_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_SI, { 0x90310000 }
48947
  },
48948
/* sub.l${G} #${Imm-24-SI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
48949
  {
48950
    { 0, 0, 0, 0 },
48951
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_SI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48952
    & ifmt_mov32_l_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_SI, { 0x92310000 }
48953
  },
48954
/* sub.l${G} #${Imm-24-SI},${Dsp-16-u8}[sb] */
48955
  {
48956
    { 0, 0, 0, 0 },
48957
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_SI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
48958
    & ifmt_mov32_l_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_SI, { 0x92b10000 }
48959
  },
48960
/* sub.l${G} #${Imm-24-SI},${Dsp-16-s8}[fb] */
48961
  {
48962
    { 0, 0, 0, 0 },
48963
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_SI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
48964
    & ifmt_mov32_l_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_SI, { 0x92f10000 }
48965
  },
48966
/* sub.l${G} #${Imm-32-SI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
48967
  {
48968
    { 0, 0, 0, 0 },
48969
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_SI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48970
    & ifmt_mov32_l_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_SI, { 0x94310000 }
48971
  },
48972
/* sub.l${G} #${Imm-32-SI},${Dsp-16-u16}[sb] */
48973
  {
48974
    { 0, 0, 0, 0 },
48975
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_SI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
48976
    & ifmt_mov32_l_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_SI, { 0x94b10000 }
48977
  },
48978
/* sub.l${G} #${Imm-32-SI},${Dsp-16-s16}[fb] */
48979
  {
48980
    { 0, 0, 0, 0 },
48981
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_SI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
48982
    & ifmt_mov32_l_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_SI, { 0x94f10000 }
48983
  },
48984
/* sub.l${G} #${Imm-32-SI},${Dsp-16-u16} */
48985
  {
48986
    { 0, 0, 0, 0 },
48987
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_SI), ',', OP (DSP_16_U16), 0 } },
48988
    & ifmt_mov32_l_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_SI, { 0x96f10000 }
48989
  },
48990
/* sub.l${G} #${Imm-40-SI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
48991
  {
48992
    { 0, 0, 0, 0 },
48993
    { { MNEM, OP (G), ' ', '#', OP (IMM_40_SI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
48994
    & ifmt_mov32_l_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_SI, { 0x96310000 }
48995
  },
48996
/* sub.l${G} #${Imm-40-SI},${Dsp-16-u24} */
48997
  {
48998
    { 0, 0, 0, 0 },
48999
    { { MNEM, OP (G), ' ', '#', OP (IMM_40_SI), ',', OP (DSP_16_U24), 0 } },
49000
    & ifmt_mov32_l_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_SI, { 0x96b10000 }
49001
  },
49002
/* sub.b${S} ${SrcDst16-r0l-r0h-S-normal} */
49003
  {
49004
    { 0, 0, 0, 0 },
49005
    { { MNEM, OP (S), ' ', OP (SRCDST16_R0L_R0H_S_NORMAL), 0 } },
49006
    & ifmt_or16_b_S_r0l_r0h_srcdst16_r0l_r0h_S_derived, { 0x28 }
49007
  },
49008
/* sub.b${S} ${Dsp-8-u8}[sb],${Dst16RnQI-S} */
49009
  {
49010
    { 0, 0, 0, 0 },
49011
    { { MNEM, OP (S), ' ', OP (DSP_8_U8), '[', 's', 'b', ']', ',', OP (DST16RNQI_S), 0 } },
49012
    & ifmt_or16_b_S_src2_src16_2_S_8_SB_relative_QI, { 0x2900 }
49013
  },
49014
/* sub.b${S} ${Dsp-8-s8}[fb],${Dst16RnQI-S} */
49015
  {
49016
    { 0, 0, 0, 0 },
49017
    { { MNEM, OP (S), ' ', OP (DSP_8_S8), '[', 'f', 'b', ']', ',', OP (DST16RNQI_S), 0 } },
49018
    & ifmt_or16_b_S_src2_src16_2_S_8_FB_relative_QI, { 0x2a00 }
49019
  },
49020
/* sub.b${S} ${Dsp-8-u16},${Dst16RnQI-S} */
49021
  {
49022
    { 0, 0, 0, 0 },
49023
    { { MNEM, OP (S), ' ', OP (DSP_8_U16), ',', OP (DST16RNQI_S), 0 } },
49024
    & ifmt_or16_b_S_src2_src16_2_S_16_absolute_QI, { 0x2b0000 }
49025
  },
49026
/* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
49027
  {
49028
    { 0, 0, 0, 0 },
49029
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
49030
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x990a00 }
49031
  },
49032
/* sub.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */
49033
  {
49034
    { 0, 0, 0, 0 },
49035
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
49036
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x992a00 }
49037
  },
49038
/* sub.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */
49039
  {
49040
    { 0, 0, 0, 0 },
49041
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
49042
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x993a00 }
49043
  },
49044
/* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
49045
  {
49046
    { 0, 0, 0, 0 },
49047
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
49048
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x918a00 }
49049
  },
49050
/* sub.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */
49051
  {
49052
    { 0, 0, 0, 0 },
49053
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
49054
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x91aa00 }
49055
  },
49056
/* sub.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */
49057
  {
49058
    { 0, 0, 0, 0 },
49059
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
49060
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x91ba00 }
49061
  },
49062
/* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
49063
  {
49064
    { 0, 0, 0, 0 },
49065
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49066
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x910a00 }
49067
  },
49068
/* sub.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
49069
  {
49070
    { 0, 0, 0, 0 },
49071
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49072
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x912a00 }
49073
  },
49074
/* sub.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
49075
  {
49076
    { 0, 0, 0, 0 },
49077
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49078
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x913a00 }
49079
  },
49080
/* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
49081
  {
49082
    { 0, 0, 0, 0 },
49083
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49084
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x930a0000 }
49085
  },
49086
/* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
49087
  {
49088
    { 0, 0, 0, 0 },
49089
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49090
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x932a0000 }
49091
  },
49092
/* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
49093
  {
49094
    { 0, 0, 0, 0 },
49095
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49096
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x933a0000 }
49097
  },
49098
/* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
49099
  {
49100
    { 0, 0, 0, 0 },
49101
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49102
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x950a0000 }
49103
  },
49104
/* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
49105
  {
49106
    { 0, 0, 0, 0 },
49107
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49108
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x952a0000 }
49109
  },
49110
/* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
49111
  {
49112
    { 0, 0, 0, 0 },
49113
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49114
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x953a0000 }
49115
  },
49116
/* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
49117
  {
49118
    { 0, 0, 0, 0 },
49119
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49120
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x970a0000 }
49121
  },
49122
/* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
49123
  {
49124
    { 0, 0, 0, 0 },
49125
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49126
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x972a0000 }
49127
  },
49128
/* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
49129
  {
49130
    { 0, 0, 0, 0 },
49131
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49132
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x973a0000 }
49133
  },
49134
/* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
49135
  {
49136
    { 0, 0, 0, 0 },
49137
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
49138
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x938a0000 }
49139
  },
49140
/* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
49141
  {
49142
    { 0, 0, 0, 0 },
49143
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
49144
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93aa0000 }
49145
  },
49146
/* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
49147
  {
49148
    { 0, 0, 0, 0 },
49149
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
49150
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93ba0000 }
49151
  },
49152
/* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
49153
  {
49154
    { 0, 0, 0, 0 },
49155
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
49156
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x958a0000 }
49157
  },
49158
/* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
49159
  {
49160
    { 0, 0, 0, 0 },
49161
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
49162
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95aa0000 }
49163
  },
49164
/* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
49165
  {
49166
    { 0, 0, 0, 0 },
49167
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
49168
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95ba0000 }
49169
  },
49170
/* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
49171
  {
49172
    { 0, 0, 0, 0 },
49173
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
49174
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93ca0000 }
49175
  },
49176
/* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
49177
  {
49178
    { 0, 0, 0, 0 },
49179
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
49180
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93ea0000 }
49181
  },
49182
/* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
49183
  {
49184
    { 0, 0, 0, 0 },
49185
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
49186
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93fa0000 }
49187
  },
49188
/* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
49189
  {
49190
    { 0, 0, 0, 0 },
49191
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
49192
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95ca0000 }
49193
  },
49194
/* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
49195
  {
49196
    { 0, 0, 0, 0 },
49197
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
49198
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95ea0000 }
49199
  },
49200
/* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
49201
  {
49202
    { 0, 0, 0, 0 },
49203
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
49204
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95fa0000 }
49205
  },
49206
/* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
49207
  {
49208
    { 0, 0, 0, 0 },
49209
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
49210
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97ca0000 }
49211
  },
49212
/* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
49213
  {
49214
    { 0, 0, 0, 0 },
49215
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
49216
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97ea0000 }
49217
  },
49218
/* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
49219
  {
49220
    { 0, 0, 0, 0 },
49221
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
49222
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97fa0000 }
49223
  },
49224
/* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
49225
  {
49226
    { 0, 0, 0, 0 },
49227
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
49228
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x978a0000 }
49229
  },
49230
/* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
49231
  {
49232
    { 0, 0, 0, 0 },
49233
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } },
49234
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97aa0000 }
49235
  },
49236
/* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
49237
  {
49238
    { 0, 0, 0, 0 },
49239
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } },
49240
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97ba0000 }
49241
  },
49242
/* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
49243
  {
49244
    { 0, 0, 0, 0 },
49245
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
49246
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa90a0000 }
49247
  },
49248
/* sub.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */
49249
  {
49250
    { 0, 0, 0, 0 },
49251
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
49252
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa92a0000 }
49253
  },
49254
/* sub.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */
49255
  {
49256
    { 0, 0, 0, 0 },
49257
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
49258
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa93a0000 }
49259
  },
49260
/* sub.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */
49261
  {
49262
    { 0, 0, 0, 0 },
49263
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
49264
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb93a0000 }
49265
  },
49266
/* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
49267
  {
49268
    { 0, 0, 0, 0 },
49269
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
49270
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa18a0000 }
49271
  },
49272
/* sub.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */
49273
  {
49274
    { 0, 0, 0, 0 },
49275
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
49276
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1aa0000 }
49277
  },
49278
/* sub.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */
49279
  {
49280
    { 0, 0, 0, 0 },
49281
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
49282
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1ba0000 }
49283
  },
49284
/* sub.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */
49285
  {
49286
    { 0, 0, 0, 0 },
49287
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
49288
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1ba0000 }
49289
  },
49290
/* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
49291
  {
49292
    { 0, 0, 0, 0 },
49293
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49294
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa10a0000 }
49295
  },
49296
/* sub.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
49297
  {
49298
    { 0, 0, 0, 0 },
49299
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49300
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa12a0000 }
49301
  },
49302
/* sub.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
49303
  {
49304
    { 0, 0, 0, 0 },
49305
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49306
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa13a0000 }
49307
  },
49308
/* sub.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
49309
  {
49310
    { 0, 0, 0, 0 },
49311
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49312
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb13a0000 }
49313
  },
49314
/* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
49315
  {
49316
    { 0, 0, 0, 0 },
49317
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49318
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa30a0000 }
49319
  },
49320
/* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
49321
  {
49322
    { 0, 0, 0, 0 },
49323
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49324
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa32a0000 }
49325
  },
49326
/* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
49327
  {
49328
    { 0, 0, 0, 0 },
49329
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49330
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa33a0000 }
49331
  },
49332
/* sub.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
49333
  {
49334
    { 0, 0, 0, 0 },
49335
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49336
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xb33a0000 }
49337
  },
49338
/* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
49339
  {
49340
    { 0, 0, 0, 0 },
49341
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49342
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa50a0000 }
49343
  },
49344
/* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
49345
  {
49346
    { 0, 0, 0, 0 },
49347
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49348
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa52a0000 }
49349
  },
49350
/* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
49351
  {
49352
    { 0, 0, 0, 0 },
49353
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49354
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa53a0000 }
49355
  },
49356
/* sub.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
49357
  {
49358
    { 0, 0, 0, 0 },
49359
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49360
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xb53a0000 }
49361
  },
49362
/* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
49363
  {
49364
    { 0, 0, 0, 0 },
49365
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49366
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa70a0000 }
49367
  },
49368
/* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
49369
  {
49370
    { 0, 0, 0, 0 },
49371
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49372
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa72a0000 }
49373
  },
49374
/* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
49375
  {
49376
    { 0, 0, 0, 0 },
49377
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49378
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa73a0000 }
49379
  },
49380
/* sub.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
49381
  {
49382
    { 0, 0, 0, 0 },
49383
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49384
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xb73a0000 }
49385
  },
49386
/* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
49387
  {
49388
    { 0, 0, 0, 0 },
49389
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
49390
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa38a0000 }
49391
  },
49392
/* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
49393
  {
49394
    { 0, 0, 0, 0 },
49395
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
49396
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3aa0000 }
49397
  },
49398
/* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
49399
  {
49400
    { 0, 0, 0, 0 },
49401
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
49402
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3ba0000 }
49403
  },
49404
/* sub.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
49405
  {
49406
    { 0, 0, 0, 0 },
49407
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
49408
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xb3ba0000 }
49409
  },
49410
/* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
49411
  {
49412
    { 0, 0, 0, 0 },
49413
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
49414
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa58a0000 }
49415
  },
49416
/* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
49417
  {
49418
    { 0, 0, 0, 0 },
49419
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
49420
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5aa0000 }
49421
  },
49422
/* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
49423
  {
49424
    { 0, 0, 0, 0 },
49425
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
49426
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5ba0000 }
49427
  },
49428
/* sub.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
49429
  {
49430
    { 0, 0, 0, 0 },
49431
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
49432
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xb5ba0000 }
49433
  },
49434
/* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
49435
  {
49436
    { 0, 0, 0, 0 },
49437
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
49438
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3ca0000 }
49439
  },
49440
/* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
49441
  {
49442
    { 0, 0, 0, 0 },
49443
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
49444
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3ea0000 }
49445
  },
49446
/* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
49447
  {
49448
    { 0, 0, 0, 0 },
49449
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
49450
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3fa0000 }
49451
  },
49452
/* sub.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
49453
  {
49454
    { 0, 0, 0, 0 },
49455
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
49456
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xb3fa0000 }
49457
  },
49458
/* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
49459
  {
49460
    { 0, 0, 0, 0 },
49461
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
49462
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5ca0000 }
49463
  },
49464
/* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
49465
  {
49466
    { 0, 0, 0, 0 },
49467
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
49468
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5ea0000 }
49469
  },
49470
/* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
49471
  {
49472
    { 0, 0, 0, 0 },
49473
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
49474
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5fa0000 }
49475
  },
49476
/* sub.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
49477
  {
49478
    { 0, 0, 0, 0 },
49479
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
49480
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xb5fa0000 }
49481
  },
49482
/* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
49483
  {
49484
    { 0, 0, 0, 0 },
49485
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
49486
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7ca0000 }
49487
  },
49488
/* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
49489
  {
49490
    { 0, 0, 0, 0 },
49491
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
49492
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7ea0000 }
49493
  },
49494
/* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
49495
  {
49496
    { 0, 0, 0, 0 },
49497
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
49498
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7fa0000 }
49499
  },
49500
/* sub.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
49501
  {
49502
    { 0, 0, 0, 0 },
49503
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
49504
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xb7fa0000 }
49505
  },
49506
/* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
49507
  {
49508
    { 0, 0, 0, 0 },
49509
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
49510
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa78a0000 }
49511
  },
49512
/* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
49513
  {
49514
    { 0, 0, 0, 0 },
49515
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
49516
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7aa0000 }
49517
  },
49518
/* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
49519
  {
49520
    { 0, 0, 0, 0 },
49521
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
49522
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7ba0000 }
49523
  },
49524
/* sub.w${G} ${Dsp-16-u16},${Dsp-32-u24} */
49525
  {
49526
    { 0, 0, 0, 0 },
49527
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } },
49528
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xb7ba0000 }
49529
  },
49530
/* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
49531
  {
49532
    { 0, 0, 0, 0 },
49533
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
49534
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb90a0000 }
49535
  },
49536
/* sub.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */
49537
  {
49538
    { 0, 0, 0, 0 },
49539
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
49540
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb92a0000 }
49541
  },
49542
/* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
49543
  {
49544
    { 0, 0, 0, 0 },
49545
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
49546
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb18a0000 }
49547
  },
49548
/* sub.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */
49549
  {
49550
    { 0, 0, 0, 0 },
49551
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
49552
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1aa0000 }
49553
  },
49554
/* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
49555
  {
49556
    { 0, 0, 0, 0 },
49557
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49558
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb10a0000 }
49559
  },
49560
/* sub.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
49561
  {
49562
    { 0, 0, 0, 0 },
49563
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49564
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb12a0000 }
49565
  },
49566
/* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
49567
  {
49568
    { 0, 0, 0, 0 },
49569
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49570
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_An_relative_Unprefixed_HI, { 0xb30a0000 }
49571
  },
49572
/* sub.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
49573
  {
49574
    { 0, 0, 0, 0 },
49575
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49576
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_An_relative_Unprefixed_HI, { 0xb32a0000 }
49577
  },
49578
/* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
49579
  {
49580
    { 0, 0, 0, 0 },
49581
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49582
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_An_relative_Unprefixed_HI, { 0xb50a0000 }
49583
  },
49584
/* sub.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
49585
  {
49586
    { 0, 0, 0, 0 },
49587
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49588
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_An_relative_Unprefixed_HI, { 0xb52a0000 }
49589
  },
49590
/* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
49591
  {
49592
    { 0, 0, 0, 0 },
49593
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49594
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_24_An_relative_Unprefixed_HI, { 0xb70a0000 }
49595
  },
49596
/* sub.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
49597
  {
49598
    { 0, 0, 0, 0 },
49599
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49600
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_24_An_relative_Unprefixed_HI, { 0xb72a0000 }
49601
  },
49602
/* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
49603
  {
49604
    { 0, 0, 0, 0 },
49605
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
49606
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_SB_relative_Unprefixed_HI, { 0xb38a0000 }
49607
  },
49608
/* sub.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
49609
  {
49610
    { 0, 0, 0, 0 },
49611
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
49612
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_SB_relative_Unprefixed_HI, { 0xb3aa0000 }
49613
  },
49614
/* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
49615
  {
49616
    { 0, 0, 0, 0 },
49617
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
49618
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_SB_relative_Unprefixed_HI, { 0xb58a0000 }
49619
  },
49620
/* sub.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
49621
  {
49622
    { 0, 0, 0, 0 },
49623
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
49624
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_SB_relative_Unprefixed_HI, { 0xb5aa0000 }
49625
  },
49626
/* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
49627
  {
49628
    { 0, 0, 0, 0 },
49629
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
49630
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_FB_relative_Unprefixed_HI, { 0xb3ca0000 }
49631
  },
49632
/* sub.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
49633
  {
49634
    { 0, 0, 0, 0 },
49635
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
49636
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_FB_relative_Unprefixed_HI, { 0xb3ea0000 }
49637
  },
49638
/* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
49639
  {
49640
    { 0, 0, 0, 0 },
49641
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
49642
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_FB_relative_Unprefixed_HI, { 0xb5ca0000 }
49643
  },
49644
/* sub.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
49645
  {
49646
    { 0, 0, 0, 0 },
49647
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
49648
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_FB_relative_Unprefixed_HI, { 0xb5ea0000 }
49649
  },
49650
/* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
49651
  {
49652
    { 0, 0, 0, 0 },
49653
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
49654
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_absolute_Unprefixed_HI, { 0xb7ca0000 }
49655
  },
49656
/* sub.w${G} ${Dsp-16-u24},${Dsp-40-u16} */
49657
  {
49658
    { 0, 0, 0, 0 },
49659
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } },
49660
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_absolute_Unprefixed_HI, { 0xb7ea0000 }
49661
  },
49662
/* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
49663
  {
49664
    { 0, 0, 0, 0 },
49665
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
49666
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_24_absolute_Unprefixed_HI, { 0xb78a0000 }
49667
  },
49668
/* sub.w${G} ${Dsp-16-u24},${Dsp-40-u24} */
49669
  {
49670
    { 0, 0, 0, 0 },
49671
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } },
49672
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_24_absolute_Unprefixed_HI, { 0xb7aa0000 }
49673
  },
49674
/* sub.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */
49675
  {
49676
    { 0, 0, 0, 0 },
49677
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
49678
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xc90a }
49679
  },
49680
/* sub.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */
49681
  {
49682
    { 0, 0, 0, 0 },
49683
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
49684
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x892a }
49685
  },
49686
/* sub.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
49687
  {
49688
    { 0, 0, 0, 0 },
49689
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
49690
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x890a }
49691
  },
49692
/* sub.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */
49693
  {
49694
    { 0, 0, 0, 0 },
49695
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
49696
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xc18a }
49697
  },
49698
/* sub.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */
49699
  {
49700
    { 0, 0, 0, 0 },
49701
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
49702
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x81aa }
49703
  },
49704
/* sub.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
49705
  {
49706
    { 0, 0, 0, 0 },
49707
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
49708
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x818a }
49709
  },
49710
/* sub.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */
49711
  {
49712
    { 0, 0, 0, 0 },
49713
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49714
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xc10a }
49715
  },
49716
/* sub.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */
49717
  {
49718
    { 0, 0, 0, 0 },
49719
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49720
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x812a }
49721
  },
49722
/* sub.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
49723
  {
49724
    { 0, 0, 0, 0 },
49725
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49726
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x810a }
49727
  },
49728
/* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
49729
  {
49730
    { 0, 0, 0, 0 },
49731
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49732
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0xc30a00 }
49733
  },
49734
/* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
49735
  {
49736
    { 0, 0, 0, 0 },
49737
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49738
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0x832a00 }
49739
  },
49740
/* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
49741
  {
49742
    { 0, 0, 0, 0 },
49743
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49744
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0x830a00 }
49745
  },
49746
/* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
49747
  {
49748
    { 0, 0, 0, 0 },
49749
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49750
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0xc50a0000 }
49751
  },
49752
/* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
49753
  {
49754
    { 0, 0, 0, 0 },
49755
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49756
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0x852a0000 }
49757
  },
49758
/* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
49759
  {
49760
    { 0, 0, 0, 0 },
49761
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49762
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0x850a0000 }
49763
  },
49764
/* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
49765
  {
49766
    { 0, 0, 0, 0 },
49767
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49768
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0xc70a0000 }
49769
  },
49770
/* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
49771
  {
49772
    { 0, 0, 0, 0 },
49773
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49774
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0x872a0000 }
49775
  },
49776
/* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
49777
  {
49778
    { 0, 0, 0, 0 },
49779
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49780
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0x870a0000 }
49781
  },
49782
/* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */
49783
  {
49784
    { 0, 0, 0, 0 },
49785
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
49786
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0xc38a00 }
49787
  },
49788
/* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */
49789
  {
49790
    { 0, 0, 0, 0 },
49791
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
49792
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0x83aa00 }
49793
  },
49794
/* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
49795
  {
49796
    { 0, 0, 0, 0 },
49797
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
49798
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0x838a00 }
49799
  },
49800
/* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */
49801
  {
49802
    { 0, 0, 0, 0 },
49803
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
49804
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0xc58a0000 }
49805
  },
49806
/* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */
49807
  {
49808
    { 0, 0, 0, 0 },
49809
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
49810
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0x85aa0000 }
49811
  },
49812
/* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
49813
  {
49814
    { 0, 0, 0, 0 },
49815
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
49816
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0x858a0000 }
49817
  },
49818
/* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */
49819
  {
49820
    { 0, 0, 0, 0 },
49821
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
49822
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0xc3ca00 }
49823
  },
49824
/* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */
49825
  {
49826
    { 0, 0, 0, 0 },
49827
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
49828
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83ea00 }
49829
  },
49830
/* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
49831
  {
49832
    { 0, 0, 0, 0 },
49833
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
49834
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83ca00 }
49835
  },
49836
/* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */
49837
  {
49838
    { 0, 0, 0, 0 },
49839
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
49840
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0xc5ca0000 }
49841
  },
49842
/* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */
49843
  {
49844
    { 0, 0, 0, 0 },
49845
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
49846
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85ea0000 }
49847
  },
49848
/* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
49849
  {
49850
    { 0, 0, 0, 0 },
49851
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
49852
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85ca0000 }
49853
  },
49854
/* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */
49855
  {
49856
    { 0, 0, 0, 0 },
49857
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), 0 } },
49858
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0xc7ca0000 }
49859
  },
49860
/* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */
49861
  {
49862
    { 0, 0, 0, 0 },
49863
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), 0 } },
49864
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0x87ea0000 }
49865
  },
49866
/* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
49867
  {
49868
    { 0, 0, 0, 0 },
49869
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } },
49870
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0x87ca0000 }
49871
  },
49872
/* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */
49873
  {
49874
    { 0, 0, 0, 0 },
49875
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U24), 0 } },
49876
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0xc78a0000 }
49877
  },
49878
/* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */
49879
  {
49880
    { 0, 0, 0, 0 },
49881
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U24), 0 } },
49882
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0x87aa0000 }
49883
  },
49884
/* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
49885
  {
49886
    { 0, 0, 0, 0 },
49887
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } },
49888
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0x878a0000 }
49889
  },
49890
/* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
49891
  {
49892
    { 0, 0, 0, 0 },
49893
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
49894
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x980a00 }
49895
  },
49896
/* sub.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */
49897
  {
49898
    { 0, 0, 0, 0 },
49899
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
49900
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x982a00 }
49901
  },
49902
/* sub.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */
49903
  {
49904
    { 0, 0, 0, 0 },
49905
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
49906
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x983a00 }
49907
  },
49908
/* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
49909
  {
49910
    { 0, 0, 0, 0 },
49911
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
49912
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x908a00 }
49913
  },
49914
/* sub.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */
49915
  {
49916
    { 0, 0, 0, 0 },
49917
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
49918
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x90aa00 }
49919
  },
49920
/* sub.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */
49921
  {
49922
    { 0, 0, 0, 0 },
49923
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
49924
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x90ba00 }
49925
  },
49926
/* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
49927
  {
49928
    { 0, 0, 0, 0 },
49929
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49930
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x900a00 }
49931
  },
49932
/* sub.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
49933
  {
49934
    { 0, 0, 0, 0 },
49935
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49936
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x902a00 }
49937
  },
49938
/* sub.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
49939
  {
49940
    { 0, 0, 0, 0 },
49941
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49942
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x903a00 }
49943
  },
49944
/* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
49945
  {
49946
    { 0, 0, 0, 0 },
49947
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49948
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x920a0000 }
49949
  },
49950
/* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
49951
  {
49952
    { 0, 0, 0, 0 },
49953
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49954
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x922a0000 }
49955
  },
49956
/* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
49957
  {
49958
    { 0, 0, 0, 0 },
49959
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49960
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x923a0000 }
49961
  },
49962
/* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
49963
  {
49964
    { 0, 0, 0, 0 },
49965
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49966
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x940a0000 }
49967
  },
49968
/* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
49969
  {
49970
    { 0, 0, 0, 0 },
49971
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49972
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x942a0000 }
49973
  },
49974
/* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
49975
  {
49976
    { 0, 0, 0, 0 },
49977
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49978
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x943a0000 }
49979
  },
49980
/* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
49981
  {
49982
    { 0, 0, 0, 0 },
49983
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49984
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x960a0000 }
49985
  },
49986
/* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
49987
  {
49988
    { 0, 0, 0, 0 },
49989
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49990
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x962a0000 }
49991
  },
49992
/* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
49993
  {
49994
    { 0, 0, 0, 0 },
49995
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
49996
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x963a0000 }
49997
  },
49998
/* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
49999
  {
50000
    { 0, 0, 0, 0 },
50001
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
50002
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x928a0000 }
50003
  },
50004
/* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
50005
  {
50006
    { 0, 0, 0, 0 },
50007
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
50008
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92aa0000 }
50009
  },
50010
/* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
50011
  {
50012
    { 0, 0, 0, 0 },
50013
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
50014
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92ba0000 }
50015
  },
50016
/* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
50017
  {
50018
    { 0, 0, 0, 0 },
50019
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
50020
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x948a0000 }
50021
  },
50022
/* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
50023
  {
50024
    { 0, 0, 0, 0 },
50025
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
50026
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94aa0000 }
50027
  },
50028
/* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
50029
  {
50030
    { 0, 0, 0, 0 },
50031
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
50032
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94ba0000 }
50033
  },
50034
/* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
50035
  {
50036
    { 0, 0, 0, 0 },
50037
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
50038
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92ca0000 }
50039
  },
50040
/* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
50041
  {
50042
    { 0, 0, 0, 0 },
50043
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
50044
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92ea0000 }
50045
  },
50046
/* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
50047
  {
50048
    { 0, 0, 0, 0 },
50049
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
50050
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92fa0000 }
50051
  },
50052
/* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
50053
  {
50054
    { 0, 0, 0, 0 },
50055
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
50056
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94ca0000 }
50057
  },
50058
/* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
50059
  {
50060
    { 0, 0, 0, 0 },
50061
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
50062
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94ea0000 }
50063
  },
50064
/* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
50065
  {
50066
    { 0, 0, 0, 0 },
50067
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
50068
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94fa0000 }
50069
  },
50070
/* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
50071
  {
50072
    { 0, 0, 0, 0 },
50073
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
50074
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96ca0000 }
50075
  },
50076
/* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
50077
  {
50078
    { 0, 0, 0, 0 },
50079
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
50080
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96ea0000 }
50081
  },
50082
/* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
50083
  {
50084
    { 0, 0, 0, 0 },
50085
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
50086
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96fa0000 }
50087
  },
50088
/* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
50089
  {
50090
    { 0, 0, 0, 0 },
50091
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
50092
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x968a0000 }
50093
  },
50094
/* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
50095
  {
50096
    { 0, 0, 0, 0 },
50097
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } },
50098
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96aa0000 }
50099
  },
50100
/* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
50101
  {
50102
    { 0, 0, 0, 0 },
50103
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } },
50104
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96ba0000 }
50105
  },
50106
/* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
50107
  {
50108
    { 0, 0, 0, 0 },
50109
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
50110
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa80a0000 }
50111
  },
50112
/* sub.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */
50113
  {
50114
    { 0, 0, 0, 0 },
50115
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
50116
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa82a0000 }
50117
  },
50118
/* sub.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */
50119
  {
50120
    { 0, 0, 0, 0 },
50121
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
50122
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa83a0000 }
50123
  },
50124
/* sub.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */
50125
  {
50126
    { 0, 0, 0, 0 },
50127
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
50128
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb83a0000 }
50129
  },
50130
/* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
50131
  {
50132
    { 0, 0, 0, 0 },
50133
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
50134
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa08a0000 }
50135
  },
50136
/* sub.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */
50137
  {
50138
    { 0, 0, 0, 0 },
50139
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
50140
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0aa0000 }
50141
  },
50142
/* sub.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */
50143
  {
50144
    { 0, 0, 0, 0 },
50145
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
50146
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0ba0000 }
50147
  },
50148
/* sub.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */
50149
  {
50150
    { 0, 0, 0, 0 },
50151
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
50152
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0ba0000 }
50153
  },
50154
/* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
50155
  {
50156
    { 0, 0, 0, 0 },
50157
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
50158
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa00a0000 }
50159
  },
50160
/* sub.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
50161
  {
50162
    { 0, 0, 0, 0 },
50163
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
50164
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa02a0000 }
50165
  },
50166
/* sub.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
50167
  {
50168
    { 0, 0, 0, 0 },
50169
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
50170
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa03a0000 }
50171
  },
50172
/* sub.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
50173
  {
50174
    { 0, 0, 0, 0 },
50175
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
50176
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb03a0000 }
50177
  },
50178
/* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
50179
  {
50180
    { 0, 0, 0, 0 },
50181
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
50182
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa20a0000 }
50183
  },
50184
/* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
50185
  {
50186
    { 0, 0, 0, 0 },
50187
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
50188
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa22a0000 }
50189
  },
50190
/* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
50191
  {
50192
    { 0, 0, 0, 0 },
50193
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
50194
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa23a0000 }
50195
  },
50196
/* sub.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
50197
  {
50198
    { 0, 0, 0, 0 },
50199
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
50200
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xb23a0000 }
50201
  },
50202
/* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
50203
  {
50204
    { 0, 0, 0, 0 },
50205
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
50206
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa40a0000 }
50207
  },
50208
/* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
50209
  {
50210
    { 0, 0, 0, 0 },
50211
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
50212
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa42a0000 }
50213
  },
50214
/* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
50215
  {
50216
    { 0, 0, 0, 0 },
50217
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
50218
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa43a0000 }
50219
  },
50220
/* sub.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
50221
  {
50222
    { 0, 0, 0, 0 },
50223
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
50224
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xb43a0000 }
50225
  },
50226
/* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
50227
  {
50228
    { 0, 0, 0, 0 },
50229
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
50230
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa60a0000 }
50231
  },
50232
/* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
50233
  {
50234
    { 0, 0, 0, 0 },
50235
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
50236
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa62a0000 }
50237
  },
50238
/* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
50239
  {
50240
    { 0, 0, 0, 0 },
50241
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
50242
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa63a0000 }
50243
  },
50244
/* sub.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
50245
  {
50246
    { 0, 0, 0, 0 },
50247
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
50248
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xb63a0000 }
50249
  },
50250
/* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
50251
  {
50252
    { 0, 0, 0, 0 },
50253
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
50254
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa28a0000 }
50255
  },
50256
/* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
50257
  {
50258
    { 0, 0, 0, 0 },
50259
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
50260
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2aa0000 }
50261
  },
50262
/* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
50263
  {
50264
    { 0, 0, 0, 0 },
50265
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
50266
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2ba0000 }
50267
  },
50268
/* sub.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
50269
  {
50270
    { 0, 0, 0, 0 },
50271
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
50272
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xb2ba0000 }
50273
  },
50274
/* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
50275
  {
50276
    { 0, 0, 0, 0 },
50277
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
50278
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa48a0000 }
50279
  },
50280
/* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
50281
  {
50282
    { 0, 0, 0, 0 },
50283
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
50284
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4aa0000 }
50285
  },
50286
/* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
50287
  {
50288
    { 0, 0, 0, 0 },
50289
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
50290
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4ba0000 }
50291
  },
50292
/* sub.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
50293
  {
50294
    { 0, 0, 0, 0 },
50295
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
50296
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xb4ba0000 }
50297
  },
50298
/* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
50299
  {
50300
    { 0, 0, 0, 0 },
50301
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
50302
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2ca0000 }
50303
  },
50304
/* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
50305
  {
50306
    { 0, 0, 0, 0 },
50307
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
50308
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2ea0000 }
50309
  },
50310
/* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
50311
  {
50312
    { 0, 0, 0, 0 },
50313
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
50314
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2fa0000 }
50315
  },
50316
/* sub.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
50317
  {
50318
    { 0, 0, 0, 0 },
50319
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
50320
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xb2fa0000 }
50321
  },
50322
/* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
50323
  {
50324
    { 0, 0, 0, 0 },
50325
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
50326
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4ca0000 }
50327
  },
50328
/* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
50329
  {
50330
    { 0, 0, 0, 0 },
50331
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
50332
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4ea0000 }
50333
  },
50334
/* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
50335
  {
50336
    { 0, 0, 0, 0 },
50337
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
50338
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4fa0000 }
50339
  },
50340
/* sub.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
50341
  {
50342
    { 0, 0, 0, 0 },
50343
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
50344
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xb4fa0000 }
50345
  },
50346
/* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
50347
  {
50348
    { 0, 0, 0, 0 },
50349
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
50350
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6ca0000 }
50351
  },
50352
/* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
50353
  {
50354
    { 0, 0, 0, 0 },
50355
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
50356
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6ea0000 }
50357
  },
50358
/* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
50359
  {
50360
    { 0, 0, 0, 0 },
50361
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
50362
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6fa0000 }
50363
  },
50364
/* sub.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
50365
  {
50366
    { 0, 0, 0, 0 },
50367
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
50368
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xb6fa0000 }
50369
  },
50370
/* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
50371
  {
50372
    { 0, 0, 0, 0 },
50373
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
50374
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa68a0000 }
50375
  },
50376
/* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
50377
  {
50378
    { 0, 0, 0, 0 },
50379
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
50380
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6aa0000 }
50381
  },
50382
/* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
50383
  {
50384
    { 0, 0, 0, 0 },
50385
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
50386
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6ba0000 }
50387
  },
50388
/* sub.b${G} ${Dsp-16-u16},${Dsp-32-u24} */
50389
  {
50390
    { 0, 0, 0, 0 },
50391
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } },
50392
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xb6ba0000 }
50393
  },
50394
/* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
50395
  {
50396
    { 0, 0, 0, 0 },
50397
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
50398
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb80a0000 }
50399
  },
50400
/* sub.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */
50401
  {
50402
    { 0, 0, 0, 0 },
50403
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
50404
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb82a0000 }
50405
  },
50406
/* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
50407
  {
50408
    { 0, 0, 0, 0 },
50409
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
50410
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb08a0000 }
50411
  },
50412
/* sub.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */
50413
  {
50414
    { 0, 0, 0, 0 },
50415
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
50416
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0aa0000 }
50417
  },
50418
/* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
50419
  {
50420
    { 0, 0, 0, 0 },
50421
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
50422
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb00a0000 }
50423
  },
50424
/* sub.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
50425
  {
50426
    { 0, 0, 0, 0 },
50427
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
50428
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb02a0000 }
50429
  },
50430
/* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
50431
  {
50432
    { 0, 0, 0, 0 },
50433
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
50434
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_QI, { 0xb20a0000 }
50435
  },
50436
/* sub.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
50437
  {
50438
    { 0, 0, 0, 0 },
50439
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
50440
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_QI, { 0xb22a0000 }
50441
  },
50442
/* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
50443
  {
50444
    { 0, 0, 0, 0 },
50445
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
50446
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_QI, { 0xb40a0000 }
50447
  },
50448
/* sub.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
50449
  {
50450
    { 0, 0, 0, 0 },
50451
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
50452
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_QI, { 0xb42a0000 }
50453
  },
50454
/* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
50455
  {
50456
    { 0, 0, 0, 0 },
50457
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
50458
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_QI, { 0xb60a0000 }
50459
  },
50460
/* sub.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
50461
  {
50462
    { 0, 0, 0, 0 },
50463
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
50464
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_QI, { 0xb62a0000 }
50465
  },
50466
/* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
50467
  {
50468
    { 0, 0, 0, 0 },
50469
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
50470
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_QI, { 0xb28a0000 }
50471
  },
50472
/* sub.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
50473
  {
50474
    { 0, 0, 0, 0 },
50475
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
50476
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_QI, { 0xb2aa0000 }
50477
  },
50478
/* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
50479
  {
50480
    { 0, 0, 0, 0 },
50481
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
50482
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_QI, { 0xb48a0000 }
50483
  },
50484
/* sub.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
50485
  {
50486
    { 0, 0, 0, 0 },
50487
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
50488
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_QI, { 0xb4aa0000 }
50489
  },
50490
/* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
50491
  {
50492
    { 0, 0, 0, 0 },
50493
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
50494
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_QI, { 0xb2ca0000 }
50495
  },
50496
/* sub.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
50497
  {
50498
    { 0, 0, 0, 0 },
50499
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
50500
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_QI, { 0xb2ea0000 }
50501
  },
50502
/* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
50503
  {
50504
    { 0, 0, 0, 0 },
50505
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
50506
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_QI, { 0xb4ca0000 }
50507
  },
50508
/* sub.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
50509
  {
50510
    { 0, 0, 0, 0 },
50511
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
50512
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_QI, { 0xb4ea0000 }
50513
  },
50514
/* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
50515
  {
50516
    { 0, 0, 0, 0 },
50517
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
50518
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_QI, { 0xb6ca0000 }
50519
  },
50520
/* sub.b${G} ${Dsp-16-u24},${Dsp-40-u16} */
50521
  {
50522
    { 0, 0, 0, 0 },
50523
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } },
50524
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_QI, { 0xb6ea0000 }
50525
  },
50526
/* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
50527
  {
50528
    { 0, 0, 0, 0 },
50529
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
50530
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_QI, { 0xb68a0000 }
50531
  },
50532
/* sub.b${G} ${Dsp-16-u24},${Dsp-40-u24} */
50533
  {
50534
    { 0, 0, 0, 0 },
50535
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } },
50536
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_QI, { 0xb6aa0000 }
50537
  },
50538
/* sub.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */
50539
  {
50540
    { 0, 0, 0, 0 },
50541
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
50542
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xc80a }
50543
  },
50544
/* sub.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */
50545
  {
50546
    { 0, 0, 0, 0 },
50547
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
50548
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x882a }
50549
  },
50550
/* sub.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
50551
  {
50552
    { 0, 0, 0, 0 },
50553
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
50554
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x880a }
50555
  },
50556
/* sub.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */
50557
  {
50558
    { 0, 0, 0, 0 },
50559
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
50560
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xc08a }
50561
  },
50562
/* sub.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */
50563
  {
50564
    { 0, 0, 0, 0 },
50565
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
50566
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x80aa }
50567
  },
50568
/* sub.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
50569
  {
50570
    { 0, 0, 0, 0 },
50571
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
50572
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x808a }
50573
  },
50574
/* sub.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */
50575
  {
50576
    { 0, 0, 0, 0 },
50577
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
50578
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xc00a }
50579
  },
50580
/* sub.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */
50581
  {
50582
    { 0, 0, 0, 0 },
50583
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
50584
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x802a }
50585
  },
50586
/* sub.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
50587
  {
50588
    { 0, 0, 0, 0 },
50589
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
50590
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x800a }
50591
  },
50592
/* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
50593
  {
50594
    { 0, 0, 0, 0 },
50595
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
50596
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0xc20a00 }
50597
  },
50598
/* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
50599
  {
50600
    { 0, 0, 0, 0 },
50601
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
50602
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0x822a00 }
50603
  },
50604
/* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
50605
  {
50606
    { 0, 0, 0, 0 },
50607
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
50608
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0x820a00 }
50609
  },
50610
/* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
50611
  {
50612
    { 0, 0, 0, 0 },
50613
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
50614
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0xc40a0000 }
50615
  },
50616
/* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
50617
  {
50618
    { 0, 0, 0, 0 },
50619
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
50620
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0x842a0000 }
50621
  },
50622
/* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
50623
  {
50624
    { 0, 0, 0, 0 },
50625
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
50626
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0x840a0000 }
50627
  },
50628
/* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
50629
  {
50630
    { 0, 0, 0, 0 },
50631
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
50632
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0xc60a0000 }
50633
  },
50634
/* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
50635
  {
50636
    { 0, 0, 0, 0 },
50637
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
50638
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0x862a0000 }
50639
  },
50640
/* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
50641
  {
50642
    { 0, 0, 0, 0 },
50643
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
50644
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0x860a0000 }
50645
  },
50646
/* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */
50647
  {
50648
    { 0, 0, 0, 0 },
50649
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
50650
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0xc28a00 }
50651
  },
50652
/* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */
50653
  {
50654
    { 0, 0, 0, 0 },
50655
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
50656
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0x82aa00 }
50657
  },
50658
/* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
50659
  {
50660
    { 0, 0, 0, 0 },
50661
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
50662
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0x828a00 }
50663
  },
50664
/* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */
50665
  {
50666
    { 0, 0, 0, 0 },
50667
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
50668
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0xc48a0000 }
50669
  },
50670
/* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */
50671
  {
50672
    { 0, 0, 0, 0 },
50673
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
50674
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0x84aa0000 }
50675
  },
50676
/* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
50677
  {
50678
    { 0, 0, 0, 0 },
50679
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
50680
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0x848a0000 }
50681
  },
50682
/* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */
50683
  {
50684
    { 0, 0, 0, 0 },
50685
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
50686
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0xc2ca00 }
50687
  },
50688
/* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */
50689
  {
50690
    { 0, 0, 0, 0 },
50691
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
50692
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82ea00 }
50693
  },
50694
/* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
50695
  {
50696
    { 0, 0, 0, 0 },
50697
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
50698
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82ca00 }
50699
  },
50700
/* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */
50701
  {
50702
    { 0, 0, 0, 0 },
50703
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
50704
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0xc4ca0000 }
50705
  },
50706
/* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */
50707
  {
50708
    { 0, 0, 0, 0 },
50709
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
50710
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84ea0000 }
50711
  },
50712
/* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
50713
  {
50714
    { 0, 0, 0, 0 },
50715
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
50716
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84ca0000 }
50717
  },
50718
/* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */
50719
  {
50720
    { 0, 0, 0, 0 },
50721
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), 0 } },
50722
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0xc6ca0000 }
50723
  },
50724
/* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */
50725
  {
50726
    { 0, 0, 0, 0 },
50727
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), 0 } },
50728
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0x86ea0000 }
50729
  },
50730
/* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
50731
  {
50732
    { 0, 0, 0, 0 },
50733
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } },
50734
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0x86ca0000 }
50735
  },
50736
/* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */
50737
  {
50738
    { 0, 0, 0, 0 },
50739
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U24), 0 } },
50740
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0xc68a0000 }
50741
  },
50742
/* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */
50743
  {
50744
    { 0, 0, 0, 0 },
50745
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U24), 0 } },
50746
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0x86aa0000 }
50747
  },
50748
/* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
50749
  {
50750
    { 0, 0, 0, 0 },
50751
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } },
50752
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0x868a0000 }
50753
  },
50754
/* sub.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
50755
  {
50756
    { 0, 0, 0, 0 },
50757
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } },
50758
    & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_Rn_direct_HI, { 0xa98000 }
50759
  },
50760
/* sub.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */
50761
  {
50762
    { 0, 0, 0, 0 },
50763
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } },
50764
    & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_Rn_direct_HI, { 0xa9a000 }
50765
  },
50766
/* sub.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */
50767
  {
50768
    { 0, 0, 0, 0 },
50769
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNHI), 0 } },
50770
    & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_Rn_direct_HI, { 0xa9b000 }
50771
  },
50772
/* sub.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
50773
  {
50774
    { 0, 0, 0, 0 },
50775
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } },
50776
    & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_direct_HI, { 0xa98400 }
50777
  },
50778
/* sub.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */
50779
  {
50780
    { 0, 0, 0, 0 },
50781
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } },
50782
    & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_direct_HI, { 0xa9a400 }
50783
  },
50784
/* sub.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */
50785
  {
50786
    { 0, 0, 0, 0 },
50787
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANHI), 0 } },
50788
    & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_direct_HI, { 0xa9b400 }
50789
  },
50790
/* sub.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
50791
  {
50792
    { 0, 0, 0, 0 },
50793
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
50794
    & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_indirect_HI, { 0xa98600 }
50795
  },
50796
/* sub.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */
50797
  {
50798
    { 0, 0, 0, 0 },
50799
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
50800
    & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_indirect_HI, { 0xa9a600 }
50801
  },
50802
/* sub.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */
50803
  {
50804
    { 0, 0, 0, 0 },
50805
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
50806
    & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_indirect_HI, { 0xa9b600 }
50807
  },
50808
/* sub.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
50809
  {
50810
    { 0, 0, 0, 0 },
50811
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
50812
    & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_An_relative_HI, { 0xa9880000 }
50813
  },
50814
/* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
50815
  {
50816
    { 0, 0, 0, 0 },
50817
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
50818
    & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_An_relative_HI, { 0xa9a80000 }
50819
  },
50820
/* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
50821
  {
50822
    { 0, 0, 0, 0 },
50823
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
50824
    & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_An_relative_HI, { 0xa9b80000 }
50825
  },
50826
/* sub.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
50827
  {
50828
    { 0, 0, 0, 0 },
50829
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
50830
    & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_An_relative_HI, { 0xa98c0000 }
50831
  },
50832
/* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
50833
  {
50834
    { 0, 0, 0, 0 },
50835
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
50836
    & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_An_relative_HI, { 0xa9ac0000 }
50837
  },
50838
/* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
50839
  {
50840
    { 0, 0, 0, 0 },
50841
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
50842
    & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_An_relative_HI, { 0xa9bc0000 }
50843
  },
50844
/* sub.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
50845
  {
50846
    { 0, 0, 0, 0 },
50847
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
50848
    & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_SB_relative_HI, { 0xa98a0000 }
50849
  },
50850
/* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
50851
  {
50852
    { 0, 0, 0, 0 },
50853
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
50854
    & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_SB_relative_HI, { 0xa9aa0000 }
50855
  },
50856
/* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
50857
  {
50858
    { 0, 0, 0, 0 },
50859
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
50860
    & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_SB_relative_HI, { 0xa9ba0000 }
50861
  },
50862
/* sub.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
50863
  {
50864
    { 0, 0, 0, 0 },
50865
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
50866
    & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_SB_relative_HI, { 0xa98e0000 }
50867
  },
50868
/* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
50869
  {
50870
    { 0, 0, 0, 0 },
50871
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
50872
    & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_SB_relative_HI, { 0xa9ae0000 }
50873
  },
50874
/* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
50875
  {
50876
    { 0, 0, 0, 0 },
50877
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
50878
    & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_SB_relative_HI, { 0xa9be0000 }
50879
  },
50880
/* sub.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
50881
  {
50882
    { 0, 0, 0, 0 },
50883
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
50884
    & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_FB_relative_HI, { 0xa98b0000 }
50885
  },
50886
/* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
50887
  {
50888
    { 0, 0, 0, 0 },
50889
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
50890
    & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_FB_relative_HI, { 0xa9ab0000 }
50891
  },
50892
/* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
50893
  {
50894
    { 0, 0, 0, 0 },
50895
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
50896
    & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_FB_relative_HI, { 0xa9bb0000 }
50897
  },
50898
/* sub.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
50899
  {
50900
    { 0, 0, 0, 0 },
50901
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } },
50902
    & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_absolute_HI, { 0xa98f0000 }
50903
  },
50904
/* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
50905
  {
50906
    { 0, 0, 0, 0 },
50907
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
50908
    & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_absolute_HI, { 0xa9af0000 }
50909
  },
50910
/* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
50911
  {
50912
    { 0, 0, 0, 0 },
50913
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
50914
    & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_absolute_HI, { 0xa9bf0000 }
50915
  },
50916
/* sub.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
50917
  {
50918
    { 0, 0, 0, 0 },
50919
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } },
50920
    & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_Rn_direct_HI, { 0xa9c00000 }
50921
  },
50922
/* sub.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */
50923
  {
50924
    { 0, 0, 0, 0 },
50925
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } },
50926
    & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_Rn_direct_HI, { 0xa9e00000 }
50927
  },
50928
/* sub.w${G} ${Dsp-16-u16},$Dst16RnHI */
50929
  {
50930
    { 0, 0, 0, 0 },
50931
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16RNHI), 0 } },
50932
    & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_Rn_direct_HI, { 0xa9f00000 }
50933
  },
50934
/* sub.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
50935
  {
50936
    { 0, 0, 0, 0 },
50937
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } },
50938
    & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_direct_HI, { 0xa9c40000 }
50939
  },
50940
/* sub.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */
50941
  {
50942
    { 0, 0, 0, 0 },
50943
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } },
50944
    & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_direct_HI, { 0xa9e40000 }
50945
  },
50946
/* sub.w${G} ${Dsp-16-u16},$Dst16AnHI */
50947
  {
50948
    { 0, 0, 0, 0 },
50949
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16ANHI), 0 } },
50950
    & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_direct_HI, { 0xa9f40000 }
50951
  },
50952
/* sub.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
50953
  {
50954
    { 0, 0, 0, 0 },
50955
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
50956
    & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_indirect_HI, { 0xa9c60000 }
50957
  },
50958
/* sub.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */
50959
  {
50960
    { 0, 0, 0, 0 },
50961
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
50962
    & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_indirect_HI, { 0xa9e60000 }
50963
  },
50964
/* sub.w${G} ${Dsp-16-u16},[$Dst16An] */
50965
  {
50966
    { 0, 0, 0, 0 },
50967
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } },
50968
    & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_indirect_HI, { 0xa9f60000 }
50969
  },
50970
/* sub.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
50971
  {
50972
    { 0, 0, 0, 0 },
50973
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
50974
    & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_An_relative_HI, { 0xa9c80000 }
50975
  },
50976
/* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
50977
  {
50978
    { 0, 0, 0, 0 },
50979
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
50980
    & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_An_relative_HI, { 0xa9e80000 }
50981
  },
50982
/* sub.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
50983
  {
50984
    { 0, 0, 0, 0 },
50985
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
50986
    & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_An_relative_HI, { 0xa9f80000 }
50987
  },
50988
/* sub.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
50989
  {
50990
    { 0, 0, 0, 0 },
50991
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
50992
    & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_An_relative_HI, { 0xa9cc0000 }
50993
  },
50994
/* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
50995
  {
50996
    { 0, 0, 0, 0 },
50997
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
50998
    & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_An_relative_HI, { 0xa9ec0000 }
50999
  },
51000
/* sub.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
51001
  {
51002
    { 0, 0, 0, 0 },
51003
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
51004
    & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_An_relative_HI, { 0xa9fc0000 }
51005
  },
51006
/* sub.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
51007
  {
51008
    { 0, 0, 0, 0 },
51009
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
51010
    & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_SB_relative_HI, { 0xa9ca0000 }
51011
  },
51012
/* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
51013
  {
51014
    { 0, 0, 0, 0 },
51015
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
51016
    & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_SB_relative_HI, { 0xa9ea0000 }
51017
  },
51018
/* sub.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
51019
  {
51020
    { 0, 0, 0, 0 },
51021
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
51022
    & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_SB_relative_HI, { 0xa9fa0000 }
51023
  },
51024
/* sub.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
51025
  {
51026
    { 0, 0, 0, 0 },
51027
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
51028
    & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_SB_relative_HI, { 0xa9ce0000 }
51029
  },
51030
/* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
51031
  {
51032
    { 0, 0, 0, 0 },
51033
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
51034
    & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_SB_relative_HI, { 0xa9ee0000 }
51035
  },
51036
/* sub.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
51037
  {
51038
    { 0, 0, 0, 0 },
51039
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
51040
    & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_SB_relative_HI, { 0xa9fe0000 }
51041
  },
51042
/* sub.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
51043
  {
51044
    { 0, 0, 0, 0 },
51045
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
51046
    & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_FB_relative_HI, { 0xa9cb0000 }
51047
  },
51048
/* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
51049
  {
51050
    { 0, 0, 0, 0 },
51051
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
51052
    & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_FB_relative_HI, { 0xa9eb0000 }
51053
  },
51054
/* sub.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
51055
  {
51056
    { 0, 0, 0, 0 },
51057
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
51058
    & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_FB_relative_HI, { 0xa9fb0000 }
51059
  },
51060
/* sub.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
51061
  {
51062
    { 0, 0, 0, 0 },
51063
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } },
51064
    & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_absolute_HI, { 0xa9cf0000 }
51065
  },
51066
/* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
51067
  {
51068
    { 0, 0, 0, 0 },
51069
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
51070
    & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_absolute_HI, { 0xa9ef0000 }
51071
  },
51072
/* sub.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
51073
  {
51074
    { 0, 0, 0, 0 },
51075
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
51076
    & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_absolute_HI, { 0xa9ff0000 }
51077
  },
51078
/* sub.w${G} $Src16RnHI,$Dst16RnHI */
51079
  {
51080
    { 0, 0, 0, 0 },
51081
    { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DST16RNHI), 0 } },
51082
    & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_Rn_direct_HI, { 0xa900 }
51083
  },
51084
/* sub.w${G} $Src16AnHI,$Dst16RnHI */
51085
  {
51086
    { 0, 0, 0, 0 },
51087
    { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DST16RNHI), 0 } },
51088
    & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_Rn_direct_HI, { 0xa940 }
51089
  },
51090
/* sub.w${G} [$Src16An],$Dst16RnHI */
51091
  {
51092
    { 0, 0, 0, 0 },
51093
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } },
51094
    & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_Rn_direct_HI, { 0xa960 }
51095
  },
51096
/* sub.w${G} $Src16RnHI,$Dst16AnHI */
51097
  {
51098
    { 0, 0, 0, 0 },
51099
    { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DST16ANHI), 0 } },
51100
    & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_direct_HI, { 0xa904 }
51101
  },
51102
/* sub.w${G} $Src16AnHI,$Dst16AnHI */
51103
  {
51104
    { 0, 0, 0, 0 },
51105
    { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DST16ANHI), 0 } },
51106
    & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_direct_HI, { 0xa944 }
51107
  },
51108
/* sub.w${G} [$Src16An],$Dst16AnHI */
51109
  {
51110
    { 0, 0, 0, 0 },
51111
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } },
51112
    & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_direct_HI, { 0xa964 }
51113
  },
51114
/* sub.w${G} $Src16RnHI,[$Dst16An] */
51115
  {
51116
    { 0, 0, 0, 0 },
51117
    { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', '[', OP (DST16AN), ']', 0 } },
51118
    & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_indirect_HI, { 0xa906 }
51119
  },
51120
/* sub.w${G} $Src16AnHI,[$Dst16An] */
51121
  {
51122
    { 0, 0, 0, 0 },
51123
    { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', '[', OP (DST16AN), ']', 0 } },
51124
    & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_indirect_HI, { 0xa946 }
51125
  },
51126
/* sub.w${G} [$Src16An],[$Dst16An] */
51127
  {
51128
    { 0, 0, 0, 0 },
51129
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
51130
    & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_indirect_HI, { 0xa966 }
51131
  },
51132
/* sub.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
51133
  {
51134
    { 0, 0, 0, 0 },
51135
    { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
51136
    & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_An_relative_HI, { 0xa90800 }
51137
  },
51138
/* sub.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
51139
  {
51140
    { 0, 0, 0, 0 },
51141
    { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
51142
    & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_An_relative_HI, { 0xa94800 }
51143
  },
51144
/* sub.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
51145
  {
51146
    { 0, 0, 0, 0 },
51147
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
51148
    & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_An_relative_HI, { 0xa96800 }
51149
  },
51150
/* sub.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
51151
  {
51152
    { 0, 0, 0, 0 },
51153
    { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
51154
    & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_An_relative_HI, { 0xa90c0000 }
51155
  },
51156
/* sub.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
51157
  {
51158
    { 0, 0, 0, 0 },
51159
    { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
51160
    & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_An_relative_HI, { 0xa94c0000 }
51161
  },
51162
/* sub.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
51163
  {
51164
    { 0, 0, 0, 0 },
51165
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
51166
    & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_An_relative_HI, { 0xa96c0000 }
51167
  },
51168
/* sub.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */
51169
  {
51170
    { 0, 0, 0, 0 },
51171
    { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
51172
    & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_SB_relative_HI, { 0xa90a00 }
51173
  },
51174
/* sub.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */
51175
  {
51176
    { 0, 0, 0, 0 },
51177
    { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
51178
    & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_SB_relative_HI, { 0xa94a00 }
51179
  },
51180
/* sub.w${G} [$Src16An],${Dsp-16-u8}[sb] */
51181
  {
51182
    { 0, 0, 0, 0 },
51183
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
51184
    & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_SB_relative_HI, { 0xa96a00 }
51185
  },
51186
/* sub.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */
51187
  {
51188
    { 0, 0, 0, 0 },
51189
    { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
51190
    & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_SB_relative_HI, { 0xa90e0000 }
51191
  },
51192
/* sub.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */
51193
  {
51194
    { 0, 0, 0, 0 },
51195
    { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
51196
    & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_SB_relative_HI, { 0xa94e0000 }
51197
  },
51198
/* sub.w${G} [$Src16An],${Dsp-16-u16}[sb] */
51199
  {
51200
    { 0, 0, 0, 0 },
51201
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
51202
    & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_SB_relative_HI, { 0xa96e0000 }
51203
  },
51204
/* sub.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */
51205
  {
51206
    { 0, 0, 0, 0 },
51207
    { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
51208
    & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_FB_relative_HI, { 0xa90b00 }
51209
  },
51210
/* sub.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */
51211
  {
51212
    { 0, 0, 0, 0 },
51213
    { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
51214
    & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_FB_relative_HI, { 0xa94b00 }
51215
  },
51216
/* sub.w${G} [$Src16An],${Dsp-16-s8}[fb] */
51217
  {
51218
    { 0, 0, 0, 0 },
51219
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
51220
    & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_FB_relative_HI, { 0xa96b00 }
51221
  },
51222
/* sub.w${G} $Src16RnHI,${Dsp-16-u16} */
51223
  {
51224
    { 0, 0, 0, 0 },
51225
    { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), 0 } },
51226
    & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_absolute_HI, { 0xa90f0000 }
51227
  },
51228
/* sub.w${G} $Src16AnHI,${Dsp-16-u16} */
51229
  {
51230
    { 0, 0, 0, 0 },
51231
    { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), 0 } },
51232
    & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_absolute_HI, { 0xa94f0000 }
51233
  },
51234
/* sub.w${G} [$Src16An],${Dsp-16-u16} */
51235
  {
51236
    { 0, 0, 0, 0 },
51237
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } },
51238
    & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_absolute_HI, { 0xa96f0000 }
51239
  },
51240
/* sub.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
51241
  {
51242
    { 0, 0, 0, 0 },
51243
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } },
51244
    & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_Rn_direct_QI, { 0xa88000 }
51245
  },
51246
/* sub.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */
51247
  {
51248
    { 0, 0, 0, 0 },
51249
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } },
51250
    & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_Rn_direct_QI, { 0xa8a000 }
51251
  },
51252
/* sub.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */
51253
  {
51254
    { 0, 0, 0, 0 },
51255
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNQI), 0 } },
51256
    & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_Rn_direct_QI, { 0xa8b000 }
51257
  },
51258
/* sub.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
51259
  {
51260
    { 0, 0, 0, 0 },
51261
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } },
51262
    & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_direct_QI, { 0xa88400 }
51263
  },
51264
/* sub.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */
51265
  {
51266
    { 0, 0, 0, 0 },
51267
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } },
51268
    & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_direct_QI, { 0xa8a400 }
51269
  },
51270
/* sub.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */
51271
  {
51272
    { 0, 0, 0, 0 },
51273
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANQI), 0 } },
51274
    & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_direct_QI, { 0xa8b400 }
51275
  },
51276
/* sub.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
51277
  {
51278
    { 0, 0, 0, 0 },
51279
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
51280
    & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_indirect_QI, { 0xa88600 }
51281
  },
51282
/* sub.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */
51283
  {
51284
    { 0, 0, 0, 0 },
51285
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
51286
    & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_indirect_QI, { 0xa8a600 }
51287
  },
51288
/* sub.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */
51289
  {
51290
    { 0, 0, 0, 0 },
51291
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
51292
    & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_indirect_QI, { 0xa8b600 }
51293
  },
51294
/* sub.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
51295
  {
51296
    { 0, 0, 0, 0 },
51297
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
51298
    & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_An_relative_QI, { 0xa8880000 }
51299
  },
51300
/* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
51301
  {
51302
    { 0, 0, 0, 0 },
51303
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
51304
    & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_An_relative_QI, { 0xa8a80000 }
51305
  },
51306
/* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
51307
  {
51308
    { 0, 0, 0, 0 },
51309
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
51310
    & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_An_relative_QI, { 0xa8b80000 }
51311
  },
51312
/* sub.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
51313
  {
51314
    { 0, 0, 0, 0 },
51315
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
51316
    & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_An_relative_QI, { 0xa88c0000 }
51317
  },
51318
/* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
51319
  {
51320
    { 0, 0, 0, 0 },
51321
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
51322
    & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_An_relative_QI, { 0xa8ac0000 }
51323
  },
51324
/* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
51325
  {
51326
    { 0, 0, 0, 0 },
51327
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
51328
    & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_An_relative_QI, { 0xa8bc0000 }
51329
  },
51330
/* sub.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
51331
  {
51332
    { 0, 0, 0, 0 },
51333
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
51334
    & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_SB_relative_QI, { 0xa88a0000 }
51335
  },
51336
/* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
51337
  {
51338
    { 0, 0, 0, 0 },
51339
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
51340
    & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_SB_relative_QI, { 0xa8aa0000 }
51341
  },
51342
/* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
51343
  {
51344
    { 0, 0, 0, 0 },
51345
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
51346
    & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_SB_relative_QI, { 0xa8ba0000 }
51347
  },
51348
/* sub.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
51349
  {
51350
    { 0, 0, 0, 0 },
51351
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
51352
    & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_SB_relative_QI, { 0xa88e0000 }
51353
  },
51354
/* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
51355
  {
51356
    { 0, 0, 0, 0 },
51357
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
51358
    & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_SB_relative_QI, { 0xa8ae0000 }
51359
  },
51360
/* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
51361
  {
51362
    { 0, 0, 0, 0 },
51363
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
51364
    & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_SB_relative_QI, { 0xa8be0000 }
51365
  },
51366
/* sub.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
51367
  {
51368
    { 0, 0, 0, 0 },
51369
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
51370
    & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_FB_relative_QI, { 0xa88b0000 }
51371
  },
51372
/* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
51373
  {
51374
    { 0, 0, 0, 0 },
51375
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
51376
    & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_FB_relative_QI, { 0xa8ab0000 }
51377
  },
51378
/* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
51379
  {
51380
    { 0, 0, 0, 0 },
51381
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
51382
    & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_FB_relative_QI, { 0xa8bb0000 }
51383
  },
51384
/* sub.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
51385
  {
51386
    { 0, 0, 0, 0 },
51387
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } },
51388
    & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_absolute_QI, { 0xa88f0000 }
51389
  },
51390
/* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
51391
  {
51392
    { 0, 0, 0, 0 },
51393
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
51394
    & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_absolute_QI, { 0xa8af0000 }
51395
  },
51396
/* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
51397
  {
51398
    { 0, 0, 0, 0 },
51399
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
51400
    & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_absolute_QI, { 0xa8bf0000 }
51401
  },
51402
/* sub.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
51403
  {
51404
    { 0, 0, 0, 0 },
51405
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } },
51406
    & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_Rn_direct_QI, { 0xa8c00000 }
51407
  },
51408
/* sub.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */
51409
  {
51410
    { 0, 0, 0, 0 },
51411
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } },
51412
    & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_Rn_direct_QI, { 0xa8e00000 }
51413
  },
51414
/* sub.b${G} ${Dsp-16-u16},$Dst16RnQI */
51415
  {
51416
    { 0, 0, 0, 0 },
51417
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16RNQI), 0 } },
51418
    & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_Rn_direct_QI, { 0xa8f00000 }
51419
  },
51420
/* sub.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
51421
  {
51422
    { 0, 0, 0, 0 },
51423
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } },
51424
    & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_direct_QI, { 0xa8c40000 }
51425
  },
51426
/* sub.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */
51427
  {
51428
    { 0, 0, 0, 0 },
51429
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } },
51430
    & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_direct_QI, { 0xa8e40000 }
51431
  },
51432
/* sub.b${G} ${Dsp-16-u16},$Dst16AnQI */
51433
  {
51434
    { 0, 0, 0, 0 },
51435
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16ANQI), 0 } },
51436
    & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_direct_QI, { 0xa8f40000 }
51437
  },
51438
/* sub.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
51439
  {
51440
    { 0, 0, 0, 0 },
51441
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
51442
    & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_indirect_QI, { 0xa8c60000 }
51443
  },
51444
/* sub.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */
51445
  {
51446
    { 0, 0, 0, 0 },
51447
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
51448
    & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_indirect_QI, { 0xa8e60000 }
51449
  },
51450
/* sub.b${G} ${Dsp-16-u16},[$Dst16An] */
51451
  {
51452
    { 0, 0, 0, 0 },
51453
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } },
51454
    & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_indirect_QI, { 0xa8f60000 }
51455
  },
51456
/* sub.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
51457
  {
51458
    { 0, 0, 0, 0 },
51459
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
51460
    & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_An_relative_QI, { 0xa8c80000 }
51461
  },
51462
/* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
51463
  {
51464
    { 0, 0, 0, 0 },
51465
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
51466
    & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_An_relative_QI, { 0xa8e80000 }
51467
  },
51468
/* sub.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
51469
  {
51470
    { 0, 0, 0, 0 },
51471
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
51472
    & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_An_relative_QI, { 0xa8f80000 }
51473
  },
51474
/* sub.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
51475
  {
51476
    { 0, 0, 0, 0 },
51477
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
51478
    & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_An_relative_QI, { 0xa8cc0000 }
51479
  },
51480
/* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
51481
  {
51482
    { 0, 0, 0, 0 },
51483
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
51484
    & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_An_relative_QI, { 0xa8ec0000 }
51485
  },
51486
/* sub.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
51487
  {
51488
    { 0, 0, 0, 0 },
51489
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
51490
    & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_An_relative_QI, { 0xa8fc0000 }
51491
  },
51492
/* sub.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
51493
  {
51494
    { 0, 0, 0, 0 },
51495
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
51496
    & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_SB_relative_QI, { 0xa8ca0000 }
51497
  },
51498
/* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
51499
  {
51500
    { 0, 0, 0, 0 },
51501
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
51502
    & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_SB_relative_QI, { 0xa8ea0000 }
51503
  },
51504
/* sub.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
51505
  {
51506
    { 0, 0, 0, 0 },
51507
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
51508
    & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_SB_relative_QI, { 0xa8fa0000 }
51509
  },
51510
/* sub.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
51511
  {
51512
    { 0, 0, 0, 0 },
51513
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
51514
    & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_SB_relative_QI, { 0xa8ce0000 }
51515
  },
51516
/* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
51517
  {
51518
    { 0, 0, 0, 0 },
51519
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
51520
    & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_SB_relative_QI, { 0xa8ee0000 }
51521
  },
51522
/* sub.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
51523
  {
51524
    { 0, 0, 0, 0 },
51525
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
51526
    & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_SB_relative_QI, { 0xa8fe0000 }
51527
  },
51528
/* sub.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
51529
  {
51530
    { 0, 0, 0, 0 },
51531
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
51532
    & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_FB_relative_QI, { 0xa8cb0000 }
51533
  },
51534
/* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
51535
  {
51536
    { 0, 0, 0, 0 },
51537
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
51538
    & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_FB_relative_QI, { 0xa8eb0000 }
51539
  },
51540
/* sub.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
51541
  {
51542
    { 0, 0, 0, 0 },
51543
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
51544
    & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_FB_relative_QI, { 0xa8fb0000 }
51545
  },
51546
/* sub.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
51547
  {
51548
    { 0, 0, 0, 0 },
51549
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } },
51550
    & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_absolute_QI, { 0xa8cf0000 }
51551
  },
51552
/* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
51553
  {
51554
    { 0, 0, 0, 0 },
51555
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
51556
    & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_absolute_QI, { 0xa8ef0000 }
51557
  },
51558
/* sub.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
51559
  {
51560
    { 0, 0, 0, 0 },
51561
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
51562
    & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_absolute_QI, { 0xa8ff0000 }
51563
  },
51564
/* sub.b${G} $Src16RnQI,$Dst16RnQI */
51565
  {
51566
    { 0, 0, 0, 0 },
51567
    { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DST16RNQI), 0 } },
51568
    & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_Rn_direct_QI, { 0xa800 }
51569
  },
51570
/* sub.b${G} $Src16AnQI,$Dst16RnQI */
51571
  {
51572
    { 0, 0, 0, 0 },
51573
    { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DST16RNQI), 0 } },
51574
    & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_Rn_direct_QI, { 0xa840 }
51575
  },
51576
/* sub.b${G} [$Src16An],$Dst16RnQI */
51577
  {
51578
    { 0, 0, 0, 0 },
51579
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } },
51580
    & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_Rn_direct_QI, { 0xa860 }
51581
  },
51582
/* sub.b${G} $Src16RnQI,$Dst16AnQI */
51583
  {
51584
    { 0, 0, 0, 0 },
51585
    { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DST16ANQI), 0 } },
51586
    & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_direct_QI, { 0xa804 }
51587
  },
51588
/* sub.b${G} $Src16AnQI,$Dst16AnQI */
51589
  {
51590
    { 0, 0, 0, 0 },
51591
    { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DST16ANQI), 0 } },
51592
    & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_direct_QI, { 0xa844 }
51593
  },
51594
/* sub.b${G} [$Src16An],$Dst16AnQI */
51595
  {
51596
    { 0, 0, 0, 0 },
51597
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } },
51598
    & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_direct_QI, { 0xa864 }
51599
  },
51600
/* sub.b${G} $Src16RnQI,[$Dst16An] */
51601
  {
51602
    { 0, 0, 0, 0 },
51603
    { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', '[', OP (DST16AN), ']', 0 } },
51604
    & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_indirect_QI, { 0xa806 }
51605
  },
51606
/* sub.b${G} $Src16AnQI,[$Dst16An] */
51607
  {
51608
    { 0, 0, 0, 0 },
51609
    { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', '[', OP (DST16AN), ']', 0 } },
51610
    & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_indirect_QI, { 0xa846 }
51611
  },
51612
/* sub.b${G} [$Src16An],[$Dst16An] */
51613
  {
51614
    { 0, 0, 0, 0 },
51615
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
51616
    & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_indirect_QI, { 0xa866 }
51617
  },
51618
/* sub.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
51619
  {
51620
    { 0, 0, 0, 0 },
51621
    { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
51622
    & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_An_relative_QI, { 0xa80800 }
51623
  },
51624
/* sub.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
51625
  {
51626
    { 0, 0, 0, 0 },
51627
    { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
51628
    & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_An_relative_QI, { 0xa84800 }
51629
  },
51630
/* sub.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
51631
  {
51632
    { 0, 0, 0, 0 },
51633
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
51634
    & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_An_relative_QI, { 0xa86800 }
51635
  },
51636
/* sub.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
51637
  {
51638
    { 0, 0, 0, 0 },
51639
    { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
51640
    & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_An_relative_QI, { 0xa80c0000 }
51641
  },
51642
/* sub.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
51643
  {
51644
    { 0, 0, 0, 0 },
51645
    { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
51646
    & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_An_relative_QI, { 0xa84c0000 }
51647
  },
51648
/* sub.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
51649
  {
51650
    { 0, 0, 0, 0 },
51651
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
51652
    & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_An_relative_QI, { 0xa86c0000 }
51653
  },
51654
/* sub.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */
51655
  {
51656
    { 0, 0, 0, 0 },
51657
    { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
51658
    & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_SB_relative_QI, { 0xa80a00 }
51659
  },
51660
/* sub.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */
51661
  {
51662
    { 0, 0, 0, 0 },
51663
    { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
51664
    & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_SB_relative_QI, { 0xa84a00 }
51665
  },
51666
/* sub.b${G} [$Src16An],${Dsp-16-u8}[sb] */
51667
  {
51668
    { 0, 0, 0, 0 },
51669
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
51670
    & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_SB_relative_QI, { 0xa86a00 }
51671
  },
51672
/* sub.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */
51673
  {
51674
    { 0, 0, 0, 0 },
51675
    { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
51676
    & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_SB_relative_QI, { 0xa80e0000 }
51677
  },
51678
/* sub.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */
51679
  {
51680
    { 0, 0, 0, 0 },
51681
    { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
51682
    & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_SB_relative_QI, { 0xa84e0000 }
51683
  },
51684
/* sub.b${G} [$Src16An],${Dsp-16-u16}[sb] */
51685
  {
51686
    { 0, 0, 0, 0 },
51687
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
51688
    & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_SB_relative_QI, { 0xa86e0000 }
51689
  },
51690
/* sub.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */
51691
  {
51692
    { 0, 0, 0, 0 },
51693
    { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
51694
    & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_FB_relative_QI, { 0xa80b00 }
51695
  },
51696
/* sub.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */
51697
  {
51698
    { 0, 0, 0, 0 },
51699
    { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
51700
    & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_FB_relative_QI, { 0xa84b00 }
51701
  },
51702
/* sub.b${G} [$Src16An],${Dsp-16-s8}[fb] */
51703
  {
51704
    { 0, 0, 0, 0 },
51705
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
51706
    & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_FB_relative_QI, { 0xa86b00 }
51707
  },
51708
/* sub.b${G} $Src16RnQI,${Dsp-16-u16} */
51709
  {
51710
    { 0, 0, 0, 0 },
51711
    { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), 0 } },
51712
    & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_absolute_QI, { 0xa80f0000 }
51713
  },
51714
/* sub.b${G} $Src16AnQI,${Dsp-16-u16} */
51715
  {
51716
    { 0, 0, 0, 0 },
51717
    { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), 0 } },
51718
    & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_absolute_QI, { 0xa84f0000 }
51719
  },
51720
/* sub.b${G} [$Src16An],${Dsp-16-u16} */
51721
  {
51722
    { 0, 0, 0, 0 },
51723
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } },
51724
    & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_absolute_QI, { 0xa86f0000 }
51725
  },
51726
/* sub.b${S} #${Imm-8-QI},r0l */
51727
  {
51728
    { 0, 0, 0, 0 },
51729
    { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'l', 0 } },
51730
    & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_R0l_direct_QI, { 0x8c00 }
51731
  },
51732
/* sub.b${S} #${Imm-8-QI},r0h */
51733
  {
51734
    { 0, 0, 0, 0 },
51735
    { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'h', 0 } },
51736
    & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_R0h_direct_QI, { 0x8b00 }
51737
  },
51738
/* sub.b${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */
51739
  {
51740
    { 0, 0, 0, 0 },
51741
    { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
51742
    & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_8_SB_relative_QI, { 0x8d0000 }
51743
  },
51744
/* sub.b${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */
51745
  {
51746
    { 0, 0, 0, 0 },
51747
    { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
51748
    & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_8_FB_relative_QI, { 0x8e0000 }
51749
  },
51750
/* sub.b${S} #${Imm-8-QI},${Dsp-16-u16} */
51751
  {
51752
    { 0, 0, 0, 0 },
51753
    { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_U16), 0 } },
51754
    & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_16_absolute_QI, { 0x8f000000 }
51755
  },
51756
/* sub.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */
51757
  {
51758
    { 0, 0, 0, 0 },
51759
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
51760
    & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0x893e0000 }
51761
  },
51762
/* sub.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */
51763
  {
51764
    { 0, 0, 0, 0 },
51765
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
51766
    & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0x81be0000 }
51767
  },
51768
/* sub.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */
51769
  {
51770
    { 0, 0, 0, 0 },
51771
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
51772
    & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0x813e0000 }
51773
  },
51774
/* sub.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
51775
  {
51776
    { 0, 0, 0, 0 },
51777
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
51778
    & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0x833e0000 }
51779
  },
51780
/* sub.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
51781
  {
51782
    { 0, 0, 0, 0 },
51783
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
51784
    & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0x83be0000 }
51785
  },
51786
/* sub.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
51787
  {
51788
    { 0, 0, 0, 0 },
51789
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
51790
    & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83fe0000 }
51791
  },
51792
/* sub.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
51793
  {
51794
    { 0, 0, 0, 0 },
51795
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
51796
    & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0x853e0000 }
51797
  },
51798
/* sub.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
51799
  {
51800
    { 0, 0, 0, 0 },
51801
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
51802
    & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0x85be0000 }
51803
  },
51804
/* sub.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */
51805
  {
51806
    { 0, 0, 0, 0 },
51807
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
51808
    & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85fe0000 }
51809
  },
51810
/* sub.w${G} #${Imm-32-HI},${Dsp-16-u16} */
51811
  {
51812
    { 0, 0, 0, 0 },
51813
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } },
51814
    & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0x87fe0000 }
51815
  },
51816
/* sub.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
51817
  {
51818
    { 0, 0, 0, 0 },
51819
    { { MNEM, OP (G), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
51820
    & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0x873e0000 }
51821
  },
51822
/* sub.w${G} #${Imm-40-HI},${Dsp-16-u24} */
51823
  {
51824
    { 0, 0, 0, 0 },
51825
    { { MNEM, OP (G), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), 0 } },
51826
    & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0x87be0000 }
51827
  },
51828
/* sub.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */
51829
  {
51830
    { 0, 0, 0, 0 },
51831
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
51832
    & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0x883e00 }
51833
  },
51834
/* sub.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */
51835
  {
51836
    { 0, 0, 0, 0 },
51837
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
51838
    & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0x80be00 }
51839
  },
51840
/* sub.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */
51841
  {
51842
    { 0, 0, 0, 0 },
51843
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
51844
    & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0x803e00 }
51845
  },
51846
/* sub.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
51847
  {
51848
    { 0, 0, 0, 0 },
51849
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
51850
    & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0x823e0000 }
51851
  },
51852
/* sub.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
51853
  {
51854
    { 0, 0, 0, 0 },
51855
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
51856
    & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0x82be0000 }
51857
  },
51858
/* sub.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
51859
  {
51860
    { 0, 0, 0, 0 },
51861
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
51862
    & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82fe0000 }
51863
  },
51864
/* sub.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
51865
  {
51866
    { 0, 0, 0, 0 },
51867
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
51868
    & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0x843e0000 }
51869
  },
51870
/* sub.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
51871
  {
51872
    { 0, 0, 0, 0 },
51873
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
51874
    & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0x84be0000 }
51875
  },
51876
/* sub.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */
51877
  {
51878
    { 0, 0, 0, 0 },
51879
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
51880
    & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84fe0000 }
51881
  },
51882
/* sub.b${G} #${Imm-32-QI},${Dsp-16-u16} */
51883
  {
51884
    { 0, 0, 0, 0 },
51885
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } },
51886
    & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0x86fe0000 }
51887
  },
51888
/* sub.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
51889
  {
51890
    { 0, 0, 0, 0 },
51891
    { { MNEM, OP (G), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
51892
    & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0x863e0000 }
51893
  },
51894
/* sub.b${G} #${Imm-40-QI},${Dsp-16-u24} */
51895
  {
51896
    { 0, 0, 0, 0 },
51897
    { { MNEM, OP (G), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), 0 } },
51898
    & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0x86be0000 }
51899
  },
51900
/* sub.w${G} #${Imm-16-HI},$Dst16RnHI */
51901
  {
51902
    { 0, 0, 0, 0 },
51903
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST16RNHI), 0 } },
51904
    & ifmt_xor16_w_imm_G_basic_dst16_Rn_direct_HI, { 0x77500000 }
51905
  },
51906
/* sub.w${G} #${Imm-16-HI},$Dst16AnHI */
51907
  {
51908
    { 0, 0, 0, 0 },
51909
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST16ANHI), 0 } },
51910
    & ifmt_xor16_w_imm_G_basic_dst16_An_direct_HI, { 0x77540000 }
51911
  },
51912
/* sub.w${G} #${Imm-16-HI},[$Dst16An] */
51913
  {
51914
    { 0, 0, 0, 0 },
51915
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST16AN), ']', 0 } },
51916
    & ifmt_xor16_w_imm_G_basic_dst16_An_indirect_HI, { 0x77560000 }
51917
  },
51918
/* sub.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
51919
  {
51920
    { 0, 0, 0, 0 },
51921
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
51922
    & ifmt_xor16_w_imm_G_16_8_dst16_16_8_An_relative_HI, { 0x77580000 }
51923
  },
51924
/* sub.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
51925
  {
51926
    { 0, 0, 0, 0 },
51927
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
51928
    & ifmt_xor16_w_imm_G_16_8_dst16_16_8_SB_relative_HI, { 0x775a0000 }
51929
  },
51930
/* sub.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
51931
  {
51932
    { 0, 0, 0, 0 },
51933
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
51934
    & ifmt_xor16_w_imm_G_16_8_dst16_16_8_FB_relative_HI, { 0x775b0000 }
51935
  },
51936
/* sub.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
51937
  {
51938
    { 0, 0, 0, 0 },
51939
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
51940
    & ifmt_xor16_w_imm_G_16_16_dst16_16_16_An_relative_HI, { 0x775c0000 }
51941
  },
51942
/* sub.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
51943
  {
51944
    { 0, 0, 0, 0 },
51945
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
51946
    & ifmt_xor16_w_imm_G_16_16_dst16_16_16_SB_relative_HI, { 0x775e0000 }
51947
  },
51948
/* sub.w${G} #${Imm-32-HI},${Dsp-16-u16} */
51949
  {
51950
    { 0, 0, 0, 0 },
51951
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } },
51952
    & ifmt_xor16_w_imm_G_16_16_dst16_16_16_absolute_HI, { 0x775f0000 }
51953
  },
51954
/* sub.b${G} #${Imm-16-QI},$Dst16RnQI */
51955
  {
51956
    { 0, 0, 0, 0 },
51957
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST16RNQI), 0 } },
51958
    & ifmt_xor16_b_imm_G_basic_dst16_Rn_direct_QI, { 0x765000 }
51959
  },
51960
/* sub.b${G} #${Imm-16-QI},$Dst16AnQI */
51961
  {
51962
    { 0, 0, 0, 0 },
51963
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST16ANQI), 0 } },
51964
    & ifmt_xor16_b_imm_G_basic_dst16_An_direct_QI, { 0x765400 }
51965
  },
51966
/* sub.b${G} #${Imm-16-QI},[$Dst16An] */
51967
  {
51968
    { 0, 0, 0, 0 },
51969
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST16AN), ']', 0 } },
51970
    & ifmt_xor16_b_imm_G_basic_dst16_An_indirect_QI, { 0x765600 }
51971
  },
51972
/* sub.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
51973
  {
51974
    { 0, 0, 0, 0 },
51975
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
51976
    & ifmt_xor16_b_imm_G_16_8_dst16_16_8_An_relative_QI, { 0x76580000 }
51977
  },
51978
/* sub.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
51979
  {
51980
    { 0, 0, 0, 0 },
51981
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
51982
    & ifmt_xor16_b_imm_G_16_8_dst16_16_8_SB_relative_QI, { 0x765a0000 }
51983
  },
51984
/* sub.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
51985
  {
51986
    { 0, 0, 0, 0 },
51987
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
51988
    & ifmt_xor16_b_imm_G_16_8_dst16_16_8_FB_relative_QI, { 0x765b0000 }
51989
  },
51990
/* sub.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
51991
  {
51992
    { 0, 0, 0, 0 },
51993
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
51994
    & ifmt_xor16_b_imm_G_16_16_dst16_16_16_An_relative_QI, { 0x765c0000 }
51995
  },
51996
/* sub.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
51997
  {
51998
    { 0, 0, 0, 0 },
51999
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
52000
    & ifmt_xor16_b_imm_G_16_16_dst16_16_16_SB_relative_QI, { 0x765e0000 }
52001
  },
52002
/* sub.b${G} #${Imm-32-QI},${Dsp-16-u16} */
52003
  {
52004
    { 0, 0, 0, 0 },
52005
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } },
52006
    & ifmt_xor16_b_imm_G_16_16_dst16_16_16_absolute_QI, { 0x765f0000 }
52007
  },
52008
/* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
52009
  {
52010
    { 0, 0, 0, 0 },
52011
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
52012
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1990200 }
52013
  },
52014
/* dsub.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
52015
  {
52016
    { 0, 0, 0, 0 },
52017
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
52018
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1992200 }
52019
  },
52020
/* dsub.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
52021
  {
52022
    { 0, 0, 0, 0 },
52023
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
52024
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1993200 }
52025
  },
52026
/* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
52027
  {
52028
    { 0, 0, 0, 0 },
52029
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
52030
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1918200 }
52031
  },
52032
/* dsub.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
52033
  {
52034
    { 0, 0, 0, 0 },
52035
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
52036
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x191a200 }
52037
  },
52038
/* dsub.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
52039
  {
52040
    { 0, 0, 0, 0 },
52041
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
52042
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x191b200 }
52043
  },
52044
/* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
52045
  {
52046
    { 0, 0, 0, 0 },
52047
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
52048
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1910200 }
52049
  },
52050
/* dsub.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
52051
  {
52052
    { 0, 0, 0, 0 },
52053
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
52054
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1912200 }
52055
  },
52056
/* dsub.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
52057
  {
52058
    { 0, 0, 0, 0 },
52059
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
52060
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1913200 }
52061
  },
52062
/* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
52063
  {
52064
    { 0, 0, 0, 0 },
52065
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
52066
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1930200 }
52067
  },
52068
/* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
52069
  {
52070
    { 0, 0, 0, 0 },
52071
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
52072
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1932200 }
52073
  },
52074
/* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
52075
  {
52076
    { 0, 0, 0, 0 },
52077
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
52078
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1933200 }
52079
  },
52080
/* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
52081
  {
52082
    { 0, 0, 0, 0 },
52083
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
52084
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1950200 }
52085
  },
52086
/* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
52087
  {
52088
    { 0, 0, 0, 0 },
52089
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
52090
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1952200 }
52091
  },
52092
/* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
52093
  {
52094
    { 0, 0, 0, 0 },
52095
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
52096
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1953200 }
52097
  },
52098
/* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
52099
  {
52100
    { 0, 0, 0, 0 },
52101
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
52102
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1970200 }
52103
  },
52104
/* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
52105
  {
52106
    { 0, 0, 0, 0 },
52107
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
52108
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1972200 }
52109
  },
52110
/* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
52111
  {
52112
    { 0, 0, 0, 0 },
52113
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
52114
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1973200 }
52115
  },
52116
/* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
52117
  {
52118
    { 0, 0, 0, 0 },
52119
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
52120
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x1938200 }
52121
  },
52122
/* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
52123
  {
52124
    { 0, 0, 0, 0 },
52125
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
52126
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x193a200 }
52127
  },
52128
/* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
52129
  {
52130
    { 0, 0, 0, 0 },
52131
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
52132
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x193b200 }
52133
  },
52134
/* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
52135
  {
52136
    { 0, 0, 0, 0 },
52137
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
52138
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x1958200 }
52139
  },
52140
/* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
52141
  {
52142
    { 0, 0, 0, 0 },
52143
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
52144
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x195a200 }
52145
  },
52146
/* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
52147
  {
52148
    { 0, 0, 0, 0 },
52149
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
52150
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x195b200 }
52151
  },
52152
/* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
52153
  {
52154
    { 0, 0, 0, 0 },
52155
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
52156
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193c200 }
52157
  },
52158
/* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
52159
  {
52160
    { 0, 0, 0, 0 },
52161
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
52162
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193e200 }
52163
  },
52164
/* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
52165
  {
52166
    { 0, 0, 0, 0 },
52167
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
52168
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193f200 }
52169
  },
52170
/* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
52171
  {
52172
    { 0, 0, 0, 0 },
52173
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
52174
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195c200 }
52175
  },
52176
/* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
52177
  {
52178
    { 0, 0, 0, 0 },
52179
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
52180
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195e200 }
52181
  },
52182
/* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
52183
  {
52184
    { 0, 0, 0, 0 },
52185
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
52186
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195f200 }
52187
  },
52188
/* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
52189
  {
52190
    { 0, 0, 0, 0 },
52191
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
52192
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197c200 }
52193
  },
52194
/* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
52195
  {
52196
    { 0, 0, 0, 0 },
52197
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
52198
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197e200 }
52199
  },
52200
/* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
52201
  {
52202
    { 0, 0, 0, 0 },
52203
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
52204
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197f200 }
52205
  },
52206
/* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
52207
  {
52208
    { 0, 0, 0, 0 },
52209
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
52210
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x1978200 }
52211
  },
52212
/* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
52213
  {
52214
    { 0, 0, 0, 0 },
52215
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
52216
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x197a200 }
52217
  },
52218
/* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
52219
  {
52220
    { 0, 0, 0, 0 },
52221
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
52222
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x197b200 }
52223
  },
52224
/* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
52225
  {
52226
    { 0, 0, 0, 0 },
52227
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
52228
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a90200 }
52229
  },
52230
/* dsub.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
52231
  {
52232
    { 0, 0, 0, 0 },
52233
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
52234
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a92200 }
52235
  },
52236
/* dsub.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
52237
  {
52238
    { 0, 0, 0, 0 },
52239
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
52240
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a93200 }
52241
  },
52242
/* dsub.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */
52243
  {
52244
    { 0, 0, 0, 0 },
52245
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32RNPREFIXEDHI), 0 } },
52246
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b93200 }
52247
  },
52248
/* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
52249
  {
52250
    { 0, 0, 0, 0 },
52251
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
52252
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a18200 }
52253
  },
52254
/* dsub.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
52255
  {
52256
    { 0, 0, 0, 0 },
52257
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
52258
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a1a200 }
52259
  },
52260
/* dsub.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
52261
  {
52262
    { 0, 0, 0, 0 },
52263
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
52264
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a1b200 }
52265
  },
52266
/* dsub.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */
52267
  {
52268
    { 0, 0, 0, 0 },
52269
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32ANPREFIXEDHI), 0 } },
52270
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b1b200 }
52271
  },
52272
/* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
52273
  {
52274
    { 0, 0, 0, 0 },
52275
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
52276
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a10200 }
52277
  },
52278
/* dsub.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
52279
  {
52280
    { 0, 0, 0, 0 },
52281
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
52282
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a12200 }
52283
  },
52284
/* dsub.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
52285
  {
52286
    { 0, 0, 0, 0 },
52287
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
52288
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a13200 }
52289
  },
52290
/* dsub.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
52291
  {
52292
    { 0, 0, 0, 0 },
52293
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
52294
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b13200 }
52295
  },
52296
/* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
52297
  {
52298
    { 0, 0, 0, 0 },
52299
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
52300
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a30200 }
52301
  },
52302
/* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
52303
  {
52304
    { 0, 0, 0, 0 },
52305
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
52306
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a32200 }
52307
  },
52308
/* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
52309
  {
52310
    { 0, 0, 0, 0 },
52311
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
52312
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a33200 }
52313
  },
52314
/* dsub.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
52315
  {
52316
    { 0, 0, 0, 0 },
52317
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
52318
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1b33200 }
52319
  },
52320
/* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
52321
  {
52322
    { 0, 0, 0, 0 },
52323
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
52324
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a50200 }
52325
  },
52326
/* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
52327
  {
52328
    { 0, 0, 0, 0 },
52329
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
52330
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a52200 }
52331
  },
52332
/* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
52333
  {
52334
    { 0, 0, 0, 0 },
52335
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
52336
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a53200 }
52337
  },
52338
/* dsub.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
52339
  {
52340
    { 0, 0, 0, 0 },
52341
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
52342
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1b53200 }
52343
  },
52344
/* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
52345
  {
52346
    { 0, 0, 0, 0 },
52347
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
52348
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a70200 }
52349
  },
52350
/* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
52351
  {
52352
    { 0, 0, 0, 0 },
52353
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
52354
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a72200 }
52355
  },
52356
/* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
52357
  {
52358
    { 0, 0, 0, 0 },
52359
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
52360
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a73200 }
52361
  },
52362
/* dsub.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
52363
  {
52364
    { 0, 0, 0, 0 },
52365
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
52366
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1b73200 }
52367
  },
52368
/* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
52369
  {
52370
    { 0, 0, 0, 0 },
52371
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
52372
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a38200 }
52373
  },
52374
/* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
52375
  {
52376
    { 0, 0, 0, 0 },
52377
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
52378
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a3a200 }
52379
  },
52380
/* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
52381
  {
52382
    { 0, 0, 0, 0 },
52383
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
52384
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a3b200 }
52385
  },
52386
/* dsub.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
52387
  {
52388
    { 0, 0, 0, 0 },
52389
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
52390
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1b3b200 }
52391
  },
52392
/* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
52393
  {
52394
    { 0, 0, 0, 0 },
52395
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
52396
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a58200 }
52397
  },
52398
/* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
52399
  {
52400
    { 0, 0, 0, 0 },
52401
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
52402
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a5a200 }
52403
  },
52404
/* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
52405
  {
52406
    { 0, 0, 0, 0 },
52407
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
52408
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a5b200 }
52409
  },
52410
/* dsub.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
52411
  {
52412
    { 0, 0, 0, 0 },
52413
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
52414
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1b5b200 }
52415
  },
52416
/* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
52417
  {
52418
    { 0, 0, 0, 0 },
52419
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
52420
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3c200 }
52421
  },
52422
/* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
52423
  {
52424
    { 0, 0, 0, 0 },
52425
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
52426
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3e200 }
52427
  },
52428
/* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
52429
  {
52430
    { 0, 0, 0, 0 },
52431
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
52432
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3f200 }
52433
  },
52434
/* dsub.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
52435
  {
52436
    { 0, 0, 0, 0 },
52437
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
52438
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1b3f200 }
52439
  },
52440
/* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
52441
  {
52442
    { 0, 0, 0, 0 },
52443
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
52444
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5c200 }
52445
  },
52446
/* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
52447
  {
52448
    { 0, 0, 0, 0 },
52449
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
52450
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5e200 }
52451
  },
52452
/* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
52453
  {
52454
    { 0, 0, 0, 0 },
52455
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
52456
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5f200 }
52457
  },
52458
/* dsub.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
52459
  {
52460
    { 0, 0, 0, 0 },
52461
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
52462
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1b5f200 }
52463
  },
52464
/* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
52465
  {
52466
    { 0, 0, 0, 0 },
52467
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
52468
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7c200 }
52469
  },
52470
/* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
52471
  {
52472
    { 0, 0, 0, 0 },
52473
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), 0 } },
52474
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7e200 }
52475
  },
52476
/* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
52477
  {
52478
    { 0, 0, 0, 0 },
52479
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), 0 } },
52480
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7f200 }
52481
  },
52482
/* dsub.w${X} ${Dsp-24-u16},${Dsp-40-u16} */
52483
  {
52484
    { 0, 0, 0, 0 },
52485
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), 0 } },
52486
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1b7f200 }
52487
  },
52488
/* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
52489
  {
52490
    { 0, 0, 0, 0 },
52491
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
52492
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a78200 }
52493
  },
52494
/* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
52495
  {
52496
    { 0, 0, 0, 0 },
52497
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), 0 } },
52498
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a7a200 }
52499
  },
52500
/* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
52501
  {
52502
    { 0, 0, 0, 0 },
52503
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), 0 } },
52504
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a7b200 }
52505
  },
52506
/* dsub.w${X} ${Dsp-24-u16},${Dsp-40-u24} */
52507
  {
52508
    { 0, 0, 0, 0 },
52509
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), 0 } },
52510
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1b7b200 }
52511
  },
52512
/* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
52513
  {
52514
    { 0, 0, 0, 0 },
52515
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
52516
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b90200 }
52517
  },
52518
/* dsub.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */
52519
  {
52520
    { 0, 0, 0, 0 },
52521
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32RNPREFIXEDHI), 0 } },
52522
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b92200 }
52523
  },
52524
/* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
52525
  {
52526
    { 0, 0, 0, 0 },
52527
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
52528
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b18200 }
52529
  },
52530
/* dsub.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */
52531
  {
52532
    { 0, 0, 0, 0 },
52533
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32ANPREFIXEDHI), 0 } },
52534
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b1a200 }
52535
  },
52536
/* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
52537
  {
52538
    { 0, 0, 0, 0 },
52539
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
52540
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b10200 }
52541
  },
52542
/* dsub.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
52543
  {
52544
    { 0, 0, 0, 0 },
52545
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
52546
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b12200 }
52547
  },
52548
/* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
52549
  {
52550
    { 0, 0, 0, 0 },
52551
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
52552
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b30200 }
52553
  },
52554
/* dsub.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
52555
  {
52556
    { 0, 0, 0, 0 },
52557
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
52558
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b32200 }
52559
  },
52560
/* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
52561
  {
52562
    { 0, 0, 0, 0 },
52563
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
52564
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b50200 }
52565
  },
52566
/* dsub.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
52567
  {
52568
    { 0, 0, 0, 0 },
52569
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
52570
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b52200 }
52571
  },
52572
/* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
52573
  {
52574
    { 0, 0, 0, 0 },
52575
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
52576
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b70200 }
52577
  },
52578
/* dsub.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
52579
  {
52580
    { 0, 0, 0, 0 },
52581
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
52582
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b72200 }
52583
  },
52584
/* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
52585
  {
52586
    { 0, 0, 0, 0 },
52587
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
52588
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b38200 }
52589
  },
52590
/* dsub.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
52591
  {
52592
    { 0, 0, 0, 0 },
52593
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
52594
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b3a200 }
52595
  },
52596
/* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
52597
  {
52598
    { 0, 0, 0, 0 },
52599
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
52600
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b58200 }
52601
  },
52602
/* dsub.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
52603
  {
52604
    { 0, 0, 0, 0 },
52605
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
52606
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b5a200 }
52607
  },
52608
/* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
52609
  {
52610
    { 0, 0, 0, 0 },
52611
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
52612
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b3c200 }
52613
  },
52614
/* dsub.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
52615
  {
52616
    { 0, 0, 0, 0 },
52617
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
52618
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b3e200 }
52619
  },
52620
/* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
52621
  {
52622
    { 0, 0, 0, 0 },
52623
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
52624
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b5c200 }
52625
  },
52626
/* dsub.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
52627
  {
52628
    { 0, 0, 0, 0 },
52629
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
52630
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b5e200 }
52631
  },
52632
/* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
52633
  {
52634
    { 0, 0, 0, 0 },
52635
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), 0 } },
52636
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_absolute_Prefixed_HI, { 0x1b7c200 }
52637
  },
52638
/* dsub.w${X} ${Dsp-24-u24},${Dsp-48-u16} */
52639
  {
52640
    { 0, 0, 0, 0 },
52641
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), 0 } },
52642
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_absolute_Prefixed_HI, { 0x1b7e200 }
52643
  },
52644
/* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
52645
  {
52646
    { 0, 0, 0, 0 },
52647
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), 0 } },
52648
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_24_absolute_Prefixed_HI, { 0x1b78200 }
52649
  },
52650
/* dsub.w${X} ${Dsp-24-u24},${Dsp-48-u24} */
52651
  {
52652
    { 0, 0, 0, 0 },
52653
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), 0 } },
52654
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_24_absolute_Prefixed_HI, { 0x1b7a200 }
52655
  },
52656
/* dsub.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */
52657
  {
52658
    { 0, 0, 0, 0 },
52659
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DST32RNPREFIXEDHI), 0 } },
52660
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1c902 }
52661
  },
52662
/* dsub.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */
52663
  {
52664
    { 0, 0, 0, 0 },
52665
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DST32RNPREFIXEDHI), 0 } },
52666
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x18922 }
52667
  },
52668
/* dsub.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */
52669
  {
52670
    { 0, 0, 0, 0 },
52671
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
52672
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x18902 }
52673
  },
52674
/* dsub.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */
52675
  {
52676
    { 0, 0, 0, 0 },
52677
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DST32ANPREFIXEDHI), 0 } },
52678
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1c182 }
52679
  },
52680
/* dsub.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */
52681
  {
52682
    { 0, 0, 0, 0 },
52683
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DST32ANPREFIXEDHI), 0 } },
52684
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x181a2 }
52685
  },
52686
/* dsub.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */
52687
  {
52688
    { 0, 0, 0, 0 },
52689
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
52690
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x18182 }
52691
  },
52692
/* dsub.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */
52693
  {
52694
    { 0, 0, 0, 0 },
52695
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
52696
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1c102 }
52697
  },
52698
/* dsub.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */
52699
  {
52700
    { 0, 0, 0, 0 },
52701
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
52702
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x18122 }
52703
  },
52704
/* dsub.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
52705
  {
52706
    { 0, 0, 0, 0 },
52707
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
52708
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x18102 }
52709
  },
52710
/* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
52711
  {
52712
    { 0, 0, 0, 0 },
52713
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
52714
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1c30200 }
52715
  },
52716
/* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
52717
  {
52718
    { 0, 0, 0, 0 },
52719
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
52720
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1832200 }
52721
  },
52722
/* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
52723
  {
52724
    { 0, 0, 0, 0 },
52725
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
52726
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1830200 }
52727
  },
52728
/* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
52729
  {
52730
    { 0, 0, 0, 0 },
52731
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
52732
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1c50200 }
52733
  },
52734
/* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
52735
  {
52736
    { 0, 0, 0, 0 },
52737
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
52738
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1852200 }
52739
  },
52740
/* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
52741
  {
52742
    { 0, 0, 0, 0 },
52743
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
52744
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1850200 }
52745
  },
52746
/* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
52747
  {
52748
    { 0, 0, 0, 0 },
52749
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
52750
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1c70200 }
52751
  },
52752
/* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
52753
  {
52754
    { 0, 0, 0, 0 },
52755
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
52756
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1872200 }
52757
  },
52758
/* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
52759
  {
52760
    { 0, 0, 0, 0 },
52761
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
52762
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1870200 }
52763
  },
52764
/* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */
52765
  {
52766
    { 0, 0, 0, 0 },
52767
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
52768
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1c38200 }
52769
  },
52770
/* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */
52771
  {
52772
    { 0, 0, 0, 0 },
52773
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
52774
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x183a200 }
52775
  },
52776
/* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
52777
  {
52778
    { 0, 0, 0, 0 },
52779
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
52780
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1838200 }
52781
  },
52782
/* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */
52783
  {
52784
    { 0, 0, 0, 0 },
52785
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
52786
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1c58200 }
52787
  },
52788
/* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */
52789
  {
52790
    { 0, 0, 0, 0 },
52791
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
52792
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x185a200 }
52793
  },
52794
/* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
52795
  {
52796
    { 0, 0, 0, 0 },
52797
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
52798
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1858200 }
52799
  },
52800
/* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */
52801
  {
52802
    { 0, 0, 0, 0 },
52803
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
52804
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x1c3c200 }
52805
  },
52806
/* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */
52807
  {
52808
    { 0, 0, 0, 0 },
52809
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
52810
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x183e200 }
52811
  },
52812
/* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
52813
  {
52814
    { 0, 0, 0, 0 },
52815
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
52816
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x183c200 }
52817
  },
52818
/* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */
52819
  {
52820
    { 0, 0, 0, 0 },
52821
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
52822
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x1c5c200 }
52823
  },
52824
/* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */
52825
  {
52826
    { 0, 0, 0, 0 },
52827
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
52828
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x185e200 }
52829
  },
52830
/* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
52831
  {
52832
    { 0, 0, 0, 0 },
52833
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
52834
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x185c200 }
52835
  },
52836
/* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */
52837
  {
52838
    { 0, 0, 0, 0 },
52839
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), 0 } },
52840
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x1c7c200 }
52841
  },
52842
/* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */
52843
  {
52844
    { 0, 0, 0, 0 },
52845
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), 0 } },
52846
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x187e200 }
52847
  },
52848
/* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */
52849
  {
52850
    { 0, 0, 0, 0 },
52851
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
52852
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x187c200 }
52853
  },
52854
/* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */
52855
  {
52856
    { 0, 0, 0, 0 },
52857
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U24), 0 } },
52858
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x1c78200 }
52859
  },
52860
/* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */
52861
  {
52862
    { 0, 0, 0, 0 },
52863
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U24), 0 } },
52864
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x187a200 }
52865
  },
52866
/* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */
52867
  {
52868
    { 0, 0, 0, 0 },
52869
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
52870
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x1878200 }
52871
  },
52872
/* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
52873
  {
52874
    { 0, 0, 0, 0 },
52875
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
52876
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1980200 }
52877
  },
52878
/* dsub.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */
52879
  {
52880
    { 0, 0, 0, 0 },
52881
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
52882
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1982200 }
52883
  },
52884
/* dsub.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */
52885
  {
52886
    { 0, 0, 0, 0 },
52887
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
52888
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1983200 }
52889
  },
52890
/* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
52891
  {
52892
    { 0, 0, 0, 0 },
52893
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
52894
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1908200 }
52895
  },
52896
/* dsub.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */
52897
  {
52898
    { 0, 0, 0, 0 },
52899
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
52900
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x190a200 }
52901
  },
52902
/* dsub.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */
52903
  {
52904
    { 0, 0, 0, 0 },
52905
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
52906
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x190b200 }
52907
  },
52908
/* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
52909
  {
52910
    { 0, 0, 0, 0 },
52911
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
52912
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1900200 }
52913
  },
52914
/* dsub.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
52915
  {
52916
    { 0, 0, 0, 0 },
52917
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
52918
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1902200 }
52919
  },
52920
/* dsub.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
52921
  {
52922
    { 0, 0, 0, 0 },
52923
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
52924
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1903200 }
52925
  },
52926
/* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
52927
  {
52928
    { 0, 0, 0, 0 },
52929
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
52930
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1920200 }
52931
  },
52932
/* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
52933
  {
52934
    { 0, 0, 0, 0 },
52935
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
52936
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1922200 }
52937
  },
52938
/* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
52939
  {
52940
    { 0, 0, 0, 0 },
52941
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
52942
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1923200 }
52943
  },
52944
/* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
52945
  {
52946
    { 0, 0, 0, 0 },
52947
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
52948
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1940200 }
52949
  },
52950
/* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
52951
  {
52952
    { 0, 0, 0, 0 },
52953
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
52954
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1942200 }
52955
  },
52956
/* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
52957
  {
52958
    { 0, 0, 0, 0 },
52959
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
52960
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1943200 }
52961
  },
52962
/* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
52963
  {
52964
    { 0, 0, 0, 0 },
52965
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
52966
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1960200 }
52967
  },
52968
/* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
52969
  {
52970
    { 0, 0, 0, 0 },
52971
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
52972
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1962200 }
52973
  },
52974
/* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
52975
  {
52976
    { 0, 0, 0, 0 },
52977
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
52978
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1963200 }
52979
  },
52980
/* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
52981
  {
52982
    { 0, 0, 0, 0 },
52983
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
52984
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x1928200 }
52985
  },
52986
/* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
52987
  {
52988
    { 0, 0, 0, 0 },
52989
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
52990
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x192a200 }
52991
  },
52992
/* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
52993
  {
52994
    { 0, 0, 0, 0 },
52995
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
52996
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x192b200 }
52997
  },
52998
/* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
52999
  {
53000
    { 0, 0, 0, 0 },
53001
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
53002
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x1948200 }
53003
  },
53004
/* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
53005
  {
53006
    { 0, 0, 0, 0 },
53007
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
53008
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x194a200 }
53009
  },
53010
/* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
53011
  {
53012
    { 0, 0, 0, 0 },
53013
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
53014
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x194b200 }
53015
  },
53016
/* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
53017
  {
53018
    { 0, 0, 0, 0 },
53019
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
53020
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192c200 }
53021
  },
53022
/* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
53023
  {
53024
    { 0, 0, 0, 0 },
53025
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
53026
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192e200 }
53027
  },
53028
/* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
53029
  {
53030
    { 0, 0, 0, 0 },
53031
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
53032
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192f200 }
53033
  },
53034
/* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
53035
  {
53036
    { 0, 0, 0, 0 },
53037
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
53038
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194c200 }
53039
  },
53040
/* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
53041
  {
53042
    { 0, 0, 0, 0 },
53043
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
53044
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194e200 }
53045
  },
53046
/* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
53047
  {
53048
    { 0, 0, 0, 0 },
53049
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
53050
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194f200 }
53051
  },
53052
/* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
53053
  {
53054
    { 0, 0, 0, 0 },
53055
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
53056
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196c200 }
53057
  },
53058
/* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
53059
  {
53060
    { 0, 0, 0, 0 },
53061
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
53062
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196e200 }
53063
  },
53064
/* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
53065
  {
53066
    { 0, 0, 0, 0 },
53067
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
53068
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196f200 }
53069
  },
53070
/* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
53071
  {
53072
    { 0, 0, 0, 0 },
53073
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
53074
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x1968200 }
53075
  },
53076
/* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
53077
  {
53078
    { 0, 0, 0, 0 },
53079
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
53080
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x196a200 }
53081
  },
53082
/* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
53083
  {
53084
    { 0, 0, 0, 0 },
53085
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
53086
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x196b200 }
53087
  },
53088
/* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
53089
  {
53090
    { 0, 0, 0, 0 },
53091
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
53092
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a80200 }
53093
  },
53094
/* dsub.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */
53095
  {
53096
    { 0, 0, 0, 0 },
53097
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
53098
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a82200 }
53099
  },
53100
/* dsub.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */
53101
  {
53102
    { 0, 0, 0, 0 },
53103
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
53104
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a83200 }
53105
  },
53106
/* dsub.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */
53107
  {
53108
    { 0, 0, 0, 0 },
53109
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32RNPREFIXEDQI), 0 } },
53110
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b83200 }
53111
  },
53112
/* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
53113
  {
53114
    { 0, 0, 0, 0 },
53115
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
53116
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a08200 }
53117
  },
53118
/* dsub.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */
53119
  {
53120
    { 0, 0, 0, 0 },
53121
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
53122
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a0a200 }
53123
  },
53124
/* dsub.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */
53125
  {
53126
    { 0, 0, 0, 0 },
53127
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
53128
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a0b200 }
53129
  },
53130
/* dsub.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */
53131
  {
53132
    { 0, 0, 0, 0 },
53133
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32ANPREFIXEDQI), 0 } },
53134
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b0b200 }
53135
  },
53136
/* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
53137
  {
53138
    { 0, 0, 0, 0 },
53139
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
53140
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a00200 }
53141
  },
53142
/* dsub.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
53143
  {
53144
    { 0, 0, 0, 0 },
53145
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
53146
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a02200 }
53147
  },
53148
/* dsub.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
53149
  {
53150
    { 0, 0, 0, 0 },
53151
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
53152
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a03200 }
53153
  },
53154
/* dsub.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
53155
  {
53156
    { 0, 0, 0, 0 },
53157
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
53158
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b03200 }
53159
  },
53160
/* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
53161
  {
53162
    { 0, 0, 0, 0 },
53163
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
53164
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a20200 }
53165
  },
53166
/* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
53167
  {
53168
    { 0, 0, 0, 0 },
53169
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
53170
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a22200 }
53171
  },
53172
/* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
53173
  {
53174
    { 0, 0, 0, 0 },
53175
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
53176
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a23200 }
53177
  },
53178
/* dsub.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
53179
  {
53180
    { 0, 0, 0, 0 },
53181
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
53182
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1b23200 }
53183
  },
53184
/* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
53185
  {
53186
    { 0, 0, 0, 0 },
53187
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
53188
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a40200 }
53189
  },
53190
/* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
53191
  {
53192
    { 0, 0, 0, 0 },
53193
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
53194
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a42200 }
53195
  },
53196
/* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
53197
  {
53198
    { 0, 0, 0, 0 },
53199
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
53200
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a43200 }
53201
  },
53202
/* dsub.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
53203
  {
53204
    { 0, 0, 0, 0 },
53205
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
53206
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1b43200 }
53207
  },
53208
/* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
53209
  {
53210
    { 0, 0, 0, 0 },
53211
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
53212
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a60200 }
53213
  },
53214
/* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
53215
  {
53216
    { 0, 0, 0, 0 },
53217
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
53218
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a62200 }
53219
  },
53220
/* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
53221
  {
53222
    { 0, 0, 0, 0 },
53223
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
53224
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a63200 }
53225
  },
53226
/* dsub.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
53227
  {
53228
    { 0, 0, 0, 0 },
53229
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
53230
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1b63200 }
53231
  },
53232
/* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
53233
  {
53234
    { 0, 0, 0, 0 },
53235
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
53236
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a28200 }
53237
  },
53238
/* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
53239
  {
53240
    { 0, 0, 0, 0 },
53241
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
53242
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a2a200 }
53243
  },
53244
/* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
53245
  {
53246
    { 0, 0, 0, 0 },
53247
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
53248
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a2b200 }
53249
  },
53250
/* dsub.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
53251
  {
53252
    { 0, 0, 0, 0 },
53253
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
53254
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1b2b200 }
53255
  },
53256
/* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
53257
  {
53258
    { 0, 0, 0, 0 },
53259
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
53260
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a48200 }
53261
  },
53262
/* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
53263
  {
53264
    { 0, 0, 0, 0 },
53265
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
53266
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a4a200 }
53267
  },
53268
/* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
53269
  {
53270
    { 0, 0, 0, 0 },
53271
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
53272
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a4b200 }
53273
  },
53274
/* dsub.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
53275
  {
53276
    { 0, 0, 0, 0 },
53277
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
53278
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1b4b200 }
53279
  },
53280
/* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
53281
  {
53282
    { 0, 0, 0, 0 },
53283
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
53284
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2c200 }
53285
  },
53286
/* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
53287
  {
53288
    { 0, 0, 0, 0 },
53289
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
53290
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2e200 }
53291
  },
53292
/* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
53293
  {
53294
    { 0, 0, 0, 0 },
53295
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
53296
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2f200 }
53297
  },
53298
/* dsub.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
53299
  {
53300
    { 0, 0, 0, 0 },
53301
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
53302
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1b2f200 }
53303
  },
53304
/* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
53305
  {
53306
    { 0, 0, 0, 0 },
53307
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
53308
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4c200 }
53309
  },
53310
/* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
53311
  {
53312
    { 0, 0, 0, 0 },
53313
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
53314
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4e200 }
53315
  },
53316
/* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
53317
  {
53318
    { 0, 0, 0, 0 },
53319
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
53320
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4f200 }
53321
  },
53322
/* dsub.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
53323
  {
53324
    { 0, 0, 0, 0 },
53325
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
53326
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1b4f200 }
53327
  },
53328
/* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
53329
  {
53330
    { 0, 0, 0, 0 },
53331
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
53332
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6c200 }
53333
  },
53334
/* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
53335
  {
53336
    { 0, 0, 0, 0 },
53337
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), 0 } },
53338
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6e200 }
53339
  },
53340
/* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
53341
  {
53342
    { 0, 0, 0, 0 },
53343
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), 0 } },
53344
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6f200 }
53345
  },
53346
/* dsub.b${X} ${Dsp-24-u16},${Dsp-40-u16} */
53347
  {
53348
    { 0, 0, 0, 0 },
53349
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), 0 } },
53350
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1b6f200 }
53351
  },
53352
/* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
53353
  {
53354
    { 0, 0, 0, 0 },
53355
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
53356
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a68200 }
53357
  },
53358
/* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
53359
  {
53360
    { 0, 0, 0, 0 },
53361
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), 0 } },
53362
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a6a200 }
53363
  },
53364
/* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
53365
  {
53366
    { 0, 0, 0, 0 },
53367
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), 0 } },
53368
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a6b200 }
53369
  },
53370
/* dsub.b${X} ${Dsp-24-u16},${Dsp-40-u24} */
53371
  {
53372
    { 0, 0, 0, 0 },
53373
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), 0 } },
53374
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1b6b200 }
53375
  },
53376
/* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
53377
  {
53378
    { 0, 0, 0, 0 },
53379
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
53380
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b80200 }
53381
  },
53382
/* dsub.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */
53383
  {
53384
    { 0, 0, 0, 0 },
53385
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32RNPREFIXEDQI), 0 } },
53386
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b82200 }
53387
  },
53388
/* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
53389
  {
53390
    { 0, 0, 0, 0 },
53391
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
53392
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b08200 }
53393
  },
53394
/* dsub.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */
53395
  {
53396
    { 0, 0, 0, 0 },
53397
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32ANPREFIXEDQI), 0 } },
53398
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b0a200 }
53399
  },
53400
/* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
53401
  {
53402
    { 0, 0, 0, 0 },
53403
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
53404
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b00200 }
53405
  },
53406
/* dsub.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
53407
  {
53408
    { 0, 0, 0, 0 },
53409
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
53410
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b02200 }
53411
  },
53412
/* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
53413
  {
53414
    { 0, 0, 0, 0 },
53415
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
53416
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_An_relative_Prefixed_QI, { 0x1b20200 }
53417
  },
53418
/* dsub.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
53419
  {
53420
    { 0, 0, 0, 0 },
53421
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
53422
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_An_relative_Prefixed_QI, { 0x1b22200 }
53423
  },
53424
/* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
53425
  {
53426
    { 0, 0, 0, 0 },
53427
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
53428
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_An_relative_Prefixed_QI, { 0x1b40200 }
53429
  },
53430
/* dsub.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
53431
  {
53432
    { 0, 0, 0, 0 },
53433
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
53434
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_An_relative_Prefixed_QI, { 0x1b42200 }
53435
  },
53436
/* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
53437
  {
53438
    { 0, 0, 0, 0 },
53439
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
53440
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_An_relative_Prefixed_QI, { 0x1b60200 }
53441
  },
53442
/* dsub.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
53443
  {
53444
    { 0, 0, 0, 0 },
53445
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
53446
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_An_relative_Prefixed_QI, { 0x1b62200 }
53447
  },
53448
/* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
53449
  {
53450
    { 0, 0, 0, 0 },
53451
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
53452
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_QI, { 0x1b28200 }
53453
  },
53454
/* dsub.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
53455
  {
53456
    { 0, 0, 0, 0 },
53457
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
53458
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_QI, { 0x1b2a200 }
53459
  },
53460
/* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
53461
  {
53462
    { 0, 0, 0, 0 },
53463
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
53464
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_QI, { 0x1b48200 }
53465
  },
53466
/* dsub.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
53467
  {
53468
    { 0, 0, 0, 0 },
53469
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
53470
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_QI, { 0x1b4a200 }
53471
  },
53472
/* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
53473
  {
53474
    { 0, 0, 0, 0 },
53475
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
53476
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_QI, { 0x1b2c200 }
53477
  },
53478
/* dsub.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
53479
  {
53480
    { 0, 0, 0, 0 },
53481
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
53482
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_QI, { 0x1b2e200 }
53483
  },
53484
/* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
53485
  {
53486
    { 0, 0, 0, 0 },
53487
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
53488
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_QI, { 0x1b4c200 }
53489
  },
53490
/* dsub.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
53491
  {
53492
    { 0, 0, 0, 0 },
53493
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
53494
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_QI, { 0x1b4e200 }
53495
  },
53496
/* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
53497
  {
53498
    { 0, 0, 0, 0 },
53499
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), 0 } },
53500
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_absolute_Prefixed_QI, { 0x1b6c200 }
53501
  },
53502
/* dsub.b${X} ${Dsp-24-u24},${Dsp-48-u16} */
53503
  {
53504
    { 0, 0, 0, 0 },
53505
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), 0 } },
53506
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_absolute_Prefixed_QI, { 0x1b6e200 }
53507
  },
53508
/* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
53509
  {
53510
    { 0, 0, 0, 0 },
53511
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), 0 } },
53512
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_absolute_Prefixed_QI, { 0x1b68200 }
53513
  },
53514
/* dsub.b${X} ${Dsp-24-u24},${Dsp-48-u24} */
53515
  {
53516
    { 0, 0, 0, 0 },
53517
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), 0 } },
53518
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_absolute_Prefixed_QI, { 0x1b6a200 }
53519
  },
53520
/* dsub.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */
53521
  {
53522
    { 0, 0, 0, 0 },
53523
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32RNPREFIXEDQI), 0 } },
53524
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1c802 }
53525
  },
53526
/* dsub.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */
53527
  {
53528
    { 0, 0, 0, 0 },
53529
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DST32RNPREFIXEDQI), 0 } },
53530
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x18822 }
53531
  },
53532
/* dsub.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */
53533
  {
53534
    { 0, 0, 0, 0 },
53535
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
53536
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x18802 }
53537
  },
53538
/* dsub.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */
53539
  {
53540
    { 0, 0, 0, 0 },
53541
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32ANPREFIXEDQI), 0 } },
53542
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1c082 }
53543
  },
53544
/* dsub.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */
53545
  {
53546
    { 0, 0, 0, 0 },
53547
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DST32ANPREFIXEDQI), 0 } },
53548
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x180a2 }
53549
  },
53550
/* dsub.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */
53551
  {
53552
    { 0, 0, 0, 0 },
53553
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
53554
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x18082 }
53555
  },
53556
/* dsub.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
53557
  {
53558
    { 0, 0, 0, 0 },
53559
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
53560
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1c002 }
53561
  },
53562
/* dsub.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */
53563
  {
53564
    { 0, 0, 0, 0 },
53565
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
53566
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x18022 }
53567
  },
53568
/* dsub.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
53569
  {
53570
    { 0, 0, 0, 0 },
53571
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
53572
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x18002 }
53573
  },
53574
/* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
53575
  {
53576
    { 0, 0, 0, 0 },
53577
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
53578
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1c20200 }
53579
  },
53580
/* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
53581
  {
53582
    { 0, 0, 0, 0 },
53583
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
53584
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1822200 }
53585
  },
53586
/* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
53587
  {
53588
    { 0, 0, 0, 0 },
53589
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
53590
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1820200 }
53591
  },
53592
/* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
53593
  {
53594
    { 0, 0, 0, 0 },
53595
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
53596
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1c40200 }
53597
  },
53598
/* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
53599
  {
53600
    { 0, 0, 0, 0 },
53601
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
53602
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1842200 }
53603
  },
53604
/* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
53605
  {
53606
    { 0, 0, 0, 0 },
53607
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
53608
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1840200 }
53609
  },
53610
/* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
53611
  {
53612
    { 0, 0, 0, 0 },
53613
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
53614
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1c60200 }
53615
  },
53616
/* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
53617
  {
53618
    { 0, 0, 0, 0 },
53619
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
53620
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1862200 }
53621
  },
53622
/* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
53623
  {
53624
    { 0, 0, 0, 0 },
53625
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
53626
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1860200 }
53627
  },
53628
/* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
53629
  {
53630
    { 0, 0, 0, 0 },
53631
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
53632
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x1c28200 }
53633
  },
53634
/* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */
53635
  {
53636
    { 0, 0, 0, 0 },
53637
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
53638
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x182a200 }
53639
  },
53640
/* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
53641
  {
53642
    { 0, 0, 0, 0 },
53643
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
53644
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x1828200 }
53645
  },
53646
/* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
53647
  {
53648
    { 0, 0, 0, 0 },
53649
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
53650
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x1c48200 }
53651
  },
53652
/* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */
53653
  {
53654
    { 0, 0, 0, 0 },
53655
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
53656
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x184a200 }
53657
  },
53658
/* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
53659
  {
53660
    { 0, 0, 0, 0 },
53661
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
53662
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x1848200 }
53663
  },
53664
/* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
53665
  {
53666
    { 0, 0, 0, 0 },
53667
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
53668
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x1c2c200 }
53669
  },
53670
/* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */
53671
  {
53672
    { 0, 0, 0, 0 },
53673
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
53674
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x182e200 }
53675
  },
53676
/* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
53677
  {
53678
    { 0, 0, 0, 0 },
53679
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
53680
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x182c200 }
53681
  },
53682
/* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
53683
  {
53684
    { 0, 0, 0, 0 },
53685
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
53686
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x1c4c200 }
53687
  },
53688
/* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */
53689
  {
53690
    { 0, 0, 0, 0 },
53691
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
53692
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x184e200 }
53693
  },
53694
/* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
53695
  {
53696
    { 0, 0, 0, 0 },
53697
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
53698
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x184c200 }
53699
  },
53700
/* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */
53701
  {
53702
    { 0, 0, 0, 0 },
53703
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), 0 } },
53704
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x1c6c200 }
53705
  },
53706
/* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */
53707
  {
53708
    { 0, 0, 0, 0 },
53709
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), 0 } },
53710
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x186e200 }
53711
  },
53712
/* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */
53713
  {
53714
    { 0, 0, 0, 0 },
53715
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
53716
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x186c200 }
53717
  },
53718
/* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */
53719
  {
53720
    { 0, 0, 0, 0 },
53721
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), 0 } },
53722
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x1c68200 }
53723
  },
53724
/* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */
53725
  {
53726
    { 0, 0, 0, 0 },
53727
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U24), 0 } },
53728
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x186a200 }
53729
  },
53730
/* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */
53731
  {
53732
    { 0, 0, 0, 0 },
53733
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
53734
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x1868200 }
53735
  },
53736
/* dsub.w${X} #${Imm-24-HI},$Dst32RnPrefixedHI */
53737
  {
53738
    { 0, 0, 0, 0 },
53739
    { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DST32RNPREFIXEDHI), 0 } },
53740
    & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_Rn_direct_Prefixed_HI, { 0x1991e00 }
53741
  },
53742
/* dsub.w${X} #${Imm-24-HI},$Dst32AnPrefixedHI */
53743
  {
53744
    { 0, 0, 0, 0 },
53745
    { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DST32ANPREFIXEDHI), 0 } },
53746
    & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_An_direct_Prefixed_HI, { 0x1919e00 }
53747
  },
53748
/* dsub.w${X} #${Imm-24-HI},[$Dst32AnPrefixed] */
53749
  {
53750
    { 0, 0, 0, 0 },
53751
    { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
53752
    & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_An_indirect_Prefixed_HI, { 0x1911e00 }
53753
  },
53754
/* dsub.w${X} #${Imm-32-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */
53755
  {
53756
    { 0, 0, 0, 0 },
53757
    { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
53758
    & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_An_relative_Prefixed_HI, { 0x1931e00 }
53759
  },
53760
/* dsub.w${X} #${Imm-32-HI},${Dsp-24-u8}[sb] */
53761
  {
53762
    { 0, 0, 0, 0 },
53763
    { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
53764
    & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_SB_relative_Prefixed_HI, { 0x1939e00 }
53765
  },
53766
/* dsub.w${X} #${Imm-32-HI},${Dsp-24-s8}[fb] */
53767
  {
53768
    { 0, 0, 0, 0 },
53769
    { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
53770
    & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_FB_relative_Prefixed_HI, { 0x193de00 }
53771
  },
53772
/* dsub.w${X} #${Imm-40-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */
53773
  {
53774
    { 0, 0, 0, 0 },
53775
    { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
53776
    & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_An_relative_Prefixed_HI, { 0x1951e00 }
53777
  },
53778
/* dsub.w${X} #${Imm-40-HI},${Dsp-24-u16}[sb] */
53779
  {
53780
    { 0, 0, 0, 0 },
53781
    { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
53782
    & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_SB_relative_Prefixed_HI, { 0x1959e00 }
53783
  },
53784
/* dsub.w${X} #${Imm-40-HI},${Dsp-24-s16}[fb] */
53785
  {
53786
    { 0, 0, 0, 0 },
53787
    { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
53788
    & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_FB_relative_Prefixed_HI, { 0x195de00 }
53789
  },
53790
/* dsub.w${X} #${Imm-40-HI},${Dsp-24-u16} */
53791
  {
53792
    { 0, 0, 0, 0 },
53793
    { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), 0 } },
53794
    & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_absolute_Prefixed_HI, { 0x197de00 }
53795
  },
53796
/* dsub.w${X} #${Imm-48-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */
53797
  {
53798
    { 0, 0, 0, 0 },
53799
    { { MNEM, OP (X), ' ', '#', OP (IMM_48_HI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
53800
    & ifmt_sbb32_w_imm_G_24_24_Prefixed_dst32_24_24_An_relative_Prefixed_HI, { 0x1971e00 }
53801
  },
53802
/* dsub.w${X} #${Imm-48-HI},${Dsp-24-u24} */
53803
  {
53804
    { 0, 0, 0, 0 },
53805
    { { MNEM, OP (X), ' ', '#', OP (IMM_48_HI), ',', OP (DSP_24_U24), 0 } },
53806
    & ifmt_sbb32_w_imm_G_24_24_Prefixed_dst32_24_24_absolute_Prefixed_HI, { 0x1979e00 }
53807
  },
53808
/* dsub.b${X} #${Imm-24-QI},$Dst32RnPrefixedQI */
53809
  {
53810
    { 0, 0, 0, 0 },
53811
    { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DST32RNPREFIXEDQI), 0 } },
53812
    & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_Rn_direct_Prefixed_QI, { 0x1981e00 }
53813
  },
53814
/* dsub.b${X} #${Imm-24-QI},$Dst32AnPrefixedQI */
53815
  {
53816
    { 0, 0, 0, 0 },
53817
    { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DST32ANPREFIXEDQI), 0 } },
53818
    & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_An_direct_Prefixed_QI, { 0x1909e00 }
53819
  },
53820
/* dsub.b${X} #${Imm-24-QI},[$Dst32AnPrefixed] */
53821
  {
53822
    { 0, 0, 0, 0 },
53823
    { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
53824
    & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_An_indirect_Prefixed_QI, { 0x1901e00 }
53825
  },
53826
/* dsub.b${X} #${Imm-32-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */
53827
  {
53828
    { 0, 0, 0, 0 },
53829
    { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
53830
    & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_An_relative_Prefixed_QI, { 0x1921e00 }
53831
  },
53832
/* dsub.b${X} #${Imm-32-QI},${Dsp-24-u8}[sb] */
53833
  {
53834
    { 0, 0, 0, 0 },
53835
    { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
53836
    & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_SB_relative_Prefixed_QI, { 0x1929e00 }
53837
  },
53838
/* dsub.b${X} #${Imm-32-QI},${Dsp-24-s8}[fb] */
53839
  {
53840
    { 0, 0, 0, 0 },
53841
    { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
53842
    & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_FB_relative_Prefixed_QI, { 0x192de00 }
53843
  },
53844
/* dsub.b${X} #${Imm-40-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */
53845
  {
53846
    { 0, 0, 0, 0 },
53847
    { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
53848
    & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_An_relative_Prefixed_QI, { 0x1941e00 }
53849
  },
53850
/* dsub.b${X} #${Imm-40-QI},${Dsp-24-u16}[sb] */
53851
  {
53852
    { 0, 0, 0, 0 },
53853
    { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
53854
    & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_SB_relative_Prefixed_QI, { 0x1949e00 }
53855
  },
53856
/* dsub.b${X} #${Imm-40-QI},${Dsp-24-s16}[fb] */
53857
  {
53858
    { 0, 0, 0, 0 },
53859
    { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
53860
    & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_FB_relative_Prefixed_QI, { 0x194de00 }
53861
  },
53862
/* dsub.b${X} #${Imm-40-QI},${Dsp-24-u16} */
53863
  {
53864
    { 0, 0, 0, 0 },
53865
    { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), 0 } },
53866
    & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_absolute_Prefixed_QI, { 0x196de00 }
53867
  },
53868
/* dsub.b${X} #${Imm-48-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */
53869
  {
53870
    { 0, 0, 0, 0 },
53871
    { { MNEM, OP (X), ' ', '#', OP (IMM_48_QI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
53872
    & ifmt_sbb32_b_imm_G_24_24_Prefixed_dst32_24_24_An_relative_Prefixed_QI, { 0x1961e00 }
53873
  },
53874
/* dsub.b${X} #${Imm-48-QI},${Dsp-24-u24} */
53875
  {
53876
    { 0, 0, 0, 0 },
53877
    { { MNEM, OP (X), ' ', '#', OP (IMM_48_QI), ',', OP (DSP_24_U24), 0 } },
53878
    & ifmt_sbb32_b_imm_G_24_24_Prefixed_dst32_24_24_absolute_Prefixed_QI, { 0x1969e00 }
53879
  },
53880
/* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
53881
  {
53882
    { 0, 0, 0, 0 },
53883
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
53884
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1990a00 }
53885
  },
53886
/* dsbb.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
53887
  {
53888
    { 0, 0, 0, 0 },
53889
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
53890
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1992a00 }
53891
  },
53892
/* dsbb.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
53893
  {
53894
    { 0, 0, 0, 0 },
53895
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
53896
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1993a00 }
53897
  },
53898
/* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
53899
  {
53900
    { 0, 0, 0, 0 },
53901
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
53902
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1918a00 }
53903
  },
53904
/* dsbb.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
53905
  {
53906
    { 0, 0, 0, 0 },
53907
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
53908
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x191aa00 }
53909
  },
53910
/* dsbb.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
53911
  {
53912
    { 0, 0, 0, 0 },
53913
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
53914
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x191ba00 }
53915
  },
53916
/* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
53917
  {
53918
    { 0, 0, 0, 0 },
53919
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
53920
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1910a00 }
53921
  },
53922
/* dsbb.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
53923
  {
53924
    { 0, 0, 0, 0 },
53925
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
53926
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1912a00 }
53927
  },
53928
/* dsbb.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
53929
  {
53930
    { 0, 0, 0, 0 },
53931
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
53932
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1913a00 }
53933
  },
53934
/* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
53935
  {
53936
    { 0, 0, 0, 0 },
53937
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
53938
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1930a00 }
53939
  },
53940
/* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
53941
  {
53942
    { 0, 0, 0, 0 },
53943
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
53944
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1932a00 }
53945
  },
53946
/* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
53947
  {
53948
    { 0, 0, 0, 0 },
53949
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
53950
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1933a00 }
53951
  },
53952
/* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
53953
  {
53954
    { 0, 0, 0, 0 },
53955
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
53956
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1950a00 }
53957
  },
53958
/* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
53959
  {
53960
    { 0, 0, 0, 0 },
53961
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
53962
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1952a00 }
53963
  },
53964
/* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
53965
  {
53966
    { 0, 0, 0, 0 },
53967
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
53968
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1953a00 }
53969
  },
53970
/* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
53971
  {
53972
    { 0, 0, 0, 0 },
53973
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
53974
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1970a00 }
53975
  },
53976
/* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
53977
  {
53978
    { 0, 0, 0, 0 },
53979
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
53980
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1972a00 }
53981
  },
53982
/* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
53983
  {
53984
    { 0, 0, 0, 0 },
53985
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
53986
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1973a00 }
53987
  },
53988
/* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
53989
  {
53990
    { 0, 0, 0, 0 },
53991
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
53992
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x1938a00 }
53993
  },
53994
/* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
53995
  {
53996
    { 0, 0, 0, 0 },
53997
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
53998
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x193aa00 }
53999
  },
54000
/* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
54001
  {
54002
    { 0, 0, 0, 0 },
54003
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
54004
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x193ba00 }
54005
  },
54006
/* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
54007
  {
54008
    { 0, 0, 0, 0 },
54009
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
54010
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x1958a00 }
54011
  },
54012
/* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
54013
  {
54014
    { 0, 0, 0, 0 },
54015
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
54016
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x195aa00 }
54017
  },
54018
/* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
54019
  {
54020
    { 0, 0, 0, 0 },
54021
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
54022
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x195ba00 }
54023
  },
54024
/* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
54025
  {
54026
    { 0, 0, 0, 0 },
54027
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
54028
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193ca00 }
54029
  },
54030
/* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
54031
  {
54032
    { 0, 0, 0, 0 },
54033
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
54034
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193ea00 }
54035
  },
54036
/* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
54037
  {
54038
    { 0, 0, 0, 0 },
54039
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
54040
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193fa00 }
54041
  },
54042
/* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
54043
  {
54044
    { 0, 0, 0, 0 },
54045
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
54046
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195ca00 }
54047
  },
54048
/* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
54049
  {
54050
    { 0, 0, 0, 0 },
54051
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
54052
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195ea00 }
54053
  },
54054
/* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
54055
  {
54056
    { 0, 0, 0, 0 },
54057
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
54058
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195fa00 }
54059
  },
54060
/* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
54061
  {
54062
    { 0, 0, 0, 0 },
54063
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
54064
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197ca00 }
54065
  },
54066
/* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
54067
  {
54068
    { 0, 0, 0, 0 },
54069
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
54070
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197ea00 }
54071
  },
54072
/* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
54073
  {
54074
    { 0, 0, 0, 0 },
54075
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
54076
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197fa00 }
54077
  },
54078
/* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
54079
  {
54080
    { 0, 0, 0, 0 },
54081
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
54082
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x1978a00 }
54083
  },
54084
/* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
54085
  {
54086
    { 0, 0, 0, 0 },
54087
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
54088
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x197aa00 }
54089
  },
54090
/* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
54091
  {
54092
    { 0, 0, 0, 0 },
54093
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
54094
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x197ba00 }
54095
  },
54096
/* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
54097
  {
54098
    { 0, 0, 0, 0 },
54099
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
54100
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a90a00 }
54101
  },
54102
/* dsbb.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
54103
  {
54104
    { 0, 0, 0, 0 },
54105
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
54106
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a92a00 }
54107
  },
54108
/* dsbb.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
54109
  {
54110
    { 0, 0, 0, 0 },
54111
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
54112
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a93a00 }
54113
  },
54114
/* dsbb.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */
54115
  {
54116
    { 0, 0, 0, 0 },
54117
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32RNPREFIXEDHI), 0 } },
54118
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b93a00 }
54119
  },
54120
/* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
54121
  {
54122
    { 0, 0, 0, 0 },
54123
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
54124
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a18a00 }
54125
  },
54126
/* dsbb.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
54127
  {
54128
    { 0, 0, 0, 0 },
54129
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
54130
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a1aa00 }
54131
  },
54132
/* dsbb.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
54133
  {
54134
    { 0, 0, 0, 0 },
54135
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
54136
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a1ba00 }
54137
  },
54138
/* dsbb.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */
54139
  {
54140
    { 0, 0, 0, 0 },
54141
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32ANPREFIXEDHI), 0 } },
54142
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b1ba00 }
54143
  },
54144
/* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
54145
  {
54146
    { 0, 0, 0, 0 },
54147
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
54148
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a10a00 }
54149
  },
54150
/* dsbb.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
54151
  {
54152
    { 0, 0, 0, 0 },
54153
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
54154
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a12a00 }
54155
  },
54156
/* dsbb.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
54157
  {
54158
    { 0, 0, 0, 0 },
54159
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
54160
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a13a00 }
54161
  },
54162
/* dsbb.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
54163
  {
54164
    { 0, 0, 0, 0 },
54165
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
54166
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b13a00 }
54167
  },
54168
/* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
54169
  {
54170
    { 0, 0, 0, 0 },
54171
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
54172
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a30a00 }
54173
  },
54174
/* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
54175
  {
54176
    { 0, 0, 0, 0 },
54177
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
54178
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a32a00 }
54179
  },
54180
/* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
54181
  {
54182
    { 0, 0, 0, 0 },
54183
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
54184
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a33a00 }
54185
  },
54186
/* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
54187
  {
54188
    { 0, 0, 0, 0 },
54189
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
54190
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1b33a00 }
54191
  },
54192
/* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
54193
  {
54194
    { 0, 0, 0, 0 },
54195
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
54196
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a50a00 }
54197
  },
54198
/* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
54199
  {
54200
    { 0, 0, 0, 0 },
54201
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
54202
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a52a00 }
54203
  },
54204
/* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
54205
  {
54206
    { 0, 0, 0, 0 },
54207
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
54208
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a53a00 }
54209
  },
54210
/* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
54211
  {
54212
    { 0, 0, 0, 0 },
54213
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
54214
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1b53a00 }
54215
  },
54216
/* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
54217
  {
54218
    { 0, 0, 0, 0 },
54219
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
54220
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a70a00 }
54221
  },
54222
/* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
54223
  {
54224
    { 0, 0, 0, 0 },
54225
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
54226
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a72a00 }
54227
  },
54228
/* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
54229
  {
54230
    { 0, 0, 0, 0 },
54231
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
54232
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a73a00 }
54233
  },
54234
/* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
54235
  {
54236
    { 0, 0, 0, 0 },
54237
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
54238
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1b73a00 }
54239
  },
54240
/* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
54241
  {
54242
    { 0, 0, 0, 0 },
54243
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
54244
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a38a00 }
54245
  },
54246
/* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
54247
  {
54248
    { 0, 0, 0, 0 },
54249
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
54250
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a3aa00 }
54251
  },
54252
/* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
54253
  {
54254
    { 0, 0, 0, 0 },
54255
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
54256
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a3ba00 }
54257
  },
54258
/* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
54259
  {
54260
    { 0, 0, 0, 0 },
54261
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
54262
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1b3ba00 }
54263
  },
54264
/* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
54265
  {
54266
    { 0, 0, 0, 0 },
54267
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
54268
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a58a00 }
54269
  },
54270
/* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
54271
  {
54272
    { 0, 0, 0, 0 },
54273
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
54274
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a5aa00 }
54275
  },
54276
/* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
54277
  {
54278
    { 0, 0, 0, 0 },
54279
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
54280
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a5ba00 }
54281
  },
54282
/* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
54283
  {
54284
    { 0, 0, 0, 0 },
54285
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
54286
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1b5ba00 }
54287
  },
54288
/* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
54289
  {
54290
    { 0, 0, 0, 0 },
54291
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
54292
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3ca00 }
54293
  },
54294
/* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
54295
  {
54296
    { 0, 0, 0, 0 },
54297
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
54298
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3ea00 }
54299
  },
54300
/* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
54301
  {
54302
    { 0, 0, 0, 0 },
54303
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
54304
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3fa00 }
54305
  },
54306
/* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
54307
  {
54308
    { 0, 0, 0, 0 },
54309
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
54310
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1b3fa00 }
54311
  },
54312
/* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
54313
  {
54314
    { 0, 0, 0, 0 },
54315
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
54316
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5ca00 }
54317
  },
54318
/* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
54319
  {
54320
    { 0, 0, 0, 0 },
54321
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
54322
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5ea00 }
54323
  },
54324
/* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
54325
  {
54326
    { 0, 0, 0, 0 },
54327
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
54328
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5fa00 }
54329
  },
54330
/* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
54331
  {
54332
    { 0, 0, 0, 0 },
54333
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
54334
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1b5fa00 }
54335
  },
54336
/* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
54337
  {
54338
    { 0, 0, 0, 0 },
54339
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
54340
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7ca00 }
54341
  },
54342
/* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
54343
  {
54344
    { 0, 0, 0, 0 },
54345
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), 0 } },
54346
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7ea00 }
54347
  },
54348
/* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
54349
  {
54350
    { 0, 0, 0, 0 },
54351
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), 0 } },
54352
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7fa00 }
54353
  },
54354
/* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-u16} */
54355
  {
54356
    { 0, 0, 0, 0 },
54357
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), 0 } },
54358
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1b7fa00 }
54359
  },
54360
/* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
54361
  {
54362
    { 0, 0, 0, 0 },
54363
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
54364
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a78a00 }
54365
  },
54366
/* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
54367
  {
54368
    { 0, 0, 0, 0 },
54369
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), 0 } },
54370
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a7aa00 }
54371
  },
54372
/* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
54373
  {
54374
    { 0, 0, 0, 0 },
54375
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), 0 } },
54376
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a7ba00 }
54377
  },
54378
/* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-u24} */
54379
  {
54380
    { 0, 0, 0, 0 },
54381
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), 0 } },
54382
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1b7ba00 }
54383
  },
54384
/* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
54385
  {
54386
    { 0, 0, 0, 0 },
54387
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
54388
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b90a00 }
54389
  },
54390
/* dsbb.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */
54391
  {
54392
    { 0, 0, 0, 0 },
54393
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32RNPREFIXEDHI), 0 } },
54394
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b92a00 }
54395
  },
54396
/* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
54397
  {
54398
    { 0, 0, 0, 0 },
54399
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
54400
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b18a00 }
54401
  },
54402
/* dsbb.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */
54403
  {
54404
    { 0, 0, 0, 0 },
54405
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32ANPREFIXEDHI), 0 } },
54406
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b1aa00 }
54407
  },
54408
/* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
54409
  {
54410
    { 0, 0, 0, 0 },
54411
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
54412
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b10a00 }
54413
  },
54414
/* dsbb.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
54415
  {
54416
    { 0, 0, 0, 0 },
54417
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
54418
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b12a00 }
54419
  },
54420
/* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
54421
  {
54422
    { 0, 0, 0, 0 },
54423
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
54424
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b30a00 }
54425
  },
54426
/* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
54427
  {
54428
    { 0, 0, 0, 0 },
54429
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
54430
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b32a00 }
54431
  },
54432
/* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
54433
  {
54434
    { 0, 0, 0, 0 },
54435
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
54436
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b50a00 }
54437
  },
54438
/* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
54439
  {
54440
    { 0, 0, 0, 0 },
54441
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
54442
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b52a00 }
54443
  },
54444
/* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
54445
  {
54446
    { 0, 0, 0, 0 },
54447
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
54448
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b70a00 }
54449
  },
54450
/* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
54451
  {
54452
    { 0, 0, 0, 0 },
54453
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
54454
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b72a00 }
54455
  },
54456
/* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
54457
  {
54458
    { 0, 0, 0, 0 },
54459
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
54460
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b38a00 }
54461
  },
54462
/* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
54463
  {
54464
    { 0, 0, 0, 0 },
54465
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
54466
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b3aa00 }
54467
  },
54468
/* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
54469
  {
54470
    { 0, 0, 0, 0 },
54471
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
54472
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b58a00 }
54473
  },
54474
/* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
54475
  {
54476
    { 0, 0, 0, 0 },
54477
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
54478
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b5aa00 }
54479
  },
54480
/* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
54481
  {
54482
    { 0, 0, 0, 0 },
54483
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
54484
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b3ca00 }
54485
  },
54486
/* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
54487
  {
54488
    { 0, 0, 0, 0 },
54489
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
54490
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b3ea00 }
54491
  },
54492
/* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
54493
  {
54494
    { 0, 0, 0, 0 },
54495
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
54496
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b5ca00 }
54497
  },
54498
/* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
54499
  {
54500
    { 0, 0, 0, 0 },
54501
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
54502
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b5ea00 }
54503
  },
54504
/* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
54505
  {
54506
    { 0, 0, 0, 0 },
54507
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), 0 } },
54508
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_absolute_Prefixed_HI, { 0x1b7ca00 }
54509
  },
54510
/* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-u16} */
54511
  {
54512
    { 0, 0, 0, 0 },
54513
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), 0 } },
54514
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_absolute_Prefixed_HI, { 0x1b7ea00 }
54515
  },
54516
/* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
54517
  {
54518
    { 0, 0, 0, 0 },
54519
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), 0 } },
54520
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_24_absolute_Prefixed_HI, { 0x1b78a00 }
54521
  },
54522
/* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-u24} */
54523
  {
54524
    { 0, 0, 0, 0 },
54525
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), 0 } },
54526
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_24_absolute_Prefixed_HI, { 0x1b7aa00 }
54527
  },
54528
/* dsbb.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */
54529
  {
54530
    { 0, 0, 0, 0 },
54531
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DST32RNPREFIXEDHI), 0 } },
54532
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1c90a }
54533
  },
54534
/* dsbb.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */
54535
  {
54536
    { 0, 0, 0, 0 },
54537
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DST32RNPREFIXEDHI), 0 } },
54538
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1892a }
54539
  },
54540
/* dsbb.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */
54541
  {
54542
    { 0, 0, 0, 0 },
54543
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
54544
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1890a }
54545
  },
54546
/* dsbb.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */
54547
  {
54548
    { 0, 0, 0, 0 },
54549
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DST32ANPREFIXEDHI), 0 } },
54550
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1c18a }
54551
  },
54552
/* dsbb.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */
54553
  {
54554
    { 0, 0, 0, 0 },
54555
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DST32ANPREFIXEDHI), 0 } },
54556
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x181aa }
54557
  },
54558
/* dsbb.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */
54559
  {
54560
    { 0, 0, 0, 0 },
54561
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
54562
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1818a }
54563
  },
54564
/* dsbb.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */
54565
  {
54566
    { 0, 0, 0, 0 },
54567
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
54568
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1c10a }
54569
  },
54570
/* dsbb.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */
54571
  {
54572
    { 0, 0, 0, 0 },
54573
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
54574
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1812a }
54575
  },
54576
/* dsbb.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
54577
  {
54578
    { 0, 0, 0, 0 },
54579
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
54580
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1810a }
54581
  },
54582
/* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
54583
  {
54584
    { 0, 0, 0, 0 },
54585
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
54586
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1c30a00 }
54587
  },
54588
/* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
54589
  {
54590
    { 0, 0, 0, 0 },
54591
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
54592
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1832a00 }
54593
  },
54594
/* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
54595
  {
54596
    { 0, 0, 0, 0 },
54597
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
54598
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1830a00 }
54599
  },
54600
/* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
54601
  {
54602
    { 0, 0, 0, 0 },
54603
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
54604
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1c50a00 }
54605
  },
54606
/* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
54607
  {
54608
    { 0, 0, 0, 0 },
54609
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
54610
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1852a00 }
54611
  },
54612
/* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
54613
  {
54614
    { 0, 0, 0, 0 },
54615
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
54616
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1850a00 }
54617
  },
54618
/* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
54619
  {
54620
    { 0, 0, 0, 0 },
54621
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
54622
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1c70a00 }
54623
  },
54624
/* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
54625
  {
54626
    { 0, 0, 0, 0 },
54627
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
54628
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1872a00 }
54629
  },
54630
/* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
54631
  {
54632
    { 0, 0, 0, 0 },
54633
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
54634
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1870a00 }
54635
  },
54636
/* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */
54637
  {
54638
    { 0, 0, 0, 0 },
54639
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
54640
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1c38a00 }
54641
  },
54642
/* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */
54643
  {
54644
    { 0, 0, 0, 0 },
54645
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
54646
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x183aa00 }
54647
  },
54648
/* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
54649
  {
54650
    { 0, 0, 0, 0 },
54651
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
54652
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1838a00 }
54653
  },
54654
/* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */
54655
  {
54656
    { 0, 0, 0, 0 },
54657
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
54658
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1c58a00 }
54659
  },
54660
/* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */
54661
  {
54662
    { 0, 0, 0, 0 },
54663
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
54664
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x185aa00 }
54665
  },
54666
/* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
54667
  {
54668
    { 0, 0, 0, 0 },
54669
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
54670
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1858a00 }
54671
  },
54672
/* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */
54673
  {
54674
    { 0, 0, 0, 0 },
54675
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
54676
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x1c3ca00 }
54677
  },
54678
/* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */
54679
  {
54680
    { 0, 0, 0, 0 },
54681
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
54682
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x183ea00 }
54683
  },
54684
/* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
54685
  {
54686
    { 0, 0, 0, 0 },
54687
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
54688
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x183ca00 }
54689
  },
54690
/* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */
54691
  {
54692
    { 0, 0, 0, 0 },
54693
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
54694
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x1c5ca00 }
54695
  },
54696
/* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */
54697
  {
54698
    { 0, 0, 0, 0 },
54699
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
54700
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x185ea00 }
54701
  },
54702
/* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
54703
  {
54704
    { 0, 0, 0, 0 },
54705
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
54706
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x185ca00 }
54707
  },
54708
/* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */
54709
  {
54710
    { 0, 0, 0, 0 },
54711
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), 0 } },
54712
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x1c7ca00 }
54713
  },
54714
/* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */
54715
  {
54716
    { 0, 0, 0, 0 },
54717
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), 0 } },
54718
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x187ea00 }
54719
  },
54720
/* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */
54721
  {
54722
    { 0, 0, 0, 0 },
54723
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
54724
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x187ca00 }
54725
  },
54726
/* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */
54727
  {
54728
    { 0, 0, 0, 0 },
54729
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U24), 0 } },
54730
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x1c78a00 }
54731
  },
54732
/* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */
54733
  {
54734
    { 0, 0, 0, 0 },
54735
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U24), 0 } },
54736
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x187aa00 }
54737
  },
54738
/* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */
54739
  {
54740
    { 0, 0, 0, 0 },
54741
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
54742
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x1878a00 }
54743
  },
54744
/* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
54745
  {
54746
    { 0, 0, 0, 0 },
54747
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
54748
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1980a00 }
54749
  },
54750
/* dsbb.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */
54751
  {
54752
    { 0, 0, 0, 0 },
54753
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
54754
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1982a00 }
54755
  },
54756
/* dsbb.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */
54757
  {
54758
    { 0, 0, 0, 0 },
54759
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
54760
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1983a00 }
54761
  },
54762
/* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
54763
  {
54764
    { 0, 0, 0, 0 },
54765
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
54766
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1908a00 }
54767
  },
54768
/* dsbb.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */
54769
  {
54770
    { 0, 0, 0, 0 },
54771
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
54772
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x190aa00 }
54773
  },
54774
/* dsbb.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */
54775
  {
54776
    { 0, 0, 0, 0 },
54777
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
54778
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x190ba00 }
54779
  },
54780
/* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
54781
  {
54782
    { 0, 0, 0, 0 },
54783
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
54784
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1900a00 }
54785
  },
54786
/* dsbb.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
54787
  {
54788
    { 0, 0, 0, 0 },
54789
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
54790
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1902a00 }
54791
  },
54792
/* dsbb.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
54793
  {
54794
    { 0, 0, 0, 0 },
54795
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
54796
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1903a00 }
54797
  },
54798
/* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
54799
  {
54800
    { 0, 0, 0, 0 },
54801
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
54802
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1920a00 }
54803
  },
54804
/* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
54805
  {
54806
    { 0, 0, 0, 0 },
54807
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
54808
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1922a00 }
54809
  },
54810
/* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
54811
  {
54812
    { 0, 0, 0, 0 },
54813
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
54814
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1923a00 }
54815
  },
54816
/* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
54817
  {
54818
    { 0, 0, 0, 0 },
54819
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
54820
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1940a00 }
54821
  },
54822
/* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
54823
  {
54824
    { 0, 0, 0, 0 },
54825
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
54826
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1942a00 }
54827
  },
54828
/* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
54829
  {
54830
    { 0, 0, 0, 0 },
54831
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
54832
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1943a00 }
54833
  },
54834
/* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
54835
  {
54836
    { 0, 0, 0, 0 },
54837
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
54838
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1960a00 }
54839
  },
54840
/* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
54841
  {
54842
    { 0, 0, 0, 0 },
54843
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
54844
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1962a00 }
54845
  },
54846
/* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
54847
  {
54848
    { 0, 0, 0, 0 },
54849
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
54850
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1963a00 }
54851
  },
54852
/* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
54853
  {
54854
    { 0, 0, 0, 0 },
54855
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
54856
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x1928a00 }
54857
  },
54858
/* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
54859
  {
54860
    { 0, 0, 0, 0 },
54861
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
54862
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x192aa00 }
54863
  },
54864
/* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
54865
  {
54866
    { 0, 0, 0, 0 },
54867
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
54868
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x192ba00 }
54869
  },
54870
/* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
54871
  {
54872
    { 0, 0, 0, 0 },
54873
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
54874
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x1948a00 }
54875
  },
54876
/* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
54877
  {
54878
    { 0, 0, 0, 0 },
54879
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
54880
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x194aa00 }
54881
  },
54882
/* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
54883
  {
54884
    { 0, 0, 0, 0 },
54885
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
54886
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x194ba00 }
54887
  },
54888
/* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
54889
  {
54890
    { 0, 0, 0, 0 },
54891
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
54892
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192ca00 }
54893
  },
54894
/* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
54895
  {
54896
    { 0, 0, 0, 0 },
54897
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
54898
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192ea00 }
54899
  },
54900
/* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
54901
  {
54902
    { 0, 0, 0, 0 },
54903
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
54904
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192fa00 }
54905
  },
54906
/* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
54907
  {
54908
    { 0, 0, 0, 0 },
54909
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
54910
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194ca00 }
54911
  },
54912
/* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
54913
  {
54914
    { 0, 0, 0, 0 },
54915
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
54916
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194ea00 }
54917
  },
54918
/* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
54919
  {
54920
    { 0, 0, 0, 0 },
54921
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
54922
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194fa00 }
54923
  },
54924
/* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
54925
  {
54926
    { 0, 0, 0, 0 },
54927
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
54928
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196ca00 }
54929
  },
54930
/* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
54931
  {
54932
    { 0, 0, 0, 0 },
54933
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
54934
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196ea00 }
54935
  },
54936
/* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
54937
  {
54938
    { 0, 0, 0, 0 },
54939
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
54940
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196fa00 }
54941
  },
54942
/* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
54943
  {
54944
    { 0, 0, 0, 0 },
54945
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
54946
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x1968a00 }
54947
  },
54948
/* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
54949
  {
54950
    { 0, 0, 0, 0 },
54951
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
54952
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x196aa00 }
54953
  },
54954
/* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
54955
  {
54956
    { 0, 0, 0, 0 },
54957
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
54958
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x196ba00 }
54959
  },
54960
/* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
54961
  {
54962
    { 0, 0, 0, 0 },
54963
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
54964
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a80a00 }
54965
  },
54966
/* dsbb.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */
54967
  {
54968
    { 0, 0, 0, 0 },
54969
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
54970
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a82a00 }
54971
  },
54972
/* dsbb.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */
54973
  {
54974
    { 0, 0, 0, 0 },
54975
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
54976
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a83a00 }
54977
  },
54978
/* dsbb.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */
54979
  {
54980
    { 0, 0, 0, 0 },
54981
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32RNPREFIXEDQI), 0 } },
54982
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b83a00 }
54983
  },
54984
/* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
54985
  {
54986
    { 0, 0, 0, 0 },
54987
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
54988
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a08a00 }
54989
  },
54990
/* dsbb.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */
54991
  {
54992
    { 0, 0, 0, 0 },
54993
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
54994
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a0aa00 }
54995
  },
54996
/* dsbb.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */
54997
  {
54998
    { 0, 0, 0, 0 },
54999
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
55000
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a0ba00 }
55001
  },
55002
/* dsbb.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */
55003
  {
55004
    { 0, 0, 0, 0 },
55005
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32ANPREFIXEDQI), 0 } },
55006
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b0ba00 }
55007
  },
55008
/* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
55009
  {
55010
    { 0, 0, 0, 0 },
55011
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
55012
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a00a00 }
55013
  },
55014
/* dsbb.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
55015
  {
55016
    { 0, 0, 0, 0 },
55017
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
55018
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a02a00 }
55019
  },
55020
/* dsbb.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
55021
  {
55022
    { 0, 0, 0, 0 },
55023
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
55024
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a03a00 }
55025
  },
55026
/* dsbb.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
55027
  {
55028
    { 0, 0, 0, 0 },
55029
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
55030
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b03a00 }
55031
  },
55032
/* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
55033
  {
55034
    { 0, 0, 0, 0 },
55035
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
55036
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a20a00 }
55037
  },
55038
/* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
55039
  {
55040
    { 0, 0, 0, 0 },
55041
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
55042
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a22a00 }
55043
  },
55044
/* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
55045
  {
55046
    { 0, 0, 0, 0 },
55047
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
55048
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a23a00 }
55049
  },
55050
/* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
55051
  {
55052
    { 0, 0, 0, 0 },
55053
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
55054
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1b23a00 }
55055
  },
55056
/* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
55057
  {
55058
    { 0, 0, 0, 0 },
55059
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
55060
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a40a00 }
55061
  },
55062
/* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
55063
  {
55064
    { 0, 0, 0, 0 },
55065
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
55066
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a42a00 }
55067
  },
55068
/* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
55069
  {
55070
    { 0, 0, 0, 0 },
55071
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
55072
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a43a00 }
55073
  },
55074
/* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
55075
  {
55076
    { 0, 0, 0, 0 },
55077
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
55078
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1b43a00 }
55079
  },
55080
/* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
55081
  {
55082
    { 0, 0, 0, 0 },
55083
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
55084
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a60a00 }
55085
  },
55086
/* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
55087
  {
55088
    { 0, 0, 0, 0 },
55089
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
55090
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a62a00 }
55091
  },
55092
/* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
55093
  {
55094
    { 0, 0, 0, 0 },
55095
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
55096
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a63a00 }
55097
  },
55098
/* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
55099
  {
55100
    { 0, 0, 0, 0 },
55101
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
55102
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1b63a00 }
55103
  },
55104
/* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
55105
  {
55106
    { 0, 0, 0, 0 },
55107
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
55108
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a28a00 }
55109
  },
55110
/* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
55111
  {
55112
    { 0, 0, 0, 0 },
55113
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
55114
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a2aa00 }
55115
  },
55116
/* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
55117
  {
55118
    { 0, 0, 0, 0 },
55119
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
55120
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a2ba00 }
55121
  },
55122
/* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
55123
  {
55124
    { 0, 0, 0, 0 },
55125
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
55126
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1b2ba00 }
55127
  },
55128
/* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
55129
  {
55130
    { 0, 0, 0, 0 },
55131
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
55132
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a48a00 }
55133
  },
55134
/* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
55135
  {
55136
    { 0, 0, 0, 0 },
55137
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
55138
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a4aa00 }
55139
  },
55140
/* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
55141
  {
55142
    { 0, 0, 0, 0 },
55143
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
55144
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a4ba00 }
55145
  },
55146
/* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
55147
  {
55148
    { 0, 0, 0, 0 },
55149
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
55150
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1b4ba00 }
55151
  },
55152
/* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
55153
  {
55154
    { 0, 0, 0, 0 },
55155
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
55156
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2ca00 }
55157
  },
55158
/* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
55159
  {
55160
    { 0, 0, 0, 0 },
55161
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
55162
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2ea00 }
55163
  },
55164
/* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
55165
  {
55166
    { 0, 0, 0, 0 },
55167
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
55168
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2fa00 }
55169
  },
55170
/* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
55171
  {
55172
    { 0, 0, 0, 0 },
55173
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
55174
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1b2fa00 }
55175
  },
55176
/* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
55177
  {
55178
    { 0, 0, 0, 0 },
55179
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
55180
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4ca00 }
55181
  },
55182
/* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
55183
  {
55184
    { 0, 0, 0, 0 },
55185
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
55186
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4ea00 }
55187
  },
55188
/* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
55189
  {
55190
    { 0, 0, 0, 0 },
55191
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
55192
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4fa00 }
55193
  },
55194
/* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
55195
  {
55196
    { 0, 0, 0, 0 },
55197
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
55198
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1b4fa00 }
55199
  },
55200
/* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
55201
  {
55202
    { 0, 0, 0, 0 },
55203
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
55204
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6ca00 }
55205
  },
55206
/* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
55207
  {
55208
    { 0, 0, 0, 0 },
55209
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), 0 } },
55210
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6ea00 }
55211
  },
55212
/* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
55213
  {
55214
    { 0, 0, 0, 0 },
55215
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), 0 } },
55216
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6fa00 }
55217
  },
55218
/* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-u16} */
55219
  {
55220
    { 0, 0, 0, 0 },
55221
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), 0 } },
55222
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1b6fa00 }
55223
  },
55224
/* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
55225
  {
55226
    { 0, 0, 0, 0 },
55227
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
55228
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a68a00 }
55229
  },
55230
/* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
55231
  {
55232
    { 0, 0, 0, 0 },
55233
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), 0 } },
55234
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a6aa00 }
55235
  },
55236
/* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
55237
  {
55238
    { 0, 0, 0, 0 },
55239
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), 0 } },
55240
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a6ba00 }
55241
  },
55242
/* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-u24} */
55243
  {
55244
    { 0, 0, 0, 0 },
55245
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), 0 } },
55246
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1b6ba00 }
55247
  },
55248
/* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
55249
  {
55250
    { 0, 0, 0, 0 },
55251
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
55252
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b80a00 }
55253
  },
55254
/* dsbb.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */
55255
  {
55256
    { 0, 0, 0, 0 },
55257
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32RNPREFIXEDQI), 0 } },
55258
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b82a00 }
55259
  },
55260
/* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
55261
  {
55262
    { 0, 0, 0, 0 },
55263
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
55264
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b08a00 }
55265
  },
55266
/* dsbb.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */
55267
  {
55268
    { 0, 0, 0, 0 },
55269
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32ANPREFIXEDQI), 0 } },
55270
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b0aa00 }
55271
  },
55272
/* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
55273
  {
55274
    { 0, 0, 0, 0 },
55275
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
55276
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b00a00 }
55277
  },
55278
/* dsbb.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
55279
  {
55280
    { 0, 0, 0, 0 },
55281
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
55282
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b02a00 }
55283
  },
55284
/* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
55285
  {
55286
    { 0, 0, 0, 0 },
55287
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
55288
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_An_relative_Prefixed_QI, { 0x1b20a00 }
55289
  },
55290
/* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
55291
  {
55292
    { 0, 0, 0, 0 },
55293
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
55294
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_An_relative_Prefixed_QI, { 0x1b22a00 }
55295
  },
55296
/* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
55297
  {
55298
    { 0, 0, 0, 0 },
55299
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
55300
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_An_relative_Prefixed_QI, { 0x1b40a00 }
55301
  },
55302
/* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
55303
  {
55304
    { 0, 0, 0, 0 },
55305
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
55306
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_An_relative_Prefixed_QI, { 0x1b42a00 }
55307
  },
55308
/* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
55309
  {
55310
    { 0, 0, 0, 0 },
55311
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
55312
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_An_relative_Prefixed_QI, { 0x1b60a00 }
55313
  },
55314
/* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
55315
  {
55316
    { 0, 0, 0, 0 },
55317
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
55318
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_An_relative_Prefixed_QI, { 0x1b62a00 }
55319
  },
55320
/* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
55321
  {
55322
    { 0, 0, 0, 0 },
55323
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
55324
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_QI, { 0x1b28a00 }
55325
  },
55326
/* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
55327
  {
55328
    { 0, 0, 0, 0 },
55329
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
55330
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_QI, { 0x1b2aa00 }
55331
  },
55332
/* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
55333
  {
55334
    { 0, 0, 0, 0 },
55335
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
55336
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_QI, { 0x1b48a00 }
55337
  },
55338
/* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
55339
  {
55340
    { 0, 0, 0, 0 },
55341
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
55342
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_QI, { 0x1b4aa00 }
55343
  },
55344
/* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
55345
  {
55346
    { 0, 0, 0, 0 },
55347
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
55348
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_QI, { 0x1b2ca00 }
55349
  },
55350
/* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
55351
  {
55352
    { 0, 0, 0, 0 },
55353
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
55354
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_QI, { 0x1b2ea00 }
55355
  },
55356
/* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
55357
  {
55358
    { 0, 0, 0, 0 },
55359
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
55360
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_QI, { 0x1b4ca00 }
55361
  },
55362
/* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
55363
  {
55364
    { 0, 0, 0, 0 },
55365
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
55366
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_QI, { 0x1b4ea00 }
55367
  },
55368
/* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
55369
  {
55370
    { 0, 0, 0, 0 },
55371
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), 0 } },
55372
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_absolute_Prefixed_QI, { 0x1b6ca00 }
55373
  },
55374
/* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-u16} */
55375
  {
55376
    { 0, 0, 0, 0 },
55377
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), 0 } },
55378
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_absolute_Prefixed_QI, { 0x1b6ea00 }
55379
  },
55380
/* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
55381
  {
55382
    { 0, 0, 0, 0 },
55383
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), 0 } },
55384
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_absolute_Prefixed_QI, { 0x1b68a00 }
55385
  },
55386
/* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-u24} */
55387
  {
55388
    { 0, 0, 0, 0 },
55389
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), 0 } },
55390
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_absolute_Prefixed_QI, { 0x1b6aa00 }
55391
  },
55392
/* dsbb.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */
55393
  {
55394
    { 0, 0, 0, 0 },
55395
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32RNPREFIXEDQI), 0 } },
55396
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1c80a }
55397
  },
55398
/* dsbb.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */
55399
  {
55400
    { 0, 0, 0, 0 },
55401
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DST32RNPREFIXEDQI), 0 } },
55402
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1882a }
55403
  },
55404
/* dsbb.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */
55405
  {
55406
    { 0, 0, 0, 0 },
55407
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
55408
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1880a }
55409
  },
55410
/* dsbb.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */
55411
  {
55412
    { 0, 0, 0, 0 },
55413
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32ANPREFIXEDQI), 0 } },
55414
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1c08a }
55415
  },
55416
/* dsbb.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */
55417
  {
55418
    { 0, 0, 0, 0 },
55419
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DST32ANPREFIXEDQI), 0 } },
55420
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x180aa }
55421
  },
55422
/* dsbb.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */
55423
  {
55424
    { 0, 0, 0, 0 },
55425
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
55426
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1808a }
55427
  },
55428
/* dsbb.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
55429
  {
55430
    { 0, 0, 0, 0 },
55431
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
55432
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1c00a }
55433
  },
55434
/* dsbb.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */
55435
  {
55436
    { 0, 0, 0, 0 },
55437
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
55438
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1802a }
55439
  },
55440
/* dsbb.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
55441
  {
55442
    { 0, 0, 0, 0 },
55443
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
55444
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1800a }
55445
  },
55446
/* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
55447
  {
55448
    { 0, 0, 0, 0 },
55449
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
55450
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1c20a00 }
55451
  },
55452
/* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
55453
  {
55454
    { 0, 0, 0, 0 },
55455
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
55456
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1822a00 }
55457
  },
55458
/* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
55459
  {
55460
    { 0, 0, 0, 0 },
55461
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
55462
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1820a00 }
55463
  },
55464
/* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
55465
  {
55466
    { 0, 0, 0, 0 },
55467
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
55468
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1c40a00 }
55469
  },
55470
/* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
55471
  {
55472
    { 0, 0, 0, 0 },
55473
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
55474
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1842a00 }
55475
  },
55476
/* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
55477
  {
55478
    { 0, 0, 0, 0 },
55479
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
55480
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1840a00 }
55481
  },
55482
/* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
55483
  {
55484
    { 0, 0, 0, 0 },
55485
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
55486
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1c60a00 }
55487
  },
55488
/* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
55489
  {
55490
    { 0, 0, 0, 0 },
55491
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
55492
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1862a00 }
55493
  },
55494
/* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
55495
  {
55496
    { 0, 0, 0, 0 },
55497
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
55498
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1860a00 }
55499
  },
55500
/* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
55501
  {
55502
    { 0, 0, 0, 0 },
55503
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
55504
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x1c28a00 }
55505
  },
55506
/* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */
55507
  {
55508
    { 0, 0, 0, 0 },
55509
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
55510
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x182aa00 }
55511
  },
55512
/* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
55513
  {
55514
    { 0, 0, 0, 0 },
55515
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
55516
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x1828a00 }
55517
  },
55518
/* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
55519
  {
55520
    { 0, 0, 0, 0 },
55521
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
55522
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x1c48a00 }
55523
  },
55524
/* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */
55525
  {
55526
    { 0, 0, 0, 0 },
55527
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
55528
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x184aa00 }
55529
  },
55530
/* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
55531
  {
55532
    { 0, 0, 0, 0 },
55533
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
55534
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x1848a00 }
55535
  },
55536
/* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
55537
  {
55538
    { 0, 0, 0, 0 },
55539
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
55540
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x1c2ca00 }
55541
  },
55542
/* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */
55543
  {
55544
    { 0, 0, 0, 0 },
55545
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
55546
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x182ea00 }
55547
  },
55548
/* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
55549
  {
55550
    { 0, 0, 0, 0 },
55551
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
55552
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x182ca00 }
55553
  },
55554
/* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
55555
  {
55556
    { 0, 0, 0, 0 },
55557
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
55558
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x1c4ca00 }
55559
  },
55560
/* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */
55561
  {
55562
    { 0, 0, 0, 0 },
55563
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
55564
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x184ea00 }
55565
  },
55566
/* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
55567
  {
55568
    { 0, 0, 0, 0 },
55569
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
55570
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x184ca00 }
55571
  },
55572
/* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */
55573
  {
55574
    { 0, 0, 0, 0 },
55575
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), 0 } },
55576
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x1c6ca00 }
55577
  },
55578
/* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */
55579
  {
55580
    { 0, 0, 0, 0 },
55581
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), 0 } },
55582
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x186ea00 }
55583
  },
55584
/* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */
55585
  {
55586
    { 0, 0, 0, 0 },
55587
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
55588
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x186ca00 }
55589
  },
55590
/* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */
55591
  {
55592
    { 0, 0, 0, 0 },
55593
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), 0 } },
55594
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x1c68a00 }
55595
  },
55596
/* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */
55597
  {
55598
    { 0, 0, 0, 0 },
55599
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U24), 0 } },
55600
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x186aa00 }
55601
  },
55602
/* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */
55603
  {
55604
    { 0, 0, 0, 0 },
55605
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
55606
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x1868a00 }
55607
  },
55608
/* dsbb.w${X} #${Imm-24-HI},$Dst32RnPrefixedHI */
55609
  {
55610
    { 0, 0, 0, 0 },
55611
    { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DST32RNPREFIXEDHI), 0 } },
55612
    & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_Rn_direct_Prefixed_HI, { 0x1990e00 }
55613
  },
55614
/* dsbb.w${X} #${Imm-24-HI},$Dst32AnPrefixedHI */
55615
  {
55616
    { 0, 0, 0, 0 },
55617
    { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DST32ANPREFIXEDHI), 0 } },
55618
    & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_An_direct_Prefixed_HI, { 0x1918e00 }
55619
  },
55620
/* dsbb.w${X} #${Imm-24-HI},[$Dst32AnPrefixed] */
55621
  {
55622
    { 0, 0, 0, 0 },
55623
    { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
55624
    & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_An_indirect_Prefixed_HI, { 0x1910e00 }
55625
  },
55626
/* dsbb.w${X} #${Imm-32-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */
55627
  {
55628
    { 0, 0, 0, 0 },
55629
    { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
55630
    & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_An_relative_Prefixed_HI, { 0x1930e00 }
55631
  },
55632
/* dsbb.w${X} #${Imm-32-HI},${Dsp-24-u8}[sb] */
55633
  {
55634
    { 0, 0, 0, 0 },
55635
    { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
55636
    & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_SB_relative_Prefixed_HI, { 0x1938e00 }
55637
  },
55638
/* dsbb.w${X} #${Imm-32-HI},${Dsp-24-s8}[fb] */
55639
  {
55640
    { 0, 0, 0, 0 },
55641
    { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
55642
    & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_FB_relative_Prefixed_HI, { 0x193ce00 }
55643
  },
55644
/* dsbb.w${X} #${Imm-40-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */
55645
  {
55646
    { 0, 0, 0, 0 },
55647
    { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
55648
    & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_An_relative_Prefixed_HI, { 0x1950e00 }
55649
  },
55650
/* dsbb.w${X} #${Imm-40-HI},${Dsp-24-u16}[sb] */
55651
  {
55652
    { 0, 0, 0, 0 },
55653
    { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
55654
    & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_SB_relative_Prefixed_HI, { 0x1958e00 }
55655
  },
55656
/* dsbb.w${X} #${Imm-40-HI},${Dsp-24-s16}[fb] */
55657
  {
55658
    { 0, 0, 0, 0 },
55659
    { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
55660
    & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_FB_relative_Prefixed_HI, { 0x195ce00 }
55661
  },
55662
/* dsbb.w${X} #${Imm-40-HI},${Dsp-24-u16} */
55663
  {
55664
    { 0, 0, 0, 0 },
55665
    { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), 0 } },
55666
    & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_absolute_Prefixed_HI, { 0x197ce00 }
55667
  },
55668
/* dsbb.w${X} #${Imm-48-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */
55669
  {
55670
    { 0, 0, 0, 0 },
55671
    { { MNEM, OP (X), ' ', '#', OP (IMM_48_HI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
55672
    & ifmt_sbb32_w_imm_G_24_24_Prefixed_dst32_24_24_An_relative_Prefixed_HI, { 0x1970e00 }
55673
  },
55674
/* dsbb.w${X} #${Imm-48-HI},${Dsp-24-u24} */
55675
  {
55676
    { 0, 0, 0, 0 },
55677
    { { MNEM, OP (X), ' ', '#', OP (IMM_48_HI), ',', OP (DSP_24_U24), 0 } },
55678
    & ifmt_sbb32_w_imm_G_24_24_Prefixed_dst32_24_24_absolute_Prefixed_HI, { 0x1978e00 }
55679
  },
55680
/* dsbb.b${X} #${Imm-24-QI},$Dst32RnPrefixedQI */
55681
  {
55682
    { 0, 0, 0, 0 },
55683
    { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DST32RNPREFIXEDQI), 0 } },
55684
    & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_Rn_direct_Prefixed_QI, { 0x1980e00 }
55685
  },
55686
/* dsbb.b${X} #${Imm-24-QI},$Dst32AnPrefixedQI */
55687
  {
55688
    { 0, 0, 0, 0 },
55689
    { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DST32ANPREFIXEDQI), 0 } },
55690
    & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_An_direct_Prefixed_QI, { 0x1908e00 }
55691
  },
55692
/* dsbb.b${X} #${Imm-24-QI},[$Dst32AnPrefixed] */
55693
  {
55694
    { 0, 0, 0, 0 },
55695
    { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
55696
    & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_An_indirect_Prefixed_QI, { 0x1900e00 }
55697
  },
55698
/* dsbb.b${X} #${Imm-32-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */
55699
  {
55700
    { 0, 0, 0, 0 },
55701
    { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
55702
    & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_An_relative_Prefixed_QI, { 0x1920e00 }
55703
  },
55704
/* dsbb.b${X} #${Imm-32-QI},${Dsp-24-u8}[sb] */
55705
  {
55706
    { 0, 0, 0, 0 },
55707
    { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
55708
    & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_SB_relative_Prefixed_QI, { 0x1928e00 }
55709
  },
55710
/* dsbb.b${X} #${Imm-32-QI},${Dsp-24-s8}[fb] */
55711
  {
55712
    { 0, 0, 0, 0 },
55713
    { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
55714
    & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_FB_relative_Prefixed_QI, { 0x192ce00 }
55715
  },
55716
/* dsbb.b${X} #${Imm-40-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */
55717
  {
55718
    { 0, 0, 0, 0 },
55719
    { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
55720
    & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_An_relative_Prefixed_QI, { 0x1940e00 }
55721
  },
55722
/* dsbb.b${X} #${Imm-40-QI},${Dsp-24-u16}[sb] */
55723
  {
55724
    { 0, 0, 0, 0 },
55725
    { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
55726
    & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_SB_relative_Prefixed_QI, { 0x1948e00 }
55727
  },
55728
/* dsbb.b${X} #${Imm-40-QI},${Dsp-24-s16}[fb] */
55729
  {
55730
    { 0, 0, 0, 0 },
55731
    { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
55732
    & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_FB_relative_Prefixed_QI, { 0x194ce00 }
55733
  },
55734
/* dsbb.b${X} #${Imm-40-QI},${Dsp-24-u16} */
55735
  {
55736
    { 0, 0, 0, 0 },
55737
    { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), 0 } },
55738
    & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_absolute_Prefixed_QI, { 0x196ce00 }
55739
  },
55740
/* dsbb.b${X} #${Imm-48-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */
55741
  {
55742
    { 0, 0, 0, 0 },
55743
    { { MNEM, OP (X), ' ', '#', OP (IMM_48_QI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
55744
    & ifmt_sbb32_b_imm_G_24_24_Prefixed_dst32_24_24_An_relative_Prefixed_QI, { 0x1960e00 }
55745
  },
55746
/* dsbb.b${X} #${Imm-48-QI},${Dsp-24-u24} */
55747
  {
55748
    { 0, 0, 0, 0 },
55749
    { { MNEM, OP (X), ' ', '#', OP (IMM_48_QI), ',', OP (DSP_24_U24), 0 } },
55750
    & ifmt_sbb32_b_imm_G_24_24_Prefixed_dst32_24_24_absolute_Prefixed_QI, { 0x1968e00 }
55751
  },
55752
/* divx.l $Dst32RnPrefixedSI */
55753
  {
55754
    { 0, 0, 0, 0 },
55755
    { { MNEM, ' ', OP (DST32RNPREFIXEDSI), 0 } },
55756
    & ifmt_mulu_l_dst32_Rn_direct_Prefixed_SI, { 0x1a92f }
55757
  },
55758
/* divx.l $Dst32AnPrefixedSI */
55759
  {
55760
    { 0, 0, 0, 0 },
55761
    { { MNEM, ' ', OP (DST32ANPREFIXEDSI), 0 } },
55762
    & ifmt_mulu_l_dst32_An_direct_Prefixed_SI, { 0x1a1af }
55763
  },
55764
/* divx.l [$Dst32AnPrefixed] */
55765
  {
55766
    { 0, 0, 0, 0 },
55767
    { { MNEM, ' ', '[', OP (DST32ANPREFIXED), ']', 0 } },
55768
    & ifmt_mulu_l_dst32_An_indirect_Prefixed_SI, { 0x1a12f }
55769
  },
55770
/* divx.l ${Dsp-24-u8}[$Dst32AnPrefixed] */
55771
  {
55772
    { 0, 0, 0, 0 },
55773
    { { MNEM, ' ', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
55774
    & ifmt_mulu_l_dst32_24_8_An_relative_Prefixed_SI, { 0x1a32f00 }
55775
  },
55776
/* divx.l ${Dsp-24-u16}[$Dst32AnPrefixed] */
55777
  {
55778
    { 0, 0, 0, 0 },
55779
    { { MNEM, ' ', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
55780
    & ifmt_mulu_l_dst32_24_16_An_relative_Prefixed_SI, { 0x1a52f00 }
55781
  },
55782
/* divx.l ${Dsp-24-u24}[$Dst32AnPrefixed] */
55783
  {
55784
    { 0, 0, 0, 0 },
55785
    { { MNEM, ' ', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
55786
    & ifmt_mulu_l_dst32_24_24_An_relative_Prefixed_SI, { 0x1a72f00 }
55787
  },
55788
/* divx.l ${Dsp-24-u8}[sb] */
55789
  {
55790
    { 0, 0, 0, 0 },
55791
    { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
55792
    & ifmt_mulu_l_dst32_24_8_SB_relative_Prefixed_SI, { 0x1a3af00 }
55793
  },
55794
/* divx.l ${Dsp-24-u16}[sb] */
55795
  {
55796
    { 0, 0, 0, 0 },
55797
    { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
55798
    & ifmt_mulu_l_dst32_24_16_SB_relative_Prefixed_SI, { 0x1a5af00 }
55799
  },
55800
/* divx.l ${Dsp-24-s8}[fb] */
55801
  {
55802
    { 0, 0, 0, 0 },
55803
    { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
55804
    & ifmt_mulu_l_dst32_24_8_FB_relative_Prefixed_SI, { 0x1a3ef00 }
55805
  },
55806
/* divx.l ${Dsp-24-s16}[fb] */
55807
  {
55808
    { 0, 0, 0, 0 },
55809
    { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
55810
    & ifmt_mulu_l_dst32_24_16_FB_relative_Prefixed_SI, { 0x1a5ef00 }
55811
  },
55812
/* divx.l ${Dsp-24-u16} */
55813
  {
55814
    { 0, 0, 0, 0 },
55815
    { { MNEM, ' ', OP (DSP_24_U16), 0 } },
55816
    & ifmt_mulu_l_dst32_24_16_absolute_Prefixed_SI, { 0x1a7ef00 }
55817
  },
55818
/* divx.l ${Dsp-24-u24} */
55819
  {
55820
    { 0, 0, 0, 0 },
55821
    { { MNEM, ' ', OP (DSP_24_U24), 0 } },
55822
    & ifmt_mulu_l_dst32_24_24_absolute_Prefixed_SI, { 0x1a7af00 }
55823
  },
55824
/* divu.l $Dst32RnPrefixedSI */
55825
  {
55826
    { 0, 0, 0, 0 },
55827
    { { MNEM, ' ', OP (DST32RNPREFIXEDSI), 0 } },
55828
    & ifmt_mulu_l_dst32_Rn_direct_Prefixed_SI, { 0x1a90f }
55829
  },
55830
/* divu.l $Dst32AnPrefixedSI */
55831
  {
55832
    { 0, 0, 0, 0 },
55833
    { { MNEM, ' ', OP (DST32ANPREFIXEDSI), 0 } },
55834
    & ifmt_mulu_l_dst32_An_direct_Prefixed_SI, { 0x1a18f }
55835
  },
55836
/* divu.l [$Dst32AnPrefixed] */
55837
  {
55838
    { 0, 0, 0, 0 },
55839
    { { MNEM, ' ', '[', OP (DST32ANPREFIXED), ']', 0 } },
55840
    & ifmt_mulu_l_dst32_An_indirect_Prefixed_SI, { 0x1a10f }
55841
  },
55842
/* divu.l ${Dsp-24-u8}[$Dst32AnPrefixed] */
55843
  {
55844
    { 0, 0, 0, 0 },
55845
    { { MNEM, ' ', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
55846
    & ifmt_mulu_l_dst32_24_8_An_relative_Prefixed_SI, { 0x1a30f00 }
55847
  },
55848
/* divu.l ${Dsp-24-u16}[$Dst32AnPrefixed] */
55849
  {
55850
    { 0, 0, 0, 0 },
55851
    { { MNEM, ' ', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
55852
    & ifmt_mulu_l_dst32_24_16_An_relative_Prefixed_SI, { 0x1a50f00 }
55853
  },
55854
/* divu.l ${Dsp-24-u24}[$Dst32AnPrefixed] */
55855
  {
55856
    { 0, 0, 0, 0 },
55857
    { { MNEM, ' ', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
55858
    & ifmt_mulu_l_dst32_24_24_An_relative_Prefixed_SI, { 0x1a70f00 }
55859
  },
55860
/* divu.l ${Dsp-24-u8}[sb] */
55861
  {
55862
    { 0, 0, 0, 0 },
55863
    { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
55864
    & ifmt_mulu_l_dst32_24_8_SB_relative_Prefixed_SI, { 0x1a38f00 }
55865
  },
55866
/* divu.l ${Dsp-24-u16}[sb] */
55867
  {
55868
    { 0, 0, 0, 0 },
55869
    { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
55870
    & ifmt_mulu_l_dst32_24_16_SB_relative_Prefixed_SI, { 0x1a58f00 }
55871
  },
55872
/* divu.l ${Dsp-24-s8}[fb] */
55873
  {
55874
    { 0, 0, 0, 0 },
55875
    { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
55876
    & ifmt_mulu_l_dst32_24_8_FB_relative_Prefixed_SI, { 0x1a3cf00 }
55877
  },
55878
/* divu.l ${Dsp-24-s16}[fb] */
55879
  {
55880
    { 0, 0, 0, 0 },
55881
    { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
55882
    & ifmt_mulu_l_dst32_24_16_FB_relative_Prefixed_SI, { 0x1a5cf00 }
55883
  },
55884
/* divu.l ${Dsp-24-u16} */
55885
  {
55886
    { 0, 0, 0, 0 },
55887
    { { MNEM, ' ', OP (DSP_24_U16), 0 } },
55888
    & ifmt_mulu_l_dst32_24_16_absolute_Prefixed_SI, { 0x1a7cf00 }
55889
  },
55890
/* divu.l ${Dsp-24-u24} */
55891
  {
55892
    { 0, 0, 0, 0 },
55893
    { { MNEM, ' ', OP (DSP_24_U24), 0 } },
55894
    & ifmt_mulu_l_dst32_24_24_absolute_Prefixed_SI, { 0x1a78f00 }
55895
  },
55896
/* div.l $Dst32RnPrefixedSI */
55897
  {
55898
    { 0, 0, 0, 0 },
55899
    { { MNEM, ' ', OP (DST32RNPREFIXEDSI), 0 } },
55900
    & ifmt_mulu_l_dst32_Rn_direct_Prefixed_SI, { 0x1a91f }
55901
  },
55902
/* div.l $Dst32AnPrefixedSI */
55903
  {
55904
    { 0, 0, 0, 0 },
55905
    { { MNEM, ' ', OP (DST32ANPREFIXEDSI), 0 } },
55906
    & ifmt_mulu_l_dst32_An_direct_Prefixed_SI, { 0x1a19f }
55907
  },
55908
/* div.l [$Dst32AnPrefixed] */
55909
  {
55910
    { 0, 0, 0, 0 },
55911
    { { MNEM, ' ', '[', OP (DST32ANPREFIXED), ']', 0 } },
55912
    & ifmt_mulu_l_dst32_An_indirect_Prefixed_SI, { 0x1a11f }
55913
  },
55914
/* div.l ${Dsp-24-u8}[$Dst32AnPrefixed] */
55915
  {
55916
    { 0, 0, 0, 0 },
55917
    { { MNEM, ' ', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
55918
    & ifmt_mulu_l_dst32_24_8_An_relative_Prefixed_SI, { 0x1a31f00 }
55919
  },
55920
/* div.l ${Dsp-24-u16}[$Dst32AnPrefixed] */
55921
  {
55922
    { 0, 0, 0, 0 },
55923
    { { MNEM, ' ', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
55924
    & ifmt_mulu_l_dst32_24_16_An_relative_Prefixed_SI, { 0x1a51f00 }
55925
  },
55926
/* div.l ${Dsp-24-u24}[$Dst32AnPrefixed] */
55927
  {
55928
    { 0, 0, 0, 0 },
55929
    { { MNEM, ' ', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
55930
    & ifmt_mulu_l_dst32_24_24_An_relative_Prefixed_SI, { 0x1a71f00 }
55931
  },
55932
/* div.l ${Dsp-24-u8}[sb] */
55933
  {
55934
    { 0, 0, 0, 0 },
55935
    { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
55936
    & ifmt_mulu_l_dst32_24_8_SB_relative_Prefixed_SI, { 0x1a39f00 }
55937
  },
55938
/* div.l ${Dsp-24-u16}[sb] */
55939
  {
55940
    { 0, 0, 0, 0 },
55941
    { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
55942
    & ifmt_mulu_l_dst32_24_16_SB_relative_Prefixed_SI, { 0x1a59f00 }
55943
  },
55944
/* div.l ${Dsp-24-s8}[fb] */
55945
  {
55946
    { 0, 0, 0, 0 },
55947
    { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
55948
    & ifmt_mulu_l_dst32_24_8_FB_relative_Prefixed_SI, { 0x1a3df00 }
55949
  },
55950
/* div.l ${Dsp-24-s16}[fb] */
55951
  {
55952
    { 0, 0, 0, 0 },
55953
    { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
55954
    & ifmt_mulu_l_dst32_24_16_FB_relative_Prefixed_SI, { 0x1a5df00 }
55955
  },
55956
/* div.l ${Dsp-24-u16} */
55957
  {
55958
    { 0, 0, 0, 0 },
55959
    { { MNEM, ' ', OP (DSP_24_U16), 0 } },
55960
    & ifmt_mulu_l_dst32_24_16_absolute_Prefixed_SI, { 0x1a7df00 }
55961
  },
55962
/* div.l ${Dsp-24-u24} */
55963
  {
55964
    { 0, 0, 0, 0 },
55965
    { { MNEM, ' ', OP (DSP_24_U24), 0 } },
55966
    & ifmt_mulu_l_dst32_24_24_absolute_Prefixed_SI, { 0x1a79f00 }
55967
  },
55968
/* divx.w $Dst32RnUnprefixedHI */
55969
  {
55970
    { 0, 0, 0, 0 },
55971
    { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } },
55972
    & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0x991e }
55973
  },
55974
/* divx.w $Dst32AnUnprefixedHI */
55975
  {
55976
    { 0, 0, 0, 0 },
55977
    { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } },
55978
    & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0x919e }
55979
  },
55980
/* divx.w [$Dst32AnUnprefixed] */
55981
  {
55982
    { 0, 0, 0, 0 },
55983
    { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
55984
    & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0x911e }
55985
  },
55986
/* divx.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
55987
  {
55988
    { 0, 0, 0, 0 },
55989
    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
55990
    & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0x931e00 }
55991
  },
55992
/* divx.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
55993
  {
55994
    { 0, 0, 0, 0 },
55995
    { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
55996
    & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0x951e0000 }
55997
  },
55998
/* divx.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
55999
  {
56000
    { 0, 0, 0, 0 },
56001
    { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
56002
    & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0x971e0000 }
56003
  },
56004
/* divx.w ${Dsp-16-u8}[sb] */
56005
  {
56006
    { 0, 0, 0, 0 },
56007
    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
56008
    & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0x939e00 }
56009
  },
56010
/* divx.w ${Dsp-16-u16}[sb] */
56011
  {
56012
    { 0, 0, 0, 0 },
56013
    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
56014
    & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0x959e0000 }
56015
  },
56016
/* divx.w ${Dsp-16-s8}[fb] */
56017
  {
56018
    { 0, 0, 0, 0 },
56019
    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
56020
    & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0x93de00 }
56021
  },
56022
/* divx.w ${Dsp-16-s16}[fb] */
56023
  {
56024
    { 0, 0, 0, 0 },
56025
    { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
56026
    & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0x95de0000 }
56027
  },
56028
/* divx.w ${Dsp-16-u16} */
56029
  {
56030
    { 0, 0, 0, 0 },
56031
    { { MNEM, ' ', OP (DSP_16_U16), 0 } },
56032
    & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0x97de0000 }
56033
  },
56034
/* divx.w ${Dsp-16-u24} */
56035
  {
56036
    { 0, 0, 0, 0 },
56037
    { { MNEM, ' ', OP (DSP_16_U24), 0 } },
56038
    & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0x979e0000 }
56039
  },
56040
/* divx.b $Dst32RnUnprefixedQI */
56041
  {
56042
    { 0, 0, 0, 0 },
56043
    { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } },
56044
    & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0x981e }
56045
  },
56046
/* divx.b $Dst32AnUnprefixedQI */
56047
  {
56048
    { 0, 0, 0, 0 },
56049
    { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } },
56050
    & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0x909e }
56051
  },
56052
/* divx.b [$Dst32AnUnprefixed] */
56053
  {
56054
    { 0, 0, 0, 0 },
56055
    { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
56056
    & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0x901e }
56057
  },
56058
/* divx.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
56059
  {
56060
    { 0, 0, 0, 0 },
56061
    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
56062
    & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0x921e00 }
56063
  },
56064
/* divx.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
56065
  {
56066
    { 0, 0, 0, 0 },
56067
    { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
56068
    & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0x941e0000 }
56069
  },
56070
/* divx.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
56071
  {
56072
    { 0, 0, 0, 0 },
56073
    { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
56074
    & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0x961e0000 }
56075
  },
56076
/* divx.b ${Dsp-16-u8}[sb] */
56077
  {
56078
    { 0, 0, 0, 0 },
56079
    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
56080
    & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0x929e00 }
56081
  },
56082
/* divx.b ${Dsp-16-u16}[sb] */
56083
  {
56084
    { 0, 0, 0, 0 },
56085
    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
56086
    & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0x949e0000 }
56087
  },
56088
/* divx.b ${Dsp-16-s8}[fb] */
56089
  {
56090
    { 0, 0, 0, 0 },
56091
    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
56092
    & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0x92de00 }
56093
  },
56094
/* divx.b ${Dsp-16-s16}[fb] */
56095
  {
56096
    { 0, 0, 0, 0 },
56097
    { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
56098
    & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0x94de0000 }
56099
  },
56100
/* divx.b ${Dsp-16-u16} */
56101
  {
56102
    { 0, 0, 0, 0 },
56103
    { { MNEM, ' ', OP (DSP_16_U16), 0 } },
56104
    & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0x96de0000 }
56105
  },
56106
/* divx.b ${Dsp-16-u24} */
56107
  {
56108
    { 0, 0, 0, 0 },
56109
    { { MNEM, ' ', OP (DSP_16_U24), 0 } },
56110
    & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0x969e0000 }
56111
  },
56112
/* divx.w $Dst16RnHI */
56113
  {
56114
    { 0, 0, 0, 0 },
56115
    { { MNEM, ' ', OP (DST16RNHI), 0 } },
56116
    & ifmt_rorc16_w_16_dst16_Rn_direct_HI, { 0x7790 }
56117
  },
56118
/* divx.w $Dst16AnHI */
56119
  {
56120
    { 0, 0, 0, 0 },
56121
    { { MNEM, ' ', OP (DST16ANHI), 0 } },
56122
    & ifmt_rorc16_w_16_dst16_An_direct_HI, { 0x7794 }
56123
  },
56124
/* divx.w [$Dst16An] */
56125
  {
56126
    { 0, 0, 0, 0 },
56127
    { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } },
56128
    & ifmt_rorc16_w_16_dst16_An_indirect_HI, { 0x7796 }
56129
  },
56130
/* divx.w ${Dsp-16-u8}[$Dst16An] */
56131
  {
56132
    { 0, 0, 0, 0 },
56133
    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
56134
    & ifmt_rorc16_w_16_dst16_16_8_An_relative_HI, { 0x779800 }
56135
  },
56136
/* divx.w ${Dsp-16-u16}[$Dst16An] */
56137
  {
56138
    { 0, 0, 0, 0 },
56139
    { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
56140
    & ifmt_rorc16_w_16_dst16_16_16_An_relative_HI, { 0x779c0000 }
56141
  },
56142
/* divx.w ${Dsp-16-u8}[sb] */
56143
  {
56144
    { 0, 0, 0, 0 },
56145
    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
56146
    & ifmt_rorc16_w_16_dst16_16_8_SB_relative_HI, { 0x779a00 }
56147
  },
56148
/* divx.w ${Dsp-16-u16}[sb] */
56149
  {
56150
    { 0, 0, 0, 0 },
56151
    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
56152
    & ifmt_rorc16_w_16_dst16_16_16_SB_relative_HI, { 0x779e0000 }
56153
  },
56154
/* divx.w ${Dsp-16-s8}[fb] */
56155
  {
56156
    { 0, 0, 0, 0 },
56157
    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
56158
    & ifmt_rorc16_w_16_dst16_16_8_FB_relative_HI, { 0x779b00 }
56159
  },
56160
/* divx.w ${Dsp-16-u16} */
56161
  {
56162
    { 0, 0, 0, 0 },
56163
    { { MNEM, ' ', OP (DSP_16_U16), 0 } },
56164
    & ifmt_rorc16_w_16_dst16_16_16_absolute_HI, { 0x779f0000 }
56165
  },
56166
/* divx.b $Dst16RnQI */
56167
  {
56168
    { 0, 0, 0, 0 },
56169
    { { MNEM, ' ', OP (DST16RNQI), 0 } },
56170
    & ifmt_rorc16_b_16_dst16_Rn_direct_QI, { 0x7690 }
56171
  },
56172
/* divx.b $Dst16AnQI */
56173
  {
56174
    { 0, 0, 0, 0 },
56175
    { { MNEM, ' ', OP (DST16ANQI), 0 } },
56176
    & ifmt_rorc16_b_16_dst16_An_direct_QI, { 0x7694 }
56177
  },
56178
/* divx.b [$Dst16An] */
56179
  {
56180
    { 0, 0, 0, 0 },
56181
    { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } },
56182
    & ifmt_rorc16_b_16_dst16_An_indirect_QI, { 0x7696 }
56183
  },
56184
/* divx.b ${Dsp-16-u8}[$Dst16An] */
56185
  {
56186
    { 0, 0, 0, 0 },
56187
    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
56188
    & ifmt_rorc16_b_16_dst16_16_8_An_relative_QI, { 0x769800 }
56189
  },
56190
/* divx.b ${Dsp-16-u16}[$Dst16An] */
56191
  {
56192
    { 0, 0, 0, 0 },
56193
    { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
56194
    & ifmt_rorc16_b_16_dst16_16_16_An_relative_QI, { 0x769c0000 }
56195
  },
56196
/* divx.b ${Dsp-16-u8}[sb] */
56197
  {
56198
    { 0, 0, 0, 0 },
56199
    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
56200
    & ifmt_rorc16_b_16_dst16_16_8_SB_relative_QI, { 0x769a00 }
56201
  },
56202
/* divx.b ${Dsp-16-u16}[sb] */
56203
  {
56204
    { 0, 0, 0, 0 },
56205
    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
56206
    & ifmt_rorc16_b_16_dst16_16_16_SB_relative_QI, { 0x769e0000 }
56207
  },
56208
/* divx.b ${Dsp-16-s8}[fb] */
56209
  {
56210
    { 0, 0, 0, 0 },
56211
    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
56212
    & ifmt_rorc16_b_16_dst16_16_8_FB_relative_QI, { 0x769b00 }
56213
  },
56214
/* divx.b ${Dsp-16-u16} */
56215
  {
56216
    { 0, 0, 0, 0 },
56217
    { { MNEM, ' ', OP (DSP_16_U16), 0 } },
56218
    & ifmt_rorc16_b_16_dst16_16_16_absolute_QI, { 0x769f0000 }
56219
  },
56220
/* divu.w $Dst32RnUnprefixedHI */
56221
  {
56222
    { 0, 0, 0, 0 },
56223
    { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } },
56224
    & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0x890e }
56225
  },
56226
/* divu.w $Dst32AnUnprefixedHI */
56227
  {
56228
    { 0, 0, 0, 0 },
56229
    { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } },
56230
    & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0x818e }
56231
  },
56232
/* divu.w [$Dst32AnUnprefixed] */
56233
  {
56234
    { 0, 0, 0, 0 },
56235
    { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
56236
    & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0x810e }
56237
  },
56238
/* divu.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
56239
  {
56240
    { 0, 0, 0, 0 },
56241
    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
56242
    & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0x830e00 }
56243
  },
56244
/* divu.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
56245
  {
56246
    { 0, 0, 0, 0 },
56247
    { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
56248
    & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0x850e0000 }
56249
  },
56250
/* divu.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
56251
  {
56252
    { 0, 0, 0, 0 },
56253
    { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
56254
    & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0x870e0000 }
56255
  },
56256
/* divu.w ${Dsp-16-u8}[sb] */
56257
  {
56258
    { 0, 0, 0, 0 },
56259
    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
56260
    & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0x838e00 }
56261
  },
56262
/* divu.w ${Dsp-16-u16}[sb] */
56263
  {
56264
    { 0, 0, 0, 0 },
56265
    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
56266
    & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0x858e0000 }
56267
  },
56268
/* divu.w ${Dsp-16-s8}[fb] */
56269
  {
56270
    { 0, 0, 0, 0 },
56271
    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
56272
    & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83ce00 }
56273
  },
56274
/* divu.w ${Dsp-16-s16}[fb] */
56275
  {
56276
    { 0, 0, 0, 0 },
56277
    { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
56278
    & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85ce0000 }
56279
  },
56280
/* divu.w ${Dsp-16-u16} */
56281
  {
56282
    { 0, 0, 0, 0 },
56283
    { { MNEM, ' ', OP (DSP_16_U16), 0 } },
56284
    & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0x87ce0000 }
56285
  },
56286
/* divu.w ${Dsp-16-u24} */
56287
  {
56288
    { 0, 0, 0, 0 },
56289
    { { MNEM, ' ', OP (DSP_16_U24), 0 } },
56290
    & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0x878e0000 }
56291
  },
56292
/* divu.b $Dst32RnUnprefixedQI */
56293
  {
56294
    { 0, 0, 0, 0 },
56295
    { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } },
56296
    & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0x880e }
56297
  },
56298
/* divu.b $Dst32AnUnprefixedQI */
56299
  {
56300
    { 0, 0, 0, 0 },
56301
    { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } },
56302
    & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0x808e }
56303
  },
56304
/* divu.b [$Dst32AnUnprefixed] */
56305
  {
56306
    { 0, 0, 0, 0 },
56307
    { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
56308
    & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0x800e }
56309
  },
56310
/* divu.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
56311
  {
56312
    { 0, 0, 0, 0 },
56313
    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
56314
    & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0x820e00 }
56315
  },
56316
/* divu.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
56317
  {
56318
    { 0, 0, 0, 0 },
56319
    { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
56320
    & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0x840e0000 }
56321
  },
56322
/* divu.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
56323
  {
56324
    { 0, 0, 0, 0 },
56325
    { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
56326
    & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0x860e0000 }
56327
  },
56328
/* divu.b ${Dsp-16-u8}[sb] */
56329
  {
56330
    { 0, 0, 0, 0 },
56331
    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
56332
    & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0x828e00 }
56333
  },
56334
/* divu.b ${Dsp-16-u16}[sb] */
56335
  {
56336
    { 0, 0, 0, 0 },
56337
    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
56338
    & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0x848e0000 }
56339
  },
56340
/* divu.b ${Dsp-16-s8}[fb] */
56341
  {
56342
    { 0, 0, 0, 0 },
56343
    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
56344
    & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82ce00 }
56345
  },
56346
/* divu.b ${Dsp-16-s16}[fb] */
56347
  {
56348
    { 0, 0, 0, 0 },
56349
    { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
56350
    & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84ce0000 }
56351
  },
56352
/* divu.b ${Dsp-16-u16} */
56353
  {
56354
    { 0, 0, 0, 0 },
56355
    { { MNEM, ' ', OP (DSP_16_U16), 0 } },
56356
    & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0x86ce0000 }
56357
  },
56358
/* divu.b ${Dsp-16-u24} */
56359
  {
56360
    { 0, 0, 0, 0 },
56361
    { { MNEM, ' ', OP (DSP_16_U24), 0 } },
56362
    & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0x868e0000 }
56363
  },
56364
/* divu.w $Dst16RnHI */
56365
  {
56366
    { 0, 0, 0, 0 },
56367
    { { MNEM, ' ', OP (DST16RNHI), 0 } },
56368
    & ifmt_rorc16_w_16_dst16_Rn_direct_HI, { 0x77c0 }
56369
  },
56370
/* divu.w $Dst16AnHI */
56371
  {
56372
    { 0, 0, 0, 0 },
56373
    { { MNEM, ' ', OP (DST16ANHI), 0 } },
56374
    & ifmt_rorc16_w_16_dst16_An_direct_HI, { 0x77c4 }
56375
  },
56376
/* divu.w [$Dst16An] */
56377
  {
56378
    { 0, 0, 0, 0 },
56379
    { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } },
56380
    & ifmt_rorc16_w_16_dst16_An_indirect_HI, { 0x77c6 }
56381
  },
56382
/* divu.w ${Dsp-16-u8}[$Dst16An] */
56383
  {
56384
    { 0, 0, 0, 0 },
56385
    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
56386
    & ifmt_rorc16_w_16_dst16_16_8_An_relative_HI, { 0x77c800 }
56387
  },
56388
/* divu.w ${Dsp-16-u16}[$Dst16An] */
56389
  {
56390
    { 0, 0, 0, 0 },
56391
    { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
56392
    & ifmt_rorc16_w_16_dst16_16_16_An_relative_HI, { 0x77cc0000 }
56393
  },
56394
/* divu.w ${Dsp-16-u8}[sb] */
56395
  {
56396
    { 0, 0, 0, 0 },
56397
    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
56398
    & ifmt_rorc16_w_16_dst16_16_8_SB_relative_HI, { 0x77ca00 }
56399
  },
56400
/* divu.w ${Dsp-16-u16}[sb] */
56401
  {
56402
    { 0, 0, 0, 0 },
56403
    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
56404
    & ifmt_rorc16_w_16_dst16_16_16_SB_relative_HI, { 0x77ce0000 }
56405
  },
56406
/* divu.w ${Dsp-16-s8}[fb] */
56407
  {
56408
    { 0, 0, 0, 0 },
56409
    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
56410
    & ifmt_rorc16_w_16_dst16_16_8_FB_relative_HI, { 0x77cb00 }
56411
  },
56412
/* divu.w ${Dsp-16-u16} */
56413
  {
56414
    { 0, 0, 0, 0 },
56415
    { { MNEM, ' ', OP (DSP_16_U16), 0 } },
56416
    & ifmt_rorc16_w_16_dst16_16_16_absolute_HI, { 0x77cf0000 }
56417
  },
56418
/* divu.b $Dst16RnQI */
56419
  {
56420
    { 0, 0, 0, 0 },
56421
    { { MNEM, ' ', OP (DST16RNQI), 0 } },
56422
    & ifmt_rorc16_b_16_dst16_Rn_direct_QI, { 0x76c0 }
56423
  },
56424
/* divu.b $Dst16AnQI */
56425
  {
56426
    { 0, 0, 0, 0 },
56427
    { { MNEM, ' ', OP (DST16ANQI), 0 } },
56428
    & ifmt_rorc16_b_16_dst16_An_direct_QI, { 0x76c4 }
56429
  },
56430
/* divu.b [$Dst16An] */
56431
  {
56432
    { 0, 0, 0, 0 },
56433
    { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } },
56434
    & ifmt_rorc16_b_16_dst16_An_indirect_QI, { 0x76c6 }
56435
  },
56436
/* divu.b ${Dsp-16-u8}[$Dst16An] */
56437
  {
56438
    { 0, 0, 0, 0 },
56439
    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
56440
    & ifmt_rorc16_b_16_dst16_16_8_An_relative_QI, { 0x76c800 }
56441
  },
56442
/* divu.b ${Dsp-16-u16}[$Dst16An] */
56443
  {
56444
    { 0, 0, 0, 0 },
56445
    { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
56446
    & ifmt_rorc16_b_16_dst16_16_16_An_relative_QI, { 0x76cc0000 }
56447
  },
56448
/* divu.b ${Dsp-16-u8}[sb] */
56449
  {
56450
    { 0, 0, 0, 0 },
56451
    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
56452
    & ifmt_rorc16_b_16_dst16_16_8_SB_relative_QI, { 0x76ca00 }
56453
  },
56454
/* divu.b ${Dsp-16-u16}[sb] */
56455
  {
56456
    { 0, 0, 0, 0 },
56457
    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
56458
    & ifmt_rorc16_b_16_dst16_16_16_SB_relative_QI, { 0x76ce0000 }
56459
  },
56460
/* divu.b ${Dsp-16-s8}[fb] */
56461
  {
56462
    { 0, 0, 0, 0 },
56463
    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
56464
    & ifmt_rorc16_b_16_dst16_16_8_FB_relative_QI, { 0x76cb00 }
56465
  },
56466
/* divu.b ${Dsp-16-u16} */
56467
  {
56468
    { 0, 0, 0, 0 },
56469
    { { MNEM, ' ', OP (DSP_16_U16), 0 } },
56470
    & ifmt_rorc16_b_16_dst16_16_16_absolute_QI, { 0x76cf0000 }
56471
  },
56472
/* div.w $Dst32RnUnprefixedHI */
56473
  {
56474
    { 0, 0, 0, 0 },
56475
    { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } },
56476
    & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0x891e }
56477
  },
56478
/* div.w $Dst32AnUnprefixedHI */
56479
  {
56480
    { 0, 0, 0, 0 },
56481
    { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } },
56482
    & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0x819e }
56483
  },
56484
/* div.w [$Dst32AnUnprefixed] */
56485
  {
56486
    { 0, 0, 0, 0 },
56487
    { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
56488
    & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0x811e }
56489
  },
56490
/* div.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
56491
  {
56492
    { 0, 0, 0, 0 },
56493
    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
56494
    & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0x831e00 }
56495
  },
56496
/* div.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
56497
  {
56498
    { 0, 0, 0, 0 },
56499
    { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
56500
    & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0x851e0000 }
56501
  },
56502
/* div.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
56503
  {
56504
    { 0, 0, 0, 0 },
56505
    { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
56506
    & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0x871e0000 }
56507
  },
56508
/* div.w ${Dsp-16-u8}[sb] */
56509
  {
56510
    { 0, 0, 0, 0 },
56511
    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
56512
    & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0x839e00 }
56513
  },
56514
/* div.w ${Dsp-16-u16}[sb] */
56515
  {
56516
    { 0, 0, 0, 0 },
56517
    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
56518
    & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0x859e0000 }
56519
  },
56520
/* div.w ${Dsp-16-s8}[fb] */
56521
  {
56522
    { 0, 0, 0, 0 },
56523
    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
56524
    & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83de00 }
56525
  },
56526
/* div.w ${Dsp-16-s16}[fb] */
56527
  {
56528
    { 0, 0, 0, 0 },
56529
    { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
56530
    & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85de0000 }
56531
  },
56532
/* div.w ${Dsp-16-u16} */
56533
  {
56534
    { 0, 0, 0, 0 },
56535
    { { MNEM, ' ', OP (DSP_16_U16), 0 } },
56536
    & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0x87de0000 }
56537
  },
56538
/* div.w ${Dsp-16-u24} */
56539
  {
56540
    { 0, 0, 0, 0 },
56541
    { { MNEM, ' ', OP (DSP_16_U24), 0 } },
56542
    & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0x879e0000 }
56543
  },
56544
/* div.b $Dst32RnUnprefixedQI */
56545
  {
56546
    { 0, 0, 0, 0 },
56547
    { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } },
56548
    & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0x881e }
56549
  },
56550
/* div.b $Dst32AnUnprefixedQI */
56551
  {
56552
    { 0, 0, 0, 0 },
56553
    { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } },
56554
    & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0x809e }
56555
  },
56556
/* div.b [$Dst32AnUnprefixed] */
56557
  {
56558
    { 0, 0, 0, 0 },
56559
    { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
56560
    & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0x801e }
56561
  },
56562
/* div.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
56563
  {
56564
    { 0, 0, 0, 0 },
56565
    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
56566
    & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0x821e00 }
56567
  },
56568
/* div.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
56569
  {
56570
    { 0, 0, 0, 0 },
56571
    { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
56572
    & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0x841e0000 }
56573
  },
56574
/* div.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
56575
  {
56576
    { 0, 0, 0, 0 },
56577
    { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
56578
    & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0x861e0000 }
56579
  },
56580
/* div.b ${Dsp-16-u8}[sb] */
56581
  {
56582
    { 0, 0, 0, 0 },
56583
    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
56584
    & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0x829e00 }
56585
  },
56586
/* div.b ${Dsp-16-u16}[sb] */
56587
  {
56588
    { 0, 0, 0, 0 },
56589
    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
56590
    & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0x849e0000 }
56591
  },
56592
/* div.b ${Dsp-16-s8}[fb] */
56593
  {
56594
    { 0, 0, 0, 0 },
56595
    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
56596
    & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82de00 }
56597
  },
56598
/* div.b ${Dsp-16-s16}[fb] */
56599
  {
56600
    { 0, 0, 0, 0 },
56601
    { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
56602
    & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84de0000 }
56603
  },
56604
/* div.b ${Dsp-16-u16} */
56605
  {
56606
    { 0, 0, 0, 0 },
56607
    { { MNEM, ' ', OP (DSP_16_U16), 0 } },
56608
    & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0x86de0000 }
56609
  },
56610
/* div.b ${Dsp-16-u24} */
56611
  {
56612
    { 0, 0, 0, 0 },
56613
    { { MNEM, ' ', OP (DSP_16_U24), 0 } },
56614
    & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0x869e0000 }
56615
  },
56616
/* div.w $Dst16RnHI */
56617
  {
56618
    { 0, 0, 0, 0 },
56619
    { { MNEM, ' ', OP (DST16RNHI), 0 } },
56620
    & ifmt_rorc16_w_16_dst16_Rn_direct_HI, { 0x77d0 }
56621
  },
56622
/* div.w $Dst16AnHI */
56623
  {
56624
    { 0, 0, 0, 0 },
56625
    { { MNEM, ' ', OP (DST16ANHI), 0 } },
56626
    & ifmt_rorc16_w_16_dst16_An_direct_HI, { 0x77d4 }
56627
  },
56628
/* div.w [$Dst16An] */
56629
  {
56630
    { 0, 0, 0, 0 },
56631
    { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } },
56632
    & ifmt_rorc16_w_16_dst16_An_indirect_HI, { 0x77d6 }
56633
  },
56634
/* div.w ${Dsp-16-u8}[$Dst16An] */
56635
  {
56636
    { 0, 0, 0, 0 },
56637
    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
56638
    & ifmt_rorc16_w_16_dst16_16_8_An_relative_HI, { 0x77d800 }
56639
  },
56640
/* div.w ${Dsp-16-u16}[$Dst16An] */
56641
  {
56642
    { 0, 0, 0, 0 },
56643
    { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
56644
    & ifmt_rorc16_w_16_dst16_16_16_An_relative_HI, { 0x77dc0000 }
56645
  },
56646
/* div.w ${Dsp-16-u8}[sb] */
56647
  {
56648
    { 0, 0, 0, 0 },
56649
    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
56650
    & ifmt_rorc16_w_16_dst16_16_8_SB_relative_HI, { 0x77da00 }
56651
  },
56652
/* div.w ${Dsp-16-u16}[sb] */
56653
  {
56654
    { 0, 0, 0, 0 },
56655
    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
56656
    & ifmt_rorc16_w_16_dst16_16_16_SB_relative_HI, { 0x77de0000 }
56657
  },
56658
/* div.w ${Dsp-16-s8}[fb] */
56659
  {
56660
    { 0, 0, 0, 0 },
56661
    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
56662
    & ifmt_rorc16_w_16_dst16_16_8_FB_relative_HI, { 0x77db00 }
56663
  },
56664
/* div.w ${Dsp-16-u16} */
56665
  {
56666
    { 0, 0, 0, 0 },
56667
    { { MNEM, ' ', OP (DSP_16_U16), 0 } },
56668
    & ifmt_rorc16_w_16_dst16_16_16_absolute_HI, { 0x77df0000 }
56669
  },
56670
/* div.b $Dst16RnQI */
56671
  {
56672
    { 0, 0, 0, 0 },
56673
    { { MNEM, ' ', OP (DST16RNQI), 0 } },
56674
    & ifmt_rorc16_b_16_dst16_Rn_direct_QI, { 0x76d0 }
56675
  },
56676
/* div.b $Dst16AnQI */
56677
  {
56678
    { 0, 0, 0, 0 },
56679
    { { MNEM, ' ', OP (DST16ANQI), 0 } },
56680
    & ifmt_rorc16_b_16_dst16_An_direct_QI, { 0x76d4 }
56681
  },
56682
/* div.b [$Dst16An] */
56683
  {
56684
    { 0, 0, 0, 0 },
56685
    { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } },
56686
    & ifmt_rorc16_b_16_dst16_An_indirect_QI, { 0x76d6 }
56687
  },
56688
/* div.b ${Dsp-16-u8}[$Dst16An] */
56689
  {
56690
    { 0, 0, 0, 0 },
56691
    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
56692
    & ifmt_rorc16_b_16_dst16_16_8_An_relative_QI, { 0x76d800 }
56693
  },
56694
/* div.b ${Dsp-16-u16}[$Dst16An] */
56695
  {
56696
    { 0, 0, 0, 0 },
56697
    { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
56698
    & ifmt_rorc16_b_16_dst16_16_16_An_relative_QI, { 0x76dc0000 }
56699
  },
56700
/* div.b ${Dsp-16-u8}[sb] */
56701
  {
56702
    { 0, 0, 0, 0 },
56703
    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
56704
    & ifmt_rorc16_b_16_dst16_16_8_SB_relative_QI, { 0x76da00 }
56705
  },
56706
/* div.b ${Dsp-16-u16}[sb] */
56707
  {
56708
    { 0, 0, 0, 0 },
56709
    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
56710
    & ifmt_rorc16_b_16_dst16_16_16_SB_relative_QI, { 0x76de0000 }
56711
  },
56712
/* div.b ${Dsp-16-s8}[fb] */
56713
  {
56714
    { 0, 0, 0, 0 },
56715
    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
56716
    & ifmt_rorc16_b_16_dst16_16_8_FB_relative_QI, { 0x76db00 }
56717
  },
56718
/* div.b ${Dsp-16-u16} */
56719
  {
56720
    { 0, 0, 0, 0 },
56721
    { { MNEM, ' ', OP (DSP_16_U16), 0 } },
56722
    & ifmt_rorc16_b_16_dst16_16_16_absolute_QI, { 0x76df0000 }
56723
  },
56724
/* dec.w $Dst32RnUnprefixedHI */
56725
  {
56726
    { 0, 0, 0, 0 },
56727
    { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } },
56728
    & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xb90e }
56729
  },
56730
/* dec.w $Dst32AnUnprefixedHI */
56731
  {
56732
    { 0, 0, 0, 0 },
56733
    { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } },
56734
    & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xb18e }
56735
  },
56736
/* dec.w [$Dst32AnUnprefixed] */
56737
  {
56738
    { 0, 0, 0, 0 },
56739
    { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
56740
    & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xb10e }
56741
  },
56742
/* dec.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
56743
  {
56744
    { 0, 0, 0, 0 },
56745
    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
56746
    & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xb30e00 }
56747
  },
56748
/* dec.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
56749
  {
56750
    { 0, 0, 0, 0 },
56751
    { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
56752
    & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xb50e0000 }
56753
  },
56754
/* dec.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
56755
  {
56756
    { 0, 0, 0, 0 },
56757
    { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
56758
    & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xb70e0000 }
56759
  },
56760
/* dec.w ${Dsp-16-u8}[sb] */
56761
  {
56762
    { 0, 0, 0, 0 },
56763
    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
56764
    & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xb38e00 }
56765
  },
56766
/* dec.w ${Dsp-16-u16}[sb] */
56767
  {
56768
    { 0, 0, 0, 0 },
56769
    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
56770
    & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xb58e0000 }
56771
  },
56772
/* dec.w ${Dsp-16-s8}[fb] */
56773
  {
56774
    { 0, 0, 0, 0 },
56775
    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
56776
    & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xb3ce00 }
56777
  },
56778
/* dec.w ${Dsp-16-s16}[fb] */
56779
  {
56780
    { 0, 0, 0, 0 },
56781
    { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
56782
    & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xb5ce0000 }
56783
  },
56784
/* dec.w ${Dsp-16-u16} */
56785
  {
56786
    { 0, 0, 0, 0 },
56787
    { { MNEM, ' ', OP (DSP_16_U16), 0 } },
56788
    & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xb7ce0000 }
56789
  },
56790
/* dec.w ${Dsp-16-u24} */
56791
  {
56792
    { 0, 0, 0, 0 },
56793
    { { MNEM, ' ', OP (DSP_16_U24), 0 } },
56794
    & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xb78e0000 }
56795
  },
56796
/* dec.b $Dst32RnUnprefixedQI */
56797
  {
56798
    { 0, 0, 0, 0 },
56799
    { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } },
56800
    & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0xb80e }
56801
  },
56802
/* dec.b $Dst32AnUnprefixedQI */
56803
  {
56804
    { 0, 0, 0, 0 },
56805
    { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } },
56806
    & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0xb08e }
56807
  },
56808
/* dec.b [$Dst32AnUnprefixed] */
56809
  {
56810
    { 0, 0, 0, 0 },
56811
    { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
56812
    & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0xb00e }
56813
  },
56814
/* dec.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
56815
  {
56816
    { 0, 0, 0, 0 },
56817
    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
56818
    & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0xb20e00 }
56819
  },
56820
/* dec.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
56821
  {
56822
    { 0, 0, 0, 0 },
56823
    { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
56824
    & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0xb40e0000 }
56825
  },
56826
/* dec.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
56827
  {
56828
    { 0, 0, 0, 0 },
56829
    { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
56830
    & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0xb60e0000 }
56831
  },
56832
/* dec.b ${Dsp-16-u8}[sb] */
56833
  {
56834
    { 0, 0, 0, 0 },
56835
    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
56836
    & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0xb28e00 }
56837
  },
56838
/* dec.b ${Dsp-16-u16}[sb] */
56839
  {
56840
    { 0, 0, 0, 0 },
56841
    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
56842
    & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0xb48e0000 }
56843
  },
56844
/* dec.b ${Dsp-16-s8}[fb] */
56845
  {
56846
    { 0, 0, 0, 0 },
56847
    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
56848
    & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0xb2ce00 }
56849
  },
56850
/* dec.b ${Dsp-16-s16}[fb] */
56851
  {
56852
    { 0, 0, 0, 0 },
56853
    { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
56854
    & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0xb4ce0000 }
56855
  },
56856
/* dec.b ${Dsp-16-u16} */
56857
  {
56858
    { 0, 0, 0, 0 },
56859
    { { MNEM, ' ', OP (DSP_16_U16), 0 } },
56860
    & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0xb6ce0000 }
56861
  },
56862
/* dec.b ${Dsp-16-u24} */
56863
  {
56864
    { 0, 0, 0, 0 },
56865
    { { MNEM, ' ', OP (DSP_16_U24), 0 } },
56866
    & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0xb68e0000 }
56867
  },
56868
/* dec.b r0l */
56869
  {
56870
    { 0, 0, 0, 0 },
56871
    { { MNEM, ' ', 'r', '0', 'l', 0 } },
56872
    & ifmt_not16_b_s_dst16_3_S_R0l_direct_QI, { 0xac }
56873
  },
56874
/* dec.b r0h */
56875
  {
56876
    { 0, 0, 0, 0 },
56877
    { { MNEM, ' ', 'r', '0', 'h', 0 } },
56878
    & ifmt_not16_b_s_dst16_3_S_R0h_direct_QI, { 0xab }
56879
  },
56880
/* dec.b ${Dsp-8-u8}[sb] */
56881
  {
56882
    { 0, 0, 0, 0 },
56883
    { { MNEM, ' ', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } },
56884
    & ifmt_not16_b_s_dst16_3_S_8_8_SB_relative_QI, { 0xad00 }
56885
  },
56886
/* dec.b ${Dsp-8-s8}[fb] */
56887
  {
56888
    { 0, 0, 0, 0 },
56889
    { { MNEM, ' ', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } },
56890
    & ifmt_not16_b_s_dst16_3_S_8_8_FB_relative_QI, { 0xae00 }
56891
  },
56892
/* dec.b ${Dsp-8-u16} */
56893
  {
56894
    { 0, 0, 0, 0 },
56895
    { { MNEM, ' ', OP (DSP_8_U16), 0 } },
56896
    & ifmt_not16_b_s_dst16_3_S_8_16_absolute_QI, { 0xaf0000 }
56897
  },
56898
/* cmpx${X} #${Imm-16-QI},$Dst32RnUnprefixedSI */
56899
  {
56900
    { 0, 0, 0, 0 },
56901
    { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
56902
    & ifmt_subx32_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_SI, { 0xa81100 }
56903
  },
56904
/* cmpx${X} #${Imm-16-QI},$Dst32AnUnprefixedSI */
56905
  {
56906
    { 0, 0, 0, 0 },
56907
    { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
56908
    & ifmt_subx32_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_SI, { 0xa09100 }
56909
  },
56910
/* cmpx${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */
56911
  {
56912
    { 0, 0, 0, 0 },
56913
    { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
56914
    & ifmt_subx32_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_SI, { 0xa01100 }
56915
  },
56916
/* cmpx${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
56917
  {
56918
    { 0, 0, 0, 0 },
56919
    { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
56920
    & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_SI, { 0xa2110000 }
56921
  },
56922
/* cmpx${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
56923
  {
56924
    { 0, 0, 0, 0 },
56925
    { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
56926
    & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_SI, { 0xa2910000 }
56927
  },
56928
/* cmpx${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
56929
  {
56930
    { 0, 0, 0, 0 },
56931
    { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
56932
    & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_SI, { 0xa2d10000 }
56933
  },
56934
/* cmpx${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
56935
  {
56936
    { 0, 0, 0, 0 },
56937
    { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
56938
    & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_SI, { 0xa4110000 }
56939
  },
56940
/* cmpx${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
56941
  {
56942
    { 0, 0, 0, 0 },
56943
    { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
56944
    & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_SI, { 0xa4910000 }
56945
  },
56946
/* cmpx${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */
56947
  {
56948
    { 0, 0, 0, 0 },
56949
    { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
56950
    & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_SI, { 0xa4d10000 }
56951
  },
56952
/* cmpx${X} #${Imm-32-QI},${Dsp-16-u16} */
56953
  {
56954
    { 0, 0, 0, 0 },
56955
    { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } },
56956
    & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_SI, { 0xa6d10000 }
56957
  },
56958
/* cmpx${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
56959
  {
56960
    { 0, 0, 0, 0 },
56961
    { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
56962
    & ifmt_subx32_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_SI, { 0xa6110000 }
56963
  },
56964
/* cmpx${X} #${Imm-40-QI},${Dsp-16-u24} */
56965
  {
56966
    { 0, 0, 0, 0 },
56967
    { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), 0 } },
56968
    & ifmt_subx32_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_SI, { 0xa6910000 }
56969
  },
56970
/* cmp.w${S} ${Dsp-8-u8}[sb],${Dst32R0HI-S} */
56971
  {
56972
    { 0, 0, 0, 0 },
56973
    { { MNEM, OP (S), ' ', OP (DSP_8_U8), '[', 's', 'b', ']', ',', OP (DST32R0HI_S), 0 } },
56974
    & ifmt_cmp32_w_S_src2_r0_HI_src32_2_S_8_SB_relative_HI, { 0x6100 }
56975
  },
56976
/* cmp.w${S} ${Dsp-8-s8}[fb],${Dst32R0HI-S} */
56977
  {
56978
    { 0, 0, 0, 0 },
56979
    { { MNEM, OP (S), ' ', OP (DSP_8_S8), '[', 'f', 'b', ']', ',', OP (DST32R0HI_S), 0 } },
56980
    & ifmt_cmp32_w_S_src2_r0_HI_src32_2_S_8_FB_relative_HI, { 0x7100 }
56981
  },
56982
/* cmp.w${S} ${Dsp-8-u16},${Dst32R0HI-S} */
56983
  {
56984
    { 0, 0, 0, 0 },
56985
    { { MNEM, OP (S), ' ', OP (DSP_8_U16), ',', OP (DST32R0HI_S), 0 } },
56986
    & ifmt_cmp32_w_S_src2_r0_HI_src32_2_S_16_absolute_HI, { 0x510000 }
56987
  },
56988
/* cmp.b${S} ${Dsp-8-u8}[sb],${Dst32R0QI-S} */
56989
  {
56990
    { 0, 0, 0, 0 },
56991
    { { MNEM, OP (S), ' ', OP (DSP_8_U8), '[', 's', 'b', ']', ',', OP (DST32R0QI_S), 0 } },
56992
    & ifmt_cmp32_b_S_src2_r0_QI_src32_2_S_8_SB_relative_QI, { 0x6000 }
56993
  },
56994
/* cmp.b${S} ${Dsp-8-s8}[fb],${Dst32R0QI-S} */
56995
  {
56996
    { 0, 0, 0, 0 },
56997
    { { MNEM, OP (S), ' ', OP (DSP_8_S8), '[', 'f', 'b', ']', ',', OP (DST32R0QI_S), 0 } },
56998
    & ifmt_cmp32_b_S_src2_r0_QI_src32_2_S_8_FB_relative_QI, { 0x7000 }
56999
  },
57000
/* cmp.b${S} ${Dsp-8-u16},${Dst32R0QI-S} */
57001
  {
57002
    { 0, 0, 0, 0 },
57003
    { { MNEM, OP (S), ' ', OP (DSP_8_U16), ',', OP (DST32R0QI_S), 0 } },
57004
    & ifmt_cmp32_b_S_src2_r0_QI_src32_2_S_16_absolute_QI, { 0x500000 }
57005
  },
57006
/* cmp.w${S} #${Imm-16-HI},${Dsp-8-u8}[sb] */
57007
  {
57008
    { 0, 0, 0, 0 },
57009
    { { MNEM, OP (S), ' ', '#', OP (IMM_16_HI), ',', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } },
57010
    & ifmt_tst32_w_imm_S_2_S_8_dst32_2_S_8_SB_relative_HI, { 0x67000000 }
57011
  },
57012
/* cmp.w${S} #${Imm-16-HI},${Dsp-8-s8}[fb] */
57013
  {
57014
    { 0, 0, 0, 0 },
57015
    { { MNEM, OP (S), ' ', '#', OP (IMM_16_HI), ',', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } },
57016
    & ifmt_tst32_w_imm_S_2_S_8_dst32_2_S_8_FB_relative_HI, { 0x77000000 }
57017
  },
57018
/* cmp.w${S} #${Imm-24-HI},${Dsp-8-u16} */
57019
  {
57020
    { 0, 0, 0, 0 },
57021
    { { MNEM, OP (S), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_8_U16), 0 } },
57022
    & ifmt_tst32_w_imm_S_2_S_16_dst32_2_S_16_absolute_HI, { 0x57000000 }
57023
  },
57024
/* cmp.w${S} #${Imm-8-HI},r0 */
57025
  {
57026
    { 0, 0, 0, 0 },
57027
    { { MNEM, OP (S), ' ', '#', OP (IMM_8_HI), ',', 'r', '0', 0 } },
57028
    & ifmt_tst32_w_imm_S_2_S_basic_dst32_2_S_R0_direct_HI, { 0x470000 }
57029
  },
57030
/* cmp.b${S} #${Imm-16-QI},${Dsp-8-u8}[sb] */
57031
  {
57032
    { 0, 0, 0, 0 },
57033
    { { MNEM, OP (S), ' ', '#', OP (IMM_16_QI), ',', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } },
57034
    & ifmt_tst32_b_imm_S_2_S_8_dst32_2_S_8_SB_relative_QI, { 0x660000 }
57035
  },
57036
/* cmp.b${S} #${Imm-16-QI},${Dsp-8-s8}[fb] */
57037
  {
57038
    { 0, 0, 0, 0 },
57039
    { { MNEM, OP (S), ' ', '#', OP (IMM_16_QI), ',', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } },
57040
    & ifmt_tst32_b_imm_S_2_S_8_dst32_2_S_8_FB_relative_QI, { 0x760000 }
57041
  },
57042
/* cmp.b${S} #${Imm-24-QI},${Dsp-8-u16} */
57043
  {
57044
    { 0, 0, 0, 0 },
57045
    { { MNEM, OP (S), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_8_U16), 0 } },
57046
    & ifmt_tst32_b_imm_S_2_S_16_dst32_2_S_16_absolute_QI, { 0x56000000 }
57047
  },
57048
/* cmp.b${S} #${Imm-8-QI},r0l */
57049
  {
57050
    { 0, 0, 0, 0 },
57051
    { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'l', 0 } },
57052
    & ifmt_tst32_b_imm_S_2_S_basic_dst32_2_S_R0l_direct_QI, { 0x4600 }
57053
  },
57054
/* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
57055
  {
57056
    { 0, 0, 0, 0 },
57057
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
57058
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0x990100 }
57059
  },
57060
/* cmp.l${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedSI */
57061
  {
57062
    { 0, 0, 0, 0 },
57063
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
57064
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0x992100 }
57065
  },
57066
/* cmp.l${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedSI */
57067
  {
57068
    { 0, 0, 0, 0 },
57069
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
57070
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0x993100 }
57071
  },
57072
/* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
57073
  {
57074
    { 0, 0, 0, 0 },
57075
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
57076
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0x918100 }
57077
  },
57078
/* cmp.l${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedSI */
57079
  {
57080
    { 0, 0, 0, 0 },
57081
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
57082
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0x91a100 }
57083
  },
57084
/* cmp.l${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedSI */
57085
  {
57086
    { 0, 0, 0, 0 },
57087
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
57088
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0x91b100 }
57089
  },
57090
/* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
57091
  {
57092
    { 0, 0, 0, 0 },
57093
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57094
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0x910100 }
57095
  },
57096
/* cmp.l${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
57097
  {
57098
    { 0, 0, 0, 0 },
57099
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57100
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0x912100 }
57101
  },
57102
/* cmp.l${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
57103
  {
57104
    { 0, 0, 0, 0 },
57105
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57106
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0x913100 }
57107
  },
57108
/* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
57109
  {
57110
    { 0, 0, 0, 0 },
57111
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57112
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_8_An_relative_Unprefixed_SI, { 0x93010000 }
57113
  },
57114
/* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
57115
  {
57116
    { 0, 0, 0, 0 },
57117
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57118
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_8_An_relative_Unprefixed_SI, { 0x93210000 }
57119
  },
57120
/* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
57121
  {
57122
    { 0, 0, 0, 0 },
57123
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57124
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_8_An_relative_Unprefixed_SI, { 0x93310000 }
57125
  },
57126
/* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
57127
  {
57128
    { 0, 0, 0, 0 },
57129
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57130
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_16_An_relative_Unprefixed_SI, { 0x95010000 }
57131
  },
57132
/* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
57133
  {
57134
    { 0, 0, 0, 0 },
57135
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57136
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_16_An_relative_Unprefixed_SI, { 0x95210000 }
57137
  },
57138
/* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
57139
  {
57140
    { 0, 0, 0, 0 },
57141
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57142
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_16_An_relative_Unprefixed_SI, { 0x95310000 }
57143
  },
57144
/* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
57145
  {
57146
    { 0, 0, 0, 0 },
57147
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57148
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_24_An_relative_Unprefixed_SI, { 0x97010000 }
57149
  },
57150
/* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
57151
  {
57152
    { 0, 0, 0, 0 },
57153
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57154
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_24_An_relative_Unprefixed_SI, { 0x97210000 }
57155
  },
57156
/* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
57157
  {
57158
    { 0, 0, 0, 0 },
57159
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57160
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_24_An_relative_Unprefixed_SI, { 0x97310000 }
57161
  },
57162
/* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
57163
  {
57164
    { 0, 0, 0, 0 },
57165
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
57166
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_8_SB_relative_Unprefixed_SI, { 0x93810000 }
57167
  },
57168
/* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
57169
  {
57170
    { 0, 0, 0, 0 },
57171
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
57172
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_8_SB_relative_Unprefixed_SI, { 0x93a10000 }
57173
  },
57174
/* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
57175
  {
57176
    { 0, 0, 0, 0 },
57177
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
57178
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_8_SB_relative_Unprefixed_SI, { 0x93b10000 }
57179
  },
57180
/* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
57181
  {
57182
    { 0, 0, 0, 0 },
57183
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
57184
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_16_SB_relative_Unprefixed_SI, { 0x95810000 }
57185
  },
57186
/* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
57187
  {
57188
    { 0, 0, 0, 0 },
57189
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
57190
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_16_SB_relative_Unprefixed_SI, { 0x95a10000 }
57191
  },
57192
/* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
57193
  {
57194
    { 0, 0, 0, 0 },
57195
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
57196
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_16_SB_relative_Unprefixed_SI, { 0x95b10000 }
57197
  },
57198
/* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
57199
  {
57200
    { 0, 0, 0, 0 },
57201
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
57202
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_8_FB_relative_Unprefixed_SI, { 0x93c10000 }
57203
  },
57204
/* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
57205
  {
57206
    { 0, 0, 0, 0 },
57207
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
57208
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_8_FB_relative_Unprefixed_SI, { 0x93e10000 }
57209
  },
57210
/* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
57211
  {
57212
    { 0, 0, 0, 0 },
57213
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
57214
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_8_FB_relative_Unprefixed_SI, { 0x93f10000 }
57215
  },
57216
/* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
57217
  {
57218
    { 0, 0, 0, 0 },
57219
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
57220
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_16_FB_relative_Unprefixed_SI, { 0x95c10000 }
57221
  },
57222
/* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
57223
  {
57224
    { 0, 0, 0, 0 },
57225
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
57226
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_16_FB_relative_Unprefixed_SI, { 0x95e10000 }
57227
  },
57228
/* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
57229
  {
57230
    { 0, 0, 0, 0 },
57231
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
57232
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_16_FB_relative_Unprefixed_SI, { 0x95f10000 }
57233
  },
57234
/* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
57235
  {
57236
    { 0, 0, 0, 0 },
57237
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
57238
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_16_absolute_Unprefixed_SI, { 0x97c10000 }
57239
  },
57240
/* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
57241
  {
57242
    { 0, 0, 0, 0 },
57243
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
57244
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_16_absolute_Unprefixed_SI, { 0x97e10000 }
57245
  },
57246
/* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
57247
  {
57248
    { 0, 0, 0, 0 },
57249
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
57250
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_16_absolute_Unprefixed_SI, { 0x97f10000 }
57251
  },
57252
/* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
57253
  {
57254
    { 0, 0, 0, 0 },
57255
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
57256
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_24_absolute_Unprefixed_SI, { 0x97810000 }
57257
  },
57258
/* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
57259
  {
57260
    { 0, 0, 0, 0 },
57261
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } },
57262
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_24_absolute_Unprefixed_SI, { 0x97a10000 }
57263
  },
57264
/* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
57265
  {
57266
    { 0, 0, 0, 0 },
57267
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } },
57268
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_24_absolute_Unprefixed_SI, { 0x97b10000 }
57269
  },
57270
/* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
57271
  {
57272
    { 0, 0, 0, 0 },
57273
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
57274
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xa9010000 }
57275
  },
57276
/* cmp.l${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedSI */
57277
  {
57278
    { 0, 0, 0, 0 },
57279
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
57280
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xa9210000 }
57281
  },
57282
/* cmp.l${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedSI */
57283
  {
57284
    { 0, 0, 0, 0 },
57285
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
57286
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xa9310000 }
57287
  },
57288
/* cmp.l${G} ${Dsp-16-u16},$Dst32RnUnprefixedSI */
57289
  {
57290
    { 0, 0, 0, 0 },
57291
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
57292
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xb9310000 }
57293
  },
57294
/* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
57295
  {
57296
    { 0, 0, 0, 0 },
57297
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
57298
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xa1810000 }
57299
  },
57300
/* cmp.l${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedSI */
57301
  {
57302
    { 0, 0, 0, 0 },
57303
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
57304
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xa1a10000 }
57305
  },
57306
/* cmp.l${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedSI */
57307
  {
57308
    { 0, 0, 0, 0 },
57309
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
57310
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xa1b10000 }
57311
  },
57312
/* cmp.l${G} ${Dsp-16-u16},$Dst32AnUnprefixedSI */
57313
  {
57314
    { 0, 0, 0, 0 },
57315
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
57316
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xb1b10000 }
57317
  },
57318
/* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
57319
  {
57320
    { 0, 0, 0, 0 },
57321
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57322
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xa1010000 }
57323
  },
57324
/* cmp.l${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
57325
  {
57326
    { 0, 0, 0, 0 },
57327
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57328
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xa1210000 }
57329
  },
57330
/* cmp.l${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
57331
  {
57332
    { 0, 0, 0, 0 },
57333
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57334
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xa1310000 }
57335
  },
57336
/* cmp.l${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
57337
  {
57338
    { 0, 0, 0, 0 },
57339
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57340
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xb1310000 }
57341
  },
57342
/* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
57343
  {
57344
    { 0, 0, 0, 0 },
57345
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57346
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_8_An_relative_Unprefixed_SI, { 0xa3010000 }
57347
  },
57348
/* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
57349
  {
57350
    { 0, 0, 0, 0 },
57351
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57352
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_8_An_relative_Unprefixed_SI, { 0xa3210000 }
57353
  },
57354
/* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
57355
  {
57356
    { 0, 0, 0, 0 },
57357
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57358
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_8_An_relative_Unprefixed_SI, { 0xa3310000 }
57359
  },
57360
/* cmp.l${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
57361
  {
57362
    { 0, 0, 0, 0 },
57363
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57364
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_8_An_relative_Unprefixed_SI, { 0xb3310000 }
57365
  },
57366
/* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
57367
  {
57368
    { 0, 0, 0, 0 },
57369
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57370
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_16_An_relative_Unprefixed_SI, { 0xa5010000 }
57371
  },
57372
/* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
57373
  {
57374
    { 0, 0, 0, 0 },
57375
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57376
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_16_An_relative_Unprefixed_SI, { 0xa5210000 }
57377
  },
57378
/* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
57379
  {
57380
    { 0, 0, 0, 0 },
57381
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57382
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_16_An_relative_Unprefixed_SI, { 0xa5310000 }
57383
  },
57384
/* cmp.l${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
57385
  {
57386
    { 0, 0, 0, 0 },
57387
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57388
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_16_An_relative_Unprefixed_SI, { 0xb5310000 }
57389
  },
57390
/* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
57391
  {
57392
    { 0, 0, 0, 0 },
57393
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57394
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_24_An_relative_Unprefixed_SI, { 0xa7010000 }
57395
  },
57396
/* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
57397
  {
57398
    { 0, 0, 0, 0 },
57399
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57400
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_24_An_relative_Unprefixed_SI, { 0xa7210000 }
57401
  },
57402
/* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
57403
  {
57404
    { 0, 0, 0, 0 },
57405
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57406
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_24_An_relative_Unprefixed_SI, { 0xa7310000 }
57407
  },
57408
/* cmp.l${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
57409
  {
57410
    { 0, 0, 0, 0 },
57411
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57412
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_24_An_relative_Unprefixed_SI, { 0xb7310000 }
57413
  },
57414
/* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
57415
  {
57416
    { 0, 0, 0, 0 },
57417
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
57418
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xa3810000 }
57419
  },
57420
/* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
57421
  {
57422
    { 0, 0, 0, 0 },
57423
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
57424
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xa3a10000 }
57425
  },
57426
/* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
57427
  {
57428
    { 0, 0, 0, 0 },
57429
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
57430
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xa3b10000 }
57431
  },
57432
/* cmp.l${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
57433
  {
57434
    { 0, 0, 0, 0 },
57435
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
57436
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xb3b10000 }
57437
  },
57438
/* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
57439
  {
57440
    { 0, 0, 0, 0 },
57441
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
57442
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xa5810000 }
57443
  },
57444
/* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
57445
  {
57446
    { 0, 0, 0, 0 },
57447
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
57448
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xa5a10000 }
57449
  },
57450
/* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
57451
  {
57452
    { 0, 0, 0, 0 },
57453
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
57454
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xa5b10000 }
57455
  },
57456
/* cmp.l${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
57457
  {
57458
    { 0, 0, 0, 0 },
57459
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
57460
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xb5b10000 }
57461
  },
57462
/* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
57463
  {
57464
    { 0, 0, 0, 0 },
57465
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
57466
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xa3c10000 }
57467
  },
57468
/* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
57469
  {
57470
    { 0, 0, 0, 0 },
57471
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
57472
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xa3e10000 }
57473
  },
57474
/* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
57475
  {
57476
    { 0, 0, 0, 0 },
57477
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
57478
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xa3f10000 }
57479
  },
57480
/* cmp.l${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
57481
  {
57482
    { 0, 0, 0, 0 },
57483
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
57484
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xb3f10000 }
57485
  },
57486
/* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
57487
  {
57488
    { 0, 0, 0, 0 },
57489
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
57490
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xa5c10000 }
57491
  },
57492
/* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
57493
  {
57494
    { 0, 0, 0, 0 },
57495
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
57496
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xa5e10000 }
57497
  },
57498
/* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
57499
  {
57500
    { 0, 0, 0, 0 },
57501
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
57502
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xa5f10000 }
57503
  },
57504
/* cmp.l${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
57505
  {
57506
    { 0, 0, 0, 0 },
57507
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
57508
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xb5f10000 }
57509
  },
57510
/* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
57511
  {
57512
    { 0, 0, 0, 0 },
57513
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
57514
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_16_absolute_Unprefixed_SI, { 0xa7c10000 }
57515
  },
57516
/* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
57517
  {
57518
    { 0, 0, 0, 0 },
57519
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
57520
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_16_absolute_Unprefixed_SI, { 0xa7e10000 }
57521
  },
57522
/* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
57523
  {
57524
    { 0, 0, 0, 0 },
57525
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
57526
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_16_absolute_Unprefixed_SI, { 0xa7f10000 }
57527
  },
57528
/* cmp.l${G} ${Dsp-16-u16},${Dsp-32-u16} */
57529
  {
57530
    { 0, 0, 0, 0 },
57531
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
57532
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_16_absolute_Unprefixed_SI, { 0xb7f10000 }
57533
  },
57534
/* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
57535
  {
57536
    { 0, 0, 0, 0 },
57537
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
57538
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_24_absolute_Unprefixed_SI, { 0xa7810000 }
57539
  },
57540
/* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
57541
  {
57542
    { 0, 0, 0, 0 },
57543
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
57544
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_24_absolute_Unprefixed_SI, { 0xa7a10000 }
57545
  },
57546
/* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
57547
  {
57548
    { 0, 0, 0, 0 },
57549
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
57550
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_24_absolute_Unprefixed_SI, { 0xa7b10000 }
57551
  },
57552
/* cmp.l${G} ${Dsp-16-u16},${Dsp-32-u24} */
57553
  {
57554
    { 0, 0, 0, 0 },
57555
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } },
57556
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_24_absolute_Unprefixed_SI, { 0xb7b10000 }
57557
  },
57558
/* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
57559
  {
57560
    { 0, 0, 0, 0 },
57561
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
57562
    & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xb9010000 }
57563
  },
57564
/* cmp.l${G} ${Dsp-16-u24},$Dst32RnUnprefixedSI */
57565
  {
57566
    { 0, 0, 0, 0 },
57567
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
57568
    & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xb9210000 }
57569
  },
57570
/* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
57571
  {
57572
    { 0, 0, 0, 0 },
57573
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
57574
    & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xb1810000 }
57575
  },
57576
/* cmp.l${G} ${Dsp-16-u24},$Dst32AnUnprefixedSI */
57577
  {
57578
    { 0, 0, 0, 0 },
57579
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
57580
    & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xb1a10000 }
57581
  },
57582
/* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
57583
  {
57584
    { 0, 0, 0, 0 },
57585
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57586
    & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xb1010000 }
57587
  },
57588
/* cmp.l${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
57589
  {
57590
    { 0, 0, 0, 0 },
57591
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57592
    & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xb1210000 }
57593
  },
57594
/* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
57595
  {
57596
    { 0, 0, 0, 0 },
57597
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57598
    & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_8_An_relative_Unprefixed_SI, { 0xb3010000 }
57599
  },
57600
/* cmp.l${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
57601
  {
57602
    { 0, 0, 0, 0 },
57603
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57604
    & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_8_An_relative_Unprefixed_SI, { 0xb3210000 }
57605
  },
57606
/* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
57607
  {
57608
    { 0, 0, 0, 0 },
57609
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57610
    & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_16_An_relative_Unprefixed_SI, { 0xb5010000 }
57611
  },
57612
/* cmp.l${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
57613
  {
57614
    { 0, 0, 0, 0 },
57615
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57616
    & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_16_An_relative_Unprefixed_SI, { 0xb5210000 }
57617
  },
57618
/* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
57619
  {
57620
    { 0, 0, 0, 0 },
57621
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57622
    & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_24_An_relative_Unprefixed_SI, { 0xb7010000 }
57623
  },
57624
/* cmp.l${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
57625
  {
57626
    { 0, 0, 0, 0 },
57627
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57628
    & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_24_An_relative_Unprefixed_SI, { 0xb7210000 }
57629
  },
57630
/* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
57631
  {
57632
    { 0, 0, 0, 0 },
57633
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
57634
    & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_8_SB_relative_Unprefixed_SI, { 0xb3810000 }
57635
  },
57636
/* cmp.l${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
57637
  {
57638
    { 0, 0, 0, 0 },
57639
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
57640
    & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_8_SB_relative_Unprefixed_SI, { 0xb3a10000 }
57641
  },
57642
/* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
57643
  {
57644
    { 0, 0, 0, 0 },
57645
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
57646
    & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_16_SB_relative_Unprefixed_SI, { 0xb5810000 }
57647
  },
57648
/* cmp.l${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
57649
  {
57650
    { 0, 0, 0, 0 },
57651
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
57652
    & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_16_SB_relative_Unprefixed_SI, { 0xb5a10000 }
57653
  },
57654
/* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
57655
  {
57656
    { 0, 0, 0, 0 },
57657
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
57658
    & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_8_FB_relative_Unprefixed_SI, { 0xb3c10000 }
57659
  },
57660
/* cmp.l${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
57661
  {
57662
    { 0, 0, 0, 0 },
57663
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
57664
    & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_8_FB_relative_Unprefixed_SI, { 0xb3e10000 }
57665
  },
57666
/* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
57667
  {
57668
    { 0, 0, 0, 0 },
57669
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
57670
    & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_16_FB_relative_Unprefixed_SI, { 0xb5c10000 }
57671
  },
57672
/* cmp.l${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
57673
  {
57674
    { 0, 0, 0, 0 },
57675
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
57676
    & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_16_FB_relative_Unprefixed_SI, { 0xb5e10000 }
57677
  },
57678
/* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
57679
  {
57680
    { 0, 0, 0, 0 },
57681
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
57682
    & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_16_absolute_Unprefixed_SI, { 0xb7c10000 }
57683
  },
57684
/* cmp.l${G} ${Dsp-16-u24},${Dsp-40-u16} */
57685
  {
57686
    { 0, 0, 0, 0 },
57687
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } },
57688
    & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_16_absolute_Unprefixed_SI, { 0xb7e10000 }
57689
  },
57690
/* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
57691
  {
57692
    { 0, 0, 0, 0 },
57693
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
57694
    & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_24_absolute_Unprefixed_SI, { 0xb7810000 }
57695
  },
57696
/* cmp.l${G} ${Dsp-16-u24},${Dsp-40-u24} */
57697
  {
57698
    { 0, 0, 0, 0 },
57699
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } },
57700
    & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_24_absolute_Unprefixed_SI, { 0xb7a10000 }
57701
  },
57702
/* cmp.l${G} $Src32RnUnprefixedSI,$Dst32RnUnprefixedSI */
57703
  {
57704
    { 0, 0, 0, 0 },
57705
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
57706
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xc901 }
57707
  },
57708
/* cmp.l${G} $Src32AnUnprefixedSI,$Dst32RnUnprefixedSI */
57709
  {
57710
    { 0, 0, 0, 0 },
57711
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
57712
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0x8921 }
57713
  },
57714
/* cmp.l${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
57715
  {
57716
    { 0, 0, 0, 0 },
57717
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
57718
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0x8901 }
57719
  },
57720
/* cmp.l${G} $Src32RnUnprefixedSI,$Dst32AnUnprefixedSI */
57721
  {
57722
    { 0, 0, 0, 0 },
57723
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
57724
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xc181 }
57725
  },
57726
/* cmp.l${G} $Src32AnUnprefixedSI,$Dst32AnUnprefixedSI */
57727
  {
57728
    { 0, 0, 0, 0 },
57729
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
57730
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0x81a1 }
57731
  },
57732
/* cmp.l${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
57733
  {
57734
    { 0, 0, 0, 0 },
57735
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
57736
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0x8181 }
57737
  },
57738
/* cmp.l${G} $Src32RnUnprefixedSI,[$Dst32AnUnprefixed] */
57739
  {
57740
    { 0, 0, 0, 0 },
57741
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57742
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xc101 }
57743
  },
57744
/* cmp.l${G} $Src32AnUnprefixedSI,[$Dst32AnUnprefixed] */
57745
  {
57746
    { 0, 0, 0, 0 },
57747
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57748
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0x8121 }
57749
  },
57750
/* cmp.l${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
57751
  {
57752
    { 0, 0, 0, 0 },
57753
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57754
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0x8101 }
57755
  },
57756
/* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
57757
  {
57758
    { 0, 0, 0, 0 },
57759
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57760
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_8_An_relative_Unprefixed_SI, { 0xc30100 }
57761
  },
57762
/* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
57763
  {
57764
    { 0, 0, 0, 0 },
57765
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57766
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_8_An_relative_Unprefixed_SI, { 0x832100 }
57767
  },
57768
/* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
57769
  {
57770
    { 0, 0, 0, 0 },
57771
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57772
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_8_An_relative_Unprefixed_SI, { 0x830100 }
57773
  },
57774
/* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
57775
  {
57776
    { 0, 0, 0, 0 },
57777
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57778
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_16_An_relative_Unprefixed_SI, { 0xc5010000 }
57779
  },
57780
/* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
57781
  {
57782
    { 0, 0, 0, 0 },
57783
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57784
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_16_An_relative_Unprefixed_SI, { 0x85210000 }
57785
  },
57786
/* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
57787
  {
57788
    { 0, 0, 0, 0 },
57789
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57790
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_16_An_relative_Unprefixed_SI, { 0x85010000 }
57791
  },
57792
/* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
57793
  {
57794
    { 0, 0, 0, 0 },
57795
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57796
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_24_An_relative_Unprefixed_SI, { 0xc7010000 }
57797
  },
57798
/* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
57799
  {
57800
    { 0, 0, 0, 0 },
57801
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57802
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_24_An_relative_Unprefixed_SI, { 0x87210000 }
57803
  },
57804
/* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
57805
  {
57806
    { 0, 0, 0, 0 },
57807
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57808
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_24_An_relative_Unprefixed_SI, { 0x87010000 }
57809
  },
57810
/* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-u8}[sb] */
57811
  {
57812
    { 0, 0, 0, 0 },
57813
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
57814
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_8_SB_relative_Unprefixed_SI, { 0xc38100 }
57815
  },
57816
/* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-u8}[sb] */
57817
  {
57818
    { 0, 0, 0, 0 },
57819
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
57820
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_8_SB_relative_Unprefixed_SI, { 0x83a100 }
57821
  },
57822
/* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
57823
  {
57824
    { 0, 0, 0, 0 },
57825
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
57826
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_8_SB_relative_Unprefixed_SI, { 0x838100 }
57827
  },
57828
/* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16}[sb] */
57829
  {
57830
    { 0, 0, 0, 0 },
57831
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
57832
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_16_SB_relative_Unprefixed_SI, { 0xc5810000 }
57833
  },
57834
/* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16}[sb] */
57835
  {
57836
    { 0, 0, 0, 0 },
57837
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
57838
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_16_SB_relative_Unprefixed_SI, { 0x85a10000 }
57839
  },
57840
/* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
57841
  {
57842
    { 0, 0, 0, 0 },
57843
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
57844
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_16_SB_relative_Unprefixed_SI, { 0x85810000 }
57845
  },
57846
/* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-s8}[fb] */
57847
  {
57848
    { 0, 0, 0, 0 },
57849
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
57850
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_8_FB_relative_Unprefixed_SI, { 0xc3c100 }
57851
  },
57852
/* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-s8}[fb] */
57853
  {
57854
    { 0, 0, 0, 0 },
57855
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
57856
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_8_FB_relative_Unprefixed_SI, { 0x83e100 }
57857
  },
57858
/* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
57859
  {
57860
    { 0, 0, 0, 0 },
57861
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
57862
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_8_FB_relative_Unprefixed_SI, { 0x83c100 }
57863
  },
57864
/* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-s16}[fb] */
57865
  {
57866
    { 0, 0, 0, 0 },
57867
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
57868
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_16_FB_relative_Unprefixed_SI, { 0xc5c10000 }
57869
  },
57870
/* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-s16}[fb] */
57871
  {
57872
    { 0, 0, 0, 0 },
57873
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
57874
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_16_FB_relative_Unprefixed_SI, { 0x85e10000 }
57875
  },
57876
/* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
57877
  {
57878
    { 0, 0, 0, 0 },
57879
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
57880
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_16_FB_relative_Unprefixed_SI, { 0x85c10000 }
57881
  },
57882
/* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16} */
57883
  {
57884
    { 0, 0, 0, 0 },
57885
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U16), 0 } },
57886
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_16_absolute_Unprefixed_SI, { 0xc7c10000 }
57887
  },
57888
/* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16} */
57889
  {
57890
    { 0, 0, 0, 0 },
57891
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U16), 0 } },
57892
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_16_absolute_Unprefixed_SI, { 0x87e10000 }
57893
  },
57894
/* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
57895
  {
57896
    { 0, 0, 0, 0 },
57897
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } },
57898
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_16_absolute_Unprefixed_SI, { 0x87c10000 }
57899
  },
57900
/* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-u24} */
57901
  {
57902
    { 0, 0, 0, 0 },
57903
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U24), 0 } },
57904
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_24_absolute_Unprefixed_SI, { 0xc7810000 }
57905
  },
57906
/* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-u24} */
57907
  {
57908
    { 0, 0, 0, 0 },
57909
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U24), 0 } },
57910
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_24_absolute_Unprefixed_SI, { 0x87a10000 }
57911
  },
57912
/* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
57913
  {
57914
    { 0, 0, 0, 0 },
57915
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } },
57916
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_24_absolute_Unprefixed_SI, { 0x87810000 }
57917
  },
57918
/* cmp.b${S} ${SrcDst16-r0l-r0h-S-normal} */
57919
  {
57920
    { 0, 0, 0, 0 },
57921
    { { MNEM, OP (S), ' ', OP (SRCDST16_R0L_R0H_S_NORMAL), 0 } },
57922
    & ifmt_or16_b_S_r0l_r0h_srcdst16_r0l_r0h_S_derived, { 0x38 }
57923
  },
57924
/* cmp.b${S} ${Dsp-8-u8}[sb],${Dst16RnQI-S} */
57925
  {
57926
    { 0, 0, 0, 0 },
57927
    { { MNEM, OP (S), ' ', OP (DSP_8_U8), '[', 's', 'b', ']', ',', OP (DST16RNQI_S), 0 } },
57928
    & ifmt_or16_b_S_src2_src16_2_S_8_SB_relative_QI, { 0x3900 }
57929
  },
57930
/* cmp.b${S} ${Dsp-8-s8}[fb],${Dst16RnQI-S} */
57931
  {
57932
    { 0, 0, 0, 0 },
57933
    { { MNEM, OP (S), ' ', OP (DSP_8_S8), '[', 'f', 'b', ']', ',', OP (DST16RNQI_S), 0 } },
57934
    & ifmt_or16_b_S_src2_src16_2_S_8_FB_relative_QI, { 0x3a00 }
57935
  },
57936
/* cmp.b${S} ${Dsp-8-u16},${Dst16RnQI-S} */
57937
  {
57938
    { 0, 0, 0, 0 },
57939
    { { MNEM, OP (S), ' ', OP (DSP_8_U16), ',', OP (DST16RNQI_S), 0 } },
57940
    & ifmt_or16_b_S_src2_src16_2_S_16_absolute_QI, { 0x3b0000 }
57941
  },
57942
/* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
57943
  {
57944
    { 0, 0, 0, 0 },
57945
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
57946
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x990600 }
57947
  },
57948
/* cmp.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */
57949
  {
57950
    { 0, 0, 0, 0 },
57951
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
57952
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x992600 }
57953
  },
57954
/* cmp.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */
57955
  {
57956
    { 0, 0, 0, 0 },
57957
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
57958
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x993600 }
57959
  },
57960
/* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
57961
  {
57962
    { 0, 0, 0, 0 },
57963
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
57964
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x918600 }
57965
  },
57966
/* cmp.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */
57967
  {
57968
    { 0, 0, 0, 0 },
57969
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
57970
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x91a600 }
57971
  },
57972
/* cmp.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */
57973
  {
57974
    { 0, 0, 0, 0 },
57975
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
57976
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x91b600 }
57977
  },
57978
/* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
57979
  {
57980
    { 0, 0, 0, 0 },
57981
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57982
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x910600 }
57983
  },
57984
/* cmp.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
57985
  {
57986
    { 0, 0, 0, 0 },
57987
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57988
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x912600 }
57989
  },
57990
/* cmp.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
57991
  {
57992
    { 0, 0, 0, 0 },
57993
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
57994
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x913600 }
57995
  },
57996
/* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
57997
  {
57998
    { 0, 0, 0, 0 },
57999
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58000
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x93060000 }
58001
  },
58002
/* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
58003
  {
58004
    { 0, 0, 0, 0 },
58005
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58006
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x93260000 }
58007
  },
58008
/* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
58009
  {
58010
    { 0, 0, 0, 0 },
58011
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58012
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x93360000 }
58013
  },
58014
/* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
58015
  {
58016
    { 0, 0, 0, 0 },
58017
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58018
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x95060000 }
58019
  },
58020
/* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
58021
  {
58022
    { 0, 0, 0, 0 },
58023
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58024
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x95260000 }
58025
  },
58026
/* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
58027
  {
58028
    { 0, 0, 0, 0 },
58029
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58030
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x95360000 }
58031
  },
58032
/* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
58033
  {
58034
    { 0, 0, 0, 0 },
58035
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58036
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x97060000 }
58037
  },
58038
/* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
58039
  {
58040
    { 0, 0, 0, 0 },
58041
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58042
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x97260000 }
58043
  },
58044
/* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
58045
  {
58046
    { 0, 0, 0, 0 },
58047
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58048
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x97360000 }
58049
  },
58050
/* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
58051
  {
58052
    { 0, 0, 0, 0 },
58053
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
58054
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93860000 }
58055
  },
58056
/* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
58057
  {
58058
    { 0, 0, 0, 0 },
58059
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
58060
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93a60000 }
58061
  },
58062
/* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
58063
  {
58064
    { 0, 0, 0, 0 },
58065
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
58066
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93b60000 }
58067
  },
58068
/* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
58069
  {
58070
    { 0, 0, 0, 0 },
58071
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
58072
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95860000 }
58073
  },
58074
/* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
58075
  {
58076
    { 0, 0, 0, 0 },
58077
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
58078
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95a60000 }
58079
  },
58080
/* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
58081
  {
58082
    { 0, 0, 0, 0 },
58083
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
58084
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95b60000 }
58085
  },
58086
/* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
58087
  {
58088
    { 0, 0, 0, 0 },
58089
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
58090
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93c60000 }
58091
  },
58092
/* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
58093
  {
58094
    { 0, 0, 0, 0 },
58095
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
58096
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93e60000 }
58097
  },
58098
/* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
58099
  {
58100
    { 0, 0, 0, 0 },
58101
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
58102
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93f60000 }
58103
  },
58104
/* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
58105
  {
58106
    { 0, 0, 0, 0 },
58107
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
58108
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95c60000 }
58109
  },
58110
/* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
58111
  {
58112
    { 0, 0, 0, 0 },
58113
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
58114
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95e60000 }
58115
  },
58116
/* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
58117
  {
58118
    { 0, 0, 0, 0 },
58119
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
58120
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95f60000 }
58121
  },
58122
/* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
58123
  {
58124
    { 0, 0, 0, 0 },
58125
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
58126
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97c60000 }
58127
  },
58128
/* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
58129
  {
58130
    { 0, 0, 0, 0 },
58131
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
58132
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97e60000 }
58133
  },
58134
/* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
58135
  {
58136
    { 0, 0, 0, 0 },
58137
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
58138
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97f60000 }
58139
  },
58140
/* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
58141
  {
58142
    { 0, 0, 0, 0 },
58143
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
58144
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97860000 }
58145
  },
58146
/* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
58147
  {
58148
    { 0, 0, 0, 0 },
58149
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } },
58150
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97a60000 }
58151
  },
58152
/* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
58153
  {
58154
    { 0, 0, 0, 0 },
58155
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } },
58156
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97b60000 }
58157
  },
58158
/* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
58159
  {
58160
    { 0, 0, 0, 0 },
58161
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
58162
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa9060000 }
58163
  },
58164
/* cmp.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */
58165
  {
58166
    { 0, 0, 0, 0 },
58167
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
58168
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa9260000 }
58169
  },
58170
/* cmp.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */
58171
  {
58172
    { 0, 0, 0, 0 },
58173
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
58174
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa9360000 }
58175
  },
58176
/* cmp.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */
58177
  {
58178
    { 0, 0, 0, 0 },
58179
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
58180
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb9360000 }
58181
  },
58182
/* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
58183
  {
58184
    { 0, 0, 0, 0 },
58185
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
58186
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1860000 }
58187
  },
58188
/* cmp.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */
58189
  {
58190
    { 0, 0, 0, 0 },
58191
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
58192
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1a60000 }
58193
  },
58194
/* cmp.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */
58195
  {
58196
    { 0, 0, 0, 0 },
58197
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
58198
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1b60000 }
58199
  },
58200
/* cmp.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */
58201
  {
58202
    { 0, 0, 0, 0 },
58203
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
58204
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1b60000 }
58205
  },
58206
/* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
58207
  {
58208
    { 0, 0, 0, 0 },
58209
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58210
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa1060000 }
58211
  },
58212
/* cmp.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
58213
  {
58214
    { 0, 0, 0, 0 },
58215
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58216
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa1260000 }
58217
  },
58218
/* cmp.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
58219
  {
58220
    { 0, 0, 0, 0 },
58221
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58222
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa1360000 }
58223
  },
58224
/* cmp.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
58225
  {
58226
    { 0, 0, 0, 0 },
58227
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58228
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb1360000 }
58229
  },
58230
/* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
58231
  {
58232
    { 0, 0, 0, 0 },
58233
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58234
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa3060000 }
58235
  },
58236
/* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
58237
  {
58238
    { 0, 0, 0, 0 },
58239
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58240
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa3260000 }
58241
  },
58242
/* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
58243
  {
58244
    { 0, 0, 0, 0 },
58245
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58246
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa3360000 }
58247
  },
58248
/* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
58249
  {
58250
    { 0, 0, 0, 0 },
58251
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58252
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xb3360000 }
58253
  },
58254
/* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
58255
  {
58256
    { 0, 0, 0, 0 },
58257
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58258
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa5060000 }
58259
  },
58260
/* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
58261
  {
58262
    { 0, 0, 0, 0 },
58263
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58264
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa5260000 }
58265
  },
58266
/* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
58267
  {
58268
    { 0, 0, 0, 0 },
58269
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58270
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa5360000 }
58271
  },
58272
/* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
58273
  {
58274
    { 0, 0, 0, 0 },
58275
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58276
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xb5360000 }
58277
  },
58278
/* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
58279
  {
58280
    { 0, 0, 0, 0 },
58281
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58282
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa7060000 }
58283
  },
58284
/* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
58285
  {
58286
    { 0, 0, 0, 0 },
58287
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58288
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa7260000 }
58289
  },
58290
/* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
58291
  {
58292
    { 0, 0, 0, 0 },
58293
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58294
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa7360000 }
58295
  },
58296
/* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
58297
  {
58298
    { 0, 0, 0, 0 },
58299
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58300
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xb7360000 }
58301
  },
58302
/* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
58303
  {
58304
    { 0, 0, 0, 0 },
58305
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
58306
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3860000 }
58307
  },
58308
/* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
58309
  {
58310
    { 0, 0, 0, 0 },
58311
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
58312
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3a60000 }
58313
  },
58314
/* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
58315
  {
58316
    { 0, 0, 0, 0 },
58317
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
58318
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3b60000 }
58319
  },
58320
/* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
58321
  {
58322
    { 0, 0, 0, 0 },
58323
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
58324
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xb3b60000 }
58325
  },
58326
/* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
58327
  {
58328
    { 0, 0, 0, 0 },
58329
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
58330
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5860000 }
58331
  },
58332
/* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
58333
  {
58334
    { 0, 0, 0, 0 },
58335
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
58336
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5a60000 }
58337
  },
58338
/* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
58339
  {
58340
    { 0, 0, 0, 0 },
58341
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
58342
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5b60000 }
58343
  },
58344
/* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
58345
  {
58346
    { 0, 0, 0, 0 },
58347
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
58348
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xb5b60000 }
58349
  },
58350
/* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
58351
  {
58352
    { 0, 0, 0, 0 },
58353
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
58354
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3c60000 }
58355
  },
58356
/* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
58357
  {
58358
    { 0, 0, 0, 0 },
58359
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
58360
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3e60000 }
58361
  },
58362
/* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
58363
  {
58364
    { 0, 0, 0, 0 },
58365
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
58366
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3f60000 }
58367
  },
58368
/* cmp.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
58369
  {
58370
    { 0, 0, 0, 0 },
58371
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
58372
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xb3f60000 }
58373
  },
58374
/* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
58375
  {
58376
    { 0, 0, 0, 0 },
58377
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
58378
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5c60000 }
58379
  },
58380
/* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
58381
  {
58382
    { 0, 0, 0, 0 },
58383
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
58384
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5e60000 }
58385
  },
58386
/* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
58387
  {
58388
    { 0, 0, 0, 0 },
58389
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
58390
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5f60000 }
58391
  },
58392
/* cmp.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
58393
  {
58394
    { 0, 0, 0, 0 },
58395
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
58396
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xb5f60000 }
58397
  },
58398
/* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
58399
  {
58400
    { 0, 0, 0, 0 },
58401
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
58402
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7c60000 }
58403
  },
58404
/* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
58405
  {
58406
    { 0, 0, 0, 0 },
58407
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
58408
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7e60000 }
58409
  },
58410
/* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
58411
  {
58412
    { 0, 0, 0, 0 },
58413
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
58414
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7f60000 }
58415
  },
58416
/* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
58417
  {
58418
    { 0, 0, 0, 0 },
58419
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
58420
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xb7f60000 }
58421
  },
58422
/* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
58423
  {
58424
    { 0, 0, 0, 0 },
58425
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
58426
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7860000 }
58427
  },
58428
/* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
58429
  {
58430
    { 0, 0, 0, 0 },
58431
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
58432
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7a60000 }
58433
  },
58434
/* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
58435
  {
58436
    { 0, 0, 0, 0 },
58437
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
58438
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7b60000 }
58439
  },
58440
/* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u24} */
58441
  {
58442
    { 0, 0, 0, 0 },
58443
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } },
58444
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xb7b60000 }
58445
  },
58446
/* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
58447
  {
58448
    { 0, 0, 0, 0 },
58449
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
58450
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb9060000 }
58451
  },
58452
/* cmp.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */
58453
  {
58454
    { 0, 0, 0, 0 },
58455
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
58456
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb9260000 }
58457
  },
58458
/* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
58459
  {
58460
    { 0, 0, 0, 0 },
58461
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
58462
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1860000 }
58463
  },
58464
/* cmp.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */
58465
  {
58466
    { 0, 0, 0, 0 },
58467
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
58468
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1a60000 }
58469
  },
58470
/* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
58471
  {
58472
    { 0, 0, 0, 0 },
58473
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58474
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb1060000 }
58475
  },
58476
/* cmp.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
58477
  {
58478
    { 0, 0, 0, 0 },
58479
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58480
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb1260000 }
58481
  },
58482
/* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
58483
  {
58484
    { 0, 0, 0, 0 },
58485
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58486
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_An_relative_Unprefixed_HI, { 0xb3060000 }
58487
  },
58488
/* cmp.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
58489
  {
58490
    { 0, 0, 0, 0 },
58491
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58492
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_An_relative_Unprefixed_HI, { 0xb3260000 }
58493
  },
58494
/* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
58495
  {
58496
    { 0, 0, 0, 0 },
58497
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58498
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_An_relative_Unprefixed_HI, { 0xb5060000 }
58499
  },
58500
/* cmp.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
58501
  {
58502
    { 0, 0, 0, 0 },
58503
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58504
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_An_relative_Unprefixed_HI, { 0xb5260000 }
58505
  },
58506
/* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
58507
  {
58508
    { 0, 0, 0, 0 },
58509
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58510
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_24_An_relative_Unprefixed_HI, { 0xb7060000 }
58511
  },
58512
/* cmp.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
58513
  {
58514
    { 0, 0, 0, 0 },
58515
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58516
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_24_An_relative_Unprefixed_HI, { 0xb7260000 }
58517
  },
58518
/* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
58519
  {
58520
    { 0, 0, 0, 0 },
58521
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
58522
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_SB_relative_Unprefixed_HI, { 0xb3860000 }
58523
  },
58524
/* cmp.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
58525
  {
58526
    { 0, 0, 0, 0 },
58527
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
58528
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_SB_relative_Unprefixed_HI, { 0xb3a60000 }
58529
  },
58530
/* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
58531
  {
58532
    { 0, 0, 0, 0 },
58533
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
58534
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_SB_relative_Unprefixed_HI, { 0xb5860000 }
58535
  },
58536
/* cmp.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
58537
  {
58538
    { 0, 0, 0, 0 },
58539
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
58540
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_SB_relative_Unprefixed_HI, { 0xb5a60000 }
58541
  },
58542
/* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
58543
  {
58544
    { 0, 0, 0, 0 },
58545
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
58546
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_FB_relative_Unprefixed_HI, { 0xb3c60000 }
58547
  },
58548
/* cmp.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
58549
  {
58550
    { 0, 0, 0, 0 },
58551
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
58552
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_FB_relative_Unprefixed_HI, { 0xb3e60000 }
58553
  },
58554
/* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
58555
  {
58556
    { 0, 0, 0, 0 },
58557
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
58558
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_FB_relative_Unprefixed_HI, { 0xb5c60000 }
58559
  },
58560
/* cmp.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
58561
  {
58562
    { 0, 0, 0, 0 },
58563
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
58564
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_FB_relative_Unprefixed_HI, { 0xb5e60000 }
58565
  },
58566
/* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
58567
  {
58568
    { 0, 0, 0, 0 },
58569
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
58570
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_absolute_Unprefixed_HI, { 0xb7c60000 }
58571
  },
58572
/* cmp.w${G} ${Dsp-16-u24},${Dsp-40-u16} */
58573
  {
58574
    { 0, 0, 0, 0 },
58575
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } },
58576
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_absolute_Unprefixed_HI, { 0xb7e60000 }
58577
  },
58578
/* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
58579
  {
58580
    { 0, 0, 0, 0 },
58581
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
58582
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_24_absolute_Unprefixed_HI, { 0xb7860000 }
58583
  },
58584
/* cmp.w${G} ${Dsp-16-u24},${Dsp-40-u24} */
58585
  {
58586
    { 0, 0, 0, 0 },
58587
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } },
58588
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_24_absolute_Unprefixed_HI, { 0xb7a60000 }
58589
  },
58590
/* cmp.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */
58591
  {
58592
    { 0, 0, 0, 0 },
58593
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
58594
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xc906 }
58595
  },
58596
/* cmp.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */
58597
  {
58598
    { 0, 0, 0, 0 },
58599
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
58600
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x8926 }
58601
  },
58602
/* cmp.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
58603
  {
58604
    { 0, 0, 0, 0 },
58605
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
58606
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x8906 }
58607
  },
58608
/* cmp.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */
58609
  {
58610
    { 0, 0, 0, 0 },
58611
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
58612
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xc186 }
58613
  },
58614
/* cmp.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */
58615
  {
58616
    { 0, 0, 0, 0 },
58617
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
58618
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x81a6 }
58619
  },
58620
/* cmp.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
58621
  {
58622
    { 0, 0, 0, 0 },
58623
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
58624
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x8186 }
58625
  },
58626
/* cmp.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */
58627
  {
58628
    { 0, 0, 0, 0 },
58629
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58630
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xc106 }
58631
  },
58632
/* cmp.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */
58633
  {
58634
    { 0, 0, 0, 0 },
58635
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58636
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x8126 }
58637
  },
58638
/* cmp.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
58639
  {
58640
    { 0, 0, 0, 0 },
58641
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58642
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x8106 }
58643
  },
58644
/* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
58645
  {
58646
    { 0, 0, 0, 0 },
58647
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58648
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0xc30600 }
58649
  },
58650
/* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
58651
  {
58652
    { 0, 0, 0, 0 },
58653
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58654
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0x832600 }
58655
  },
58656
/* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
58657
  {
58658
    { 0, 0, 0, 0 },
58659
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58660
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0x830600 }
58661
  },
58662
/* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
58663
  {
58664
    { 0, 0, 0, 0 },
58665
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58666
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0xc5060000 }
58667
  },
58668
/* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
58669
  {
58670
    { 0, 0, 0, 0 },
58671
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58672
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0x85260000 }
58673
  },
58674
/* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
58675
  {
58676
    { 0, 0, 0, 0 },
58677
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58678
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0x85060000 }
58679
  },
58680
/* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
58681
  {
58682
    { 0, 0, 0, 0 },
58683
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58684
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0xc7060000 }
58685
  },
58686
/* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
58687
  {
58688
    { 0, 0, 0, 0 },
58689
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58690
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0x87260000 }
58691
  },
58692
/* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
58693
  {
58694
    { 0, 0, 0, 0 },
58695
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58696
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0x87060000 }
58697
  },
58698
/* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */
58699
  {
58700
    { 0, 0, 0, 0 },
58701
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
58702
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0xc38600 }
58703
  },
58704
/* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */
58705
  {
58706
    { 0, 0, 0, 0 },
58707
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
58708
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0x83a600 }
58709
  },
58710
/* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
58711
  {
58712
    { 0, 0, 0, 0 },
58713
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
58714
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0x838600 }
58715
  },
58716
/* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */
58717
  {
58718
    { 0, 0, 0, 0 },
58719
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
58720
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0xc5860000 }
58721
  },
58722
/* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */
58723
  {
58724
    { 0, 0, 0, 0 },
58725
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
58726
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0x85a60000 }
58727
  },
58728
/* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
58729
  {
58730
    { 0, 0, 0, 0 },
58731
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
58732
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0x85860000 }
58733
  },
58734
/* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */
58735
  {
58736
    { 0, 0, 0, 0 },
58737
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
58738
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0xc3c600 }
58739
  },
58740
/* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */
58741
  {
58742
    { 0, 0, 0, 0 },
58743
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
58744
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83e600 }
58745
  },
58746
/* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
58747
  {
58748
    { 0, 0, 0, 0 },
58749
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
58750
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83c600 }
58751
  },
58752
/* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */
58753
  {
58754
    { 0, 0, 0, 0 },
58755
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
58756
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0xc5c60000 }
58757
  },
58758
/* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */
58759
  {
58760
    { 0, 0, 0, 0 },
58761
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
58762
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85e60000 }
58763
  },
58764
/* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
58765
  {
58766
    { 0, 0, 0, 0 },
58767
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
58768
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85c60000 }
58769
  },
58770
/* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */
58771
  {
58772
    { 0, 0, 0, 0 },
58773
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), 0 } },
58774
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0xc7c60000 }
58775
  },
58776
/* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */
58777
  {
58778
    { 0, 0, 0, 0 },
58779
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), 0 } },
58780
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0x87e60000 }
58781
  },
58782
/* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
58783
  {
58784
    { 0, 0, 0, 0 },
58785
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } },
58786
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0x87c60000 }
58787
  },
58788
/* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */
58789
  {
58790
    { 0, 0, 0, 0 },
58791
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U24), 0 } },
58792
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0xc7860000 }
58793
  },
58794
/* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */
58795
  {
58796
    { 0, 0, 0, 0 },
58797
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U24), 0 } },
58798
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0x87a60000 }
58799
  },
58800
/* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
58801
  {
58802
    { 0, 0, 0, 0 },
58803
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } },
58804
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0x87860000 }
58805
  },
58806
/* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
58807
  {
58808
    { 0, 0, 0, 0 },
58809
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
58810
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x980600 }
58811
  },
58812
/* cmp.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */
58813
  {
58814
    { 0, 0, 0, 0 },
58815
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
58816
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x982600 }
58817
  },
58818
/* cmp.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */
58819
  {
58820
    { 0, 0, 0, 0 },
58821
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
58822
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x983600 }
58823
  },
58824
/* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
58825
  {
58826
    { 0, 0, 0, 0 },
58827
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
58828
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x908600 }
58829
  },
58830
/* cmp.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */
58831
  {
58832
    { 0, 0, 0, 0 },
58833
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
58834
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x90a600 }
58835
  },
58836
/* cmp.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */
58837
  {
58838
    { 0, 0, 0, 0 },
58839
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
58840
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x90b600 }
58841
  },
58842
/* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
58843
  {
58844
    { 0, 0, 0, 0 },
58845
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58846
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x900600 }
58847
  },
58848
/* cmp.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
58849
  {
58850
    { 0, 0, 0, 0 },
58851
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58852
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x902600 }
58853
  },
58854
/* cmp.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
58855
  {
58856
    { 0, 0, 0, 0 },
58857
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58858
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x903600 }
58859
  },
58860
/* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
58861
  {
58862
    { 0, 0, 0, 0 },
58863
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58864
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x92060000 }
58865
  },
58866
/* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
58867
  {
58868
    { 0, 0, 0, 0 },
58869
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58870
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x92260000 }
58871
  },
58872
/* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
58873
  {
58874
    { 0, 0, 0, 0 },
58875
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58876
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x92360000 }
58877
  },
58878
/* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
58879
  {
58880
    { 0, 0, 0, 0 },
58881
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58882
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x94060000 }
58883
  },
58884
/* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
58885
  {
58886
    { 0, 0, 0, 0 },
58887
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58888
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x94260000 }
58889
  },
58890
/* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
58891
  {
58892
    { 0, 0, 0, 0 },
58893
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58894
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x94360000 }
58895
  },
58896
/* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
58897
  {
58898
    { 0, 0, 0, 0 },
58899
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58900
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x96060000 }
58901
  },
58902
/* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
58903
  {
58904
    { 0, 0, 0, 0 },
58905
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58906
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x96260000 }
58907
  },
58908
/* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
58909
  {
58910
    { 0, 0, 0, 0 },
58911
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
58912
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x96360000 }
58913
  },
58914
/* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
58915
  {
58916
    { 0, 0, 0, 0 },
58917
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
58918
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92860000 }
58919
  },
58920
/* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
58921
  {
58922
    { 0, 0, 0, 0 },
58923
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
58924
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92a60000 }
58925
  },
58926
/* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
58927
  {
58928
    { 0, 0, 0, 0 },
58929
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
58930
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92b60000 }
58931
  },
58932
/* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
58933
  {
58934
    { 0, 0, 0, 0 },
58935
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
58936
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94860000 }
58937
  },
58938
/* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
58939
  {
58940
    { 0, 0, 0, 0 },
58941
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
58942
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94a60000 }
58943
  },
58944
/* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
58945
  {
58946
    { 0, 0, 0, 0 },
58947
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
58948
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94b60000 }
58949
  },
58950
/* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
58951
  {
58952
    { 0, 0, 0, 0 },
58953
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
58954
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92c60000 }
58955
  },
58956
/* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
58957
  {
58958
    { 0, 0, 0, 0 },
58959
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
58960
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92e60000 }
58961
  },
58962
/* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
58963
  {
58964
    { 0, 0, 0, 0 },
58965
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
58966
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92f60000 }
58967
  },
58968
/* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
58969
  {
58970
    { 0, 0, 0, 0 },
58971
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
58972
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94c60000 }
58973
  },
58974
/* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
58975
  {
58976
    { 0, 0, 0, 0 },
58977
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
58978
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94e60000 }
58979
  },
58980
/* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
58981
  {
58982
    { 0, 0, 0, 0 },
58983
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
58984
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94f60000 }
58985
  },
58986
/* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
58987
  {
58988
    { 0, 0, 0, 0 },
58989
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
58990
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96c60000 }
58991
  },
58992
/* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
58993
  {
58994
    { 0, 0, 0, 0 },
58995
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
58996
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96e60000 }
58997
  },
58998
/* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
58999
  {
59000
    { 0, 0, 0, 0 },
59001
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
59002
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96f60000 }
59003
  },
59004
/* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
59005
  {
59006
    { 0, 0, 0, 0 },
59007
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
59008
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96860000 }
59009
  },
59010
/* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
59011
  {
59012
    { 0, 0, 0, 0 },
59013
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } },
59014
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96a60000 }
59015
  },
59016
/* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
59017
  {
59018
    { 0, 0, 0, 0 },
59019
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } },
59020
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96b60000 }
59021
  },
59022
/* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
59023
  {
59024
    { 0, 0, 0, 0 },
59025
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
59026
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa8060000 }
59027
  },
59028
/* cmp.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */
59029
  {
59030
    { 0, 0, 0, 0 },
59031
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
59032
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa8260000 }
59033
  },
59034
/* cmp.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */
59035
  {
59036
    { 0, 0, 0, 0 },
59037
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
59038
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa8360000 }
59039
  },
59040
/* cmp.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */
59041
  {
59042
    { 0, 0, 0, 0 },
59043
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
59044
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb8360000 }
59045
  },
59046
/* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
59047
  {
59048
    { 0, 0, 0, 0 },
59049
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
59050
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0860000 }
59051
  },
59052
/* cmp.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */
59053
  {
59054
    { 0, 0, 0, 0 },
59055
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
59056
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0a60000 }
59057
  },
59058
/* cmp.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */
59059
  {
59060
    { 0, 0, 0, 0 },
59061
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
59062
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0b60000 }
59063
  },
59064
/* cmp.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */
59065
  {
59066
    { 0, 0, 0, 0 },
59067
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
59068
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0b60000 }
59069
  },
59070
/* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
59071
  {
59072
    { 0, 0, 0, 0 },
59073
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
59074
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa0060000 }
59075
  },
59076
/* cmp.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
59077
  {
59078
    { 0, 0, 0, 0 },
59079
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
59080
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa0260000 }
59081
  },
59082
/* cmp.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
59083
  {
59084
    { 0, 0, 0, 0 },
59085
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
59086
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa0360000 }
59087
  },
59088
/* cmp.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
59089
  {
59090
    { 0, 0, 0, 0 },
59091
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
59092
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb0360000 }
59093
  },
59094
/* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
59095
  {
59096
    { 0, 0, 0, 0 },
59097
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
59098
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa2060000 }
59099
  },
59100
/* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
59101
  {
59102
    { 0, 0, 0, 0 },
59103
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
59104
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa2260000 }
59105
  },
59106
/* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
59107
  {
59108
    { 0, 0, 0, 0 },
59109
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
59110
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa2360000 }
59111
  },
59112
/* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
59113
  {
59114
    { 0, 0, 0, 0 },
59115
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
59116
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xb2360000 }
59117
  },
59118
/* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
59119
  {
59120
    { 0, 0, 0, 0 },
59121
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
59122
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa4060000 }
59123
  },
59124
/* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
59125
  {
59126
    { 0, 0, 0, 0 },
59127
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
59128
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa4260000 }
59129
  },
59130
/* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
59131
  {
59132
    { 0, 0, 0, 0 },
59133
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
59134
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa4360000 }
59135
  },
59136
/* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
59137
  {
59138
    { 0, 0, 0, 0 },
59139
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
59140
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xb4360000 }
59141
  },
59142
/* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
59143
  {
59144
    { 0, 0, 0, 0 },
59145
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
59146
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa6060000 }
59147
  },
59148
/* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
59149
  {
59150
    { 0, 0, 0, 0 },
59151
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
59152
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa6260000 }
59153
  },
59154
/* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
59155
  {
59156
    { 0, 0, 0, 0 },
59157
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
59158
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa6360000 }
59159
  },
59160
/* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
59161
  {
59162
    { 0, 0, 0, 0 },
59163
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
59164
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xb6360000 }
59165
  },
59166
/* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
59167
  {
59168
    { 0, 0, 0, 0 },
59169
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
59170
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2860000 }
59171
  },
59172
/* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
59173
  {
59174
    { 0, 0, 0, 0 },
59175
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
59176
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2a60000 }
59177
  },
59178
/* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
59179
  {
59180
    { 0, 0, 0, 0 },
59181
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
59182
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2b60000 }
59183
  },
59184
/* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
59185
  {
59186
    { 0, 0, 0, 0 },
59187
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
59188
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xb2b60000 }
59189
  },
59190
/* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
59191
  {
59192
    { 0, 0, 0, 0 },
59193
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
59194
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4860000 }
59195
  },
59196
/* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
59197
  {
59198
    { 0, 0, 0, 0 },
59199
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
59200
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4a60000 }
59201
  },
59202
/* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
59203
  {
59204
    { 0, 0, 0, 0 },
59205
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
59206
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4b60000 }
59207
  },
59208
/* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
59209
  {
59210
    { 0, 0, 0, 0 },
59211
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
59212
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xb4b60000 }
59213
  },
59214
/* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
59215
  {
59216
    { 0, 0, 0, 0 },
59217
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
59218
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2c60000 }
59219
  },
59220
/* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
59221
  {
59222
    { 0, 0, 0, 0 },
59223
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
59224
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2e60000 }
59225
  },
59226
/* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
59227
  {
59228
    { 0, 0, 0, 0 },
59229
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
59230
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2f60000 }
59231
  },
59232
/* cmp.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
59233
  {
59234
    { 0, 0, 0, 0 },
59235
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
59236
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xb2f60000 }
59237
  },
59238
/* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
59239
  {
59240
    { 0, 0, 0, 0 },
59241
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
59242
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4c60000 }
59243
  },
59244
/* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
59245
  {
59246
    { 0, 0, 0, 0 },
59247
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
59248
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4e60000 }
59249
  },
59250
/* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
59251
  {
59252
    { 0, 0, 0, 0 },
59253
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
59254
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4f60000 }
59255
  },
59256
/* cmp.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
59257
  {
59258
    { 0, 0, 0, 0 },
59259
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
59260
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xb4f60000 }
59261
  },
59262
/* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
59263
  {
59264
    { 0, 0, 0, 0 },
59265
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
59266
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6c60000 }
59267
  },
59268
/* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
59269
  {
59270
    { 0, 0, 0, 0 },
59271
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
59272
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6e60000 }
59273
  },
59274
/* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
59275
  {
59276
    { 0, 0, 0, 0 },
59277
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
59278
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6f60000 }
59279
  },
59280
/* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
59281
  {
59282
    { 0, 0, 0, 0 },
59283
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
59284
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xb6f60000 }
59285
  },
59286
/* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
59287
  {
59288
    { 0, 0, 0, 0 },
59289
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
59290
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6860000 }
59291
  },
59292
/* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
59293
  {
59294
    { 0, 0, 0, 0 },
59295
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
59296
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6a60000 }
59297
  },
59298
/* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
59299
  {
59300
    { 0, 0, 0, 0 },
59301
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
59302
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6b60000 }
59303
  },
59304
/* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u24} */
59305
  {
59306
    { 0, 0, 0, 0 },
59307
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } },
59308
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xb6b60000 }
59309
  },
59310
/* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
59311
  {
59312
    { 0, 0, 0, 0 },
59313
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
59314
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb8060000 }
59315
  },
59316
/* cmp.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */
59317
  {
59318
    { 0, 0, 0, 0 },
59319
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
59320
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb8260000 }
59321
  },
59322
/* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
59323
  {
59324
    { 0, 0, 0, 0 },
59325
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
59326
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0860000 }
59327
  },
59328
/* cmp.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */
59329
  {
59330
    { 0, 0, 0, 0 },
59331
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
59332
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0a60000 }
59333
  },
59334
/* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
59335
  {
59336
    { 0, 0, 0, 0 },
59337
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
59338
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb0060000 }
59339
  },
59340
/* cmp.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
59341
  {
59342
    { 0, 0, 0, 0 },
59343
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
59344
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb0260000 }
59345
  },
59346
/* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
59347
  {
59348
    { 0, 0, 0, 0 },
59349
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
59350
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_QI, { 0xb2060000 }
59351
  },
59352
/* cmp.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
59353
  {
59354
    { 0, 0, 0, 0 },
59355
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
59356
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_QI, { 0xb2260000 }
59357
  },
59358
/* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
59359
  {
59360
    { 0, 0, 0, 0 },
59361
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
59362
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_QI, { 0xb4060000 }
59363
  },
59364
/* cmp.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
59365
  {
59366
    { 0, 0, 0, 0 },
59367
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
59368
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_QI, { 0xb4260000 }
59369
  },
59370
/* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
59371
  {
59372
    { 0, 0, 0, 0 },
59373
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
59374
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_QI, { 0xb6060000 }
59375
  },
59376
/* cmp.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
59377
  {
59378
    { 0, 0, 0, 0 },
59379
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
59380
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_QI, { 0xb6260000 }
59381
  },
59382
/* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
59383
  {
59384
    { 0, 0, 0, 0 },
59385
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
59386
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_QI, { 0xb2860000 }
59387
  },
59388
/* cmp.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
59389
  {
59390
    { 0, 0, 0, 0 },
59391
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
59392
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_QI, { 0xb2a60000 }
59393
  },
59394
/* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
59395
  {
59396
    { 0, 0, 0, 0 },
59397
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
59398
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_QI, { 0xb4860000 }
59399
  },
59400
/* cmp.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
59401
  {
59402
    { 0, 0, 0, 0 },
59403
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
59404
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_QI, { 0xb4a60000 }
59405
  },
59406
/* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
59407
  {
59408
    { 0, 0, 0, 0 },
59409
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
59410
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_QI, { 0xb2c60000 }
59411
  },
59412
/* cmp.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
59413
  {
59414
    { 0, 0, 0, 0 },
59415
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
59416
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_QI, { 0xb2e60000 }
59417
  },
59418
/* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
59419
  {
59420
    { 0, 0, 0, 0 },
59421
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
59422
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_QI, { 0xb4c60000 }
59423
  },
59424
/* cmp.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
59425
  {
59426
    { 0, 0, 0, 0 },
59427
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
59428
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_QI, { 0xb4e60000 }
59429
  },
59430
/* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
59431
  {
59432
    { 0, 0, 0, 0 },
59433
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
59434
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_QI, { 0xb6c60000 }
59435
  },
59436
/* cmp.b${G} ${Dsp-16-u24},${Dsp-40-u16} */
59437
  {
59438
    { 0, 0, 0, 0 },
59439
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } },
59440
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_QI, { 0xb6e60000 }
59441
  },
59442
/* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
59443
  {
59444
    { 0, 0, 0, 0 },
59445
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
59446
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_QI, { 0xb6860000 }
59447
  },
59448
/* cmp.b${G} ${Dsp-16-u24},${Dsp-40-u24} */
59449
  {
59450
    { 0, 0, 0, 0 },
59451
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } },
59452
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_QI, { 0xb6a60000 }
59453
  },
59454
/* cmp.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */
59455
  {
59456
    { 0, 0, 0, 0 },
59457
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
59458
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xc806 }
59459
  },
59460
/* cmp.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */
59461
  {
59462
    { 0, 0, 0, 0 },
59463
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
59464
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x8826 }
59465
  },
59466
/* cmp.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
59467
  {
59468
    { 0, 0, 0, 0 },
59469
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
59470
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x8806 }
59471
  },
59472
/* cmp.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */
59473
  {
59474
    { 0, 0, 0, 0 },
59475
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
59476
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xc086 }
59477
  },
59478
/* cmp.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */
59479
  {
59480
    { 0, 0, 0, 0 },
59481
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
59482
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x80a6 }
59483
  },
59484
/* cmp.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
59485
  {
59486
    { 0, 0, 0, 0 },
59487
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
59488
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x8086 }
59489
  },
59490
/* cmp.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */
59491
  {
59492
    { 0, 0, 0, 0 },
59493
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
59494
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xc006 }
59495
  },
59496
/* cmp.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */
59497
  {
59498
    { 0, 0, 0, 0 },
59499
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
59500
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x8026 }
59501
  },
59502
/* cmp.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
59503
  {
59504
    { 0, 0, 0, 0 },
59505
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
59506
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x8006 }
59507
  },
59508
/* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
59509
  {
59510
    { 0, 0, 0, 0 },
59511
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
59512
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0xc20600 }
59513
  },
59514
/* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
59515
  {
59516
    { 0, 0, 0, 0 },
59517
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
59518
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0x822600 }
59519
  },
59520
/* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
59521
  {
59522
    { 0, 0, 0, 0 },
59523
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
59524
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0x820600 }
59525
  },
59526
/* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
59527
  {
59528
    { 0, 0, 0, 0 },
59529
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
59530
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0xc4060000 }
59531
  },
59532
/* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
59533
  {
59534
    { 0, 0, 0, 0 },
59535
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
59536
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0x84260000 }
59537
  },
59538
/* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
59539
  {
59540
    { 0, 0, 0, 0 },
59541
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
59542
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0x84060000 }
59543
  },
59544
/* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
59545
  {
59546
    { 0, 0, 0, 0 },
59547
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
59548
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0xc6060000 }
59549
  },
59550
/* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
59551
  {
59552
    { 0, 0, 0, 0 },
59553
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
59554
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0x86260000 }
59555
  },
59556
/* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
59557
  {
59558
    { 0, 0, 0, 0 },
59559
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
59560
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0x86060000 }
59561
  },
59562
/* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */
59563
  {
59564
    { 0, 0, 0, 0 },
59565
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
59566
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0xc28600 }
59567
  },
59568
/* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */
59569
  {
59570
    { 0, 0, 0, 0 },
59571
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
59572
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0x82a600 }
59573
  },
59574
/* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
59575
  {
59576
    { 0, 0, 0, 0 },
59577
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
59578
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0x828600 }
59579
  },
59580
/* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */
59581
  {
59582
    { 0, 0, 0, 0 },
59583
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
59584
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0xc4860000 }
59585
  },
59586
/* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */
59587
  {
59588
    { 0, 0, 0, 0 },
59589
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
59590
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0x84a60000 }
59591
  },
59592
/* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
59593
  {
59594
    { 0, 0, 0, 0 },
59595
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
59596
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0x84860000 }
59597
  },
59598
/* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */
59599
  {
59600
    { 0, 0, 0, 0 },
59601
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
59602
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0xc2c600 }
59603
  },
59604
/* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */
59605
  {
59606
    { 0, 0, 0, 0 },
59607
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
59608
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82e600 }
59609
  },
59610
/* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
59611
  {
59612
    { 0, 0, 0, 0 },
59613
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
59614
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82c600 }
59615
  },
59616
/* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */
59617
  {
59618
    { 0, 0, 0, 0 },
59619
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
59620
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0xc4c60000 }
59621
  },
59622
/* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */
59623
  {
59624
    { 0, 0, 0, 0 },
59625
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
59626
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84e60000 }
59627
  },
59628
/* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
59629
  {
59630
    { 0, 0, 0, 0 },
59631
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
59632
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84c60000 }
59633
  },
59634
/* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */
59635
  {
59636
    { 0, 0, 0, 0 },
59637
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), 0 } },
59638
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0xc6c60000 }
59639
  },
59640
/* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */
59641
  {
59642
    { 0, 0, 0, 0 },
59643
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), 0 } },
59644
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0x86e60000 }
59645
  },
59646
/* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
59647
  {
59648
    { 0, 0, 0, 0 },
59649
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } },
59650
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0x86c60000 }
59651
  },
59652
/* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */
59653
  {
59654
    { 0, 0, 0, 0 },
59655
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U24), 0 } },
59656
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0xc6860000 }
59657
  },
59658
/* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */
59659
  {
59660
    { 0, 0, 0, 0 },
59661
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U24), 0 } },
59662
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0x86a60000 }
59663
  },
59664
/* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
59665
  {
59666
    { 0, 0, 0, 0 },
59667
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } },
59668
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0x86860000 }
59669
  },
59670
/* cmp.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
59671
  {
59672
    { 0, 0, 0, 0 },
59673
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } },
59674
    & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_Rn_direct_HI, { 0xc18000 }
59675
  },
59676
/* cmp.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */
59677
  {
59678
    { 0, 0, 0, 0 },
59679
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } },
59680
    & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_Rn_direct_HI, { 0xc1a000 }
59681
  },
59682
/* cmp.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */
59683
  {
59684
    { 0, 0, 0, 0 },
59685
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNHI), 0 } },
59686
    & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_Rn_direct_HI, { 0xc1b000 }
59687
  },
59688
/* cmp.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
59689
  {
59690
    { 0, 0, 0, 0 },
59691
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } },
59692
    & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_direct_HI, { 0xc18400 }
59693
  },
59694
/* cmp.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */
59695
  {
59696
    { 0, 0, 0, 0 },
59697
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } },
59698
    & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_direct_HI, { 0xc1a400 }
59699
  },
59700
/* cmp.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */
59701
  {
59702
    { 0, 0, 0, 0 },
59703
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANHI), 0 } },
59704
    & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_direct_HI, { 0xc1b400 }
59705
  },
59706
/* cmp.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
59707
  {
59708
    { 0, 0, 0, 0 },
59709
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
59710
    & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_indirect_HI, { 0xc18600 }
59711
  },
59712
/* cmp.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */
59713
  {
59714
    { 0, 0, 0, 0 },
59715
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
59716
    & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_indirect_HI, { 0xc1a600 }
59717
  },
59718
/* cmp.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */
59719
  {
59720
    { 0, 0, 0, 0 },
59721
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
59722
    & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_indirect_HI, { 0xc1b600 }
59723
  },
59724
/* cmp.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
59725
  {
59726
    { 0, 0, 0, 0 },
59727
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
59728
    & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_An_relative_HI, { 0xc1880000 }
59729
  },
59730
/* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
59731
  {
59732
    { 0, 0, 0, 0 },
59733
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
59734
    & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_An_relative_HI, { 0xc1a80000 }
59735
  },
59736
/* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
59737
  {
59738
    { 0, 0, 0, 0 },
59739
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
59740
    & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_An_relative_HI, { 0xc1b80000 }
59741
  },
59742
/* cmp.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
59743
  {
59744
    { 0, 0, 0, 0 },
59745
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
59746
    & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_An_relative_HI, { 0xc18c0000 }
59747
  },
59748
/* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
59749
  {
59750
    { 0, 0, 0, 0 },
59751
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
59752
    & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_An_relative_HI, { 0xc1ac0000 }
59753
  },
59754
/* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
59755
  {
59756
    { 0, 0, 0, 0 },
59757
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
59758
    & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_An_relative_HI, { 0xc1bc0000 }
59759
  },
59760
/* cmp.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
59761
  {
59762
    { 0, 0, 0, 0 },
59763
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
59764
    & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_SB_relative_HI, { 0xc18a0000 }
59765
  },
59766
/* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
59767
  {
59768
    { 0, 0, 0, 0 },
59769
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
59770
    & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_SB_relative_HI, { 0xc1aa0000 }
59771
  },
59772
/* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
59773
  {
59774
    { 0, 0, 0, 0 },
59775
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
59776
    & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_SB_relative_HI, { 0xc1ba0000 }
59777
  },
59778
/* cmp.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
59779
  {
59780
    { 0, 0, 0, 0 },
59781
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
59782
    & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_SB_relative_HI, { 0xc18e0000 }
59783
  },
59784
/* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
59785
  {
59786
    { 0, 0, 0, 0 },
59787
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
59788
    & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_SB_relative_HI, { 0xc1ae0000 }
59789
  },
59790
/* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
59791
  {
59792
    { 0, 0, 0, 0 },
59793
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
59794
    & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_SB_relative_HI, { 0xc1be0000 }
59795
  },
59796
/* cmp.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
59797
  {
59798
    { 0, 0, 0, 0 },
59799
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
59800
    & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_FB_relative_HI, { 0xc18b0000 }
59801
  },
59802
/* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
59803
  {
59804
    { 0, 0, 0, 0 },
59805
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
59806
    & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_FB_relative_HI, { 0xc1ab0000 }
59807
  },
59808
/* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
59809
  {
59810
    { 0, 0, 0, 0 },
59811
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
59812
    & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_FB_relative_HI, { 0xc1bb0000 }
59813
  },
59814
/* cmp.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
59815
  {
59816
    { 0, 0, 0, 0 },
59817
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } },
59818
    & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_absolute_HI, { 0xc18f0000 }
59819
  },
59820
/* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
59821
  {
59822
    { 0, 0, 0, 0 },
59823
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
59824
    & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_absolute_HI, { 0xc1af0000 }
59825
  },
59826
/* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
59827
  {
59828
    { 0, 0, 0, 0 },
59829
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
59830
    & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_absolute_HI, { 0xc1bf0000 }
59831
  },
59832
/* cmp.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
59833
  {
59834
    { 0, 0, 0, 0 },
59835
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } },
59836
    & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_Rn_direct_HI, { 0xc1c00000 }
59837
  },
59838
/* cmp.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */
59839
  {
59840
    { 0, 0, 0, 0 },
59841
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } },
59842
    & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_Rn_direct_HI, { 0xc1e00000 }
59843
  },
59844
/* cmp.w${G} ${Dsp-16-u16},$Dst16RnHI */
59845
  {
59846
    { 0, 0, 0, 0 },
59847
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16RNHI), 0 } },
59848
    & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_Rn_direct_HI, { 0xc1f00000 }
59849
  },
59850
/* cmp.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
59851
  {
59852
    { 0, 0, 0, 0 },
59853
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } },
59854
    & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_direct_HI, { 0xc1c40000 }
59855
  },
59856
/* cmp.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */
59857
  {
59858
    { 0, 0, 0, 0 },
59859
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } },
59860
    & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_direct_HI, { 0xc1e40000 }
59861
  },
59862
/* cmp.w${G} ${Dsp-16-u16},$Dst16AnHI */
59863
  {
59864
    { 0, 0, 0, 0 },
59865
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16ANHI), 0 } },
59866
    & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_direct_HI, { 0xc1f40000 }
59867
  },
59868
/* cmp.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
59869
  {
59870
    { 0, 0, 0, 0 },
59871
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
59872
    & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_indirect_HI, { 0xc1c60000 }
59873
  },
59874
/* cmp.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */
59875
  {
59876
    { 0, 0, 0, 0 },
59877
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
59878
    & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_indirect_HI, { 0xc1e60000 }
59879
  },
59880
/* cmp.w${G} ${Dsp-16-u16},[$Dst16An] */
59881
  {
59882
    { 0, 0, 0, 0 },
59883
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } },
59884
    & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_indirect_HI, { 0xc1f60000 }
59885
  },
59886
/* cmp.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
59887
  {
59888
    { 0, 0, 0, 0 },
59889
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
59890
    & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_An_relative_HI, { 0xc1c80000 }
59891
  },
59892
/* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
59893
  {
59894
    { 0, 0, 0, 0 },
59895
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
59896
    & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_An_relative_HI, { 0xc1e80000 }
59897
  },
59898
/* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
59899
  {
59900
    { 0, 0, 0, 0 },
59901
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
59902
    & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_An_relative_HI, { 0xc1f80000 }
59903
  },
59904
/* cmp.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
59905
  {
59906
    { 0, 0, 0, 0 },
59907
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
59908
    & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_An_relative_HI, { 0xc1cc0000 }
59909
  },
59910
/* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
59911
  {
59912
    { 0, 0, 0, 0 },
59913
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
59914
    & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_An_relative_HI, { 0xc1ec0000 }
59915
  },
59916
/* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
59917
  {
59918
    { 0, 0, 0, 0 },
59919
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
59920
    & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_An_relative_HI, { 0xc1fc0000 }
59921
  },
59922
/* cmp.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
59923
  {
59924
    { 0, 0, 0, 0 },
59925
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
59926
    & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_SB_relative_HI, { 0xc1ca0000 }
59927
  },
59928
/* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
59929
  {
59930
    { 0, 0, 0, 0 },
59931
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
59932
    & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_SB_relative_HI, { 0xc1ea0000 }
59933
  },
59934
/* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
59935
  {
59936
    { 0, 0, 0, 0 },
59937
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
59938
    & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_SB_relative_HI, { 0xc1fa0000 }
59939
  },
59940
/* cmp.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
59941
  {
59942
    { 0, 0, 0, 0 },
59943
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
59944
    & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_SB_relative_HI, { 0xc1ce0000 }
59945
  },
59946
/* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
59947
  {
59948
    { 0, 0, 0, 0 },
59949
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
59950
    & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_SB_relative_HI, { 0xc1ee0000 }
59951
  },
59952
/* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
59953
  {
59954
    { 0, 0, 0, 0 },
59955
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
59956
    & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_SB_relative_HI, { 0xc1fe0000 }
59957
  },
59958
/* cmp.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
59959
  {
59960
    { 0, 0, 0, 0 },
59961
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
59962
    & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_FB_relative_HI, { 0xc1cb0000 }
59963
  },
59964
/* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
59965
  {
59966
    { 0, 0, 0, 0 },
59967
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
59968
    & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_FB_relative_HI, { 0xc1eb0000 }
59969
  },
59970
/* cmp.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
59971
  {
59972
    { 0, 0, 0, 0 },
59973
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
59974
    & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_FB_relative_HI, { 0xc1fb0000 }
59975
  },
59976
/* cmp.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
59977
  {
59978
    { 0, 0, 0, 0 },
59979
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } },
59980
    & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_absolute_HI, { 0xc1cf0000 }
59981
  },
59982
/* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
59983
  {
59984
    { 0, 0, 0, 0 },
59985
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
59986
    & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_absolute_HI, { 0xc1ef0000 }
59987
  },
59988
/* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
59989
  {
59990
    { 0, 0, 0, 0 },
59991
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
59992
    & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_absolute_HI, { 0xc1ff0000 }
59993
  },
59994
/* cmp.w${G} $Src16RnHI,$Dst16RnHI */
59995
  {
59996
    { 0, 0, 0, 0 },
59997
    { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DST16RNHI), 0 } },
59998
    & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_Rn_direct_HI, { 0xc100 }
59999
  },
60000
/* cmp.w${G} $Src16AnHI,$Dst16RnHI */
60001
  {
60002
    { 0, 0, 0, 0 },
60003
    { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DST16RNHI), 0 } },
60004
    & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_Rn_direct_HI, { 0xc140 }
60005
  },
60006
/* cmp.w${G} [$Src16An],$Dst16RnHI */
60007
  {
60008
    { 0, 0, 0, 0 },
60009
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } },
60010
    & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_Rn_direct_HI, { 0xc160 }
60011
  },
60012
/* cmp.w${G} $Src16RnHI,$Dst16AnHI */
60013
  {
60014
    { 0, 0, 0, 0 },
60015
    { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DST16ANHI), 0 } },
60016
    & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_direct_HI, { 0xc104 }
60017
  },
60018
/* cmp.w${G} $Src16AnHI,$Dst16AnHI */
60019
  {
60020
    { 0, 0, 0, 0 },
60021
    { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DST16ANHI), 0 } },
60022
    & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_direct_HI, { 0xc144 }
60023
  },
60024
/* cmp.w${G} [$Src16An],$Dst16AnHI */
60025
  {
60026
    { 0, 0, 0, 0 },
60027
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } },
60028
    & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_direct_HI, { 0xc164 }
60029
  },
60030
/* cmp.w${G} $Src16RnHI,[$Dst16An] */
60031
  {
60032
    { 0, 0, 0, 0 },
60033
    { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', '[', OP (DST16AN), ']', 0 } },
60034
    & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_indirect_HI, { 0xc106 }
60035
  },
60036
/* cmp.w${G} $Src16AnHI,[$Dst16An] */
60037
  {
60038
    { 0, 0, 0, 0 },
60039
    { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', '[', OP (DST16AN), ']', 0 } },
60040
    & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_indirect_HI, { 0xc146 }
60041
  },
60042
/* cmp.w${G} [$Src16An],[$Dst16An] */
60043
  {
60044
    { 0, 0, 0, 0 },
60045
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
60046
    & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_indirect_HI, { 0xc166 }
60047
  },
60048
/* cmp.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
60049
  {
60050
    { 0, 0, 0, 0 },
60051
    { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
60052
    & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_An_relative_HI, { 0xc10800 }
60053
  },
60054
/* cmp.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
60055
  {
60056
    { 0, 0, 0, 0 },
60057
    { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
60058
    & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_An_relative_HI, { 0xc14800 }
60059
  },
60060
/* cmp.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
60061
  {
60062
    { 0, 0, 0, 0 },
60063
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
60064
    & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_An_relative_HI, { 0xc16800 }
60065
  },
60066
/* cmp.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
60067
  {
60068
    { 0, 0, 0, 0 },
60069
    { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
60070
    & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_An_relative_HI, { 0xc10c0000 }
60071
  },
60072
/* cmp.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
60073
  {
60074
    { 0, 0, 0, 0 },
60075
    { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
60076
    & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_An_relative_HI, { 0xc14c0000 }
60077
  },
60078
/* cmp.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
60079
  {
60080
    { 0, 0, 0, 0 },
60081
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
60082
    & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_An_relative_HI, { 0xc16c0000 }
60083
  },
60084
/* cmp.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */
60085
  {
60086
    { 0, 0, 0, 0 },
60087
    { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
60088
    & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_SB_relative_HI, { 0xc10a00 }
60089
  },
60090
/* cmp.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */
60091
  {
60092
    { 0, 0, 0, 0 },
60093
    { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
60094
    & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_SB_relative_HI, { 0xc14a00 }
60095
  },
60096
/* cmp.w${G} [$Src16An],${Dsp-16-u8}[sb] */
60097
  {
60098
    { 0, 0, 0, 0 },
60099
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
60100
    & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_SB_relative_HI, { 0xc16a00 }
60101
  },
60102
/* cmp.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */
60103
  {
60104
    { 0, 0, 0, 0 },
60105
    { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
60106
    & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_SB_relative_HI, { 0xc10e0000 }
60107
  },
60108
/* cmp.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */
60109
  {
60110
    { 0, 0, 0, 0 },
60111
    { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
60112
    & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_SB_relative_HI, { 0xc14e0000 }
60113
  },
60114
/* cmp.w${G} [$Src16An],${Dsp-16-u16}[sb] */
60115
  {
60116
    { 0, 0, 0, 0 },
60117
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
60118
    & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_SB_relative_HI, { 0xc16e0000 }
60119
  },
60120
/* cmp.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */
60121
  {
60122
    { 0, 0, 0, 0 },
60123
    { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
60124
    & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_FB_relative_HI, { 0xc10b00 }
60125
  },
60126
/* cmp.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */
60127
  {
60128
    { 0, 0, 0, 0 },
60129
    { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
60130
    & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_FB_relative_HI, { 0xc14b00 }
60131
  },
60132
/* cmp.w${G} [$Src16An],${Dsp-16-s8}[fb] */
60133
  {
60134
    { 0, 0, 0, 0 },
60135
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
60136
    & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_FB_relative_HI, { 0xc16b00 }
60137
  },
60138
/* cmp.w${G} $Src16RnHI,${Dsp-16-u16} */
60139
  {
60140
    { 0, 0, 0, 0 },
60141
    { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), 0 } },
60142
    & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_absolute_HI, { 0xc10f0000 }
60143
  },
60144
/* cmp.w${G} $Src16AnHI,${Dsp-16-u16} */
60145
  {
60146
    { 0, 0, 0, 0 },
60147
    { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), 0 } },
60148
    & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_absolute_HI, { 0xc14f0000 }
60149
  },
60150
/* cmp.w${G} [$Src16An],${Dsp-16-u16} */
60151
  {
60152
    { 0, 0, 0, 0 },
60153
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } },
60154
    & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_absolute_HI, { 0xc16f0000 }
60155
  },
60156
/* cmp.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
60157
  {
60158
    { 0, 0, 0, 0 },
60159
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } },
60160
    & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_Rn_direct_QI, { 0xc08000 }
60161
  },
60162
/* cmp.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */
60163
  {
60164
    { 0, 0, 0, 0 },
60165
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } },
60166
    & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_Rn_direct_QI, { 0xc0a000 }
60167
  },
60168
/* cmp.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */
60169
  {
60170
    { 0, 0, 0, 0 },
60171
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNQI), 0 } },
60172
    & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_Rn_direct_QI, { 0xc0b000 }
60173
  },
60174
/* cmp.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
60175
  {
60176
    { 0, 0, 0, 0 },
60177
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } },
60178
    & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_direct_QI, { 0xc08400 }
60179
  },
60180
/* cmp.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */
60181
  {
60182
    { 0, 0, 0, 0 },
60183
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } },
60184
    & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_direct_QI, { 0xc0a400 }
60185
  },
60186
/* cmp.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */
60187
  {
60188
    { 0, 0, 0, 0 },
60189
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANQI), 0 } },
60190
    & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_direct_QI, { 0xc0b400 }
60191
  },
60192
/* cmp.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
60193
  {
60194
    { 0, 0, 0, 0 },
60195
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
60196
    & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_indirect_QI, { 0xc08600 }
60197
  },
60198
/* cmp.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */
60199
  {
60200
    { 0, 0, 0, 0 },
60201
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
60202
    & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_indirect_QI, { 0xc0a600 }
60203
  },
60204
/* cmp.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */
60205
  {
60206
    { 0, 0, 0, 0 },
60207
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
60208
    & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_indirect_QI, { 0xc0b600 }
60209
  },
60210
/* cmp.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
60211
  {
60212
    { 0, 0, 0, 0 },
60213
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
60214
    & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_An_relative_QI, { 0xc0880000 }
60215
  },
60216
/* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
60217
  {
60218
    { 0, 0, 0, 0 },
60219
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
60220
    & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_An_relative_QI, { 0xc0a80000 }
60221
  },
60222
/* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
60223
  {
60224
    { 0, 0, 0, 0 },
60225
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
60226
    & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_An_relative_QI, { 0xc0b80000 }
60227
  },
60228
/* cmp.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
60229
  {
60230
    { 0, 0, 0, 0 },
60231
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
60232
    & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_An_relative_QI, { 0xc08c0000 }
60233
  },
60234
/* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
60235
  {
60236
    { 0, 0, 0, 0 },
60237
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
60238
    & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_An_relative_QI, { 0xc0ac0000 }
60239
  },
60240
/* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
60241
  {
60242
    { 0, 0, 0, 0 },
60243
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
60244
    & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_An_relative_QI, { 0xc0bc0000 }
60245
  },
60246
/* cmp.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
60247
  {
60248
    { 0, 0, 0, 0 },
60249
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
60250
    & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_SB_relative_QI, { 0xc08a0000 }
60251
  },
60252
/* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
60253
  {
60254
    { 0, 0, 0, 0 },
60255
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
60256
    & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_SB_relative_QI, { 0xc0aa0000 }
60257
  },
60258
/* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
60259
  {
60260
    { 0, 0, 0, 0 },
60261
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
60262
    & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_SB_relative_QI, { 0xc0ba0000 }
60263
  },
60264
/* cmp.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
60265
  {
60266
    { 0, 0, 0, 0 },
60267
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
60268
    & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_SB_relative_QI, { 0xc08e0000 }
60269
  },
60270
/* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
60271
  {
60272
    { 0, 0, 0, 0 },
60273
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
60274
    & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_SB_relative_QI, { 0xc0ae0000 }
60275
  },
60276
/* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
60277
  {
60278
    { 0, 0, 0, 0 },
60279
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
60280
    & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_SB_relative_QI, { 0xc0be0000 }
60281
  },
60282
/* cmp.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
60283
  {
60284
    { 0, 0, 0, 0 },
60285
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
60286
    & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_FB_relative_QI, { 0xc08b0000 }
60287
  },
60288
/* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
60289
  {
60290
    { 0, 0, 0, 0 },
60291
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
60292
    & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_FB_relative_QI, { 0xc0ab0000 }
60293
  },
60294
/* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
60295
  {
60296
    { 0, 0, 0, 0 },
60297
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
60298
    & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_FB_relative_QI, { 0xc0bb0000 }
60299
  },
60300
/* cmp.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
60301
  {
60302
    { 0, 0, 0, 0 },
60303
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } },
60304
    & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_absolute_QI, { 0xc08f0000 }
60305
  },
60306
/* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
60307
  {
60308
    { 0, 0, 0, 0 },
60309
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
60310
    & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_absolute_QI, { 0xc0af0000 }
60311
  },
60312
/* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
60313
  {
60314
    { 0, 0, 0, 0 },
60315
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
60316
    & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_absolute_QI, { 0xc0bf0000 }
60317
  },
60318
/* cmp.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
60319
  {
60320
    { 0, 0, 0, 0 },
60321
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } },
60322
    & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_Rn_direct_QI, { 0xc0c00000 }
60323
  },
60324
/* cmp.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */
60325
  {
60326
    { 0, 0, 0, 0 },
60327
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } },
60328
    & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_Rn_direct_QI, { 0xc0e00000 }
60329
  },
60330
/* cmp.b${G} ${Dsp-16-u16},$Dst16RnQI */
60331
  {
60332
    { 0, 0, 0, 0 },
60333
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16RNQI), 0 } },
60334
    & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_Rn_direct_QI, { 0xc0f00000 }
60335
  },
60336
/* cmp.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
60337
  {
60338
    { 0, 0, 0, 0 },
60339
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } },
60340
    & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_direct_QI, { 0xc0c40000 }
60341
  },
60342
/* cmp.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */
60343
  {
60344
    { 0, 0, 0, 0 },
60345
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } },
60346
    & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_direct_QI, { 0xc0e40000 }
60347
  },
60348
/* cmp.b${G} ${Dsp-16-u16},$Dst16AnQI */
60349
  {
60350
    { 0, 0, 0, 0 },
60351
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16ANQI), 0 } },
60352
    & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_direct_QI, { 0xc0f40000 }
60353
  },
60354
/* cmp.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
60355
  {
60356
    { 0, 0, 0, 0 },
60357
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
60358
    & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_indirect_QI, { 0xc0c60000 }
60359
  },
60360
/* cmp.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */
60361
  {
60362
    { 0, 0, 0, 0 },
60363
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
60364
    & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_indirect_QI, { 0xc0e60000 }
60365
  },
60366
/* cmp.b${G} ${Dsp-16-u16},[$Dst16An] */
60367
  {
60368
    { 0, 0, 0, 0 },
60369
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } },
60370
    & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_indirect_QI, { 0xc0f60000 }
60371
  },
60372
/* cmp.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
60373
  {
60374
    { 0, 0, 0, 0 },
60375
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
60376
    & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_An_relative_QI, { 0xc0c80000 }
60377
  },
60378
/* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
60379
  {
60380
    { 0, 0, 0, 0 },
60381
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
60382
    & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_An_relative_QI, { 0xc0e80000 }
60383
  },
60384
/* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
60385
  {
60386
    { 0, 0, 0, 0 },
60387
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
60388
    & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_An_relative_QI, { 0xc0f80000 }
60389
  },
60390
/* cmp.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
60391
  {
60392
    { 0, 0, 0, 0 },
60393
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
60394
    & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_An_relative_QI, { 0xc0cc0000 }
60395
  },
60396
/* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
60397
  {
60398
    { 0, 0, 0, 0 },
60399
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
60400
    & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_An_relative_QI, { 0xc0ec0000 }
60401
  },
60402
/* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
60403
  {
60404
    { 0, 0, 0, 0 },
60405
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
60406
    & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_An_relative_QI, { 0xc0fc0000 }
60407
  },
60408
/* cmp.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
60409
  {
60410
    { 0, 0, 0, 0 },
60411
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
60412
    & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_SB_relative_QI, { 0xc0ca0000 }
60413
  },
60414
/* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
60415
  {
60416
    { 0, 0, 0, 0 },
60417
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
60418
    & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_SB_relative_QI, { 0xc0ea0000 }
60419
  },
60420
/* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
60421
  {
60422
    { 0, 0, 0, 0 },
60423
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
60424
    & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_SB_relative_QI, { 0xc0fa0000 }
60425
  },
60426
/* cmp.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
60427
  {
60428
    { 0, 0, 0, 0 },
60429
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
60430
    & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_SB_relative_QI, { 0xc0ce0000 }
60431
  },
60432
/* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
60433
  {
60434
    { 0, 0, 0, 0 },
60435
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
60436
    & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_SB_relative_QI, { 0xc0ee0000 }
60437
  },
60438
/* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
60439
  {
60440
    { 0, 0, 0, 0 },
60441
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
60442
    & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_SB_relative_QI, { 0xc0fe0000 }
60443
  },
60444
/* cmp.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
60445
  {
60446
    { 0, 0, 0, 0 },
60447
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
60448
    & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_FB_relative_QI, { 0xc0cb0000 }
60449
  },
60450
/* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
60451
  {
60452
    { 0, 0, 0, 0 },
60453
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
60454
    & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_FB_relative_QI, { 0xc0eb0000 }
60455
  },
60456
/* cmp.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
60457
  {
60458
    { 0, 0, 0, 0 },
60459
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
60460
    & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_FB_relative_QI, { 0xc0fb0000 }
60461
  },
60462
/* cmp.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
60463
  {
60464
    { 0, 0, 0, 0 },
60465
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } },
60466
    & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_absolute_QI, { 0xc0cf0000 }
60467
  },
60468
/* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
60469
  {
60470
    { 0, 0, 0, 0 },
60471
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
60472
    & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_absolute_QI, { 0xc0ef0000 }
60473
  },
60474
/* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
60475
  {
60476
    { 0, 0, 0, 0 },
60477
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
60478
    & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_absolute_QI, { 0xc0ff0000 }
60479
  },
60480
/* cmp.b${G} $Src16RnQI,$Dst16RnQI */
60481
  {
60482
    { 0, 0, 0, 0 },
60483
    { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DST16RNQI), 0 } },
60484
    & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_Rn_direct_QI, { 0xc000 }
60485
  },
60486
/* cmp.b${G} $Src16AnQI,$Dst16RnQI */
60487
  {
60488
    { 0, 0, 0, 0 },
60489
    { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DST16RNQI), 0 } },
60490
    & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_Rn_direct_QI, { 0xc040 }
60491
  },
60492
/* cmp.b${G} [$Src16An],$Dst16RnQI */
60493
  {
60494
    { 0, 0, 0, 0 },
60495
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } },
60496
    & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_Rn_direct_QI, { 0xc060 }
60497
  },
60498
/* cmp.b${G} $Src16RnQI,$Dst16AnQI */
60499
  {
60500
    { 0, 0, 0, 0 },
60501
    { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DST16ANQI), 0 } },
60502
    & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_direct_QI, { 0xc004 }
60503
  },
60504
/* cmp.b${G} $Src16AnQI,$Dst16AnQI */
60505
  {
60506
    { 0, 0, 0, 0 },
60507
    { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DST16ANQI), 0 } },
60508
    & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_direct_QI, { 0xc044 }
60509
  },
60510
/* cmp.b${G} [$Src16An],$Dst16AnQI */
60511
  {
60512
    { 0, 0, 0, 0 },
60513
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } },
60514
    & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_direct_QI, { 0xc064 }
60515
  },
60516
/* cmp.b${G} $Src16RnQI,[$Dst16An] */
60517
  {
60518
    { 0, 0, 0, 0 },
60519
    { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', '[', OP (DST16AN), ']', 0 } },
60520
    & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_indirect_QI, { 0xc006 }
60521
  },
60522
/* cmp.b${G} $Src16AnQI,[$Dst16An] */
60523
  {
60524
    { 0, 0, 0, 0 },
60525
    { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', '[', OP (DST16AN), ']', 0 } },
60526
    & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_indirect_QI, { 0xc046 }
60527
  },
60528
/* cmp.b${G} [$Src16An],[$Dst16An] */
60529
  {
60530
    { 0, 0, 0, 0 },
60531
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
60532
    & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_indirect_QI, { 0xc066 }
60533
  },
60534
/* cmp.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
60535
  {
60536
    { 0, 0, 0, 0 },
60537
    { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
60538
    & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_An_relative_QI, { 0xc00800 }
60539
  },
60540
/* cmp.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
60541
  {
60542
    { 0, 0, 0, 0 },
60543
    { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
60544
    & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_An_relative_QI, { 0xc04800 }
60545
  },
60546
/* cmp.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
60547
  {
60548
    { 0, 0, 0, 0 },
60549
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
60550
    & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_An_relative_QI, { 0xc06800 }
60551
  },
60552
/* cmp.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
60553
  {
60554
    { 0, 0, 0, 0 },
60555
    { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
60556
    & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_An_relative_QI, { 0xc00c0000 }
60557
  },
60558
/* cmp.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
60559
  {
60560
    { 0, 0, 0, 0 },
60561
    { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
60562
    & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_An_relative_QI, { 0xc04c0000 }
60563
  },
60564
/* cmp.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
60565
  {
60566
    { 0, 0, 0, 0 },
60567
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
60568
    & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_An_relative_QI, { 0xc06c0000 }
60569
  },
60570
/* cmp.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */
60571
  {
60572
    { 0, 0, 0, 0 },
60573
    { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
60574
    & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_SB_relative_QI, { 0xc00a00 }
60575
  },
60576
/* cmp.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */
60577
  {
60578
    { 0, 0, 0, 0 },
60579
    { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
60580
    & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_SB_relative_QI, { 0xc04a00 }
60581
  },
60582
/* cmp.b${G} [$Src16An],${Dsp-16-u8}[sb] */
60583
  {
60584
    { 0, 0, 0, 0 },
60585
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
60586
    & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_SB_relative_QI, { 0xc06a00 }
60587
  },
60588
/* cmp.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */
60589
  {
60590
    { 0, 0, 0, 0 },
60591
    { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
60592
    & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_SB_relative_QI, { 0xc00e0000 }
60593
  },
60594
/* cmp.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */
60595
  {
60596
    { 0, 0, 0, 0 },
60597
    { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
60598
    & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_SB_relative_QI, { 0xc04e0000 }
60599
  },
60600
/* cmp.b${G} [$Src16An],${Dsp-16-u16}[sb] */
60601
  {
60602
    { 0, 0, 0, 0 },
60603
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
60604
    & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_SB_relative_QI, { 0xc06e0000 }
60605
  },
60606
/* cmp.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */
60607
  {
60608
    { 0, 0, 0, 0 },
60609
    { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
60610
    & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_FB_relative_QI, { 0xc00b00 }
60611
  },
60612
/* cmp.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */
60613
  {
60614
    { 0, 0, 0, 0 },
60615
    { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
60616
    & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_FB_relative_QI, { 0xc04b00 }
60617
  },
60618
/* cmp.b${G} [$Src16An],${Dsp-16-s8}[fb] */
60619
  {
60620
    { 0, 0, 0, 0 },
60621
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
60622
    & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_FB_relative_QI, { 0xc06b00 }
60623
  },
60624
/* cmp.b${G} $Src16RnQI,${Dsp-16-u16} */
60625
  {
60626
    { 0, 0, 0, 0 },
60627
    { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), 0 } },
60628
    & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_absolute_QI, { 0xc00f0000 }
60629
  },
60630
/* cmp.b${G} $Src16AnQI,${Dsp-16-u16} */
60631
  {
60632
    { 0, 0, 0, 0 },
60633
    { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), 0 } },
60634
    & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_absolute_QI, { 0xc04f0000 }
60635
  },
60636
/* cmp.b${G} [$Src16An],${Dsp-16-u16} */
60637
  {
60638
    { 0, 0, 0, 0 },
60639
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } },
60640
    & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_absolute_QI, { 0xc06f0000 }
60641
  },
60642
/* cmp.b${S} #${Imm-8-QI},r0l */
60643
  {
60644
    { 0, 0, 0, 0 },
60645
    { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'l', 0 } },
60646
    & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_R0l_direct_QI, { 0xe400 }
60647
  },
60648
/* cmp.b${S} #${Imm-8-QI},r0h */
60649
  {
60650
    { 0, 0, 0, 0 },
60651
    { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'h', 0 } },
60652
    & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_R0h_direct_QI, { 0xe300 }
60653
  },
60654
/* cmp.b${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */
60655
  {
60656
    { 0, 0, 0, 0 },
60657
    { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
60658
    & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_8_SB_relative_QI, { 0xe50000 }
60659
  },
60660
/* cmp.b${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */
60661
  {
60662
    { 0, 0, 0, 0 },
60663
    { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
60664
    & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_8_FB_relative_QI, { 0xe60000 }
60665
  },
60666
/* cmp.b${S} #${Imm-8-QI},${Dsp-16-u16} */
60667
  {
60668
    { 0, 0, 0, 0 },
60669
    { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_U16), 0 } },
60670
    & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_16_absolute_QI, { 0xe7000000 }
60671
  },
60672
/* cmp.w${Q} #${Imm-12-s4},$Dst32RnUnprefixedHI */
60673
  {
60674
    { 0, 0, 0, 0 },
60675
    { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
60676
    & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0xe910 }
60677
  },
60678
/* cmp.w${Q} #${Imm-12-s4},$Dst32AnUnprefixedHI */
60679
  {
60680
    { 0, 0, 0, 0 },
60681
    { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
60682
    & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0xe190 }
60683
  },
60684
/* cmp.w${Q} #${Imm-12-s4},[$Dst32AnUnprefixed] */
60685
  {
60686
    { 0, 0, 0, 0 },
60687
    { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
60688
    & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0xe110 }
60689
  },
60690
/* cmp.w${Q} #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
60691
  {
60692
    { 0, 0, 0, 0 },
60693
    { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
60694
    & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0xe31000 }
60695
  },
60696
/* cmp.w${Q} #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
60697
  {
60698
    { 0, 0, 0, 0 },
60699
    { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
60700
    & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0xe5100000 }
60701
  },
60702
/* cmp.w${Q} #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
60703
  {
60704
    { 0, 0, 0, 0 },
60705
    { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
60706
    & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0xe7100000 }
60707
  },
60708
/* cmp.w${Q} #${Imm-12-s4},${Dsp-16-u8}[sb] */
60709
  {
60710
    { 0, 0, 0, 0 },
60711
    { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
60712
    & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0xe39000 }
60713
  },
60714
/* cmp.w${Q} #${Imm-12-s4},${Dsp-16-u16}[sb] */
60715
  {
60716
    { 0, 0, 0, 0 },
60717
    { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
60718
    & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0xe5900000 }
60719
  },
60720
/* cmp.w${Q} #${Imm-12-s4},${Dsp-16-s8}[fb] */
60721
  {
60722
    { 0, 0, 0, 0 },
60723
    { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
60724
    & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0xe3d000 }
60725
  },
60726
/* cmp.w${Q} #${Imm-12-s4},${Dsp-16-s16}[fb] */
60727
  {
60728
    { 0, 0, 0, 0 },
60729
    { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
60730
    & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0xe5d00000 }
60731
  },
60732
/* cmp.w${Q} #${Imm-12-s4},${Dsp-16-u16} */
60733
  {
60734
    { 0, 0, 0, 0 },
60735
    { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), 0 } },
60736
    & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0xe7d00000 }
60737
  },
60738
/* cmp.w${Q} #${Imm-12-s4},${Dsp-16-u24} */
60739
  {
60740
    { 0, 0, 0, 0 },
60741
    { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U24), 0 } },
60742
    & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0xe7900000 }
60743
  },
60744
/* cmp.b${Q} #${Imm-12-s4},$Dst32RnUnprefixedQI */
60745
  {
60746
    { 0, 0, 0, 0 },
60747
    { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
60748
    & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0xe810 }
60749
  },
60750
/* cmp.b${Q} #${Imm-12-s4},$Dst32AnUnprefixedQI */
60751
  {
60752
    { 0, 0, 0, 0 },
60753
    { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
60754
    & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0xe090 }
60755
  },
60756
/* cmp.b${Q} #${Imm-12-s4},[$Dst32AnUnprefixed] */
60757
  {
60758
    { 0, 0, 0, 0 },
60759
    { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
60760
    & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0xe010 }
60761
  },
60762
/* cmp.b${Q} #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
60763
  {
60764
    { 0, 0, 0, 0 },
60765
    { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
60766
    & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0xe21000 }
60767
  },
60768
/* cmp.b${Q} #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
60769
  {
60770
    { 0, 0, 0, 0 },
60771
    { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
60772
    & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0xe4100000 }
60773
  },
60774
/* cmp.b${Q} #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
60775
  {
60776
    { 0, 0, 0, 0 },
60777
    { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
60778
    & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0xe6100000 }
60779
  },
60780
/* cmp.b${Q} #${Imm-12-s4},${Dsp-16-u8}[sb] */
60781
  {
60782
    { 0, 0, 0, 0 },
60783
    { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
60784
    & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0xe29000 }
60785
  },
60786
/* cmp.b${Q} #${Imm-12-s4},${Dsp-16-u16}[sb] */
60787
  {
60788
    { 0, 0, 0, 0 },
60789
    { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
60790
    & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0xe4900000 }
60791
  },
60792
/* cmp.b${Q} #${Imm-12-s4},${Dsp-16-s8}[fb] */
60793
  {
60794
    { 0, 0, 0, 0 },
60795
    { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
60796
    & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0xe2d000 }
60797
  },
60798
/* cmp.b${Q} #${Imm-12-s4},${Dsp-16-s16}[fb] */
60799
  {
60800
    { 0, 0, 0, 0 },
60801
    { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
60802
    & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0xe4d00000 }
60803
  },
60804
/* cmp.b${Q} #${Imm-12-s4},${Dsp-16-u16} */
60805
  {
60806
    { 0, 0, 0, 0 },
60807
    { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), 0 } },
60808
    & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0xe6d00000 }
60809
  },
60810
/* cmp.b${Q} #${Imm-12-s4},${Dsp-16-u24} */
60811
  {
60812
    { 0, 0, 0, 0 },
60813
    { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U24), 0 } },
60814
    & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0xe6900000 }
60815
  },
60816
/* cmp.w${Q} #${Imm-8-s4},$Dst16RnHI */
60817
  {
60818
    { 0, 0, 0, 0 },
60819
    { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DST16RNHI), 0 } },
60820
    & ifmt_mov16_w_imm4_Q_16_dst16_Rn_direct_HI, { 0xd100 }
60821
  },
60822
/* cmp.w${Q} #${Imm-8-s4},$Dst16AnHI */
60823
  {
60824
    { 0, 0, 0, 0 },
60825
    { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DST16ANHI), 0 } },
60826
    & ifmt_mov16_w_imm4_Q_16_dst16_An_direct_HI, { 0xd104 }
60827
  },
60828
/* cmp.w${Q} #${Imm-8-s4},[$Dst16An] */
60829
  {
60830
    { 0, 0, 0, 0 },
60831
    { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', '[', OP (DST16AN), ']', 0 } },
60832
    & ifmt_mov16_w_imm4_Q_16_dst16_An_indirect_HI, { 0xd106 }
60833
  },
60834
/* cmp.w${Q} #${Imm-8-s4},${Dsp-16-u8}[$Dst16An] */
60835
  {
60836
    { 0, 0, 0, 0 },
60837
    { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
60838
    & ifmt_mov16_w_imm4_Q_16_dst16_16_8_An_relative_HI, { 0xd10800 }
60839
  },
60840
/* cmp.w${Q} #${Imm-8-s4},${Dsp-16-u16}[$Dst16An] */
60841
  {
60842
    { 0, 0, 0, 0 },
60843
    { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
60844
    & ifmt_mov16_w_imm4_Q_16_dst16_16_16_An_relative_HI, { 0xd10c0000 }
60845
  },
60846
/* cmp.w${Q} #${Imm-8-s4},${Dsp-16-u8}[sb] */
60847
  {
60848
    { 0, 0, 0, 0 },
60849
    { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
60850
    & ifmt_mov16_w_imm4_Q_16_dst16_16_8_SB_relative_HI, { 0xd10a00 }
60851
  },
60852
/* cmp.w${Q} #${Imm-8-s4},${Dsp-16-u16}[sb] */
60853
  {
60854
    { 0, 0, 0, 0 },
60855
    { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
60856
    & ifmt_mov16_w_imm4_Q_16_dst16_16_16_SB_relative_HI, { 0xd10e0000 }
60857
  },
60858
/* cmp.w${Q} #${Imm-8-s4},${Dsp-16-s8}[fb] */
60859
  {
60860
    { 0, 0, 0, 0 },
60861
    { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
60862
    & ifmt_mov16_w_imm4_Q_16_dst16_16_8_FB_relative_HI, { 0xd10b00 }
60863
  },
60864
/* cmp.w${Q} #${Imm-8-s4},${Dsp-16-u16} */
60865
  {
60866
    { 0, 0, 0, 0 },
60867
    { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), 0 } },
60868
    & ifmt_mov16_w_imm4_Q_16_dst16_16_16_absolute_HI, { 0xd10f0000 }
60869
  },
60870
/* cmp.b${Q} #${Imm-8-s4},$Dst16RnQI */
60871
  {
60872
    { 0, 0, 0, 0 },
60873
    { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DST16RNQI), 0 } },
60874
    & ifmt_mov16_b_imm4_Q_16_dst16_Rn_direct_QI, { 0xd000 }
60875
  },
60876
/* cmp.b${Q} #${Imm-8-s4},$Dst16AnQI */
60877
  {
60878
    { 0, 0, 0, 0 },
60879
    { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DST16ANQI), 0 } },
60880
    & ifmt_mov16_b_imm4_Q_16_dst16_An_direct_QI, { 0xd004 }
60881
  },
60882
/* cmp.b${Q} #${Imm-8-s4},[$Dst16An] */
60883
  {
60884
    { 0, 0, 0, 0 },
60885
    { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', '[', OP (DST16AN), ']', 0 } },
60886
    & ifmt_mov16_b_imm4_Q_16_dst16_An_indirect_QI, { 0xd006 }
60887
  },
60888
/* cmp.b${Q} #${Imm-8-s4},${Dsp-16-u8}[$Dst16An] */
60889
  {
60890
    { 0, 0, 0, 0 },
60891
    { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
60892
    & ifmt_mov16_b_imm4_Q_16_dst16_16_8_An_relative_QI, { 0xd00800 }
60893
  },
60894
/* cmp.b${Q} #${Imm-8-s4},${Dsp-16-u16}[$Dst16An] */
60895
  {
60896
    { 0, 0, 0, 0 },
60897
    { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
60898
    & ifmt_mov16_b_imm4_Q_16_dst16_16_16_An_relative_QI, { 0xd00c0000 }
60899
  },
60900
/* cmp.b${Q} #${Imm-8-s4},${Dsp-16-u8}[sb] */
60901
  {
60902
    { 0, 0, 0, 0 },
60903
    { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
60904
    & ifmt_mov16_b_imm4_Q_16_dst16_16_8_SB_relative_QI, { 0xd00a00 }
60905
  },
60906
/* cmp.b${Q} #${Imm-8-s4},${Dsp-16-u16}[sb] */
60907
  {
60908
    { 0, 0, 0, 0 },
60909
    { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
60910
    & ifmt_mov16_b_imm4_Q_16_dst16_16_16_SB_relative_QI, { 0xd00e0000 }
60911
  },
60912
/* cmp.b${Q} #${Imm-8-s4},${Dsp-16-s8}[fb] */
60913
  {
60914
    { 0, 0, 0, 0 },
60915
    { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
60916
    & ifmt_mov16_b_imm4_Q_16_dst16_16_8_FB_relative_QI, { 0xd00b00 }
60917
  },
60918
/* cmp.b${Q} #${Imm-8-s4},${Dsp-16-u16} */
60919
  {
60920
    { 0, 0, 0, 0 },
60921
    { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), 0 } },
60922
    & ifmt_mov16_b_imm4_Q_16_dst16_16_16_absolute_QI, { 0xd00f0000 }
60923
  },
60924
/* cmp.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */
60925
  {
60926
    { 0, 0, 0, 0 },
60927
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
60928
    & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0x992e0000 }
60929
  },
60930
/* cmp.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */
60931
  {
60932
    { 0, 0, 0, 0 },
60933
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
60934
    & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0x91ae0000 }
60935
  },
60936
/* cmp.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */
60937
  {
60938
    { 0, 0, 0, 0 },
60939
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
60940
    & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0x912e0000 }
60941
  },
60942
/* cmp.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
60943
  {
60944
    { 0, 0, 0, 0 },
60945
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
60946
    & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0x932e0000 }
60947
  },
60948
/* cmp.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
60949
  {
60950
    { 0, 0, 0, 0 },
60951
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
60952
    & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0x93ae0000 }
60953
  },
60954
/* cmp.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
60955
  {
60956
    { 0, 0, 0, 0 },
60957
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
60958
    & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0x93ee0000 }
60959
  },
60960
/* cmp.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
60961
  {
60962
    { 0, 0, 0, 0 },
60963
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
60964
    & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0x952e0000 }
60965
  },
60966
/* cmp.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
60967
  {
60968
    { 0, 0, 0, 0 },
60969
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
60970
    & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0x95ae0000 }
60971
  },
60972
/* cmp.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */
60973
  {
60974
    { 0, 0, 0, 0 },
60975
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
60976
    & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0x95ee0000 }
60977
  },
60978
/* cmp.w${G} #${Imm-32-HI},${Dsp-16-u16} */
60979
  {
60980
    { 0, 0, 0, 0 },
60981
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } },
60982
    & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0x97ee0000 }
60983
  },
60984
/* cmp.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
60985
  {
60986
    { 0, 0, 0, 0 },
60987
    { { MNEM, OP (G), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
60988
    & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0x972e0000 }
60989
  },
60990
/* cmp.w${G} #${Imm-40-HI},${Dsp-16-u24} */
60991
  {
60992
    { 0, 0, 0, 0 },
60993
    { { MNEM, OP (G), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), 0 } },
60994
    & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0x97ae0000 }
60995
  },
60996
/* cmp.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */
60997
  {
60998
    { 0, 0, 0, 0 },
60999
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
61000
    & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0x982e00 }
61001
  },
61002
/* cmp.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */
61003
  {
61004
    { 0, 0, 0, 0 },
61005
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
61006
    & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0x90ae00 }
61007
  },
61008
/* cmp.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */
61009
  {
61010
    { 0, 0, 0, 0 },
61011
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
61012
    & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0x902e00 }
61013
  },
61014
/* cmp.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
61015
  {
61016
    { 0, 0, 0, 0 },
61017
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
61018
    & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0x922e0000 }
61019
  },
61020
/* cmp.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
61021
  {
61022
    { 0, 0, 0, 0 },
61023
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
61024
    & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0x92ae0000 }
61025
  },
61026
/* cmp.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
61027
  {
61028
    { 0, 0, 0, 0 },
61029
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
61030
    & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0x92ee0000 }
61031
  },
61032
/* cmp.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
61033
  {
61034
    { 0, 0, 0, 0 },
61035
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
61036
    & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0x942e0000 }
61037
  },
61038
/* cmp.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
61039
  {
61040
    { 0, 0, 0, 0 },
61041
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
61042
    & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0x94ae0000 }
61043
  },
61044
/* cmp.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */
61045
  {
61046
    { 0, 0, 0, 0 },
61047
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
61048
    & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0x94ee0000 }
61049
  },
61050
/* cmp.b${G} #${Imm-32-QI},${Dsp-16-u16} */
61051
  {
61052
    { 0, 0, 0, 0 },
61053
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } },
61054
    & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0x96ee0000 }
61055
  },
61056
/* cmp.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
61057
  {
61058
    { 0, 0, 0, 0 },
61059
    { { MNEM, OP (G), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
61060
    & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0x962e0000 }
61061
  },
61062
/* cmp.b${G} #${Imm-40-QI},${Dsp-16-u24} */
61063
  {
61064
    { 0, 0, 0, 0 },
61065
    { { MNEM, OP (G), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), 0 } },
61066
    & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0x96ae0000 }
61067
  },
61068
/* cmp.w${G} #${Imm-16-HI},$Dst16RnHI */
61069
  {
61070
    { 0, 0, 0, 0 },
61071
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST16RNHI), 0 } },
61072
    & ifmt_xor16_w_imm_G_basic_dst16_Rn_direct_HI, { 0x77800000 }
61073
  },
61074
/* cmp.w${G} #${Imm-16-HI},$Dst16AnHI */
61075
  {
61076
    { 0, 0, 0, 0 },
61077
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST16ANHI), 0 } },
61078
    & ifmt_xor16_w_imm_G_basic_dst16_An_direct_HI, { 0x77840000 }
61079
  },
61080
/* cmp.w${G} #${Imm-16-HI},[$Dst16An] */
61081
  {
61082
    { 0, 0, 0, 0 },
61083
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST16AN), ']', 0 } },
61084
    & ifmt_xor16_w_imm_G_basic_dst16_An_indirect_HI, { 0x77860000 }
61085
  },
61086
/* cmp.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
61087
  {
61088
    { 0, 0, 0, 0 },
61089
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
61090
    & ifmt_xor16_w_imm_G_16_8_dst16_16_8_An_relative_HI, { 0x77880000 }
61091
  },
61092
/* cmp.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
61093
  {
61094
    { 0, 0, 0, 0 },
61095
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
61096
    & ifmt_xor16_w_imm_G_16_8_dst16_16_8_SB_relative_HI, { 0x778a0000 }
61097
  },
61098
/* cmp.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
61099
  {
61100
    { 0, 0, 0, 0 },
61101
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
61102
    & ifmt_xor16_w_imm_G_16_8_dst16_16_8_FB_relative_HI, { 0x778b0000 }
61103
  },
61104
/* cmp.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
61105
  {
61106
    { 0, 0, 0, 0 },
61107
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
61108
    & ifmt_xor16_w_imm_G_16_16_dst16_16_16_An_relative_HI, { 0x778c0000 }
61109
  },
61110
/* cmp.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
61111
  {
61112
    { 0, 0, 0, 0 },
61113
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
61114
    & ifmt_xor16_w_imm_G_16_16_dst16_16_16_SB_relative_HI, { 0x778e0000 }
61115
  },
61116
/* cmp.w${G} #${Imm-32-HI},${Dsp-16-u16} */
61117
  {
61118
    { 0, 0, 0, 0 },
61119
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } },
61120
    & ifmt_xor16_w_imm_G_16_16_dst16_16_16_absolute_HI, { 0x778f0000 }
61121
  },
61122
/* cmp.b${G} #${Imm-16-QI},$Dst16RnQI */
61123
  {
61124
    { 0, 0, 0, 0 },
61125
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST16RNQI), 0 } },
61126
    & ifmt_xor16_b_imm_G_basic_dst16_Rn_direct_QI, { 0x768000 }
61127
  },
61128
/* cmp.b${G} #${Imm-16-QI},$Dst16AnQI */
61129
  {
61130
    { 0, 0, 0, 0 },
61131
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST16ANQI), 0 } },
61132
    & ifmt_xor16_b_imm_G_basic_dst16_An_direct_QI, { 0x768400 }
61133
  },
61134
/* cmp.b${G} #${Imm-16-QI},[$Dst16An] */
61135
  {
61136
    { 0, 0, 0, 0 },
61137
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST16AN), ']', 0 } },
61138
    & ifmt_xor16_b_imm_G_basic_dst16_An_indirect_QI, { 0x768600 }
61139
  },
61140
/* cmp.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
61141
  {
61142
    { 0, 0, 0, 0 },
61143
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
61144
    & ifmt_xor16_b_imm_G_16_8_dst16_16_8_An_relative_QI, { 0x76880000 }
61145
  },
61146
/* cmp.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
61147
  {
61148
    { 0, 0, 0, 0 },
61149
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
61150
    & ifmt_xor16_b_imm_G_16_8_dst16_16_8_SB_relative_QI, { 0x768a0000 }
61151
  },
61152
/* cmp.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
61153
  {
61154
    { 0, 0, 0, 0 },
61155
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
61156
    & ifmt_xor16_b_imm_G_16_8_dst16_16_8_FB_relative_QI, { 0x768b0000 }
61157
  },
61158
/* cmp.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
61159
  {
61160
    { 0, 0, 0, 0 },
61161
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
61162
    & ifmt_xor16_b_imm_G_16_16_dst16_16_16_An_relative_QI, { 0x768c0000 }
61163
  },
61164
/* cmp.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
61165
  {
61166
    { 0, 0, 0, 0 },
61167
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
61168
    & ifmt_xor16_b_imm_G_16_16_dst16_16_16_SB_relative_QI, { 0x768e0000 }
61169
  },
61170
/* cmp.b${G} #${Imm-32-QI},${Dsp-16-u16} */
61171
  {
61172
    { 0, 0, 0, 0 },
61173
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } },
61174
    & ifmt_xor16_b_imm_G_16_16_dst16_16_16_absolute_QI, { 0x768f0000 }
61175
  },
61176
/* cmp.l${G} #${Imm-16-SI},$Dst32RnUnprefixedSI */
61177
  {
61178
    { 0, 0, 0, 0 },
61179
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_SI), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
61180
    & ifmt_mov32_l_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_SI, { 0xa8310000 }
61181
  },
61182
/* cmp.l${G} #${Imm-16-SI},$Dst32AnUnprefixedSI */
61183
  {
61184
    { 0, 0, 0, 0 },
61185
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_SI), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
61186
    & ifmt_mov32_l_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_SI, { 0xa0b10000 }
61187
  },
61188
/* cmp.l${G} #${Imm-16-SI},[$Dst32AnUnprefixed] */
61189
  {
61190
    { 0, 0, 0, 0 },
61191
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_SI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
61192
    & ifmt_mov32_l_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_SI, { 0xa0310000 }
61193
  },
61194
/* cmp.l${G} #${Imm-24-SI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
61195
  {
61196
    { 0, 0, 0, 0 },
61197
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_SI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
61198
    & ifmt_mov32_l_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_SI, { 0xa2310000 }
61199
  },
61200
/* cmp.l${G} #${Imm-24-SI},${Dsp-16-u8}[sb] */
61201
  {
61202
    { 0, 0, 0, 0 },
61203
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_SI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
61204
    & ifmt_mov32_l_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_SI, { 0xa2b10000 }
61205
  },
61206
/* cmp.l${G} #${Imm-24-SI},${Dsp-16-s8}[fb] */
61207
  {
61208
    { 0, 0, 0, 0 },
61209
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_SI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
61210
    & ifmt_mov32_l_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_SI, { 0xa2f10000 }
61211
  },
61212
/* cmp.l${G} #${Imm-32-SI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
61213
  {
61214
    { 0, 0, 0, 0 },
61215
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_SI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
61216
    & ifmt_mov32_l_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_SI, { 0xa4310000 }
61217
  },
61218
/* cmp.l${G} #${Imm-32-SI},${Dsp-16-u16}[sb] */
61219
  {
61220
    { 0, 0, 0, 0 },
61221
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_SI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
61222
    & ifmt_mov32_l_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_SI, { 0xa4b10000 }
61223
  },
61224
/* cmp.l${G} #${Imm-32-SI},${Dsp-16-s16}[fb] */
61225
  {
61226
    { 0, 0, 0, 0 },
61227
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_SI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
61228
    & ifmt_mov32_l_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_SI, { 0xa4f10000 }
61229
  },
61230
/* cmp.l${G} #${Imm-32-SI},${Dsp-16-u16} */
61231
  {
61232
    { 0, 0, 0, 0 },
61233
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_SI), ',', OP (DSP_16_U16), 0 } },
61234
    & ifmt_mov32_l_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_SI, { 0xa6f10000 }
61235
  },
61236
/* cmp.l${G} #${Imm-40-SI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
61237
  {
61238
    { 0, 0, 0, 0 },
61239
    { { MNEM, OP (G), ' ', '#', OP (IMM_40_SI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
61240
    & ifmt_mov32_l_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_SI, { 0xa6310000 }
61241
  },
61242
/* cmp.l${G} #${Imm-40-SI},${Dsp-16-u24} */
61243
  {
61244
    { 0, 0, 0, 0 },
61245
    { { MNEM, OP (G), ' ', '#', OP (IMM_40_SI), ',', OP (DSP_16_U24), 0 } },
61246
    & ifmt_mov32_l_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_SI, { 0xa6b10000 }
61247
  },
61248
/* clip.w #${Imm-24-HI},#${Imm-40-HI},$Dst32RnPrefixedHI */
61249
  {
61250
    { 0, 0, 0, 0 },
61251
    { { MNEM, ' ', '#', OP (IMM_24_HI), ',', '#', OP (IMM_40_HI), ',', OP (DST32RNPREFIXEDHI), 0 } },
61252
    & ifmt_clip32_w_Imm_24_HI_Imm_40_HI_basic_Prefixed_dst32_Rn_direct_Prefixed_HI, { 0x1893e00 }
61253
  },
61254
/* clip.w #${Imm-24-HI},#${Imm-40-HI},$Dst32AnPrefixedHI */
61255
  {
61256
    { 0, 0, 0, 0 },
61257
    { { MNEM, ' ', '#', OP (IMM_24_HI), ',', '#', OP (IMM_40_HI), ',', OP (DST32ANPREFIXEDHI), 0 } },
61258
    & ifmt_clip32_w_Imm_24_HI_Imm_40_HI_basic_Prefixed_dst32_An_direct_Prefixed_HI, { 0x181be00 }
61259
  },
61260
/* clip.w #${Imm-24-HI},#${Imm-40-HI},[$Dst32AnPrefixed] */
61261
  {
61262
    { 0, 0, 0, 0 },
61263
    { { MNEM, ' ', '#', OP (IMM_24_HI), ',', '#', OP (IMM_40_HI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
61264
    & ifmt_clip32_w_Imm_24_HI_Imm_40_HI_basic_Prefixed_dst32_An_indirect_Prefixed_HI, { 0x1813e00 }
61265
  },
61266
/* clip.w #${Imm-32-HI},#${Imm-48-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */
61267
  {
61268
    { 0, 0, 0, 0 },
61269
    { { MNEM, ' ', '#', OP (IMM_32_HI), ',', '#', OP (IMM_48_HI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
61270
    & ifmt_clip32_w_Imm_32_HI_Imm_48_HI_24_8_Prefixed_dst32_24_8_An_relative_Prefixed_HI, { 0x1833e00 }
61271
  },
61272
/* clip.w #${Imm-32-HI},#${Imm-48-HI},${Dsp-24-u8}[sb] */
61273
  {
61274
    { 0, 0, 0, 0 },
61275
    { { MNEM, ' ', '#', OP (IMM_32_HI), ',', '#', OP (IMM_48_HI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
61276
    & ifmt_clip32_w_Imm_32_HI_Imm_48_HI_24_8_Prefixed_dst32_24_8_SB_relative_Prefixed_HI, { 0x183be00 }
61277
  },
61278
/* clip.w #${Imm-32-HI},#${Imm-48-HI},${Dsp-24-s8}[fb] */
61279
  {
61280
    { 0, 0, 0, 0 },
61281
    { { MNEM, ' ', '#', OP (IMM_32_HI), ',', '#', OP (IMM_48_HI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
61282
    & ifmt_clip32_w_Imm_32_HI_Imm_48_HI_24_8_Prefixed_dst32_24_8_FB_relative_Prefixed_HI, { 0x183fe00 }
61283
  },
61284
/* clip.w #${Imm-40-HI},#${Imm-56-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */
61285
  {
61286
    { 0, 0, 0, 0 },
61287
    { { MNEM, ' ', '#', OP (IMM_40_HI), ',', '#', OP (IMM_56_HI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
61288
    & ifmt_clip32_w_Imm_40_HI_Imm_56_HI_24_16_Prefixed_dst32_24_16_An_relative_Prefixed_HI, { 0x1853e00 }
61289
  },
61290
/* clip.w #${Imm-40-HI},#${Imm-56-HI},${Dsp-24-u16}[sb] */
61291
  {
61292
    { 0, 0, 0, 0 },
61293
    { { MNEM, ' ', '#', OP (IMM_40_HI), ',', '#', OP (IMM_56_HI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
61294
    & ifmt_clip32_w_Imm_40_HI_Imm_56_HI_24_16_Prefixed_dst32_24_16_SB_relative_Prefixed_HI, { 0x185be00 }
61295
  },
61296
/* clip.w #${Imm-40-HI},#${Imm-56-HI},${Dsp-24-s16}[fb] */
61297
  {
61298
    { 0, 0, 0, 0 },
61299
    { { MNEM, ' ', '#', OP (IMM_40_HI), ',', '#', OP (IMM_56_HI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
61300
    & ifmt_clip32_w_Imm_40_HI_Imm_56_HI_24_16_Prefixed_dst32_24_16_FB_relative_Prefixed_HI, { 0x185fe00 }
61301
  },
61302
/* clip.w #${Imm-40-HI},#${Imm-56-HI},${Dsp-24-u16} */
61303
  {
61304
    { 0, 0, 0, 0 },
61305
    { { MNEM, ' ', '#', OP (IMM_40_HI), ',', '#', OP (IMM_56_HI), ',', OP (DSP_24_U16), 0 } },
61306
    & ifmt_clip32_w_Imm_40_HI_Imm_56_HI_24_16_Prefixed_dst32_24_16_absolute_Prefixed_HI, { 0x187fe00 }
61307
  },
61308
/* clip.w #${Imm-48-HI},#${Imm-64-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */
61309
  {
61310
    { 0, 0, 0, 0 },
61311
    { { MNEM, ' ', '#', OP (IMM_48_HI), ',', '#', OP (IMM_64_HI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
61312
    & ifmt_clip32_w_Imm_48_HI_Imm_64_HI_24_24_Prefixed_dst32_24_24_An_relative_Prefixed_HI, { 0x1873e00 }
61313
  },
61314
/* clip.w #${Imm-48-HI},#${Imm-64-HI},${Dsp-24-u24} */
61315
  {
61316
    { 0, 0, 0, 0 },
61317
    { { MNEM, ' ', '#', OP (IMM_48_HI), ',', '#', OP (IMM_64_HI), ',', OP (DSP_24_U24), 0 } },
61318
    & ifmt_clip32_w_Imm_48_HI_Imm_64_HI_24_24_Prefixed_dst32_24_24_absolute_Prefixed_HI, { 0x187be00 }
61319
  },
61320
/* clip.b #${Imm-24-QI},#${Imm-32-QI},$Dst32RnPrefixedQI */
61321
  {
61322
    { 0, 0, 0, 0 },
61323
    { { MNEM, ' ', '#', OP (IMM_24_QI), ',', '#', OP (IMM_32_QI), ',', OP (DST32RNPREFIXEDQI), 0 } },
61324
    & ifmt_clip32_b_Imm_24_QI_Imm_32_QI_basic_Prefixed_dst32_Rn_direct_Prefixed_QI, { 0x1883e00 }
61325
  },
61326
/* clip.b #${Imm-24-QI},#${Imm-32-QI},$Dst32AnPrefixedQI */
61327
  {
61328
    { 0, 0, 0, 0 },
61329
    { { MNEM, ' ', '#', OP (IMM_24_QI), ',', '#', OP (IMM_32_QI), ',', OP (DST32ANPREFIXEDQI), 0 } },
61330
    & ifmt_clip32_b_Imm_24_QI_Imm_32_QI_basic_Prefixed_dst32_An_direct_Prefixed_QI, { 0x180be00 }
61331
  },
61332
/* clip.b #${Imm-24-QI},#${Imm-32-QI},[$Dst32AnPrefixed] */
61333
  {
61334
    { 0, 0, 0, 0 },
61335
    { { MNEM, ' ', '#', OP (IMM_24_QI), ',', '#', OP (IMM_32_QI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
61336
    & ifmt_clip32_b_Imm_24_QI_Imm_32_QI_basic_Prefixed_dst32_An_indirect_Prefixed_QI, { 0x1803e00 }
61337
  },
61338
/* clip.b #${Imm-32-QI},#${Imm-40-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */
61339
  {
61340
    { 0, 0, 0, 0 },
61341
    { { MNEM, ' ', '#', OP (IMM_32_QI), ',', '#', OP (IMM_40_QI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
61342
    & ifmt_clip32_b_Imm_32_QI_Imm_40_QI_24_8_Prefixed_dst32_24_8_An_relative_Prefixed_QI, { 0x1823e00 }
61343
  },
61344
/* clip.b #${Imm-32-QI},#${Imm-40-QI},${Dsp-24-u8}[sb] */
61345
  {
61346
    { 0, 0, 0, 0 },
61347
    { { MNEM, ' ', '#', OP (IMM_32_QI), ',', '#', OP (IMM_40_QI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
61348
    & ifmt_clip32_b_Imm_32_QI_Imm_40_QI_24_8_Prefixed_dst32_24_8_SB_relative_Prefixed_QI, { 0x182be00 }
61349
  },
61350
/* clip.b #${Imm-32-QI},#${Imm-40-QI},${Dsp-24-s8}[fb] */
61351
  {
61352
    { 0, 0, 0, 0 },
61353
    { { MNEM, ' ', '#', OP (IMM_32_QI), ',', '#', OP (IMM_40_QI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
61354
    & ifmt_clip32_b_Imm_32_QI_Imm_40_QI_24_8_Prefixed_dst32_24_8_FB_relative_Prefixed_QI, { 0x182fe00 }
61355
  },
61356
/* clip.b #${Imm-40-QI},#${Imm-48-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */
61357
  {
61358
    { 0, 0, 0, 0 },
61359
    { { MNEM, ' ', '#', OP (IMM_40_QI), ',', '#', OP (IMM_48_QI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
61360
    & ifmt_clip32_b_Imm_40_QI_Imm_48_QI_24_16_Prefixed_dst32_24_16_An_relative_Prefixed_QI, { 0x1843e00 }
61361
  },
61362
/* clip.b #${Imm-40-QI},#${Imm-48-QI},${Dsp-24-u16}[sb] */
61363
  {
61364
    { 0, 0, 0, 0 },
61365
    { { MNEM, ' ', '#', OP (IMM_40_QI), ',', '#', OP (IMM_48_QI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
61366
    & ifmt_clip32_b_Imm_40_QI_Imm_48_QI_24_16_Prefixed_dst32_24_16_SB_relative_Prefixed_QI, { 0x184be00 }
61367
  },
61368
/* clip.b #${Imm-40-QI},#${Imm-48-QI},${Dsp-24-s16}[fb] */
61369
  {
61370
    { 0, 0, 0, 0 },
61371
    { { MNEM, ' ', '#', OP (IMM_40_QI), ',', '#', OP (IMM_48_QI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
61372
    & ifmt_clip32_b_Imm_40_QI_Imm_48_QI_24_16_Prefixed_dst32_24_16_FB_relative_Prefixed_QI, { 0x184fe00 }
61373
  },
61374
/* clip.b #${Imm-40-QI},#${Imm-48-QI},${Dsp-24-u16} */
61375
  {
61376
    { 0, 0, 0, 0 },
61377
    { { MNEM, ' ', '#', OP (IMM_40_QI), ',', '#', OP (IMM_48_QI), ',', OP (DSP_24_U16), 0 } },
61378
    & ifmt_clip32_b_Imm_40_QI_Imm_48_QI_24_16_Prefixed_dst32_24_16_absolute_Prefixed_QI, { 0x186fe00 }
61379
  },
61380
/* clip.b #${Imm-48-QI},#${Imm-56-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */
61381
  {
61382
    { 0, 0, 0, 0 },
61383
    { { MNEM, ' ', '#', OP (IMM_48_QI), ',', '#', OP (IMM_56_QI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
61384
    & ifmt_clip32_b_Imm_48_QI_Imm_56_QI_24_24_Prefixed_dst32_24_24_An_relative_Prefixed_QI, { 0x1863e00 }
61385
  },
61386
/* clip.b #${Imm-48-QI},#${Imm-56-QI},${Dsp-24-u24} */
61387
  {
61388
    { 0, 0, 0, 0 },
61389
    { { MNEM, ' ', '#', OP (IMM_48_QI), ',', '#', OP (IMM_56_QI), ',', OP (DSP_24_U24), 0 } },
61390
    & ifmt_clip32_b_Imm_48_QI_Imm_56_QI_24_24_Prefixed_dst32_24_24_absolute_Prefixed_QI, { 0x186be00 }
61391
  },
61392
/* bxor${X} $Bitno32Prefixed,$Bit32RnPrefixed */
61393
  {
61394
    { 0, 0, 0, 0 },
61395
    { { MNEM, OP (X), ' ', OP (BITNO32PREFIXED), ',', OP (BIT32RNPREFIXED), 0 } },
61396
    & ifmt_bxor32_X_bit32_24_Prefixed_bit32_Rn_direct_Prefixed, { 0x1d828 }
61397
  },
61398
/* bxor${X} $Bitno32Prefixed,$Bit32AnPrefixed */
61399
  {
61400
    { 0, 0, 0, 0 },
61401
    { { MNEM, OP (X), ' ', OP (BITNO32PREFIXED), ',', OP (BIT32ANPREFIXED), 0 } },
61402
    & ifmt_bxor32_X_bit32_24_Prefixed_bit32_An_direct_Prefixed, { 0x1d0a8 }
61403
  },
61404
/* bxor${X} $Bitno32Prefixed,[$Bit32AnPrefixed] */
61405
  {
61406
    { 0, 0, 0, 0 },
61407
    { { MNEM, OP (X), ' ', OP (BITNO32PREFIXED), ',', '[', OP (BIT32ANPREFIXED), ']', 0 } },
61408
    & ifmt_bxor32_X_bit32_24_Prefixed_bit32_An_indirect_Prefixed, { 0x1d028 }
61409
  },
61410
/* bxor${X} ${BitBase32-24-u11-Prefixed}[$Bit32AnPrefixed] */
61411
  {
61412
    { 0, 0, 0, 0 },
61413
    { { MNEM, OP (X), ' ', OP (BITBASE32_24_U11_PREFIXED), '[', OP (BIT32ANPREFIXED), ']', 0 } },
61414
    & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_An_relative_Prefixed, { 0x1d22800 }
61415
  },
61416
/* bxor${X} ${BitBase32-24-u19-Prefixed}[$Bit32AnPrefixed] */
61417
  {
61418
    { 0, 0, 0, 0 },
61419
    { { MNEM, OP (X), ' ', OP (BITBASE32_24_U19_PREFIXED), '[', OP (BIT32ANPREFIXED), ']', 0 } },
61420
    & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_An_relative_Prefixed, { 0x1d42800 }
61421
  },
61422
/* bxor${X} ${BitBase32-24-u27-Prefixed}[$Bit32AnPrefixed] */
61423
  {
61424
    { 0, 0, 0, 0 },
61425
    { { MNEM, OP (X), ' ', OP (BITBASE32_24_U27_PREFIXED), '[', OP (BIT32ANPREFIXED), ']', 0 } },
61426
    & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_27_An_relative_Prefixed, { 0x1d62800 }
61427
  },
61428
/* bxor${X} ${BitBase32-24-u11-Prefixed}[sb] */
61429
  {
61430
    { 0, 0, 0, 0 },
61431
    { { MNEM, OP (X), ' ', OP (BITBASE32_24_U11_PREFIXED), '[', 's', 'b', ']', 0 } },
61432
    & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_SB_relative_Prefixed, { 0x1d2a800 }
61433
  },
61434
/* bxor${X} ${BitBase32-24-u19-Prefixed}[sb] */
61435
  {
61436
    { 0, 0, 0, 0 },
61437
    { { MNEM, OP (X), ' ', OP (BITBASE32_24_U19_PREFIXED), '[', 's', 'b', ']', 0 } },
61438
    & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_SB_relative_Prefixed, { 0x1d4a800 }
61439
  },
61440
/* bxor${X} ${BitBase32-24-s11-Prefixed}[fb] */
61441
  {
61442
    { 0, 0, 0, 0 },
61443
    { { MNEM, OP (X), ' ', OP (BITBASE32_24_S11_PREFIXED), '[', 'f', 'b', ']', 0 } },
61444
    & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_FB_relative_Prefixed, { 0x1d2e800 }
61445
  },
61446
/* bxor${X} ${BitBase32-24-s19-Prefixed}[fb] */
61447
  {
61448
    { 0, 0, 0, 0 },
61449
    { { MNEM, OP (X), ' ', OP (BITBASE32_24_S19_PREFIXED), '[', 'f', 'b', ']', 0 } },
61450
    & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_FB_relative_Prefixed, { 0x1d4e800 }
61451
  },
61452
/* bxor${X} ${BitBase32-24-u19-Prefixed} */
61453
  {
61454
    { 0, 0, 0, 0 },
61455
    { { MNEM, OP (X), ' ', OP (BITBASE32_24_U19_PREFIXED), 0 } },
61456
    & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_absolute_Prefixed, { 0x1d6e800 }
61457
  },
61458
/* bxor${X} ${BitBase32-24-u27-Prefixed} */
61459
  {
61460
    { 0, 0, 0, 0 },
61461
    { { MNEM, OP (X), ' ', OP (BITBASE32_24_U27_PREFIXED), 0 } },
61462
    & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_27_absolute_Prefixed, { 0x1d6a800 }
61463
  },
61464
/* bxor${X} $Bitno16R,$Bit16Rn */
61465
  {
61466
    { 0, 0, 0, 0 },
61467
    { { MNEM, OP (X), ' ', OP (BITNO16R), ',', OP (BIT16RN), 0 } },
61468
    & ifmt_bxor16_X_bit16_16_bit16_Rn_direct, { 0x7ec000 }
61469
  },
61470
/* bxor${X} $Bitno16R,$Bit16An */
61471
  {
61472
    { 0, 0, 0, 0 },
61473
    { { MNEM, OP (X), ' ', OP (BITNO16R), ',', OP (BIT16AN), 0 } },
61474
    & ifmt_bxor16_X_bit16_16_bit16_An_direct, { 0x7ec400 }
61475
  },
61476
/* bxor${X} [$Bit16An] */
61477
  {
61478
    { 0, 0, 0, 0 },
61479
    { { MNEM, OP (X), ' ', '[', OP (BIT16AN), ']', 0 } },
61480
    & ifmt_bxor16_X_bit16_16_bit16_An_indirect, { 0x7ec6 }
61481
  },
61482
/* bxor${X} ${Dsp-16-u8}[$Bit16An] */
61483
  {
61484
    { 0, 0, 0, 0 },
61485
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (BIT16AN), ']', 0 } },
61486
    & ifmt_bxor16_X_bit16_16_bit16_16_8_An_relative, { 0x7ec800 }
61487
  },
61488
/* bxor${X} ${Dsp-16-u16}[$Bit16An] */
61489
  {
61490
    { 0, 0, 0, 0 },
61491
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (BIT16AN), ']', 0 } },
61492
    & ifmt_bxor16_X_bit16_16_bit16_16_16_An_relative, { 0x7ecc0000 }
61493
  },
61494
/* bxor${X} ${BitBase16-16-u8}[sb] */
61495
  {
61496
    { 0, 0, 0, 0 },
61497
    { { MNEM, OP (X), ' ', OP (BITBASE16_16_U8), '[', 's', 'b', ']', 0 } },
61498
    & ifmt_bxor16_X_bit16_16_bit16_16_8_SB_relative, { 0x7eca00 }
61499
  },
61500
/* bxor${X} ${BitBase16-16-u16}[sb] */
61501
  {
61502
    { 0, 0, 0, 0 },
61503
    { { MNEM, OP (X), ' ', OP (BITBASE16_16_U16), '[', 's', 'b', ']', 0 } },
61504
    & ifmt_bxor16_X_bit16_16_bit16_16_16_SB_relative, { 0x7ece0000 }
61505
  },
61506
/* bxor${X} ${BitBase16-16-s8}[fb] */
61507
  {
61508
    { 0, 0, 0, 0 },
61509
    { { MNEM, OP (X), ' ', OP (BITBASE16_16_S8), '[', 'f', 'b', ']', 0 } },
61510
    & ifmt_bxor16_X_bit16_16_bit16_16_8_FB_relative, { 0x7ecb00 }
61511
  },
61512
/* bxor${X} ${BitBase16-16-u16} */
61513
  {
61514
    { 0, 0, 0, 0 },
61515
    { { MNEM, OP (X), ' ', OP (BITBASE16_16_U16), 0 } },
61516
    & ifmt_bxor16_X_bit16_16_bit16_16_16_absolute, { 0x7ecf0000 }
61517
  },
61518
/* btsts${X} $Bitno32Unprefixed,$Bit32RnUnprefixed */
61519
  {
61520
    { 0, 0, 0, 0 },
61521
    { { MNEM, OP (X), ' ', OP (BITNO32UNPREFIXED), ',', OP (BIT32RNUNPREFIXED), 0 } },
61522
    & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_Rn_direct_Unprefixed, { 0xd828 }
61523
  },
61524
/* btsts${X} $Bitno32Unprefixed,$Bit32AnUnprefixed */
61525
  {
61526
    { 0, 0, 0, 0 },
61527
    { { MNEM, OP (X), ' ', OP (BITNO32UNPREFIXED), ',', OP (BIT32ANUNPREFIXED), 0 } },
61528
    & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_An_direct_Unprefixed, { 0xd0a8 }
61529
  },
61530
/* btsts${X} $Bitno32Unprefixed,[$Bit32AnUnprefixed] */
61531
  {
61532
    { 0, 0, 0, 0 },
61533
    { { MNEM, OP (X), ' ', OP (BITNO32UNPREFIXED), ',', '[', OP (BIT32ANUNPREFIXED), ']', 0 } },
61534
    & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_An_indirect_Unprefixed, { 0xd028 }
61535
  },
61536
/* btsts${X} ${BitBase32-16-u11-Unprefixed}[$Bit32AnUnprefixed] */
61537
  {
61538
    { 0, 0, 0, 0 },
61539
    { { MNEM, OP (X), ' ', OP (BITBASE32_16_U11_UNPREFIXED), '[', OP (BIT32ANUNPREFIXED), ']', 0 } },
61540
    & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_11_An_relative_Unprefixed, { 0xd22800 }
61541
  },
61542
/* btsts${X} ${BitBase32-16-u19-Unprefixed}[$Bit32AnUnprefixed] */
61543
  {
61544
    { 0, 0, 0, 0 },
61545
    { { MNEM, OP (X), ' ', OP (BITBASE32_16_U19_UNPREFIXED), '[', OP (BIT32ANUNPREFIXED), ']', 0 } },
61546
    & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_An_relative_Unprefixed, { 0xd4280000 }
61547
  },
61548
/* btsts${X} ${BitBase32-16-u27-Unprefixed}[$Bit32AnUnprefixed] */
61549
  {
61550
    { 0, 0, 0, 0 },
61551
    { { MNEM, OP (X), ' ', OP (BITBASE32_16_U27_UNPREFIXED), '[', OP (BIT32ANUNPREFIXED), ']', 0 } },
61552
    & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_27_An_relative_Unprefixed, { 0xd6280000 }
61553
  },
61554
/* btsts${X} ${BitBase32-16-u11-Unprefixed}[sb] */
61555
  {
61556
    { 0, 0, 0, 0 },
61557
    { { MNEM, OP (X), ' ', OP (BITBASE32_16_U11_UNPREFIXED), '[', 's', 'b', ']', 0 } },
61558
    & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_11_SB_relative_Unprefixed, { 0xd2a800 }
61559
  },
61560
/* btsts${X} ${BitBase32-16-u19-Unprefixed}[sb] */
61561
  {
61562
    { 0, 0, 0, 0 },
61563
    { { MNEM, OP (X), ' ', OP (BITBASE32_16_U19_UNPREFIXED), '[', 's', 'b', ']', 0 } },
61564
    & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_SB_relative_Unprefixed, { 0xd4a80000 }
61565
  },
61566
/* btsts${X} ${BitBase32-16-s11-Unprefixed}[fb] */
61567
  {
61568
    { 0, 0, 0, 0 },
61569
    { { MNEM, OP (X), ' ', OP (BITBASE32_16_S11_UNPREFIXED), '[', 'f', 'b', ']', 0 } },
61570
    & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_11_FB_relative_Unprefixed, { 0xd2e800 }
61571
  },
61572
/* btsts${X} ${BitBase32-16-s19-Unprefixed}[fb] */
61573
  {
61574
    { 0, 0, 0, 0 },
61575
    { { MNEM, OP (X), ' ', OP (BITBASE32_16_S19_UNPREFIXED), '[', 'f', 'b', ']', 0 } },
61576
    & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_FB_relative_Unprefixed, { 0xd4e80000 }
61577
  },
61578
/* btsts${X} ${BitBase32-16-u19-Unprefixed} */
61579
  {
61580
    { 0, 0, 0, 0 },
61581
    { { MNEM, OP (X), ' ', OP (BITBASE32_16_U19_UNPREFIXED), 0 } },
61582
    & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_absolute_Unprefixed, { 0xd6e80000 }
61583
  },
61584
/* btsts${X} ${BitBase32-16-u27-Unprefixed} */
61585
  {
61586
    { 0, 0, 0, 0 },
61587
    { { MNEM, OP (X), ' ', OP (BITBASE32_16_U27_UNPREFIXED), 0 } },
61588
    & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_27_absolute_Unprefixed, { 0xd6a80000 }
61589
  },
61590
/* btsts${X} $Bitno16R,$Bit16Rn */
61591
  {
61592
    { 0, 0, 0, 0 },
61593
    { { MNEM, OP (X), ' ', OP (BITNO16R), ',', OP (BIT16RN), 0 } },
61594
    & ifmt_bxor16_X_bit16_16_bit16_Rn_direct, { 0x7e1000 }
61595
  },
61596
/* btsts${X} $Bitno16R,$Bit16An */
61597
  {
61598
    { 0, 0, 0, 0 },
61599
    { { MNEM, OP (X), ' ', OP (BITNO16R), ',', OP (BIT16AN), 0 } },
61600
    & ifmt_bxor16_X_bit16_16_bit16_An_direct, { 0x7e1400 }
61601
  },
61602
/* btsts${X} [$Bit16An] */
61603
  {
61604
    { 0, 0, 0, 0 },
61605
    { { MNEM, OP (X), ' ', '[', OP (BIT16AN), ']', 0 } },
61606
    & ifmt_bxor16_X_bit16_16_bit16_An_indirect, { 0x7e16 }
61607
  },
61608
/* btsts${X} ${Dsp-16-u8}[$Bit16An] */
61609
  {
61610
    { 0, 0, 0, 0 },
61611
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (BIT16AN), ']', 0 } },
61612
    & ifmt_bxor16_X_bit16_16_bit16_16_8_An_relative, { 0x7e1800 }
61613
  },
61614
/* btsts${X} ${Dsp-16-u16}[$Bit16An] */
61615
  {
61616
    { 0, 0, 0, 0 },
61617
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (BIT16AN), ']', 0 } },
61618
    & ifmt_bxor16_X_bit16_16_bit16_16_16_An_relative, { 0x7e1c0000 }
61619
  },
61620
/* btsts${X} ${BitBase16-16-u8}[sb] */
61621
  {
61622
    { 0, 0, 0, 0 },
61623
    { { MNEM, OP (X), ' ', OP (BITBASE16_16_U8), '[', 's', 'b', ']', 0 } },
61624
    & ifmt_bxor16_X_bit16_16_bit16_16_8_SB_relative, { 0x7e1a00 }
61625
  },
61626
/* btsts${X} ${BitBase16-16-u16}[sb] */
61627
  {
61628
    { 0, 0, 0, 0 },
61629
    { { MNEM, OP (X), ' ', OP (BITBASE16_16_U16), '[', 's', 'b', ']', 0 } },
61630
    & ifmt_bxor16_X_bit16_16_bit16_16_16_SB_relative, { 0x7e1e0000 }
61631
  },
61632
/* btsts${X} ${BitBase16-16-s8}[fb] */
61633
  {
61634
    { 0, 0, 0, 0 },
61635
    { { MNEM, OP (X), ' ', OP (BITBASE16_16_S8), '[', 'f', 'b', ']', 0 } },
61636
    & ifmt_bxor16_X_bit16_16_bit16_16_8_FB_relative, { 0x7e1b00 }
61637
  },
61638
/* btsts${X} ${BitBase16-16-u16} */
61639
  {
61640
    { 0, 0, 0, 0 },
61641
    { { MNEM, OP (X), ' ', OP (BITBASE16_16_U16), 0 } },
61642
    & ifmt_bxor16_X_bit16_16_bit16_16_16_absolute, { 0x7e1f0000 }
61643
  },
61644
/* btstc${X} $Bitno32Unprefixed,$Bit32RnUnprefixed */
61645
  {
61646
    { 0, 0, 0, 0 },
61647
    { { MNEM, OP (X), ' ', OP (BITNO32UNPREFIXED), ',', OP (BIT32RNUNPREFIXED), 0 } },
61648
    & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_Rn_direct_Unprefixed, { 0xd820 }
61649
  },
61650
/* btstc${X} $Bitno32Unprefixed,$Bit32AnUnprefixed */
61651
  {
61652
    { 0, 0, 0, 0 },
61653
    { { MNEM, OP (X), ' ', OP (BITNO32UNPREFIXED), ',', OP (BIT32ANUNPREFIXED), 0 } },
61654
    & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_An_direct_Unprefixed, { 0xd0a0 }
61655
  },
61656
/* btstc${X} $Bitno32Unprefixed,[$Bit32AnUnprefixed] */
61657
  {
61658
    { 0, 0, 0, 0 },
61659
    { { MNEM, OP (X), ' ', OP (BITNO32UNPREFIXED), ',', '[', OP (BIT32ANUNPREFIXED), ']', 0 } },
61660
    & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_An_indirect_Unprefixed, { 0xd020 }
61661
  },
61662
/* btstc${X} ${BitBase32-16-u11-Unprefixed}[$Bit32AnUnprefixed] */
61663
  {
61664
    { 0, 0, 0, 0 },
61665
    { { MNEM, OP (X), ' ', OP (BITBASE32_16_U11_UNPREFIXED), '[', OP (BIT32ANUNPREFIXED), ']', 0 } },
61666
    & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_11_An_relative_Unprefixed, { 0xd22000 }
61667
  },
61668
/* btstc${X} ${BitBase32-16-u19-Unprefixed}[$Bit32AnUnprefixed] */
61669
  {
61670
    { 0, 0, 0, 0 },
61671
    { { MNEM, OP (X), ' ', OP (BITBASE32_16_U19_UNPREFIXED), '[', OP (BIT32ANUNPREFIXED), ']', 0 } },
61672
    & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_An_relative_Unprefixed, { 0xd4200000 }
61673
  },
61674
/* btstc${X} ${BitBase32-16-u27-Unprefixed}[$Bit32AnUnprefixed] */
61675
  {
61676
    { 0, 0, 0, 0 },
61677
    { { MNEM, OP (X), ' ', OP (BITBASE32_16_U27_UNPREFIXED), '[', OP (BIT32ANUNPREFIXED), ']', 0 } },
61678
    & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_27_An_relative_Unprefixed, { 0xd6200000 }
61679
  },
61680
/* btstc${X} ${BitBase32-16-u11-Unprefixed}[sb] */
61681
  {
61682
    { 0, 0, 0, 0 },
61683
    { { MNEM, OP (X), ' ', OP (BITBASE32_16_U11_UNPREFIXED), '[', 's', 'b', ']', 0 } },
61684
    & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_11_SB_relative_Unprefixed, { 0xd2a000 }
61685
  },
61686
/* btstc${X} ${BitBase32-16-u19-Unprefixed}[sb] */
61687
  {
61688
    { 0, 0, 0, 0 },
61689
    { { MNEM, OP (X), ' ', OP (BITBASE32_16_U19_UNPREFIXED), '[', 's', 'b', ']', 0 } },
61690
    & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_SB_relative_Unprefixed, { 0xd4a00000 }
61691
  },
61692
/* btstc${X} ${BitBase32-16-s11-Unprefixed}[fb] */
61693
  {
61694
    { 0, 0, 0, 0 },
61695
    { { MNEM, OP (X), ' ', OP (BITBASE32_16_S11_UNPREFIXED), '[', 'f', 'b', ']', 0 } },
61696
    & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_11_FB_relative_Unprefixed, { 0xd2e000 }
61697
  },
61698
/* btstc${X} ${BitBase32-16-s19-Unprefixed}[fb] */
61699
  {
61700
    { 0, 0, 0, 0 },
61701
    { { MNEM, OP (X), ' ', OP (BITBASE32_16_S19_UNPREFIXED), '[', 'f', 'b', ']', 0 } },
61702
    & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_FB_relative_Unprefixed, { 0xd4e00000 }
61703
  },
61704
/* btstc${X} ${BitBase32-16-u19-Unprefixed} */
61705
  {
61706
    { 0, 0, 0, 0 },
61707
    { { MNEM, OP (X), ' ', OP (BITBASE32_16_U19_UNPREFIXED), 0 } },
61708
    & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_absolute_Unprefixed, { 0xd6e00000 }
61709
  },
61710
/* btstc${X} ${BitBase32-16-u27-Unprefixed} */
61711
  {
61712
    { 0, 0, 0, 0 },
61713
    { { MNEM, OP (X), ' ', OP (BITBASE32_16_U27_UNPREFIXED), 0 } },
61714
    & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_27_absolute_Unprefixed, { 0xd6a00000 }
61715
  },
61716
/* btstc${X} $Bitno16R,$Bit16Rn */
61717
  {
61718
    { 0, 0, 0, 0 },
61719
    { { MNEM, OP (X), ' ', OP (BITNO16R), ',', OP (BIT16RN), 0 } },
61720
    & ifmt_bxor16_X_bit16_16_bit16_Rn_direct, { 0x7e0000 }
61721
  },
61722
/* btstc${X} $Bitno16R,$Bit16An */
61723
  {
61724
    { 0, 0, 0, 0 },
61725
    { { MNEM, OP (X), ' ', OP (BITNO16R), ',', OP (BIT16AN), 0 } },
61726
    & ifmt_bxor16_X_bit16_16_bit16_An_direct, { 0x7e0400 }
61727
  },
61728
/* btstc${X} [$Bit16An] */
61729
  {
61730
    { 0, 0, 0, 0 },
61731
    { { MNEM, OP (X), ' ', '[', OP (BIT16AN), ']', 0 } },
61732
    & ifmt_bxor16_X_bit16_16_bit16_An_indirect, { 0x7e06 }
61733
  },
61734
/* btstc${X} ${Dsp-16-u8}[$Bit16An] */
61735
  {
61736
    { 0, 0, 0, 0 },
61737
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (BIT16AN), ']', 0 } },
61738
    & ifmt_bxor16_X_bit16_16_bit16_16_8_An_relative, { 0x7e0800 }
61739
  },
61740
/* btstc${X} ${Dsp-16-u16}[$Bit16An] */
61741
  {
61742
    { 0, 0, 0, 0 },
61743
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (BIT16AN), ']', 0 } },
61744
    & ifmt_bxor16_X_bit16_16_bit16_16_16_An_relative, { 0x7e0c0000 }
61745
  },
61746
/* btstc${X} ${BitBase16-16-u8}[sb] */
61747
  {
61748
    { 0, 0, 0, 0 },
61749
    { { MNEM, OP (X), ' ', OP (BITBASE16_16_U8), '[', 's', 'b', ']', 0 } },
61750
    & ifmt_bxor16_X_bit16_16_bit16_16_8_SB_relative, { 0x7e0a00 }
61751
  },
61752
/* btstc${X} ${BitBase16-16-u16}[sb] */
61753
  {
61754
    { 0, 0, 0, 0 },
61755
    { { MNEM, OP (X), ' ', OP (BITBASE16_16_U16), '[', 's', 'b', ']', 0 } },
61756
    & ifmt_bxor16_X_bit16_16_bit16_16_16_SB_relative, { 0x7e0e0000 }
61757
  },
61758
/* btstc${X} ${BitBase16-16-s8}[fb] */
61759
  {
61760
    { 0, 0, 0, 0 },
61761
    { { MNEM, OP (X), ' ', OP (BITBASE16_16_S8), '[', 'f', 'b', ']', 0 } },
61762
    & ifmt_bxor16_X_bit16_16_bit16_16_8_FB_relative, { 0x7e0b00 }
61763
  },
61764
/* btstc${X} ${BitBase16-16-u16} */
61765
  {
61766
    { 0, 0, 0, 0 },
61767
    { { MNEM, OP (X), ' ', OP (BITBASE16_16_U16), 0 } },
61768
    & ifmt_bxor16_X_bit16_16_bit16_16_16_absolute, { 0x7e0f0000 }
61769
  },
61770
/* btst${G} $Bitno32Unprefixed,$Bit32RnUnprefixed */
61771
  {
61772
    { 0, 0, 0, 0 },
61773
    { { MNEM, OP (G), ' ', OP (BITNO32UNPREFIXED), ',', OP (BIT32RNUNPREFIXED), 0 } },
61774
    & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_Rn_direct_Unprefixed, { 0xd800 }
61775
  },
61776
/* btst${G} $Bitno32Unprefixed,$Bit32AnUnprefixed */
61777
  {
61778
    { 0, 0, 0, 0 },
61779
    { { MNEM, OP (G), ' ', OP (BITNO32UNPREFIXED), ',', OP (BIT32ANUNPREFIXED), 0 } },
61780
    & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_An_direct_Unprefixed, { 0xd080 }
61781
  },
61782
/* btst${G} $Bitno32Unprefixed,[$Bit32AnUnprefixed] */
61783
  {
61784
    { 0, 0, 0, 0 },
61785
    { { MNEM, OP (G), ' ', OP (BITNO32UNPREFIXED), ',', '[', OP (BIT32ANUNPREFIXED), ']', 0 } },
61786
    & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_An_indirect_Unprefixed, { 0xd000 }
61787
  },
61788
/* btst${G} ${BitBase32-16-u11-Unprefixed}[$Bit32AnUnprefixed] */
61789
  {
61790
    { 0, 0, 0, 0 },
61791
    { { MNEM, OP (G), ' ', OP (BITBASE32_16_U11_UNPREFIXED), '[', OP (BIT32ANUNPREFIXED), ']', 0 } },
61792
    & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_11_An_relative_Unprefixed, { 0xd20000 }
61793
  },
61794
/* btst${G} ${BitBase32-16-u19-Unprefixed}[$Bit32AnUnprefixed] */
61795
  {
61796
    { 0, 0, 0, 0 },
61797
    { { MNEM, OP (G), ' ', OP (BITBASE32_16_U19_UNPREFIXED), '[', OP (BIT32ANUNPREFIXED), ']', 0 } },
61798
    & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_An_relative_Unprefixed, { 0xd4000000 }
61799
  },
61800
/* btst${G} ${BitBase32-16-u27-Unprefixed}[$Bit32AnUnprefixed] */
61801
  {
61802
    { 0, 0, 0, 0 },
61803
    { { MNEM, OP (G), ' ', OP (BITBASE32_16_U27_UNPREFIXED), '[', OP (BIT32ANUNPREFIXED), ']', 0 } },
61804
    & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_27_An_relative_Unprefixed, { 0xd6000000 }
61805
  },
61806
/* btst${G} ${BitBase32-16-u11-Unprefixed}[sb] */
61807
  {
61808
    { 0, 0, 0, 0 },
61809
    { { MNEM, OP (G), ' ', OP (BITBASE32_16_U11_UNPREFIXED), '[', 's', 'b', ']', 0 } },
61810
    & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_11_SB_relative_Unprefixed, { 0xd28000 }
61811
  },
61812
/* btst${G} ${BitBase32-16-u19-Unprefixed}[sb] */
61813
  {
61814
    { 0, 0, 0, 0 },
61815
    { { MNEM, OP (G), ' ', OP (BITBASE32_16_U19_UNPREFIXED), '[', 's', 'b', ']', 0 } },
61816
    & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_SB_relative_Unprefixed, { 0xd4800000 }
61817
  },
61818
/* btst${G} ${BitBase32-16-s11-Unprefixed}[fb] */
61819
  {
61820
    { 0, 0, 0, 0 },
61821
    { { MNEM, OP (G), ' ', OP (BITBASE32_16_S11_UNPREFIXED), '[', 'f', 'b', ']', 0 } },
61822
    & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_11_FB_relative_Unprefixed, { 0xd2c000 }
61823
  },
61824
/* btst${G} ${BitBase32-16-s19-Unprefixed}[fb] */
61825
  {
61826
    { 0, 0, 0, 0 },
61827
    { { MNEM, OP (G), ' ', OP (BITBASE32_16_S19_UNPREFIXED), '[', 'f', 'b', ']', 0 } },
61828
    & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_FB_relative_Unprefixed, { 0xd4c00000 }
61829
  },
61830
/* btst${G} ${BitBase32-16-u19-Unprefixed} */
61831
  {
61832
    { 0, 0, 0, 0 },
61833
    { { MNEM, OP (G), ' ', OP (BITBASE32_16_U19_UNPREFIXED), 0 } },
61834
    & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_absolute_Unprefixed, { 0xd6c00000 }
61835
  },
61836
/* btst${G} ${BitBase32-16-u27-Unprefixed} */
61837
  {
61838
    { 0, 0, 0, 0 },
61839
    { { MNEM, OP (G), ' ', OP (BITBASE32_16_U27_UNPREFIXED), 0 } },
61840
    & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_27_absolute_Unprefixed, { 0xd6800000 }
61841
  },
61842
/* btst${G} $Bitno16R,$Bit16Rn */
61843
  {
61844
    { 0, 0, 0, 0 },
61845
    { { MNEM, OP (G), ' ', OP (BITNO16R), ',', OP (BIT16RN), 0 } },
61846
    & ifmt_bxor16_X_bit16_16_bit16_Rn_direct, { 0x7eb000 }
61847
  },
61848
/* btst${G} $Bitno16R,$Bit16An */
61849
  {
61850
    { 0, 0, 0, 0 },
61851
    { { MNEM, OP (G), ' ', OP (BITNO16R), ',', OP (BIT16AN), 0 } },
61852
    & ifmt_bxor16_X_bit16_16_bit16_An_direct, { 0x7eb400 }
61853
  },
61854
/* btst${G} ${Dsp-16-u8}[$Bit16An] */
61855
  {
61856
    { 0, 0, 0, 0 },
61857
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (BIT16AN), ']', 0 } },
61858
    & ifmt_bxor16_X_bit16_16_bit16_16_8_An_relative, { 0x7eb800 }
61859
  },
61860
/* btst${G} ${BitBase16-16-u8}[sb] */
61861
  {
61862
    { 0, 0, 0, 0 },
61863
    { { MNEM, OP (G), ' ', OP (BITBASE16_16_U8), '[', 's', 'b', ']', 0 } },
61864
    & ifmt_bxor16_X_bit16_16_bit16_16_8_SB_relative, { 0x7eba00 }
61865
  },
61866
/* btst${G} ${BitBase16-16-s8}[fb] */
61867
  {
61868
    { 0, 0, 0, 0 },
61869
    { { MNEM, OP (G), ' ', OP (BITBASE16_16_S8), '[', 'f', 'b', ']', 0 } },
61870
    & ifmt_bxor16_X_bit16_16_bit16_16_8_FB_relative, { 0x7ebb00 }
61871
  },
61872
/* btst${S} ${BitBase16-8-u11-S}[sb] */
61873
  {
61874
    { 0, 0, 0, 0 },
61875
    { { MNEM, OP (S), ' ', OP (BITBASE16_8_U11_S), '[', 's', 'b', ']', 0 } },
61876
    & ifmt_btst16_S_bit16_11_S_bit16_11_SB_relative_S, { 0x5800 }
61877
  },
61878
/* btst${G} ${Dsp-16-u16}[$Bit16An] */
61879
  {
61880
    { 0, 0, 0, 0 },
61881
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (BIT16AN), ']', 0 } },
61882
    & ifmt_bxor16_X_bit16_16_bit16_16_16_An_relative, { 0x7ebc0000 }
61883
  },
61884
/* btst${G} ${BitBase16-16-u16}[sb] */
61885
  {
61886
    { 0, 0, 0, 0 },
61887
    { { MNEM, OP (G), ' ', OP (BITBASE16_16_U16), '[', 's', 'b', ']', 0 } },
61888
    & ifmt_bxor16_X_bit16_16_bit16_16_16_SB_relative, { 0x7ebe0000 }
61889
  },
61890
/* btst${G} ${BitBase16-16-u16} */
61891
  {
61892
    { 0, 0, 0, 0 },
61893
    { { MNEM, OP (G), ' ', OP (BITBASE16_16_U16), 0 } },
61894
    & ifmt_bxor16_X_bit16_16_bit16_16_16_absolute, { 0x7ebf0000 }
61895
  },
61896
/* btst${G} [$Bit16An] */
61897
  {
61898
    { 0, 0, 0, 0 },
61899
    { { MNEM, OP (G), ' ', '[', OP (BIT16AN), ']', 0 } },
61900
    & ifmt_bxor16_X_bit16_16_bit16_An_indirect, { 0x7eb6 }
61901
  },
61902
/* bset${X} $Bitno32Unprefixed,$Bit32RnUnprefixed */
61903
  {
61904
    { 0, 0, 0, 0 },
61905
    { { MNEM, OP (X), ' ', OP (BITNO32UNPREFIXED), ',', OP (BIT32RNUNPREFIXED), 0 } },
61906
    & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_Rn_direct_Unprefixed, { 0xd838 }
61907
  },
61908
/* bset${X} $Bitno32Unprefixed,$Bit32AnUnprefixed */
61909
  {
61910
    { 0, 0, 0, 0 },
61911
    { { MNEM, OP (X), ' ', OP (BITNO32UNPREFIXED), ',', OP (BIT32ANUNPREFIXED), 0 } },
61912
    & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_An_direct_Unprefixed, { 0xd0b8 }
61913
  },
61914
/* bset${X} $Bitno32Unprefixed,[$Bit32AnUnprefixed] */
61915
  {
61916
    { 0, 0, 0, 0 },
61917
    { { MNEM, OP (X), ' ', OP (BITNO32UNPREFIXED), ',', '[', OP (BIT32ANUNPREFIXED), ']', 0 } },
61918
    & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_An_indirect_Unprefixed, { 0xd038 }
61919
  },
61920
/* bset${X} ${BitBase32-16-u11-Unprefixed}[$Bit32AnUnprefixed] */
61921
  {
61922
    { 0, 0, 0, 0 },
61923
    { { MNEM, OP (X), ' ', OP (BITBASE32_16_U11_UNPREFIXED), '[', OP (BIT32ANUNPREFIXED), ']', 0 } },
61924
    & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_11_An_relative_Unprefixed, { 0xd23800 }
61925
  },
61926
/* bset${X} ${BitBase32-16-u19-Unprefixed}[$Bit32AnUnprefixed] */
61927
  {
61928
    { 0, 0, 0, 0 },
61929
    { { MNEM, OP (X), ' ', OP (BITBASE32_16_U19_UNPREFIXED), '[', OP (BIT32ANUNPREFIXED), ']', 0 } },
61930
    & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_An_relative_Unprefixed, { 0xd4380000 }
61931
  },
61932
/* bset${X} ${BitBase32-16-u27-Unprefixed}[$Bit32AnUnprefixed] */
61933
  {
61934
    { 0, 0, 0, 0 },
61935
    { { MNEM, OP (X), ' ', OP (BITBASE32_16_U27_UNPREFIXED), '[', OP (BIT32ANUNPREFIXED), ']', 0 } },
61936
    & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_27_An_relative_Unprefixed, { 0xd6380000 }
61937
  },
61938
/* bset${X} ${BitBase32-16-u11-Unprefixed}[sb] */
61939
  {
61940
    { 0, 0, 0, 0 },
61941
    { { MNEM, OP (X), ' ', OP (BITBASE32_16_U11_UNPREFIXED), '[', 's', 'b', ']', 0 } },
61942
    & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_11_SB_relative_Unprefixed, { 0xd2b800 }
61943
  },
61944
/* bset${X} ${BitBase32-16-u19-Unprefixed}[sb] */
61945
  {
61946
    { 0, 0, 0, 0 },
61947
    { { MNEM, OP (X), ' ', OP (BITBASE32_16_U19_UNPREFIXED), '[', 's', 'b', ']', 0 } },
61948
    & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_SB_relative_Unprefixed, { 0xd4b80000 }
61949
  },
61950
/* bset${X} ${BitBase32-16-s11-Unprefixed}[fb] */
61951
  {
61952
    { 0, 0, 0, 0 },
61953
    { { MNEM, OP (X), ' ', OP (BITBASE32_16_S11_UNPREFIXED), '[', 'f', 'b', ']', 0 } },
61954
    & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_11_FB_relative_Unprefixed, { 0xd2f800 }
61955
  },
61956
/* bset${X} ${BitBase32-16-s19-Unprefixed}[fb] */
61957
  {
61958
    { 0, 0, 0, 0 },
61959
    { { MNEM, OP (X), ' ', OP (BITBASE32_16_S19_UNPREFIXED), '[', 'f', 'b', ']', 0 } },
61960
    & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_FB_relative_Unprefixed, { 0xd4f80000 }
61961
  },
61962
/* bset${X} ${BitBase32-16-u19-Unprefixed} */
61963
  {
61964
    { 0, 0, 0, 0 },
61965
    { { MNEM, OP (X), ' ', OP (BITBASE32_16_U19_UNPREFIXED), 0 } },
61966
    & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_absolute_Unprefixed, { 0xd6f80000 }
61967
  },
61968
/* bset${X} ${BitBase32-16-u27-Unprefixed} */
61969
  {
61970
    { 0, 0, 0, 0 },
61971
    { { MNEM, OP (X), ' ', OP (BITBASE32_16_U27_UNPREFIXED), 0 } },
61972
    & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_27_absolute_Unprefixed, { 0xd6b80000 }
61973
  },
61974
/* bset${G} $Bitno16R,$Bit16Rn */
61975
  {
61976
    { 0, 0, 0, 0 },
61977
    { { MNEM, OP (G), ' ', OP (BITNO16R), ',', OP (BIT16RN), 0 } },
61978
    & ifmt_bxor16_X_bit16_16_bit16_Rn_direct, { 0x7e9000 }
61979
  },
61980
/* bset${G} $Bitno16R,$Bit16An */
61981
  {
61982
    { 0, 0, 0, 0 },
61983
    { { MNEM, OP (G), ' ', OP (BITNO16R), ',', OP (BIT16AN), 0 } },
61984
    & ifmt_bxor16_X_bit16_16_bit16_An_direct, { 0x7e9400 }
61985
  },
61986
/* bset${G} ${Dsp-16-u8}[$Bit16An] */
61987
  {
61988
    { 0, 0, 0, 0 },
61989
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (BIT16AN), ']', 0 } },
61990
    & ifmt_bxor16_X_bit16_16_bit16_16_8_An_relative, { 0x7e9800 }
61991
  },
61992
/* bset${G} ${BitBase16-16-u8}[sb] */
61993
  {
61994
    { 0, 0, 0, 0 },
61995
    { { MNEM, OP (G), ' ', OP (BITBASE16_16_U8), '[', 's', 'b', ']', 0 } },
61996
    & ifmt_bxor16_X_bit16_16_bit16_16_8_SB_relative, { 0x7e9a00 }
61997
  },
61998
/* bset${G} ${BitBase16-16-s8}[fb] */
61999
  {
62000
    { 0, 0, 0, 0 },
62001
    { { MNEM, OP (G), ' ', OP (BITBASE16_16_S8), '[', 'f', 'b', ']', 0 } },
62002
    & ifmt_bxor16_X_bit16_16_bit16_16_8_FB_relative, { 0x7e9b00 }
62003
  },
62004
/* bset${S} ${BitBase16-8-u11-S}[sb] */
62005
  {
62006
    { 0, 0, 0, 0 },
62007
    { { MNEM, OP (S), ' ', OP (BITBASE16_8_U11_S), '[', 's', 'b', ']', 0 } },
62008
    & ifmt_btst16_S_bit16_11_S_bit16_11_SB_relative_S, { 0x4800 }
62009
  },
62010
/* bset${G} ${Dsp-16-u16}[$Bit16An] */
62011
  {
62012
    { 0, 0, 0, 0 },
62013
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (BIT16AN), ']', 0 } },
62014
    & ifmt_bxor16_X_bit16_16_bit16_16_16_An_relative, { 0x7e9c0000 }
62015
  },
62016
/* bset${G} ${BitBase16-16-u16}[sb] */
62017
  {
62018
    { 0, 0, 0, 0 },
62019
    { { MNEM, OP (G), ' ', OP (BITBASE16_16_U16), '[', 's', 'b', ']', 0 } },
62020
    & ifmt_bxor16_X_bit16_16_bit16_16_16_SB_relative, { 0x7e9e0000 }
62021
  },
62022
/* bset${G} ${BitBase16-16-u16} */
62023
  {
62024
    { 0, 0, 0, 0 },
62025
    { { MNEM, OP (G), ' ', OP (BITBASE16_16_U16), 0 } },
62026
    & ifmt_bxor16_X_bit16_16_bit16_16_16_absolute, { 0x7e9f0000 }
62027
  },
62028
/* bset${G} [$Bit16An] */
62029
  {
62030
    { 0, 0, 0, 0 },
62031
    { { MNEM, OP (G), ' ', '[', OP (BIT16AN), ']', 0 } },
62032
    & ifmt_bxor16_X_bit16_16_bit16_An_indirect, { 0x7e96 }
62033
  },
62034
/* bor${X} $Bitno32Prefixed,$Bit32RnPrefixed */
62035
  {
62036
    { 0, 0, 0, 0 },
62037
    { { MNEM, OP (X), ' ', OP (BITNO32PREFIXED), ',', OP (BIT32RNPREFIXED), 0 } },
62038
    & ifmt_bxor32_X_bit32_24_Prefixed_bit32_Rn_direct_Prefixed, { 0x1d820 }
62039
  },
62040
/* bor${X} $Bitno32Prefixed,$Bit32AnPrefixed */
62041
  {
62042
    { 0, 0, 0, 0 },
62043
    { { MNEM, OP (X), ' ', OP (BITNO32PREFIXED), ',', OP (BIT32ANPREFIXED), 0 } },
62044
    & ifmt_bxor32_X_bit32_24_Prefixed_bit32_An_direct_Prefixed, { 0x1d0a0 }
62045
  },
62046
/* bor${X} $Bitno32Prefixed,[$Bit32AnPrefixed] */
62047
  {
62048
    { 0, 0, 0, 0 },
62049
    { { MNEM, OP (X), ' ', OP (BITNO32PREFIXED), ',', '[', OP (BIT32ANPREFIXED), ']', 0 } },
62050
    & ifmt_bxor32_X_bit32_24_Prefixed_bit32_An_indirect_Prefixed, { 0x1d020 }
62051
  },
62052
/* bor${X} ${BitBase32-24-u11-Prefixed}[$Bit32AnPrefixed] */
62053
  {
62054
    { 0, 0, 0, 0 },
62055
    { { MNEM, OP (X), ' ', OP (BITBASE32_24_U11_PREFIXED), '[', OP (BIT32ANPREFIXED), ']', 0 } },
62056
    & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_An_relative_Prefixed, { 0x1d22000 }
62057
  },
62058
/* bor${X} ${BitBase32-24-u19-Prefixed}[$Bit32AnPrefixed] */
62059
  {
62060
    { 0, 0, 0, 0 },
62061
    { { MNEM, OP (X), ' ', OP (BITBASE32_24_U19_PREFIXED), '[', OP (BIT32ANPREFIXED), ']', 0 } },
62062
    & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_An_relative_Prefixed, { 0x1d42000 }
62063
  },
62064
/* bor${X} ${BitBase32-24-u27-Prefixed}[$Bit32AnPrefixed] */
62065
  {
62066
    { 0, 0, 0, 0 },
62067
    { { MNEM, OP (X), ' ', OP (BITBASE32_24_U27_PREFIXED), '[', OP (BIT32ANPREFIXED), ']', 0 } },
62068
    & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_27_An_relative_Prefixed, { 0x1d62000 }
62069
  },
62070
/* bor${X} ${BitBase32-24-u11-Prefixed}[sb] */
62071
  {
62072
    { 0, 0, 0, 0 },
62073
    { { MNEM, OP (X), ' ', OP (BITBASE32_24_U11_PREFIXED), '[', 's', 'b', ']', 0 } },
62074
    & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_SB_relative_Prefixed, { 0x1d2a000 }
62075
  },
62076
/* bor${X} ${BitBase32-24-u19-Prefixed}[sb] */
62077
  {
62078
    { 0, 0, 0, 0 },
62079
    { { MNEM, OP (X), ' ', OP (BITBASE32_24_U19_PREFIXED), '[', 's', 'b', ']', 0 } },
62080
    & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_SB_relative_Prefixed, { 0x1d4a000 }
62081
  },
62082
/* bor${X} ${BitBase32-24-s11-Prefixed}[fb] */
62083
  {
62084
    { 0, 0, 0, 0 },
62085
    { { MNEM, OP (X), ' ', OP (BITBASE32_24_S11_PREFIXED), '[', 'f', 'b', ']', 0 } },
62086
    & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_FB_relative_Prefixed, { 0x1d2e000 }
62087
  },
62088
/* bor${X} ${BitBase32-24-s19-Prefixed}[fb] */
62089
  {
62090
    { 0, 0, 0, 0 },
62091
    { { MNEM, OP (X), ' ', OP (BITBASE32_24_S19_PREFIXED), '[', 'f', 'b', ']', 0 } },
62092
    & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_FB_relative_Prefixed, { 0x1d4e000 }
62093
  },
62094
/* bor${X} ${BitBase32-24-u19-Prefixed} */
62095
  {
62096
    { 0, 0, 0, 0 },
62097
    { { MNEM, OP (X), ' ', OP (BITBASE32_24_U19_PREFIXED), 0 } },
62098
    & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_absolute_Prefixed, { 0x1d6e000 }
62099
  },
62100
/* bor${X} ${BitBase32-24-u27-Prefixed} */
62101
  {
62102
    { 0, 0, 0, 0 },
62103
    { { MNEM, OP (X), ' ', OP (BITBASE32_24_U27_PREFIXED), 0 } },
62104
    & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_27_absolute_Prefixed, { 0x1d6a000 }
62105
  },
62106
/* bor${X} $Bitno16R,$Bit16Rn */
62107
  {
62108
    { 0, 0, 0, 0 },
62109
    { { MNEM, OP (X), ' ', OP (BITNO16R), ',', OP (BIT16RN), 0 } },
62110
    & ifmt_bxor16_X_bit16_16_bit16_Rn_direct, { 0x7e6000 }
62111
  },
62112
/* bor${X} $Bitno16R,$Bit16An */
62113
  {
62114
    { 0, 0, 0, 0 },
62115
    { { MNEM, OP (X), ' ', OP (BITNO16R), ',', OP (BIT16AN), 0 } },
62116
    & ifmt_bxor16_X_bit16_16_bit16_An_direct, { 0x7e6400 }
62117
  },
62118
/* bor${X} [$Bit16An] */
62119
  {
62120
    { 0, 0, 0, 0 },
62121
    { { MNEM, OP (X), ' ', '[', OP (BIT16AN), ']', 0 } },
62122
    & ifmt_bxor16_X_bit16_16_bit16_An_indirect, { 0x7e66 }
62123
  },
62124
/* bor${X} ${Dsp-16-u8}[$Bit16An] */
62125
  {
62126
    { 0, 0, 0, 0 },
62127
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (BIT16AN), ']', 0 } },
62128
    & ifmt_bxor16_X_bit16_16_bit16_16_8_An_relative, { 0x7e6800 }
62129
  },
62130
/* bor${X} ${Dsp-16-u16}[$Bit16An] */
62131
  {
62132
    { 0, 0, 0, 0 },
62133
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (BIT16AN), ']', 0 } },
62134
    & ifmt_bxor16_X_bit16_16_bit16_16_16_An_relative, { 0x7e6c0000 }
62135
  },
62136
/* bor${X} ${BitBase16-16-u8}[sb] */
62137
  {
62138
    { 0, 0, 0, 0 },
62139
    { { MNEM, OP (X), ' ', OP (BITBASE16_16_U8), '[', 's', 'b', ']', 0 } },
62140
    & ifmt_bxor16_X_bit16_16_bit16_16_8_SB_relative, { 0x7e6a00 }
62141
  },
62142
/* bor${X} ${BitBase16-16-u16}[sb] */
62143
  {
62144
    { 0, 0, 0, 0 },
62145
    { { MNEM, OP (X), ' ', OP (BITBASE16_16_U16), '[', 's', 'b', ']', 0 } },
62146
    & ifmt_bxor16_X_bit16_16_bit16_16_16_SB_relative, { 0x7e6e0000 }
62147
  },
62148
/* bor${X} ${BitBase16-16-s8}[fb] */
62149
  {
62150
    { 0, 0, 0, 0 },
62151
    { { MNEM, OP (X), ' ', OP (BITBASE16_16_S8), '[', 'f', 'b', ']', 0 } },
62152
    & ifmt_bxor16_X_bit16_16_bit16_16_8_FB_relative, { 0x7e6b00 }
62153
  },
62154
/* bor${X} ${BitBase16-16-u16} */
62155
  {
62156
    { 0, 0, 0, 0 },
62157
    { { MNEM, OP (X), ' ', OP (BITBASE16_16_U16), 0 } },
62158
    & ifmt_bxor16_X_bit16_16_bit16_16_16_absolute, { 0x7e6f0000 }
62159
  },
62160
/* bnxor${X} $Bitno32Prefixed,$Bit32RnPrefixed */
62161
  {
62162
    { 0, 0, 0, 0 },
62163
    { { MNEM, OP (X), ' ', OP (BITNO32PREFIXED), ',', OP (BIT32RNPREFIXED), 0 } },
62164
    & ifmt_bxor32_X_bit32_24_Prefixed_bit32_Rn_direct_Prefixed, { 0x1d838 }
62165
  },
62166
/* bnxor${X} $Bitno32Prefixed,$Bit32AnPrefixed */
62167
  {
62168
    { 0, 0, 0, 0 },
62169
    { { MNEM, OP (X), ' ', OP (BITNO32PREFIXED), ',', OP (BIT32ANPREFIXED), 0 } },
62170
    & ifmt_bxor32_X_bit32_24_Prefixed_bit32_An_direct_Prefixed, { 0x1d0b8 }
62171
  },
62172
/* bnxor${X} $Bitno32Prefixed,[$Bit32AnPrefixed] */
62173
  {
62174
    { 0, 0, 0, 0 },
62175
    { { MNEM, OP (X), ' ', OP (BITNO32PREFIXED), ',', '[', OP (BIT32ANPREFIXED), ']', 0 } },
62176
    & ifmt_bxor32_X_bit32_24_Prefixed_bit32_An_indirect_Prefixed, { 0x1d038 }
62177
  },
62178
/* bnxor${X} ${BitBase32-24-u11-Prefixed}[$Bit32AnPrefixed] */
62179
  {
62180
    { 0, 0, 0, 0 },
62181
    { { MNEM, OP (X), ' ', OP (BITBASE32_24_U11_PREFIXED), '[', OP (BIT32ANPREFIXED), ']', 0 } },
62182
    & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_An_relative_Prefixed, { 0x1d23800 }
62183
  },
62184
/* bnxor${X} ${BitBase32-24-u19-Prefixed}[$Bit32AnPrefixed] */
62185
  {
62186
    { 0, 0, 0, 0 },
62187
    { { MNEM, OP (X), ' ', OP (BITBASE32_24_U19_PREFIXED), '[', OP (BIT32ANPREFIXED), ']', 0 } },
62188
    & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_An_relative_Prefixed, { 0x1d43800 }
62189
  },
62190
/* bnxor${X} ${BitBase32-24-u27-Prefixed}[$Bit32AnPrefixed] */
62191
  {
62192
    { 0, 0, 0, 0 },
62193
    { { MNEM, OP (X), ' ', OP (BITBASE32_24_U27_PREFIXED), '[', OP (BIT32ANPREFIXED), ']', 0 } },
62194
    & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_27_An_relative_Prefixed, { 0x1d63800 }
62195
  },
62196
/* bnxor${X} ${BitBase32-24-u11-Prefixed}[sb] */
62197
  {
62198
    { 0, 0, 0, 0 },
62199
    { { MNEM, OP (X), ' ', OP (BITBASE32_24_U11_PREFIXED), '[', 's', 'b', ']', 0 } },
62200
    & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_SB_relative_Prefixed, { 0x1d2b800 }
62201
  },
62202
/* bnxor${X} ${BitBase32-24-u19-Prefixed}[sb] */
62203
  {
62204
    { 0, 0, 0, 0 },
62205
    { { MNEM, OP (X), ' ', OP (BITBASE32_24_U19_PREFIXED), '[', 's', 'b', ']', 0 } },
62206
    & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_SB_relative_Prefixed, { 0x1d4b800 }
62207
  },
62208
/* bnxor${X} ${BitBase32-24-s11-Prefixed}[fb] */
62209
  {
62210
    { 0, 0, 0, 0 },
62211
    { { MNEM, OP (X), ' ', OP (BITBASE32_24_S11_PREFIXED), '[', 'f', 'b', ']', 0 } },
62212
    & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_FB_relative_Prefixed, { 0x1d2f800 }
62213
  },
62214
/* bnxor${X} ${BitBase32-24-s19-Prefixed}[fb] */
62215
  {
62216
    { 0, 0, 0, 0 },
62217
    { { MNEM, OP (X), ' ', OP (BITBASE32_24_S19_PREFIXED), '[', 'f', 'b', ']', 0 } },
62218
    & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_FB_relative_Prefixed, { 0x1d4f800 }
62219
  },
62220
/* bnxor${X} ${BitBase32-24-u19-Prefixed} */
62221
  {
62222
    { 0, 0, 0, 0 },
62223
    { { MNEM, OP (X), ' ', OP (BITBASE32_24_U19_PREFIXED), 0 } },
62224
    & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_absolute_Prefixed, { 0x1d6f800 }
62225
  },
62226
/* bnxor${X} ${BitBase32-24-u27-Prefixed} */
62227
  {
62228
    { 0, 0, 0, 0 },
62229
    { { MNEM, OP (X), ' ', OP (BITBASE32_24_U27_PREFIXED), 0 } },
62230
    & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_27_absolute_Prefixed, { 0x1d6b800 }
62231
  },
62232
/* bnxor${X} $Bitno16R,$Bit16Rn */
62233
  {
62234
    { 0, 0, 0, 0 },
62235
    { { MNEM, OP (X), ' ', OP (BITNO16R), ',', OP (BIT16RN), 0 } },
62236
    & ifmt_bxor16_X_bit16_16_bit16_Rn_direct, { 0x7ed000 }
62237
  },
62238
/* bnxor${X} $Bitno16R,$Bit16An */
62239
  {
62240
    { 0, 0, 0, 0 },
62241
    { { MNEM, OP (X), ' ', OP (BITNO16R), ',', OP (BIT16AN), 0 } },
62242
    & ifmt_bxor16_X_bit16_16_bit16_An_direct, { 0x7ed400 }
62243
  },
62244
/* bnxor${X} [$Bit16An] */
62245
  {
62246
    { 0, 0, 0, 0 },
62247
    { { MNEM, OP (X), ' ', '[', OP (BIT16AN), ']', 0 } },
62248
    & ifmt_bxor16_X_bit16_16_bit16_An_indirect, { 0x7ed6 }
62249
  },
62250
/* bnxor${X} ${Dsp-16-u8}[$Bit16An] */
62251
  {
62252
    { 0, 0, 0, 0 },
62253
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (BIT16AN), ']', 0 } },
62254
    & ifmt_bxor16_X_bit16_16_bit16_16_8_An_relative, { 0x7ed800 }
62255
  },
62256
/* bnxor${X} ${Dsp-16-u16}[$Bit16An] */
62257
  {
62258
    { 0, 0, 0, 0 },
62259
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (BIT16AN), ']', 0 } },
62260
    & ifmt_bxor16_X_bit16_16_bit16_16_16_An_relative, { 0x7edc0000 }
62261
  },
62262
/* bnxor${X} ${BitBase16-16-u8}[sb] */
62263
  {
62264
    { 0, 0, 0, 0 },
62265
    { { MNEM, OP (X), ' ', OP (BITBASE16_16_U8), '[', 's', 'b', ']', 0 } },
62266
    & ifmt_bxor16_X_bit16_16_bit16_16_8_SB_relative, { 0x7eda00 }
62267
  },
62268
/* bnxor${X} ${BitBase16-16-u16}[sb] */
62269
  {
62270
    { 0, 0, 0, 0 },
62271
    { { MNEM, OP (X), ' ', OP (BITBASE16_16_U16), '[', 's', 'b', ']', 0 } },
62272
    & ifmt_bxor16_X_bit16_16_bit16_16_16_SB_relative, { 0x7ede0000 }
62273
  },
62274
/* bnxor${X} ${BitBase16-16-s8}[fb] */
62275
  {
62276
    { 0, 0, 0, 0 },
62277
    { { MNEM, OP (X), ' ', OP (BITBASE16_16_S8), '[', 'f', 'b', ']', 0 } },
62278
    & ifmt_bxor16_X_bit16_16_bit16_16_8_FB_relative, { 0x7edb00 }
62279
  },
62280
/* bnxor${X} ${BitBase16-16-u16} */
62281
  {
62282
    { 0, 0, 0, 0 },
62283
    { { MNEM, OP (X), ' ', OP (BITBASE16_16_U16), 0 } },
62284
    & ifmt_bxor16_X_bit16_16_bit16_16_16_absolute, { 0x7edf0000 }
62285
  },
62286
/* bntst${X} $Bitno32Prefixed,$Bit32RnPrefixed */
62287
  {
62288
    { 0, 0, 0, 0 },
62289
    { { MNEM, OP (X), ' ', OP (BITNO32PREFIXED), ',', OP (BIT32RNPREFIXED), 0 } },
62290
    & ifmt_bxor32_X_bit32_24_Prefixed_bit32_Rn_direct_Prefixed, { 0x1d800 }
62291
  },
62292
/* bntst${X} $Bitno32Prefixed,$Bit32AnPrefixed */
62293
  {
62294
    { 0, 0, 0, 0 },
62295
    { { MNEM, OP (X), ' ', OP (BITNO32PREFIXED), ',', OP (BIT32ANPREFIXED), 0 } },
62296
    & ifmt_bxor32_X_bit32_24_Prefixed_bit32_An_direct_Prefixed, { 0x1d080 }
62297
  },
62298
/* bntst${X} $Bitno32Prefixed,[$Bit32AnPrefixed] */
62299
  {
62300
    { 0, 0, 0, 0 },
62301
    { { MNEM, OP (X), ' ', OP (BITNO32PREFIXED), ',', '[', OP (BIT32ANPREFIXED), ']', 0 } },
62302
    & ifmt_bxor32_X_bit32_24_Prefixed_bit32_An_indirect_Prefixed, { 0x1d000 }
62303
  },
62304
/* bntst${X} ${BitBase32-24-u11-Prefixed}[$Bit32AnPrefixed] */
62305
  {
62306
    { 0, 0, 0, 0 },
62307
    { { MNEM, OP (X), ' ', OP (BITBASE32_24_U11_PREFIXED), '[', OP (BIT32ANPREFIXED), ']', 0 } },
62308
    & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_An_relative_Prefixed, { 0x1d20000 }
62309
  },
62310
/* bntst${X} ${BitBase32-24-u19-Prefixed}[$Bit32AnPrefixed] */
62311
  {
62312
    { 0, 0, 0, 0 },
62313
    { { MNEM, OP (X), ' ', OP (BITBASE32_24_U19_PREFIXED), '[', OP (BIT32ANPREFIXED), ']', 0 } },
62314
    & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_An_relative_Prefixed, { 0x1d40000 }
62315
  },
62316
/* bntst${X} ${BitBase32-24-u27-Prefixed}[$Bit32AnPrefixed] */
62317
  {
62318
    { 0, 0, 0, 0 },
62319
    { { MNEM, OP (X), ' ', OP (BITBASE32_24_U27_PREFIXED), '[', OP (BIT32ANPREFIXED), ']', 0 } },
62320
    & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_27_An_relative_Prefixed, { 0x1d60000 }
62321
  },
62322
/* bntst${X} ${BitBase32-24-u11-Prefixed}[sb] */
62323
  {
62324
    { 0, 0, 0, 0 },
62325
    { { MNEM, OP (X), ' ', OP (BITBASE32_24_U11_PREFIXED), '[', 's', 'b', ']', 0 } },
62326
    & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_SB_relative_Prefixed, { 0x1d28000 }
62327
  },
62328
/* bntst${X} ${BitBase32-24-u19-Prefixed}[sb] */
62329
  {
62330
    { 0, 0, 0, 0 },
62331
    { { MNEM, OP (X), ' ', OP (BITBASE32_24_U19_PREFIXED), '[', 's', 'b', ']', 0 } },
62332
    & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_SB_relative_Prefixed, { 0x1d48000 }
62333
  },
62334
/* bntst${X} ${BitBase32-24-s11-Prefixed}[fb] */
62335
  {
62336
    { 0, 0, 0, 0 },
62337
    { { MNEM, OP (X), ' ', OP (BITBASE32_24_S11_PREFIXED), '[', 'f', 'b', ']', 0 } },
62338
    & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_FB_relative_Prefixed, { 0x1d2c000 }
62339
  },
62340
/* bntst${X} ${BitBase32-24-s19-Prefixed}[fb] */
62341
  {
62342
    { 0, 0, 0, 0 },
62343
    { { MNEM, OP (X), ' ', OP (BITBASE32_24_S19_PREFIXED), '[', 'f', 'b', ']', 0 } },
62344
    & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_FB_relative_Prefixed, { 0x1d4c000 }
62345
  },
62346
/* bntst${X} ${BitBase32-24-u19-Prefixed} */
62347
  {
62348
    { 0, 0, 0, 0 },
62349
    { { MNEM, OP (X), ' ', OP (BITBASE32_24_U19_PREFIXED), 0 } },
62350
    & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_absolute_Prefixed, { 0x1d6c000 }
62351
  },
62352
/* bntst${X} ${BitBase32-24-u27-Prefixed} */
62353
  {
62354
    { 0, 0, 0, 0 },
62355
    { { MNEM, OP (X), ' ', OP (BITBASE32_24_U27_PREFIXED), 0 } },
62356
    & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_27_absolute_Prefixed, { 0x1d68000 }
62357
  },
62358
/* bntst${X} $Bitno16R,$Bit16Rn */
62359
  {
62360
    { 0, 0, 0, 0 },
62361
    { { MNEM, OP (X), ' ', OP (BITNO16R), ',', OP (BIT16RN), 0 } },
62362
    & ifmt_bxor16_X_bit16_16_bit16_Rn_direct, { 0x7e3000 }
62363
  },
62364
/* bntst${X} $Bitno16R,$Bit16An */
62365
  {
62366
    { 0, 0, 0, 0 },
62367
    { { MNEM, OP (X), ' ', OP (BITNO16R), ',', OP (BIT16AN), 0 } },
62368
    & ifmt_bxor16_X_bit16_16_bit16_An_direct, { 0x7e3400 }
62369
  },
62370
/* bntst${X} [$Bit16An] */
62371
  {
62372
    { 0, 0, 0, 0 },
62373
    { { MNEM, OP (X), ' ', '[', OP (BIT16AN), ']', 0 } },
62374
    & ifmt_bxor16_X_bit16_16_bit16_An_indirect, { 0x7e36 }
62375
  },
62376
/* bntst${X} ${Dsp-16-u8}[$Bit16An] */
62377
  {
62378
    { 0, 0, 0, 0 },
62379
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (BIT16AN), ']', 0 } },
62380
    & ifmt_bxor16_X_bit16_16_bit16_16_8_An_relative, { 0x7e3800 }
62381
  },
62382
/* bntst${X} ${Dsp-16-u16}[$Bit16An] */
62383
  {
62384
    { 0, 0, 0, 0 },
62385
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (BIT16AN), ']', 0 } },
62386
    & ifmt_bxor16_X_bit16_16_bit16_16_16_An_relative, { 0x7e3c0000 }
62387
  },
62388
/* bntst${X} ${BitBase16-16-u8}[sb] */
62389
  {
62390
    { 0, 0, 0, 0 },
62391
    { { MNEM, OP (X), ' ', OP (BITBASE16_16_U8), '[', 's', 'b', ']', 0 } },
62392
    & ifmt_bxor16_X_bit16_16_bit16_16_8_SB_relative, { 0x7e3a00 }
62393
  },
62394
/* bntst${X} ${BitBase16-16-u16}[sb] */
62395
  {
62396
    { 0, 0, 0, 0 },
62397
    { { MNEM, OP (X), ' ', OP (BITBASE16_16_U16), '[', 's', 'b', ']', 0 } },
62398
    & ifmt_bxor16_X_bit16_16_bit16_16_16_SB_relative, { 0x7e3e0000 }
62399
  },
62400
/* bntst${X} ${BitBase16-16-s8}[fb] */
62401
  {
62402
    { 0, 0, 0, 0 },
62403
    { { MNEM, OP (X), ' ', OP (BITBASE16_16_S8), '[', 'f', 'b', ']', 0 } },
62404
    & ifmt_bxor16_X_bit16_16_bit16_16_8_FB_relative, { 0x7e3b00 }
62405
  },
62406
/* bntst${X} ${BitBase16-16-u16} */
62407
  {
62408
    { 0, 0, 0, 0 },
62409
    { { MNEM, OP (X), ' ', OP (BITBASE16_16_U16), 0 } },
62410
    & ifmt_bxor16_X_bit16_16_bit16_16_16_absolute, { 0x7e3f0000 }
62411
  },
62412
/* bnot${X} $Bitno32Unprefixed,$Bit32RnUnprefixed */
62413
  {
62414
    { 0, 0, 0, 0 },
62415
    { { MNEM, OP (X), ' ', OP (BITNO32UNPREFIXED), ',', OP (BIT32RNUNPREFIXED), 0 } },
62416
    & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_Rn_direct_Unprefixed, { 0xd818 }
62417
  },
62418
/* bnot${X} $Bitno32Unprefixed,$Bit32AnUnprefixed */
62419
  {
62420
    { 0, 0, 0, 0 },
62421
    { { MNEM, OP (X), ' ', OP (BITNO32UNPREFIXED), ',', OP (BIT32ANUNPREFIXED), 0 } },
62422
    & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_An_direct_Unprefixed, { 0xd098 }
62423
  },
62424
/* bnot${X} $Bitno32Unprefixed,[$Bit32AnUnprefixed] */
62425
  {
62426
    { 0, 0, 0, 0 },
62427
    { { MNEM, OP (X), ' ', OP (BITNO32UNPREFIXED), ',', '[', OP (BIT32ANUNPREFIXED), ']', 0 } },
62428
    & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_An_indirect_Unprefixed, { 0xd018 }
62429
  },
62430
/* bnot${X} ${BitBase32-16-u11-Unprefixed}[$Bit32AnUnprefixed] */
62431
  {
62432
    { 0, 0, 0, 0 },
62433
    { { MNEM, OP (X), ' ', OP (BITBASE32_16_U11_UNPREFIXED), '[', OP (BIT32ANUNPREFIXED), ']', 0 } },
62434
    & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_11_An_relative_Unprefixed, { 0xd21800 }
62435
  },
62436
/* bnot${X} ${BitBase32-16-u19-Unprefixed}[$Bit32AnUnprefixed] */
62437
  {
62438
    { 0, 0, 0, 0 },
62439
    { { MNEM, OP (X), ' ', OP (BITBASE32_16_U19_UNPREFIXED), '[', OP (BIT32ANUNPREFIXED), ']', 0 } },
62440
    & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_An_relative_Unprefixed, { 0xd4180000 }
62441
  },
62442
/* bnot${X} ${BitBase32-16-u27-Unprefixed}[$Bit32AnUnprefixed] */
62443
  {
62444
    { 0, 0, 0, 0 },
62445
    { { MNEM, OP (X), ' ', OP (BITBASE32_16_U27_UNPREFIXED), '[', OP (BIT32ANUNPREFIXED), ']', 0 } },
62446
    & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_27_An_relative_Unprefixed, { 0xd6180000 }
62447
  },
62448
/* bnot${X} ${BitBase32-16-u11-Unprefixed}[sb] */
62449
  {
62450
    { 0, 0, 0, 0 },
62451
    { { MNEM, OP (X), ' ', OP (BITBASE32_16_U11_UNPREFIXED), '[', 's', 'b', ']', 0 } },
62452
    & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_11_SB_relative_Unprefixed, { 0xd29800 }
62453
  },
62454
/* bnot${X} ${BitBase32-16-u19-Unprefixed}[sb] */
62455
  {
62456
    { 0, 0, 0, 0 },
62457
    { { MNEM, OP (X), ' ', OP (BITBASE32_16_U19_UNPREFIXED), '[', 's', 'b', ']', 0 } },
62458
    & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_SB_relative_Unprefixed, { 0xd4980000 }
62459
  },
62460
/* bnot${X} ${BitBase32-16-s11-Unprefixed}[fb] */
62461
  {
62462
    { 0, 0, 0, 0 },
62463
    { { MNEM, OP (X), ' ', OP (BITBASE32_16_S11_UNPREFIXED), '[', 'f', 'b', ']', 0 } },
62464
    & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_11_FB_relative_Unprefixed, { 0xd2d800 }
62465
  },
62466
/* bnot${X} ${BitBase32-16-s19-Unprefixed}[fb] */
62467
  {
62468
    { 0, 0, 0, 0 },
62469
    { { MNEM, OP (X), ' ', OP (BITBASE32_16_S19_UNPREFIXED), '[', 'f', 'b', ']', 0 } },
62470
    & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_FB_relative_Unprefixed, { 0xd4d80000 }
62471
  },
62472
/* bnot${X} ${BitBase32-16-u19-Unprefixed} */
62473
  {
62474
    { 0, 0, 0, 0 },
62475
    { { MNEM, OP (X), ' ', OP (BITBASE32_16_U19_UNPREFIXED), 0 } },
62476
    & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_absolute_Unprefixed, { 0xd6d80000 }
62477
  },
62478
/* bnot${X} ${BitBase32-16-u27-Unprefixed} */
62479
  {
62480
    { 0, 0, 0, 0 },
62481
    { { MNEM, OP (X), ' ', OP (BITBASE32_16_U27_UNPREFIXED), 0 } },
62482
    & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_27_absolute_Unprefixed, { 0xd6980000 }
62483
  },
62484
/* bnot${G} $Bitno16R,$Bit16Rn */
62485
  {
62486
    { 0, 0, 0, 0 },
62487
    { { MNEM, OP (G), ' ', OP (BITNO16R), ',', OP (BIT16RN), 0 } },
62488
    & ifmt_bxor16_X_bit16_16_bit16_Rn_direct, { 0x7ea000 }
62489
  },
62490
/* bnot${G} $Bitno16R,$Bit16An */
62491
  {
62492
    { 0, 0, 0, 0 },
62493
    { { MNEM, OP (G), ' ', OP (BITNO16R), ',', OP (BIT16AN), 0 } },
62494
    & ifmt_bxor16_X_bit16_16_bit16_An_direct, { 0x7ea400 }
62495
  },
62496
/* bnot${G} ${Dsp-16-u8}[$Bit16An] */
62497
  {
62498
    { 0, 0, 0, 0 },
62499
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (BIT16AN), ']', 0 } },
62500
    & ifmt_bxor16_X_bit16_16_bit16_16_8_An_relative, { 0x7ea800 }
62501
  },
62502
/* bnot${G} ${BitBase16-16-u8}[sb] */
62503
  {
62504
    { 0, 0, 0, 0 },
62505
    { { MNEM, OP (G), ' ', OP (BITBASE16_16_U8), '[', 's', 'b', ']', 0 } },
62506
    & ifmt_bxor16_X_bit16_16_bit16_16_8_SB_relative, { 0x7eaa00 }
62507
  },
62508
/* bnot${G} ${BitBase16-16-s8}[fb] */
62509
  {
62510
    { 0, 0, 0, 0 },
62511
    { { MNEM, OP (G), ' ', OP (BITBASE16_16_S8), '[', 'f', 'b', ']', 0 } },
62512
    & ifmt_bxor16_X_bit16_16_bit16_16_8_FB_relative, { 0x7eab00 }
62513
  },
62514
/* bnot${S} ${BitBase16-8-u11-S}[sb] */
62515
  {
62516
    { 0, 0, 0, 0 },
62517
    { { MNEM, OP (S), ' ', OP (BITBASE16_8_U11_S), '[', 's', 'b', ']', 0 } },
62518
    & ifmt_btst16_S_bit16_11_S_bit16_11_SB_relative_S, { 0x5000 }
62519
  },
62520
/* bnot${G} ${Dsp-16-u16}[$Bit16An] */
62521
  {
62522
    { 0, 0, 0, 0 },
62523
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (BIT16AN), ']', 0 } },
62524
    & ifmt_bxor16_X_bit16_16_bit16_16_16_An_relative, { 0x7eac0000 }
62525
  },
62526
/* bnot${G} ${BitBase16-16-u16}[sb] */
62527
  {
62528
    { 0, 0, 0, 0 },
62529
    { { MNEM, OP (G), ' ', OP (BITBASE16_16_U16), '[', 's', 'b', ']', 0 } },
62530
    & ifmt_bxor16_X_bit16_16_bit16_16_16_SB_relative, { 0x7eae0000 }
62531
  },
62532
/* bnot${G} ${BitBase16-16-u16} */
62533
  {
62534
    { 0, 0, 0, 0 },
62535
    { { MNEM, OP (G), ' ', OP (BITBASE16_16_U16), 0 } },
62536
    & ifmt_bxor16_X_bit16_16_bit16_16_16_absolute, { 0x7eaf0000 }
62537
  },
62538
/* bnot${G} [$Bit16An] */
62539
  {
62540
    { 0, 0, 0, 0 },
62541
    { { MNEM, OP (G), ' ', '[', OP (BIT16AN), ']', 0 } },
62542
    & ifmt_bxor16_X_bit16_16_bit16_An_indirect, { 0x7ea6 }
62543
  },
62544
/* bnor${X} $Bitno32Prefixed,$Bit32RnPrefixed */
62545
  {
62546
    { 0, 0, 0, 0 },
62547
    { { MNEM, OP (X), ' ', OP (BITNO32PREFIXED), ',', OP (BIT32RNPREFIXED), 0 } },
62548
    & ifmt_bxor32_X_bit32_24_Prefixed_bit32_Rn_direct_Prefixed, { 0x1d830 }
62549
  },
62550
/* bnor${X} $Bitno32Prefixed,$Bit32AnPrefixed */
62551
  {
62552
    { 0, 0, 0, 0 },
62553
    { { MNEM, OP (X), ' ', OP (BITNO32PREFIXED), ',', OP (BIT32ANPREFIXED), 0 } },
62554
    & ifmt_bxor32_X_bit32_24_Prefixed_bit32_An_direct_Prefixed, { 0x1d0b0 }
62555
  },
62556
/* bnor${X} $Bitno32Prefixed,[$Bit32AnPrefixed] */
62557
  {
62558
    { 0, 0, 0, 0 },
62559
    { { MNEM, OP (X), ' ', OP (BITNO32PREFIXED), ',', '[', OP (BIT32ANPREFIXED), ']', 0 } },
62560
    & ifmt_bxor32_X_bit32_24_Prefixed_bit32_An_indirect_Prefixed, { 0x1d030 }
62561
  },
62562
/* bnor${X} ${BitBase32-24-u11-Prefixed}[$Bit32AnPrefixed] */
62563
  {
62564
    { 0, 0, 0, 0 },
62565
    { { MNEM, OP (X), ' ', OP (BITBASE32_24_U11_PREFIXED), '[', OP (BIT32ANPREFIXED), ']', 0 } },
62566
    & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_An_relative_Prefixed, { 0x1d23000 }
62567
  },
62568
/* bnor${X} ${BitBase32-24-u19-Prefixed}[$Bit32AnPrefixed] */
62569
  {
62570
    { 0, 0, 0, 0 },
62571
    { { MNEM, OP (X), ' ', OP (BITBASE32_24_U19_PREFIXED), '[', OP (BIT32ANPREFIXED), ']', 0 } },
62572
    & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_An_relative_Prefixed, { 0x1d43000 }
62573
  },
62574
/* bnor${X} ${BitBase32-24-u27-Prefixed}[$Bit32AnPrefixed] */
62575
  {
62576
    { 0, 0, 0, 0 },
62577
    { { MNEM, OP (X), ' ', OP (BITBASE32_24_U27_PREFIXED), '[', OP (BIT32ANPREFIXED), ']', 0 } },
62578
    & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_27_An_relative_Prefixed, { 0x1d63000 }
62579
  },
62580
/* bnor${X} ${BitBase32-24-u11-Prefixed}[sb] */
62581
  {
62582
    { 0, 0, 0, 0 },
62583
    { { MNEM, OP (X), ' ', OP (BITBASE32_24_U11_PREFIXED), '[', 's', 'b', ']', 0 } },
62584
    & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_SB_relative_Prefixed, { 0x1d2b000 }
62585
  },
62586
/* bnor${X} ${BitBase32-24-u19-Prefixed}[sb] */
62587
  {
62588
    { 0, 0, 0, 0 },
62589
    { { MNEM, OP (X), ' ', OP (BITBASE32_24_U19_PREFIXED), '[', 's', 'b', ']', 0 } },
62590
    & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_SB_relative_Prefixed, { 0x1d4b000 }
62591
  },
62592
/* bnor${X} ${BitBase32-24-s11-Prefixed}[fb] */
62593
  {
62594
    { 0, 0, 0, 0 },
62595
    { { MNEM, OP (X), ' ', OP (BITBASE32_24_S11_PREFIXED), '[', 'f', 'b', ']', 0 } },
62596
    & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_FB_relative_Prefixed, { 0x1d2f000 }
62597
  },
62598
/* bnor${X} ${BitBase32-24-s19-Prefixed}[fb] */
62599
  {
62600
    { 0, 0, 0, 0 },
62601
    { { MNEM, OP (X), ' ', OP (BITBASE32_24_S19_PREFIXED), '[', 'f', 'b', ']', 0 } },
62602
    & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_FB_relative_Prefixed, { 0x1d4f000 }
62603
  },
62604
/* bnor${X} ${BitBase32-24-u19-Prefixed} */
62605
  {
62606
    { 0, 0, 0, 0 },
62607
    { { MNEM, OP (X), ' ', OP (BITBASE32_24_U19_PREFIXED), 0 } },
62608
    & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_absolute_Prefixed, { 0x1d6f000 }
62609
  },
62610
/* bnor${X} ${BitBase32-24-u27-Prefixed} */
62611
  {
62612
    { 0, 0, 0, 0 },
62613
    { { MNEM, OP (X), ' ', OP (BITBASE32_24_U27_PREFIXED), 0 } },
62614
    & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_27_absolute_Prefixed, { 0x1d6b000 }
62615
  },
62616
/* bnor${X} $Bitno16R,$Bit16Rn */
62617
  {
62618
    { 0, 0, 0, 0 },
62619
    { { MNEM, OP (X), ' ', OP (BITNO16R), ',', OP (BIT16RN), 0 } },
62620
    & ifmt_bxor16_X_bit16_16_bit16_Rn_direct, { 0x7e7000 }
62621
  },
62622
/* bnor${X} $Bitno16R,$Bit16An */
62623
  {
62624
    { 0, 0, 0, 0 },
62625
    { { MNEM, OP (X), ' ', OP (BITNO16R), ',', OP (BIT16AN), 0 } },
62626
    & ifmt_bxor16_X_bit16_16_bit16_An_direct, { 0x7e7400 }
62627
  },
62628
/* bnor${X} [$Bit16An] */
62629
  {
62630
    { 0, 0, 0, 0 },
62631
    { { MNEM, OP (X), ' ', '[', OP (BIT16AN), ']', 0 } },
62632
    & ifmt_bxor16_X_bit16_16_bit16_An_indirect, { 0x7e76 }
62633
  },
62634
/* bnor${X} ${Dsp-16-u8}[$Bit16An] */
62635
  {
62636
    { 0, 0, 0, 0 },
62637
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (BIT16AN), ']', 0 } },
62638
    & ifmt_bxor16_X_bit16_16_bit16_16_8_An_relative, { 0x7e7800 }
62639
  },
62640
/* bnor${X} ${Dsp-16-u16}[$Bit16An] */
62641
  {
62642
    { 0, 0, 0, 0 },
62643
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (BIT16AN), ']', 0 } },
62644
    & ifmt_bxor16_X_bit16_16_bit16_16_16_An_relative, { 0x7e7c0000 }
62645
  },
62646
/* bnor${X} ${BitBase16-16-u8}[sb] */
62647
  {
62648
    { 0, 0, 0, 0 },
62649
    { { MNEM, OP (X), ' ', OP (BITBASE16_16_U8), '[', 's', 'b', ']', 0 } },
62650
    & ifmt_bxor16_X_bit16_16_bit16_16_8_SB_relative, { 0x7e7a00 }
62651
  },
62652
/* bnor${X} ${BitBase16-16-u16}[sb] */
62653
  {
62654
    { 0, 0, 0, 0 },
62655
    { { MNEM, OP (X), ' ', OP (BITBASE16_16_U16), '[', 's', 'b', ']', 0 } },
62656
    & ifmt_bxor16_X_bit16_16_bit16_16_16_SB_relative, { 0x7e7e0000 }
62657
  },
62658
/* bnor${X} ${BitBase16-16-s8}[fb] */
62659
  {
62660
    { 0, 0, 0, 0 },
62661
    { { MNEM, OP (X), ' ', OP (BITBASE16_16_S8), '[', 'f', 'b', ']', 0 } },
62662
    & ifmt_bxor16_X_bit16_16_bit16_16_8_FB_relative, { 0x7e7b00 }
62663
  },
62664
/* bnor${X} ${BitBase16-16-u16} */
62665
  {
62666
    { 0, 0, 0, 0 },
62667
    { { MNEM, OP (X), ' ', OP (BITBASE16_16_U16), 0 } },
62668
    & ifmt_bxor16_X_bit16_16_bit16_16_16_absolute, { 0x7e7f0000 }
62669
  },
62670
/* bnand${X} $Bitno32Prefixed,$Bit32RnPrefixed */
62671
  {
62672
    { 0, 0, 0, 0 },
62673
    { { MNEM, OP (X), ' ', OP (BITNO32PREFIXED), ',', OP (BIT32RNPREFIXED), 0 } },
62674
    & ifmt_bxor32_X_bit32_24_Prefixed_bit32_Rn_direct_Prefixed, { 0x1d818 }
62675
  },
62676
/* bnand${X} $Bitno32Prefixed,$Bit32AnPrefixed */
62677
  {
62678
    { 0, 0, 0, 0 },
62679
    { { MNEM, OP (X), ' ', OP (BITNO32PREFIXED), ',', OP (BIT32ANPREFIXED), 0 } },
62680
    & ifmt_bxor32_X_bit32_24_Prefixed_bit32_An_direct_Prefixed, { 0x1d098 }
62681
  },
62682
/* bnand${X} $Bitno32Prefixed,[$Bit32AnPrefixed] */
62683
  {
62684
    { 0, 0, 0, 0 },
62685
    { { MNEM, OP (X), ' ', OP (BITNO32PREFIXED), ',', '[', OP (BIT32ANPREFIXED), ']', 0 } },
62686
    & ifmt_bxor32_X_bit32_24_Prefixed_bit32_An_indirect_Prefixed, { 0x1d018 }
62687
  },
62688
/* bnand${X} ${BitBase32-24-u11-Prefixed}[$Bit32AnPrefixed] */
62689
  {
62690
    { 0, 0, 0, 0 },
62691
    { { MNEM, OP (X), ' ', OP (BITBASE32_24_U11_PREFIXED), '[', OP (BIT32ANPREFIXED), ']', 0 } },
62692
    & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_An_relative_Prefixed, { 0x1d21800 }
62693
  },
62694
/* bnand${X} ${BitBase32-24-u19-Prefixed}[$Bit32AnPrefixed] */
62695
  {
62696
    { 0, 0, 0, 0 },
62697
    { { MNEM, OP (X), ' ', OP (BITBASE32_24_U19_PREFIXED), '[', OP (BIT32ANPREFIXED), ']', 0 } },
62698
    & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_An_relative_Prefixed, { 0x1d41800 }
62699
  },
62700
/* bnand${X} ${BitBase32-24-u27-Prefixed}[$Bit32AnPrefixed] */
62701
  {
62702
    { 0, 0, 0, 0 },
62703
    { { MNEM, OP (X), ' ', OP (BITBASE32_24_U27_PREFIXED), '[', OP (BIT32ANPREFIXED), ']', 0 } },
62704
    & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_27_An_relative_Prefixed, { 0x1d61800 }
62705
  },
62706
/* bnand${X} ${BitBase32-24-u11-Prefixed}[sb] */
62707
  {
62708
    { 0, 0, 0, 0 },
62709
    { { MNEM, OP (X), ' ', OP (BITBASE32_24_U11_PREFIXED), '[', 's', 'b', ']', 0 } },
62710
    & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_SB_relative_Prefixed, { 0x1d29800 }
62711
  },
62712
/* bnand${X} ${BitBase32-24-u19-Prefixed}[sb] */
62713
  {
62714
    { 0, 0, 0, 0 },
62715
    { { MNEM, OP (X), ' ', OP (BITBASE32_24_U19_PREFIXED), '[', 's', 'b', ']', 0 } },
62716
    & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_SB_relative_Prefixed, { 0x1d49800 }
62717
  },
62718
/* bnand${X} ${BitBase32-24-s11-Prefixed}[fb] */
62719
  {
62720
    { 0, 0, 0, 0 },
62721
    { { MNEM, OP (X), ' ', OP (BITBASE32_24_S11_PREFIXED), '[', 'f', 'b', ']', 0 } },
62722
    & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_FB_relative_Prefixed, { 0x1d2d800 }
62723
  },
62724
/* bnand${X} ${BitBase32-24-s19-Prefixed}[fb] */
62725
  {
62726
    { 0, 0, 0, 0 },
62727
    { { MNEM, OP (X), ' ', OP (BITBASE32_24_S19_PREFIXED), '[', 'f', 'b', ']', 0 } },
62728
    & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_FB_relative_Prefixed, { 0x1d4d800 }
62729
  },
62730
/* bnand${X} ${BitBase32-24-u19-Prefixed} */
62731
  {
62732
    { 0, 0, 0, 0 },
62733
    { { MNEM, OP (X), ' ', OP (BITBASE32_24_U19_PREFIXED), 0 } },
62734
    & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_absolute_Prefixed, { 0x1d6d800 }
62735
  },
62736
/* bnand${X} ${BitBase32-24-u27-Prefixed} */
62737
  {
62738
    { 0, 0, 0, 0 },
62739
    { { MNEM, OP (X), ' ', OP (BITBASE32_24_U27_PREFIXED), 0 } },
62740
    & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_27_absolute_Prefixed, { 0x1d69800 }
62741
  },
62742
/* bnand${X} $Bitno16R,$Bit16Rn */
62743
  {
62744
    { 0, 0, 0, 0 },
62745
    { { MNEM, OP (X), ' ', OP (BITNO16R), ',', OP (BIT16RN), 0 } },
62746
    & ifmt_bxor16_X_bit16_16_bit16_Rn_direct, { 0x7e5000 }
62747
  },
62748
/* bnand${X} $Bitno16R,$Bit16An */
62749
  {
62750
    { 0, 0, 0, 0 },
62751
    { { MNEM, OP (X), ' ', OP (BITNO16R), ',', OP (BIT16AN), 0 } },
62752
    & ifmt_bxor16_X_bit16_16_bit16_An_direct, { 0x7e5400 }
62753
  },
62754
/* bnand${X} [$Bit16An] */
62755
  {
62756
    { 0, 0, 0, 0 },
62757
    { { MNEM, OP (X), ' ', '[', OP (BIT16AN), ']', 0 } },
62758
    & ifmt_bxor16_X_bit16_16_bit16_An_indirect, { 0x7e56 }
62759
  },
62760
/* bnand${X} ${Dsp-16-u8}[$Bit16An] */
62761
  {
62762
    { 0, 0, 0, 0 },
62763
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (BIT16AN), ']', 0 } },
62764
    & ifmt_bxor16_X_bit16_16_bit16_16_8_An_relative, { 0x7e5800 }
62765
  },
62766
/* bnand${X} ${Dsp-16-u16}[$Bit16An] */
62767
  {
62768
    { 0, 0, 0, 0 },
62769
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (BIT16AN), ']', 0 } },
62770
    & ifmt_bxor16_X_bit16_16_bit16_16_16_An_relative, { 0x7e5c0000 }
62771
  },
62772
/* bnand${X} ${BitBase16-16-u8}[sb] */
62773
  {
62774
    { 0, 0, 0, 0 },
62775
    { { MNEM, OP (X), ' ', OP (BITBASE16_16_U8), '[', 's', 'b', ']', 0 } },
62776
    & ifmt_bxor16_X_bit16_16_bit16_16_8_SB_relative, { 0x7e5a00 }
62777
  },
62778
/* bnand${X} ${BitBase16-16-u16}[sb] */
62779
  {
62780
    { 0, 0, 0, 0 },
62781
    { { MNEM, OP (X), ' ', OP (BITBASE16_16_U16), '[', 's', 'b', ']', 0 } },
62782
    & ifmt_bxor16_X_bit16_16_bit16_16_16_SB_relative, { 0x7e5e0000 }
62783
  },
62784
/* bnand${X} ${BitBase16-16-s8}[fb] */
62785
  {
62786
    { 0, 0, 0, 0 },
62787
    { { MNEM, OP (X), ' ', OP (BITBASE16_16_S8), '[', 'f', 'b', ']', 0 } },
62788
    & ifmt_bxor16_X_bit16_16_bit16_16_8_FB_relative, { 0x7e5b00 }
62789
  },
62790
/* bnand${X} ${BitBase16-16-u16} */
62791
  {
62792
    { 0, 0, 0, 0 },
62793
    { { MNEM, OP (X), ' ', OP (BITBASE16_16_U16), 0 } },
62794
    & ifmt_bxor16_X_bit16_16_bit16_16_16_absolute, { 0x7e5f0000 }
62795
  },
62796
/* bm${cond32-16} $Bitno32Unprefixed,$Bit32RnUnprefixed */
62797
  {
62798
    { 0, 0, 0, 0 },
62799
    { { MNEM, OP (COND32_16), ' ', OP (BITNO32UNPREFIXED), ',', OP (BIT32RNUNPREFIXED), 0 } },
62800
    & ifmt_bm32_bit32_basic_Unprefixed_cond32_16_bit32_Rn_direct_Unprefixed, { 0xd81000 }
62801
  },
62802
/* bm${cond32-16} $Bitno32Unprefixed,$Bit32AnUnprefixed */
62803
  {
62804
    { 0, 0, 0, 0 },
62805
    { { MNEM, OP (COND32_16), ' ', OP (BITNO32UNPREFIXED), ',', OP (BIT32ANUNPREFIXED), 0 } },
62806
    & ifmt_bm32_bit32_basic_Unprefixed_cond32_16_bit32_An_direct_Unprefixed, { 0xd09000 }
62807
  },
62808
/* bm${cond32-16} $Bitno32Unprefixed,[$Bit32AnUnprefixed] */
62809
  {
62810
    { 0, 0, 0, 0 },
62811
    { { MNEM, OP (COND32_16), ' ', OP (BITNO32UNPREFIXED), ',', '[', OP (BIT32ANUNPREFIXED), ']', 0 } },
62812
    & ifmt_bm32_bit32_basic_Unprefixed_cond32_16_bit32_An_indirect_Unprefixed, { 0xd01000 }
62813
  },
62814
/* bm${cond32-24} ${BitBase32-16-u11-Unprefixed}[$Bit32AnUnprefixed] */
62815
  {
62816
    { 0, 0, 0, 0 },
62817
    { { MNEM, OP (COND32_24), ' ', OP (BITBASE32_16_U11_UNPREFIXED), '[', OP (BIT32ANUNPREFIXED), ']', 0 } },
62818
    & ifmt_bm32_bit32_16_8_Unprefixed_cond32_24_bit32_16_11_An_relative_Unprefixed, { 0xd2100000 }
62819
  },
62820
/* bm${cond32-24} ${BitBase32-16-u11-Unprefixed}[sb] */
62821
  {
62822
    { 0, 0, 0, 0 },
62823
    { { MNEM, OP (COND32_24), ' ', OP (BITBASE32_16_U11_UNPREFIXED), '[', 's', 'b', ']', 0 } },
62824
    & ifmt_bm32_bit32_16_8_Unprefixed_cond32_24_bit32_16_11_SB_relative_Unprefixed, { 0xd2900000 }
62825
  },
62826
/* bm${cond32-24} ${BitBase32-16-s11-Unprefixed}[fb] */
62827
  {
62828
    { 0, 0, 0, 0 },
62829
    { { MNEM, OP (COND32_24), ' ', OP (BITBASE32_16_S11_UNPREFIXED), '[', 'f', 'b', ']', 0 } },
62830
    & ifmt_bm32_bit32_16_8_Unprefixed_cond32_24_bit32_16_11_FB_relative_Unprefixed, { 0xd2d00000 }
62831
  },
62832
/* bm${cond32-32} ${BitBase32-16-u19-Unprefixed}[$Bit32AnUnprefixed] */
62833
  {
62834
    { 0, 0, 0, 0 },
62835
    { { MNEM, OP (COND32_32), ' ', OP (BITBASE32_16_U19_UNPREFIXED), '[', OP (BIT32ANUNPREFIXED), ']', 0 } },
62836
    & ifmt_bm32_bit32_16_16_Unprefixed_cond32_32_bit32_16_19_An_relative_Unprefixed, { 0xd4100000 }
62837
  },
62838
/* bm${cond32-32} ${BitBase32-16-u19-Unprefixed}[sb] */
62839
  {
62840
    { 0, 0, 0, 0 },
62841
    { { MNEM, OP (COND32_32), ' ', OP (BITBASE32_16_U19_UNPREFIXED), '[', 's', 'b', ']', 0 } },
62842
    & ifmt_bm32_bit32_16_16_Unprefixed_cond32_32_bit32_16_19_SB_relative_Unprefixed, { 0xd4900000 }
62843
  },
62844
/* bm${cond32-32} ${BitBase32-16-s19-Unprefixed}[fb] */
62845
  {
62846
    { 0, 0, 0, 0 },
62847
    { { MNEM, OP (COND32_32), ' ', OP (BITBASE32_16_S19_UNPREFIXED), '[', 'f', 'b', ']', 0 } },
62848
    & ifmt_bm32_bit32_16_16_Unprefixed_cond32_32_bit32_16_19_FB_relative_Unprefixed, { 0xd4d00000 }
62849
  },
62850
/* bm${cond32-32} ${BitBase32-16-u19-Unprefixed} */
62851
  {
62852
    { 0, 0, 0, 0 },
62853
    { { MNEM, OP (COND32_32), ' ', OP (BITBASE32_16_U19_UNPREFIXED), 0 } },
62854
    & ifmt_bm32_bit32_16_16_Unprefixed_cond32_32_bit32_16_19_absolute_Unprefixed, { 0xd6d00000 }
62855
  },
62856
/* bm${cond32-40} ${BitBase32-16-u27-Unprefixed}[$Bit32AnUnprefixed] */
62857
  {
62858
    { 0, 0, 0, 0 },
62859
    { { MNEM, OP (COND32_40), ' ', OP (BITBASE32_16_U27_UNPREFIXED), '[', OP (BIT32ANUNPREFIXED), ']', 0 } },
62860
    & ifmt_bm32_bit32_16_24_Unprefixed_cond32_40_bit32_16_27_An_relative_Unprefixed, { 0xd6100000 }
62861
  },
62862
/* bm${cond32-40} ${BitBase32-16-u27-Unprefixed} */
62863
  {
62864
    { 0, 0, 0, 0 },
62865
    { { MNEM, OP (COND32_40), ' ', OP (BITBASE32_16_U27_UNPREFIXED), 0 } },
62866
    & ifmt_bm32_bit32_16_24_Unprefixed_cond32_40_bit32_16_27_absolute_Unprefixed, { 0xd6900000 }
62867
  },
62868
/* bm${cond16-24} $Bitno16R,$Bit16Rn */
62869
  {
62870
    { 0, 0, 0, 0 },
62871
    { { MNEM, OP (COND16_24), ' ', OP (BITNO16R), ',', OP (BIT16RN), 0 } },
62872
    & ifmt_bm16_bit16_16_8_cond16_24_bit16_Rn_direct, { 0x7e200000 }
62873
  },
62874
/* bm${cond16-24} $Bitno16R,$Bit16An */
62875
  {
62876
    { 0, 0, 0, 0 },
62877
    { { MNEM, OP (COND16_24), ' ', OP (BITNO16R), ',', OP (BIT16AN), 0 } },
62878
    & ifmt_bm16_bit16_16_8_cond16_24_bit16_An_direct, { 0x7e240000 }
62879
  },
62880
/* bm${cond16-24} ${Dsp-16-u8}[$Bit16An] */
62881
  {
62882
    { 0, 0, 0, 0 },
62883
    { { MNEM, OP (COND16_24), ' ', OP (DSP_16_U8), '[', OP (BIT16AN), ']', 0 } },
62884
    & ifmt_bm16_bit16_16_8_cond16_24_bit16_16_8_An_relative, { 0x7e280000 }
62885
  },
62886
/* bm${cond16-24} ${BitBase16-16-u8}[sb] */
62887
  {
62888
    { 0, 0, 0, 0 },
62889
    { { MNEM, OP (COND16_24), ' ', OP (BITBASE16_16_U8), '[', 's', 'b', ']', 0 } },
62890
    & ifmt_bm16_bit16_16_8_cond16_24_bit16_16_8_SB_relative, { 0x7e2a0000 }
62891
  },
62892
/* bm${cond16-24} ${BitBase16-16-s8}[fb] */
62893
  {
62894
    { 0, 0, 0, 0 },
62895
    { { MNEM, OP (COND16_24), ' ', OP (BITBASE16_16_S8), '[', 'f', 'b', ']', 0 } },
62896
    & ifmt_bm16_bit16_16_8_cond16_24_bit16_16_8_FB_relative, { 0x7e2b0000 }
62897
  },
62898
/* bm${cond16-32} ${Dsp-16-u16}[$Bit16An] */
62899
  {
62900
    { 0, 0, 0, 0 },
62901
    { { MNEM, OP (COND16_32), ' ', OP (DSP_16_U16), '[', OP (BIT16AN), ']', 0 } },
62902
    & ifmt_bm16_bit16_16_16_cond16_32_bit16_16_16_An_relative, { 0x7e2c0000 }
62903
  },
62904
/* bm${cond16-32} ${BitBase16-16-u16}[sb] */
62905
  {
62906
    { 0, 0, 0, 0 },
62907
    { { MNEM, OP (COND16_32), ' ', OP (BITBASE16_16_U16), '[', 's', 'b', ']', 0 } },
62908
    & ifmt_bm16_bit16_16_16_cond16_32_bit16_16_16_SB_relative, { 0x7e2e0000 }
62909
  },
62910
/* bm${cond16-32} ${BitBase16-16-u16} */
62911
  {
62912
    { 0, 0, 0, 0 },
62913
    { { MNEM, OP (COND16_32), ' ', OP (BITBASE16_16_U16), 0 } },
62914
    & ifmt_bm16_bit16_16_16_cond16_32_bit16_16_16_absolute, { 0x7e2f0000 }
62915
  },
62916
/* bm${cond16-16} [$Bit16An] */
62917
  {
62918
    { 0, 0, 0, 0 },
62919
    { { MNEM, OP (COND16_16), ' ', '[', OP (BIT16AN), ']', 0 } },
62920
    & ifmt_bm16_bit16_16_basic_cond16_16_bit16_An_indirect, { 0x7e2600 }
62921
  },
62922
/* bitindex.w $Dst32RnUnprefixedHI */
62923
  {
62924
    { 0, 0, 0, 0 },
62925
    { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } },
62926
    & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xc92e }
62927
  },
62928
/* bitindex.w $Dst32AnUnprefixedHI */
62929
  {
62930
    { 0, 0, 0, 0 },
62931
    { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } },
62932
    & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xc1ae }
62933
  },
62934
/* bitindex.w [$Dst32AnUnprefixed] */
62935
  {
62936
    { 0, 0, 0, 0 },
62937
    { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
62938
    & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xc12e }
62939
  },
62940
/* bitindex.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
62941
  {
62942
    { 0, 0, 0, 0 },
62943
    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
62944
    & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xc32e00 }
62945
  },
62946
/* bitindex.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
62947
  {
62948
    { 0, 0, 0, 0 },
62949
    { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
62950
    & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xc52e0000 }
62951
  },
62952
/* bitindex.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
62953
  {
62954
    { 0, 0, 0, 0 },
62955
    { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
62956
    & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xc72e0000 }
62957
  },
62958
/* bitindex.w ${Dsp-16-u8}[sb] */
62959
  {
62960
    { 0, 0, 0, 0 },
62961
    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
62962
    & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xc3ae00 }
62963
  },
62964
/* bitindex.w ${Dsp-16-u16}[sb] */
62965
  {
62966
    { 0, 0, 0, 0 },
62967
    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
62968
    & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xc5ae0000 }
62969
  },
62970
/* bitindex.w ${Dsp-16-s8}[fb] */
62971
  {
62972
    { 0, 0, 0, 0 },
62973
    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
62974
    & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xc3ee00 }
62975
  },
62976
/* bitindex.w ${Dsp-16-s16}[fb] */
62977
  {
62978
    { 0, 0, 0, 0 },
62979
    { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
62980
    & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xc5ee0000 }
62981
  },
62982
/* bitindex.w ${Dsp-16-u16} */
62983
  {
62984
    { 0, 0, 0, 0 },
62985
    { { MNEM, ' ', OP (DSP_16_U16), 0 } },
62986
    & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xc7ee0000 }
62987
  },
62988
/* bitindex.w ${Dsp-16-u24} */
62989
  {
62990
    { 0, 0, 0, 0 },
62991
    { { MNEM, ' ', OP (DSP_16_U24), 0 } },
62992
    & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xc7ae0000 }
62993
  },
62994
/* bitindex.b $Dst32RnUnprefixedQI */
62995
  {
62996
    { 0, 0, 0, 0 },
62997
    { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } },
62998
    & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0xc82e }
62999
  },
63000
/* bitindex.b $Dst32AnUnprefixedQI */
63001
  {
63002
    { 0, 0, 0, 0 },
63003
    { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } },
63004
    & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0xc0ae }
63005
  },
63006
/* bitindex.b [$Dst32AnUnprefixed] */
63007
  {
63008
    { 0, 0, 0, 0 },
63009
    { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63010
    & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0xc02e }
63011
  },
63012
/* bitindex.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
63013
  {
63014
    { 0, 0, 0, 0 },
63015
    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63016
    & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0xc22e00 }
63017
  },
63018
/* bitindex.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
63019
  {
63020
    { 0, 0, 0, 0 },
63021
    { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63022
    & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0xc42e0000 }
63023
  },
63024
/* bitindex.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
63025
  {
63026
    { 0, 0, 0, 0 },
63027
    { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63028
    & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0xc62e0000 }
63029
  },
63030
/* bitindex.b ${Dsp-16-u8}[sb] */
63031
  {
63032
    { 0, 0, 0, 0 },
63033
    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
63034
    & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0xc2ae00 }
63035
  },
63036
/* bitindex.b ${Dsp-16-u16}[sb] */
63037
  {
63038
    { 0, 0, 0, 0 },
63039
    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
63040
    & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0xc4ae0000 }
63041
  },
63042
/* bitindex.b ${Dsp-16-s8}[fb] */
63043
  {
63044
    { 0, 0, 0, 0 },
63045
    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
63046
    & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0xc2ee00 }
63047
  },
63048
/* bitindex.b ${Dsp-16-s16}[fb] */
63049
  {
63050
    { 0, 0, 0, 0 },
63051
    { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
63052
    & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0xc4ee0000 }
63053
  },
63054
/* bitindex.b ${Dsp-16-u16} */
63055
  {
63056
    { 0, 0, 0, 0 },
63057
    { { MNEM, ' ', OP (DSP_16_U16), 0 } },
63058
    & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0xc6ee0000 }
63059
  },
63060
/* bitindex.b ${Dsp-16-u24} */
63061
  {
63062
    { 0, 0, 0, 0 },
63063
    { { MNEM, ' ', OP (DSP_16_U24), 0 } },
63064
    & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0xc6ae0000 }
63065
  },
63066
/* bclr${X} $Bitno32Unprefixed,$Bit32RnUnprefixed */
63067
  {
63068
    { 0, 0, 0, 0 },
63069
    { { MNEM, OP (X), ' ', OP (BITNO32UNPREFIXED), ',', OP (BIT32RNUNPREFIXED), 0 } },
63070
    & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_Rn_direct_Unprefixed, { 0xd830 }
63071
  },
63072
/* bclr${X} $Bitno32Unprefixed,$Bit32AnUnprefixed */
63073
  {
63074
    { 0, 0, 0, 0 },
63075
    { { MNEM, OP (X), ' ', OP (BITNO32UNPREFIXED), ',', OP (BIT32ANUNPREFIXED), 0 } },
63076
    & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_An_direct_Unprefixed, { 0xd0b0 }
63077
  },
63078
/* bclr${X} $Bitno32Unprefixed,[$Bit32AnUnprefixed] */
63079
  {
63080
    { 0, 0, 0, 0 },
63081
    { { MNEM, OP (X), ' ', OP (BITNO32UNPREFIXED), ',', '[', OP (BIT32ANUNPREFIXED), ']', 0 } },
63082
    & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_An_indirect_Unprefixed, { 0xd030 }
63083
  },
63084
/* bclr${X} ${BitBase32-16-u11-Unprefixed}[$Bit32AnUnprefixed] */
63085
  {
63086
    { 0, 0, 0, 0 },
63087
    { { MNEM, OP (X), ' ', OP (BITBASE32_16_U11_UNPREFIXED), '[', OP (BIT32ANUNPREFIXED), ']', 0 } },
63088
    & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_11_An_relative_Unprefixed, { 0xd23000 }
63089
  },
63090
/* bclr${X} ${BitBase32-16-u19-Unprefixed}[$Bit32AnUnprefixed] */
63091
  {
63092
    { 0, 0, 0, 0 },
63093
    { { MNEM, OP (X), ' ', OP (BITBASE32_16_U19_UNPREFIXED), '[', OP (BIT32ANUNPREFIXED), ']', 0 } },
63094
    & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_An_relative_Unprefixed, { 0xd4300000 }
63095
  },
63096
/* bclr${X} ${BitBase32-16-u27-Unprefixed}[$Bit32AnUnprefixed] */
63097
  {
63098
    { 0, 0, 0, 0 },
63099
    { { MNEM, OP (X), ' ', OP (BITBASE32_16_U27_UNPREFIXED), '[', OP (BIT32ANUNPREFIXED), ']', 0 } },
63100
    & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_27_An_relative_Unprefixed, { 0xd6300000 }
63101
  },
63102
/* bclr${X} ${BitBase32-16-u11-Unprefixed}[sb] */
63103
  {
63104
    { 0, 0, 0, 0 },
63105
    { { MNEM, OP (X), ' ', OP (BITBASE32_16_U11_UNPREFIXED), '[', 's', 'b', ']', 0 } },
63106
    & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_11_SB_relative_Unprefixed, { 0xd2b000 }
63107
  },
63108
/* bclr${X} ${BitBase32-16-u19-Unprefixed}[sb] */
63109
  {
63110
    { 0, 0, 0, 0 },
63111
    { { MNEM, OP (X), ' ', OP (BITBASE32_16_U19_UNPREFIXED), '[', 's', 'b', ']', 0 } },
63112
    & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_SB_relative_Unprefixed, { 0xd4b00000 }
63113
  },
63114
/* bclr${X} ${BitBase32-16-s11-Unprefixed}[fb] */
63115
  {
63116
    { 0, 0, 0, 0 },
63117
    { { MNEM, OP (X), ' ', OP (BITBASE32_16_S11_UNPREFIXED), '[', 'f', 'b', ']', 0 } },
63118
    & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_11_FB_relative_Unprefixed, { 0xd2f000 }
63119
  },
63120
/* bclr${X} ${BitBase32-16-s19-Unprefixed}[fb] */
63121
  {
63122
    { 0, 0, 0, 0 },
63123
    { { MNEM, OP (X), ' ', OP (BITBASE32_16_S19_UNPREFIXED), '[', 'f', 'b', ']', 0 } },
63124
    & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_FB_relative_Unprefixed, { 0xd4f00000 }
63125
  },
63126
/* bclr${X} ${BitBase32-16-u19-Unprefixed} */
63127
  {
63128
    { 0, 0, 0, 0 },
63129
    { { MNEM, OP (X), ' ', OP (BITBASE32_16_U19_UNPREFIXED), 0 } },
63130
    & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_absolute_Unprefixed, { 0xd6f00000 }
63131
  },
63132
/* bclr${X} ${BitBase32-16-u27-Unprefixed} */
63133
  {
63134
    { 0, 0, 0, 0 },
63135
    { { MNEM, OP (X), ' ', OP (BITBASE32_16_U27_UNPREFIXED), 0 } },
63136
    & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_27_absolute_Unprefixed, { 0xd6b00000 }
63137
  },
63138
/* bclr${G} $Bitno16R,$Bit16Rn */
63139
  {
63140
    { 0, 0, 0, 0 },
63141
    { { MNEM, OP (G), ' ', OP (BITNO16R), ',', OP (BIT16RN), 0 } },
63142
    & ifmt_bxor16_X_bit16_16_bit16_Rn_direct, { 0x7e8000 }
63143
  },
63144
/* bclr${G} $Bitno16R,$Bit16An */
63145
  {
63146
    { 0, 0, 0, 0 },
63147
    { { MNEM, OP (G), ' ', OP (BITNO16R), ',', OP (BIT16AN), 0 } },
63148
    & ifmt_bxor16_X_bit16_16_bit16_An_direct, { 0x7e8400 }
63149
  },
63150
/* bclr${G} ${Dsp-16-u8}[$Bit16An] */
63151
  {
63152
    { 0, 0, 0, 0 },
63153
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (BIT16AN), ']', 0 } },
63154
    & ifmt_bxor16_X_bit16_16_bit16_16_8_An_relative, { 0x7e8800 }
63155
  },
63156
/* bclr${G} ${BitBase16-16-u8}[sb] */
63157
  {
63158
    { 0, 0, 0, 0 },
63159
    { { MNEM, OP (G), ' ', OP (BITBASE16_16_U8), '[', 's', 'b', ']', 0 } },
63160
    & ifmt_bxor16_X_bit16_16_bit16_16_8_SB_relative, { 0x7e8a00 }
63161
  },
63162
/* bclr${G} ${BitBase16-16-s8}[fb] */
63163
  {
63164
    { 0, 0, 0, 0 },
63165
    { { MNEM, OP (G), ' ', OP (BITBASE16_16_S8), '[', 'f', 'b', ']', 0 } },
63166
    & ifmt_bxor16_X_bit16_16_bit16_16_8_FB_relative, { 0x7e8b00 }
63167
  },
63168
/* bclr${S} ${BitBase16-8-u11-S}[sb] */
63169
  {
63170
    { 0, 0, 0, 0 },
63171
    { { MNEM, OP (S), ' ', OP (BITBASE16_8_U11_S), '[', 's', 'b', ']', 0 } },
63172
    & ifmt_btst16_S_bit16_11_S_bit16_11_SB_relative_S, { 0x4000 }
63173
  },
63174
/* bclr${G} ${Dsp-16-u16}[$Bit16An] */
63175
  {
63176
    { 0, 0, 0, 0 },
63177
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (BIT16AN), ']', 0 } },
63178
    & ifmt_bxor16_X_bit16_16_bit16_16_16_An_relative, { 0x7e8c0000 }
63179
  },
63180
/* bclr${G} ${BitBase16-16-u16}[sb] */
63181
  {
63182
    { 0, 0, 0, 0 },
63183
    { { MNEM, OP (G), ' ', OP (BITBASE16_16_U16), '[', 's', 'b', ']', 0 } },
63184
    & ifmt_bxor16_X_bit16_16_bit16_16_16_SB_relative, { 0x7e8e0000 }
63185
  },
63186
/* bclr${G} ${BitBase16-16-u16} */
63187
  {
63188
    { 0, 0, 0, 0 },
63189
    { { MNEM, OP (G), ' ', OP (BITBASE16_16_U16), 0 } },
63190
    & ifmt_bxor16_X_bit16_16_bit16_16_16_absolute, { 0x7e8f0000 }
63191
  },
63192
/* bclr${G} [$Bit16An] */
63193
  {
63194
    { 0, 0, 0, 0 },
63195
    { { MNEM, OP (G), ' ', '[', OP (BIT16AN), ']', 0 } },
63196
    & ifmt_bxor16_X_bit16_16_bit16_An_indirect, { 0x7e86 }
63197
  },
63198
/* band${X} $Bitno32Prefixed,$Bit32RnPrefixed */
63199
  {
63200
    { 0, 0, 0, 0 },
63201
    { { MNEM, OP (X), ' ', OP (BITNO32PREFIXED), ',', OP (BIT32RNPREFIXED), 0 } },
63202
    & ifmt_bxor32_X_bit32_24_Prefixed_bit32_Rn_direct_Prefixed, { 0x1d808 }
63203
  },
63204
/* band${X} $Bitno32Prefixed,$Bit32AnPrefixed */
63205
  {
63206
    { 0, 0, 0, 0 },
63207
    { { MNEM, OP (X), ' ', OP (BITNO32PREFIXED), ',', OP (BIT32ANPREFIXED), 0 } },
63208
    & ifmt_bxor32_X_bit32_24_Prefixed_bit32_An_direct_Prefixed, { 0x1d088 }
63209
  },
63210
/* band${X} $Bitno32Prefixed,[$Bit32AnPrefixed] */
63211
  {
63212
    { 0, 0, 0, 0 },
63213
    { { MNEM, OP (X), ' ', OP (BITNO32PREFIXED), ',', '[', OP (BIT32ANPREFIXED), ']', 0 } },
63214
    & ifmt_bxor32_X_bit32_24_Prefixed_bit32_An_indirect_Prefixed, { 0x1d008 }
63215
  },
63216
/* band${X} ${BitBase32-24-u11-Prefixed}[$Bit32AnPrefixed] */
63217
  {
63218
    { 0, 0, 0, 0 },
63219
    { { MNEM, OP (X), ' ', OP (BITBASE32_24_U11_PREFIXED), '[', OP (BIT32ANPREFIXED), ']', 0 } },
63220
    & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_An_relative_Prefixed, { 0x1d20800 }
63221
  },
63222
/* band${X} ${BitBase32-24-u19-Prefixed}[$Bit32AnPrefixed] */
63223
  {
63224
    { 0, 0, 0, 0 },
63225
    { { MNEM, OP (X), ' ', OP (BITBASE32_24_U19_PREFIXED), '[', OP (BIT32ANPREFIXED), ']', 0 } },
63226
    & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_An_relative_Prefixed, { 0x1d40800 }
63227
  },
63228
/* band${X} ${BitBase32-24-u27-Prefixed}[$Bit32AnPrefixed] */
63229
  {
63230
    { 0, 0, 0, 0 },
63231
    { { MNEM, OP (X), ' ', OP (BITBASE32_24_U27_PREFIXED), '[', OP (BIT32ANPREFIXED), ']', 0 } },
63232
    & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_27_An_relative_Prefixed, { 0x1d60800 }
63233
  },
63234
/* band${X} ${BitBase32-24-u11-Prefixed}[sb] */
63235
  {
63236
    { 0, 0, 0, 0 },
63237
    { { MNEM, OP (X), ' ', OP (BITBASE32_24_U11_PREFIXED), '[', 's', 'b', ']', 0 } },
63238
    & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_SB_relative_Prefixed, { 0x1d28800 }
63239
  },
63240
/* band${X} ${BitBase32-24-u19-Prefixed}[sb] */
63241
  {
63242
    { 0, 0, 0, 0 },
63243
    { { MNEM, OP (X), ' ', OP (BITBASE32_24_U19_PREFIXED), '[', 's', 'b', ']', 0 } },
63244
    & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_SB_relative_Prefixed, { 0x1d48800 }
63245
  },
63246
/* band${X} ${BitBase32-24-s11-Prefixed}[fb] */
63247
  {
63248
    { 0, 0, 0, 0 },
63249
    { { MNEM, OP (X), ' ', OP (BITBASE32_24_S11_PREFIXED), '[', 'f', 'b', ']', 0 } },
63250
    & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_FB_relative_Prefixed, { 0x1d2c800 }
63251
  },
63252
/* band${X} ${BitBase32-24-s19-Prefixed}[fb] */
63253
  {
63254
    { 0, 0, 0, 0 },
63255
    { { MNEM, OP (X), ' ', OP (BITBASE32_24_S19_PREFIXED), '[', 'f', 'b', ']', 0 } },
63256
    & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_FB_relative_Prefixed, { 0x1d4c800 }
63257
  },
63258
/* band${X} ${BitBase32-24-u19-Prefixed} */
63259
  {
63260
    { 0, 0, 0, 0 },
63261
    { { MNEM, OP (X), ' ', OP (BITBASE32_24_U19_PREFIXED), 0 } },
63262
    & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_absolute_Prefixed, { 0x1d6c800 }
63263
  },
63264
/* band${X} ${BitBase32-24-u27-Prefixed} */
63265
  {
63266
    { 0, 0, 0, 0 },
63267
    { { MNEM, OP (X), ' ', OP (BITBASE32_24_U27_PREFIXED), 0 } },
63268
    & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_27_absolute_Prefixed, { 0x1d68800 }
63269
  },
63270
/* band${X} $Bitno16R,$Bit16Rn */
63271
  {
63272
    { 0, 0, 0, 0 },
63273
    { { MNEM, OP (X), ' ', OP (BITNO16R), ',', OP (BIT16RN), 0 } },
63274
    & ifmt_bxor16_X_bit16_16_bit16_Rn_direct, { 0x7e4000 }
63275
  },
63276
/* band${X} $Bitno16R,$Bit16An */
63277
  {
63278
    { 0, 0, 0, 0 },
63279
    { { MNEM, OP (X), ' ', OP (BITNO16R), ',', OP (BIT16AN), 0 } },
63280
    & ifmt_bxor16_X_bit16_16_bit16_An_direct, { 0x7e4400 }
63281
  },
63282
/* band${X} [$Bit16An] */
63283
  {
63284
    { 0, 0, 0, 0 },
63285
    { { MNEM, OP (X), ' ', '[', OP (BIT16AN), ']', 0 } },
63286
    & ifmt_bxor16_X_bit16_16_bit16_An_indirect, { 0x7e46 }
63287
  },
63288
/* band${X} ${Dsp-16-u8}[$Bit16An] */
63289
  {
63290
    { 0, 0, 0, 0 },
63291
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (BIT16AN), ']', 0 } },
63292
    & ifmt_bxor16_X_bit16_16_bit16_16_8_An_relative, { 0x7e4800 }
63293
  },
63294
/* band${X} ${Dsp-16-u16}[$Bit16An] */
63295
  {
63296
    { 0, 0, 0, 0 },
63297
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (BIT16AN), ']', 0 } },
63298
    & ifmt_bxor16_X_bit16_16_bit16_16_16_An_relative, { 0x7e4c0000 }
63299
  },
63300
/* band${X} ${BitBase16-16-u8}[sb] */
63301
  {
63302
    { 0, 0, 0, 0 },
63303
    { { MNEM, OP (X), ' ', OP (BITBASE16_16_U8), '[', 's', 'b', ']', 0 } },
63304
    & ifmt_bxor16_X_bit16_16_bit16_16_8_SB_relative, { 0x7e4a00 }
63305
  },
63306
/* band${X} ${BitBase16-16-u16}[sb] */
63307
  {
63308
    { 0, 0, 0, 0 },
63309
    { { MNEM, OP (X), ' ', OP (BITBASE16_16_U16), '[', 's', 'b', ']', 0 } },
63310
    & ifmt_bxor16_X_bit16_16_bit16_16_16_SB_relative, { 0x7e4e0000 }
63311
  },
63312
/* band${X} ${BitBase16-16-s8}[fb] */
63313
  {
63314
    { 0, 0, 0, 0 },
63315
    { { MNEM, OP (X), ' ', OP (BITBASE16_16_S8), '[', 'f', 'b', ']', 0 } },
63316
    & ifmt_bxor16_X_bit16_16_bit16_16_8_FB_relative, { 0x7e4b00 }
63317
  },
63318
/* band${X} ${BitBase16-16-u16} */
63319
  {
63320
    { 0, 0, 0, 0 },
63321
    { { MNEM, OP (X), ' ', OP (BITBASE16_16_U16), 0 } },
63322
    & ifmt_bxor16_X_bit16_16_bit16_16_16_absolute, { 0x7e4f0000 }
63323
  },
63324
/* and.w${S} #${Imm-16-HI},${Dsp-8-u8}[sb] */
63325
  {
63326
    { 0, 0, 0, 0 },
63327
    { { MNEM, OP (S), ' ', '#', OP (IMM_16_HI), ',', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } },
63328
    & ifmt_tst32_w_imm_S_2_S_8_dst32_2_S_8_SB_relative_HI, { 0x6d000000 }
63329
  },
63330
/* and.w${S} #${Imm-16-HI},${Dsp-8-s8}[fb] */
63331
  {
63332
    { 0, 0, 0, 0 },
63333
    { { MNEM, OP (S), ' ', '#', OP (IMM_16_HI), ',', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } },
63334
    & ifmt_tst32_w_imm_S_2_S_8_dst32_2_S_8_FB_relative_HI, { 0x7d000000 }
63335
  },
63336
/* and.w${S} #${Imm-24-HI},${Dsp-8-u16} */
63337
  {
63338
    { 0, 0, 0, 0 },
63339
    { { MNEM, OP (S), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_8_U16), 0 } },
63340
    & ifmt_tst32_w_imm_S_2_S_16_dst32_2_S_16_absolute_HI, { 0x5d000000 }
63341
  },
63342
/* and.w${S} #${Imm-8-HI},r0 */
63343
  {
63344
    { 0, 0, 0, 0 },
63345
    { { MNEM, OP (S), ' ', '#', OP (IMM_8_HI), ',', 'r', '0', 0 } },
63346
    & ifmt_tst32_w_imm_S_2_S_basic_dst32_2_S_R0_direct_HI, { 0x4d0000 }
63347
  },
63348
/* and.b${S} #${Imm-16-QI},${Dsp-8-u8}[sb] */
63349
  {
63350
    { 0, 0, 0, 0 },
63351
    { { MNEM, OP (S), ' ', '#', OP (IMM_16_QI), ',', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } },
63352
    & ifmt_tst32_b_imm_S_2_S_8_dst32_2_S_8_SB_relative_QI, { 0x6c0000 }
63353
  },
63354
/* and.b${S} #${Imm-16-QI},${Dsp-8-s8}[fb] */
63355
  {
63356
    { 0, 0, 0, 0 },
63357
    { { MNEM, OP (S), ' ', '#', OP (IMM_16_QI), ',', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } },
63358
    & ifmt_tst32_b_imm_S_2_S_8_dst32_2_S_8_FB_relative_QI, { 0x7c0000 }
63359
  },
63360
/* and.b${S} #${Imm-24-QI},${Dsp-8-u16} */
63361
  {
63362
    { 0, 0, 0, 0 },
63363
    { { MNEM, OP (S), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_8_U16), 0 } },
63364
    & ifmt_tst32_b_imm_S_2_S_16_dst32_2_S_16_absolute_QI, { 0x5c000000 }
63365
  },
63366
/* and.b${S} #${Imm-8-QI},r0l */
63367
  {
63368
    { 0, 0, 0, 0 },
63369
    { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'l', 0 } },
63370
    & ifmt_tst32_b_imm_S_2_S_basic_dst32_2_S_R0l_direct_QI, { 0x4c00 }
63371
  },
63372
/* and.b${S} ${SrcDst16-r0l-r0h-S-normal} */
63373
  {
63374
    { 0, 0, 0, 0 },
63375
    { { MNEM, OP (S), ' ', OP (SRCDST16_R0L_R0H_S_NORMAL), 0 } },
63376
    & ifmt_or16_b_S_r0l_r0h_srcdst16_r0l_r0h_S_derived, { 0x10 }
63377
  },
63378
/* and.b${S} ${Dsp-8-u8}[sb],${Dst16RnQI-S} */
63379
  {
63380
    { 0, 0, 0, 0 },
63381
    { { MNEM, OP (S), ' ', OP (DSP_8_U8), '[', 's', 'b', ']', ',', OP (DST16RNQI_S), 0 } },
63382
    & ifmt_or16_b_S_src2_src16_2_S_8_SB_relative_QI, { 0x1100 }
63383
  },
63384
/* and.b${S} ${Dsp-8-s8}[fb],${Dst16RnQI-S} */
63385
  {
63386
    { 0, 0, 0, 0 },
63387
    { { MNEM, OP (S), ' ', OP (DSP_8_S8), '[', 'f', 'b', ']', ',', OP (DST16RNQI_S), 0 } },
63388
    & ifmt_or16_b_S_src2_src16_2_S_8_FB_relative_QI, { 0x1200 }
63389
  },
63390
/* and.b${S} ${Dsp-8-u16},${Dst16RnQI-S} */
63391
  {
63392
    { 0, 0, 0, 0 },
63393
    { { MNEM, OP (S), ' ', OP (DSP_8_U16), ',', OP (DST16RNQI_S), 0 } },
63394
    & ifmt_or16_b_S_src2_src16_2_S_16_absolute_QI, { 0x130000 }
63395
  },
63396
/* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
63397
  {
63398
    { 0, 0, 0, 0 },
63399
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
63400
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x990d00 }
63401
  },
63402
/* and.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */
63403
  {
63404
    { 0, 0, 0, 0 },
63405
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
63406
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x992d00 }
63407
  },
63408
/* and.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */
63409
  {
63410
    { 0, 0, 0, 0 },
63411
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
63412
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x993d00 }
63413
  },
63414
/* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
63415
  {
63416
    { 0, 0, 0, 0 },
63417
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
63418
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x918d00 }
63419
  },
63420
/* and.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */
63421
  {
63422
    { 0, 0, 0, 0 },
63423
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
63424
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x91ad00 }
63425
  },
63426
/* and.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */
63427
  {
63428
    { 0, 0, 0, 0 },
63429
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
63430
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x91bd00 }
63431
  },
63432
/* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
63433
  {
63434
    { 0, 0, 0, 0 },
63435
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63436
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x910d00 }
63437
  },
63438
/* and.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
63439
  {
63440
    { 0, 0, 0, 0 },
63441
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63442
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x912d00 }
63443
  },
63444
/* and.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
63445
  {
63446
    { 0, 0, 0, 0 },
63447
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63448
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x913d00 }
63449
  },
63450
/* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
63451
  {
63452
    { 0, 0, 0, 0 },
63453
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63454
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x930d0000 }
63455
  },
63456
/* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
63457
  {
63458
    { 0, 0, 0, 0 },
63459
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63460
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x932d0000 }
63461
  },
63462
/* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
63463
  {
63464
    { 0, 0, 0, 0 },
63465
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63466
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x933d0000 }
63467
  },
63468
/* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
63469
  {
63470
    { 0, 0, 0, 0 },
63471
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63472
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x950d0000 }
63473
  },
63474
/* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
63475
  {
63476
    { 0, 0, 0, 0 },
63477
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63478
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x952d0000 }
63479
  },
63480
/* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
63481
  {
63482
    { 0, 0, 0, 0 },
63483
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63484
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x953d0000 }
63485
  },
63486
/* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
63487
  {
63488
    { 0, 0, 0, 0 },
63489
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63490
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x970d0000 }
63491
  },
63492
/* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
63493
  {
63494
    { 0, 0, 0, 0 },
63495
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63496
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x972d0000 }
63497
  },
63498
/* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
63499
  {
63500
    { 0, 0, 0, 0 },
63501
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63502
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x973d0000 }
63503
  },
63504
/* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
63505
  {
63506
    { 0, 0, 0, 0 },
63507
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
63508
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x938d0000 }
63509
  },
63510
/* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
63511
  {
63512
    { 0, 0, 0, 0 },
63513
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
63514
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93ad0000 }
63515
  },
63516
/* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
63517
  {
63518
    { 0, 0, 0, 0 },
63519
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
63520
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93bd0000 }
63521
  },
63522
/* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
63523
  {
63524
    { 0, 0, 0, 0 },
63525
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
63526
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x958d0000 }
63527
  },
63528
/* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
63529
  {
63530
    { 0, 0, 0, 0 },
63531
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
63532
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95ad0000 }
63533
  },
63534
/* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
63535
  {
63536
    { 0, 0, 0, 0 },
63537
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
63538
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95bd0000 }
63539
  },
63540
/* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
63541
  {
63542
    { 0, 0, 0, 0 },
63543
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
63544
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93cd0000 }
63545
  },
63546
/* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
63547
  {
63548
    { 0, 0, 0, 0 },
63549
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
63550
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93ed0000 }
63551
  },
63552
/* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
63553
  {
63554
    { 0, 0, 0, 0 },
63555
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
63556
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93fd0000 }
63557
  },
63558
/* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
63559
  {
63560
    { 0, 0, 0, 0 },
63561
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
63562
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95cd0000 }
63563
  },
63564
/* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
63565
  {
63566
    { 0, 0, 0, 0 },
63567
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
63568
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95ed0000 }
63569
  },
63570
/* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
63571
  {
63572
    { 0, 0, 0, 0 },
63573
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
63574
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95fd0000 }
63575
  },
63576
/* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
63577
  {
63578
    { 0, 0, 0, 0 },
63579
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
63580
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97cd0000 }
63581
  },
63582
/* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
63583
  {
63584
    { 0, 0, 0, 0 },
63585
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
63586
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97ed0000 }
63587
  },
63588
/* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
63589
  {
63590
    { 0, 0, 0, 0 },
63591
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
63592
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97fd0000 }
63593
  },
63594
/* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
63595
  {
63596
    { 0, 0, 0, 0 },
63597
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
63598
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x978d0000 }
63599
  },
63600
/* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
63601
  {
63602
    { 0, 0, 0, 0 },
63603
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } },
63604
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97ad0000 }
63605
  },
63606
/* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
63607
  {
63608
    { 0, 0, 0, 0 },
63609
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } },
63610
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97bd0000 }
63611
  },
63612
/* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
63613
  {
63614
    { 0, 0, 0, 0 },
63615
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
63616
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa90d0000 }
63617
  },
63618
/* and.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */
63619
  {
63620
    { 0, 0, 0, 0 },
63621
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
63622
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa92d0000 }
63623
  },
63624
/* and.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */
63625
  {
63626
    { 0, 0, 0, 0 },
63627
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
63628
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa93d0000 }
63629
  },
63630
/* and.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */
63631
  {
63632
    { 0, 0, 0, 0 },
63633
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
63634
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb93d0000 }
63635
  },
63636
/* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
63637
  {
63638
    { 0, 0, 0, 0 },
63639
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
63640
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa18d0000 }
63641
  },
63642
/* and.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */
63643
  {
63644
    { 0, 0, 0, 0 },
63645
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
63646
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1ad0000 }
63647
  },
63648
/* and.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */
63649
  {
63650
    { 0, 0, 0, 0 },
63651
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
63652
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1bd0000 }
63653
  },
63654
/* and.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */
63655
  {
63656
    { 0, 0, 0, 0 },
63657
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
63658
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1bd0000 }
63659
  },
63660
/* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
63661
  {
63662
    { 0, 0, 0, 0 },
63663
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63664
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa10d0000 }
63665
  },
63666
/* and.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
63667
  {
63668
    { 0, 0, 0, 0 },
63669
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63670
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa12d0000 }
63671
  },
63672
/* and.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
63673
  {
63674
    { 0, 0, 0, 0 },
63675
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63676
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa13d0000 }
63677
  },
63678
/* and.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
63679
  {
63680
    { 0, 0, 0, 0 },
63681
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63682
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb13d0000 }
63683
  },
63684
/* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
63685
  {
63686
    { 0, 0, 0, 0 },
63687
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63688
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa30d0000 }
63689
  },
63690
/* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
63691
  {
63692
    { 0, 0, 0, 0 },
63693
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63694
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa32d0000 }
63695
  },
63696
/* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
63697
  {
63698
    { 0, 0, 0, 0 },
63699
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63700
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa33d0000 }
63701
  },
63702
/* and.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
63703
  {
63704
    { 0, 0, 0, 0 },
63705
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63706
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xb33d0000 }
63707
  },
63708
/* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
63709
  {
63710
    { 0, 0, 0, 0 },
63711
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63712
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa50d0000 }
63713
  },
63714
/* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
63715
  {
63716
    { 0, 0, 0, 0 },
63717
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63718
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa52d0000 }
63719
  },
63720
/* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
63721
  {
63722
    { 0, 0, 0, 0 },
63723
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63724
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa53d0000 }
63725
  },
63726
/* and.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
63727
  {
63728
    { 0, 0, 0, 0 },
63729
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63730
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xb53d0000 }
63731
  },
63732
/* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
63733
  {
63734
    { 0, 0, 0, 0 },
63735
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63736
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa70d0000 }
63737
  },
63738
/* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
63739
  {
63740
    { 0, 0, 0, 0 },
63741
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63742
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa72d0000 }
63743
  },
63744
/* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
63745
  {
63746
    { 0, 0, 0, 0 },
63747
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63748
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa73d0000 }
63749
  },
63750
/* and.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
63751
  {
63752
    { 0, 0, 0, 0 },
63753
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63754
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xb73d0000 }
63755
  },
63756
/* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
63757
  {
63758
    { 0, 0, 0, 0 },
63759
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
63760
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa38d0000 }
63761
  },
63762
/* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
63763
  {
63764
    { 0, 0, 0, 0 },
63765
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
63766
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3ad0000 }
63767
  },
63768
/* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
63769
  {
63770
    { 0, 0, 0, 0 },
63771
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
63772
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3bd0000 }
63773
  },
63774
/* and.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
63775
  {
63776
    { 0, 0, 0, 0 },
63777
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
63778
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xb3bd0000 }
63779
  },
63780
/* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
63781
  {
63782
    { 0, 0, 0, 0 },
63783
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
63784
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa58d0000 }
63785
  },
63786
/* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
63787
  {
63788
    { 0, 0, 0, 0 },
63789
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
63790
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5ad0000 }
63791
  },
63792
/* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
63793
  {
63794
    { 0, 0, 0, 0 },
63795
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
63796
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5bd0000 }
63797
  },
63798
/* and.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
63799
  {
63800
    { 0, 0, 0, 0 },
63801
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
63802
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xb5bd0000 }
63803
  },
63804
/* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
63805
  {
63806
    { 0, 0, 0, 0 },
63807
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
63808
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3cd0000 }
63809
  },
63810
/* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
63811
  {
63812
    { 0, 0, 0, 0 },
63813
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
63814
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3ed0000 }
63815
  },
63816
/* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
63817
  {
63818
    { 0, 0, 0, 0 },
63819
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
63820
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3fd0000 }
63821
  },
63822
/* and.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
63823
  {
63824
    { 0, 0, 0, 0 },
63825
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
63826
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xb3fd0000 }
63827
  },
63828
/* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
63829
  {
63830
    { 0, 0, 0, 0 },
63831
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
63832
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5cd0000 }
63833
  },
63834
/* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
63835
  {
63836
    { 0, 0, 0, 0 },
63837
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
63838
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5ed0000 }
63839
  },
63840
/* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
63841
  {
63842
    { 0, 0, 0, 0 },
63843
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
63844
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5fd0000 }
63845
  },
63846
/* and.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
63847
  {
63848
    { 0, 0, 0, 0 },
63849
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
63850
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xb5fd0000 }
63851
  },
63852
/* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
63853
  {
63854
    { 0, 0, 0, 0 },
63855
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
63856
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7cd0000 }
63857
  },
63858
/* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
63859
  {
63860
    { 0, 0, 0, 0 },
63861
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
63862
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7ed0000 }
63863
  },
63864
/* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
63865
  {
63866
    { 0, 0, 0, 0 },
63867
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
63868
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7fd0000 }
63869
  },
63870
/* and.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
63871
  {
63872
    { 0, 0, 0, 0 },
63873
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
63874
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xb7fd0000 }
63875
  },
63876
/* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
63877
  {
63878
    { 0, 0, 0, 0 },
63879
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
63880
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa78d0000 }
63881
  },
63882
/* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
63883
  {
63884
    { 0, 0, 0, 0 },
63885
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
63886
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7ad0000 }
63887
  },
63888
/* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
63889
  {
63890
    { 0, 0, 0, 0 },
63891
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
63892
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7bd0000 }
63893
  },
63894
/* and.w${G} ${Dsp-16-u16},${Dsp-32-u24} */
63895
  {
63896
    { 0, 0, 0, 0 },
63897
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } },
63898
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xb7bd0000 }
63899
  },
63900
/* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
63901
  {
63902
    { 0, 0, 0, 0 },
63903
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
63904
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb90d0000 }
63905
  },
63906
/* and.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */
63907
  {
63908
    { 0, 0, 0, 0 },
63909
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
63910
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb92d0000 }
63911
  },
63912
/* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
63913
  {
63914
    { 0, 0, 0, 0 },
63915
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
63916
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb18d0000 }
63917
  },
63918
/* and.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */
63919
  {
63920
    { 0, 0, 0, 0 },
63921
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
63922
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1ad0000 }
63923
  },
63924
/* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
63925
  {
63926
    { 0, 0, 0, 0 },
63927
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63928
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb10d0000 }
63929
  },
63930
/* and.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
63931
  {
63932
    { 0, 0, 0, 0 },
63933
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63934
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb12d0000 }
63935
  },
63936
/* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
63937
  {
63938
    { 0, 0, 0, 0 },
63939
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63940
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_An_relative_Unprefixed_HI, { 0xb30d0000 }
63941
  },
63942
/* and.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
63943
  {
63944
    { 0, 0, 0, 0 },
63945
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63946
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_An_relative_Unprefixed_HI, { 0xb32d0000 }
63947
  },
63948
/* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
63949
  {
63950
    { 0, 0, 0, 0 },
63951
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63952
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_An_relative_Unprefixed_HI, { 0xb50d0000 }
63953
  },
63954
/* and.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
63955
  {
63956
    { 0, 0, 0, 0 },
63957
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63958
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_An_relative_Unprefixed_HI, { 0xb52d0000 }
63959
  },
63960
/* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
63961
  {
63962
    { 0, 0, 0, 0 },
63963
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63964
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_24_An_relative_Unprefixed_HI, { 0xb70d0000 }
63965
  },
63966
/* and.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
63967
  {
63968
    { 0, 0, 0, 0 },
63969
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
63970
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_24_An_relative_Unprefixed_HI, { 0xb72d0000 }
63971
  },
63972
/* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
63973
  {
63974
    { 0, 0, 0, 0 },
63975
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
63976
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_SB_relative_Unprefixed_HI, { 0xb38d0000 }
63977
  },
63978
/* and.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
63979
  {
63980
    { 0, 0, 0, 0 },
63981
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
63982
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_SB_relative_Unprefixed_HI, { 0xb3ad0000 }
63983
  },
63984
/* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
63985
  {
63986
    { 0, 0, 0, 0 },
63987
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
63988
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_SB_relative_Unprefixed_HI, { 0xb58d0000 }
63989
  },
63990
/* and.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
63991
  {
63992
    { 0, 0, 0, 0 },
63993
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
63994
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_SB_relative_Unprefixed_HI, { 0xb5ad0000 }
63995
  },
63996
/* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
63997
  {
63998
    { 0, 0, 0, 0 },
63999
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
64000
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_FB_relative_Unprefixed_HI, { 0xb3cd0000 }
64001
  },
64002
/* and.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
64003
  {
64004
    { 0, 0, 0, 0 },
64005
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
64006
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_FB_relative_Unprefixed_HI, { 0xb3ed0000 }
64007
  },
64008
/* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
64009
  {
64010
    { 0, 0, 0, 0 },
64011
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
64012
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_FB_relative_Unprefixed_HI, { 0xb5cd0000 }
64013
  },
64014
/* and.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
64015
  {
64016
    { 0, 0, 0, 0 },
64017
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
64018
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_FB_relative_Unprefixed_HI, { 0xb5ed0000 }
64019
  },
64020
/* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
64021
  {
64022
    { 0, 0, 0, 0 },
64023
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
64024
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_absolute_Unprefixed_HI, { 0xb7cd0000 }
64025
  },
64026
/* and.w${G} ${Dsp-16-u24},${Dsp-40-u16} */
64027
  {
64028
    { 0, 0, 0, 0 },
64029
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } },
64030
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_absolute_Unprefixed_HI, { 0xb7ed0000 }
64031
  },
64032
/* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
64033
  {
64034
    { 0, 0, 0, 0 },
64035
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
64036
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_24_absolute_Unprefixed_HI, { 0xb78d0000 }
64037
  },
64038
/* and.w${G} ${Dsp-16-u24},${Dsp-40-u24} */
64039
  {
64040
    { 0, 0, 0, 0 },
64041
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } },
64042
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_24_absolute_Unprefixed_HI, { 0xb7ad0000 }
64043
  },
64044
/* and.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */
64045
  {
64046
    { 0, 0, 0, 0 },
64047
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
64048
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xc90d }
64049
  },
64050
/* and.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */
64051
  {
64052
    { 0, 0, 0, 0 },
64053
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
64054
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x892d }
64055
  },
64056
/* and.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
64057
  {
64058
    { 0, 0, 0, 0 },
64059
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
64060
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x890d }
64061
  },
64062
/* and.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */
64063
  {
64064
    { 0, 0, 0, 0 },
64065
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
64066
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xc18d }
64067
  },
64068
/* and.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */
64069
  {
64070
    { 0, 0, 0, 0 },
64071
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
64072
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x81ad }
64073
  },
64074
/* and.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
64075
  {
64076
    { 0, 0, 0, 0 },
64077
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
64078
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x818d }
64079
  },
64080
/* and.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */
64081
  {
64082
    { 0, 0, 0, 0 },
64083
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64084
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xc10d }
64085
  },
64086
/* and.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */
64087
  {
64088
    { 0, 0, 0, 0 },
64089
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64090
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x812d }
64091
  },
64092
/* and.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
64093
  {
64094
    { 0, 0, 0, 0 },
64095
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64096
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x810d }
64097
  },
64098
/* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
64099
  {
64100
    { 0, 0, 0, 0 },
64101
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64102
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0xc30d00 }
64103
  },
64104
/* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
64105
  {
64106
    { 0, 0, 0, 0 },
64107
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64108
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0x832d00 }
64109
  },
64110
/* and.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
64111
  {
64112
    { 0, 0, 0, 0 },
64113
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64114
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0x830d00 }
64115
  },
64116
/* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
64117
  {
64118
    { 0, 0, 0, 0 },
64119
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64120
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0xc50d0000 }
64121
  },
64122
/* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
64123
  {
64124
    { 0, 0, 0, 0 },
64125
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64126
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0x852d0000 }
64127
  },
64128
/* and.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
64129
  {
64130
    { 0, 0, 0, 0 },
64131
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64132
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0x850d0000 }
64133
  },
64134
/* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
64135
  {
64136
    { 0, 0, 0, 0 },
64137
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64138
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0xc70d0000 }
64139
  },
64140
/* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
64141
  {
64142
    { 0, 0, 0, 0 },
64143
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64144
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0x872d0000 }
64145
  },
64146
/* and.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
64147
  {
64148
    { 0, 0, 0, 0 },
64149
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64150
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0x870d0000 }
64151
  },
64152
/* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */
64153
  {
64154
    { 0, 0, 0, 0 },
64155
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
64156
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0xc38d00 }
64157
  },
64158
/* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */
64159
  {
64160
    { 0, 0, 0, 0 },
64161
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
64162
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0x83ad00 }
64163
  },
64164
/* and.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
64165
  {
64166
    { 0, 0, 0, 0 },
64167
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
64168
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0x838d00 }
64169
  },
64170
/* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */
64171
  {
64172
    { 0, 0, 0, 0 },
64173
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
64174
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0xc58d0000 }
64175
  },
64176
/* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */
64177
  {
64178
    { 0, 0, 0, 0 },
64179
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
64180
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0x85ad0000 }
64181
  },
64182
/* and.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
64183
  {
64184
    { 0, 0, 0, 0 },
64185
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
64186
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0x858d0000 }
64187
  },
64188
/* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */
64189
  {
64190
    { 0, 0, 0, 0 },
64191
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
64192
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0xc3cd00 }
64193
  },
64194
/* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */
64195
  {
64196
    { 0, 0, 0, 0 },
64197
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
64198
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83ed00 }
64199
  },
64200
/* and.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
64201
  {
64202
    { 0, 0, 0, 0 },
64203
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
64204
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83cd00 }
64205
  },
64206
/* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */
64207
  {
64208
    { 0, 0, 0, 0 },
64209
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
64210
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0xc5cd0000 }
64211
  },
64212
/* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */
64213
  {
64214
    { 0, 0, 0, 0 },
64215
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
64216
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85ed0000 }
64217
  },
64218
/* and.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
64219
  {
64220
    { 0, 0, 0, 0 },
64221
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
64222
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85cd0000 }
64223
  },
64224
/* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */
64225
  {
64226
    { 0, 0, 0, 0 },
64227
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), 0 } },
64228
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0xc7cd0000 }
64229
  },
64230
/* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */
64231
  {
64232
    { 0, 0, 0, 0 },
64233
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), 0 } },
64234
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0x87ed0000 }
64235
  },
64236
/* and.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
64237
  {
64238
    { 0, 0, 0, 0 },
64239
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } },
64240
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0x87cd0000 }
64241
  },
64242
/* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */
64243
  {
64244
    { 0, 0, 0, 0 },
64245
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U24), 0 } },
64246
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0xc78d0000 }
64247
  },
64248
/* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */
64249
  {
64250
    { 0, 0, 0, 0 },
64251
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U24), 0 } },
64252
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0x87ad0000 }
64253
  },
64254
/* and.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
64255
  {
64256
    { 0, 0, 0, 0 },
64257
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } },
64258
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0x878d0000 }
64259
  },
64260
/* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
64261
  {
64262
    { 0, 0, 0, 0 },
64263
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
64264
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x980d00 }
64265
  },
64266
/* and.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */
64267
  {
64268
    { 0, 0, 0, 0 },
64269
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
64270
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x982d00 }
64271
  },
64272
/* and.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */
64273
  {
64274
    { 0, 0, 0, 0 },
64275
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
64276
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x983d00 }
64277
  },
64278
/* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
64279
  {
64280
    { 0, 0, 0, 0 },
64281
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
64282
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x908d00 }
64283
  },
64284
/* and.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */
64285
  {
64286
    { 0, 0, 0, 0 },
64287
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
64288
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x90ad00 }
64289
  },
64290
/* and.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */
64291
  {
64292
    { 0, 0, 0, 0 },
64293
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
64294
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x90bd00 }
64295
  },
64296
/* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
64297
  {
64298
    { 0, 0, 0, 0 },
64299
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64300
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x900d00 }
64301
  },
64302
/* and.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
64303
  {
64304
    { 0, 0, 0, 0 },
64305
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64306
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x902d00 }
64307
  },
64308
/* and.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
64309
  {
64310
    { 0, 0, 0, 0 },
64311
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64312
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x903d00 }
64313
  },
64314
/* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
64315
  {
64316
    { 0, 0, 0, 0 },
64317
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64318
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x920d0000 }
64319
  },
64320
/* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
64321
  {
64322
    { 0, 0, 0, 0 },
64323
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64324
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x922d0000 }
64325
  },
64326
/* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
64327
  {
64328
    { 0, 0, 0, 0 },
64329
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64330
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x923d0000 }
64331
  },
64332
/* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
64333
  {
64334
    { 0, 0, 0, 0 },
64335
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64336
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x940d0000 }
64337
  },
64338
/* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
64339
  {
64340
    { 0, 0, 0, 0 },
64341
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64342
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x942d0000 }
64343
  },
64344
/* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
64345
  {
64346
    { 0, 0, 0, 0 },
64347
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64348
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x943d0000 }
64349
  },
64350
/* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
64351
  {
64352
    { 0, 0, 0, 0 },
64353
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64354
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x960d0000 }
64355
  },
64356
/* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
64357
  {
64358
    { 0, 0, 0, 0 },
64359
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64360
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x962d0000 }
64361
  },
64362
/* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
64363
  {
64364
    { 0, 0, 0, 0 },
64365
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64366
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x963d0000 }
64367
  },
64368
/* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
64369
  {
64370
    { 0, 0, 0, 0 },
64371
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
64372
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x928d0000 }
64373
  },
64374
/* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
64375
  {
64376
    { 0, 0, 0, 0 },
64377
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
64378
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92ad0000 }
64379
  },
64380
/* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
64381
  {
64382
    { 0, 0, 0, 0 },
64383
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
64384
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92bd0000 }
64385
  },
64386
/* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
64387
  {
64388
    { 0, 0, 0, 0 },
64389
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
64390
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x948d0000 }
64391
  },
64392
/* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
64393
  {
64394
    { 0, 0, 0, 0 },
64395
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
64396
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94ad0000 }
64397
  },
64398
/* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
64399
  {
64400
    { 0, 0, 0, 0 },
64401
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
64402
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94bd0000 }
64403
  },
64404
/* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
64405
  {
64406
    { 0, 0, 0, 0 },
64407
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
64408
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92cd0000 }
64409
  },
64410
/* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
64411
  {
64412
    { 0, 0, 0, 0 },
64413
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
64414
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92ed0000 }
64415
  },
64416
/* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
64417
  {
64418
    { 0, 0, 0, 0 },
64419
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
64420
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92fd0000 }
64421
  },
64422
/* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
64423
  {
64424
    { 0, 0, 0, 0 },
64425
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
64426
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94cd0000 }
64427
  },
64428
/* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
64429
  {
64430
    { 0, 0, 0, 0 },
64431
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
64432
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94ed0000 }
64433
  },
64434
/* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
64435
  {
64436
    { 0, 0, 0, 0 },
64437
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
64438
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94fd0000 }
64439
  },
64440
/* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
64441
  {
64442
    { 0, 0, 0, 0 },
64443
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
64444
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96cd0000 }
64445
  },
64446
/* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
64447
  {
64448
    { 0, 0, 0, 0 },
64449
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
64450
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96ed0000 }
64451
  },
64452
/* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
64453
  {
64454
    { 0, 0, 0, 0 },
64455
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
64456
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96fd0000 }
64457
  },
64458
/* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
64459
  {
64460
    { 0, 0, 0, 0 },
64461
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
64462
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x968d0000 }
64463
  },
64464
/* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
64465
  {
64466
    { 0, 0, 0, 0 },
64467
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } },
64468
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96ad0000 }
64469
  },
64470
/* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
64471
  {
64472
    { 0, 0, 0, 0 },
64473
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } },
64474
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96bd0000 }
64475
  },
64476
/* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
64477
  {
64478
    { 0, 0, 0, 0 },
64479
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
64480
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa80d0000 }
64481
  },
64482
/* and.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */
64483
  {
64484
    { 0, 0, 0, 0 },
64485
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
64486
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa82d0000 }
64487
  },
64488
/* and.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */
64489
  {
64490
    { 0, 0, 0, 0 },
64491
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
64492
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa83d0000 }
64493
  },
64494
/* and.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */
64495
  {
64496
    { 0, 0, 0, 0 },
64497
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
64498
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb83d0000 }
64499
  },
64500
/* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
64501
  {
64502
    { 0, 0, 0, 0 },
64503
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
64504
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa08d0000 }
64505
  },
64506
/* and.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */
64507
  {
64508
    { 0, 0, 0, 0 },
64509
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
64510
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0ad0000 }
64511
  },
64512
/* and.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */
64513
  {
64514
    { 0, 0, 0, 0 },
64515
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
64516
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0bd0000 }
64517
  },
64518
/* and.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */
64519
  {
64520
    { 0, 0, 0, 0 },
64521
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
64522
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0bd0000 }
64523
  },
64524
/* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
64525
  {
64526
    { 0, 0, 0, 0 },
64527
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64528
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa00d0000 }
64529
  },
64530
/* and.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
64531
  {
64532
    { 0, 0, 0, 0 },
64533
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64534
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa02d0000 }
64535
  },
64536
/* and.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
64537
  {
64538
    { 0, 0, 0, 0 },
64539
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64540
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa03d0000 }
64541
  },
64542
/* and.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
64543
  {
64544
    { 0, 0, 0, 0 },
64545
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64546
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb03d0000 }
64547
  },
64548
/* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
64549
  {
64550
    { 0, 0, 0, 0 },
64551
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64552
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa20d0000 }
64553
  },
64554
/* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
64555
  {
64556
    { 0, 0, 0, 0 },
64557
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64558
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa22d0000 }
64559
  },
64560
/* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
64561
  {
64562
    { 0, 0, 0, 0 },
64563
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64564
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa23d0000 }
64565
  },
64566
/* and.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
64567
  {
64568
    { 0, 0, 0, 0 },
64569
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64570
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xb23d0000 }
64571
  },
64572
/* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
64573
  {
64574
    { 0, 0, 0, 0 },
64575
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64576
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa40d0000 }
64577
  },
64578
/* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
64579
  {
64580
    { 0, 0, 0, 0 },
64581
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64582
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa42d0000 }
64583
  },
64584
/* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
64585
  {
64586
    { 0, 0, 0, 0 },
64587
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64588
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa43d0000 }
64589
  },
64590
/* and.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
64591
  {
64592
    { 0, 0, 0, 0 },
64593
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64594
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xb43d0000 }
64595
  },
64596
/* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
64597
  {
64598
    { 0, 0, 0, 0 },
64599
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64600
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa60d0000 }
64601
  },
64602
/* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
64603
  {
64604
    { 0, 0, 0, 0 },
64605
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64606
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa62d0000 }
64607
  },
64608
/* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
64609
  {
64610
    { 0, 0, 0, 0 },
64611
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64612
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa63d0000 }
64613
  },
64614
/* and.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
64615
  {
64616
    { 0, 0, 0, 0 },
64617
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64618
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xb63d0000 }
64619
  },
64620
/* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
64621
  {
64622
    { 0, 0, 0, 0 },
64623
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
64624
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa28d0000 }
64625
  },
64626
/* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
64627
  {
64628
    { 0, 0, 0, 0 },
64629
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
64630
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2ad0000 }
64631
  },
64632
/* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
64633
  {
64634
    { 0, 0, 0, 0 },
64635
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
64636
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2bd0000 }
64637
  },
64638
/* and.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
64639
  {
64640
    { 0, 0, 0, 0 },
64641
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
64642
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xb2bd0000 }
64643
  },
64644
/* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
64645
  {
64646
    { 0, 0, 0, 0 },
64647
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
64648
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa48d0000 }
64649
  },
64650
/* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
64651
  {
64652
    { 0, 0, 0, 0 },
64653
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
64654
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4ad0000 }
64655
  },
64656
/* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
64657
  {
64658
    { 0, 0, 0, 0 },
64659
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
64660
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4bd0000 }
64661
  },
64662
/* and.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
64663
  {
64664
    { 0, 0, 0, 0 },
64665
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
64666
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xb4bd0000 }
64667
  },
64668
/* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
64669
  {
64670
    { 0, 0, 0, 0 },
64671
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
64672
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2cd0000 }
64673
  },
64674
/* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
64675
  {
64676
    { 0, 0, 0, 0 },
64677
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
64678
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2ed0000 }
64679
  },
64680
/* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
64681
  {
64682
    { 0, 0, 0, 0 },
64683
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
64684
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2fd0000 }
64685
  },
64686
/* and.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
64687
  {
64688
    { 0, 0, 0, 0 },
64689
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
64690
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xb2fd0000 }
64691
  },
64692
/* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
64693
  {
64694
    { 0, 0, 0, 0 },
64695
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
64696
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4cd0000 }
64697
  },
64698
/* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
64699
  {
64700
    { 0, 0, 0, 0 },
64701
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
64702
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4ed0000 }
64703
  },
64704
/* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
64705
  {
64706
    { 0, 0, 0, 0 },
64707
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
64708
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4fd0000 }
64709
  },
64710
/* and.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
64711
  {
64712
    { 0, 0, 0, 0 },
64713
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
64714
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xb4fd0000 }
64715
  },
64716
/* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
64717
  {
64718
    { 0, 0, 0, 0 },
64719
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
64720
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6cd0000 }
64721
  },
64722
/* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
64723
  {
64724
    { 0, 0, 0, 0 },
64725
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
64726
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6ed0000 }
64727
  },
64728
/* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
64729
  {
64730
    { 0, 0, 0, 0 },
64731
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
64732
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6fd0000 }
64733
  },
64734
/* and.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
64735
  {
64736
    { 0, 0, 0, 0 },
64737
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
64738
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xb6fd0000 }
64739
  },
64740
/* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
64741
  {
64742
    { 0, 0, 0, 0 },
64743
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
64744
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa68d0000 }
64745
  },
64746
/* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
64747
  {
64748
    { 0, 0, 0, 0 },
64749
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
64750
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6ad0000 }
64751
  },
64752
/* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
64753
  {
64754
    { 0, 0, 0, 0 },
64755
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
64756
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6bd0000 }
64757
  },
64758
/* and.b${G} ${Dsp-16-u16},${Dsp-32-u24} */
64759
  {
64760
    { 0, 0, 0, 0 },
64761
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } },
64762
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xb6bd0000 }
64763
  },
64764
/* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
64765
  {
64766
    { 0, 0, 0, 0 },
64767
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
64768
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb80d0000 }
64769
  },
64770
/* and.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */
64771
  {
64772
    { 0, 0, 0, 0 },
64773
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
64774
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb82d0000 }
64775
  },
64776
/* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
64777
  {
64778
    { 0, 0, 0, 0 },
64779
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
64780
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb08d0000 }
64781
  },
64782
/* and.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */
64783
  {
64784
    { 0, 0, 0, 0 },
64785
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
64786
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0ad0000 }
64787
  },
64788
/* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
64789
  {
64790
    { 0, 0, 0, 0 },
64791
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64792
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb00d0000 }
64793
  },
64794
/* and.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
64795
  {
64796
    { 0, 0, 0, 0 },
64797
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64798
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb02d0000 }
64799
  },
64800
/* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
64801
  {
64802
    { 0, 0, 0, 0 },
64803
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64804
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_QI, { 0xb20d0000 }
64805
  },
64806
/* and.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
64807
  {
64808
    { 0, 0, 0, 0 },
64809
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64810
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_QI, { 0xb22d0000 }
64811
  },
64812
/* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
64813
  {
64814
    { 0, 0, 0, 0 },
64815
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64816
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_QI, { 0xb40d0000 }
64817
  },
64818
/* and.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
64819
  {
64820
    { 0, 0, 0, 0 },
64821
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64822
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_QI, { 0xb42d0000 }
64823
  },
64824
/* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
64825
  {
64826
    { 0, 0, 0, 0 },
64827
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64828
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_QI, { 0xb60d0000 }
64829
  },
64830
/* and.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
64831
  {
64832
    { 0, 0, 0, 0 },
64833
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64834
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_QI, { 0xb62d0000 }
64835
  },
64836
/* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
64837
  {
64838
    { 0, 0, 0, 0 },
64839
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
64840
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_QI, { 0xb28d0000 }
64841
  },
64842
/* and.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
64843
  {
64844
    { 0, 0, 0, 0 },
64845
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
64846
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_QI, { 0xb2ad0000 }
64847
  },
64848
/* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
64849
  {
64850
    { 0, 0, 0, 0 },
64851
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
64852
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_QI, { 0xb48d0000 }
64853
  },
64854
/* and.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
64855
  {
64856
    { 0, 0, 0, 0 },
64857
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
64858
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_QI, { 0xb4ad0000 }
64859
  },
64860
/* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
64861
  {
64862
    { 0, 0, 0, 0 },
64863
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
64864
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_QI, { 0xb2cd0000 }
64865
  },
64866
/* and.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
64867
  {
64868
    { 0, 0, 0, 0 },
64869
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
64870
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_QI, { 0xb2ed0000 }
64871
  },
64872
/* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
64873
  {
64874
    { 0, 0, 0, 0 },
64875
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
64876
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_QI, { 0xb4cd0000 }
64877
  },
64878
/* and.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
64879
  {
64880
    { 0, 0, 0, 0 },
64881
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
64882
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_QI, { 0xb4ed0000 }
64883
  },
64884
/* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
64885
  {
64886
    { 0, 0, 0, 0 },
64887
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
64888
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_QI, { 0xb6cd0000 }
64889
  },
64890
/* and.b${G} ${Dsp-16-u24},${Dsp-40-u16} */
64891
  {
64892
    { 0, 0, 0, 0 },
64893
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } },
64894
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_QI, { 0xb6ed0000 }
64895
  },
64896
/* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
64897
  {
64898
    { 0, 0, 0, 0 },
64899
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
64900
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_QI, { 0xb68d0000 }
64901
  },
64902
/* and.b${G} ${Dsp-16-u24},${Dsp-40-u24} */
64903
  {
64904
    { 0, 0, 0, 0 },
64905
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } },
64906
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_QI, { 0xb6ad0000 }
64907
  },
64908
/* and.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */
64909
  {
64910
    { 0, 0, 0, 0 },
64911
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
64912
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xc80d }
64913
  },
64914
/* and.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */
64915
  {
64916
    { 0, 0, 0, 0 },
64917
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
64918
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x882d }
64919
  },
64920
/* and.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
64921
  {
64922
    { 0, 0, 0, 0 },
64923
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
64924
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x880d }
64925
  },
64926
/* and.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */
64927
  {
64928
    { 0, 0, 0, 0 },
64929
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
64930
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xc08d }
64931
  },
64932
/* and.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */
64933
  {
64934
    { 0, 0, 0, 0 },
64935
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
64936
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x80ad }
64937
  },
64938
/* and.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
64939
  {
64940
    { 0, 0, 0, 0 },
64941
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
64942
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x808d }
64943
  },
64944
/* and.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */
64945
  {
64946
    { 0, 0, 0, 0 },
64947
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64948
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xc00d }
64949
  },
64950
/* and.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */
64951
  {
64952
    { 0, 0, 0, 0 },
64953
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64954
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x802d }
64955
  },
64956
/* and.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
64957
  {
64958
    { 0, 0, 0, 0 },
64959
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64960
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x800d }
64961
  },
64962
/* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
64963
  {
64964
    { 0, 0, 0, 0 },
64965
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64966
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0xc20d00 }
64967
  },
64968
/* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
64969
  {
64970
    { 0, 0, 0, 0 },
64971
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64972
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0x822d00 }
64973
  },
64974
/* and.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
64975
  {
64976
    { 0, 0, 0, 0 },
64977
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64978
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0x820d00 }
64979
  },
64980
/* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
64981
  {
64982
    { 0, 0, 0, 0 },
64983
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64984
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0xc40d0000 }
64985
  },
64986
/* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
64987
  {
64988
    { 0, 0, 0, 0 },
64989
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64990
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0x842d0000 }
64991
  },
64992
/* and.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
64993
  {
64994
    { 0, 0, 0, 0 },
64995
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
64996
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0x840d0000 }
64997
  },
64998
/* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
64999
  {
65000
    { 0, 0, 0, 0 },
65001
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
65002
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0xc60d0000 }
65003
  },
65004
/* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
65005
  {
65006
    { 0, 0, 0, 0 },
65007
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
65008
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0x862d0000 }
65009
  },
65010
/* and.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
65011
  {
65012
    { 0, 0, 0, 0 },
65013
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
65014
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0x860d0000 }
65015
  },
65016
/* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */
65017
  {
65018
    { 0, 0, 0, 0 },
65019
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
65020
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0xc28d00 }
65021
  },
65022
/* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */
65023
  {
65024
    { 0, 0, 0, 0 },
65025
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
65026
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0x82ad00 }
65027
  },
65028
/* and.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
65029
  {
65030
    { 0, 0, 0, 0 },
65031
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
65032
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0x828d00 }
65033
  },
65034
/* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */
65035
  {
65036
    { 0, 0, 0, 0 },
65037
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
65038
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0xc48d0000 }
65039
  },
65040
/* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */
65041
  {
65042
    { 0, 0, 0, 0 },
65043
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
65044
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0x84ad0000 }
65045
  },
65046
/* and.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
65047
  {
65048
    { 0, 0, 0, 0 },
65049
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
65050
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0x848d0000 }
65051
  },
65052
/* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */
65053
  {
65054
    { 0, 0, 0, 0 },
65055
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
65056
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0xc2cd00 }
65057
  },
65058
/* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */
65059
  {
65060
    { 0, 0, 0, 0 },
65061
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
65062
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82ed00 }
65063
  },
65064
/* and.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
65065
  {
65066
    { 0, 0, 0, 0 },
65067
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
65068
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82cd00 }
65069
  },
65070
/* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */
65071
  {
65072
    { 0, 0, 0, 0 },
65073
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
65074
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0xc4cd0000 }
65075
  },
65076
/* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */
65077
  {
65078
    { 0, 0, 0, 0 },
65079
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
65080
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84ed0000 }
65081
  },
65082
/* and.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
65083
  {
65084
    { 0, 0, 0, 0 },
65085
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
65086
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84cd0000 }
65087
  },
65088
/* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */
65089
  {
65090
    { 0, 0, 0, 0 },
65091
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), 0 } },
65092
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0xc6cd0000 }
65093
  },
65094
/* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */
65095
  {
65096
    { 0, 0, 0, 0 },
65097
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), 0 } },
65098
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0x86ed0000 }
65099
  },
65100
/* and.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
65101
  {
65102
    { 0, 0, 0, 0 },
65103
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } },
65104
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0x86cd0000 }
65105
  },
65106
/* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */
65107
  {
65108
    { 0, 0, 0, 0 },
65109
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U24), 0 } },
65110
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0xc68d0000 }
65111
  },
65112
/* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */
65113
  {
65114
    { 0, 0, 0, 0 },
65115
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U24), 0 } },
65116
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0x86ad0000 }
65117
  },
65118
/* and.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
65119
  {
65120
    { 0, 0, 0, 0 },
65121
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } },
65122
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0x868d0000 }
65123
  },
65124
/* and.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
65125
  {
65126
    { 0, 0, 0, 0 },
65127
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } },
65128
    & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_Rn_direct_HI, { 0x918000 }
65129
  },
65130
/* and.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */
65131
  {
65132
    { 0, 0, 0, 0 },
65133
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } },
65134
    & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_Rn_direct_HI, { 0x91a000 }
65135
  },
65136
/* and.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */
65137
  {
65138
    { 0, 0, 0, 0 },
65139
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNHI), 0 } },
65140
    & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_Rn_direct_HI, { 0x91b000 }
65141
  },
65142
/* and.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
65143
  {
65144
    { 0, 0, 0, 0 },
65145
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } },
65146
    & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_direct_HI, { 0x918400 }
65147
  },
65148
/* and.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */
65149
  {
65150
    { 0, 0, 0, 0 },
65151
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } },
65152
    & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_direct_HI, { 0x91a400 }
65153
  },
65154
/* and.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */
65155
  {
65156
    { 0, 0, 0, 0 },
65157
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANHI), 0 } },
65158
    & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_direct_HI, { 0x91b400 }
65159
  },
65160
/* and.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
65161
  {
65162
    { 0, 0, 0, 0 },
65163
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
65164
    & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_indirect_HI, { 0x918600 }
65165
  },
65166
/* and.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */
65167
  {
65168
    { 0, 0, 0, 0 },
65169
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
65170
    & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_indirect_HI, { 0x91a600 }
65171
  },
65172
/* and.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */
65173
  {
65174
    { 0, 0, 0, 0 },
65175
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
65176
    & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_indirect_HI, { 0x91b600 }
65177
  },
65178
/* and.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
65179
  {
65180
    { 0, 0, 0, 0 },
65181
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
65182
    & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_An_relative_HI, { 0x91880000 }
65183
  },
65184
/* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
65185
  {
65186
    { 0, 0, 0, 0 },
65187
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
65188
    & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_An_relative_HI, { 0x91a80000 }
65189
  },
65190
/* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
65191
  {
65192
    { 0, 0, 0, 0 },
65193
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
65194
    & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_An_relative_HI, { 0x91b80000 }
65195
  },
65196
/* and.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
65197
  {
65198
    { 0, 0, 0, 0 },
65199
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
65200
    & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_An_relative_HI, { 0x918c0000 }
65201
  },
65202
/* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
65203
  {
65204
    { 0, 0, 0, 0 },
65205
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
65206
    & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_An_relative_HI, { 0x91ac0000 }
65207
  },
65208
/* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
65209
  {
65210
    { 0, 0, 0, 0 },
65211
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
65212
    & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_An_relative_HI, { 0x91bc0000 }
65213
  },
65214
/* and.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
65215
  {
65216
    { 0, 0, 0, 0 },
65217
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
65218
    & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_SB_relative_HI, { 0x918a0000 }
65219
  },
65220
/* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
65221
  {
65222
    { 0, 0, 0, 0 },
65223
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
65224
    & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_SB_relative_HI, { 0x91aa0000 }
65225
  },
65226
/* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
65227
  {
65228
    { 0, 0, 0, 0 },
65229
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
65230
    & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_SB_relative_HI, { 0x91ba0000 }
65231
  },
65232
/* and.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
65233
  {
65234
    { 0, 0, 0, 0 },
65235
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
65236
    & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_SB_relative_HI, { 0x918e0000 }
65237
  },
65238
/* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
65239
  {
65240
    { 0, 0, 0, 0 },
65241
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
65242
    & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_SB_relative_HI, { 0x91ae0000 }
65243
  },
65244
/* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
65245
  {
65246
    { 0, 0, 0, 0 },
65247
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
65248
    & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_SB_relative_HI, { 0x91be0000 }
65249
  },
65250
/* and.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
65251
  {
65252
    { 0, 0, 0, 0 },
65253
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
65254
    & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_FB_relative_HI, { 0x918b0000 }
65255
  },
65256
/* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
65257
  {
65258
    { 0, 0, 0, 0 },
65259
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
65260
    & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_FB_relative_HI, { 0x91ab0000 }
65261
  },
65262
/* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
65263
  {
65264
    { 0, 0, 0, 0 },
65265
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
65266
    & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_FB_relative_HI, { 0x91bb0000 }
65267
  },
65268
/* and.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
65269
  {
65270
    { 0, 0, 0, 0 },
65271
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } },
65272
    & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_absolute_HI, { 0x918f0000 }
65273
  },
65274
/* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
65275
  {
65276
    { 0, 0, 0, 0 },
65277
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
65278
    & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_absolute_HI, { 0x91af0000 }
65279
  },
65280
/* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
65281
  {
65282
    { 0, 0, 0, 0 },
65283
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
65284
    & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_absolute_HI, { 0x91bf0000 }
65285
  },
65286
/* and.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
65287
  {
65288
    { 0, 0, 0, 0 },
65289
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } },
65290
    & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_Rn_direct_HI, { 0x91c00000 }
65291
  },
65292
/* and.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */
65293
  {
65294
    { 0, 0, 0, 0 },
65295
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } },
65296
    & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_Rn_direct_HI, { 0x91e00000 }
65297
  },
65298
/* and.w${G} ${Dsp-16-u16},$Dst16RnHI */
65299
  {
65300
    { 0, 0, 0, 0 },
65301
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16RNHI), 0 } },
65302
    & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_Rn_direct_HI, { 0x91f00000 }
65303
  },
65304
/* and.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
65305
  {
65306
    { 0, 0, 0, 0 },
65307
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } },
65308
    & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_direct_HI, { 0x91c40000 }
65309
  },
65310
/* and.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */
65311
  {
65312
    { 0, 0, 0, 0 },
65313
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } },
65314
    & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_direct_HI, { 0x91e40000 }
65315
  },
65316
/* and.w${G} ${Dsp-16-u16},$Dst16AnHI */
65317
  {
65318
    { 0, 0, 0, 0 },
65319
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16ANHI), 0 } },
65320
    & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_direct_HI, { 0x91f40000 }
65321
  },
65322
/* and.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
65323
  {
65324
    { 0, 0, 0, 0 },
65325
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
65326
    & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_indirect_HI, { 0x91c60000 }
65327
  },
65328
/* and.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */
65329
  {
65330
    { 0, 0, 0, 0 },
65331
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
65332
    & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_indirect_HI, { 0x91e60000 }
65333
  },
65334
/* and.w${G} ${Dsp-16-u16},[$Dst16An] */
65335
  {
65336
    { 0, 0, 0, 0 },
65337
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } },
65338
    & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_indirect_HI, { 0x91f60000 }
65339
  },
65340
/* and.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
65341
  {
65342
    { 0, 0, 0, 0 },
65343
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
65344
    & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_An_relative_HI, { 0x91c80000 }
65345
  },
65346
/* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
65347
  {
65348
    { 0, 0, 0, 0 },
65349
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
65350
    & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_An_relative_HI, { 0x91e80000 }
65351
  },
65352
/* and.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
65353
  {
65354
    { 0, 0, 0, 0 },
65355
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
65356
    & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_An_relative_HI, { 0x91f80000 }
65357
  },
65358
/* and.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
65359
  {
65360
    { 0, 0, 0, 0 },
65361
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
65362
    & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_An_relative_HI, { 0x91cc0000 }
65363
  },
65364
/* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
65365
  {
65366
    { 0, 0, 0, 0 },
65367
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
65368
    & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_An_relative_HI, { 0x91ec0000 }
65369
  },
65370
/* and.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
65371
  {
65372
    { 0, 0, 0, 0 },
65373
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
65374
    & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_An_relative_HI, { 0x91fc0000 }
65375
  },
65376
/* and.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
65377
  {
65378
    { 0, 0, 0, 0 },
65379
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
65380
    & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_SB_relative_HI, { 0x91ca0000 }
65381
  },
65382
/* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
65383
  {
65384
    { 0, 0, 0, 0 },
65385
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
65386
    & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_SB_relative_HI, { 0x91ea0000 }
65387
  },
65388
/* and.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
65389
  {
65390
    { 0, 0, 0, 0 },
65391
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
65392
    & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_SB_relative_HI, { 0x91fa0000 }
65393
  },
65394
/* and.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
65395
  {
65396
    { 0, 0, 0, 0 },
65397
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
65398
    & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_SB_relative_HI, { 0x91ce0000 }
65399
  },
65400
/* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
65401
  {
65402
    { 0, 0, 0, 0 },
65403
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
65404
    & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_SB_relative_HI, { 0x91ee0000 }
65405
  },
65406
/* and.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
65407
  {
65408
    { 0, 0, 0, 0 },
65409
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
65410
    & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_SB_relative_HI, { 0x91fe0000 }
65411
  },
65412
/* and.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
65413
  {
65414
    { 0, 0, 0, 0 },
65415
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
65416
    & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_FB_relative_HI, { 0x91cb0000 }
65417
  },
65418
/* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
65419
  {
65420
    { 0, 0, 0, 0 },
65421
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
65422
    & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_FB_relative_HI, { 0x91eb0000 }
65423
  },
65424
/* and.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
65425
  {
65426
    { 0, 0, 0, 0 },
65427
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
65428
    & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_FB_relative_HI, { 0x91fb0000 }
65429
  },
65430
/* and.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
65431
  {
65432
    { 0, 0, 0, 0 },
65433
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } },
65434
    & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_absolute_HI, { 0x91cf0000 }
65435
  },
65436
/* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
65437
  {
65438
    { 0, 0, 0, 0 },
65439
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
65440
    & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_absolute_HI, { 0x91ef0000 }
65441
  },
65442
/* and.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
65443
  {
65444
    { 0, 0, 0, 0 },
65445
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
65446
    & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_absolute_HI, { 0x91ff0000 }
65447
  },
65448
/* and.w${G} $Src16RnHI,$Dst16RnHI */
65449
  {
65450
    { 0, 0, 0, 0 },
65451
    { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DST16RNHI), 0 } },
65452
    & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_Rn_direct_HI, { 0x9100 }
65453
  },
65454
/* and.w${G} $Src16AnHI,$Dst16RnHI */
65455
  {
65456
    { 0, 0, 0, 0 },
65457
    { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DST16RNHI), 0 } },
65458
    & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_Rn_direct_HI, { 0x9140 }
65459
  },
65460
/* and.w${G} [$Src16An],$Dst16RnHI */
65461
  {
65462
    { 0, 0, 0, 0 },
65463
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } },
65464
    & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_Rn_direct_HI, { 0x9160 }
65465
  },
65466
/* and.w${G} $Src16RnHI,$Dst16AnHI */
65467
  {
65468
    { 0, 0, 0, 0 },
65469
    { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DST16ANHI), 0 } },
65470
    & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_direct_HI, { 0x9104 }
65471
  },
65472
/* and.w${G} $Src16AnHI,$Dst16AnHI */
65473
  {
65474
    { 0, 0, 0, 0 },
65475
    { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DST16ANHI), 0 } },
65476
    & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_direct_HI, { 0x9144 }
65477
  },
65478
/* and.w${G} [$Src16An],$Dst16AnHI */
65479
  {
65480
    { 0, 0, 0, 0 },
65481
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } },
65482
    & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_direct_HI, { 0x9164 }
65483
  },
65484
/* and.w${G} $Src16RnHI,[$Dst16An] */
65485
  {
65486
    { 0, 0, 0, 0 },
65487
    { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', '[', OP (DST16AN), ']', 0 } },
65488
    & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_indirect_HI, { 0x9106 }
65489
  },
65490
/* and.w${G} $Src16AnHI,[$Dst16An] */
65491
  {
65492
    { 0, 0, 0, 0 },
65493
    { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', '[', OP (DST16AN), ']', 0 } },
65494
    & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_indirect_HI, { 0x9146 }
65495
  },
65496
/* and.w${G} [$Src16An],[$Dst16An] */
65497
  {
65498
    { 0, 0, 0, 0 },
65499
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
65500
    & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_indirect_HI, { 0x9166 }
65501
  },
65502
/* and.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
65503
  {
65504
    { 0, 0, 0, 0 },
65505
    { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
65506
    & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_An_relative_HI, { 0x910800 }
65507
  },
65508
/* and.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
65509
  {
65510
    { 0, 0, 0, 0 },
65511
    { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
65512
    & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_An_relative_HI, { 0x914800 }
65513
  },
65514
/* and.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
65515
  {
65516
    { 0, 0, 0, 0 },
65517
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
65518
    & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_An_relative_HI, { 0x916800 }
65519
  },
65520
/* and.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
65521
  {
65522
    { 0, 0, 0, 0 },
65523
    { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
65524
    & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_An_relative_HI, { 0x910c0000 }
65525
  },
65526
/* and.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
65527
  {
65528
    { 0, 0, 0, 0 },
65529
    { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
65530
    & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_An_relative_HI, { 0x914c0000 }
65531
  },
65532
/* and.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
65533
  {
65534
    { 0, 0, 0, 0 },
65535
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
65536
    & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_An_relative_HI, { 0x916c0000 }
65537
  },
65538
/* and.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */
65539
  {
65540
    { 0, 0, 0, 0 },
65541
    { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
65542
    & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_SB_relative_HI, { 0x910a00 }
65543
  },
65544
/* and.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */
65545
  {
65546
    { 0, 0, 0, 0 },
65547
    { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
65548
    & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_SB_relative_HI, { 0x914a00 }
65549
  },
65550
/* and.w${G} [$Src16An],${Dsp-16-u8}[sb] */
65551
  {
65552
    { 0, 0, 0, 0 },
65553
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
65554
    & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_SB_relative_HI, { 0x916a00 }
65555
  },
65556
/* and.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */
65557
  {
65558
    { 0, 0, 0, 0 },
65559
    { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
65560
    & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_SB_relative_HI, { 0x910e0000 }
65561
  },
65562
/* and.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */
65563
  {
65564
    { 0, 0, 0, 0 },
65565
    { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
65566
    & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_SB_relative_HI, { 0x914e0000 }
65567
  },
65568
/* and.w${G} [$Src16An],${Dsp-16-u16}[sb] */
65569
  {
65570
    { 0, 0, 0, 0 },
65571
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
65572
    & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_SB_relative_HI, { 0x916e0000 }
65573
  },
65574
/* and.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */
65575
  {
65576
    { 0, 0, 0, 0 },
65577
    { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
65578
    & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_FB_relative_HI, { 0x910b00 }
65579
  },
65580
/* and.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */
65581
  {
65582
    { 0, 0, 0, 0 },
65583
    { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
65584
    & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_FB_relative_HI, { 0x914b00 }
65585
  },
65586
/* and.w${G} [$Src16An],${Dsp-16-s8}[fb] */
65587
  {
65588
    { 0, 0, 0, 0 },
65589
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
65590
    & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_FB_relative_HI, { 0x916b00 }
65591
  },
65592
/* and.w${G} $Src16RnHI,${Dsp-16-u16} */
65593
  {
65594
    { 0, 0, 0, 0 },
65595
    { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), 0 } },
65596
    & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_absolute_HI, { 0x910f0000 }
65597
  },
65598
/* and.w${G} $Src16AnHI,${Dsp-16-u16} */
65599
  {
65600
    { 0, 0, 0, 0 },
65601
    { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), 0 } },
65602
    & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_absolute_HI, { 0x914f0000 }
65603
  },
65604
/* and.w${G} [$Src16An],${Dsp-16-u16} */
65605
  {
65606
    { 0, 0, 0, 0 },
65607
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } },
65608
    & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_absolute_HI, { 0x916f0000 }
65609
  },
65610
/* and.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
65611
  {
65612
    { 0, 0, 0, 0 },
65613
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } },
65614
    & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_Rn_direct_QI, { 0x908000 }
65615
  },
65616
/* and.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */
65617
  {
65618
    { 0, 0, 0, 0 },
65619
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } },
65620
    & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_Rn_direct_QI, { 0x90a000 }
65621
  },
65622
/* and.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */
65623
  {
65624
    { 0, 0, 0, 0 },
65625
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNQI), 0 } },
65626
    & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_Rn_direct_QI, { 0x90b000 }
65627
  },
65628
/* and.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
65629
  {
65630
    { 0, 0, 0, 0 },
65631
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } },
65632
    & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_direct_QI, { 0x908400 }
65633
  },
65634
/* and.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */
65635
  {
65636
    { 0, 0, 0, 0 },
65637
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } },
65638
    & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_direct_QI, { 0x90a400 }
65639
  },
65640
/* and.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */
65641
  {
65642
    { 0, 0, 0, 0 },
65643
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANQI), 0 } },
65644
    & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_direct_QI, { 0x90b400 }
65645
  },
65646
/* and.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
65647
  {
65648
    { 0, 0, 0, 0 },
65649
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
65650
    & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_indirect_QI, { 0x908600 }
65651
  },
65652
/* and.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */
65653
  {
65654
    { 0, 0, 0, 0 },
65655
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
65656
    & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_indirect_QI, { 0x90a600 }
65657
  },
65658
/* and.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */
65659
  {
65660
    { 0, 0, 0, 0 },
65661
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
65662
    & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_indirect_QI, { 0x90b600 }
65663
  },
65664
/* and.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
65665
  {
65666
    { 0, 0, 0, 0 },
65667
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
65668
    & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_An_relative_QI, { 0x90880000 }
65669
  },
65670
/* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
65671
  {
65672
    { 0, 0, 0, 0 },
65673
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
65674
    & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_An_relative_QI, { 0x90a80000 }
65675
  },
65676
/* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
65677
  {
65678
    { 0, 0, 0, 0 },
65679
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
65680
    & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_An_relative_QI, { 0x90b80000 }
65681
  },
65682
/* and.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
65683
  {
65684
    { 0, 0, 0, 0 },
65685
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
65686
    & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_An_relative_QI, { 0x908c0000 }
65687
  },
65688
/* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
65689
  {
65690
    { 0, 0, 0, 0 },
65691
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
65692
    & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_An_relative_QI, { 0x90ac0000 }
65693
  },
65694
/* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
65695
  {
65696
    { 0, 0, 0, 0 },
65697
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
65698
    & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_An_relative_QI, { 0x90bc0000 }
65699
  },
65700
/* and.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
65701
  {
65702
    { 0, 0, 0, 0 },
65703
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
65704
    & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_SB_relative_QI, { 0x908a0000 }
65705
  },
65706
/* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
65707
  {
65708
    { 0, 0, 0, 0 },
65709
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
65710
    & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_SB_relative_QI, { 0x90aa0000 }
65711
  },
65712
/* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
65713
  {
65714
    { 0, 0, 0, 0 },
65715
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
65716
    & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_SB_relative_QI, { 0x90ba0000 }
65717
  },
65718
/* and.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
65719
  {
65720
    { 0, 0, 0, 0 },
65721
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
65722
    & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_SB_relative_QI, { 0x908e0000 }
65723
  },
65724
/* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
65725
  {
65726
    { 0, 0, 0, 0 },
65727
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
65728
    & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_SB_relative_QI, { 0x90ae0000 }
65729
  },
65730
/* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
65731
  {
65732
    { 0, 0, 0, 0 },
65733
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
65734
    & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_SB_relative_QI, { 0x90be0000 }
65735
  },
65736
/* and.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
65737
  {
65738
    { 0, 0, 0, 0 },
65739
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
65740
    & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_FB_relative_QI, { 0x908b0000 }
65741
  },
65742
/* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
65743
  {
65744
    { 0, 0, 0, 0 },
65745
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
65746
    & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_FB_relative_QI, { 0x90ab0000 }
65747
  },
65748
/* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
65749
  {
65750
    { 0, 0, 0, 0 },
65751
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
65752
    & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_FB_relative_QI, { 0x90bb0000 }
65753
  },
65754
/* and.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
65755
  {
65756
    { 0, 0, 0, 0 },
65757
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } },
65758
    & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_absolute_QI, { 0x908f0000 }
65759
  },
65760
/* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
65761
  {
65762
    { 0, 0, 0, 0 },
65763
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
65764
    & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_absolute_QI, { 0x90af0000 }
65765
  },
65766
/* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
65767
  {
65768
    { 0, 0, 0, 0 },
65769
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
65770
    & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_absolute_QI, { 0x90bf0000 }
65771
  },
65772
/* and.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
65773
  {
65774
    { 0, 0, 0, 0 },
65775
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } },
65776
    & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_Rn_direct_QI, { 0x90c00000 }
65777
  },
65778
/* and.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */
65779
  {
65780
    { 0, 0, 0, 0 },
65781
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } },
65782
    & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_Rn_direct_QI, { 0x90e00000 }
65783
  },
65784
/* and.b${G} ${Dsp-16-u16},$Dst16RnQI */
65785
  {
65786
    { 0, 0, 0, 0 },
65787
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16RNQI), 0 } },
65788
    & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_Rn_direct_QI, { 0x90f00000 }
65789
  },
65790
/* and.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
65791
  {
65792
    { 0, 0, 0, 0 },
65793
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } },
65794
    & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_direct_QI, { 0x90c40000 }
65795
  },
65796
/* and.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */
65797
  {
65798
    { 0, 0, 0, 0 },
65799
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } },
65800
    & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_direct_QI, { 0x90e40000 }
65801
  },
65802
/* and.b${G} ${Dsp-16-u16},$Dst16AnQI */
65803
  {
65804
    { 0, 0, 0, 0 },
65805
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16ANQI), 0 } },
65806
    & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_direct_QI, { 0x90f40000 }
65807
  },
65808
/* and.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
65809
  {
65810
    { 0, 0, 0, 0 },
65811
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
65812
    & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_indirect_QI, { 0x90c60000 }
65813
  },
65814
/* and.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */
65815
  {
65816
    { 0, 0, 0, 0 },
65817
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
65818
    & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_indirect_QI, { 0x90e60000 }
65819
  },
65820
/* and.b${G} ${Dsp-16-u16},[$Dst16An] */
65821
  {
65822
    { 0, 0, 0, 0 },
65823
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } },
65824
    & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_indirect_QI, { 0x90f60000 }
65825
  },
65826
/* and.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
65827
  {
65828
    { 0, 0, 0, 0 },
65829
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
65830
    & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_An_relative_QI, { 0x90c80000 }
65831
  },
65832
/* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
65833
  {
65834
    { 0, 0, 0, 0 },
65835
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
65836
    & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_An_relative_QI, { 0x90e80000 }
65837
  },
65838
/* and.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
65839
  {
65840
    { 0, 0, 0, 0 },
65841
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
65842
    & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_An_relative_QI, { 0x90f80000 }
65843
  },
65844
/* and.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
65845
  {
65846
    { 0, 0, 0, 0 },
65847
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
65848
    & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_An_relative_QI, { 0x90cc0000 }
65849
  },
65850
/* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
65851
  {
65852
    { 0, 0, 0, 0 },
65853
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
65854
    & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_An_relative_QI, { 0x90ec0000 }
65855
  },
65856
/* and.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
65857
  {
65858
    { 0, 0, 0, 0 },
65859
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
65860
    & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_An_relative_QI, { 0x90fc0000 }
65861
  },
65862
/* and.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
65863
  {
65864
    { 0, 0, 0, 0 },
65865
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
65866
    & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_SB_relative_QI, { 0x90ca0000 }
65867
  },
65868
/* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
65869
  {
65870
    { 0, 0, 0, 0 },
65871
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
65872
    & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_SB_relative_QI, { 0x90ea0000 }
65873
  },
65874
/* and.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
65875
  {
65876
    { 0, 0, 0, 0 },
65877
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
65878
    & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_SB_relative_QI, { 0x90fa0000 }
65879
  },
65880
/* and.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
65881
  {
65882
    { 0, 0, 0, 0 },
65883
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
65884
    & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_SB_relative_QI, { 0x90ce0000 }
65885
  },
65886
/* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
65887
  {
65888
    { 0, 0, 0, 0 },
65889
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
65890
    & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_SB_relative_QI, { 0x90ee0000 }
65891
  },
65892
/* and.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
65893
  {
65894
    { 0, 0, 0, 0 },
65895
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
65896
    & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_SB_relative_QI, { 0x90fe0000 }
65897
  },
65898
/* and.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
65899
  {
65900
    { 0, 0, 0, 0 },
65901
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
65902
    & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_FB_relative_QI, { 0x90cb0000 }
65903
  },
65904
/* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
65905
  {
65906
    { 0, 0, 0, 0 },
65907
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
65908
    & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_FB_relative_QI, { 0x90eb0000 }
65909
  },
65910
/* and.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
65911
  {
65912
    { 0, 0, 0, 0 },
65913
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
65914
    & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_FB_relative_QI, { 0x90fb0000 }
65915
  },
65916
/* and.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
65917
  {
65918
    { 0, 0, 0, 0 },
65919
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } },
65920
    & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_absolute_QI, { 0x90cf0000 }
65921
  },
65922
/* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
65923
  {
65924
    { 0, 0, 0, 0 },
65925
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
65926
    & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_absolute_QI, { 0x90ef0000 }
65927
  },
65928
/* and.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
65929
  {
65930
    { 0, 0, 0, 0 },
65931
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
65932
    & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_absolute_QI, { 0x90ff0000 }
65933
  },
65934
/* and.b${G} $Src16RnQI,$Dst16RnQI */
65935
  {
65936
    { 0, 0, 0, 0 },
65937
    { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DST16RNQI), 0 } },
65938
    & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_Rn_direct_QI, { 0x9000 }
65939
  },
65940
/* and.b${G} $Src16AnQI,$Dst16RnQI */
65941
  {
65942
    { 0, 0, 0, 0 },
65943
    { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DST16RNQI), 0 } },
65944
    & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_Rn_direct_QI, { 0x9040 }
65945
  },
65946
/* and.b${G} [$Src16An],$Dst16RnQI */
65947
  {
65948
    { 0, 0, 0, 0 },
65949
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } },
65950
    & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_Rn_direct_QI, { 0x9060 }
65951
  },
65952
/* and.b${G} $Src16RnQI,$Dst16AnQI */
65953
  {
65954
    { 0, 0, 0, 0 },
65955
    { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DST16ANQI), 0 } },
65956
    & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_direct_QI, { 0x9004 }
65957
  },
65958
/* and.b${G} $Src16AnQI,$Dst16AnQI */
65959
  {
65960
    { 0, 0, 0, 0 },
65961
    { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DST16ANQI), 0 } },
65962
    & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_direct_QI, { 0x9044 }
65963
  },
65964
/* and.b${G} [$Src16An],$Dst16AnQI */
65965
  {
65966
    { 0, 0, 0, 0 },
65967
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } },
65968
    & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_direct_QI, { 0x9064 }
65969
  },
65970
/* and.b${G} $Src16RnQI,[$Dst16An] */
65971
  {
65972
    { 0, 0, 0, 0 },
65973
    { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', '[', OP (DST16AN), ']', 0 } },
65974
    & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_indirect_QI, { 0x9006 }
65975
  },
65976
/* and.b${G} $Src16AnQI,[$Dst16An] */
65977
  {
65978
    { 0, 0, 0, 0 },
65979
    { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', '[', OP (DST16AN), ']', 0 } },
65980
    & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_indirect_QI, { 0x9046 }
65981
  },
65982
/* and.b${G} [$Src16An],[$Dst16An] */
65983
  {
65984
    { 0, 0, 0, 0 },
65985
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
65986
    & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_indirect_QI, { 0x9066 }
65987
  },
65988
/* and.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
65989
  {
65990
    { 0, 0, 0, 0 },
65991
    { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
65992
    & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_An_relative_QI, { 0x900800 }
65993
  },
65994
/* and.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
65995
  {
65996
    { 0, 0, 0, 0 },
65997
    { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
65998
    & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_An_relative_QI, { 0x904800 }
65999
  },
66000
/* and.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
66001
  {
66002
    { 0, 0, 0, 0 },
66003
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
66004
    & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_An_relative_QI, { 0x906800 }
66005
  },
66006
/* and.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
66007
  {
66008
    { 0, 0, 0, 0 },
66009
    { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
66010
    & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_An_relative_QI, { 0x900c0000 }
66011
  },
66012
/* and.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
66013
  {
66014
    { 0, 0, 0, 0 },
66015
    { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
66016
    & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_An_relative_QI, { 0x904c0000 }
66017
  },
66018
/* and.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
66019
  {
66020
    { 0, 0, 0, 0 },
66021
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
66022
    & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_An_relative_QI, { 0x906c0000 }
66023
  },
66024
/* and.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */
66025
  {
66026
    { 0, 0, 0, 0 },
66027
    { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
66028
    & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_SB_relative_QI, { 0x900a00 }
66029
  },
66030
/* and.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */
66031
  {
66032
    { 0, 0, 0, 0 },
66033
    { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
66034
    & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_SB_relative_QI, { 0x904a00 }
66035
  },
66036
/* and.b${G} [$Src16An],${Dsp-16-u8}[sb] */
66037
  {
66038
    { 0, 0, 0, 0 },
66039
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
66040
    & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_SB_relative_QI, { 0x906a00 }
66041
  },
66042
/* and.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */
66043
  {
66044
    { 0, 0, 0, 0 },
66045
    { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
66046
    & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_SB_relative_QI, { 0x900e0000 }
66047
  },
66048
/* and.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */
66049
  {
66050
    { 0, 0, 0, 0 },
66051
    { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
66052
    & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_SB_relative_QI, { 0x904e0000 }
66053
  },
66054
/* and.b${G} [$Src16An],${Dsp-16-u16}[sb] */
66055
  {
66056
    { 0, 0, 0, 0 },
66057
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
66058
    & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_SB_relative_QI, { 0x906e0000 }
66059
  },
66060
/* and.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */
66061
  {
66062
    { 0, 0, 0, 0 },
66063
    { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
66064
    & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_FB_relative_QI, { 0x900b00 }
66065
  },
66066
/* and.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */
66067
  {
66068
    { 0, 0, 0, 0 },
66069
    { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
66070
    & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_FB_relative_QI, { 0x904b00 }
66071
  },
66072
/* and.b${G} [$Src16An],${Dsp-16-s8}[fb] */
66073
  {
66074
    { 0, 0, 0, 0 },
66075
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
66076
    & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_FB_relative_QI, { 0x906b00 }
66077
  },
66078
/* and.b${G} $Src16RnQI,${Dsp-16-u16} */
66079
  {
66080
    { 0, 0, 0, 0 },
66081
    { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), 0 } },
66082
    & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_absolute_QI, { 0x900f0000 }
66083
  },
66084
/* and.b${G} $Src16AnQI,${Dsp-16-u16} */
66085
  {
66086
    { 0, 0, 0, 0 },
66087
    { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), 0 } },
66088
    & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_absolute_QI, { 0x904f0000 }
66089
  },
66090
/* and.b${G} [$Src16An],${Dsp-16-u16} */
66091
  {
66092
    { 0, 0, 0, 0 },
66093
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } },
66094
    & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_absolute_QI, { 0x906f0000 }
66095
  },
66096
/* and.b${S} #${Imm-8-QI},r0l */
66097
  {
66098
    { 0, 0, 0, 0 },
66099
    { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'l', 0 } },
66100
    & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_R0l_direct_QI, { 0x9400 }
66101
  },
66102
/* and.b${S} #${Imm-8-QI},r0h */
66103
  {
66104
    { 0, 0, 0, 0 },
66105
    { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'h', 0 } },
66106
    & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_R0h_direct_QI, { 0x9300 }
66107
  },
66108
/* and.b${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */
66109
  {
66110
    { 0, 0, 0, 0 },
66111
    { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
66112
    & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_8_SB_relative_QI, { 0x950000 }
66113
  },
66114
/* and.b${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */
66115
  {
66116
    { 0, 0, 0, 0 },
66117
    { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
66118
    & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_8_FB_relative_QI, { 0x960000 }
66119
  },
66120
/* and.b${S} #${Imm-8-QI},${Dsp-16-u16} */
66121
  {
66122
    { 0, 0, 0, 0 },
66123
    { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_U16), 0 } },
66124
    & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_16_absolute_QI, { 0x97000000 }
66125
  },
66126
/* and.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */
66127
  {
66128
    { 0, 0, 0, 0 },
66129
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
66130
    & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0x893f0000 }
66131
  },
66132
/* and.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */
66133
  {
66134
    { 0, 0, 0, 0 },
66135
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
66136
    & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0x81bf0000 }
66137
  },
66138
/* and.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */
66139
  {
66140
    { 0, 0, 0, 0 },
66141
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66142
    & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0x813f0000 }
66143
  },
66144
/* and.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
66145
  {
66146
    { 0, 0, 0, 0 },
66147
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66148
    & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0x833f0000 }
66149
  },
66150
/* and.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
66151
  {
66152
    { 0, 0, 0, 0 },
66153
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
66154
    & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0x83bf0000 }
66155
  },
66156
/* and.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
66157
  {
66158
    { 0, 0, 0, 0 },
66159
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
66160
    & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83ff0000 }
66161
  },
66162
/* and.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
66163
  {
66164
    { 0, 0, 0, 0 },
66165
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66166
    & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0x853f0000 }
66167
  },
66168
/* and.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
66169
  {
66170
    { 0, 0, 0, 0 },
66171
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
66172
    & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0x85bf0000 }
66173
  },
66174
/* and.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */
66175
  {
66176
    { 0, 0, 0, 0 },
66177
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
66178
    & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85ff0000 }
66179
  },
66180
/* and.w${G} #${Imm-32-HI},${Dsp-16-u16} */
66181
  {
66182
    { 0, 0, 0, 0 },
66183
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } },
66184
    & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0x87ff0000 }
66185
  },
66186
/* and.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
66187
  {
66188
    { 0, 0, 0, 0 },
66189
    { { MNEM, OP (G), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66190
    & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0x873f0000 }
66191
  },
66192
/* and.w${G} #${Imm-40-HI},${Dsp-16-u24} */
66193
  {
66194
    { 0, 0, 0, 0 },
66195
    { { MNEM, OP (G), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), 0 } },
66196
    & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0x87bf0000 }
66197
  },
66198
/* and.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */
66199
  {
66200
    { 0, 0, 0, 0 },
66201
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
66202
    & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0x883f00 }
66203
  },
66204
/* and.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */
66205
  {
66206
    { 0, 0, 0, 0 },
66207
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
66208
    & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0x80bf00 }
66209
  },
66210
/* and.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */
66211
  {
66212
    { 0, 0, 0, 0 },
66213
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66214
    & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0x803f00 }
66215
  },
66216
/* and.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
66217
  {
66218
    { 0, 0, 0, 0 },
66219
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66220
    & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0x823f0000 }
66221
  },
66222
/* and.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
66223
  {
66224
    { 0, 0, 0, 0 },
66225
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
66226
    & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0x82bf0000 }
66227
  },
66228
/* and.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
66229
  {
66230
    { 0, 0, 0, 0 },
66231
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
66232
    & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82ff0000 }
66233
  },
66234
/* and.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
66235
  {
66236
    { 0, 0, 0, 0 },
66237
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66238
    & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0x843f0000 }
66239
  },
66240
/* and.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
66241
  {
66242
    { 0, 0, 0, 0 },
66243
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
66244
    & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0x84bf0000 }
66245
  },
66246
/* and.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */
66247
  {
66248
    { 0, 0, 0, 0 },
66249
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
66250
    & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84ff0000 }
66251
  },
66252
/* and.b${G} #${Imm-32-QI},${Dsp-16-u16} */
66253
  {
66254
    { 0, 0, 0, 0 },
66255
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } },
66256
    & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0x86ff0000 }
66257
  },
66258
/* and.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
66259
  {
66260
    { 0, 0, 0, 0 },
66261
    { { MNEM, OP (G), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66262
    & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0x863f0000 }
66263
  },
66264
/* and.b${G} #${Imm-40-QI},${Dsp-16-u24} */
66265
  {
66266
    { 0, 0, 0, 0 },
66267
    { { MNEM, OP (G), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), 0 } },
66268
    & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0x86bf0000 }
66269
  },
66270
/* and.w${G} #${Imm-16-HI},$Dst16RnHI */
66271
  {
66272
    { 0, 0, 0, 0 },
66273
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST16RNHI), 0 } },
66274
    & ifmt_xor16_w_imm_G_basic_dst16_Rn_direct_HI, { 0x77200000 }
66275
  },
66276
/* and.w${G} #${Imm-16-HI},$Dst16AnHI */
66277
  {
66278
    { 0, 0, 0, 0 },
66279
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST16ANHI), 0 } },
66280
    & ifmt_xor16_w_imm_G_basic_dst16_An_direct_HI, { 0x77240000 }
66281
  },
66282
/* and.w${G} #${Imm-16-HI},[$Dst16An] */
66283
  {
66284
    { 0, 0, 0, 0 },
66285
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST16AN), ']', 0 } },
66286
    & ifmt_xor16_w_imm_G_basic_dst16_An_indirect_HI, { 0x77260000 }
66287
  },
66288
/* and.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
66289
  {
66290
    { 0, 0, 0, 0 },
66291
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
66292
    & ifmt_xor16_w_imm_G_16_8_dst16_16_8_An_relative_HI, { 0x77280000 }
66293
  },
66294
/* and.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
66295
  {
66296
    { 0, 0, 0, 0 },
66297
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
66298
    & ifmt_xor16_w_imm_G_16_8_dst16_16_8_SB_relative_HI, { 0x772a0000 }
66299
  },
66300
/* and.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
66301
  {
66302
    { 0, 0, 0, 0 },
66303
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
66304
    & ifmt_xor16_w_imm_G_16_8_dst16_16_8_FB_relative_HI, { 0x772b0000 }
66305
  },
66306
/* and.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
66307
  {
66308
    { 0, 0, 0, 0 },
66309
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
66310
    & ifmt_xor16_w_imm_G_16_16_dst16_16_16_An_relative_HI, { 0x772c0000 }
66311
  },
66312
/* and.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
66313
  {
66314
    { 0, 0, 0, 0 },
66315
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
66316
    & ifmt_xor16_w_imm_G_16_16_dst16_16_16_SB_relative_HI, { 0x772e0000 }
66317
  },
66318
/* and.w${G} #${Imm-32-HI},${Dsp-16-u16} */
66319
  {
66320
    { 0, 0, 0, 0 },
66321
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } },
66322
    & ifmt_xor16_w_imm_G_16_16_dst16_16_16_absolute_HI, { 0x772f0000 }
66323
  },
66324
/* and.b${G} #${Imm-16-QI},$Dst16RnQI */
66325
  {
66326
    { 0, 0, 0, 0 },
66327
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST16RNQI), 0 } },
66328
    & ifmt_xor16_b_imm_G_basic_dst16_Rn_direct_QI, { 0x762000 }
66329
  },
66330
/* and.b${G} #${Imm-16-QI},$Dst16AnQI */
66331
  {
66332
    { 0, 0, 0, 0 },
66333
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST16ANQI), 0 } },
66334
    & ifmt_xor16_b_imm_G_basic_dst16_An_direct_QI, { 0x762400 }
66335
  },
66336
/* and.b${G} #${Imm-16-QI},[$Dst16An] */
66337
  {
66338
    { 0, 0, 0, 0 },
66339
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST16AN), ']', 0 } },
66340
    & ifmt_xor16_b_imm_G_basic_dst16_An_indirect_QI, { 0x762600 }
66341
  },
66342
/* and.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
66343
  {
66344
    { 0, 0, 0, 0 },
66345
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
66346
    & ifmt_xor16_b_imm_G_16_8_dst16_16_8_An_relative_QI, { 0x76280000 }
66347
  },
66348
/* and.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
66349
  {
66350
    { 0, 0, 0, 0 },
66351
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
66352
    & ifmt_xor16_b_imm_G_16_8_dst16_16_8_SB_relative_QI, { 0x762a0000 }
66353
  },
66354
/* and.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
66355
  {
66356
    { 0, 0, 0, 0 },
66357
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
66358
    & ifmt_xor16_b_imm_G_16_8_dst16_16_8_FB_relative_QI, { 0x762b0000 }
66359
  },
66360
/* and.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
66361
  {
66362
    { 0, 0, 0, 0 },
66363
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
66364
    & ifmt_xor16_b_imm_G_16_16_dst16_16_16_An_relative_QI, { 0x762c0000 }
66365
  },
66366
/* and.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
66367
  {
66368
    { 0, 0, 0, 0 },
66369
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
66370
    & ifmt_xor16_b_imm_G_16_16_dst16_16_16_SB_relative_QI, { 0x762e0000 }
66371
  },
66372
/* and.b${G} #${Imm-32-QI},${Dsp-16-u16} */
66373
  {
66374
    { 0, 0, 0, 0 },
66375
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } },
66376
    & ifmt_xor16_b_imm_G_16_16_dst16_16_16_absolute_QI, { 0x762f0000 }
66377
  },
66378
/* adjnz.w #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed],${Lab-24-8} */
66379
  {
66380
    { 0, 0, 0, 0 },
66381
    { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (LAB_24_8), 0 } },
66382
    & ifmt_adjnz32_w_imm4_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0xf3100000 }
66383
  },
66384
/* adjnz.w #${Imm-12-s4},${Dsp-16-u8}[sb],${Lab-24-8} */
66385
  {
66386
    { 0, 0, 0, 0 },
66387
    { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (LAB_24_8), 0 } },
66388
    & ifmt_adjnz32_w_imm4_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0xf3900000 }
66389
  },
66390
/* adjnz.w #${Imm-12-s4},${Dsp-16-s8}[fb],${Lab-24-8} */
66391
  {
66392
    { 0, 0, 0, 0 },
66393
    { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (LAB_24_8), 0 } },
66394
    & ifmt_adjnz32_w_imm4_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0xf3d00000 }
66395
  },
66396
/* adjnz.w #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed],${Lab-32-8} */
66397
  {
66398
    { 0, 0, 0, 0 },
66399
    { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (LAB_32_8), 0 } },
66400
    & ifmt_adjnz32_w_imm4_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0xf5100000 }
66401
  },
66402
/* adjnz.w #${Imm-12-s4},${Dsp-16-u16}[sb],${Lab-32-8} */
66403
  {
66404
    { 0, 0, 0, 0 },
66405
    { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (LAB_32_8), 0 } },
66406
    & ifmt_adjnz32_w_imm4_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0xf5900000 }
66407
  },
66408
/* adjnz.w #${Imm-12-s4},${Dsp-16-s16}[fb],${Lab-32-8} */
66409
  {
66410
    { 0, 0, 0, 0 },
66411
    { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (LAB_32_8), 0 } },
66412
    & ifmt_adjnz32_w_imm4_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0xf5d00000 }
66413
  },
66414
/* adjnz.w #${Imm-12-s4},${Dsp-16-u16},${Lab-32-8} */
66415
  {
66416
    { 0, 0, 0, 0 },
66417
    { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), ',', OP (LAB_32_8), 0 } },
66418
    & ifmt_adjnz32_w_imm4_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0xf7d00000 }
66419
  },
66420
/* adjnz.w #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed],${Lab-40-8} */
66421
  {
66422
    { 0, 0, 0, 0 },
66423
    { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (LAB_40_8), 0 } },
66424
    & ifmt_adjnz32_w_imm4_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0xf7100000 }
66425
  },
66426
/* adjnz.w #${Imm-12-s4},${Dsp-16-u24},${Lab-40-8} */
66427
  {
66428
    { 0, 0, 0, 0 },
66429
    { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U24), ',', OP (LAB_40_8), 0 } },
66430
    & ifmt_adjnz32_w_imm4_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0xf7900000 }
66431
  },
66432
/* adjnz.w #${Imm-12-s4},$Dst32RnUnprefixedHI,${Lab-16-8} */
66433
  {
66434
    { 0, 0, 0, 0 },
66435
    { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DST32RNUNPREFIXEDHI), ',', OP (LAB_16_8), 0 } },
66436
    & ifmt_adjnz32_w_imm4_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0xf91000 }
66437
  },
66438
/* adjnz.w #${Imm-12-s4},$Dst32AnUnprefixedHI,${Lab-16-8} */
66439
  {
66440
    { 0, 0, 0, 0 },
66441
    { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DST32ANUNPREFIXEDHI), ',', OP (LAB_16_8), 0 } },
66442
    & ifmt_adjnz32_w_imm4_basic_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0xf19000 }
66443
  },
66444
/* adjnz.w #${Imm-12-s4},[$Dst32AnUnprefixed],${Lab-16-8} */
66445
  {
66446
    { 0, 0, 0, 0 },
66447
    { { MNEM, ' ', '#', OP (IMM_12_S4), ',', '[', OP (DST32ANUNPREFIXED), ']', ',', OP (LAB_16_8), 0 } },
66448
    & ifmt_adjnz32_w_imm4_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0xf11000 }
66449
  },
66450
/* adjnz.b #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed],${Lab-24-8} */
66451
  {
66452
    { 0, 0, 0, 0 },
66453
    { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (LAB_24_8), 0 } },
66454
    & ifmt_adjnz32_b_imm4_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0xf2100000 }
66455
  },
66456
/* adjnz.b #${Imm-12-s4},${Dsp-16-u8}[sb],${Lab-24-8} */
66457
  {
66458
    { 0, 0, 0, 0 },
66459
    { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (LAB_24_8), 0 } },
66460
    & ifmt_adjnz32_b_imm4_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0xf2900000 }
66461
  },
66462
/* adjnz.b #${Imm-12-s4},${Dsp-16-s8}[fb],${Lab-24-8} */
66463
  {
66464
    { 0, 0, 0, 0 },
66465
    { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (LAB_24_8), 0 } },
66466
    & ifmt_adjnz32_b_imm4_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0xf2d00000 }
66467
  },
66468
/* adjnz.b #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed],${Lab-32-8} */
66469
  {
66470
    { 0, 0, 0, 0 },
66471
    { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (LAB_32_8), 0 } },
66472
    & ifmt_adjnz32_b_imm4_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0xf4100000 }
66473
  },
66474
/* adjnz.b #${Imm-12-s4},${Dsp-16-u16}[sb],${Lab-32-8} */
66475
  {
66476
    { 0, 0, 0, 0 },
66477
    { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (LAB_32_8), 0 } },
66478
    & ifmt_adjnz32_b_imm4_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0xf4900000 }
66479
  },
66480
/* adjnz.b #${Imm-12-s4},${Dsp-16-s16}[fb],${Lab-32-8} */
66481
  {
66482
    { 0, 0, 0, 0 },
66483
    { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (LAB_32_8), 0 } },
66484
    & ifmt_adjnz32_b_imm4_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0xf4d00000 }
66485
  },
66486
/* adjnz.b #${Imm-12-s4},${Dsp-16-u16},${Lab-32-8} */
66487
  {
66488
    { 0, 0, 0, 0 },
66489
    { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), ',', OP (LAB_32_8), 0 } },
66490
    & ifmt_adjnz32_b_imm4_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0xf6d00000 }
66491
  },
66492
/* adjnz.b #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed],${Lab-40-8} */
66493
  {
66494
    { 0, 0, 0, 0 },
66495
    { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (LAB_40_8), 0 } },
66496
    & ifmt_adjnz32_b_imm4_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0xf6100000 }
66497
  },
66498
/* adjnz.b #${Imm-12-s4},${Dsp-16-u24},${Lab-40-8} */
66499
  {
66500
    { 0, 0, 0, 0 },
66501
    { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U24), ',', OP (LAB_40_8), 0 } },
66502
    & ifmt_adjnz32_b_imm4_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0xf6900000 }
66503
  },
66504
/* adjnz.b #${Imm-12-s4},$Dst32RnUnprefixedQI,${Lab-16-8} */
66505
  {
66506
    { 0, 0, 0, 0 },
66507
    { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DST32RNUNPREFIXEDQI), ',', OP (LAB_16_8), 0 } },
66508
    & ifmt_adjnz32_b_imm4_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0xf81000 }
66509
  },
66510
/* adjnz.b #${Imm-12-s4},$Dst32AnUnprefixedQI,${Lab-16-8} */
66511
  {
66512
    { 0, 0, 0, 0 },
66513
    { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DST32ANUNPREFIXEDQI), ',', OP (LAB_16_8), 0 } },
66514
    & ifmt_adjnz32_b_imm4_basic_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0xf09000 }
66515
  },
66516
/* adjnz.b #${Imm-12-s4},[$Dst32AnUnprefixed],${Lab-16-8} */
66517
  {
66518
    { 0, 0, 0, 0 },
66519
    { { MNEM, ' ', '#', OP (IMM_12_S4), ',', '[', OP (DST32ANUNPREFIXED), ']', ',', OP (LAB_16_8), 0 } },
66520
    & ifmt_adjnz32_b_imm4_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0xf01000 }
66521
  },
66522
/* adjnz.w #${Imm-8-s4},${Dsp-16-u8}[$Dst16An],${Lab-24-8} */
66523
  {
66524
    { 0, 0, 0, 0 },
66525
    { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', OP (LAB_24_8), 0 } },
66526
    & ifmt_adjnz16_w_imm4_16_8_dst16_16_8_An_relative_HI, { 0xf9080000 }
66527
  },
66528
/* adjnz.w #${Imm-8-s4},${Dsp-16-u8}[sb],${Lab-24-8} */
66529
  {
66530
    { 0, 0, 0, 0 },
66531
    { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (LAB_24_8), 0 } },
66532
    & ifmt_adjnz16_w_imm4_16_8_dst16_16_8_SB_relative_HI, { 0xf90a0000 }
66533
  },
66534
/* adjnz.w #${Imm-8-s4},${Dsp-16-s8}[fb],${Lab-24-8} */
66535
  {
66536
    { 0, 0, 0, 0 },
66537
    { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (LAB_24_8), 0 } },
66538
    & ifmt_adjnz16_w_imm4_16_8_dst16_16_8_FB_relative_HI, { 0xf90b0000 }
66539
  },
66540
/* adjnz.w #${Imm-8-s4},${Dsp-16-u16}[$Dst16An],${Lab-32-8} */
66541
  {
66542
    { 0, 0, 0, 0 },
66543
    { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', OP (LAB_32_8), 0 } },
66544
    & ifmt_adjnz16_w_imm4_16_16_dst16_16_16_An_relative_HI, { 0xf90c0000 }
66545
  },
66546
/* adjnz.w #${Imm-8-s4},${Dsp-16-u16}[sb],${Lab-32-8} */
66547
  {
66548
    { 0, 0, 0, 0 },
66549
    { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (LAB_32_8), 0 } },
66550
    & ifmt_adjnz16_w_imm4_16_16_dst16_16_16_SB_relative_HI, { 0xf90e0000 }
66551
  },
66552
/* adjnz.w #${Imm-8-s4},${Dsp-16-u16},${Lab-32-8} */
66553
  {
66554
    { 0, 0, 0, 0 },
66555
    { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), ',', OP (LAB_32_8), 0 } },
66556
    & ifmt_adjnz16_w_imm4_16_16_dst16_16_16_absolute_HI, { 0xf90f0000 }
66557
  },
66558
/* adjnz.w #${Imm-8-s4},$Dst16RnHI,${Lab-16-8} */
66559
  {
66560
    { 0, 0, 0, 0 },
66561
    { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DST16RNHI), ',', OP (LAB_16_8), 0 } },
66562
    & ifmt_adjnz16_w_imm4_basic_dst16_Rn_direct_HI, { 0xf90000 }
66563
  },
66564
/* adjnz.w #${Imm-8-s4},$Dst16AnHI,${Lab-16-8} */
66565
  {
66566
    { 0, 0, 0, 0 },
66567
    { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DST16ANHI), ',', OP (LAB_16_8), 0 } },
66568
    & ifmt_adjnz16_w_imm4_basic_dst16_An_direct_HI, { 0xf90400 }
66569
  },
66570
/* adjnz.w #${Imm-8-s4},[$Dst16An],${Lab-16-8} */
66571
  {
66572
    { 0, 0, 0, 0 },
66573
    { { MNEM, ' ', '#', OP (IMM_8_S4), ',', '[', OP (DST16AN), ']', ',', OP (LAB_16_8), 0 } },
66574
    & ifmt_adjnz16_w_imm4_basic_dst16_An_indirect_HI, { 0xf90600 }
66575
  },
66576
/* adjnz.b #${Imm-8-s4},${Dsp-16-u8}[$Dst16An],${Lab-24-8} */
66577
  {
66578
    { 0, 0, 0, 0 },
66579
    { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', OP (LAB_24_8), 0 } },
66580
    & ifmt_adjnz16_b_imm4_16_8_dst16_16_8_An_relative_QI, { 0xf8080000 }
66581
  },
66582
/* adjnz.b #${Imm-8-s4},${Dsp-16-u8}[sb],${Lab-24-8} */
66583
  {
66584
    { 0, 0, 0, 0 },
66585
    { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (LAB_24_8), 0 } },
66586
    & ifmt_adjnz16_b_imm4_16_8_dst16_16_8_SB_relative_QI, { 0xf80a0000 }
66587
  },
66588
/* adjnz.b #${Imm-8-s4},${Dsp-16-s8}[fb],${Lab-24-8} */
66589
  {
66590
    { 0, 0, 0, 0 },
66591
    { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (LAB_24_8), 0 } },
66592
    & ifmt_adjnz16_b_imm4_16_8_dst16_16_8_FB_relative_QI, { 0xf80b0000 }
66593
  },
66594
/* adjnz.b #${Imm-8-s4},${Dsp-16-u16}[$Dst16An],${Lab-32-8} */
66595
  {
66596
    { 0, 0, 0, 0 },
66597
    { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', OP (LAB_32_8), 0 } },
66598
    & ifmt_adjnz16_b_imm4_16_16_dst16_16_16_An_relative_QI, { 0xf80c0000 }
66599
  },
66600
/* adjnz.b #${Imm-8-s4},${Dsp-16-u16}[sb],${Lab-32-8} */
66601
  {
66602
    { 0, 0, 0, 0 },
66603
    { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (LAB_32_8), 0 } },
66604
    & ifmt_adjnz16_b_imm4_16_16_dst16_16_16_SB_relative_QI, { 0xf80e0000 }
66605
  },
66606
/* adjnz.b #${Imm-8-s4},${Dsp-16-u16},${Lab-32-8} */
66607
  {
66608
    { 0, 0, 0, 0 },
66609
    { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), ',', OP (LAB_32_8), 0 } },
66610
    & ifmt_adjnz16_b_imm4_16_16_dst16_16_16_absolute_QI, { 0xf80f0000 }
66611
  },
66612
/* adjnz.b #${Imm-8-s4},$Dst16RnQI,${Lab-16-8} */
66613
  {
66614
    { 0, 0, 0, 0 },
66615
    { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DST16RNQI), ',', OP (LAB_16_8), 0 } },
66616
    & ifmt_adjnz16_b_imm4_basic_dst16_Rn_direct_QI, { 0xf80000 }
66617
  },
66618
/* adjnz.b #${Imm-8-s4},$Dst16AnQI,${Lab-16-8} */
66619
  {
66620
    { 0, 0, 0, 0 },
66621
    { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DST16ANQI), ',', OP (LAB_16_8), 0 } },
66622
    & ifmt_adjnz16_b_imm4_basic_dst16_An_direct_QI, { 0xf80400 }
66623
  },
66624
/* adjnz.b #${Imm-8-s4},[$Dst16An],${Lab-16-8} */
66625
  {
66626
    { 0, 0, 0, 0 },
66627
    { { MNEM, ' ', '#', OP (IMM_8_S4), ',', '[', OP (DST16AN), ']', ',', OP (LAB_16_8), 0 } },
66628
    & ifmt_adjnz16_b_imm4_basic_dst16_An_indirect_QI, { 0xf80600 }
66629
  },
66630
/* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
66631
  {
66632
    { 0, 0, 0, 0 },
66633
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
66634
    & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0x980200 }
66635
  },
66636
/* addx${X} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedSI */
66637
  {
66638
    { 0, 0, 0, 0 },
66639
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
66640
    & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0x982200 }
66641
  },
66642
/* addx${X} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedSI */
66643
  {
66644
    { 0, 0, 0, 0 },
66645
    { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
66646
    & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0x983200 }
66647
  },
66648
/* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
66649
  {
66650
    { 0, 0, 0, 0 },
66651
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
66652
    & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0x908200 }
66653
  },
66654
/* addx${X} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedSI */
66655
  {
66656
    { 0, 0, 0, 0 },
66657
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
66658
    & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0x90a200 }
66659
  },
66660
/* addx${X} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedSI */
66661
  {
66662
    { 0, 0, 0, 0 },
66663
    { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
66664
    & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0x90b200 }
66665
  },
66666
/* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
66667
  {
66668
    { 0, 0, 0, 0 },
66669
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66670
    & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0x900200 }
66671
  },
66672
/* addx${X} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
66673
  {
66674
    { 0, 0, 0, 0 },
66675
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66676
    & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0x902200 }
66677
  },
66678
/* addx${X} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
66679
  {
66680
    { 0, 0, 0, 0 },
66681
    { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66682
    & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0x903200 }
66683
  },
66684
/* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
66685
  {
66686
    { 0, 0, 0, 0 },
66687
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66688
    & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_SI, { 0x92020000 }
66689
  },
66690
/* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
66691
  {
66692
    { 0, 0, 0, 0 },
66693
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66694
    & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_SI, { 0x92220000 }
66695
  },
66696
/* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
66697
  {
66698
    { 0, 0, 0, 0 },
66699
    { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66700
    & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_SI, { 0x92320000 }
66701
  },
66702
/* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
66703
  {
66704
    { 0, 0, 0, 0 },
66705
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66706
    & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_SI, { 0x94020000 }
66707
  },
66708
/* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
66709
  {
66710
    { 0, 0, 0, 0 },
66711
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66712
    & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_SI, { 0x94220000 }
66713
  },
66714
/* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
66715
  {
66716
    { 0, 0, 0, 0 },
66717
    { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66718
    & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_SI, { 0x94320000 }
66719
  },
66720
/* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
66721
  {
66722
    { 0, 0, 0, 0 },
66723
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66724
    & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_SI, { 0x96020000 }
66725
  },
66726
/* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
66727
  {
66728
    { 0, 0, 0, 0 },
66729
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66730
    & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_SI, { 0x96220000 }
66731
  },
66732
/* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
66733
  {
66734
    { 0, 0, 0, 0 },
66735
    { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66736
    & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_SI, { 0x96320000 }
66737
  },
66738
/* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
66739
  {
66740
    { 0, 0, 0, 0 },
66741
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
66742
    & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_SI, { 0x92820000 }
66743
  },
66744
/* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
66745
  {
66746
    { 0, 0, 0, 0 },
66747
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
66748
    & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_SI, { 0x92a20000 }
66749
  },
66750
/* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
66751
  {
66752
    { 0, 0, 0, 0 },
66753
    { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
66754
    & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_SI, { 0x92b20000 }
66755
  },
66756
/* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
66757
  {
66758
    { 0, 0, 0, 0 },
66759
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
66760
    & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_SI, { 0x94820000 }
66761
  },
66762
/* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
66763
  {
66764
    { 0, 0, 0, 0 },
66765
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
66766
    & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_SI, { 0x94a20000 }
66767
  },
66768
/* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
66769
  {
66770
    { 0, 0, 0, 0 },
66771
    { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
66772
    & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_SI, { 0x94b20000 }
66773
  },
66774
/* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
66775
  {
66776
    { 0, 0, 0, 0 },
66777
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
66778
    & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_SI, { 0x92c20000 }
66779
  },
66780
/* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
66781
  {
66782
    { 0, 0, 0, 0 },
66783
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
66784
    & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_SI, { 0x92e20000 }
66785
  },
66786
/* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
66787
  {
66788
    { 0, 0, 0, 0 },
66789
    { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
66790
    & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_SI, { 0x92f20000 }
66791
  },
66792
/* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
66793
  {
66794
    { 0, 0, 0, 0 },
66795
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
66796
    & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_SI, { 0x94c20000 }
66797
  },
66798
/* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
66799
  {
66800
    { 0, 0, 0, 0 },
66801
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
66802
    & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_SI, { 0x94e20000 }
66803
  },
66804
/* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
66805
  {
66806
    { 0, 0, 0, 0 },
66807
    { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
66808
    & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_SI, { 0x94f20000 }
66809
  },
66810
/* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
66811
  {
66812
    { 0, 0, 0, 0 },
66813
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
66814
    & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_SI, { 0x96c20000 }
66815
  },
66816
/* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
66817
  {
66818
    { 0, 0, 0, 0 },
66819
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
66820
    & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_SI, { 0x96e20000 }
66821
  },
66822
/* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
66823
  {
66824
    { 0, 0, 0, 0 },
66825
    { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
66826
    & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_SI, { 0x96f20000 }
66827
  },
66828
/* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
66829
  {
66830
    { 0, 0, 0, 0 },
66831
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
66832
    & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_SI, { 0x96820000 }
66833
  },
66834
/* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
66835
  {
66836
    { 0, 0, 0, 0 },
66837
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } },
66838
    & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_SI, { 0x96a20000 }
66839
  },
66840
/* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
66841
  {
66842
    { 0, 0, 0, 0 },
66843
    { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } },
66844
    & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_SI, { 0x96b20000 }
66845
  },
66846
/* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
66847
  {
66848
    { 0, 0, 0, 0 },
66849
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
66850
    & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0xa8020000 }
66851
  },
66852
/* addx${X} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedSI */
66853
  {
66854
    { 0, 0, 0, 0 },
66855
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
66856
    & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0xa8220000 }
66857
  },
66858
/* addx${X} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedSI */
66859
  {
66860
    { 0, 0, 0, 0 },
66861
    { { MNEM, OP (X), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
66862
    & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0xa8320000 }
66863
  },
66864
/* addx${X} ${Dsp-16-u16},$Dst32RnUnprefixedSI */
66865
  {
66866
    { 0, 0, 0, 0 },
66867
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
66868
    & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0xb8320000 }
66869
  },
66870
/* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
66871
  {
66872
    { 0, 0, 0, 0 },
66873
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
66874
    & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0xa0820000 }
66875
  },
66876
/* addx${X} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedSI */
66877
  {
66878
    { 0, 0, 0, 0 },
66879
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
66880
    & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0xa0a20000 }
66881
  },
66882
/* addx${X} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedSI */
66883
  {
66884
    { 0, 0, 0, 0 },
66885
    { { MNEM, OP (X), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
66886
    & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0xa0b20000 }
66887
  },
66888
/* addx${X} ${Dsp-16-u16},$Dst32AnUnprefixedSI */
66889
  {
66890
    { 0, 0, 0, 0 },
66891
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
66892
    & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0xb0b20000 }
66893
  },
66894
/* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
66895
  {
66896
    { 0, 0, 0, 0 },
66897
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66898
    & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0xa0020000 }
66899
  },
66900
/* addx${X} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
66901
  {
66902
    { 0, 0, 0, 0 },
66903
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66904
    & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0xa0220000 }
66905
  },
66906
/* addx${X} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
66907
  {
66908
    { 0, 0, 0, 0 },
66909
    { { MNEM, OP (X), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66910
    & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0xa0320000 }
66911
  },
66912
/* addx${X} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
66913
  {
66914
    { 0, 0, 0, 0 },
66915
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66916
    & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0xb0320000 }
66917
  },
66918
/* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
66919
  {
66920
    { 0, 0, 0, 0 },
66921
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66922
    & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_SI, { 0xa2020000 }
66923
  },
66924
/* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
66925
  {
66926
    { 0, 0, 0, 0 },
66927
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66928
    & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_SI, { 0xa2220000 }
66929
  },
66930
/* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
66931
  {
66932
    { 0, 0, 0, 0 },
66933
    { { MNEM, OP (X), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66934
    & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_SI, { 0xa2320000 }
66935
  },
66936
/* addx${X} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
66937
  {
66938
    { 0, 0, 0, 0 },
66939
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66940
    & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_SI, { 0xb2320000 }
66941
  },
66942
/* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
66943
  {
66944
    { 0, 0, 0, 0 },
66945
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66946
    & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_SI, { 0xa4020000 }
66947
  },
66948
/* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
66949
  {
66950
    { 0, 0, 0, 0 },
66951
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66952
    & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_SI, { 0xa4220000 }
66953
  },
66954
/* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
66955
  {
66956
    { 0, 0, 0, 0 },
66957
    { { MNEM, OP (X), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66958
    & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_SI, { 0xa4320000 }
66959
  },
66960
/* addx${X} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
66961
  {
66962
    { 0, 0, 0, 0 },
66963
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66964
    & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_SI, { 0xb4320000 }
66965
  },
66966
/* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
66967
  {
66968
    { 0, 0, 0, 0 },
66969
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66970
    & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_SI, { 0xa6020000 }
66971
  },
66972
/* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
66973
  {
66974
    { 0, 0, 0, 0 },
66975
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66976
    & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_SI, { 0xa6220000 }
66977
  },
66978
/* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
66979
  {
66980
    { 0, 0, 0, 0 },
66981
    { { MNEM, OP (X), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66982
    & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_SI, { 0xa6320000 }
66983
  },
66984
/* addx${X} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
66985
  {
66986
    { 0, 0, 0, 0 },
66987
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
66988
    & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_SI, { 0xb6320000 }
66989
  },
66990
/* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
66991
  {
66992
    { 0, 0, 0, 0 },
66993
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
66994
    & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xa2820000 }
66995
  },
66996
/* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
66997
  {
66998
    { 0, 0, 0, 0 },
66999
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
67000
    & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xa2a20000 }
67001
  },
67002
/* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
67003
  {
67004
    { 0, 0, 0, 0 },
67005
    { { MNEM, OP (X), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
67006
    & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xa2b20000 }
67007
  },
67008
/* addx${X} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
67009
  {
67010
    { 0, 0, 0, 0 },
67011
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
67012
    & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xb2b20000 }
67013
  },
67014
/* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
67015
  {
67016
    { 0, 0, 0, 0 },
67017
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
67018
    & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xa4820000 }
67019
  },
67020
/* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
67021
  {
67022
    { 0, 0, 0, 0 },
67023
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
67024
    & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xa4a20000 }
67025
  },
67026
/* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
67027
  {
67028
    { 0, 0, 0, 0 },
67029
    { { MNEM, OP (X), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
67030
    & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xa4b20000 }
67031
  },
67032
/* addx${X} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
67033
  {
67034
    { 0, 0, 0, 0 },
67035
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
67036
    & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xb4b20000 }
67037
  },
67038
/* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
67039
  {
67040
    { 0, 0, 0, 0 },
67041
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
67042
    & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xa2c20000 }
67043
  },
67044
/* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
67045
  {
67046
    { 0, 0, 0, 0 },
67047
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
67048
    & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xa2e20000 }
67049
  },
67050
/* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
67051
  {
67052
    { 0, 0, 0, 0 },
67053
    { { MNEM, OP (X), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
67054
    & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xa2f20000 }
67055
  },
67056
/* addx${X} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
67057
  {
67058
    { 0, 0, 0, 0 },
67059
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
67060
    & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xb2f20000 }
67061
  },
67062
/* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
67063
  {
67064
    { 0, 0, 0, 0 },
67065
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
67066
    & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xa4c20000 }
67067
  },
67068
/* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
67069
  {
67070
    { 0, 0, 0, 0 },
67071
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
67072
    & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xa4e20000 }
67073
  },
67074
/* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
67075
  {
67076
    { 0, 0, 0, 0 },
67077
    { { MNEM, OP (X), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
67078
    & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xa4f20000 }
67079
  },
67080
/* addx${X} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
67081
  {
67082
    { 0, 0, 0, 0 },
67083
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
67084
    & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xb4f20000 }
67085
  },
67086
/* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
67087
  {
67088
    { 0, 0, 0, 0 },
67089
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
67090
    & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_SI, { 0xa6c20000 }
67091
  },
67092
/* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
67093
  {
67094
    { 0, 0, 0, 0 },
67095
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
67096
    & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_SI, { 0xa6e20000 }
67097
  },
67098
/* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
67099
  {
67100
    { 0, 0, 0, 0 },
67101
    { { MNEM, OP (X), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
67102
    & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_SI, { 0xa6f20000 }
67103
  },
67104
/* addx${X} ${Dsp-16-u16},${Dsp-32-u16} */
67105
  {
67106
    { 0, 0, 0, 0 },
67107
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
67108
    & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_SI, { 0xb6f20000 }
67109
  },
67110
/* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
67111
  {
67112
    { 0, 0, 0, 0 },
67113
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
67114
    & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_SI, { 0xa6820000 }
67115
  },
67116
/* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
67117
  {
67118
    { 0, 0, 0, 0 },
67119
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
67120
    & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_SI, { 0xa6a20000 }
67121
  },
67122
/* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
67123
  {
67124
    { 0, 0, 0, 0 },
67125
    { { MNEM, OP (X), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
67126
    & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_SI, { 0xa6b20000 }
67127
  },
67128
/* addx${X} ${Dsp-16-u16},${Dsp-32-u24} */
67129
  {
67130
    { 0, 0, 0, 0 },
67131
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } },
67132
    & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_SI, { 0xb6b20000 }
67133
  },
67134
/* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
67135
  {
67136
    { 0, 0, 0, 0 },
67137
    { { MNEM, OP (X), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
67138
    & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0xb8020000 }
67139
  },
67140
/* addx${X} ${Dsp-16-u24},$Dst32RnUnprefixedSI */
67141
  {
67142
    { 0, 0, 0, 0 },
67143
    { { MNEM, OP (X), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
67144
    & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0xb8220000 }
67145
  },
67146
/* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
67147
  {
67148
    { 0, 0, 0, 0 },
67149
    { { MNEM, OP (X), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
67150
    & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0xb0820000 }
67151
  },
67152
/* addx${X} ${Dsp-16-u24},$Dst32AnUnprefixedSI */
67153
  {
67154
    { 0, 0, 0, 0 },
67155
    { { MNEM, OP (X), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
67156
    & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0xb0a20000 }
67157
  },
67158
/* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
67159
  {
67160
    { 0, 0, 0, 0 },
67161
    { { MNEM, OP (X), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
67162
    & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0xb0020000 }
67163
  },
67164
/* addx${X} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
67165
  {
67166
    { 0, 0, 0, 0 },
67167
    { { MNEM, OP (X), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
67168
    & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0xb0220000 }
67169
  },
67170
/* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
67171
  {
67172
    { 0, 0, 0, 0 },
67173
    { { MNEM, OP (X), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
67174
    & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_SI, { 0xb2020000 }
67175
  },
67176
/* addx${X} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
67177
  {
67178
    { 0, 0, 0, 0 },
67179
    { { MNEM, OP (X), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
67180
    & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_SI, { 0xb2220000 }
67181
  },
67182
/* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
67183
  {
67184
    { 0, 0, 0, 0 },
67185
    { { MNEM, OP (X), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
67186
    & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_SI, { 0xb4020000 }
67187
  },
67188
/* addx${X} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
67189
  {
67190
    { 0, 0, 0, 0 },
67191
    { { MNEM, OP (X), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
67192
    & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_SI, { 0xb4220000 }
67193
  },
67194
/* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
67195
  {
67196
    { 0, 0, 0, 0 },
67197
    { { MNEM, OP (X), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
67198
    & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_SI, { 0xb6020000 }
67199
  },
67200
/* addx${X} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
67201
  {
67202
    { 0, 0, 0, 0 },
67203
    { { MNEM, OP (X), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
67204
    & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_SI, { 0xb6220000 }
67205
  },
67206
/* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
67207
  {
67208
    { 0, 0, 0, 0 },
67209
    { { MNEM, OP (X), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
67210
    & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_SI, { 0xb2820000 }
67211
  },
67212
/* addx${X} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
67213
  {
67214
    { 0, 0, 0, 0 },
67215
    { { MNEM, OP (X), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
67216
    & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_SI, { 0xb2a20000 }
67217
  },
67218
/* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
67219
  {
67220
    { 0, 0, 0, 0 },
67221
    { { MNEM, OP (X), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
67222
    & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_SI, { 0xb4820000 }
67223
  },
67224
/* addx${X} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
67225
  {
67226
    { 0, 0, 0, 0 },
67227
    { { MNEM, OP (X), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
67228
    & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_SI, { 0xb4a20000 }
67229
  },
67230
/* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
67231
  {
67232
    { 0, 0, 0, 0 },
67233
    { { MNEM, OP (X), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
67234
    & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_SI, { 0xb2c20000 }
67235
  },
67236
/* addx${X} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
67237
  {
67238
    { 0, 0, 0, 0 },
67239
    { { MNEM, OP (X), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
67240
    & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_SI, { 0xb2e20000 }
67241
  },
67242
/* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
67243
  {
67244
    { 0, 0, 0, 0 },
67245
    { { MNEM, OP (X), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
67246
    & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_SI, { 0xb4c20000 }
67247
  },
67248
/* addx${X} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
67249
  {
67250
    { 0, 0, 0, 0 },
67251
    { { MNEM, OP (X), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
67252
    & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_SI, { 0xb4e20000 }
67253
  },
67254
/* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
67255
  {
67256
    { 0, 0, 0, 0 },
67257
    { { MNEM, OP (X), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
67258
    & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_SI, { 0xb6c20000 }
67259
  },
67260
/* addx${X} ${Dsp-16-u24},${Dsp-40-u16} */
67261
  {
67262
    { 0, 0, 0, 0 },
67263
    { { MNEM, OP (X), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } },
67264
    & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_SI, { 0xb6e20000 }
67265
  },
67266
/* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
67267
  {
67268
    { 0, 0, 0, 0 },
67269
    { { MNEM, OP (X), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
67270
    & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_SI, { 0xb6820000 }
67271
  },
67272
/* addx${X} ${Dsp-16-u24},${Dsp-40-u24} */
67273
  {
67274
    { 0, 0, 0, 0 },
67275
    { { MNEM, OP (X), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } },
67276
    & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_SI, { 0xb6a20000 }
67277
  },
67278
/* addx${X} $Src32RnUnprefixedQI,$Dst32RnUnprefixedSI */
67279
  {
67280
    { 0, 0, 0, 0 },
67281
    { { MNEM, OP (X), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
67282
    & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0xc802 }
67283
  },
67284
/* addx${X} $Src32AnUnprefixedQI,$Dst32RnUnprefixedSI */
67285
  {
67286
    { 0, 0, 0, 0 },
67287
    { { MNEM, OP (X), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
67288
    & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0x8822 }
67289
  },
67290
/* addx${X} [$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
67291
  {
67292
    { 0, 0, 0, 0 },
67293
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
67294
    & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0x8802 }
67295
  },
67296
/* addx${X} $Src32RnUnprefixedQI,$Dst32AnUnprefixedSI */
67297
  {
67298
    { 0, 0, 0, 0 },
67299
    { { MNEM, OP (X), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
67300
    & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0xc082 }
67301
  },
67302
/* addx${X} $Src32AnUnprefixedQI,$Dst32AnUnprefixedSI */
67303
  {
67304
    { 0, 0, 0, 0 },
67305
    { { MNEM, OP (X), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
67306
    & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0x80a2 }
67307
  },
67308
/* addx${X} [$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
67309
  {
67310
    { 0, 0, 0, 0 },
67311
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
67312
    & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0x8082 }
67313
  },
67314
/* addx${X} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */
67315
  {
67316
    { 0, 0, 0, 0 },
67317
    { { MNEM, OP (X), ' ', OP (SRC32RNUNPREFIXEDQI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
67318
    & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0xc002 }
67319
  },
67320
/* addx${X} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */
67321
  {
67322
    { 0, 0, 0, 0 },
67323
    { { MNEM, OP (X), ' ', OP (SRC32ANUNPREFIXEDQI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
67324
    & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0x8022 }
67325
  },
67326
/* addx${X} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
67327
  {
67328
    { 0, 0, 0, 0 },
67329
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
67330
    & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0x8002 }
67331
  },
67332
/* addx${X} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
67333
  {
67334
    { 0, 0, 0, 0 },
67335
    { { MNEM, OP (X), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
67336
    & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_SI, { 0xc20200 }
67337
  },
67338
/* addx${X} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
67339
  {
67340
    { 0, 0, 0, 0 },
67341
    { { MNEM, OP (X), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
67342
    & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_SI, { 0x822200 }
67343
  },
67344
/* addx${X} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
67345
  {
67346
    { 0, 0, 0, 0 },
67347
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
67348
    & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_SI, { 0x820200 }
67349
  },
67350
/* addx${X} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
67351
  {
67352
    { 0, 0, 0, 0 },
67353
    { { MNEM, OP (X), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
67354
    & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_SI, { 0xc4020000 }
67355
  },
67356
/* addx${X} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
67357
  {
67358
    { 0, 0, 0, 0 },
67359
    { { MNEM, OP (X), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
67360
    & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_SI, { 0x84220000 }
67361
  },
67362
/* addx${X} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
67363
  {
67364
    { 0, 0, 0, 0 },
67365
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
67366
    & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_SI, { 0x84020000 }
67367
  },
67368
/* addx${X} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
67369
  {
67370
    { 0, 0, 0, 0 },
67371
    { { MNEM, OP (X), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
67372
    & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_SI, { 0xc6020000 }
67373
  },
67374
/* addx${X} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
67375
  {
67376
    { 0, 0, 0, 0 },
67377
    { { MNEM, OP (X), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
67378
    & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_SI, { 0x86220000 }
67379
  },
67380
/* addx${X} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
67381
  {
67382
    { 0, 0, 0, 0 },
67383
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
67384
    & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_SI, { 0x86020000 }
67385
  },
67386
/* addx${X} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */
67387
  {
67388
    { 0, 0, 0, 0 },
67389
    { { MNEM, OP (X), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
67390
    & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_SI, { 0xc28200 }
67391
  },
67392
/* addx${X} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */
67393
  {
67394
    { 0, 0, 0, 0 },
67395
    { { MNEM, OP (X), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
67396
    & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_SI, { 0x82a200 }
67397
  },
67398
/* addx${X} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
67399
  {
67400
    { 0, 0, 0, 0 },
67401
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
67402
    & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_SI, { 0x828200 }
67403
  },
67404
/* addx${X} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */
67405
  {
67406
    { 0, 0, 0, 0 },
67407
    { { MNEM, OP (X), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
67408
    & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_SI, { 0xc4820000 }
67409
  },
67410
/* addx${X} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */
67411
  {
67412
    { 0, 0, 0, 0 },
67413
    { { MNEM, OP (X), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
67414
    & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_SI, { 0x84a20000 }
67415
  },
67416
/* addx${X} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
67417
  {
67418
    { 0, 0, 0, 0 },
67419
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
67420
    & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_SI, { 0x84820000 }
67421
  },
67422
/* addx${X} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */
67423
  {
67424
    { 0, 0, 0, 0 },
67425
    { { MNEM, OP (X), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
67426
    & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_SI, { 0xc2c200 }
67427
  },
67428
/* addx${X} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */
67429
  {
67430
    { 0, 0, 0, 0 },
67431
    { { MNEM, OP (X), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
67432
    & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_SI, { 0x82e200 }
67433
  },
67434
/* addx${X} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
67435
  {
67436
    { 0, 0, 0, 0 },
67437
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
67438
    & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_SI, { 0x82c200 }
67439
  },
67440
/* addx${X} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */
67441
  {
67442
    { 0, 0, 0, 0 },
67443
    { { MNEM, OP (X), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
67444
    & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_SI, { 0xc4c20000 }
67445
  },
67446
/* addx${X} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */
67447
  {
67448
    { 0, 0, 0, 0 },
67449
    { { MNEM, OP (X), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
67450
    & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_SI, { 0x84e20000 }
67451
  },
67452
/* addx${X} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
67453
  {
67454
    { 0, 0, 0, 0 },
67455
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
67456
    & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_SI, { 0x84c20000 }
67457
  },
67458
/* addx${X} $Src32RnUnprefixedQI,${Dsp-16-u16} */
67459
  {
67460
    { 0, 0, 0, 0 },
67461
    { { MNEM, OP (X), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), 0 } },
67462
    & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_SI, { 0xc6c20000 }
67463
  },
67464
/* addx${X} $Src32AnUnprefixedQI,${Dsp-16-u16} */
67465
  {
67466
    { 0, 0, 0, 0 },
67467
    { { MNEM, OP (X), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), 0 } },
67468
    & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_SI, { 0x86e20000 }
67469
  },
67470
/* addx${X} [$Src32AnUnprefixed],${Dsp-16-u16} */
67471
  {
67472
    { 0, 0, 0, 0 },
67473
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } },
67474
    & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_SI, { 0x86c20000 }
67475
  },
67476
/* addx${X} $Src32RnUnprefixedQI,${Dsp-16-u24} */
67477
  {
67478
    { 0, 0, 0, 0 },
67479
    { { MNEM, OP (X), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U24), 0 } },
67480
    & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_SI, { 0xc6820000 }
67481
  },
67482
/* addx${X} $Src32AnUnprefixedQI,${Dsp-16-u24} */
67483
  {
67484
    { 0, 0, 0, 0 },
67485
    { { MNEM, OP (X), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U24), 0 } },
67486
    & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_SI, { 0x86a20000 }
67487
  },
67488
/* addx${X} [$Src32AnUnprefixed],${Dsp-16-u24} */
67489
  {
67490
    { 0, 0, 0, 0 },
67491
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } },
67492
    & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_SI, { 0x86820000 }
67493
  },
67494
/* addx${X} #${Imm-16-QI},$Dst32RnUnprefixedSI */
67495
  {
67496
    { 0, 0, 0, 0 },
67497
    { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
67498
    & ifmt_subx32_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_SI, { 0x881100 }
67499
  },
67500
/* addx${X} #${Imm-16-QI},$Dst32AnUnprefixedSI */
67501
  {
67502
    { 0, 0, 0, 0 },
67503
    { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
67504
    & ifmt_subx32_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_SI, { 0x809100 }
67505
  },
67506
/* addx${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */
67507
  {
67508
    { 0, 0, 0, 0 },
67509
    { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
67510
    & ifmt_subx32_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_SI, { 0x801100 }
67511
  },
67512
/* addx${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
67513
  {
67514
    { 0, 0, 0, 0 },
67515
    { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
67516
    & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_SI, { 0x82110000 }
67517
  },
67518
/* addx${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
67519
  {
67520
    { 0, 0, 0, 0 },
67521
    { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
67522
    & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_SI, { 0x82910000 }
67523
  },
67524
/* addx${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
67525
  {
67526
    { 0, 0, 0, 0 },
67527
    { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
67528
    & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_SI, { 0x82d10000 }
67529
  },
67530
/* addx${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
67531
  {
67532
    { 0, 0, 0, 0 },
67533
    { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
67534
    & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_SI, { 0x84110000 }
67535
  },
67536
/* addx${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
67537
  {
67538
    { 0, 0, 0, 0 },
67539
    { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
67540
    & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_SI, { 0x84910000 }
67541
  },
67542
/* addx${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */
67543
  {
67544
    { 0, 0, 0, 0 },
67545
    { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
67546
    & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_SI, { 0x84d10000 }
67547
  },
67548
/* addx${X} #${Imm-32-QI},${Dsp-16-u16} */
67549
  {
67550
    { 0, 0, 0, 0 },
67551
    { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } },
67552
    & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_SI, { 0x86d10000 }
67553
  },
67554
/* addx${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
67555
  {
67556
    { 0, 0, 0, 0 },
67557
    { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
67558
    & ifmt_subx32_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_SI, { 0x86110000 }
67559
  },
67560
/* addx${X} #${Imm-40-QI},${Dsp-16-u24} */
67561
  {
67562
    { 0, 0, 0, 0 },
67563
    { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), 0 } },
67564
    & ifmt_subx32_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_SI, { 0x86910000 }
67565
  },
67566
/* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
67567
  {
67568
    { 0, 0, 0, 0 },
67569
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
67570
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1990000 }
67571
  },
67572
/* dadd.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
67573
  {
67574
    { 0, 0, 0, 0 },
67575
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
67576
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1992000 }
67577
  },
67578
/* dadd.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
67579
  {
67580
    { 0, 0, 0, 0 },
67581
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
67582
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1993000 }
67583
  },
67584
/* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
67585
  {
67586
    { 0, 0, 0, 0 },
67587
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
67588
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1918000 }
67589
  },
67590
/* dadd.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
67591
  {
67592
    { 0, 0, 0, 0 },
67593
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
67594
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x191a000 }
67595
  },
67596
/* dadd.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
67597
  {
67598
    { 0, 0, 0, 0 },
67599
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
67600
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x191b000 }
67601
  },
67602
/* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
67603
  {
67604
    { 0, 0, 0, 0 },
67605
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
67606
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1910000 }
67607
  },
67608
/* dadd.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
67609
  {
67610
    { 0, 0, 0, 0 },
67611
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
67612
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1912000 }
67613
  },
67614
/* dadd.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
67615
  {
67616
    { 0, 0, 0, 0 },
67617
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
67618
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1913000 }
67619
  },
67620
/* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
67621
  {
67622
    { 0, 0, 0, 0 },
67623
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
67624
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1930000 }
67625
  },
67626
/* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
67627
  {
67628
    { 0, 0, 0, 0 },
67629
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
67630
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1932000 }
67631
  },
67632
/* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
67633
  {
67634
    { 0, 0, 0, 0 },
67635
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
67636
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1933000 }
67637
  },
67638
/* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
67639
  {
67640
    { 0, 0, 0, 0 },
67641
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
67642
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1950000 }
67643
  },
67644
/* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
67645
  {
67646
    { 0, 0, 0, 0 },
67647
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
67648
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1952000 }
67649
  },
67650
/* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
67651
  {
67652
    { 0, 0, 0, 0 },
67653
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
67654
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1953000 }
67655
  },
67656
/* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
67657
  {
67658
    { 0, 0, 0, 0 },
67659
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
67660
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1970000 }
67661
  },
67662
/* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
67663
  {
67664
    { 0, 0, 0, 0 },
67665
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
67666
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1972000 }
67667
  },
67668
/* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
67669
  {
67670
    { 0, 0, 0, 0 },
67671
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
67672
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1973000 }
67673
  },
67674
/* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
67675
  {
67676
    { 0, 0, 0, 0 },
67677
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
67678
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x1938000 }
67679
  },
67680
/* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
67681
  {
67682
    { 0, 0, 0, 0 },
67683
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
67684
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x193a000 }
67685
  },
67686
/* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
67687
  {
67688
    { 0, 0, 0, 0 },
67689
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
67690
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x193b000 }
67691
  },
67692
/* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
67693
  {
67694
    { 0, 0, 0, 0 },
67695
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
67696
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x1958000 }
67697
  },
67698
/* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
67699
  {
67700
    { 0, 0, 0, 0 },
67701
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
67702
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x195a000 }
67703
  },
67704
/* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
67705
  {
67706
    { 0, 0, 0, 0 },
67707
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
67708
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x195b000 }
67709
  },
67710
/* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
67711
  {
67712
    { 0, 0, 0, 0 },
67713
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
67714
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193c000 }
67715
  },
67716
/* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
67717
  {
67718
    { 0, 0, 0, 0 },
67719
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
67720
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193e000 }
67721
  },
67722
/* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
67723
  {
67724
    { 0, 0, 0, 0 },
67725
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
67726
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193f000 }
67727
  },
67728
/* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
67729
  {
67730
    { 0, 0, 0, 0 },
67731
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
67732
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195c000 }
67733
  },
67734
/* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
67735
  {
67736
    { 0, 0, 0, 0 },
67737
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
67738
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195e000 }
67739
  },
67740
/* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
67741
  {
67742
    { 0, 0, 0, 0 },
67743
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
67744
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195f000 }
67745
  },
67746
/* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
67747
  {
67748
    { 0, 0, 0, 0 },
67749
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
67750
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197c000 }
67751
  },
67752
/* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
67753
  {
67754
    { 0, 0, 0, 0 },
67755
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
67756
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197e000 }
67757
  },
67758
/* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
67759
  {
67760
    { 0, 0, 0, 0 },
67761
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
67762
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197f000 }
67763
  },
67764
/* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
67765
  {
67766
    { 0, 0, 0, 0 },
67767
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
67768
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x1978000 }
67769
  },
67770
/* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
67771
  {
67772
    { 0, 0, 0, 0 },
67773
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
67774
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x197a000 }
67775
  },
67776
/* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
67777
  {
67778
    { 0, 0, 0, 0 },
67779
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
67780
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x197b000 }
67781
  },
67782
/* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
67783
  {
67784
    { 0, 0, 0, 0 },
67785
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
67786
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a90000 }
67787
  },
67788
/* dadd.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
67789
  {
67790
    { 0, 0, 0, 0 },
67791
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
67792
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a92000 }
67793
  },
67794
/* dadd.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
67795
  {
67796
    { 0, 0, 0, 0 },
67797
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
67798
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a93000 }
67799
  },
67800
/* dadd.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */
67801
  {
67802
    { 0, 0, 0, 0 },
67803
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32RNPREFIXEDHI), 0 } },
67804
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b93000 }
67805
  },
67806
/* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
67807
  {
67808
    { 0, 0, 0, 0 },
67809
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
67810
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a18000 }
67811
  },
67812
/* dadd.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
67813
  {
67814
    { 0, 0, 0, 0 },
67815
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
67816
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a1a000 }
67817
  },
67818
/* dadd.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
67819
  {
67820
    { 0, 0, 0, 0 },
67821
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
67822
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a1b000 }
67823
  },
67824
/* dadd.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */
67825
  {
67826
    { 0, 0, 0, 0 },
67827
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32ANPREFIXEDHI), 0 } },
67828
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b1b000 }
67829
  },
67830
/* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
67831
  {
67832
    { 0, 0, 0, 0 },
67833
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
67834
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a10000 }
67835
  },
67836
/* dadd.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
67837
  {
67838
    { 0, 0, 0, 0 },
67839
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
67840
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a12000 }
67841
  },
67842
/* dadd.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
67843
  {
67844
    { 0, 0, 0, 0 },
67845
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
67846
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a13000 }
67847
  },
67848
/* dadd.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
67849
  {
67850
    { 0, 0, 0, 0 },
67851
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
67852
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b13000 }
67853
  },
67854
/* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
67855
  {
67856
    { 0, 0, 0, 0 },
67857
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
67858
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a30000 }
67859
  },
67860
/* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
67861
  {
67862
    { 0, 0, 0, 0 },
67863
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
67864
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a32000 }
67865
  },
67866
/* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
67867
  {
67868
    { 0, 0, 0, 0 },
67869
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
67870
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a33000 }
67871
  },
67872
/* dadd.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
67873
  {
67874
    { 0, 0, 0, 0 },
67875
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
67876
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1b33000 }
67877
  },
67878
/* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
67879
  {
67880
    { 0, 0, 0, 0 },
67881
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
67882
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a50000 }
67883
  },
67884
/* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
67885
  {
67886
    { 0, 0, 0, 0 },
67887
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
67888
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a52000 }
67889
  },
67890
/* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
67891
  {
67892
    { 0, 0, 0, 0 },
67893
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
67894
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a53000 }
67895
  },
67896
/* dadd.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
67897
  {
67898
    { 0, 0, 0, 0 },
67899
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
67900
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1b53000 }
67901
  },
67902
/* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
67903
  {
67904
    { 0, 0, 0, 0 },
67905
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
67906
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a70000 }
67907
  },
67908
/* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
67909
  {
67910
    { 0, 0, 0, 0 },
67911
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
67912
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a72000 }
67913
  },
67914
/* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
67915
  {
67916
    { 0, 0, 0, 0 },
67917
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
67918
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a73000 }
67919
  },
67920
/* dadd.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
67921
  {
67922
    { 0, 0, 0, 0 },
67923
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
67924
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1b73000 }
67925
  },
67926
/* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
67927
  {
67928
    { 0, 0, 0, 0 },
67929
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
67930
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a38000 }
67931
  },
67932
/* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
67933
  {
67934
    { 0, 0, 0, 0 },
67935
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
67936
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a3a000 }
67937
  },
67938
/* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
67939
  {
67940
    { 0, 0, 0, 0 },
67941
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
67942
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a3b000 }
67943
  },
67944
/* dadd.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
67945
  {
67946
    { 0, 0, 0, 0 },
67947
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
67948
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1b3b000 }
67949
  },
67950
/* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
67951
  {
67952
    { 0, 0, 0, 0 },
67953
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
67954
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a58000 }
67955
  },
67956
/* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
67957
  {
67958
    { 0, 0, 0, 0 },
67959
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
67960
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a5a000 }
67961
  },
67962
/* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
67963
  {
67964
    { 0, 0, 0, 0 },
67965
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
67966
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a5b000 }
67967
  },
67968
/* dadd.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
67969
  {
67970
    { 0, 0, 0, 0 },
67971
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
67972
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1b5b000 }
67973
  },
67974
/* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
67975
  {
67976
    { 0, 0, 0, 0 },
67977
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
67978
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3c000 }
67979
  },
67980
/* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
67981
  {
67982
    { 0, 0, 0, 0 },
67983
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
67984
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3e000 }
67985
  },
67986
/* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
67987
  {
67988
    { 0, 0, 0, 0 },
67989
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
67990
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3f000 }
67991
  },
67992
/* dadd.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
67993
  {
67994
    { 0, 0, 0, 0 },
67995
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
67996
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1b3f000 }
67997
  },
67998
/* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
67999
  {
68000
    { 0, 0, 0, 0 },
68001
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
68002
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5c000 }
68003
  },
68004
/* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
68005
  {
68006
    { 0, 0, 0, 0 },
68007
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
68008
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5e000 }
68009
  },
68010
/* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
68011
  {
68012
    { 0, 0, 0, 0 },
68013
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
68014
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5f000 }
68015
  },
68016
/* dadd.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
68017
  {
68018
    { 0, 0, 0, 0 },
68019
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
68020
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1b5f000 }
68021
  },
68022
/* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
68023
  {
68024
    { 0, 0, 0, 0 },
68025
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
68026
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7c000 }
68027
  },
68028
/* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
68029
  {
68030
    { 0, 0, 0, 0 },
68031
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), 0 } },
68032
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7e000 }
68033
  },
68034
/* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
68035
  {
68036
    { 0, 0, 0, 0 },
68037
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), 0 } },
68038
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7f000 }
68039
  },
68040
/* dadd.w${X} ${Dsp-24-u16},${Dsp-40-u16} */
68041
  {
68042
    { 0, 0, 0, 0 },
68043
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), 0 } },
68044
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1b7f000 }
68045
  },
68046
/* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
68047
  {
68048
    { 0, 0, 0, 0 },
68049
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
68050
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a78000 }
68051
  },
68052
/* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
68053
  {
68054
    { 0, 0, 0, 0 },
68055
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), 0 } },
68056
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a7a000 }
68057
  },
68058
/* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
68059
  {
68060
    { 0, 0, 0, 0 },
68061
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), 0 } },
68062
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a7b000 }
68063
  },
68064
/* dadd.w${X} ${Dsp-24-u16},${Dsp-40-u24} */
68065
  {
68066
    { 0, 0, 0, 0 },
68067
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), 0 } },
68068
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1b7b000 }
68069
  },
68070
/* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
68071
  {
68072
    { 0, 0, 0, 0 },
68073
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
68074
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b90000 }
68075
  },
68076
/* dadd.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */
68077
  {
68078
    { 0, 0, 0, 0 },
68079
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32RNPREFIXEDHI), 0 } },
68080
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b92000 }
68081
  },
68082
/* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
68083
  {
68084
    { 0, 0, 0, 0 },
68085
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
68086
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b18000 }
68087
  },
68088
/* dadd.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */
68089
  {
68090
    { 0, 0, 0, 0 },
68091
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32ANPREFIXEDHI), 0 } },
68092
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b1a000 }
68093
  },
68094
/* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
68095
  {
68096
    { 0, 0, 0, 0 },
68097
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
68098
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b10000 }
68099
  },
68100
/* dadd.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
68101
  {
68102
    { 0, 0, 0, 0 },
68103
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
68104
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b12000 }
68105
  },
68106
/* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
68107
  {
68108
    { 0, 0, 0, 0 },
68109
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
68110
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b30000 }
68111
  },
68112
/* dadd.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
68113
  {
68114
    { 0, 0, 0, 0 },
68115
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
68116
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b32000 }
68117
  },
68118
/* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
68119
  {
68120
    { 0, 0, 0, 0 },
68121
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
68122
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b50000 }
68123
  },
68124
/* dadd.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
68125
  {
68126
    { 0, 0, 0, 0 },
68127
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
68128
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b52000 }
68129
  },
68130
/* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
68131
  {
68132
    { 0, 0, 0, 0 },
68133
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
68134
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b70000 }
68135
  },
68136
/* dadd.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
68137
  {
68138
    { 0, 0, 0, 0 },
68139
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
68140
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b72000 }
68141
  },
68142
/* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
68143
  {
68144
    { 0, 0, 0, 0 },
68145
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
68146
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b38000 }
68147
  },
68148
/* dadd.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
68149
  {
68150
    { 0, 0, 0, 0 },
68151
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
68152
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b3a000 }
68153
  },
68154
/* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
68155
  {
68156
    { 0, 0, 0, 0 },
68157
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
68158
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b58000 }
68159
  },
68160
/* dadd.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
68161
  {
68162
    { 0, 0, 0, 0 },
68163
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
68164
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b5a000 }
68165
  },
68166
/* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
68167
  {
68168
    { 0, 0, 0, 0 },
68169
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
68170
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b3c000 }
68171
  },
68172
/* dadd.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
68173
  {
68174
    { 0, 0, 0, 0 },
68175
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
68176
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b3e000 }
68177
  },
68178
/* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
68179
  {
68180
    { 0, 0, 0, 0 },
68181
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
68182
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b5c000 }
68183
  },
68184
/* dadd.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
68185
  {
68186
    { 0, 0, 0, 0 },
68187
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
68188
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b5e000 }
68189
  },
68190
/* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
68191
  {
68192
    { 0, 0, 0, 0 },
68193
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), 0 } },
68194
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_absolute_Prefixed_HI, { 0x1b7c000 }
68195
  },
68196
/* dadd.w${X} ${Dsp-24-u24},${Dsp-48-u16} */
68197
  {
68198
    { 0, 0, 0, 0 },
68199
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), 0 } },
68200
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_absolute_Prefixed_HI, { 0x1b7e000 }
68201
  },
68202
/* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
68203
  {
68204
    { 0, 0, 0, 0 },
68205
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), 0 } },
68206
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_24_absolute_Prefixed_HI, { 0x1b78000 }
68207
  },
68208
/* dadd.w${X} ${Dsp-24-u24},${Dsp-48-u24} */
68209
  {
68210
    { 0, 0, 0, 0 },
68211
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), 0 } },
68212
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_24_absolute_Prefixed_HI, { 0x1b7a000 }
68213
  },
68214
/* dadd.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */
68215
  {
68216
    { 0, 0, 0, 0 },
68217
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DST32RNPREFIXEDHI), 0 } },
68218
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1c900 }
68219
  },
68220
/* dadd.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */
68221
  {
68222
    { 0, 0, 0, 0 },
68223
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DST32RNPREFIXEDHI), 0 } },
68224
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x18920 }
68225
  },
68226
/* dadd.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */
68227
  {
68228
    { 0, 0, 0, 0 },
68229
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
68230
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x18900 }
68231
  },
68232
/* dadd.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */
68233
  {
68234
    { 0, 0, 0, 0 },
68235
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DST32ANPREFIXEDHI), 0 } },
68236
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1c180 }
68237
  },
68238
/* dadd.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */
68239
  {
68240
    { 0, 0, 0, 0 },
68241
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DST32ANPREFIXEDHI), 0 } },
68242
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x181a0 }
68243
  },
68244
/* dadd.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */
68245
  {
68246
    { 0, 0, 0, 0 },
68247
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
68248
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x18180 }
68249
  },
68250
/* dadd.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */
68251
  {
68252
    { 0, 0, 0, 0 },
68253
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
68254
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1c100 }
68255
  },
68256
/* dadd.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */
68257
  {
68258
    { 0, 0, 0, 0 },
68259
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
68260
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x18120 }
68261
  },
68262
/* dadd.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
68263
  {
68264
    { 0, 0, 0, 0 },
68265
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
68266
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x18100 }
68267
  },
68268
/* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
68269
  {
68270
    { 0, 0, 0, 0 },
68271
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
68272
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1c30000 }
68273
  },
68274
/* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
68275
  {
68276
    { 0, 0, 0, 0 },
68277
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
68278
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1832000 }
68279
  },
68280
/* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
68281
  {
68282
    { 0, 0, 0, 0 },
68283
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
68284
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1830000 }
68285
  },
68286
/* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
68287
  {
68288
    { 0, 0, 0, 0 },
68289
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
68290
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1c50000 }
68291
  },
68292
/* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
68293
  {
68294
    { 0, 0, 0, 0 },
68295
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
68296
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1852000 }
68297
  },
68298
/* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
68299
  {
68300
    { 0, 0, 0, 0 },
68301
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
68302
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1850000 }
68303
  },
68304
/* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
68305
  {
68306
    { 0, 0, 0, 0 },
68307
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
68308
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1c70000 }
68309
  },
68310
/* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
68311
  {
68312
    { 0, 0, 0, 0 },
68313
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
68314
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1872000 }
68315
  },
68316
/* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
68317
  {
68318
    { 0, 0, 0, 0 },
68319
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
68320
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1870000 }
68321
  },
68322
/* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */
68323
  {
68324
    { 0, 0, 0, 0 },
68325
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
68326
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1c38000 }
68327
  },
68328
/* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */
68329
  {
68330
    { 0, 0, 0, 0 },
68331
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
68332
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x183a000 }
68333
  },
68334
/* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
68335
  {
68336
    { 0, 0, 0, 0 },
68337
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
68338
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1838000 }
68339
  },
68340
/* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */
68341
  {
68342
    { 0, 0, 0, 0 },
68343
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
68344
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1c58000 }
68345
  },
68346
/* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */
68347
  {
68348
    { 0, 0, 0, 0 },
68349
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
68350
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x185a000 }
68351
  },
68352
/* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
68353
  {
68354
    { 0, 0, 0, 0 },
68355
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
68356
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1858000 }
68357
  },
68358
/* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */
68359
  {
68360
    { 0, 0, 0, 0 },
68361
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
68362
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x1c3c000 }
68363
  },
68364
/* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */
68365
  {
68366
    { 0, 0, 0, 0 },
68367
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
68368
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x183e000 }
68369
  },
68370
/* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
68371
  {
68372
    { 0, 0, 0, 0 },
68373
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
68374
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x183c000 }
68375
  },
68376
/* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */
68377
  {
68378
    { 0, 0, 0, 0 },
68379
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
68380
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x1c5c000 }
68381
  },
68382
/* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */
68383
  {
68384
    { 0, 0, 0, 0 },
68385
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
68386
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x185e000 }
68387
  },
68388
/* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
68389
  {
68390
    { 0, 0, 0, 0 },
68391
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
68392
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x185c000 }
68393
  },
68394
/* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */
68395
  {
68396
    { 0, 0, 0, 0 },
68397
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), 0 } },
68398
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x1c7c000 }
68399
  },
68400
/* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */
68401
  {
68402
    { 0, 0, 0, 0 },
68403
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), 0 } },
68404
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x187e000 }
68405
  },
68406
/* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */
68407
  {
68408
    { 0, 0, 0, 0 },
68409
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
68410
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x187c000 }
68411
  },
68412
/* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */
68413
  {
68414
    { 0, 0, 0, 0 },
68415
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U24), 0 } },
68416
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x1c78000 }
68417
  },
68418
/* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */
68419
  {
68420
    { 0, 0, 0, 0 },
68421
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U24), 0 } },
68422
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x187a000 }
68423
  },
68424
/* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */
68425
  {
68426
    { 0, 0, 0, 0 },
68427
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
68428
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x1878000 }
68429
  },
68430
/* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
68431
  {
68432
    { 0, 0, 0, 0 },
68433
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
68434
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1980000 }
68435
  },
68436
/* dadd.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */
68437
  {
68438
    { 0, 0, 0, 0 },
68439
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
68440
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1982000 }
68441
  },
68442
/* dadd.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */
68443
  {
68444
    { 0, 0, 0, 0 },
68445
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
68446
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1983000 }
68447
  },
68448
/* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
68449
  {
68450
    { 0, 0, 0, 0 },
68451
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
68452
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1908000 }
68453
  },
68454
/* dadd.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */
68455
  {
68456
    { 0, 0, 0, 0 },
68457
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
68458
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x190a000 }
68459
  },
68460
/* dadd.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */
68461
  {
68462
    { 0, 0, 0, 0 },
68463
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
68464
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x190b000 }
68465
  },
68466
/* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
68467
  {
68468
    { 0, 0, 0, 0 },
68469
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
68470
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1900000 }
68471
  },
68472
/* dadd.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
68473
  {
68474
    { 0, 0, 0, 0 },
68475
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
68476
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1902000 }
68477
  },
68478
/* dadd.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
68479
  {
68480
    { 0, 0, 0, 0 },
68481
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
68482
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1903000 }
68483
  },
68484
/* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
68485
  {
68486
    { 0, 0, 0, 0 },
68487
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
68488
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1920000 }
68489
  },
68490
/* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
68491
  {
68492
    { 0, 0, 0, 0 },
68493
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
68494
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1922000 }
68495
  },
68496
/* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
68497
  {
68498
    { 0, 0, 0, 0 },
68499
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
68500
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1923000 }
68501
  },
68502
/* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
68503
  {
68504
    { 0, 0, 0, 0 },
68505
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
68506
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1940000 }
68507
  },
68508
/* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
68509
  {
68510
    { 0, 0, 0, 0 },
68511
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
68512
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1942000 }
68513
  },
68514
/* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
68515
  {
68516
    { 0, 0, 0, 0 },
68517
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
68518
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1943000 }
68519
  },
68520
/* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
68521
  {
68522
    { 0, 0, 0, 0 },
68523
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
68524
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1960000 }
68525
  },
68526
/* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
68527
  {
68528
    { 0, 0, 0, 0 },
68529
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
68530
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1962000 }
68531
  },
68532
/* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
68533
  {
68534
    { 0, 0, 0, 0 },
68535
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
68536
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1963000 }
68537
  },
68538
/* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
68539
  {
68540
    { 0, 0, 0, 0 },
68541
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
68542
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x1928000 }
68543
  },
68544
/* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
68545
  {
68546
    { 0, 0, 0, 0 },
68547
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
68548
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x192a000 }
68549
  },
68550
/* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
68551
  {
68552
    { 0, 0, 0, 0 },
68553
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
68554
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x192b000 }
68555
  },
68556
/* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
68557
  {
68558
    { 0, 0, 0, 0 },
68559
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
68560
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x1948000 }
68561
  },
68562
/* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
68563
  {
68564
    { 0, 0, 0, 0 },
68565
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
68566
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x194a000 }
68567
  },
68568
/* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
68569
  {
68570
    { 0, 0, 0, 0 },
68571
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
68572
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x194b000 }
68573
  },
68574
/* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
68575
  {
68576
    { 0, 0, 0, 0 },
68577
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
68578
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192c000 }
68579
  },
68580
/* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
68581
  {
68582
    { 0, 0, 0, 0 },
68583
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
68584
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192e000 }
68585
  },
68586
/* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
68587
  {
68588
    { 0, 0, 0, 0 },
68589
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
68590
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192f000 }
68591
  },
68592
/* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
68593
  {
68594
    { 0, 0, 0, 0 },
68595
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
68596
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194c000 }
68597
  },
68598
/* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
68599
  {
68600
    { 0, 0, 0, 0 },
68601
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
68602
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194e000 }
68603
  },
68604
/* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
68605
  {
68606
    { 0, 0, 0, 0 },
68607
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
68608
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194f000 }
68609
  },
68610
/* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
68611
  {
68612
    { 0, 0, 0, 0 },
68613
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
68614
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196c000 }
68615
  },
68616
/* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
68617
  {
68618
    { 0, 0, 0, 0 },
68619
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
68620
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196e000 }
68621
  },
68622
/* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
68623
  {
68624
    { 0, 0, 0, 0 },
68625
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
68626
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196f000 }
68627
  },
68628
/* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
68629
  {
68630
    { 0, 0, 0, 0 },
68631
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
68632
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x1968000 }
68633
  },
68634
/* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
68635
  {
68636
    { 0, 0, 0, 0 },
68637
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
68638
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x196a000 }
68639
  },
68640
/* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
68641
  {
68642
    { 0, 0, 0, 0 },
68643
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
68644
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x196b000 }
68645
  },
68646
/* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
68647
  {
68648
    { 0, 0, 0, 0 },
68649
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
68650
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a80000 }
68651
  },
68652
/* dadd.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */
68653
  {
68654
    { 0, 0, 0, 0 },
68655
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
68656
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a82000 }
68657
  },
68658
/* dadd.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */
68659
  {
68660
    { 0, 0, 0, 0 },
68661
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
68662
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a83000 }
68663
  },
68664
/* dadd.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */
68665
  {
68666
    { 0, 0, 0, 0 },
68667
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32RNPREFIXEDQI), 0 } },
68668
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b83000 }
68669
  },
68670
/* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
68671
  {
68672
    { 0, 0, 0, 0 },
68673
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
68674
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a08000 }
68675
  },
68676
/* dadd.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */
68677
  {
68678
    { 0, 0, 0, 0 },
68679
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
68680
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a0a000 }
68681
  },
68682
/* dadd.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */
68683
  {
68684
    { 0, 0, 0, 0 },
68685
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
68686
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a0b000 }
68687
  },
68688
/* dadd.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */
68689
  {
68690
    { 0, 0, 0, 0 },
68691
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32ANPREFIXEDQI), 0 } },
68692
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b0b000 }
68693
  },
68694
/* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
68695
  {
68696
    { 0, 0, 0, 0 },
68697
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
68698
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a00000 }
68699
  },
68700
/* dadd.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
68701
  {
68702
    { 0, 0, 0, 0 },
68703
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
68704
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a02000 }
68705
  },
68706
/* dadd.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
68707
  {
68708
    { 0, 0, 0, 0 },
68709
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
68710
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a03000 }
68711
  },
68712
/* dadd.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
68713
  {
68714
    { 0, 0, 0, 0 },
68715
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
68716
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b03000 }
68717
  },
68718
/* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
68719
  {
68720
    { 0, 0, 0, 0 },
68721
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
68722
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a20000 }
68723
  },
68724
/* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
68725
  {
68726
    { 0, 0, 0, 0 },
68727
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
68728
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a22000 }
68729
  },
68730
/* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
68731
  {
68732
    { 0, 0, 0, 0 },
68733
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
68734
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a23000 }
68735
  },
68736
/* dadd.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
68737
  {
68738
    { 0, 0, 0, 0 },
68739
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
68740
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1b23000 }
68741
  },
68742
/* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
68743
  {
68744
    { 0, 0, 0, 0 },
68745
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
68746
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a40000 }
68747
  },
68748
/* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
68749
  {
68750
    { 0, 0, 0, 0 },
68751
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
68752
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a42000 }
68753
  },
68754
/* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
68755
  {
68756
    { 0, 0, 0, 0 },
68757
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
68758
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a43000 }
68759
  },
68760
/* dadd.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
68761
  {
68762
    { 0, 0, 0, 0 },
68763
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
68764
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1b43000 }
68765
  },
68766
/* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
68767
  {
68768
    { 0, 0, 0, 0 },
68769
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
68770
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a60000 }
68771
  },
68772
/* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
68773
  {
68774
    { 0, 0, 0, 0 },
68775
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
68776
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a62000 }
68777
  },
68778
/* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
68779
  {
68780
    { 0, 0, 0, 0 },
68781
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
68782
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a63000 }
68783
  },
68784
/* dadd.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
68785
  {
68786
    { 0, 0, 0, 0 },
68787
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
68788
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1b63000 }
68789
  },
68790
/* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
68791
  {
68792
    { 0, 0, 0, 0 },
68793
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
68794
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a28000 }
68795
  },
68796
/* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
68797
  {
68798
    { 0, 0, 0, 0 },
68799
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
68800
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a2a000 }
68801
  },
68802
/* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
68803
  {
68804
    { 0, 0, 0, 0 },
68805
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
68806
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a2b000 }
68807
  },
68808
/* dadd.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
68809
  {
68810
    { 0, 0, 0, 0 },
68811
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
68812
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1b2b000 }
68813
  },
68814
/* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
68815
  {
68816
    { 0, 0, 0, 0 },
68817
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
68818
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a48000 }
68819
  },
68820
/* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
68821
  {
68822
    { 0, 0, 0, 0 },
68823
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
68824
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a4a000 }
68825
  },
68826
/* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
68827
  {
68828
    { 0, 0, 0, 0 },
68829
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
68830
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a4b000 }
68831
  },
68832
/* dadd.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
68833
  {
68834
    { 0, 0, 0, 0 },
68835
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
68836
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1b4b000 }
68837
  },
68838
/* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
68839
  {
68840
    { 0, 0, 0, 0 },
68841
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
68842
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2c000 }
68843
  },
68844
/* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
68845
  {
68846
    { 0, 0, 0, 0 },
68847
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
68848
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2e000 }
68849
  },
68850
/* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
68851
  {
68852
    { 0, 0, 0, 0 },
68853
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
68854
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2f000 }
68855
  },
68856
/* dadd.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
68857
  {
68858
    { 0, 0, 0, 0 },
68859
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
68860
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1b2f000 }
68861
  },
68862
/* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
68863
  {
68864
    { 0, 0, 0, 0 },
68865
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
68866
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4c000 }
68867
  },
68868
/* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
68869
  {
68870
    { 0, 0, 0, 0 },
68871
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
68872
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4e000 }
68873
  },
68874
/* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
68875
  {
68876
    { 0, 0, 0, 0 },
68877
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
68878
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4f000 }
68879
  },
68880
/* dadd.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
68881
  {
68882
    { 0, 0, 0, 0 },
68883
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
68884
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1b4f000 }
68885
  },
68886
/* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
68887
  {
68888
    { 0, 0, 0, 0 },
68889
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
68890
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6c000 }
68891
  },
68892
/* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
68893
  {
68894
    { 0, 0, 0, 0 },
68895
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), 0 } },
68896
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6e000 }
68897
  },
68898
/* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
68899
  {
68900
    { 0, 0, 0, 0 },
68901
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), 0 } },
68902
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6f000 }
68903
  },
68904
/* dadd.b${X} ${Dsp-24-u16},${Dsp-40-u16} */
68905
  {
68906
    { 0, 0, 0, 0 },
68907
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), 0 } },
68908
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1b6f000 }
68909
  },
68910
/* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
68911
  {
68912
    { 0, 0, 0, 0 },
68913
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
68914
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a68000 }
68915
  },
68916
/* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
68917
  {
68918
    { 0, 0, 0, 0 },
68919
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), 0 } },
68920
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a6a000 }
68921
  },
68922
/* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
68923
  {
68924
    { 0, 0, 0, 0 },
68925
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), 0 } },
68926
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a6b000 }
68927
  },
68928
/* dadd.b${X} ${Dsp-24-u16},${Dsp-40-u24} */
68929
  {
68930
    { 0, 0, 0, 0 },
68931
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), 0 } },
68932
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1b6b000 }
68933
  },
68934
/* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
68935
  {
68936
    { 0, 0, 0, 0 },
68937
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
68938
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b80000 }
68939
  },
68940
/* dadd.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */
68941
  {
68942
    { 0, 0, 0, 0 },
68943
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32RNPREFIXEDQI), 0 } },
68944
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b82000 }
68945
  },
68946
/* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
68947
  {
68948
    { 0, 0, 0, 0 },
68949
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
68950
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b08000 }
68951
  },
68952
/* dadd.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */
68953
  {
68954
    { 0, 0, 0, 0 },
68955
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32ANPREFIXEDQI), 0 } },
68956
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b0a000 }
68957
  },
68958
/* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
68959
  {
68960
    { 0, 0, 0, 0 },
68961
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
68962
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b00000 }
68963
  },
68964
/* dadd.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
68965
  {
68966
    { 0, 0, 0, 0 },
68967
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
68968
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b02000 }
68969
  },
68970
/* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
68971
  {
68972
    { 0, 0, 0, 0 },
68973
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
68974
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_An_relative_Prefixed_QI, { 0x1b20000 }
68975
  },
68976
/* dadd.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
68977
  {
68978
    { 0, 0, 0, 0 },
68979
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
68980
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_An_relative_Prefixed_QI, { 0x1b22000 }
68981
  },
68982
/* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
68983
  {
68984
    { 0, 0, 0, 0 },
68985
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
68986
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_An_relative_Prefixed_QI, { 0x1b40000 }
68987
  },
68988
/* dadd.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
68989
  {
68990
    { 0, 0, 0, 0 },
68991
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
68992
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_An_relative_Prefixed_QI, { 0x1b42000 }
68993
  },
68994
/* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
68995
  {
68996
    { 0, 0, 0, 0 },
68997
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
68998
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_An_relative_Prefixed_QI, { 0x1b60000 }
68999
  },
69000
/* dadd.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
69001
  {
69002
    { 0, 0, 0, 0 },
69003
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
69004
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_An_relative_Prefixed_QI, { 0x1b62000 }
69005
  },
69006
/* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
69007
  {
69008
    { 0, 0, 0, 0 },
69009
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
69010
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_QI, { 0x1b28000 }
69011
  },
69012
/* dadd.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
69013
  {
69014
    { 0, 0, 0, 0 },
69015
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
69016
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_QI, { 0x1b2a000 }
69017
  },
69018
/* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
69019
  {
69020
    { 0, 0, 0, 0 },
69021
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
69022
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_QI, { 0x1b48000 }
69023
  },
69024
/* dadd.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
69025
  {
69026
    { 0, 0, 0, 0 },
69027
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
69028
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_QI, { 0x1b4a000 }
69029
  },
69030
/* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
69031
  {
69032
    { 0, 0, 0, 0 },
69033
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
69034
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_QI, { 0x1b2c000 }
69035
  },
69036
/* dadd.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
69037
  {
69038
    { 0, 0, 0, 0 },
69039
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
69040
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_QI, { 0x1b2e000 }
69041
  },
69042
/* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
69043
  {
69044
    { 0, 0, 0, 0 },
69045
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
69046
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_QI, { 0x1b4c000 }
69047
  },
69048
/* dadd.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
69049
  {
69050
    { 0, 0, 0, 0 },
69051
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
69052
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_QI, { 0x1b4e000 }
69053
  },
69054
/* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
69055
  {
69056
    { 0, 0, 0, 0 },
69057
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), 0 } },
69058
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_absolute_Prefixed_QI, { 0x1b6c000 }
69059
  },
69060
/* dadd.b${X} ${Dsp-24-u24},${Dsp-48-u16} */
69061
  {
69062
    { 0, 0, 0, 0 },
69063
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), 0 } },
69064
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_absolute_Prefixed_QI, { 0x1b6e000 }
69065
  },
69066
/* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
69067
  {
69068
    { 0, 0, 0, 0 },
69069
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), 0 } },
69070
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_absolute_Prefixed_QI, { 0x1b68000 }
69071
  },
69072
/* dadd.b${X} ${Dsp-24-u24},${Dsp-48-u24} */
69073
  {
69074
    { 0, 0, 0, 0 },
69075
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), 0 } },
69076
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_absolute_Prefixed_QI, { 0x1b6a000 }
69077
  },
69078
/* dadd.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */
69079
  {
69080
    { 0, 0, 0, 0 },
69081
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32RNPREFIXEDQI), 0 } },
69082
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1c800 }
69083
  },
69084
/* dadd.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */
69085
  {
69086
    { 0, 0, 0, 0 },
69087
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DST32RNPREFIXEDQI), 0 } },
69088
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x18820 }
69089
  },
69090
/* dadd.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */
69091
  {
69092
    { 0, 0, 0, 0 },
69093
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
69094
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x18800 }
69095
  },
69096
/* dadd.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */
69097
  {
69098
    { 0, 0, 0, 0 },
69099
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32ANPREFIXEDQI), 0 } },
69100
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1c080 }
69101
  },
69102
/* dadd.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */
69103
  {
69104
    { 0, 0, 0, 0 },
69105
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DST32ANPREFIXEDQI), 0 } },
69106
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x180a0 }
69107
  },
69108
/* dadd.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */
69109
  {
69110
    { 0, 0, 0, 0 },
69111
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
69112
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x18080 }
69113
  },
69114
/* dadd.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
69115
  {
69116
    { 0, 0, 0, 0 },
69117
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
69118
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1c000 }
69119
  },
69120
/* dadd.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */
69121
  {
69122
    { 0, 0, 0, 0 },
69123
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
69124
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x18020 }
69125
  },
69126
/* dadd.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
69127
  {
69128
    { 0, 0, 0, 0 },
69129
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
69130
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x18000 }
69131
  },
69132
/* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
69133
  {
69134
    { 0, 0, 0, 0 },
69135
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
69136
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1c20000 }
69137
  },
69138
/* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
69139
  {
69140
    { 0, 0, 0, 0 },
69141
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
69142
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1822000 }
69143
  },
69144
/* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
69145
  {
69146
    { 0, 0, 0, 0 },
69147
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
69148
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1820000 }
69149
  },
69150
/* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
69151
  {
69152
    { 0, 0, 0, 0 },
69153
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
69154
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1c40000 }
69155
  },
69156
/* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
69157
  {
69158
    { 0, 0, 0, 0 },
69159
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
69160
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1842000 }
69161
  },
69162
/* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
69163
  {
69164
    { 0, 0, 0, 0 },
69165
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
69166
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1840000 }
69167
  },
69168
/* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
69169
  {
69170
    { 0, 0, 0, 0 },
69171
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
69172
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1c60000 }
69173
  },
69174
/* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
69175
  {
69176
    { 0, 0, 0, 0 },
69177
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
69178
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1862000 }
69179
  },
69180
/* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
69181
  {
69182
    { 0, 0, 0, 0 },
69183
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
69184
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1860000 }
69185
  },
69186
/* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
69187
  {
69188
    { 0, 0, 0, 0 },
69189
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
69190
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x1c28000 }
69191
  },
69192
/* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */
69193
  {
69194
    { 0, 0, 0, 0 },
69195
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
69196
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x182a000 }
69197
  },
69198
/* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
69199
  {
69200
    { 0, 0, 0, 0 },
69201
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
69202
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x1828000 }
69203
  },
69204
/* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
69205
  {
69206
    { 0, 0, 0, 0 },
69207
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
69208
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x1c48000 }
69209
  },
69210
/* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */
69211
  {
69212
    { 0, 0, 0, 0 },
69213
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
69214
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x184a000 }
69215
  },
69216
/* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
69217
  {
69218
    { 0, 0, 0, 0 },
69219
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
69220
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x1848000 }
69221
  },
69222
/* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
69223
  {
69224
    { 0, 0, 0, 0 },
69225
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
69226
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x1c2c000 }
69227
  },
69228
/* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */
69229
  {
69230
    { 0, 0, 0, 0 },
69231
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
69232
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x182e000 }
69233
  },
69234
/* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
69235
  {
69236
    { 0, 0, 0, 0 },
69237
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
69238
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x182c000 }
69239
  },
69240
/* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
69241
  {
69242
    { 0, 0, 0, 0 },
69243
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
69244
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x1c4c000 }
69245
  },
69246
/* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */
69247
  {
69248
    { 0, 0, 0, 0 },
69249
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
69250
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x184e000 }
69251
  },
69252
/* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
69253
  {
69254
    { 0, 0, 0, 0 },
69255
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
69256
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x184c000 }
69257
  },
69258
/* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */
69259
  {
69260
    { 0, 0, 0, 0 },
69261
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), 0 } },
69262
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x1c6c000 }
69263
  },
69264
/* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */
69265
  {
69266
    { 0, 0, 0, 0 },
69267
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), 0 } },
69268
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x186e000 }
69269
  },
69270
/* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */
69271
  {
69272
    { 0, 0, 0, 0 },
69273
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
69274
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x186c000 }
69275
  },
69276
/* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */
69277
  {
69278
    { 0, 0, 0, 0 },
69279
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), 0 } },
69280
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x1c68000 }
69281
  },
69282
/* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */
69283
  {
69284
    { 0, 0, 0, 0 },
69285
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U24), 0 } },
69286
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x186a000 }
69287
  },
69288
/* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */
69289
  {
69290
    { 0, 0, 0, 0 },
69291
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
69292
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x1868000 }
69293
  },
69294
/* dadd.w${X} #${Imm-24-HI},$Dst32RnPrefixedHI */
69295
  {
69296
    { 0, 0, 0, 0 },
69297
    { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DST32RNPREFIXEDHI), 0 } },
69298
    & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_Rn_direct_Prefixed_HI, { 0x1891e00 }
69299
  },
69300
/* dadd.w${X} #${Imm-24-HI},$Dst32AnPrefixedHI */
69301
  {
69302
    { 0, 0, 0, 0 },
69303
    { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DST32ANPREFIXEDHI), 0 } },
69304
    & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_An_direct_Prefixed_HI, { 0x1819e00 }
69305
  },
69306
/* dadd.w${X} #${Imm-24-HI},[$Dst32AnPrefixed] */
69307
  {
69308
    { 0, 0, 0, 0 },
69309
    { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
69310
    & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_An_indirect_Prefixed_HI, { 0x1811e00 }
69311
  },
69312
/* dadd.w${X} #${Imm-32-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */
69313
  {
69314
    { 0, 0, 0, 0 },
69315
    { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
69316
    & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_An_relative_Prefixed_HI, { 0x1831e00 }
69317
  },
69318
/* dadd.w${X} #${Imm-32-HI},${Dsp-24-u8}[sb] */
69319
  {
69320
    { 0, 0, 0, 0 },
69321
    { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
69322
    & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_SB_relative_Prefixed_HI, { 0x1839e00 }
69323
  },
69324
/* dadd.w${X} #${Imm-32-HI},${Dsp-24-s8}[fb] */
69325
  {
69326
    { 0, 0, 0, 0 },
69327
    { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
69328
    & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_FB_relative_Prefixed_HI, { 0x183de00 }
69329
  },
69330
/* dadd.w${X} #${Imm-40-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */
69331
  {
69332
    { 0, 0, 0, 0 },
69333
    { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
69334
    & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_An_relative_Prefixed_HI, { 0x1851e00 }
69335
  },
69336
/* dadd.w${X} #${Imm-40-HI},${Dsp-24-u16}[sb] */
69337
  {
69338
    { 0, 0, 0, 0 },
69339
    { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
69340
    & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_SB_relative_Prefixed_HI, { 0x1859e00 }
69341
  },
69342
/* dadd.w${X} #${Imm-40-HI},${Dsp-24-s16}[fb] */
69343
  {
69344
    { 0, 0, 0, 0 },
69345
    { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
69346
    & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_FB_relative_Prefixed_HI, { 0x185de00 }
69347
  },
69348
/* dadd.w${X} #${Imm-40-HI},${Dsp-24-u16} */
69349
  {
69350
    { 0, 0, 0, 0 },
69351
    { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), 0 } },
69352
    & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_absolute_Prefixed_HI, { 0x187de00 }
69353
  },
69354
/* dadd.w${X} #${Imm-48-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */
69355
  {
69356
    { 0, 0, 0, 0 },
69357
    { { MNEM, OP (X), ' ', '#', OP (IMM_48_HI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
69358
    & ifmt_sbb32_w_imm_G_24_24_Prefixed_dst32_24_24_An_relative_Prefixed_HI, { 0x1871e00 }
69359
  },
69360
/* dadd.w${X} #${Imm-48-HI},${Dsp-24-u24} */
69361
  {
69362
    { 0, 0, 0, 0 },
69363
    { { MNEM, OP (X), ' ', '#', OP (IMM_48_HI), ',', OP (DSP_24_U24), 0 } },
69364
    & ifmt_sbb32_w_imm_G_24_24_Prefixed_dst32_24_24_absolute_Prefixed_HI, { 0x1879e00 }
69365
  },
69366
/* dadd.b${X} #${Imm-24-QI},$Dst32RnPrefixedQI */
69367
  {
69368
    { 0, 0, 0, 0 },
69369
    { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DST32RNPREFIXEDQI), 0 } },
69370
    & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_Rn_direct_Prefixed_QI, { 0x1881e00 }
69371
  },
69372
/* dadd.b${X} #${Imm-24-QI},$Dst32AnPrefixedQI */
69373
  {
69374
    { 0, 0, 0, 0 },
69375
    { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DST32ANPREFIXEDQI), 0 } },
69376
    & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_An_direct_Prefixed_QI, { 0x1809e00 }
69377
  },
69378
/* dadd.b${X} #${Imm-24-QI},[$Dst32AnPrefixed] */
69379
  {
69380
    { 0, 0, 0, 0 },
69381
    { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
69382
    & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_An_indirect_Prefixed_QI, { 0x1801e00 }
69383
  },
69384
/* dadd.b${X} #${Imm-32-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */
69385
  {
69386
    { 0, 0, 0, 0 },
69387
    { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
69388
    & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_An_relative_Prefixed_QI, { 0x1821e00 }
69389
  },
69390
/* dadd.b${X} #${Imm-32-QI},${Dsp-24-u8}[sb] */
69391
  {
69392
    { 0, 0, 0, 0 },
69393
    { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
69394
    & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_SB_relative_Prefixed_QI, { 0x1829e00 }
69395
  },
69396
/* dadd.b${X} #${Imm-32-QI},${Dsp-24-s8}[fb] */
69397
  {
69398
    { 0, 0, 0, 0 },
69399
    { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
69400
    & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_FB_relative_Prefixed_QI, { 0x182de00 }
69401
  },
69402
/* dadd.b${X} #${Imm-40-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */
69403
  {
69404
    { 0, 0, 0, 0 },
69405
    { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
69406
    & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_An_relative_Prefixed_QI, { 0x1841e00 }
69407
  },
69408
/* dadd.b${X} #${Imm-40-QI},${Dsp-24-u16}[sb] */
69409
  {
69410
    { 0, 0, 0, 0 },
69411
    { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
69412
    & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_SB_relative_Prefixed_QI, { 0x1849e00 }
69413
  },
69414
/* dadd.b${X} #${Imm-40-QI},${Dsp-24-s16}[fb] */
69415
  {
69416
    { 0, 0, 0, 0 },
69417
    { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
69418
    & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_FB_relative_Prefixed_QI, { 0x184de00 }
69419
  },
69420
/* dadd.b${X} #${Imm-40-QI},${Dsp-24-u16} */
69421
  {
69422
    { 0, 0, 0, 0 },
69423
    { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), 0 } },
69424
    & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_absolute_Prefixed_QI, { 0x186de00 }
69425
  },
69426
/* dadd.b${X} #${Imm-48-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */
69427
  {
69428
    { 0, 0, 0, 0 },
69429
    { { MNEM, OP (X), ' ', '#', OP (IMM_48_QI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
69430
    & ifmt_sbb32_b_imm_G_24_24_Prefixed_dst32_24_24_An_relative_Prefixed_QI, { 0x1861e00 }
69431
  },
69432
/* dadd.b${X} #${Imm-48-QI},${Dsp-24-u24} */
69433
  {
69434
    { 0, 0, 0, 0 },
69435
    { { MNEM, OP (X), ' ', '#', OP (IMM_48_QI), ',', OP (DSP_24_U24), 0 } },
69436
    & ifmt_sbb32_b_imm_G_24_24_Prefixed_dst32_24_24_absolute_Prefixed_QI, { 0x1869e00 }
69437
  },
69438
/* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
69439
  {
69440
    { 0, 0, 0, 0 },
69441
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
69442
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1990800 }
69443
  },
69444
/* dadc.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
69445
  {
69446
    { 0, 0, 0, 0 },
69447
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
69448
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1992800 }
69449
  },
69450
/* dadc.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
69451
  {
69452
    { 0, 0, 0, 0 },
69453
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
69454
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1993800 }
69455
  },
69456
/* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
69457
  {
69458
    { 0, 0, 0, 0 },
69459
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
69460
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1918800 }
69461
  },
69462
/* dadc.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
69463
  {
69464
    { 0, 0, 0, 0 },
69465
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
69466
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x191a800 }
69467
  },
69468
/* dadc.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
69469
  {
69470
    { 0, 0, 0, 0 },
69471
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
69472
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x191b800 }
69473
  },
69474
/* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
69475
  {
69476
    { 0, 0, 0, 0 },
69477
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
69478
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1910800 }
69479
  },
69480
/* dadc.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
69481
  {
69482
    { 0, 0, 0, 0 },
69483
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
69484
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1912800 }
69485
  },
69486
/* dadc.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
69487
  {
69488
    { 0, 0, 0, 0 },
69489
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
69490
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1913800 }
69491
  },
69492
/* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
69493
  {
69494
    { 0, 0, 0, 0 },
69495
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
69496
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1930800 }
69497
  },
69498
/* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
69499
  {
69500
    { 0, 0, 0, 0 },
69501
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
69502
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1932800 }
69503
  },
69504
/* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
69505
  {
69506
    { 0, 0, 0, 0 },
69507
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
69508
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1933800 }
69509
  },
69510
/* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
69511
  {
69512
    { 0, 0, 0, 0 },
69513
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
69514
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1950800 }
69515
  },
69516
/* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
69517
  {
69518
    { 0, 0, 0, 0 },
69519
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
69520
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1952800 }
69521
  },
69522
/* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
69523
  {
69524
    { 0, 0, 0, 0 },
69525
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
69526
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1953800 }
69527
  },
69528
/* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
69529
  {
69530
    { 0, 0, 0, 0 },
69531
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
69532
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1970800 }
69533
  },
69534
/* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
69535
  {
69536
    { 0, 0, 0, 0 },
69537
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
69538
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1972800 }
69539
  },
69540
/* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
69541
  {
69542
    { 0, 0, 0, 0 },
69543
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
69544
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1973800 }
69545
  },
69546
/* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
69547
  {
69548
    { 0, 0, 0, 0 },
69549
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
69550
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x1938800 }
69551
  },
69552
/* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
69553
  {
69554
    { 0, 0, 0, 0 },
69555
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
69556
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x193a800 }
69557
  },
69558
/* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
69559
  {
69560
    { 0, 0, 0, 0 },
69561
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
69562
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x193b800 }
69563
  },
69564
/* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
69565
  {
69566
    { 0, 0, 0, 0 },
69567
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
69568
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x1958800 }
69569
  },
69570
/* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
69571
  {
69572
    { 0, 0, 0, 0 },
69573
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
69574
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x195a800 }
69575
  },
69576
/* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
69577
  {
69578
    { 0, 0, 0, 0 },
69579
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
69580
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x195b800 }
69581
  },
69582
/* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
69583
  {
69584
    { 0, 0, 0, 0 },
69585
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
69586
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193c800 }
69587
  },
69588
/* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
69589
  {
69590
    { 0, 0, 0, 0 },
69591
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
69592
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193e800 }
69593
  },
69594
/* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
69595
  {
69596
    { 0, 0, 0, 0 },
69597
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
69598
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193f800 }
69599
  },
69600
/* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
69601
  {
69602
    { 0, 0, 0, 0 },
69603
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
69604
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195c800 }
69605
  },
69606
/* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
69607
  {
69608
    { 0, 0, 0, 0 },
69609
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
69610
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195e800 }
69611
  },
69612
/* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
69613
  {
69614
    { 0, 0, 0, 0 },
69615
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
69616
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195f800 }
69617
  },
69618
/* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
69619
  {
69620
    { 0, 0, 0, 0 },
69621
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
69622
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197c800 }
69623
  },
69624
/* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
69625
  {
69626
    { 0, 0, 0, 0 },
69627
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
69628
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197e800 }
69629
  },
69630
/* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
69631
  {
69632
    { 0, 0, 0, 0 },
69633
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
69634
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197f800 }
69635
  },
69636
/* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
69637
  {
69638
    { 0, 0, 0, 0 },
69639
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
69640
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x1978800 }
69641
  },
69642
/* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
69643
  {
69644
    { 0, 0, 0, 0 },
69645
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
69646
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x197a800 }
69647
  },
69648
/* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
69649
  {
69650
    { 0, 0, 0, 0 },
69651
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
69652
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x197b800 }
69653
  },
69654
/* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
69655
  {
69656
    { 0, 0, 0, 0 },
69657
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
69658
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a90800 }
69659
  },
69660
/* dadc.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
69661
  {
69662
    { 0, 0, 0, 0 },
69663
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
69664
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a92800 }
69665
  },
69666
/* dadc.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
69667
  {
69668
    { 0, 0, 0, 0 },
69669
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
69670
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a93800 }
69671
  },
69672
/* dadc.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */
69673
  {
69674
    { 0, 0, 0, 0 },
69675
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32RNPREFIXEDHI), 0 } },
69676
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b93800 }
69677
  },
69678
/* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
69679
  {
69680
    { 0, 0, 0, 0 },
69681
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
69682
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a18800 }
69683
  },
69684
/* dadc.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
69685
  {
69686
    { 0, 0, 0, 0 },
69687
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
69688
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a1a800 }
69689
  },
69690
/* dadc.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
69691
  {
69692
    { 0, 0, 0, 0 },
69693
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
69694
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a1b800 }
69695
  },
69696
/* dadc.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */
69697
  {
69698
    { 0, 0, 0, 0 },
69699
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32ANPREFIXEDHI), 0 } },
69700
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b1b800 }
69701
  },
69702
/* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
69703
  {
69704
    { 0, 0, 0, 0 },
69705
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
69706
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a10800 }
69707
  },
69708
/* dadc.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
69709
  {
69710
    { 0, 0, 0, 0 },
69711
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
69712
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a12800 }
69713
  },
69714
/* dadc.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
69715
  {
69716
    { 0, 0, 0, 0 },
69717
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
69718
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a13800 }
69719
  },
69720
/* dadc.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
69721
  {
69722
    { 0, 0, 0, 0 },
69723
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
69724
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b13800 }
69725
  },
69726
/* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
69727
  {
69728
    { 0, 0, 0, 0 },
69729
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
69730
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a30800 }
69731
  },
69732
/* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
69733
  {
69734
    { 0, 0, 0, 0 },
69735
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
69736
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a32800 }
69737
  },
69738
/* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
69739
  {
69740
    { 0, 0, 0, 0 },
69741
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
69742
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a33800 }
69743
  },
69744
/* dadc.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
69745
  {
69746
    { 0, 0, 0, 0 },
69747
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
69748
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1b33800 }
69749
  },
69750
/* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
69751
  {
69752
    { 0, 0, 0, 0 },
69753
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
69754
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a50800 }
69755
  },
69756
/* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
69757
  {
69758
    { 0, 0, 0, 0 },
69759
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
69760
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a52800 }
69761
  },
69762
/* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
69763
  {
69764
    { 0, 0, 0, 0 },
69765
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
69766
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a53800 }
69767
  },
69768
/* dadc.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
69769
  {
69770
    { 0, 0, 0, 0 },
69771
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
69772
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1b53800 }
69773
  },
69774
/* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
69775
  {
69776
    { 0, 0, 0, 0 },
69777
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
69778
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a70800 }
69779
  },
69780
/* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
69781
  {
69782
    { 0, 0, 0, 0 },
69783
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
69784
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a72800 }
69785
  },
69786
/* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
69787
  {
69788
    { 0, 0, 0, 0 },
69789
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
69790
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a73800 }
69791
  },
69792
/* dadc.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
69793
  {
69794
    { 0, 0, 0, 0 },
69795
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
69796
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1b73800 }
69797
  },
69798
/* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
69799
  {
69800
    { 0, 0, 0, 0 },
69801
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
69802
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a38800 }
69803
  },
69804
/* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
69805
  {
69806
    { 0, 0, 0, 0 },
69807
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
69808
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a3a800 }
69809
  },
69810
/* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
69811
  {
69812
    { 0, 0, 0, 0 },
69813
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
69814
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a3b800 }
69815
  },
69816
/* dadc.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
69817
  {
69818
    { 0, 0, 0, 0 },
69819
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
69820
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1b3b800 }
69821
  },
69822
/* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
69823
  {
69824
    { 0, 0, 0, 0 },
69825
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
69826
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a58800 }
69827
  },
69828
/* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
69829
  {
69830
    { 0, 0, 0, 0 },
69831
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
69832
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a5a800 }
69833
  },
69834
/* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
69835
  {
69836
    { 0, 0, 0, 0 },
69837
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
69838
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a5b800 }
69839
  },
69840
/* dadc.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
69841
  {
69842
    { 0, 0, 0, 0 },
69843
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
69844
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1b5b800 }
69845
  },
69846
/* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
69847
  {
69848
    { 0, 0, 0, 0 },
69849
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
69850
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3c800 }
69851
  },
69852
/* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
69853
  {
69854
    { 0, 0, 0, 0 },
69855
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
69856
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3e800 }
69857
  },
69858
/* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
69859
  {
69860
    { 0, 0, 0, 0 },
69861
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
69862
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3f800 }
69863
  },
69864
/* dadc.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
69865
  {
69866
    { 0, 0, 0, 0 },
69867
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
69868
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1b3f800 }
69869
  },
69870
/* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
69871
  {
69872
    { 0, 0, 0, 0 },
69873
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
69874
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5c800 }
69875
  },
69876
/* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
69877
  {
69878
    { 0, 0, 0, 0 },
69879
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
69880
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5e800 }
69881
  },
69882
/* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
69883
  {
69884
    { 0, 0, 0, 0 },
69885
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
69886
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5f800 }
69887
  },
69888
/* dadc.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
69889
  {
69890
    { 0, 0, 0, 0 },
69891
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
69892
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1b5f800 }
69893
  },
69894
/* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
69895
  {
69896
    { 0, 0, 0, 0 },
69897
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
69898
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7c800 }
69899
  },
69900
/* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
69901
  {
69902
    { 0, 0, 0, 0 },
69903
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), 0 } },
69904
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7e800 }
69905
  },
69906
/* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
69907
  {
69908
    { 0, 0, 0, 0 },
69909
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), 0 } },
69910
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7f800 }
69911
  },
69912
/* dadc.w${X} ${Dsp-24-u16},${Dsp-40-u16} */
69913
  {
69914
    { 0, 0, 0, 0 },
69915
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), 0 } },
69916
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1b7f800 }
69917
  },
69918
/* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
69919
  {
69920
    { 0, 0, 0, 0 },
69921
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
69922
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a78800 }
69923
  },
69924
/* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
69925
  {
69926
    { 0, 0, 0, 0 },
69927
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), 0 } },
69928
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a7a800 }
69929
  },
69930
/* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
69931
  {
69932
    { 0, 0, 0, 0 },
69933
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), 0 } },
69934
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a7b800 }
69935
  },
69936
/* dadc.w${X} ${Dsp-24-u16},${Dsp-40-u24} */
69937
  {
69938
    { 0, 0, 0, 0 },
69939
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), 0 } },
69940
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1b7b800 }
69941
  },
69942
/* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
69943
  {
69944
    { 0, 0, 0, 0 },
69945
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
69946
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b90800 }
69947
  },
69948
/* dadc.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */
69949
  {
69950
    { 0, 0, 0, 0 },
69951
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32RNPREFIXEDHI), 0 } },
69952
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b92800 }
69953
  },
69954
/* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
69955
  {
69956
    { 0, 0, 0, 0 },
69957
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
69958
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b18800 }
69959
  },
69960
/* dadc.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */
69961
  {
69962
    { 0, 0, 0, 0 },
69963
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32ANPREFIXEDHI), 0 } },
69964
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b1a800 }
69965
  },
69966
/* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
69967
  {
69968
    { 0, 0, 0, 0 },
69969
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
69970
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b10800 }
69971
  },
69972
/* dadc.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
69973
  {
69974
    { 0, 0, 0, 0 },
69975
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
69976
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b12800 }
69977
  },
69978
/* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
69979
  {
69980
    { 0, 0, 0, 0 },
69981
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
69982
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b30800 }
69983
  },
69984
/* dadc.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
69985
  {
69986
    { 0, 0, 0, 0 },
69987
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
69988
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b32800 }
69989
  },
69990
/* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
69991
  {
69992
    { 0, 0, 0, 0 },
69993
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
69994
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b50800 }
69995
  },
69996
/* dadc.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
69997
  {
69998
    { 0, 0, 0, 0 },
69999
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
70000
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b52800 }
70001
  },
70002
/* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
70003
  {
70004
    { 0, 0, 0, 0 },
70005
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
70006
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b70800 }
70007
  },
70008
/* dadc.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
70009
  {
70010
    { 0, 0, 0, 0 },
70011
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
70012
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b72800 }
70013
  },
70014
/* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
70015
  {
70016
    { 0, 0, 0, 0 },
70017
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
70018
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b38800 }
70019
  },
70020
/* dadc.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
70021
  {
70022
    { 0, 0, 0, 0 },
70023
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
70024
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b3a800 }
70025
  },
70026
/* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
70027
  {
70028
    { 0, 0, 0, 0 },
70029
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
70030
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b58800 }
70031
  },
70032
/* dadc.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
70033
  {
70034
    { 0, 0, 0, 0 },
70035
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
70036
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b5a800 }
70037
  },
70038
/* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
70039
  {
70040
    { 0, 0, 0, 0 },
70041
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
70042
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b3c800 }
70043
  },
70044
/* dadc.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
70045
  {
70046
    { 0, 0, 0, 0 },
70047
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
70048
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b3e800 }
70049
  },
70050
/* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
70051
  {
70052
    { 0, 0, 0, 0 },
70053
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
70054
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b5c800 }
70055
  },
70056
/* dadc.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
70057
  {
70058
    { 0, 0, 0, 0 },
70059
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
70060
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b5e800 }
70061
  },
70062
/* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
70063
  {
70064
    { 0, 0, 0, 0 },
70065
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), 0 } },
70066
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_absolute_Prefixed_HI, { 0x1b7c800 }
70067
  },
70068
/* dadc.w${X} ${Dsp-24-u24},${Dsp-48-u16} */
70069
  {
70070
    { 0, 0, 0, 0 },
70071
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), 0 } },
70072
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_absolute_Prefixed_HI, { 0x1b7e800 }
70073
  },
70074
/* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
70075
  {
70076
    { 0, 0, 0, 0 },
70077
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), 0 } },
70078
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_24_absolute_Prefixed_HI, { 0x1b78800 }
70079
  },
70080
/* dadc.w${X} ${Dsp-24-u24},${Dsp-48-u24} */
70081
  {
70082
    { 0, 0, 0, 0 },
70083
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), 0 } },
70084
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_24_absolute_Prefixed_HI, { 0x1b7a800 }
70085
  },
70086
/* dadc.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */
70087
  {
70088
    { 0, 0, 0, 0 },
70089
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DST32RNPREFIXEDHI), 0 } },
70090
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1c908 }
70091
  },
70092
/* dadc.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */
70093
  {
70094
    { 0, 0, 0, 0 },
70095
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DST32RNPREFIXEDHI), 0 } },
70096
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x18928 }
70097
  },
70098
/* dadc.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */
70099
  {
70100
    { 0, 0, 0, 0 },
70101
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
70102
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x18908 }
70103
  },
70104
/* dadc.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */
70105
  {
70106
    { 0, 0, 0, 0 },
70107
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DST32ANPREFIXEDHI), 0 } },
70108
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1c188 }
70109
  },
70110
/* dadc.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */
70111
  {
70112
    { 0, 0, 0, 0 },
70113
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DST32ANPREFIXEDHI), 0 } },
70114
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x181a8 }
70115
  },
70116
/* dadc.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */
70117
  {
70118
    { 0, 0, 0, 0 },
70119
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
70120
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x18188 }
70121
  },
70122
/* dadc.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */
70123
  {
70124
    { 0, 0, 0, 0 },
70125
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
70126
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1c108 }
70127
  },
70128
/* dadc.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */
70129
  {
70130
    { 0, 0, 0, 0 },
70131
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
70132
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x18128 }
70133
  },
70134
/* dadc.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
70135
  {
70136
    { 0, 0, 0, 0 },
70137
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
70138
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x18108 }
70139
  },
70140
/* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
70141
  {
70142
    { 0, 0, 0, 0 },
70143
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
70144
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1c30800 }
70145
  },
70146
/* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
70147
  {
70148
    { 0, 0, 0, 0 },
70149
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
70150
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1832800 }
70151
  },
70152
/* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
70153
  {
70154
    { 0, 0, 0, 0 },
70155
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
70156
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1830800 }
70157
  },
70158
/* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
70159
  {
70160
    { 0, 0, 0, 0 },
70161
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
70162
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1c50800 }
70163
  },
70164
/* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
70165
  {
70166
    { 0, 0, 0, 0 },
70167
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
70168
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1852800 }
70169
  },
70170
/* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
70171
  {
70172
    { 0, 0, 0, 0 },
70173
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
70174
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1850800 }
70175
  },
70176
/* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
70177
  {
70178
    { 0, 0, 0, 0 },
70179
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
70180
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1c70800 }
70181
  },
70182
/* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
70183
  {
70184
    { 0, 0, 0, 0 },
70185
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
70186
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1872800 }
70187
  },
70188
/* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
70189
  {
70190
    { 0, 0, 0, 0 },
70191
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
70192
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1870800 }
70193
  },
70194
/* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */
70195
  {
70196
    { 0, 0, 0, 0 },
70197
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
70198
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1c38800 }
70199
  },
70200
/* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */
70201
  {
70202
    { 0, 0, 0, 0 },
70203
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
70204
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x183a800 }
70205
  },
70206
/* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
70207
  {
70208
    { 0, 0, 0, 0 },
70209
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
70210
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1838800 }
70211
  },
70212
/* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */
70213
  {
70214
    { 0, 0, 0, 0 },
70215
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
70216
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1c58800 }
70217
  },
70218
/* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */
70219
  {
70220
    { 0, 0, 0, 0 },
70221
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
70222
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x185a800 }
70223
  },
70224
/* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
70225
  {
70226
    { 0, 0, 0, 0 },
70227
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
70228
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1858800 }
70229
  },
70230
/* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */
70231
  {
70232
    { 0, 0, 0, 0 },
70233
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
70234
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x1c3c800 }
70235
  },
70236
/* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */
70237
  {
70238
    { 0, 0, 0, 0 },
70239
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
70240
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x183e800 }
70241
  },
70242
/* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
70243
  {
70244
    { 0, 0, 0, 0 },
70245
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
70246
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x183c800 }
70247
  },
70248
/* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */
70249
  {
70250
    { 0, 0, 0, 0 },
70251
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
70252
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x1c5c800 }
70253
  },
70254
/* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */
70255
  {
70256
    { 0, 0, 0, 0 },
70257
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
70258
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x185e800 }
70259
  },
70260
/* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
70261
  {
70262
    { 0, 0, 0, 0 },
70263
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
70264
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x185c800 }
70265
  },
70266
/* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */
70267
  {
70268
    { 0, 0, 0, 0 },
70269
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), 0 } },
70270
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x1c7c800 }
70271
  },
70272
/* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */
70273
  {
70274
    { 0, 0, 0, 0 },
70275
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), 0 } },
70276
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x187e800 }
70277
  },
70278
/* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */
70279
  {
70280
    { 0, 0, 0, 0 },
70281
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
70282
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x187c800 }
70283
  },
70284
/* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */
70285
  {
70286
    { 0, 0, 0, 0 },
70287
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U24), 0 } },
70288
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x1c78800 }
70289
  },
70290
/* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */
70291
  {
70292
    { 0, 0, 0, 0 },
70293
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U24), 0 } },
70294
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x187a800 }
70295
  },
70296
/* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */
70297
  {
70298
    { 0, 0, 0, 0 },
70299
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
70300
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x1878800 }
70301
  },
70302
/* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
70303
  {
70304
    { 0, 0, 0, 0 },
70305
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
70306
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1980800 }
70307
  },
70308
/* dadc.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */
70309
  {
70310
    { 0, 0, 0, 0 },
70311
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
70312
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1982800 }
70313
  },
70314
/* dadc.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */
70315
  {
70316
    { 0, 0, 0, 0 },
70317
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
70318
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1983800 }
70319
  },
70320
/* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
70321
  {
70322
    { 0, 0, 0, 0 },
70323
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
70324
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1908800 }
70325
  },
70326
/* dadc.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */
70327
  {
70328
    { 0, 0, 0, 0 },
70329
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
70330
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x190a800 }
70331
  },
70332
/* dadc.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */
70333
  {
70334
    { 0, 0, 0, 0 },
70335
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
70336
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x190b800 }
70337
  },
70338
/* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
70339
  {
70340
    { 0, 0, 0, 0 },
70341
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
70342
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1900800 }
70343
  },
70344
/* dadc.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
70345
  {
70346
    { 0, 0, 0, 0 },
70347
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
70348
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1902800 }
70349
  },
70350
/* dadc.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
70351
  {
70352
    { 0, 0, 0, 0 },
70353
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
70354
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1903800 }
70355
  },
70356
/* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
70357
  {
70358
    { 0, 0, 0, 0 },
70359
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
70360
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1920800 }
70361
  },
70362
/* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
70363
  {
70364
    { 0, 0, 0, 0 },
70365
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
70366
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1922800 }
70367
  },
70368
/* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
70369
  {
70370
    { 0, 0, 0, 0 },
70371
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
70372
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1923800 }
70373
  },
70374
/* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
70375
  {
70376
    { 0, 0, 0, 0 },
70377
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
70378
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1940800 }
70379
  },
70380
/* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
70381
  {
70382
    { 0, 0, 0, 0 },
70383
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
70384
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1942800 }
70385
  },
70386
/* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
70387
  {
70388
    { 0, 0, 0, 0 },
70389
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
70390
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1943800 }
70391
  },
70392
/* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
70393
  {
70394
    { 0, 0, 0, 0 },
70395
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
70396
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1960800 }
70397
  },
70398
/* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
70399
  {
70400
    { 0, 0, 0, 0 },
70401
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
70402
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1962800 }
70403
  },
70404
/* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
70405
  {
70406
    { 0, 0, 0, 0 },
70407
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
70408
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1963800 }
70409
  },
70410
/* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
70411
  {
70412
    { 0, 0, 0, 0 },
70413
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
70414
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x1928800 }
70415
  },
70416
/* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
70417
  {
70418
    { 0, 0, 0, 0 },
70419
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
70420
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x192a800 }
70421
  },
70422
/* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
70423
  {
70424
    { 0, 0, 0, 0 },
70425
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
70426
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x192b800 }
70427
  },
70428
/* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
70429
  {
70430
    { 0, 0, 0, 0 },
70431
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
70432
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x1948800 }
70433
  },
70434
/* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
70435
  {
70436
    { 0, 0, 0, 0 },
70437
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
70438
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x194a800 }
70439
  },
70440
/* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
70441
  {
70442
    { 0, 0, 0, 0 },
70443
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
70444
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x194b800 }
70445
  },
70446
/* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
70447
  {
70448
    { 0, 0, 0, 0 },
70449
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
70450
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192c800 }
70451
  },
70452
/* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
70453
  {
70454
    { 0, 0, 0, 0 },
70455
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
70456
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192e800 }
70457
  },
70458
/* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
70459
  {
70460
    { 0, 0, 0, 0 },
70461
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
70462
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192f800 }
70463
  },
70464
/* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
70465
  {
70466
    { 0, 0, 0, 0 },
70467
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
70468
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194c800 }
70469
  },
70470
/* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
70471
  {
70472
    { 0, 0, 0, 0 },
70473
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
70474
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194e800 }
70475
  },
70476
/* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
70477
  {
70478
    { 0, 0, 0, 0 },
70479
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
70480
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194f800 }
70481
  },
70482
/* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
70483
  {
70484
    { 0, 0, 0, 0 },
70485
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
70486
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196c800 }
70487
  },
70488
/* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
70489
  {
70490
    { 0, 0, 0, 0 },
70491
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
70492
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196e800 }
70493
  },
70494
/* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
70495
  {
70496
    { 0, 0, 0, 0 },
70497
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
70498
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196f800 }
70499
  },
70500
/* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
70501
  {
70502
    { 0, 0, 0, 0 },
70503
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
70504
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x1968800 }
70505
  },
70506
/* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
70507
  {
70508
    { 0, 0, 0, 0 },
70509
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
70510
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x196a800 }
70511
  },
70512
/* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
70513
  {
70514
    { 0, 0, 0, 0 },
70515
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
70516
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x196b800 }
70517
  },
70518
/* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
70519
  {
70520
    { 0, 0, 0, 0 },
70521
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
70522
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a80800 }
70523
  },
70524
/* dadc.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */
70525
  {
70526
    { 0, 0, 0, 0 },
70527
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
70528
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a82800 }
70529
  },
70530
/* dadc.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */
70531
  {
70532
    { 0, 0, 0, 0 },
70533
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
70534
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a83800 }
70535
  },
70536
/* dadc.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */
70537
  {
70538
    { 0, 0, 0, 0 },
70539
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32RNPREFIXEDQI), 0 } },
70540
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b83800 }
70541
  },
70542
/* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
70543
  {
70544
    { 0, 0, 0, 0 },
70545
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
70546
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a08800 }
70547
  },
70548
/* dadc.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */
70549
  {
70550
    { 0, 0, 0, 0 },
70551
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
70552
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a0a800 }
70553
  },
70554
/* dadc.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */
70555
  {
70556
    { 0, 0, 0, 0 },
70557
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
70558
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a0b800 }
70559
  },
70560
/* dadc.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */
70561
  {
70562
    { 0, 0, 0, 0 },
70563
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32ANPREFIXEDQI), 0 } },
70564
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b0b800 }
70565
  },
70566
/* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
70567
  {
70568
    { 0, 0, 0, 0 },
70569
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
70570
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a00800 }
70571
  },
70572
/* dadc.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
70573
  {
70574
    { 0, 0, 0, 0 },
70575
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
70576
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a02800 }
70577
  },
70578
/* dadc.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
70579
  {
70580
    { 0, 0, 0, 0 },
70581
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
70582
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a03800 }
70583
  },
70584
/* dadc.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
70585
  {
70586
    { 0, 0, 0, 0 },
70587
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
70588
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b03800 }
70589
  },
70590
/* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
70591
  {
70592
    { 0, 0, 0, 0 },
70593
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
70594
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a20800 }
70595
  },
70596
/* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
70597
  {
70598
    { 0, 0, 0, 0 },
70599
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
70600
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a22800 }
70601
  },
70602
/* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
70603
  {
70604
    { 0, 0, 0, 0 },
70605
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
70606
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a23800 }
70607
  },
70608
/* dadc.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
70609
  {
70610
    { 0, 0, 0, 0 },
70611
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
70612
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1b23800 }
70613
  },
70614
/* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
70615
  {
70616
    { 0, 0, 0, 0 },
70617
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
70618
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a40800 }
70619
  },
70620
/* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
70621
  {
70622
    { 0, 0, 0, 0 },
70623
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
70624
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a42800 }
70625
  },
70626
/* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
70627
  {
70628
    { 0, 0, 0, 0 },
70629
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
70630
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a43800 }
70631
  },
70632
/* dadc.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
70633
  {
70634
    { 0, 0, 0, 0 },
70635
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
70636
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1b43800 }
70637
  },
70638
/* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
70639
  {
70640
    { 0, 0, 0, 0 },
70641
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
70642
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a60800 }
70643
  },
70644
/* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
70645
  {
70646
    { 0, 0, 0, 0 },
70647
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
70648
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a62800 }
70649
  },
70650
/* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
70651
  {
70652
    { 0, 0, 0, 0 },
70653
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
70654
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a63800 }
70655
  },
70656
/* dadc.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
70657
  {
70658
    { 0, 0, 0, 0 },
70659
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
70660
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1b63800 }
70661
  },
70662
/* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
70663
  {
70664
    { 0, 0, 0, 0 },
70665
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
70666
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a28800 }
70667
  },
70668
/* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
70669
  {
70670
    { 0, 0, 0, 0 },
70671
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
70672
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a2a800 }
70673
  },
70674
/* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
70675
  {
70676
    { 0, 0, 0, 0 },
70677
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
70678
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a2b800 }
70679
  },
70680
/* dadc.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
70681
  {
70682
    { 0, 0, 0, 0 },
70683
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
70684
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1b2b800 }
70685
  },
70686
/* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
70687
  {
70688
    { 0, 0, 0, 0 },
70689
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
70690
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a48800 }
70691
  },
70692
/* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
70693
  {
70694
    { 0, 0, 0, 0 },
70695
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
70696
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a4a800 }
70697
  },
70698
/* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
70699
  {
70700
    { 0, 0, 0, 0 },
70701
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
70702
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a4b800 }
70703
  },
70704
/* dadc.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
70705
  {
70706
    { 0, 0, 0, 0 },
70707
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
70708
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1b4b800 }
70709
  },
70710
/* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
70711
  {
70712
    { 0, 0, 0, 0 },
70713
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
70714
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2c800 }
70715
  },
70716
/* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
70717
  {
70718
    { 0, 0, 0, 0 },
70719
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
70720
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2e800 }
70721
  },
70722
/* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
70723
  {
70724
    { 0, 0, 0, 0 },
70725
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
70726
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2f800 }
70727
  },
70728
/* dadc.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
70729
  {
70730
    { 0, 0, 0, 0 },
70731
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
70732
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1b2f800 }
70733
  },
70734
/* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
70735
  {
70736
    { 0, 0, 0, 0 },
70737
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
70738
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4c800 }
70739
  },
70740
/* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
70741
  {
70742
    { 0, 0, 0, 0 },
70743
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
70744
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4e800 }
70745
  },
70746
/* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
70747
  {
70748
    { 0, 0, 0, 0 },
70749
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
70750
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4f800 }
70751
  },
70752
/* dadc.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
70753
  {
70754
    { 0, 0, 0, 0 },
70755
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
70756
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1b4f800 }
70757
  },
70758
/* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
70759
  {
70760
    { 0, 0, 0, 0 },
70761
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
70762
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6c800 }
70763
  },
70764
/* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
70765
  {
70766
    { 0, 0, 0, 0 },
70767
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), 0 } },
70768
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6e800 }
70769
  },
70770
/* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
70771
  {
70772
    { 0, 0, 0, 0 },
70773
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), 0 } },
70774
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6f800 }
70775
  },
70776
/* dadc.b${X} ${Dsp-24-u16},${Dsp-40-u16} */
70777
  {
70778
    { 0, 0, 0, 0 },
70779
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), 0 } },
70780
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1b6f800 }
70781
  },
70782
/* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
70783
  {
70784
    { 0, 0, 0, 0 },
70785
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
70786
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a68800 }
70787
  },
70788
/* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
70789
  {
70790
    { 0, 0, 0, 0 },
70791
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), 0 } },
70792
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a6a800 }
70793
  },
70794
/* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
70795
  {
70796
    { 0, 0, 0, 0 },
70797
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), 0 } },
70798
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a6b800 }
70799
  },
70800
/* dadc.b${X} ${Dsp-24-u16},${Dsp-40-u24} */
70801
  {
70802
    { 0, 0, 0, 0 },
70803
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), 0 } },
70804
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1b6b800 }
70805
  },
70806
/* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
70807
  {
70808
    { 0, 0, 0, 0 },
70809
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
70810
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b80800 }
70811
  },
70812
/* dadc.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */
70813
  {
70814
    { 0, 0, 0, 0 },
70815
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32RNPREFIXEDQI), 0 } },
70816
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b82800 }
70817
  },
70818
/* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
70819
  {
70820
    { 0, 0, 0, 0 },
70821
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
70822
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b08800 }
70823
  },
70824
/* dadc.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */
70825
  {
70826
    { 0, 0, 0, 0 },
70827
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32ANPREFIXEDQI), 0 } },
70828
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b0a800 }
70829
  },
70830
/* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
70831
  {
70832
    { 0, 0, 0, 0 },
70833
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
70834
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b00800 }
70835
  },
70836
/* dadc.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
70837
  {
70838
    { 0, 0, 0, 0 },
70839
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
70840
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b02800 }
70841
  },
70842
/* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
70843
  {
70844
    { 0, 0, 0, 0 },
70845
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
70846
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_An_relative_Prefixed_QI, { 0x1b20800 }
70847
  },
70848
/* dadc.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
70849
  {
70850
    { 0, 0, 0, 0 },
70851
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
70852
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_An_relative_Prefixed_QI, { 0x1b22800 }
70853
  },
70854
/* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
70855
  {
70856
    { 0, 0, 0, 0 },
70857
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
70858
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_An_relative_Prefixed_QI, { 0x1b40800 }
70859
  },
70860
/* dadc.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
70861
  {
70862
    { 0, 0, 0, 0 },
70863
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
70864
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_An_relative_Prefixed_QI, { 0x1b42800 }
70865
  },
70866
/* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
70867
  {
70868
    { 0, 0, 0, 0 },
70869
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
70870
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_An_relative_Prefixed_QI, { 0x1b60800 }
70871
  },
70872
/* dadc.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
70873
  {
70874
    { 0, 0, 0, 0 },
70875
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
70876
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_An_relative_Prefixed_QI, { 0x1b62800 }
70877
  },
70878
/* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
70879
  {
70880
    { 0, 0, 0, 0 },
70881
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
70882
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_QI, { 0x1b28800 }
70883
  },
70884
/* dadc.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
70885
  {
70886
    { 0, 0, 0, 0 },
70887
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
70888
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_QI, { 0x1b2a800 }
70889
  },
70890
/* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
70891
  {
70892
    { 0, 0, 0, 0 },
70893
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
70894
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_QI, { 0x1b48800 }
70895
  },
70896
/* dadc.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
70897
  {
70898
    { 0, 0, 0, 0 },
70899
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
70900
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_QI, { 0x1b4a800 }
70901
  },
70902
/* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
70903
  {
70904
    { 0, 0, 0, 0 },
70905
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
70906
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_QI, { 0x1b2c800 }
70907
  },
70908
/* dadc.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
70909
  {
70910
    { 0, 0, 0, 0 },
70911
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
70912
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_QI, { 0x1b2e800 }
70913
  },
70914
/* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
70915
  {
70916
    { 0, 0, 0, 0 },
70917
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
70918
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_QI, { 0x1b4c800 }
70919
  },
70920
/* dadc.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
70921
  {
70922
    { 0, 0, 0, 0 },
70923
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
70924
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_QI, { 0x1b4e800 }
70925
  },
70926
/* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
70927
  {
70928
    { 0, 0, 0, 0 },
70929
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), 0 } },
70930
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_absolute_Prefixed_QI, { 0x1b6c800 }
70931
  },
70932
/* dadc.b${X} ${Dsp-24-u24},${Dsp-48-u16} */
70933
  {
70934
    { 0, 0, 0, 0 },
70935
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), 0 } },
70936
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_absolute_Prefixed_QI, { 0x1b6e800 }
70937
  },
70938
/* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
70939
  {
70940
    { 0, 0, 0, 0 },
70941
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), 0 } },
70942
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_absolute_Prefixed_QI, { 0x1b68800 }
70943
  },
70944
/* dadc.b${X} ${Dsp-24-u24},${Dsp-48-u24} */
70945
  {
70946
    { 0, 0, 0, 0 },
70947
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), 0 } },
70948
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_absolute_Prefixed_QI, { 0x1b6a800 }
70949
  },
70950
/* dadc.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */
70951
  {
70952
    { 0, 0, 0, 0 },
70953
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32RNPREFIXEDQI), 0 } },
70954
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1c808 }
70955
  },
70956
/* dadc.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */
70957
  {
70958
    { 0, 0, 0, 0 },
70959
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DST32RNPREFIXEDQI), 0 } },
70960
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x18828 }
70961
  },
70962
/* dadc.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */
70963
  {
70964
    { 0, 0, 0, 0 },
70965
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
70966
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x18808 }
70967
  },
70968
/* dadc.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */
70969
  {
70970
    { 0, 0, 0, 0 },
70971
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32ANPREFIXEDQI), 0 } },
70972
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1c088 }
70973
  },
70974
/* dadc.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */
70975
  {
70976
    { 0, 0, 0, 0 },
70977
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DST32ANPREFIXEDQI), 0 } },
70978
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x180a8 }
70979
  },
70980
/* dadc.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */
70981
  {
70982
    { 0, 0, 0, 0 },
70983
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
70984
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x18088 }
70985
  },
70986
/* dadc.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
70987
  {
70988
    { 0, 0, 0, 0 },
70989
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
70990
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1c008 }
70991
  },
70992
/* dadc.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */
70993
  {
70994
    { 0, 0, 0, 0 },
70995
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
70996
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x18028 }
70997
  },
70998
/* dadc.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
70999
  {
71000
    { 0, 0, 0, 0 },
71001
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
71002
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x18008 }
71003
  },
71004
/* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
71005
  {
71006
    { 0, 0, 0, 0 },
71007
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
71008
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1c20800 }
71009
  },
71010
/* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
71011
  {
71012
    { 0, 0, 0, 0 },
71013
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
71014
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1822800 }
71015
  },
71016
/* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
71017
  {
71018
    { 0, 0, 0, 0 },
71019
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
71020
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1820800 }
71021
  },
71022
/* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
71023
  {
71024
    { 0, 0, 0, 0 },
71025
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
71026
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1c40800 }
71027
  },
71028
/* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
71029
  {
71030
    { 0, 0, 0, 0 },
71031
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
71032
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1842800 }
71033
  },
71034
/* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
71035
  {
71036
    { 0, 0, 0, 0 },
71037
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
71038
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1840800 }
71039
  },
71040
/* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
71041
  {
71042
    { 0, 0, 0, 0 },
71043
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
71044
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1c60800 }
71045
  },
71046
/* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
71047
  {
71048
    { 0, 0, 0, 0 },
71049
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
71050
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1862800 }
71051
  },
71052
/* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
71053
  {
71054
    { 0, 0, 0, 0 },
71055
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
71056
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1860800 }
71057
  },
71058
/* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
71059
  {
71060
    { 0, 0, 0, 0 },
71061
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
71062
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x1c28800 }
71063
  },
71064
/* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */
71065
  {
71066
    { 0, 0, 0, 0 },
71067
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
71068
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x182a800 }
71069
  },
71070
/* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
71071
  {
71072
    { 0, 0, 0, 0 },
71073
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
71074
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x1828800 }
71075
  },
71076
/* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
71077
  {
71078
    { 0, 0, 0, 0 },
71079
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
71080
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x1c48800 }
71081
  },
71082
/* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */
71083
  {
71084
    { 0, 0, 0, 0 },
71085
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
71086
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x184a800 }
71087
  },
71088
/* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
71089
  {
71090
    { 0, 0, 0, 0 },
71091
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
71092
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x1848800 }
71093
  },
71094
/* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
71095
  {
71096
    { 0, 0, 0, 0 },
71097
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
71098
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x1c2c800 }
71099
  },
71100
/* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */
71101
  {
71102
    { 0, 0, 0, 0 },
71103
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
71104
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x182e800 }
71105
  },
71106
/* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
71107
  {
71108
    { 0, 0, 0, 0 },
71109
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
71110
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x182c800 }
71111
  },
71112
/* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
71113
  {
71114
    { 0, 0, 0, 0 },
71115
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
71116
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x1c4c800 }
71117
  },
71118
/* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */
71119
  {
71120
    { 0, 0, 0, 0 },
71121
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
71122
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x184e800 }
71123
  },
71124
/* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
71125
  {
71126
    { 0, 0, 0, 0 },
71127
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
71128
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x184c800 }
71129
  },
71130
/* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */
71131
  {
71132
    { 0, 0, 0, 0 },
71133
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), 0 } },
71134
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x1c6c800 }
71135
  },
71136
/* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */
71137
  {
71138
    { 0, 0, 0, 0 },
71139
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), 0 } },
71140
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x186e800 }
71141
  },
71142
/* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */
71143
  {
71144
    { 0, 0, 0, 0 },
71145
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
71146
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x186c800 }
71147
  },
71148
/* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */
71149
  {
71150
    { 0, 0, 0, 0 },
71151
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), 0 } },
71152
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x1c68800 }
71153
  },
71154
/* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */
71155
  {
71156
    { 0, 0, 0, 0 },
71157
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U24), 0 } },
71158
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x186a800 }
71159
  },
71160
/* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */
71161
  {
71162
    { 0, 0, 0, 0 },
71163
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
71164
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x1868800 }
71165
  },
71166
/* dadc.w${X} #${Imm-24-HI},$Dst32RnPrefixedHI */
71167
  {
71168
    { 0, 0, 0, 0 },
71169
    { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DST32RNPREFIXEDHI), 0 } },
71170
    & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_Rn_direct_Prefixed_HI, { 0x1890e00 }
71171
  },
71172
/* dadc.w${X} #${Imm-24-HI},$Dst32AnPrefixedHI */
71173
  {
71174
    { 0, 0, 0, 0 },
71175
    { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DST32ANPREFIXEDHI), 0 } },
71176
    & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_An_direct_Prefixed_HI, { 0x1818e00 }
71177
  },
71178
/* dadc.w${X} #${Imm-24-HI},[$Dst32AnPrefixed] */
71179
  {
71180
    { 0, 0, 0, 0 },
71181
    { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
71182
    & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_An_indirect_Prefixed_HI, { 0x1810e00 }
71183
  },
71184
/* dadc.w${X} #${Imm-32-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */
71185
  {
71186
    { 0, 0, 0, 0 },
71187
    { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
71188
    & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_An_relative_Prefixed_HI, { 0x1830e00 }
71189
  },
71190
/* dadc.w${X} #${Imm-32-HI},${Dsp-24-u8}[sb] */
71191
  {
71192
    { 0, 0, 0, 0 },
71193
    { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
71194
    & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_SB_relative_Prefixed_HI, { 0x1838e00 }
71195
  },
71196
/* dadc.w${X} #${Imm-32-HI},${Dsp-24-s8}[fb] */
71197
  {
71198
    { 0, 0, 0, 0 },
71199
    { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
71200
    & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_FB_relative_Prefixed_HI, { 0x183ce00 }
71201
  },
71202
/* dadc.w${X} #${Imm-40-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */
71203
  {
71204
    { 0, 0, 0, 0 },
71205
    { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
71206
    & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_An_relative_Prefixed_HI, { 0x1850e00 }
71207
  },
71208
/* dadc.w${X} #${Imm-40-HI},${Dsp-24-u16}[sb] */
71209
  {
71210
    { 0, 0, 0, 0 },
71211
    { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
71212
    & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_SB_relative_Prefixed_HI, { 0x1858e00 }
71213
  },
71214
/* dadc.w${X} #${Imm-40-HI},${Dsp-24-s16}[fb] */
71215
  {
71216
    { 0, 0, 0, 0 },
71217
    { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
71218
    & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_FB_relative_Prefixed_HI, { 0x185ce00 }
71219
  },
71220
/* dadc.w${X} #${Imm-40-HI},${Dsp-24-u16} */
71221
  {
71222
    { 0, 0, 0, 0 },
71223
    { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), 0 } },
71224
    & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_absolute_Prefixed_HI, { 0x187ce00 }
71225
  },
71226
/* dadc.w${X} #${Imm-48-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */
71227
  {
71228
    { 0, 0, 0, 0 },
71229
    { { MNEM, OP (X), ' ', '#', OP (IMM_48_HI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
71230
    & ifmt_sbb32_w_imm_G_24_24_Prefixed_dst32_24_24_An_relative_Prefixed_HI, { 0x1870e00 }
71231
  },
71232
/* dadc.w${X} #${Imm-48-HI},${Dsp-24-u24} */
71233
  {
71234
    { 0, 0, 0, 0 },
71235
    { { MNEM, OP (X), ' ', '#', OP (IMM_48_HI), ',', OP (DSP_24_U24), 0 } },
71236
    & ifmt_sbb32_w_imm_G_24_24_Prefixed_dst32_24_24_absolute_Prefixed_HI, { 0x1878e00 }
71237
  },
71238
/* dadc.b${X} #${Imm-24-QI},$Dst32RnPrefixedQI */
71239
  {
71240
    { 0, 0, 0, 0 },
71241
    { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DST32RNPREFIXEDQI), 0 } },
71242
    & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_Rn_direct_Prefixed_QI, { 0x1880e00 }
71243
  },
71244
/* dadc.b${X} #${Imm-24-QI},$Dst32AnPrefixedQI */
71245
  {
71246
    { 0, 0, 0, 0 },
71247
    { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DST32ANPREFIXEDQI), 0 } },
71248
    & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_An_direct_Prefixed_QI, { 0x1808e00 }
71249
  },
71250
/* dadc.b${X} #${Imm-24-QI},[$Dst32AnPrefixed] */
71251
  {
71252
    { 0, 0, 0, 0 },
71253
    { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
71254
    & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_An_indirect_Prefixed_QI, { 0x1800e00 }
71255
  },
71256
/* dadc.b${X} #${Imm-32-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */
71257
  {
71258
    { 0, 0, 0, 0 },
71259
    { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
71260
    & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_An_relative_Prefixed_QI, { 0x1820e00 }
71261
  },
71262
/* dadc.b${X} #${Imm-32-QI},${Dsp-24-u8}[sb] */
71263
  {
71264
    { 0, 0, 0, 0 },
71265
    { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
71266
    & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_SB_relative_Prefixed_QI, { 0x1828e00 }
71267
  },
71268
/* dadc.b${X} #${Imm-32-QI},${Dsp-24-s8}[fb] */
71269
  {
71270
    { 0, 0, 0, 0 },
71271
    { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
71272
    & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_FB_relative_Prefixed_QI, { 0x182ce00 }
71273
  },
71274
/* dadc.b${X} #${Imm-40-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */
71275
  {
71276
    { 0, 0, 0, 0 },
71277
    { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
71278
    & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_An_relative_Prefixed_QI, { 0x1840e00 }
71279
  },
71280
/* dadc.b${X} #${Imm-40-QI},${Dsp-24-u16}[sb] */
71281
  {
71282
    { 0, 0, 0, 0 },
71283
    { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
71284
    & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_SB_relative_Prefixed_QI, { 0x1848e00 }
71285
  },
71286
/* dadc.b${X} #${Imm-40-QI},${Dsp-24-s16}[fb] */
71287
  {
71288
    { 0, 0, 0, 0 },
71289
    { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
71290
    & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_FB_relative_Prefixed_QI, { 0x184ce00 }
71291
  },
71292
/* dadc.b${X} #${Imm-40-QI},${Dsp-24-u16} */
71293
  {
71294
    { 0, 0, 0, 0 },
71295
    { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), 0 } },
71296
    & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_absolute_Prefixed_QI, { 0x186ce00 }
71297
  },
71298
/* dadc.b${X} #${Imm-48-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */
71299
  {
71300
    { 0, 0, 0, 0 },
71301
    { { MNEM, OP (X), ' ', '#', OP (IMM_48_QI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
71302
    & ifmt_sbb32_b_imm_G_24_24_Prefixed_dst32_24_24_An_relative_Prefixed_QI, { 0x1860e00 }
71303
  },
71304
/* dadc.b${X} #${Imm-48-QI},${Dsp-24-u24} */
71305
  {
71306
    { 0, 0, 0, 0 },
71307
    { { MNEM, OP (X), ' ', '#', OP (IMM_48_QI), ',', OP (DSP_24_U24), 0 } },
71308
    & ifmt_sbb32_b_imm_G_24_24_Prefixed_dst32_24_24_absolute_Prefixed_QI, { 0x1868e00 }
71309
  },
71310
/* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
71311
  {
71312
    { 0, 0, 0, 0 },
71313
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
71314
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1990400 }
71315
  },
71316
/* adc.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
71317
  {
71318
    { 0, 0, 0, 0 },
71319
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
71320
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1992400 }
71321
  },
71322
/* adc.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
71323
  {
71324
    { 0, 0, 0, 0 },
71325
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
71326
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1993400 }
71327
  },
71328
/* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
71329
  {
71330
    { 0, 0, 0, 0 },
71331
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
71332
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1918400 }
71333
  },
71334
/* adc.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
71335
  {
71336
    { 0, 0, 0, 0 },
71337
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
71338
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x191a400 }
71339
  },
71340
/* adc.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
71341
  {
71342
    { 0, 0, 0, 0 },
71343
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
71344
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x191b400 }
71345
  },
71346
/* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
71347
  {
71348
    { 0, 0, 0, 0 },
71349
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
71350
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1910400 }
71351
  },
71352
/* adc.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
71353
  {
71354
    { 0, 0, 0, 0 },
71355
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
71356
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1912400 }
71357
  },
71358
/* adc.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
71359
  {
71360
    { 0, 0, 0, 0 },
71361
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
71362
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1913400 }
71363
  },
71364
/* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
71365
  {
71366
    { 0, 0, 0, 0 },
71367
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
71368
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1930400 }
71369
  },
71370
/* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
71371
  {
71372
    { 0, 0, 0, 0 },
71373
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
71374
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1932400 }
71375
  },
71376
/* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
71377
  {
71378
    { 0, 0, 0, 0 },
71379
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
71380
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1933400 }
71381
  },
71382
/* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
71383
  {
71384
    { 0, 0, 0, 0 },
71385
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
71386
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1950400 }
71387
  },
71388
/* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
71389
  {
71390
    { 0, 0, 0, 0 },
71391
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
71392
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1952400 }
71393
  },
71394
/* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
71395
  {
71396
    { 0, 0, 0, 0 },
71397
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
71398
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1953400 }
71399
  },
71400
/* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
71401
  {
71402
    { 0, 0, 0, 0 },
71403
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
71404
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1970400 }
71405
  },
71406
/* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
71407
  {
71408
    { 0, 0, 0, 0 },
71409
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
71410
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1972400 }
71411
  },
71412
/* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
71413
  {
71414
    { 0, 0, 0, 0 },
71415
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
71416
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1973400 }
71417
  },
71418
/* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
71419
  {
71420
    { 0, 0, 0, 0 },
71421
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
71422
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x1938400 }
71423
  },
71424
/* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
71425
  {
71426
    { 0, 0, 0, 0 },
71427
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
71428
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x193a400 }
71429
  },
71430
/* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
71431
  {
71432
    { 0, 0, 0, 0 },
71433
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
71434
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x193b400 }
71435
  },
71436
/* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
71437
  {
71438
    { 0, 0, 0, 0 },
71439
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
71440
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x1958400 }
71441
  },
71442
/* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
71443
  {
71444
    { 0, 0, 0, 0 },
71445
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
71446
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x195a400 }
71447
  },
71448
/* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
71449
  {
71450
    { 0, 0, 0, 0 },
71451
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
71452
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x195b400 }
71453
  },
71454
/* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
71455
  {
71456
    { 0, 0, 0, 0 },
71457
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
71458
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193c400 }
71459
  },
71460
/* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
71461
  {
71462
    { 0, 0, 0, 0 },
71463
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
71464
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193e400 }
71465
  },
71466
/* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
71467
  {
71468
    { 0, 0, 0, 0 },
71469
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
71470
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193f400 }
71471
  },
71472
/* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
71473
  {
71474
    { 0, 0, 0, 0 },
71475
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
71476
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195c400 }
71477
  },
71478
/* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
71479
  {
71480
    { 0, 0, 0, 0 },
71481
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
71482
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195e400 }
71483
  },
71484
/* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
71485
  {
71486
    { 0, 0, 0, 0 },
71487
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
71488
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195f400 }
71489
  },
71490
/* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
71491
  {
71492
    { 0, 0, 0, 0 },
71493
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
71494
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197c400 }
71495
  },
71496
/* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
71497
  {
71498
    { 0, 0, 0, 0 },
71499
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
71500
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197e400 }
71501
  },
71502
/* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
71503
  {
71504
    { 0, 0, 0, 0 },
71505
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
71506
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197f400 }
71507
  },
71508
/* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
71509
  {
71510
    { 0, 0, 0, 0 },
71511
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
71512
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x1978400 }
71513
  },
71514
/* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
71515
  {
71516
    { 0, 0, 0, 0 },
71517
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
71518
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x197a400 }
71519
  },
71520
/* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
71521
  {
71522
    { 0, 0, 0, 0 },
71523
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
71524
    & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x197b400 }
71525
  },
71526
/* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
71527
  {
71528
    { 0, 0, 0, 0 },
71529
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
71530
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a90400 }
71531
  },
71532
/* adc.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
71533
  {
71534
    { 0, 0, 0, 0 },
71535
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
71536
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a92400 }
71537
  },
71538
/* adc.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
71539
  {
71540
    { 0, 0, 0, 0 },
71541
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
71542
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a93400 }
71543
  },
71544
/* adc.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */
71545
  {
71546
    { 0, 0, 0, 0 },
71547
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32RNPREFIXEDHI), 0 } },
71548
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b93400 }
71549
  },
71550
/* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
71551
  {
71552
    { 0, 0, 0, 0 },
71553
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
71554
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a18400 }
71555
  },
71556
/* adc.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
71557
  {
71558
    { 0, 0, 0, 0 },
71559
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
71560
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a1a400 }
71561
  },
71562
/* adc.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
71563
  {
71564
    { 0, 0, 0, 0 },
71565
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
71566
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a1b400 }
71567
  },
71568
/* adc.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */
71569
  {
71570
    { 0, 0, 0, 0 },
71571
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32ANPREFIXEDHI), 0 } },
71572
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b1b400 }
71573
  },
71574
/* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
71575
  {
71576
    { 0, 0, 0, 0 },
71577
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
71578
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a10400 }
71579
  },
71580
/* adc.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
71581
  {
71582
    { 0, 0, 0, 0 },
71583
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
71584
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a12400 }
71585
  },
71586
/* adc.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
71587
  {
71588
    { 0, 0, 0, 0 },
71589
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
71590
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a13400 }
71591
  },
71592
/* adc.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
71593
  {
71594
    { 0, 0, 0, 0 },
71595
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
71596
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b13400 }
71597
  },
71598
/* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
71599
  {
71600
    { 0, 0, 0, 0 },
71601
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
71602
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a30400 }
71603
  },
71604
/* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
71605
  {
71606
    { 0, 0, 0, 0 },
71607
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
71608
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a32400 }
71609
  },
71610
/* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
71611
  {
71612
    { 0, 0, 0, 0 },
71613
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
71614
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a33400 }
71615
  },
71616
/* adc.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
71617
  {
71618
    { 0, 0, 0, 0 },
71619
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
71620
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1b33400 }
71621
  },
71622
/* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
71623
  {
71624
    { 0, 0, 0, 0 },
71625
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
71626
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a50400 }
71627
  },
71628
/* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
71629
  {
71630
    { 0, 0, 0, 0 },
71631
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
71632
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a52400 }
71633
  },
71634
/* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
71635
  {
71636
    { 0, 0, 0, 0 },
71637
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
71638
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a53400 }
71639
  },
71640
/* adc.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
71641
  {
71642
    { 0, 0, 0, 0 },
71643
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
71644
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1b53400 }
71645
  },
71646
/* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
71647
  {
71648
    { 0, 0, 0, 0 },
71649
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
71650
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a70400 }
71651
  },
71652
/* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
71653
  {
71654
    { 0, 0, 0, 0 },
71655
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
71656
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a72400 }
71657
  },
71658
/* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
71659
  {
71660
    { 0, 0, 0, 0 },
71661
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
71662
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a73400 }
71663
  },
71664
/* adc.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
71665
  {
71666
    { 0, 0, 0, 0 },
71667
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
71668
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1b73400 }
71669
  },
71670
/* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
71671
  {
71672
    { 0, 0, 0, 0 },
71673
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
71674
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a38400 }
71675
  },
71676
/* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
71677
  {
71678
    { 0, 0, 0, 0 },
71679
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
71680
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a3a400 }
71681
  },
71682
/* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
71683
  {
71684
    { 0, 0, 0, 0 },
71685
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
71686
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a3b400 }
71687
  },
71688
/* adc.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
71689
  {
71690
    { 0, 0, 0, 0 },
71691
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
71692
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1b3b400 }
71693
  },
71694
/* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
71695
  {
71696
    { 0, 0, 0, 0 },
71697
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
71698
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a58400 }
71699
  },
71700
/* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
71701
  {
71702
    { 0, 0, 0, 0 },
71703
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
71704
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a5a400 }
71705
  },
71706
/* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
71707
  {
71708
    { 0, 0, 0, 0 },
71709
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
71710
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a5b400 }
71711
  },
71712
/* adc.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
71713
  {
71714
    { 0, 0, 0, 0 },
71715
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
71716
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1b5b400 }
71717
  },
71718
/* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
71719
  {
71720
    { 0, 0, 0, 0 },
71721
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
71722
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3c400 }
71723
  },
71724
/* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
71725
  {
71726
    { 0, 0, 0, 0 },
71727
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
71728
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3e400 }
71729
  },
71730
/* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
71731
  {
71732
    { 0, 0, 0, 0 },
71733
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
71734
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3f400 }
71735
  },
71736
/* adc.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
71737
  {
71738
    { 0, 0, 0, 0 },
71739
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
71740
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1b3f400 }
71741
  },
71742
/* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
71743
  {
71744
    { 0, 0, 0, 0 },
71745
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
71746
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5c400 }
71747
  },
71748
/* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
71749
  {
71750
    { 0, 0, 0, 0 },
71751
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
71752
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5e400 }
71753
  },
71754
/* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
71755
  {
71756
    { 0, 0, 0, 0 },
71757
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
71758
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5f400 }
71759
  },
71760
/* adc.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
71761
  {
71762
    { 0, 0, 0, 0 },
71763
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
71764
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1b5f400 }
71765
  },
71766
/* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
71767
  {
71768
    { 0, 0, 0, 0 },
71769
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
71770
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7c400 }
71771
  },
71772
/* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
71773
  {
71774
    { 0, 0, 0, 0 },
71775
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), 0 } },
71776
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7e400 }
71777
  },
71778
/* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
71779
  {
71780
    { 0, 0, 0, 0 },
71781
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), 0 } },
71782
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7f400 }
71783
  },
71784
/* adc.w${X} ${Dsp-24-u16},${Dsp-40-u16} */
71785
  {
71786
    { 0, 0, 0, 0 },
71787
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), 0 } },
71788
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1b7f400 }
71789
  },
71790
/* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
71791
  {
71792
    { 0, 0, 0, 0 },
71793
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
71794
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a78400 }
71795
  },
71796
/* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
71797
  {
71798
    { 0, 0, 0, 0 },
71799
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), 0 } },
71800
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a7a400 }
71801
  },
71802
/* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
71803
  {
71804
    { 0, 0, 0, 0 },
71805
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), 0 } },
71806
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a7b400 }
71807
  },
71808
/* adc.w${X} ${Dsp-24-u16},${Dsp-40-u24} */
71809
  {
71810
    { 0, 0, 0, 0 },
71811
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), 0 } },
71812
    & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1b7b400 }
71813
  },
71814
/* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
71815
  {
71816
    { 0, 0, 0, 0 },
71817
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
71818
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b90400 }
71819
  },
71820
/* adc.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */
71821
  {
71822
    { 0, 0, 0, 0 },
71823
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32RNPREFIXEDHI), 0 } },
71824
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b92400 }
71825
  },
71826
/* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
71827
  {
71828
    { 0, 0, 0, 0 },
71829
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
71830
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b18400 }
71831
  },
71832
/* adc.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */
71833
  {
71834
    { 0, 0, 0, 0 },
71835
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32ANPREFIXEDHI), 0 } },
71836
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b1a400 }
71837
  },
71838
/* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
71839
  {
71840
    { 0, 0, 0, 0 },
71841
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
71842
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b10400 }
71843
  },
71844
/* adc.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
71845
  {
71846
    { 0, 0, 0, 0 },
71847
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
71848
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b12400 }
71849
  },
71850
/* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
71851
  {
71852
    { 0, 0, 0, 0 },
71853
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
71854
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b30400 }
71855
  },
71856
/* adc.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
71857
  {
71858
    { 0, 0, 0, 0 },
71859
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
71860
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b32400 }
71861
  },
71862
/* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
71863
  {
71864
    { 0, 0, 0, 0 },
71865
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
71866
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b50400 }
71867
  },
71868
/* adc.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
71869
  {
71870
    { 0, 0, 0, 0 },
71871
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
71872
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b52400 }
71873
  },
71874
/* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
71875
  {
71876
    { 0, 0, 0, 0 },
71877
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
71878
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b70400 }
71879
  },
71880
/* adc.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
71881
  {
71882
    { 0, 0, 0, 0 },
71883
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
71884
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b72400 }
71885
  },
71886
/* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
71887
  {
71888
    { 0, 0, 0, 0 },
71889
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
71890
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b38400 }
71891
  },
71892
/* adc.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
71893
  {
71894
    { 0, 0, 0, 0 },
71895
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
71896
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b3a400 }
71897
  },
71898
/* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
71899
  {
71900
    { 0, 0, 0, 0 },
71901
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
71902
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b58400 }
71903
  },
71904
/* adc.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
71905
  {
71906
    { 0, 0, 0, 0 },
71907
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
71908
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b5a400 }
71909
  },
71910
/* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
71911
  {
71912
    { 0, 0, 0, 0 },
71913
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
71914
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b3c400 }
71915
  },
71916
/* adc.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
71917
  {
71918
    { 0, 0, 0, 0 },
71919
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
71920
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b3e400 }
71921
  },
71922
/* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
71923
  {
71924
    { 0, 0, 0, 0 },
71925
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
71926
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b5c400 }
71927
  },
71928
/* adc.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
71929
  {
71930
    { 0, 0, 0, 0 },
71931
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
71932
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b5e400 }
71933
  },
71934
/* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
71935
  {
71936
    { 0, 0, 0, 0 },
71937
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), 0 } },
71938
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_absolute_Prefixed_HI, { 0x1b7c400 }
71939
  },
71940
/* adc.w${X} ${Dsp-24-u24},${Dsp-48-u16} */
71941
  {
71942
    { 0, 0, 0, 0 },
71943
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), 0 } },
71944
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_absolute_Prefixed_HI, { 0x1b7e400 }
71945
  },
71946
/* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
71947
  {
71948
    { 0, 0, 0, 0 },
71949
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), 0 } },
71950
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_24_absolute_Prefixed_HI, { 0x1b78400 }
71951
  },
71952
/* adc.w${X} ${Dsp-24-u24},${Dsp-48-u24} */
71953
  {
71954
    { 0, 0, 0, 0 },
71955
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), 0 } },
71956
    & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_24_absolute_Prefixed_HI, { 0x1b7a400 }
71957
  },
71958
/* adc.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */
71959
  {
71960
    { 0, 0, 0, 0 },
71961
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DST32RNPREFIXEDHI), 0 } },
71962
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1c904 }
71963
  },
71964
/* adc.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */
71965
  {
71966
    { 0, 0, 0, 0 },
71967
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DST32RNPREFIXEDHI), 0 } },
71968
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x18924 }
71969
  },
71970
/* adc.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */
71971
  {
71972
    { 0, 0, 0, 0 },
71973
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } },
71974
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x18904 }
71975
  },
71976
/* adc.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */
71977
  {
71978
    { 0, 0, 0, 0 },
71979
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DST32ANPREFIXEDHI), 0 } },
71980
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1c184 }
71981
  },
71982
/* adc.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */
71983
  {
71984
    { 0, 0, 0, 0 },
71985
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DST32ANPREFIXEDHI), 0 } },
71986
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x181a4 }
71987
  },
71988
/* adc.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */
71989
  {
71990
    { 0, 0, 0, 0 },
71991
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } },
71992
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x18184 }
71993
  },
71994
/* adc.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */
71995
  {
71996
    { 0, 0, 0, 0 },
71997
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
71998
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1c104 }
71999
  },
72000
/* adc.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */
72001
  {
72002
    { 0, 0, 0, 0 },
72003
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
72004
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x18124 }
72005
  },
72006
/* adc.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
72007
  {
72008
    { 0, 0, 0, 0 },
72009
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
72010
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x18104 }
72011
  },
72012
/* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
72013
  {
72014
    { 0, 0, 0, 0 },
72015
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
72016
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1c30400 }
72017
  },
72018
/* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
72019
  {
72020
    { 0, 0, 0, 0 },
72021
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
72022
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1832400 }
72023
  },
72024
/* adc.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
72025
  {
72026
    { 0, 0, 0, 0 },
72027
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
72028
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1830400 }
72029
  },
72030
/* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
72031
  {
72032
    { 0, 0, 0, 0 },
72033
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
72034
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1c50400 }
72035
  },
72036
/* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
72037
  {
72038
    { 0, 0, 0, 0 },
72039
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
72040
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1852400 }
72041
  },
72042
/* adc.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
72043
  {
72044
    { 0, 0, 0, 0 },
72045
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
72046
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1850400 }
72047
  },
72048
/* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
72049
  {
72050
    { 0, 0, 0, 0 },
72051
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
72052
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1c70400 }
72053
  },
72054
/* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
72055
  {
72056
    { 0, 0, 0, 0 },
72057
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
72058
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1872400 }
72059
  },
72060
/* adc.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
72061
  {
72062
    { 0, 0, 0, 0 },
72063
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
72064
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1870400 }
72065
  },
72066
/* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */
72067
  {
72068
    { 0, 0, 0, 0 },
72069
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
72070
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1c38400 }
72071
  },
72072
/* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */
72073
  {
72074
    { 0, 0, 0, 0 },
72075
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
72076
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x183a400 }
72077
  },
72078
/* adc.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
72079
  {
72080
    { 0, 0, 0, 0 },
72081
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
72082
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1838400 }
72083
  },
72084
/* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */
72085
  {
72086
    { 0, 0, 0, 0 },
72087
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
72088
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1c58400 }
72089
  },
72090
/* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */
72091
  {
72092
    { 0, 0, 0, 0 },
72093
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
72094
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x185a400 }
72095
  },
72096
/* adc.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
72097
  {
72098
    { 0, 0, 0, 0 },
72099
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
72100
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1858400 }
72101
  },
72102
/* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */
72103
  {
72104
    { 0, 0, 0, 0 },
72105
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
72106
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x1c3c400 }
72107
  },
72108
/* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */
72109
  {
72110
    { 0, 0, 0, 0 },
72111
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
72112
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x183e400 }
72113
  },
72114
/* adc.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
72115
  {
72116
    { 0, 0, 0, 0 },
72117
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
72118
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x183c400 }
72119
  },
72120
/* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */
72121
  {
72122
    { 0, 0, 0, 0 },
72123
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
72124
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x1c5c400 }
72125
  },
72126
/* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */
72127
  {
72128
    { 0, 0, 0, 0 },
72129
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
72130
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x185e400 }
72131
  },
72132
/* adc.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
72133
  {
72134
    { 0, 0, 0, 0 },
72135
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
72136
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x185c400 }
72137
  },
72138
/* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */
72139
  {
72140
    { 0, 0, 0, 0 },
72141
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), 0 } },
72142
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x1c7c400 }
72143
  },
72144
/* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */
72145
  {
72146
    { 0, 0, 0, 0 },
72147
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), 0 } },
72148
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x187e400 }
72149
  },
72150
/* adc.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */
72151
  {
72152
    { 0, 0, 0, 0 },
72153
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
72154
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x187c400 }
72155
  },
72156
/* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */
72157
  {
72158
    { 0, 0, 0, 0 },
72159
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U24), 0 } },
72160
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x1c78400 }
72161
  },
72162
/* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */
72163
  {
72164
    { 0, 0, 0, 0 },
72165
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U24), 0 } },
72166
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x187a400 }
72167
  },
72168
/* adc.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */
72169
  {
72170
    { 0, 0, 0, 0 },
72171
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
72172
    & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x1878400 }
72173
  },
72174
/* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
72175
  {
72176
    { 0, 0, 0, 0 },
72177
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
72178
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1980400 }
72179
  },
72180
/* adc.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */
72181
  {
72182
    { 0, 0, 0, 0 },
72183
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
72184
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1982400 }
72185
  },
72186
/* adc.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */
72187
  {
72188
    { 0, 0, 0, 0 },
72189
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
72190
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1983400 }
72191
  },
72192
/* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
72193
  {
72194
    { 0, 0, 0, 0 },
72195
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
72196
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1908400 }
72197
  },
72198
/* adc.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */
72199
  {
72200
    { 0, 0, 0, 0 },
72201
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
72202
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x190a400 }
72203
  },
72204
/* adc.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */
72205
  {
72206
    { 0, 0, 0, 0 },
72207
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
72208
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x190b400 }
72209
  },
72210
/* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
72211
  {
72212
    { 0, 0, 0, 0 },
72213
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
72214
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1900400 }
72215
  },
72216
/* adc.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
72217
  {
72218
    { 0, 0, 0, 0 },
72219
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
72220
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1902400 }
72221
  },
72222
/* adc.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
72223
  {
72224
    { 0, 0, 0, 0 },
72225
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
72226
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1903400 }
72227
  },
72228
/* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
72229
  {
72230
    { 0, 0, 0, 0 },
72231
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
72232
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1920400 }
72233
  },
72234
/* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
72235
  {
72236
    { 0, 0, 0, 0 },
72237
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
72238
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1922400 }
72239
  },
72240
/* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
72241
  {
72242
    { 0, 0, 0, 0 },
72243
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
72244
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1923400 }
72245
  },
72246
/* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
72247
  {
72248
    { 0, 0, 0, 0 },
72249
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
72250
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1940400 }
72251
  },
72252
/* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
72253
  {
72254
    { 0, 0, 0, 0 },
72255
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
72256
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1942400 }
72257
  },
72258
/* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
72259
  {
72260
    { 0, 0, 0, 0 },
72261
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
72262
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1943400 }
72263
  },
72264
/* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
72265
  {
72266
    { 0, 0, 0, 0 },
72267
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
72268
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1960400 }
72269
  },
72270
/* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
72271
  {
72272
    { 0, 0, 0, 0 },
72273
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
72274
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1962400 }
72275
  },
72276
/* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
72277
  {
72278
    { 0, 0, 0, 0 },
72279
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
72280
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1963400 }
72281
  },
72282
/* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
72283
  {
72284
    { 0, 0, 0, 0 },
72285
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
72286
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x1928400 }
72287
  },
72288
/* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
72289
  {
72290
    { 0, 0, 0, 0 },
72291
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
72292
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x192a400 }
72293
  },
72294
/* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
72295
  {
72296
    { 0, 0, 0, 0 },
72297
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
72298
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x192b400 }
72299
  },
72300
/* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
72301
  {
72302
    { 0, 0, 0, 0 },
72303
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
72304
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x1948400 }
72305
  },
72306
/* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
72307
  {
72308
    { 0, 0, 0, 0 },
72309
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
72310
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x194a400 }
72311
  },
72312
/* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
72313
  {
72314
    { 0, 0, 0, 0 },
72315
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
72316
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x194b400 }
72317
  },
72318
/* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
72319
  {
72320
    { 0, 0, 0, 0 },
72321
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
72322
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192c400 }
72323
  },
72324
/* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
72325
  {
72326
    { 0, 0, 0, 0 },
72327
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
72328
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192e400 }
72329
  },
72330
/* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
72331
  {
72332
    { 0, 0, 0, 0 },
72333
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
72334
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192f400 }
72335
  },
72336
/* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
72337
  {
72338
    { 0, 0, 0, 0 },
72339
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
72340
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194c400 }
72341
  },
72342
/* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
72343
  {
72344
    { 0, 0, 0, 0 },
72345
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
72346
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194e400 }
72347
  },
72348
/* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
72349
  {
72350
    { 0, 0, 0, 0 },
72351
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
72352
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194f400 }
72353
  },
72354
/* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
72355
  {
72356
    { 0, 0, 0, 0 },
72357
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
72358
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196c400 }
72359
  },
72360
/* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
72361
  {
72362
    { 0, 0, 0, 0 },
72363
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
72364
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196e400 }
72365
  },
72366
/* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
72367
  {
72368
    { 0, 0, 0, 0 },
72369
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
72370
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196f400 }
72371
  },
72372
/* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
72373
  {
72374
    { 0, 0, 0, 0 },
72375
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
72376
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x1968400 }
72377
  },
72378
/* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
72379
  {
72380
    { 0, 0, 0, 0 },
72381
    { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
72382
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x196a400 }
72383
  },
72384
/* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
72385
  {
72386
    { 0, 0, 0, 0 },
72387
    { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
72388
    & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x196b400 }
72389
  },
72390
/* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
72391
  {
72392
    { 0, 0, 0, 0 },
72393
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
72394
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a80400 }
72395
  },
72396
/* adc.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */
72397
  {
72398
    { 0, 0, 0, 0 },
72399
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
72400
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a82400 }
72401
  },
72402
/* adc.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */
72403
  {
72404
    { 0, 0, 0, 0 },
72405
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
72406
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a83400 }
72407
  },
72408
/* adc.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */
72409
  {
72410
    { 0, 0, 0, 0 },
72411
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32RNPREFIXEDQI), 0 } },
72412
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b83400 }
72413
  },
72414
/* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
72415
  {
72416
    { 0, 0, 0, 0 },
72417
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
72418
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a08400 }
72419
  },
72420
/* adc.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */
72421
  {
72422
    { 0, 0, 0, 0 },
72423
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
72424
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a0a400 }
72425
  },
72426
/* adc.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */
72427
  {
72428
    { 0, 0, 0, 0 },
72429
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
72430
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a0b400 }
72431
  },
72432
/* adc.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */
72433
  {
72434
    { 0, 0, 0, 0 },
72435
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32ANPREFIXEDQI), 0 } },
72436
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b0b400 }
72437
  },
72438
/* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
72439
  {
72440
    { 0, 0, 0, 0 },
72441
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
72442
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a00400 }
72443
  },
72444
/* adc.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
72445
  {
72446
    { 0, 0, 0, 0 },
72447
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
72448
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a02400 }
72449
  },
72450
/* adc.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
72451
  {
72452
    { 0, 0, 0, 0 },
72453
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
72454
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a03400 }
72455
  },
72456
/* adc.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
72457
  {
72458
    { 0, 0, 0, 0 },
72459
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
72460
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b03400 }
72461
  },
72462
/* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
72463
  {
72464
    { 0, 0, 0, 0 },
72465
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
72466
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a20400 }
72467
  },
72468
/* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
72469
  {
72470
    { 0, 0, 0, 0 },
72471
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
72472
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a22400 }
72473
  },
72474
/* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
72475
  {
72476
    { 0, 0, 0, 0 },
72477
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
72478
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a23400 }
72479
  },
72480
/* adc.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
72481
  {
72482
    { 0, 0, 0, 0 },
72483
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
72484
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1b23400 }
72485
  },
72486
/* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
72487
  {
72488
    { 0, 0, 0, 0 },
72489
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
72490
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a40400 }
72491
  },
72492
/* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
72493
  {
72494
    { 0, 0, 0, 0 },
72495
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
72496
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a42400 }
72497
  },
72498
/* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
72499
  {
72500
    { 0, 0, 0, 0 },
72501
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
72502
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a43400 }
72503
  },
72504
/* adc.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
72505
  {
72506
    { 0, 0, 0, 0 },
72507
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
72508
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1b43400 }
72509
  },
72510
/* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
72511
  {
72512
    { 0, 0, 0, 0 },
72513
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
72514
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a60400 }
72515
  },
72516
/* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
72517
  {
72518
    { 0, 0, 0, 0 },
72519
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
72520
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a62400 }
72521
  },
72522
/* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
72523
  {
72524
    { 0, 0, 0, 0 },
72525
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
72526
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a63400 }
72527
  },
72528
/* adc.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
72529
  {
72530
    { 0, 0, 0, 0 },
72531
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
72532
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1b63400 }
72533
  },
72534
/* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
72535
  {
72536
    { 0, 0, 0, 0 },
72537
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
72538
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a28400 }
72539
  },
72540
/* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
72541
  {
72542
    { 0, 0, 0, 0 },
72543
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
72544
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a2a400 }
72545
  },
72546
/* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
72547
  {
72548
    { 0, 0, 0, 0 },
72549
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
72550
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a2b400 }
72551
  },
72552
/* adc.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
72553
  {
72554
    { 0, 0, 0, 0 },
72555
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
72556
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1b2b400 }
72557
  },
72558
/* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
72559
  {
72560
    { 0, 0, 0, 0 },
72561
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
72562
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a48400 }
72563
  },
72564
/* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
72565
  {
72566
    { 0, 0, 0, 0 },
72567
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
72568
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a4a400 }
72569
  },
72570
/* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
72571
  {
72572
    { 0, 0, 0, 0 },
72573
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
72574
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a4b400 }
72575
  },
72576
/* adc.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
72577
  {
72578
    { 0, 0, 0, 0 },
72579
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
72580
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1b4b400 }
72581
  },
72582
/* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
72583
  {
72584
    { 0, 0, 0, 0 },
72585
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
72586
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2c400 }
72587
  },
72588
/* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
72589
  {
72590
    { 0, 0, 0, 0 },
72591
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
72592
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2e400 }
72593
  },
72594
/* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
72595
  {
72596
    { 0, 0, 0, 0 },
72597
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
72598
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2f400 }
72599
  },
72600
/* adc.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
72601
  {
72602
    { 0, 0, 0, 0 },
72603
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
72604
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1b2f400 }
72605
  },
72606
/* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
72607
  {
72608
    { 0, 0, 0, 0 },
72609
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
72610
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4c400 }
72611
  },
72612
/* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
72613
  {
72614
    { 0, 0, 0, 0 },
72615
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
72616
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4e400 }
72617
  },
72618
/* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
72619
  {
72620
    { 0, 0, 0, 0 },
72621
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
72622
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4f400 }
72623
  },
72624
/* adc.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
72625
  {
72626
    { 0, 0, 0, 0 },
72627
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
72628
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1b4f400 }
72629
  },
72630
/* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
72631
  {
72632
    { 0, 0, 0, 0 },
72633
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
72634
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6c400 }
72635
  },
72636
/* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
72637
  {
72638
    { 0, 0, 0, 0 },
72639
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), 0 } },
72640
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6e400 }
72641
  },
72642
/* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
72643
  {
72644
    { 0, 0, 0, 0 },
72645
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), 0 } },
72646
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6f400 }
72647
  },
72648
/* adc.b${X} ${Dsp-24-u16},${Dsp-40-u16} */
72649
  {
72650
    { 0, 0, 0, 0 },
72651
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), 0 } },
72652
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1b6f400 }
72653
  },
72654
/* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
72655
  {
72656
    { 0, 0, 0, 0 },
72657
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
72658
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a68400 }
72659
  },
72660
/* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
72661
  {
72662
    { 0, 0, 0, 0 },
72663
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), 0 } },
72664
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a6a400 }
72665
  },
72666
/* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
72667
  {
72668
    { 0, 0, 0, 0 },
72669
    { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), 0 } },
72670
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a6b400 }
72671
  },
72672
/* adc.b${X} ${Dsp-24-u16},${Dsp-40-u24} */
72673
  {
72674
    { 0, 0, 0, 0 },
72675
    { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), 0 } },
72676
    & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1b6b400 }
72677
  },
72678
/* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
72679
  {
72680
    { 0, 0, 0, 0 },
72681
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
72682
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b80400 }
72683
  },
72684
/* adc.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */
72685
  {
72686
    { 0, 0, 0, 0 },
72687
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32RNPREFIXEDQI), 0 } },
72688
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b82400 }
72689
  },
72690
/* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
72691
  {
72692
    { 0, 0, 0, 0 },
72693
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
72694
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b08400 }
72695
  },
72696
/* adc.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */
72697
  {
72698
    { 0, 0, 0, 0 },
72699
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32ANPREFIXEDQI), 0 } },
72700
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b0a400 }
72701
  },
72702
/* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
72703
  {
72704
    { 0, 0, 0, 0 },
72705
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
72706
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b00400 }
72707
  },
72708
/* adc.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
72709
  {
72710
    { 0, 0, 0, 0 },
72711
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
72712
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b02400 }
72713
  },
72714
/* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
72715
  {
72716
    { 0, 0, 0, 0 },
72717
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
72718
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_An_relative_Prefixed_QI, { 0x1b20400 }
72719
  },
72720
/* adc.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
72721
  {
72722
    { 0, 0, 0, 0 },
72723
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
72724
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_An_relative_Prefixed_QI, { 0x1b22400 }
72725
  },
72726
/* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
72727
  {
72728
    { 0, 0, 0, 0 },
72729
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
72730
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_An_relative_Prefixed_QI, { 0x1b40400 }
72731
  },
72732
/* adc.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
72733
  {
72734
    { 0, 0, 0, 0 },
72735
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
72736
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_An_relative_Prefixed_QI, { 0x1b42400 }
72737
  },
72738
/* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
72739
  {
72740
    { 0, 0, 0, 0 },
72741
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
72742
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_An_relative_Prefixed_QI, { 0x1b60400 }
72743
  },
72744
/* adc.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
72745
  {
72746
    { 0, 0, 0, 0 },
72747
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
72748
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_An_relative_Prefixed_QI, { 0x1b62400 }
72749
  },
72750
/* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
72751
  {
72752
    { 0, 0, 0, 0 },
72753
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
72754
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_QI, { 0x1b28400 }
72755
  },
72756
/* adc.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
72757
  {
72758
    { 0, 0, 0, 0 },
72759
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } },
72760
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_QI, { 0x1b2a400 }
72761
  },
72762
/* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
72763
  {
72764
    { 0, 0, 0, 0 },
72765
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
72766
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_QI, { 0x1b48400 }
72767
  },
72768
/* adc.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
72769
  {
72770
    { 0, 0, 0, 0 },
72771
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } },
72772
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_QI, { 0x1b4a400 }
72773
  },
72774
/* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
72775
  {
72776
    { 0, 0, 0, 0 },
72777
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
72778
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_QI, { 0x1b2c400 }
72779
  },
72780
/* adc.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
72781
  {
72782
    { 0, 0, 0, 0 },
72783
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } },
72784
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_QI, { 0x1b2e400 }
72785
  },
72786
/* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
72787
  {
72788
    { 0, 0, 0, 0 },
72789
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
72790
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_QI, { 0x1b4c400 }
72791
  },
72792
/* adc.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
72793
  {
72794
    { 0, 0, 0, 0 },
72795
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } },
72796
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_QI, { 0x1b4e400 }
72797
  },
72798
/* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
72799
  {
72800
    { 0, 0, 0, 0 },
72801
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), 0 } },
72802
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_absolute_Prefixed_QI, { 0x1b6c400 }
72803
  },
72804
/* adc.b${X} ${Dsp-24-u24},${Dsp-48-u16} */
72805
  {
72806
    { 0, 0, 0, 0 },
72807
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), 0 } },
72808
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_absolute_Prefixed_QI, { 0x1b6e400 }
72809
  },
72810
/* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
72811
  {
72812
    { 0, 0, 0, 0 },
72813
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), 0 } },
72814
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_absolute_Prefixed_QI, { 0x1b68400 }
72815
  },
72816
/* adc.b${X} ${Dsp-24-u24},${Dsp-48-u24} */
72817
  {
72818
    { 0, 0, 0, 0 },
72819
    { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), 0 } },
72820
    & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_absolute_Prefixed_QI, { 0x1b6a400 }
72821
  },
72822
/* adc.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */
72823
  {
72824
    { 0, 0, 0, 0 },
72825
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32RNPREFIXEDQI), 0 } },
72826
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1c804 }
72827
  },
72828
/* adc.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */
72829
  {
72830
    { 0, 0, 0, 0 },
72831
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DST32RNPREFIXEDQI), 0 } },
72832
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x18824 }
72833
  },
72834
/* adc.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */
72835
  {
72836
    { 0, 0, 0, 0 },
72837
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } },
72838
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x18804 }
72839
  },
72840
/* adc.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */
72841
  {
72842
    { 0, 0, 0, 0 },
72843
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32ANPREFIXEDQI), 0 } },
72844
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1c084 }
72845
  },
72846
/* adc.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */
72847
  {
72848
    { 0, 0, 0, 0 },
72849
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DST32ANPREFIXEDQI), 0 } },
72850
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x180a4 }
72851
  },
72852
/* adc.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */
72853
  {
72854
    { 0, 0, 0, 0 },
72855
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } },
72856
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x18084 }
72857
  },
72858
/* adc.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
72859
  {
72860
    { 0, 0, 0, 0 },
72861
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
72862
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1c004 }
72863
  },
72864
/* adc.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */
72865
  {
72866
    { 0, 0, 0, 0 },
72867
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
72868
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x18024 }
72869
  },
72870
/* adc.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
72871
  {
72872
    { 0, 0, 0, 0 },
72873
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
72874
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x18004 }
72875
  },
72876
/* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
72877
  {
72878
    { 0, 0, 0, 0 },
72879
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
72880
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1c20400 }
72881
  },
72882
/* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
72883
  {
72884
    { 0, 0, 0, 0 },
72885
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
72886
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1822400 }
72887
  },
72888
/* adc.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
72889
  {
72890
    { 0, 0, 0, 0 },
72891
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
72892
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1820400 }
72893
  },
72894
/* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
72895
  {
72896
    { 0, 0, 0, 0 },
72897
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
72898
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1c40400 }
72899
  },
72900
/* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
72901
  {
72902
    { 0, 0, 0, 0 },
72903
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
72904
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1842400 }
72905
  },
72906
/* adc.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
72907
  {
72908
    { 0, 0, 0, 0 },
72909
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
72910
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1840400 }
72911
  },
72912
/* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
72913
  {
72914
    { 0, 0, 0, 0 },
72915
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
72916
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1c60400 }
72917
  },
72918
/* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
72919
  {
72920
    { 0, 0, 0, 0 },
72921
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
72922
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1862400 }
72923
  },
72924
/* adc.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
72925
  {
72926
    { 0, 0, 0, 0 },
72927
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
72928
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1860400 }
72929
  },
72930
/* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
72931
  {
72932
    { 0, 0, 0, 0 },
72933
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
72934
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x1c28400 }
72935
  },
72936
/* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */
72937
  {
72938
    { 0, 0, 0, 0 },
72939
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
72940
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x182a400 }
72941
  },
72942
/* adc.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
72943
  {
72944
    { 0, 0, 0, 0 },
72945
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
72946
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x1828400 }
72947
  },
72948
/* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
72949
  {
72950
    { 0, 0, 0, 0 },
72951
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
72952
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x1c48400 }
72953
  },
72954
/* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */
72955
  {
72956
    { 0, 0, 0, 0 },
72957
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
72958
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x184a400 }
72959
  },
72960
/* adc.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
72961
  {
72962
    { 0, 0, 0, 0 },
72963
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
72964
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x1848400 }
72965
  },
72966
/* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
72967
  {
72968
    { 0, 0, 0, 0 },
72969
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
72970
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x1c2c400 }
72971
  },
72972
/* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */
72973
  {
72974
    { 0, 0, 0, 0 },
72975
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
72976
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x182e400 }
72977
  },
72978
/* adc.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
72979
  {
72980
    { 0, 0, 0, 0 },
72981
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
72982
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x182c400 }
72983
  },
72984
/* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
72985
  {
72986
    { 0, 0, 0, 0 },
72987
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
72988
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x1c4c400 }
72989
  },
72990
/* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */
72991
  {
72992
    { 0, 0, 0, 0 },
72993
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
72994
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x184e400 }
72995
  },
72996
/* adc.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
72997
  {
72998
    { 0, 0, 0, 0 },
72999
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
73000
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x184c400 }
73001
  },
73002
/* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */
73003
  {
73004
    { 0, 0, 0, 0 },
73005
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), 0 } },
73006
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x1c6c400 }
73007
  },
73008
/* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */
73009
  {
73010
    { 0, 0, 0, 0 },
73011
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), 0 } },
73012
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x186e400 }
73013
  },
73014
/* adc.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */
73015
  {
73016
    { 0, 0, 0, 0 },
73017
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
73018
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x186c400 }
73019
  },
73020
/* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */
73021
  {
73022
    { 0, 0, 0, 0 },
73023
    { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), 0 } },
73024
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x1c68400 }
73025
  },
73026
/* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */
73027
  {
73028
    { 0, 0, 0, 0 },
73029
    { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U24), 0 } },
73030
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x186a400 }
73031
  },
73032
/* adc.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */
73033
  {
73034
    { 0, 0, 0, 0 },
73035
    { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
73036
    & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x1868400 }
73037
  },
73038
/* adc.w${X} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
73039
  {
73040
    { 0, 0, 0, 0 },
73041
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } },
73042
    & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_Rn_direct_HI, { 0xb18000 }
73043
  },
73044
/* adc.w${X} ${Dsp-16-u8}[sb],$Dst16RnHI */
73045
  {
73046
    { 0, 0, 0, 0 },
73047
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } },
73048
    & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_Rn_direct_HI, { 0xb1a000 }
73049
  },
73050
/* adc.w${X} ${Dsp-16-s8}[fb],$Dst16RnHI */
73051
  {
73052
    { 0, 0, 0, 0 },
73053
    { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNHI), 0 } },
73054
    & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_Rn_direct_HI, { 0xb1b000 }
73055
  },
73056
/* adc.w${X} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
73057
  {
73058
    { 0, 0, 0, 0 },
73059
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } },
73060
    & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_direct_HI, { 0xb18400 }
73061
  },
73062
/* adc.w${X} ${Dsp-16-u8}[sb],$Dst16AnHI */
73063
  {
73064
    { 0, 0, 0, 0 },
73065
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } },
73066
    & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_direct_HI, { 0xb1a400 }
73067
  },
73068
/* adc.w${X} ${Dsp-16-s8}[fb],$Dst16AnHI */
73069
  {
73070
    { 0, 0, 0, 0 },
73071
    { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANHI), 0 } },
73072
    & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_direct_HI, { 0xb1b400 }
73073
  },
73074
/* adc.w${X} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
73075
  {
73076
    { 0, 0, 0, 0 },
73077
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
73078
    & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_indirect_HI, { 0xb18600 }
73079
  },
73080
/* adc.w${X} ${Dsp-16-u8}[sb],[$Dst16An] */
73081
  {
73082
    { 0, 0, 0, 0 },
73083
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
73084
    & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_indirect_HI, { 0xb1a600 }
73085
  },
73086
/* adc.w${X} ${Dsp-16-s8}[fb],[$Dst16An] */
73087
  {
73088
    { 0, 0, 0, 0 },
73089
    { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
73090
    & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_indirect_HI, { 0xb1b600 }
73091
  },
73092
/* adc.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
73093
  {
73094
    { 0, 0, 0, 0 },
73095
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
73096
    & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_An_relative_HI, { 0xb1880000 }
73097
  },
73098
/* adc.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
73099
  {
73100
    { 0, 0, 0, 0 },
73101
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
73102
    & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_An_relative_HI, { 0xb1a80000 }
73103
  },
73104
/* adc.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
73105
  {
73106
    { 0, 0, 0, 0 },
73107
    { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
73108
    & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_An_relative_HI, { 0xb1b80000 }
73109
  },
73110
/* adc.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
73111
  {
73112
    { 0, 0, 0, 0 },
73113
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
73114
    & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_An_relative_HI, { 0xb18c0000 }
73115
  },
73116
/* adc.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
73117
  {
73118
    { 0, 0, 0, 0 },
73119
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
73120
    & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_An_relative_HI, { 0xb1ac0000 }
73121
  },
73122
/* adc.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
73123
  {
73124
    { 0, 0, 0, 0 },
73125
    { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
73126
    & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_An_relative_HI, { 0xb1bc0000 }
73127
  },
73128
/* adc.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
73129
  {
73130
    { 0, 0, 0, 0 },
73131
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
73132
    & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_SB_relative_HI, { 0xb18a0000 }
73133
  },
73134
/* adc.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
73135
  {
73136
    { 0, 0, 0, 0 },
73137
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
73138
    & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_SB_relative_HI, { 0xb1aa0000 }
73139
  },
73140
/* adc.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
73141
  {
73142
    { 0, 0, 0, 0 },
73143
    { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
73144
    & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_SB_relative_HI, { 0xb1ba0000 }
73145
  },
73146
/* adc.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
73147
  {
73148
    { 0, 0, 0, 0 },
73149
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
73150
    & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_SB_relative_HI, { 0xb18e0000 }
73151
  },
73152
/* adc.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
73153
  {
73154
    { 0, 0, 0, 0 },
73155
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
73156
    & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_SB_relative_HI, { 0xb1ae0000 }
73157
  },
73158
/* adc.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
73159
  {
73160
    { 0, 0, 0, 0 },
73161
    { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
73162
    & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_SB_relative_HI, { 0xb1be0000 }
73163
  },
73164
/* adc.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
73165
  {
73166
    { 0, 0, 0, 0 },
73167
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
73168
    & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_FB_relative_HI, { 0xb18b0000 }
73169
  },
73170
/* adc.w${X} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
73171
  {
73172
    { 0, 0, 0, 0 },
73173
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
73174
    & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_FB_relative_HI, { 0xb1ab0000 }
73175
  },
73176
/* adc.w${X} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
73177
  {
73178
    { 0, 0, 0, 0 },
73179
    { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
73180
    & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_FB_relative_HI, { 0xb1bb0000 }
73181
  },
73182
/* adc.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
73183
  {
73184
    { 0, 0, 0, 0 },
73185
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } },
73186
    & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_absolute_HI, { 0xb18f0000 }
73187
  },
73188
/* adc.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
73189
  {
73190
    { 0, 0, 0, 0 },
73191
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
73192
    & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_absolute_HI, { 0xb1af0000 }
73193
  },
73194
/* adc.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
73195
  {
73196
    { 0, 0, 0, 0 },
73197
    { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
73198
    & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_absolute_HI, { 0xb1bf0000 }
73199
  },
73200
/* adc.w${X} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
73201
  {
73202
    { 0, 0, 0, 0 },
73203
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } },
73204
    & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_Rn_direct_HI, { 0xb1c00000 }
73205
  },
73206
/* adc.w${X} ${Dsp-16-u16}[sb],$Dst16RnHI */
73207
  {
73208
    { 0, 0, 0, 0 },
73209
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } },
73210
    & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_Rn_direct_HI, { 0xb1e00000 }
73211
  },
73212
/* adc.w${X} ${Dsp-16-u16},$Dst16RnHI */
73213
  {
73214
    { 0, 0, 0, 0 },
73215
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DST16RNHI), 0 } },
73216
    & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_Rn_direct_HI, { 0xb1f00000 }
73217
  },
73218
/* adc.w${X} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
73219
  {
73220
    { 0, 0, 0, 0 },
73221
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } },
73222
    & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_direct_HI, { 0xb1c40000 }
73223
  },
73224
/* adc.w${X} ${Dsp-16-u16}[sb],$Dst16AnHI */
73225
  {
73226
    { 0, 0, 0, 0 },
73227
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } },
73228
    & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_direct_HI, { 0xb1e40000 }
73229
  },
73230
/* adc.w${X} ${Dsp-16-u16},$Dst16AnHI */
73231
  {
73232
    { 0, 0, 0, 0 },
73233
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DST16ANHI), 0 } },
73234
    & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_direct_HI, { 0xb1f40000 }
73235
  },
73236
/* adc.w${X} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
73237
  {
73238
    { 0, 0, 0, 0 },
73239
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
73240
    & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_indirect_HI, { 0xb1c60000 }
73241
  },
73242
/* adc.w${X} ${Dsp-16-u16}[sb],[$Dst16An] */
73243
  {
73244
    { 0, 0, 0, 0 },
73245
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
73246
    & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_indirect_HI, { 0xb1e60000 }
73247
  },
73248
/* adc.w${X} ${Dsp-16-u16},[$Dst16An] */
73249
  {
73250
    { 0, 0, 0, 0 },
73251
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } },
73252
    & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_indirect_HI, { 0xb1f60000 }
73253
  },
73254
/* adc.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
73255
  {
73256
    { 0, 0, 0, 0 },
73257
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
73258
    & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_An_relative_HI, { 0xb1c80000 }
73259
  },
73260
/* adc.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
73261
  {
73262
    { 0, 0, 0, 0 },
73263
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
73264
    & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_An_relative_HI, { 0xb1e80000 }
73265
  },
73266
/* adc.w${X} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
73267
  {
73268
    { 0, 0, 0, 0 },
73269
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
73270
    & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_An_relative_HI, { 0xb1f80000 }
73271
  },
73272
/* adc.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
73273
  {
73274
    { 0, 0, 0, 0 },
73275
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
73276
    & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_An_relative_HI, { 0xb1cc0000 }
73277
  },
73278
/* adc.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
73279
  {
73280
    { 0, 0, 0, 0 },
73281
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
73282
    & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_An_relative_HI, { 0xb1ec0000 }
73283
  },
73284
/* adc.w${X} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
73285
  {
73286
    { 0, 0, 0, 0 },
73287
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
73288
    & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_An_relative_HI, { 0xb1fc0000 }
73289
  },
73290
/* adc.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
73291
  {
73292
    { 0, 0, 0, 0 },
73293
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
73294
    & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_SB_relative_HI, { 0xb1ca0000 }
73295
  },
73296
/* adc.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
73297
  {
73298
    { 0, 0, 0, 0 },
73299
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
73300
    & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_SB_relative_HI, { 0xb1ea0000 }
73301
  },
73302
/* adc.w${X} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
73303
  {
73304
    { 0, 0, 0, 0 },
73305
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
73306
    & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_SB_relative_HI, { 0xb1fa0000 }
73307
  },
73308
/* adc.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
73309
  {
73310
    { 0, 0, 0, 0 },
73311
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
73312
    & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_SB_relative_HI, { 0xb1ce0000 }
73313
  },
73314
/* adc.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
73315
  {
73316
    { 0, 0, 0, 0 },
73317
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
73318
    & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_SB_relative_HI, { 0xb1ee0000 }
73319
  },
73320
/* adc.w${X} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
73321
  {
73322
    { 0, 0, 0, 0 },
73323
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
73324
    & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_SB_relative_HI, { 0xb1fe0000 }
73325
  },
73326
/* adc.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
73327
  {
73328
    { 0, 0, 0, 0 },
73329
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
73330
    & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_FB_relative_HI, { 0xb1cb0000 }
73331
  },
73332
/* adc.w${X} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
73333
  {
73334
    { 0, 0, 0, 0 },
73335
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
73336
    & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_FB_relative_HI, { 0xb1eb0000 }
73337
  },
73338
/* adc.w${X} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
73339
  {
73340
    { 0, 0, 0, 0 },
73341
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
73342
    & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_FB_relative_HI, { 0xb1fb0000 }
73343
  },
73344
/* adc.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
73345
  {
73346
    { 0, 0, 0, 0 },
73347
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } },
73348
    & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_absolute_HI, { 0xb1cf0000 }
73349
  },
73350
/* adc.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
73351
  {
73352
    { 0, 0, 0, 0 },
73353
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
73354
    & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_absolute_HI, { 0xb1ef0000 }
73355
  },
73356
/* adc.w${X} ${Dsp-16-u16},${Dsp-32-u16} */
73357
  {
73358
    { 0, 0, 0, 0 },
73359
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
73360
    & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_absolute_HI, { 0xb1ff0000 }
73361
  },
73362
/* adc.w${X} $Src16RnHI,$Dst16RnHI */
73363
  {
73364
    { 0, 0, 0, 0 },
73365
    { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DST16RNHI), 0 } },
73366
    & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_Rn_direct_HI, { 0xb100 }
73367
  },
73368
/* adc.w${X} $Src16AnHI,$Dst16RnHI */
73369
  {
73370
    { 0, 0, 0, 0 },
73371
    { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DST16RNHI), 0 } },
73372
    & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_Rn_direct_HI, { 0xb140 }
73373
  },
73374
/* adc.w${X} [$Src16An],$Dst16RnHI */
73375
  {
73376
    { 0, 0, 0, 0 },
73377
    { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } },
73378
    & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_Rn_direct_HI, { 0xb160 }
73379
  },
73380
/* adc.w${X} $Src16RnHI,$Dst16AnHI */
73381
  {
73382
    { 0, 0, 0, 0 },
73383
    { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DST16ANHI), 0 } },
73384
    & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_direct_HI, { 0xb104 }
73385
  },
73386
/* adc.w${X} $Src16AnHI,$Dst16AnHI */
73387
  {
73388
    { 0, 0, 0, 0 },
73389
    { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DST16ANHI), 0 } },
73390
    & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_direct_HI, { 0xb144 }
73391
  },
73392
/* adc.w${X} [$Src16An],$Dst16AnHI */
73393
  {
73394
    { 0, 0, 0, 0 },
73395
    { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } },
73396
    & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_direct_HI, { 0xb164 }
73397
  },
73398
/* adc.w${X} $Src16RnHI,[$Dst16An] */
73399
  {
73400
    { 0, 0, 0, 0 },
73401
    { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', '[', OP (DST16AN), ']', 0 } },
73402
    & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_indirect_HI, { 0xb106 }
73403
  },
73404
/* adc.w${X} $Src16AnHI,[$Dst16An] */
73405
  {
73406
    { 0, 0, 0, 0 },
73407
    { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', '[', OP (DST16AN), ']', 0 } },
73408
    & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_indirect_HI, { 0xb146 }
73409
  },
73410
/* adc.w${X} [$Src16An],[$Dst16An] */
73411
  {
73412
    { 0, 0, 0, 0 },
73413
    { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
73414
    & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_indirect_HI, { 0xb166 }
73415
  },
73416
/* adc.w${X} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
73417
  {
73418
    { 0, 0, 0, 0 },
73419
    { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
73420
    & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_An_relative_HI, { 0xb10800 }
73421
  },
73422
/* adc.w${X} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
73423
  {
73424
    { 0, 0, 0, 0 },
73425
    { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
73426
    & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_An_relative_HI, { 0xb14800 }
73427
  },
73428
/* adc.w${X} [$Src16An],${Dsp-16-u8}[$Dst16An] */
73429
  {
73430
    { 0, 0, 0, 0 },
73431
    { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
73432
    & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_An_relative_HI, { 0xb16800 }
73433
  },
73434
/* adc.w${X} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
73435
  {
73436
    { 0, 0, 0, 0 },
73437
    { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
73438
    & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_An_relative_HI, { 0xb10c0000 }
73439
  },
73440
/* adc.w${X} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
73441
  {
73442
    { 0, 0, 0, 0 },
73443
    { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
73444
    & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_An_relative_HI, { 0xb14c0000 }
73445
  },
73446
/* adc.w${X} [$Src16An],${Dsp-16-u16}[$Dst16An] */
73447
  {
73448
    { 0, 0, 0, 0 },
73449
    { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
73450
    & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_An_relative_HI, { 0xb16c0000 }
73451
  },
73452
/* adc.w${X} $Src16RnHI,${Dsp-16-u8}[sb] */
73453
  {
73454
    { 0, 0, 0, 0 },
73455
    { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
73456
    & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_SB_relative_HI, { 0xb10a00 }
73457
  },
73458
/* adc.w${X} $Src16AnHI,${Dsp-16-u8}[sb] */
73459
  {
73460
    { 0, 0, 0, 0 },
73461
    { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
73462
    & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_SB_relative_HI, { 0xb14a00 }
73463
  },
73464
/* adc.w${X} [$Src16An],${Dsp-16-u8}[sb] */
73465
  {
73466
    { 0, 0, 0, 0 },
73467
    { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
73468
    & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_SB_relative_HI, { 0xb16a00 }
73469
  },
73470
/* adc.w${X} $Src16RnHI,${Dsp-16-u16}[sb] */
73471
  {
73472
    { 0, 0, 0, 0 },
73473
    { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
73474
    & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_SB_relative_HI, { 0xb10e0000 }
73475
  },
73476
/* adc.w${X} $Src16AnHI,${Dsp-16-u16}[sb] */
73477
  {
73478
    { 0, 0, 0, 0 },
73479
    { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
73480
    & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_SB_relative_HI, { 0xb14e0000 }
73481
  },
73482
/* adc.w${X} [$Src16An],${Dsp-16-u16}[sb] */
73483
  {
73484
    { 0, 0, 0, 0 },
73485
    { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
73486
    & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_SB_relative_HI, { 0xb16e0000 }
73487
  },
73488
/* adc.w${X} $Src16RnHI,${Dsp-16-s8}[fb] */
73489
  {
73490
    { 0, 0, 0, 0 },
73491
    { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
73492
    & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_FB_relative_HI, { 0xb10b00 }
73493
  },
73494
/* adc.w${X} $Src16AnHI,${Dsp-16-s8}[fb] */
73495
  {
73496
    { 0, 0, 0, 0 },
73497
    { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
73498
    & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_FB_relative_HI, { 0xb14b00 }
73499
  },
73500
/* adc.w${X} [$Src16An],${Dsp-16-s8}[fb] */
73501
  {
73502
    { 0, 0, 0, 0 },
73503
    { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
73504
    & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_FB_relative_HI, { 0xb16b00 }
73505
  },
73506
/* adc.w${X} $Src16RnHI,${Dsp-16-u16} */
73507
  {
73508
    { 0, 0, 0, 0 },
73509
    { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), 0 } },
73510
    & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_absolute_HI, { 0xb10f0000 }
73511
  },
73512
/* adc.w${X} $Src16AnHI,${Dsp-16-u16} */
73513
  {
73514
    { 0, 0, 0, 0 },
73515
    { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), 0 } },
73516
    & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_absolute_HI, { 0xb14f0000 }
73517
  },
73518
/* adc.w${X} [$Src16An],${Dsp-16-u16} */
73519
  {
73520
    { 0, 0, 0, 0 },
73521
    { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } },
73522
    & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_absolute_HI, { 0xb16f0000 }
73523
  },
73524
/* adc.b${X} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
73525
  {
73526
    { 0, 0, 0, 0 },
73527
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } },
73528
    & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_Rn_direct_QI, { 0xb08000 }
73529
  },
73530
/* adc.b${X} ${Dsp-16-u8}[sb],$Dst16RnQI */
73531
  {
73532
    { 0, 0, 0, 0 },
73533
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } },
73534
    & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_Rn_direct_QI, { 0xb0a000 }
73535
  },
73536
/* adc.b${X} ${Dsp-16-s8}[fb],$Dst16RnQI */
73537
  {
73538
    { 0, 0, 0, 0 },
73539
    { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNQI), 0 } },
73540
    & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_Rn_direct_QI, { 0xb0b000 }
73541
  },
73542
/* adc.b${X} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
73543
  {
73544
    { 0, 0, 0, 0 },
73545
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } },
73546
    & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_direct_QI, { 0xb08400 }
73547
  },
73548
/* adc.b${X} ${Dsp-16-u8}[sb],$Dst16AnQI */
73549
  {
73550
    { 0, 0, 0, 0 },
73551
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } },
73552
    & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_direct_QI, { 0xb0a400 }
73553
  },
73554
/* adc.b${X} ${Dsp-16-s8}[fb],$Dst16AnQI */
73555
  {
73556
    { 0, 0, 0, 0 },
73557
    { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANQI), 0 } },
73558
    & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_direct_QI, { 0xb0b400 }
73559
  },
73560
/* adc.b${X} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
73561
  {
73562
    { 0, 0, 0, 0 },
73563
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
73564
    & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_indirect_QI, { 0xb08600 }
73565
  },
73566
/* adc.b${X} ${Dsp-16-u8}[sb],[$Dst16An] */
73567
  {
73568
    { 0, 0, 0, 0 },
73569
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
73570
    & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_indirect_QI, { 0xb0a600 }
73571
  },
73572
/* adc.b${X} ${Dsp-16-s8}[fb],[$Dst16An] */
73573
  {
73574
    { 0, 0, 0, 0 },
73575
    { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
73576
    & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_indirect_QI, { 0xb0b600 }
73577
  },
73578
/* adc.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
73579
  {
73580
    { 0, 0, 0, 0 },
73581
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
73582
    & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_An_relative_QI, { 0xb0880000 }
73583
  },
73584
/* adc.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
73585
  {
73586
    { 0, 0, 0, 0 },
73587
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
73588
    & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_An_relative_QI, { 0xb0a80000 }
73589
  },
73590
/* adc.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
73591
  {
73592
    { 0, 0, 0, 0 },
73593
    { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
73594
    & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_An_relative_QI, { 0xb0b80000 }
73595
  },
73596
/* adc.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
73597
  {
73598
    { 0, 0, 0, 0 },
73599
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
73600
    & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_An_relative_QI, { 0xb08c0000 }
73601
  },
73602
/* adc.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
73603
  {
73604
    { 0, 0, 0, 0 },
73605
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
73606
    & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_An_relative_QI, { 0xb0ac0000 }
73607
  },
73608
/* adc.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
73609
  {
73610
    { 0, 0, 0, 0 },
73611
    { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
73612
    & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_An_relative_QI, { 0xb0bc0000 }
73613
  },
73614
/* adc.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
73615
  {
73616
    { 0, 0, 0, 0 },
73617
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
73618
    & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_SB_relative_QI, { 0xb08a0000 }
73619
  },
73620
/* adc.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
73621
  {
73622
    { 0, 0, 0, 0 },
73623
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
73624
    & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_SB_relative_QI, { 0xb0aa0000 }
73625
  },
73626
/* adc.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
73627
  {
73628
    { 0, 0, 0, 0 },
73629
    { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
73630
    & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_SB_relative_QI, { 0xb0ba0000 }
73631
  },
73632
/* adc.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
73633
  {
73634
    { 0, 0, 0, 0 },
73635
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
73636
    & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_SB_relative_QI, { 0xb08e0000 }
73637
  },
73638
/* adc.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
73639
  {
73640
    { 0, 0, 0, 0 },
73641
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
73642
    & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_SB_relative_QI, { 0xb0ae0000 }
73643
  },
73644
/* adc.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
73645
  {
73646
    { 0, 0, 0, 0 },
73647
    { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
73648
    & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_SB_relative_QI, { 0xb0be0000 }
73649
  },
73650
/* adc.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
73651
  {
73652
    { 0, 0, 0, 0 },
73653
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
73654
    & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_FB_relative_QI, { 0xb08b0000 }
73655
  },
73656
/* adc.b${X} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
73657
  {
73658
    { 0, 0, 0, 0 },
73659
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
73660
    & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_FB_relative_QI, { 0xb0ab0000 }
73661
  },
73662
/* adc.b${X} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
73663
  {
73664
    { 0, 0, 0, 0 },
73665
    { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
73666
    & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_FB_relative_QI, { 0xb0bb0000 }
73667
  },
73668
/* adc.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
73669
  {
73670
    { 0, 0, 0, 0 },
73671
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } },
73672
    & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_absolute_QI, { 0xb08f0000 }
73673
  },
73674
/* adc.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
73675
  {
73676
    { 0, 0, 0, 0 },
73677
    { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
73678
    & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_absolute_QI, { 0xb0af0000 }
73679
  },
73680
/* adc.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
73681
  {
73682
    { 0, 0, 0, 0 },
73683
    { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
73684
    & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_absolute_QI, { 0xb0bf0000 }
73685
  },
73686
/* adc.b${X} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
73687
  {
73688
    { 0, 0, 0, 0 },
73689
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } },
73690
    & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_Rn_direct_QI, { 0xb0c00000 }
73691
  },
73692
/* adc.b${X} ${Dsp-16-u16}[sb],$Dst16RnQI */
73693
  {
73694
    { 0, 0, 0, 0 },
73695
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } },
73696
    & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_Rn_direct_QI, { 0xb0e00000 }
73697
  },
73698
/* adc.b${X} ${Dsp-16-u16},$Dst16RnQI */
73699
  {
73700
    { 0, 0, 0, 0 },
73701
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DST16RNQI), 0 } },
73702
    & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_Rn_direct_QI, { 0xb0f00000 }
73703
  },
73704
/* adc.b${X} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
73705
  {
73706
    { 0, 0, 0, 0 },
73707
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } },
73708
    & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_direct_QI, { 0xb0c40000 }
73709
  },
73710
/* adc.b${X} ${Dsp-16-u16}[sb],$Dst16AnQI */
73711
  {
73712
    { 0, 0, 0, 0 },
73713
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } },
73714
    & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_direct_QI, { 0xb0e40000 }
73715
  },
73716
/* adc.b${X} ${Dsp-16-u16},$Dst16AnQI */
73717
  {
73718
    { 0, 0, 0, 0 },
73719
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DST16ANQI), 0 } },
73720
    & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_direct_QI, { 0xb0f40000 }
73721
  },
73722
/* adc.b${X} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
73723
  {
73724
    { 0, 0, 0, 0 },
73725
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
73726
    & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_indirect_QI, { 0xb0c60000 }
73727
  },
73728
/* adc.b${X} ${Dsp-16-u16}[sb],[$Dst16An] */
73729
  {
73730
    { 0, 0, 0, 0 },
73731
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
73732
    & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_indirect_QI, { 0xb0e60000 }
73733
  },
73734
/* adc.b${X} ${Dsp-16-u16},[$Dst16An] */
73735
  {
73736
    { 0, 0, 0, 0 },
73737
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } },
73738
    & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_indirect_QI, { 0xb0f60000 }
73739
  },
73740
/* adc.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
73741
  {
73742
    { 0, 0, 0, 0 },
73743
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
73744
    & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_An_relative_QI, { 0xb0c80000 }
73745
  },
73746
/* adc.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
73747
  {
73748
    { 0, 0, 0, 0 },
73749
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
73750
    & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_An_relative_QI, { 0xb0e80000 }
73751
  },
73752
/* adc.b${X} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
73753
  {
73754
    { 0, 0, 0, 0 },
73755
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
73756
    & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_An_relative_QI, { 0xb0f80000 }
73757
  },
73758
/* adc.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
73759
  {
73760
    { 0, 0, 0, 0 },
73761
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
73762
    & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_An_relative_QI, { 0xb0cc0000 }
73763
  },
73764
/* adc.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
73765
  {
73766
    { 0, 0, 0, 0 },
73767
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
73768
    & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_An_relative_QI, { 0xb0ec0000 }
73769
  },
73770
/* adc.b${X} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
73771
  {
73772
    { 0, 0, 0, 0 },
73773
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
73774
    & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_An_relative_QI, { 0xb0fc0000 }
73775
  },
73776
/* adc.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
73777
  {
73778
    { 0, 0, 0, 0 },
73779
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
73780
    & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_SB_relative_QI, { 0xb0ca0000 }
73781
  },
73782
/* adc.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
73783
  {
73784
    { 0, 0, 0, 0 },
73785
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
73786
    & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_SB_relative_QI, { 0xb0ea0000 }
73787
  },
73788
/* adc.b${X} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
73789
  {
73790
    { 0, 0, 0, 0 },
73791
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
73792
    & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_SB_relative_QI, { 0xb0fa0000 }
73793
  },
73794
/* adc.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
73795
  {
73796
    { 0, 0, 0, 0 },
73797
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
73798
    & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_SB_relative_QI, { 0xb0ce0000 }
73799
  },
73800
/* adc.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
73801
  {
73802
    { 0, 0, 0, 0 },
73803
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
73804
    & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_SB_relative_QI, { 0xb0ee0000 }
73805
  },
73806
/* adc.b${X} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
73807
  {
73808
    { 0, 0, 0, 0 },
73809
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
73810
    & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_SB_relative_QI, { 0xb0fe0000 }
73811
  },
73812
/* adc.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
73813
  {
73814
    { 0, 0, 0, 0 },
73815
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
73816
    & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_FB_relative_QI, { 0xb0cb0000 }
73817
  },
73818
/* adc.b${X} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
73819
  {
73820
    { 0, 0, 0, 0 },
73821
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
73822
    & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_FB_relative_QI, { 0xb0eb0000 }
73823
  },
73824
/* adc.b${X} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
73825
  {
73826
    { 0, 0, 0, 0 },
73827
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
73828
    & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_FB_relative_QI, { 0xb0fb0000 }
73829
  },
73830
/* adc.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
73831
  {
73832
    { 0, 0, 0, 0 },
73833
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } },
73834
    & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_absolute_QI, { 0xb0cf0000 }
73835
  },
73836
/* adc.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
73837
  {
73838
    { 0, 0, 0, 0 },
73839
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
73840
    & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_absolute_QI, { 0xb0ef0000 }
73841
  },
73842
/* adc.b${X} ${Dsp-16-u16},${Dsp-32-u16} */
73843
  {
73844
    { 0, 0, 0, 0 },
73845
    { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
73846
    & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_absolute_QI, { 0xb0ff0000 }
73847
  },
73848
/* adc.b${X} $Src16RnQI,$Dst16RnQI */
73849
  {
73850
    { 0, 0, 0, 0 },
73851
    { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DST16RNQI), 0 } },
73852
    & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_Rn_direct_QI, { 0xb000 }
73853
  },
73854
/* adc.b${X} $Src16AnQI,$Dst16RnQI */
73855
  {
73856
    { 0, 0, 0, 0 },
73857
    { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DST16RNQI), 0 } },
73858
    & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_Rn_direct_QI, { 0xb040 }
73859
  },
73860
/* adc.b${X} [$Src16An],$Dst16RnQI */
73861
  {
73862
    { 0, 0, 0, 0 },
73863
    { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } },
73864
    & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_Rn_direct_QI, { 0xb060 }
73865
  },
73866
/* adc.b${X} $Src16RnQI,$Dst16AnQI */
73867
  {
73868
    { 0, 0, 0, 0 },
73869
    { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DST16ANQI), 0 } },
73870
    & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_direct_QI, { 0xb004 }
73871
  },
73872
/* adc.b${X} $Src16AnQI,$Dst16AnQI */
73873
  {
73874
    { 0, 0, 0, 0 },
73875
    { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DST16ANQI), 0 } },
73876
    & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_direct_QI, { 0xb044 }
73877
  },
73878
/* adc.b${X} [$Src16An],$Dst16AnQI */
73879
  {
73880
    { 0, 0, 0, 0 },
73881
    { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } },
73882
    & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_direct_QI, { 0xb064 }
73883
  },
73884
/* adc.b${X} $Src16RnQI,[$Dst16An] */
73885
  {
73886
    { 0, 0, 0, 0 },
73887
    { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', '[', OP (DST16AN), ']', 0 } },
73888
    & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_indirect_QI, { 0xb006 }
73889
  },
73890
/* adc.b${X} $Src16AnQI,[$Dst16An] */
73891
  {
73892
    { 0, 0, 0, 0 },
73893
    { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', '[', OP (DST16AN), ']', 0 } },
73894
    & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_indirect_QI, { 0xb046 }
73895
  },
73896
/* adc.b${X} [$Src16An],[$Dst16An] */
73897
  {
73898
    { 0, 0, 0, 0 },
73899
    { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
73900
    & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_indirect_QI, { 0xb066 }
73901
  },
73902
/* adc.b${X} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
73903
  {
73904
    { 0, 0, 0, 0 },
73905
    { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
73906
    & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_An_relative_QI, { 0xb00800 }
73907
  },
73908
/* adc.b${X} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
73909
  {
73910
    { 0, 0, 0, 0 },
73911
    { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
73912
    & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_An_relative_QI, { 0xb04800 }
73913
  },
73914
/* adc.b${X} [$Src16An],${Dsp-16-u8}[$Dst16An] */
73915
  {
73916
    { 0, 0, 0, 0 },
73917
    { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
73918
    & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_An_relative_QI, { 0xb06800 }
73919
  },
73920
/* adc.b${X} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
73921
  {
73922
    { 0, 0, 0, 0 },
73923
    { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
73924
    & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_An_relative_QI, { 0xb00c0000 }
73925
  },
73926
/* adc.b${X} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
73927
  {
73928
    { 0, 0, 0, 0 },
73929
    { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
73930
    & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_An_relative_QI, { 0xb04c0000 }
73931
  },
73932
/* adc.b${X} [$Src16An],${Dsp-16-u16}[$Dst16An] */
73933
  {
73934
    { 0, 0, 0, 0 },
73935
    { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
73936
    & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_An_relative_QI, { 0xb06c0000 }
73937
  },
73938
/* adc.b${X} $Src16RnQI,${Dsp-16-u8}[sb] */
73939
  {
73940
    { 0, 0, 0, 0 },
73941
    { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
73942
    & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_SB_relative_QI, { 0xb00a00 }
73943
  },
73944
/* adc.b${X} $Src16AnQI,${Dsp-16-u8}[sb] */
73945
  {
73946
    { 0, 0, 0, 0 },
73947
    { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
73948
    & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_SB_relative_QI, { 0xb04a00 }
73949
  },
73950
/* adc.b${X} [$Src16An],${Dsp-16-u8}[sb] */
73951
  {
73952
    { 0, 0, 0, 0 },
73953
    { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
73954
    & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_SB_relative_QI, { 0xb06a00 }
73955
  },
73956
/* adc.b${X} $Src16RnQI,${Dsp-16-u16}[sb] */
73957
  {
73958
    { 0, 0, 0, 0 },
73959
    { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
73960
    & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_SB_relative_QI, { 0xb00e0000 }
73961
  },
73962
/* adc.b${X} $Src16AnQI,${Dsp-16-u16}[sb] */
73963
  {
73964
    { 0, 0, 0, 0 },
73965
    { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
73966
    & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_SB_relative_QI, { 0xb04e0000 }
73967
  },
73968
/* adc.b${X} [$Src16An],${Dsp-16-u16}[sb] */
73969
  {
73970
    { 0, 0, 0, 0 },
73971
    { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
73972
    & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_SB_relative_QI, { 0xb06e0000 }
73973
  },
73974
/* adc.b${X} $Src16RnQI,${Dsp-16-s8}[fb] */
73975
  {
73976
    { 0, 0, 0, 0 },
73977
    { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
73978
    & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_FB_relative_QI, { 0xb00b00 }
73979
  },
73980
/* adc.b${X} $Src16AnQI,${Dsp-16-s8}[fb] */
73981
  {
73982
    { 0, 0, 0, 0 },
73983
    { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
73984
    & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_FB_relative_QI, { 0xb04b00 }
73985
  },
73986
/* adc.b${X} [$Src16An],${Dsp-16-s8}[fb] */
73987
  {
73988
    { 0, 0, 0, 0 },
73989
    { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
73990
    & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_FB_relative_QI, { 0xb06b00 }
73991
  },
73992
/* adc.b${X} $Src16RnQI,${Dsp-16-u16} */
73993
  {
73994
    { 0, 0, 0, 0 },
73995
    { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), 0 } },
73996
    & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_absolute_QI, { 0xb00f0000 }
73997
  },
73998
/* adc.b${X} $Src16AnQI,${Dsp-16-u16} */
73999
  {
74000
    { 0, 0, 0, 0 },
74001
    { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), 0 } },
74002
    & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_absolute_QI, { 0xb04f0000 }
74003
  },
74004
/* adc.b${X} [$Src16An],${Dsp-16-u16} */
74005
  {
74006
    { 0, 0, 0, 0 },
74007
    { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } },
74008
    & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_absolute_QI, { 0xb06f0000 }
74009
  },
74010
/* adc.w${X} #${Imm-24-HI},$Dst32RnPrefixedHI */
74011
  {
74012
    { 0, 0, 0, 0 },
74013
    { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DST32RNPREFIXEDHI), 0 } },
74014
    & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_Rn_direct_Prefixed_HI, { 0x1892e00 }
74015
  },
74016
/* adc.w${X} #${Imm-24-HI},$Dst32AnPrefixedHI */
74017
  {
74018
    { 0, 0, 0, 0 },
74019
    { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DST32ANPREFIXEDHI), 0 } },
74020
    & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_An_direct_Prefixed_HI, { 0x181ae00 }
74021
  },
74022
/* adc.w${X} #${Imm-24-HI},[$Dst32AnPrefixed] */
74023
  {
74024
    { 0, 0, 0, 0 },
74025
    { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
74026
    & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_An_indirect_Prefixed_HI, { 0x1812e00 }
74027
  },
74028
/* adc.w${X} #${Imm-32-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */
74029
  {
74030
    { 0, 0, 0, 0 },
74031
    { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
74032
    & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_An_relative_Prefixed_HI, { 0x1832e00 }
74033
  },
74034
/* adc.w${X} #${Imm-32-HI},${Dsp-24-u8}[sb] */
74035
  {
74036
    { 0, 0, 0, 0 },
74037
    { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
74038
    & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_SB_relative_Prefixed_HI, { 0x183ae00 }
74039
  },
74040
/* adc.w${X} #${Imm-32-HI},${Dsp-24-s8}[fb] */
74041
  {
74042
    { 0, 0, 0, 0 },
74043
    { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
74044
    & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_FB_relative_Prefixed_HI, { 0x183ee00 }
74045
  },
74046
/* adc.w${X} #${Imm-40-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */
74047
  {
74048
    { 0, 0, 0, 0 },
74049
    { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
74050
    & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_An_relative_Prefixed_HI, { 0x1852e00 }
74051
  },
74052
/* adc.w${X} #${Imm-40-HI},${Dsp-24-u16}[sb] */
74053
  {
74054
    { 0, 0, 0, 0 },
74055
    { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
74056
    & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_SB_relative_Prefixed_HI, { 0x185ae00 }
74057
  },
74058
/* adc.w${X} #${Imm-40-HI},${Dsp-24-s16}[fb] */
74059
  {
74060
    { 0, 0, 0, 0 },
74061
    { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
74062
    & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_FB_relative_Prefixed_HI, { 0x185ee00 }
74063
  },
74064
/* adc.w${X} #${Imm-40-HI},${Dsp-24-u16} */
74065
  {
74066
    { 0, 0, 0, 0 },
74067
    { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), 0 } },
74068
    & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_absolute_Prefixed_HI, { 0x187ee00 }
74069
  },
74070
/* adc.w${X} #${Imm-48-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */
74071
  {
74072
    { 0, 0, 0, 0 },
74073
    { { MNEM, OP (X), ' ', '#', OP (IMM_48_HI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
74074
    & ifmt_sbb32_w_imm_G_24_24_Prefixed_dst32_24_24_An_relative_Prefixed_HI, { 0x1872e00 }
74075
  },
74076
/* adc.w${X} #${Imm-48-HI},${Dsp-24-u24} */
74077
  {
74078
    { 0, 0, 0, 0 },
74079
    { { MNEM, OP (X), ' ', '#', OP (IMM_48_HI), ',', OP (DSP_24_U24), 0 } },
74080
    & ifmt_sbb32_w_imm_G_24_24_Prefixed_dst32_24_24_absolute_Prefixed_HI, { 0x187ae00 }
74081
  },
74082
/* adc.b${X} #${Imm-24-QI},$Dst32RnPrefixedQI */
74083
  {
74084
    { 0, 0, 0, 0 },
74085
    { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DST32RNPREFIXEDQI), 0 } },
74086
    & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_Rn_direct_Prefixed_QI, { 0x1882e00 }
74087
  },
74088
/* adc.b${X} #${Imm-24-QI},$Dst32AnPrefixedQI */
74089
  {
74090
    { 0, 0, 0, 0 },
74091
    { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DST32ANPREFIXEDQI), 0 } },
74092
    & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_An_direct_Prefixed_QI, { 0x180ae00 }
74093
  },
74094
/* adc.b${X} #${Imm-24-QI},[$Dst32AnPrefixed] */
74095
  {
74096
    { 0, 0, 0, 0 },
74097
    { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } },
74098
    & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_An_indirect_Prefixed_QI, { 0x1802e00 }
74099
  },
74100
/* adc.b${X} #${Imm-32-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */
74101
  {
74102
    { 0, 0, 0, 0 },
74103
    { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } },
74104
    & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_An_relative_Prefixed_QI, { 0x1822e00 }
74105
  },
74106
/* adc.b${X} #${Imm-32-QI},${Dsp-24-u8}[sb] */
74107
  {
74108
    { 0, 0, 0, 0 },
74109
    { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
74110
    & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_SB_relative_Prefixed_QI, { 0x182ae00 }
74111
  },
74112
/* adc.b${X} #${Imm-32-QI},${Dsp-24-s8}[fb] */
74113
  {
74114
    { 0, 0, 0, 0 },
74115
    { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
74116
    & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_FB_relative_Prefixed_QI, { 0x182ee00 }
74117
  },
74118
/* adc.b${X} #${Imm-40-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */
74119
  {
74120
    { 0, 0, 0, 0 },
74121
    { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } },
74122
    & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_An_relative_Prefixed_QI, { 0x1842e00 }
74123
  },
74124
/* adc.b${X} #${Imm-40-QI},${Dsp-24-u16}[sb] */
74125
  {
74126
    { 0, 0, 0, 0 },
74127
    { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
74128
    & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_SB_relative_Prefixed_QI, { 0x184ae00 }
74129
  },
74130
/* adc.b${X} #${Imm-40-QI},${Dsp-24-s16}[fb] */
74131
  {
74132
    { 0, 0, 0, 0 },
74133
    { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
74134
    & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_FB_relative_Prefixed_QI, { 0x184ee00 }
74135
  },
74136
/* adc.b${X} #${Imm-40-QI},${Dsp-24-u16} */
74137
  {
74138
    { 0, 0, 0, 0 },
74139
    { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), 0 } },
74140
    & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_absolute_Prefixed_QI, { 0x186ee00 }
74141
  },
74142
/* adc.b${X} #${Imm-48-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */
74143
  {
74144
    { 0, 0, 0, 0 },
74145
    { { MNEM, OP (X), ' ', '#', OP (IMM_48_QI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } },
74146
    & ifmt_sbb32_b_imm_G_24_24_Prefixed_dst32_24_24_An_relative_Prefixed_QI, { 0x1862e00 }
74147
  },
74148
/* adc.b${X} #${Imm-48-QI},${Dsp-24-u24} */
74149
  {
74150
    { 0, 0, 0, 0 },
74151
    { { MNEM, OP (X), ' ', '#', OP (IMM_48_QI), ',', OP (DSP_24_U24), 0 } },
74152
    & ifmt_sbb32_b_imm_G_24_24_Prefixed_dst32_24_24_absolute_Prefixed_QI, { 0x186ae00 }
74153
  },
74154
/* adc.w${X} #${Imm-16-HI},$Dst16RnHI */
74155
  {
74156
    { 0, 0, 0, 0 },
74157
    { { MNEM, OP (X), ' ', '#', OP (IMM_16_HI), ',', OP (DST16RNHI), 0 } },
74158
    & ifmt_xor16_w_imm_G_basic_dst16_Rn_direct_HI, { 0x77600000 }
74159
  },
74160
/* adc.w${X} #${Imm-16-HI},$Dst16AnHI */
74161
  {
74162
    { 0, 0, 0, 0 },
74163
    { { MNEM, OP (X), ' ', '#', OP (IMM_16_HI), ',', OP (DST16ANHI), 0 } },
74164
    & ifmt_xor16_w_imm_G_basic_dst16_An_direct_HI, { 0x77640000 }
74165
  },
74166
/* adc.w${X} #${Imm-16-HI},[$Dst16An] */
74167
  {
74168
    { 0, 0, 0, 0 },
74169
    { { MNEM, OP (X), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST16AN), ']', 0 } },
74170
    & ifmt_xor16_w_imm_G_basic_dst16_An_indirect_HI, { 0x77660000 }
74171
  },
74172
/* adc.w${X} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
74173
  {
74174
    { 0, 0, 0, 0 },
74175
    { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
74176
    & ifmt_xor16_w_imm_G_16_8_dst16_16_8_An_relative_HI, { 0x77680000 }
74177
  },
74178
/* adc.w${X} #${Imm-24-HI},${Dsp-16-u8}[sb] */
74179
  {
74180
    { 0, 0, 0, 0 },
74181
    { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
74182
    & ifmt_xor16_w_imm_G_16_8_dst16_16_8_SB_relative_HI, { 0x776a0000 }
74183
  },
74184
/* adc.w${X} #${Imm-24-HI},${Dsp-16-s8}[fb] */
74185
  {
74186
    { 0, 0, 0, 0 },
74187
    { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
74188
    & ifmt_xor16_w_imm_G_16_8_dst16_16_8_FB_relative_HI, { 0x776b0000 }
74189
  },
74190
/* adc.w${X} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
74191
  {
74192
    { 0, 0, 0, 0 },
74193
    { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
74194
    & ifmt_xor16_w_imm_G_16_16_dst16_16_16_An_relative_HI, { 0x776c0000 }
74195
  },
74196
/* adc.w${X} #${Imm-32-HI},${Dsp-16-u16}[sb] */
74197
  {
74198
    { 0, 0, 0, 0 },
74199
    { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
74200
    & ifmt_xor16_w_imm_G_16_16_dst16_16_16_SB_relative_HI, { 0x776e0000 }
74201
  },
74202
/* adc.w${X} #${Imm-32-HI},${Dsp-16-u16} */
74203
  {
74204
    { 0, 0, 0, 0 },
74205
    { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } },
74206
    & ifmt_xor16_w_imm_G_16_16_dst16_16_16_absolute_HI, { 0x776f0000 }
74207
  },
74208
/* adc.b${X} #${Imm-16-QI},$Dst16RnQI */
74209
  {
74210
    { 0, 0, 0, 0 },
74211
    { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST16RNQI), 0 } },
74212
    & ifmt_xor16_b_imm_G_basic_dst16_Rn_direct_QI, { 0x766000 }
74213
  },
74214
/* adc.b${X} #${Imm-16-QI},$Dst16AnQI */
74215
  {
74216
    { 0, 0, 0, 0 },
74217
    { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST16ANQI), 0 } },
74218
    & ifmt_xor16_b_imm_G_basic_dst16_An_direct_QI, { 0x766400 }
74219
  },
74220
/* adc.b${X} #${Imm-16-QI},[$Dst16An] */
74221
  {
74222
    { 0, 0, 0, 0 },
74223
    { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST16AN), ']', 0 } },
74224
    & ifmt_xor16_b_imm_G_basic_dst16_An_indirect_QI, { 0x766600 }
74225
  },
74226
/* adc.b${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
74227
  {
74228
    { 0, 0, 0, 0 },
74229
    { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
74230
    & ifmt_xor16_b_imm_G_16_8_dst16_16_8_An_relative_QI, { 0x76680000 }
74231
  },
74232
/* adc.b${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
74233
  {
74234
    { 0, 0, 0, 0 },
74235
    { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
74236
    & ifmt_xor16_b_imm_G_16_8_dst16_16_8_SB_relative_QI, { 0x766a0000 }
74237
  },
74238
/* adc.b${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
74239
  {
74240
    { 0, 0, 0, 0 },
74241
    { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
74242
    & ifmt_xor16_b_imm_G_16_8_dst16_16_8_FB_relative_QI, { 0x766b0000 }
74243
  },
74244
/* adc.b${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
74245
  {
74246
    { 0, 0, 0, 0 },
74247
    { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
74248
    & ifmt_xor16_b_imm_G_16_16_dst16_16_16_An_relative_QI, { 0x766c0000 }
74249
  },
74250
/* adc.b${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
74251
  {
74252
    { 0, 0, 0, 0 },
74253
    { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
74254
    & ifmt_xor16_b_imm_G_16_16_dst16_16_16_SB_relative_QI, { 0x766e0000 }
74255
  },
74256
/* adc.b${X} #${Imm-32-QI},${Dsp-16-u16} */
74257
  {
74258
    { 0, 0, 0, 0 },
74259
    { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } },
74260
    & ifmt_xor16_b_imm_G_16_16_dst16_16_16_absolute_QI, { 0x766f0000 }
74261
  },
74262
/* add.w${S} #${Imm-16-HI},${Dsp-8-u8}[sb] */
74263
  {
74264
    { 0, 0, 0, 0 },
74265
    { { MNEM, OP (S), ' ', '#', OP (IMM_16_HI), ',', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } },
74266
    & ifmt_tst32_w_imm_S_2_S_8_dst32_2_S_8_SB_relative_HI, { 0x27000000 }
74267
  },
74268
/* add.w${S} #${Imm-16-HI},${Dsp-8-s8}[fb] */
74269
  {
74270
    { 0, 0, 0, 0 },
74271
    { { MNEM, OP (S), ' ', '#', OP (IMM_16_HI), ',', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } },
74272
    & ifmt_tst32_w_imm_S_2_S_8_dst32_2_S_8_FB_relative_HI, { 0x37000000 }
74273
  },
74274
/* add.w${S} #${Imm-24-HI},${Dsp-8-u16} */
74275
  {
74276
    { 0, 0, 0, 0 },
74277
    { { MNEM, OP (S), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_8_U16), 0 } },
74278
    & ifmt_tst32_w_imm_S_2_S_16_dst32_2_S_16_absolute_HI, { 0x17000000 }
74279
  },
74280
/* add.w${S} #${Imm-8-HI},r0 */
74281
  {
74282
    { 0, 0, 0, 0 },
74283
    { { MNEM, OP (S), ' ', '#', OP (IMM_8_HI), ',', 'r', '0', 0 } },
74284
    & ifmt_tst32_w_imm_S_2_S_basic_dst32_2_S_R0_direct_HI, { 0x70000 }
74285
  },
74286
/* add.b${S} #${Imm-16-QI},${Dsp-8-u8}[sb] */
74287
  {
74288
    { 0, 0, 0, 0 },
74289
    { { MNEM, OP (S), ' ', '#', OP (IMM_16_QI), ',', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } },
74290
    & ifmt_tst32_b_imm_S_2_S_8_dst32_2_S_8_SB_relative_QI, { 0x260000 }
74291
  },
74292
/* add.b${S} #${Imm-16-QI},${Dsp-8-s8}[fb] */
74293
  {
74294
    { 0, 0, 0, 0 },
74295
    { { MNEM, OP (S), ' ', '#', OP (IMM_16_QI), ',', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } },
74296
    & ifmt_tst32_b_imm_S_2_S_8_dst32_2_S_8_FB_relative_QI, { 0x360000 }
74297
  },
74298
/* add.b${S} #${Imm-24-QI},${Dsp-8-u16} */
74299
  {
74300
    { 0, 0, 0, 0 },
74301
    { { MNEM, OP (S), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_8_U16), 0 } },
74302
    & ifmt_tst32_b_imm_S_2_S_16_dst32_2_S_16_absolute_QI, { 0x16000000 }
74303
  },
74304
/* add.b${S} #${Imm-8-QI},r0l */
74305
  {
74306
    { 0, 0, 0, 0 },
74307
    { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'l', 0 } },
74308
    & ifmt_tst32_b_imm_S_2_S_basic_dst32_2_S_R0l_direct_QI, { 0x600 }
74309
  },
74310
/* add.l${S} #${Imm1-S},a0 */
74311
  {
74312
    { 0, 0, 0, 0 },
74313
    { { MNEM, OP (S), ' ', '#', OP (IMM1_S), ',', 'a', '0', 0 } },
74314
    & ifmt_add32_l_s_imm1_S_an_dst32_1_S_A0_direct_HI, { 0x8c }
74315
  },
74316
/* add.l${S} #${Imm1-S},a1 */
74317
  {
74318
    { 0, 0, 0, 0 },
74319
    { { MNEM, OP (S), ' ', '#', OP (IMM1_S), ',', 'a', '1', 0 } },
74320
    & ifmt_add32_l_s_imm1_S_an_dst32_1_S_A1_direct_HI, { 0x8d }
74321
  },
74322
/* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
74323
  {
74324
    { 0, 0, 0, 0 },
74325
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
74326
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0x990200 }
74327
  },
74328
/* add.l${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedSI */
74329
  {
74330
    { 0, 0, 0, 0 },
74331
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
74332
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0x992200 }
74333
  },
74334
/* add.l${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedSI */
74335
  {
74336
    { 0, 0, 0, 0 },
74337
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
74338
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0x993200 }
74339
  },
74340
/* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
74341
  {
74342
    { 0, 0, 0, 0 },
74343
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
74344
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0x918200 }
74345
  },
74346
/* add.l${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedSI */
74347
  {
74348
    { 0, 0, 0, 0 },
74349
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
74350
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0x91a200 }
74351
  },
74352
/* add.l${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedSI */
74353
  {
74354
    { 0, 0, 0, 0 },
74355
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
74356
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0x91b200 }
74357
  },
74358
/* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
74359
  {
74360
    { 0, 0, 0, 0 },
74361
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74362
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0x910200 }
74363
  },
74364
/* add.l${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
74365
  {
74366
    { 0, 0, 0, 0 },
74367
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74368
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0x912200 }
74369
  },
74370
/* add.l${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
74371
  {
74372
    { 0, 0, 0, 0 },
74373
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74374
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0x913200 }
74375
  },
74376
/* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
74377
  {
74378
    { 0, 0, 0, 0 },
74379
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74380
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_8_An_relative_Unprefixed_SI, { 0x93020000 }
74381
  },
74382
/* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
74383
  {
74384
    { 0, 0, 0, 0 },
74385
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74386
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_8_An_relative_Unprefixed_SI, { 0x93220000 }
74387
  },
74388
/* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
74389
  {
74390
    { 0, 0, 0, 0 },
74391
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74392
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_8_An_relative_Unprefixed_SI, { 0x93320000 }
74393
  },
74394
/* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
74395
  {
74396
    { 0, 0, 0, 0 },
74397
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74398
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_16_An_relative_Unprefixed_SI, { 0x95020000 }
74399
  },
74400
/* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
74401
  {
74402
    { 0, 0, 0, 0 },
74403
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74404
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_16_An_relative_Unprefixed_SI, { 0x95220000 }
74405
  },
74406
/* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
74407
  {
74408
    { 0, 0, 0, 0 },
74409
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74410
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_16_An_relative_Unprefixed_SI, { 0x95320000 }
74411
  },
74412
/* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
74413
  {
74414
    { 0, 0, 0, 0 },
74415
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74416
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_24_An_relative_Unprefixed_SI, { 0x97020000 }
74417
  },
74418
/* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
74419
  {
74420
    { 0, 0, 0, 0 },
74421
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74422
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_24_An_relative_Unprefixed_SI, { 0x97220000 }
74423
  },
74424
/* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
74425
  {
74426
    { 0, 0, 0, 0 },
74427
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74428
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_24_An_relative_Unprefixed_SI, { 0x97320000 }
74429
  },
74430
/* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
74431
  {
74432
    { 0, 0, 0, 0 },
74433
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
74434
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_8_SB_relative_Unprefixed_SI, { 0x93820000 }
74435
  },
74436
/* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
74437
  {
74438
    { 0, 0, 0, 0 },
74439
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
74440
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_8_SB_relative_Unprefixed_SI, { 0x93a20000 }
74441
  },
74442
/* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
74443
  {
74444
    { 0, 0, 0, 0 },
74445
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
74446
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_8_SB_relative_Unprefixed_SI, { 0x93b20000 }
74447
  },
74448
/* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
74449
  {
74450
    { 0, 0, 0, 0 },
74451
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
74452
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_16_SB_relative_Unprefixed_SI, { 0x95820000 }
74453
  },
74454
/* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
74455
  {
74456
    { 0, 0, 0, 0 },
74457
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
74458
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_16_SB_relative_Unprefixed_SI, { 0x95a20000 }
74459
  },
74460
/* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
74461
  {
74462
    { 0, 0, 0, 0 },
74463
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
74464
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_16_SB_relative_Unprefixed_SI, { 0x95b20000 }
74465
  },
74466
/* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
74467
  {
74468
    { 0, 0, 0, 0 },
74469
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
74470
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_8_FB_relative_Unprefixed_SI, { 0x93c20000 }
74471
  },
74472
/* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
74473
  {
74474
    { 0, 0, 0, 0 },
74475
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
74476
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_8_FB_relative_Unprefixed_SI, { 0x93e20000 }
74477
  },
74478
/* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
74479
  {
74480
    { 0, 0, 0, 0 },
74481
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
74482
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_8_FB_relative_Unprefixed_SI, { 0x93f20000 }
74483
  },
74484
/* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
74485
  {
74486
    { 0, 0, 0, 0 },
74487
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
74488
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_16_FB_relative_Unprefixed_SI, { 0x95c20000 }
74489
  },
74490
/* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
74491
  {
74492
    { 0, 0, 0, 0 },
74493
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
74494
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_16_FB_relative_Unprefixed_SI, { 0x95e20000 }
74495
  },
74496
/* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
74497
  {
74498
    { 0, 0, 0, 0 },
74499
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
74500
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_16_FB_relative_Unprefixed_SI, { 0x95f20000 }
74501
  },
74502
/* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
74503
  {
74504
    { 0, 0, 0, 0 },
74505
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
74506
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_16_absolute_Unprefixed_SI, { 0x97c20000 }
74507
  },
74508
/* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
74509
  {
74510
    { 0, 0, 0, 0 },
74511
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
74512
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_16_absolute_Unprefixed_SI, { 0x97e20000 }
74513
  },
74514
/* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
74515
  {
74516
    { 0, 0, 0, 0 },
74517
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
74518
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_16_absolute_Unprefixed_SI, { 0x97f20000 }
74519
  },
74520
/* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
74521
  {
74522
    { 0, 0, 0, 0 },
74523
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
74524
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_24_absolute_Unprefixed_SI, { 0x97820000 }
74525
  },
74526
/* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
74527
  {
74528
    { 0, 0, 0, 0 },
74529
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } },
74530
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_24_absolute_Unprefixed_SI, { 0x97a20000 }
74531
  },
74532
/* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
74533
  {
74534
    { 0, 0, 0, 0 },
74535
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } },
74536
    & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_24_absolute_Unprefixed_SI, { 0x97b20000 }
74537
  },
74538
/* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
74539
  {
74540
    { 0, 0, 0, 0 },
74541
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
74542
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xa9020000 }
74543
  },
74544
/* add.l${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedSI */
74545
  {
74546
    { 0, 0, 0, 0 },
74547
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
74548
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xa9220000 }
74549
  },
74550
/* add.l${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedSI */
74551
  {
74552
    { 0, 0, 0, 0 },
74553
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
74554
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xa9320000 }
74555
  },
74556
/* add.l${G} ${Dsp-16-u16},$Dst32RnUnprefixedSI */
74557
  {
74558
    { 0, 0, 0, 0 },
74559
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
74560
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xb9320000 }
74561
  },
74562
/* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
74563
  {
74564
    { 0, 0, 0, 0 },
74565
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
74566
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xa1820000 }
74567
  },
74568
/* add.l${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedSI */
74569
  {
74570
    { 0, 0, 0, 0 },
74571
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
74572
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xa1a20000 }
74573
  },
74574
/* add.l${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedSI */
74575
  {
74576
    { 0, 0, 0, 0 },
74577
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
74578
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xa1b20000 }
74579
  },
74580
/* add.l${G} ${Dsp-16-u16},$Dst32AnUnprefixedSI */
74581
  {
74582
    { 0, 0, 0, 0 },
74583
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
74584
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xb1b20000 }
74585
  },
74586
/* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
74587
  {
74588
    { 0, 0, 0, 0 },
74589
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74590
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xa1020000 }
74591
  },
74592
/* add.l${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
74593
  {
74594
    { 0, 0, 0, 0 },
74595
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74596
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xa1220000 }
74597
  },
74598
/* add.l${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
74599
  {
74600
    { 0, 0, 0, 0 },
74601
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74602
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xa1320000 }
74603
  },
74604
/* add.l${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
74605
  {
74606
    { 0, 0, 0, 0 },
74607
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74608
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xb1320000 }
74609
  },
74610
/* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
74611
  {
74612
    { 0, 0, 0, 0 },
74613
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74614
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_8_An_relative_Unprefixed_SI, { 0xa3020000 }
74615
  },
74616
/* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
74617
  {
74618
    { 0, 0, 0, 0 },
74619
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74620
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_8_An_relative_Unprefixed_SI, { 0xa3220000 }
74621
  },
74622
/* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
74623
  {
74624
    { 0, 0, 0, 0 },
74625
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74626
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_8_An_relative_Unprefixed_SI, { 0xa3320000 }
74627
  },
74628
/* add.l${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
74629
  {
74630
    { 0, 0, 0, 0 },
74631
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74632
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_8_An_relative_Unprefixed_SI, { 0xb3320000 }
74633
  },
74634
/* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
74635
  {
74636
    { 0, 0, 0, 0 },
74637
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74638
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_16_An_relative_Unprefixed_SI, { 0xa5020000 }
74639
  },
74640
/* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
74641
  {
74642
    { 0, 0, 0, 0 },
74643
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74644
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_16_An_relative_Unprefixed_SI, { 0xa5220000 }
74645
  },
74646
/* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
74647
  {
74648
    { 0, 0, 0, 0 },
74649
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74650
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_16_An_relative_Unprefixed_SI, { 0xa5320000 }
74651
  },
74652
/* add.l${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
74653
  {
74654
    { 0, 0, 0, 0 },
74655
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74656
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_16_An_relative_Unprefixed_SI, { 0xb5320000 }
74657
  },
74658
/* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
74659
  {
74660
    { 0, 0, 0, 0 },
74661
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74662
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_24_An_relative_Unprefixed_SI, { 0xa7020000 }
74663
  },
74664
/* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
74665
  {
74666
    { 0, 0, 0, 0 },
74667
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74668
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_24_An_relative_Unprefixed_SI, { 0xa7220000 }
74669
  },
74670
/* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
74671
  {
74672
    { 0, 0, 0, 0 },
74673
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74674
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_24_An_relative_Unprefixed_SI, { 0xa7320000 }
74675
  },
74676
/* add.l${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
74677
  {
74678
    { 0, 0, 0, 0 },
74679
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74680
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_24_An_relative_Unprefixed_SI, { 0xb7320000 }
74681
  },
74682
/* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
74683
  {
74684
    { 0, 0, 0, 0 },
74685
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
74686
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xa3820000 }
74687
  },
74688
/* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
74689
  {
74690
    { 0, 0, 0, 0 },
74691
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
74692
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xa3a20000 }
74693
  },
74694
/* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
74695
  {
74696
    { 0, 0, 0, 0 },
74697
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
74698
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xa3b20000 }
74699
  },
74700
/* add.l${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
74701
  {
74702
    { 0, 0, 0, 0 },
74703
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
74704
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xb3b20000 }
74705
  },
74706
/* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
74707
  {
74708
    { 0, 0, 0, 0 },
74709
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
74710
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xa5820000 }
74711
  },
74712
/* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
74713
  {
74714
    { 0, 0, 0, 0 },
74715
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
74716
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xa5a20000 }
74717
  },
74718
/* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
74719
  {
74720
    { 0, 0, 0, 0 },
74721
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
74722
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xa5b20000 }
74723
  },
74724
/* add.l${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
74725
  {
74726
    { 0, 0, 0, 0 },
74727
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
74728
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xb5b20000 }
74729
  },
74730
/* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
74731
  {
74732
    { 0, 0, 0, 0 },
74733
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
74734
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xa3c20000 }
74735
  },
74736
/* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
74737
  {
74738
    { 0, 0, 0, 0 },
74739
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
74740
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xa3e20000 }
74741
  },
74742
/* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
74743
  {
74744
    { 0, 0, 0, 0 },
74745
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
74746
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xa3f20000 }
74747
  },
74748
/* add.l${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
74749
  {
74750
    { 0, 0, 0, 0 },
74751
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
74752
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xb3f20000 }
74753
  },
74754
/* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
74755
  {
74756
    { 0, 0, 0, 0 },
74757
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
74758
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xa5c20000 }
74759
  },
74760
/* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
74761
  {
74762
    { 0, 0, 0, 0 },
74763
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
74764
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xa5e20000 }
74765
  },
74766
/* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
74767
  {
74768
    { 0, 0, 0, 0 },
74769
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
74770
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xa5f20000 }
74771
  },
74772
/* add.l${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
74773
  {
74774
    { 0, 0, 0, 0 },
74775
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
74776
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xb5f20000 }
74777
  },
74778
/* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
74779
  {
74780
    { 0, 0, 0, 0 },
74781
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
74782
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_16_absolute_Unprefixed_SI, { 0xa7c20000 }
74783
  },
74784
/* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
74785
  {
74786
    { 0, 0, 0, 0 },
74787
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
74788
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_16_absolute_Unprefixed_SI, { 0xa7e20000 }
74789
  },
74790
/* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
74791
  {
74792
    { 0, 0, 0, 0 },
74793
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
74794
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_16_absolute_Unprefixed_SI, { 0xa7f20000 }
74795
  },
74796
/* add.l${G} ${Dsp-16-u16},${Dsp-32-u16} */
74797
  {
74798
    { 0, 0, 0, 0 },
74799
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
74800
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_16_absolute_Unprefixed_SI, { 0xb7f20000 }
74801
  },
74802
/* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
74803
  {
74804
    { 0, 0, 0, 0 },
74805
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
74806
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_24_absolute_Unprefixed_SI, { 0xa7820000 }
74807
  },
74808
/* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
74809
  {
74810
    { 0, 0, 0, 0 },
74811
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
74812
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_24_absolute_Unprefixed_SI, { 0xa7a20000 }
74813
  },
74814
/* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
74815
  {
74816
    { 0, 0, 0, 0 },
74817
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
74818
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_24_absolute_Unprefixed_SI, { 0xa7b20000 }
74819
  },
74820
/* add.l${G} ${Dsp-16-u16},${Dsp-32-u24} */
74821
  {
74822
    { 0, 0, 0, 0 },
74823
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } },
74824
    & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_24_absolute_Unprefixed_SI, { 0xb7b20000 }
74825
  },
74826
/* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
74827
  {
74828
    { 0, 0, 0, 0 },
74829
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
74830
    & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xb9020000 }
74831
  },
74832
/* add.l${G} ${Dsp-16-u24},$Dst32RnUnprefixedSI */
74833
  {
74834
    { 0, 0, 0, 0 },
74835
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
74836
    & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xb9220000 }
74837
  },
74838
/* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
74839
  {
74840
    { 0, 0, 0, 0 },
74841
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
74842
    & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xb1820000 }
74843
  },
74844
/* add.l${G} ${Dsp-16-u24},$Dst32AnUnprefixedSI */
74845
  {
74846
    { 0, 0, 0, 0 },
74847
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
74848
    & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xb1a20000 }
74849
  },
74850
/* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
74851
  {
74852
    { 0, 0, 0, 0 },
74853
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74854
    & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xb1020000 }
74855
  },
74856
/* add.l${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
74857
  {
74858
    { 0, 0, 0, 0 },
74859
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74860
    & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xb1220000 }
74861
  },
74862
/* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
74863
  {
74864
    { 0, 0, 0, 0 },
74865
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74866
    & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_8_An_relative_Unprefixed_SI, { 0xb3020000 }
74867
  },
74868
/* add.l${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
74869
  {
74870
    { 0, 0, 0, 0 },
74871
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74872
    & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_8_An_relative_Unprefixed_SI, { 0xb3220000 }
74873
  },
74874
/* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
74875
  {
74876
    { 0, 0, 0, 0 },
74877
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74878
    & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_16_An_relative_Unprefixed_SI, { 0xb5020000 }
74879
  },
74880
/* add.l${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
74881
  {
74882
    { 0, 0, 0, 0 },
74883
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74884
    & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_16_An_relative_Unprefixed_SI, { 0xb5220000 }
74885
  },
74886
/* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
74887
  {
74888
    { 0, 0, 0, 0 },
74889
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74890
    & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_24_An_relative_Unprefixed_SI, { 0xb7020000 }
74891
  },
74892
/* add.l${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
74893
  {
74894
    { 0, 0, 0, 0 },
74895
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
74896
    & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_24_An_relative_Unprefixed_SI, { 0xb7220000 }
74897
  },
74898
/* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
74899
  {
74900
    { 0, 0, 0, 0 },
74901
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
74902
    & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_8_SB_relative_Unprefixed_SI, { 0xb3820000 }
74903
  },
74904
/* add.l${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
74905
  {
74906
    { 0, 0, 0, 0 },
74907
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
74908
    & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_8_SB_relative_Unprefixed_SI, { 0xb3a20000 }
74909
  },
74910
/* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
74911
  {
74912
    { 0, 0, 0, 0 },
74913
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
74914
    & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_16_SB_relative_Unprefixed_SI, { 0xb5820000 }
74915
  },
74916
/* add.l${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
74917
  {
74918
    { 0, 0, 0, 0 },
74919
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
74920
    & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_16_SB_relative_Unprefixed_SI, { 0xb5a20000 }
74921
  },
74922
/* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
74923
  {
74924
    { 0, 0, 0, 0 },
74925
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
74926
    & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_8_FB_relative_Unprefixed_SI, { 0xb3c20000 }
74927
  },
74928
/* add.l${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
74929
  {
74930
    { 0, 0, 0, 0 },
74931
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
74932
    & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_8_FB_relative_Unprefixed_SI, { 0xb3e20000 }
74933
  },
74934
/* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
74935
  {
74936
    { 0, 0, 0, 0 },
74937
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
74938
    & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_16_FB_relative_Unprefixed_SI, { 0xb5c20000 }
74939
  },
74940
/* add.l${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
74941
  {
74942
    { 0, 0, 0, 0 },
74943
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
74944
    & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_16_FB_relative_Unprefixed_SI, { 0xb5e20000 }
74945
  },
74946
/* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
74947
  {
74948
    { 0, 0, 0, 0 },
74949
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
74950
    & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_16_absolute_Unprefixed_SI, { 0xb7c20000 }
74951
  },
74952
/* add.l${G} ${Dsp-16-u24},${Dsp-40-u16} */
74953
  {
74954
    { 0, 0, 0, 0 },
74955
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } },
74956
    & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_16_absolute_Unprefixed_SI, { 0xb7e20000 }
74957
  },
74958
/* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
74959
  {
74960
    { 0, 0, 0, 0 },
74961
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
74962
    & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_24_absolute_Unprefixed_SI, { 0xb7820000 }
74963
  },
74964
/* add.l${G} ${Dsp-16-u24},${Dsp-40-u24} */
74965
  {
74966
    { 0, 0, 0, 0 },
74967
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } },
74968
    & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_24_absolute_Unprefixed_SI, { 0xb7a20000 }
74969
  },
74970
/* add.l${G} $Src32RnUnprefixedSI,$Dst32RnUnprefixedSI */
74971
  {
74972
    { 0, 0, 0, 0 },
74973
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
74974
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xc902 }
74975
  },
74976
/* add.l${G} $Src32AnUnprefixedSI,$Dst32RnUnprefixedSI */
74977
  {
74978
    { 0, 0, 0, 0 },
74979
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
74980
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0x8922 }
74981
  },
74982
/* add.l${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
74983
  {
74984
    { 0, 0, 0, 0 },
74985
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } },
74986
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0x8902 }
74987
  },
74988
/* add.l${G} $Src32RnUnprefixedSI,$Dst32AnUnprefixedSI */
74989
  {
74990
    { 0, 0, 0, 0 },
74991
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
74992
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xc182 }
74993
  },
74994
/* add.l${G} $Src32AnUnprefixedSI,$Dst32AnUnprefixedSI */
74995
  {
74996
    { 0, 0, 0, 0 },
74997
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
74998
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0x81a2 }
74999
  },
75000
/* add.l${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
75001
  {
75002
    { 0, 0, 0, 0 },
75003
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } },
75004
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0x8182 }
75005
  },
75006
/* add.l${G} $Src32RnUnprefixedSI,[$Dst32AnUnprefixed] */
75007
  {
75008
    { 0, 0, 0, 0 },
75009
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75010
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xc102 }
75011
  },
75012
/* add.l${G} $Src32AnUnprefixedSI,[$Dst32AnUnprefixed] */
75013
  {
75014
    { 0, 0, 0, 0 },
75015
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75016
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0x8122 }
75017
  },
75018
/* add.l${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
75019
  {
75020
    { 0, 0, 0, 0 },
75021
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75022
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0x8102 }
75023
  },
75024
/* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
75025
  {
75026
    { 0, 0, 0, 0 },
75027
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75028
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_8_An_relative_Unprefixed_SI, { 0xc30200 }
75029
  },
75030
/* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
75031
  {
75032
    { 0, 0, 0, 0 },
75033
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75034
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_8_An_relative_Unprefixed_SI, { 0x832200 }
75035
  },
75036
/* add.l${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
75037
  {
75038
    { 0, 0, 0, 0 },
75039
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75040
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_8_An_relative_Unprefixed_SI, { 0x830200 }
75041
  },
75042
/* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
75043
  {
75044
    { 0, 0, 0, 0 },
75045
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75046
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_16_An_relative_Unprefixed_SI, { 0xc5020000 }
75047
  },
75048
/* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
75049
  {
75050
    { 0, 0, 0, 0 },
75051
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75052
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_16_An_relative_Unprefixed_SI, { 0x85220000 }
75053
  },
75054
/* add.l${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
75055
  {
75056
    { 0, 0, 0, 0 },
75057
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75058
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_16_An_relative_Unprefixed_SI, { 0x85020000 }
75059
  },
75060
/* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
75061
  {
75062
    { 0, 0, 0, 0 },
75063
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75064
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_24_An_relative_Unprefixed_SI, { 0xc7020000 }
75065
  },
75066
/* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
75067
  {
75068
    { 0, 0, 0, 0 },
75069
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75070
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_24_An_relative_Unprefixed_SI, { 0x87220000 }
75071
  },
75072
/* add.l${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
75073
  {
75074
    { 0, 0, 0, 0 },
75075
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75076
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_24_An_relative_Unprefixed_SI, { 0x87020000 }
75077
  },
75078
/* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-u8}[sb] */
75079
  {
75080
    { 0, 0, 0, 0 },
75081
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
75082
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_8_SB_relative_Unprefixed_SI, { 0xc38200 }
75083
  },
75084
/* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-u8}[sb] */
75085
  {
75086
    { 0, 0, 0, 0 },
75087
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
75088
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_8_SB_relative_Unprefixed_SI, { 0x83a200 }
75089
  },
75090
/* add.l${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
75091
  {
75092
    { 0, 0, 0, 0 },
75093
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
75094
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_8_SB_relative_Unprefixed_SI, { 0x838200 }
75095
  },
75096
/* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16}[sb] */
75097
  {
75098
    { 0, 0, 0, 0 },
75099
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
75100
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_16_SB_relative_Unprefixed_SI, { 0xc5820000 }
75101
  },
75102
/* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16}[sb] */
75103
  {
75104
    { 0, 0, 0, 0 },
75105
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
75106
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_16_SB_relative_Unprefixed_SI, { 0x85a20000 }
75107
  },
75108
/* add.l${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
75109
  {
75110
    { 0, 0, 0, 0 },
75111
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
75112
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_16_SB_relative_Unprefixed_SI, { 0x85820000 }
75113
  },
75114
/* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-s8}[fb] */
75115
  {
75116
    { 0, 0, 0, 0 },
75117
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
75118
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_8_FB_relative_Unprefixed_SI, { 0xc3c200 }
75119
  },
75120
/* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-s8}[fb] */
75121
  {
75122
    { 0, 0, 0, 0 },
75123
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
75124
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_8_FB_relative_Unprefixed_SI, { 0x83e200 }
75125
  },
75126
/* add.l${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
75127
  {
75128
    { 0, 0, 0, 0 },
75129
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
75130
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_8_FB_relative_Unprefixed_SI, { 0x83c200 }
75131
  },
75132
/* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-s16}[fb] */
75133
  {
75134
    { 0, 0, 0, 0 },
75135
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
75136
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_16_FB_relative_Unprefixed_SI, { 0xc5c20000 }
75137
  },
75138
/* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-s16}[fb] */
75139
  {
75140
    { 0, 0, 0, 0 },
75141
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
75142
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_16_FB_relative_Unprefixed_SI, { 0x85e20000 }
75143
  },
75144
/* add.l${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
75145
  {
75146
    { 0, 0, 0, 0 },
75147
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
75148
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_16_FB_relative_Unprefixed_SI, { 0x85c20000 }
75149
  },
75150
/* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16} */
75151
  {
75152
    { 0, 0, 0, 0 },
75153
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U16), 0 } },
75154
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_16_absolute_Unprefixed_SI, { 0xc7c20000 }
75155
  },
75156
/* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16} */
75157
  {
75158
    { 0, 0, 0, 0 },
75159
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U16), 0 } },
75160
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_16_absolute_Unprefixed_SI, { 0x87e20000 }
75161
  },
75162
/* add.l${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
75163
  {
75164
    { 0, 0, 0, 0 },
75165
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } },
75166
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_16_absolute_Unprefixed_SI, { 0x87c20000 }
75167
  },
75168
/* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-u24} */
75169
  {
75170
    { 0, 0, 0, 0 },
75171
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U24), 0 } },
75172
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_24_absolute_Unprefixed_SI, { 0xc7820000 }
75173
  },
75174
/* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-u24} */
75175
  {
75176
    { 0, 0, 0, 0 },
75177
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U24), 0 } },
75178
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_24_absolute_Unprefixed_SI, { 0x87a20000 }
75179
  },
75180
/* add.l${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
75181
  {
75182
    { 0, 0, 0, 0 },
75183
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } },
75184
    & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_24_absolute_Unprefixed_SI, { 0x87820000 }
75185
  },
75186
/* add.b${S} ${SrcDst16-r0l-r0h-S-normal} */
75187
  {
75188
    { 0, 0, 0, 0 },
75189
    { { MNEM, OP (S), ' ', OP (SRCDST16_R0L_R0H_S_NORMAL), 0 } },
75190
    & ifmt_or16_b_S_r0l_r0h_srcdst16_r0l_r0h_S_derived, { 0x20 }
75191
  },
75192
/* add.b${S} ${Dsp-8-u8}[sb],${Dst16RnQI-S} */
75193
  {
75194
    { 0, 0, 0, 0 },
75195
    { { MNEM, OP (S), ' ', OP (DSP_8_U8), '[', 's', 'b', ']', ',', OP (DST16RNQI_S), 0 } },
75196
    & ifmt_or16_b_S_src2_src16_2_S_8_SB_relative_QI, { 0x2100 }
75197
  },
75198
/* add.b${S} ${Dsp-8-s8}[fb],${Dst16RnQI-S} */
75199
  {
75200
    { 0, 0, 0, 0 },
75201
    { { MNEM, OP (S), ' ', OP (DSP_8_S8), '[', 'f', 'b', ']', ',', OP (DST16RNQI_S), 0 } },
75202
    & ifmt_or16_b_S_src2_src16_2_S_8_FB_relative_QI, { 0x2200 }
75203
  },
75204
/* add.b${S} ${Dsp-8-u16},${Dst16RnQI-S} */
75205
  {
75206
    { 0, 0, 0, 0 },
75207
    { { MNEM, OP (S), ' ', OP (DSP_8_U16), ',', OP (DST16RNQI_S), 0 } },
75208
    & ifmt_or16_b_S_src2_src16_2_S_16_absolute_QI, { 0x230000 }
75209
  },
75210
/* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
75211
  {
75212
    { 0, 0, 0, 0 },
75213
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
75214
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x990800 }
75215
  },
75216
/* add.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */
75217
  {
75218
    { 0, 0, 0, 0 },
75219
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
75220
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x992800 }
75221
  },
75222
/* add.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */
75223
  {
75224
    { 0, 0, 0, 0 },
75225
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
75226
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x993800 }
75227
  },
75228
/* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
75229
  {
75230
    { 0, 0, 0, 0 },
75231
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
75232
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x918800 }
75233
  },
75234
/* add.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */
75235
  {
75236
    { 0, 0, 0, 0 },
75237
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
75238
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x91a800 }
75239
  },
75240
/* add.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */
75241
  {
75242
    { 0, 0, 0, 0 },
75243
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
75244
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x91b800 }
75245
  },
75246
/* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
75247
  {
75248
    { 0, 0, 0, 0 },
75249
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75250
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x910800 }
75251
  },
75252
/* add.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
75253
  {
75254
    { 0, 0, 0, 0 },
75255
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75256
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x912800 }
75257
  },
75258
/* add.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
75259
  {
75260
    { 0, 0, 0, 0 },
75261
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75262
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x913800 }
75263
  },
75264
/* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
75265
  {
75266
    { 0, 0, 0, 0 },
75267
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75268
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x93080000 }
75269
  },
75270
/* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
75271
  {
75272
    { 0, 0, 0, 0 },
75273
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75274
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x93280000 }
75275
  },
75276
/* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
75277
  {
75278
    { 0, 0, 0, 0 },
75279
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75280
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x93380000 }
75281
  },
75282
/* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
75283
  {
75284
    { 0, 0, 0, 0 },
75285
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75286
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x95080000 }
75287
  },
75288
/* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
75289
  {
75290
    { 0, 0, 0, 0 },
75291
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75292
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x95280000 }
75293
  },
75294
/* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
75295
  {
75296
    { 0, 0, 0, 0 },
75297
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75298
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x95380000 }
75299
  },
75300
/* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
75301
  {
75302
    { 0, 0, 0, 0 },
75303
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75304
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x97080000 }
75305
  },
75306
/* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
75307
  {
75308
    { 0, 0, 0, 0 },
75309
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75310
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x97280000 }
75311
  },
75312
/* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
75313
  {
75314
    { 0, 0, 0, 0 },
75315
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75316
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x97380000 }
75317
  },
75318
/* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
75319
  {
75320
    { 0, 0, 0, 0 },
75321
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
75322
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93880000 }
75323
  },
75324
/* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
75325
  {
75326
    { 0, 0, 0, 0 },
75327
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
75328
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93a80000 }
75329
  },
75330
/* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
75331
  {
75332
    { 0, 0, 0, 0 },
75333
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
75334
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93b80000 }
75335
  },
75336
/* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
75337
  {
75338
    { 0, 0, 0, 0 },
75339
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
75340
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95880000 }
75341
  },
75342
/* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
75343
  {
75344
    { 0, 0, 0, 0 },
75345
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
75346
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95a80000 }
75347
  },
75348
/* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
75349
  {
75350
    { 0, 0, 0, 0 },
75351
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
75352
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95b80000 }
75353
  },
75354
/* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
75355
  {
75356
    { 0, 0, 0, 0 },
75357
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
75358
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93c80000 }
75359
  },
75360
/* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
75361
  {
75362
    { 0, 0, 0, 0 },
75363
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
75364
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93e80000 }
75365
  },
75366
/* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
75367
  {
75368
    { 0, 0, 0, 0 },
75369
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
75370
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93f80000 }
75371
  },
75372
/* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
75373
  {
75374
    { 0, 0, 0, 0 },
75375
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
75376
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95c80000 }
75377
  },
75378
/* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
75379
  {
75380
    { 0, 0, 0, 0 },
75381
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
75382
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95e80000 }
75383
  },
75384
/* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
75385
  {
75386
    { 0, 0, 0, 0 },
75387
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
75388
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95f80000 }
75389
  },
75390
/* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
75391
  {
75392
    { 0, 0, 0, 0 },
75393
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
75394
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97c80000 }
75395
  },
75396
/* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
75397
  {
75398
    { 0, 0, 0, 0 },
75399
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
75400
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97e80000 }
75401
  },
75402
/* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
75403
  {
75404
    { 0, 0, 0, 0 },
75405
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
75406
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97f80000 }
75407
  },
75408
/* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
75409
  {
75410
    { 0, 0, 0, 0 },
75411
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
75412
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97880000 }
75413
  },
75414
/* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
75415
  {
75416
    { 0, 0, 0, 0 },
75417
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } },
75418
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97a80000 }
75419
  },
75420
/* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
75421
  {
75422
    { 0, 0, 0, 0 },
75423
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } },
75424
    & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97b80000 }
75425
  },
75426
/* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
75427
  {
75428
    { 0, 0, 0, 0 },
75429
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
75430
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa9080000 }
75431
  },
75432
/* add.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */
75433
  {
75434
    { 0, 0, 0, 0 },
75435
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
75436
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa9280000 }
75437
  },
75438
/* add.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */
75439
  {
75440
    { 0, 0, 0, 0 },
75441
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
75442
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa9380000 }
75443
  },
75444
/* add.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */
75445
  {
75446
    { 0, 0, 0, 0 },
75447
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
75448
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb9380000 }
75449
  },
75450
/* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
75451
  {
75452
    { 0, 0, 0, 0 },
75453
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
75454
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1880000 }
75455
  },
75456
/* add.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */
75457
  {
75458
    { 0, 0, 0, 0 },
75459
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
75460
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1a80000 }
75461
  },
75462
/* add.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */
75463
  {
75464
    { 0, 0, 0, 0 },
75465
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
75466
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1b80000 }
75467
  },
75468
/* add.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */
75469
  {
75470
    { 0, 0, 0, 0 },
75471
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
75472
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1b80000 }
75473
  },
75474
/* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
75475
  {
75476
    { 0, 0, 0, 0 },
75477
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75478
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa1080000 }
75479
  },
75480
/* add.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
75481
  {
75482
    { 0, 0, 0, 0 },
75483
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75484
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa1280000 }
75485
  },
75486
/* add.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
75487
  {
75488
    { 0, 0, 0, 0 },
75489
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75490
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa1380000 }
75491
  },
75492
/* add.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
75493
  {
75494
    { 0, 0, 0, 0 },
75495
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75496
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb1380000 }
75497
  },
75498
/* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
75499
  {
75500
    { 0, 0, 0, 0 },
75501
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75502
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa3080000 }
75503
  },
75504
/* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
75505
  {
75506
    { 0, 0, 0, 0 },
75507
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75508
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa3280000 }
75509
  },
75510
/* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
75511
  {
75512
    { 0, 0, 0, 0 },
75513
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75514
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa3380000 }
75515
  },
75516
/* add.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
75517
  {
75518
    { 0, 0, 0, 0 },
75519
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75520
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xb3380000 }
75521
  },
75522
/* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
75523
  {
75524
    { 0, 0, 0, 0 },
75525
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75526
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa5080000 }
75527
  },
75528
/* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
75529
  {
75530
    { 0, 0, 0, 0 },
75531
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75532
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa5280000 }
75533
  },
75534
/* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
75535
  {
75536
    { 0, 0, 0, 0 },
75537
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75538
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa5380000 }
75539
  },
75540
/* add.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
75541
  {
75542
    { 0, 0, 0, 0 },
75543
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75544
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xb5380000 }
75545
  },
75546
/* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
75547
  {
75548
    { 0, 0, 0, 0 },
75549
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75550
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa7080000 }
75551
  },
75552
/* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
75553
  {
75554
    { 0, 0, 0, 0 },
75555
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75556
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa7280000 }
75557
  },
75558
/* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
75559
  {
75560
    { 0, 0, 0, 0 },
75561
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75562
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa7380000 }
75563
  },
75564
/* add.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
75565
  {
75566
    { 0, 0, 0, 0 },
75567
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75568
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xb7380000 }
75569
  },
75570
/* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
75571
  {
75572
    { 0, 0, 0, 0 },
75573
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
75574
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3880000 }
75575
  },
75576
/* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
75577
  {
75578
    { 0, 0, 0, 0 },
75579
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
75580
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3a80000 }
75581
  },
75582
/* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
75583
  {
75584
    { 0, 0, 0, 0 },
75585
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
75586
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3b80000 }
75587
  },
75588
/* add.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
75589
  {
75590
    { 0, 0, 0, 0 },
75591
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
75592
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xb3b80000 }
75593
  },
75594
/* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
75595
  {
75596
    { 0, 0, 0, 0 },
75597
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
75598
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5880000 }
75599
  },
75600
/* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
75601
  {
75602
    { 0, 0, 0, 0 },
75603
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
75604
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5a80000 }
75605
  },
75606
/* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
75607
  {
75608
    { 0, 0, 0, 0 },
75609
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
75610
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5b80000 }
75611
  },
75612
/* add.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
75613
  {
75614
    { 0, 0, 0, 0 },
75615
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
75616
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xb5b80000 }
75617
  },
75618
/* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
75619
  {
75620
    { 0, 0, 0, 0 },
75621
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
75622
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3c80000 }
75623
  },
75624
/* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
75625
  {
75626
    { 0, 0, 0, 0 },
75627
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
75628
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3e80000 }
75629
  },
75630
/* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
75631
  {
75632
    { 0, 0, 0, 0 },
75633
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
75634
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3f80000 }
75635
  },
75636
/* add.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
75637
  {
75638
    { 0, 0, 0, 0 },
75639
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
75640
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xb3f80000 }
75641
  },
75642
/* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
75643
  {
75644
    { 0, 0, 0, 0 },
75645
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
75646
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5c80000 }
75647
  },
75648
/* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
75649
  {
75650
    { 0, 0, 0, 0 },
75651
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
75652
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5e80000 }
75653
  },
75654
/* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
75655
  {
75656
    { 0, 0, 0, 0 },
75657
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
75658
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5f80000 }
75659
  },
75660
/* add.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
75661
  {
75662
    { 0, 0, 0, 0 },
75663
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
75664
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xb5f80000 }
75665
  },
75666
/* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
75667
  {
75668
    { 0, 0, 0, 0 },
75669
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
75670
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7c80000 }
75671
  },
75672
/* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
75673
  {
75674
    { 0, 0, 0, 0 },
75675
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
75676
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7e80000 }
75677
  },
75678
/* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
75679
  {
75680
    { 0, 0, 0, 0 },
75681
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
75682
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7f80000 }
75683
  },
75684
/* add.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
75685
  {
75686
    { 0, 0, 0, 0 },
75687
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
75688
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xb7f80000 }
75689
  },
75690
/* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
75691
  {
75692
    { 0, 0, 0, 0 },
75693
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
75694
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7880000 }
75695
  },
75696
/* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
75697
  {
75698
    { 0, 0, 0, 0 },
75699
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
75700
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7a80000 }
75701
  },
75702
/* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
75703
  {
75704
    { 0, 0, 0, 0 },
75705
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
75706
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7b80000 }
75707
  },
75708
/* add.w${G} ${Dsp-16-u16},${Dsp-32-u24} */
75709
  {
75710
    { 0, 0, 0, 0 },
75711
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } },
75712
    & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xb7b80000 }
75713
  },
75714
/* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
75715
  {
75716
    { 0, 0, 0, 0 },
75717
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
75718
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb9080000 }
75719
  },
75720
/* add.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */
75721
  {
75722
    { 0, 0, 0, 0 },
75723
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
75724
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb9280000 }
75725
  },
75726
/* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
75727
  {
75728
    { 0, 0, 0, 0 },
75729
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
75730
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1880000 }
75731
  },
75732
/* add.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */
75733
  {
75734
    { 0, 0, 0, 0 },
75735
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
75736
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1a80000 }
75737
  },
75738
/* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
75739
  {
75740
    { 0, 0, 0, 0 },
75741
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75742
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb1080000 }
75743
  },
75744
/* add.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
75745
  {
75746
    { 0, 0, 0, 0 },
75747
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75748
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb1280000 }
75749
  },
75750
/* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
75751
  {
75752
    { 0, 0, 0, 0 },
75753
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75754
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_An_relative_Unprefixed_HI, { 0xb3080000 }
75755
  },
75756
/* add.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
75757
  {
75758
    { 0, 0, 0, 0 },
75759
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75760
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_An_relative_Unprefixed_HI, { 0xb3280000 }
75761
  },
75762
/* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
75763
  {
75764
    { 0, 0, 0, 0 },
75765
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75766
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_An_relative_Unprefixed_HI, { 0xb5080000 }
75767
  },
75768
/* add.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
75769
  {
75770
    { 0, 0, 0, 0 },
75771
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75772
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_An_relative_Unprefixed_HI, { 0xb5280000 }
75773
  },
75774
/* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
75775
  {
75776
    { 0, 0, 0, 0 },
75777
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75778
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_24_An_relative_Unprefixed_HI, { 0xb7080000 }
75779
  },
75780
/* add.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
75781
  {
75782
    { 0, 0, 0, 0 },
75783
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75784
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_24_An_relative_Unprefixed_HI, { 0xb7280000 }
75785
  },
75786
/* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
75787
  {
75788
    { 0, 0, 0, 0 },
75789
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
75790
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_SB_relative_Unprefixed_HI, { 0xb3880000 }
75791
  },
75792
/* add.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
75793
  {
75794
    { 0, 0, 0, 0 },
75795
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
75796
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_SB_relative_Unprefixed_HI, { 0xb3a80000 }
75797
  },
75798
/* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
75799
  {
75800
    { 0, 0, 0, 0 },
75801
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
75802
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_SB_relative_Unprefixed_HI, { 0xb5880000 }
75803
  },
75804
/* add.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
75805
  {
75806
    { 0, 0, 0, 0 },
75807
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
75808
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_SB_relative_Unprefixed_HI, { 0xb5a80000 }
75809
  },
75810
/* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
75811
  {
75812
    { 0, 0, 0, 0 },
75813
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
75814
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_FB_relative_Unprefixed_HI, { 0xb3c80000 }
75815
  },
75816
/* add.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
75817
  {
75818
    { 0, 0, 0, 0 },
75819
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
75820
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_FB_relative_Unprefixed_HI, { 0xb3e80000 }
75821
  },
75822
/* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
75823
  {
75824
    { 0, 0, 0, 0 },
75825
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
75826
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_FB_relative_Unprefixed_HI, { 0xb5c80000 }
75827
  },
75828
/* add.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
75829
  {
75830
    { 0, 0, 0, 0 },
75831
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
75832
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_FB_relative_Unprefixed_HI, { 0xb5e80000 }
75833
  },
75834
/* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
75835
  {
75836
    { 0, 0, 0, 0 },
75837
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
75838
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_absolute_Unprefixed_HI, { 0xb7c80000 }
75839
  },
75840
/* add.w${G} ${Dsp-16-u24},${Dsp-40-u16} */
75841
  {
75842
    { 0, 0, 0, 0 },
75843
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } },
75844
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_absolute_Unprefixed_HI, { 0xb7e80000 }
75845
  },
75846
/* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
75847
  {
75848
    { 0, 0, 0, 0 },
75849
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
75850
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_24_absolute_Unprefixed_HI, { 0xb7880000 }
75851
  },
75852
/* add.w${G} ${Dsp-16-u24},${Dsp-40-u24} */
75853
  {
75854
    { 0, 0, 0, 0 },
75855
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } },
75856
    & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_24_absolute_Unprefixed_HI, { 0xb7a80000 }
75857
  },
75858
/* add.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */
75859
  {
75860
    { 0, 0, 0, 0 },
75861
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
75862
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xc908 }
75863
  },
75864
/* add.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */
75865
  {
75866
    { 0, 0, 0, 0 },
75867
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
75868
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x8928 }
75869
  },
75870
/* add.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
75871
  {
75872
    { 0, 0, 0, 0 },
75873
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } },
75874
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x8908 }
75875
  },
75876
/* add.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */
75877
  {
75878
    { 0, 0, 0, 0 },
75879
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
75880
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xc188 }
75881
  },
75882
/* add.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */
75883
  {
75884
    { 0, 0, 0, 0 },
75885
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
75886
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x81a8 }
75887
  },
75888
/* add.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
75889
  {
75890
    { 0, 0, 0, 0 },
75891
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } },
75892
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x8188 }
75893
  },
75894
/* add.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */
75895
  {
75896
    { 0, 0, 0, 0 },
75897
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75898
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xc108 }
75899
  },
75900
/* add.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */
75901
  {
75902
    { 0, 0, 0, 0 },
75903
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75904
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x8128 }
75905
  },
75906
/* add.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
75907
  {
75908
    { 0, 0, 0, 0 },
75909
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75910
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x8108 }
75911
  },
75912
/* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
75913
  {
75914
    { 0, 0, 0, 0 },
75915
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75916
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0xc30800 }
75917
  },
75918
/* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
75919
  {
75920
    { 0, 0, 0, 0 },
75921
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75922
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0x832800 }
75923
  },
75924
/* add.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
75925
  {
75926
    { 0, 0, 0, 0 },
75927
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75928
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0x830800 }
75929
  },
75930
/* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
75931
  {
75932
    { 0, 0, 0, 0 },
75933
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75934
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0xc5080000 }
75935
  },
75936
/* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
75937
  {
75938
    { 0, 0, 0, 0 },
75939
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75940
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0x85280000 }
75941
  },
75942
/* add.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
75943
  {
75944
    { 0, 0, 0, 0 },
75945
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75946
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0x85080000 }
75947
  },
75948
/* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
75949
  {
75950
    { 0, 0, 0, 0 },
75951
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75952
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0xc7080000 }
75953
  },
75954
/* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
75955
  {
75956
    { 0, 0, 0, 0 },
75957
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75958
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0x87280000 }
75959
  },
75960
/* add.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
75961
  {
75962
    { 0, 0, 0, 0 },
75963
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
75964
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0x87080000 }
75965
  },
75966
/* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */
75967
  {
75968
    { 0, 0, 0, 0 },
75969
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
75970
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0xc38800 }
75971
  },
75972
/* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */
75973
  {
75974
    { 0, 0, 0, 0 },
75975
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
75976
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0x83a800 }
75977
  },
75978
/* add.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
75979
  {
75980
    { 0, 0, 0, 0 },
75981
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
75982
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0x838800 }
75983
  },
75984
/* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */
75985
  {
75986
    { 0, 0, 0, 0 },
75987
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
75988
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0xc5880000 }
75989
  },
75990
/* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */
75991
  {
75992
    { 0, 0, 0, 0 },
75993
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
75994
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0x85a80000 }
75995
  },
75996
/* add.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
75997
  {
75998
    { 0, 0, 0, 0 },
75999
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
76000
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0x85880000 }
76001
  },
76002
/* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */
76003
  {
76004
    { 0, 0, 0, 0 },
76005
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
76006
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0xc3c800 }
76007
  },
76008
/* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */
76009
  {
76010
    { 0, 0, 0, 0 },
76011
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
76012
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83e800 }
76013
  },
76014
/* add.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
76015
  {
76016
    { 0, 0, 0, 0 },
76017
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
76018
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83c800 }
76019
  },
76020
/* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */
76021
  {
76022
    { 0, 0, 0, 0 },
76023
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
76024
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0xc5c80000 }
76025
  },
76026
/* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */
76027
  {
76028
    { 0, 0, 0, 0 },
76029
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
76030
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85e80000 }
76031
  },
76032
/* add.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
76033
  {
76034
    { 0, 0, 0, 0 },
76035
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
76036
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85c80000 }
76037
  },
76038
/* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */
76039
  {
76040
    { 0, 0, 0, 0 },
76041
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), 0 } },
76042
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0xc7c80000 }
76043
  },
76044
/* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */
76045
  {
76046
    { 0, 0, 0, 0 },
76047
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), 0 } },
76048
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0x87e80000 }
76049
  },
76050
/* add.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
76051
  {
76052
    { 0, 0, 0, 0 },
76053
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } },
76054
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0x87c80000 }
76055
  },
76056
/* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */
76057
  {
76058
    { 0, 0, 0, 0 },
76059
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U24), 0 } },
76060
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0xc7880000 }
76061
  },
76062
/* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */
76063
  {
76064
    { 0, 0, 0, 0 },
76065
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U24), 0 } },
76066
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0x87a80000 }
76067
  },
76068
/* add.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
76069
  {
76070
    { 0, 0, 0, 0 },
76071
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } },
76072
    & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0x87880000 }
76073
  },
76074
/* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
76075
  {
76076
    { 0, 0, 0, 0 },
76077
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
76078
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x980800 }
76079
  },
76080
/* add.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */
76081
  {
76082
    { 0, 0, 0, 0 },
76083
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
76084
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x982800 }
76085
  },
76086
/* add.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */
76087
  {
76088
    { 0, 0, 0, 0 },
76089
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
76090
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x983800 }
76091
  },
76092
/* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
76093
  {
76094
    { 0, 0, 0, 0 },
76095
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
76096
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x908800 }
76097
  },
76098
/* add.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */
76099
  {
76100
    { 0, 0, 0, 0 },
76101
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
76102
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x90a800 }
76103
  },
76104
/* add.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */
76105
  {
76106
    { 0, 0, 0, 0 },
76107
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
76108
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x90b800 }
76109
  },
76110
/* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
76111
  {
76112
    { 0, 0, 0, 0 },
76113
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76114
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x900800 }
76115
  },
76116
/* add.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
76117
  {
76118
    { 0, 0, 0, 0 },
76119
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76120
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x902800 }
76121
  },
76122
/* add.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
76123
  {
76124
    { 0, 0, 0, 0 },
76125
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76126
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x903800 }
76127
  },
76128
/* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
76129
  {
76130
    { 0, 0, 0, 0 },
76131
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76132
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x92080000 }
76133
  },
76134
/* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
76135
  {
76136
    { 0, 0, 0, 0 },
76137
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76138
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x92280000 }
76139
  },
76140
/* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
76141
  {
76142
    { 0, 0, 0, 0 },
76143
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76144
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x92380000 }
76145
  },
76146
/* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
76147
  {
76148
    { 0, 0, 0, 0 },
76149
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76150
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x94080000 }
76151
  },
76152
/* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
76153
  {
76154
    { 0, 0, 0, 0 },
76155
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76156
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x94280000 }
76157
  },
76158
/* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
76159
  {
76160
    { 0, 0, 0, 0 },
76161
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76162
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x94380000 }
76163
  },
76164
/* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
76165
  {
76166
    { 0, 0, 0, 0 },
76167
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76168
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x96080000 }
76169
  },
76170
/* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
76171
  {
76172
    { 0, 0, 0, 0 },
76173
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76174
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x96280000 }
76175
  },
76176
/* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
76177
  {
76178
    { 0, 0, 0, 0 },
76179
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76180
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x96380000 }
76181
  },
76182
/* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
76183
  {
76184
    { 0, 0, 0, 0 },
76185
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
76186
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92880000 }
76187
  },
76188
/* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
76189
  {
76190
    { 0, 0, 0, 0 },
76191
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
76192
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92a80000 }
76193
  },
76194
/* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
76195
  {
76196
    { 0, 0, 0, 0 },
76197
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
76198
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92b80000 }
76199
  },
76200
/* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
76201
  {
76202
    { 0, 0, 0, 0 },
76203
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
76204
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94880000 }
76205
  },
76206
/* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
76207
  {
76208
    { 0, 0, 0, 0 },
76209
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
76210
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94a80000 }
76211
  },
76212
/* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
76213
  {
76214
    { 0, 0, 0, 0 },
76215
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
76216
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94b80000 }
76217
  },
76218
/* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
76219
  {
76220
    { 0, 0, 0, 0 },
76221
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
76222
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92c80000 }
76223
  },
76224
/* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
76225
  {
76226
    { 0, 0, 0, 0 },
76227
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
76228
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92e80000 }
76229
  },
76230
/* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
76231
  {
76232
    { 0, 0, 0, 0 },
76233
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
76234
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92f80000 }
76235
  },
76236
/* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
76237
  {
76238
    { 0, 0, 0, 0 },
76239
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
76240
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94c80000 }
76241
  },
76242
/* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
76243
  {
76244
    { 0, 0, 0, 0 },
76245
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
76246
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94e80000 }
76247
  },
76248
/* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
76249
  {
76250
    { 0, 0, 0, 0 },
76251
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } },
76252
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94f80000 }
76253
  },
76254
/* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
76255
  {
76256
    { 0, 0, 0, 0 },
76257
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } },
76258
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96c80000 }
76259
  },
76260
/* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
76261
  {
76262
    { 0, 0, 0, 0 },
76263
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
76264
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96e80000 }
76265
  },
76266
/* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
76267
  {
76268
    { 0, 0, 0, 0 },
76269
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
76270
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96f80000 }
76271
  },
76272
/* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
76273
  {
76274
    { 0, 0, 0, 0 },
76275
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } },
76276
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96880000 }
76277
  },
76278
/* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
76279
  {
76280
    { 0, 0, 0, 0 },
76281
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } },
76282
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96a80000 }
76283
  },
76284
/* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
76285
  {
76286
    { 0, 0, 0, 0 },
76287
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } },
76288
    & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96b80000 }
76289
  },
76290
/* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
76291
  {
76292
    { 0, 0, 0, 0 },
76293
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
76294
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa8080000 }
76295
  },
76296
/* add.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */
76297
  {
76298
    { 0, 0, 0, 0 },
76299
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
76300
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa8280000 }
76301
  },
76302
/* add.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */
76303
  {
76304
    { 0, 0, 0, 0 },
76305
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
76306
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa8380000 }
76307
  },
76308
/* add.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */
76309
  {
76310
    { 0, 0, 0, 0 },
76311
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
76312
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb8380000 }
76313
  },
76314
/* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
76315
  {
76316
    { 0, 0, 0, 0 },
76317
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
76318
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0880000 }
76319
  },
76320
/* add.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */
76321
  {
76322
    { 0, 0, 0, 0 },
76323
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
76324
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0a80000 }
76325
  },
76326
/* add.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */
76327
  {
76328
    { 0, 0, 0, 0 },
76329
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
76330
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0b80000 }
76331
  },
76332
/* add.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */
76333
  {
76334
    { 0, 0, 0, 0 },
76335
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
76336
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0b80000 }
76337
  },
76338
/* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
76339
  {
76340
    { 0, 0, 0, 0 },
76341
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76342
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa0080000 }
76343
  },
76344
/* add.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
76345
  {
76346
    { 0, 0, 0, 0 },
76347
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76348
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa0280000 }
76349
  },
76350
/* add.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
76351
  {
76352
    { 0, 0, 0, 0 },
76353
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76354
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa0380000 }
76355
  },
76356
/* add.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
76357
  {
76358
    { 0, 0, 0, 0 },
76359
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76360
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb0380000 }
76361
  },
76362
/* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
76363
  {
76364
    { 0, 0, 0, 0 },
76365
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76366
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa2080000 }
76367
  },
76368
/* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
76369
  {
76370
    { 0, 0, 0, 0 },
76371
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76372
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa2280000 }
76373
  },
76374
/* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
76375
  {
76376
    { 0, 0, 0, 0 },
76377
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76378
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa2380000 }
76379
  },
76380
/* add.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
76381
  {
76382
    { 0, 0, 0, 0 },
76383
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76384
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xb2380000 }
76385
  },
76386
/* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
76387
  {
76388
    { 0, 0, 0, 0 },
76389
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76390
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa4080000 }
76391
  },
76392
/* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
76393
  {
76394
    { 0, 0, 0, 0 },
76395
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76396
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa4280000 }
76397
  },
76398
/* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
76399
  {
76400
    { 0, 0, 0, 0 },
76401
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76402
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa4380000 }
76403
  },
76404
/* add.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
76405
  {
76406
    { 0, 0, 0, 0 },
76407
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76408
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xb4380000 }
76409
  },
76410
/* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
76411
  {
76412
    { 0, 0, 0, 0 },
76413
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76414
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa6080000 }
76415
  },
76416
/* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
76417
  {
76418
    { 0, 0, 0, 0 },
76419
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76420
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa6280000 }
76421
  },
76422
/* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
76423
  {
76424
    { 0, 0, 0, 0 },
76425
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76426
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa6380000 }
76427
  },
76428
/* add.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
76429
  {
76430
    { 0, 0, 0, 0 },
76431
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76432
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xb6380000 }
76433
  },
76434
/* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
76435
  {
76436
    { 0, 0, 0, 0 },
76437
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
76438
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2880000 }
76439
  },
76440
/* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
76441
  {
76442
    { 0, 0, 0, 0 },
76443
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
76444
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2a80000 }
76445
  },
76446
/* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
76447
  {
76448
    { 0, 0, 0, 0 },
76449
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
76450
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2b80000 }
76451
  },
76452
/* add.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
76453
  {
76454
    { 0, 0, 0, 0 },
76455
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
76456
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xb2b80000 }
76457
  },
76458
/* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
76459
  {
76460
    { 0, 0, 0, 0 },
76461
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
76462
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4880000 }
76463
  },
76464
/* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
76465
  {
76466
    { 0, 0, 0, 0 },
76467
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
76468
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4a80000 }
76469
  },
76470
/* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
76471
  {
76472
    { 0, 0, 0, 0 },
76473
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
76474
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4b80000 }
76475
  },
76476
/* add.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
76477
  {
76478
    { 0, 0, 0, 0 },
76479
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
76480
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xb4b80000 }
76481
  },
76482
/* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
76483
  {
76484
    { 0, 0, 0, 0 },
76485
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
76486
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2c80000 }
76487
  },
76488
/* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
76489
  {
76490
    { 0, 0, 0, 0 },
76491
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
76492
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2e80000 }
76493
  },
76494
/* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
76495
  {
76496
    { 0, 0, 0, 0 },
76497
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
76498
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2f80000 }
76499
  },
76500
/* add.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
76501
  {
76502
    { 0, 0, 0, 0 },
76503
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
76504
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xb2f80000 }
76505
  },
76506
/* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
76507
  {
76508
    { 0, 0, 0, 0 },
76509
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
76510
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4c80000 }
76511
  },
76512
/* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
76513
  {
76514
    { 0, 0, 0, 0 },
76515
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
76516
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4e80000 }
76517
  },
76518
/* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
76519
  {
76520
    { 0, 0, 0, 0 },
76521
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
76522
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4f80000 }
76523
  },
76524
/* add.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
76525
  {
76526
    { 0, 0, 0, 0 },
76527
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } },
76528
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xb4f80000 }
76529
  },
76530
/* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
76531
  {
76532
    { 0, 0, 0, 0 },
76533
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } },
76534
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6c80000 }
76535
  },
76536
/* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
76537
  {
76538
    { 0, 0, 0, 0 },
76539
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
76540
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6e80000 }
76541
  },
76542
/* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
76543
  {
76544
    { 0, 0, 0, 0 },
76545
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } },
76546
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6f80000 }
76547
  },
76548
/* add.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
76549
  {
76550
    { 0, 0, 0, 0 },
76551
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
76552
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xb6f80000 }
76553
  },
76554
/* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
76555
  {
76556
    { 0, 0, 0, 0 },
76557
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } },
76558
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6880000 }
76559
  },
76560
/* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
76561
  {
76562
    { 0, 0, 0, 0 },
76563
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } },
76564
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6a80000 }
76565
  },
76566
/* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
76567
  {
76568
    { 0, 0, 0, 0 },
76569
    { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } },
76570
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6b80000 }
76571
  },
76572
/* add.b${G} ${Dsp-16-u16},${Dsp-32-u24} */
76573
  {
76574
    { 0, 0, 0, 0 },
76575
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } },
76576
    & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xb6b80000 }
76577
  },
76578
/* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
76579
  {
76580
    { 0, 0, 0, 0 },
76581
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
76582
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb8080000 }
76583
  },
76584
/* add.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */
76585
  {
76586
    { 0, 0, 0, 0 },
76587
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
76588
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb8280000 }
76589
  },
76590
/* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
76591
  {
76592
    { 0, 0, 0, 0 },
76593
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
76594
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0880000 }
76595
  },
76596
/* add.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */
76597
  {
76598
    { 0, 0, 0, 0 },
76599
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
76600
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0a80000 }
76601
  },
76602
/* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
76603
  {
76604
    { 0, 0, 0, 0 },
76605
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76606
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb0080000 }
76607
  },
76608
/* add.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
76609
  {
76610
    { 0, 0, 0, 0 },
76611
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76612
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb0280000 }
76613
  },
76614
/* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
76615
  {
76616
    { 0, 0, 0, 0 },
76617
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76618
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_QI, { 0xb2080000 }
76619
  },
76620
/* add.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
76621
  {
76622
    { 0, 0, 0, 0 },
76623
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76624
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_QI, { 0xb2280000 }
76625
  },
76626
/* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
76627
  {
76628
    { 0, 0, 0, 0 },
76629
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76630
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_QI, { 0xb4080000 }
76631
  },
76632
/* add.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
76633
  {
76634
    { 0, 0, 0, 0 },
76635
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76636
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_QI, { 0xb4280000 }
76637
  },
76638
/* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
76639
  {
76640
    { 0, 0, 0, 0 },
76641
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76642
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_QI, { 0xb6080000 }
76643
  },
76644
/* add.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
76645
  {
76646
    { 0, 0, 0, 0 },
76647
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76648
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_QI, { 0xb6280000 }
76649
  },
76650
/* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
76651
  {
76652
    { 0, 0, 0, 0 },
76653
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
76654
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_QI, { 0xb2880000 }
76655
  },
76656
/* add.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
76657
  {
76658
    { 0, 0, 0, 0 },
76659
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } },
76660
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_QI, { 0xb2a80000 }
76661
  },
76662
/* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
76663
  {
76664
    { 0, 0, 0, 0 },
76665
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
76666
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_QI, { 0xb4880000 }
76667
  },
76668
/* add.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
76669
  {
76670
    { 0, 0, 0, 0 },
76671
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } },
76672
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_QI, { 0xb4a80000 }
76673
  },
76674
/* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
76675
  {
76676
    { 0, 0, 0, 0 },
76677
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
76678
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_QI, { 0xb2c80000 }
76679
  },
76680
/* add.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
76681
  {
76682
    { 0, 0, 0, 0 },
76683
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } },
76684
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_QI, { 0xb2e80000 }
76685
  },
76686
/* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
76687
  {
76688
    { 0, 0, 0, 0 },
76689
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
76690
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_QI, { 0xb4c80000 }
76691
  },
76692
/* add.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
76693
  {
76694
    { 0, 0, 0, 0 },
76695
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } },
76696
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_QI, { 0xb4e80000 }
76697
  },
76698
/* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
76699
  {
76700
    { 0, 0, 0, 0 },
76701
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } },
76702
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_QI, { 0xb6c80000 }
76703
  },
76704
/* add.b${G} ${Dsp-16-u24},${Dsp-40-u16} */
76705
  {
76706
    { 0, 0, 0, 0 },
76707
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } },
76708
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_QI, { 0xb6e80000 }
76709
  },
76710
/* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
76711
  {
76712
    { 0, 0, 0, 0 },
76713
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } },
76714
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_QI, { 0xb6880000 }
76715
  },
76716
/* add.b${G} ${Dsp-16-u24},${Dsp-40-u24} */
76717
  {
76718
    { 0, 0, 0, 0 },
76719
    { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } },
76720
    & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_QI, { 0xb6a80000 }
76721
  },
76722
/* add.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */
76723
  {
76724
    { 0, 0, 0, 0 },
76725
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
76726
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xc808 }
76727
  },
76728
/* add.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */
76729
  {
76730
    { 0, 0, 0, 0 },
76731
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
76732
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x8828 }
76733
  },
76734
/* add.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
76735
  {
76736
    { 0, 0, 0, 0 },
76737
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } },
76738
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x8808 }
76739
  },
76740
/* add.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */
76741
  {
76742
    { 0, 0, 0, 0 },
76743
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
76744
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xc088 }
76745
  },
76746
/* add.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */
76747
  {
76748
    { 0, 0, 0, 0 },
76749
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
76750
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x80a8 }
76751
  },
76752
/* add.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
76753
  {
76754
    { 0, 0, 0, 0 },
76755
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } },
76756
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x8088 }
76757
  },
76758
/* add.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */
76759
  {
76760
    { 0, 0, 0, 0 },
76761
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76762
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xc008 }
76763
  },
76764
/* add.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */
76765
  {
76766
    { 0, 0, 0, 0 },
76767
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76768
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x8028 }
76769
  },
76770
/* add.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
76771
  {
76772
    { 0, 0, 0, 0 },
76773
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76774
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x8008 }
76775
  },
76776
/* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
76777
  {
76778
    { 0, 0, 0, 0 },
76779
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76780
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0xc20800 }
76781
  },
76782
/* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
76783
  {
76784
    { 0, 0, 0, 0 },
76785
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76786
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0x822800 }
76787
  },
76788
/* add.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
76789
  {
76790
    { 0, 0, 0, 0 },
76791
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76792
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0x820800 }
76793
  },
76794
/* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
76795
  {
76796
    { 0, 0, 0, 0 },
76797
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76798
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0xc4080000 }
76799
  },
76800
/* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
76801
  {
76802
    { 0, 0, 0, 0 },
76803
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76804
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0x84280000 }
76805
  },
76806
/* add.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
76807
  {
76808
    { 0, 0, 0, 0 },
76809
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76810
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0x84080000 }
76811
  },
76812
/* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
76813
  {
76814
    { 0, 0, 0, 0 },
76815
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76816
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0xc6080000 }
76817
  },
76818
/* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
76819
  {
76820
    { 0, 0, 0, 0 },
76821
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76822
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0x86280000 }
76823
  },
76824
/* add.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
76825
  {
76826
    { 0, 0, 0, 0 },
76827
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
76828
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0x86080000 }
76829
  },
76830
/* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */
76831
  {
76832
    { 0, 0, 0, 0 },
76833
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
76834
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0xc28800 }
76835
  },
76836
/* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */
76837
  {
76838
    { 0, 0, 0, 0 },
76839
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
76840
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0x82a800 }
76841
  },
76842
/* add.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
76843
  {
76844
    { 0, 0, 0, 0 },
76845
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
76846
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0x828800 }
76847
  },
76848
/* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */
76849
  {
76850
    { 0, 0, 0, 0 },
76851
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
76852
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0xc4880000 }
76853
  },
76854
/* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */
76855
  {
76856
    { 0, 0, 0, 0 },
76857
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
76858
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0x84a80000 }
76859
  },
76860
/* add.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
76861
  {
76862
    { 0, 0, 0, 0 },
76863
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
76864
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0x84880000 }
76865
  },
76866
/* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */
76867
  {
76868
    { 0, 0, 0, 0 },
76869
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
76870
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0xc2c800 }
76871
  },
76872
/* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */
76873
  {
76874
    { 0, 0, 0, 0 },
76875
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
76876
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82e800 }
76877
  },
76878
/* add.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
76879
  {
76880
    { 0, 0, 0, 0 },
76881
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
76882
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82c800 }
76883
  },
76884
/* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */
76885
  {
76886
    { 0, 0, 0, 0 },
76887
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
76888
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0xc4c80000 }
76889
  },
76890
/* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */
76891
  {
76892
    { 0, 0, 0, 0 },
76893
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
76894
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84e80000 }
76895
  },
76896
/* add.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
76897
  {
76898
    { 0, 0, 0, 0 },
76899
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
76900
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84c80000 }
76901
  },
76902
/* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */
76903
  {
76904
    { 0, 0, 0, 0 },
76905
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), 0 } },
76906
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0xc6c80000 }
76907
  },
76908
/* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */
76909
  {
76910
    { 0, 0, 0, 0 },
76911
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), 0 } },
76912
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0x86e80000 }
76913
  },
76914
/* add.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
76915
  {
76916
    { 0, 0, 0, 0 },
76917
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } },
76918
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0x86c80000 }
76919
  },
76920
/* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */
76921
  {
76922
    { 0, 0, 0, 0 },
76923
    { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U24), 0 } },
76924
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0xc6880000 }
76925
  },
76926
/* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */
76927
  {
76928
    { 0, 0, 0, 0 },
76929
    { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U24), 0 } },
76930
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0x86a80000 }
76931
  },
76932
/* add.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
76933
  {
76934
    { 0, 0, 0, 0 },
76935
    { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } },
76936
    & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0x86880000 }
76937
  },
76938
/* add.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
76939
  {
76940
    { 0, 0, 0, 0 },
76941
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } },
76942
    & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_Rn_direct_HI, { 0xa18000 }
76943
  },
76944
/* add.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */
76945
  {
76946
    { 0, 0, 0, 0 },
76947
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } },
76948
    & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_Rn_direct_HI, { 0xa1a000 }
76949
  },
76950
/* add.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */
76951
  {
76952
    { 0, 0, 0, 0 },
76953
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNHI), 0 } },
76954
    & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_Rn_direct_HI, { 0xa1b000 }
76955
  },
76956
/* add.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
76957
  {
76958
    { 0, 0, 0, 0 },
76959
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } },
76960
    & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_direct_HI, { 0xa18400 }
76961
  },
76962
/* add.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */
76963
  {
76964
    { 0, 0, 0, 0 },
76965
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } },
76966
    & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_direct_HI, { 0xa1a400 }
76967
  },
76968
/* add.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */
76969
  {
76970
    { 0, 0, 0, 0 },
76971
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANHI), 0 } },
76972
    & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_direct_HI, { 0xa1b400 }
76973
  },
76974
/* add.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
76975
  {
76976
    { 0, 0, 0, 0 },
76977
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
76978
    & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_indirect_HI, { 0xa18600 }
76979
  },
76980
/* add.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */
76981
  {
76982
    { 0, 0, 0, 0 },
76983
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
76984
    & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_indirect_HI, { 0xa1a600 }
76985
  },
76986
/* add.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */
76987
  {
76988
    { 0, 0, 0, 0 },
76989
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
76990
    & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_indirect_HI, { 0xa1b600 }
76991
  },
76992
/* add.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
76993
  {
76994
    { 0, 0, 0, 0 },
76995
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
76996
    & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_An_relative_HI, { 0xa1880000 }
76997
  },
76998
/* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
76999
  {
77000
    { 0, 0, 0, 0 },
77001
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
77002
    & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_An_relative_HI, { 0xa1a80000 }
77003
  },
77004
/* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
77005
  {
77006
    { 0, 0, 0, 0 },
77007
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
77008
    & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_An_relative_HI, { 0xa1b80000 }
77009
  },
77010
/* add.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
77011
  {
77012
    { 0, 0, 0, 0 },
77013
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
77014
    & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_An_relative_HI, { 0xa18c0000 }
77015
  },
77016
/* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
77017
  {
77018
    { 0, 0, 0, 0 },
77019
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
77020
    & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_An_relative_HI, { 0xa1ac0000 }
77021
  },
77022
/* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
77023
  {
77024
    { 0, 0, 0, 0 },
77025
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
77026
    & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_An_relative_HI, { 0xa1bc0000 }
77027
  },
77028
/* add.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
77029
  {
77030
    { 0, 0, 0, 0 },
77031
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
77032
    & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_SB_relative_HI, { 0xa18a0000 }
77033
  },
77034
/* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
77035
  {
77036
    { 0, 0, 0, 0 },
77037
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
77038
    & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_SB_relative_HI, { 0xa1aa0000 }
77039
  },
77040
/* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
77041
  {
77042
    { 0, 0, 0, 0 },
77043
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
77044
    & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_SB_relative_HI, { 0xa1ba0000 }
77045
  },
77046
/* add.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
77047
  {
77048
    { 0, 0, 0, 0 },
77049
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
77050
    & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_SB_relative_HI, { 0xa18e0000 }
77051
  },
77052
/* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
77053
  {
77054
    { 0, 0, 0, 0 },
77055
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
77056
    & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_SB_relative_HI, { 0xa1ae0000 }
77057
  },
77058
/* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
77059
  {
77060
    { 0, 0, 0, 0 },
77061
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
77062
    & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_SB_relative_HI, { 0xa1be0000 }
77063
  },
77064
/* add.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
77065
  {
77066
    { 0, 0, 0, 0 },
77067
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
77068
    & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_FB_relative_HI, { 0xa18b0000 }
77069
  },
77070
/* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
77071
  {
77072
    { 0, 0, 0, 0 },
77073
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
77074
    & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_FB_relative_HI, { 0xa1ab0000 }
77075
  },
77076
/* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
77077
  {
77078
    { 0, 0, 0, 0 },
77079
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
77080
    & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_FB_relative_HI, { 0xa1bb0000 }
77081
  },
77082
/* add.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
77083
  {
77084
    { 0, 0, 0, 0 },
77085
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } },
77086
    & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_absolute_HI, { 0xa18f0000 }
77087
  },
77088
/* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
77089
  {
77090
    { 0, 0, 0, 0 },
77091
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
77092
    & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_absolute_HI, { 0xa1af0000 }
77093
  },
77094
/* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
77095
  {
77096
    { 0, 0, 0, 0 },
77097
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
77098
    & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_absolute_HI, { 0xa1bf0000 }
77099
  },
77100
/* add.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
77101
  {
77102
    { 0, 0, 0, 0 },
77103
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } },
77104
    & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_Rn_direct_HI, { 0xa1c00000 }
77105
  },
77106
/* add.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */
77107
  {
77108
    { 0, 0, 0, 0 },
77109
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } },
77110
    & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_Rn_direct_HI, { 0xa1e00000 }
77111
  },
77112
/* add.w${G} ${Dsp-16-u16},$Dst16RnHI */
77113
  {
77114
    { 0, 0, 0, 0 },
77115
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16RNHI), 0 } },
77116
    & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_Rn_direct_HI, { 0xa1f00000 }
77117
  },
77118
/* add.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
77119
  {
77120
    { 0, 0, 0, 0 },
77121
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } },
77122
    & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_direct_HI, { 0xa1c40000 }
77123
  },
77124
/* add.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */
77125
  {
77126
    { 0, 0, 0, 0 },
77127
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } },
77128
    & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_direct_HI, { 0xa1e40000 }
77129
  },
77130
/* add.w${G} ${Dsp-16-u16},$Dst16AnHI */
77131
  {
77132
    { 0, 0, 0, 0 },
77133
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16ANHI), 0 } },
77134
    & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_direct_HI, { 0xa1f40000 }
77135
  },
77136
/* add.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
77137
  {
77138
    { 0, 0, 0, 0 },
77139
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
77140
    & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_indirect_HI, { 0xa1c60000 }
77141
  },
77142
/* add.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */
77143
  {
77144
    { 0, 0, 0, 0 },
77145
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
77146
    & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_indirect_HI, { 0xa1e60000 }
77147
  },
77148
/* add.w${G} ${Dsp-16-u16},[$Dst16An] */
77149
  {
77150
    { 0, 0, 0, 0 },
77151
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } },
77152
    & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_indirect_HI, { 0xa1f60000 }
77153
  },
77154
/* add.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
77155
  {
77156
    { 0, 0, 0, 0 },
77157
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
77158
    & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_An_relative_HI, { 0xa1c80000 }
77159
  },
77160
/* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
77161
  {
77162
    { 0, 0, 0, 0 },
77163
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
77164
    & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_An_relative_HI, { 0xa1e80000 }
77165
  },
77166
/* add.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
77167
  {
77168
    { 0, 0, 0, 0 },
77169
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
77170
    & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_An_relative_HI, { 0xa1f80000 }
77171
  },
77172
/* add.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
77173
  {
77174
    { 0, 0, 0, 0 },
77175
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
77176
    & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_An_relative_HI, { 0xa1cc0000 }
77177
  },
77178
/* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
77179
  {
77180
    { 0, 0, 0, 0 },
77181
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
77182
    & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_An_relative_HI, { 0xa1ec0000 }
77183
  },
77184
/* add.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
77185
  {
77186
    { 0, 0, 0, 0 },
77187
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
77188
    & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_An_relative_HI, { 0xa1fc0000 }
77189
  },
77190
/* add.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
77191
  {
77192
    { 0, 0, 0, 0 },
77193
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
77194
    & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_SB_relative_HI, { 0xa1ca0000 }
77195
  },
77196
/* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
77197
  {
77198
    { 0, 0, 0, 0 },
77199
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
77200
    & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_SB_relative_HI, { 0xa1ea0000 }
77201
  },
77202
/* add.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
77203
  {
77204
    { 0, 0, 0, 0 },
77205
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
77206
    & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_SB_relative_HI, { 0xa1fa0000 }
77207
  },
77208
/* add.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
77209
  {
77210
    { 0, 0, 0, 0 },
77211
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
77212
    & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_SB_relative_HI, { 0xa1ce0000 }
77213
  },
77214
/* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
77215
  {
77216
    { 0, 0, 0, 0 },
77217
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
77218
    & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_SB_relative_HI, { 0xa1ee0000 }
77219
  },
77220
/* add.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
77221
  {
77222
    { 0, 0, 0, 0 },
77223
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
77224
    & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_SB_relative_HI, { 0xa1fe0000 }
77225
  },
77226
/* add.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
77227
  {
77228
    { 0, 0, 0, 0 },
77229
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
77230
    & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_FB_relative_HI, { 0xa1cb0000 }
77231
  },
77232
/* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
77233
  {
77234
    { 0, 0, 0, 0 },
77235
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
77236
    & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_FB_relative_HI, { 0xa1eb0000 }
77237
  },
77238
/* add.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
77239
  {
77240
    { 0, 0, 0, 0 },
77241
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
77242
    & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_FB_relative_HI, { 0xa1fb0000 }
77243
  },
77244
/* add.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
77245
  {
77246
    { 0, 0, 0, 0 },
77247
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } },
77248
    & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_absolute_HI, { 0xa1cf0000 }
77249
  },
77250
/* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
77251
  {
77252
    { 0, 0, 0, 0 },
77253
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
77254
    & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_absolute_HI, { 0xa1ef0000 }
77255
  },
77256
/* add.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
77257
  {
77258
    { 0, 0, 0, 0 },
77259
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
77260
    & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_absolute_HI, { 0xa1ff0000 }
77261
  },
77262
/* add.w${G} $Src16RnHI,$Dst16RnHI */
77263
  {
77264
    { 0, 0, 0, 0 },
77265
    { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DST16RNHI), 0 } },
77266
    & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_Rn_direct_HI, { 0xa100 }
77267
  },
77268
/* add.w${G} $Src16AnHI,$Dst16RnHI */
77269
  {
77270
    { 0, 0, 0, 0 },
77271
    { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DST16RNHI), 0 } },
77272
    & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_Rn_direct_HI, { 0xa140 }
77273
  },
77274
/* add.w${G} [$Src16An],$Dst16RnHI */
77275
  {
77276
    { 0, 0, 0, 0 },
77277
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } },
77278
    & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_Rn_direct_HI, { 0xa160 }
77279
  },
77280
/* add.w${G} $Src16RnHI,$Dst16AnHI */
77281
  {
77282
    { 0, 0, 0, 0 },
77283
    { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DST16ANHI), 0 } },
77284
    & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_direct_HI, { 0xa104 }
77285
  },
77286
/* add.w${G} $Src16AnHI,$Dst16AnHI */
77287
  {
77288
    { 0, 0, 0, 0 },
77289
    { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DST16ANHI), 0 } },
77290
    & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_direct_HI, { 0xa144 }
77291
  },
77292
/* add.w${G} [$Src16An],$Dst16AnHI */
77293
  {
77294
    { 0, 0, 0, 0 },
77295
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } },
77296
    & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_direct_HI, { 0xa164 }
77297
  },
77298
/* add.w${G} $Src16RnHI,[$Dst16An] */
77299
  {
77300
    { 0, 0, 0, 0 },
77301
    { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', '[', OP (DST16AN), ']', 0 } },
77302
    & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_indirect_HI, { 0xa106 }
77303
  },
77304
/* add.w${G} $Src16AnHI,[$Dst16An] */
77305
  {
77306
    { 0, 0, 0, 0 },
77307
    { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', '[', OP (DST16AN), ']', 0 } },
77308
    & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_indirect_HI, { 0xa146 }
77309
  },
77310
/* add.w${G} [$Src16An],[$Dst16An] */
77311
  {
77312
    { 0, 0, 0, 0 },
77313
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
77314
    & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_indirect_HI, { 0xa166 }
77315
  },
77316
/* add.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
77317
  {
77318
    { 0, 0, 0, 0 },
77319
    { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
77320
    & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_An_relative_HI, { 0xa10800 }
77321
  },
77322
/* add.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
77323
  {
77324
    { 0, 0, 0, 0 },
77325
    { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
77326
    & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_An_relative_HI, { 0xa14800 }
77327
  },
77328
/* add.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
77329
  {
77330
    { 0, 0, 0, 0 },
77331
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
77332
    & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_An_relative_HI, { 0xa16800 }
77333
  },
77334
/* add.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
77335
  {
77336
    { 0, 0, 0, 0 },
77337
    { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
77338
    & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_An_relative_HI, { 0xa10c0000 }
77339
  },
77340
/* add.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
77341
  {
77342
    { 0, 0, 0, 0 },
77343
    { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
77344
    & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_An_relative_HI, { 0xa14c0000 }
77345
  },
77346
/* add.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
77347
  {
77348
    { 0, 0, 0, 0 },
77349
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
77350
    & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_An_relative_HI, { 0xa16c0000 }
77351
  },
77352
/* add.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */
77353
  {
77354
    { 0, 0, 0, 0 },
77355
    { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
77356
    & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_SB_relative_HI, { 0xa10a00 }
77357
  },
77358
/* add.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */
77359
  {
77360
    { 0, 0, 0, 0 },
77361
    { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
77362
    & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_SB_relative_HI, { 0xa14a00 }
77363
  },
77364
/* add.w${G} [$Src16An],${Dsp-16-u8}[sb] */
77365
  {
77366
    { 0, 0, 0, 0 },
77367
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
77368
    & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_SB_relative_HI, { 0xa16a00 }
77369
  },
77370
/* add.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */
77371
  {
77372
    { 0, 0, 0, 0 },
77373
    { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
77374
    & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_SB_relative_HI, { 0xa10e0000 }
77375
  },
77376
/* add.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */
77377
  {
77378
    { 0, 0, 0, 0 },
77379
    { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
77380
    & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_SB_relative_HI, { 0xa14e0000 }
77381
  },
77382
/* add.w${G} [$Src16An],${Dsp-16-u16}[sb] */
77383
  {
77384
    { 0, 0, 0, 0 },
77385
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
77386
    & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_SB_relative_HI, { 0xa16e0000 }
77387
  },
77388
/* add.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */
77389
  {
77390
    { 0, 0, 0, 0 },
77391
    { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
77392
    & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_FB_relative_HI, { 0xa10b00 }
77393
  },
77394
/* add.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */
77395
  {
77396
    { 0, 0, 0, 0 },
77397
    { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
77398
    & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_FB_relative_HI, { 0xa14b00 }
77399
  },
77400
/* add.w${G} [$Src16An],${Dsp-16-s8}[fb] */
77401
  {
77402
    { 0, 0, 0, 0 },
77403
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
77404
    & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_FB_relative_HI, { 0xa16b00 }
77405
  },
77406
/* add.w${G} $Src16RnHI,${Dsp-16-u16} */
77407
  {
77408
    { 0, 0, 0, 0 },
77409
    { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), 0 } },
77410
    & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_absolute_HI, { 0xa10f0000 }
77411
  },
77412
/* add.w${G} $Src16AnHI,${Dsp-16-u16} */
77413
  {
77414
    { 0, 0, 0, 0 },
77415
    { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), 0 } },
77416
    & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_absolute_HI, { 0xa14f0000 }
77417
  },
77418
/* add.w${G} [$Src16An],${Dsp-16-u16} */
77419
  {
77420
    { 0, 0, 0, 0 },
77421
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } },
77422
    & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_absolute_HI, { 0xa16f0000 }
77423
  },
77424
/* add.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
77425
  {
77426
    { 0, 0, 0, 0 },
77427
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } },
77428
    & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_Rn_direct_QI, { 0xa08000 }
77429
  },
77430
/* add.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */
77431
  {
77432
    { 0, 0, 0, 0 },
77433
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } },
77434
    & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_Rn_direct_QI, { 0xa0a000 }
77435
  },
77436
/* add.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */
77437
  {
77438
    { 0, 0, 0, 0 },
77439
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNQI), 0 } },
77440
    & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_Rn_direct_QI, { 0xa0b000 }
77441
  },
77442
/* add.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
77443
  {
77444
    { 0, 0, 0, 0 },
77445
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } },
77446
    & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_direct_QI, { 0xa08400 }
77447
  },
77448
/* add.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */
77449
  {
77450
    { 0, 0, 0, 0 },
77451
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } },
77452
    & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_direct_QI, { 0xa0a400 }
77453
  },
77454
/* add.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */
77455
  {
77456
    { 0, 0, 0, 0 },
77457
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANQI), 0 } },
77458
    & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_direct_QI, { 0xa0b400 }
77459
  },
77460
/* add.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
77461
  {
77462
    { 0, 0, 0, 0 },
77463
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
77464
    & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_indirect_QI, { 0xa08600 }
77465
  },
77466
/* add.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */
77467
  {
77468
    { 0, 0, 0, 0 },
77469
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
77470
    & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_indirect_QI, { 0xa0a600 }
77471
  },
77472
/* add.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */
77473
  {
77474
    { 0, 0, 0, 0 },
77475
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
77476
    & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_indirect_QI, { 0xa0b600 }
77477
  },
77478
/* add.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
77479
  {
77480
    { 0, 0, 0, 0 },
77481
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
77482
    & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_An_relative_QI, { 0xa0880000 }
77483
  },
77484
/* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
77485
  {
77486
    { 0, 0, 0, 0 },
77487
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
77488
    & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_An_relative_QI, { 0xa0a80000 }
77489
  },
77490
/* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
77491
  {
77492
    { 0, 0, 0, 0 },
77493
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } },
77494
    & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_An_relative_QI, { 0xa0b80000 }
77495
  },
77496
/* add.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
77497
  {
77498
    { 0, 0, 0, 0 },
77499
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
77500
    & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_An_relative_QI, { 0xa08c0000 }
77501
  },
77502
/* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
77503
  {
77504
    { 0, 0, 0, 0 },
77505
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
77506
    & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_An_relative_QI, { 0xa0ac0000 }
77507
  },
77508
/* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
77509
  {
77510
    { 0, 0, 0, 0 },
77511
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } },
77512
    & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_An_relative_QI, { 0xa0bc0000 }
77513
  },
77514
/* add.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
77515
  {
77516
    { 0, 0, 0, 0 },
77517
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
77518
    & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_SB_relative_QI, { 0xa08a0000 }
77519
  },
77520
/* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
77521
  {
77522
    { 0, 0, 0, 0 },
77523
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
77524
    & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_SB_relative_QI, { 0xa0aa0000 }
77525
  },
77526
/* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
77527
  {
77528
    { 0, 0, 0, 0 },
77529
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } },
77530
    & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_SB_relative_QI, { 0xa0ba0000 }
77531
  },
77532
/* add.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
77533
  {
77534
    { 0, 0, 0, 0 },
77535
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
77536
    & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_SB_relative_QI, { 0xa08e0000 }
77537
  },
77538
/* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
77539
  {
77540
    { 0, 0, 0, 0 },
77541
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
77542
    & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_SB_relative_QI, { 0xa0ae0000 }
77543
  },
77544
/* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
77545
  {
77546
    { 0, 0, 0, 0 },
77547
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } },
77548
    & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_SB_relative_QI, { 0xa0be0000 }
77549
  },
77550
/* add.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
77551
  {
77552
    { 0, 0, 0, 0 },
77553
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
77554
    & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_FB_relative_QI, { 0xa08b0000 }
77555
  },
77556
/* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
77557
  {
77558
    { 0, 0, 0, 0 },
77559
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
77560
    & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_FB_relative_QI, { 0xa0ab0000 }
77561
  },
77562
/* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
77563
  {
77564
    { 0, 0, 0, 0 },
77565
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } },
77566
    & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_FB_relative_QI, { 0xa0bb0000 }
77567
  },
77568
/* add.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
77569
  {
77570
    { 0, 0, 0, 0 },
77571
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } },
77572
    & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_absolute_QI, { 0xa08f0000 }
77573
  },
77574
/* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
77575
  {
77576
    { 0, 0, 0, 0 },
77577
    { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } },
77578
    & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_absolute_QI, { 0xa0af0000 }
77579
  },
77580
/* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
77581
  {
77582
    { 0, 0, 0, 0 },
77583
    { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } },
77584
    & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_absolute_QI, { 0xa0bf0000 }
77585
  },
77586
/* add.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
77587
  {
77588
    { 0, 0, 0, 0 },
77589
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } },
77590
    & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_Rn_direct_QI, { 0xa0c00000 }
77591
  },
77592
/* add.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */
77593
  {
77594
    { 0, 0, 0, 0 },
77595
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } },
77596
    & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_Rn_direct_QI, { 0xa0e00000 }
77597
  },
77598
/* add.b${G} ${Dsp-16-u16},$Dst16RnQI */
77599
  {
77600
    { 0, 0, 0, 0 },
77601
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16RNQI), 0 } },
77602
    & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_Rn_direct_QI, { 0xa0f00000 }
77603
  },
77604
/* add.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
77605
  {
77606
    { 0, 0, 0, 0 },
77607
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } },
77608
    & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_direct_QI, { 0xa0c40000 }
77609
  },
77610
/* add.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */
77611
  {
77612
    { 0, 0, 0, 0 },
77613
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } },
77614
    & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_direct_QI, { 0xa0e40000 }
77615
  },
77616
/* add.b${G} ${Dsp-16-u16},$Dst16AnQI */
77617
  {
77618
    { 0, 0, 0, 0 },
77619
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16ANQI), 0 } },
77620
    & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_direct_QI, { 0xa0f40000 }
77621
  },
77622
/* add.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
77623
  {
77624
    { 0, 0, 0, 0 },
77625
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
77626
    & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_indirect_QI, { 0xa0c60000 }
77627
  },
77628
/* add.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */
77629
  {
77630
    { 0, 0, 0, 0 },
77631
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } },
77632
    & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_indirect_QI, { 0xa0e60000 }
77633
  },
77634
/* add.b${G} ${Dsp-16-u16},[$Dst16An] */
77635
  {
77636
    { 0, 0, 0, 0 },
77637
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } },
77638
    & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_indirect_QI, { 0xa0f60000 }
77639
  },
77640
/* add.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
77641
  {
77642
    { 0, 0, 0, 0 },
77643
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
77644
    & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_An_relative_QI, { 0xa0c80000 }
77645
  },
77646
/* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
77647
  {
77648
    { 0, 0, 0, 0 },
77649
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
77650
    & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_An_relative_QI, { 0xa0e80000 }
77651
  },
77652
/* add.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
77653
  {
77654
    { 0, 0, 0, 0 },
77655
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } },
77656
    & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_An_relative_QI, { 0xa0f80000 }
77657
  },
77658
/* add.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
77659
  {
77660
    { 0, 0, 0, 0 },
77661
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
77662
    & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_An_relative_QI, { 0xa0cc0000 }
77663
  },
77664
/* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
77665
  {
77666
    { 0, 0, 0, 0 },
77667
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
77668
    & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_An_relative_QI, { 0xa0ec0000 }
77669
  },
77670
/* add.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
77671
  {
77672
    { 0, 0, 0, 0 },
77673
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } },
77674
    & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_An_relative_QI, { 0xa0fc0000 }
77675
  },
77676
/* add.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
77677
  {
77678
    { 0, 0, 0, 0 },
77679
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
77680
    & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_SB_relative_QI, { 0xa0ca0000 }
77681
  },
77682
/* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
77683
  {
77684
    { 0, 0, 0, 0 },
77685
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
77686
    & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_SB_relative_QI, { 0xa0ea0000 }
77687
  },
77688
/* add.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
77689
  {
77690
    { 0, 0, 0, 0 },
77691
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } },
77692
    & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_SB_relative_QI, { 0xa0fa0000 }
77693
  },
77694
/* add.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
77695
  {
77696
    { 0, 0, 0, 0 },
77697
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
77698
    & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_SB_relative_QI, { 0xa0ce0000 }
77699
  },
77700
/* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
77701
  {
77702
    { 0, 0, 0, 0 },
77703
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
77704
    & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_SB_relative_QI, { 0xa0ee0000 }
77705
  },
77706
/* add.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
77707
  {
77708
    { 0, 0, 0, 0 },
77709
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } },
77710
    & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_SB_relative_QI, { 0xa0fe0000 }
77711
  },
77712
/* add.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
77713
  {
77714
    { 0, 0, 0, 0 },
77715
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
77716
    & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_FB_relative_QI, { 0xa0cb0000 }
77717
  },
77718
/* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
77719
  {
77720
    { 0, 0, 0, 0 },
77721
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
77722
    & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_FB_relative_QI, { 0xa0eb0000 }
77723
  },
77724
/* add.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
77725
  {
77726
    { 0, 0, 0, 0 },
77727
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } },
77728
    & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_FB_relative_QI, { 0xa0fb0000 }
77729
  },
77730
/* add.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
77731
  {
77732
    { 0, 0, 0, 0 },
77733
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } },
77734
    & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_absolute_QI, { 0xa0cf0000 }
77735
  },
77736
/* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
77737
  {
77738
    { 0, 0, 0, 0 },
77739
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } },
77740
    & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_absolute_QI, { 0xa0ef0000 }
77741
  },
77742
/* add.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
77743
  {
77744
    { 0, 0, 0, 0 },
77745
    { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } },
77746
    & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_absolute_QI, { 0xa0ff0000 }
77747
  },
77748
/* add.b${G} $Src16RnQI,$Dst16RnQI */
77749
  {
77750
    { 0, 0, 0, 0 },
77751
    { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DST16RNQI), 0 } },
77752
    & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_Rn_direct_QI, { 0xa000 }
77753
  },
77754
/* add.b${G} $Src16AnQI,$Dst16RnQI */
77755
  {
77756
    { 0, 0, 0, 0 },
77757
    { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DST16RNQI), 0 } },
77758
    & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_Rn_direct_QI, { 0xa040 }
77759
  },
77760
/* add.b${G} [$Src16An],$Dst16RnQI */
77761
  {
77762
    { 0, 0, 0, 0 },
77763
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } },
77764
    & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_Rn_direct_QI, { 0xa060 }
77765
  },
77766
/* add.b${G} $Src16RnQI,$Dst16AnQI */
77767
  {
77768
    { 0, 0, 0, 0 },
77769
    { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DST16ANQI), 0 } },
77770
    & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_direct_QI, { 0xa004 }
77771
  },
77772
/* add.b${G} $Src16AnQI,$Dst16AnQI */
77773
  {
77774
    { 0, 0, 0, 0 },
77775
    { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DST16ANQI), 0 } },
77776
    & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_direct_QI, { 0xa044 }
77777
  },
77778
/* add.b${G} [$Src16An],$Dst16AnQI */
77779
  {
77780
    { 0, 0, 0, 0 },
77781
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } },
77782
    & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_direct_QI, { 0xa064 }
77783
  },
77784
/* add.b${G} $Src16RnQI,[$Dst16An] */
77785
  {
77786
    { 0, 0, 0, 0 },
77787
    { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', '[', OP (DST16AN), ']', 0 } },
77788
    & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_indirect_QI, { 0xa006 }
77789
  },
77790
/* add.b${G} $Src16AnQI,[$Dst16An] */
77791
  {
77792
    { 0, 0, 0, 0 },
77793
    { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', '[', OP (DST16AN), ']', 0 } },
77794
    & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_indirect_QI, { 0xa046 }
77795
  },
77796
/* add.b${G} [$Src16An],[$Dst16An] */
77797
  {
77798
    { 0, 0, 0, 0 },
77799
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } },
77800
    & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_indirect_QI, { 0xa066 }
77801
  },
77802
/* add.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
77803
  {
77804
    { 0, 0, 0, 0 },
77805
    { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
77806
    & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_An_relative_QI, { 0xa00800 }
77807
  },
77808
/* add.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
77809
  {
77810
    { 0, 0, 0, 0 },
77811
    { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
77812
    & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_An_relative_QI, { 0xa04800 }
77813
  },
77814
/* add.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
77815
  {
77816
    { 0, 0, 0, 0 },
77817
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
77818
    & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_An_relative_QI, { 0xa06800 }
77819
  },
77820
/* add.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
77821
  {
77822
    { 0, 0, 0, 0 },
77823
    { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
77824
    & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_An_relative_QI, { 0xa00c0000 }
77825
  },
77826
/* add.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
77827
  {
77828
    { 0, 0, 0, 0 },
77829
    { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
77830
    & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_An_relative_QI, { 0xa04c0000 }
77831
  },
77832
/* add.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
77833
  {
77834
    { 0, 0, 0, 0 },
77835
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
77836
    & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_An_relative_QI, { 0xa06c0000 }
77837
  },
77838
/* add.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */
77839
  {
77840
    { 0, 0, 0, 0 },
77841
    { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
77842
    & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_SB_relative_QI, { 0xa00a00 }
77843
  },
77844
/* add.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */
77845
  {
77846
    { 0, 0, 0, 0 },
77847
    { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
77848
    & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_SB_relative_QI, { 0xa04a00 }
77849
  },
77850
/* add.b${G} [$Src16An],${Dsp-16-u8}[sb] */
77851
  {
77852
    { 0, 0, 0, 0 },
77853
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
77854
    & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_SB_relative_QI, { 0xa06a00 }
77855
  },
77856
/* add.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */
77857
  {
77858
    { 0, 0, 0, 0 },
77859
    { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
77860
    & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_SB_relative_QI, { 0xa00e0000 }
77861
  },
77862
/* add.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */
77863
  {
77864
    { 0, 0, 0, 0 },
77865
    { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
77866
    & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_SB_relative_QI, { 0xa04e0000 }
77867
  },
77868
/* add.b${G} [$Src16An],${Dsp-16-u16}[sb] */
77869
  {
77870
    { 0, 0, 0, 0 },
77871
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
77872
    & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_SB_relative_QI, { 0xa06e0000 }
77873
  },
77874
/* add.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */
77875
  {
77876
    { 0, 0, 0, 0 },
77877
    { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
77878
    & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_FB_relative_QI, { 0xa00b00 }
77879
  },
77880
/* add.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */
77881
  {
77882
    { 0, 0, 0, 0 },
77883
    { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
77884
    & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_FB_relative_QI, { 0xa04b00 }
77885
  },
77886
/* add.b${G} [$Src16An],${Dsp-16-s8}[fb] */
77887
  {
77888
    { 0, 0, 0, 0 },
77889
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
77890
    & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_FB_relative_QI, { 0xa06b00 }
77891
  },
77892
/* add.b${G} $Src16RnQI,${Dsp-16-u16} */
77893
  {
77894
    { 0, 0, 0, 0 },
77895
    { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), 0 } },
77896
    & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_absolute_QI, { 0xa00f0000 }
77897
  },
77898
/* add.b${G} $Src16AnQI,${Dsp-16-u16} */
77899
  {
77900
    { 0, 0, 0, 0 },
77901
    { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), 0 } },
77902
    & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_absolute_QI, { 0xa04f0000 }
77903
  },
77904
/* add.b${G} [$Src16An],${Dsp-16-u16} */
77905
  {
77906
    { 0, 0, 0, 0 },
77907
    { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } },
77908
    & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_absolute_QI, { 0xa06f0000 }
77909
  },
77910
/* add.b${S} #${Imm-8-QI},r0l */
77911
  {
77912
    { 0, 0, 0, 0 },
77913
    { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'l', 0 } },
77914
    & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_R0l_direct_QI, { 0x8400 }
77915
  },
77916
/* add.b${S} #${Imm-8-QI},r0h */
77917
  {
77918
    { 0, 0, 0, 0 },
77919
    { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'h', 0 } },
77920
    & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_R0h_direct_QI, { 0x8300 }
77921
  },
77922
/* add.b${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */
77923
  {
77924
    { 0, 0, 0, 0 },
77925
    { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
77926
    & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_8_SB_relative_QI, { 0x850000 }
77927
  },
77928
/* add.b${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */
77929
  {
77930
    { 0, 0, 0, 0 },
77931
    { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
77932
    & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_8_FB_relative_QI, { 0x860000 }
77933
  },
77934
/* add.b${S} #${Imm-8-QI},${Dsp-16-u16} */
77935
  {
77936
    { 0, 0, 0, 0 },
77937
    { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_U16), 0 } },
77938
    & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_16_absolute_QI, { 0x87000000 }
77939
  },
77940
/* add.l${Q} #${Imm-12-s4},$Dst32RnUnprefixedSI */
77941
  {
77942
    { 0, 0, 0, 0 },
77943
    { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
77944
    & ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_Rn_direct_Unprefixed_SI, { 0xf830 }
77945
  },
77946
/* add.l${Q} #${Imm-12-s4},$Dst32AnUnprefixedSI */
77947
  {
77948
    { 0, 0, 0, 0 },
77949
    { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
77950
    & ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_An_direct_Unprefixed_SI, { 0xf0b0 }
77951
  },
77952
/* add.l${Q} #${Imm-12-s4},[$Dst32AnUnprefixed] */
77953
  {
77954
    { 0, 0, 0, 0 },
77955
    { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
77956
    & ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_An_indirect_Unprefixed_SI, { 0xf030 }
77957
  },
77958
/* add.l${Q} #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
77959
  {
77960
    { 0, 0, 0, 0 },
77961
    { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
77962
    & ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_16_8_An_relative_Unprefixed_SI, { 0xf23000 }
77963
  },
77964
/* add.l${Q} #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
77965
  {
77966
    { 0, 0, 0, 0 },
77967
    { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
77968
    & ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_SI, { 0xf4300000 }
77969
  },
77970
/* add.l${Q} #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
77971
  {
77972
    { 0, 0, 0, 0 },
77973
    { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
77974
    & ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_16_24_An_relative_Unprefixed_SI, { 0xf6300000 }
77975
  },
77976
/* add.l${Q} #${Imm-12-s4},${Dsp-16-u8}[sb] */
77977
  {
77978
    { 0, 0, 0, 0 },
77979
    { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
77980
    & ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_16_8_SB_relative_Unprefixed_SI, { 0xf2b000 }
77981
  },
77982
/* add.l${Q} #${Imm-12-s4},${Dsp-16-u16}[sb] */
77983
  {
77984
    { 0, 0, 0, 0 },
77985
    { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
77986
    & ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_SI, { 0xf4b00000 }
77987
  },
77988
/* add.l${Q} #${Imm-12-s4},${Dsp-16-s8}[fb] */
77989
  {
77990
    { 0, 0, 0, 0 },
77991
    { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
77992
    & ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_16_8_FB_relative_Unprefixed_SI, { 0xf2f000 }
77993
  },
77994
/* add.l${Q} #${Imm-12-s4},${Dsp-16-s16}[fb] */
77995
  {
77996
    { 0, 0, 0, 0 },
77997
    { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
77998
    & ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_SI, { 0xf4f00000 }
77999
  },
78000
/* add.l${Q} #${Imm-12-s4},${Dsp-16-u16} */
78001
  {
78002
    { 0, 0, 0, 0 },
78003
    { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), 0 } },
78004
    & ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_16_16_absolute_Unprefixed_SI, { 0xf6f00000 }
78005
  },
78006
/* add.l${Q} #${Imm-12-s4},${Dsp-16-u24} */
78007
  {
78008
    { 0, 0, 0, 0 },
78009
    { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U24), 0 } },
78010
    & ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_16_24_absolute_Unprefixed_SI, { 0xf6b00000 }
78011
  },
78012
/* add.w${Q} #${Imm-12-s4},$Dst32RnUnprefixedHI */
78013
  {
78014
    { 0, 0, 0, 0 },
78015
    { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
78016
    & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0xe930 }
78017
  },
78018
/* add.w${Q} #${Imm-12-s4},$Dst32AnUnprefixedHI */
78019
  {
78020
    { 0, 0, 0, 0 },
78021
    { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
78022
    & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0xe1b0 }
78023
  },
78024
/* add.w${Q} #${Imm-12-s4},[$Dst32AnUnprefixed] */
78025
  {
78026
    { 0, 0, 0, 0 },
78027
    { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
78028
    & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0xe130 }
78029
  },
78030
/* add.w${Q} #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
78031
  {
78032
    { 0, 0, 0, 0 },
78033
    { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
78034
    & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0xe33000 }
78035
  },
78036
/* add.w${Q} #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
78037
  {
78038
    { 0, 0, 0, 0 },
78039
    { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
78040
    & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0xe5300000 }
78041
  },
78042
/* add.w${Q} #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
78043
  {
78044
    { 0, 0, 0, 0 },
78045
    { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
78046
    & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0xe7300000 }
78047
  },
78048
/* add.w${Q} #${Imm-12-s4},${Dsp-16-u8}[sb] */
78049
  {
78050
    { 0, 0, 0, 0 },
78051
    { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
78052
    & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0xe3b000 }
78053
  },
78054
/* add.w${Q} #${Imm-12-s4},${Dsp-16-u16}[sb] */
78055
  {
78056
    { 0, 0, 0, 0 },
78057
    { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
78058
    & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0xe5b00000 }
78059
  },
78060
/* add.w${Q} #${Imm-12-s4},${Dsp-16-s8}[fb] */
78061
  {
78062
    { 0, 0, 0, 0 },
78063
    { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
78064
    & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0xe3f000 }
78065
  },
78066
/* add.w${Q} #${Imm-12-s4},${Dsp-16-s16}[fb] */
78067
  {
78068
    { 0, 0, 0, 0 },
78069
    { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
78070
    & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0xe5f00000 }
78071
  },
78072
/* add.w${Q} #${Imm-12-s4},${Dsp-16-u16} */
78073
  {
78074
    { 0, 0, 0, 0 },
78075
    { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), 0 } },
78076
    & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0xe7f00000 }
78077
  },
78078
/* add.w${Q} #${Imm-12-s4},${Dsp-16-u24} */
78079
  {
78080
    { 0, 0, 0, 0 },
78081
    { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U24), 0 } },
78082
    & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0xe7b00000 }
78083
  },
78084
/* add.b${Q} #${Imm-12-s4},$Dst32RnUnprefixedQI */
78085
  {
78086
    { 0, 0, 0, 0 },
78087
    { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
78088
    & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0xe830 }
78089
  },
78090
/* add.b${Q} #${Imm-12-s4},$Dst32AnUnprefixedQI */
78091
  {
78092
    { 0, 0, 0, 0 },
78093
    { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
78094
    & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0xe0b0 }
78095
  },
78096
/* add.b${Q} #${Imm-12-s4},[$Dst32AnUnprefixed] */
78097
  {
78098
    { 0, 0, 0, 0 },
78099
    { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
78100
    & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0xe030 }
78101
  },
78102
/* add.b${Q} #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
78103
  {
78104
    { 0, 0, 0, 0 },
78105
    { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
78106
    & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0xe23000 }
78107
  },
78108
/* add.b${Q} #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
78109
  {
78110
    { 0, 0, 0, 0 },
78111
    { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
78112
    & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0xe4300000 }
78113
  },
78114
/* add.b${Q} #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
78115
  {
78116
    { 0, 0, 0, 0 },
78117
    { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
78118
    & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0xe6300000 }
78119
  },
78120
/* add.b${Q} #${Imm-12-s4},${Dsp-16-u8}[sb] */
78121
  {
78122
    { 0, 0, 0, 0 },
78123
    { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
78124
    & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0xe2b000 }
78125
  },
78126
/* add.b${Q} #${Imm-12-s4},${Dsp-16-u16}[sb] */
78127
  {
78128
    { 0, 0, 0, 0 },
78129
    { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
78130
    & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0xe4b00000 }
78131
  },
78132
/* add.b${Q} #${Imm-12-s4},${Dsp-16-s8}[fb] */
78133
  {
78134
    { 0, 0, 0, 0 },
78135
    { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
78136
    & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0xe2f000 }
78137
  },
78138
/* add.b${Q} #${Imm-12-s4},${Dsp-16-s16}[fb] */
78139
  {
78140
    { 0, 0, 0, 0 },
78141
    { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
78142
    & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0xe4f00000 }
78143
  },
78144
/* add.b${Q} #${Imm-12-s4},${Dsp-16-u16} */
78145
  {
78146
    { 0, 0, 0, 0 },
78147
    { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), 0 } },
78148
    & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0xe6f00000 }
78149
  },
78150
/* add.b${Q} #${Imm-12-s4},${Dsp-16-u24} */
78151
  {
78152
    { 0, 0, 0, 0 },
78153
    { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U24), 0 } },
78154
    & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0xe6b00000 }
78155
  },
78156
/* add.w${Q} #${Imm-8-s4},$Dst16RnHI */
78157
  {
78158
    { 0, 0, 0, 0 },
78159
    { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DST16RNHI), 0 } },
78160
    & ifmt_mov16_w_imm4_Q_16_dst16_Rn_direct_HI, { 0xc900 }
78161
  },
78162
/* add.w${Q} #${Imm-8-s4},$Dst16AnHI */
78163
  {
78164
    { 0, 0, 0, 0 },
78165
    { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DST16ANHI), 0 } },
78166
    & ifmt_mov16_w_imm4_Q_16_dst16_An_direct_HI, { 0xc904 }
78167
  },
78168
/* add.w${Q} #${Imm-8-s4},[$Dst16An] */
78169
  {
78170
    { 0, 0, 0, 0 },
78171
    { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', '[', OP (DST16AN), ']', 0 } },
78172
    & ifmt_mov16_w_imm4_Q_16_dst16_An_indirect_HI, { 0xc906 }
78173
  },
78174
/* add.w${Q} #${Imm-8-s4},${Dsp-16-u8}[$Dst16An] */
78175
  {
78176
    { 0, 0, 0, 0 },
78177
    { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
78178
    & ifmt_mov16_w_imm4_Q_16_dst16_16_8_An_relative_HI, { 0xc90800 }
78179
  },
78180
/* add.w${Q} #${Imm-8-s4},${Dsp-16-u16}[$Dst16An] */
78181
  {
78182
    { 0, 0, 0, 0 },
78183
    { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
78184
    & ifmt_mov16_w_imm4_Q_16_dst16_16_16_An_relative_HI, { 0xc90c0000 }
78185
  },
78186
/* add.w${Q} #${Imm-8-s4},${Dsp-16-u8}[sb] */
78187
  {
78188
    { 0, 0, 0, 0 },
78189
    { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
78190
    & ifmt_mov16_w_imm4_Q_16_dst16_16_8_SB_relative_HI, { 0xc90a00 }
78191
  },
78192
/* add.w${Q} #${Imm-8-s4},${Dsp-16-u16}[sb] */
78193
  {
78194
    { 0, 0, 0, 0 },
78195
    { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
78196
    & ifmt_mov16_w_imm4_Q_16_dst16_16_16_SB_relative_HI, { 0xc90e0000 }
78197
  },
78198
/* add.w${Q} #${Imm-8-s4},${Dsp-16-s8}[fb] */
78199
  {
78200
    { 0, 0, 0, 0 },
78201
    { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
78202
    & ifmt_mov16_w_imm4_Q_16_dst16_16_8_FB_relative_HI, { 0xc90b00 }
78203
  },
78204
/* add.w${Q} #${Imm-8-s4},${Dsp-16-u16} */
78205
  {
78206
    { 0, 0, 0, 0 },
78207
    { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), 0 } },
78208
    & ifmt_mov16_w_imm4_Q_16_dst16_16_16_absolute_HI, { 0xc90f0000 }
78209
  },
78210
/* add.b${Q} #${Imm-8-s4},$Dst16RnQI */
78211
  {
78212
    { 0, 0, 0, 0 },
78213
    { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DST16RNQI), 0 } },
78214
    & ifmt_mov16_b_imm4_Q_16_dst16_Rn_direct_QI, { 0xc800 }
78215
  },
78216
/* add.b${Q} #${Imm-8-s4},$Dst16AnQI */
78217
  {
78218
    { 0, 0, 0, 0 },
78219
    { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DST16ANQI), 0 } },
78220
    & ifmt_mov16_b_imm4_Q_16_dst16_An_direct_QI, { 0xc804 }
78221
  },
78222
/* add.b${Q} #${Imm-8-s4},[$Dst16An] */
78223
  {
78224
    { 0, 0, 0, 0 },
78225
    { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', '[', OP (DST16AN), ']', 0 } },
78226
    & ifmt_mov16_b_imm4_Q_16_dst16_An_indirect_QI, { 0xc806 }
78227
  },
78228
/* add.b${Q} #${Imm-8-s4},${Dsp-16-u8}[$Dst16An] */
78229
  {
78230
    { 0, 0, 0, 0 },
78231
    { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
78232
    & ifmt_mov16_b_imm4_Q_16_dst16_16_8_An_relative_QI, { 0xc80800 }
78233
  },
78234
/* add.b${Q} #${Imm-8-s4},${Dsp-16-u16}[$Dst16An] */
78235
  {
78236
    { 0, 0, 0, 0 },
78237
    { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
78238
    & ifmt_mov16_b_imm4_Q_16_dst16_16_16_An_relative_QI, { 0xc80c0000 }
78239
  },
78240
/* add.b${Q} #${Imm-8-s4},${Dsp-16-u8}[sb] */
78241
  {
78242
    { 0, 0, 0, 0 },
78243
    { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
78244
    & ifmt_mov16_b_imm4_Q_16_dst16_16_8_SB_relative_QI, { 0xc80a00 }
78245
  },
78246
/* add.b${Q} #${Imm-8-s4},${Dsp-16-u16}[sb] */
78247
  {
78248
    { 0, 0, 0, 0 },
78249
    { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
78250
    & ifmt_mov16_b_imm4_Q_16_dst16_16_16_SB_relative_QI, { 0xc80e0000 }
78251
  },
78252
/* add.b${Q} #${Imm-8-s4},${Dsp-16-s8}[fb] */
78253
  {
78254
    { 0, 0, 0, 0 },
78255
    { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
78256
    & ifmt_mov16_b_imm4_Q_16_dst16_16_8_FB_relative_QI, { 0xc80b00 }
78257
  },
78258
/* add.b${Q} #${Imm-8-s4},${Dsp-16-u16} */
78259
  {
78260
    { 0, 0, 0, 0 },
78261
    { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), 0 } },
78262
    & ifmt_mov16_b_imm4_Q_16_dst16_16_16_absolute_QI, { 0xc80f0000 }
78263
  },
78264
/* add.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */
78265
  {
78266
    { 0, 0, 0, 0 },
78267
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST32RNUNPREFIXEDHI), 0 } },
78268
    & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0x892e0000 }
78269
  },
78270
/* add.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */
78271
  {
78272
    { 0, 0, 0, 0 },
78273
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST32ANUNPREFIXEDHI), 0 } },
78274
    & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0x81ae0000 }
78275
  },
78276
/* add.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */
78277
  {
78278
    { 0, 0, 0, 0 },
78279
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
78280
    & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0x812e0000 }
78281
  },
78282
/* add.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
78283
  {
78284
    { 0, 0, 0, 0 },
78285
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
78286
    & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0x832e0000 }
78287
  },
78288
/* add.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
78289
  {
78290
    { 0, 0, 0, 0 },
78291
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
78292
    & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0x83ae0000 }
78293
  },
78294
/* add.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
78295
  {
78296
    { 0, 0, 0, 0 },
78297
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
78298
    & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83ee0000 }
78299
  },
78300
/* add.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
78301
  {
78302
    { 0, 0, 0, 0 },
78303
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
78304
    & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0x852e0000 }
78305
  },
78306
/* add.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
78307
  {
78308
    { 0, 0, 0, 0 },
78309
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
78310
    & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0x85ae0000 }
78311
  },
78312
/* add.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */
78313
  {
78314
    { 0, 0, 0, 0 },
78315
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
78316
    & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85ee0000 }
78317
  },
78318
/* add.w${G} #${Imm-32-HI},${Dsp-16-u16} */
78319
  {
78320
    { 0, 0, 0, 0 },
78321
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } },
78322
    & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0x87ee0000 }
78323
  },
78324
/* add.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
78325
  {
78326
    { 0, 0, 0, 0 },
78327
    { { MNEM, OP (G), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
78328
    & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0x872e0000 }
78329
  },
78330
/* add.w${G} #${Imm-40-HI},${Dsp-16-u24} */
78331
  {
78332
    { 0, 0, 0, 0 },
78333
    { { MNEM, OP (G), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), 0 } },
78334
    & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0x87ae0000 }
78335
  },
78336
/* add.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */
78337
  {
78338
    { 0, 0, 0, 0 },
78339
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST32RNUNPREFIXEDQI), 0 } },
78340
    & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0x882e00 }
78341
  },
78342
/* add.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */
78343
  {
78344
    { 0, 0, 0, 0 },
78345
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST32ANUNPREFIXEDQI), 0 } },
78346
    & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0x80ae00 }
78347
  },
78348
/* add.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */
78349
  {
78350
    { 0, 0, 0, 0 },
78351
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
78352
    & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0x802e00 }
78353
  },
78354
/* add.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
78355
  {
78356
    { 0, 0, 0, 0 },
78357
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
78358
    & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0x822e0000 }
78359
  },
78360
/* add.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
78361
  {
78362
    { 0, 0, 0, 0 },
78363
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
78364
    & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0x82ae0000 }
78365
  },
78366
/* add.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
78367
  {
78368
    { 0, 0, 0, 0 },
78369
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
78370
    & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82ee0000 }
78371
  },
78372
/* add.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
78373
  {
78374
    { 0, 0, 0, 0 },
78375
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
78376
    & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0x842e0000 }
78377
  },
78378
/* add.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
78379
  {
78380
    { 0, 0, 0, 0 },
78381
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
78382
    & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0x84ae0000 }
78383
  },
78384
/* add.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */
78385
  {
78386
    { 0, 0, 0, 0 },
78387
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
78388
    & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84ee0000 }
78389
  },
78390
/* add.b${G} #${Imm-32-QI},${Dsp-16-u16} */
78391
  {
78392
    { 0, 0, 0, 0 },
78393
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } },
78394
    & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0x86ee0000 }
78395
  },
78396
/* add.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
78397
  {
78398
    { 0, 0, 0, 0 },
78399
    { { MNEM, OP (G), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
78400
    & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0x862e0000 }
78401
  },
78402
/* add.b${G} #${Imm-40-QI},${Dsp-16-u24} */
78403
  {
78404
    { 0, 0, 0, 0 },
78405
    { { MNEM, OP (G), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), 0 } },
78406
    & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0x86ae0000 }
78407
  },
78408
/* add.w${G} #${Imm-16-HI},$Dst16RnHI */
78409
  {
78410
    { 0, 0, 0, 0 },
78411
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST16RNHI), 0 } },
78412
    & ifmt_xor16_w_imm_G_basic_dst16_Rn_direct_HI, { 0x77400000 }
78413
  },
78414
/* add.w${G} #${Imm-16-HI},$Dst16AnHI */
78415
  {
78416
    { 0, 0, 0, 0 },
78417
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST16ANHI), 0 } },
78418
    & ifmt_xor16_w_imm_G_basic_dst16_An_direct_HI, { 0x77440000 }
78419
  },
78420
/* add.w${G} #${Imm-16-HI},[$Dst16An] */
78421
  {
78422
    { 0, 0, 0, 0 },
78423
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST16AN), ']', 0 } },
78424
    & ifmt_xor16_w_imm_G_basic_dst16_An_indirect_HI, { 0x77460000 }
78425
  },
78426
/* add.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
78427
  {
78428
    { 0, 0, 0, 0 },
78429
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
78430
    & ifmt_xor16_w_imm_G_16_8_dst16_16_8_An_relative_HI, { 0x77480000 }
78431
  },
78432
/* add.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
78433
  {
78434
    { 0, 0, 0, 0 },
78435
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
78436
    & ifmt_xor16_w_imm_G_16_8_dst16_16_8_SB_relative_HI, { 0x774a0000 }
78437
  },
78438
/* add.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
78439
  {
78440
    { 0, 0, 0, 0 },
78441
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
78442
    & ifmt_xor16_w_imm_G_16_8_dst16_16_8_FB_relative_HI, { 0x774b0000 }
78443
  },
78444
/* add.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
78445
  {
78446
    { 0, 0, 0, 0 },
78447
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
78448
    & ifmt_xor16_w_imm_G_16_16_dst16_16_16_An_relative_HI, { 0x774c0000 }
78449
  },
78450
/* add.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
78451
  {
78452
    { 0, 0, 0, 0 },
78453
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
78454
    & ifmt_xor16_w_imm_G_16_16_dst16_16_16_SB_relative_HI, { 0x774e0000 }
78455
  },
78456
/* add.w${G} #${Imm-32-HI},${Dsp-16-u16} */
78457
  {
78458
    { 0, 0, 0, 0 },
78459
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } },
78460
    & ifmt_xor16_w_imm_G_16_16_dst16_16_16_absolute_HI, { 0x774f0000 }
78461
  },
78462
/* add.b${G} #${Imm-16-QI},$Dst16RnQI */
78463
  {
78464
    { 0, 0, 0, 0 },
78465
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST16RNQI), 0 } },
78466
    & ifmt_xor16_b_imm_G_basic_dst16_Rn_direct_QI, { 0x764000 }
78467
  },
78468
/* add.b${G} #${Imm-16-QI},$Dst16AnQI */
78469
  {
78470
    { 0, 0, 0, 0 },
78471
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST16ANQI), 0 } },
78472
    & ifmt_xor16_b_imm_G_basic_dst16_An_direct_QI, { 0x764400 }
78473
  },
78474
/* add.b${G} #${Imm-16-QI},[$Dst16An] */
78475
  {
78476
    { 0, 0, 0, 0 },
78477
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST16AN), ']', 0 } },
78478
    & ifmt_xor16_b_imm_G_basic_dst16_An_indirect_QI, { 0x764600 }
78479
  },
78480
/* add.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
78481
  {
78482
    { 0, 0, 0, 0 },
78483
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
78484
    & ifmt_xor16_b_imm_G_16_8_dst16_16_8_An_relative_QI, { 0x76480000 }
78485
  },
78486
/* add.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
78487
  {
78488
    { 0, 0, 0, 0 },
78489
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
78490
    & ifmt_xor16_b_imm_G_16_8_dst16_16_8_SB_relative_QI, { 0x764a0000 }
78491
  },
78492
/* add.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
78493
  {
78494
    { 0, 0, 0, 0 },
78495
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
78496
    & ifmt_xor16_b_imm_G_16_8_dst16_16_8_FB_relative_QI, { 0x764b0000 }
78497
  },
78498
/* add.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
78499
  {
78500
    { 0, 0, 0, 0 },
78501
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
78502
    & ifmt_xor16_b_imm_G_16_16_dst16_16_16_An_relative_QI, { 0x764c0000 }
78503
  },
78504
/* add.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
78505
  {
78506
    { 0, 0, 0, 0 },
78507
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
78508
    & ifmt_xor16_b_imm_G_16_16_dst16_16_16_SB_relative_QI, { 0x764e0000 }
78509
  },
78510
/* add.b${G} #${Imm-32-QI},${Dsp-16-u16} */
78511
  {
78512
    { 0, 0, 0, 0 },
78513
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } },
78514
    & ifmt_xor16_b_imm_G_16_16_dst16_16_16_absolute_QI, { 0x764f0000 }
78515
  },
78516
/* add.l${G} #${Imm-16-SI},$Dst32RnUnprefixedSI */
78517
  {
78518
    { 0, 0, 0, 0 },
78519
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_SI), ',', OP (DST32RNUNPREFIXEDSI), 0 } },
78520
    & ifmt_mov32_l_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_SI, { 0x88310000 }
78521
  },
78522
/* add.l${G} #${Imm-16-SI},$Dst32AnUnprefixedSI */
78523
  {
78524
    { 0, 0, 0, 0 },
78525
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_SI), ',', OP (DST32ANUNPREFIXEDSI), 0 } },
78526
    & ifmt_mov32_l_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_SI, { 0x80b10000 }
78527
  },
78528
/* add.l${G} #${Imm-16-SI},[$Dst32AnUnprefixed] */
78529
  {
78530
    { 0, 0, 0, 0 },
78531
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_SI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
78532
    & ifmt_mov32_l_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_SI, { 0x80310000 }
78533
  },
78534
/* add.l${G} #${Imm-24-SI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
78535
  {
78536
    { 0, 0, 0, 0 },
78537
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_SI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
78538
    & ifmt_mov32_l_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_SI, { 0x82310000 }
78539
  },
78540
/* add.l${G} #${Imm-24-SI},${Dsp-16-u8}[sb] */
78541
  {
78542
    { 0, 0, 0, 0 },
78543
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_SI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
78544
    & ifmt_mov32_l_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_SI, { 0x82b10000 }
78545
  },
78546
/* add.l${G} #${Imm-24-SI},${Dsp-16-s8}[fb] */
78547
  {
78548
    { 0, 0, 0, 0 },
78549
    { { MNEM, OP (G), ' ', '#', OP (IMM_24_SI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
78550
    & ifmt_mov32_l_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_SI, { 0x82f10000 }
78551
  },
78552
/* add.l${G} #${Imm-32-SI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
78553
  {
78554
    { 0, 0, 0, 0 },
78555
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_SI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
78556
    & ifmt_mov32_l_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_SI, { 0x84310000 }
78557
  },
78558
/* add.l${G} #${Imm-32-SI},${Dsp-16-u16}[sb] */
78559
  {
78560
    { 0, 0, 0, 0 },
78561
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_SI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
78562
    & ifmt_mov32_l_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_SI, { 0x84b10000 }
78563
  },
78564
/* add.l${G} #${Imm-32-SI},${Dsp-16-s16}[fb] */
78565
  {
78566
    { 0, 0, 0, 0 },
78567
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_SI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
78568
    & ifmt_mov32_l_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_SI, { 0x84f10000 }
78569
  },
78570
/* add.l${G} #${Imm-32-SI},${Dsp-16-u16} */
78571
  {
78572
    { 0, 0, 0, 0 },
78573
    { { MNEM, OP (G), ' ', '#', OP (IMM_32_SI), ',', OP (DSP_16_U16), 0 } },
78574
    & ifmt_mov32_l_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_SI, { 0x86f10000 }
78575
  },
78576
/* add.l${G} #${Imm-40-SI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
78577
  {
78578
    { 0, 0, 0, 0 },
78579
    { { MNEM, OP (G), ' ', '#', OP (IMM_40_SI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
78580
    & ifmt_mov32_l_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_SI, { 0x86310000 }
78581
  },
78582
/* add.l${G} #${Imm-40-SI},${Dsp-16-u24} */
78583
  {
78584
    { 0, 0, 0, 0 },
78585
    { { MNEM, OP (G), ' ', '#', OP (IMM_40_SI), ',', OP (DSP_16_U24), 0 } },
78586
    & ifmt_mov32_l_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_SI, { 0x86b10000 }
78587
  },
78588
/* adcf.w $Dst32RnUnprefixedHI */
78589
  {
78590
    { 0, 0, 0, 0 },
78591
    { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } },
78592
    & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xb91e }
78593
  },
78594
/* adcf.w $Dst32AnUnprefixedHI */
78595
  {
78596
    { 0, 0, 0, 0 },
78597
    { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } },
78598
    & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xb19e }
78599
  },
78600
/* adcf.w [$Dst32AnUnprefixed] */
78601
  {
78602
    { 0, 0, 0, 0 },
78603
    { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
78604
    & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xb11e }
78605
  },
78606
/* adcf.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
78607
  {
78608
    { 0, 0, 0, 0 },
78609
    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
78610
    & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xb31e00 }
78611
  },
78612
/* adcf.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
78613
  {
78614
    { 0, 0, 0, 0 },
78615
    { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
78616
    & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xb51e0000 }
78617
  },
78618
/* adcf.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
78619
  {
78620
    { 0, 0, 0, 0 },
78621
    { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
78622
    & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xb71e0000 }
78623
  },
78624
/* adcf.w ${Dsp-16-u8}[sb] */
78625
  {
78626
    { 0, 0, 0, 0 },
78627
    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
78628
    & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xb39e00 }
78629
  },
78630
/* adcf.w ${Dsp-16-u16}[sb] */
78631
  {
78632
    { 0, 0, 0, 0 },
78633
    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
78634
    & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xb59e0000 }
78635
  },
78636
/* adcf.w ${Dsp-16-s8}[fb] */
78637
  {
78638
    { 0, 0, 0, 0 },
78639
    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
78640
    & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xb3de00 }
78641
  },
78642
/* adcf.w ${Dsp-16-s16}[fb] */
78643
  {
78644
    { 0, 0, 0, 0 },
78645
    { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
78646
    & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xb5de0000 }
78647
  },
78648
/* adcf.w ${Dsp-16-u16} */
78649
  {
78650
    { 0, 0, 0, 0 },
78651
    { { MNEM, ' ', OP (DSP_16_U16), 0 } },
78652
    & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xb7de0000 }
78653
  },
78654
/* adcf.w ${Dsp-16-u24} */
78655
  {
78656
    { 0, 0, 0, 0 },
78657
    { { MNEM, ' ', OP (DSP_16_U24), 0 } },
78658
    & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xb79e0000 }
78659
  },
78660
/* adcf.b $Dst32RnUnprefixedQI */
78661
  {
78662
    { 0, 0, 0, 0 },
78663
    { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } },
78664
    & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0xb81e }
78665
  },
78666
/* adcf.b $Dst32AnUnprefixedQI */
78667
  {
78668
    { 0, 0, 0, 0 },
78669
    { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } },
78670
    & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0xb09e }
78671
  },
78672
/* adcf.b [$Dst32AnUnprefixed] */
78673
  {
78674
    { 0, 0, 0, 0 },
78675
    { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
78676
    & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0xb01e }
78677
  },
78678
/* adcf.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
78679
  {
78680
    { 0, 0, 0, 0 },
78681
    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
78682
    & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0xb21e00 }
78683
  },
78684
/* adcf.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
78685
  {
78686
    { 0, 0, 0, 0 },
78687
    { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
78688
    & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0xb41e0000 }
78689
  },
78690
/* adcf.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
78691
  {
78692
    { 0, 0, 0, 0 },
78693
    { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
78694
    & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0xb61e0000 }
78695
  },
78696
/* adcf.b ${Dsp-16-u8}[sb] */
78697
  {
78698
    { 0, 0, 0, 0 },
78699
    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
78700
    & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0xb29e00 }
78701
  },
78702
/* adcf.b ${Dsp-16-u16}[sb] */
78703
  {
78704
    { 0, 0, 0, 0 },
78705
    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
78706
    & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0xb49e0000 }
78707
  },
78708
/* adcf.b ${Dsp-16-s8}[fb] */
78709
  {
78710
    { 0, 0, 0, 0 },
78711
    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
78712
    & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0xb2de00 }
78713
  },
78714
/* adcf.b ${Dsp-16-s16}[fb] */
78715
  {
78716
    { 0, 0, 0, 0 },
78717
    { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
78718
    & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0xb4de0000 }
78719
  },
78720
/* adcf.b ${Dsp-16-u16} */
78721
  {
78722
    { 0, 0, 0, 0 },
78723
    { { MNEM, ' ', OP (DSP_16_U16), 0 } },
78724
    & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0xb6de0000 }
78725
  },
78726
/* adcf.b ${Dsp-16-u24} */
78727
  {
78728
    { 0, 0, 0, 0 },
78729
    { { MNEM, ' ', OP (DSP_16_U24), 0 } },
78730
    & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0xb69e0000 }
78731
  },
78732
/* adcf.w $Dst16RnHI */
78733
  {
78734
    { 0, 0, 0, 0 },
78735
    { { MNEM, ' ', OP (DST16RNHI), 0 } },
78736
    & ifmt_rorc16_w_16_dst16_Rn_direct_HI, { 0x77e0 }
78737
  },
78738
/* adcf.w $Dst16AnHI */
78739
  {
78740
    { 0, 0, 0, 0 },
78741
    { { MNEM, ' ', OP (DST16ANHI), 0 } },
78742
    & ifmt_rorc16_w_16_dst16_An_direct_HI, { 0x77e4 }
78743
  },
78744
/* adcf.w [$Dst16An] */
78745
  {
78746
    { 0, 0, 0, 0 },
78747
    { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } },
78748
    & ifmt_rorc16_w_16_dst16_An_indirect_HI, { 0x77e6 }
78749
  },
78750
/* adcf.w ${Dsp-16-u8}[$Dst16An] */
78751
  {
78752
    { 0, 0, 0, 0 },
78753
    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
78754
    & ifmt_rorc16_w_16_dst16_16_8_An_relative_HI, { 0x77e800 }
78755
  },
78756
/* adcf.w ${Dsp-16-u16}[$Dst16An] */
78757
  {
78758
    { 0, 0, 0, 0 },
78759
    { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
78760
    & ifmt_rorc16_w_16_dst16_16_16_An_relative_HI, { 0x77ec0000 }
78761
  },
78762
/* adcf.w ${Dsp-16-u8}[sb] */
78763
  {
78764
    { 0, 0, 0, 0 },
78765
    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
78766
    & ifmt_rorc16_w_16_dst16_16_8_SB_relative_HI, { 0x77ea00 }
78767
  },
78768
/* adcf.w ${Dsp-16-u16}[sb] */
78769
  {
78770
    { 0, 0, 0, 0 },
78771
    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
78772
    & ifmt_rorc16_w_16_dst16_16_16_SB_relative_HI, { 0x77ee0000 }
78773
  },
78774
/* adcf.w ${Dsp-16-s8}[fb] */
78775
  {
78776
    { 0, 0, 0, 0 },
78777
    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
78778
    & ifmt_rorc16_w_16_dst16_16_8_FB_relative_HI, { 0x77eb00 }
78779
  },
78780
/* adcf.w ${Dsp-16-u16} */
78781
  {
78782
    { 0, 0, 0, 0 },
78783
    { { MNEM, ' ', OP (DSP_16_U16), 0 } },
78784
    & ifmt_rorc16_w_16_dst16_16_16_absolute_HI, { 0x77ef0000 }
78785
  },
78786
/* adcf.b $Dst16RnQI */
78787
  {
78788
    { 0, 0, 0, 0 },
78789
    { { MNEM, ' ', OP (DST16RNQI), 0 } },
78790
    & ifmt_rorc16_b_16_dst16_Rn_direct_QI, { 0x76e0 }
78791
  },
78792
/* adcf.b $Dst16AnQI */
78793
  {
78794
    { 0, 0, 0, 0 },
78795
    { { MNEM, ' ', OP (DST16ANQI), 0 } },
78796
    & ifmt_rorc16_b_16_dst16_An_direct_QI, { 0x76e4 }
78797
  },
78798
/* adcf.b [$Dst16An] */
78799
  {
78800
    { 0, 0, 0, 0 },
78801
    { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } },
78802
    & ifmt_rorc16_b_16_dst16_An_indirect_QI, { 0x76e6 }
78803
  },
78804
/* adcf.b ${Dsp-16-u8}[$Dst16An] */
78805
  {
78806
    { 0, 0, 0, 0 },
78807
    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
78808
    & ifmt_rorc16_b_16_dst16_16_8_An_relative_QI, { 0x76e800 }
78809
  },
78810
/* adcf.b ${Dsp-16-u16}[$Dst16An] */
78811
  {
78812
    { 0, 0, 0, 0 },
78813
    { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
78814
    & ifmt_rorc16_b_16_dst16_16_16_An_relative_QI, { 0x76ec0000 }
78815
  },
78816
/* adcf.b ${Dsp-16-u8}[sb] */
78817
  {
78818
    { 0, 0, 0, 0 },
78819
    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
78820
    & ifmt_rorc16_b_16_dst16_16_8_SB_relative_QI, { 0x76ea00 }
78821
  },
78822
/* adcf.b ${Dsp-16-u16}[sb] */
78823
  {
78824
    { 0, 0, 0, 0 },
78825
    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
78826
    & ifmt_rorc16_b_16_dst16_16_16_SB_relative_QI, { 0x76ee0000 }
78827
  },
78828
/* adcf.b ${Dsp-16-s8}[fb] */
78829
  {
78830
    { 0, 0, 0, 0 },
78831
    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
78832
    & ifmt_rorc16_b_16_dst16_16_8_FB_relative_QI, { 0x76eb00 }
78833
  },
78834
/* adcf.b ${Dsp-16-u16} */
78835
  {
78836
    { 0, 0, 0, 0 },
78837
    { { MNEM, ' ', OP (DSP_16_U16), 0 } },
78838
    & ifmt_rorc16_b_16_dst16_16_16_absolute_QI, { 0x76ef0000 }
78839
  },
78840
/* abs.w $Dst32RnUnprefixedHI */
78841
  {
78842
    { 0, 0, 0, 0 },
78843
    { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } },
78844
    & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xa91f }
78845
  },
78846
/* abs.w $Dst32AnUnprefixedHI */
78847
  {
78848
    { 0, 0, 0, 0 },
78849
    { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } },
78850
    & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xa19f }
78851
  },
78852
/* abs.w [$Dst32AnUnprefixed] */
78853
  {
78854
    { 0, 0, 0, 0 },
78855
    { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
78856
    & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xa11f }
78857
  },
78858
/* abs.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
78859
  {
78860
    { 0, 0, 0, 0 },
78861
    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
78862
    & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xa31f00 }
78863
  },
78864
/* abs.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
78865
  {
78866
    { 0, 0, 0, 0 },
78867
    { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
78868
    & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xa51f0000 }
78869
  },
78870
/* abs.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
78871
  {
78872
    { 0, 0, 0, 0 },
78873
    { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
78874
    & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xa71f0000 }
78875
  },
78876
/* abs.w ${Dsp-16-u8}[sb] */
78877
  {
78878
    { 0, 0, 0, 0 },
78879
    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
78880
    & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xa39f00 }
78881
  },
78882
/* abs.w ${Dsp-16-u16}[sb] */
78883
  {
78884
    { 0, 0, 0, 0 },
78885
    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
78886
    & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xa59f0000 }
78887
  },
78888
/* abs.w ${Dsp-16-s8}[fb] */
78889
  {
78890
    { 0, 0, 0, 0 },
78891
    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
78892
    & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xa3df00 }
78893
  },
78894
/* abs.w ${Dsp-16-s16}[fb] */
78895
  {
78896
    { 0, 0, 0, 0 },
78897
    { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
78898
    & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xa5df0000 }
78899
  },
78900
/* abs.w ${Dsp-16-u16} */
78901
  {
78902
    { 0, 0, 0, 0 },
78903
    { { MNEM, ' ', OP (DSP_16_U16), 0 } },
78904
    & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xa7df0000 }
78905
  },
78906
/* abs.w ${Dsp-16-u24} */
78907
  {
78908
    { 0, 0, 0, 0 },
78909
    { { MNEM, ' ', OP (DSP_16_U24), 0 } },
78910
    & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xa79f0000 }
78911
  },
78912
/* abs.b $Dst32RnUnprefixedQI */
78913
  {
78914
    { 0, 0, 0, 0 },
78915
    { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } },
78916
    & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0xa81f }
78917
  },
78918
/* abs.b $Dst32AnUnprefixedQI */
78919
  {
78920
    { 0, 0, 0, 0 },
78921
    { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } },
78922
    & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0xa09f }
78923
  },
78924
/* abs.b [$Dst32AnUnprefixed] */
78925
  {
78926
    { 0, 0, 0, 0 },
78927
    { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } },
78928
    & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0xa01f }
78929
  },
78930
/* abs.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
78931
  {
78932
    { 0, 0, 0, 0 },
78933
    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
78934
    & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0xa21f00 }
78935
  },
78936
/* abs.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
78937
  {
78938
    { 0, 0, 0, 0 },
78939
    { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
78940
    & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0xa41f0000 }
78941
  },
78942
/* abs.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
78943
  {
78944
    { 0, 0, 0, 0 },
78945
    { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } },
78946
    & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0xa61f0000 }
78947
  },
78948
/* abs.b ${Dsp-16-u8}[sb] */
78949
  {
78950
    { 0, 0, 0, 0 },
78951
    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
78952
    & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0xa29f00 }
78953
  },
78954
/* abs.b ${Dsp-16-u16}[sb] */
78955
  {
78956
    { 0, 0, 0, 0 },
78957
    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
78958
    & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0xa49f0000 }
78959
  },
78960
/* abs.b ${Dsp-16-s8}[fb] */
78961
  {
78962
    { 0, 0, 0, 0 },
78963
    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
78964
    & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0xa2df00 }
78965
  },
78966
/* abs.b ${Dsp-16-s16}[fb] */
78967
  {
78968
    { 0, 0, 0, 0 },
78969
    { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } },
78970
    & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0xa4df0000 }
78971
  },
78972
/* abs.b ${Dsp-16-u16} */
78973
  {
78974
    { 0, 0, 0, 0 },
78975
    { { MNEM, ' ', OP (DSP_16_U16), 0 } },
78976
    & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0xa6df0000 }
78977
  },
78978
/* abs.b ${Dsp-16-u24} */
78979
  {
78980
    { 0, 0, 0, 0 },
78981
    { { MNEM, ' ', OP (DSP_16_U24), 0 } },
78982
    & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0xa69f0000 }
78983
  },
78984
/* abs.w $Dst16RnHI */
78985
  {
78986
    { 0, 0, 0, 0 },
78987
    { { MNEM, ' ', OP (DST16RNHI), 0 } },
78988
    & ifmt_rorc16_w_16_dst16_Rn_direct_HI, { 0x77f0 }
78989
  },
78990
/* abs.w $Dst16AnHI */
78991
  {
78992
    { 0, 0, 0, 0 },
78993
    { { MNEM, ' ', OP (DST16ANHI), 0 } },
78994
    & ifmt_rorc16_w_16_dst16_An_direct_HI, { 0x77f4 }
78995
  },
78996
/* abs.w [$Dst16An] */
78997
  {
78998
    { 0, 0, 0, 0 },
78999
    { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } },
79000
    & ifmt_rorc16_w_16_dst16_An_indirect_HI, { 0x77f6 }
79001
  },
79002
/* abs.w ${Dsp-16-u8}[$Dst16An] */
79003
  {
79004
    { 0, 0, 0, 0 },
79005
    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
79006
    & ifmt_rorc16_w_16_dst16_16_8_An_relative_HI, { 0x77f800 }
79007
  },
79008
/* abs.w ${Dsp-16-u16}[$Dst16An] */
79009
  {
79010
    { 0, 0, 0, 0 },
79011
    { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
79012
    & ifmt_rorc16_w_16_dst16_16_16_An_relative_HI, { 0x77fc0000 }
79013
  },
79014
/* abs.w ${Dsp-16-u8}[sb] */
79015
  {
79016
    { 0, 0, 0, 0 },
79017
    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
79018
    & ifmt_rorc16_w_16_dst16_16_8_SB_relative_HI, { 0x77fa00 }
79019
  },
79020
/* abs.w ${Dsp-16-u16}[sb] */
79021
  {
79022
    { 0, 0, 0, 0 },
79023
    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
79024
    & ifmt_rorc16_w_16_dst16_16_16_SB_relative_HI, { 0x77fe0000 }
79025
  },
79026
/* abs.w ${Dsp-16-s8}[fb] */
79027
  {
79028
    { 0, 0, 0, 0 },
79029
    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
79030
    & ifmt_rorc16_w_16_dst16_16_8_FB_relative_HI, { 0x77fb00 }
79031
  },
79032
/* abs.w ${Dsp-16-u16} */
79033
  {
79034
    { 0, 0, 0, 0 },
79035
    { { MNEM, ' ', OP (DSP_16_U16), 0 } },
79036
    & ifmt_rorc16_w_16_dst16_16_16_absolute_HI, { 0x77ff0000 }
79037
  },
79038
/* abs.b $Dst16RnQI */
79039
  {
79040
    { 0, 0, 0, 0 },
79041
    { { MNEM, ' ', OP (DST16RNQI), 0 } },
79042
    & ifmt_rorc16_b_16_dst16_Rn_direct_QI, { 0x76f0 }
79043
  },
79044
/* abs.b $Dst16AnQI */
79045
  {
79046
    { 0, 0, 0, 0 },
79047
    { { MNEM, ' ', OP (DST16ANQI), 0 } },
79048
    & ifmt_rorc16_b_16_dst16_An_direct_QI, { 0x76f4 }
79049
  },
79050
/* abs.b [$Dst16An] */
79051
  {
79052
    { 0, 0, 0, 0 },
79053
    { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } },
79054
    & ifmt_rorc16_b_16_dst16_An_indirect_QI, { 0x76f6 }
79055
  },
79056
/* abs.b ${Dsp-16-u8}[$Dst16An] */
79057
  {
79058
    { 0, 0, 0, 0 },
79059
    { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } },
79060
    & ifmt_rorc16_b_16_dst16_16_8_An_relative_QI, { 0x76f800 }
79061
  },
79062
/* abs.b ${Dsp-16-u16}[$Dst16An] */
79063
  {
79064
    { 0, 0, 0, 0 },
79065
    { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } },
79066
    & ifmt_rorc16_b_16_dst16_16_16_An_relative_QI, { 0x76fc0000 }
79067
  },
79068
/* abs.b ${Dsp-16-u8}[sb] */
79069
  {
79070
    { 0, 0, 0, 0 },
79071
    { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
79072
    & ifmt_rorc16_b_16_dst16_16_8_SB_relative_QI, { 0x76fa00 }
79073
  },
79074
/* abs.b ${Dsp-16-u16}[sb] */
79075
  {
79076
    { 0, 0, 0, 0 },
79077
    { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } },
79078
    & ifmt_rorc16_b_16_dst16_16_16_SB_relative_QI, { 0x76fe0000 }
79079
  },
79080
/* abs.b ${Dsp-16-s8}[fb] */
79081
  {
79082
    { 0, 0, 0, 0 },
79083
    { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
79084
    & ifmt_rorc16_b_16_dst16_16_8_FB_relative_QI, { 0x76fb00 }
79085
  },
79086
/* abs.b ${Dsp-16-u16} */
79087
  {
79088
    { 0, 0, 0, 0 },
79089
    { { MNEM, ' ', OP (DSP_16_U16), 0 } },
79090
    & ifmt_rorc16_b_16_dst16_16_16_absolute_QI, { 0x76ff0000 }
79091
  },
79092
/* add.w$Q #${Imm-12-s4},sp */
79093
  {
79094
    { 0, 0, 0, 0 },
79095
    { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', 's', 'p', 0 } },
79096
    & ifmt_add16_wQ_sp, { 0x7db0 }
79097
  },
79098
/* add.b$G #${Imm-16-QI},sp */
79099
  {
79100
    { 0, 0, 0, 0 },
79101
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', 's', 'p', 0 } },
79102
    & ifmt_add16_b_G_sp, { 0x7ceb00 }
79103
  },
79104
/* add.w$G #${Imm-16-HI},sp */
79105
  {
79106
    { 0, 0, 0, 0 },
79107
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', 's', 'p', 0 } },
79108
    & ifmt_add16_w_G_sp, { 0x7deb0000 }
79109
  },
79110
/* add.l$Q #${Imm3-S},sp */
79111
  {
79112
    { 0, 0, 0, 0 },
79113
    { { MNEM, OP (Q), ' ', '#', OP (IMM3_S), ',', 's', 'p', 0 } },
79114
    & ifmt_add32_l_imm3_Q, { 0x42 }
79115
  },
79116
/* add.l$S #${Imm-16-QI},sp */
79117
  {
79118
    { 0, 0, 0, 0 },
79119
    { { MNEM, OP (S), ' ', '#', OP (IMM_16_QI), ',', 's', 'p', 0 } },
79120
    & ifmt_add32_l_imm8_S, { 0xb60300 }
79121
  },
79122
/* add.l$G #${Imm-16-HI},sp */
79123
  {
79124
    { 0, 0, 0, 0 },
79125
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', 's', 'p', 0 } },
79126
    & ifmt_add32_l_imm16_G, { 0xb6130000 }
79127
  },
79128
/* dadc.b #${Imm-16-QI},r0l */
79129
  {
79130
    { 0, 0, 0, 0 },
79131
    { { MNEM, ' ', '#', OP (IMM_16_QI), ',', 'r', '0', 'l', 0 } },
79132
    & ifmt_add32_l_imm8_S, { 0x7cee00 }
79133
  },
79134
/* dadc.w #${Imm-16-HI},r0 */
79135
  {
79136
    { 0, 0, 0, 0 },
79137
    { { MNEM, ' ', '#', OP (IMM_16_HI), ',', 'r', '0', 0 } },
79138
    & ifmt_add32_l_imm16_G, { 0x7dee0000 }
79139
  },
79140
/* dadc.b r0h,r0l */
79141
  {
79142
    { 0, 0, 0, 0 },
79143
    { { MNEM, ' ', 'r', '0', 'h', ',', 'r', '0', 'l', 0 } },
79144
    & ifmt_dadc16_b_r0h_r0l, { 0x7ce6 }
79145
  },
79146
/* dadc.w r1,r0 */
79147
  {
79148
    { 0, 0, 0, 0 },
79149
    { { MNEM, ' ', 'r', '1', ',', 'r', '0', 0 } },
79150
    & ifmt_dadc16_b_r0h_r0l, { 0x7de6 }
79151
  },
79152
/* dadd.b #${Imm-16-QI},r0l */
79153
  {
79154
    { 0, 0, 0, 0 },
79155
    { { MNEM, ' ', '#', OP (IMM_16_QI), ',', 'r', '0', 'l', 0 } },
79156
    & ifmt_add32_l_imm8_S, { 0x7cec00 }
79157
  },
79158
/* dadd.w #${Imm-16-HI},r0 */
79159
  {
79160
    { 0, 0, 0, 0 },
79161
    { { MNEM, ' ', '#', OP (IMM_16_HI), ',', 'r', '0', 0 } },
79162
    & ifmt_add32_l_imm16_G, { 0x7dec0000 }
79163
  },
79164
/* dadd.b r0h,r0l */
79165
  {
79166
    { 0, 0, 0, 0 },
79167
    { { MNEM, ' ', 'r', '0', 'h', ',', 'r', '0', 'l', 0 } },
79168
    & ifmt_dadc16_b_r0h_r0l, { 0x7ce4 }
79169
  },
79170
/* dadd.w r1,r0 */
79171
  {
79172
    { 0, 0, 0, 0 },
79173
    { { MNEM, ' ', 'r', '1', ',', 'r', '0', 0 } },
79174
    & ifmt_dadc16_b_r0h_r0l, { 0x7de4 }
79175
  },
79176
/* bm$cond16c c */
79177
  {
79178
    { 0, 0, 0, 0 },
79179
    { { MNEM, OP (COND16C), ' ', 'c', 0 } },
79180
    & ifmt_bm16_c, { 0x7dd0 }
79181
  },
79182
/* bm$cond32 c */
79183
  {
79184
    { 0, 0, 0, 0 },
79185
    { { MNEM, OP (COND32), ' ', 'c', 0 } },
79186
    & ifmt_bm32_c, { 0xd928 }
79187
  },
79188
/* brk */
79189
  {
79190
    { 0, 0, 0, 0 },
79191
    { { MNEM, 0 } },
79192
    & ifmt_brk16, { 0x0 }
79193
  },
79194
/* brk */
79195
  {
79196
    { 0, 0, 0, 0 },
79197
    { { MNEM, 0 } },
79198
    & ifmt_brk16, { 0x0 }
79199
  },
79200
/* brk2 */
79201
  {
79202
    { 0, 0, 0, 0 },
79203
    { { MNEM, 0 } },
79204
    & ifmt_brk16, { 0x8 }
79205
  },
79206
/* btst:s ${Bit3-S},${Dsp-8-u16} */
79207
  {
79208
    { 0, 0, 0, 0 },
79209
    { { MNEM, ' ', OP (BIT3_S), ',', OP (DSP_8_U16), 0 } },
79210
    & ifmt_btst_s, { 0xa0000 }
79211
  },
79212
/* dec.w ${Dst16An-S} */
79213
  {
79214
    { 0, 0, 0, 0 },
79215
    { { MNEM, ' ', OP (DST16AN_S), 0 } },
79216
    & ifmt_dec16_w, { 0xf2 }
79217
  },
79218
/* div.b #${Imm-16-QI} */
79219
  {
79220
    { 0, 0, 0, 0 },
79221
    { { MNEM, ' ', '#', OP (IMM_16_QI), 0 } },
79222
    & ifmt_add16_b_G_sp, { 0x7ce100 }
79223
  },
79224
/* div.w #${Imm-16-HI} */
79225
  {
79226
    { 0, 0, 0, 0 },
79227
    { { MNEM, ' ', '#', OP (IMM_16_HI), 0 } },
79228
    & ifmt_add16_w_G_sp, { 0x7de10000 }
79229
  },
79230
/* div.b #${Imm-16-QI} */
79231
  {
79232
    { 0, 0, 0, 0 },
79233
    { { MNEM, ' ', '#', OP (IMM_16_QI), 0 } },
79234
    & ifmt_div32_b_Imm_16_QI, { 0xb04300 }
79235
  },
79236
/* div.w #${Imm-16-HI} */
79237
  {
79238
    { 0, 0, 0, 0 },
79239
    { { MNEM, ' ', '#', OP (IMM_16_HI), 0 } },
79240
    & ifmt_div32_w_Imm_16_HI, { 0xb0530000 }
79241
  },
79242
/* divu.b #${Imm-16-QI} */
79243
  {
79244
    { 0, 0, 0, 0 },
79245
    { { MNEM, ' ', '#', OP (IMM_16_QI), 0 } },
79246
    & ifmt_add16_b_G_sp, { 0x7ce000 }
79247
  },
79248
/* divu.w #${Imm-16-HI} */
79249
  {
79250
    { 0, 0, 0, 0 },
79251
    { { MNEM, ' ', '#', OP (IMM_16_HI), 0 } },
79252
    & ifmt_add16_w_G_sp, { 0x7de00000 }
79253
  },
79254
/* divu.b #${Imm-16-QI} */
79255
  {
79256
    { 0, 0, 0, 0 },
79257
    { { MNEM, ' ', '#', OP (IMM_16_QI), 0 } },
79258
    & ifmt_div32_b_Imm_16_QI, { 0xb00300 }
79259
  },
79260
/* divu.w #${Imm-16-HI} */
79261
  {
79262
    { 0, 0, 0, 0 },
79263
    { { MNEM, ' ', '#', OP (IMM_16_HI), 0 } },
79264
    & ifmt_div32_w_Imm_16_HI, { 0xb0130000 }
79265
  },
79266
/* divx.b #${Imm-16-QI} */
79267
  {
79268
    { 0, 0, 0, 0 },
79269
    { { MNEM, ' ', '#', OP (IMM_16_QI), 0 } },
79270
    & ifmt_add16_b_G_sp, { 0x7ce300 }
79271
  },
79272
/* divx.w #${Imm-16-HI} */
79273
  {
79274
    { 0, 0, 0, 0 },
79275
    { { MNEM, ' ', '#', OP (IMM_16_HI), 0 } },
79276
    & ifmt_add16_w_G_sp, { 0x7de30000 }
79277
  },
79278
/* divx.b #${Imm-16-QI} */
79279
  {
79280
    { 0, 0, 0, 0 },
79281
    { { MNEM, ' ', '#', OP (IMM_16_QI), 0 } },
79282
    & ifmt_div32_b_Imm_16_QI, { 0xb24300 }
79283
  },
79284
/* divx.w #${Imm-16-HI} */
79285
  {
79286
    { 0, 0, 0, 0 },
79287
    { { MNEM, ' ', '#', OP (IMM_16_HI), 0 } },
79288
    & ifmt_div32_w_Imm_16_HI, { 0xb2530000 }
79289
  },
79290
/* dsbb.b #${Imm-16-QI},r0l */
79291
  {
79292
    { 0, 0, 0, 0 },
79293
    { { MNEM, ' ', '#', OP (IMM_16_QI), ',', 'r', '0', 'l', 0 } },
79294
    & ifmt_add32_l_imm8_S, { 0x7cef00 }
79295
  },
79296
/* dsbb.w #${Imm-16-HI},r0 */
79297
  {
79298
    { 0, 0, 0, 0 },
79299
    { { MNEM, ' ', '#', OP (IMM_16_HI), ',', 'r', '0', 0 } },
79300
    & ifmt_add32_l_imm16_G, { 0x7def0000 }
79301
  },
79302
/* dsbb.b r0h,r0l */
79303
  {
79304
    { 0, 0, 0, 0 },
79305
    { { MNEM, ' ', 'r', '0', 'h', ',', 'r', '0', 'l', 0 } },
79306
    & ifmt_dadc16_b_r0h_r0l, { 0x7ce7 }
79307
  },
79308
/* dsbb.w r1,r0 */
79309
  {
79310
    { 0, 0, 0, 0 },
79311
    { { MNEM, ' ', 'r', '1', ',', 'r', '0', 0 } },
79312
    & ifmt_dadc16_b_r0h_r0l, { 0x7de7 }
79313
  },
79314
/* dsub.b #${Imm-16-QI},r0l */
79315
  {
79316
    { 0, 0, 0, 0 },
79317
    { { MNEM, ' ', '#', OP (IMM_16_QI), ',', 'r', '0', 'l', 0 } },
79318
    & ifmt_add32_l_imm8_S, { 0x7ced00 }
79319
  },
79320
/* dsub.w #${Imm-16-HI},r0 */
79321
  {
79322
    { 0, 0, 0, 0 },
79323
    { { MNEM, ' ', '#', OP (IMM_16_HI), ',', 'r', '0', 0 } },
79324
    & ifmt_add32_l_imm16_G, { 0x7ded0000 }
79325
  },
79326
/* dsub.b r0h,r0l */
79327
  {
79328
    { 0, 0, 0, 0 },
79329
    { { MNEM, ' ', 'r', '0', 'h', ',', 'r', '0', 'l', 0 } },
79330
    & ifmt_dadc16_b_r0h_r0l, { 0x7ce5 }
79331
  },
79332
/* dsub.w r1,r0 */
79333
  {
79334
    { 0, 0, 0, 0 },
79335
    { { MNEM, ' ', 'r', '1', ',', 'r', '0', 0 } },
79336
    & ifmt_dadc16_b_r0h_r0l, { 0x7de5 }
79337
  },
79338
/* enter #${Dsp-16-u8} */
79339
  {
79340
    { 0, 0, 0, 0 },
79341
    { { MNEM, ' ', '#', OP (DSP_16_U8), 0 } },
79342
    & ifmt_enter16, { 0x7cf200 }
79343
  },
79344
/* exitd */
79345
  {
79346
    { 0, 0, 0, 0 },
79347
    { { MNEM, 0 } },
79348
    & ifmt_dadc16_b_r0h_r0l, { 0x7df2 }
79349
  },
79350
/* enter #${Dsp-8-u8} */
79351
  {
79352
    { 0, 0, 0, 0 },
79353
    { { MNEM, ' ', '#', OP (DSP_8_U8), 0 } },
79354
    & ifmt_enter32, { 0xec00 }
79355
  },
79356
/* exitd */
79357
  {
79358
    { 0, 0, 0, 0 },
79359
    { { MNEM, 0 } },
79360
    & ifmt_brk16, { 0xfc }
79361
  },
79362
/* fclr ${flags16} */
79363
  {
79364
    { 0, 0, 0, 0 },
79365
    { { MNEM, ' ', OP (FLAGS16), 0 } },
79366
    & ifmt_fclr16, { 0xeb05 }
79367
  },
79368
/* fset ${flags16} */
79369
  {
79370
    { 0, 0, 0, 0 },
79371
    { { MNEM, ' ', OP (FLAGS16), 0 } },
79372
    & ifmt_fclr16, { 0xeb04 }
79373
  },
79374
/* fclr ${flags32} */
79375
  {
79376
    { 0, 0, 0, 0 },
79377
    { { MNEM, ' ', OP (FLAGS32), 0 } },
79378
    & ifmt_fclr, { 0xd3e8 }
79379
  },
79380
/* fset ${flags32} */
79381
  {
79382
    { 0, 0, 0, 0 },
79383
    { { MNEM, ' ', OP (FLAGS32), 0 } },
79384
    & ifmt_fclr, { 0xd1e8 }
79385
  },
79386
/* inc.w ${Dst16An-S} */
79387
  {
79388
    { 0, 0, 0, 0 },
79389
    { { MNEM, ' ', OP (DST16AN_S), 0 } },
79390
    & ifmt_dec16_w, { 0xb2 }
79391
  },
79392
/* freit */
79393
  {
79394
    { 0, 0, 0, 0 },
79395
    { { MNEM, 0 } },
79396
    & ifmt_brk16, { 0x9f }
79397
  },
79398
/* int #${Dsp-10-u6} */
79399
  {
79400
    { 0, 0, 0, 0 },
79401
    { { MNEM, ' ', '#', OP (DSP_10_U6), 0 } },
79402
    & ifmt_int16, { 0xebc0 }
79403
  },
79404
/* into */
79405
  {
79406
    { 0, 0, 0, 0 },
79407
    { { MNEM, 0 } },
79408
    & ifmt_brk16, { 0xf6 }
79409
  },
79410
/* int #${Dsp-8-u6} */
79411
  {
79412
    { 0, 0, 0, 0 },
79413
    { { MNEM, ' ', '#', OP (DSP_8_U6), 0 } },
79414
    & ifmt_int32, { 0xbe00 }
79415
  },
79416
/* into */
79417
  {
79418
    { 0, 0, 0, 0 },
79419
    { { MNEM, 0 } },
79420
    & ifmt_brk16, { 0xbf }
79421
  },
79422
/* j$cond16j5 ${Lab-8-8} */
79423
  {
79424
    { 0, 0, 0, 0 },
79425
    { { MNEM, OP (COND16J5), ' ', OP (LAB_8_8), 0 } },
79426
    & ifmt_jcnd16_5, { 0x6800 }
79427
  },
79428
/* j$cond16j ${Lab-16-8} */
79429
  {
79430
    { 0, 0, 0, 0 },
79431
    { { MNEM, OP (COND16J), ' ', OP (LAB_16_8), 0 } },
79432
    & ifmt_jcnd16, { 0x7dc000 }
79433
  },
79434
/* j$cond32j ${Lab-8-8} */
79435
  {
79436
    { 0, 0, 0, 0 },
79437
    { { MNEM, OP (COND32J), ' ', OP (LAB_8_8), 0 } },
79438
    & ifmt_jcnd32, { 0x8a00 }
79439
  },
79440
/* jmp.s ${Lab-5-3} */
79441
  {
79442
    { 0, 0, 0, 0 },
79443
    { { MNEM, ' ', OP (LAB_5_3), 0 } },
79444
    & ifmt_jmp16_s, { 0x60 }
79445
  },
79446
/* jmp.b ${Lab-8-8} */
79447
  {
79448
    { 0, 0, 0, 0 },
79449
    { { MNEM, ' ', OP (LAB_8_8), 0 } },
79450
    & ifmt_jmp16_b, { 0xfe00 }
79451
  },
79452
/* jmp.w ${Lab-8-16} */
79453
  {
79454
    { 0, 0, 0, 0 },
79455
    { { MNEM, ' ', OP (LAB_8_16), 0 } },
79456
    & ifmt_jmp16_w, { 0xf40000 }
79457
  },
79458
/* jmp.a ${Lab-8-24} */
79459
  {
79460
    { 0, 0, 0, 0 },
79461
    { { MNEM, ' ', OP (LAB_8_24), 0 } },
79462
    & ifmt_jmp16_a, { 0xfc000000 }
79463
  },
79464
/* jmps #${Imm-8-QI} */
79465
  {
79466
    { 0, 0, 0, 0 },
79467
    { { MNEM, ' ', '#', OP (IMM_8_QI), 0 } },
79468
    & ifmt_jmps16, { 0xee00 }
79469
  },
79470
/* jmp.s ${Lab32-jmp-s} */
79471
  {
79472
    { 0, 0, 0, 0 },
79473
    { { MNEM, ' ', OP (LAB32_JMP_S), 0 } },
79474
    & ifmt_jmp32_s, { 0x4a }
79475
  },
79476
/* jmp.b ${Lab-8-8} */
79477
  {
79478
    { 0, 0, 0, 0 },
79479
    { { MNEM, ' ', OP (LAB_8_8), 0 } },
79480
    & ifmt_jmp16_b, { 0xbb00 }
79481
  },
79482
/* jmp.w ${Lab-8-16} */
79483
  {
79484
    { 0, 0, 0, 0 },
79485
    { { MNEM, ' ', OP (LAB_8_16), 0 } },
79486
    & ifmt_jmp16_w, { 0xce0000 }
79487
  },
79488
/* jmp.a ${Lab-8-24} */
79489
  {
79490
    { 0, 0, 0, 0 },
79491
    { { MNEM, ' ', OP (LAB_8_24), 0 } },
79492
    & ifmt_jmp16_a, { 0xcc000000 }
79493
  },
79494
/* jmps #${Imm-8-QI} */
79495
  {
79496
    { 0, 0, 0, 0 },
79497
    { { MNEM, ' ', '#', OP (IMM_8_QI), 0 } },
79498
    & ifmt_jmps16, { 0xdc00 }
79499
  },
79500
/* jsr.w ${Lab-8-16} */
79501
  {
79502
    { 0, 0, 0, 0 },
79503
    { { MNEM, ' ', OP (LAB_8_16), 0 } },
79504
    & ifmt_jmp16_w, { 0xf50000 }
79505
  },
79506
/* jsr.a ${Lab-8-24} */
79507
  {
79508
    { 0, 0, 0, 0 },
79509
    { { MNEM, ' ', OP (LAB_8_24), 0 } },
79510
    & ifmt_jmp16_a, { 0xfd000000 }
79511
  },
79512
/* jsr.w ${Lab-8-16} */
79513
  {
79514
    { 0, 0, 0, 0 },
79515
    { { MNEM, ' ', OP (LAB_8_16), 0 } },
79516
    & ifmt_jmp16_w, { 0xcf0000 }
79517
  },
79518
/* jsr.a ${Lab-8-24} */
79519
  {
79520
    { 0, 0, 0, 0 },
79521
    { { MNEM, ' ', OP (LAB_8_24), 0 } },
79522
    & ifmt_jmp16_a, { 0xcd000000 }
79523
  },
79524
/* jsrs #${Imm-8-QI} */
79525
  {
79526
    { 0, 0, 0, 0 },
79527
    { { MNEM, ' ', '#', OP (IMM_8_QI), 0 } },
79528
    & ifmt_jmps16, { 0xef00 }
79529
  },
79530
/* jsrs #${Imm-8-QI} */
79531
  {
79532
    { 0, 0, 0, 0 },
79533
    { { MNEM, ' ', '#', OP (IMM_8_QI), 0 } },
79534
    & ifmt_jmps16, { 0xdd00 }
79535
  },
79536
/* ldc #${Imm-16-HI},${cr16} */
79537
  {
79538
    { 0, 0, 0, 0 },
79539
    { { MNEM, ' ', '#', OP (IMM_16_HI), ',', OP (CR16), 0 } },
79540
    & ifmt_ldc16_imm16, { 0xeb000000 }
79541
  },
79542
/* ldc #${Imm-16-HI},${cr1-Unprefixed-32} */
79543
  {
79544
    { 0, 0, 0, 0 },
79545
    { { MNEM, ' ', '#', OP (IMM_16_HI), ',', OP (CR1_UNPREFIXED_32), 0 } },
79546
    & ifmt_ldc32_imm16_cr1, { 0xd5a80000 }
79547
  },
79548
/* ldc #${Dsp-16-u24},${cr2-32} */
79549
  {
79550
    { 0, 0, 0, 0 },
79551
    { { MNEM, ' ', '#', OP (DSP_16_U24), ',', OP (CR2_32), 0 } },
79552
    & ifmt_ldc32_imm16_cr2, { 0xd5280000 }
79553
  },
79554
/* ldc #${Dsp-16-u24},${cr3-Unprefixed-32} */
79555
  {
79556
    { 0, 0, 0, 0 },
79557
    { { MNEM, ' ', '#', OP (DSP_16_U24), ',', OP (CR3_UNPREFIXED_32), 0 } },
79558
    & ifmt_ldc32_imm16_cr3, { 0xd5680000 }
79559
  },
79560
/* ldctx ${Dsp-16-u16},${Dsp-32-u24} */
79561
  {
79562
    { 0, 0, 0, 0 },
79563
    { { MNEM, ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } },
79564
    & ifmt_ldctx16, { 0x7cf00000 }
79565
  },
79566
/* ldctx ${Dsp-16-u16},${Dsp-32-u24} */
79567
  {
79568
    { 0, 0, 0, 0 },
79569
    { { MNEM, ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } },
79570
    & ifmt_ldctx16, { 0xb6c30000 }
79571
  },
79572
/* stctx ${Dsp-16-u16},${Dsp-32-u24} */
79573
  {
79574
    { 0, 0, 0, 0 },
79575
    { { MNEM, ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } },
79576
    & ifmt_ldctx16, { 0x7df00000 }
79577
  },
79578
/* stctx ${Dsp-16-u16},${Dsp-32-u24} */
79579
  {
79580
    { 0, 0, 0, 0 },
79581
    { { MNEM, ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } },
79582
    & ifmt_ldctx16, { 0xb6d30000 }
79583
  },
79584
/* ldipl #${Imm-13-u3} */
79585
  {
79586
    { 0, 0, 0, 0 },
79587
    { { MNEM, ' ', '#', OP (IMM_13_U3), 0 } },
79588
    & ifmt_ldipl16_imm, { 0x7da0 }
79589
  },
79590
/* ldipl #${Imm-13-u3} */
79591
  {
79592
    { 0, 0, 0, 0 },
79593
    { { MNEM, ' ', '#', OP (IMM_13_U3), 0 } },
79594
    & ifmt_ldipl16_imm, { 0xd5e8 }
79595
  },
79596
/* mov.b$S #${Imm-8-QI},a0 */
79597
  {
79598
    { 0, 0, 0, 0 },
79599
    { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'a', '0', 0 } },
79600
    & ifmt_jmps16, { 0xe200 }
79601
  },
79602
/* mov.b$S #${Imm-8-QI},a1 */
79603
  {
79604
    { 0, 0, 0, 0 },
79605
    { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'a', '1', 0 } },
79606
    & ifmt_jmps16, { 0xea00 }
79607
  },
79608
/* mov.w$S #${Imm-8-HI},a0 */
79609
  {
79610
    { 0, 0, 0, 0 },
79611
    { { MNEM, OP (S), ' ', '#', OP (IMM_8_HI), ',', 'a', '0', 0 } },
79612
    & ifmt_mov16_w_S_imm_a0, { 0xa20000 }
79613
  },
79614
/* mov.w$S #${Imm-8-HI},a1 */
79615
  {
79616
    { 0, 0, 0, 0 },
79617
    { { MNEM, OP (S), ' ', '#', OP (IMM_8_HI), ',', 'a', '1', 0 } },
79618
    & ifmt_mov16_w_S_imm_a0, { 0xaa0000 }
79619
  },
79620
/* mov.w$S #${Imm-8-HI},a0 */
79621
  {
79622
    { 0, 0, 0, 0 },
79623
    { { MNEM, OP (S), ' ', '#', OP (IMM_8_HI), ',', 'a', '0', 0 } },
79624
    & ifmt_mov16_w_S_imm_a0, { 0x9c0000 }
79625
  },
79626
/* mov.w$S #${Imm-8-HI},a1 */
79627
  {
79628
    { 0, 0, 0, 0 },
79629
    { { MNEM, OP (S), ' ', '#', OP (IMM_8_HI), ',', 'a', '1', 0 } },
79630
    & ifmt_mov16_w_S_imm_a0, { 0x9d0000 }
79631
  },
79632
/* mov.l$S #${Dsp-8-s24},a0 */
79633
  {
79634
    { 0, 0, 0, 0 },
79635
    { { MNEM, OP (S), ' ', '#', OP (DSP_8_S24), ',', 'a', '0', 0 } },
79636
    & ifmt_mov32_l_a0, { 0xbc000000 }
79637
  },
79638
/* mov.l$S #${Dsp-8-s24},a1 */
79639
  {
79640
    { 0, 0, 0, 0 },
79641
    { { MNEM, OP (S), ' ', '#', OP (DSP_8_S24), ',', 'a', '1', 0 } },
79642
    & ifmt_mov32_l_a0, { 0xbd000000 }
79643
  },
79644
/* mov.b$S r0l,a1 */
79645
  {
79646
    { 0, 0, 0, 0 },
79647
    { { MNEM, OP (S), ' ', 'r', '0', 'l', ',', 'a', '1', 0 } },
79648
    & ifmt_brk16, { 0x34 }
79649
  },
79650
/* mov.b$S r0h,a0 */
79651
  {
79652
    { 0, 0, 0, 0 },
79653
    { { MNEM, OP (S), ' ', 'r', '0', 'h', ',', 'a', '0', 0 } },
79654
    & ifmt_brk16, { 0x30 }
79655
  },
79656
/* nop */
79657
  {
79658
    { 0, 0, 0, 0 },
79659
    { { MNEM, 0 } },
79660
    & ifmt_brk16, { 0x4 }
79661
  },
79662
/* nop */
79663
  {
79664
    { 0, 0, 0, 0 },
79665
    { { MNEM, 0 } },
79666
    & ifmt_brk16, { 0xde }
79667
  },
79668
/* popc ${cr16} */
79669
  {
79670
    { 0, 0, 0, 0 },
79671
    { { MNEM, ' ', OP (CR16), 0 } },
79672
    & ifmt_popc16_imm16, { 0xeb03 }
79673
  },
79674
/* popc ${cr1-Unprefixed-32} */
79675
  {
79676
    { 0, 0, 0, 0 },
79677
    { { MNEM, ' ', OP (CR1_UNPREFIXED_32), 0 } },
79678
    & ifmt_popc32_imm16_cr1, { 0xd3a8 }
79679
  },
79680
/* popc ${cr2-32} */
79681
  {
79682
    { 0, 0, 0, 0 },
79683
    { { MNEM, ' ', OP (CR2_32), 0 } },
79684
    & ifmt_popc32_imm16_cr2, { 0xd328 }
79685
  },
79686
/* pushc ${cr16} */
79687
  {
79688
    { 0, 0, 0, 0 },
79689
    { { MNEM, ' ', OP (CR16), 0 } },
79690
    & ifmt_popc16_imm16, { 0xeb02 }
79691
  },
79692
/* pushc ${cr1-Unprefixed-32} */
79693
  {
79694
    { 0, 0, 0, 0 },
79695
    { { MNEM, ' ', OP (CR1_UNPREFIXED_32), 0 } },
79696
    & ifmt_popc32_imm16_cr1, { 0xd1a8 }
79697
  },
79698
/* pushc ${cr2-32} */
79699
  {
79700
    { 0, 0, 0, 0 },
79701
    { { MNEM, ' ', OP (CR2_32), 0 } },
79702
    & ifmt_popc32_imm16_cr2, { 0xd128 }
79703
  },
79704
/* popm ${Regsetpop} */
79705
  {
79706
    { 0, 0, 0, 0 },
79707
    { { MNEM, ' ', OP (REGSETPOP), 0 } },
79708
    & ifmt_popm16, { 0xed00 }
79709
  },
79710
/* pushm ${Regsetpush} */
79711
  {
79712
    { 0, 0, 0, 0 },
79713
    { { MNEM, ' ', OP (REGSETPUSH), 0 } },
79714
    & ifmt_pushm16, { 0xec00 }
79715
  },
79716
/* popm ${Regsetpop} */
79717
  {
79718
    { 0, 0, 0, 0 },
79719
    { { MNEM, ' ', OP (REGSETPOP), 0 } },
79720
    & ifmt_popm16, { 0x8e00 }
79721
  },
79722
/* pushm ${Regsetpush} */
79723
  {
79724
    { 0, 0, 0, 0 },
79725
    { { MNEM, ' ', OP (REGSETPUSH), 0 } },
79726
    & ifmt_pushm16, { 0x8f00 }
79727
  },
79728
/* push.b$G #${Imm-16-QI} */
79729
  {
79730
    { 0, 0, 0, 0 },
79731
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), 0 } },
79732
    & ifmt_add32_l_imm8_S, { 0x7ce200 }
79733
  },
79734
/* push.w$G #${Imm-16-HI} */
79735
  {
79736
    { 0, 0, 0, 0 },
79737
    { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), 0 } },
79738
    & ifmt_add32_l_imm16_G, { 0x7de20000 }
79739
  },
79740
/* push.b #${Imm-8-QI} */
79741
  {
79742
    { 0, 0, 0, 0 },
79743
    { { MNEM, ' ', '#', OP (IMM_8_QI), 0 } },
79744
    & ifmt_jmps16, { 0xae00 }
79745
  },
79746
/* push.w #${Imm-8-HI} */
79747
  {
79748
    { 0, 0, 0, 0 },
79749
    { { MNEM, ' ', '#', OP (IMM_8_HI), 0 } },
79750
    & ifmt_mov16_w_S_imm_a0, { 0xaf0000 }
79751
  },
79752
/* push.l #${Imm-16-SI} */
79753
  {
79754
    { 0, 0, 0, 0 },
79755
    { { MNEM, ' ', '#', OP (IMM_16_SI), 0 } },
79756
    & ifmt_push32_l_imm, { 0xb6530000 }
79757
  },
79758
/* reit */
79759
  {
79760
    { 0, 0, 0, 0 },
79761
    { { MNEM, 0 } },
79762
    & ifmt_brk16, { 0xfb }
79763
  },
79764
/* reit */
79765
  {
79766
    { 0, 0, 0, 0 },
79767
    { { MNEM, 0 } },
79768
    & ifmt_brk16, { 0x9e }
79769
  },
79770
/* rmpa.b */
79771
  {
79772
    { 0, 0, 0, 0 },
79773
    { { MNEM, 0 } },
79774
    & ifmt_dadc16_b_r0h_r0l, { 0x7cf1 }
79775
  },
79776
/* rmpa.w */
79777
  {
79778
    { 0, 0, 0, 0 },
79779
    { { MNEM, 0 } },
79780
    & ifmt_dadc16_b_r0h_r0l, { 0x7df1 }
79781
  },
79782
/* rmpa.b */
79783
  {
79784
    { 0, 0, 0, 0 },
79785
    { { MNEM, 0 } },
79786
    & ifmt_dadc16_b_r0h_r0l, { 0xb843 }
79787
  },
79788
/* rmpa.w */
79789
  {
79790
    { 0, 0, 0, 0 },
79791
    { { MNEM, 0 } },
79792
    & ifmt_dadc16_b_r0h_r0l, { 0xb853 }
79793
  },
79794
/* rts */
79795
  {
79796
    { 0, 0, 0, 0 },
79797
    { { MNEM, 0 } },
79798
    & ifmt_brk16, { 0xf3 }
79799
  },
79800
/* rts */
79801
  {
79802
    { 0, 0, 0, 0 },
79803
    { { MNEM, 0 } },
79804
    & ifmt_brk16, { 0xdf }
79805
  },
79806
/* scmpu.b */
79807
  {
79808
    { 0, 0, 0, 0 },
79809
    { { MNEM, 0 } },
79810
    & ifmt_dadc16_b_r0h_r0l, { 0xb8c3 }
79811
  },
79812
/* scmpu.w */
79813
  {
79814
    { 0, 0, 0, 0 },
79815
    { { MNEM, 0 } },
79816
    & ifmt_dadc16_b_r0h_r0l, { 0xb8d3 }
79817
  },
79818
/* sha.l #${Imm-sh-12-s4},r2r0 */
79819
  {
79820
    { 0, 0, 0, 0 },
79821
    { { MNEM, ' ', '#', OP (IMM_SH_12_S4), ',', 'r', '2', 'r', '0', 0 } },
79822
    & ifmt_sha16_L_imm_r2r0, { 0xeba0 }
79823
  },
79824
/* sha.l #${Imm-sh-12-s4},r3r1 */
79825
  {
79826
    { 0, 0, 0, 0 },
79827
    { { MNEM, ' ', '#', OP (IMM_SH_12_S4), ',', 'r', '3', 'r', '1', 0 } },
79828
    & ifmt_sha16_L_imm_r2r0, { 0xebb0 }
79829
  },
79830
/* sha.l r1h,r2r0 */
79831
  {
79832
    { 0, 0, 0, 0 },
79833
    { { MNEM, ' ', 'r', '1', 'h', ',', 'r', '2', 'r', '0', 0 } },
79834
    & ifmt_dadc16_b_r0h_r0l, { 0xeb21 }
79835
  },
79836
/* sha.l r1h,r3r1 */
79837
  {
79838
    { 0, 0, 0, 0 },
79839
    { { MNEM, ' ', 'r', '1', 'h', ',', 'r', '3', 'r', '1', 0 } },
79840
    & ifmt_dadc16_b_r0h_r0l, { 0xeb31 }
79841
  },
79842
/* shl.l #${Imm-sh-12-s4},r2r0 */
79843
  {
79844
    { 0, 0, 0, 0 },
79845
    { { MNEM, ' ', '#', OP (IMM_SH_12_S4), ',', 'r', '2', 'r', '0', 0 } },
79846
    & ifmt_sha16_L_imm_r2r0, { 0xeb80 }
79847
  },
79848
/* shl.l #${Imm-sh-12-s4},r3r1 */
79849
  {
79850
    { 0, 0, 0, 0 },
79851
    { { MNEM, ' ', '#', OP (IMM_SH_12_S4), ',', 'r', '3', 'r', '1', 0 } },
79852
    & ifmt_sha16_L_imm_r2r0, { 0xeb90 }
79853
  },
79854
/* shl.l r1h,r2r0 */
79855
  {
79856
    { 0, 0, 0, 0 },
79857
    { { MNEM, ' ', 'r', '1', 'h', ',', 'r', '2', 'r', '0', 0 } },
79858
    & ifmt_dadc16_b_r0h_r0l, { 0xeb01 }
79859
  },
79860
/* shl.l r1h,r3r1 */
79861
  {
79862
    { 0, 0, 0, 0 },
79863
    { { MNEM, ' ', 'r', '1', 'h', ',', 'r', '3', 'r', '1', 0 } },
79864
    & ifmt_dadc16_b_r0h_r0l, { 0xeb11 }
79865
  },
79866
/* sin.b */
79867
  {
79868
    { 0, 0, 0, 0 },
79869
    { { MNEM, 0 } },
79870
    & ifmt_dadc16_b_r0h_r0l, { 0xb283 }
79871
  },
79872
/* sin.w */
79873
  {
79874
    { 0, 0, 0, 0 },
79875
    { { MNEM, 0 } },
79876
    & ifmt_dadc16_b_r0h_r0l, { 0xb293 }
79877
  },
79878
/* smovb.b */
79879
  {
79880
    { 0, 0, 0, 0 },
79881
    { { MNEM, 0 } },
79882
    & ifmt_dadc16_b_r0h_r0l, { 0x7ce9 }
79883
  },
79884
/* smovb.w */
79885
  {
79886
    { 0, 0, 0, 0 },
79887
    { { MNEM, 0 } },
79888
    & ifmt_dadc16_b_r0h_r0l, { 0x7de9 }
79889
  },
79890
/* smovb.b */
79891
  {
79892
    { 0, 0, 0, 0 },
79893
    { { MNEM, 0 } },
79894
    & ifmt_dadc16_b_r0h_r0l, { 0xb683 }
79895
  },
79896
/* smovb.w */
79897
  {
79898
    { 0, 0, 0, 0 },
79899
    { { MNEM, 0 } },
79900
    & ifmt_dadc16_b_r0h_r0l, { 0xb693 }
79901
  },
79902
/* smovf.b */
79903
  {
79904
    { 0, 0, 0, 0 },
79905
    { { MNEM, 0 } },
79906
    & ifmt_dadc16_b_r0h_r0l, { 0x7ce8 }
79907
  },
79908
/* smovf.w */
79909
  {
79910
    { 0, 0, 0, 0 },
79911
    { { MNEM, 0 } },
79912
    & ifmt_dadc16_b_r0h_r0l, { 0x7de8 }
79913
  },
79914
/* smovf.b */
79915
  {
79916
    { 0, 0, 0, 0 },
79917
    { { MNEM, 0 } },
79918
    & ifmt_dadc16_b_r0h_r0l, { 0xb083 }
79919
  },
79920
/* smovf.w */
79921
  {
79922
    { 0, 0, 0, 0 },
79923
    { { MNEM, 0 } },
79924
    & ifmt_dadc16_b_r0h_r0l, { 0xb093 }
79925
  },
79926
/* smovu.b */
79927
  {
79928
    { 0, 0, 0, 0 },
79929
    { { MNEM, 0 } },
79930
    & ifmt_dadc16_b_r0h_r0l, { 0xb883 }
79931
  },
79932
/* smovu.w */
79933
  {
79934
    { 0, 0, 0, 0 },
79935
    { { MNEM, 0 } },
79936
    & ifmt_dadc16_b_r0h_r0l, { 0xb893 }
79937
  },
79938
/* sout.b */
79939
  {
79940
    { 0, 0, 0, 0 },
79941
    { { MNEM, 0 } },
79942
    & ifmt_dadc16_b_r0h_r0l, { 0xb483 }
79943
  },
79944
/* sout.w */
79945
  {
79946
    { 0, 0, 0, 0 },
79947
    { { MNEM, 0 } },
79948
    & ifmt_dadc16_b_r0h_r0l, { 0xb493 }
79949
  },
79950
/* sstr.b */
79951
  {
79952
    { 0, 0, 0, 0 },
79953
    { { MNEM, 0 } },
79954
    & ifmt_dadc16_b_r0h_r0l, { 0x7cea }
79955
  },
79956
/* sstr.w */
79957
  {
79958
    { 0, 0, 0, 0 },
79959
    { { MNEM, 0 } },
79960
    & ifmt_dadc16_b_r0h_r0l, { 0x7dea }
79961
  },
79962
/* sstr.b */
79963
  {
79964
    { 0, 0, 0, 0 },
79965
    { { MNEM, 0 } },
79966
    & ifmt_dadc16_b_r0h_r0l, { 0xb803 }
79967
  },
79968
/* sstr.w */
79969
  {
79970
    { 0, 0, 0, 0 },
79971
    { { MNEM, 0 } },
79972
    & ifmt_dadc16_b_r0h_r0l, { 0xb813 }
79973
  },
79974
/* stzx #${Imm-8-QI},#${Imm-16-QI},r0h */
79975
  {
79976
    { 0, 0, 0, 0 },
79977
    { { MNEM, ' ', '#', OP (IMM_8_QI), ',', '#', OP (IMM_16_QI), ',', 'r', '0', 'h', 0 } },
79978
    & ifmt_stzx16_imm8_imm8_r0h, { 0xdb0000 }
79979
  },
79980
/* stzx #${Imm-8-QI},#${Imm-16-QI},r0l */
79981
  {
79982
    { 0, 0, 0, 0 },
79983
    { { MNEM, ' ', '#', OP (IMM_8_QI), ',', '#', OP (IMM_16_QI), ',', 'r', '0', 'l', 0 } },
79984
    & ifmt_stzx16_imm8_imm8_r0h, { 0xdc0000 }
79985
  },
79986
/* stzx #${Imm-8-QI},#${Imm-24-QI},${Dsp-16-u8}[sb] */
79987
  {
79988
    { 0, 0, 0, 0 },
79989
    { { MNEM, ' ', '#', OP (IMM_8_QI), ',', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
79990
    & ifmt_stzx16_imm8_imm8_dsp8sb, { 0xdd000000 }
79991
  },
79992
/* stzx #${Imm-8-QI},#${Imm-24-QI},${Dsp-16-s8}[fb] */
79993
  {
79994
    { 0, 0, 0, 0 },
79995
    { { MNEM, ' ', '#', OP (IMM_8_QI), ',', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
79996
    & ifmt_stzx16_imm8_imm8_dsp8fb, { 0xde000000 }
79997
  },
79998
/* stzx #${Imm-8-QI},#${Imm-32-QI},${Dsp-16-u16} */
79999
  {
80000
    { 0, 0, 0, 0 },
80001
    { { MNEM, ' ', '#', OP (IMM_8_QI), ',', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } },
80002
    & ifmt_stzx16_imm8_imm8_abs16, { 0xdf000000 }
80003
  },
80004
/* und */
80005
  {
80006
    { 0, 0, 0, 0 },
80007
    { { MNEM, 0 } },
80008
    & ifmt_brk16, { 0xff }
80009
  },
80010
/* und */
80011
  {
80012
    { 0, 0, 0, 0 },
80013
    { { MNEM, 0 } },
80014
    & ifmt_brk16, { 0xff }
80015
  },
80016
/* wait */
80017
  {
80018
    { 0, 0, 0, 0 },
80019
    { { MNEM, 0 } },
80020
    & ifmt_dadc16_b_r0h_r0l, { 0x7df3 }
80021
  },
80022
/* wait */
80023
  {
80024
    { 0, 0, 0, 0 },
80025
    { { MNEM, 0 } },
80026
    & ifmt_dadc16_b_r0h_r0l, { 0xb203 }
80027
  },
80028
/* exts.w r0 */
80029
  {
80030
    { 0, 0, 0, 0 },
80031
    { { MNEM, ' ', 'r', '0', 0 } },
80032
    & ifmt_dadc16_b_r0h_r0l, { 0x7cf3 }
80033
  },
80034
/* src-indirect */
80035
  {
80036
    { 0, 0, 0, 0 },
80037
    { { MNEM, 0 } },
80038
    & ifmt_brk16, { 0x41 }
80039
  },
80040
/* dest-indirect */
80041
  {
80042
    { 0, 0, 0, 0 },
80043
    { { MNEM, 0 } },
80044
    & ifmt_brk16, { 0x9 }
80045
  },
80046
/* src-dest-indirect */
80047
  {
80048
    { 0, 0, 0, 0 },
80049
    { { MNEM, 0 } },
80050
    & ifmt_brk16, { 0x49 }
80051
  },
80052
};
80053
80054
#undef A
80055
#undef OPERAND
80056
#undef MNEM
80057
#undef OP
80058
80059
/* Formats for ALIAS macro-insns.  */
80060
80061
#define F(f) & m32c_cgen_ifld_table[M32C_##f]
80062
static const CGEN_IFMT ifmt_add16_bQ_sp ATTRIBUTE_UNUSED = {
80063
  16, 16, 0xfff0, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_IMM_12_S4) }, { 0 } }
80064
};
80065
80066
#undef F
80067
80068
/* Each non-simple macro entry points to an array of expansion possibilities.  */
80069
80070
#define A(a) (1 << CGEN_INSN_##a)
80071
#define OPERAND(op) M32C_OPERAND_##op
80072
#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
80073
#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
80074
80075
/* The macro instruction table.  */
80076
80077
static const CGEN_IBASE m32c_cgen_macro_insn_table[] =
80078
{
80079
/* add.b:q #${Imm-12-s4},sp */
80080
  {
80081
    -1, "add16-bQ-sp", "add.b:q", 16,
80082
    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
80083
  },
80084
};
80085
80086
/* The macro instruction opcode table.  */
80087
80088
static const CGEN_OPCODE m32c_cgen_macro_insn_opcode_table[] =
80089
{
80090
/* add.b:q #${Imm-12-s4},sp */
80091
  {
80092
    { 0, 0, 0, 0 },
80093
    { { MNEM, ' ', '#', OP (IMM_12_S4), ',', 's', 'p', 0 } },
80094
    & ifmt_add16_bQ_sp, { 0x7db0 }
80095
  },
80096
};
80097
80098
#undef A
80099
#undef OPERAND
80100
#undef MNEM
80101
#undef OP
80102
80103
#ifndef CGEN_ASM_HASH_P
80104
0
#define CGEN_ASM_HASH_P(insn) 1
80105
#endif
80106
80107
#ifndef CGEN_DIS_HASH_P
80108
36.0k
#define CGEN_DIS_HASH_P(insn) 1
80109
#endif
80110
80111
/* Return non-zero if INSN is to be added to the hash table.
80112
   Targets are free to override CGEN_{ASM,DIS}_HASH_P in the .opc file.  */
80113
80114
static int
80115
asm_hash_insn_p (const CGEN_INSN *insn ATTRIBUTE_UNUSED)
80116
0
{
80117
0
  return CGEN_ASM_HASH_P (insn);
80118
0
}
80119
80120
static int
80121
dis_hash_insn_p (const CGEN_INSN *insn)
80122
36.0k
{
80123
  /* If building the hash table and the NO-DIS attribute is present,
80124
     ignore.  */
80125
36.0k
  if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_NO_DIS))
80126
0
    return 0;
80127
36.0k
  return CGEN_DIS_HASH_P (insn);
80128
36.0k
}
80129
80130
#ifndef CGEN_ASM_HASH
80131
#define CGEN_ASM_HASH_SIZE 127
80132
#ifdef CGEN_MNEMONIC_OPERANDS
80133
#define CGEN_ASM_HASH(mnem) (*(unsigned char *) (mnem) % CGEN_ASM_HASH_SIZE)
80134
#else
80135
#define CGEN_ASM_HASH(mnem) (*(unsigned char *) (mnem) % CGEN_ASM_HASH_SIZE) /*FIXME*/
80136
#endif
80137
#endif
80138
80139
/* It doesn't make much sense to provide a default here,
80140
   but while this is under development we do.
80141
   BUFFER is a pointer to the bytes of the insn, target order.
80142
   VALUE is the first base_insn_bitsize bits as an int in host order.  */
80143
80144
#ifndef CGEN_DIS_HASH
80145
#define CGEN_DIS_HASH_SIZE 256
80146
#define CGEN_DIS_HASH(buf, value) (*(unsigned char *) (buf))
80147
#endif
80148
80149
/* The result is the hash value of the insn.
80150
   Targets are free to override CGEN_{ASM,DIS}_HASH in the .opc file.  */
80151
80152
static unsigned int
80153
asm_hash_insn (const char *mnem)
80154
0
{
80155
0
  return CGEN_ASM_HASH (mnem);
80156
0
}
80157
80158
/* BUF is a pointer to the bytes of the insn, target order.
80159
   VALUE is the first base_insn_bitsize bits as an int in host order.  */
80160
80161
static unsigned int
80162
dis_hash_insn (const char *buf ATTRIBUTE_UNUSED,
80163
         CGEN_INSN_INT value ATTRIBUTE_UNUSED)
80164
382k
{
80165
382k
  return CGEN_DIS_HASH (buf, value);
80166
382k
}
80167
80168
/* Set the recorded length of the insn in the CGEN_FIELDS struct.  */
80169
80170
static void
80171
set_fields_bitsize (CGEN_FIELDS *fields, int size)
80172
0
{
80173
0
  CGEN_FIELDS_BITSIZE (fields) = size;
80174
0
}
80175
80176
/* Function to call before using the operand instance table.
80177
   This plugs the opcode entries and macro instructions into the cpu table.  */
80178
80179
void
80180
m32c_cgen_init_opcode_table (CGEN_CPU_DESC cd)
80181
3
{
80182
3
  int i;
80183
3
  int num_macros = (sizeof (m32c_cgen_macro_insn_table) /
80184
3
        sizeof (m32c_cgen_macro_insn_table[0]));
80185
3
  const CGEN_IBASE *ib = & m32c_cgen_macro_insn_table[0];
80186
3
  const CGEN_OPCODE *oc = & m32c_cgen_macro_insn_opcode_table[0];
80187
3
  CGEN_INSN *insns = xmalloc (num_macros * sizeof (CGEN_INSN));
80188
80189
  /* This test has been added to avoid a warning generated
80190
     if memset is called with a third argument of value zero.  */
80191
3
  if (num_macros >= 1)
80192
3
    memset (insns, 0, num_macros * sizeof (CGEN_INSN));
80193
6
  for (i = 0; i < num_macros; ++i)
80194
3
    {
80195
3
      insns[i].base = &ib[i];
80196
3
      insns[i].opcode = &oc[i];
80197
3
      m32c_cgen_build_insn_regex (& insns[i]);
80198
3
    }
80199
3
  cd->macro_insn_table.init_entries = insns;
80200
3
  cd->macro_insn_table.entry_size = sizeof (CGEN_IBASE);
80201
3
  cd->macro_insn_table.num_init_entries = num_macros;
80202
80203
3
  oc = & m32c_cgen_insn_opcode_table[0];
80204
3
  insns = (CGEN_INSN *) cd->insn_table.init_entries;
80205
36.0k
  for (i = 0; i < MAX_INSNS; ++i)
80206
36.0k
    {
80207
36.0k
      insns[i].opcode = &oc[i];
80208
36.0k
      m32c_cgen_build_insn_regex (& insns[i]);
80209
36.0k
    }
80210
80211
3
  cd->sizeof_fields = sizeof (CGEN_FIELDS);
80212
3
  cd->set_fields_bitsize = set_fields_bitsize;
80213
80214
3
  cd->asm_hash_p = asm_hash_insn_p;
80215
3
  cd->asm_hash = asm_hash_insn;
80216
3
  cd->asm_hash_size = CGEN_ASM_HASH_SIZE;
80217
80218
3
  cd->dis_hash_p = dis_hash_insn_p;
80219
3
  cd->dis_hash = dis_hash_insn;
80220
3
  cd->dis_hash_size = CGEN_DIS_HASH_SIZE;
80221
3
}