Coverage Report

Created: 2025-06-24 06:45

/src/binutils-gdb/opcodes/m32r-desc.c
Line
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Source (jump to first uncovered line)
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/* DO NOT EDIT!  -*- buffer-read-only: t -*- vi:set ro:  */
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/* CPU data for m32r.
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4
THIS FILE IS MACHINE GENERATED WITH CGEN.
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6
Copyright (C) 1996-2025 Free Software Foundation, Inc.
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8
This file is part of the GNU Binutils and/or GDB, the GNU debugger.
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   This file is free software; you can redistribute it and/or modify
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   it under the terms of the GNU General Public License as published by
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   the Free Software Foundation; either version 3, or (at your option)
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   any later version.
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   It is distributed in the hope that it will be useful, but WITHOUT
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   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
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   License for more details.
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   You should have received a copy of the GNU General Public License along
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   with this program; if not, write to the Free Software Foundation, Inc.,
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   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
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24
*/
25
26
#include "sysdep.h"
27
#include <stdio.h>
28
#include <stdarg.h>
29
#include <stdlib.h>
30
#include "ansidecl.h"
31
#include "bfd.h"
32
#include "symcat.h"
33
#include "m32r-desc.h"
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#include "m32r-opc.h"
35
#include "opintl.h"
36
#include "libiberty.h"
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#include "xregex.h"
38
39
/* Attributes.  */
40
41
static const CGEN_ATTR_ENTRY bool_attr[] =
42
{
43
  { "#f", 0 },
44
  { "#t", 1 },
45
  { 0, 0 }
46
};
47
48
static const CGEN_ATTR_ENTRY MACH_attr[] ATTRIBUTE_UNUSED =
49
{
50
  { "base", MACH_BASE },
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  { "m32r", MACH_M32R },
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  { "m32rx", MACH_M32RX },
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  { "m32r2", MACH_M32R2 },
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  { "max", MACH_MAX },
55
  { 0, 0 }
56
};
57
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static const CGEN_ATTR_ENTRY ISA_attr[] ATTRIBUTE_UNUSED =
59
{
60
  { "m32r", ISA_M32R },
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  { "max", ISA_MAX },
62
  { 0, 0 }
63
};
64
65
static const CGEN_ATTR_ENTRY PIPE_attr[] ATTRIBUTE_UNUSED =
66
{
67
  { "NONE", PIPE_NONE },
68
  { "O", PIPE_O },
69
  { "S", PIPE_S },
70
  { "OS", PIPE_OS },
71
  { "O_OS", PIPE_O_OS },
72
  { 0, 0 }
73
};
74
75
const CGEN_ATTR_TABLE m32r_cgen_ifield_attr_table[] =
76
{
77
  { "MACH", & MACH_attr[0], & MACH_attr[0] },
78
  { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
79
  { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
80
  { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
81
  { "RESERVED", &bool_attr[0], &bool_attr[0] },
82
  { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
83
  { "SIGNED", &bool_attr[0], &bool_attr[0] },
84
  { "RELOC", &bool_attr[0], &bool_attr[0] },
85
  { 0, 0, 0 }
86
};
87
88
const CGEN_ATTR_TABLE m32r_cgen_hardware_attr_table[] =
89
{
90
  { "MACH", & MACH_attr[0], & MACH_attr[0] },
91
  { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
92
  { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
93
  { "PC", &bool_attr[0], &bool_attr[0] },
94
  { "PROFILE", &bool_attr[0], &bool_attr[0] },
95
  { 0, 0, 0 }
96
};
97
98
const CGEN_ATTR_TABLE m32r_cgen_operand_attr_table[] =
99
{
100
  { "MACH", & MACH_attr[0], & MACH_attr[0] },
101
  { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
102
  { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
103
  { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
104
  { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
105
  { "SIGNED", &bool_attr[0], &bool_attr[0] },
106
  { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
107
  { "RELAX", &bool_attr[0], &bool_attr[0] },
108
  { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
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  { "RELOC", &bool_attr[0], &bool_attr[0] },
110
  { 0, 0, 0 }
111
};
112
113
const CGEN_ATTR_TABLE m32r_cgen_insn_attr_table[] =
114
{
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  { "MACH", & MACH_attr[0], & MACH_attr[0] },
116
  { "PIPE", & PIPE_attr[0], & PIPE_attr[0] },
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  { "ALIAS", &bool_attr[0], &bool_attr[0] },
118
  { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
119
  { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
120
  { "COND-CTI", &bool_attr[0], &bool_attr[0] },
121
  { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
122
  { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
123
  { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
124
  { "RELAXED", &bool_attr[0], &bool_attr[0] },
125
  { "NO-DIS", &bool_attr[0], &bool_attr[0] },
126
  { "PBB", &bool_attr[0], &bool_attr[0] },
127
  { "FILL-SLOT", &bool_attr[0], &bool_attr[0] },
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  { "SPECIAL", &bool_attr[0], &bool_attr[0] },
129
  { "SPECIAL_M32R", &bool_attr[0], &bool_attr[0] },
130
  { "SPECIAL_FLOAT", &bool_attr[0], &bool_attr[0] },
131
  { 0, 0, 0 }
132
};
133
134
/* Instruction set variants.  */
135
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static const CGEN_ISA m32r_cgen_isa_table[] = {
137
  { "m32r", 32, 32, 16, 32 },
138
  { 0, 0, 0, 0, 0 }
139
};
140
141
/* Machine variants.  */
142
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static const CGEN_MACH m32r_cgen_mach_table[] = {
144
  { "m32r", "m32r", MACH_M32R, 0 },
145
  { "m32rx", "m32rx", MACH_M32RX, 0 },
146
  { "m32r2", "m32r2", MACH_M32R2, 0 },
147
  { 0, 0, 0, 0 }
148
};
149
150
static CGEN_KEYWORD_ENTRY m32r_cgen_opval_gr_names_entries[] =
151
{
152
  { "fp", 13, {0, {{{0, 0}}}}, 0, 0 },
153
  { "lr", 14, {0, {{{0, 0}}}}, 0, 0 },
154
  { "sp", 15, {0, {{{0, 0}}}}, 0, 0 },
155
  { "r0", 0, {0, {{{0, 0}}}}, 0, 0 },
156
  { "r1", 1, {0, {{{0, 0}}}}, 0, 0 },
157
  { "r2", 2, {0, {{{0, 0}}}}, 0, 0 },
158
  { "r3", 3, {0, {{{0, 0}}}}, 0, 0 },
159
  { "r4", 4, {0, {{{0, 0}}}}, 0, 0 },
160
  { "r5", 5, {0, {{{0, 0}}}}, 0, 0 },
161
  { "r6", 6, {0, {{{0, 0}}}}, 0, 0 },
162
  { "r7", 7, {0, {{{0, 0}}}}, 0, 0 },
163
  { "r8", 8, {0, {{{0, 0}}}}, 0, 0 },
164
  { "r9", 9, {0, {{{0, 0}}}}, 0, 0 },
165
  { "r10", 10, {0, {{{0, 0}}}}, 0, 0 },
166
  { "r11", 11, {0, {{{0, 0}}}}, 0, 0 },
167
  { "r12", 12, {0, {{{0, 0}}}}, 0, 0 },
168
  { "r13", 13, {0, {{{0, 0}}}}, 0, 0 },
169
  { "r14", 14, {0, {{{0, 0}}}}, 0, 0 },
170
  { "r15", 15, {0, {{{0, 0}}}}, 0, 0 }
171
};
172
173
CGEN_KEYWORD m32r_cgen_opval_gr_names =
174
{
175
  & m32r_cgen_opval_gr_names_entries[0],
176
  19,
177
  0, 0, 0, 0, ""
178
};
179
180
static CGEN_KEYWORD_ENTRY m32r_cgen_opval_cr_names_entries[] =
181
{
182
  { "psw", 0, {0, {{{0, 0}}}}, 0, 0 },
183
  { "cbr", 1, {0, {{{0, 0}}}}, 0, 0 },
184
  { "spi", 2, {0, {{{0, 0}}}}, 0, 0 },
185
  { "spu", 3, {0, {{{0, 0}}}}, 0, 0 },
186
  { "bpc", 6, {0, {{{0, 0}}}}, 0, 0 },
187
  { "bbpsw", 8, {0, {{{0, 0}}}}, 0, 0 },
188
  { "bbpc", 14, {0, {{{0, 0}}}}, 0, 0 },
189
  { "evb", 5, {0, {{{0, 0}}}}, 0, 0 },
190
  { "cr0", 0, {0, {{{0, 0}}}}, 0, 0 },
191
  { "cr1", 1, {0, {{{0, 0}}}}, 0, 0 },
192
  { "cr2", 2, {0, {{{0, 0}}}}, 0, 0 },
193
  { "cr3", 3, {0, {{{0, 0}}}}, 0, 0 },
194
  { "cr4", 4, {0, {{{0, 0}}}}, 0, 0 },
195
  { "cr5", 5, {0, {{{0, 0}}}}, 0, 0 },
196
  { "cr6", 6, {0, {{{0, 0}}}}, 0, 0 },
197
  { "cr7", 7, {0, {{{0, 0}}}}, 0, 0 },
198
  { "cr8", 8, {0, {{{0, 0}}}}, 0, 0 },
199
  { "cr9", 9, {0, {{{0, 0}}}}, 0, 0 },
200
  { "cr10", 10, {0, {{{0, 0}}}}, 0, 0 },
201
  { "cr11", 11, {0, {{{0, 0}}}}, 0, 0 },
202
  { "cr12", 12, {0, {{{0, 0}}}}, 0, 0 },
203
  { "cr13", 13, {0, {{{0, 0}}}}, 0, 0 },
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  { "cr14", 14, {0, {{{0, 0}}}}, 0, 0 },
205
  { "cr15", 15, {0, {{{0, 0}}}}, 0, 0 }
206
};
207
208
CGEN_KEYWORD m32r_cgen_opval_cr_names =
209
{
210
  & m32r_cgen_opval_cr_names_entries[0],
211
  24,
212
  0, 0, 0, 0, ""
213
};
214
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static CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_accums_entries[] =
216
{
217
  { "a0", 0, {0, {{{0, 0}}}}, 0, 0 },
218
  { "a1", 1, {0, {{{0, 0}}}}, 0, 0 }
219
};
220
221
CGEN_KEYWORD m32r_cgen_opval_h_accums =
222
{
223
  & m32r_cgen_opval_h_accums_entries[0],
224
  2,
225
  0, 0, 0, 0, ""
226
};
227
228
229
/* The hardware table.  */
230
231
#define A(a) (1 << CGEN_HW_##a)
232
233
const CGEN_HW_ENTRY m32r_cgen_hw_table[] =
234
{
235
  { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
236
  { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
237
  { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
238
  { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
239
  { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
240
  { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { { { (1<<MACH_BASE), 0 } } } } },
241
  { "h-hi16", HW_H_HI16, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
242
  { "h-slo16", HW_H_SLO16, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
243
  { "h-ulo16", HW_H_ULO16, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
244
  { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, & m32r_cgen_opval_gr_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
245
  { "h-cr", HW_H_CR, CGEN_ASM_KEYWORD, & m32r_cgen_opval_cr_names, { 0, { { { (1<<MACH_BASE), 0 } } } } },
246
  { "h-accum", HW_H_ACCUM, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
247
  { "h-accums", HW_H_ACCUMS, CGEN_ASM_KEYWORD, & m32r_cgen_opval_h_accums, { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } } } } },
248
  { "h-cond", HW_H_COND, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
249
  { "h-psw", HW_H_PSW, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
250
  { "h-bpsw", HW_H_BPSW, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
251
  { "h-bbpsw", HW_H_BBPSW, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
252
  { "h-lock", HW_H_LOCK, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
253
  { 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
254
};
255
256
#undef A
257
258
259
/* The instruction field table.  */
260
261
#define A(a) (1 << CGEN_IFLD_##a)
262
263
const CGEN_IFLD m32r_cgen_ifld_table[] =
264
{
265
  { M32R_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
266
  { M32R_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
267
  { M32R_F_OP1, "f-op1", 0, 32, 0, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
268
  { M32R_F_OP2, "f-op2", 0, 32, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
269
  { M32R_F_COND, "f-cond", 0, 32, 4, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
270
  { M32R_F_R1, "f-r1", 0, 32, 4, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
271
  { M32R_F_R2, "f-r2", 0, 32, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
272
  { M32R_F_SIMM8, "f-simm8", 0, 32, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
273
  { M32R_F_SIMM16, "f-simm16", 0, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
274
  { M32R_F_SHIFT_OP2, "f-shift-op2", 0, 32, 8, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
275
  { M32R_F_UIMM3, "f-uimm3", 0, 32, 5, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
276
  { M32R_F_UIMM4, "f-uimm4", 0, 32, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
277
  { M32R_F_UIMM5, "f-uimm5", 0, 32, 11, 5, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
278
  { M32R_F_UIMM8, "f-uimm8", 0, 32, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
279
  { M32R_F_UIMM16, "f-uimm16", 0, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
280
  { M32R_F_UIMM24, "f-uimm24", 0, 32, 8, 24, { 0|A(RELOC)|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
281
  { M32R_F_HI16, "f-hi16", 0, 32, 16, 16, { 0|A(SIGN_OPT), { { { (1<<MACH_BASE), 0 } } } }  },
282
  { M32R_F_DISP8, "f-disp8", 0, 32, 8, 8, { 0|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
283
  { M32R_F_DISP16, "f-disp16", 0, 32, 16, 16, { 0|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
284
  { M32R_F_DISP24, "f-disp24", 0, 32, 8, 24, { 0|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
285
  { M32R_F_OP23, "f-op23", 0, 32, 9, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
286
  { M32R_F_OP3, "f-op3", 0, 32, 14, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
287
  { M32R_F_ACC, "f-acc", 0, 32, 8, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
288
  { M32R_F_ACCS, "f-accs", 0, 32, 12, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
289
  { M32R_F_ACCD, "f-accd", 0, 32, 4, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
290
  { M32R_F_BITS67, "f-bits67", 0, 32, 6, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
291
  { M32R_F_BIT4, "f-bit4", 0, 32, 4, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
292
  { M32R_F_BIT14, "f-bit14", 0, 32, 14, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
293
  { M32R_F_IMM1, "f-imm1", 0, 32, 15, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
294
  { 0, 0, 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
295
};
296
297
#undef A
298
299
300
301
/* multi ifield declarations */
302
303
304
305
/* multi ifield definitions */
306
307
308
/* The operand table.  */
309
310
#define A(a) (1 << CGEN_OPERAND_##a)
311
#define OPERAND(op) M32R_OPERAND_##op
312
313
const CGEN_OPERAND m32r_cgen_operand_table[] =
314
{
315
/* pc: program counter */
316
  { "pc", M32R_OPERAND_PC, HW_H_PC, 0, 0,
317
    { 0, { &m32r_cgen_ifld_table[M32R_F_NIL] } },
318
    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
319
/* sr: source register */
320
  { "sr", M32R_OPERAND_SR, HW_H_GR, 12, 4,
321
    { 0, { &m32r_cgen_ifld_table[M32R_F_R2] } },
322
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
323
/* dr: destination register */
324
  { "dr", M32R_OPERAND_DR, HW_H_GR, 4, 4,
325
    { 0, { &m32r_cgen_ifld_table[M32R_F_R1] } },
326
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
327
/* src1: source register 1 */
328
  { "src1", M32R_OPERAND_SRC1, HW_H_GR, 4, 4,
329
    { 0, { &m32r_cgen_ifld_table[M32R_F_R1] } },
330
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
331
/* src2: source register 2 */
332
  { "src2", M32R_OPERAND_SRC2, HW_H_GR, 12, 4,
333
    { 0, { &m32r_cgen_ifld_table[M32R_F_R2] } },
334
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
335
/* scr: source control register */
336
  { "scr", M32R_OPERAND_SCR, HW_H_CR, 12, 4,
337
    { 0, { &m32r_cgen_ifld_table[M32R_F_R2] } },
338
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
339
/* dcr: destination control register */
340
  { "dcr", M32R_OPERAND_DCR, HW_H_CR, 4, 4,
341
    { 0, { &m32r_cgen_ifld_table[M32R_F_R1] } },
342
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
343
/* simm8: 8 bit signed immediate */
344
  { "simm8", M32R_OPERAND_SIMM8, HW_H_SINT, 8, 8,
345
    { 0, { &m32r_cgen_ifld_table[M32R_F_SIMM8] } },
346
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
347
/* simm16: 16 bit signed immediate */
348
  { "simm16", M32R_OPERAND_SIMM16, HW_H_SINT, 16, 16,
349
    { 0, { &m32r_cgen_ifld_table[M32R_F_SIMM16] } },
350
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
351
/* uimm3: 3 bit unsigned number */
352
  { "uimm3", M32R_OPERAND_UIMM3, HW_H_UINT, 5, 3,
353
    { 0, { &m32r_cgen_ifld_table[M32R_F_UIMM3] } },
354
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
355
/* uimm4: 4 bit trap number */
356
  { "uimm4", M32R_OPERAND_UIMM4, HW_H_UINT, 12, 4,
357
    { 0, { &m32r_cgen_ifld_table[M32R_F_UIMM4] } },
358
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
359
/* uimm5: 5 bit shift count */
360
  { "uimm5", M32R_OPERAND_UIMM5, HW_H_UINT, 11, 5,
361
    { 0, { &m32r_cgen_ifld_table[M32R_F_UIMM5] } },
362
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
363
/* uimm8: 8 bit unsigned immediate */
364
  { "uimm8", M32R_OPERAND_UIMM8, HW_H_UINT, 8, 8,
365
    { 0, { &m32r_cgen_ifld_table[M32R_F_UIMM8] } },
366
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
367
/* uimm16: 16 bit unsigned immediate */
368
  { "uimm16", M32R_OPERAND_UIMM16, HW_H_UINT, 16, 16,
369
    { 0, { &m32r_cgen_ifld_table[M32R_F_UIMM16] } },
370
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
371
/* imm1: 1 bit immediate */
372
  { "imm1", M32R_OPERAND_IMM1, HW_H_UINT, 15, 1,
373
    { 0, { &m32r_cgen_ifld_table[M32R_F_IMM1] } },
374
    { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } } } }  },
375
/* accd: accumulator destination register */
376
  { "accd", M32R_OPERAND_ACCD, HW_H_ACCUMS, 4, 2,
377
    { 0, { &m32r_cgen_ifld_table[M32R_F_ACCD] } },
378
    { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } } } }  },
379
/* accs: accumulator source register */
380
  { "accs", M32R_OPERAND_ACCS, HW_H_ACCUMS, 12, 2,
381
    { 0, { &m32r_cgen_ifld_table[M32R_F_ACCS] } },
382
    { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } } } }  },
383
/* acc: accumulator reg (d) */
384
  { "acc", M32R_OPERAND_ACC, HW_H_ACCUMS, 8, 1,
385
    { 0, { &m32r_cgen_ifld_table[M32R_F_ACC] } },
386
    { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } } } }  },
387
/* hash: # prefix */
388
  { "hash", M32R_OPERAND_HASH, HW_H_SINT, 0, 0,
389
    { 0, { 0 } },
390
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
391
/* hi16: high 16 bit immediate, sign optional */
392
  { "hi16", M32R_OPERAND_HI16, HW_H_HI16, 16, 16,
393
    { 0, { &m32r_cgen_ifld_table[M32R_F_HI16] } },
394
    { 0|A(SIGN_OPT), { { { (1<<MACH_BASE), 0 } } } }  },
395
/* slo16: 16 bit signed immediate, for low() */
396
  { "slo16", M32R_OPERAND_SLO16, HW_H_SLO16, 16, 16,
397
    { 0, { &m32r_cgen_ifld_table[M32R_F_SIMM16] } },
398
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
399
/* ulo16: 16 bit unsigned immediate, for low() */
400
  { "ulo16", M32R_OPERAND_ULO16, HW_H_ULO16, 16, 16,
401
    { 0, { &m32r_cgen_ifld_table[M32R_F_UIMM16] } },
402
    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
403
/* uimm24: 24 bit address */
404
  { "uimm24", M32R_OPERAND_UIMM24, HW_H_ADDR, 8, 24,
405
    { 0, { &m32r_cgen_ifld_table[M32R_F_UIMM24] } },
406
    { 0|A(RELOC)|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
407
/* disp8: 8 bit displacement */
408
  { "disp8", M32R_OPERAND_DISP8, HW_H_IADDR, 8, 8,
409
    { 0, { &m32r_cgen_ifld_table[M32R_F_DISP8] } },
410
    { 0|A(RELAX)|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
411
/* disp16: 16 bit displacement */
412
  { "disp16", M32R_OPERAND_DISP16, HW_H_IADDR, 16, 16,
413
    { 0, { &m32r_cgen_ifld_table[M32R_F_DISP16] } },
414
    { 0|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
415
/* disp24: 24 bit displacement */
416
  { "disp24", M32R_OPERAND_DISP24, HW_H_IADDR, 8, 24,
417
    { 0, { &m32r_cgen_ifld_table[M32R_F_DISP24] } },
418
    { 0|A(RELAX)|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
419
/* condbit: condition bit */
420
  { "condbit", M32R_OPERAND_CONDBIT, HW_H_COND, 0, 0,
421
    { 0, { 0 } },
422
    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
423
/* accum: accumulator */
424
  { "accum", M32R_OPERAND_ACCUM, HW_H_ACCUM, 0, 0,
425
    { 0, { 0 } },
426
    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
427
/* sentinel */
428
  { 0, 0, 0, 0, 0,
429
    { 0, { 0 } },
430
    { 0, { { { (1<<MACH_BASE), 0 } } } } }
431
};
432
433
#undef A
434
435
436
/* The instruction table.  */
437
438
#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
439
#define A(a) (1 << CGEN_INSN_##a)
440
441
static const CGEN_IBASE m32r_cgen_insn_table[MAX_INSNS] =
442
{
443
  /* Special null first entry.
444
     A `num' value of zero is thus invalid.
445
     Also, the special `invalid' insn resides here.  */
446
  { 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } },
447
/* add $dr,$sr */
448
  {
449
    M32R_INSN_ADD, "add", "add", 16,
450
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
451
  },
452
/* add3 $dr,$sr,$hash$slo16 */
453
  {
454
    M32R_INSN_ADD3, "add3", "add3", 32,
455
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
456
  },
457
/* and $dr,$sr */
458
  {
459
    M32R_INSN_AND, "and", "and", 16,
460
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
461
  },
462
/* and3 $dr,$sr,$uimm16 */
463
  {
464
    M32R_INSN_AND3, "and3", "and3", 32,
465
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
466
  },
467
/* or $dr,$sr */
468
  {
469
    M32R_INSN_OR, "or", "or", 16,
470
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
471
  },
472
/* or3 $dr,$sr,$hash$ulo16 */
473
  {
474
    M32R_INSN_OR3, "or3", "or3", 32,
475
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
476
  },
477
/* xor $dr,$sr */
478
  {
479
    M32R_INSN_XOR, "xor", "xor", 16,
480
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
481
  },
482
/* xor3 $dr,$sr,$uimm16 */
483
  {
484
    M32R_INSN_XOR3, "xor3", "xor3", 32,
485
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
486
  },
487
/* addi $dr,$simm8 */
488
  {
489
    M32R_INSN_ADDI, "addi", "addi", 16,
490
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
491
  },
492
/* addv $dr,$sr */
493
  {
494
    M32R_INSN_ADDV, "addv", "addv", 16,
495
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
496
  },
497
/* addv3 $dr,$sr,$simm16 */
498
  {
499
    M32R_INSN_ADDV3, "addv3", "addv3", 32,
500
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
501
  },
502
/* addx $dr,$sr */
503
  {
504
    M32R_INSN_ADDX, "addx", "addx", 16,
505
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
506
  },
507
/* bc.s $disp8 */
508
  {
509
    M32R_INSN_BC8, "bc8", "bc.s", 16,
510
    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
511
  },
512
/* bc.l $disp24 */
513
  {
514
    M32R_INSN_BC24, "bc24", "bc.l", 32,
515
    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
516
  },
517
/* beq $src1,$src2,$disp16 */
518
  {
519
    M32R_INSN_BEQ, "beq", "beq", 32,
520
    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
521
  },
522
/* beqz $src2,$disp16 */
523
  {
524
    M32R_INSN_BEQZ, "beqz", "beqz", 32,
525
    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
526
  },
527
/* bgez $src2,$disp16 */
528
  {
529
    M32R_INSN_BGEZ, "bgez", "bgez", 32,
530
    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
531
  },
532
/* bgtz $src2,$disp16 */
533
  {
534
    M32R_INSN_BGTZ, "bgtz", "bgtz", 32,
535
    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
536
  },
537
/* blez $src2,$disp16 */
538
  {
539
    M32R_INSN_BLEZ, "blez", "blez", 32,
540
    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
541
  },
542
/* bltz $src2,$disp16 */
543
  {
544
    M32R_INSN_BLTZ, "bltz", "bltz", 32,
545
    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
546
  },
547
/* bnez $src2,$disp16 */
548
  {
549
    M32R_INSN_BNEZ, "bnez", "bnez", 32,
550
    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
551
  },
552
/* bl.s $disp8 */
553
  {
554
    M32R_INSN_BL8, "bl8", "bl.s", 16,
555
    { 0|A(FILL_SLOT)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
556
  },
557
/* bl.l $disp24 */
558
  {
559
    M32R_INSN_BL24, "bl24", "bl.l", 32,
560
    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
561
  },
562
/* bcl.s $disp8 */
563
  {
564
    M32R_INSN_BCL8, "bcl8", "bcl.s", 16,
565
    { 0|A(FILL_SLOT)|A(COND_CTI), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_O, 0 } } } }
566
  },
567
/* bcl.l $disp24 */
568
  {
569
    M32R_INSN_BCL24, "bcl24", "bcl.l", 32,
570
    { 0|A(COND_CTI), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } }
571
  },
572
/* bnc.s $disp8 */
573
  {
574
    M32R_INSN_BNC8, "bnc8", "bnc.s", 16,
575
    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
576
  },
577
/* bnc.l $disp24 */
578
  {
579
    M32R_INSN_BNC24, "bnc24", "bnc.l", 32,
580
    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
581
  },
582
/* bne $src1,$src2,$disp16 */
583
  {
584
    M32R_INSN_BNE, "bne", "bne", 32,
585
    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
586
  },
587
/* bra.s $disp8 */
588
  {
589
    M32R_INSN_BRA8, "bra8", "bra.s", 16,
590
    { 0|A(FILL_SLOT)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
591
  },
592
/* bra.l $disp24 */
593
  {
594
    M32R_INSN_BRA24, "bra24", "bra.l", 32,
595
    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
596
  },
597
/* bncl.s $disp8 */
598
  {
599
    M32R_INSN_BNCL8, "bncl8", "bncl.s", 16,
600
    { 0|A(FILL_SLOT)|A(COND_CTI), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_O, 0 } } } }
601
  },
602
/* bncl.l $disp24 */
603
  {
604
    M32R_INSN_BNCL24, "bncl24", "bncl.l", 32,
605
    { 0|A(COND_CTI), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } }
606
  },
607
/* cmp $src1,$src2 */
608
  {
609
    M32R_INSN_CMP, "cmp", "cmp", 16,
610
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
611
  },
612
/* cmpi $src2,$simm16 */
613
  {
614
    M32R_INSN_CMPI, "cmpi", "cmpi", 32,
615
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
616
  },
617
/* cmpu $src1,$src2 */
618
  {
619
    M32R_INSN_CMPU, "cmpu", "cmpu", 16,
620
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
621
  },
622
/* cmpui $src2,$simm16 */
623
  {
624
    M32R_INSN_CMPUI, "cmpui", "cmpui", 32,
625
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
626
  },
627
/* cmpeq $src1,$src2 */
628
  {
629
    M32R_INSN_CMPEQ, "cmpeq", "cmpeq", 16,
630
    { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_OS, 0 } } } }
631
  },
632
/* cmpz $src2 */
633
  {
634
    M32R_INSN_CMPZ, "cmpz", "cmpz", 16,
635
    { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_OS, 0 } } } }
636
  },
637
/* div $dr,$sr */
638
  {
639
    M32R_INSN_DIV, "div", "div", 32,
640
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
641
  },
642
/* divu $dr,$sr */
643
  {
644
    M32R_INSN_DIVU, "divu", "divu", 32,
645
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
646
  },
647
/* rem $dr,$sr */
648
  {
649
    M32R_INSN_REM, "rem", "rem", 32,
650
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
651
  },
652
/* remu $dr,$sr */
653
  {
654
    M32R_INSN_REMU, "remu", "remu", 32,
655
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
656
  },
657
/* remh $dr,$sr */
658
  {
659
    M32R_INSN_REMH, "remh", "remh", 32,
660
    { 0, { { { (1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } }
661
  },
662
/* remuh $dr,$sr */
663
  {
664
    M32R_INSN_REMUH, "remuh", "remuh", 32,
665
    { 0, { { { (1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } }
666
  },
667
/* remb $dr,$sr */
668
  {
669
    M32R_INSN_REMB, "remb", "remb", 32,
670
    { 0, { { { (1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } }
671
  },
672
/* remub $dr,$sr */
673
  {
674
    M32R_INSN_REMUB, "remub", "remub", 32,
675
    { 0, { { { (1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } }
676
  },
677
/* divuh $dr,$sr */
678
  {
679
    M32R_INSN_DIVUH, "divuh", "divuh", 32,
680
    { 0, { { { (1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } }
681
  },
682
/* divb $dr,$sr */
683
  {
684
    M32R_INSN_DIVB, "divb", "divb", 32,
685
    { 0, { { { (1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } }
686
  },
687
/* divub $dr,$sr */
688
  {
689
    M32R_INSN_DIVUB, "divub", "divub", 32,
690
    { 0, { { { (1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } }
691
  },
692
/* divh $dr,$sr */
693
  {
694
    M32R_INSN_DIVH, "divh", "divh", 32,
695
    { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } }
696
  },
697
/* jc $sr */
698
  {
699
    M32R_INSN_JC, "jc", "jc", 16,
700
    { 0|A(SPECIAL)|A(COND_CTI), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_O, 0 } } } }
701
  },
702
/* jnc $sr */
703
  {
704
    M32R_INSN_JNC, "jnc", "jnc", 16,
705
    { 0|A(SPECIAL)|A(COND_CTI), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_O, 0 } } } }
706
  },
707
/* jl $sr */
708
  {
709
    M32R_INSN_JL, "jl", "jl", 16,
710
    { 0|A(FILL_SLOT)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
711
  },
712
/* jmp $sr */
713
  {
714
    M32R_INSN_JMP, "jmp", "jmp", 16,
715
    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
716
  },
717
/* ld $dr,@$sr */
718
  {
719
    M32R_INSN_LD, "ld", "ld", 16,
720
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
721
  },
722
/* ld $dr,@($slo16,$sr) */
723
  {
724
    M32R_INSN_LD_D, "ld-d", "ld", 32,
725
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
726
  },
727
/* ldb $dr,@$sr */
728
  {
729
    M32R_INSN_LDB, "ldb", "ldb", 16,
730
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
731
  },
732
/* ldb $dr,@($slo16,$sr) */
733
  {
734
    M32R_INSN_LDB_D, "ldb-d", "ldb", 32,
735
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
736
  },
737
/* ldh $dr,@$sr */
738
  {
739
    M32R_INSN_LDH, "ldh", "ldh", 16,
740
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
741
  },
742
/* ldh $dr,@($slo16,$sr) */
743
  {
744
    M32R_INSN_LDH_D, "ldh-d", "ldh", 32,
745
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
746
  },
747
/* ldub $dr,@$sr */
748
  {
749
    M32R_INSN_LDUB, "ldub", "ldub", 16,
750
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
751
  },
752
/* ldub $dr,@($slo16,$sr) */
753
  {
754
    M32R_INSN_LDUB_D, "ldub-d", "ldub", 32,
755
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
756
  },
757
/* lduh $dr,@$sr */
758
  {
759
    M32R_INSN_LDUH, "lduh", "lduh", 16,
760
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
761
  },
762
/* lduh $dr,@($slo16,$sr) */
763
  {
764
    M32R_INSN_LDUH_D, "lduh-d", "lduh", 32,
765
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
766
  },
767
/* ld $dr,@$sr+ */
768
  {
769
    M32R_INSN_LD_PLUS, "ld-plus", "ld", 16,
770
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
771
  },
772
/* ld24 $dr,$uimm24 */
773
  {
774
    M32R_INSN_LD24, "ld24", "ld24", 32,
775
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
776
  },
777
/* ldi8 $dr,$simm8 */
778
  {
779
    M32R_INSN_LDI8, "ldi8", "ldi8", 16,
780
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
781
  },
782
/* ldi16 $dr,$hash$slo16 */
783
  {
784
    M32R_INSN_LDI16, "ldi16", "ldi16", 32,
785
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
786
  },
787
/* lock $dr,@$sr */
788
  {
789
    M32R_INSN_LOCK, "lock", "lock", 16,
790
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
791
  },
792
/* machi $src1,$src2 */
793
  {
794
    M32R_INSN_MACHI, "machi", "machi", 16,
795
    { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } }
796
  },
797
/* machi $src1,$src2,$acc */
798
  {
799
    M32R_INSN_MACHI_A, "machi-a", "machi", 16,
800
    { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
801
  },
802
/* maclo $src1,$src2 */
803
  {
804
    M32R_INSN_MACLO, "maclo", "maclo", 16,
805
    { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } }
806
  },
807
/* maclo $src1,$src2,$acc */
808
  {
809
    M32R_INSN_MACLO_A, "maclo-a", "maclo", 16,
810
    { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
811
  },
812
/* macwhi $src1,$src2 */
813
  {
814
    M32R_INSN_MACWHI, "macwhi", "macwhi", 16,
815
    { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } }
816
  },
817
/* macwhi $src1,$src2,$acc */
818
  {
819
    M32R_INSN_MACWHI_A, "macwhi-a", "macwhi", 16,
820
    { 0|A(SPECIAL), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
821
  },
822
/* macwlo $src1,$src2 */
823
  {
824
    M32R_INSN_MACWLO, "macwlo", "macwlo", 16,
825
    { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } }
826
  },
827
/* macwlo $src1,$src2,$acc */
828
  {
829
    M32R_INSN_MACWLO_A, "macwlo-a", "macwlo", 16,
830
    { 0|A(SPECIAL), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
831
  },
832
/* mul $dr,$sr */
833
  {
834
    M32R_INSN_MUL, "mul", "mul", 16,
835
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_S, 0 } } } }
836
  },
837
/* mulhi $src1,$src2 */
838
  {
839
    M32R_INSN_MULHI, "mulhi", "mulhi", 16,
840
    { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } }
841
  },
842
/* mulhi $src1,$src2,$acc */
843
  {
844
    M32R_INSN_MULHI_A, "mulhi-a", "mulhi", 16,
845
    { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
846
  },
847
/* mullo $src1,$src2 */
848
  {
849
    M32R_INSN_MULLO, "mullo", "mullo", 16,
850
    { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } }
851
  },
852
/* mullo $src1,$src2,$acc */
853
  {
854
    M32R_INSN_MULLO_A, "mullo-a", "mullo", 16,
855
    { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
856
  },
857
/* mulwhi $src1,$src2 */
858
  {
859
    M32R_INSN_MULWHI, "mulwhi", "mulwhi", 16,
860
    { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } }
861
  },
862
/* mulwhi $src1,$src2,$acc */
863
  {
864
    M32R_INSN_MULWHI_A, "mulwhi-a", "mulwhi", 16,
865
    { 0|A(SPECIAL), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
866
  },
867
/* mulwlo $src1,$src2 */
868
  {
869
    M32R_INSN_MULWLO, "mulwlo", "mulwlo", 16,
870
    { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } }
871
  },
872
/* mulwlo $src1,$src2,$acc */
873
  {
874
    M32R_INSN_MULWLO_A, "mulwlo-a", "mulwlo", 16,
875
    { 0|A(SPECIAL), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
876
  },
877
/* mv $dr,$sr */
878
  {
879
    M32R_INSN_MV, "mv", "mv", 16,
880
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
881
  },
882
/* mvfachi $dr */
883
  {
884
    M32R_INSN_MVFACHI, "mvfachi", "mvfachi", 16,
885
    { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } }
886
  },
887
/* mvfachi $dr,$accs */
888
  {
889
    M32R_INSN_MVFACHI_A, "mvfachi-a", "mvfachi", 16,
890
    { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
891
  },
892
/* mvfaclo $dr */
893
  {
894
    M32R_INSN_MVFACLO, "mvfaclo", "mvfaclo", 16,
895
    { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } }
896
  },
897
/* mvfaclo $dr,$accs */
898
  {
899
    M32R_INSN_MVFACLO_A, "mvfaclo-a", "mvfaclo", 16,
900
    { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
901
  },
902
/* mvfacmi $dr */
903
  {
904
    M32R_INSN_MVFACMI, "mvfacmi", "mvfacmi", 16,
905
    { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } }
906
  },
907
/* mvfacmi $dr,$accs */
908
  {
909
    M32R_INSN_MVFACMI_A, "mvfacmi-a", "mvfacmi", 16,
910
    { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
911
  },
912
/* mvfc $dr,$scr */
913
  {
914
    M32R_INSN_MVFC, "mvfc", "mvfc", 16,
915
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
916
  },
917
/* mvtachi $src1 */
918
  {
919
    M32R_INSN_MVTACHI, "mvtachi", "mvtachi", 16,
920
    { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } }
921
  },
922
/* mvtachi $src1,$accs */
923
  {
924
    M32R_INSN_MVTACHI_A, "mvtachi-a", "mvtachi", 16,
925
    { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
926
  },
927
/* mvtaclo $src1 */
928
  {
929
    M32R_INSN_MVTACLO, "mvtaclo", "mvtaclo", 16,
930
    { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } }
931
  },
932
/* mvtaclo $src1,$accs */
933
  {
934
    M32R_INSN_MVTACLO_A, "mvtaclo-a", "mvtaclo", 16,
935
    { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
936
  },
937
/* mvtc $sr,$dcr */
938
  {
939
    M32R_INSN_MVTC, "mvtc", "mvtc", 16,
940
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
941
  },
942
/* neg $dr,$sr */
943
  {
944
    M32R_INSN_NEG, "neg", "neg", 16,
945
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
946
  },
947
/* nop */
948
  {
949
    M32R_INSN_NOP, "nop", "nop", 16,
950
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
951
  },
952
/* not $dr,$sr */
953
  {
954
    M32R_INSN_NOT, "not", "not", 16,
955
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
956
  },
957
/* rac */
958
  {
959
    M32R_INSN_RAC, "rac", "rac", 16,
960
    { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } }
961
  },
962
/* rac $accd,$accs,$imm1 */
963
  {
964
    M32R_INSN_RAC_DSI, "rac-dsi", "rac", 16,
965
    { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
966
  },
967
/* rach */
968
  {
969
    M32R_INSN_RACH, "rach", "rach", 16,
970
    { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } }
971
  },
972
/* rach $accd,$accs,$imm1 */
973
  {
974
    M32R_INSN_RACH_DSI, "rach-dsi", "rach", 16,
975
    { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
976
  },
977
/* rte */
978
  {
979
    M32R_INSN_RTE, "rte", "rte", 16,
980
    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
981
  },
982
/* seth $dr,$hash$hi16 */
983
  {
984
    M32R_INSN_SETH, "seth", "seth", 32,
985
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
986
  },
987
/* sll $dr,$sr */
988
  {
989
    M32R_INSN_SLL, "sll", "sll", 16,
990
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O_OS, 0 } } } }
991
  },
992
/* sll3 $dr,$sr,$simm16 */
993
  {
994
    M32R_INSN_SLL3, "sll3", "sll3", 32,
995
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
996
  },
997
/* slli $dr,$uimm5 */
998
  {
999
    M32R_INSN_SLLI, "slli", "slli", 16,
1000
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O_OS, 0 } } } }
1001
  },
1002
/* sra $dr,$sr */
1003
  {
1004
    M32R_INSN_SRA, "sra", "sra", 16,
1005
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O_OS, 0 } } } }
1006
  },
1007
/* sra3 $dr,$sr,$simm16 */
1008
  {
1009
    M32R_INSN_SRA3, "sra3", "sra3", 32,
1010
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
1011
  },
1012
/* srai $dr,$uimm5 */
1013
  {
1014
    M32R_INSN_SRAI, "srai", "srai", 16,
1015
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O_OS, 0 } } } }
1016
  },
1017
/* srl $dr,$sr */
1018
  {
1019
    M32R_INSN_SRL, "srl", "srl", 16,
1020
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O_OS, 0 } } } }
1021
  },
1022
/* srl3 $dr,$sr,$simm16 */
1023
  {
1024
    M32R_INSN_SRL3, "srl3", "srl3", 32,
1025
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
1026
  },
1027
/* srli $dr,$uimm5 */
1028
  {
1029
    M32R_INSN_SRLI, "srli", "srli", 16,
1030
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O_OS, 0 } } } }
1031
  },
1032
/* st $src1,@$src2 */
1033
  {
1034
    M32R_INSN_ST, "st", "st", 16,
1035
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
1036
  },
1037
/* st $src1,@($slo16,$src2) */
1038
  {
1039
    M32R_INSN_ST_D, "st-d", "st", 32,
1040
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
1041
  },
1042
/* stb $src1,@$src2 */
1043
  {
1044
    M32R_INSN_STB, "stb", "stb", 16,
1045
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
1046
  },
1047
/* stb $src1,@($slo16,$src2) */
1048
  {
1049
    M32R_INSN_STB_D, "stb-d", "stb", 32,
1050
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
1051
  },
1052
/* sth $src1,@$src2 */
1053
  {
1054
    M32R_INSN_STH, "sth", "sth", 16,
1055
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
1056
  },
1057
/* sth $src1,@($slo16,$src2) */
1058
  {
1059
    M32R_INSN_STH_D, "sth-d", "sth", 32,
1060
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
1061
  },
1062
/* st $src1,@+$src2 */
1063
  {
1064
    M32R_INSN_ST_PLUS, "st-plus", "st", 16,
1065
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
1066
  },
1067
/* sth $src1,@$src2+ */
1068
  {
1069
    M32R_INSN_STH_PLUS, "sth-plus", "sth", 16,
1070
    { 0|A(SPECIAL), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_O, 0 } } } }
1071
  },
1072
/* stb $src1,@$src2+ */
1073
  {
1074
    M32R_INSN_STB_PLUS, "stb-plus", "stb", 16,
1075
    { 0|A(SPECIAL), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_O, 0 } } } }
1076
  },
1077
/* st $src1,@-$src2 */
1078
  {
1079
    M32R_INSN_ST_MINUS, "st-minus", "st", 16,
1080
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
1081
  },
1082
/* sub $dr,$sr */
1083
  {
1084
    M32R_INSN_SUB, "sub", "sub", 16,
1085
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1086
  },
1087
/* subv $dr,$sr */
1088
  {
1089
    M32R_INSN_SUBV, "subv", "subv", 16,
1090
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1091
  },
1092
/* subx $dr,$sr */
1093
  {
1094
    M32R_INSN_SUBX, "subx", "subx", 16,
1095
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1096
  },
1097
/* trap $uimm4 */
1098
  {
1099
    M32R_INSN_TRAP, "trap", "trap", 16,
1100
    { 0|A(FILL_SLOT)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
1101
  },
1102
/* unlock $src1,@$src2 */
1103
  {
1104
    M32R_INSN_UNLOCK, "unlock", "unlock", 16,
1105
    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
1106
  },
1107
/* satb $dr,$sr */
1108
  {
1109
    M32R_INSN_SATB, "satb", "satb", 32,
1110
    { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } }
1111
  },
1112
/* sath $dr,$sr */
1113
  {
1114
    M32R_INSN_SATH, "sath", "sath", 32,
1115
    { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } }
1116
  },
1117
/* sat $dr,$sr */
1118
  {
1119
    M32R_INSN_SAT, "sat", "sat", 32,
1120
    { 0|A(SPECIAL), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } }
1121
  },
1122
/* pcmpbz $src2 */
1123
  {
1124
    M32R_INSN_PCMPBZ, "pcmpbz", "pcmpbz", 16,
1125
    { 0|A(SPECIAL), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_OS, 0 } } } }
1126
  },
1127
/* sadd */
1128
  {
1129
    M32R_INSN_SADD, "sadd", "sadd", 16,
1130
    { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
1131
  },
1132
/* macwu1 $src1,$src2 */
1133
  {
1134
    M32R_INSN_MACWU1, "macwu1", "macwu1", 16,
1135
    { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
1136
  },
1137
/* msblo $src1,$src2 */
1138
  {
1139
    M32R_INSN_MSBLO, "msblo", "msblo", 16,
1140
    { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
1141
  },
1142
/* mulwu1 $src1,$src2 */
1143
  {
1144
    M32R_INSN_MULWU1, "mulwu1", "mulwu1", 16,
1145
    { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
1146
  },
1147
/* maclh1 $src1,$src2 */
1148
  {
1149
    M32R_INSN_MACLH1, "maclh1", "maclh1", 16,
1150
    { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
1151
  },
1152
/* sc */
1153
  {
1154
    M32R_INSN_SC, "sc", "sc", 16,
1155
    { 0|A(SPECIAL)|A(SKIP_CTI), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_O, 0 } } } }
1156
  },
1157
/* snc */
1158
  {
1159
    M32R_INSN_SNC, "snc", "snc", 16,
1160
    { 0|A(SPECIAL)|A(SKIP_CTI), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_O, 0 } } } }
1161
  },
1162
/* clrpsw $uimm8 */
1163
  {
1164
    M32R_INSN_CLRPSW, "clrpsw", "clrpsw", 16,
1165
    { 0|A(SPECIAL_M32R), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
1166
  },
1167
/* setpsw $uimm8 */
1168
  {
1169
    M32R_INSN_SETPSW, "setpsw", "setpsw", 16,
1170
    { 0|A(SPECIAL_M32R), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
1171
  },
1172
/* bset $uimm3,@($slo16,$sr) */
1173
  {
1174
    M32R_INSN_BSET, "bset", "bset", 32,
1175
    { 0|A(SPECIAL_M32R), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
1176
  },
1177
/* bclr $uimm3,@($slo16,$sr) */
1178
  {
1179
    M32R_INSN_BCLR, "bclr", "bclr", 32,
1180
    { 0|A(SPECIAL_M32R), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
1181
  },
1182
/* btst $uimm3,$sr */
1183
  {
1184
    M32R_INSN_BTST, "btst", "btst", 16,
1185
    { 0|A(SPECIAL_M32R), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
1186
  },
1187
};
1188
1189
#undef OP
1190
#undef A
1191
1192
/* Initialize anything needed to be done once, before any cpu_open call.  */
1193
1194
static void
1195
init_tables (void)
1196
2
{
1197
2
}
1198
1199
#ifndef opcodes_error_handler
1200
#define opcodes_error_handler(...) \
1201
  fprintf (stderr, __VA_ARGS__); fputc ('\n', stderr)
1202
#endif
1203
1204
static const CGEN_MACH * lookup_mach_via_bfd_name (const CGEN_MACH *, const char *);
1205
static void build_hw_table      (CGEN_CPU_TABLE *);
1206
static void build_ifield_table  (CGEN_CPU_TABLE *);
1207
static void build_operand_table (CGEN_CPU_TABLE *);
1208
static void build_insn_table    (CGEN_CPU_TABLE *);
1209
static void m32r_cgen_rebuild_tables (CGEN_CPU_TABLE *);
1210
1211
/* Subroutine of m32r_cgen_cpu_open to look up a mach via its bfd name.  */
1212
1213
static const CGEN_MACH *
1214
lookup_mach_via_bfd_name (const CGEN_MACH *table, const char *name)
1215
5
{
1216
8
  while (table->name)
1217
8
    {
1218
8
      if (strcmp (name, table->bfd_name) == 0)
1219
5
  return table;
1220
3
      ++table;
1221
3
    }
1222
0
  return NULL;
1223
5
}
1224
1225
/* Subroutine of m32r_cgen_cpu_open to build the hardware table.  */
1226
1227
static void
1228
build_hw_table (CGEN_CPU_TABLE *cd)
1229
5
{
1230
5
  int i;
1231
5
  int machs = cd->machs;
1232
5
  const CGEN_HW_ENTRY *init = & m32r_cgen_hw_table[0];
1233
  /* MAX_HW is only an upper bound on the number of selected entries.
1234
     However each entry is indexed by it's enum so there can be holes in
1235
     the table.  */
1236
5
  const CGEN_HW_ENTRY **selected =
1237
5
    (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *));
1238
1239
5
  cd->hw_table.init_entries = init;
1240
5
  cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY);
1241
5
  memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *));
1242
  /* ??? For now we just use machs to determine which ones we want.  */
1243
95
  for (i = 0; init[i].name != NULL; ++i)
1244
90
    if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH)
1245
90
  & machs)
1246
87
      selected[init[i].type] = &init[i];
1247
5
  cd->hw_table.entries = selected;
1248
5
  cd->hw_table.num_entries = MAX_HW;
1249
5
}
1250
1251
/* Subroutine of m32r_cgen_cpu_open to build the hardware table.  */
1252
1253
static void
1254
build_ifield_table (CGEN_CPU_TABLE *cd)
1255
5
{
1256
5
  cd->ifld_table = & m32r_cgen_ifld_table[0];
1257
5
}
1258
1259
/* Subroutine of m32r_cgen_cpu_open to build the hardware table.  */
1260
1261
static void
1262
build_operand_table (CGEN_CPU_TABLE *cd)
1263
5
{
1264
5
  int i;
1265
5
  int machs = cd->machs;
1266
5
  const CGEN_OPERAND *init = & m32r_cgen_operand_table[0];
1267
  /* MAX_OPERANDS is only an upper bound on the number of selected entries.
1268
     However each entry is indexed by it's enum so there can be holes in
1269
     the table.  */
1270
5
  const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected));
1271
1272
5
  cd->operand_table.init_entries = init;
1273
5
  cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
1274
5
  memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *));
1275
  /* ??? For now we just use mach to determine which ones we want.  */
1276
145
  for (i = 0; init[i].name != NULL; ++i)
1277
140
    if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH)
1278
140
  & machs)
1279
128
      selected[init[i].type] = &init[i];
1280
5
  cd->operand_table.entries = selected;
1281
5
  cd->operand_table.num_entries = MAX_OPERANDS;
1282
5
}
1283
1284
/* Subroutine of m32r_cgen_cpu_open to build the hardware table.
1285
   ??? This could leave out insns not supported by the specified mach/isa,
1286
   but that would cause errors like "foo only supported by bar" to become
1287
   "unknown insn", so for now we include all insns and require the app to
1288
   do the checking later.
1289
   ??? On the other hand, parsing of such insns may require their hardware or
1290
   operand elements to be in the table [which they mightn't be].  */
1291
1292
static void
1293
build_insn_table (CGEN_CPU_TABLE *cd)
1294
5
{
1295
5
  int i;
1296
5
  const CGEN_IBASE *ib = & m32r_cgen_insn_table[0];
1297
5
  CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
1298
1299
5
  memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
1300
750
  for (i = 0; i < MAX_INSNS; ++i)
1301
745
    insns[i].base = &ib[i];
1302
5
  cd->insn_table.init_entries = insns;
1303
5
  cd->insn_table.entry_size = sizeof (CGEN_IBASE);
1304
5
  cd->insn_table.num_init_entries = MAX_INSNS;
1305
5
}
1306
1307
/* Subroutine of m32r_cgen_cpu_open to rebuild the tables.  */
1308
1309
static void
1310
m32r_cgen_rebuild_tables (CGEN_CPU_TABLE *cd)
1311
5
{
1312
5
  int i;
1313
5
  CGEN_BITSET *isas = cd->isas;
1314
5
  unsigned int machs = cd->machs;
1315
1316
5
  cd->int_insn_p = CGEN_INT_INSN_P;
1317
1318
  /* Data derived from the isa spec.  */
1319
20
#define UNSET (CGEN_SIZE_UNKNOWN + 1)
1320
5
  cd->default_insn_bitsize = UNSET;
1321
5
  cd->base_insn_bitsize = UNSET;
1322
5
  cd->min_insn_bitsize = 65535; /* Some ridiculously big number.  */
1323
5
  cd->max_insn_bitsize = 0;
1324
10
  for (i = 0; i < MAX_ISAS; ++i)
1325
5
    if (cgen_bitset_contains (isas, i))
1326
5
      {
1327
5
  const CGEN_ISA *isa = & m32r_cgen_isa_table[i];
1328
1329
  /* Default insn sizes of all selected isas must be
1330
     equal or we set the result to 0, meaning "unknown".  */
1331
5
  if (cd->default_insn_bitsize == UNSET)
1332
5
    cd->default_insn_bitsize = isa->default_insn_bitsize;
1333
0
  else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
1334
0
    ; /* This is ok.  */
1335
0
  else
1336
0
    cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
1337
1338
  /* Base insn sizes of all selected isas must be equal
1339
     or we set the result to 0, meaning "unknown".  */
1340
5
  if (cd->base_insn_bitsize == UNSET)
1341
5
    cd->base_insn_bitsize = isa->base_insn_bitsize;
1342
0
  else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
1343
0
    ; /* This is ok.  */
1344
0
  else
1345
0
    cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
1346
1347
  /* Set min,max insn sizes.  */
1348
5
  if (isa->min_insn_bitsize < cd->min_insn_bitsize)
1349
5
    cd->min_insn_bitsize = isa->min_insn_bitsize;
1350
5
  if (isa->max_insn_bitsize > cd->max_insn_bitsize)
1351
5
    cd->max_insn_bitsize = isa->max_insn_bitsize;
1352
5
      }
1353
1354
  /* Data derived from the mach spec.  */
1355
25
  for (i = 0; i < MAX_MACHS; ++i)
1356
20
    if (((1 << i) & machs) != 0)
1357
10
      {
1358
10
  const CGEN_MACH *mach = & m32r_cgen_mach_table[i];
1359
1360
10
  if (mach->insn_chunk_bitsize != 0)
1361
0
  {
1362
0
    if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize)
1363
0
      {
1364
0
        opcodes_error_handler
1365
0
    (/* xgettext:c-format */
1366
0
     _("internal error: m32r_cgen_rebuild_tables: "
1367
0
       "conflicting insn-chunk-bitsize values: `%d' vs. `%d'"),
1368
0
     cd->insn_chunk_bitsize, mach->insn_chunk_bitsize);
1369
0
        abort ();
1370
0
      }
1371
1372
0
    cd->insn_chunk_bitsize = mach->insn_chunk_bitsize;
1373
0
  }
1374
10
      }
1375
1376
  /* Determine which hw elements are used by MACH.  */
1377
5
  build_hw_table (cd);
1378
1379
  /* Build the ifield table.  */
1380
5
  build_ifield_table (cd);
1381
1382
  /* Determine which operands are used by MACH/ISA.  */
1383
5
  build_operand_table (cd);
1384
1385
  /* Build the instruction table.  */
1386
5
  build_insn_table (cd);
1387
5
}
1388
1389
/* Initialize a cpu table and return a descriptor.
1390
   It's much like opening a file, and must be the first function called.
1391
   The arguments are a set of (type/value) pairs, terminated with
1392
   CGEN_CPU_OPEN_END.
1393
1394
   Currently supported values:
1395
   CGEN_CPU_OPEN_ISAS:    bitmap of values in enum isa_attr
1396
   CGEN_CPU_OPEN_MACHS:   bitmap of values in enum mach_attr
1397
   CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name
1398
   CGEN_CPU_OPEN_ENDIAN:  specify endian choice
1399
   CGEN_CPU_OPEN_INSN_ENDIAN: specify instruction endian choice
1400
   CGEN_CPU_OPEN_END:     terminates arguments
1401
1402
   ??? Simultaneous multiple isas might not make sense, but it's not (yet)
1403
   precluded.  */
1404
1405
CGEN_CPU_DESC
1406
m32r_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
1407
5
{
1408
5
  CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
1409
5
  static int init_p;
1410
5
  CGEN_BITSET *isas = 0;  /* 0 = "unspecified" */
1411
5
  unsigned int machs = 0; /* 0 = "unspecified" */
1412
5
  enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
1413
5
  enum cgen_endian insn_endian = CGEN_ENDIAN_UNKNOWN;
1414
5
  va_list ap;
1415
1416
5
  if (! init_p)
1417
2
    {
1418
2
      init_tables ();
1419
2
      init_p = 1;
1420
2
    }
1421
1422
5
  memset (cd, 0, sizeof (*cd));
1423
1424
5
  va_start (ap, arg_type);
1425
25
  while (arg_type != CGEN_CPU_OPEN_END)
1426
20
    {
1427
20
      switch (arg_type)
1428
20
  {
1429
5
  case CGEN_CPU_OPEN_ISAS :
1430
5
    isas = va_arg (ap, CGEN_BITSET *);
1431
5
    break;
1432
0
  case CGEN_CPU_OPEN_MACHS :
1433
0
    machs = va_arg (ap, unsigned int);
1434
0
    break;
1435
5
  case CGEN_CPU_OPEN_BFDMACH :
1436
5
    {
1437
5
      const char *name = va_arg (ap, const char *);
1438
5
      const CGEN_MACH *mach =
1439
5
        lookup_mach_via_bfd_name (m32r_cgen_mach_table, name);
1440
1441
5
      if (mach != NULL)
1442
5
        machs |= 1 << mach->num;
1443
5
      break;
1444
0
    }
1445
5
  case CGEN_CPU_OPEN_ENDIAN :
1446
5
    endian = va_arg (ap, enum cgen_endian);
1447
5
    break;
1448
5
  case CGEN_CPU_OPEN_INSN_ENDIAN :
1449
5
    insn_endian = va_arg (ap, enum cgen_endian);
1450
5
    break;
1451
0
  default :
1452
0
    opcodes_error_handler
1453
0
      (/* xgettext:c-format */
1454
0
       _("internal error: m32r_cgen_cpu_open: "
1455
0
         "unsupported argument `%d'"),
1456
0
       arg_type);
1457
0
    abort (); /* ??? return NULL? */
1458
20
  }
1459
20
      arg_type = va_arg (ap, enum cgen_cpu_open_arg);
1460
20
    }
1461
5
  va_end (ap);
1462
1463
  /* Mach unspecified means "all".  */
1464
5
  if (machs == 0)
1465
0
    machs = (1 << MAX_MACHS) - 1;
1466
  /* Base mach is always selected.  */
1467
5
  machs |= 1;
1468
5
  if (endian == CGEN_ENDIAN_UNKNOWN)
1469
0
    {
1470
      /* ??? If target has only one, could have a default.  */
1471
0
      opcodes_error_handler
1472
0
  (/* xgettext:c-format */
1473
0
   _("internal error: m32r_cgen_cpu_open: no endianness specified"));
1474
0
      abort ();
1475
0
    }
1476
1477
5
  cd->isas = cgen_bitset_copy (isas);
1478
5
  cd->machs = machs;
1479
5
  cd->endian = endian;
1480
5
  cd->insn_endian
1481
5
    = (insn_endian == CGEN_ENDIAN_UNKNOWN ? endian : insn_endian);
1482
1483
  /* Table (re)builder.  */
1484
5
  cd->rebuild_tables = m32r_cgen_rebuild_tables;
1485
5
  m32r_cgen_rebuild_tables (cd);
1486
1487
  /* Default to not allowing signed overflow.  */
1488
5
  cd->signed_overflow_ok_p = 0;
1489
1490
5
  return (CGEN_CPU_DESC) cd;
1491
5
}
1492
1493
/* Cover fn to m32r_cgen_cpu_open to handle the simple case of 1 isa, 1 mach.
1494
   MACH_NAME is the bfd name of the mach.  */
1495
1496
CGEN_CPU_DESC
1497
m32r_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian)
1498
0
{
1499
0
  return m32r_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
1500
0
             CGEN_CPU_OPEN_ENDIAN, endian,
1501
0
             CGEN_CPU_OPEN_END);
1502
0
}
1503
1504
/* Close a cpu table.
1505
   ??? This can live in a machine independent file, but there's currently
1506
   no place to put this file (there's no libcgen).  libopcodes is the wrong
1507
   place as some simulator ports use this but they don't use libopcodes.  */
1508
1509
void
1510
m32r_cgen_cpu_close (CGEN_CPU_DESC cd)
1511
0
{
1512
0
  unsigned int i;
1513
0
  const CGEN_INSN *insns;
1514
1515
0
  if (cd->macro_insn_table.init_entries)
1516
0
    {
1517
0
      insns = cd->macro_insn_table.init_entries;
1518
0
      for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
1519
0
  if (CGEN_INSN_RX ((insns)))
1520
0
    regfree (CGEN_INSN_RX (insns));
1521
0
    }
1522
1523
0
  if (cd->insn_table.init_entries)
1524
0
    {
1525
0
      insns = cd->insn_table.init_entries;
1526
0
      for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
1527
0
  if (CGEN_INSN_RX (insns))
1528
0
    regfree (CGEN_INSN_RX (insns));
1529
0
    }
1530
1531
0
  free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
1532
0
  free ((CGEN_INSN *) cd->insn_table.init_entries);
1533
0
  free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
1534
0
  free ((CGEN_HW_ENTRY *) cd->operand_table.entries);
1535
0
  free (cd);
1536
0
}
1537