/src/binutils-gdb/opcodes/mt-desc.c
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1 | | /* DO NOT EDIT! -*- buffer-read-only: t -*- vi:set ro: */ |
2 | | /* CPU data for mt. |
3 | | |
4 | | THIS FILE IS MACHINE GENERATED WITH CGEN. |
5 | | |
6 | | Copyright (C) 1996-2025 Free Software Foundation, Inc. |
7 | | |
8 | | This file is part of the GNU Binutils and/or GDB, the GNU debugger. |
9 | | |
10 | | This file is free software; you can redistribute it and/or modify |
11 | | it under the terms of the GNU General Public License as published by |
12 | | the Free Software Foundation; either version 3, or (at your option) |
13 | | any later version. |
14 | | |
15 | | It is distributed in the hope that it will be useful, but WITHOUT |
16 | | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY |
17 | | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public |
18 | | License for more details. |
19 | | |
20 | | You should have received a copy of the GNU General Public License along |
21 | | with this program; if not, write to the Free Software Foundation, Inc., |
22 | | 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. |
23 | | |
24 | | */ |
25 | | |
26 | | #include "sysdep.h" |
27 | | #include <stdio.h> |
28 | | #include <stdarg.h> |
29 | | #include <stdlib.h> |
30 | | #include "ansidecl.h" |
31 | | #include "bfd.h" |
32 | | #include "symcat.h" |
33 | | #include "mt-desc.h" |
34 | | #include "mt-opc.h" |
35 | | #include "opintl.h" |
36 | | #include "libiberty.h" |
37 | | #include "xregex.h" |
38 | | |
39 | | /* Attributes. */ |
40 | | |
41 | | static const CGEN_ATTR_ENTRY bool_attr[] = |
42 | | { |
43 | | { "#f", 0 }, |
44 | | { "#t", 1 }, |
45 | | { 0, 0 } |
46 | | }; |
47 | | |
48 | | static const CGEN_ATTR_ENTRY MACH_attr[] ATTRIBUTE_UNUSED = |
49 | | { |
50 | | { "base", MACH_BASE }, |
51 | | { "ms1", MACH_MS1 }, |
52 | | { "ms1_003", MACH_MS1_003 }, |
53 | | { "ms2", MACH_MS2 }, |
54 | | { "max", MACH_MAX }, |
55 | | { 0, 0 } |
56 | | }; |
57 | | |
58 | | static const CGEN_ATTR_ENTRY ISA_attr[] ATTRIBUTE_UNUSED = |
59 | | { |
60 | | { "mt", ISA_MT }, |
61 | | { "max", ISA_MAX }, |
62 | | { 0, 0 } |
63 | | }; |
64 | | |
65 | | const CGEN_ATTR_TABLE mt_cgen_ifield_attr_table[] = |
66 | | { |
67 | | { "MACH", & MACH_attr[0], & MACH_attr[0] }, |
68 | | { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, |
69 | | { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] }, |
70 | | { "ABS-ADDR", &bool_attr[0], &bool_attr[0] }, |
71 | | { "RESERVED", &bool_attr[0], &bool_attr[0] }, |
72 | | { "SIGN-OPT", &bool_attr[0], &bool_attr[0] }, |
73 | | { "SIGNED", &bool_attr[0], &bool_attr[0] }, |
74 | | { 0, 0, 0 } |
75 | | }; |
76 | | |
77 | | const CGEN_ATTR_TABLE mt_cgen_hardware_attr_table[] = |
78 | | { |
79 | | { "MACH", & MACH_attr[0], & MACH_attr[0] }, |
80 | | { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, |
81 | | { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] }, |
82 | | { "PC", &bool_attr[0], &bool_attr[0] }, |
83 | | { "PROFILE", &bool_attr[0], &bool_attr[0] }, |
84 | | { 0, 0, 0 } |
85 | | }; |
86 | | |
87 | | const CGEN_ATTR_TABLE mt_cgen_operand_attr_table[] = |
88 | | { |
89 | | { "MACH", & MACH_attr[0], & MACH_attr[0] }, |
90 | | { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, |
91 | | { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] }, |
92 | | { "ABS-ADDR", &bool_attr[0], &bool_attr[0] }, |
93 | | { "SIGN-OPT", &bool_attr[0], &bool_attr[0] }, |
94 | | { "SIGNED", &bool_attr[0], &bool_attr[0] }, |
95 | | { "NEGATIVE", &bool_attr[0], &bool_attr[0] }, |
96 | | { "RELAX", &bool_attr[0], &bool_attr[0] }, |
97 | | { "SEM-ONLY", &bool_attr[0], &bool_attr[0] }, |
98 | | { 0, 0, 0 } |
99 | | }; |
100 | | |
101 | | const CGEN_ATTR_TABLE mt_cgen_insn_attr_table[] = |
102 | | { |
103 | | { "MACH", & MACH_attr[0], & MACH_attr[0] }, |
104 | | { "ALIAS", &bool_attr[0], &bool_attr[0] }, |
105 | | { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, |
106 | | { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] }, |
107 | | { "COND-CTI", &bool_attr[0], &bool_attr[0] }, |
108 | | { "SKIP-CTI", &bool_attr[0], &bool_attr[0] }, |
109 | | { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] }, |
110 | | { "RELAXABLE", &bool_attr[0], &bool_attr[0] }, |
111 | | { "RELAXED", &bool_attr[0], &bool_attr[0] }, |
112 | | { "NO-DIS", &bool_attr[0], &bool_attr[0] }, |
113 | | { "PBB", &bool_attr[0], &bool_attr[0] }, |
114 | | { "LOAD-DELAY", &bool_attr[0], &bool_attr[0] }, |
115 | | { "MEMORY-ACCESS", &bool_attr[0], &bool_attr[0] }, |
116 | | { "AL-INSN", &bool_attr[0], &bool_attr[0] }, |
117 | | { "IO-INSN", &bool_attr[0], &bool_attr[0] }, |
118 | | { "BR-INSN", &bool_attr[0], &bool_attr[0] }, |
119 | | { "JAL-HAZARD", &bool_attr[0], &bool_attr[0] }, |
120 | | { "USES-FRDR", &bool_attr[0], &bool_attr[0] }, |
121 | | { "USES-FRDRRR", &bool_attr[0], &bool_attr[0] }, |
122 | | { "USES-FRSR1", &bool_attr[0], &bool_attr[0] }, |
123 | | { "USES-FRSR2", &bool_attr[0], &bool_attr[0] }, |
124 | | { "SKIPA", &bool_attr[0], &bool_attr[0] }, |
125 | | { 0, 0, 0 } |
126 | | }; |
127 | | |
128 | | /* Instruction set variants. */ |
129 | | |
130 | | static const CGEN_ISA mt_cgen_isa_table[] = { |
131 | | { "mt", 32, 32, 32, 32 }, |
132 | | { 0, 0, 0, 0, 0 } |
133 | | }; |
134 | | |
135 | | /* Machine variants. */ |
136 | | |
137 | | static const CGEN_MACH mt_cgen_mach_table[] = { |
138 | | { "ms1", "ms1", MACH_MS1, 0 }, |
139 | | { "ms1-003", "ms1-003", MACH_MS1_003, 0 }, |
140 | | { "ms2", "ms2", MACH_MS2, 0 }, |
141 | | { 0, 0, 0, 0 } |
142 | | }; |
143 | | |
144 | | static CGEN_KEYWORD_ENTRY mt_cgen_opval_msys_syms_entries[] = |
145 | | { |
146 | | { "DUP", 1, {0, {{{0, 0}}}}, 0, 0 }, |
147 | | { "XX", 0, {0, {{{0, 0}}}}, 0, 0 } |
148 | | }; |
149 | | |
150 | | CGEN_KEYWORD mt_cgen_opval_msys_syms = |
151 | | { |
152 | | & mt_cgen_opval_msys_syms_entries[0], |
153 | | 2, |
154 | | 0, 0, 0, 0, "" |
155 | | }; |
156 | | |
157 | | static CGEN_KEYWORD_ENTRY mt_cgen_opval_h_spr_entries[] = |
158 | | { |
159 | | { "R0", 0, {0, {{{0, 0}}}}, 0, 0 }, |
160 | | { "R1", 1, {0, {{{0, 0}}}}, 0, 0 }, |
161 | | { "R2", 2, {0, {{{0, 0}}}}, 0, 0 }, |
162 | | { "R3", 3, {0, {{{0, 0}}}}, 0, 0 }, |
163 | | { "R4", 4, {0, {{{0, 0}}}}, 0, 0 }, |
164 | | { "R5", 5, {0, {{{0, 0}}}}, 0, 0 }, |
165 | | { "R6", 6, {0, {{{0, 0}}}}, 0, 0 }, |
166 | | { "R7", 7, {0, {{{0, 0}}}}, 0, 0 }, |
167 | | { "R8", 8, {0, {{{0, 0}}}}, 0, 0 }, |
168 | | { "R9", 9, {0, {{{0, 0}}}}, 0, 0 }, |
169 | | { "R10", 10, {0, {{{0, 0}}}}, 0, 0 }, |
170 | | { "R11", 11, {0, {{{0, 0}}}}, 0, 0 }, |
171 | | { "R12", 12, {0, {{{0, 0}}}}, 0, 0 }, |
172 | | { "fp", 12, {0, {{{0, 0}}}}, 0, 0 }, |
173 | | { "R13", 13, {0, {{{0, 0}}}}, 0, 0 }, |
174 | | { "sp", 13, {0, {{{0, 0}}}}, 0, 0 }, |
175 | | { "R14", 14, {0, {{{0, 0}}}}, 0, 0 }, |
176 | | { "ra", 14, {0, {{{0, 0}}}}, 0, 0 }, |
177 | | { "R15", 15, {0, {{{0, 0}}}}, 0, 0 }, |
178 | | { "ira", 15, {0, {{{0, 0}}}}, 0, 0 } |
179 | | }; |
180 | | |
181 | | CGEN_KEYWORD mt_cgen_opval_h_spr = |
182 | | { |
183 | | & mt_cgen_opval_h_spr_entries[0], |
184 | | 20, |
185 | | 0, 0, 0, 0, "" |
186 | | }; |
187 | | |
188 | | |
189 | | /* The hardware table. */ |
190 | | |
191 | | #define A(a) (1 << CGEN_HW_##a) |
192 | | |
193 | | const CGEN_HW_ENTRY mt_cgen_hw_table[] = |
194 | | { |
195 | | { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
196 | | { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
197 | | { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
198 | | { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
199 | | { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
200 | | { "h-spr", HW_H_SPR, CGEN_ASM_KEYWORD, & mt_cgen_opval_h_spr, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
201 | | { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { { { (1<<MACH_BASE), 0 } } } } }, |
202 | | { 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } } |
203 | | }; |
204 | | |
205 | | #undef A |
206 | | |
207 | | |
208 | | /* The instruction field table. */ |
209 | | |
210 | | #define A(a) (1 << CGEN_IFLD_##a) |
211 | | |
212 | | const CGEN_IFLD mt_cgen_ifld_table[] = |
213 | | { |
214 | | { MT_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
215 | | { MT_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
216 | | { MT_F_MSYS, "f-msys", 0, 32, 31, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
217 | | { MT_F_OPC, "f-opc", 0, 32, 30, 6, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
218 | | { MT_F_IMM, "f-imm", 0, 32, 24, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
219 | | { MT_F_UU24, "f-uu24", 0, 32, 23, 24, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
220 | | { MT_F_SR1, "f-sr1", 0, 32, 23, 4, { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, |
221 | | { MT_F_SR2, "f-sr2", 0, 32, 19, 4, { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, |
222 | | { MT_F_DR, "f-dr", 0, 32, 19, 4, { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, |
223 | | { MT_F_DRRR, "f-drrr", 0, 32, 15, 4, { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, |
224 | | { MT_F_IMM16U, "f-imm16u", 0, 32, 15, 16, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
225 | | { MT_F_IMM16S, "f-imm16s", 0, 32, 15, 16, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
226 | | { MT_F_IMM16A, "f-imm16a", 0, 32, 15, 16, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, |
227 | | { MT_F_UU4A, "f-uu4a", 0, 32, 19, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
228 | | { MT_F_UU4B, "f-uu4b", 0, 32, 23, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
229 | | { MT_F_UU12, "f-uu12", 0, 32, 11, 12, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
230 | | { MT_F_UU8, "f-uu8", 0, 32, 15, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
231 | | { MT_F_UU16, "f-uu16", 0, 32, 15, 16, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
232 | | { MT_F_UU1, "f-uu1", 0, 32, 7, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
233 | | { MT_F_MSOPC, "f-msopc", 0, 32, 30, 5, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
234 | | { MT_F_UU_26_25, "f-uu-26-25", 0, 32, 25, 26, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
235 | | { MT_F_MASK, "f-mask", 0, 32, 25, 16, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
236 | | { MT_F_BANKADDR, "f-bankaddr", 0, 32, 25, 13, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
237 | | { MT_F_RDA, "f-rda", 0, 32, 25, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
238 | | { MT_F_UU_2_25, "f-uu-2-25", 0, 32, 25, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
239 | | { MT_F_RBBC, "f-rbbc", 0, 32, 25, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
240 | | { MT_F_PERM, "f-perm", 0, 32, 25, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
241 | | { MT_F_MODE, "f-mode", 0, 32, 25, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
242 | | { MT_F_UU_1_24, "f-uu-1-24", 0, 32, 24, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
243 | | { MT_F_WR, "f-wr", 0, 32, 24, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
244 | | { MT_F_FBINCR, "f-fbincr", 0, 32, 23, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
245 | | { MT_F_UU_2_23, "f-uu-2-23", 0, 32, 23, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
246 | | { MT_F_XMODE, "f-xmode", 0, 32, 23, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
247 | | { MT_F_A23, "f-a23", 0, 32, 23, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
248 | | { MT_F_MASK1, "f-mask1", 0, 32, 22, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
249 | | { MT_F_CR, "f-cr", 0, 32, 22, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
250 | | { MT_F_TYPE, "f-type", 0, 32, 21, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
251 | | { MT_F_INCAMT, "f-incamt", 0, 32, 19, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
252 | | { MT_F_CBS, "f-cbs", 0, 32, 19, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
253 | | { MT_F_UU_1_19, "f-uu-1-19", 0, 32, 19, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
254 | | { MT_F_BALL, "f-ball", 0, 32, 19, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
255 | | { MT_F_COLNUM, "f-colnum", 0, 32, 18, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
256 | | { MT_F_BRC, "f-brc", 0, 32, 18, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
257 | | { MT_F_INCR, "f-incr", 0, 32, 17, 6, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
258 | | { MT_F_FBDISP, "f-fbdisp", 0, 32, 15, 6, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
259 | | { MT_F_UU_4_15, "f-uu-4-15", 0, 32, 15, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
260 | | { MT_F_LENGTH, "f-length", 0, 32, 15, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
261 | | { MT_F_UU_1_15, "f-uu-1-15", 0, 32, 15, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
262 | | { MT_F_RC, "f-rc", 0, 32, 15, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
263 | | { MT_F_RCNUM, "f-rcnum", 0, 32, 14, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
264 | | { MT_F_ROWNUM, "f-rownum", 0, 32, 14, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
265 | | { MT_F_CBX, "f-cbx", 0, 32, 14, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
266 | | { MT_F_ID, "f-id", 0, 32, 14, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
267 | | { MT_F_SIZE, "f-size", 0, 32, 13, 14, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
268 | | { MT_F_ROWNUM1, "f-rownum1", 0, 32, 12, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
269 | | { MT_F_UU_3_11, "f-uu-3-11", 0, 32, 11, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
270 | | { MT_F_RC1, "f-rc1", 0, 32, 11, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
271 | | { MT_F_CCB, "f-ccb", 0, 32, 11, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
272 | | { MT_F_CBRB, "f-cbrb", 0, 32, 10, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
273 | | { MT_F_CDB, "f-cdb", 0, 32, 10, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
274 | | { MT_F_ROWNUM2, "f-rownum2", 0, 32, 9, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
275 | | { MT_F_CELL, "f-cell", 0, 32, 9, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
276 | | { MT_F_UU_3_9, "f-uu-3-9", 0, 32, 9, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
277 | | { MT_F_CONTNUM, "f-contnum", 0, 32, 8, 9, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
278 | | { MT_F_UU_1_6, "f-uu-1-6", 0, 32, 6, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
279 | | { MT_F_DUP, "f-dup", 0, 32, 6, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
280 | | { MT_F_RC2, "f-rc2", 0, 32, 6, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
281 | | { MT_F_CTXDISP, "f-ctxdisp", 0, 32, 5, 6, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
282 | | { MT_F_IMM16L, "f-imm16l", 0, 32, 23, 16, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
283 | | { MT_F_LOOPO, "f-loopo", 0, 32, 7, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
284 | | { MT_F_CB1SEL, "f-cb1sel", 0, 32, 25, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
285 | | { MT_F_CB2SEL, "f-cb2sel", 0, 32, 22, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
286 | | { MT_F_CB1INCR, "f-cb1incr", 0, 32, 19, 6, { 0|A(SIGNED), { { { (1<<MACH_BASE), 0 } } } } }, |
287 | | { MT_F_CB2INCR, "f-cb2incr", 0, 32, 13, 6, { 0|A(SIGNED), { { { (1<<MACH_BASE), 0 } } } } }, |
288 | | { MT_F_RC3, "f-rc3", 0, 32, 7, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
289 | | { MT_F_MSYSFRSR2, "f-msysfrsr2", 0, 32, 19, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
290 | | { MT_F_BRC2, "f-brc2", 0, 32, 14, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
291 | | { MT_F_BALL2, "f-ball2", 0, 32, 15, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
292 | | { 0, 0, 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } } |
293 | | }; |
294 | | |
295 | | #undef A |
296 | | |
297 | | |
298 | | |
299 | | /* multi ifield declarations */ |
300 | | |
301 | | |
302 | | |
303 | | /* multi ifield definitions */ |
304 | | |
305 | | |
306 | | /* The operand table. */ |
307 | | |
308 | | #define A(a) (1 << CGEN_OPERAND_##a) |
309 | | #define OPERAND(op) MT_OPERAND_##op |
310 | | |
311 | | const CGEN_OPERAND mt_cgen_operand_table[] = |
312 | | { |
313 | | /* pc: program counter */ |
314 | | { "pc", MT_OPERAND_PC, HW_H_PC, 0, 0, |
315 | | { 0, { &mt_cgen_ifld_table[MT_F_NIL] } }, |
316 | | { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, |
317 | | /* frsr1: register */ |
318 | | { "frsr1", MT_OPERAND_FRSR1, HW_H_SPR, 23, 4, |
319 | | { 0, { &mt_cgen_ifld_table[MT_F_SR1] } }, |
320 | | { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, |
321 | | /* frsr2: register */ |
322 | | { "frsr2", MT_OPERAND_FRSR2, HW_H_SPR, 19, 4, |
323 | | { 0, { &mt_cgen_ifld_table[MT_F_SR2] } }, |
324 | | { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, |
325 | | /* frdr: register */ |
326 | | { "frdr", MT_OPERAND_FRDR, HW_H_SPR, 19, 4, |
327 | | { 0, { &mt_cgen_ifld_table[MT_F_DR] } }, |
328 | | { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, |
329 | | /* frdrrr: register */ |
330 | | { "frdrrr", MT_OPERAND_FRDRRR, HW_H_SPR, 15, 4, |
331 | | { 0, { &mt_cgen_ifld_table[MT_F_DRRR] } }, |
332 | | { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, |
333 | | /* imm16: immediate value - sign extd */ |
334 | | { "imm16", MT_OPERAND_IMM16, HW_H_SINT, 15, 16, |
335 | | { 0, { &mt_cgen_ifld_table[MT_F_IMM16S] } }, |
336 | | { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
337 | | /* imm16z: immediate value - zero extd */ |
338 | | { "imm16z", MT_OPERAND_IMM16Z, HW_H_UINT, 15, 16, |
339 | | { 0, { &mt_cgen_ifld_table[MT_F_IMM16U] } }, |
340 | | { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
341 | | /* imm16o: immediate value */ |
342 | | { "imm16o", MT_OPERAND_IMM16O, HW_H_UINT, 15, 16, |
343 | | { 0, { &mt_cgen_ifld_table[MT_F_IMM16S] } }, |
344 | | { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, |
345 | | /* rc: rc */ |
346 | | { "rc", MT_OPERAND_RC, HW_H_UINT, 15, 1, |
347 | | { 0, { &mt_cgen_ifld_table[MT_F_RC] } }, |
348 | | { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
349 | | /* rcnum: rcnum */ |
350 | | { "rcnum", MT_OPERAND_RCNUM, HW_H_UINT, 14, 3, |
351 | | { 0, { &mt_cgen_ifld_table[MT_F_RCNUM] } }, |
352 | | { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
353 | | /* contnum: context number */ |
354 | | { "contnum", MT_OPERAND_CONTNUM, HW_H_UINT, 8, 9, |
355 | | { 0, { &mt_cgen_ifld_table[MT_F_CONTNUM] } }, |
356 | | { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
357 | | /* rbbc: omega network configuration */ |
358 | | { "rbbc", MT_OPERAND_RBBC, HW_H_UINT, 25, 2, |
359 | | { 0, { &mt_cgen_ifld_table[MT_F_RBBC] } }, |
360 | | { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
361 | | /* colnum: column number */ |
362 | | { "colnum", MT_OPERAND_COLNUM, HW_H_UINT, 18, 3, |
363 | | { 0, { &mt_cgen_ifld_table[MT_F_COLNUM] } }, |
364 | | { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
365 | | /* rownum: row number */ |
366 | | { "rownum", MT_OPERAND_ROWNUM, HW_H_UINT, 14, 3, |
367 | | { 0, { &mt_cgen_ifld_table[MT_F_ROWNUM] } }, |
368 | | { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
369 | | /* rownum1: row number */ |
370 | | { "rownum1", MT_OPERAND_ROWNUM1, HW_H_UINT, 12, 3, |
371 | | { 0, { &mt_cgen_ifld_table[MT_F_ROWNUM1] } }, |
372 | | { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
373 | | /* rownum2: row number */ |
374 | | { "rownum2", MT_OPERAND_ROWNUM2, HW_H_UINT, 9, 3, |
375 | | { 0, { &mt_cgen_ifld_table[MT_F_ROWNUM2] } }, |
376 | | { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
377 | | /* rc1: rc1 */ |
378 | | { "rc1", MT_OPERAND_RC1, HW_H_UINT, 11, 1, |
379 | | { 0, { &mt_cgen_ifld_table[MT_F_RC1] } }, |
380 | | { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
381 | | /* rc2: rc2 */ |
382 | | { "rc2", MT_OPERAND_RC2, HW_H_UINT, 6, 1, |
383 | | { 0, { &mt_cgen_ifld_table[MT_F_RC2] } }, |
384 | | { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
385 | | /* cbrb: data-bus orientation */ |
386 | | { "cbrb", MT_OPERAND_CBRB, HW_H_UINT, 10, 1, |
387 | | { 0, { &mt_cgen_ifld_table[MT_F_CBRB] } }, |
388 | | { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
389 | | /* cell: cell */ |
390 | | { "cell", MT_OPERAND_CELL, HW_H_UINT, 9, 3, |
391 | | { 0, { &mt_cgen_ifld_table[MT_F_CELL] } }, |
392 | | { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
393 | | /* dup: dup */ |
394 | | { "dup", MT_OPERAND_DUP, HW_H_UINT, 6, 1, |
395 | | { 0, { &mt_cgen_ifld_table[MT_F_DUP] } }, |
396 | | { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
397 | | /* ctxdisp: context displacement */ |
398 | | { "ctxdisp", MT_OPERAND_CTXDISP, HW_H_UINT, 5, 6, |
399 | | { 0, { &mt_cgen_ifld_table[MT_F_CTXDISP] } }, |
400 | | { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
401 | | /* fbdisp: frame buffer displacement */ |
402 | | { "fbdisp", MT_OPERAND_FBDISP, HW_H_UINT, 15, 6, |
403 | | { 0, { &mt_cgen_ifld_table[MT_F_FBDISP] } }, |
404 | | { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
405 | | /* type: type */ |
406 | | { "type", MT_OPERAND_TYPE, HW_H_UINT, 21, 2, |
407 | | { 0, { &mt_cgen_ifld_table[MT_F_TYPE] } }, |
408 | | { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
409 | | /* mask: mask */ |
410 | | { "mask", MT_OPERAND_MASK, HW_H_UINT, 25, 16, |
411 | | { 0, { &mt_cgen_ifld_table[MT_F_MASK] } }, |
412 | | { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
413 | | /* bankaddr: bank address */ |
414 | | { "bankaddr", MT_OPERAND_BANKADDR, HW_H_UINT, 25, 13, |
415 | | { 0, { &mt_cgen_ifld_table[MT_F_BANKADDR] } }, |
416 | | { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
417 | | /* incamt: increment amount */ |
418 | | { "incamt", MT_OPERAND_INCAMT, HW_H_UINT, 19, 8, |
419 | | { 0, { &mt_cgen_ifld_table[MT_F_INCAMT] } }, |
420 | | { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
421 | | /* xmode: xmode */ |
422 | | { "xmode", MT_OPERAND_XMODE, HW_H_UINT, 23, 1, |
423 | | { 0, { &mt_cgen_ifld_table[MT_F_XMODE] } }, |
424 | | { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
425 | | /* mask1: mask1 */ |
426 | | { "mask1", MT_OPERAND_MASK1, HW_H_UINT, 22, 3, |
427 | | { 0, { &mt_cgen_ifld_table[MT_F_MASK1] } }, |
428 | | { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
429 | | /* ball: b_all */ |
430 | | { "ball", MT_OPERAND_BALL, HW_H_UINT, 19, 1, |
431 | | { 0, { &mt_cgen_ifld_table[MT_F_BALL] } }, |
432 | | { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
433 | | /* brc: b_r_c */ |
434 | | { "brc", MT_OPERAND_BRC, HW_H_UINT, 18, 3, |
435 | | { 0, { &mt_cgen_ifld_table[MT_F_BRC] } }, |
436 | | { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
437 | | /* rda: rd */ |
438 | | { "rda", MT_OPERAND_RDA, HW_H_UINT, 25, 1, |
439 | | { 0, { &mt_cgen_ifld_table[MT_F_RDA] } }, |
440 | | { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
441 | | /* wr: wr */ |
442 | | { "wr", MT_OPERAND_WR, HW_H_UINT, 24, 1, |
443 | | { 0, { &mt_cgen_ifld_table[MT_F_WR] } }, |
444 | | { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
445 | | /* ball2: b_all2 */ |
446 | | { "ball2", MT_OPERAND_BALL2, HW_H_UINT, 15, 1, |
447 | | { 0, { &mt_cgen_ifld_table[MT_F_BALL2] } }, |
448 | | { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
449 | | /* brc2: b_r_c2 */ |
450 | | { "brc2", MT_OPERAND_BRC2, HW_H_UINT, 14, 3, |
451 | | { 0, { &mt_cgen_ifld_table[MT_F_BRC2] } }, |
452 | | { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
453 | | /* perm: perm */ |
454 | | { "perm", MT_OPERAND_PERM, HW_H_UINT, 25, 2, |
455 | | { 0, { &mt_cgen_ifld_table[MT_F_PERM] } }, |
456 | | { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
457 | | /* a23: a23 */ |
458 | | { "a23", MT_OPERAND_A23, HW_H_UINT, 23, 1, |
459 | | { 0, { &mt_cgen_ifld_table[MT_F_A23] } }, |
460 | | { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
461 | | /* cr: c-r */ |
462 | | { "cr", MT_OPERAND_CR, HW_H_UINT, 22, 3, |
463 | | { 0, { &mt_cgen_ifld_table[MT_F_CR] } }, |
464 | | { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
465 | | /* cbs: cbs */ |
466 | | { "cbs", MT_OPERAND_CBS, HW_H_UINT, 19, 2, |
467 | | { 0, { &mt_cgen_ifld_table[MT_F_CBS] } }, |
468 | | { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
469 | | /* incr: incr */ |
470 | | { "incr", MT_OPERAND_INCR, HW_H_UINT, 17, 6, |
471 | | { 0, { &mt_cgen_ifld_table[MT_F_INCR] } }, |
472 | | { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
473 | | /* length: length */ |
474 | | { "length", MT_OPERAND_LENGTH, HW_H_UINT, 15, 3, |
475 | | { 0, { &mt_cgen_ifld_table[MT_F_LENGTH] } }, |
476 | | { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
477 | | /* cbx: cbx */ |
478 | | { "cbx", MT_OPERAND_CBX, HW_H_UINT, 14, 3, |
479 | | { 0, { &mt_cgen_ifld_table[MT_F_CBX] } }, |
480 | | { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
481 | | /* ccb: ccb */ |
482 | | { "ccb", MT_OPERAND_CCB, HW_H_UINT, 11, 1, |
483 | | { 0, { &mt_cgen_ifld_table[MT_F_CCB] } }, |
484 | | { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
485 | | /* cdb: cdb */ |
486 | | { "cdb", MT_OPERAND_CDB, HW_H_UINT, 10, 1, |
487 | | { 0, { &mt_cgen_ifld_table[MT_F_CDB] } }, |
488 | | { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
489 | | /* mode: mode */ |
490 | | { "mode", MT_OPERAND_MODE, HW_H_UINT, 25, 2, |
491 | | { 0, { &mt_cgen_ifld_table[MT_F_MODE] } }, |
492 | | { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
493 | | /* id: i/d */ |
494 | | { "id", MT_OPERAND_ID, HW_H_UINT, 14, 1, |
495 | | { 0, { &mt_cgen_ifld_table[MT_F_ID] } }, |
496 | | { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
497 | | /* size: size */ |
498 | | { "size", MT_OPERAND_SIZE, HW_H_UINT, 13, 14, |
499 | | { 0, { &mt_cgen_ifld_table[MT_F_SIZE] } }, |
500 | | { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
501 | | /* fbincr: fb incr */ |
502 | | { "fbincr", MT_OPERAND_FBINCR, HW_H_UINT, 23, 4, |
503 | | { 0, { &mt_cgen_ifld_table[MT_F_FBINCR] } }, |
504 | | { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
505 | | /* loopsize: immediate value */ |
506 | | { "loopsize", MT_OPERAND_LOOPSIZE, HW_H_UINT, 7, 8, |
507 | | { 0, { &mt_cgen_ifld_table[MT_F_LOOPO] } }, |
508 | | { 0|A(PCREL_ADDR), { { { (1<<MACH_MS2), 0 } } } } }, |
509 | | /* imm16l: immediate value */ |
510 | | { "imm16l", MT_OPERAND_IMM16L, HW_H_UINT, 23, 16, |
511 | | { 0, { &mt_cgen_ifld_table[MT_F_IMM16L] } }, |
512 | | { 0, { { { (1<<MACH_MS2), 0 } } } } }, |
513 | | /* rc3: rc3 */ |
514 | | { "rc3", MT_OPERAND_RC3, HW_H_UINT, 7, 1, |
515 | | { 0, { &mt_cgen_ifld_table[MT_F_RC3] } }, |
516 | | { 0, { { { (1<<MACH_MS2), 0 } } } } }, |
517 | | /* cb1sel: cb1sel */ |
518 | | { "cb1sel", MT_OPERAND_CB1SEL, HW_H_UINT, 25, 3, |
519 | | { 0, { &mt_cgen_ifld_table[MT_F_CB1SEL] } }, |
520 | | { 0, { { { (1<<MACH_MS2), 0 } } } } }, |
521 | | /* cb2sel: cb2sel */ |
522 | | { "cb2sel", MT_OPERAND_CB2SEL, HW_H_UINT, 22, 3, |
523 | | { 0, { &mt_cgen_ifld_table[MT_F_CB2SEL] } }, |
524 | | { 0, { { { (1<<MACH_MS2), 0 } } } } }, |
525 | | /* cb1incr: cb1incr */ |
526 | | { "cb1incr", MT_OPERAND_CB1INCR, HW_H_SINT, 19, 6, |
527 | | { 0, { &mt_cgen_ifld_table[MT_F_CB1INCR] } }, |
528 | | { 0|A(SIGNED), { { { (1<<MACH_MS2), 0 } } } } }, |
529 | | /* cb2incr: cb2incr */ |
530 | | { "cb2incr", MT_OPERAND_CB2INCR, HW_H_SINT, 13, 6, |
531 | | { 0, { &mt_cgen_ifld_table[MT_F_CB2INCR] } }, |
532 | | { 0|A(SIGNED), { { { (1<<MACH_MS2), 0 } } } } }, |
533 | | /* sentinel */ |
534 | | { 0, 0, 0, 0, 0, |
535 | | { 0, { 0 } }, |
536 | | { 0, { { { (1<<MACH_BASE), 0 } } } } } |
537 | | }; |
538 | | |
539 | | #undef A |
540 | | |
541 | | |
542 | | /* The instruction table. */ |
543 | | |
544 | | #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field)) |
545 | | #define A(a) (1 << CGEN_INSN_##a) |
546 | | |
547 | | static const CGEN_IBASE mt_cgen_insn_table[MAX_INSNS] = |
548 | | { |
549 | | /* Special null first entry. |
550 | | A `num' value of zero is thus invalid. |
551 | | Also, the special `invalid' insn resides here. */ |
552 | | { 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
553 | | /* add $frdrrr,$frsr1,$frsr2 */ |
554 | | { |
555 | | MT_INSN_ADD, "add", "add", 32, |
556 | | { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } } |
557 | | }, |
558 | | /* addu $frdrrr,$frsr1,$frsr2 */ |
559 | | { |
560 | | MT_INSN_ADDU, "addu", "addu", 32, |
561 | | { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } } |
562 | | }, |
563 | | /* addi $frdr,$frsr1,#$imm16 */ |
564 | | { |
565 | | MT_INSN_ADDI, "addi", "addi", 32, |
566 | | { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } } |
567 | | }, |
568 | | /* addui $frdr,$frsr1,#$imm16z */ |
569 | | { |
570 | | MT_INSN_ADDUI, "addui", "addui", 32, |
571 | | { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } } |
572 | | }, |
573 | | /* sub $frdrrr,$frsr1,$frsr2 */ |
574 | | { |
575 | | MT_INSN_SUB, "sub", "sub", 32, |
576 | | { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } } |
577 | | }, |
578 | | /* subu $frdrrr,$frsr1,$frsr2 */ |
579 | | { |
580 | | MT_INSN_SUBU, "subu", "subu", 32, |
581 | | { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } } |
582 | | }, |
583 | | /* subi $frdr,$frsr1,#$imm16 */ |
584 | | { |
585 | | MT_INSN_SUBI, "subi", "subi", 32, |
586 | | { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } } |
587 | | }, |
588 | | /* subui $frdr,$frsr1,#$imm16z */ |
589 | | { |
590 | | MT_INSN_SUBUI, "subui", "subui", 32, |
591 | | { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } } |
592 | | }, |
593 | | /* mul $frdrrr,$frsr1,$frsr2 */ |
594 | | { |
595 | | MT_INSN_MUL, "mul", "mul", 32, |
596 | | { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { { { (1<<MACH_MS1_003)|(1<<MACH_MS2), 0 } } } } |
597 | | }, |
598 | | /* muli $frdr,$frsr1,#$imm16 */ |
599 | | { |
600 | | MT_INSN_MULI, "muli", "muli", 32, |
601 | | { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_MS1_003)|(1<<MACH_MS2), 0 } } } } |
602 | | }, |
603 | | /* and $frdrrr,$frsr1,$frsr2 */ |
604 | | { |
605 | | MT_INSN_AND, "and", "and", 32, |
606 | | { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } } |
607 | | }, |
608 | | /* andi $frdr,$frsr1,#$imm16z */ |
609 | | { |
610 | | MT_INSN_ANDI, "andi", "andi", 32, |
611 | | { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } } |
612 | | }, |
613 | | /* or $frdrrr,$frsr1,$frsr2 */ |
614 | | { |
615 | | MT_INSN_OR, "or", "or", 32, |
616 | | { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } } |
617 | | }, |
618 | | /* nop */ |
619 | | { |
620 | | MT_INSN_NOP, "nop", "nop", 32, |
621 | | { 0, { { { (1<<MACH_BASE), 0 } } } } |
622 | | }, |
623 | | /* ori $frdr,$frsr1,#$imm16z */ |
624 | | { |
625 | | MT_INSN_ORI, "ori", "ori", 32, |
626 | | { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } } |
627 | | }, |
628 | | /* xor $frdrrr,$frsr1,$frsr2 */ |
629 | | { |
630 | | MT_INSN_XOR, "xor", "xor", 32, |
631 | | { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } } |
632 | | }, |
633 | | /* xori $frdr,$frsr1,#$imm16z */ |
634 | | { |
635 | | MT_INSN_XORI, "xori", "xori", 32, |
636 | | { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } } |
637 | | }, |
638 | | /* nand $frdrrr,$frsr1,$frsr2 */ |
639 | | { |
640 | | MT_INSN_NAND, "nand", "nand", 32, |
641 | | { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } } |
642 | | }, |
643 | | /* nandi $frdr,$frsr1,#$imm16z */ |
644 | | { |
645 | | MT_INSN_NANDI, "nandi", "nandi", 32, |
646 | | { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } } |
647 | | }, |
648 | | /* nor $frdrrr,$frsr1,$frsr2 */ |
649 | | { |
650 | | MT_INSN_NOR, "nor", "nor", 32, |
651 | | { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } } |
652 | | }, |
653 | | /* nori $frdr,$frsr1,#$imm16z */ |
654 | | { |
655 | | MT_INSN_NORI, "nori", "nori", 32, |
656 | | { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } } |
657 | | }, |
658 | | /* xnor $frdrrr,$frsr1,$frsr2 */ |
659 | | { |
660 | | MT_INSN_XNOR, "xnor", "xnor", 32, |
661 | | { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } } |
662 | | }, |
663 | | /* xnori $frdr,$frsr1,#$imm16z */ |
664 | | { |
665 | | MT_INSN_XNORI, "xnori", "xnori", 32, |
666 | | { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } } |
667 | | }, |
668 | | /* ldui $frdr,#$imm16z */ |
669 | | { |
670 | | MT_INSN_LDUI, "ldui", "ldui", 32, |
671 | | { 0|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } } |
672 | | }, |
673 | | /* lsl $frdrrr,$frsr1,$frsr2 */ |
674 | | { |
675 | | MT_INSN_LSL, "lsl", "lsl", 32, |
676 | | { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR), { { { (1<<MACH_BASE), 0 } } } } |
677 | | }, |
678 | | /* lsli $frdr,$frsr1,#$imm16 */ |
679 | | { |
680 | | MT_INSN_LSLI, "lsli", "lsli", 32, |
681 | | { 0|A(USES_FRSR1)|A(USES_FRDR), { { { (1<<MACH_BASE), 0 } } } } |
682 | | }, |
683 | | /* lsr $frdrrr,$frsr1,$frsr2 */ |
684 | | { |
685 | | MT_INSN_LSR, "lsr", "lsr", 32, |
686 | | { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR), { { { (1<<MACH_BASE), 0 } } } } |
687 | | }, |
688 | | /* lsri $frdr,$frsr1,#$imm16 */ |
689 | | { |
690 | | MT_INSN_LSRI, "lsri", "lsri", 32, |
691 | | { 0|A(USES_FRSR1)|A(USES_FRDR), { { { (1<<MACH_BASE), 0 } } } } |
692 | | }, |
693 | | /* asr $frdrrr,$frsr1,$frsr2 */ |
694 | | { |
695 | | MT_INSN_ASR, "asr", "asr", 32, |
696 | | { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR), { { { (1<<MACH_BASE), 0 } } } } |
697 | | }, |
698 | | /* asri $frdr,$frsr1,#$imm16 */ |
699 | | { |
700 | | MT_INSN_ASRI, "asri", "asri", 32, |
701 | | { 0|A(USES_FRSR1)|A(USES_FRDR), { { { (1<<MACH_BASE), 0 } } } } |
702 | | }, |
703 | | /* brlt $frsr1,$frsr2,$imm16o */ |
704 | | { |
705 | | MT_INSN_BRLT, "brlt", "brlt", 32, |
706 | | { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(DELAY_SLOT)|A(BR_INSN), { { { (1<<MACH_BASE), 0 } } } } |
707 | | }, |
708 | | /* brle $frsr1,$frsr2,$imm16o */ |
709 | | { |
710 | | MT_INSN_BRLE, "brle", "brle", 32, |
711 | | { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(DELAY_SLOT)|A(BR_INSN), { { { (1<<MACH_BASE), 0 } } } } |
712 | | }, |
713 | | /* breq $frsr1,$frsr2,$imm16o */ |
714 | | { |
715 | | MT_INSN_BREQ, "breq", "breq", 32, |
716 | | { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(DELAY_SLOT)|A(BR_INSN), { { { (1<<MACH_BASE), 0 } } } } |
717 | | }, |
718 | | /* brne $frsr1,$frsr2,$imm16o */ |
719 | | { |
720 | | MT_INSN_BRNE, "brne", "brne", 32, |
721 | | { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(DELAY_SLOT)|A(BR_INSN), { { { (1<<MACH_BASE), 0 } } } } |
722 | | }, |
723 | | /* jmp $imm16o */ |
724 | | { |
725 | | MT_INSN_JMP, "jmp", "jmp", 32, |
726 | | { 0|A(BR_INSN)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } |
727 | | }, |
728 | | /* jal $frdrrr,$frsr1 */ |
729 | | { |
730 | | MT_INSN_JAL, "jal", "jal", 32, |
731 | | { 0|A(JAL_HAZARD)|A(USES_FRSR1)|A(USES_FRDR)|A(BR_INSN)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } |
732 | | }, |
733 | | /* dbnz $frsr1,$imm16o */ |
734 | | { |
735 | | MT_INSN_DBNZ, "dbnz", "dbnz", 32, |
736 | | { 0|A(USES_FRSR1)|A(DELAY_SLOT)|A(BR_INSN), { { { (1<<MACH_MS1_003)|(1<<MACH_MS2), 0 } } } } |
737 | | }, |
738 | | /* ei */ |
739 | | { |
740 | | MT_INSN_EI, "ei", "ei", 32, |
741 | | { 0, { { { (1<<MACH_BASE), 0 } } } } |
742 | | }, |
743 | | /* di */ |
744 | | { |
745 | | MT_INSN_DI, "di", "di", 32, |
746 | | { 0, { { { (1<<MACH_BASE), 0 } } } } |
747 | | }, |
748 | | /* si $frdrrr */ |
749 | | { |
750 | | MT_INSN_SI, "si", "si", 32, |
751 | | { 0|A(USES_FRDR)|A(BR_INSN)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } |
752 | | }, |
753 | | /* reti $frsr1 */ |
754 | | { |
755 | | MT_INSN_RETI, "reti", "reti", 32, |
756 | | { 0|A(JAL_HAZARD)|A(USES_FRSR1)|A(BR_INSN)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } |
757 | | }, |
758 | | /* ldw $frdr,$frsr1,#$imm16 */ |
759 | | { |
760 | | MT_INSN_LDW, "ldw", "ldw", 32, |
761 | | { 0|A(USES_FRSR1)|A(USES_FRDR)|A(MEMORY_ACCESS)|A(LOAD_DELAY), { { { (1<<MACH_BASE), 0 } } } } |
762 | | }, |
763 | | /* stw $frsr2,$frsr1,#$imm16 */ |
764 | | { |
765 | | MT_INSN_STW, "stw", "stw", 32, |
766 | | { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(MEMORY_ACCESS), { { { (1<<MACH_BASE), 0 } } } } |
767 | | }, |
768 | | /* break */ |
769 | | { |
770 | | MT_INSN_BREAK, "break", "break", 32, |
771 | | { 0, { { { (1<<MACH_BASE), 0 } } } } |
772 | | }, |
773 | | /* iflush */ |
774 | | { |
775 | | MT_INSN_IFLUSH, "iflush", "iflush", 32, |
776 | | { 0, { { { (1<<MACH_MS1_003)|(1<<MACH_MS2), 0 } } } } |
777 | | }, |
778 | | /* ldctxt $frsr1,$frsr2,#$rc,#$rcnum,#$contnum */ |
779 | | { |
780 | | MT_INSN_LDCTXT, "ldctxt", "ldctxt", 32, |
781 | | { 0, { { { (1<<MACH_MS1), 0 } } } } |
782 | | }, |
783 | | /* ldfb $frsr1,$frsr2,#$imm16z */ |
784 | | { |
785 | | MT_INSN_LDFB, "ldfb", "ldfb", 32, |
786 | | { 0, { { { (1<<MACH_MS1), 0 } } } } |
787 | | }, |
788 | | /* stfb $frsr1,$frsr2,#$imm16z */ |
789 | | { |
790 | | MT_INSN_STFB, "stfb", "stfb", 32, |
791 | | { 0, { { { (1<<MACH_MS1), 0 } } } } |
792 | | }, |
793 | | /* fbcb $frsr1,#$rbbc,#$ball,#$brc,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp */ |
794 | | { |
795 | | MT_INSN_FBCB, "fbcb", "fbcb", 32, |
796 | | { 0, { { { (1<<MACH_MS1)|(1<<MACH_MS1_003), 0 } } } } |
797 | | }, |
798 | | /* mfbcb $frsr1,#$rbbc,$frsr2,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp */ |
799 | | { |
800 | | MT_INSN_MFBCB, "mfbcb", "mfbcb", 32, |
801 | | { 0, { { { (1<<MACH_BASE), 0 } } } } |
802 | | }, |
803 | | /* fbcci $frsr1,#$rbbc,#$ball,#$brc,#$fbdisp,#$cell,#$dup,#$ctxdisp */ |
804 | | { |
805 | | MT_INSN_FBCCI, "fbcci", "fbcci", 32, |
806 | | { 0, { { { (1<<MACH_BASE), 0 } } } } |
807 | | }, |
808 | | /* fbrci $frsr1,#$rbbc,#$ball,#$brc,#$fbdisp,#$cell,#$dup,#$ctxdisp */ |
809 | | { |
810 | | MT_INSN_FBRCI, "fbrci", "fbrci", 32, |
811 | | { 0, { { { (1<<MACH_BASE), 0 } } } } |
812 | | }, |
813 | | /* fbcri $frsr1,#$rbbc,#$ball,#$brc,#$fbdisp,#$cell,#$dup,#$ctxdisp */ |
814 | | { |
815 | | MT_INSN_FBCRI, "fbcri", "fbcri", 32, |
816 | | { 0, { { { (1<<MACH_BASE), 0 } } } } |
817 | | }, |
818 | | /* fbrri $frsr1,#$rbbc,#$ball,#$brc,#$fbdisp,#$cell,#$dup,#$ctxdisp */ |
819 | | { |
820 | | MT_INSN_FBRRI, "fbrri", "fbrri", 32, |
821 | | { 0, { { { (1<<MACH_BASE), 0 } } } } |
822 | | }, |
823 | | /* mfbcci $frsr1,#$rbbc,$frsr2,#$fbdisp,#$cell,#$dup,#$ctxdisp */ |
824 | | { |
825 | | MT_INSN_MFBCCI, "mfbcci", "mfbcci", 32, |
826 | | { 0, { { { (1<<MACH_BASE), 0 } } } } |
827 | | }, |
828 | | /* mfbrci $frsr1,#$rbbc,$frsr2,#$fbdisp,#$cell,#$dup,#$ctxdisp */ |
829 | | { |
830 | | MT_INSN_MFBRCI, "mfbrci", "mfbrci", 32, |
831 | | { 0, { { { (1<<MACH_BASE), 0 } } } } |
832 | | }, |
833 | | /* mfbcri $frsr1,#$rbbc,$frsr2,#$fbdisp,#$cell,#$dup,#$ctxdisp */ |
834 | | { |
835 | | MT_INSN_MFBCRI, "mfbcri", "mfbcri", 32, |
836 | | { 0, { { { (1<<MACH_BASE), 0 } } } } |
837 | | }, |
838 | | /* mfbrri $frsr1,#$rbbc,$frsr2,#$fbdisp,#$cell,#$dup,#$ctxdisp */ |
839 | | { |
840 | | MT_INSN_MFBRRI, "mfbrri", "mfbrri", 32, |
841 | | { 0, { { { (1<<MACH_BASE), 0 } } } } |
842 | | }, |
843 | | /* fbcbdr $frsr1,#$rbbc,$frsr2,#$ball2,#$brc2,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp */ |
844 | | { |
845 | | MT_INSN_FBCBDR, "fbcbdr", "fbcbdr", 32, |
846 | | { 0, { { { (1<<MACH_BASE), 0 } } } } |
847 | | }, |
848 | | /* rcfbcb #$rbbc,#$type,#$ball,#$brc,#$rownum,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp */ |
849 | | { |
850 | | MT_INSN_RCFBCB, "rcfbcb", "rcfbcb", 32, |
851 | | { 0, { { { (1<<MACH_BASE), 0 } } } } |
852 | | }, |
853 | | /* mrcfbcb $frsr2,#$rbbc,#$type,#$rownum,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp */ |
854 | | { |
855 | | MT_INSN_MRCFBCB, "mrcfbcb", "mrcfbcb", 32, |
856 | | { 0, { { { (1<<MACH_BASE), 0 } } } } |
857 | | }, |
858 | | /* cbcast #$mask,#$rc2,#$ctxdisp */ |
859 | | { |
860 | | MT_INSN_CBCAST, "cbcast", "cbcast", 32, |
861 | | { 0, { { { (1<<MACH_BASE), 0 } } } } |
862 | | }, |
863 | | /* dupcbcast #$mask,#$cell,#$rc2,#$ctxdisp */ |
864 | | { |
865 | | MT_INSN_DUPCBCAST, "dupcbcast", "dupcbcast", 32, |
866 | | { 0, { { { (1<<MACH_BASE), 0 } } } } |
867 | | }, |
868 | | /* wfbi #$bankaddr,#$rownum1,#$cell,#$dup,#$ctxdisp */ |
869 | | { |
870 | | MT_INSN_WFBI, "wfbi", "wfbi", 32, |
871 | | { 0, { { { (1<<MACH_BASE), 0 } } } } |
872 | | }, |
873 | | /* wfb $frsr1,$frsr2,#$fbdisp,#$rownum2,#$ctxdisp */ |
874 | | { |
875 | | MT_INSN_WFB, "wfb", "wfb", 32, |
876 | | { 0, { { { (1<<MACH_BASE), 0 } } } } |
877 | | }, |
878 | | /* rcrisc $frdrrr,#$rbbc,$frsr1,#$colnum,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp */ |
879 | | { |
880 | | MT_INSN_RCRISC, "rcrisc", "rcrisc", 32, |
881 | | { 0, { { { (1<<MACH_BASE), 0 } } } } |
882 | | }, |
883 | | /* fbcbinc $frsr1,#$rbbc,#$incamt,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp */ |
884 | | { |
885 | | MT_INSN_FBCBINC, "fbcbinc", "fbcbinc", 32, |
886 | | { 0, { { { (1<<MACH_BASE), 0 } } } } |
887 | | }, |
888 | | /* rcxmode $frsr2,#$rda,#$wr,#$xmode,#$mask1,#$fbdisp,#$rownum2,#$rc2,#$ctxdisp */ |
889 | | { |
890 | | MT_INSN_RCXMODE, "rcxmode", "rcxmode", 32, |
891 | | { 0, { { { (1<<MACH_BASE), 0 } } } } |
892 | | }, |
893 | | /* intlvr $frsr1,#$mode,$frsr2,#$id,#$size */ |
894 | | { |
895 | | MT_INSN_INTERLEAVER, "interleaver", "intlvr", 32, |
896 | | { 0, { { { (1<<MACH_BASE), 0 } } } } |
897 | | }, |
898 | | /* wfbinc #$rda,#$wr,#$fbincr,#$ball,#$colnum,#$length,#$rownum1,#$rownum2,#$dup,#$ctxdisp */ |
899 | | { |
900 | | MT_INSN_WFBINC, "wfbinc", "wfbinc", 32, |
901 | | { 0, { { { (1<<MACH_MS1_003)|(1<<MACH_MS2), 0 } } } } |
902 | | }, |
903 | | /* mwfbinc $frsr2,#$rda,#$wr,#$fbincr,#$length,#$rownum1,#$rownum2,#$dup,#$ctxdisp */ |
904 | | { |
905 | | MT_INSN_MWFBINC, "mwfbinc", "mwfbinc", 32, |
906 | | { 0, { { { (1<<MACH_MS1_003)|(1<<MACH_MS2), 0 } } } } |
907 | | }, |
908 | | /* wfbincr $frsr1,#$rda,#$wr,#$ball,#$colnum,#$length,#$rownum1,#$rownum2,#$dup,#$ctxdisp */ |
909 | | { |
910 | | MT_INSN_WFBINCR, "wfbincr", "wfbincr", 32, |
911 | | { 0, { { { (1<<MACH_MS1_003)|(1<<MACH_MS2), 0 } } } } |
912 | | }, |
913 | | /* mwfbincr $frsr1,$frsr2,#$rda,#$wr,#$length,#$rownum1,#$rownum2,#$dup,#$ctxdisp */ |
914 | | { |
915 | | MT_INSN_MWFBINCR, "mwfbincr", "mwfbincr", 32, |
916 | | { 0, { { { (1<<MACH_MS1_003)|(1<<MACH_MS2), 0 } } } } |
917 | | }, |
918 | | /* fbcbincs #$perm,#$a23,#$cr,#$cbs,#$incr,#$ccb,#$cdb,#$rownum2,#$dup,#$ctxdisp */ |
919 | | { |
920 | | MT_INSN_FBCBINCS, "fbcbincs", "fbcbincs", 32, |
921 | | { 0, { { { (1<<MACH_MS1_003)|(1<<MACH_MS2), 0 } } } } |
922 | | }, |
923 | | /* mfbcbincs $frsr1,#$perm,#$cbs,#$incr,#$ccb,#$cdb,#$rownum2,#$dup,#$ctxdisp */ |
924 | | { |
925 | | MT_INSN_MFBCBINCS, "mfbcbincs", "mfbcbincs", 32, |
926 | | { 0, { { { (1<<MACH_MS1_003)|(1<<MACH_MS2), 0 } } } } |
927 | | }, |
928 | | /* fbcbincrs $frsr1,#$perm,#$ball,#$colnum,#$cbx,#$ccb,#$cdb,#$rownum2,#$dup,#$ctxdisp */ |
929 | | { |
930 | | MT_INSN_FBCBINCRS, "fbcbincrs", "fbcbincrs", 32, |
931 | | { 0, { { { (1<<MACH_MS1_003)|(1<<MACH_MS2), 0 } } } } |
932 | | }, |
933 | | /* mfbcbincrs $frsr1,$frsr2,#$perm,#$cbx,#$ccb,#$cdb,#$rownum2,#$dup,#$ctxdisp */ |
934 | | { |
935 | | MT_INSN_MFBCBINCRS, "mfbcbincrs", "mfbcbincrs", 32, |
936 | | { 0, { { { (1<<MACH_MS1_003)|(1<<MACH_MS2), 0 } } } } |
937 | | }, |
938 | | /* loop $frsr1,$loopsize */ |
939 | | { |
940 | | MT_INSN_LOOP, "loop", "loop", 32, |
941 | | { 0|A(USES_FRSR1)|A(DELAY_SLOT), { { { (1<<MACH_MS2), 0 } } } } |
942 | | }, |
943 | | /* loopi #$imm16l,$loopsize */ |
944 | | { |
945 | | MT_INSN_LOOPI, "loopi", "loopi", 32, |
946 | | { 0|A(DELAY_SLOT), { { { (1<<MACH_MS2), 0 } } } } |
947 | | }, |
948 | | /* dfbc #$cb1sel,#$cb2sel,#$cb1incr,#$cb2incr,#$rc3,#$rc2,#$ctxdisp */ |
949 | | { |
950 | | MT_INSN_DFBC, "dfbc", "dfbc", 32, |
951 | | { 0, { { { (1<<MACH_MS2), 0 } } } } |
952 | | }, |
953 | | /* dwfb #$cb1sel,#$cb2sel,#$cb1incr,#$cb2incr,#$rc2,#$ctxdisp */ |
954 | | { |
955 | | MT_INSN_DWFB, "dwfb", "dwfb", 32, |
956 | | { 0, { { { (1<<MACH_MS2), 0 } } } } |
957 | | }, |
958 | | /* fbwfb #$cb1sel,#$cb2sel,#$cb1incr,#$cb2incr,#$rc3,#$rc2,#$ctxdisp */ |
959 | | { |
960 | | MT_INSN_FBWFB, "fbwfb", "fbwfb", 32, |
961 | | { 0, { { { (1<<MACH_MS2), 0 } } } } |
962 | | }, |
963 | | /* dfbr #$cb1sel,#$cb2sel,$frsr2,#$length,#$rownum1,#$rownum2,#$rc2,#$ctxdisp */ |
964 | | { |
965 | | MT_INSN_DFBR, "dfbr", "dfbr", 32, |
966 | | { 0|A(USES_FRSR2), { { { (1<<MACH_MS2), 0 } } } } |
967 | | }, |
968 | | }; |
969 | | |
970 | | #undef OP |
971 | | #undef A |
972 | | |
973 | | /* Initialize anything needed to be done once, before any cpu_open call. */ |
974 | | |
975 | | static void |
976 | | init_tables (void) |
977 | 2 | { |
978 | 2 | } |
979 | | |
980 | | #ifndef opcodes_error_handler |
981 | | #define opcodes_error_handler(...) \ |
982 | | fprintf (stderr, __VA_ARGS__); fputc ('\n', stderr) |
983 | | #endif |
984 | | |
985 | | static const CGEN_MACH * lookup_mach_via_bfd_name (const CGEN_MACH *, const char *); |
986 | | static void build_hw_table (CGEN_CPU_TABLE *); |
987 | | static void build_ifield_table (CGEN_CPU_TABLE *); |
988 | | static void build_operand_table (CGEN_CPU_TABLE *); |
989 | | static void build_insn_table (CGEN_CPU_TABLE *); |
990 | | static void mt_cgen_rebuild_tables (CGEN_CPU_TABLE *); |
991 | | |
992 | | /* Subroutine of mt_cgen_cpu_open to look up a mach via its bfd name. */ |
993 | | |
994 | | static const CGEN_MACH * |
995 | | lookup_mach_via_bfd_name (const CGEN_MACH *table, const char *name) |
996 | 5 | { |
997 | 9 | while (table->name) |
998 | 9 | { |
999 | 9 | if (strcmp (name, table->bfd_name) == 0) |
1000 | 5 | return table; |
1001 | 4 | ++table; |
1002 | 4 | } |
1003 | 0 | return NULL; |
1004 | 5 | } |
1005 | | |
1006 | | /* Subroutine of mt_cgen_cpu_open to build the hardware table. */ |
1007 | | |
1008 | | static void |
1009 | | build_hw_table (CGEN_CPU_TABLE *cd) |
1010 | 5 | { |
1011 | 5 | int i; |
1012 | 5 | int machs = cd->machs; |
1013 | 5 | const CGEN_HW_ENTRY *init = & mt_cgen_hw_table[0]; |
1014 | | /* MAX_HW is only an upper bound on the number of selected entries. |
1015 | | However each entry is indexed by it's enum so there can be holes in |
1016 | | the table. */ |
1017 | 5 | const CGEN_HW_ENTRY **selected = |
1018 | 5 | (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *)); |
1019 | | |
1020 | 5 | cd->hw_table.init_entries = init; |
1021 | 5 | cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY); |
1022 | 5 | memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *)); |
1023 | | /* ??? For now we just use machs to determine which ones we want. */ |
1024 | 40 | for (i = 0; init[i].name != NULL; ++i) |
1025 | 35 | if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH) |
1026 | 35 | & machs) |
1027 | 35 | selected[init[i].type] = &init[i]; |
1028 | 5 | cd->hw_table.entries = selected; |
1029 | 5 | cd->hw_table.num_entries = MAX_HW; |
1030 | 5 | } |
1031 | | |
1032 | | /* Subroutine of mt_cgen_cpu_open to build the hardware table. */ |
1033 | | |
1034 | | static void |
1035 | | build_ifield_table (CGEN_CPU_TABLE *cd) |
1036 | 5 | { |
1037 | 5 | cd->ifld_table = & mt_cgen_ifld_table[0]; |
1038 | 5 | } |
1039 | | |
1040 | | /* Subroutine of mt_cgen_cpu_open to build the hardware table. */ |
1041 | | |
1042 | | static void |
1043 | | build_operand_table (CGEN_CPU_TABLE *cd) |
1044 | 5 | { |
1045 | 5 | int i; |
1046 | 5 | int machs = cd->machs; |
1047 | 5 | const CGEN_OPERAND *init = & mt_cgen_operand_table[0]; |
1048 | | /* MAX_OPERANDS is only an upper bound on the number of selected entries. |
1049 | | However each entry is indexed by it's enum so there can be holes in |
1050 | | the table. */ |
1051 | 5 | const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected)); |
1052 | | |
1053 | 5 | cd->operand_table.init_entries = init; |
1054 | 5 | cd->operand_table.entry_size = sizeof (CGEN_OPERAND); |
1055 | 5 | memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *)); |
1056 | | /* ??? For now we just use mach to determine which ones we want. */ |
1057 | 280 | for (i = 0; init[i].name != NULL; ++i) |
1058 | 275 | if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH) |
1059 | 275 | & machs) |
1060 | 247 | selected[init[i].type] = &init[i]; |
1061 | 5 | cd->operand_table.entries = selected; |
1062 | 5 | cd->operand_table.num_entries = MAX_OPERANDS; |
1063 | 5 | } |
1064 | | |
1065 | | /* Subroutine of mt_cgen_cpu_open to build the hardware table. |
1066 | | ??? This could leave out insns not supported by the specified mach/isa, |
1067 | | but that would cause errors like "foo only supported by bar" to become |
1068 | | "unknown insn", so for now we include all insns and require the app to |
1069 | | do the checking later. |
1070 | | ??? On the other hand, parsing of such insns may require their hardware or |
1071 | | operand elements to be in the table [which they mightn't be]. */ |
1072 | | |
1073 | | static void |
1074 | | build_insn_table (CGEN_CPU_TABLE *cd) |
1075 | 5 | { |
1076 | 5 | int i; |
1077 | 5 | const CGEN_IBASE *ib = & mt_cgen_insn_table[0]; |
1078 | 5 | CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN)); |
1079 | | |
1080 | 5 | memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN)); |
1081 | 425 | for (i = 0; i < MAX_INSNS; ++i) |
1082 | 420 | insns[i].base = &ib[i]; |
1083 | 5 | cd->insn_table.init_entries = insns; |
1084 | 5 | cd->insn_table.entry_size = sizeof (CGEN_IBASE); |
1085 | 5 | cd->insn_table.num_init_entries = MAX_INSNS; |
1086 | 5 | } |
1087 | | |
1088 | | /* Subroutine of mt_cgen_cpu_open to rebuild the tables. */ |
1089 | | |
1090 | | static void |
1091 | | mt_cgen_rebuild_tables (CGEN_CPU_TABLE *cd) |
1092 | 5 | { |
1093 | 5 | int i; |
1094 | 5 | CGEN_BITSET *isas = cd->isas; |
1095 | 5 | unsigned int machs = cd->machs; |
1096 | | |
1097 | 5 | cd->int_insn_p = CGEN_INT_INSN_P; |
1098 | | |
1099 | | /* Data derived from the isa spec. */ |
1100 | 20 | #define UNSET (CGEN_SIZE_UNKNOWN + 1) |
1101 | 5 | cd->default_insn_bitsize = UNSET; |
1102 | 5 | cd->base_insn_bitsize = UNSET; |
1103 | 5 | cd->min_insn_bitsize = 65535; /* Some ridiculously big number. */ |
1104 | 5 | cd->max_insn_bitsize = 0; |
1105 | 10 | for (i = 0; i < MAX_ISAS; ++i) |
1106 | 5 | if (cgen_bitset_contains (isas, i)) |
1107 | 5 | { |
1108 | 5 | const CGEN_ISA *isa = & mt_cgen_isa_table[i]; |
1109 | | |
1110 | | /* Default insn sizes of all selected isas must be |
1111 | | equal or we set the result to 0, meaning "unknown". */ |
1112 | 5 | if (cd->default_insn_bitsize == UNSET) |
1113 | 5 | cd->default_insn_bitsize = isa->default_insn_bitsize; |
1114 | 0 | else if (isa->default_insn_bitsize == cd->default_insn_bitsize) |
1115 | 0 | ; /* This is ok. */ |
1116 | 0 | else |
1117 | 0 | cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN; |
1118 | | |
1119 | | /* Base insn sizes of all selected isas must be equal |
1120 | | or we set the result to 0, meaning "unknown". */ |
1121 | 5 | if (cd->base_insn_bitsize == UNSET) |
1122 | 5 | cd->base_insn_bitsize = isa->base_insn_bitsize; |
1123 | 0 | else if (isa->base_insn_bitsize == cd->base_insn_bitsize) |
1124 | 0 | ; /* This is ok. */ |
1125 | 0 | else |
1126 | 0 | cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN; |
1127 | | |
1128 | | /* Set min,max insn sizes. */ |
1129 | 5 | if (isa->min_insn_bitsize < cd->min_insn_bitsize) |
1130 | 5 | cd->min_insn_bitsize = isa->min_insn_bitsize; |
1131 | 5 | if (isa->max_insn_bitsize > cd->max_insn_bitsize) |
1132 | 5 | cd->max_insn_bitsize = isa->max_insn_bitsize; |
1133 | 5 | } |
1134 | | |
1135 | | /* Data derived from the mach spec. */ |
1136 | 25 | for (i = 0; i < MAX_MACHS; ++i) |
1137 | 20 | if (((1 << i) & machs) != 0) |
1138 | 10 | { |
1139 | 10 | const CGEN_MACH *mach = & mt_cgen_mach_table[i]; |
1140 | | |
1141 | 10 | if (mach->insn_chunk_bitsize != 0) |
1142 | 0 | { |
1143 | 0 | if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize) |
1144 | 0 | { |
1145 | 0 | opcodes_error_handler |
1146 | 0 | (/* xgettext:c-format */ |
1147 | 0 | _("internal error: mt_cgen_rebuild_tables: " |
1148 | 0 | "conflicting insn-chunk-bitsize values: `%d' vs. `%d'"), |
1149 | 0 | cd->insn_chunk_bitsize, mach->insn_chunk_bitsize); |
1150 | 0 | abort (); |
1151 | 0 | } |
1152 | | |
1153 | 0 | cd->insn_chunk_bitsize = mach->insn_chunk_bitsize; |
1154 | 0 | } |
1155 | 10 | } |
1156 | | |
1157 | | /* Determine which hw elements are used by MACH. */ |
1158 | 5 | build_hw_table (cd); |
1159 | | |
1160 | | /* Build the ifield table. */ |
1161 | 5 | build_ifield_table (cd); |
1162 | | |
1163 | | /* Determine which operands are used by MACH/ISA. */ |
1164 | 5 | build_operand_table (cd); |
1165 | | |
1166 | | /* Build the instruction table. */ |
1167 | 5 | build_insn_table (cd); |
1168 | 5 | } |
1169 | | |
1170 | | /* Initialize a cpu table and return a descriptor. |
1171 | | It's much like opening a file, and must be the first function called. |
1172 | | The arguments are a set of (type/value) pairs, terminated with |
1173 | | CGEN_CPU_OPEN_END. |
1174 | | |
1175 | | Currently supported values: |
1176 | | CGEN_CPU_OPEN_ISAS: bitmap of values in enum isa_attr |
1177 | | CGEN_CPU_OPEN_MACHS: bitmap of values in enum mach_attr |
1178 | | CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name |
1179 | | CGEN_CPU_OPEN_ENDIAN: specify endian choice |
1180 | | CGEN_CPU_OPEN_INSN_ENDIAN: specify instruction endian choice |
1181 | | CGEN_CPU_OPEN_END: terminates arguments |
1182 | | |
1183 | | ??? Simultaneous multiple isas might not make sense, but it's not (yet) |
1184 | | precluded. */ |
1185 | | |
1186 | | CGEN_CPU_DESC |
1187 | | mt_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) |
1188 | 5 | { |
1189 | 5 | CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE)); |
1190 | 5 | static int init_p; |
1191 | 5 | CGEN_BITSET *isas = 0; /* 0 = "unspecified" */ |
1192 | 5 | unsigned int machs = 0; /* 0 = "unspecified" */ |
1193 | 5 | enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN; |
1194 | 5 | enum cgen_endian insn_endian = CGEN_ENDIAN_UNKNOWN; |
1195 | 5 | va_list ap; |
1196 | | |
1197 | 5 | if (! init_p) |
1198 | 2 | { |
1199 | 2 | init_tables (); |
1200 | 2 | init_p = 1; |
1201 | 2 | } |
1202 | | |
1203 | 5 | memset (cd, 0, sizeof (*cd)); |
1204 | | |
1205 | 5 | va_start (ap, arg_type); |
1206 | 25 | while (arg_type != CGEN_CPU_OPEN_END) |
1207 | 20 | { |
1208 | 20 | switch (arg_type) |
1209 | 20 | { |
1210 | 5 | case CGEN_CPU_OPEN_ISAS : |
1211 | 5 | isas = va_arg (ap, CGEN_BITSET *); |
1212 | 5 | break; |
1213 | 0 | case CGEN_CPU_OPEN_MACHS : |
1214 | 0 | machs = va_arg (ap, unsigned int); |
1215 | 0 | break; |
1216 | 5 | case CGEN_CPU_OPEN_BFDMACH : |
1217 | 5 | { |
1218 | 5 | const char *name = va_arg (ap, const char *); |
1219 | 5 | const CGEN_MACH *mach = |
1220 | 5 | lookup_mach_via_bfd_name (mt_cgen_mach_table, name); |
1221 | | |
1222 | 5 | if (mach != NULL) |
1223 | 5 | machs |= 1 << mach->num; |
1224 | 5 | break; |
1225 | 0 | } |
1226 | 5 | case CGEN_CPU_OPEN_ENDIAN : |
1227 | 5 | endian = va_arg (ap, enum cgen_endian); |
1228 | 5 | break; |
1229 | 5 | case CGEN_CPU_OPEN_INSN_ENDIAN : |
1230 | 5 | insn_endian = va_arg (ap, enum cgen_endian); |
1231 | 5 | break; |
1232 | 0 | default : |
1233 | 0 | opcodes_error_handler |
1234 | 0 | (/* xgettext:c-format */ |
1235 | 0 | _("internal error: mt_cgen_cpu_open: " |
1236 | 0 | "unsupported argument `%d'"), |
1237 | 0 | arg_type); |
1238 | 0 | abort (); /* ??? return NULL? */ |
1239 | 20 | } |
1240 | 20 | arg_type = va_arg (ap, enum cgen_cpu_open_arg); |
1241 | 20 | } |
1242 | 5 | va_end (ap); |
1243 | | |
1244 | | /* Mach unspecified means "all". */ |
1245 | 5 | if (machs == 0) |
1246 | 0 | machs = (1 << MAX_MACHS) - 1; |
1247 | | /* Base mach is always selected. */ |
1248 | 5 | machs |= 1; |
1249 | 5 | if (endian == CGEN_ENDIAN_UNKNOWN) |
1250 | 0 | { |
1251 | | /* ??? If target has only one, could have a default. */ |
1252 | 0 | opcodes_error_handler |
1253 | 0 | (/* xgettext:c-format */ |
1254 | 0 | _("internal error: mt_cgen_cpu_open: no endianness specified")); |
1255 | 0 | abort (); |
1256 | 0 | } |
1257 | | |
1258 | 5 | cd->isas = cgen_bitset_copy (isas); |
1259 | 5 | cd->machs = machs; |
1260 | 5 | cd->endian = endian; |
1261 | 5 | cd->insn_endian |
1262 | 5 | = (insn_endian == CGEN_ENDIAN_UNKNOWN ? endian : insn_endian); |
1263 | | |
1264 | | /* Table (re)builder. */ |
1265 | 5 | cd->rebuild_tables = mt_cgen_rebuild_tables; |
1266 | 5 | mt_cgen_rebuild_tables (cd); |
1267 | | |
1268 | | /* Default to not allowing signed overflow. */ |
1269 | 5 | cd->signed_overflow_ok_p = 0; |
1270 | | |
1271 | 5 | return (CGEN_CPU_DESC) cd; |
1272 | 5 | } |
1273 | | |
1274 | | /* Cover fn to mt_cgen_cpu_open to handle the simple case of 1 isa, 1 mach. |
1275 | | MACH_NAME is the bfd name of the mach. */ |
1276 | | |
1277 | | CGEN_CPU_DESC |
1278 | | mt_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian) |
1279 | 0 | { |
1280 | 0 | return mt_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name, |
1281 | 0 | CGEN_CPU_OPEN_ENDIAN, endian, |
1282 | 0 | CGEN_CPU_OPEN_END); |
1283 | 0 | } |
1284 | | |
1285 | | /* Close a cpu table. |
1286 | | ??? This can live in a machine independent file, but there's currently |
1287 | | no place to put this file (there's no libcgen). libopcodes is the wrong |
1288 | | place as some simulator ports use this but they don't use libopcodes. */ |
1289 | | |
1290 | | void |
1291 | | mt_cgen_cpu_close (CGEN_CPU_DESC cd) |
1292 | 0 | { |
1293 | 0 | unsigned int i; |
1294 | 0 | const CGEN_INSN *insns; |
1295 | |
|
1296 | 0 | if (cd->macro_insn_table.init_entries) |
1297 | 0 | { |
1298 | 0 | insns = cd->macro_insn_table.init_entries; |
1299 | 0 | for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns) |
1300 | 0 | if (CGEN_INSN_RX ((insns))) |
1301 | 0 | regfree (CGEN_INSN_RX (insns)); |
1302 | 0 | } |
1303 | |
|
1304 | 0 | if (cd->insn_table.init_entries) |
1305 | 0 | { |
1306 | 0 | insns = cd->insn_table.init_entries; |
1307 | 0 | for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns) |
1308 | 0 | if (CGEN_INSN_RX (insns)) |
1309 | 0 | regfree (CGEN_INSN_RX (insns)); |
1310 | 0 | } |
1311 | |
|
1312 | 0 | free ((CGEN_INSN *) cd->macro_insn_table.init_entries); |
1313 | 0 | free ((CGEN_INSN *) cd->insn_table.init_entries); |
1314 | 0 | free ((CGEN_HW_ENTRY *) cd->hw_table.entries); |
1315 | 0 | free ((CGEN_HW_ENTRY *) cd->operand_table.entries); |
1316 | 0 | free (cd); |
1317 | 0 | } |
1318 | | |