/src/binutils-gdb/opcodes/s390-opc.c
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1 | | /* s390-opc.c -- S390 opcode list |
2 | | Copyright (C) 2000-2025 Free Software Foundation, Inc. |
3 | | Contributed by Martin Schwidefsky (schwidefsky@de.ibm.com). |
4 | | |
5 | | This file is part of the GNU opcodes library. |
6 | | |
7 | | This library is free software; you can redistribute it and/or modify |
8 | | it under the terms of the GNU General Public License as published by |
9 | | the Free Software Foundation; either version 3, or (at your option) |
10 | | any later version. |
11 | | |
12 | | It is distributed in the hope that it will be useful, but WITHOUT |
13 | | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY |
14 | | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public |
15 | | License for more details. |
16 | | |
17 | | You should have received a copy of the GNU General Public License |
18 | | along with this file; see the file COPYING. If not, write to the |
19 | | Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, |
20 | | MA 02110-1301, USA. */ |
21 | | |
22 | | #include <stdio.h> |
23 | | #include "ansidecl.h" |
24 | | #include "opcode/s390.h" |
25 | | |
26 | | /* This file holds the S390 opcode table. The opcode table |
27 | | includes almost all of the extended instruction mnemonics. This |
28 | | permits the disassembler to use them, and simplifies the assembler |
29 | | logic, at the cost of increasing the table size. The table is |
30 | | strictly constant data, so the compiler should be able to put it in |
31 | | the .text section. |
32 | | |
33 | | This file also holds the operand table. All knowledge about |
34 | | inserting operands into instructions and vice-versa is kept in this |
35 | | file. */ |
36 | | |
37 | | /* Build-time checks are preferrable over runtime ones. Use this construct |
38 | | in preference where possible. */ |
39 | | #ifndef static_assert |
40 | | #define static_assert(e) ((void)sizeof (struct { int _:1 - 2 * !(e); })) |
41 | | #endif |
42 | | |
43 | | #define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) |
44 | | |
45 | | /* The operands table. |
46 | | The fields are bits, shift, insert, extract, flags. */ |
47 | | |
48 | | const struct s390_operand s390_operands[] = |
49 | | { |
50 | | #define UNUSED 0 |
51 | | { 0, 0, 0 }, /* Indicates the end of the operand list */ |
52 | | |
53 | | /* General purpose register operands. */ |
54 | | |
55 | | #define R_8 (UNUSED + 1) /* GPR starting at position 8 */ |
56 | | { 4, 8, S390_OPERAND_GPR }, |
57 | | #define R_12 (R_8 + 1) /* GPR starting at position 12 */ |
58 | | { 4, 12, S390_OPERAND_GPR }, |
59 | | #define R_16 (R_12 + 1) /* GPR starting at position 16 */ |
60 | | { 4, 16, S390_OPERAND_GPR }, |
61 | | #define R_20 (R_16 + 1) /* GPR starting at position 20 */ |
62 | | { 4, 20, S390_OPERAND_GPR }, |
63 | | #define R_24 (R_20 + 1) /* GPR starting at position 24 */ |
64 | | { 4, 24, S390_OPERAND_GPR }, |
65 | | #define R_28 (R_24 + 1) /* GPR starting at position 28 */ |
66 | | { 4, 28, S390_OPERAND_GPR }, |
67 | | #define R_CP16_28 (R_28 + 1) /* GPR starting at position 28 */ |
68 | | { 4, 28, S390_OPERAND_GPR | S390_OPERAND_CP16 }, /* with a copy at pos 16 */ |
69 | | #define R_32 (R_CP16_28+1) /* GPR starting at position 32 */ |
70 | | { 4, 32, S390_OPERAND_GPR }, |
71 | | |
72 | | /* General purpose register pair operands. */ |
73 | | |
74 | | #define RE_8 (R_32 + 1) /* GPR starting at position 8 */ |
75 | | { 4, 8, S390_OPERAND_GPR | S390_OPERAND_REG_PAIR }, |
76 | | #define RE_12 (RE_8 + 1) /* GPR starting at position 12 */ |
77 | | { 4, 12, S390_OPERAND_GPR | S390_OPERAND_REG_PAIR }, |
78 | | #define RE_16 (RE_12 + 1) /* GPR starting at position 16 */ |
79 | | { 4, 16, S390_OPERAND_GPR | S390_OPERAND_REG_PAIR }, |
80 | | #define RE_20 (RE_16 + 1) /* GPR starting at position 20 */ |
81 | | { 4, 20, S390_OPERAND_GPR | S390_OPERAND_REG_PAIR }, |
82 | | #define RE_24 (RE_20 + 1) /* GPR starting at position 24 */ |
83 | | { 4, 24, S390_OPERAND_GPR | S390_OPERAND_REG_PAIR }, |
84 | | #define RE_28 (RE_24 + 1) /* GPR starting at position 28 */ |
85 | | { 4, 28, S390_OPERAND_GPR | S390_OPERAND_REG_PAIR }, |
86 | | #define RE_32 (RE_28 + 1) /* GPR starting at position 32 */ |
87 | | { 4, 32, S390_OPERAND_GPR | S390_OPERAND_REG_PAIR }, |
88 | | |
89 | | /* Floating point register operands. */ |
90 | | |
91 | | #define F_8 (RE_32 + 1) /* FPR starting at position 8 */ |
92 | | { 4, 8, S390_OPERAND_FPR }, |
93 | | #define F_12 (F_8 + 1) /* FPR starting at position 12 */ |
94 | | { 4, 12, S390_OPERAND_FPR }, |
95 | | #define F_16 (F_12 + 1) /* FPR starting at position 16 */ |
96 | | { 4, 16, S390_OPERAND_FPR }, |
97 | | #define F_24 (F_16 + 1) /* FPR starting at position 24 */ |
98 | | { 4, 24, S390_OPERAND_FPR }, |
99 | | #define F_28 (F_24 + 1) /* FPR starting at position 28 */ |
100 | | { 4, 28, S390_OPERAND_FPR }, |
101 | | #define F_32 (F_28 + 1) /* FPR starting at position 32 */ |
102 | | { 4, 32, S390_OPERAND_FPR }, |
103 | | |
104 | | /* Floating point register pair operands. */ |
105 | | |
106 | | #define FE_8 (F_32 + 1) /* FPR starting at position 8 */ |
107 | | { 4, 8, S390_OPERAND_FPR | S390_OPERAND_REG_PAIR }, |
108 | | #define FE_12 (FE_8 + 1) /* FPR starting at position 12 */ |
109 | | { 4, 12, S390_OPERAND_FPR | S390_OPERAND_REG_PAIR }, |
110 | | #define FE_16 (FE_12 + 1) /* FPR starting at position 16 */ |
111 | | { 4, 16, S390_OPERAND_FPR | S390_OPERAND_REG_PAIR }, |
112 | | #define FE_24 (FE_16 + 1) /* FPR starting at position 24 */ |
113 | | { 4, 24, S390_OPERAND_FPR | S390_OPERAND_REG_PAIR }, |
114 | | #define FE_28 (FE_24 + 1) /* FPR starting at position 28 */ |
115 | | { 4, 28, S390_OPERAND_FPR | S390_OPERAND_REG_PAIR }, |
116 | | #define FE_32 (FE_28 + 1) /* FPR starting at position 32 */ |
117 | | { 4, 32, S390_OPERAND_FPR | S390_OPERAND_REG_PAIR }, |
118 | | |
119 | | /* Vector register operands. */ |
120 | | |
121 | | /* For each of these operands and additional bit in the RXB operand is |
122 | | needed. */ |
123 | | |
124 | | #define V_8 (FE_32 + 1) /* Vector reg. starting at position 8 */ |
125 | | { 4, 8, S390_OPERAND_VR }, |
126 | | #define V_12 (V_8 + 1) /* Vector reg. starting at position 12 */ |
127 | | { 4, 12, S390_OPERAND_VR }, |
128 | | #define V_CP16_12 (V_12 + 1) /* Vector reg. starting at position 12 */ |
129 | | { 4, 12, S390_OPERAND_VR | S390_OPERAND_CP16 }, /* with a copy at pos 16 */ |
130 | | #define V_16 (V_CP16_12+1) /* Vector reg. starting at position 16 */ |
131 | | { 4, 16, S390_OPERAND_VR }, |
132 | | #define V_32 (V_16 + 1) /* Vector reg. starting at position 32 */ |
133 | | { 4, 32, S390_OPERAND_VR }, |
134 | | |
135 | | /* Access register operands. */ |
136 | | |
137 | | #define A_8 (V_32 + 1) /* Access reg. starting at position 8 */ |
138 | | { 4, 8, S390_OPERAND_AR }, |
139 | | #define A_12 (A_8 + 1) /* Access reg. starting at position 12 */ |
140 | | { 4, 12, S390_OPERAND_AR }, |
141 | | #define A_24 (A_12 + 1) /* Access reg. starting at position 24 */ |
142 | | { 4, 24, S390_OPERAND_AR }, |
143 | | #define A_28 (A_24 + 1) /* Access reg. starting at position 28 */ |
144 | | { 4, 28, S390_OPERAND_AR }, |
145 | | |
146 | | /* Control register operands. */ |
147 | | |
148 | | #define C_8 (A_28 + 1) /* Control reg. starting at position 8 */ |
149 | | { 4, 8, S390_OPERAND_CR }, |
150 | | #define C_12 (C_8 + 1) /* Control reg. starting at position 12 */ |
151 | | { 4, 12, S390_OPERAND_CR }, |
152 | | |
153 | | /* Base register operands. */ |
154 | | |
155 | | #define B_16 (C_12 + 1) /* Base register starting at position 16 */ |
156 | | { 4, 16, S390_OPERAND_BASE | S390_OPERAND_GPR }, |
157 | | #define B_32 (B_16 + 1) /* Base register starting at position 32 */ |
158 | | { 4, 32, S390_OPERAND_BASE | S390_OPERAND_GPR }, |
159 | | |
160 | | #define X_12 (B_32 + 1) /* Index register starting at position 12 */ |
161 | | { 4, 12, S390_OPERAND_INDEX | S390_OPERAND_GPR }, |
162 | | |
163 | | #define VX_12 (X_12+1) /* Vector index register starting at position 12 */ |
164 | | { 4, 12, S390_OPERAND_INDEX | S390_OPERAND_VR }, |
165 | | |
166 | | /* Address displacement operands. */ |
167 | | |
168 | | #define D_20 (VX_12 + 1) /* Displacement starting at position 20 */ |
169 | | { 12, 20, S390_OPERAND_DISP }, |
170 | | #define D_36 (D_20 + 1) /* Displacement starting at position 36 */ |
171 | | { 12, 36, S390_OPERAND_DISP }, |
172 | | #define D20_20 (D_36 + 1) /* 20 bit displacement starting at 20 */ |
173 | | { 20, 20, S390_OPERAND_DISP | S390_OPERAND_SIGNED }, |
174 | | |
175 | | /* Length operands. */ |
176 | | |
177 | | #define L4_8 (D20_20 + 1) /* 4 bit length starting at position 8 */ |
178 | | { 4, 8, S390_OPERAND_LENGTH }, |
179 | | #define L4_12 (L4_8 + 1) /* 4 bit length starting at position 12 */ |
180 | | { 4, 12, S390_OPERAND_LENGTH }, |
181 | | #define L8_8 (L4_12 + 1) /* 8 bit length starting at position 8 */ |
182 | | { 8, 8, S390_OPERAND_LENGTH }, |
183 | | |
184 | | /* Signed immediate operands. */ |
185 | | |
186 | | #define I8_8 (L8_8 + 1) /* 8 bit signed value starting at 8 */ |
187 | | { 8, 8, S390_OPERAND_SIGNED }, |
188 | | #define I8_32 (I8_8 + 1) /* 8 bit signed value starting at 32 */ |
189 | | { 8, 32, S390_OPERAND_SIGNED }, |
190 | | #define I12_12 (I8_32 + 1) /* 12 bit signed value starting at 12 */ |
191 | | { 12, 12, S390_OPERAND_SIGNED }, |
192 | | #define I16_16 (I12_12 + 1) /* 16 bit signed value starting at 16 */ |
193 | | { 16, 16, S390_OPERAND_SIGNED }, |
194 | | #define I16_32 (I16_16 + 1) /* 16 bit signed value starting at 32 */ |
195 | | { 16, 32, S390_OPERAND_SIGNED }, |
196 | | #define I24_24 (I16_32 + 1) /* 24 bit signed value starting at 24 */ |
197 | | { 24, 24, S390_OPERAND_SIGNED }, |
198 | | #define I32_16 (I24_24 + 1) /* 32 bit signed value starting at 16 */ |
199 | | { 32, 16, S390_OPERAND_SIGNED }, |
200 | | |
201 | | /* Unsigned immediate operands. */ |
202 | | |
203 | | #define U4_8 (I32_16 + 1) /* 4 bit unsigned value starting at 8 */ |
204 | | { 4, 8, 0 }, |
205 | | #define U4_12 (U4_8 + 1) /* 4 bit unsigned value starting at 12 */ |
206 | | { 4, 12, 0 }, |
207 | | #define U4_16 (U4_12 + 1) /* 4 bit unsigned value starting at 16 */ |
208 | | { 4, 16, 0 }, |
209 | | #define U4_20 (U4_16 + 1) /* 4 bit unsigned value starting at 20 */ |
210 | | { 4, 20, 0 }, |
211 | | #define U4_24 (U4_20 + 1) /* 4 bit unsigned value starting at 24 */ |
212 | | { 4, 24, 0 }, |
213 | | #define U4_28 (U4_24+1) /* 4 bit unsigned value starting at 28 */ |
214 | | { 4, 28, 0 }, |
215 | | #define U4_32 (U4_28+1) /* 4 bit unsigned value starting at 32 */ |
216 | | { 4, 32, 0 }, |
217 | | #define U4_36 (U4_32 + 1) /* 4 bit unsigned value starting at 36 */ |
218 | | { 4, 36, 0 }, |
219 | | #define U8_8 (U4_36 + 1) /* 8 bit unsigned value starting at 8 */ |
220 | | { 8, 8, 0 }, |
221 | | #define U8_16 (U8_8 + 1) /* 8 bit unsigned value starting at 16 */ |
222 | | { 8, 16, 0 }, |
223 | | #define U8_24 (U8_16 + 1) /* 8 bit unsigned value starting at 24 */ |
224 | | { 8, 24, 0 }, |
225 | | #define U8_28 (U8_24 + 1) /* 8 bit unsigned value starting at 28 */ |
226 | | { 8, 28, 0 }, |
227 | | #define U8_32 (U8_28 + 1) /* 8 bit unsigned value starting at 32 */ |
228 | | { 8, 32, 0 }, |
229 | | #define U12_16 (U8_32 + 1) /* 12 bit unsigned value starting at 16 */ |
230 | | { 12, 16, 0 }, |
231 | | #define U16_16 (U12_16 + 1) /* 16 bit unsigned value starting at 16 */ |
232 | | { 16, 16, 0 }, |
233 | | #define U16_20 (U16_16 + 1) /* 16 bit unsigned value starting at 20 */ |
234 | | { 16, 20, 0 }, |
235 | | #define U16_32 (U16_20 + 1) /* 16 bit unsigned value starting at 32 */ |
236 | | { 16, 32, 0 }, |
237 | | #define U32_16 (U16_32 + 1) /* 32 bit unsigned value starting at 16 */ |
238 | | { 32, 16, 0 }, |
239 | | |
240 | | /* PC-relative address operands. */ |
241 | | |
242 | | #define J12_12 (U32_16 + 1) /* 12 bit PC relative offset at 12 */ |
243 | | { 12, 12, S390_OPERAND_PCREL }, |
244 | | #define J16_16 (J12_12 + 1) /* 16 bit PC relative offset at 16 */ |
245 | | { 16, 16, S390_OPERAND_PCREL }, |
246 | | #define J16_32 (J16_16 + 1) /* 16 bit PC relative offset at 32 */ |
247 | | { 16, 32, S390_OPERAND_PCREL }, |
248 | | #define J24_24 (J16_32 + 1) /* 24 bit PC relative offset at 24 */ |
249 | | { 24, 24, S390_OPERAND_PCREL }, |
250 | | #define J32_16 (J24_24 + 1) /* 32 bit PC relative offset at 16 */ |
251 | | { 32, 16, S390_OPERAND_PCREL }, |
252 | | |
253 | | }; |
254 | | |
255 | | static inline void ATTRIBUTE_UNUSED |
256 | | unused_s390_operands_static_asserts (void) |
257 | 0 | { |
258 | 0 | static_assert (ARRAY_SIZE (s390_operands) - 1 == J32_16); |
259 | 0 | } |
260 | | |
261 | | /* Macros used to form opcodes. */ |
262 | | |
263 | | /* 8/16/48 bit opcodes. */ |
264 | | #define OP8(x) { x, 0x00, 0x00, 0x00, 0x00, 0x00 } |
265 | | #define OP16(x) { x >> 8, x & 255, 0x00, 0x00, 0x00, 0x00 } |
266 | | #define OP32(x) { x >> 24, (x >> 16) & 255, (x >> 8) & 255, x & 255, \ |
267 | | 0x00, 0x00 } |
268 | | #define OP48(x) { x >> 40, (x >> 32) & 255, (x >> 24) & 255, \ |
269 | | (x >> 16) & 255, (x >> 8) & 255, x & 255} |
270 | | |
271 | | /* The new format of the INSTR_x_y and MASK_x_y defines is based |
272 | | on the following rules: |
273 | | 1) the middle part of the definition (x in INSTR_x_y) is the official |
274 | | names of the instruction format that you can find in the principals |
275 | | of operation. |
276 | | 2) the last part of the definition (y in INSTR_x_y) gives you an idea |
277 | | which operands the binary represenation of the instruction has. |
278 | | The meanings of the letters in y are: |
279 | | a - access register |
280 | | c - control register |
281 | | d - displacement, 12 bit |
282 | | f - floating pointer register |
283 | | fe - fpr extended operand, a valid floating pointer register pair |
284 | | i - signed integer, 4, 8, 16 or 32 bit |
285 | | l - length, 4 or 8 bit |
286 | | p - pc relative |
287 | | r - general purpose register |
288 | | re - gpr extended operand, a valid general purpose register pair |
289 | | u - unsigned integer, 4, 8, 16 or 32 bit |
290 | | m - mode field, 4 bit |
291 | | 0 - operand skipped. |
292 | | The order of the letters reflects the layout of the format in |
293 | | storage and not the order of the paramaters of the instructions. |
294 | | The use of the letters is not a 100% match with the PoP but it is |
295 | | quite close. |
296 | | |
297 | | For example the instruction "mvo" is defined in the PoP as follows: |
298 | | |
299 | | MVO D1(L1,B1),D2(L2,B2) [SS] |
300 | | |
301 | | -------------------------------------- |
302 | | | 'F1' | L1 | L2 | B1 | D1 | B2 | D2 | |
303 | | -------------------------------------- |
304 | | 0 8 12 16 20 32 36 |
305 | | |
306 | | The instruction format is: INSTR_SS_LLRDRD / MASK_SS_LLRDRD. */ |
307 | | |
308 | | #define INSTR_E 2, { 0,0,0,0,0,0 } /* e.g. pr */ |
309 | | #define INSTR_IE_UU 4, { U4_24,U4_28,0,0,0,0 } /* e.g. niai */ |
310 | | #define INSTR_MII_UPP 6, { U4_8,J12_12,J24_24 } /* e.g. bprp */ |
311 | | #define INSTR_RIE_RRP 6, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxhg */ |
312 | | #define INSTR_RIE_RRPU 6, { R_8,R_12,U4_32,J16_16,0,0 } /* e.g. crj */ |
313 | | #define INSTR_RIE_RRP0 6, { R_8,R_12,J16_16,0,0,0 } /* e.g. cgrjne */ |
314 | | #define INSTR_RIE_RRI0 6, { R_8,R_12,I16_16,0,0,0 } /* e.g. ahik */ |
315 | | #define INSTR_RIE_RUPI 6, { R_8,I8_32,U4_12,J16_16,0,0 } /* e.g. cij */ |
316 | | #define INSTR_RIE_R0PI 6, { R_8,I8_32,J16_16,0,0,0 } /* e.g. cijne */ |
317 | | #define INSTR_RIE_RUPU 6, { R_8,U8_32,U4_12,J16_16,0,0 } /* e.g. clij */ |
318 | | #define INSTR_RIE_R0PU 6, { R_8,U8_32,J16_16,0,0,0 } /* e.g. clijne */ |
319 | | #define INSTR_RIE_R0IU 6, { R_8,I16_16,U4_32,0,0,0 } /* e.g. cit */ |
320 | | #define INSTR_RIE_R0I0 6, { R_8,I16_16,0,0,0,0 } /* e.g. citne */ |
321 | | #define INSTR_RIE_R0UU 6, { R_8,U16_16,U4_32,0,0,0 } /* e.g. clfit */ |
322 | | #define INSTR_RIE_R0U0 6, { R_8,U16_16,0,0,0,0 } /* e.g. clfitne */ |
323 | | #define INSTR_RIE_RUI0 6, { R_8,I16_16,U4_12,0,0,0 } /* e.g. lochi */ |
324 | | #define INSTR_RIE_RRUUU 6, { R_8,R_12,U8_16,U8_24,U8_32,0 } /* e.g. rnsbg */ |
325 | | #define INSTR_RIE_RRUUU2 INSTR_RIE_RRUUU /* e.g. risbgz */ |
326 | | #define INSTR_RIE_RRUUU3 INSTR_RIE_RRUUU /* e.g. risbhg */ |
327 | | #define INSTR_RIE_RRUUU4 INSTR_RIE_RRUUU /* e.g. rnsbgt */ |
328 | | #define INSTR_RIL_0P 6, { J32_16,0,0,0,0 } /* e.g. jg */ |
329 | | #define INSTR_RIL_RP 6, { R_8,J32_16,0,0,0,0 } /* e.g. brasl */ |
330 | | #define INSTR_RIL_UP 6, { U4_8,J32_16,0,0,0,0 } /* e.g. brcl */ |
331 | | #define INSTR_RIL_RI 6, { R_8,I32_16,0,0,0,0 } /* e.g. afi */ |
332 | | #define INSTR_RIL_RU 6, { R_8,U32_16,0,0,0,0 } /* e.g. alfi */ |
333 | | #define INSTR_RI_0P 4, { J16_16,0,0,0,0,0 } /* e.g. j */ |
334 | | #define INSTR_RI_RI 4, { R_8,I16_16,0,0,0,0 } /* e.g. ahi */ |
335 | | #define INSTR_RI_RP 4, { R_8,J16_16,0,0,0,0 } /* e.g. brct */ |
336 | | #define INSTR_RI_RU 4, { R_8,U16_16,0,0,0,0 } /* e.g. tml */ |
337 | | #define INSTR_RI_UP 4, { U4_8,J16_16,0,0,0,0 } /* e.g. brc */ |
338 | | #define INSTR_RIS_RURDI 6, { R_8,I8_32,U4_12,D_20,B_16,0 } /* e.g. cib */ |
339 | | #define INSTR_RIS_R0RDI 6, { R_8,I8_32,D_20,B_16,0,0 } /* e.g. cibne */ |
340 | | #define INSTR_RIS_RURDU 6, { R_8,U8_32,U4_12,D_20,B_16,0 } /* e.g. clib */ |
341 | | #define INSTR_RIS_R0RDU 6, { R_8,U8_32,D_20,B_16,0,0 } /* e.g. clibne*/ |
342 | | #define INSTR_RRE_00 4, { 0,0,0,0,0,0 } /* e.g. palb */ |
343 | | #define INSTR_RRE_0R 4, { R_28,0,0,0,0,0 } /* e.g. tb */ |
344 | | #define INSTR_RRE_AA 4, { A_24,A_28,0,0,0,0 } /* e.g. cpya */ |
345 | | #define INSTR_RRE_AR 4, { A_24,R_28,0,0,0,0 } /* e.g. sar */ |
346 | | #define INSTR_RRE_F0 4, { F_24,0,0,0,0,0 } /* e.g. lzer */ |
347 | | #define INSTR_RRE_FE0 4, { FE_24,0,0,0,0,0 } /* e.g. lzxr */ |
348 | | #define INSTR_RRE_FF 4, { F_24,F_28,0,0,0,0 } /* e.g. debr */ |
349 | | #define INSTR_RRE_FEF 4, { FE_24,F_28,0,0,0,0 } /* e.g. lxdbr */ |
350 | | #define INSTR_RRE_FFE 4, { F_24,FE_28,0,0,0,0 } /* e.g. lexr */ |
351 | | #define INSTR_RRE_FEFE 4, { FE_24,FE_28,0,0,0,0 } /* e.g. dxr */ |
352 | | #define INSTR_RRE_R0 4, { R_24,0,0,0,0,0 } /* e.g. ipm */ |
353 | | #define INSTR_RRE_RA 4, { R_24,A_28,0,0,0,0 } /* e.g. ear */ |
354 | | #define INSTR_RRE_RF 4, { R_24,F_28,0,0,0,0 } /* e.g. lgdr */ |
355 | | #define INSTR_RRE_RFE 4, { R_24,FE_28,0,0,0,0 } /* e.g. csxtr */ |
356 | | #define INSTR_RRE_RR 4, { R_24,R_28,0,0,0,0 } /* e.g. lura */ |
357 | | #define INSTR_RRE_RER 4, { RE_24,R_28,0,0,0,0 } /* e.g. tre */ |
358 | | #define INSTR_RRE_RERE 4, { RE_24,RE_28,0,0,0,0 } /* e.g. cuse */ |
359 | | #define INSTR_RRE_FR 4, { F_24,R_28,0,0,0,0 } /* e.g. ldgr */ |
360 | | #define INSTR_RRE_FER 4, { FE_24,R_28,0,0,0,0 } /* e.g. cxfbr */ |
361 | | #define INSTR_RRF_F0FF 4, { F_16,F_24,F_28,0,0,0 } /* e.g. madbr */ |
362 | | #define INSTR_RRF_FE0FF 4, { F_16,F_24,F_28,0,0,0 } /* e.g. myr */ |
363 | | #define INSTR_RRF_F0FF2 4, { F_24,F_16,F_28,0,0,0 } /* e.g. cpsdr */ |
364 | | #define INSTR_RRF_F0FR 4, { F_24,F_16,R_28,0,0,0 } /* e.g. iedtr */ |
365 | | #define INSTR_RRF_FE0FER 4, { FE_24,FE_16,R_28,0,0,0 } /* e.g. iextr */ |
366 | | #define INSTR_RRF_FUFF 4, { F_24,F_16,F_28,U4_20,0,0 } /* e.g. didbr */ |
367 | | #define INSTR_RRF_FEUFEFE 4, { FE_24,FE_16,FE_28,U4_20,0,0 } /* e.g. qaxtr */ |
368 | | #define INSTR_RRF_FUFF2 4, { F_24,F_28,F_16,U4_20,0,0 } /* e.g. adtra */ |
369 | | #define INSTR_RRF_FEUFEFE2 4, { FE_24,FE_28,FE_16,U4_20,0,0 } /* e.g. axtra */ |
370 | | #define INSTR_RRF_RURR 4, { R_24,R_28,R_16,U4_20,0,0 } /* e.g. ipte */ |
371 | | #define INSTR_RRF_RURR2 4, { R_24,R_16,R_28,U4_20,0,0 } /* e.g. lptea */ |
372 | | #define INSTR_RRF_R0RR 4, { R_24,R_16,R_28,0,0,0 } /* e.g. idte */ |
373 | | #define INSTR_RRF_R0RR2 4, { R_24,R_28,R_16,0,0,0 } /* e.g. ark */ |
374 | | #define INSTR_RRF_R0RER 4, { RE_24,R_28,R_16,0,0,0 } /* e.g. mgrk */ |
375 | | #define INSTR_RRF_R0RR3 4, { R_24,R_28,R_16,0,0,0 } /* e.g. selrz */ |
376 | | #define INSTR_RRF_R0RR4 4, { R_24,R_CP16_28,0,0,0,0 } /* e.g. notr */ |
377 | | #define INSTR_RRF_U0FF 4, { F_24,U4_16,F_28,0,0,0 } /* e.g. fidbr */ |
378 | | #define INSTR_RRF_U0FEFE 4, { FE_24,U4_16,FE_28,0,0,0 } /* e.g. fixbr */ |
379 | | #define INSTR_RRF_U0RF 4, { R_24,U4_16,F_28,0,0,0 } /* e.g. cfebr */ |
380 | | #define INSTR_RRF_U0RFE 4, { R_24,U4_16,FE_28,0,0,0 } /* e.g. cfxbr */ |
381 | | #define INSTR_RRF_UUFF 4, { F_24,U4_16,F_28,U4_20,0,0 } /* e.g. fidtr */ |
382 | | #define INSTR_RRF_UUFFE 4, { F_24,U4_16,FE_28,U4_20,0,0 } /* e.g. ldxtr */ |
383 | | #define INSTR_RRF_UUFEFE 4, { FE_24,U4_16,FE_28,U4_20,0,0 } /* e.g. fixtr */ |
384 | | #define INSTR_RRF_0UFF 4, { F_24,F_28,U4_20,0,0,0 } /* e.g. ldetr */ |
385 | | #define INSTR_RRF_0UFEF 4, { FE_24,F_28,U4_20,0,0,0 } /* e.g. lxdtr */ |
386 | | #define INSTR_RRF_FFRU 4, { F_24,F_16,R_28,U4_20,0,0 } /* e.g. rrdtr */ |
387 | | #define INSTR_RRF_FEFERU 4, { FE_24,FE_16,R_28,U4_20,0,0 } /* e.g. rrxtr */ |
388 | | #define INSTR_RRF_U0RR 4, { R_24,R_28,U4_16,0,0,0 } /* e.g. sske */ |
389 | | #define INSTR_RRF_U0RER 4, { RE_24,R_28,U4_16,0,0,0 } /* e.g. trte */ |
390 | | #define INSTR_RRF_U0RERE 4, { RE_24,RE_28,U4_16,0,0,0 } /* e.g. cu24 */ |
391 | | #define INSTR_RRF_00RR 4, { R_24,R_28,0,0,0,0 } /* e.g. clrtne */ |
392 | | #define INSTR_RRF_0URF 4, { R_24,F_28,U4_20,0,0,0 } /* e.g. csdtr */ |
393 | | #define INSTR_RRF_0UREFE 4, { RE_24,FE_28,U4_20,0,0,0 } /* e.g. csxtr */ |
394 | | #define INSTR_RRF_UUFR 4, { F_24,U4_16,R_28,U4_20,0,0 } /* e.g. cdgtra */ |
395 | | #define INSTR_RRF_UUFER 4, { FE_24,U4_16,R_28,U4_20,0,0 } /* e.g. cxfbra */ |
396 | | #define INSTR_RRF_UURF 4, { R_24,U4_16,F_28,U4_20,0,0 } /* e.g. cgdtra */ |
397 | | #define INSTR_RRF_UURFE 4, { R_24,U4_16,FE_28,U4_20,0,0 } /* e.g. cfxbra */ |
398 | | #define INSTR_RR_0R 2, { R_12, 0,0,0,0,0 } /* e.g. br */ |
399 | | #define INSTR_RR_FF 2, { F_8,F_12,0,0,0,0 } /* e.g. adr */ |
400 | | #define INSTR_RR_FEF 2, { FE_8,F_12,0,0,0,0 } /* e.g. mxdr */ |
401 | | #define INSTR_RR_FFE 2, { F_8,FE_12,0,0,0,0 } /* e.g. ldxr */ |
402 | | #define INSTR_RR_FEFE 2, { FE_8,FE_12,0,0,0,0 } /* e.g. axr */ |
403 | | #define INSTR_RR_R0 2, { R_8, 0,0,0,0,0 } /* e.g. spm */ |
404 | | #define INSTR_RR_RR 2, { R_8,R_12,0,0,0,0 } /* e.g. lr */ |
405 | | #define INSTR_RR_RER 2, { RE_8,R_12,0,0,0,0 } /* e.g. dr */ |
406 | | #define INSTR_RR_U0 2, { U8_8, 0,0,0,0,0 } /* e.g. svc */ |
407 | | #define INSTR_RR_UR 2, { U4_8,R_12,0,0,0,0 } /* e.g. bcr */ |
408 | | #define INSTR_RRR_F0FF 4, { F_24,F_28,F_16,0,0,0 } /* e.g. ddtr */ |
409 | | #define INSTR_RRR_FE0FEFE 4, { FE_24,FE_28,FE_16,0,0,0 } /* e.g. axtr */ |
410 | | #define INSTR_RRS_RRRDU 6, { R_8,R_12,U4_32,D_20,B_16 } /* e.g. crb */ |
411 | | #define INSTR_RRS_RRRD0 6, { R_8,R_12,D_20,B_16,0 } /* e.g. crbne */ |
412 | | #define INSTR_RSE_RRRD 6, { R_8,R_12,D_20,B_16,0,0 } /* e.g. lmh */ |
413 | | #define INSTR_RSE_RERERD 6, { RE_8,RE_12,D_20,B_16,0,0 } /* e.g. mvclu */ |
414 | | #define INSTR_RSE_CCRD 6, { C_8,C_12,D_20,B_16,0,0 } /* e.g. stctg */ |
415 | | #define INSTR_RSE_RURD 6, { R_8,U4_12,D_20,B_16,0,0 } /* e.g. icmh */ |
416 | | #define INSTR_RSL_R0RD 6, { D_20,L4_8,B_16,0,0,0 } /* e.g. tp */ |
417 | | #define INSTR_RSL_LRDFU 6, { F_32,D_20,L8_8,B_16,U4_36,0 } /* e.g. cdzt */ |
418 | | #define INSTR_RSL_LRDFEU 6, { FE_32,D_20,L8_8,B_16,U4_36,0 } /* e.g. cxzt */ |
419 | | #define INSTR_RSI_RRP 4, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxh */ |
420 | | #define INSTR_RSY_RRRD 6, { R_8,R_12,D20_20,B_16,0,0 } /* e.g. stmy */ |
421 | | #define INSTR_RSY_RERERD 6, { RE_8,RE_12,D20_20,B_16,0,0 } /* e.g. cdsy */ |
422 | | #define INSTR_RSY_RURD 6, { R_8,U4_12,D20_20,B_16,0,0 } /* e.g. icmh */ |
423 | | #define INSTR_RSY_RURD2 6, { R_8,D20_20,B_16,U4_12,0,0 } /* e.g. loc */ |
424 | | #define INSTR_RSY_R0RD 6, { R_8,D20_20,B_16,0,0,0 } /* e.g. locne */ |
425 | | #define INSTR_RSY_AARD 6, { A_8,A_12,D20_20,B_16,0,0 } /* e.g. lamy */ |
426 | | #define INSTR_RSY_CCRD 6, { C_8,C_12,D20_20,B_16,0,0 } /* e.g. stctg */ |
427 | | #define INSTR_RS_AARD 4, { A_8,A_12,D_20,B_16,0,0 } /* e.g. lam */ |
428 | | #define INSTR_RS_CCRD 4, { C_8,C_12,D_20,B_16,0,0 } /* e.g. lctl */ |
429 | | #define INSTR_RS_R0RD 4, { R_8,D_20,B_16,0,0,0 } /* e.g. sll */ |
430 | | #define INSTR_RS_RE0RD 4, { RE_8,D_20,B_16,0,0,0 } /* e.g. slda */ |
431 | | #define INSTR_RS_RRRD 4, { R_8,R_12,D_20,B_16,0,0 } /* e.g. cs */ |
432 | | #define INSTR_RS_RERERD 4, { RE_8,RE_12,D_20,B_16,0,0 } /* e.g. cds */ |
433 | | #define INSTR_RS_RURD 4, { R_8,U4_12,D_20,B_16,0,0 } /* e.g. icm */ |
434 | | #define INSTR_RXE_FRRD 6, { F_8,D_20,X_12,B_16,0,0 } /* e.g. adb */ |
435 | | #define INSTR_RXE_FERRD 6, { FE_8,D_20,X_12,B_16,0,0 } /* e.g. lxdb */ |
436 | | #define INSTR_RXE_RRRD 6, { R_8,D_20,X_12,B_16,0,0 } /* e.g. lg */ |
437 | | #define INSTR_RXE_RRRDU 6, { R_8,D_20,X_12,B_16,U4_32,0 } /* e.g. lcbb */ |
438 | | #define INSTR_RXE_RERRD 6, { RE_8,D_20,X_12,B_16,0,0 } /* e.g. dsg */ |
439 | | #define INSTR_RXF_FRRDF 6, { F_32,F_8,D_20,X_12,B_16,0 } /* e.g. madb */ |
440 | | #define INSTR_RXF_FRRDFE 6, { FE_32,F_8,D_20,X_12,B_16,0 } /* e.g. my */ |
441 | | #define INSTR_RXF_FERRDFE 6, { FE_32,FE_8,D_20,X_12,B_16,0 } /* e.g. slxt */ |
442 | | #define INSTR_RXF_RRRDR 6, { R_32,R_8,D_20,X_12,B_16,0 } /* e.g. .insn */ |
443 | | #define INSTR_RXY_RRRD 6, { R_8,D20_20,X_12,B_16,0,0 } /* e.g. ly */ |
444 | | #define INSTR_RXY_RERRD 6, { RE_8,D20_20,X_12,B_16,0,0 } /* e.g. dsg */ |
445 | | #define INSTR_RXY_FRRD 6, { F_8,D20_20,X_12,B_16,0,0 } /* e.g. ley */ |
446 | | #define INSTR_RXY_URRD 6, { U4_8,D20_20,X_12,B_16,0,0 } /* e.g. pfd */ |
447 | | #define INSTR_RXY_0RRD 6, { D20_20,X_12,B_16,0,0 } /* e.g. bic */ |
448 | | #define INSTR_RX_0RRD 4, { D_20,X_12,B_16,0,0,0 } /* e.g. be */ |
449 | | #define INSTR_RX_FRRD 4, { F_8,D_20,X_12,B_16,0,0 } /* e.g. ae */ |
450 | | #define INSTR_RX_FERRD 4, { FE_8,D_20,X_12,B_16,0,0 } /* e.g. mxd */ |
451 | | #define INSTR_RX_RRRD 4, { R_8,D_20,X_12,B_16,0,0 } /* e.g. l */ |
452 | | #define INSTR_RX_RERRD 4, { RE_8,D_20,X_12,B_16,0,0 } /* e.g. d */ |
453 | | #define INSTR_RX_URRD 4, { U4_8,D_20,X_12,B_16,0,0 } /* e.g. bc */ |
454 | | #define INSTR_SI_RD 4, { D_20,B_16,0,0,0,0 } /* e.g. lpsw */ |
455 | | #define INSTR_SI_URD 4, { D_20,B_16,U8_8,0,0,0 } /* e.g. cli */ |
456 | | #define INSTR_SIY_RD 6, { D20_20,B_16,0,0,0,0 } /* e.g. lpswey*/ |
457 | | #define INSTR_SIY_URD 6, { D20_20,B_16,U8_8,0,0,0 } /* e.g. tmy */ |
458 | | #define INSTR_SIY_IRD 6, { D20_20,B_16,I8_8,0,0,0 } /* e.g. asi */ |
459 | | #define INSTR_SIL_RDI 6, { D_20,B_16,I16_32,0,0,0 } /* e.g. chhsi */ |
460 | | #define INSTR_SIL_RDU 6, { D_20,B_16,U16_32,0,0,0 } /* e.g. clfhsi */ |
461 | | #define INSTR_SMI_U0RDP 6, { U4_8,J16_32,D_20,B_16,0,0 } /* e.g. bpp */ |
462 | | #define INSTR_SSE_RDRD 6, { D_20,B_16,D_36,B_32,0,0 } /* e.g. mvcdk */ |
463 | | #define INSTR_SS_L0RDRD 6, { D_20,L8_8,B_16,D_36,B_32,0 } /* e.g. mvc */ |
464 | | #define INSTR_SS_L2RDRD 6, { D_20,B_16,D_36,L8_8,B_32,0 } /* e.g. pka */ |
465 | | #define INSTR_SS_LIRDRD 6, { D_20,L4_8,B_16,D_36,B_32,U4_12 } /* e.g. srp */ |
466 | | #define INSTR_SS_LLRDRD 6, { D_20,L4_8,B_16,D_36,L4_12,B_32 } /* e.g. pack */ |
467 | | #define INSTR_SS_RRRDRD 6, { D_20,R_8,B_16,D_36,B_32,R_12 } /* e.g. mvck */ |
468 | | #define INSTR_SS_RRRDRD2 6, { R_8,D_20,B_16,R_12,D_36,B_32 } /* e.g. plo */ |
469 | | #define INSTR_SS_RRRDRD3 6, { R_8,R_12,D_20,B_16,D_36,B_32 } /* e.g. lmd */ |
470 | | #define INSTR_SSF_RRDRD 6, { D_20,B_16,D_36,B_32,R_8,0 } /* e.g. mvcos */ |
471 | | #define INSTR_SSF_RRDRD2 6, { R_8,D_20,B_16,D_36,B_32,0 } /* e.g. cal */ |
472 | | #define INSTR_SSF_RERDRD2 6, { RE_8,D_20,B_16,D_36,B_32,0 } /* e.g. lpd */ |
473 | | #define INSTR_S_00 4, { 0,0,0,0,0,0 } /* e.g. hsch */ |
474 | | #define INSTR_S_RD 4, { D_20,B_16,0,0,0,0 } /* e.g. stck */ |
475 | | #define INSTR_VRV_VVXRDU 6, { V_8,D_20,VX_12,B_16,U4_32,0 } /* e.g. vgef */ |
476 | | #define INSTR_VRI_V0U 6, { V_8,U16_16,0,0,0,0 } /* e.g. vgbm */ |
477 | | #define INSTR_VRI_V 6, { V_8,0,0,0,0,0 } /* e.g. vzero */ |
478 | | #define INSTR_VRI_V0UUU 6, { V_8,U8_16,U8_24,U4_32,0,0 } /* e.g. vgm */ |
479 | | #define INSTR_VRI_V0UU 6, { V_8,U8_16,U8_24,0,0,0 } /* e.g. vgmb */ |
480 | | #define INSTR_VRI_V0UU2 6, { V_8,U16_16,U4_32,0,0,0 } /* e.g. vlip */ |
481 | | #define INSTR_VRI_VVUU 6, { V_8,V_12,U16_16,U4_32,0,0 } /* e.g. vrep */ |
482 | | #define INSTR_VRI_VVU 6, { V_8,V_12,U16_16,0,0,0 } /* e.g. vrepb */ |
483 | | #define INSTR_VRI_VVU2 6, { V_8,V_12,U12_16,0,0,0 } /* e.g. vftcidb */ |
484 | | #define INSTR_VRI_V0IU 6, { V_8,I16_16,U4_32,0,0,0 } /* e.g. vrepi */ |
485 | | #define INSTR_VRI_V0I 6, { V_8,I16_16,0,0,0,0 } /* e.g. vrepib */ |
486 | | #define INSTR_VRI_VVV0UU 6, { V_8,V_12,V_16,U8_24,U4_32,0 } /* e.g. verim */ |
487 | | #define INSTR_VRI_VVV0UU2 6, { V_8,V_12,V_16,U8_28,U4_24,0 } /* e.g. vap */ |
488 | | #define INSTR_VRI_VVV0U 6, { V_8,V_12,V_16,U8_24,0,0 } /* e.g. verimb*/ |
489 | | #define INSTR_VRI_VVUUU 6, { V_8,V_12,U12_16,U4_32,U4_28,0 } /* e.g. vftci */ |
490 | | #define INSTR_VRI_VVUUU2 6, { V_8,V_12,U8_28,U8_16,U4_24,0 } /* e.g. vpsop */ |
491 | | #define INSTR_VRI_VR0UU 6, { V_8,R_12,U8_28,U4_24,0,0 } /* e.g. vcvd */ |
492 | | #define INSTR_VRI_VV0UU 6, { V_8,V_12,U8_28,U4_24,0,0 } /* e.g. vcvdq */ |
493 | | #define INSTR_VRI_VVV0UV 6, { V_8,V_12,V_16,V_32,U8_24,0 } /* e.g. veval */ |
494 | | #define INSTR_VRX_VRRD 6, { V_8,D_20,X_12,B_16,0,0 } /* e.g. vl */ |
495 | | #define INSTR_VRX_VV 6, { V_8,V_12,0,0,0,0 } /* e.g. vlr */ |
496 | | #define INSTR_VRX_VRRDU 6, { V_8,D_20,X_12,B_16,U4_32,0 } /* e.g. vlrep */ |
497 | | #define INSTR_VRS_RVRDU 6, { R_8,V_12,D_20,B_16,U4_32,0 } /* e.g. vlgv */ |
498 | | #define INSTR_VRS_RVRD 6, { R_8,V_12,D_20,B_16,0,0 } /* e.g. vlgvb */ |
499 | | #define INSTR_VRS_VVRDU 6, { V_8,V_12,D_20,B_16,U4_32,0 } /* e.g. verll */ |
500 | | #define INSTR_VRS_VVRD 6, { V_8,V_12,D_20,B_16,0,0 } /* e.g. vlm */ |
501 | | #define INSTR_VRS_VRRDU 6, { V_8,R_12,D_20,B_16,U4_32,0 } /* e.g. vlvg */ |
502 | | #define INSTR_VRS_VRRD 6, { V_8,R_12,D_20,B_16,0,0 } /* e.g. vlvgb */ |
503 | | #define INSTR_VRS_RRDV 6, { V_32,R_12,D_20,B_16,0,0 } /* e.g. vlrlr */ |
504 | | #define INSTR_VRR_VRR 6, { V_8,R_12,R_16,0,0,0 } /* e.g. vlvgp */ |
505 | | #define INSTR_VRR_VVV0U 6, { V_8,V_12,V_16,U4_32,0,0 } /* e.g. vmrh */ |
506 | | #define INSTR_VRR_VVV0U0 6, { V_8,V_12,V_16,U4_24,0,0 } /* e.g. vfaeb */ |
507 | | #define INSTR_VRR_VVV0U02 6, { V_8,V_12,V_16,U4_28,0,0 } /* e.g. vd */ |
508 | | #define INSTR_VRR_VVV0U1 INSTR_VRR_VVV0U0 /* e.g. vfaebs*/ |
509 | | #define INSTR_VRR_VVV0U2 INSTR_VRR_VVV0U0 /* e.g. vfaezb*/ |
510 | | #define INSTR_VRR_VVV0U3 INSTR_VRR_VVV0U0 /* e.g. vfaezbs*/ |
511 | | #define INSTR_VRR_VVV 6, { V_8,V_12,V_16,0,0,0 } /* e.g. vmrhb */ |
512 | | #define INSTR_VRR_VVV2 6, { V_8,V_CP16_12,0,0,0,0 } /* e.g. vnot */ |
513 | | #define INSTR_VRR_VV0U 6, { V_8,V_12,U4_32,0,0,0 } /* e.g. vseg */ |
514 | | #define INSTR_VRR_VV0U2 6, { V_8,V_12,U4_24,0,0,0 } /* e.g. vistrb*/ |
515 | | #define INSTR_VRR_VV0UU 6, { V_8,V_12,U4_28,U4_24,0,0 } /* e.g. vcdgb */ |
516 | | #define INSTR_VRR_VV0UU2 6, { V_8,V_12,U4_32,U4_28,0,0 } /* e.g. wfc */ |
517 | | #define INSTR_VRR_VV0UU8 INSTR_VRR_VV0UU /* e.g. wcdgb */ |
518 | | #define INSTR_VRR_VV 6, { V_8,V_12,0,0,0,0 } /* e.g. vsegb */ |
519 | | #define INSTR_VRR_VVVUU0V 6, { V_8,V_12,V_16,V_32,U4_20,U4_24 } /* e.g. vstrc */ |
520 | | #define INSTR_VRR_VVVU0V 6, { V_8,V_12,V_16,V_32,U4_20,0 } /* e.g. vac */ |
521 | | #define INSTR_VRR_VVVU0VB 6, { V_8,V_12,V_16,V_32,U4_24,0 } /* e.g. vstrcb*/ |
522 | | #define INSTR_VRR_VVVU0VB1 INSTR_VRR_VVVU0VB /* e.g. vstrcbs*/ |
523 | | #define INSTR_VRR_VVVU0VB2 INSTR_VRR_VVVU0VB /* e.g. vstrczb*/ |
524 | | #define INSTR_VRR_VVVU0VB3 INSTR_VRR_VVVU0VB /* e.g. vstrczbs*/ |
525 | | #define INSTR_VRR_VVV0V 6, { V_8,V_12,V_16,V_32,0,0 } /* e.g. vacq */ |
526 | | #define INSTR_VRR_VVV0U0U 6, { V_8,V_12,V_16,U4_32,U4_24,0 } /* e.g. vfae */ |
527 | | #define INSTR_VRR_VVVV 6, { V_8,V_12,V_16,V_32,0,0 } /* e.g. vfmadb*/ |
528 | | #define INSTR_VRR_VVV0UUU 6, { V_8,V_12,V_16,U4_32,U4_28,U4_24 }/* e.g. vfch */ |
529 | | #define INSTR_VRR_VVV0UU 6, { V_8,V_12,V_16,U4_32,U4_28,0 } /* e.g. vfa */ |
530 | | #define INSTR_VRR_VV0UUU 6, { V_8,V_12,U4_32,U4_28,U4_24,0 } /* e.g. vcdg */ |
531 | | #define INSTR_VRR_VVVU0UV 6, { V_8,V_12,V_16,V_32,U4_28,U4_20 } /* e.g. vfma */ |
532 | | #define INSTR_VRR_VV0U0U 6, { V_8,V_12,U4_32,U4_24,0,0 } /* e.g. vistr */ |
533 | | #define INSTR_VRR_0V 6, { V_12,0,0,0,0,0 } /* e.g. vtp */ |
534 | | #define INSTR_VRR_0V0U 6, { V_12,U16_20,0,0,0,0 } /* e.g. vtp */ |
535 | | #define INSTR_VRR_0VVU 6, { V_12,V_16,U16_20,0,0,0 } /* e.g. vtz */ |
536 | | #define INSTR_VRR_0VV0U 6, { V_12,V_16,U4_24,0,0,0 } /* e.g. vcp */ |
537 | | #define INSTR_VRR_RV0U 6, { R_8,V_12,U4_24,0,0,0 } /* e.g. vcvb */ |
538 | | #define INSTR_VRR_RV0UU 6, { R_8,V_12,U4_24,U4_28,0,0 } /* e.g. vcvb */ |
539 | | #define INSTR_VSI_URDV 6, { V_32,D_20,B_16,U8_8,0,0 } /* e.g. vlrl */ |
540 | | |
541 | | #define MASK_E { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } |
542 | | #define MASK_IE_UU { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } |
543 | | #define MASK_MII_UPP { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
544 | | #define MASK_RIE_RRP { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
545 | | #define MASK_RIE_RRPU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
546 | | #define MASK_RIE_RRP0 { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff } |
547 | | #define MASK_RIE_RRI0 { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff } |
548 | | #define MASK_RIE_RUPI { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
549 | | #define MASK_RIE_R0PI { 0xff, 0x0f, 0x00, 0x00, 0x00, 0xff } |
550 | | #define MASK_RIE_RUPU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
551 | | #define MASK_RIE_R0PU { 0xff, 0x0f, 0x00, 0x00, 0x00, 0xff } |
552 | | #define MASK_RIE_R0IU { 0xff, 0x0f, 0x00, 0x00, 0x0f, 0xff } |
553 | | #define MASK_RIE_R0I0 { 0xff, 0x0f, 0x00, 0x00, 0xff, 0xff } |
554 | | #define MASK_RIE_R0UU { 0xff, 0x0f, 0x00, 0x00, 0x0f, 0xff } |
555 | | #define MASK_RIE_R0U0 { 0xff, 0x0f, 0x00, 0x00, 0xff, 0xff } |
556 | | #define MASK_RIE_RUI0 { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } |
557 | | #define MASK_RIE_RRUUU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
558 | | #define MASK_RIE_RRUUU2 { 0xff, 0x00, 0x00, 0x80, 0x00, 0xff } |
559 | | #define MASK_RIE_RRUUU3 { 0xff, 0x00, 0x00, 0x80, 0x00, 0xff } |
560 | | #define MASK_RIE_RRUUU4 { 0xff, 0x00, 0x80, 0x00, 0x00, 0xff } |
561 | | #define MASK_RIL_0P { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } |
562 | | #define MASK_RIL_RP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } |
563 | | #define MASK_RIL_UP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } |
564 | | #define MASK_RIL_RI { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } |
565 | | #define MASK_RIL_RU { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } |
566 | | #define MASK_RI_0P { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } |
567 | | #define MASK_RI_RI { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } |
568 | | #define MASK_RI_RP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } |
569 | | #define MASK_RI_RU { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } |
570 | | #define MASK_RI_UP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } |
571 | | #define MASK_RIS_RURDI { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
572 | | #define MASK_RIS_R0RDI { 0xff, 0x0f, 0x00, 0x00, 0x00, 0xff } |
573 | | #define MASK_RIS_RURDU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
574 | | #define MASK_RIS_R0RDU { 0xff, 0x0f, 0x00, 0x00, 0x00, 0xff } |
575 | | #define MASK_RRE_00 { 0xff, 0xff, 0xff, 0xff, 0x00, 0x00 } |
576 | | #define MASK_RRE_0R { 0xff, 0xff, 0xff, 0xf0, 0x00, 0x00 } |
577 | | #define MASK_RRE_AA { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } |
578 | | #define MASK_RRE_AR { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } |
579 | | #define MASK_RRE_F0 { 0xff, 0xff, 0xff, 0x0f, 0x00, 0x00 } |
580 | | #define MASK_RRE_FE0 { 0xff, 0xff, 0xff, 0x0f, 0x00, 0x00 } |
581 | | #define MASK_RRE_FF { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } |
582 | | #define MASK_RRE_FEF { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } |
583 | | #define MASK_RRE_FFE { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } |
584 | | #define MASK_RRE_FEFE { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } |
585 | | #define MASK_RRE_R0 { 0xff, 0xff, 0xff, 0x0f, 0x00, 0x00 } |
586 | | #define MASK_RRE_RA { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } |
587 | | #define MASK_RRE_RF { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } |
588 | | #define MASK_RRE_RFE { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } |
589 | | #define MASK_RRE_RR { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } |
590 | | #define MASK_RRE_RER { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } |
591 | | #define MASK_RRE_RERE { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } |
592 | | #define MASK_RRE_FR { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } |
593 | | #define MASK_RRE_FER { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } |
594 | | #define MASK_RRF_F0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } |
595 | | #define MASK_RRF_FE0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } |
596 | | #define MASK_RRF_F0FF2 { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } |
597 | | #define MASK_RRF_F0FR { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } |
598 | | #define MASK_RRF_FE0FER { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } |
599 | | #define MASK_RRF_FUFF { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } |
600 | | #define MASK_RRF_FEUFEFE { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } |
601 | | #define MASK_RRF_FUFF2 { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } |
602 | | #define MASK_RRF_FEUFEFE2 { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } |
603 | | #define MASK_RRF_RURR { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } |
604 | | #define MASK_RRF_RURR2 { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } |
605 | | #define MASK_RRF_R0RR { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } |
606 | | #define MASK_RRF_R0RR2 { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } |
607 | | #define MASK_RRF_R0RER { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } |
608 | | #define MASK_RRF_R0RR3 { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } |
609 | | #define MASK_RRF_R0RR4 { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } |
610 | | #define MASK_RRF_U0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } |
611 | | #define MASK_RRF_U0FEFE { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } |
612 | | #define MASK_RRF_U0RF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } |
613 | | #define MASK_RRF_U0RFE { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } |
614 | | #define MASK_RRF_UUFF { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } |
615 | | #define MASK_RRF_UUFFE { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } |
616 | | #define MASK_RRF_UUFEFE { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } |
617 | | #define MASK_RRF_0UFF { 0xff, 0xff, 0xf0, 0x00, 0x00, 0x00 } |
618 | | #define MASK_RRF_0UFEF { 0xff, 0xff, 0xf0, 0x00, 0x00, 0x00 } |
619 | | #define MASK_RRF_FFRU { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } |
620 | | #define MASK_RRF_FEFERU { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } |
621 | | #define MASK_RRF_U0RR { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } |
622 | | #define MASK_RRF_U0RER { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } |
623 | | #define MASK_RRF_U0RERE { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } |
624 | | #define MASK_RRF_00RR { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } |
625 | | #define MASK_RRF_0URF { 0xff, 0xff, 0xf0, 0x00, 0x00, 0x00 } |
626 | | #define MASK_RRF_0UREFE { 0xff, 0xff, 0xf0, 0x00, 0x00, 0x00 } |
627 | | #define MASK_RRF_UUFR { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } |
628 | | #define MASK_RRF_UUFER { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } |
629 | | #define MASK_RRF_UURF { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } |
630 | | #define MASK_RRF_UURFE { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } |
631 | | #define MASK_RR_0R { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 } |
632 | | #define MASK_RR_FF { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
633 | | #define MASK_RR_FEF { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
634 | | #define MASK_RR_FFE { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
635 | | #define MASK_RR_FEFE { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
636 | | #define MASK_RR_R0 { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } |
637 | | #define MASK_RR_RR { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
638 | | #define MASK_RR_RER { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
639 | | #define MASK_RR_U0 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
640 | | #define MASK_RR_UR { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
641 | | #define MASK_RRR_F0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } |
642 | | #define MASK_RRR_FE0FEFE { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } |
643 | | #define MASK_RRS_RRRDU { 0xff, 0x00, 0x00, 0x00, 0x0f, 0xff } |
644 | | #define MASK_RRS_RRRD0 { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } |
645 | | #define MASK_RSE_RRRD { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } |
646 | | #define MASK_RSE_RERERD { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } |
647 | | #define MASK_RSE_CCRD { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } |
648 | | #define MASK_RSE_RURD { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } |
649 | | #define MASK_RSL_R0RD { 0xff, 0x0f, 0x00, 0x00, 0xff, 0xff } |
650 | | #define MASK_RSL_LRDFU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
651 | | #define MASK_RSL_LRDFEU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
652 | | #define MASK_RSI_RRP { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
653 | | #define MASK_RS_AARD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
654 | | #define MASK_RS_CCRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
655 | | #define MASK_RS_R0RD { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } |
656 | | #define MASK_RS_RE0RD { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } |
657 | | #define MASK_RS_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
658 | | #define MASK_RS_RERERD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
659 | | #define MASK_RS_RURD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
660 | | #define MASK_RSY_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
661 | | #define MASK_RSY_RERERD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
662 | | #define MASK_RSY_RURD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
663 | | #define MASK_RSY_RURD2 { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
664 | | #define MASK_RSY_R0RD { 0xff, 0x0f, 0x00, 0x00, 0x00, 0xff } |
665 | | #define MASK_RSY_AARD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
666 | | #define MASK_RSY_CCRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
667 | | #define MASK_RXE_FRRD { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } |
668 | | #define MASK_RXE_FERRD { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } |
669 | | #define MASK_RXE_RRRD { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } |
670 | | #define MASK_RXE_RRRDU { 0xff, 0x00, 0x00, 0x00, 0x0f, 0xff } |
671 | | #define MASK_RXE_RERRD { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } |
672 | | #define MASK_RXF_FRRDF { 0xff, 0x00, 0x00, 0x00, 0x0f, 0xff } |
673 | | #define MASK_RXF_FRRDFE { 0xff, 0x00, 0x00, 0x00, 0x0f, 0xff } |
674 | | #define MASK_RXF_FERRDFE { 0xff, 0x00, 0x00, 0x00, 0x0f, 0xff } |
675 | | #define MASK_RXF_RRRDR { 0xff, 0x00, 0x00, 0x00, 0x0f, 0xff } |
676 | | #define MASK_RXY_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
677 | | #define MASK_RXY_RERRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
678 | | #define MASK_RXY_FRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
679 | | #define MASK_RXY_URRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
680 | | #define MASK_RXY_0RRD { 0xff, 0xf0, 0x00, 0x00, 0x00, 0xff } |
681 | | #define MASK_RX_0RRD { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 } |
682 | | #define MASK_RX_FRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
683 | | #define MASK_RX_FERRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
684 | | #define MASK_RX_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
685 | | #define MASK_RX_RERRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
686 | | #define MASK_RX_URRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
687 | | #define MASK_SI_RD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
688 | | #define MASK_SI_URD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
689 | | #define MASK_SIY_RD { 0xff, 0xff, 0x00, 0x00, 0x00, 0xff } |
690 | | #define MASK_SIY_URD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
691 | | #define MASK_SIY_IRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
692 | | #define MASK_SIL_RDI { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } |
693 | | #define MASK_SIL_RDU { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } |
694 | | #define MASK_SMI_U0RDP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } |
695 | | #define MASK_SSE_RDRD { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } |
696 | | #define MASK_SS_L0RDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
697 | | #define MASK_SS_L2RDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
698 | | #define MASK_SS_LIRDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
699 | | #define MASK_SS_LLRDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
700 | | #define MASK_SS_RRRDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
701 | | #define MASK_SS_RRRDRD2 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
702 | | #define MASK_SS_RRRDRD3 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
703 | | #define MASK_SSF_RRDRD { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } |
704 | | #define MASK_SSF_RRDRD2 { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } |
705 | | #define MASK_SSF_RERDRD2 { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } |
706 | | #define MASK_S_00 { 0xff, 0xff, 0xff, 0xff, 0x00, 0x00 } |
707 | | #define MASK_S_RD { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } |
708 | | #define MASK_VRV_VVXRDU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
709 | | #define MASK_VRI_V0U { 0xff, 0x0f, 0x00, 0x00, 0xf0, 0xff } |
710 | | #define MASK_VRI_V { 0xff, 0x0f, 0xff, 0xff, 0xf0, 0xff } |
711 | | #define MASK_VRI_V0UUU { 0xff, 0x0f, 0x00, 0x00, 0x00, 0xff } |
712 | | #define MASK_VRI_V0UU { 0xff, 0x0f, 0x00, 0x00, 0xf0, 0xff } |
713 | | #define MASK_VRI_V0UU2 { 0xff, 0x0f, 0x00, 0x00, 0x00, 0xff } |
714 | | #define MASK_VRI_VVUU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
715 | | #define MASK_VRI_VVU { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff } |
716 | | #define MASK_VRI_VVU2 { 0xff, 0x00, 0x00, 0x0f, 0xf0, 0xff } |
717 | | #define MASK_VRI_V0IU { 0xff, 0x0f, 0x00, 0x00, 0x00, 0xff } |
718 | | #define MASK_VRI_V0I { 0xff, 0x0f, 0x00, 0x00, 0xf0, 0xff } |
719 | | #define MASK_VRI_VVV0UU { 0xff, 0x00, 0x0f, 0x00, 0x00, 0xff } |
720 | | #define MASK_VRI_VVV0UU2 { 0xff, 0x00, 0x0f, 0x00, 0x00, 0xff } |
721 | | #define MASK_VRI_VVV0U { 0xff, 0x00, 0x0f, 0x00, 0xf0, 0xff } |
722 | | #define MASK_VRI_VVUUU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
723 | | #define MASK_VRI_VVUUU2 { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
724 | | #define MASK_VRI_VR0UU { 0xff, 0x00, 0xff, 0x00, 0x00, 0xff } |
725 | | #define MASK_VRI_VV0UU { 0xff, 0x00, 0xff, 0x00, 0x00, 0xff } |
726 | | #define MASK_VRI_VVV0UV { 0xff, 0x00, 0x0f, 0x00, 0x00, 0xff } |
727 | | #define MASK_VRX_VRRD { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff } |
728 | | #define MASK_VRX_VV { 0xff, 0x00, 0xff, 0xff, 0xf0, 0xff } |
729 | | #define MASK_VRX_VRRDU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
730 | | #define MASK_VRS_RVRDU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
731 | | #define MASK_VRS_RVRD { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff } |
732 | | #define MASK_VRS_VVRDU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
733 | | #define MASK_VRS_VVRD { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff } |
734 | | #define MASK_VRS_VRRDU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
735 | | #define MASK_VRS_VRRD { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff } |
736 | | #define MASK_VRS_RRDV { 0xff, 0xf0, 0x00, 0x00, 0x00, 0xff } |
737 | | #define MASK_VRR_VRR { 0xff, 0x00, 0x0f, 0xff, 0xf0, 0xff } |
738 | | #define MASK_VRR_VVV0U { 0xff, 0x00, 0x0f, 0xff, 0x00, 0xff } |
739 | | #define MASK_VRR_VVV0U0 { 0xff, 0x00, 0x0f, 0x0f, 0xf0, 0xff } |
740 | | #define MASK_VRR_VVV0U02 { 0xff, 0x00, 0x0f, 0xf0, 0xf0, 0xff } |
741 | | #define MASK_VRR_VVV0U1 { 0xff, 0x00, 0x0f, 0x1f, 0xf0, 0xff } |
742 | | #define MASK_VRR_VVV0U2 { 0xff, 0x00, 0x0f, 0x2f, 0xf0, 0xff } |
743 | | #define MASK_VRR_VVV0U3 { 0xff, 0x00, 0x0f, 0x3f, 0xf0, 0xff } |
744 | | #define MASK_VRR_VVV { 0xff, 0x00, 0x0f, 0xff, 0xf0, 0xff } |
745 | | #define MASK_VRR_VVV2 { 0xff, 0x00, 0x0f, 0xff, 0xf0, 0xff } |
746 | | #define MASK_VRR_VVV0V { 0xff, 0x00, 0x0f, 0xff, 0x00, 0xff } |
747 | | #define MASK_VRR_VV0U { 0xff, 0x00, 0xff, 0xff, 0x00, 0xff } |
748 | | #define MASK_VRR_VV0U2 { 0xff, 0x00, 0xff, 0x0f, 0xf0, 0xff } |
749 | | #define MASK_VRR_VV0UU { 0xff, 0x00, 0xff, 0x00, 0xf0, 0xff } |
750 | | #define MASK_VRR_VV0UU2 { 0xff, 0x00, 0xff, 0xf0, 0x00, 0xff } |
751 | | #define MASK_VRR_VV0UU8 { 0xff, 0x00, 0xff, 0x08, 0xf0, 0xff } |
752 | | #define MASK_VRR_VV { 0xff, 0x00, 0xff, 0xff, 0xf0, 0xff } |
753 | | #define MASK_VRR_VVVUU0V { 0xff, 0x00, 0x00, 0x0f, 0x00, 0xff } |
754 | | #define MASK_VRR_VVVU0V { 0xff, 0x00, 0x00, 0xff, 0x00, 0xff } |
755 | | #define MASK_VRR_VVVU0VB { 0xff, 0x00, 0x0f, 0x0f, 0x00, 0xff } |
756 | | #define MASK_VRR_VVVU0VB1 { 0xff, 0x00, 0x0f, 0x1f, 0x00, 0xff } |
757 | | #define MASK_VRR_VVVU0VB2 { 0xff, 0x00, 0x0f, 0x2f, 0x00, 0xff } |
758 | | #define MASK_VRR_VVVU0VB3 { 0xff, 0x00, 0x0f, 0x3f, 0x00, 0xff } |
759 | | #define MASK_VRR_VVV0U0U { 0xff, 0x00, 0x0f, 0x0f, 0x00, 0xff } |
760 | | #define MASK_VRR_VVVV { 0xff, 0x00, 0x0f, 0xff, 0x00, 0xff } |
761 | | #define MASK_VRR_VVV0UUU { 0xff, 0x00, 0x0f, 0x00, 0x00, 0xff } |
762 | | #define MASK_VRR_VVV0UU { 0xff, 0x00, 0x0f, 0xf0, 0x00, 0xff } |
763 | | #define MASK_VRR_VV0UUU { 0xff, 0x00, 0xff, 0x00, 0x00, 0xff } |
764 | | #define MASK_VRR_VVVU0UV { 0xff, 0x00, 0x00, 0xf0, 0x00, 0xff } |
765 | | #define MASK_VRR_VV0U0U { 0xff, 0x00, 0xff, 0x0f, 0x00, 0xff } |
766 | | #define MASK_VRR_0V { 0xff, 0xf0, 0xff, 0xff, 0xf0, 0xff } |
767 | | #define MASK_VRR_0V0U { 0xff, 0xf0, 0xf0, 0x00, 0x00, 0xff } |
768 | | #define MASK_VRR_0VVU { 0xff, 0xf0, 0x00, 0x00, 0x00, 0xff } |
769 | | #define MASK_VRR_0VV0U { 0xff, 0xf0, 0x0f, 0x0f, 0xf0, 0xff } |
770 | | #define MASK_VRR_RV0U { 0xff, 0x00, 0xff, 0x0f, 0xf0, 0xff } |
771 | | #define MASK_VRR_RV0UU { 0xff, 0x00, 0xff, 0x00, 0xf0, 0xff } |
772 | | #define MASK_VSI_URDV { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
773 | | |
774 | | |
775 | | /* The opcode formats table (blueprints for .insn pseudo mnemonic). */ |
776 | | |
777 | | const struct s390_opcode s390_opformats[] = |
778 | | { |
779 | | { "e", OP8(0x00LL), MASK_E, INSTR_E, 3, 0, 256, NULL }, |
780 | | { "ri", OP8(0x00LL), MASK_RI_RI, INSTR_RI_RI, 3, 0, 256, NULL }, |
781 | | { "rie", OP8(0x00LL), MASK_RIE_RRP, INSTR_RIE_RRP, 3, 0, 256, NULL }, |
782 | | { "ril", OP8(0x00LL), MASK_RIL_RP, INSTR_RIL_RP, 3, 0, 256, NULL }, |
783 | | { "rilu", OP8(0x00LL), MASK_RIL_RU, INSTR_RIL_RU, 3, 0, 256, NULL }, |
784 | | { "ris", OP8(0x00LL), MASK_RIS_RURDI, INSTR_RIS_RURDI, 3, 6, 256, NULL }, |
785 | | { "rr", OP8(0x00LL), MASK_RR_RR, INSTR_RR_RR, 3, 0, 256, NULL }, |
786 | | { "rre", OP8(0x00LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0, 256, NULL }, |
787 | | { "rrf", OP8(0x00LL), MASK_RRF_RURR, INSTR_RRF_RURR, 3, 0, 256, NULL }, |
788 | | { "rrs", OP8(0x00LL), MASK_RRS_RRRDU, INSTR_RRS_RRRDU, 3, 6, 256, NULL }, |
789 | | { "rs", OP8(0x00LL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0, 256, NULL }, |
790 | | { "rse", OP8(0x00LL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 3, 0, 256, NULL }, |
791 | | { "rsi", OP8(0x00LL), MASK_RSI_RRP, INSTR_RSI_RRP, 3, 0, 256, NULL }, |
792 | | { "rsy", OP8(0x00LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 3, 3, 256, NULL }, |
793 | | { "rx", OP8(0x00LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0, 256, NULL }, |
794 | | { "rxe", OP8(0x00LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 3, 0, 256, NULL }, |
795 | | { "rxf", OP8(0x00LL), MASK_RXF_RRRDR, INSTR_RXF_RRRDR, 3, 0, 256, NULL }, |
796 | | { "rxy", OP8(0x00LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 3, 3, 256, NULL }, |
797 | | { "s", OP8(0x00LL), MASK_S_RD, INSTR_S_RD, 3, 0, 256, NULL }, |
798 | | { "si", OP8(0x00LL), MASK_SI_URD, INSTR_SI_URD, 3, 0, 256, NULL }, |
799 | | { "siy", OP8(0x00LL), MASK_SIY_URD, INSTR_SIY_URD, 3, 3, 256, NULL }, |
800 | | { "sil", OP8(0x00LL), MASK_SIL_RDI, INSTR_SIL_RDI, 3, 6, 256, NULL }, |
801 | | { "ss", OP8(0x00LL), MASK_SS_RRRDRD, INSTR_SS_RRRDRD, 3, 0, 256, NULL }, |
802 | | { "sse", OP8(0x00LL), MASK_SSE_RDRD, INSTR_SSE_RDRD, 3, 0, 256, NULL }, |
803 | | { "ssf", OP8(0x00LL), MASK_SSF_RRDRD, INSTR_SSF_RRDRD, 3, 0, 256, NULL }, |
804 | | { "vrv", OP8(0x00LL), MASK_VRV_VVXRDU, INSTR_VRV_VVXRDU, 3, 9, 256, NULL }, |
805 | | { "vri", OP8(0x00LL), MASK_VRI_VVUUU, INSTR_VRI_VVUUU, 3, 9, 256, NULL }, |
806 | | { "vrx", OP8(0x00LL), MASK_VRX_VRRDU, INSTR_VRX_VRRDU, 3, 9, 256, NULL }, |
807 | | { "vrs", OP8(0x00LL), MASK_VRS_RVRDU, INSTR_VRS_RVRDU, 3, 9, 256, NULL }, |
808 | | { "vrr", OP8(0x00LL), MASK_VRR_VVV0UUU, INSTR_VRR_VVV0UUU, 3, 9, 256, NULL }, |
809 | | { "vsi", OP8(0x00LL), MASK_VSI_URDV, INSTR_VSI_URDV, 3, 10, 256, NULL }, |
810 | | }; |
811 | | |
812 | | const int s390_num_opformats = |
813 | | sizeof (s390_opformats) / sizeof (s390_opformats[0]); |
814 | | |
815 | | #include "s390-opc.tab" |