/* Table of opcodes for the sparc.

   Copyright (C) 1989-2025 Free Software Foundation, Inc.

   This file is part of the GNU opcodes library.

   This library is free software; you can redistribute it and/or modify

   it under the terms of the GNU General Public License as published by

   the Free Software Foundation; either version 3, or (at your option)

   any later version.

   It is distributed in the hope that it will be useful, but WITHOUT

   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY

   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public

   License for more details.

   You should have received a copy of the GNU General Public License

   along with this file; see the file COPYING.  If not, write to the

   Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,

   MA 02110-1301, USA.  */

/* FIXME-someday: perhaps the ,a's and such should be embedded in the

   instruction's name rather than the args.  This would make gas faster, pinsn

   slower, but would mess up some macros a bit.  xoxorich. */

#include "sysdep.h"

#include <stdio.h>

#include "opcode/sparc.h"

/* Some defines to make life easy.  */

#define MASK_V6   SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V6)

#define MASK_V7   SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V7)

#define MASK_V8   SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8)

#define MASK_LEON SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_LEON)

#define MASK_SPARCLET SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLET)

#define MASK_SPARCLITE  SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLITE)

#define MASK_V9   SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9)

#define MASK_V9A  SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A)

#define MASK_V9B  SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9B)

#define MASK_V9C  SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9C)

#define MASK_V9D  SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9D)

#define MASK_V9E  SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9E)

#define MASK_V9V  SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9V)

#define MASK_V9M  SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9M)

#define MASK_M8 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_M8)

/* Bit masks of architectures supporting the insn.  */

#define v6    (MASK_V6 | MASK_V7 | MASK_V8 | MASK_LEON \

       | MASK_SPARCLET | MASK_SPARCLITE \

       | MASK_V9 | MASK_V9A | MASK_V9B \

                         | MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M \

                         | MASK_M8)

/* v6 insns not supported on the sparclet.  */

#define v6notlet  (MASK_V6 | MASK_V7 | MASK_V8 | MASK_LEON \

       | MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B \

                         | MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M \

                         | MASK_M8)

#define v7    (MASK_V7 | MASK_V8 | MASK_LEON | MASK_SPARCLET \

       | MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B \

                         | MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M \

                         | MASK_M8)

/* Although not all insns are implemented in hardware, sparclite is defined

   to be a superset of v8.  Unimplemented insns trap and are then theoretically

   implemented in software.

   It's not clear that the same is true for sparclet, although the docs

   suggest it is.  Rather than complicating things, the sparclet assembler

   recognizes all v8 insns.  */

#define v8    (MASK_V8 | MASK_LEON | MASK_SPARCLET | MASK_SPARCLITE \

       | MASK_V9 | MASK_V9A | MASK_V9B \

                         | MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M \

                         | MASK_M8)

#define sparclet  (MASK_SPARCLET)

#define leon    (MASK_LEON)

/* sparclet insns supported by leon.  */

#define letandleon  (MASK_SPARCLET | MASK_LEON)

#define sparclite (MASK_SPARCLITE)

#define v9    (MASK_V9 | MASK_V9A | MASK_V9B \

                         | MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M \

                         | MASK_M8)

/* v9 insns supported by leon.  */

#define v9andleon (MASK_V9 | MASK_V9A | MASK_V9B \

                         | MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M \

                         | MASK_M8 | MASK_LEON)

#define v9a   (MASK_V9A | MASK_V9B \

                         | MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M \

                         | MASK_M8)

#define v9b   (MASK_V9B \

                         | MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M \

                         | MASK_M8)

#define v9c   (MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M \

                         | MASK_M8)

#define v9d   (MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M | MASK_M8)

#define v9e   (MASK_V9E | MASK_V9V | MASK_V9M | MASK_M8)

#define v9v   (MASK_V9V | MASK_V9M | MASK_M8)

#define v9m   (MASK_V9M | MASK_M8)

#define m8    (MASK_M8)

/* v6 insns not supported by v9.  */

#define v6notv9   (MASK_V6 | MASK_V7 | MASK_V8 | MASK_LEON \

       | MASK_SPARCLET | MASK_SPARCLITE)

/* v9a instructions which would appear to be aliases to v9's impdep's

   otherwise.  */

#define v9notv9a  (MASK_V9)

/* Hardware capability sets, used to keep sparc_opcode_archs easy to

   read.  */

#define HWS_V8 HWCAP_MUL32 | HWCAP_DIV32 | HWCAP_FSMULD

#define HWS_V9 HWS_V8 | HWCAP_POPC

#define HWS_VA HWS_V9 | HWCAP_VIS

#define HWS_VB HWS_VA | HWCAP_VIS2

#define HWS_VC HWS_VB | HWCAP_ASI_BLK_INIT

#define HWS_VD HWS_VC | HWCAP_FMAF | HWCAP_VIS3 | HWCAP_HPC

#define HWS_VE HWS_VD                                                   \

  | HWCAP_AES | HWCAP_DES | HWCAP_KASUMI | HWCAP_CAMELLIA               \

  | HWCAP_MD5 | HWCAP_SHA1 | HWCAP_SHA256 |HWCAP_SHA512 | HWCAP_MPMUL   \

  | HWCAP_MONT | HWCAP_CRC32C | HWCAP_CBCOND | HWCAP_PAUSE

#define HWS_VV HWS_VE | HWCAP_FJFMAU | HWCAP_IMA

#define HWS_VM HWS_VV

#define HWS_VM8 HWS_VM

#define HWS2_VM             \

  HWCAP2_VIS3B | HWCAP2_ADP | HWCAP2_SPARC5 | HWCAP2_MWAIT  \

  | HWCAP2_XMPMUL | HWCAP2_XMONT

#define HWS2_VM8 HWS2_VM \

  | HWCAP2_SPARC6 | HWCAP2_ONADDSUB | HWCAP2_ONMUL | HWCAP2_ONDIV \

  | HWCAP2_DICTUNP | HWCAP2_FPCMPSHL | HWCAP2_RLE | HWCAP2_SHA3

/* Table of opcode architectures.

   The order is defined in opcode/sparc.h.  */

const struct sparc_opcode_arch sparc_opcode_archs[] =

{

  { "v6", MASK_V6, 0, 0 },

  { "v7", MASK_V6 | MASK_V7, 0, 0 },

  { "v8", MASK_V6 | MASK_V7 | MASK_V8, HWS_V8, 0 },

  { "leon", MASK_V6 | MASK_V7 | MASK_V8 | MASK_LEON, HWS_V8, 0 },

  { "sparclet", MASK_V6 | MASK_V7 | MASK_V8 | MASK_SPARCLET, HWS_V8, 0 },

  { "sparclite", MASK_V6 | MASK_V7 | MASK_V8 | MASK_SPARCLITE, HWS_V8, 0 },

  /* ??? Don't some v8 priviledged insns conflict with v9?  */

  { "v9", MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9, HWS_V9, 0 },

  /* v9 with ultrasparc additions */

  { "v9a", MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A, HWS_VA, 0 },

  /* v9 with cheetah additions */

  { "v9b", MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A | MASK_V9B, HWS_VB, 0 },

  /* v9 with UA2005 and T1 additions.  */

  { "v9c", (MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A | MASK_V9B

            | MASK_V9C), HWS_VC, 0 },

  /* v9 with UA2007 and T3 additions.  */

  { "v9d", (MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A | MASK_V9B

            | MASK_V9C | MASK_V9D), HWS_VD, 0 },

  /* v9 with OSA2011 and T4 additions modulus integer multiply-add.  */

  { "v9e", (MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A | MASK_V9B

            | MASK_V9C | MASK_V9D | MASK_V9E), HWS_VE, 0 },

  /* V9 with OSA2011 and T4 additions, integer multiply and Fujitsu fp

     multiply-add.  */

  { "v9v", (MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A | MASK_V9B

            | MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V), HWS_VV, 0 },

  /* v9 with OSA2015 and M7 additions.  */

  { "v9m", (MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A | MASK_V9B

            | MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M), HWS_VM, HWS2_VM },

  /* v9 with OSA2017 and M8 additions.  */

  { "m8", (MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A | MASK_V9B

           | MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M | MASK_M8),

    HWS_VM8, HWS2_VM8 },

  { NULL, 0, 0, 0 }

};

/* Given NAME, return it's architecture entry.  */

enum sparc_opcode_arch_val

sparc_opcode_lookup_arch (const char *name)

{

  const struct sparc_opcode_arch *p;

  for (p = &sparc_opcode_archs[0]; p->name; ++p)

    if (strcmp (name, p->name) == 0)

      return (enum sparc_opcode_arch_val) (p - &sparc_opcode_archs[0]);

  return SPARC_OPCODE_ARCH_BAD;

}

/* Branch condition field.  */

#define COND(x)   (((x) & 0xf) << 25)

/* Compare And Branch condition field.  */

#define CBCOND(x) (((x) & 0x1f) << 25)

/* v9: Move (MOVcc and FMOVcc) condition field.  */

#define MCOND(x,i_or_f) ((((i_or_f) & 1) << 18) | (((x) >> 11) & (0xf << 14))) /* v9 */

/* v9: Move register (MOVRcc and FMOVRcc) condition field.  */

#define RCOND(x)  (((x) & 0x7) << 10) /* v9 */

#define CONDA (COND (0x8))

#define CONDCC  (COND (0xd))

#define CONDCS  (COND (0x5))

#define CONDE (COND (0x1))

#define CONDG (COND (0xa))

#define CONDGE  (COND (0xb))

#define CONDGU  (COND (0xc))

#define CONDL (COND (0x3))

#define CONDLE  (COND (0x2))

#define CONDLEU (COND (0x4))

#define CONDN (COND (0x0))

#define CONDNE  (COND (0x9))

#define CONDNEG (COND (0x6))

#define CONDPOS (COND (0xe))

#define CONDVC  (COND (0xf))

#define CONDVS  (COND (0x7))

#define CONDNZ  CONDNE

#define CONDZ CONDE

#define CONDGEU CONDCC

#define CONDLU  CONDCS

#define FCONDA    (COND (0x8))

#define FCONDE    (COND (0x9))

#define FCONDG    (COND (0x6))

#define FCONDGE   (COND (0xb))

#define FCONDL    (COND (0x4))

#define FCONDLE   (COND (0xd))

#define FCONDLG   (COND (0x2))

#define FCONDN    (COND (0x0))

#define FCONDNE   (COND (0x1))

#define FCONDO    (COND (0xf))

#define FCONDU    (COND (0x7))

#define FCONDUE   (COND (0xa))

#define FCONDUG   (COND (0x5))

#define FCONDUGE  (COND (0xc))

#define FCONDUL   (COND (0x3))

#define FCONDULE  (COND (0xe))

#define FCONDNZ FCONDNE

#define FCONDZ  FCONDE

#define ICC     (0) /* v9 */

#define XCC     (1 << 12) /* v9 */

#define CBCOND_XCC  (1 << 21)

#define FCC(x)    (((x) & 0x3) << 11) /* v9 */

#define FBFCC(x)  (((x) & 0x3) << 20) /* v9 */

/* The order of the opcodes in the table is significant:

  * The assembler requires that all instances of the same mnemonic must

  be consecutive. If they aren't, the assembler will bomb at runtime.

  * The disassembler should not care about the order of the opcodes.  */

/* Entries for commutative arithmetic operations.  */

/* ??? More entries can make use of this.  */

#define COMMUTEOP(opcode, op3, arch_mask) \

{ opcode, F3(2, op3, 0), F3(~2, ~op3, ~0)|ASI(~0),  "1,2,d", 0, 0, 0, arch_mask }, \

{ opcode, F3(2, op3, 1), F3(~2, ~op3, ~1),    "1,i,d", 0, 0, 0, arch_mask }, \

{ opcode, F3(2, op3, 1), F3(~2, ~op3, ~1),    "i,1,d", 0, 0, 0, arch_mask }

const struct sparc_opcode sparc_opcodes[] = {

{ "ld", F3(3, 0x00, 0), F3(~3, ~0x00, ~0),    "[1+2],d", 0, 0, 0, v6 },

{ "ld", F3(3, 0x00, 0), F3(~3, ~0x00, ~0)|RS2_G0, "[1],d", 0, 0, 0, v6 }, /* ld [rs1+%g0],d */

{ "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1),    "[1+i],d", 0, 0, 0, v6 },

{ "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1),    "[i+1],d", 0, 0, 0, v6 },

{ "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|RS1_G0, "[i],d", 0, 0, 0, v6 },

{ "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|SIMM13(~0), "[1],d", 0, 0, 0, v6 }, /* ld [rs1+0],d */

{ "ld", F3(3, 0x20, 0), F3(~3, ~0x20, ~0),    "[1+2],g", 0, 0, 0, v6 },

{ "ld", F3(3, 0x20, 0), F3(~3, ~0x20, ~0)|RS2_G0, "[1],g", 0, 0, 0, v6 }, /* ld [rs1+%g0],d */

{ "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1),    "[1+i],g", 0, 0, 0, v6 },

{ "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1),    "[i+1],g", 0, 0, 0, v6 },

{ "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1)|RS1_G0, "[i],g", 0, 0, 0, v6 },

{ "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1)|SIMM13(~0), "[1],g", 0, 0, 0, v6 }, /* ld [rs1+0],d */

{ "ld", F3(3, 0x21, 0), F3(~3, ~0x21, ~0)|RD(~0), "[1+2],F", 0, 0, 0, v6 },

{ "ld", F3(3, 0x21, 0), F3(~3, ~0x21, ~0)|RS2_G0|RD(~0),"[1],F", 0, 0, 0, v6 }, /* ld [rs1+%g0],d */

{ "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RD(~0), "[1+i],F", 0, 0, 0, v6 },

{ "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RD(~0), "[i+1],F", 0, 0, 0, v6 },

{ "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RS1_G0|RD(~0),"[i],F", 0, 0, 0, v6 },

{ "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|SIMM13(~0)|RD(~0),"[1],F", 0, 0, 0, v6 }, /* ld [rs1+0],d */

{ "ld", F3(3, 0x30, 0), F3(~3, ~0x30, ~0),    "[1+2],D", 0, 0, 0, v6notv9 },

{ "ld", F3(3, 0x30, 0), F3(~3, ~0x30, ~0)|RS2_G0, "[1],D", 0, 0, 0, v6notv9 }, /* ld [rs1+%g0],d */

{ "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1),    "[1+i],D", 0, 0, 0, v6notv9 },

{ "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1),    "[i+1],D", 0, 0, 0, v6notv9 },

{ "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|RS1_G0, "[i],D", 0, 0, 0, v6notv9 },

{ "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|SIMM13(~0), "[1],D", 0, 0, 0, v6notv9 }, /* ld [rs1+0],d */

{ "ld", F3(3, 0x31, 0), F3(~3, ~0x31, ~0),    "[1+2],C", 0, 0, 0, v6notv9 },

{ "ld", F3(3, 0x31, 0), F3(~3, ~0x31, ~0)|RS2_G0, "[1],C", 0, 0, 0, v6notv9 }, /* ld [rs1+%g0],d */

{ "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1),    "[1+i],C", 0, 0, 0, v6notv9 },

{ "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1),    "[i+1],C", 0, 0, 0, v6notv9 },

{ "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1)|RS1_G0, "[i],C", 0, 0, 0, v6notv9 },

{ "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1)|SIMM13(~0), "[1],C", 0, 0, 0, v6notv9 }, /* ld [rs1+0],d */

/* The v9 LDUW is the same as the old 'ld' opcode, it is not the same as the

   'ld' pseudo-op in v9.  */

{ "lduw", F3(3, 0x00, 0), F3(~3, ~0x00, ~0),    "[1+2],d", F_ALIAS, 0, 0, v9 },

{ "lduw", F3(3, 0x00, 0), F3(~3, ~0x00, ~0)|RS2_G0, "[1],d", F_ALIAS, 0, 0, v9 }, /* ld [rs1+%g0],d */

{ "lduw", F3(3, 0x00, 1), F3(~3, ~0x00, ~1),    "[1+i],d", F_ALIAS, 0, 0, v9 },

{ "lduw", F3(3, 0x00, 1), F3(~3, ~0x00, ~1),    "[i+1],d", F_ALIAS, 0, 0, v9 },

{ "lduw", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|RS1_G0, "[i],d", F_ALIAS, 0, 0, v9 },

{ "lduw", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|SIMM13(~0), "[1],d", F_ALIAS, 0, 0, v9 }, /* ld [rs1+0],d */

{ "ldtw", F3(3, 0x03, 0), F3(~3, ~0x03, ~0)|ASI(~0),  "[1+2],d", 0, 0, 0, v9 },

{ "ldtw", F3(3, 0x03, 0), F3(~3, ~0x03, ~0)|ASI_RS2(~0),  "[1],d", 0, 0, 0, v9 }, /* ldd [rs1+%g0],d */

{ "ldtw", F3(3, 0x03, 1), F3(~3, ~0x03, ~1),    "[1+i],d", 0, 0, 0, v9 },

{ "ldtw", F3(3, 0x03, 1), F3(~3, ~0x03, ~1),    "[i+1],d", 0, 0, 0, v9 },

{ "ldtw", F3(3, 0x03, 1), F3(~3, ~0x03, ~1)|RS1_G0, "[i],d", 0, 0, 0, v9 },

{ "ldtw", F3(3, 0x03, 1), F3(~3, ~0x03, ~1)|SIMM13(~0), "[1],d", 0, 0, 0, v9 }, /* ldd [rs1+0],d */

{ "ldd",  F3(3, 0x03, 0), F3(~3, ~0x03, ~0)|ASI(~0),  "[1+2],d", F_ALIAS, 0, 0, v6 },

{ "ldd",  F3(3, 0x03, 0), F3(~3, ~0x03, ~0)|ASI_RS2(~0),  "[1],d", F_ALIAS, 0, 0, v6 }, /* ldd [rs1+%g0],d */

{ "ldd",  F3(3, 0x03, 1), F3(~3, ~0x03, ~1),    "[1+i],d", F_ALIAS, 0, 0, v6 },

{ "ldd",  F3(3, 0x03, 1), F3(~3, ~0x03, ~1),    "[i+1],d", F_ALIAS, 0, 0, v6 },

{ "ldd",  F3(3, 0x03, 1), F3(~3, ~0x03, ~1)|RS1_G0, "[i],d", F_ALIAS, 0, 0, v6 },

{ "ldd",  F3(3, 0x03, 1), F3(~3, ~0x03, ~1)|SIMM13(~0), "[1],d", F_ALIAS, 0, 0, v6 }, /* ldd [rs1+0],d */

{ "ldd",  F3(3, 0x23, 0), F3(~3, ~0x23, ~0)|ASI(~0),  "[1+2],H", F_ALIAS, 0, 0, v6 },

{ "ldd",  F3(3, 0x23, 0), F3(~3, ~0x23, ~0)|ASI_RS2(~0),  "[1],H", F_ALIAS, 0, 0, v6 }, /* ldd [rs1+%g0],d */

{ "ldd",  F3(3, 0x23, 1), F3(~3, ~0x23, ~1),    "[1+i],H", F_ALIAS, 0, 0, v6 },

{ "ldd",  F3(3, 0x23, 1), F3(~3, ~0x23, ~1),    "[i+1],H", F_ALIAS, 0, 0, v6 },

{ "ldd",  F3(3, 0x23, 1), F3(~3, ~0x23, ~1)|RS1_G0, "[i],H", F_ALIAS, 0, 0, v6 },

{ "ldd",  F3(3, 0x23, 1), F3(~3, ~0x23, ~1)|SIMM13(~0), "[1],H", F_ALIAS, 0, 0, v6 }, /* ldd [rs1+0],d */

{ "ldd",  F3(3, 0x33, 0), F3(~3, ~0x33, ~0)|ASI(~0),  "[1+2],D", 0, 0, 0, v6notv9 },

{ "ldd",  F3(3, 0x33, 0), F3(~3, ~0x33, ~0)|ASI_RS2(~0),  "[1],D", 0, 0, 0, v6notv9 }, /* ldd [rs1+%g0],d */

{ "ldd",  F3(3, 0x33, 1), F3(~3, ~0x33, ~1),    "[1+i],D", 0, 0, 0, v6notv9 },

{ "ldd",  F3(3, 0x33, 1), F3(~3, ~0x33, ~1),    "[i+1],D", 0, 0, 0, v6notv9 },

{ "ldd",  F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|RS1_G0, "[i],D", 0, 0, 0, v6notv9 },

{ "ldd",  F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|SIMM13(~0), "[1],D", 0, 0, 0, v6notv9 }, /* ldd [rs1+0],d */

{ "ldq",  F3(3, 0x22, 0), F3(~3, ~0x22, ~0)|ASI(~0),  "[1+2],J", 0, 0, 0, v9 },

{ "ldq",  F3(3, 0x22, 0), F3(~3, ~0x22, ~0)|ASI_RS2(~0),  "[1],J", 0, 0, 0, v9 }, /* ldd [rs1+%g0],d */

{ "ldq",  F3(3, 0x22, 1), F3(~3, ~0x22, ~1),    "[1+i],J", 0, 0, 0, v9 },

{ "ldq",  F3(3, 0x22, 1), F3(~3, ~0x22, ~1),    "[i+1],J", 0, 0, 0, v9 },

{ "ldq",  F3(3, 0x22, 1), F3(~3, ~0x22, ~1)|RS1_G0, "[i],J", 0, 0, 0, v9 },

{ "ldq",  F3(3, 0x22, 1), F3(~3, ~0x22, ~1)|SIMM13(~0), "[1],J", 0, 0, 0, v9 }, /* ldd [rs1+0],d */

{ "ldsb", F3(3, 0x09, 0), F3(~3, ~0x09, ~0)|ASI(~0),  "[1+2],d", 0, 0, 0, v6 },

{ "ldsb", F3(3, 0x09, 0), F3(~3, ~0x09, ~0)|ASI_RS2(~0),  "[1],d", 0, 0, 0, v6 }, /* ldsb [rs1+%g0],d */

{ "ldsb", F3(3, 0x09, 1), F3(~3, ~0x09, ~1),    "[1+i],d", 0, 0, 0, v6 },

{ "ldsb", F3(3, 0x09, 1), F3(~3, ~0x09, ~1),    "[i+1],d", 0, 0, 0, v6 },

{ "ldsb", F3(3, 0x09, 1), F3(~3, ~0x09, ~1)|RS1_G0, "[i],d", 0, 0, 0, v6 },

{ "ldsb", F3(3, 0x09, 1), F3(~3, ~0x09, ~1)|SIMM13(~0), "[1],d", 0, 0, 0, v6 }, /* ldsb [rs1+0],d */

{ "ldsh", F3(3, 0x0a, 0), F3(~3, ~0x0a, ~0)|ASI_RS2(~0),  "[1],d", 0, 0, 0, v6 }, /* ldsh [rs1+%g0],d */

{ "ldsh", F3(3, 0x0a, 0), F3(~3, ~0x0a, ~0)|ASI(~0),  "[1+2],d", 0, 0, 0, v6 },

{ "ldsh", F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1),    "[1+i],d", 0, 0, 0, v6 },

{ "ldsh", F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1),    "[i+1],d", 0, 0, 0, v6 },

{ "ldsh", F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1)|RS1_G0, "[i],d", 0, 0, 0, v6 },

{ "ldsh", F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1)|SIMM13(~0), "[1],d", 0, 0, 0, v6 }, /* ldsh [rs1+0],d */

{ "ldstub", F3(3, 0x0d, 0), F3(~3, ~0x0d, ~0)|ASI(~0),  "[1+2],d", 0, 0, 0, v6 },

{ "ldstub", F3(3, 0x0d, 0), F3(~3, ~0x0d, ~0)|ASI_RS2(~0),  "[1],d", 0, 0, 0, v6 }, /* ldstub [rs1+%g0],d */

{ "ldstub", F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1),    "[1+i],d", 0, 0, 0, v6 },

{ "ldstub", F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1),    "[i+1],d", 0, 0, 0, v6 },

{ "ldstub", F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1)|RS1_G0, "[i],d", 0, 0, 0, v6 },

{ "ldstub", F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1)|SIMM13(~0), "[1],d", 0, 0, 0, v6 }, /* ldstub [rs1+0],d */

{ "ldsw", F3(3, 0x08, 0), F3(~3, ~0x08, ~0)|ASI(~0),  "[1+2],d", 0, 0, 0, v9 },

{ "ldsw", F3(3, 0x08, 0), F3(~3, ~0x08, ~0)|ASI_RS2(~0),  "[1],d", 0, 0, 0, v9 }, /* ldsw [rs1+%g0],d */

{ "ldsw", F3(3, 0x08, 1), F3(~3, ~0x08, ~1),    "[1+i],d", 0, 0, 0, v9 },

{ "ldsw", F3(3, 0x08, 1), F3(~3, ~0x08, ~1),    "[i+1],d", 0, 0, 0, v9 },

{ "ldsw", F3(3, 0x08, 1), F3(~3, ~0x08, ~1)|RS1_G0, "[i],d", 0, 0, 0, v9 },

{ "ldsw", F3(3, 0x08, 1), F3(~3, ~0x08, ~1)|SIMM13(~0), "[1],d", 0, 0, 0, v9 }, /* ldsw [rs1+0],d */

{ "ldub", F3(3, 0x01, 0), F3(~3, ~0x01, ~0)|ASI(~0),  "[1+2],d", 0, 0, 0, v6 },

{ "ldub", F3(3, 0x01, 0), F3(~3, ~0x01, ~0)|ASI_RS2(~0),  "[1],d", 0, 0, 0, v6 }, /* ldub [rs1+%g0],d */

{ "ldub", F3(3, 0x01, 1), F3(~3, ~0x01, ~1),    "[1+i],d", 0, 0, 0, v6 },

{ "ldub", F3(3, 0x01, 1), F3(~3, ~0x01, ~1),    "[i+1],d", 0, 0, 0, v6 },

{ "ldub", F3(3, 0x01, 1), F3(~3, ~0x01, ~1)|RS1_G0, "[i],d", 0, 0, 0, v6 },

{ "ldub", F3(3, 0x01, 1), F3(~3, ~0x01, ~1)|SIMM13(~0), "[1],d", 0, 0, 0, v6 }, /* ldub [rs1+0],d */

{ "lduh", F3(3, 0x02, 0), F3(~3, ~0x02, ~0)|ASI(~0),  "[1+2],d", 0, 0, 0, v6 },

{ "lduh", F3(3, 0x02, 0), F3(~3, ~0x02, ~0)|ASI_RS2(~0),  "[1],d", 0, 0, 0, v6 }, /* lduh [rs1+%g0],d */

{ "lduh", F3(3, 0x02, 1), F3(~3, ~0x02, ~1),    "[1+i],d", 0, 0, 0, v6 },

{ "lduh", F3(3, 0x02, 1), F3(~3, ~0x02, ~1),    "[i+1],d", 0, 0, 0, v6 },

{ "lduh", F3(3, 0x02, 1), F3(~3, ~0x02, ~1)|RS1_G0, "[i],d", 0, 0, 0, v6 },

{ "lduh", F3(3, 0x02, 1), F3(~3, ~0x02, ~1)|SIMM13(~0), "[1],d", 0, 0, 0, v6 }, /* lduh [rs1+0],d */

{ "ldx",  F3(3, 0x0b, 0), F3(~3, ~0x0b, ~0)|ASI(~0),  "[1+2],d", 0, 0, 0, v9 },

{ "ldx",  F3(3, 0x0b, 0), F3(~3, ~0x0b, ~0)|ASI_RS2(~0),  "[1],d", 0, 0, 0, v9 }, /* ldx [rs1+%g0],d */

{ "ldx",  F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1),    "[1+i],d", 0, 0, 0, v9 },

{ "ldx",  F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1),    "[i+1],d", 0, 0, 0, v9 },

{ "ldx",  F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1)|RS1_G0, "[i],d", 0, 0, 0, v9 },

{ "ldx",  F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1)|SIMM13(~0), "[1],d", 0, 0, 0, v9 }, /* ldx [rs1+0],d */

{ "ldx",  F3(3, 0x21, 0)|RD(1), F3(~3, ~0x21, ~0)|RD(~1), "[1+2],F", 0, 0, 0, v9 },

{ "ldx",  F3(3, 0x21, 0)|RD(1), F3(~3, ~0x21, ~0)|RS2_G0|RD(~1),  "[1],F", 0, 0, 0, v9 }, /* ld [rs1+%g0],d */

{ "ldx",  F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|RD(~1), "[1+i],F", 0, 0, 0, v9 },

{ "ldx",  F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|RD(~1), "[i+1],F", 0, 0, 0, v9 },

{ "ldx",  F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|RS1_G0|RD(~1),  "[i],F", 0, 0, 0, v9 },

{ "ldx",  F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|SIMM13(~0)|RD(~1),"[1],F", 0, 0, 0, v9 }, /* ld [rs1+0],d */

{ "ldx", F3(3, 0x21, 0)|RD(3), F3(~3, ~0x21, ~0)|RD(~3), "[1+2],(", 0, HWCAP_VIS3, HWCAP2_VIS3B, v9d }, /* ldx [rs1+rs2],%efsr */

{ "ldx", F3(3, 0x21, 0)|RD(3), F3(~3, ~0x21, ~0)|RS2_G0|RD(~3),"[1],(", 0, HWCAP_VIS3, HWCAP2_VIS3B, v9d }, /* ldx [rs1],%efsr */

{ "ldx", F3(3, 0x21, 1)|RD(3), F3(~3, ~0x21, ~1)|RD(~3), "[1+i],(", 0, HWCAP_VIS3, HWCAP2_VIS3B, v9d }, /* ldx [%rs1+0],%efsr */

{ "ldx", F3(3, 0x21, 1)|RD(3), F3(~3, ~0x21, ~1)|RD(~3), "[i+1],(", 0, HWCAP_VIS3, HWCAP2_VIS3B, v9d }, /* ldx [0+%rs1],%efsr */

{ "ldx", F3(3, 0x21, 1)|RD(3), F3(~3, ~0x21, ~1)|RS1_G0|RD(~3),"[i],(", 0, HWCAP_VIS3, HWCAP2_VIS3B, v9d }, /* ldx [0],%efsr */

{ "ldx", F3(3, 0x21, 1)|RD(3), F3(~3, ~0x21, ~1)|SIMM13(~0)|RD(~3),"[1],(", 0, HWCAP_VIS3, HWCAP2_VIS3B, v9d }, /* ldx [%rs1], %efsr */

{ "lda",  F3(3, 0x10, 0), F3(~3, ~0x10, ~0),    "[1+2]A,d", 0, 0, 0, v6 },

{ "lda",  F3(3, 0x10, 0), F3(~3, ~0x10, ~0)|RS2_G0, "[1]A,d", 0, 0, 0, v6 }, /* lda [rs1+%g0],d */

{ "lda",  F3(3, 0x10, 1), F3(~3, ~0x10, ~1),    "[1+i]o,d", 0, 0, 0, v9 },

{ "lda",  F3(3, 0x10, 1), F3(~3, ~0x10, ~1),    "[i+1]o,d", 0, 0, 0, v9 },

{ "lda",  F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|RS1_G0, "[i]o,d", 0, 0, 0, v9 },

{ "lda",  F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|SIMM13(~0), "[1]o,d", 0, 0, 0, v9 }, /* ld [rs1+0],d */

{ "lda",  F3(3, 0x30, 0), F3(~3, ~0x30, ~0),    "[1+2]A,g", 0, 0, 0, v9 },

{ "lda",  F3(3, 0x30, 0), F3(~3, ~0x30, ~0)|RS2_G0, "[1]A,g", 0, 0, 0, v9 }, /* lda [rs1+%g0],d */

{ "lda",  F3(3, 0x30, 1), F3(~3, ~0x30, ~1),    "[1+i]o,g", 0, 0, 0, v9 },

{ "lda",  F3(3, 0x30, 1), F3(~3, ~0x30, ~1),    "[i+1]o,g", 0, 0, 0, v9 },

{ "lda",  F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|RS1_G0, "[i]o,g", 0, 0, 0, v9 },

{ "lda",  F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|SIMM13(~0), "[1]o,g", 0, 0, 0, v9 }, /* ld [rs1+0],d */

/* Note that the LDTXA instructions share an opcode with the

   (deprecated) LDTWA instructions below.  They are differenciated by

   the combination of the `i' instruction field and the ASI used in

   the instruction.  */

#define ldtxa(asi) \

{ "ldtxa",  F3(3, 0x13, 0)|ASI((asi)), F3(~3, ~0x13, ~0)|ASI(~(asi)), "[1+2]A,d", 0, HWCAP_ASI_BLK_INIT, 0, v9c }, \

{ "ldtxa",  F3(3, 0x13, 0)|ASI((asi)), F3(~3, ~0x13, ~0)|ASI(~(asi))|RS2_G0, "[1]A,d", 0, HWCAP_ASI_BLK_INIT, 0, v9c }

ldtxa (0x22), /* #ASI_TWINX_AIUP  */

ldtxa (0x23), /* #ASI_TWINX_AIUS  */

ldtxa (0x26), /* #ASI_TWINX_REAL  */

ldtxa (0x27), /* #ASI_TWINX_N  */

ldtxa (0x2A), /* #ASI_TWINX_AIUP_L  */

ldtxa (0x2B), /* #ASI_TWINX_AIUS_L  */

ldtxa (0x2E), /* #ASI_TWINX_REAL_L  */

ldtxa (0x2F), /* #ASI_TWINX_NL  */

ldtxa (0xE2), /* #ASI_TWINX_P  */

ldtxa (0xE3), /* #ASI_TWINX_S  */

ldtxa (0xEA), /* #ASI_TWINX_PL  */

ldtxa (0xEB), /* #ASI_TWINX_SL  */

{ "ldtwa",  F3(3, 0x13, 0), F3(~3, ~0x13, ~0),    "[1+2]A,d", 0, 0, 0, v9 },

{ "ldtwa",  F3(3, 0x13, 0), F3(~3, ~0x13, ~0)|RS2_G0, "[1]A,d", 0, 0, 0, v9 }, /* ldda [rs1+%g0],d */

{ "ldtwa",  F3(3, 0x13, 1), F3(~3, ~0x13, ~1),    "[1+i]o,d", 0, 0, 0, v9 },

{ "ldtwa",  F3(3, 0x13, 1), F3(~3, ~0x13, ~1),    "[i+1]o,d", 0, 0, 0, v9 },

{ "ldtwa",  F3(3, 0x13, 1), F3(~3, ~0x13, ~1)|RS1_G0, "[i]o,d", 0, 0, 0, v9 },

{ "ldtwa",  F3(3, 0x13, 1), F3(~3, ~0x13, ~1)|SIMM13(~0), "[1]o,d", 0, 0, 0, v9 }, /* ld [rs1+0],d */

{ "ldda", F3(3, 0x13, 0), F3(~3, ~0x13, ~0),    "[1+2]A,d", F_ALIAS, 0, 0, v6 },

{ "ldda", F3(3, 0x13, 0), F3(~3, ~0x13, ~0)|RS2_G0, "[1]A,d", F_ALIAS, 0, 0, v6 }, /* ldda [rs1+%g0],d */

{ "ldda", F3(3, 0x13, 1), F3(~3, ~0x13, ~1),    "[1+i]o,d", F_ALIAS, 0, 0, v9 },

{ "ldda", F3(3, 0x13, 1), F3(~3, ~0x13, ~1),    "[i+1]o,d", F_ALIAS, 0, 0, v9 },

{ "ldda", F3(3, 0x13, 1), F3(~3, ~0x13, ~1)|RS1_G0, "[i]o,d", F_ALIAS, 0, 0, v9 },

{ "ldda", F3(3, 0x13, 1), F3(~3, ~0x13, ~1)|SIMM13(~0), "[1]o,d", F_ALIAS, 0, 0, v9 }, /* ld [rs1+0],d */

{ "ldda", F3(3, 0x33, 0), F3(~3, ~0x33, ~0),    "[1+2]A,H", 0, 0, 0, v9 },

{ "ldda", F3(3, 0x33, 0), F3(~3, ~0x33, ~0)|RS2_G0, "[1]A,H", 0, 0, 0, v9 }, /* ldda [rs1+%g0],d */

{ "ldda", F3(3, 0x33, 1), F3(~3, ~0x33, ~1),    "[1+i]o,H", 0, 0, 0, v9 },

{ "ldda", F3(3, 0x33, 1), F3(~3, ~0x33, ~1),    "[i+1]o,H", 0, 0, 0, v9 },

{ "ldda", F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|RS1_G0, "[i]o,H", 0, 0, 0, v9 },

{ "ldda", F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|SIMM13(~0), "[1]o,H", 0, 0, 0, v9 }, /* ld [rs1+0],d */

{ "ldqa", F3(3, 0x32, 0), F3(~3, ~0x32, ~0),    "[1+2]A,J", 0, 0, 0, v9 },

{ "ldqa", F3(3, 0x32, 0), F3(~3, ~0x32, ~0)|RS2_G0, "[1]A,J", 0, 0, 0, v9 }, /* ldd [rs1+%g0],d */

{ "ldqa", F3(3, 0x32, 1), F3(~3, ~0x32, ~1),    "[1+i]o,J", 0, 0, 0, v9 },

{ "ldqa", F3(3, 0x32, 1), F3(~3, ~0x32, ~1),    "[i+1]o,J", 0, 0, 0, v9 },

{ "ldqa", F3(3, 0x32, 1), F3(~3, ~0x32, ~1)|RS1_G0, "[i]o,J", 0, 0, 0, v9 },

{ "ldqa", F3(3, 0x32, 1), F3(~3, ~0x32, ~1)|SIMM13(~0), "[1]o,J", 0, 0, 0, v9 }, /* ldd [rs1+0],d */

{ "ldsba",  F3(3, 0x19, 0), F3(~3, ~0x19, ~0),    "[1+2]A,d", 0, 0, 0, v6 },

{ "ldsba",  F3(3, 0x19, 0), F3(~3, ~0x19, ~0)|RS2_G0, "[1]A,d", 0, 0, 0, v6 }, /* ldsba [rs1+%g0],d */

{ "ldsba",  F3(3, 0x19, 1), F3(~3, ~0x19, ~1),    "[1+i]o,d", 0, 0, 0, v9 },

{ "ldsba",  F3(3, 0x19, 1), F3(~3, ~0x19, ~1),    "[i+1]o,d", 0, 0, 0, v9 },

{ "ldsba",  F3(3, 0x19, 1), F3(~3, ~0x19, ~1)|RS1_G0, "[i]o,d", 0, 0, 0, v9 },

{ "ldsba",  F3(3, 0x19, 1), F3(~3, ~0x19, ~1)|SIMM13(~0), "[1]o,d", 0, 0, 0, v9 }, /* ld [rs1+0],d */

{ "ldsha",  F3(3, 0x1a, 0), F3(~3, ~0x1a, ~0),    "[1+2]A,d", 0, 0, 0, v6 },

{ "ldsha",  F3(3, 0x1a, 0), F3(~3, ~0x1a, ~0)|RS2_G0, "[1]A,d", 0, 0, 0, v6 }, /* ldsha [rs1+%g0],d */

{ "ldsha",  F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1),    "[1+i]o,d", 0, 0, 0, v9 },

{ "ldsha",  F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1),    "[i+1]o,d", 0, 0, 0, v9 },

{ "ldsha",  F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1)|RS1_G0, "[i]o,d", 0, 0, 0, v9 },

{ "ldsha",  F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1)|SIMM13(~0), "[1]o,d", 0, 0, 0, v9 }, /* ld [rs1+0],d */

{ "ldstuba",  F3(3, 0x1d, 0), F3(~3, ~0x1d, ~0),    "[1+2]A,d", 0, 0, 0, v6 },

{ "ldstuba",  F3(3, 0x1d, 0), F3(~3, ~0x1d, ~0)|RS2_G0, "[1]A,d", 0, 0, 0, v6 }, /* ldstuba [rs1+%g0],d */

{ "ldstuba",  F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1),    "[1+i]o,d", 0, 0, 0, v9 },

{ "ldstuba",  F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1),    "[i+1]o,d", 0, 0, 0, v9 },

{ "ldstuba",  F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1)|RS1_G0, "[i]o,d", 0, 0, 0, v9 },

{ "ldstuba",  F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1)|SIMM13(~0), "[1]o,d", 0, 0, 0, v9 }, /* ld [rs1+0],d */

{ "ldswa",  F3(3, 0x18, 0), F3(~3, ~0x18, ~0),    "[1+2]A,d", 0, 0, 0, v9 },

{ "ldswa",  F3(3, 0x18, 0), F3(~3, ~0x18, ~0)|RS2_G0, "[1]A,d", 0, 0, 0, v9 }, /* lda [rs1+%g0],d */

{ "ldswa",  F3(3, 0x18, 1), F3(~3, ~0x18, ~1),    "[1+i]o,d", 0, 0, 0, v9 },

{ "ldswa",  F3(3, 0x18, 1), F3(~3, ~0x18, ~1),    "[i+1]o,d", 0, 0, 0, v9 },

{ "ldswa",  F3(3, 0x18, 1), F3(~3, ~0x18, ~1)|RS1_G0, "[i]o,d", 0, 0, 0, v9 },

{ "ldswa",  F3(3, 0x18, 1), F3(~3, ~0x18, ~1)|SIMM13(~0), "[1]o,d", 0, 0, 0, v9 }, /* ld [rs1+0],d */

{ "lduba",  F3(3, 0x11, 0), F3(~3, ~0x11, ~0),    "[1+2]A,d", 0, 0, 0, v6 },

{ "lduba",  F3(3, 0x11, 0), F3(~3, ~0x11, ~0)|RS2_G0, "[1]A,d", 0, 0, 0, v6 }, /* lduba [rs1+%g0],d */

{ "lduba",  F3(3, 0x11, 1), F3(~3, ~0x11, ~1),    "[1+i]o,d", 0, 0, 0, v9 },

{ "lduba",  F3(3, 0x11, 1), F3(~3, ~0x11, ~1),    "[i+1]o,d", 0, 0, 0, v9 },

{ "lduba",  F3(3, 0x11, 1), F3(~3, ~0x11, ~1)|RS1_G0, "[i]o,d", 0, 0, 0, v9 },

{ "lduba",  F3(3, 0x11, 1), F3(~3, ~0x11, ~1)|SIMM13(~0), "[1]o,d", 0, 0, 0, v9 }, /* ld [rs1+0],d */

{ "lduha",  F3(3, 0x12, 0), F3(~3, ~0x12, ~0),    "[1+2]A,d", 0, 0, 0, v6 },

{ "lduha",  F3(3, 0x12, 0), F3(~3, ~0x12, ~0)|RS2_G0, "[1]A,d", 0, 0, 0, v6 }, /* lduha [rs1+%g0],d */

{ "lduha",  F3(3, 0x12, 1), F3(~3, ~0x12, ~1),    "[1+i]o,d", 0, 0, 0, v9 },

{ "lduha",  F3(3, 0x12, 1), F3(~3, ~0x12, ~1),    "[i+1]o,d", 0, 0, 0, v9 },

{ "lduha",  F3(3, 0x12, 1), F3(~3, ~0x12, ~1)|RS1_G0, "[i]o,d", 0, 0, 0, v9 },

{ "lduha",  F3(3, 0x12, 1), F3(~3, ~0x12, ~1)|SIMM13(~0), "[1]o,d", 0, 0, 0, v9 }, /* ld [rs1+0],d */

{ "lduwa",  F3(3, 0x10, 0), F3(~3, ~0x10, ~0),    "[1+2]A,d", F_ALIAS, 0, 0, v9 }, /* lduwa === lda */

{ "lduwa",  F3(3, 0x10, 0), F3(~3, ~0x10, ~0)|RS2_G0, "[1]A,d", F_ALIAS, 0, 0, v9 }, /* lda [rs1+%g0],d */

{ "lduwa",  F3(3, 0x10, 1), F3(~3, ~0x10, ~1),    "[1+i]o,d", F_ALIAS, 0, 0, v9 },

{ "lduwa",  F3(3, 0x10, 1), F3(~3, ~0x10, ~1),    "[i+1]o,d", F_ALIAS, 0, 0, v9 },

{ "lduwa",  F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|RS1_G0, "[i]o,d", F_ALIAS, 0, 0, v9 },

{ "lduwa",  F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|SIMM13(~0), "[1]o,d", F_ALIAS, 0, 0, v9 }, /* ld [rs1+0],d */

{ "ldxa", F3(3, 0x1b, 0), F3(~3, ~0x1b, ~0),    "[1+2]A,d", 0, 0, 0, v9 },

{ "ldxa", F3(3, 0x1b, 0), F3(~3, ~0x1b, ~0)|RS2_G0, "[1]A,d", 0, 0, 0, v9 }, /* lda [rs1+%g0],d */

{ "ldxa", F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1),    "[1+i]o,d", 0, 0, 0, v9 },

{ "ldxa", F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1),    "[i+1]o,d", 0, 0, 0, v9 },

{ "ldxa", F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1)|RS1_G0, "[i]o,d", 0, 0, 0, v9 },

{ "ldxa", F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1)|SIMM13(~0), "[1]o,d", 0, 0, 0, v9 }, /* ld [rs1+0],d */

{ "st", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0),    "d,[1+2]", 0, 0, 0, v6 },

{ "st", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0),    "d,[1]", 0, 0, 0, v6 }, /* st d,[rs1+%g0] */

{ "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1),      "d,[1+i]", 0, 0, 0, v6 },

{ "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1),      "d,[i+1]", 0, 0, 0, v6 },

{ "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0,   "d,[i]", 0, 0, 0, v6 },

{ "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0),   "d,[1]", 0, 0, 0, v6 }, /* st d,[rs1+0] */

{ "st", F3(3, 0x24, 0), F3(~3, ~0x24, ~0)|ASI(~0),    "g,[1+2]", 0, 0, 0, v6 },

{ "st", F3(3, 0x24, 0), F3(~3, ~0x24, ~0)|ASI_RS2(~0),    "g,[1]", 0, 0, 0, v6 }, /* st d[rs1+%g0] */

{ "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1),      "g,[1+i]", 0, 0, 0, v6 },

{ "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1),      "g,[i+1]", 0, 0, 0, v6 },

{ "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1)|RS1_G0,   "g,[i]", 0, 0, 0, v6 },

{ "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1)|SIMM13(~0),   "g,[1]", 0, 0, 0, v6 }, /* st d,[rs1+0] */

{ "st", F3(3, 0x34, 0), F3(~3, ~0x34, ~0)|ASI(~0),    "D,[1+2]", 0, 0, 0, v6notv9 },

{ "st", F3(3, 0x34, 0), F3(~3, ~0x34, ~0)|ASI_RS2(~0),    "D,[1]", 0, 0, 0, v6notv9 }, /* st d,[rs1+%g0] */

{ "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1),      "D,[1+i]", 0, 0, 0, v6notv9 },

{ "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1),      "D,[i+1]", 0, 0, 0, v6notv9 },

{ "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|RS1_G0,   "D,[i]", 0, 0, 0, v6notv9 },

{ "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|SIMM13(~0),   "D,[1]", 0, 0, 0, v6notv9 }, /* st d,[rs1+0] */

{ "st", F3(3, 0x35, 0), F3(~3, ~0x35, ~0)|ASI(~0),    "C,[1+2]", 0, 0, 0, v6notv9 },

{ "st", F3(3, 0x35, 0), F3(~3, ~0x35, ~0)|ASI_RS2(~0),    "C,[1]", 0, 0, 0, v6notv9 }, /* st d,[rs1+%g0] */

{ "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1),      "C,[1+i]", 0, 0, 0, v6notv9 },

{ "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1),      "C,[i+1]", 0, 0, 0, v6notv9 },

{ "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1)|RS1_G0,   "C,[i]", 0, 0, 0, v6notv9 },

{ "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1)|SIMM13(~0),   "C,[1]", 0, 0, 0, v6notv9 }, /* st d,[rs1+0] */

{ "st", F3(3, 0x25, 0), F3(~3, ~0x25, ~0)|RD_G0|ASI(~0),  "F,[1+2]", 0, 0, 0, v6 },

{ "st", F3(3, 0x25, 0), F3(~3, ~0x25, ~0)|RD_G0|ASI_RS2(~0),  "F,[1]", 0, 0, 0, v6 }, /* st d,[rs1+%g0] */

{ "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0,    "F,[1+i]", 0, 0, 0, v6 },

{ "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0,    "F,[i+1]", 0, 0, 0, v6 },

{ "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0|RS1_G0,   "F,[i]", 0, 0, 0, v6 },

{ "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0|SIMM13(~0), "F,[1]", 0, 0, 0, v6 }, /* st d,[rs1+0] */

{ "stw",  F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0),  "d,[1+2]", F_ALIAS, 0, 0, v9 },

{ "stw",  F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0),  "d,[1]", F_ALIAS, 0, 0, v9 }, /* st d,[rs1+%g0] */

{ "stw",  F3(3, 0x04, 1), F3(~3, ~0x04, ~1),    "d,[1+i]", F_ALIAS, 0, 0, v9 },

{ "stw",  F3(3, 0x04, 1), F3(~3, ~0x04, ~1),    "d,[i+1]", F_ALIAS, 0, 0, v9 },

{ "stw",  F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]", F_ALIAS, 0, 0, v9 },

{ "stw",  F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, 0, 0, v9 }, /* st d,[rs1+0] */

{ "stsw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0),  "d,[1+2]", F_ALIAS, 0, 0, v9 },

{ "stsw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0),  "d,[1]", F_ALIAS, 0, 0, v9 }, /* st d,[rs1+%g0] */

{ "stsw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1),    "d,[1+i]", F_ALIAS, 0, 0, v9 },

{ "stsw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1),    "d,[i+1]", F_ALIAS, 0, 0, v9 },

{ "stsw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]", F_ALIAS, 0, 0, v9 },

{ "stsw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, 0, 0, v9 }, /* st d,[rs1+0] */

{ "stuw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0),  "d,[1+2]", F_ALIAS, 0, 0, v9 },

{ "stuw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0),  "d,[1]", F_ALIAS, 0, 0, v9 }, /* st d,[rs1+%g0] */

{ "stuw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1),    "d,[1+i]", F_ALIAS, 0, 0, v9 },

{ "stuw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1),    "d,[i+1]", F_ALIAS, 0, 0, v9 },

{ "stuw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]", F_ALIAS, 0, 0, v9 },

{ "stuw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, 0, 0, v9 }, /* st d,[rs1+0] */

{ "spill",  F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0),  "d,[1+2]", F_ALIAS, 0, 0, v6 },

{ "spill",  F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0),  "d,[1]", F_ALIAS, 0, 0, v6 }, /* st d,[rs1+%g0] */

{ "spill",  F3(3, 0x04, 1), F3(~3, ~0x04, ~1),    "d,[1+i]", F_ALIAS, 0, 0, v6 },

{ "spill",  F3(3, 0x04, 1), F3(~3, ~0x04, ~1),    "d,[i+1]", F_ALIAS, 0, 0, v6 },

{ "spill",  F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]", F_ALIAS, 0, 0, v6 },

{ "spill",  F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, 0, 0, v6 }, /* st d,[rs1+0] */

{ "sta",  F3(3, 0x14, 0), F3(~3, ~0x14, ~0),    "d,[1+2]A", 0, 0, 0, v6 },

{ "sta",  F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0),  "d,[1]A", 0, 0, 0, v6 }, /* sta d,[rs1+%g0] */

{ "sta",  F3(3, 0x14, 1), F3(~3, ~0x14, ~1),    "d,[1+i]o", 0, 0, 0, v9 },

{ "sta",  F3(3, 0x14, 1), F3(~3, ~0x14, ~1),    "d,[i+1]o", 0, 0, 0, v9 },

{ "sta",  F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0, "d,[i]o", 0, 0, 0, v9 },

{ "sta",  F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0), "d,[1]o", 0, 0, 0, v9 }, /* st d,[rs1+0] */

{ "sta",  F3(3, 0x34, 0), F3(~3, ~0x34, ~0),    "g,[1+2]A", 0, 0, 0, v9 },

{ "sta",  F3(3, 0x34, 0), F3(~3, ~0x34, ~0)|RS2(~0),  "g,[1]A", 0, 0, 0, v9 }, /* sta d,[rs1+%g0] */

{ "sta",  F3(3, 0x34, 1), F3(~3, ~0x34, ~1),    "g,[1+i]o", 0, 0, 0, v9 },

{ "sta",  F3(3, 0x34, 1), F3(~3, ~0x34, ~1),    "g,[i+1]o", 0, 0, 0, v9 },

{ "sta",  F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|RS1_G0, "g,[i]o", 0, 0, 0, v9 },

{ "sta",  F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|SIMM13(~0), "g,[1]o", 0, 0, 0, v9 }, /* st d,[rs1+0] */

{ "stwa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0),    "d,[1+2]A", F_ALIAS, 0, 0, v9 },

{ "stwa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0),  "d,[1]A", F_ALIAS, 0, 0, v9 }, /* sta d,[rs1+%g0] */

{ "stwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1),    "d,[1+i]o", F_ALIAS, 0, 0, v9 },

{ "stwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1),    "d,[i+1]o", F_ALIAS, 0, 0, v9 },

{ "stwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0, "d,[i]o", F_ALIAS, 0, 0, v9 },

{ "stwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, 0, 0, v9 }, /* st d,[rs1+0] */

{ "stswa",  F3(3, 0x14, 0), F3(~3, ~0x14, ~0),    "d,[1+2]A", F_ALIAS, 0, 0, v9 },

{ "stswa",  F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0),  "d,[1]A", F_ALIAS, 0, 0, v9 }, /* sta d,[rs1+%g0] */

{ "stswa",  F3(3, 0x14, 1), F3(~3, ~0x14, ~1),    "d,[1+i]o", F_ALIAS, 0, 0, v9 },

{ "stswa",  F3(3, 0x14, 1), F3(~3, ~0x14, ~1),    "d,[i+1]o", F_ALIAS, 0, 0, v9 },

{ "stswa",  F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0, "d,[i]o", F_ALIAS, 0, 0, v9 },

{ "stswa",  F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, 0, 0, v9 }, /* st d,[rs1+0] */

{ "stuwa",  F3(3, 0x14, 0), F3(~3, ~0x14, ~0),    "d,[1+2]A", F_ALIAS, 0, 0, v9 },

{ "stuwa",  F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0),  "d,[1]A", F_ALIAS, 0, 0, v9 }, /* sta d,[rs1+%g0] */

{ "stuwa",  F3(3, 0x14, 1), F3(~3, ~0x14, ~1),    "d,[1+i]o", F_ALIAS, 0, 0, v9 },

{ "stuwa",  F3(3, 0x14, 1), F3(~3, ~0x14, ~1),    "d,[i+1]o", F_ALIAS, 0, 0, v9 },

{ "stuwa",  F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0, "d,[i]o", F_ALIAS, 0, 0, v9 },

{ "stuwa",  F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, 0, 0, v9 }, /* st d,[rs1+0] */

{ "stb",  F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI(~0),  "d,[1+2]", 0, 0, 0, v6 },

{ "stb",  F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI_RS2(~0),  "d,[1]", 0, 0, 0, v6 }, /* stb d,[rs1+%g0] */

{ "stb",  F3(3, 0x05, 1), F3(~3, ~0x05, ~1),    "d,[1+i]", 0, 0, 0, v6 },

{ "stb",  F3(3, 0x05, 1), F3(~3, ~0x05, ~1),    "d,[i+1]", 0, 0, 0, v6 },

{ "stb",  F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RS1_G0, "d,[i]", 0, 0, 0, v6 },

{ "stb",  F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|SIMM13(~0), "d,[1]", 0, 0, 0, v6 }, /* stb d,[rs1+0] */

{ "stsb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI(~0),  "d,[1+2]", F_ALIAS, 0, 0, v6 },

{ "stsb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI_RS2(~0),  "d,[1]", F_ALIAS, 0, 0, v6 }, /* stb d,[rs1+%g0] */

{ "stsb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1),    "d,[1+i]", F_ALIAS, 0, 0, v6 },

{ "stsb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1),    "d,[i+1]", F_ALIAS, 0, 0, v6 },

{ "stsb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RS1_G0, "d,[i]", F_ALIAS, 0, 0, v6 },

{ "stsb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, 0, 0, v6 }, /* stb d,[rs1+0] */

{ "stub", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI(~0),  "d,[1+2]", F_ALIAS, 0, 0, v6 },

{ "stub", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI_RS2(~0),  "d,[1]", F_ALIAS, 0, 0, v6 }, /* stb d,[rs1+%g0] */

{ "stub", F3(3, 0x05, 1), F3(~3, ~0x05, ~1),    "d,[1+i]", F_ALIAS, 0, 0, v6 },

{ "stub", F3(3, 0x05, 1), F3(~3, ~0x05, ~1),    "d,[i+1]", F_ALIAS, 0, 0, v6 },

{ "stub", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RS1_G0, "d,[i]", F_ALIAS, 0, 0, v6 },

{ "stub", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, 0, 0, v6 }, /* stb d,[rs1+0] */

{ "stba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0),    "d,[1+2]A", 0, 0, 0, v6 },

{ "stba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0)|RS2(~0),  "d,[1]A", 0, 0, 0, v6 }, /* stba d,[rs1+%g0] */

{ "stba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1),    "d,[1+i]o", 0, 0, 0, v9 },

{ "stba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1),    "d,[i+1]o", 0, 0, 0, v9 },

{ "stba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|RS1_G0, "d,[i]o", 0, 0, 0, v9 },

{ "stba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|SIMM13(~0), "d,[1]o", 0, 0, 0, v9 }, /* stb d,[rs1+0] */

{ "stsba",  F3(3, 0x15, 0), F3(~3, ~0x15, ~0),    "d,[1+2]A", F_ALIAS, 0, 0, v6 },

{ "stsba",  F3(3, 0x15, 0), F3(~3, ~0x15, ~0)|RS2(~0),  "d,[1]A", F_ALIAS, 0, 0, v6 }, /* stba d,[rs1+%g0] */

{ "stsba",  F3(3, 0x15, 1), F3(~3, ~0x15, ~1),    "d,[1+i]o", F_ALIAS, 0, 0, v9 },

{ "stsba",  F3(3, 0x15, 1), F3(~3, ~0x15, ~1),    "d,[i+1]o", F_ALIAS, 0, 0, v9 },

{ "stsba",  F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|RS1_G0, "d,[i]o", F_ALIAS, 0, 0, v9 },

{ "stsba",  F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, 0, 0, v9 }, /* stb d,[rs1+0] */

{ "stuba",  F3(3, 0x15, 0), F3(~3, ~0x15, ~0),    "d,[1+2]A", F_ALIAS, 0, 0, v6 },

{ "stuba",  F3(3, 0x15, 0), F3(~3, ~0x15, ~0)|RS2(~0),  "d,[1]A", F_ALIAS, 0, 0, v6 }, /* stba d,[rs1+%g0] */

{ "stuba",  F3(3, 0x15, 1), F3(~3, ~0x15, ~1),    "d,[1+i]o", F_ALIAS, 0, 0, v9 },

{ "stuba",  F3(3, 0x15, 1), F3(~3, ~0x15, ~1),    "d,[i+1]o", F_ALIAS, 0, 0, v9 },

{ "stuba",  F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|RS1_G0, "d,[i]o", F_ALIAS, 0, 0, v9 },

{ "stuba",  F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, 0, 0, v9 }, /* stb d,[rs1+0] */

{ "sttw", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI(~0),  "d,[1+2]", 0, 0, 0, v9 },

{ "sttw", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI_RS2(~0),  "d,[1]", 0, 0, 0, v9 }, /* std d,[rs1+%g0] */

{ "sttw", F3(3, 0x07, 1), F3(~3, ~0x07, ~1),    "d,[1+i]", 0, 0, 0, v9 },

{ "sttw", F3(3, 0x07, 1), F3(~3, ~0x07, ~1),    "d,[i+1]", 0, 0, 0, v9 },

{ "sttw", F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|RS1_G0, "d,[i]", 0, 0, 0, v9 },

{ "sttw", F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|SIMM13(~0), "d,[1]", 0, 0, 0, v9 }, /* std d,[rs1+0] */

{ "std",  F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI(~0),  "d,[1+2]", F_PREF_ALIAS, 0, 0, v6 },

{ "std",  F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI_RS2(~0),  "d,[1]", F_PREF_ALIAS, 0, 0, v6 }, /* std d,[rs1+%g0] */

{ "std",  F3(3, 0x07, 1), F3(~3, ~0x07, ~1),    "d,[1+i]", F_PREF_ALIAS, 0, 0, v6 },

{ "std",  F3(3, 0x07, 1), F3(~3, ~0x07, ~1),    "d,[i+1]", F_PREF_ALIAS, 0, 0, v6 },

{ "std",  F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|RS1_G0, "d,[i]", F_PREF_ALIAS, 0, 0, v6 },

{ "std",  F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|SIMM13(~0), "d,[1]", F_PREF_ALIAS, 0, 0, v6 }, /* std d,[rs1+0] */

{ "std",  F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI(~0),  "q,[1+2]", 0, 0, 0, v6notv9 },

{ "std",  F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI_RS2(~0),  "q,[1]", 0, 0, 0, v6notv9 }, /* std d,[rs1+%g0] */

{ "std",  F3(3, 0x26, 1), F3(~3, ~0x26, ~1),    "q,[1+i]", 0, 0, 0, v6notv9 },

{ "std",  F3(3, 0x26, 1), F3(~3, ~0x26, ~1),    "q,[i+1]", 0, 0, 0, v6notv9 },

{ "std",  F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|RS1_G0, "q,[i]", 0, 0, 0, v6notv9 },

{ "std",  F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|SIMM13(~0), "q,[1]", 0, 0, 0, v6notv9 }, /* std d,[rs1+0] */

{ "std",  F3(3, 0x27, 0), F3(~3, ~0x27, ~0)|ASI(~0),  "H,[1+2]", 0, 0, 0, v6 },

{ "std",  F3(3, 0x27, 0), F3(~3, ~0x27, ~0)|ASI_RS2(~0),  "H,[1]", 0, 0, 0, v6 }, /* std d,[rs1+%g0] */

{ "std",  F3(3, 0x27, 1), F3(~3, ~0x27, ~1),    "H,[1+i]", 0, 0, 0, v6 },

{ "std",  F3(3, 0x27, 1), F3(~3, ~0x27, ~1),    "H,[i+1]", 0, 0, 0, v6 },

{ "std",  F3(3, 0x27, 1), F3(~3, ~0x27, ~1)|RS1_G0, "H,[i]", 0, 0, 0, v6 },

{ "std",  F3(3, 0x27, 1), F3(~3, ~0x27, ~1)|SIMM13(~0), "H,[1]", 0, 0, 0, v6 }, /* std d,[rs1+0] */

{ "std",  F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI(~0),  "Q,[1+2]", 0, 0, 0, v6notv9 },

{ "std",  F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI_RS2(~0),  "Q,[1]", 0, 0, 0, v6notv9 }, /* std d,[rs1+%g0] */

{ "std",  F3(3, 0x36, 1), F3(~3, ~0x36, ~1),    "Q,[1+i]", 0, 0, 0, v6notv9 },

{ "std",  F3(3, 0x36, 1), F3(~3, ~0x36, ~1),    "Q,[i+1]", 0, 0, 0, v6notv9 },

{ "std",  F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|RS1_G0, "Q,[i]", 0, 0, 0, v6notv9 },

{ "std",  F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|SIMM13(~0), "Q,[1]", 0, 0, 0, v6notv9 }, /* std d,[rs1+0] */

{ "std",  F3(3, 0x37, 0), F3(~3, ~0x37, ~0)|ASI(~0),  "D,[1+2]", 0, 0, 0, v6notv9 },

{ "std",  F3(3, 0x37, 0), F3(~3, ~0x37, ~0)|ASI_RS2(~0),  "D,[1]", 0, 0, 0, v6notv9 }, /* std d,[rs1+%g0] */

{ "std",  F3(3, 0x37, 1), F3(~3, ~0x37, ~1),    "D,[1+i]", 0, 0, 0, v6notv9 },

{ "std",  F3(3, 0x37, 1), F3(~3, ~0x37, ~1),    "D,[i+1]", 0, 0, 0, v6notv9 },

{ "std",  F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|RS1_G0, "D,[i]", 0, 0, 0, v6notv9 },

{ "std",  F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|SIMM13(~0), "D,[1]", 0, 0, 0, v6notv9 }, /* std d,[rs1+0] */

{ "spilld", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI(~0),  "d,[1+2]", F_ALIAS, 0, 0, v6 },

{ "spilld", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI_RS2(~0),  "d,[1]", F_ALIAS, 0, 0, v6 }, /* std d,[rs1+%g0] */

{ "spilld", F3(3, 0x07, 1), F3(~3, ~0x07, ~1),    "d,[1+i]", F_ALIAS, 0, 0, v6 },

{ "spilld", F3(3, 0x07, 1), F3(~3, ~0x07, ~1),    "d,[i+1]", F_ALIAS, 0, 0, v6 },

{ "spilld", F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|RS1_G0, "d,[i]", F_ALIAS, 0, 0, v6 },

{ "spilld", F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, 0, 0, v6 }, /* std d,[rs1+0] */

{ "sttwa",  F3(3, 0x17, 0), F3(~3, ~0x17, ~0),    "d,[1+2]A", 0, 0, 0, v9 },

{ "sttwa",  F3(3, 0x17, 0), F3(~3, ~0x17, ~0)|RS2(~0),  "d,[1]A", 0, 0, 0, v9 }, /* stda d,[rs1+%g0] */

{ "sttwa",  F3(3, 0x17, 1), F3(~3, ~0x17, ~1),    "d,[1+i]o", 0, 0, 0, v9 },

{ "sttwa",  F3(3, 0x17, 1), F3(~3, ~0x17, ~1),    "d,[i+1]o", 0, 0, 0, v9 },

{ "sttwa",  F3(3, 0x17, 1), F3(~3, ~0x17, ~1)|RS1_G0, "d,[i]o", 0, 0, 0, v9 },

{ "sttwa",  F3(3, 0x17, 1), F3(~3, ~0x17, ~1)|SIMM13(~0), "d,[1]o", 0, 0, 0, v9 }, /* std d,[rs1+0] */

{ "stda", F3(3, 0x17, 0), F3(~3, ~0x17, ~0),    "d,[1+2]A", F_ALIAS, 0, 0, v6 },

{ "stda", F3(3, 0x17, 0), F3(~3, ~0x17, ~0)|RS2(~0),  "d,[1]A", F_ALIAS, 0, 0, v6 }, /* stda d,[rs1+%g0] */

{ "stda", F3(3, 0x17, 1), F3(~3, ~0x17, ~1),    "d,[1+i]o", F_ALIAS, 0, 0, v9 },

{ "stda", F3(3, 0x17, 1), F3(~3, ~0x17, ~1),    "d,[i+1]o", F_ALIAS, 0, 0, v9 },

{ "stda", F3(3, 0x17, 1), F3(~3, ~0x17, ~1)|RS1_G0, "d,[i]o", F_ALIAS, 0, 0, v9 },

{ "stda", F3(3, 0x17, 1), F3(~3, ~0x17, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, 0, 0, v9 }, /* std d,[rs1+0] */

{ "stda", F3(3, 0x37, 0), F3(~3, ~0x37, ~0),    "H,[1+2]A", 0, 0, 0, v9 },

{ "stda", F3(3, 0x37, 0), F3(~3, ~0x37, ~0)|RS2(~0),  "H,[1]A", 0, 0, 0, v9 }, /* stda d,[rs1+%g0] */

{ "stda", F3(3, 0x37, 1), F3(~3, ~0x37, ~1),    "H,[1+i]o", 0, 0, 0, v9 },

{ "stda", F3(3, 0x37, 1), F3(~3, ~0x37, ~1),    "H,[i+1]o", 0, 0, 0, v9 },

{ "stda", F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|RS1_G0, "H,[i]o", 0, 0, 0, v9 },

{ "stda", F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|SIMM13(~0), "H,[1]o", 0, 0, 0, v9 }, /* std d,[rs1+0] */

{ "sth",  F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI(~0),  "d,[1+2]", 0, 0, 0, v6 },

{ "sth",  F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI_RS2(~0),  "d,[1]", 0, 0, 0, v6 }, /* sth d,[rs1+%g0] */

{ "sth",  F3(3, 0x06, 1), F3(~3, ~0x06, ~1),    "d,[1+i]", 0, 0, 0, v6 },

{ "sth",  F3(3, 0x06, 1), F3(~3, ~0x06, ~1),    "d,[i+1]", 0, 0, 0, v6 },

{ "sth",  F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RS1_G0, "d,[i]", 0, 0, 0, v6 },

{ "sth",  F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|SIMM13(~0), "d,[1]", 0, 0, 0, v6 }, /* sth d,[rs1+0] */

{ "stsh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI(~0),  "d,[1+2]", F_ALIAS, 0, 0, v6 },

{ "stsh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI_RS2(~0),  "d,[1]", F_ALIAS, 0, 0, v6 }, /* sth d,[rs1+%g0] */

{ "stsh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1),    "d,[1+i]", F_ALIAS, 0, 0, v6 },

{ "stsh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1),    "d,[i+1]", F_ALIAS, 0, 0, v6 },

{ "stsh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RS1_G0, "d,[i]", F_ALIAS, 0, 0, v6 },

{ "stsh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, 0, 0, v6 }, /* sth d,[rs1+0] */

{ "stuh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI(~0),  "d,[1+2]", F_ALIAS, 0, 0, v6 },

{ "stuh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI_RS2(~0),  "d,[1]", F_ALIAS, 0, 0, v6 }, /* sth d,[rs1+%g0] */

{ "stuh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1),    "d,[1+i]", F_ALIAS, 0, 0, v6 },

{ "stuh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1),    "d,[i+1]", F_ALIAS, 0, 0, v6 },

{ "stuh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RS1_G0, "d,[i]", F_ALIAS, 0, 0, v6 },

{ "stuh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, 0, 0, v6 }, /* sth d,[rs1+0] */

{ "stha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0),    "d,[1+2]A", 0, 0, 0, v6 },

{ "stha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0)|RS2(~0),  "d,[1]A", 0, 0, 0, v6 }, /* stha ,[rs1+%g0] */

{ "stha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1),    "d,[1+i]o", 0, 0, 0, v9 },

{ "stha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1),    "d,[i+1]o", 0, 0, 0, v9 },

{ "stha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|RS1_G0, "d,[i]o", 0, 0, 0, v9 },

{ "stha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|SIMM13(~0), "d,[1]o", 0, 0, 0, v9 }, /* sth d,[rs1+0] */

{ "stsha",  F3(3, 0x16, 0), F3(~3, ~0x16, ~0),    "d,[1+2]A", F_ALIAS, 0, 0, v6 },

{ "stsha",  F3(3, 0x16, 0), F3(~3, ~0x16, ~0)|RS2(~0),  "d,[1]A", F_ALIAS, 0, 0, v6 }, /* stha ,[rs1+%g0] */

{ "stsha",  F3(3, 0x16, 1), F3(~3, ~0x16, ~1),    "d,[1+i]o", F_ALIAS, 0, 0, v9 },

{ "stsha",  F3(3, 0x16, 1), F3(~3, ~0x16, ~1),    "d,[i+1]o", F_ALIAS, 0, 0, v9 },

{ "stsha",  F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|RS1_G0, "d,[i]o", F_ALIAS, 0, 0, v9 },

{ "stsha",  F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, 0, 0, v9 }, /* sth d,[rs1+0] */

{ "stuha",  F3(3, 0x16, 0), F3(~3, ~0x16, ~0),    "d,[1+2]A", F_ALIAS, 0, 0, v6 },

{ "stuha",  F3(3, 0x16, 0), F3(~3, ~0x16, ~0)|RS2(~0),  "d,[1]A", F_ALIAS, 0, 0, v6 }, /* stha ,[rs1+%g0] */

{ "stuha",  F3(3, 0x16, 1), F3(~3, ~0x16, ~1),    "d,[1+i]o", F_ALIAS, 0, 0, v9 },

{ "stuha",  F3(3, 0x16, 1), F3(~3, ~0x16, ~1),    "d,[i+1]o", F_ALIAS, 0, 0, v9 },

{ "stuha",  F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|RS1_G0, "d,[i]o", F_ALIAS, 0, 0, v9 },

{ "stuha",  F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, 0, 0, v9 }, /* sth d,[rs1+0] */

{ "stx",  F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|ASI(~0),  "d,[1+2]", 0, 0, 0, v9 },

{ "stx",  F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|ASI_RS2(~0),  "d,[1]", 0, 0, 0, v9 }, /* stx d,[rs1+%g0] */

{ "stx",  F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1),    "d,[1+i]", 0, 0, 0, v9 },

{ "stx",  F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1),    "d,[i+1]", 0, 0, 0, v9 },

{ "stx",  F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RS1_G0, "d,[i]", 0, 0, 0, v9 },

{ "stx",  F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|SIMM13(~0), "d,[1]", 0, 0, 0, v9 }, /* stx d,[rs1+0] */

{ "stx",  F3(3, 0x25, 0)|RD(1), F3(~3, ~0x25, ~0)|ASI(~0)|RD(~1), "F,[1+2]", 0, 0, 0, v9 },

{ "stx",  F3(3, 0x25, 0)|RD(1), F3(~3, ~0x25, ~0)|ASI_RS2(~0)|RD(~1),"F,[1]", 0, 0, 0, v9 }, /* stx d,[rs1+%g0] */

{ "stx",  F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|RD(~1),   "F,[1+i]", 0, 0, 0, v9 },

{ "stx",  F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|RD(~1),   "F,[i+1]", 0, 0, 0, v9 },

{ "stx",  F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|RS1_G0|RD(~1),  "F,[i]", 0, 0, 0, v9 },

{ "stx",  F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|SIMM13(~0)|RD(~1),"F,[1]", 0, 0, 0, v9 }, /* stx d,[rs1+0] */

{ "stxa", F3(3, 0x1e, 0), F3(~3, ~0x1e, ~0),    "d,[1+2]A", 0, 0, 0, v9 },

{ "stxa", F3(3, 0x1e, 0), F3(~3, ~0x1e, ~0)|RS2(~0),  "d,[1]A", 0, 0, 0, v9 }, /* stxa d,[rs1+%g0] */

{ "stxa", F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1),    "d,[1+i]o", 0, 0, 0, v9 },

{ "stxa", F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1),    "d,[i+1]o", 0, 0, 0, v9 },

{ "stxa", F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1)|RS1_G0, "d,[i]o", 0, 0, 0, v9 },

{ "stxa", F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1)|SIMM13(~0), "d,[1]o", 0, 0, 0, v9 }, /* stx d,[rs1+0] */

{ "stq",  F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI(~0),  "J,[1+2]", 0, 0, 0, v9 },

{ "stq",  F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI_RS2(~0),  "J,[1]", 0, 0, 0, v9 }, /* stq [rs1+%g0] */

{ "stq",  F3(3, 0x26, 1), F3(~3, ~0x26, ~1),    "J,[1+i]", 0, 0, 0, v9 },

{ "stq",  F3(3, 0x26, 1), F3(~3, ~0x26, ~1),    "J,[i+1]", 0, 0, 0, v9 },

{ "stq",  F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|RS1_G0, "J,[i]", 0, 0, 0, v9 },

{ "stq",  F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|SIMM13(~0), "J,[1]", 0, 0, 0, v9 }, /* stq [rs1+0] */

{ "stqa", F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI(~0),  "J,[1+2]A", 0, 0, 0, v9 },

{ "stqa", F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI_RS2(~0),  "J,[1]A", 0, 0, 0, v9 }, /* stqa [rs1+%g0] */

{ "stqa", F3(3, 0x36, 1), F3(~3, ~0x36, ~1),    "J,[1+i]o", 0, 0, 0, v9 },

{ "stqa", F3(3, 0x36, 1), F3(~3, ~0x36, ~1),    "J,[i+1]o", 0, 0, 0, v9 },

{ "stqa", F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|RS1_G0, "J,[i]o", 0, 0, 0, v9 },

{ "stqa", F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|SIMM13(~0), "J,[1]o", 0, 0, 0, v9 }, /* stqa [rs1+0] */

{ "swap", F3(3, 0x0f, 0), F3(~3, ~0x0f, ~0)|ASI(~0),  "[1+2],d", 0, 0, 0, v7 },

{ "swap", F3(3, 0x0f, 0), F3(~3, ~0x0f, ~0)|ASI_RS2(~0),  "[1],d", 0, 0, 0, v7 }, /* swap [rs1+%g0],d */

{ "swap", F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1),    "[1+i],d", 0, 0, 0, v7 },

{ "swap", F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1),    "[i+1],d", 0, 0, 0, v7 },

{ "swap", F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1)|RS1_G0, "[i],d", 0, 0, 0, v7 },

{ "swap", F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1)|SIMM13(~0), "[1],d", 0, 0, 0, v7 }, /* swap [rs1+0],d */

{ "swapa",  F3(3, 0x1f, 0), F3(~3, ~0x1f, ~0),    "[1+2]A,d", 0, 0, 0, v7 },

{ "swapa",  F3(3, 0x1f, 0), F3(~3, ~0x1f, ~0)|RS2(~0),  "[1]A,d", 0, 0, 0, v7 }, /* swapa [rs1+%g0],d */

{ "swapa",  F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1),    "[1+i]o,d", 0, 0, 0, v9 },

{ "swapa",  F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1),    "[i+1]o,d", 0, 0, 0, v9 },

{ "swapa",  F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1)|RS1_G0, "[i]o,d", 0, 0, 0, v9 },

{ "swapa",  F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1)|SIMM13(~0), "[1]o,d", 0, 0, 0, v9 }, /* swap [rs1+0],d */

{ "restore",  F3(2, 0x3d, 0), F3(~2, ~0x3d, ~0)|ASI(~0),      "1,2,d", 0, 0, 0, v6 },

{ "restore",  F3(2, 0x3d, 0), F3(~2, ~0x3d, ~0)|RD_G0|RS1_G0|ASI_RS2(~0), "", 0, 0, 0, v6 }, /* restore %g0,%g0,%g0 */

{ "restore",  F3(2, 0x3d, 1), F3(~2, ~0x3d, ~1),        "1,i,d", 0, 0, 0, v6 },

{ "restore",  F3(2, 0x3d, 1), F3(~2, ~0x3d, ~1)|RD_G0|RS1_G0|SIMM13(~0),  "", 0, 0, 0, v6 }, /* restore %g0,0,%g0 */

{ "rett", F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|RD_G0|ASI(~0),  "1+2", F_UNBR|F_DELAYED, 0, 0, v6notv9 }, /* rett rs1+rs2 */

{ "rett", F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|RD_G0|ASI_RS2(~0),  "1", F_UNBR|F_DELAYED, 0, 0, v6notv9 }, /* rett rs1,%g0 */

{ "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0,    "1+i", F_UNBR|F_DELAYED, 0, 0, v6notv9 }, /* rett rs1+X */

{ "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0,    "i+1", F_UNBR|F_DELAYED, 0, 0, v6notv9 }, /* rett X+rs1 */

{ "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|RS1_G0,   "i", F_UNBR|F_DELAYED, 0, 0, v6notv9 }, /* rett X+rs1 */

{ "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|RS1_G0,   "i", F_UNBR|F_DELAYED, 0, 0, v6notv9 }, /* rett X */

{ "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|SIMM13(~0), "1", F_UNBR|F_DELAYED, 0, 0, v6notv9 }, /* rett rs1+0 */

{ "save", F3(2, 0x3c, 0), F3(~2, ~0x3c, ~0)|ASI(~0),  "1,2,d", 0, 0, 0, v6 },

{ "save", F3(2, 0x3c, 1), F3(~2, ~0x3c, ~1),    "1,i,d", 0, 0, 0, v6 },

{ "save", F3(2, 0x3c, 1), F3(~2, ~0x3c, ~1),    "i,1,d", 0, 0, 0, v6 }, /* Sun assembler compatibility */

{ "save", 0x81e00000, ~0x81e00000,      "", F_ALIAS, 0, 0, v6 },

{ "ret",  F3(2, 0x38, 1)|RS1(0x1f)|SIMM13(8), F3(~2, ~0x38, ~1)|SIMM13(~8),        "", F_UNBR|F_DELAYED, 0, 0, v6 }, /* jmpl %i7+8,%g0 */

{ "retl", F3(2, 0x38, 1)|RS1(0x0f)|SIMM13(8), F3(~2, ~0x38, ~1)|RS1(~0x0f)|SIMM13(~8), "", F_UNBR|F_DELAYED, 0, 0, v6 }, /* jmpl %o7+8,%g0 */

{ "jmpl", F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|ASI(~0),  "1+2,d", F_JSR|F_DELAYED, 0, 0, v6 },

{ "jmpl", F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|ASI_RS2(~0),  "1,d", F_JSR|F_DELAYED, 0, 0, v6 }, /* jmpl rs1+%g0,d */

{ "jmpl", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|SIMM13(~0), "1,d", F_JSR|F_DELAYED, 0, 0, v6 }, /* jmpl rs1+0,d */

{ "jmpl", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RS1_G0, "i,d", F_JSR|F_DELAYED, 0, 0, v6 }, /* jmpl %g0+i,d */

{ "jmpl", F3(2, 0x38, 1), F3(~2, ~0x38, ~1),    "1+i,d", F_JSR|F_DELAYED, 0, 0, v6 },

{ "jmpl", F3(2, 0x38, 1), F3(~2, ~0x38, ~1),    "i+1,d", F_JSR|F_DELAYED, 0, 0, v6 },

{ "done", F3(2, 0x3e, 0)|RD(0), F3(~2, ~0x3e, ~0)|RD(~0)|RS1_G0|SIMM13(~0), "", 0, 0, 0, v9 },

{ "retry",  F3(2, 0x3e, 0)|RD(1), F3(~2, ~0x3e, ~0)|RD(~1)|RS1_G0|SIMM13(~0), "", 0, 0, 0, v9 },

{ "saved",  F3(2, 0x31, 0)|RD(0), F3(~2, ~0x31, ~0)|RD(~0)|RS1_G0|SIMM13(~0), "", 0, 0, 0, v9 },

{ "restored", F3(2, 0x31, 0)|RD(1), F3(~2, ~0x31, ~0)|RD(~1)|RS1_G0|SIMM13(~0), "", 0, 0, 0, v9 },

{ "allclean", F3(2, 0x31, 0)|RD(2), F3(~2, ~0x31, ~0)|RD(~2)|RS1_G0|SIMM13(~0), "", 0, 0, 0, v9 },

{ "otherw", F3(2, 0x31, 0)|RD(3), F3(~2, ~0x31, ~0)|RD(~3)|RS1_G0|SIMM13(~0), "", 0, 0, 0, v9 },

{ "normalw",  F3(2, 0x31, 0)|RD(4), F3(~2, ~0x31, ~0)|RD(~4)|RS1_G0|SIMM13(~0), "", 0, 0, 0, v9 },

{ "invalw", F3(2, 0x31, 0)|RD(5), F3(~2, ~0x31, ~0)|RD(~5)|RS1_G0|SIMM13(~0), "", 0, 0, 0, v9 },

{ "sir",  F3(2, 0x30, 1)|RD(0xf), F3(~2, ~0x30, ~1)|RD(~0xf)|RS1_G0,    "i", 0, 0, 0, v9 },

{ "flush",  F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI(~0),  "[1+2]", 0, 0, 0, v9 },

{ "flush",  F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI_RS2(~0),  "[1]", 0, 0, 0, v9 }, /* flush rs1+%g0 */

{ "flush",  F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|SIMM13(~0), "[1]", 0, 0, 0, v9 }, /* flush rs1+0 */

{ "flush",  F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|RS1_G0, "[i]", 0, 0, 0, v9 }, /* flush %g0+i */

{ "flush",  F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1),    "[1+i]", 0, 0, 0, v9 },

{ "flush",  F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1),    "[i+1]", 0, 0, 0, v9 },

{ "flush",  F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI(~0),  "1+2", F_ALIAS, 0, 0, v8 },

{ "flush",  F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI_RS2(~0),  "1", F_ALIAS, 0, 0, v8 }, /* flush rs1+%g0 */

{ "flush",  F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|SIMM13(~0), "1", F_ALIAS, 0, 0, v8 }, /* flush rs1+0 */

{ "flush",  F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|RS1_G0, "i", F_ALIAS, 0, 0, v8 }, /* flush %g0+i */

{ "flush",  F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1),    "1+i", F_ALIAS, 0, 0, v8 },

{ "flush",  F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1),    "i+1", F_ALIAS, 0, 0, v8 },

/* IFLUSH was renamed to FLUSH in v8.  */

{ "iflush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI(~0),  "1+2", F_ALIAS, 0, 0, v6 },

{ "iflush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI_RS2(~0),  "1", F_ALIAS, 0, 0, v6 }, /* flush rs1+%g0 */

{ "iflush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|SIMM13(~0), "1", F_ALIAS, 0, 0, v6 }, /* flush rs1+0 */

{ "iflush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|RS1_G0, "i", F_ALIAS, 0, 0, v6 },

{ "iflush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1),    "1+i", F_ALIAS, 0, 0, v6 },

{ "iflush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1),    "i+1", F_ALIAS, 0, 0, v6 },

{ "return", F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|ASI(~0),  "1+2", 0, 0, 0, v9 },

{ "return", F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|ASI_RS2(~0),  "1", 0, 0, 0, v9 }, /* return rs1+%g0 */

{ "return", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|SIMM13(~0), "1", 0, 0, 0, v9 }, /* return rs1+0 */

{ "return", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RS1_G0, "i", 0, 0, 0, v9 }, /* return %g0+i */

{ "return", F3(2, 0x39, 1), F3(~2, ~0x39, ~1),    "1+i", 0, 0, 0, v9 },

{ "return", F3(2, 0x39, 1), F3(~2, ~0x39, ~1),    "i+1", 0, 0, 0, v9 },

{ "flushw", F3(2, 0x2b, 0), F3(~2, ~0x2b, ~0)|RD_G0|RS1_G0|ASI_RS2(~0), "", 0, 0, 0, v9 },

{ "membar", F3(2, 0x28, 1)|RS1(0xf), F3(~2, ~0x28, ~1)|RD_G0|RS1(~0xf)|SIMM13(~127), "K", 0, 0, 0, v9 },

{ "stbar",  F3(2, 0x28, 0)|RS1(0xf), F3(~2, ~0x28, ~0)|RD_G0|RS1(~0xf)|SIMM13(~0), "", 0, 0, 0, v8 },

{ "prefetch", F3(3, 0x2d, 0), F3(~3, ~0x2d, ~0),    "[1+2],*", 0, 0, 0, v9 },

{ "prefetch", F3(3, 0x2d, 0), F3(~3, ~0x2d, ~0)|RS2_G0, "[1],*", 0, 0, 0, v9 }, /* prefetch [rs1+%g0],prefetch_fcn */

{ "prefetch", F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1),    "[1+i],*", 0, 0, 0, v9 },

{ "prefetch", F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1),    "[i+1],*", 0, 0, 0, v9 },

{ "prefetch", F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1)|RS1_G0, "[i],*", 0, 0, 0, v9 },

{ "prefetch", F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1)|SIMM13(~0), "[1],*", 0, 0, 0, v9 }, /* prefetch [rs1+0],prefetch_fcn */

{ "prefetcha",  F3(3, 0x3d, 0), F3(~3, ~0x3d, ~0),    "[1+2]A,*", 0, 0, 0, v9 },

{ "prefetcha",  F3(3, 0x3d, 0), F3(~3, ~0x3d, ~0)|RS2_G0, "[1]A,*", 0, 0, 0, v9 }, /* prefetcha [rs1+%g0],prefetch_fcn */

{ "prefetcha",  F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1),    "[1+i]o,*", 0, 0, 0, v9 },

{ "prefetcha",  F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1),    "[i+1]o,*", 0, 0, 0, v9 },

{ "prefetcha",  F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1)|RS1_G0, "[i]o,*", 0, 0, 0, v9 },

{ "prefetcha",  F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1)|SIMM13(~0), "[1]o,*", 0, 0, 0, v9 }, /* prefetcha [rs1+0],d */

{ "sll",  F3(2, 0x25, 0), F3(~2, ~0x25, ~0)|(1<<12)|(0x7f<<5),  "1,2,d", 0, 0, 0, v6 },

{ "sll",  F3(2, 0x25, 1), F3(~2, ~0x25, ~1)|(1<<12)|(0x7f<<5),  "1,X,d", 0, 0, 0, v6 },

{ "sra",  F3(2, 0x27, 0), F3(~2, ~0x27, ~0)|(1<<12)|(0x7f<<5),  "1,2,d", 0, 0, 0, v6 },

{ "sra",  F3(2, 0x27, 1), F3(~2, ~0x27, ~1)|(1<<12)|(0x7f<<5),  "1,X,d", 0, 0, 0, v6 },

{ "srl",  F3(2, 0x26, 0), F3(~2, ~0x26, ~0)|(1<<12)|(0x7f<<5),  "1,2,d", 0, 0, 0, v6 },

{ "srl",  F3(2, 0x26, 1), F3(~2, ~0x26, ~1)|(1<<12)|(0x7f<<5),  "1,X,d", 0, 0, 0, v6 },

{ "sllx", F3(2, 0x25, 0)|(1<<12), F3(~2, ~0x25, ~0)|(0x7f<<5),  "1,2,d", 0, 0, 0, v9 },

{ "sllx", F3(2, 0x25, 1)|(1<<12), F3(~2, ~0x25, ~1)|(0x3f<<6),  "1,Y,d", 0, 0, 0, v9 },

{ "srax", F3(2, 0x27, 0)|(1<<12), F3(~2, ~0x27, ~0)|(0x7f<<5),  "1,2,d", 0, 0, 0, v9 },

{ "srax", F3(2, 0x27, 1)|(1<<12), F3(~2, ~0x27, ~1)|(0x3f<<6),  "1,Y,d", 0, 0, 0, v9 },

{ "srlx", F3(2, 0x26, 0)|(1<<12), F3(~2, ~0x26, ~0)|(0x7f<<5),  "1,2,d", 0, 0, 0, v9 },

{ "srlx", F3(2, 0x26, 1)|(1<<12), F3(~2, ~0x26, ~1)|(0x3f<<6),  "1,Y,d", 0, 0, 0, v9 },

{ "mulscc", F3(2, 0x24, 0), F3(~2, ~0x24, ~0)|ASI(~0),  "1,2,d", 0, 0, 0, v6 },

{ "mulscc", F3(2, 0x24, 1), F3(~2, ~0x24, ~1),    "1,i,d", 0, 0, 0, v6 },

{ "divscc", F3(2, 0x1d, 0), F3(~2, ~0x1d, ~0)|ASI(~0),  "1,2,d", 0, 0, 0, sparclite },

{ "divscc", F3(2, 0x1d, 1), F3(~2, ~0x1d, ~1),    "1,i,d", 0, 0, 0, sparclite },

{ "scan", F3(2, 0x2c, 0), F3(~2, ~0x2c, ~0)|ASI(~0),  "1,2,d", 0, 0, 0, sparclet|sparclite },

{ "scan", F3(2, 0x2c, 1), F3(~2, ~0x2c, ~1),    "1,i,d", 0, 0, 0, sparclet|sparclite },

{ "popc", F3(2, 0x2e, 0), F3(~2, ~0x2e, ~0)|RS1_G0|ASI(~0),"2,d", 0, HWCAP_POPC, 0, v9 },

{ "popc", F3(2, 0x2e, 1), F3(~2, ~0x2e, ~1)|RS1_G0, "i,d", 0, HWCAP_POPC, 0, v9 },

{ "clr",  F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|RD_G0|RS1_G0|ASI_RS2(~0), "d", F_ALIAS, 0, 0, v6 }, /* or %g0,%g0,d */

{ "clr",  F3(2, 0x02, 1), F3(~2, ~0x02, ~1)|RS1_G0|SIMM13(~0),    "d", F_ALIAS, 0, 0, v6 }, /* or %g0,0,d */

{ "clr",  F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|RD_G0|ASI(~0),    "[1+2]", F_ALIAS, 0, 0, v6 },

{ "clr",  F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|RD_G0|ASI_RS2(~0),    "[1]", F_ALIAS, 0, 0, v6 }, /* st %g0,[rs1+%g0] */

{ "clr",  F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0,      "[1+i]", F_ALIAS, 0, 0, v6 },

{ "clr",  F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0,      "[i+1]", F_ALIAS, 0, 0, v6 },

{ "clr",  F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0|RS1_G0,     "[i]", F_ALIAS, 0, 0, v6 },

{ "clr",  F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0|SIMM13(~0),   "[1]", F_ALIAS, 0, 0, v6 }, /* st %g0,[rs1+0] */

{ "clrb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|RD_G0|ASI(~0),  "[1+2]", F_ALIAS, 0, 0, v6 },

{ "clrb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|RD_G0|ASI_RS2(~0),  "[1]", F_ALIAS, 0, 0, v6 }, /* stb %g0,[rs1+%g0] */

{ "clrb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0,    "[1+i]", F_ALIAS, 0, 0, v6 },

{ "clrb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0,    "[i+1]", F_ALIAS, 0, 0, v6 },

{ "clrb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0|RS1_G0,   "[i]", F_ALIAS, 0, 0, v6 },

{ "clrb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0|SIMM13(~0), "[1]", F_ALIAS, 0, 0, v6 }, /* stb %g0,[rs1+0] */

{ "clrh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|RD_G0|ASI(~0),  "[1+2]", F_ALIAS, 0, 0, v6 },

{ "clrh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|RD_G0|ASI_RS2(~0),  "[1]", F_ALIAS, 0, 0, v6 }, /* sth %g0,[rs1+%g0] */

{ "clrh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0,    "[1+i]", F_ALIAS, 0, 0, v6 },

{ "clrh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0,    "[i+1]", F_ALIAS, 0, 0, v6 },

{ "clrh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0|RS1_G0,   "[i]", F_ALIAS, 0, 0, v6 },

{ "clrh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0|SIMM13(~0), "[1]", F_ALIAS, 0, 0, v6 }, /* sth %g0,[rs1+0] */

{ "clrx", F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|RD_G0|ASI(~0),  "[1+2]", F_ALIAS, 0, 0, v9 },

{ "clrx", F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|RD_G0|ASI_RS2(~0),  "[1]", F_ALIAS, 0, 0, v9 }, /* stx %g0,[rs1+%g0] */

{ "clrx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0,    "[1+i]", F_ALIAS, 0, 0, v9 },

{ "clrx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0,    "[i+1]", F_ALIAS, 0, 0, v9 },

{ "clrx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0|RS1_G0,   "[i]", F_ALIAS, 0, 0, v9 },

{ "clrx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0|SIMM13(~0), "[1]", F_ALIAS, 0, 0, v9 }, /* stx %g0,[rs1+0] */

{ "orcc", F3(2, 0x12, 0), F3(~2, ~0x12, ~0)|ASI(~0),  "1,2,d", 0, 0, 0, v6 },

{ "orcc", F3(2, 0x12, 1), F3(~2, ~0x12, ~1),    "1,i,d", 0, 0, 0, v6 },

{ "orcc", F3(2, 0x12, 1), F3(~2, ~0x12, ~1),    "i,1,d", 0, 0, 0, v6 },

/* This is not a commutative instruction.  */

{ "orncc",  F3(2, 0x16, 0), F3(~2, ~0x16, ~0)|ASI(~0),  "1,2,d", 0, 0, 0, v6 },

{ "orncc",  F3(2, 0x16, 1), F3(~2, ~0x16, ~1),    "1,i,d", 0, 0, 0, v6 },

/* This is not a commutative instruction.  */

{ "orn",  F3(2, 0x06, 0), F3(~2, ~0x06, ~0)|ASI(~0),  "1,2,d", 0, 0, 0, v6 },

{ "orn",  F3(2, 0x06, 1), F3(~2, ~0x06, ~1),    "1,i,d", 0, 0, 0, v6 },

{ "tst",  F3(2, 0x12, 0), F3(~2, ~0x12, ~0)|RD_G0|ASI_RS2(~0),  "1", 0, 0, 0, v6 }, /* orcc rs1, %g0, %g0 */

{ "tst",  F3(2, 0x12, 0), F3(~2, ~0x12, ~0)|RD_G0|RS1_G0|ASI(~0), "2", 0, 0, 0, v6 }, /* orcc %g0, rs2, %g0 */

{ "tst",  F3(2, 0x12, 1), F3(~2, ~0x12, ~1)|RD_G0|SIMM13(~0), "1", 0, 0, 0, v6 }, /* orcc rs1, 0, %g0 */

{ "wr", F3(2, 0x30, 0),   F3(~2, ~0x30, ~0)|ASI(~0),    "1,2,m", 0, 0, 0, v8 }, /* wr r,r,%asrX */

{ "wr", F3(2, 0x30, 1),   F3(~2, ~0x30, ~1),      "1,i,m", 0, 0, 0, v8 }, /* wr r,i,%asrX */

{ "wr", F3(2, 0x30, 0),   F3(~2, ~0x30, ~0)|RS1_G0|ASI(~0), "2,m", F_PREF_ALIAS, 0, 0, v8 }, /* wr %g0,rs2,%asrX */

{ "wr", F3(2, 0x30, 1),   F3(~2, ~0x30, ~1)|RS1_G0,   "i,m", F_PREF_ALIAS, 0, 0, v8 }, /* wr %g0,i,%asrX */

{ "wr", F3(2, 0x30, 1),   F3(~2, ~0x30, ~1)|SIMM13(~0),   "1,m", F_PREF_ALIAS, 0, 0, v8 }, /* wr rs1,%asrX */

{ "wr", F3(2, 0x30, 0),   F3(~2, ~0x30, ~0)|ASI_RS2(~0),    "1,m", F_PREF_ALIAS, 0, 0, v8 }, /* wr rs1,%g0,%asrX */

{ "wr", F3(2, 0x30, 0),   F3(~2, ~0x30, ~0)|RD_G0|ASI(~0),  "1,2,y", 0, 0, 0, v6 }, /* wr r,r,%y */

{ "wr", F3(2, 0x30, 1),   F3(~2, ~0x30, ~1)|RD_G0,    "1,i,y", 0, 0, 0, v6 }, /* wr r,i,%y */

{ "wr", F3(2, 0x30, 0),   F3(~2, ~0x30, ~0)|RD_G0|RS1_G0|ASI(~0), "2,y", F_PREF_ALIAS, 0, 0, v6 }, /* wr %g0,rs2,%y */

{ "wr", F3(2, 0x30, 1),   F3(~2, ~0x30, ~1)|RD_G0|RS1_G0,   "i,y", F_PREF_ALIAS, 0, 0, v6 }, /* wr %g0,i,%y */

{ "wr", F3(2, 0x30, 1),   F3(~2, ~0x30, ~1)|RD_G0|SIMM13(~0), "1,y", F_PREF_ALIAS, 0, 0, v6 }, /* wr rs1,0,%y */

{ "wr", F3(2, 0x30, 0),   F3(~2, ~0x30, ~0)|RD_G0|ASI_RS2(~0),  "1,y", F_PREF_ALIAS, 0, 0, v6 }, /* wr rs1,%g0,%y */

{ "wr", F3(2, 0x31, 0),   F3(~2, ~0x31, ~0)|RD_G0|ASI(~0),  "1,2,p", 0, 0, 0, v6notv9 }, /* wr r,r,%psr */

{ "wr", F3(2, 0x31, 1),   F3(~2, ~0x31, ~1)|RD_G0,    "1,i,p", 0, 0, 0, v6notv9 }, /* wr r,i,%psr */

{ "wr", F3(2, 0x31, 0),   F3(~2, ~0x31, ~0)|RD_G0|RS1_G0|ASI(~0), "2,p", F_PREF_ALIAS, 0, 0, v6notv9 }, /* wr %g0,rs2,%psr */

{ "wr", F3(2, 0x31, 1),   F3(~2, ~0x31, ~1)|RD_G0|RS1_G0,   "i,p", F_PREF_ALIAS, 0, 0, v6notv9 }, /* wr %g0,i,%psr */

{ "wr", F3(2, 0x31, 1),   F3(~2, ~0x31, ~1)|RD_G0|SIMM13(~0), "1,p", F_PREF_ALIAS, 0, 0, v6notv9 }, /* wr rs1,0,%psr */

{ "wr", F3(2, 0x31, 0),   F3(~2, ~0x31, ~0)|RD_G0|ASI_RS2(~0),  "1,p", F_PREF_ALIAS, 0, 0, v6notv9 }, /* wr rs1,%g0,%psr */

{ "wr", F3(2, 0x32, 0),   F3(~2, ~0x32, ~0)|RD_G0|ASI(~0),  "1,2,w", 0, 0, 0, v6notv9 }, /* wr r,r,%wim */

{ "wr", F3(2, 0x32, 1),   F3(~2, ~0x32, ~1)|RD_G0,    "1,i,w", 0, 0, 0, v6notv9 }, /* wr r,i,%wim */

{ "wr", F3(2, 0x32, 0),   F3(~2, ~0x32, ~0)|RD_G0|RS1_G0|ASI(~0), "2,w", F_PREF_ALIAS, 0, 0, v6notv9 }, /* wr %g0,rs2,%wim */

{ "wr", F3(2, 0x32, 1),   F3(~2, ~0x32, ~1)|RD_G0|RS1_G0,   "i,w", F_PREF_ALIAS, 0, 0, v6notv9 }, /* wr %g0,i,%wim */

{ "wr", F3(2, 0x32, 1),   F3(~2, ~0x32, ~1)|RD_G0|SIMM13(~0), "1,w", F_PREF_ALIAS, 0, 0, v6notv9 }, /* wr rs1,0,%wim */

{ "wr", F3(2, 0x32, 0),   F3(~2, ~0x32, ~0)|RD_G0|ASI_RS2(~0),  "1,w", F_PREF_ALIAS, 0, 0, v6notv9 }, /* wr rs1,%g0,%wim */

{ "wr", F3(2, 0x33, 0),   F3(~2, ~0x33, ~0)|RD_G0|ASI(~0),  "1,2,t", 0, 0, 0, v6notv9 }, /* wr r,r,%tbr */

{ "wr", F3(2, 0x33, 1),   F3(~2, ~0x33, ~1)|RD_G0,    "1,i,t", 0, 0, 0, v6notv9 }, /* wr r,i,%tbr */

{ "wr", F3(2, 0x33, 0),   F3(~2, ~0x33, ~0)|RD_G0|RS1_G0|ASI(~0), "2,t", F_PREF_ALIAS, 0, 0, v6notv9 }, /* wr %g0,rs2,%tbr */

{ "wr", F3(2, 0x33, 1),   F3(~2, ~0x33, ~1)|RD_G0|RS1_G0,   "i,t", F_PREF_ALIAS, 0, 0, v6notv9 }, /* wr %g0,i,%tbr */

{ "wr", F3(2, 0x33, 1),   F3(~2, ~0x33, ~1)|RD_G0|SIMM13(~0), "1,t", F_PREF_ALIAS, 0, 0, v6notv9 }, /* wr rs1,0,%tbr */

{ "wr", F3(2, 0x33, 0),   F3(~2, ~0x33, ~0)|RD_G0|ASI_RS2(~0),  "1,t", F_PREF_ALIAS, 0, 0, v6notv9 }, /* wr rs1,%g0,%tbr */

{ "wr", F3(2, 0x30, 0)|RD(2), F3(~2, ~0x30, ~0)|RD(~2)|ASI(~0), "1,2,E", 0, 0, 0, v9 }, /* wr r,r,%ccr */

{ "wr", F3(2, 0x30, 1)|RD(2), F3(~2, ~0x30, ~1)|RD(~2),   "1,i,E", 0, 0, 0, v9 }, /* wr r,i,%ccr */

{ "wr", F3(2, 0x30, 0)|RD(3), F3(~2, ~0x30, ~0)|RD(~3)|ASI(~0), "1,2,o", 0, 0, 0, v9 }, /* wr r,r,%asi */

{ "wr", F3(2, 0x30, 1)|RD(3), F3(~2, ~0x30, ~1)|RD(~3),   "1,i,o", 0, 0, 0, v9 }, /* wr r,i,%asi */

{ "wr", F3(2, 0x30, 0)|RD(6), F3(~2, ~0x30, ~0)|RD(~6)|ASI(~0), "1,2,s", 0, 0, 0, v9 }, /* wr r,r,%fprs */

{ "wr", F3(2, 0x30, 1)|RD(6), F3(~2, ~0x30, ~1)|RD(~6),   "1,i,s", 0, 0, 0, v9 }, /* wr r,i,%fprs */

{ "wr", F3(2, 0x30, 0)|RD(14),  F3(~2, ~0x30, ~0)|RD(~14),              "1,2,{", 0, 0, HWCAP2_SPARC5, v9m }, /* wr r,r,%mcdper */

{ "wr", F3(2, 0x30, 1)|RD(14),  F3(~2, ~0x30, ~1)|RD(~14),              "1,i,{", 0, 0, HWCAP2_SPARC5, v9m }, /* wr r,i,%mcdper */

/* Write to ASR registers 16..31, which is the range defined in SPARC

   V9 for implementation-dependent uses.  Note that the read-only ASR

   registers can't be used in a `wr' instruction.  */

#define wrasr(asr,hwcap,hwcap2,arch) \

{ "wr", F3(2, 0x30, 0)|RD((asr)), F3(~2, ~0x30, ~0)|RD(~(asr))|ASI(~0), "1,2,_", 0, (hwcap), (hwcap2), (arch) }, /* wr r,r,%asr */ \

{ "wr", F3(2, 0x30, 1)|RD((asr)), F3(~2, ~0x30, ~1)|RD(~(asr)),   "1,i,_", 0, (hwcap), (hwcap2), (arch) }, /* wr r,i,%asr */ \

{ "wr", F3(2, 0x30, 1)|RD((asr)), F3(~2, ~0x30, ~1)|RD(~(asr)),   "i,1,_", F_ALIAS, (hwcap), (hwcap2), (arch) } /* wr i,r,%asr */

wrasr (16, HWCAP_VIS, 0, v9a), /* wr ...,%pcr  */

wrasr (17, HWCAP_VIS, 0, v9a), /* wr ...,%pic  */

wrasr (18, HWCAP_VIS, 0, v9a), /* wr ...,%dcr  */

wrasr (19, HWCAP_VIS, 0, v9a), /* wr ...,%gsr  */

wrasr (20, HWCAP_VIS, 0, v9a), /* wr ...,%softint_set  */

wrasr (21, HWCAP_VIS, 0, v9a), /* wr ...,%softint_clear  */

wrasr (22, HWCAP_VIS, 0, v9a), /* wr ...,%softint  */

wrasr (23, HWCAP_VIS, 0, v9a), /* wr ...,%tick_cmpr  */

wrasr (24, HWCAP_VIS2, 0, v9b), /* wr ...,%sys_tick  */

wrasr (25, HWCAP_VIS2, 0, v9b), /* wr ...,%sys_tick_cmpr  */

wrasr (26, HWCAP_CBCOND, 0, v9e), /* wr ...,%cfr  */

wrasr (27, HWCAP_PAUSE, 0, v9e),  /* wr ...,%pause  */

wrasr (28, 0, HWCAP2_MWAIT, v9m), /* wr ...,%mwait  */

{ "pwr",  F3(2, 0x31, 0)|RD(1), F3(~2, ~0x31, ~0)|RD(~1)|ASI(~0),   "1,2,p", 0, 0, 0, leon }, /* pwr r,r,%psr */

{ "pwr",  F3(2, 0x31, 1)|RD(1), F3(~2, ~0x31, ~1)|RD(~1),     "1,i,p", 0, 0, 0, leon }, /* pwr r,i,%psr */

{ "pwr",  F3(2, 0x31, 0)|RD(1), F3(~2, ~0x31, ~0)|RD(~1)|RS1_G0|ASI(~0),  "2,p", F_PREF_ALIAS, 0, 0, leon }, /* pwr %g0,rs2,%psr */

{ "pwr",  F3(2, 0x31, 1)|RD(1), F3(~2, ~0x31, ~1)|RD(~1)|RS1_G0,    "i,p", F_PREF_ALIAS, 0, 0, leon }, /* pwr %g0,i,%psr */

{ "pwr",  F3(2, 0x31, 1)|RD(1), F3(~2, ~0x31, ~1)|RD(~1)|SIMM13(~0),    "1,p", F_PREF_ALIAS, 0, 0, leon }, /* pwr rs1,0,%psr */

{ "pwr",  F3(2, 0x31, 0)|RD(1), F3(~2, ~0x31, ~0)|RD(~1)|ASI_RS2(~0),   "1,p", F_PREF_ALIAS, 0, 0, leon }, /* pwr rs1,%g0,%psr */

{ "pause", F3(2, 0x30, 1)|RD(27)|RS1(0), F3(~2, ~0x30, ~1)|RD(~27)|RS1(~0), "i", 0, HWCAP_PAUSE, 0, v9e }, /* wr %g0,i,%pause */

{ "rd", F3(2, 0x28, 0)|RS1(2),    F3(~2, ~0x28, ~0)|RS1(~2)|SIMM13(~0), "E,d", 0, 0, 0, v9 }, /* rd %ccr,r */

{ "rd", F3(2, 0x28, 0)|RS1(3),    F3(~2, ~0x28, ~0)|RS1(~3)|SIMM13(~0), "o,d", 0, 0, 0, v9 }, /* rd %asi,r */

{ "rd", F3(2, 0x28, 0)|RS1(4),    F3(~2, ~0x28, ~0)|RS1(~4)|SIMM13(~0), "W,d", 0, 0, 0, v9 }, /* rd %tick,r */

{ "rd", F3(2, 0x28, 0)|RS1(5),    F3(~2, ~0x28, ~0)|RS1(~5)|SIMM13(~0), "P,d", 0, 0, 0, v9 }, /* rd %pc,r */

{ "rd", F3(2, 0x28, 0)|RS1(6),    F3(~2, ~0x28, ~0)|RS1(~6)|SIMM13(~0), "s,d", 0, 0, 0, v9 }, /* rd %fprs,r */

{ "rd", F3(2, 0x28, 0)|RS1(13),         F3(~2, ~0x28, ~0)|RS1(~13)|SIMM13(~0),  "&,d", 0, 0, HWCAP2_SPARC6, m8 }, /* rd %entropy,r */

{ "rd", F3(2, 0x28, 0)|RS1(14),         F3(~2, ~0x28, ~0)|RS1(~14)|SIMM13(~0),  "{,d", 0, 0, HWCAP2_SPARC5, v9m }, /* rd %mcdper,r */

/* Read from ASR registers 16..31, which is the range defined in SPARC

   V9 for implementation-dependent uses.  Note that the write-only ASR

   registers can't be used in a `rd' instruction.  */

#define rdasr(asr,hwcap,hwcap2,arch) \

  { "rd", F3(2, 0x28, 0)|RS1((asr)),  F3(~2, ~0x28, ~0)|RS1(~(asr))|SIMM13(~0), "/,d", 0, (hwcap), (hwcap2), (arch) }

rdasr (16, HWCAP_VIS,    0, v9a), /* rd %pcr,r  */

rdasr (17, HWCAP_VIS,    0, v9a), /* rd %pic,r  */

rdasr (18, HWCAP_VIS,    0, v9a), /* rd %dcr,r  */

rdasr (19, HWCAP_VIS,    0, v9a), /* rd %gsr,r  */

rdasr (22, HWCAP_VIS,    0, v9a), /* rd %softint,r  */

rdasr (23, HWCAP_VIS,    0, v9a), /* rd %tick_cmpr,r  */

rdasr (24, HWCAP_VIS2,   0, v9b), /* rd %sys_tick,r  */

rdasr (25, HWCAP_VIS2,   0, v9b), /* rd %sys_tick_cmpr,r  */

rdasr (26, HWCAP_CBCOND, 0, v9e), /* rd %cfr,r  */

{ "rd", F3(2, 0x28, 0),     F3(~2, ~0x28, ~0)|SIMM13(~0),   "M,d", 0, 0, 0, v8 }, /* rd %asrX,r */

{ "rd", F3(2, 0x28, 0),     F3(~2, ~0x28, ~0)|RS1_G0|SIMM13(~0),  "y,d", 0, 0, 0, v6 }, /* rd %y,r */

{ "rd", F3(2, 0x29, 0),     F3(~2, ~0x29, ~0)|RS1_G0|SIMM13(~0),  "p,d", 0, 0, 0, v6notv9 }, /* rd %psr,r */

{ "rd", F3(2, 0x2a, 0),     F3(~2, ~0x2a, ~0)|RS1_G0|SIMM13(~0),  "w,d", 0, 0, 0, v6notv9 }, /* rd %wim,r */

{ "rd", F3(2, 0x2b, 0),     F3(~2, ~0x2b, ~0)|RS1_G0|SIMM13(~0),  "t,d", 0, 0, 0, v6notv9 }, /* rd %tbr,r */

/* Instructions to read and write from/to privileged registers.  */

#define rdpr(reg,hwcap,hwcap2,arch) \

  { "rdpr", F3(2, 0x2a, 0)|RS1((reg)), F3(~2, ~0x2a, ~0)|RS1(~(reg))|SIMM13(~0),"?,d", 0, (hwcap), (hwcap2), (arch) } /* rdpr %priv,r */

rdpr (0, 0, 0, v9), /* rdpr %tpc,r  */

rdpr (1, 0, 0, v9), /* rdpr %tnpc,r  */

rdpr (2, 0, 0, v9), /* rdpr %tstate,r  */

rdpr (3, 0, 0, v9), /* rdpr %tt,r  */

rdpr (4, 0, 0, v9), /* rdpr %tick,r  */

rdpr (5, 0, 0, v9), /* rdpr %tba,r  */

rdpr (6, 0, 0, v9), /* rdpr %pstate,r  */

rdpr (7, 0, 0, v9), /* rdpr %tl,r  */

rdpr (8, 0, 0, v9), /* rdpr %pil,r  */

rdpr (9, 0, 0, v9), /* rdpr %cwp,r  */

rdpr (10, 0, 0, v9), /* rdpr %cansave,r  */

rdpr (11, 0, 0, v9), /* rdpr %canrestore,r  */

rdpr (12, 0, 0, v9), /* rdpr %cleanwin,r  */

rdpr (13, 0, 0, v9), /* rdpr %otherwin,r  */

rdpr (14, 0, 0, v9), /* rdpr %wstate,r  */

rdpr (15, 0, 0, v9), /* rdpr %fq,r  */

rdpr (16, 0, 0, v9), /* rdpr %gl,r  */

rdpr (23, 0, HWCAP2_SPARC5, v9m), /* rdpr %pmcdper,r  */

rdpr (31, 0, 0, v9), /* rdpr %ver,r  */

#define wrpr(reg,hwcap,hwcap2,arch) \

{ "wrpr", F3(2, 0x32, 0)|RD((reg)), F3(~2, ~0x32, ~0)|RD(~(reg)), "1,2,!", 0, (hwcap), (hwcap2), (arch) }, /* wrpr r1,r2,%priv */ \

{ "wrpr", F3(2, 0x32, 0)|RD((reg)), F3(~2, ~0x32, ~0)|RD(~(reg))|SIMM13(~0), "1,!", 0, (hwcap), (hwcap2), (arch) }, /* wrpr r1,%priv */ \

{ "wrpr", F3(2, 0x32, 1)|RD((reg)), F3(~2, ~0x32, ~1)|RD(~(reg)), "1,i,!", 0, (hwcap), (hwcap2), (arch) }, /* wrpr r1,i,%priv */ \

{ "wrpr", F3(2, 0x32, 1)|RD((reg)), F3(~2, ~0x32, ~1)|RD(~(reg)), "i,1,!", F_ALIAS, (hwcap), (hwcap2), (arch) }, /* wrpr i,r1,%priv */ \

{ "wrpr", F3(2, 0x32, 1)|RD((reg)), F3(~2, ~0x32, ~1)|RD(~(reg))|RS1(~0), "i,!", 0, (hwcap), (hwcap2), (arch) } /* wrpr i,%priv */

wrpr (0, 0, 0, v9), /* wrpr ...,%tpc  */

wrpr (1, 0, 0, v9), /* wrpr ...,%tnpc  */

wrpr (2, 0, 0, v9), /* wrpr ...,%tstate  */

wrpr (3, 0, 0, v9), /* wrpr ...,%tt  */

wrpr (4, 0, 0, v9), /* wrpr ...,%tick  */

wrpr (5, 0, 0, v9), /* wrpr ...,%tba  */

wrpr (6, 0, 0, v9), /* wrpr ...,%pstate  */

wrpr (7, 0, 0, v9), /* wrpr ...,%tl  */

wrpr (8, 0, 0, v9), /* wrpr ...,%pil  */

wrpr (9, 0, 0, v9), /* wrpr ...,%cwp  */

wrpr (10, 0, 0, v9), /* wrpr ...,%cansave  */

wrpr (11, 0, 0, v9), /* wrpr ...,%canrestore  */

wrpr (12, 0, 0, v9), /* wrpr ...,%cleanwin  */

wrpr (13, 0, 0, v9), /* wrpr ...,%otherwin  */

wrpr (14, 0, 0, v9), /* wrpr ...,%wstate  */

wrpr (15, 0, 0, v9), /* wrpr ...,%fq  */

wrpr (16, 0, 0, v9), /* wrpr ...,%gl  */

wrpr (23, 0, HWCAP2_SPARC5, v9m), /* wdpr ...,%pmcdper  */

wrpr (31, 0, 0, v9), /* wrpr ...,%ver */

/* Instructions to read and write from/to hyperprivileged

   registers.  */

#define rdhpr(reg,hwcap,hwcap2,arch) \

{ "rdhpr",  F3(2, 0x29, 0)|RS1((reg)),  F3(~2, ~0x29, ~0)|RS1(~(reg))|SIMM13(~0), "$,d", 0, (hwcap), (hwcap2), (arch) }

rdhpr (0, HWCAP_VIS, 0, v9a), /* rdhpr %hpstate,r  */

rdhpr (1, HWCAP_VIS, 0, v9a), /* rdhpr %htstate,r  */

rdhpr (3, HWCAP_VIS, 0, v9a), /* rdhpr %hintp,r  */

rdhpr (5, HWCAP_VIS, 0, v9a), /* rdhpr %htba,r  */

rdhpr (6, HWCAP_VIS, 0, v9a), /* rdhpr %hver,r  */

rdhpr (23, 0, HWCAP2_SPARC5, v9m), /* rdhpr %hmcdper,r  */

rdhpr (24, 0, HWCAP2_SPARC5, v9m), /* rdhpr %hmcddfr,r  */

rdhpr (27, 0, HWCAP2_SPARC5, v9m), /* rdhpr %hva_mask_nz,r  */

rdhpr (28, HWCAP_VIS, 0, v9a), /* rdhpr %hstick_offset,r  */

rdhpr (29, HWCAP_VIS, 0, v9a), /* rdhpar %hstick_enable,r  */

rdhpr (31, HWCAP_VIS, 0, v9a), /* rdhpr %hstick_cmpr,r  */

#define wrhpr(reg,hwcap,hwcap2,arch) \