/src/binutils-gdb/opcodes/v850-opc.c
Line | Count | Source (jump to first uncovered line) |
1 | | /* Assemble V850 instructions. |
2 | | Copyright (C) 1996-2025 Free Software Foundation, Inc. |
3 | | |
4 | | This file is part of the GNU opcodes library. |
5 | | |
6 | | This library is free software; you can redistribute it and/or modify |
7 | | it under the terms of the GNU General Public License as published by |
8 | | the Free Software Foundation; either version 3, or (at your option) |
9 | | any later version. |
10 | | |
11 | | It is distributed in the hope that it will be useful, but WITHOUT |
12 | | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY |
13 | | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public |
14 | | License for more details. |
15 | | |
16 | | You should have received a copy of the GNU General Public License |
17 | | along with this program; if not, write to the Free Software |
18 | | Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, |
19 | | MA 02110-1301, USA. */ |
20 | | |
21 | | #include "sysdep.h" |
22 | | #include <stdio.h> |
23 | | #include "opcode/v850.h" |
24 | | #include "bfd.h" |
25 | | #include "opintl.h" |
26 | | |
27 | | /* Regular opcodes. */ |
28 | | #define OP(x) ((x & 0x3f) << 5) |
29 | | #define OP_MASK OP (0x3f) |
30 | | |
31 | | /* Conditional branch opcodes (Format III). */ |
32 | | #define BOP(x) ((0x58 << 4) | (x & 0x0f)) |
33 | | #define BOP_MASK ((0x78 << 4) | 0x0f) |
34 | | |
35 | | /* Conditional branch opcodes (Format VII). */ |
36 | | #define BOP7(x) (0x107e0 | (x & 0xf)) |
37 | | #define BOP7_MASK (0x1ffe0 | 0xf) |
38 | | |
39 | | /* One-word opcodes. */ |
40 | | #define one(x) ((unsigned int) (x)) |
41 | | |
42 | | /* Two-word opcodes. */ |
43 | | #define two(x,y) ((unsigned int) (x) | ((unsigned int) (y) << 16)) |
44 | | |
45 | | |
46 | | /* The functions used to insert and extract complicated operands. */ |
47 | | |
48 | | /* Note: There is a conspiracy between these functions and |
49 | | v850_insert_operand() in gas/config/tc-v850.c. Error messages |
50 | | containing the string 'out of range' will be ignored unless a |
51 | | specific command line option is given to GAS. */ |
52 | | |
53 | | static const char * not_valid = N_ ("displacement value is not in range and is not aligned"); |
54 | | static const char * out_of_range = N_ ("displacement value is out of range"); |
55 | | static const char * not_aligned = N_ ("displacement value is not aligned"); |
56 | | |
57 | | static const char * immediate_out_of_range = N_ ("immediate value is out of range"); |
58 | | static const char * branch_out_of_range = N_ ("branch value out of range"); |
59 | | static const char * branch_out_of_range_and_odd_offset = N_ ("branch value not in range and to odd offset"); |
60 | | static const char * branch_to_odd_offset = N_ ("branch to odd offset"); |
61 | | static const char * pos_out_of_range = N_ ("position value is out of range"); |
62 | | static const char * width_out_of_range = N_ ("width value is out of range"); |
63 | | static const char * selid_out_of_range = N_ ("SelID is out of range"); |
64 | | static const char * vector8_out_of_range = N_ ("vector8 is out of range"); |
65 | | static const char * vector5_out_of_range = N_ ("vector5 is out of range"); |
66 | | static const char * imm10_out_of_range = N_ ("imm10 is out of range"); |
67 | | static const char * sr_selid_out_of_range = N_ ("SR/SelID is out of range"); |
68 | | |
69 | | int |
70 | | v850_msg_is_out_of_range (const char* msg) |
71 | 0 | { |
72 | 0 | return msg == out_of_range |
73 | 0 | || msg == immediate_out_of_range |
74 | 0 | || msg == branch_out_of_range; |
75 | 0 | } |
76 | | |
77 | | static unsigned long |
78 | | insert_i5div1 (unsigned long insn, unsigned long value, const char ** errmsg) |
79 | 0 | { |
80 | 0 | if (value > 30 || value < 2) |
81 | 0 | { |
82 | 0 | if (value & 1) |
83 | 0 | * errmsg = _(not_valid); |
84 | 0 | else |
85 | 0 | * errmsg = _(out_of_range); |
86 | 0 | } |
87 | 0 | else if (value & 1) |
88 | 0 | * errmsg = _(not_aligned); |
89 | |
|
90 | 0 | value = (32 - value)/2; |
91 | |
|
92 | 0 | return (insn | ((value << (2+16)) & 0x3c0000)); |
93 | 0 | } |
94 | | |
95 | | static unsigned long |
96 | | extract_i5div1 (unsigned long insn, int * invalid) |
97 | 348 | { |
98 | 348 | unsigned long ret = (insn & 0x003c0000) >> (16+2); |
99 | 348 | ret = 32 - (ret * 2); |
100 | | |
101 | 348 | if (invalid != 0) |
102 | 174 | *invalid = (ret > 30 || ret < 2) ? 1 : 0; |
103 | 348 | return ret; |
104 | 348 | } |
105 | | |
106 | | static unsigned long |
107 | | insert_i5div2 (unsigned long insn, unsigned long value, const char ** errmsg) |
108 | 0 | { |
109 | 0 | if (value > 30 || value < 4) |
110 | 0 | { |
111 | 0 | if (value & 1) |
112 | 0 | * errmsg = _(not_valid); |
113 | 0 | else |
114 | 0 | * errmsg = _(out_of_range); |
115 | 0 | } |
116 | 0 | else if (value & 1) |
117 | 0 | * errmsg = _(not_aligned); |
118 | |
|
119 | 0 | value = (32 - value)/2; |
120 | |
|
121 | 0 | return insn | ((value << (2 + 16)) & 0x3c0000); |
122 | 0 | } |
123 | | |
124 | | static unsigned long |
125 | | extract_i5div2 (unsigned long insn, int * invalid) |
126 | 706 | { |
127 | 706 | unsigned long ret = (insn & 0x003c0000) >> (16+2); |
128 | 706 | ret = 32 - (ret * 2); |
129 | | |
130 | 706 | if (invalid != 0) |
131 | 394 | *invalid = (ret > 30 || ret < 4) ? 1 : 0; |
132 | 706 | return ret; |
133 | 706 | } |
134 | | |
135 | | static unsigned long |
136 | | insert_i5div3 (unsigned long insn, unsigned long value, const char ** errmsg) |
137 | 0 | { |
138 | 0 | if (value > 32 || value < 2) |
139 | 0 | { |
140 | 0 | if (value & 1) |
141 | 0 | * errmsg = _(not_valid); |
142 | 0 | else |
143 | 0 | * errmsg = _(out_of_range); |
144 | 0 | } |
145 | 0 | else if (value & 1) |
146 | 0 | * errmsg = _(not_aligned); |
147 | |
|
148 | 0 | value = (32 - value)/2; |
149 | |
|
150 | 0 | return insn | ((value << (2+16)) & 0x3c0000); |
151 | 0 | } |
152 | | |
153 | | static unsigned long |
154 | | extract_i5div3 (unsigned long insn, int * invalid) |
155 | 470 | { |
156 | 470 | unsigned long ret = (insn & 0x003c0000) >> (16+2); |
157 | 470 | ret = 32 - (ret * 2); |
158 | | |
159 | 470 | if (invalid != 0) |
160 | 235 | *invalid = (ret > 32 || ret < 2) ? 1 : 0; |
161 | 470 | return ret; |
162 | 470 | } |
163 | | |
164 | | static unsigned long |
165 | | insert_d5_4 (unsigned long insn, unsigned long value, const char ** errmsg) |
166 | 0 | { |
167 | 0 | if (value > 0x1f) |
168 | 0 | { |
169 | 0 | if (value & 1) |
170 | 0 | * errmsg = _(not_valid); |
171 | 0 | else |
172 | 0 | * errmsg = _(out_of_range); |
173 | 0 | } |
174 | 0 | else if (value & 1) |
175 | 0 | * errmsg = _(not_aligned); |
176 | |
|
177 | 0 | value >>= 1; |
178 | |
|
179 | 0 | return insn | (value & 0x0f); |
180 | 0 | } |
181 | | |
182 | | static unsigned long |
183 | | extract_d5_4 (unsigned long insn, int * invalid) |
184 | 4.48k | { |
185 | 4.48k | unsigned long ret = (insn & 0x0f); |
186 | | |
187 | 4.48k | ret <<= 1; |
188 | | |
189 | 4.48k | if (invalid != 0) |
190 | 2.24k | *invalid = 0; |
191 | 4.48k | return ret; |
192 | 4.48k | } |
193 | | |
194 | | static unsigned long |
195 | | insert_d8_6 (unsigned long insn, unsigned long value, const char ** errmsg) |
196 | 0 | { |
197 | 0 | if (value > 0xff) |
198 | 0 | { |
199 | 0 | if ((value % 4) != 0) |
200 | 0 | * errmsg = _(not_valid); |
201 | 0 | else |
202 | 0 | * errmsg = _(out_of_range); |
203 | 0 | } |
204 | 0 | else if ((value % 4) != 0) |
205 | 0 | * errmsg = _(not_aligned); |
206 | |
|
207 | 0 | value >>= 1; |
208 | |
|
209 | 0 | return insn | (value & 0x7e); |
210 | 0 | } |
211 | | |
212 | | static unsigned long |
213 | | extract_d8_6 (unsigned long insn, int * invalid) |
214 | 42.6k | { |
215 | 42.6k | unsigned long ret = (insn & 0x7e); |
216 | | |
217 | 42.6k | ret <<= 1; |
218 | | |
219 | 42.6k | if (invalid != 0) |
220 | 21.3k | *invalid = 0; |
221 | 42.6k | return ret; |
222 | 42.6k | } |
223 | | |
224 | | static unsigned long |
225 | | insert_d8_7 (unsigned long insn, unsigned long value, const char ** errmsg) |
226 | 0 | { |
227 | 0 | if (value > 0xff) |
228 | 0 | { |
229 | 0 | if ((value % 2) != 0) |
230 | 0 | * errmsg = _(not_valid); |
231 | 0 | else |
232 | 0 | * errmsg = _(out_of_range); |
233 | 0 | } |
234 | 0 | else if ((value % 2) != 0) |
235 | 0 | * errmsg = _(not_aligned); |
236 | |
|
237 | 0 | value >>= 1; |
238 | |
|
239 | 0 | return insn | (value & 0x7f); |
240 | 0 | } |
241 | | |
242 | | static unsigned long |
243 | | extract_d8_7 (unsigned long insn, int * invalid) |
244 | 54.0k | { |
245 | 54.0k | unsigned long ret = (insn & 0x7f); |
246 | | |
247 | 54.0k | ret <<= 1; |
248 | | |
249 | 54.0k | if (invalid != 0) |
250 | 27.0k | *invalid = 0; |
251 | 54.0k | return ret; |
252 | 54.0k | } |
253 | | |
254 | | static unsigned long |
255 | | insert_v8 (unsigned long insn, unsigned long value, const char ** errmsg) |
256 | 0 | { |
257 | 0 | if (value > 0xff) |
258 | 0 | * errmsg = _(immediate_out_of_range); |
259 | |
|
260 | 0 | return insn | (value & 0x1f) | ((value & 0xe0) << (27-5)); |
261 | 0 | } |
262 | | |
263 | | static unsigned long |
264 | | extract_v8 (unsigned long insn, int * invalid) |
265 | 20 | { |
266 | 20 | unsigned long ret = (insn & 0x1f) | ((insn >> (27-5)) & 0xe0); |
267 | | |
268 | 20 | if (invalid != 0) |
269 | 10 | *invalid = 0; |
270 | 20 | return ret; |
271 | 20 | } |
272 | | |
273 | | static unsigned long |
274 | | insert_d9 (unsigned long insn, unsigned long value, const char ** errmsg) |
275 | 0 | { |
276 | 0 | if (value + 0x100 > 0x1ff) |
277 | 0 | { |
278 | 0 | if ((value % 2) != 0) |
279 | 0 | * errmsg = branch_out_of_range_and_odd_offset; |
280 | 0 | else |
281 | 0 | * errmsg = branch_out_of_range; |
282 | 0 | } |
283 | 0 | else if ((value % 2) != 0) |
284 | 0 | * errmsg = branch_to_odd_offset; |
285 | |
|
286 | 0 | return insn | ((value & 0x1f0) << 7) | ((value & 0x0e) << 3); |
287 | 0 | } |
288 | | |
289 | | static unsigned long |
290 | | extract_d9 (unsigned long insn, int * invalid) |
291 | 38.7k | { |
292 | 38.7k | unsigned long ret = ((insn >> 7) & 0x1f0) | ((insn >> 3) & 0x0e); |
293 | | |
294 | 38.7k | ret = (ret ^ 0x100) - 0x100; |
295 | | |
296 | 38.7k | if (invalid != 0) |
297 | 19.3k | *invalid = 0; |
298 | 38.7k | return ret; |
299 | 38.7k | } |
300 | | |
301 | | static unsigned long |
302 | | insert_u16_loop (unsigned long insn, unsigned long value, const char ** errmsg) |
303 | 0 | { |
304 | | /* Loop displacement is encoded as a positive value, |
305 | | even though the instruction branches backwards. */ |
306 | 0 | if (value > 0xffff) |
307 | 0 | { |
308 | 0 | if ((value % 2) != 0) |
309 | 0 | * errmsg = branch_out_of_range_and_odd_offset; |
310 | 0 | else |
311 | 0 | * errmsg = branch_out_of_range; |
312 | 0 | } |
313 | 0 | else if ((value % 2) != 0) |
314 | 0 | * errmsg = branch_to_odd_offset; |
315 | |
|
316 | 0 | return insn | ((value & 0xfffe) << 16); |
317 | 0 | } |
318 | | |
319 | | static unsigned long |
320 | | extract_u16_loop (unsigned long insn, int * invalid) |
321 | 810 | { |
322 | 810 | long ret = (insn >> 16) & 0xfffe; |
323 | | |
324 | 810 | if (invalid != 0) |
325 | 405 | *invalid = 0; |
326 | 810 | return ret; |
327 | 810 | } |
328 | | |
329 | | static unsigned long |
330 | | insert_d16_15 (unsigned long insn, unsigned long value, const char ** errmsg) |
331 | 0 | { |
332 | 0 | if (value + 0x8000 > 0xffff) |
333 | 0 | { |
334 | 0 | if ((value % 2) != 0) |
335 | 0 | * errmsg = _(not_valid); |
336 | 0 | else |
337 | 0 | * errmsg = _(out_of_range); |
338 | 0 | } |
339 | 0 | else if ((value % 2) != 0) |
340 | 0 | * errmsg = _(not_aligned); |
341 | |
|
342 | 0 | return insn | ((value & 0xfffe) << 16); |
343 | 0 | } |
344 | | |
345 | | static unsigned long |
346 | | extract_d16_15 (unsigned long insn, int * invalid) |
347 | 53.4k | { |
348 | 53.4k | unsigned long ret = (insn >> 16) & 0xfffe; |
349 | | |
350 | 53.4k | ret = (ret ^ 0x8000) - 0x8000; |
351 | | |
352 | 53.4k | if (invalid != 0) |
353 | 26.7k | *invalid = 0; |
354 | 53.4k | return ret; |
355 | 53.4k | } |
356 | | |
357 | | static unsigned long |
358 | | insert_d16_16 (unsigned long insn, unsigned long value, const char ** errmsg) |
359 | 0 | { |
360 | 0 | if (value + 0x8000 > 0xffff) |
361 | 0 | * errmsg = _(out_of_range); |
362 | |
|
363 | 0 | return insn | ((value & 0xfffe) << 16) | ((value & 1) << 5); |
364 | 0 | } |
365 | | |
366 | | static unsigned long |
367 | | extract_d16_16 (unsigned long insn, int * invalid) |
368 | 11.8k | { |
369 | 11.8k | unsigned long ret = ((insn >> 16) & 0xfffe) | ((insn >> 5) & 1); |
370 | | |
371 | 11.8k | ret = (ret ^ 0x8000) - 0x8000; |
372 | | |
373 | 11.8k | if (invalid != 0) |
374 | 7.66k | *invalid = 0; |
375 | 11.8k | return ret; |
376 | 11.8k | } |
377 | | |
378 | | static unsigned long |
379 | | insert_d17_16 (unsigned long insn, unsigned long value, const char ** errmsg) |
380 | 0 | { |
381 | 0 | if (value + 0x10000 > 0x1ffff) |
382 | 0 | * errmsg = _(out_of_range); |
383 | |
|
384 | 0 | return insn | ((value & 0xfffe) << 16) | ((value & 0x10000) >> (16 - 4)); |
385 | 0 | } |
386 | | |
387 | | static unsigned long |
388 | | extract_d17_16 (unsigned long insn, int * invalid) |
389 | 416 | { |
390 | 416 | unsigned long ret = ((insn >> 16) & 0xfffe) | ((insn << (16 - 4)) & 0x10000); |
391 | | |
392 | 416 | ret = (ret ^ 0x10000) - 0x10000; |
393 | | |
394 | 416 | if (invalid != 0) |
395 | 208 | *invalid = 0; |
396 | 416 | return ret; |
397 | 416 | } |
398 | | |
399 | | static unsigned long |
400 | | insert_d22 (unsigned long insn, unsigned long value, const char ** errmsg) |
401 | 0 | { |
402 | 0 | if (value + 0x200000 > 0x3fffff) |
403 | 0 | { |
404 | 0 | if ((value % 2) != 0) |
405 | 0 | * errmsg = branch_out_of_range_and_odd_offset; |
406 | 0 | else |
407 | 0 | * errmsg = branch_out_of_range; |
408 | 0 | } |
409 | 0 | else if ((value % 2) != 0) |
410 | 0 | * errmsg = branch_to_odd_offset; |
411 | |
|
412 | 0 | return insn | ((value & 0xfffe) << 16) | ((value & 0x3f0000) >> 16); |
413 | 0 | } |
414 | | |
415 | | static unsigned long |
416 | | extract_d22 (unsigned long insn, int * invalid) |
417 | 7.70k | { |
418 | 7.70k | unsigned long ret = ((insn >> 16) & 0xfffe) | ((insn << 16) & 0x3f0000); |
419 | | |
420 | 7.70k | ret = (ret ^ 0x200000) - 0x200000; |
421 | | |
422 | 7.70k | if (invalid != 0) |
423 | 4.31k | *invalid = 0; |
424 | 7.70k | return ret; |
425 | 7.70k | } |
426 | | |
427 | | static unsigned long |
428 | | insert_d23 (unsigned long insn, unsigned long value, const char ** errmsg) |
429 | 0 | { |
430 | 0 | if (value + 0x400000 > 0x7fffff) |
431 | 0 | * errmsg = out_of_range; |
432 | |
|
433 | 0 | return insn | ((value & 0x7f) << 4) | ((value & 0x7fff80) << (16-7)); |
434 | 0 | } |
435 | | |
436 | | static unsigned long |
437 | | insert_d23_align1 (unsigned long insn, unsigned long value, const char ** errmsg) |
438 | 0 | { |
439 | 0 | if (value + 0x400000 > 0x7fffff) |
440 | 0 | { |
441 | 0 | if (value & 0x1) |
442 | 0 | * errmsg = _(not_valid); |
443 | 0 | else |
444 | 0 | * errmsg = _(out_of_range); |
445 | 0 | } |
446 | 0 | else if (value & 0x1) |
447 | 0 | * errmsg = _(not_aligned); |
448 | |
|
449 | 0 | return insn | ((value & 0x7e) << 4) | ((value & 0x7fff80) << (16 - 7)); |
450 | 0 | } |
451 | | |
452 | | static unsigned long |
453 | | extract_d23 (unsigned long insn, int * invalid) |
454 | 4.32k | { |
455 | 4.32k | unsigned long ret = ((insn >> 4) & 0x7f) | ((insn >> (16-7)) & 0x7fff80); |
456 | | |
457 | 4.32k | ret = (ret ^ 0x400000) - 0x400000; |
458 | | |
459 | 4.32k | if (invalid != 0) |
460 | 2.16k | *invalid = 0; |
461 | 4.32k | return ret; |
462 | 4.32k | } |
463 | | |
464 | | static unsigned long |
465 | | insert_i9 (unsigned long insn, unsigned long value, const char ** errmsg) |
466 | 0 | { |
467 | 0 | if (value + 0x100 > 0x1ff) |
468 | 0 | * errmsg = _(immediate_out_of_range); |
469 | |
|
470 | 0 | return insn | ((value & 0x1e0) << 13) | (value & 0x1f); |
471 | 0 | } |
472 | | |
473 | | static unsigned long |
474 | | extract_i9 (unsigned long insn, int * invalid) |
475 | 120 | { |
476 | 120 | unsigned long ret = ((insn >> 13) & 0x1e0) | (insn & 0x1f); |
477 | | |
478 | 120 | ret = (ret ^ 0x100) - 0x100; |
479 | | |
480 | 120 | if (invalid != 0) |
481 | 60 | *invalid = 0; |
482 | 120 | return ret; |
483 | 120 | } |
484 | | |
485 | | static unsigned long |
486 | | insert_u9 (unsigned long insn, unsigned long value, const char ** errmsg) |
487 | 0 | { |
488 | 0 | if (value > 0x1ff) |
489 | 0 | * errmsg = _(immediate_out_of_range); |
490 | |
|
491 | 0 | return insn | ((value & 0x1e0) << 13) | (value & 0x1f); |
492 | 0 | } |
493 | | |
494 | | static unsigned long |
495 | | extract_u9 (unsigned long insn, int * invalid) |
496 | 98 | { |
497 | 98 | unsigned long ret = ((insn >> 13) & 0x1e0) | (insn & 0x1f); |
498 | | |
499 | 98 | if (invalid != 0) |
500 | 49 | *invalid = 0; |
501 | 98 | return ret; |
502 | 98 | } |
503 | | |
504 | | static unsigned long |
505 | | insert_spe (unsigned long insn, unsigned long value, const char ** errmsg) |
506 | 0 | { |
507 | 0 | if (value != 3) |
508 | 0 | * errmsg = _("invalid register for stack adjustment"); |
509 | |
|
510 | 0 | return insn & ~0x180000; |
511 | 0 | } |
512 | | |
513 | | static unsigned long |
514 | | extract_spe (unsigned long insn ATTRIBUTE_UNUSED, int * invalid) |
515 | 476 | { |
516 | 476 | if (invalid != 0) |
517 | 238 | *invalid = 0; |
518 | | |
519 | 476 | return 3; |
520 | 476 | } |
521 | | |
522 | | static unsigned long |
523 | | insert_r4 (unsigned long insn, unsigned long value, const char ** errmsg) |
524 | 0 | { |
525 | 0 | if (value >= 32) |
526 | 0 | * errmsg = _("invalid register name"); |
527 | |
|
528 | 0 | return insn | ((value & 0x01) << 23) | ((value & 0x1e) << 16); |
529 | 0 | } |
530 | | |
531 | | static unsigned long |
532 | | extract_r4 (unsigned long insn, int * invalid) |
533 | 140 | { |
534 | 140 | unsigned long r4; |
535 | 140 | unsigned long insn2; |
536 | | |
537 | 140 | insn2 = insn >> 16; |
538 | 140 | r4 = (((insn2 & 0x0080) >> 7) | (insn2 & 0x001e)); |
539 | | |
540 | 140 | if (invalid != 0) |
541 | 70 | *invalid = 0; |
542 | | |
543 | 140 | return r4; |
544 | 140 | } |
545 | | |
546 | | static unsigned long G_pos; |
547 | | |
548 | | static unsigned long |
549 | | insert_POS (unsigned long insn, unsigned long pos, const char ** errmsg) |
550 | 0 | { |
551 | 0 | if (pos > 0x1f) |
552 | 0 | * errmsg = _(pos_out_of_range); |
553 | |
|
554 | 0 | G_pos = pos; |
555 | |
|
556 | 0 | return insn; /* Not an oparaton until WIDTH. */ |
557 | 0 | } |
558 | | |
559 | | static unsigned long |
560 | | extract_POS_U (unsigned long insn, int * invalid) |
561 | 318 | { |
562 | 318 | unsigned long pos,lsb; |
563 | 318 | unsigned long insn2; |
564 | 318 | insn2 = insn >> 16; |
565 | | |
566 | 318 | lsb = ((insn2 & 0x0800) >> 8) |
567 | 318 | | ((insn2 & 0x000e) >> 1); |
568 | 318 | lsb += 16; |
569 | 318 | pos = lsb; |
570 | | |
571 | 318 | if (invalid != 0) |
572 | 159 | *invalid = 0; |
573 | | |
574 | 318 | return pos; |
575 | 318 | } |
576 | | |
577 | | static unsigned long |
578 | | extract_POS_L (unsigned long insn, int * invalid) |
579 | 296 | { |
580 | 296 | unsigned long pos,lsb; |
581 | 296 | unsigned long insn2; |
582 | 296 | insn2 = insn >> 16; |
583 | | |
584 | 296 | lsb = ((insn2 & 0x0800) >> 8) |
585 | 296 | | ((insn2 & 0x000e) >> 1); |
586 | 296 | pos = lsb; |
587 | | |
588 | 296 | if (invalid != 0) |
589 | 148 | *invalid = 0; |
590 | | |
591 | 296 | return pos; |
592 | 296 | } |
593 | | |
594 | | static unsigned long |
595 | | insert_WIDTH (unsigned long insn, unsigned long width, const char ** errmsg) |
596 | 0 | { |
597 | 0 | unsigned long msb, lsb, opc, ret; |
598 | 0 | unsigned long msb_expand, lsb_expand; |
599 | |
|
600 | 0 | msb = width + G_pos - 1; |
601 | 0 | lsb = G_pos; |
602 | 0 | opc = 0; |
603 | 0 | G_pos = 0; |
604 | |
|
605 | 0 | if (width > 0x20) |
606 | 0 | * errmsg = _(width_out_of_range); |
607 | |
|
608 | 0 | if ((msb >= 16) && (lsb >= 16)) |
609 | 0 | opc = 0x0090; |
610 | 0 | else if ((msb >= 16) && (lsb < 16)) |
611 | 0 | opc = 0x00b0; |
612 | 0 | else if ((msb < 16) && (lsb < 16)) |
613 | 0 | opc = 0x00d0; |
614 | 0 | else |
615 | 0 | * errmsg = _(width_out_of_range); |
616 | |
|
617 | 0 | msb &= 0x0f; |
618 | 0 | msb_expand = msb << 12; |
619 | 0 | lsb &= 0x0f; |
620 | 0 | lsb_expand = ((lsb & 0x8) << 8)|((lsb & 0x7) << 1); |
621 | |
|
622 | 0 | ret = (insn & 0x0000ffff) | ((opc | msb_expand | lsb_expand) << 16); |
623 | |
|
624 | 0 | return ret; |
625 | 0 | } |
626 | | |
627 | | static unsigned long |
628 | | extract_WIDTH_U (unsigned long insn, int * invalid) |
629 | 318 | { |
630 | 318 | unsigned long width, msb, lsb; |
631 | 318 | unsigned long insn2; |
632 | 318 | insn2 = insn >> 16; |
633 | | |
634 | 318 | msb = ((insn2 & 0xf000) >> 12); |
635 | 318 | msb += 16; |
636 | 318 | lsb = ((insn2 & 0x0800) >> 8) |
637 | 318 | | ((insn2 & 0x000e) >> 1); |
638 | 318 | lsb += 16; |
639 | | |
640 | 318 | if (invalid != 0) |
641 | 159 | *invalid = 0; |
642 | | |
643 | 318 | width = msb - lsb + 1; |
644 | | |
645 | 318 | return width; |
646 | 318 | } |
647 | | |
648 | | static unsigned long |
649 | | extract_WIDTH_M (unsigned long insn, int * invalid) |
650 | 174 | { |
651 | 174 | unsigned long width, msb, lsb; |
652 | 174 | unsigned long insn2; |
653 | 174 | insn2 = insn >> 16; |
654 | | |
655 | 174 | msb = ((insn2 & 0xf000) >> 12) ; |
656 | 174 | msb += 16; |
657 | 174 | lsb = ((insn2 & 0x0800) >> 8) |
658 | 174 | | ((insn2 & 0x000e) >> 1); |
659 | | |
660 | 174 | if (invalid != 0) |
661 | 87 | *invalid = 0; |
662 | | |
663 | 174 | width = msb - lsb + 1; |
664 | | |
665 | 174 | return width; |
666 | 174 | } |
667 | | |
668 | | static unsigned long |
669 | | extract_WIDTH_L (unsigned long insn, int * invalid) |
670 | 122 | { |
671 | 122 | unsigned long width, msb, lsb; |
672 | 122 | unsigned long insn2; |
673 | 122 | insn2 = insn >> 16; |
674 | | |
675 | 122 | msb = ((insn2 & 0xf000) >> 12) ; |
676 | 122 | lsb = ((insn2 & 0x0800) >> 8) |
677 | 122 | | ((insn2 & 0x000e) >> 1); |
678 | | |
679 | 122 | if (invalid != 0) |
680 | 61 | *invalid = 0; |
681 | | |
682 | 122 | width = msb - lsb + 1; |
683 | | |
684 | 122 | return width; |
685 | 122 | } |
686 | | |
687 | | static unsigned long |
688 | | insert_SELID (unsigned long insn, unsigned long selid, const char ** errmsg) |
689 | 0 | { |
690 | 0 | if (selid > 0x1f) |
691 | 0 | * errmsg = _(selid_out_of_range); |
692 | |
|
693 | 0 | return insn | ((selid & 0x1fUL) << 27); |
694 | 0 | } |
695 | | |
696 | | static unsigned long |
697 | | extract_SELID (unsigned long insn, int * invalid) |
698 | 686 | { |
699 | 686 | unsigned long selid; |
700 | 686 | unsigned long insn2; |
701 | | |
702 | 686 | insn2 = insn >> 16; |
703 | | |
704 | 686 | selid = ((insn2 & 0xf800) >> 11); |
705 | | |
706 | 686 | if (invalid != 0) |
707 | 343 | *invalid = 0; |
708 | | |
709 | 686 | return selid; |
710 | 686 | } |
711 | | |
712 | | static unsigned long |
713 | | insert_VECTOR8 (unsigned long insn, unsigned long vector8, const char ** errmsg) |
714 | 0 | { |
715 | 0 | unsigned long ret; |
716 | 0 | unsigned long VVV, vvvvv; |
717 | |
|
718 | 0 | if (vector8 > 0xff) |
719 | 0 | * errmsg = _(vector8_out_of_range); |
720 | |
|
721 | 0 | VVV = (vector8 & 0xe0) >> 5; |
722 | 0 | vvvvv = (vector8 & 0x1f); |
723 | |
|
724 | 0 | ret = (insn | (VVV << 27) | vvvvv); |
725 | |
|
726 | 0 | return ret; |
727 | 0 | } |
728 | | |
729 | | static unsigned long |
730 | | extract_VECTOR8 (unsigned long insn, int * invalid) |
731 | 104 | { |
732 | 104 | unsigned long vector8; |
733 | 104 | unsigned long VVV,vvvvv; |
734 | 104 | unsigned long insn2; |
735 | | |
736 | 104 | insn2 = insn >> 16; |
737 | 104 | VVV = ((insn2 & 0x3800) >> 11); |
738 | 104 | vvvvv = (insn & 0x001f); |
739 | 104 | vector8 = VVV << 5 | vvvvv; |
740 | | |
741 | 104 | if (invalid != 0) |
742 | 52 | *invalid = 0; |
743 | | |
744 | 104 | return vector8; |
745 | 104 | } |
746 | | |
747 | | static unsigned long |
748 | | insert_VECTOR5 (unsigned long insn, unsigned long vector5, const char ** errmsg) |
749 | 0 | { |
750 | 0 | unsigned long ret; |
751 | 0 | unsigned long vvvvv; |
752 | |
|
753 | 0 | if (vector5 > 0x1f) |
754 | 0 | * errmsg = _(vector5_out_of_range); |
755 | |
|
756 | 0 | vvvvv = (vector5 & 0x1f); |
757 | |
|
758 | 0 | ret = (insn | vvvvv); |
759 | |
|
760 | 0 | return ret; |
761 | 0 | } |
762 | | |
763 | | static unsigned long |
764 | | extract_VECTOR5 (unsigned long insn, int * invalid) |
765 | 80 | { |
766 | 80 | unsigned long vector5; |
767 | | |
768 | 80 | vector5 = (insn & 0x001f); |
769 | | |
770 | 80 | if (invalid != 0) |
771 | 40 | *invalid = 0; |
772 | | |
773 | 80 | return vector5; |
774 | 80 | } |
775 | | |
776 | | static unsigned long |
777 | | insert_CACHEOP (unsigned long insn, unsigned long cacheop, const char ** errmsg ATTRIBUTE_UNUSED) |
778 | 0 | { |
779 | 0 | unsigned long ret; |
780 | 0 | unsigned long pp, PPPPP; |
781 | |
|
782 | 0 | pp = (cacheop & 0x60) >> 5; |
783 | 0 | PPPPP = (cacheop & 0x1f); |
784 | |
|
785 | 0 | ret = insn | (pp << 11) | (PPPPP << 27); |
786 | |
|
787 | 0 | return ret; |
788 | 0 | } |
789 | | |
790 | | static unsigned long |
791 | | extract_CACHEOP (unsigned long insn, int * invalid) |
792 | 630 | { |
793 | 630 | unsigned long ret; |
794 | 630 | unsigned long pp, PPPPP; |
795 | 630 | unsigned long insn2; |
796 | | |
797 | 630 | insn2 = insn >> 16; |
798 | | |
799 | 630 | PPPPP = ((insn2 & 0xf800) >> 11); |
800 | 630 | pp = ((insn & 0x1800) >> 11); |
801 | | |
802 | 630 | ret = (pp << 5) | PPPPP; |
803 | | |
804 | 630 | if (invalid != 0) |
805 | 315 | *invalid = 0; |
806 | | |
807 | 630 | return ret; |
808 | 630 | } |
809 | | |
810 | | static unsigned long |
811 | | insert_PREFOP (unsigned long insn, unsigned long prefop, const char ** errmsg ATTRIBUTE_UNUSED) |
812 | 0 | { |
813 | 0 | unsigned long ret; |
814 | 0 | unsigned long PPPPP; |
815 | |
|
816 | 0 | PPPPP = (prefop & 0x1f); |
817 | |
|
818 | 0 | ret = insn | (PPPPP << 27); |
819 | |
|
820 | 0 | return ret; |
821 | 0 | } |
822 | | |
823 | | static unsigned long |
824 | | extract_PREFOP (unsigned long insn, int * invalid) |
825 | 904 | { |
826 | 904 | unsigned long ret; |
827 | 904 | unsigned long PPPPP; |
828 | 904 | unsigned long insn2; |
829 | | |
830 | 904 | insn2 = insn >> 16; |
831 | | |
832 | 904 | PPPPP = (insn2 & 0xf800) >> 11; |
833 | | |
834 | 904 | ret = PPPPP; |
835 | | |
836 | 904 | if (invalid != 0) |
837 | 452 | *invalid = 0; |
838 | | |
839 | 904 | return ret; |
840 | 904 | } |
841 | | |
842 | | static unsigned long |
843 | | insert_IMM10U (unsigned long insn, unsigned long value, const char ** errmsg) |
844 | 0 | { |
845 | 0 | unsigned long imm10, ret; |
846 | 0 | unsigned long iiiii,IIIII; |
847 | |
|
848 | 0 | if (value > 0x3ff) |
849 | 0 | * errmsg = _(imm10_out_of_range); |
850 | |
|
851 | 0 | imm10 = value & 0x3ff; |
852 | 0 | IIIII = (imm10 >> 5) & 0x1f; |
853 | 0 | iiiii = imm10 & 0x1f; |
854 | |
|
855 | 0 | ret = insn | IIIII << 27 | iiiii; |
856 | |
|
857 | 0 | return ret; |
858 | 0 | } |
859 | | |
860 | | static unsigned long |
861 | | extract_IMM10U (unsigned long insn, int * invalid) |
862 | 138 | { |
863 | 138 | unsigned long ret; |
864 | 138 | unsigned long iiiii,IIIII; |
865 | 138 | unsigned long insn2; |
866 | 138 | insn2 = insn >> 16; |
867 | | |
868 | 138 | IIIII = ((insn2 & 0xf800) >> 11); |
869 | 138 | iiiii = (insn & 0x001f); |
870 | | |
871 | 138 | ret = (IIIII << 5) | iiiii; |
872 | | |
873 | 138 | if (invalid != 0) |
874 | 69 | *invalid = 0; |
875 | | |
876 | 138 | return ret; |
877 | 138 | } |
878 | | |
879 | | static unsigned long |
880 | | insert_SRSEL1 (unsigned long insn, unsigned long value, const char ** errmsg) |
881 | 0 | { |
882 | 0 | unsigned long imm10, ret; |
883 | 0 | unsigned long sr,selid; |
884 | |
|
885 | 0 | if (value > 0x3ff) |
886 | 0 | * errmsg = _(sr_selid_out_of_range); |
887 | |
|
888 | 0 | imm10 = value; |
889 | 0 | selid = (imm10 & 0x3e0) >> 5; |
890 | 0 | sr = imm10 & 0x1f; |
891 | |
|
892 | 0 | ret = insn | selid << 27 | sr; |
893 | |
|
894 | 0 | return ret; |
895 | 0 | } |
896 | | |
897 | | static unsigned long |
898 | | extract_SRSEL1 (unsigned long insn, int * invalid) |
899 | 230 | { |
900 | 230 | unsigned long ret; |
901 | 230 | unsigned long sr, selid; |
902 | 230 | unsigned long insn2; |
903 | | |
904 | 230 | insn2 = insn >> 16; |
905 | | |
906 | 230 | selid = ((insn2 & 0xf800) >> 11); |
907 | 230 | sr = (insn & 0x001f); |
908 | | |
909 | 230 | ret = (selid << 5) | sr; |
910 | | |
911 | 230 | if (invalid != 0) |
912 | 115 | *invalid = 0; |
913 | | |
914 | 230 | return ret; |
915 | 230 | } |
916 | | |
917 | | static unsigned long |
918 | | insert_SRSEL2 (unsigned long insn, unsigned long value, const char ** errmsg) |
919 | 0 | { |
920 | 0 | unsigned long imm10, ret; |
921 | 0 | unsigned long sr, selid; |
922 | |
|
923 | 0 | if (value > 0x3ff) |
924 | 0 | * errmsg = _(sr_selid_out_of_range); |
925 | |
|
926 | 0 | imm10 = value; |
927 | 0 | selid = (imm10 & 0x3e0) >> 5; |
928 | 0 | sr = imm10 & 0x1f; |
929 | |
|
930 | 0 | ret = insn | selid << 27 | sr << 11; |
931 | |
|
932 | 0 | return ret; |
933 | 0 | } |
934 | | |
935 | | static unsigned long |
936 | | extract_SRSEL2 (unsigned long insn, int * invalid) |
937 | 456 | { |
938 | 456 | unsigned long ret; |
939 | 456 | unsigned long sr, selid; |
940 | 456 | unsigned long insn2; |
941 | | |
942 | 456 | insn2 = insn >> 16; |
943 | | |
944 | 456 | selid = ((insn2 & 0xf800) >> 11); |
945 | 456 | sr = ((insn & 0xf800) >> 11); |
946 | | |
947 | 456 | ret = (selid << 5) | sr; |
948 | | |
949 | 456 | if (invalid != 0) |
950 | 228 | *invalid = 0; |
951 | | |
952 | 456 | return ret; |
953 | 456 | } |
954 | | |
955 | | /* Warning: code in gas/config/tc-v850.c examines the contents of this array. |
956 | | If you change any of the values here, be sure to look for side effects in |
957 | | that code. */ |
958 | | const struct v850_operand v850_operands[] = |
959 | | { |
960 | | #define UNUSED 0 |
961 | | { 0, 0, NULL, NULL, 0, BFD_RELOC_NONE }, |
962 | | |
963 | | /* The R1 field in a format 1, 6, 7, 9, C insn. */ |
964 | | #define R1 (UNUSED + 1) |
965 | | { 5, 0, NULL, NULL, V850_OPERAND_REG, BFD_RELOC_NONE }, |
966 | | |
967 | | /* As above, but register 0 is not allowed. */ |
968 | | #define R1_NOTR0 (R1 + 1) |
969 | | { 5, 0, NULL, NULL, V850_OPERAND_REG | V850_NOT_R0, BFD_RELOC_NONE }, |
970 | | |
971 | | /* Even register is allowed. */ |
972 | | #define R1_EVEN (R1_NOTR0 + 1) |
973 | | { 4, 1, NULL, NULL, V850_OPERAND_REG | V850_REG_EVEN, BFD_RELOC_NONE }, |
974 | | |
975 | | /* Bang (bit reverse). */ |
976 | | #define R1_BANG (R1_EVEN + 1) |
977 | | { 5, 0, NULL, NULL, V850_OPERAND_REG | V850_OPERAND_BANG, BFD_RELOC_NONE }, |
978 | | |
979 | | /* Percent (modulo). */ |
980 | | #define R1_PERCENT (R1_BANG + 1) |
981 | | { 5, 0, NULL, NULL, V850_OPERAND_REG | V850_OPERAND_PERCENT, BFD_RELOC_NONE }, |
982 | | |
983 | | /* The R2 field in a format 1, 2, 4, 5, 6, 7, 9, C insn. */ |
984 | | #define R2 (R1_PERCENT + 1) |
985 | | { 5, 11, NULL, NULL, V850_OPERAND_REG, BFD_RELOC_NONE }, |
986 | | |
987 | | /* As above, but register 0 is not allowed. */ |
988 | | #define R2_NOTR0 (R2 + 1) |
989 | | { 5, 11, NULL, NULL, V850_OPERAND_REG | V850_NOT_R0, BFD_RELOC_NONE }, |
990 | | |
991 | | /* Even register is allowed. */ |
992 | | #define R2_EVEN (R2_NOTR0 + 1) |
993 | | { 4, 12, NULL, NULL, V850_OPERAND_REG | V850_REG_EVEN, BFD_RELOC_NONE }, |
994 | | |
995 | | /* Reg2 in dispose instruction. */ |
996 | | #define R2_DISPOSE (R2_EVEN + 1) |
997 | | { 5, 16, NULL, NULL, V850_OPERAND_REG | V850_NOT_R0, BFD_RELOC_NONE }, |
998 | | |
999 | | /* The R3 field in a format 11, 12, C insn. */ |
1000 | | #define R3 (R2_DISPOSE + 1) |
1001 | | { 5, 27, NULL, NULL, V850_OPERAND_REG, BFD_RELOC_NONE }, |
1002 | | |
1003 | | /* As above, but register 0 is not allowed. */ |
1004 | | #define R3_NOTR0 (R3 + 1) |
1005 | | { 5, 27, NULL, NULL, V850_OPERAND_REG | V850_NOT_R0, BFD_RELOC_NONE }, |
1006 | | |
1007 | | /* As above, but odd number registers are not allowed. */ |
1008 | | #define R3_EVEN (R3_NOTR0 + 1) |
1009 | | { 4, 28, NULL, NULL, V850_OPERAND_REG | V850_REG_EVEN, BFD_RELOC_NONE }, |
1010 | | |
1011 | | /* As above, but register 0 is not allowed. */ |
1012 | | #define R3_EVEN_NOTR0 (R3_EVEN + 1) |
1013 | | { 4, 28, NULL, NULL, V850_OPERAND_REG | V850_REG_EVEN | V850_NOT_R0, BFD_RELOC_NONE }, |
1014 | | |
1015 | | /* Forth register in FPU Instruction. */ |
1016 | | #define R4 (R3_EVEN_NOTR0 + 1) |
1017 | | { 5, 0, insert_r4, extract_r4, V850_OPERAND_REG, BFD_RELOC_NONE }, |
1018 | | |
1019 | | /* As above, but odd number registers are not allowed. */ |
1020 | | #define R4_EVEN (R4 + 1) |
1021 | | { 4, 17, NULL, NULL, V850_OPERAND_REG | V850_REG_EVEN, BFD_RELOC_NONE }, |
1022 | | |
1023 | | /* Stack pointer in prepare instruction. */ |
1024 | | #define SP (R4_EVEN + 1) |
1025 | | { 2, 0, insert_spe, extract_spe, V850_OPERAND_REG, BFD_RELOC_NONE }, |
1026 | | |
1027 | | /* EP Register. */ |
1028 | | #define EP (SP + 1) |
1029 | | { 0, 0, NULL, NULL, V850_OPERAND_EP, BFD_RELOC_NONE }, |
1030 | | |
1031 | | /* A list of registers in a prepare/dispose instruction. */ |
1032 | | #define LIST12 (EP + 1) |
1033 | | { -1, 0xffe00001, NULL, NULL, V850E_OPERAND_REG_LIST, BFD_RELOC_NONE }, |
1034 | | |
1035 | | /* System register operands. */ |
1036 | | #define OLDSR1 (LIST12 + 1) |
1037 | | { 5, 0, NULL, NULL, V850_OPERAND_SRG, BFD_RELOC_NONE }, |
1038 | | |
1039 | | #define SR1 (OLDSR1 + 1) |
1040 | | { 0, 0, insert_SRSEL1, extract_SRSEL1, V850_OPERAND_SRG, BFD_RELOC_NONE }, |
1041 | | |
1042 | | /* The R2 field as a system register. */ |
1043 | | #define OLDSR2 (SR1 + 1) |
1044 | | { 5, 11, NULL, NULL, V850_OPERAND_SRG, BFD_RELOC_NONE }, |
1045 | | |
1046 | | #define SR2 (OLDSR2 + 1) |
1047 | | { 0, 0, insert_SRSEL2, extract_SRSEL2, V850_OPERAND_SRG, BFD_RELOC_NONE }, |
1048 | | |
1049 | | /* FPU CC bit position. */ |
1050 | | #define FFF (SR2 + 1) |
1051 | | { 3, 17, NULL, NULL, 0, BFD_RELOC_NONE }, |
1052 | | |
1053 | | /* The 4 bit condition code in a setf instruction. */ |
1054 | | #define CCCC (FFF + 1) |
1055 | | { 4, 0, NULL, NULL, V850_OPERAND_CC, BFD_RELOC_NONE }, |
1056 | | |
1057 | | /* Condition code in adf,sdf. */ |
1058 | | #define CCCC_NOTSA (CCCC + 1) |
1059 | | { 4, 17, NULL, NULL, V850_OPERAND_CC|V850_NOT_SA, BFD_RELOC_NONE }, |
1060 | | |
1061 | | /* Condition code in conditional moves. */ |
1062 | | #define MOVCC (CCCC_NOTSA + 1) |
1063 | | { 4, 17, NULL, NULL, V850_OPERAND_CC, BFD_RELOC_NONE }, |
1064 | | |
1065 | | /* Condition code in FPU. */ |
1066 | | #define FLOAT_CCCC (MOVCC + 1) |
1067 | | { 4, 27, NULL, NULL, V850_OPERAND_FLOAT_CC, BFD_RELOC_NONE }, |
1068 | | |
1069 | | /* The 1 bit immediate field in format C insn. */ |
1070 | | #define VI1 (FLOAT_CCCC + 1) |
1071 | | { 1, 3, NULL, NULL, 0, BFD_RELOC_NONE }, |
1072 | | |
1073 | | /* The 1 bit immediate field in format C insn. */ |
1074 | | #define VC1 (VI1 + 1) |
1075 | | { 1, 0, NULL, NULL, 0, BFD_RELOC_NONE }, |
1076 | | |
1077 | | /* The 2 bit immediate field in format C insn. */ |
1078 | | #define DI2 (VC1 + 1) |
1079 | | { 2, 17, NULL, NULL, 0, BFD_RELOC_NONE }, |
1080 | | |
1081 | | /* The 2 bit immediate field in format C insn. */ |
1082 | | #define VI2 (DI2 + 1) |
1083 | | { 2, 0, NULL, NULL, 0, BFD_RELOC_NONE }, |
1084 | | |
1085 | | /* The 2 bit immediate field in format C - DUP insn. */ |
1086 | | #define VI2DUP (VI2 + 1) |
1087 | | { 2, 2, NULL, NULL, 0, BFD_RELOC_NONE }, |
1088 | | |
1089 | | /* The 3 bit immediate field in format 8 insn. */ |
1090 | | #define B3 (VI2DUP + 1) |
1091 | | { 3, 11, NULL, NULL, 0, BFD_RELOC_NONE }, |
1092 | | |
1093 | | /* The 3 bit immediate field in format C insn. */ |
1094 | | #define DI3 (B3 + 1) |
1095 | | { 3, 17, NULL, NULL, 0, BFD_RELOC_NONE }, |
1096 | | |
1097 | | /* The 3 bit immediate field in format C insn. */ |
1098 | | #define I3U (DI3 + 1) |
1099 | | { 3, 0, NULL, NULL, 0, BFD_RELOC_NONE }, |
1100 | | |
1101 | | /* The 4 bit immediate field in format C insn. */ |
1102 | | #define I4U (I3U + 1) |
1103 | | { 4, 0, NULL, NULL, 0, BFD_RELOC_NONE }, |
1104 | | |
1105 | | /* The 4 bit immediate field in fetrap. */ |
1106 | | #define I4U_NOTIMM0 (I4U + 1) |
1107 | | { 4, 11, NULL, NULL, V850_NOT_IMM0, BFD_RELOC_NONE }, |
1108 | | |
1109 | | /* The unsigned disp4 field in a sld.bu. */ |
1110 | | #define D4U (I4U_NOTIMM0 + 1) |
1111 | | { 4, 0, NULL, NULL, V850_OPERAND_DISP, BFD_RELOC_V850_TDA_4_4_OFFSET }, |
1112 | | |
1113 | | /* The imm5 field in a format 2 insn. */ |
1114 | | #define I5 (D4U + 1) |
1115 | | { 5, 0, NULL, NULL, V850_OPERAND_SIGNED, BFD_RELOC_NONE }, |
1116 | | |
1117 | | /* The imm5 field in a format 11 insn. */ |
1118 | | #define I5DIV1 (I5 + 1) |
1119 | | { 5, 0, insert_i5div1, extract_i5div1, 0, BFD_RELOC_NONE }, |
1120 | | |
1121 | | #define I5DIV2 (I5DIV1 + 1) |
1122 | | { 5, 0, insert_i5div2, extract_i5div2, 0, BFD_RELOC_NONE }, |
1123 | | |
1124 | | #define I5DIV3 (I5DIV2 + 1) |
1125 | | { 5, 0, insert_i5div3, extract_i5div3, 0, BFD_RELOC_NONE }, |
1126 | | |
1127 | | /* The unsigned imm5 field in a format 2 insn. */ |
1128 | | #define I5U (I5DIV3 + 1) |
1129 | | { 5, 0, NULL, NULL, 0, BFD_RELOC_NONE }, |
1130 | | |
1131 | | /* The imm5 field in a prepare/dispose instruction. */ |
1132 | | #define IMM5 (I5U + 1) |
1133 | | { 5, 1, NULL, NULL, 0, BFD_RELOC_NONE }, |
1134 | | |
1135 | | /* The unsigned disp5 field in a sld.hu. */ |
1136 | | #define D5_4U (IMM5 + 1) |
1137 | | { 5, 0, insert_d5_4, extract_d5_4, V850_OPERAND_DISP, BFD_RELOC_V850_TDA_4_5_OFFSET }, |
1138 | | |
1139 | | /* The IMM6 field in a callt instruction. */ |
1140 | | #define IMM6 (D5_4U + 1) |
1141 | | { 6, 0, NULL, NULL, 0, BFD_RELOC_V850_CALLT_6_7_OFFSET }, |
1142 | | |
1143 | | /* The signed disp7 field in a format 4 insn. */ |
1144 | | #define D7U (IMM6 + 1) |
1145 | | { 7, 0, NULL, NULL, V850_OPERAND_DISP, BFD_RELOC_V850_TDA_7_7_OFFSET }, |
1146 | | |
1147 | | /* The unsigned DISP8 field in a format 4 insn. */ |
1148 | | #define D8_7U (D7U + 1) |
1149 | | { 8, 0, insert_d8_7, extract_d8_7, V850_OPERAND_DISP, BFD_RELOC_V850_TDA_7_8_OFFSET }, |
1150 | | |
1151 | | /* The unsigned DISP8 field in a format 4 insn. */ |
1152 | | #define D8_6U (D8_7U + 1) |
1153 | | { 8, 0, insert_d8_6, extract_d8_6, V850_OPERAND_DISP, BFD_RELOC_V850_TDA_6_8_OFFSET }, |
1154 | | |
1155 | | /* The unsigned DISP8 field in a format 4 insn. */ |
1156 | | #define V8 (D8_6U + 1) |
1157 | | { 8, 0, insert_v8, extract_v8, 0, BFD_RELOC_NONE }, |
1158 | | |
1159 | | /* The imm9 field in a multiply word. */ |
1160 | | #define I9 (V8 + 1) |
1161 | | { 9, 0, insert_i9, extract_i9, V850_OPERAND_SIGNED, BFD_RELOC_NONE }, |
1162 | | |
1163 | | /* The unsigned imm9 field in a multiply word. */ |
1164 | | #define U9 (I9 + 1) |
1165 | | { 9, 0, insert_u9, extract_u9, 0, BFD_RELOC_NONE }, |
1166 | | |
1167 | | /* The DISP9 field in a format 3 insn. */ |
1168 | | #define D9 (U9 + 1) |
1169 | | { 9, 0, insert_d9, extract_d9, V850_OPERAND_SIGNED | V850_OPERAND_DISP | V850_PCREL, BFD_RELOC_V850_9_PCREL }, |
1170 | | |
1171 | | /* The DISP9 field in a format 3 insn, relaxable. */ |
1172 | | #define D9_RELAX (D9 + 1) |
1173 | | { 9, 0, insert_d9, extract_d9, V850_OPERAND_RELAX | V850_OPERAND_SIGNED | V850_OPERAND_DISP | V850_PCREL, BFD_RELOC_V850_9_PCREL }, |
1174 | | |
1175 | | /* The imm16 field in a format 6 insn. */ |
1176 | | #define I16 (D9_RELAX + 1) |
1177 | | { 16, 16, NULL, NULL, V850_OPERAND_SIGNED, BFD_RELOC_16 }, |
1178 | | |
1179 | | /* The signed 16 bit immediate following a prepare instruction. */ |
1180 | | #define IMM16LO (I16 + 1) |
1181 | | { 16, 32, NULL, NULL, V850E_IMMEDIATE16 | V850_OPERAND_SIGNED, BFD_RELOC_LO16 }, |
1182 | | |
1183 | | /* The hi 16 bit immediate following a 32 bit instruction. */ |
1184 | | #define IMM16HI (IMM16LO + 1) |
1185 | | { 16, 16, NULL, NULL, V850E_IMMEDIATE16HI, BFD_RELOC_HI16 }, |
1186 | | |
1187 | | /* The unsigned imm16 in a format 6 insn. */ |
1188 | | #define I16U (IMM16HI + 1) |
1189 | | { 16, 16, NULL, NULL, 0, BFD_RELOC_16 }, |
1190 | | |
1191 | | /* The disp16 field in a format 8 insn. */ |
1192 | | #define D16 (I16U + 1) |
1193 | | { 16, 16, NULL, NULL, V850_OPERAND_SIGNED | V850_OPERAND_DISP, BFD_RELOC_V850_LO16_SPLIT_OFFSET }, |
1194 | | |
1195 | | /* The disp16 field in an format 7 unsigned byte load insn. */ |
1196 | | #define D16_16 (D16 + 1) |
1197 | | { 16, 0, insert_d16_16, extract_d16_16, V850_OPERAND_SIGNED | V850_OPERAND_DISP, BFD_RELOC_V850_16_SPLIT_OFFSET }, |
1198 | | |
1199 | | /* The disp16 field in a format 6 insn. */ |
1200 | | #define D16_15 (D16_16 + 1) |
1201 | | { 16, 0, insert_d16_15, extract_d16_15, V850_OPERAND_SIGNED | V850_OPERAND_DISP , BFD_RELOC_V850_16_S1 }, |
1202 | | |
1203 | | /* The unsigned DISP16 field in a format 7 insn. */ |
1204 | | #define D16_LOOP (D16_15 + 1) |
1205 | | { 16, 0, insert_u16_loop, extract_u16_loop, V850_OPERAND_RELAX | V850_OPERAND_DISP | V850_PCREL | V850_INVERSE_PCREL, BFD_RELOC_V850_16_PCREL }, |
1206 | | |
1207 | | /* The DISP17 field in a format 7 insn. */ |
1208 | | #define D17_16 (D16_LOOP + 1) |
1209 | | { 17, 0, insert_d17_16, extract_d17_16, V850_OPERAND_SIGNED | V850_OPERAND_DISP | V850_PCREL, BFD_RELOC_V850_17_PCREL }, |
1210 | | |
1211 | | /* The DISP22 field in a format 4 insn, relaxable. |
1212 | | This _must_ follow D9_RELAX; the assembler assumes that the longer |
1213 | | version immediately follows the shorter version for relaxing. */ |
1214 | | #define D22 (D17_16 + 1) |
1215 | | { 22, 0, insert_d22, extract_d22, V850_OPERAND_SIGNED | V850_OPERAND_DISP | V850_PCREL, BFD_RELOC_V850_22_PCREL }, |
1216 | | |
1217 | | #define D23 (D22 + 1) |
1218 | | { 23, 0, insert_d23, extract_d23, V850E_IMMEDIATE23 | V850_OPERAND_SIGNED | V850_OPERAND_DISP, BFD_RELOC_V850_23 }, |
1219 | | |
1220 | | #define D23_ALIGN1 (D23 + 1) |
1221 | | { 23, 0, insert_d23_align1, extract_d23, V850E_IMMEDIATE23 | V850_OPERAND_SIGNED | V850_OPERAND_DISP, BFD_RELOC_V850_23 }, |
1222 | | |
1223 | | /* The 32 bit immediate following a 32 bit instruction. */ |
1224 | | #define IMM32 (D23_ALIGN1 + 1) |
1225 | | { 32, 32, NULL, NULL, V850E_IMMEDIATE32, BFD_RELOC_32 }, |
1226 | | |
1227 | | #define D32_31 (IMM32 + 1) |
1228 | | { 32, 32, NULL, NULL, V850E_IMMEDIATE32 | V850_OPERAND_SIGNED | V850_OPERAND_DISP, BFD_RELOC_V850_32_ABS }, |
1229 | | |
1230 | | #define D32_31_PCREL (D32_31 + 1) |
1231 | | { 32, 32, NULL, NULL, V850E_IMMEDIATE32 | V850_OPERAND_SIGNED | V850_OPERAND_DISP | V850_PCREL, BFD_RELOC_V850_32_PCREL }, |
1232 | | |
1233 | | #define POS_U (D32_31_PCREL + 1) |
1234 | | { 0, 0, insert_POS, extract_POS_U, 0, BFD_RELOC_NONE }, |
1235 | | |
1236 | | #define POS_M (POS_U + 1) |
1237 | | { 0, 0, insert_POS, extract_POS_L, 0, BFD_RELOC_NONE }, |
1238 | | |
1239 | | #define POS_L (POS_M + 1) |
1240 | | { 0, 0, insert_POS, extract_POS_L, 0, BFD_RELOC_NONE }, |
1241 | | |
1242 | | #define WIDTH_U (POS_L + 1) |
1243 | | { 0, 0, insert_WIDTH, extract_WIDTH_U, 0, BFD_RELOC_NONE }, |
1244 | | |
1245 | | #define WIDTH_M (WIDTH_U + 1) |
1246 | | { 0, 0, insert_WIDTH, extract_WIDTH_M, 0, BFD_RELOC_NONE }, |
1247 | | |
1248 | | #define WIDTH_L (WIDTH_M + 1) |
1249 | | { 0, 0, insert_WIDTH, extract_WIDTH_L, 0, BFD_RELOC_NONE }, |
1250 | | |
1251 | | #define SELID (WIDTH_L + 1) |
1252 | | { 5, 27, insert_SELID, extract_SELID, 0, BFD_RELOC_NONE }, |
1253 | | |
1254 | | #define RIE_IMM5 (SELID + 1) |
1255 | | { 5, 11, NULL, NULL, 0, BFD_RELOC_NONE }, |
1256 | | |
1257 | | #define RIE_IMM4 (RIE_IMM5 + 1) |
1258 | | { 4, 0, NULL, NULL, 0, BFD_RELOC_NONE }, |
1259 | | |
1260 | | #define VECTOR8 (RIE_IMM4 + 1) |
1261 | | { 0, 0, insert_VECTOR8, extract_VECTOR8, 0, BFD_RELOC_NONE }, |
1262 | | |
1263 | | #define VECTOR5 (VECTOR8 + 1) |
1264 | | { 0, 0, insert_VECTOR5, extract_VECTOR5, 0, BFD_RELOC_NONE }, |
1265 | | |
1266 | | #define VR1 (VECTOR5 + 1) |
1267 | | { 5, 0, NULL, NULL, V850_OPERAND_VREG, BFD_RELOC_NONE }, |
1268 | | |
1269 | | #define VR2 (VR1 + 1) |
1270 | | { 5, 11, NULL, NULL, V850_OPERAND_VREG, BFD_RELOC_NONE }, |
1271 | | |
1272 | | #define CACHEOP (VR2 + 1) |
1273 | | { 0, 0, insert_CACHEOP, extract_CACHEOP, V850_OPERAND_CACHEOP, BFD_RELOC_NONE }, |
1274 | | |
1275 | | #define PREFOP (CACHEOP + 1) |
1276 | | { 0, 0, insert_PREFOP, extract_PREFOP, V850_OPERAND_PREFOP, BFD_RELOC_NONE }, |
1277 | | |
1278 | | #define IMM10U (PREFOP + 1) |
1279 | | { 0, 0, insert_IMM10U, extract_IMM10U, 0, BFD_RELOC_NONE }, |
1280 | | }; |
1281 | | |
1282 | | |
1283 | | /* Reg - Reg instruction format (Format I). */ |
1284 | | #define IF1 {R1, R2} |
1285 | | |
1286 | | /* Imm - Reg instruction format (Format II). */ |
1287 | | #define IF2 {I5, R2} |
1288 | | |
1289 | | /* Conditional branch instruction format (Format III). */ |
1290 | | #define IF3 {D9_RELAX} |
1291 | | |
1292 | | /* 3 operand instruction (Format VI). */ |
1293 | | #define IF6 {I16, R1, R2} |
1294 | | |
1295 | | /* 3 operand instruction (Format VI). */ |
1296 | | #define IF6U {I16U, R1, R2} |
1297 | | |
1298 | | /* Conditional branch instruction format (Format VII). */ |
1299 | | #define IF7 {D17_16} |
1300 | | |
1301 | | |
1302 | | /* The opcode table. |
1303 | | |
1304 | | The format of the opcode table is: |
1305 | | |
1306 | | NAME OPCODE MASK { OPERANDS } MEMOP PROCESSOR |
1307 | | |
1308 | | NAME is the name of the instruction. |
1309 | | OPCODE is the instruction opcode. |
1310 | | MASK is the opcode mask; this is used to tell the disassembler |
1311 | | which bits in the actual opcode must match OPCODE. |
1312 | | OPERANDS is the list of operands. |
1313 | | MEMOP specifies which operand (if any) is a memory operand. |
1314 | | PROCESSORS specifies which CPU(s) support the opcode. |
1315 | | |
1316 | | The disassembler reads the table in order and prints the first |
1317 | | instruction which matches, so this table is sorted to put more |
1318 | | specific instructions before more general instructions. It is also |
1319 | | sorted by major opcode. |
1320 | | |
1321 | | The table is also sorted by name. This is used by the assembler. |
1322 | | When parsing an instruction the assembler finds the first occurance |
1323 | | of the name of the instruciton in this table and then attempts to |
1324 | | match the instruction's arguments with description of the operands |
1325 | | associated with the entry it has just found in this table. If the |
1326 | | match fails the assembler looks at the next entry in this table. |
1327 | | If that entry has the same name as the previous entry, then it |
1328 | | tries to match the instruction against that entry and so on. This |
1329 | | is how the assembler copes with multiple, different formats of the |
1330 | | same instruction. */ |
1331 | | |
1332 | | const struct v850_opcode v850_opcodes[] = |
1333 | | { |
1334 | | /* Standard instructions. */ |
1335 | | { "add", OP (0x0e), OP_MASK, IF1, 0, PROCESSOR_ALL }, |
1336 | | { "add", OP (0x12), OP_MASK, IF2, 0, PROCESSOR_ALL }, |
1337 | | |
1338 | | { "addi", OP (0x30), OP_MASK, IF6, 0, PROCESSOR_ALL }, |
1339 | | |
1340 | | { "adf", two (0x07e0, 0x03a0), two (0x07e0, 0x07e1), {CCCC_NOTSA, R1, R2, R3}, 0, PROCESSOR_V850E2_UP }, |
1341 | | |
1342 | | { "and", OP (0x0a), OP_MASK, IF1, 0, PROCESSOR_ALL }, |
1343 | | |
1344 | | { "andi", OP (0x36), OP_MASK, IF6U, 0, PROCESSOR_ALL }, |
1345 | | |
1346 | | /* Signed integer. */ |
1347 | | { "bge", BOP (0xe), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
1348 | | { "bgt", BOP (0xf), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
1349 | | { "ble", BOP (0x7), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
1350 | | { "blt", BOP (0x6), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
1351 | | /* Unsigned integer. */ |
1352 | | { "bh", BOP (0xb), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
1353 | | { "bl", BOP (0x1), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
1354 | | { "bnh", BOP (0x3), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
1355 | | { "bnl", BOP (0x9), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
1356 | | /* Common. */ |
1357 | | { "be", BOP (0x2), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
1358 | | { "bne", BOP (0xa), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
1359 | | /* Others. */ |
1360 | | { "bc", BOP (0x1), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
1361 | | { "bf", BOP (0xa), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
1362 | | { "bn", BOP (0x4), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
1363 | | { "bnc", BOP (0x9), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
1364 | | { "bnv", BOP (0x8), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
1365 | | { "bnz", BOP (0xa), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
1366 | | { "bp", BOP (0xc), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
1367 | | { "br", BOP (0x5), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
1368 | | { "bsa", BOP (0xd), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
1369 | | { "bt", BOP (0x2), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
1370 | | { "bv", BOP (0x0), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
1371 | | { "bz", BOP (0x2), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
1372 | | |
1373 | | /* Signed integer. */ |
1374 | | { "bge", two (0x07ee, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP }, |
1375 | | { "bgt", two (0x07ef, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP }, |
1376 | | { "ble", two (0x07e7, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP }, |
1377 | | { "blt", two (0x07e6, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP }, |
1378 | | /* Unsigned integer. */ |
1379 | | { "bh", two (0x07eb, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP }, |
1380 | | { "bl", two (0x07e1, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP }, |
1381 | | { "bnh", two (0x07e3, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP }, |
1382 | | { "bnl", two (0x07e9, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP }, |
1383 | | /* Common. */ |
1384 | | { "be", two (0x07e2, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP }, |
1385 | | { "bne", two (0x07ea, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP }, |
1386 | | /* Others. */ |
1387 | | { "bc", two (0x07e1, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP }, |
1388 | | { "bf", two (0x07ea, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP }, |
1389 | | { "bn", two (0x07e4, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP }, |
1390 | | { "bnc", two (0x07e9, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP }, |
1391 | | { "bnv", two (0x07e8, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP }, |
1392 | | { "bnz", two (0x07ea, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP }, |
1393 | | { "bp", two (0x07ec, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP }, |
1394 | | { "br", two (0x07e5, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP }, |
1395 | | { "bsa", two (0x07ed, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP }, |
1396 | | { "bt", two (0x07e2, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP }, |
1397 | | { "bv", two (0x07e0, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP }, |
1398 | | { "bz", two (0x07e2, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP }, |
1399 | | /* Bcond disp17 Gas local alias(not defined in spec). */ |
1400 | | |
1401 | | /* Signed integer. */ |
1402 | | { "bge17", two (0x07ee, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS }, |
1403 | | { "bgt17", two (0x07ef, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS }, |
1404 | | { "ble17", two (0x07e7, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS }, |
1405 | | { "blt17", two (0x07e6, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS }, |
1406 | | /* Unsigned integer. */ |
1407 | | { "bh17", two (0x07eb, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS }, |
1408 | | { "bl17", two (0x07e1, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS }, |
1409 | | { "bnh17", two (0x07e3, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS }, |
1410 | | { "bnl17", two (0x07e9, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS }, |
1411 | | /* Common. */ |
1412 | | { "be17", two (0x07e2, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS }, |
1413 | | { "bne17", two (0x07ea, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS }, |
1414 | | /* Others. */ |
1415 | | { "bc17", two (0x07e1, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS }, |
1416 | | { "bf17", two (0x07ea, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS }, |
1417 | | { "bn17", two (0x07e4, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS }, |
1418 | | { "bnc17", two (0x07e9, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS }, |
1419 | | { "bnv17", two (0x07e8, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS }, |
1420 | | { "bnz17", two (0x07ea, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS }, |
1421 | | { "bp17", two (0x07ec, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS }, |
1422 | | { "br17", two (0x07e5, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS }, |
1423 | | { "bsa17", two (0x07ed, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS }, |
1424 | | { "bt17", two (0x07e2, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS }, |
1425 | | { "bv17", two (0x07e0, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS }, |
1426 | | { "bz17", two (0x07e2, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS }, |
1427 | | |
1428 | | { "bsh", two (0x07e0, 0x0342), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_NOT_V850 }, |
1429 | | |
1430 | | { "bsw", two (0x07e0, 0x0340), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_NOT_V850 }, |
1431 | | |
1432 | | /* v850e3v5 bitfield instructions. */ |
1433 | | { "bins", two (0x07e0, 0x0090), two (0x07e0, 0x07f1), {R1, POS_U, WIDTH_U, R2}, 0, PROCESSOR_V850E3V5_UP }, |
1434 | | { "bins", two (0x07e0, 0x00b0), two (0x07e0, 0x07f1), {R1, POS_M, WIDTH_M, R2}, 0, PROCESSOR_V850E3V5_UP }, |
1435 | | { "bins", two (0x07e0, 0x00d0), two (0x07e0, 0x07f1), {R1, POS_L, WIDTH_L, R2}, 0, PROCESSOR_V850E3V5_UP }, |
1436 | | /* Gas local alias(not defined in spec). */ |
1437 | | { "binsu",two (0x07e0, 0x0090), two (0x07e0, 0x07f1), {R1, POS_U, WIDTH_U, R2}, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS }, |
1438 | | { "binsm",two (0x07e0, 0x00b0), two (0x07e0, 0x07f1), {R1, POS_M, WIDTH_M, R2}, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS }, |
1439 | | { "binsl",two (0x07e0, 0x00d0), two (0x07e0, 0x07f1), {R1, POS_L, WIDTH_L, R2}, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS }, |
1440 | | |
1441 | | { "cache", two (0xe7e0, 0x0160), two (0xe7e0, 0x07ff), {CACHEOP, R1}, 2, PROCESSOR_V850E3V5_UP }, |
1442 | | |
1443 | | { "callt", one (0x0200), one (0xffc0), {IMM6}, 0, PROCESSOR_NOT_V850 }, |
1444 | | |
1445 | | { "caxi", two (0x07e0, 0x00ee), two (0x07e0, 0x07ff), {R1, R2, R3}, 1, PROCESSOR_V850E2_UP }, |
1446 | | |
1447 | | { "clr1", two (0x87c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 3, PROCESSOR_ALL }, |
1448 | | { "clr1", two (0x07e0, 0x00e4), two (0x07e0, 0xffff), {R2, R1}, 3, PROCESSOR_NOT_V850 }, |
1449 | | |
1450 | | { "cmov", two (0x07e0, 0x0320), two (0x07e0, 0x07e1), {MOVCC, R1, R2, R3}, 0, PROCESSOR_NOT_V850 }, |
1451 | | { "cmov", two (0x07e0, 0x0300), two (0x07e0, 0x07e1), {MOVCC, I5, R2, R3}, 0, PROCESSOR_NOT_V850 }, |
1452 | | |
1453 | | { "cmp", OP (0x0f), OP_MASK, IF1, 0, PROCESSOR_ALL }, |
1454 | | { "cmp", OP (0x13), OP_MASK, IF2, 0, PROCESSOR_ALL }, |
1455 | | |
1456 | | { "ctret", two (0x07e0, 0x0144), two (0xffff, 0xffff), {0}, 0, PROCESSOR_NOT_V850 }, |
1457 | | |
1458 | | { "dbcp", one (0xe840), one (0xffff), {0}, 0, PROCESSOR_V850E3V5_UP }, |
1459 | | |
1460 | | { "dbhvtrap", one (0xe040), one (0xffff), {0}, 0, PROCESSOR_V850E3V5_UP }, |
1461 | | |
1462 | | { "dbpush", two (0x5fe0, 0x0160), two (0xffe0, 0x07ff), {R1, R3}, 0, PROCESSOR_V850E3V5_UP }, |
1463 | | |
1464 | | { "dbret", two (0x07e0, 0x0146), two (0xffff, 0xffff), {0}, 0, PROCESSOR_NOT_V850 }, |
1465 | | |
1466 | | { "dbtag", two (0xcfe0, 0x0160), two (0xffe0, 0x07ff), {IMM10U}, 0, PROCESSOR_V850E3V5_UP }, |
1467 | | |
1468 | | { "dbtrap", one (0xf840), one (0xffff), {0}, 0, PROCESSOR_NOT_V850 }, |
1469 | | |
1470 | | { "di", two (0x07e0, 0x0160), two (0xffff, 0xffff), {0}, 0, PROCESSOR_ALL }, |
1471 | | |
1472 | | { "dispose", two (0x0640, 0x0000), two (0xffc0, 0x0000), {IMM5, LIST12, R2_DISPOSE},3, PROCESSOR_NOT_V850 }, |
1473 | | { "dispose", two (0x0640, 0x0000), two (0xffc0, 0x001f), {IMM5, LIST12}, 0, PROCESSOR_NOT_V850 }, |
1474 | | |
1475 | | { "div", two (0x07e0, 0x02c0), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 }, |
1476 | | |
1477 | | { "divh", two (0x07e0, 0x0280), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 }, |
1478 | | { "divh", OP (0x02), OP_MASK, {R1_NOTR0, R2_NOTR0}, 0, PROCESSOR_ALL }, |
1479 | | |
1480 | | { "divhn", two (0x07e0, 0x0280), two (0x07e0, 0x07c3), {I5DIV1, R1, R2, R3}, 0, PROCESSOR_NOT_V850 | PROCESSOR_OPTION_EXTENSION }, |
1481 | | |
1482 | | { "divhu", two (0x07e0, 0x0282), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 }, |
1483 | | |
1484 | | { "divhun", two (0x07e0, 0x0282), two (0x07e0, 0x07c3), {I5DIV1, R1, R2, R3}, 0, PROCESSOR_NOT_V850 | PROCESSOR_OPTION_EXTENSION }, |
1485 | | { "divn", two (0x07e0, 0x02c0), two (0x07e0, 0x07c3), {I5DIV2, R1, R2, R3}, 0, PROCESSOR_NOT_V850 | PROCESSOR_OPTION_EXTENSION }, |
1486 | | |
1487 | | { "divq", two (0x07e0, 0x02fc), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2_UP }, |
1488 | | |
1489 | | { "divqu", two (0x07e0, 0x02fe), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2_UP }, |
1490 | | |
1491 | | { "divu", two (0x07e0, 0x02c2), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 }, |
1492 | | |
1493 | | { "divun", two (0x07e0, 0x02c2), two (0x07e0, 0x07c3), {I5DIV2, R1, R2, R3}, 0, PROCESSOR_NOT_V850 | PROCESSOR_OPTION_EXTENSION }, |
1494 | | |
1495 | | { "dst", two (0x07e0, 0x0134), two (0xfffff, 0xffff), {0}, 0, PROCESSOR_V850E3V5_UP }, |
1496 | | |
1497 | | { "ei", two (0x87e0, 0x0160), two (0xffff, 0xffff), {0}, 0, PROCESSOR_ALL }, |
1498 | | |
1499 | | { "eiret", two (0x07e0, 0x0148), two (0xffff, 0xffff), {0}, 0, PROCESSOR_V850E2_UP }, |
1500 | | |
1501 | | { "est", two (0x07e0, 0x0132), two (0xfffff, 0xffff), {0}, 0, PROCESSOR_V850E3V5_UP }, |
1502 | | |
1503 | | { "feret", two (0x07e0, 0x014a), two (0xffff, 0xffff), {0}, 0, PROCESSOR_V850E2_UP }, |
1504 | | |
1505 | | { "fetrap", one (0x0040), one (0x87ff), {I4U_NOTIMM0}, 0, PROCESSOR_V850E2_UP }, |
1506 | | |
1507 | | { "halt", two (0x07e0, 0x0120), two (0xffff, 0xffff), {0}, 0, PROCESSOR_ALL }, |
1508 | | |
1509 | | { "hsh", two (0x07e0, 0x0346), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2_UP }, |
1510 | | |
1511 | | { "hsw", two (0x07e0, 0x0344), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_NOT_V850 }, |
1512 | | |
1513 | | { "hvcall", two (0xd7e0, 0x4160), two (0xffe0, 0x41ff), {VECTOR8}, 0, PROCESSOR_V850E3V5_UP }, |
1514 | | { "hvtrap", two (0x07e0, 0x0110), two (0xffe0, 0xffff), {VECTOR5}, 0, PROCESSOR_V850E3V5_UP }, |
1515 | | |
1516 | | { "jarl", two (0xc7e0, 0x0160), two (0xffe0, 0x07ff), {R1, R3_NOTR0}, 1, PROCESSOR_V850E3V5_UP}, |
1517 | | { "jarl", two (0x0780, 0x0000), two (0x07c0, 0x0001), {D22, R2_NOTR0}, 0, PROCESSOR_ALL}, |
1518 | | { "jarl", one (0x02e0), one (0xffe0), {D32_31_PCREL, R1_NOTR0}, 0, PROCESSOR_V850E2_UP }, |
1519 | | /* Gas local alias (not defined in spec). */ |
1520 | | { "jarlr", two (0xc7e0, 0x0160), two (0xffe0, 0x07ff), {R1, R3_NOTR0}, 1, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS}, |
1521 | | /* Gas local alias of jarl imm22 (not defined in spec). */ |
1522 | | { "jarl22", two (0x0780, 0x0000), two (0x07c0, 0x0001), {D22, R2_NOTR0}, 0, PROCESSOR_ALL | PROCESSOR_OPTION_ALIAS}, |
1523 | | /* Gas local alias of jarl imm32 (not defined in spec). */ |
1524 | | { "jarl32", one (0x02e0), one (0xffe0), {D32_31_PCREL, R1_NOTR0}, 0, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_ALIAS }, |
1525 | | { "jarlw", one (0x02e0), one (0xffe0), {D32_31_PCREL, R1_NOTR0}, 0, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_ALIAS }, |
1526 | | |
1527 | | { "jmp", two (0x06e0, 0x0000), two (0xffe0, 0x0001), {D32_31, R1}, 2, PROCESSOR_V850E3V5_UP }, |
1528 | | { "jmp", one (0x06e0), one (0xffe0), {D32_31, R1}, 2, PROCESSOR_V850E2 | PROCESSOR_V850E2V3 }, |
1529 | | { "jmp", one (0x0060), one (0xffe0), {R1}, 1, PROCESSOR_ALL }, |
1530 | | /* Gas local alias of jmp disp22(not defined in spec). */ |
1531 | | { "jmp22", one (0x0060), one (0xffe0), {R1}, 1, PROCESSOR_ALL | PROCESSOR_OPTION_ALIAS }, |
1532 | | /* Gas local alias of jmp disp32(not defined in spec). */ |
1533 | | { "jmp32", one (0x06e0), one (0xffe0), {D32_31, R1}, 2, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_ALIAS }, |
1534 | | { "jmpw", one (0x06e0), one (0xffe0), {D32_31, R1}, 2, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_ALIAS }, |
1535 | | |
1536 | | { "jr", two (0x0780, 0x0000), two (0xffc0, 0x0001), {D22}, 0, PROCESSOR_ALL }, |
1537 | | { "jr", one (0x02e0), one (0xffff), {D32_31_PCREL}, 0, PROCESSOR_V850E2_UP }, |
1538 | | /* Gas local alias of mov imm22(not defined in spec). */ |
1539 | | { "jr22", two (0x0780, 0x0000), two (0xffc0, 0x0001), {D22}, 0, PROCESSOR_ALL | PROCESSOR_OPTION_ALIAS }, |
1540 | | /* Gas local alias of mov imm32(not defined in spec). */ |
1541 | | { "jr32", one (0x02e0), one (0xffff), {D32_31_PCREL}, 0, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_ALIAS }, |
1542 | | |
1543 | | /* Alias of bcond (same as CA850). */ |
1544 | | { "jgt", BOP (0xf), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
1545 | | { "jge", BOP (0xe), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
1546 | | { "jlt", BOP (0x6), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
1547 | | { "jle", BOP (0x7), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
1548 | | /* Unsigned integer. */ |
1549 | | { "jh", BOP (0xb), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
1550 | | { "jnh", BOP (0x3), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
1551 | | { "jl", BOP (0x1), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
1552 | | { "jnl", BOP (0x9), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
1553 | | /* Common. */ |
1554 | | { "je", BOP (0x2), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
1555 | | { "jne", BOP (0xa), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
1556 | | /* Others. */ |
1557 | | { "jv", BOP (0x0), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
1558 | | { "jnv", BOP (0x8), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
1559 | | { "jn", BOP (0x4), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
1560 | | { "jp", BOP (0xc), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
1561 | | { "jc", BOP (0x1), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
1562 | | { "jnc", BOP (0x9), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
1563 | | { "jz", BOP (0x2), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
1564 | | { "jnz", BOP (0xa), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
1565 | | { "jbr", BOP (0x5), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
1566 | | |
1567 | | |
1568 | | { "ldacc", two (0x07e0, 0x0bc4), two (0x07e0, 0xffff), {R1, R2}, 0, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_EXTENSION }, |
1569 | | |
1570 | | { "ld.b", two (0x0700, 0x0000), two (0x07e0, 0x0000), {D16, R1, R2}, 2, PROCESSOR_ALL }, |
1571 | | { "ld.b", two (0x0780, 0x0005), two (0xffe0, 0x000f), {D23, R1, R3}, 2, PROCESSOR_V850E2_UP }, |
1572 | | { "ld.b23", two (0x0780, 0x0005), two (0x07e0, 0x000f), {D23, R1, R3}, 2, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_ALIAS }, |
1573 | | |
1574 | | { "ld.bu", two (0x0780, 0x0001), two (0x07c0, 0x0001), {D16_16, R1, R2_NOTR0}, 2, PROCESSOR_NOT_V850 }, |
1575 | | { "ld.bu", two (0x07a0, 0x0005), two (0xffe0, 0x000f), {D23, R1, R3}, 2, PROCESSOR_V850E2_UP }, |
1576 | | { "ld.bu23", two (0x07a0, 0x0005), two (0x07e0, 0x000f), {D23, R1, R3}, 2, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_ALIAS }, |
1577 | | |
1578 | | { "ld.dw", two (0x07a0, 0x0009), two (0xffe0, 0x001f), {D23_ALIGN1, R1, R3_EVEN}, 2, PROCESSOR_V850E3V5_UP }, |
1579 | | { "ld.dw23", two (0x07a0, 0x0009), two (0xffe0, 0x001f), {D23_ALIGN1, R1, R3_EVEN}, 2, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS }, |
1580 | | |
1581 | | { "ld.h", two (0x0720, 0x0000), two (0x07e0, 0x0001), {D16_15, R1, R2}, 2, PROCESSOR_ALL }, |
1582 | | { "ld.h", two (0x0780, 0x0007), two (0x07e0, 0x000f), {D23_ALIGN1, R1, R3}, 2, PROCESSOR_V850E2_UP }, |
1583 | | { "ld.h23", two (0x0780, 0x0007), two (0x07e0, 0x000f), {D23_ALIGN1, R1, R3}, 2, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_ALIAS }, |
1584 | | |
1585 | | { "ld.hu", two (0x07e0, 0x0001), two (0x07e0, 0x0001), {D16_15, R1, R2_NOTR0}, 2, PROCESSOR_NOT_V850 }, |
1586 | | { "ld.hu", two (0x07a0, 0x0007), two (0x07e0, 0x000f), {D23_ALIGN1, R1, R3}, 2, PROCESSOR_V850E2_UP }, |
1587 | | { "ld.hu23", two (0x07a0, 0x0007), two (0x07e0, 0x000f), {D23_ALIGN1, R1, R3}, 2, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_ALIAS }, |
1588 | | |
1589 | | { "ld.w", two (0x0720, 0x0001), two (0x07e0, 0x0001), {D16_15, R1, R2}, 2, PROCESSOR_ALL }, |
1590 | | { "ld.w", two (0x0780, 0x0009), two (0xffe0, 0x001f), {D23_ALIGN1, R1, R3}, 2, PROCESSOR_V850E2_UP }, |
1591 | | { "ld.w23", two (0x0780, 0x0009), two (0x07e0, 0x001f), {D23_ALIGN1, R1, R3}, 2, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_ALIAS }, |
1592 | | |
1593 | | { "ldl.w", two (0x07e0, 0x0378), two (0xffe0, 0x07ff), {R1, R3}, 1, PROCESSOR_V850E3V5_UP }, |
1594 | | |
1595 | | { "ldsr", two (0x07e0, 0x0020), two (0x07e0, 0x07ff), {R1, SR2, SELID}, 0, PROCESSOR_V850E3V5_UP }, |
1596 | | { "ldsr", two (0x07e0, 0x0020), two (0x07e0, 0x07ff), {R1, SR2}, 0, PROCESSOR_V850E3V5_UP }, |
1597 | | { "ldsr", two (0x07e0, 0x0020), two (0x07e0, 0x07ff), {R1, OLDSR2}, 0, (PROCESSOR_ALL & (~ PROCESSOR_V850E3V5_UP)) }, |
1598 | | |
1599 | | { "ldtc.gr", two (0x07e0, 0x0032), two (0x07e0, 0xffff), {R1, R2}, 0, PROCESSOR_V850E3V5_UP }, |
1600 | | { "ldtc.sr", two (0x07e0, 0x0030), two (0x07e0, 0x07ff), {R1, SR2, SELID}, 0, PROCESSOR_V850E3V5_UP }, |
1601 | | { "ldtc.sr", two (0x07e0, 0x0030), two (0x07e0, 0x07ff), {R1, SR2}, 0, PROCESSOR_V850E3V5_UP }, |
1602 | | |
1603 | | { "ldtc.vr", two (0x07e0, 0x0832), two (0x07e0, 0xffff), {R1, VR2}, 0, PROCESSOR_V850E3V5_UP }, |
1604 | | { "ldtc.pc", two (0x07e0, 0xf832), two (0x07e0, 0xffff), {R1}, 0, PROCESSOR_V850E3V5_UP }, |
1605 | | |
1606 | | { "ldvc.sr", two (0x07e0, 0x0034), two (0x07e0, 0x07ff), {R1, SR2, SELID}, 0, PROCESSOR_V850E3V5_UP }, |
1607 | | { "ldvc.sr", two (0x07e0, 0x0034), two (0x07e0, 0x07ff), {R1, SR2}, 0, PROCESSOR_V850E3V5_UP }, |
1608 | | |
1609 | | { "loop", two (0x06e0, 0x0001), two (0xffe0, 0x0001), {R1, D16_LOOP}, 0, PROCESSOR_V850E3V5_UP }, |
1610 | | |
1611 | | { "macacc", two (0x07e0, 0x0bc0), two (0x07e0, 0xffff), {R1, R2}, 0, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_EXTENSION }, |
1612 | | |
1613 | | { "mac", two (0x07e0, 0x03c0), two (0x07e0, 0x0fe1), {R1, R2, R3_EVEN, R4_EVEN}, 0, PROCESSOR_V850E2_UP }, |
1614 | | |
1615 | | { "macu", two (0x07e0, 0x03e0), two (0x07e0, 0x0fe1), {R1, R2, R3_EVEN, R4_EVEN}, 0, PROCESSOR_V850E2_UP }, |
1616 | | |
1617 | | { "macuacc", two (0x07e0, 0x0bc2), two (0x07e0, 0xffff), {R1, R2}, 0, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_EXTENSION }, |
1618 | | |
1619 | | { "mov", OP (0x00), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL }, |
1620 | | { "mov", OP (0x10), OP_MASK, {I5, R2_NOTR0}, 0, PROCESSOR_ALL }, |
1621 | | { "mov", one (0x0620), one (0xffe0), {IMM32, R1}, 0, PROCESSOR_NOT_V850 }, |
1622 | | /* Gas local alias of mov imm32(not defined in spec). */ |
1623 | | { "movl", one (0x0620), one (0xffe0), {IMM32, R1}, 0, PROCESSOR_NOT_V850 | PROCESSOR_OPTION_ALIAS }, |
1624 | | |
1625 | | { "movea", OP (0x31), OP_MASK, {I16, R1, R2_NOTR0}, 0, PROCESSOR_ALL }, |
1626 | | |
1627 | | { "movhi", OP (0x32), OP_MASK, {I16, R1, R2_NOTR0}, 0, PROCESSOR_ALL }, |
1628 | | |
1629 | | { "mul", two (0x07e0, 0x0220), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 }, |
1630 | | { "mul", two (0x07e0, 0x0240), two (0x07e0, 0x07c3), {I9, R2, R3}, 0, PROCESSOR_NOT_V850 }, |
1631 | | |
1632 | | { "mulh", OP (0x17), OP_MASK, {I5, R2_NOTR0}, 0, PROCESSOR_ALL }, |
1633 | | { "mulh", OP (0x07), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL }, |
1634 | | |
1635 | | { "mulhi", OP (0x37), OP_MASK, {I16, R1, R2_NOTR0}, 0, PROCESSOR_ALL }, |
1636 | | |
1637 | | { "mulu", two (0x07e0, 0x0222), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 }, |
1638 | | { "mulu", two (0x07e0, 0x0242), two (0x07e0, 0x07c3), {U9, R2, R3}, 0, PROCESSOR_NOT_V850 }, |
1639 | | |
1640 | | { "nop", one (0x00), one (0xffff), {0}, 0, PROCESSOR_ALL }, |
1641 | | |
1642 | | { "not", OP (0x01), OP_MASK, IF1, 0, PROCESSOR_ALL }, |
1643 | | |
1644 | | { "not1", two (0x47c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 3, PROCESSOR_ALL }, |
1645 | | { "not1", two (0x07e0, 0x00e2), two (0x07e0, 0xffff), {R2, R1}, 3, PROCESSOR_NOT_V850 }, |
1646 | | |
1647 | | { "or", OP (0x08), OP_MASK, IF1, 0, PROCESSOR_ALL }, |
1648 | | |
1649 | | { "ori", OP (0x34), OP_MASK, IF6U, 0, PROCESSOR_ALL }, |
1650 | | |
1651 | | { "popsp", two (0x67e0, 0x0160), two (0xffe0, 0x07ff), {R1, R3}, 0, PROCESSOR_V850E3V5_UP }, |
1652 | | |
1653 | | { "pref", two (0xdfe0, 0x0160), two (0xffe0, 0x07ff), {PREFOP, R1}, 2, PROCESSOR_V850E3V5_UP }, |
1654 | | |
1655 | | { "prepare", two (0x0780, 0x0003), two (0xffc0, 0x001f), {LIST12, IMM5, SP}, 0, PROCESSOR_NOT_V850 }, |
1656 | | { "prepare", two (0x0780, 0x000b), two (0xffc0, 0x001f), {LIST12, IMM5, IMM16LO},0, PROCESSOR_NOT_V850 }, |
1657 | | { "prepare", two (0x0780, 0x0013), two (0xffc0, 0x001f), {LIST12, IMM5, IMM16HI},0, PROCESSOR_NOT_V850 }, |
1658 | | { "prepare", two (0x0780, 0x001b), two (0xffc0, 0x001f), {LIST12, IMM5, IMM32}, 0, PROCESSOR_NOT_V850 }, |
1659 | | { "prepare", two (0x0780, 0x0001), two (0xffc0, 0x001f), {LIST12, IMM5}, 0, PROCESSOR_NOT_V850 }, |
1660 | | |
1661 | | { "pushsp", two (0x47e0, 0x0160), two (0xffe0, 0x07ff), {R1, R3}, 0, PROCESSOR_V850E3V5_UP }, |
1662 | | |
1663 | | { "rotl", two (0x07e0, 0x00c6), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E3V5_UP }, |
1664 | | { "rotl", two (0x07e0, 0x00c4), two (0x07e0, 0x07ff), {I5U, R2, R3}, 0, PROCESSOR_V850E3V5_UP }, |
1665 | | |
1666 | | { "reti", two (0x07e0, 0x0140), two (0xffff, 0xffff), {0}, 0, PROCESSOR_ALL }, |
1667 | | |
1668 | | { "sar", two (0x07e0, 0x00a2), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2_UP }, |
1669 | | { "sar", OP (0x15), OP_MASK, {I5U, R2}, 0, PROCESSOR_ALL }, |
1670 | | { "sar", two (0x07e0, 0x00a0), two (0x07e0, 0xffff), {R1, R2}, 0, PROCESSOR_ALL }, |
1671 | | |
1672 | | { "sasf", two (0x07e0, 0x0200), two (0x07f0, 0xffff), {CCCC, R2}, 0, PROCESSOR_NOT_V850 }, |
1673 | | |
1674 | | { "satadd", two (0x07e0, 0x03ba), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2_UP }, |
1675 | | { "satadd", OP (0x11), OP_MASK, {I5, R2_NOTR0}, 0, PROCESSOR_ALL }, |
1676 | | { "satadd", OP (0x06), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL }, |
1677 | | |
1678 | | { "satsub", two (0x07e0, 0x039a), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2_UP }, |
1679 | | { "satsub", OP (0x05), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL }, |
1680 | | |
1681 | | { "satsubi", OP (0x33), OP_MASK, {I16, R1, R2_NOTR0}, 0, PROCESSOR_ALL }, |
1682 | | |
1683 | | { "satsubr", OP (0x04), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL }, |
1684 | | |
1685 | | { "sbf", two (0x07e0, 0x0380), two (0x07e0, 0x07e1), {CCCC_NOTSA, R1, R2, R3}, 0, PROCESSOR_V850E2_UP }, |
1686 | | |
1687 | | { "sch0l", two (0x07e0, 0x0364), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2_UP }, |
1688 | | |
1689 | | { "sch0r", two (0x07e0, 0x0360), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2_UP }, |
1690 | | |
1691 | | { "sch1l", two (0x07e0, 0x0366), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2_UP }, |
1692 | | |
1693 | | { "sch1r", two (0x07e0, 0x0362), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2_UP }, |
1694 | | |
1695 | | { "sdivhn", two (0x07e0, 0x0180), two (0x07e0, 0x07c3), {I5DIV3, R1, R2, R3}, 0, PROCESSOR_NOT_V850 | PROCESSOR_OPTION_EXTENSION }, |
1696 | | { "sdivhun", two (0x07e0, 0x0182), two (0x07e0, 0x07c3), {I5DIV3, R1, R2, R3}, 0, PROCESSOR_NOT_V850 | PROCESSOR_OPTION_EXTENSION }, |
1697 | | { "sdivn", two (0x07e0, 0x01c0), two (0x07e0, 0x07c3), {I5DIV3, R1, R2, R3}, 0, PROCESSOR_NOT_V850 | PROCESSOR_OPTION_EXTENSION }, |
1698 | | { "sdivun", two (0x07e0, 0x01c2), two (0x07e0, 0x07c3), {I5DIV3, R1, R2, R3}, 0, PROCESSOR_NOT_V850 | PROCESSOR_OPTION_EXTENSION }, |
1699 | | |
1700 | | { "set1", two (0x07c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 3, PROCESSOR_ALL }, |
1701 | | { "set1", two (0x07e0, 0x00e0), two (0x07e0, 0xffff), {R2, R1}, 3, PROCESSOR_NOT_V850 }, |
1702 | | |
1703 | | { "setf", two (0x07e0, 0x0000), two (0x07f0, 0xffff), {CCCC, R2}, 0, PROCESSOR_ALL }, |
1704 | | |
1705 | | { "shl", two (0x07e0, 0x00c2), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2_UP }, |
1706 | | { "shl", OP (0x16), OP_MASK, {I5U, R2}, 0, PROCESSOR_ALL }, |
1707 | | { "shl", two (0x07e0, 0x00c0), two (0x07e0, 0xffff), {R1, R2}, 0, PROCESSOR_ALL }, |
1708 | | |
1709 | | { "shr", two (0x07e0, 0x0082), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2_UP }, |
1710 | | { "shr", OP (0x14), OP_MASK, {I5U, R2}, 0, PROCESSOR_ALL }, |
1711 | | { "shr", two (0x07e0, 0x0080), two (0x07e0, 0xffff), {R1, R2}, 0, PROCESSOR_ALL }, |
1712 | | |
1713 | | { "sld.b", one (0x0300), one (0x0780), {D7U, EP, R2}, 2, PROCESSOR_ALL }, |
1714 | | |
1715 | | { "sld.bu", one (0x0060), one (0x07f0), {D4U, EP, R2_NOTR0}, 2, PROCESSOR_NOT_V850 }, |
1716 | | |
1717 | | { "sld.h", one (0x0400), one (0x0780), {D8_7U,EP, R2}, 2, PROCESSOR_ALL }, |
1718 | | |
1719 | | { "sld.hu", one (0x0070), one (0x07f0), {D5_4U,EP, R2_NOTR0}, 2, PROCESSOR_NOT_V850 }, |
1720 | | |
1721 | | { "sld.w", one (0x0500), one (0x0781), {D8_6U,EP, R2}, 2, PROCESSOR_ALL }, |
1722 | | |
1723 | | { "snooze", two (0x0fe0, 0x0120), two (0xffff, 0xffff), {0}, 0, PROCESSOR_V850E3V5_UP }, |
1724 | | |
1725 | | { "sst.b", one (0x0380), one (0x0780), {R2, D7U, EP}, 3, PROCESSOR_ALL }, |
1726 | | |
1727 | | { "sst.h", one (0x0480), one (0x0780), {R2, D8_7U,EP}, 3, PROCESSOR_ALL }, |
1728 | | |
1729 | | { "sst.w", one (0x0501), one (0x0781), {R2, D8_6U,EP}, 3, PROCESSOR_ALL }, |
1730 | | |
1731 | | { "stacch", two (0x07e0, 0x0bca), two (0x07ff, 0xffff), {R2}, 0, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_EXTENSION }, |
1732 | | { "staccl", two (0x07e0, 0x0bc8), two (0x07ff, 0xffff), {R2}, 0, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_EXTENSION }, |
1733 | | |
1734 | | { "st.b", two (0x0740, 0x0000), two (0x07e0, 0x0000), {R2, D16, R1}, 3, PROCESSOR_ALL }, |
1735 | | { "st.b", two (0x0780, 0x000d), two (0x07e0, 0x000f), {R3, D23, R1}, 3, PROCESSOR_V850E2_UP }, |
1736 | | { "st.b23", two (0x0780, 0x000d), two (0x07e0, 0x000f), {R3, D23, R1}, 3, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_ALIAS }, |
1737 | | |
1738 | | { "st.dw", two (0x07a0, 0x000f), two (0xffe0, 0x001f), {R3_EVEN, D23_ALIGN1, R1}, 3, PROCESSOR_V850E3V5_UP }, |
1739 | | { "st.dw23", two (0x07a0, 0x000f), two (0xffe0, 0x001f), {R3_EVEN, D23_ALIGN1, R1}, 3, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS }, |
1740 | | |
1741 | | { "st.h", two (0x0760, 0x0000), two (0x07e0, 0x0001), {R2, D16_15, R1}, 3, PROCESSOR_ALL }, |
1742 | | { "st.h", two (0x07a0, 0x000d), two (0x07e0, 0x000f), {R3, D23_ALIGN1, R1}, 3, PROCESSOR_V850E2_UP }, |
1743 | | { "st.h23", two (0x07a0, 0x000d), two (0x07e0, 0x000f), {R3, D23_ALIGN1, R1}, 3, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_ALIAS }, |
1744 | | |
1745 | | { "st.w", two (0x0760, 0x0001), two (0x07e0, 0x0001), {R2, D16_15, R1}, 3, PROCESSOR_ALL }, |
1746 | | { "st.w", two (0x0780, 0x000f), two (0x07e0, 0x000f), {R3, D23_ALIGN1, R1}, 3, PROCESSOR_V850E2_UP }, |
1747 | | { "st.w23", two (0x0780, 0x000f), two (0x07e0, 0x000f), {R3, D23_ALIGN1, R1}, 3, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_ALIAS }, |
1748 | | |
1749 | | { "stc.w", two (0x07e0, 0x037a), two (0xffe0, 0x07ff), {R3, R1}, 2, PROCESSOR_V850E3V5_UP }, |
1750 | | |
1751 | | { "stsr", two (0x07e0, 0x0040), two (0x07e0, 0x07ff), {SR1, R2, SELID}, 0, PROCESSOR_V850E3V5_UP }, |
1752 | | { "stsr", two (0x07e0, 0x0040), two (0x07e0, 0x07ff), {SR1, R2}, 0, PROCESSOR_V850E3V5_UP }, |
1753 | | { "stsr", two (0x07e0, 0x0040), two (0x07e0, 0x07ff), {OLDSR1, R2}, 0, (PROCESSOR_ALL & (~ PROCESSOR_V850E3V5_UP)) }, |
1754 | | |
1755 | | { "sttc.gr", two (0x07e0, 0x0052), two (0x07e0, 0xffff), {R1, R2}, 0, PROCESSOR_V850E3V5_UP }, |
1756 | | { "sttc.sr", two (0x07e0, 0x0050), two (0x07e0, 0x07ff), {SR1, R2, SELID}, 0, PROCESSOR_V850E3V5_UP }, |
1757 | | { "sttc.sr", two (0x07e0, 0x0050), two (0x07e0, 0x07ff), {SR1, R2}, 0, PROCESSOR_V850E3V5_UP }, |
1758 | | { "sttc.vr", two (0x07e0, 0x0852), two (0x07e0, 0xffff), {VR1, R2}, 0, PROCESSOR_V850E3V5_UP }, |
1759 | | { "sttc.pc", two (0x07e0, 0xf852), two (0x07e0, 0xffff), {R2}, 0, PROCESSOR_V850E3V5_UP }, |
1760 | | |
1761 | | { "stvc.sr", two (0x07e0, 0x0054), two (0x07e0, 0x07ff), {SR1, R2, SELID}, 0, PROCESSOR_V850E3V5_UP }, |
1762 | | { "stvc.sr", two (0x07e0, 0x0054), two (0x07e0, 0x07ff), {SR1, R2}, 0, PROCESSOR_V850E3V5_UP }, |
1763 | | |
1764 | | { "sub", OP (0x0d), OP_MASK, IF1, 0, PROCESSOR_ALL }, |
1765 | | |
1766 | | { "subr", OP (0x0c), OP_MASK, IF1, 0, PROCESSOR_ALL }, |
1767 | | |
1768 | | { "switch", one (0x0040), one (0xffe0), {R1_NOTR0}, 0, PROCESSOR_NOT_V850 }, |
1769 | | |
1770 | | { "sxb", one (0x00a0), one (0xffe0), {R1}, 0, PROCESSOR_NOT_V850 }, |
1771 | | |
1772 | | { "sxh", one (0x00e0), one (0xffe0), {R1}, 0, PROCESSOR_NOT_V850 }, |
1773 | | |
1774 | | { "tlbai", two (0x87e0, 0x8960), two (0xffff, 0xffff), {0}, 0, PROCESSOR_V850E3V5_UP }, |
1775 | | { "tlbr", two (0x87e0, 0xe960), two (0xffff, 0xffff), {0}, 0, PROCESSOR_V850E3V5_UP }, |
1776 | | { "tlbs", two (0x87e0, 0xc160), two (0xffff, 0xffff), {0}, 0, PROCESSOR_V850E3V5_UP }, |
1777 | | { "tlbvi", two (0x87e0, 0x8160), two (0xffff, 0xffff), {0}, 0, PROCESSOR_V850E3V5_UP }, |
1778 | | { "tlbw", two (0x87e0, 0xe160), two (0xffff, 0xffff), {0}, 0, PROCESSOR_V850E3V5_UP }, |
1779 | | |
1780 | | { "trap", two (0x07e0, 0x0100), two (0xffe0, 0xffff), {I5U}, 0, PROCESSOR_ALL }, |
1781 | | |
1782 | | { "tst", OP (0x0b), OP_MASK, IF1, 0, PROCESSOR_ALL }, |
1783 | | |
1784 | | { "tst1", two (0xc7c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 3, PROCESSOR_ALL }, |
1785 | | { "tst1", two (0x07e0, 0x00e6), two (0x07e0, 0xffff), {R2, R1}, 3, PROCESSOR_NOT_V850 }, |
1786 | | |
1787 | | { "xor", OP (0x09), OP_MASK, IF1, 0, PROCESSOR_ALL }, |
1788 | | |
1789 | | { "xori", OP (0x35), OP_MASK, IF6U, 0, PROCESSOR_ALL }, |
1790 | | |
1791 | | { "zxb", one (0x0080), one (0xffe0), {R1}, 0, PROCESSOR_NOT_V850 }, |
1792 | | |
1793 | | { "zxh", one (0x00c0), one (0xffe0), {R1}, 0, PROCESSOR_NOT_V850 }, |
1794 | | |
1795 | | /* Floating point operation. */ |
1796 | | { "absf.d", two (0x07e0, 0x0458), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, |
1797 | | { "absf.s", two (0x07e0, 0x0448), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP }, |
1798 | | { "addf.d", two (0x07e0, 0x0470), two (0x0fe1, 0x0fff), {R1_EVEN, R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, |
1799 | | { "addf.s", two (0x07e0, 0x0460), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2V3_UP }, |
1800 | | { "ceilf.dl", two (0x07e2, 0x0454), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, |
1801 | | { "ceilf.dul", two (0x07f2, 0x0454), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, |
1802 | | { "ceilf.duw", two (0x07f2, 0x0450), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3_UP }, |
1803 | | { "ceilf.dw", two (0x07e2, 0x0450), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3_UP }, |
1804 | | { "ceilf.sl", two (0x07e2, 0x0444), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, |
1805 | | { "ceilf.sul", two (0x07f2, 0x0444), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, |
1806 | | { "ceilf.suw", two (0x07f2, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP }, |
1807 | | { "ceilf.sw", two (0x07e2, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP }, |
1808 | | { "cmovf.d", two (0x07e0, 0x0410), two (0x0fe1, 0x0ff1), {FFF, R1_EVEN, R2_EVEN, R3_EVEN_NOTR0}, 0, PROCESSOR_V850E2V3_UP }, |
1809 | | /* Default value for FFF is 0(not defined in spec). */ |
1810 | | { "cmovf.d", two (0x07e0, 0x0410), two (0x0fe1, 0x0fff), {R1_EVEN, R2_EVEN, R3_EVEN_NOTR0}, 0, PROCESSOR_V850E2V3_UP }, |
1811 | | { "cmovf.s", two (0x07e0, 0x0400), two (0x07e0, 0x07f1), {FFF, R1, R2, R3_NOTR0}, 0, PROCESSOR_V850E2V3_UP }, |
1812 | | /* Default value for FFF is 0(not defined in spec). */ |
1813 | | { "cmovf.s", two (0x07e0, 0x0400), two (0x07e0, 0x07ff), {R1, R2, R3_NOTR0}, 0, PROCESSOR_V850E2V3_UP }, |
1814 | | { "cmpf.d", two (0x07e0, 0x0430), two (0x0fe1, 0x87f1), {FLOAT_CCCC, R2_EVEN, R1_EVEN, FFF}, 0, PROCESSOR_V850E2V3_UP }, |
1815 | | { "cmpf.d", two (0x07e0, 0x0430), two (0x0fe1, 0x87ff), {FLOAT_CCCC, R2_EVEN, R1_EVEN}, 0, PROCESSOR_V850E2V3_UP }, |
1816 | | { "cmpf.s", two (0x07e0, 0x0420), two (0x07e0, 0x87f1), {FLOAT_CCCC, R2, R1, FFF}, 0, PROCESSOR_V850E2V3_UP }, |
1817 | | { "cmpf.s", two (0x07e0, 0x0420), two (0x07e0, 0x87ff), {FLOAT_CCCC, R2, R1}, 0, PROCESSOR_V850E2V3_UP }, |
1818 | | { "cvtf.dl", two (0x07e4, 0x0454), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, |
1819 | | { "cvtf.ds", two (0x07e3, 0x0452), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3_UP }, |
1820 | | { "cvtf.dul", two (0x07f4, 0x0454), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, |
1821 | | { "cvtf.duw", two (0x07f4, 0x0450), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3_UP }, |
1822 | | { "cvtf.dw", two (0x07e4, 0x0450), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3_UP }, |
1823 | | { "cvtf.hs", two (0x07e2, 0x0442), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E3V5_UP }, |
1824 | | { "cvtf.ld", two (0x07e1, 0x0452), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, |
1825 | | { "cvtf.ls", two (0x07e1, 0x0442), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3_UP }, |
1826 | | { "cvtf.sd", two (0x07e2, 0x0452), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, |
1827 | | { "cvtf.sl", two (0x07e4, 0x0444), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, |
1828 | | { "cvtf.sh", two (0x07e3, 0x0442), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E3V5_UP }, |
1829 | | { "cvtf.sul", two (0x07f4, 0x0444), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, |
1830 | | { "cvtf.suw", two (0x07f4, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP }, |
1831 | | { "cvtf.sw", two (0x07e4, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP }, |
1832 | | { "cvtf.uld", two (0x07f1, 0x0452), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, |
1833 | | { "cvtf.uls", two (0x07f1, 0x0442), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3_UP }, |
1834 | | { "cvtf.uwd", two (0x07f0, 0x0452), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, |
1835 | | { "cvtf.uws", two (0x07f0, 0x0442), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP }, |
1836 | | { "cvtf.wd", two (0x07e0, 0x0452), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, |
1837 | | { "cvtf.ws", two (0x07e0, 0x0442), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP }, |
1838 | | { "divf.d", two (0x07e0, 0x047e), two (0x0fe1, 0x0fff), {R1_EVEN, R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, |
1839 | | { "divf.s", two (0x07e0, 0x046e), two (0x07e0, 0x07ff), {R1_NOTR0, R2, R3}, 0, PROCESSOR_V850E2V3_UP }, |
1840 | | { "floorf.dl", two (0x07e3, 0x0454), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, |
1841 | | { "floorf.dul", two (0x07f3, 0x0454), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, |
1842 | | { "floorf.duw", two (0x07f3, 0x0450), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3_UP }, |
1843 | | { "floorf.dw", two (0x07e3, 0x0450), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3_UP }, |
1844 | | { "floorf.sl", two (0x07e3, 0x0444), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, |
1845 | | { "floorf.sul", two (0x07f3, 0x0444), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, |
1846 | | { "floorf.suw", two (0x07f3, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP }, |
1847 | | { "floorf.sw", two (0x07e3, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP }, |
1848 | | { "maddf.s", two (0x07e0, 0x0500), two (0x07e0, 0x0761), {R1, R2, R3, R4}, 0, PROCESSOR_V850E2V3 }, |
1849 | | { "fmaf.s", two (0x07e0, 0x04e0), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E3V5_UP }, |
1850 | | { "maxf.d", two (0x07e0, 0x0478), two (0x0fe1, 0x0fff), {R1_EVEN, R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, |
1851 | | { "maxf.s", two (0x07e0, 0x0468), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2V3_UP }, |
1852 | | { "minf.d", two (0x07e0, 0x047a), two (0x0fe1, 0x0fff), {R1_EVEN, R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, |
1853 | | { "minf.s", two (0x07e0, 0x046a), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2V3_UP }, |
1854 | | { "msubf.s", two (0x07e0, 0x0520), two (0x07e0, 0x0761), {R1, R2, R3, R4}, 0, PROCESSOR_V850E2V3 }, |
1855 | | { "fmsf.s", two (0x07e0, 0x04e2), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E3V5_UP }, |
1856 | | { "mulf.d", two (0x07e0, 0x0474), two (0x0fe1, 0x0fff), {R1_EVEN, R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, |
1857 | | { "mulf.s", two (0x07e0, 0x0464), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2V3_UP }, |
1858 | | { "negf.d", two (0x07e1, 0x0458), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, |
1859 | | { "negf.s", two (0x07e1, 0x0448), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP }, |
1860 | | { "nmaddf.s", two (0x07e0, 0x0540), two (0x07e0, 0x0761), {R1, R2, R3, R4}, 0, PROCESSOR_V850E2V3 }, |
1861 | | { "fnmaf.s", two (0x07e0, 0x04e4), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E3V5_UP }, |
1862 | | { "nmsubf.s", two (0x07e0, 0x0560), two (0x07e0, 0x0761), {R1, R2, R3, R4}, 0, PROCESSOR_V850E2V3 }, |
1863 | | { "fnmsf.s", two (0x07e0, 0x04e6), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E3V5_UP }, |
1864 | | { "recipf.d", two (0x07e1, 0x045e), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, |
1865 | | { "recipf.s", two (0x07e1, 0x044e), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP }, |
1866 | | |
1867 | | { "roundf.dl", two (0x07e0, 0x0454), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP | PROCESSOR_OPTION_EXTENSION }, |
1868 | | { "roundf.dul", two (0x07f0, 0x0454), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP | PROCESSOR_OPTION_EXTENSION }, |
1869 | | { "roundf.duw", two (0x07f0, 0x0450), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3_UP | PROCESSOR_OPTION_EXTENSION }, |
1870 | | { "roundf.dw", two (0x07e0, 0x0450), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3_UP | PROCESSOR_OPTION_EXTENSION }, |
1871 | | { "roundf.sl", two (0x07e0, 0x0444), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP | PROCESSOR_OPTION_EXTENSION }, |
1872 | | { "roundf.sul", two (0x07f0, 0x0444), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP | PROCESSOR_OPTION_EXTENSION }, |
1873 | | { "roundf.suw", two (0x07f0, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP | PROCESSOR_OPTION_EXTENSION }, |
1874 | | { "roundf.sw", two (0x07e0, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP | PROCESSOR_OPTION_EXTENSION }, |
1875 | | |
1876 | | { "rsqrtf.d", two (0x07e2, 0x045e), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, |
1877 | | { "rsqrtf.s", two (0x07e2, 0x044e), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP }, |
1878 | | { "sqrtf.d", two (0x07e0, 0x045e), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, |
1879 | | { "sqrtf.s", two (0x07e0, 0x044e), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP }, |
1880 | | { "subf.d", two (0x07e0, 0x0472), two (0x0fe1, 0x0fff), {R1_EVEN, R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, |
1881 | | { "subf.s", two (0x07e0, 0x0462), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2V3_UP }, |
1882 | | { "trfsr", two (0x07e0, 0x0400), two (0xffff, 0xfff1), {FFF}, 0, PROCESSOR_V850E2V3_UP }, |
1883 | | { "trfsr", two (0x07e0, 0x0400), two (0xffff, 0xffff), {0}, 0, PROCESSOR_V850E2V3_UP }, |
1884 | | { "trncf.dl", two (0x07e1, 0x0454), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, |
1885 | | { "trncf.dul", two (0x07f1, 0x0454), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, |
1886 | | { "trncf.duw", two (0x07f1, 0x0450), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3_UP }, |
1887 | | { "trncf.dw", two (0x07e1, 0x0450), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3_UP }, |
1888 | | { "trncf.sl", two (0x07e1, 0x0444), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, |
1889 | | { "trncf.sul", two (0x07f1, 0x0444), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP }, |
1890 | | { "trncf.suw", two (0x07f1, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP }, |
1891 | | { "trncf.sw", two (0x07e1, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP }, |
1892 | | |
1893 | | /* Special instruction (from gdb) mov 1, r0. */ |
1894 | | { "breakpoint", one (0x0001), one (0xffff), {UNUSED}, 0, PROCESSOR_ALL }, |
1895 | | |
1896 | | { "synci", one (0x001c), one (0xffff), {0}, 0, PROCESSOR_V850E3V5_UP }, |
1897 | | |
1898 | | { "synce", one (0x001d), one (0xffff), {0}, 0, PROCESSOR_V850E2V3_UP }, |
1899 | | { "syncm", one (0x001e), one (0xffff), {0}, 0, PROCESSOR_V850E2V3_UP }, |
1900 | | { "syncp", one (0x001f), one (0xffff), {0}, 0, PROCESSOR_V850E2V3_UP }, |
1901 | | { "syscall", two (0xd7e0, 0x0160), two (0xffe0, 0xc7ff), {V8}, 0, PROCESSOR_V850E2V3_UP }, |
1902 | | /* Alias of syncp. */ |
1903 | | { "sync", one (0x001f), one (0xffff), {0}, 0, PROCESSOR_V850E2V3_UP | PROCESSOR_OPTION_ALIAS }, |
1904 | | { "rmtrap", one (0xf040), one (0xffff), {0}, 0, PROCESSOR_V850E2V3_UP }, |
1905 | | { "rie", one (0x0040), one (0xffff), {0}, 0, PROCESSOR_V850E2V3_UP }, |
1906 | | { "rie", two (0x07f0, 0x0000), two (0x07f0, 0xffff), {RIE_IMM5,RIE_IMM4}, 0, PROCESSOR_V850E2V3_UP }, |
1907 | | |
1908 | | { 0, 0, 0, {0}, 0, 0 }, |
1909 | | } ; |
1910 | | |
1911 | | const int v850_num_opcodes = |
1912 | | sizeof (v850_opcodes) / sizeof (v850_opcodes[0]); |