Coverage Report

Created: 2025-07-08 11:15

/src/binutils-gdb/gas/config/tc-i386.c
Line
Count
Source (jump to first uncovered line)
1
/* tc-i386.c -- Assemble code for the Intel 80386
2
   Copyright (C) 1989-2025 Free Software Foundation, Inc.
3
4
   This file is part of GAS, the GNU Assembler.
5
6
   GAS is free software; you can redistribute it and/or modify
7
   it under the terms of the GNU General Public License as published by
8
   the Free Software Foundation; either version 3, or (at your option)
9
   any later version.
10
11
   GAS is distributed in the hope that it will be useful,
12
   but WITHOUT ANY WARRANTY; without even the implied warranty of
13
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14
   GNU General Public License for more details.
15
16
   You should have received a copy of the GNU General Public License
17
   along with GAS; see the file COPYING.  If not, write to the Free
18
   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
19
   02110-1301, USA.  */
20
21
/* Intel 80386 machine specific gas.
22
   Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23
   x86_64 support by Jan Hubicka (jh@suse.cz)
24
   VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25
   Bugs & suggestions are completely welcome.  This is free software.
26
   Please help us make it better.  */
27
28
#include "as.h"
29
#include "safe-ctype.h"
30
#include "subsegs.h"
31
#include "dwarf2dbg.h"
32
#include "dw2gencfi.h"
33
#include "scfi.h"
34
#include "gen-sframe.h"
35
#include "sframe.h"
36
#include "elf/x86-64.h"
37
#include "opcodes/i386-init.h"
38
#include "opcodes/i386-mnem.h"
39
#include <limits.h>
40
41
#ifndef INFER_ADDR_PREFIX
42
#define INFER_ADDR_PREFIX 1
43
#endif
44
45
#ifndef DEFAULT_ARCH
46
#define DEFAULT_ARCH "i386"
47
#endif
48
49
#ifndef INLINE
50
#if __GNUC__ >= 2
51
#define INLINE __inline__
52
#else
53
#define INLINE
54
#endif
55
#endif
56
57
/* Prefixes will be emitted in the order defined below.
58
   WAIT_PREFIX must be the first prefix since FWAIT is really is an
59
   instruction, and so must come before any prefixes.
60
   The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
61
   REP_PREFIX/HLE_PREFIX, LOCK_PREFIX.  */
62
0
#define WAIT_PREFIX 0
63
0
#define SEG_PREFIX  1
64
0
#define ADDR_PREFIX 2
65
0
#define DATA_PREFIX 3
66
0
#define REP_PREFIX  4
67
0
#define HLE_PREFIX  REP_PREFIX
68
0
#define BND_PREFIX  REP_PREFIX
69
0
#define LOCK_PREFIX 5
70
0
#define REX_PREFIX  6       /* must come last.  */
71
#define MAX_PREFIXES  7 /* max prefixes per opcode */
72
73
/* we define the syntax here (modulo base,index,scale syntax) */
74
0
#define REGISTER_PREFIX '%'
75
0
#define IMMEDIATE_PREFIX '$'
76
0
#define ABSOLUTE_PREFIX '*'
77
78
/* these are the instruction mnemonic suffixes in AT&T syntax or
79
   memory operand size in Intel syntax.  */
80
0
#define WORD_MNEM_SUFFIX  'w'
81
0
#define BYTE_MNEM_SUFFIX  'b'
82
0
#define SHORT_MNEM_SUFFIX 's'
83
0
#define LONG_MNEM_SUFFIX  'l'
84
0
#define QWORD_MNEM_SUFFIX  'q'
85
86
0
#define END_OF_INSN '\0'
87
88
#define OPERAND_TYPE_NONE { .bitfield = { .class = ClassNone } }
89
90
/* This matches the C -> StaticRounding alias in the opcode table.  */
91
0
#define commutative staticrounding
92
93
/*
94
  'templates' is for grouping together 'template' structures for opcodes
95
  of the same name.  This is only used for storing the insns in the grand
96
  ole hash table of insns.
97
  The templates themselves start at START and range up to (but not including)
98
  END.
99
  */
100
typedef struct
101
{
102
  const insn_template *start;
103
  const insn_template *end;
104
}
105
templates;
106
107
/* 386 operand encoding bytes:  see 386 book for details of this.  */
108
typedef struct
109
{
110
  unsigned int regmem;  /* codes register or memory operand */
111
  unsigned int reg; /* codes register operand (or extended opcode) */
112
  unsigned int mode;  /* how to interpret regmem & reg */
113
}
114
modrm_byte;
115
116
/* x86-64 extension prefix.  */
117
typedef int rex_byte;
118
119
/* 386 opcode byte to code indirect addressing.  */
120
typedef struct
121
{
122
  unsigned base;
123
  unsigned index;
124
  unsigned scale;
125
}
126
sib_byte;
127
128
/* x86 arch names, types and features */
129
typedef struct
130
{
131
  const char *name;   /* arch name */
132
  unsigned int len:8;   /* arch string length */
133
  bool skip:1;      /* show_arch should skip this. */
134
  enum processor_type type; /* arch type */
135
  enum { vsz_none, vsz_set, vsz_reset } vsz; /* vector size control */
136
  i386_cpu_flags enable;    /* cpu feature enable flags */
137
  i386_cpu_flags disable; /* cpu feature disable flags */
138
}
139
arch_entry;
140
141
/* Modes for parse_insn() to operate in.  */
142
enum parse_mode {
143
  parse_all,
144
  parse_prefix,
145
  parse_pseudo_prefix,
146
};
147
148
static void update_code_flag (int, int);
149
static void s_insn (int);
150
static void s_noopt (int);
151
static void set_code_flag (int);
152
static void set_16bit_gcc_code_flag (int);
153
static void set_intel_syntax (int);
154
static void set_intel_mnemonic (int);
155
static void set_allow_index_reg (int);
156
static void set_check (int);
157
static void set_cpu_arch (int);
158
#ifdef TE_PE
159
static void pe_directive_secrel (int);
160
static void pe_directive_secidx (int);
161
#endif
162
static void signed_cons (int);
163
static char *output_invalid (int c);
164
static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
165
            const char *);
166
static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
167
               const char *);
168
static int i386_att_operand (char *);
169
static int i386_intel_operand (char *, int);
170
static int i386_intel_simplify (expressionS *);
171
static int i386_intel_parse_name (const char *, expressionS *, enum expr_mode);
172
static const reg_entry *parse_register (const char *, char **);
173
static const char *parse_insn (const char *, char *, enum parse_mode);
174
static char *parse_operands (char *, const char *);
175
static void copy_operand (unsigned int, unsigned int);
176
static void swap_operands (void);
177
static void swap_2_operands (unsigned int, unsigned int);
178
static enum i386_flag_code i386_addressing_mode (void);
179
static void optimize_imm (void);
180
static bool optimize_disp (const insn_template *t);
181
static const insn_template *match_template (char);
182
static int check_string (void);
183
static int process_suffix (const insn_template *);
184
static int check_byte_reg (void);
185
static int check_long_reg (void);
186
static int check_qword_reg (void);
187
static int check_word_reg (void);
188
static int finalize_imm (void);
189
static int process_operands (void);
190
static const reg_entry *build_modrm_byte (void);
191
static void output_insn (const struct last_insn *);
192
static void output_imm (fragS *, offsetT);
193
static void output_disp (fragS *, offsetT);
194
#ifdef OBJ_AOUT
195
static void s_bss (int);
196
#endif
197
#ifdef OBJ_ELF
198
static void handle_large_common (int small ATTRIBUTE_UNUSED);
199
200
/* GNU_PROPERTY_X86_ISA_1_USED.  */
201
static unsigned int x86_isa_1_used;
202
/* GNU_PROPERTY_X86_FEATURE_2_USED.  */
203
static unsigned int x86_feature_2_used;
204
/* Generate x86 used ISA and feature properties.  */
205
static unsigned int x86_used_note = DEFAULT_X86_USED_NOTE;
206
#endif
207
208
static const char *default_arch = DEFAULT_ARCH;
209
210
/* parse_register() returns this when a register alias cannot be used.  */
211
static const reg_entry bad_reg = { "<bad>", OPERAND_TYPE_NONE, 0, 0,
212
           { Dw2Inval, Dw2Inval } };
213
214
static const reg_entry *reg_eax;
215
static const reg_entry *reg_ds;
216
static const reg_entry *reg_es;
217
static const reg_entry *reg_ss;
218
static const reg_entry *reg_st0;
219
static const reg_entry *reg_k0;
220
221
/* VEX prefix.  */
222
typedef struct
223
{
224
  /* VEX prefix is either 2 byte or 3 byte.  EVEX is 4 byte.  */
225
  unsigned char bytes[4];
226
  unsigned int length;
227
  /* Destination or source register specifier.  */
228
  const reg_entry *register_specifier;
229
} vex_prefix;
230
231
/* 'md_assemble ()' gathers together information and puts it into a
232
   i386_insn.  */
233
234
union i386_op
235
  {
236
    expressionS *disps;
237
    expressionS *imms;
238
    const reg_entry *regs;
239
  };
240
241
enum i386_error
242
  {
243
    no_error, /* Must be first.  */
244
    operand_size_mismatch,
245
    operand_type_mismatch,
246
    register_type_mismatch,
247
    number_of_operands_mismatch,
248
    invalid_instruction_suffix,
249
    bad_imm4,
250
    unsupported_with_intel_mnemonic,
251
    unsupported_syntax,
252
    unsupported_EGPR_for_addressing,
253
    unsupported_nf,
254
    unsupported,
255
    unsupported_on_arch,
256
    unsupported_64bit,
257
    no_vex_encoding,
258
    no_evex_encoding,
259
    invalid_sib_address,
260
    invalid_vsib_address,
261
    invalid_vector_register_set,
262
    invalid_tmm_register_set,
263
    invalid_dest_and_src_register_set,
264
    invalid_dest_register_set,
265
    invalid_pseudo_prefix,
266
    unsupported_vector_index_register,
267
    unsupported_broadcast,
268
    broadcast_needed,
269
    unsupported_masking,
270
    mask_not_on_destination,
271
    no_default_mask,
272
    unsupported_rc_sae,
273
    unsupported_vector_size,
274
    unsupported_rsp_register,
275
    internal_error,
276
  };
277
278
#ifdef OBJ_ELF
279
enum x86_tls_error_type
280
{
281
  x86_tls_error_continue,
282
  x86_tls_error_none,
283
  x86_tls_error_insn,
284
  x86_tls_error_opcode,
285
  x86_tls_error_sib,
286
  x86_tls_error_no_base_reg,
287
  x86_tls_error_require_no_base_index_reg,
288
  x86_tls_error_base_reg,
289
  x86_tls_error_index_ebx,
290
  x86_tls_error_eax,
291
  x86_tls_error_RegA,
292
  x86_tls_error_ebx,
293
  x86_tls_error_rip,
294
  x86_tls_error_dest_eax,
295
  x86_tls_error_dest_rdi,
296
  x86_tls_error_scale_factor,
297
  x86_tls_error_base_reg_size,
298
  x86_tls_error_dest_32bit_reg_size,
299
  x86_tls_error_dest_64bit_reg_size,
300
  x86_tls_error_dest_32bit_or_64bit_reg_size
301
};
302
#endif
303
304
struct _i386_insn
305
  {
306
    /* TM holds the template for the insn were currently assembling.  */
307
    insn_template tm;
308
309
    /* SUFFIX holds the instruction size suffix for byte, word, dword
310
       or qword, if given.  */
311
    char suffix;
312
313
    /* OPCODE_LENGTH holds the number of base opcode bytes.  */
314
    unsigned char opcode_length;
315
316
    /* OPERANDS gives the number of given operands.  */
317
    unsigned int operands;
318
319
    /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
320
       of given register, displacement, memory operands and immediate
321
       operands.  */
322
    unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
323
324
    /* TYPES [i] is the type (see above #defines) which tells us how to
325
       use OP[i] for the corresponding operand.  */
326
    i386_operand_type types[MAX_OPERANDS];
327
328
    /* Displacement expression, immediate expression, or register for each
329
       operand.  */
330
    union i386_op op[MAX_OPERANDS];
331
332
    /* Flags for operands.  */
333
    unsigned int flags[MAX_OPERANDS];
334
0
#define Operand_PCrel 1
335
0
#define Operand_Mem   2
336
0
#define Operand_Signed 4 /* .insn only */
337
338
    /* Relocation type for operand */
339
    enum bfd_reloc_code_real reloc[MAX_OPERANDS];
340
341
    /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
342
       the base index byte below.  */
343
    const reg_entry *base_reg;
344
    const reg_entry *index_reg;
345
    unsigned int log2_scale_factor;
346
347
    /* SEG gives the seg_entries of this insn.  They are zero unless
348
       explicit segment overrides are given.  */
349
    const reg_entry *seg[2];
350
351
    /* PREFIX holds all the given prefix opcodes (usually null).
352
       PREFIXES is the number of prefix opcodes.  */
353
    unsigned int prefixes;
354
    unsigned char prefix[MAX_PREFIXES];
355
356
    /* .insn allows for reserved opcode spaces.  */
357
    unsigned char insn_opcode_space;
358
359
    /* .insn also allows (requires) specifying immediate size.  */
360
    unsigned char imm_bits[MAX_OPERANDS];
361
362
    /* Register is in low 3 bits of opcode.  */
363
    bool short_form;
364
365
    /* The operand to a branch insn indicates an absolute branch.  */
366
    bool jumpabsolute;
367
368
    /* The operand to a branch insn indicates a far branch.  */
369
    bool far_branch;
370
371
    /* There is a memory operand of (%dx) which should be only used
372
       with input/output instructions.  */
373
    bool input_output_operand;
374
375
    /* Extended states.  */
376
    enum
377
      {
378
  /* Use MMX state.  */
379
  xstate_mmx = 1 << 0,
380
  /* Use XMM state.  */
381
  xstate_xmm = 1 << 1,
382
  /* Use YMM state.  */
383
  xstate_ymm = 1 << 2 | xstate_xmm,
384
  /* Use ZMM state.  */
385
  xstate_zmm = 1 << 3 | xstate_ymm,
386
  /* Use TMM state.  */
387
  xstate_tmm = 1 << 4,
388
  /* Use MASK state.  */
389
  xstate_mask = 1 << 5
390
      } xstate;
391
392
    /* Has GOTPC or TLS relocation.  */
393
    bool has_gotpc_tls_reloc;
394
395
    /* Has relocation entry from the gotrel array.  */
396
    bool has_gotrel;
397
398
    /* RM and SIB are the modrm byte and the sib byte where the
399
       addressing modes of this insn are encoded.  */
400
    modrm_byte rm;
401
    rex_byte rex;
402
    rex_byte vrex;
403
    rex_byte rex2;
404
    sib_byte sib;
405
    vex_prefix vex;
406
407
    /* Masking attributes.
408
409
       The struct describes masking, applied to OPERAND in the instruction.
410
       REG is a pointer to the corresponding mask register.  ZEROING tells
411
       whether merging or zeroing mask is used.  */
412
    struct Mask_Operation
413
    {
414
      const reg_entry *reg;
415
      unsigned int zeroing;
416
      /* The operand where this operation is associated.  */
417
      unsigned int operand;
418
    } mask;
419
420
    /* Rounding control and SAE attributes.  */
421
    struct RC_Operation
422
    {
423
      enum rc_type
424
  {
425
    rc_none = -1,
426
    rne,
427
    rd,
428
    ru,
429
    rz,
430
    saeonly
431
  } type;
432
      /* In Intel syntax the operand modifier form is supposed to be used, but
433
   we continue to accept the immediate forms as well.  */
434
      bool modifier;
435
    } rounding;
436
437
    /* Broadcasting attributes.
438
439
       The struct describes broadcasting, applied to OPERAND.  TYPE is
440
       expresses the broadcast factor.  */
441
    struct Broadcast_Operation
442
    {
443
      /* Type of broadcast: {1to2}, {1to4}, {1to8}, {1to16} or {1to32}.  */
444
      unsigned int type;
445
446
      /* Index of broadcasted operand.  */
447
      unsigned int operand;
448
449
      /* Number of bytes to broadcast.  */
450
      unsigned int bytes;
451
    } broadcast;
452
453
    /* Compressed disp8*N attribute.  */
454
    unsigned int memshift;
455
456
    /* SCC = EVEX.[SC3,SC2,SC1,SC0].  */
457
    unsigned int scc;
458
459
    /* Store 4 bits of EVEX.[OF,SF,ZF,CF].  */
460
0
#define OSZC_CF 1
461
0
#define OSZC_ZF 2
462
0
#define OSZC_SF 4
463
0
#define OSZC_OF 8
464
    unsigned int oszc_flags;
465
466
    /* Invert the condition encoded in a base opcode.  */
467
    bool invert_cond;
468
469
    /* REP prefix.  */
470
    const char *rep_prefix;
471
472
    /* HLE prefix.  */
473
    const char *hle_prefix;
474
475
    /* Have BND prefix.  */
476
    const char *bnd_prefix;
477
478
    /* Have NOTRACK prefix.  */
479
    const char *notrack_prefix;
480
481
    /* Error message.  */
482
    enum i386_error error;
483
  };
484
485
typedef struct _i386_insn i386_insn;
486
487
/* Pseudo-prefix recording state, separate from i386_insn.  */
488
static struct pseudo_prefixes {
489
  /* How to encode instructions.  */
490
  enum {
491
    encoding_default = 0,
492
    encoding_vex,
493
    encoding_vex3,
494
    encoding_egpr, /* REX2 or EVEX.  */
495
    encoding_evex,
496
    encoding_evex512,
497
    encoding_error
498
  } encoding;
499
500
  /* Prefer load or store in encoding.  */
501
  enum {
502
    dir_encoding_default = 0,
503
    dir_encoding_load,
504
    dir_encoding_store,
505
    dir_encoding_swap
506
  } dir_encoding;
507
508
  /* Prefer 8bit, 16bit, 32bit displacement in encoding.  */
509
  enum {
510
    disp_encoding_default = 0,
511
    disp_encoding_8bit,
512
    disp_encoding_16bit,
513
    disp_encoding_32bit
514
  } disp_encoding;
515
516
  /* Exclude sign-extended 8bit immediate in encoding.  */
517
  bool no_imm8s;
518
519
  /* Prefer the REX byte in encoding.  */
520
  bool rex_encoding;
521
522
  /* Prefer the REX2 prefix in encoding.  */
523
  bool rex2_encoding;
524
525
  /* No CSPAZO flags update.  */
526
  bool has_nf;
527
528
  /* Disable instruction size optimization.  */
529
  bool no_optimize;
530
} pp;
531
532
/* Link RC type with corresponding string, that'll be looked for in
533
   asm.  */
534
struct RC_name
535
{
536
  enum rc_type type;
537
  const char *name;
538
  unsigned int len;
539
};
540
541
static const struct RC_name RC_NamesTable[] =
542
{
543
  {  rne, STRING_COMMA_LEN ("rn-sae") },
544
  {  rd,  STRING_COMMA_LEN ("rd-sae") },
545
  {  ru,  STRING_COMMA_LEN ("ru-sae") },
546
  {  rz,  STRING_COMMA_LEN ("rz-sae") },
547
  {  saeonly,  STRING_COMMA_LEN ("sae") },
548
};
549
550
/* To be indexed by segment register number.  */
551
static const unsigned char i386_seg_prefixes[] = {
552
  ES_PREFIX_OPCODE,
553
  CS_PREFIX_OPCODE,
554
  SS_PREFIX_OPCODE,
555
  DS_PREFIX_OPCODE,
556
  FS_PREFIX_OPCODE,
557
  GS_PREFIX_OPCODE
558
};
559
560
/* List of chars besides those in app.c:symbol_chars that can start an
561
   operand.  Used to prevent the scrubber eating vital white-space.  */
562
const char extra_symbol_chars[] = "*%-(["
563
#ifdef LEX_AT
564
  "@"
565
#endif
566
#ifdef LEX_QM
567
  "?"
568
#endif
569
  ;
570
571
#if (defined (OBJ_ELF)          \
572
     && !defined (TE_GNU)       \
573
     && !defined (TE_LINUX)       \
574
     && !defined (TE_Haiku)       \
575
     && !defined (TE_FreeBSD)       \
576
     && !defined (TE_DragonFly)       \
577
     && !defined (TE_NetBSD))
578
/* This array holds the chars that always start a comment.  If the
579
   pre-processor is disabled, these aren't very useful.  The option
580
   --divide will remove '/' from this list.  */
581
const char *i386_comment_chars = "#/";
582
#define SVR4_COMMENT_CHARS 1
583
#define PREFIX_SEPARATOR '\\'
584
585
#else
586
const char *i386_comment_chars = "#";
587
0
#define PREFIX_SEPARATOR '/'
588
#endif
589
590
/* This array holds the chars that only start a comment at the beginning of
591
   a line.  If the line seems to have the form '# 123 filename'
592
   .line and .file directives will appear in the pre-processed output.
593
   Note that input_file.c hand checks for '#' at the beginning of the
594
   first line of the input file.  This is because the compiler outputs
595
   #NO_APP at the beginning of its output.
596
   Also note that comments started like this one will always work if
597
   '/' isn't otherwise defined.  */
598
const char line_comment_chars[] = "#/";
599
600
const char line_separator_chars[] = ";";
601
602
/* Chars that can be used to separate mant from exp in floating point
603
   nums.  */
604
const char EXP_CHARS[] = "eE";
605
606
/* Chars that mean this number is a floating point constant
607
   As in 0f12.456
608
   or    0d1.2345e12.  */
609
const char FLT_CHARS[] = "fFdDxXhHbB";
610
611
/* Tables for lexical analysis.  */
612
static char mnemonic_chars[256];
613
static char register_chars[256];
614
static char operand_chars[256];
615
616
/* Lexical macros.  */
617
0
#define is_operand_char(x) (operand_chars[(unsigned char) x])
618
#define is_register_char(x) (register_chars[(unsigned char) x])
619
620
/* All non-digit non-letter characters that may occur in an operand and
621
   which aren't already in extra_symbol_chars[].  */
622
static const char operand_special_chars[] = "$+,)._~/<>|&^!=:@]{}";
623
624
/* md_assemble() always leaves the strings it's passed unaltered.  To
625
   effect this we maintain a stack of saved characters that we've smashed
626
   with '\0's (indicating end of strings for various sub-fields of the
627
   assembler instruction).  */
628
static char save_stack[32];
629
static char *save_stack_p;
630
#define END_STRING_AND_SAVE(s) \
631
0
  do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
632
#define RESTORE_END_STRING(s) \
633
0
  do { *(s) = *--save_stack_p; } while (0)
634
635
/* The instruction we're assembling.  */
636
static i386_insn i;
637
638
/* Possible templates for current insn.  */
639
static templates current_templates;
640
641
/* Per instruction expressionS buffers: max displacements & immediates.  */
642
static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
643
static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
644
645
/* Current operand we are working on.  */
646
static int this_operand = -1;
647
648
/* Are we processing a .insn directive?  */
649
0
#define dot_insn() (i.tm.mnem_off == MN__insn)
650
651
enum i386_flag_code i386_flag_code;
652
0
#define flag_code i386_flag_code /* Permit to continue using original name.  */
653
static unsigned int object_64bit;
654
static unsigned int disallow_64bit_reloc;
655
static int use_rela_relocations = 0;
656
/* __tls_get_addr/___tls_get_addr symbol for TLS.  */
657
static const char *tls_get_addr;
658
659
#ifdef OBJ_ELF
660
661
/* The ELF ABI to use.  */
662
enum x86_elf_abi
663
{
664
  I386_ABI,
665
  X86_64_ABI,
666
  X86_64_X32_ABI
667
};
668
669
static enum x86_elf_abi x86_elf_abi = I386_ABI;
670
#endif
671
672
#if defined (TE_PE) || defined (TE_PEP)
673
/* Use big object file format.  */
674
static int use_big_obj = 0;
675
#endif
676
677
#ifdef OBJ_ELF
678
/* 1 if generating code for a shared library.  */
679
static int shared = 0;
680
681
const unsigned int x86_sframe_cfa_sp_reg = REG_SP;
682
/* The other CFA base register for SFrame stack trace info.  */
683
const unsigned int x86_sframe_cfa_fp_reg = REG_FP;
684
/* The return address register for SFrame stack trace info.  For AMD64, RA
685
   tracking is not needed, but some directives like .cfi_undefined may use
686
   RA to indicate the outermost frame.  */
687
const unsigned int x86_sframe_cfa_ra_reg = REG_RA;
688
689
static ginsnS *x86_ginsn_new (const symbolS *, enum ginsn_gen_mode);
690
#endif
691
692
/* 1 for intel syntax,
693
   0 if att syntax.  */
694
static int intel_syntax = 0;
695
696
static enum x86_64_isa
697
{
698
  amd64 = 1,  /* AMD64 ISA.  */
699
  intel64 /* Intel64 ISA.  */
700
} isa64;
701
702
/* 1 for intel mnemonic,
703
   0 if att mnemonic.  */
704
static int intel_mnemonic = !SYSV386_COMPAT;
705
706
/* 1 if pseudo registers are permitted.  */
707
static int allow_pseudo_reg = 0;
708
709
/* 1 if register prefix % not required.  */
710
static int allow_naked_reg = 0;
711
712
/* 1 if the assembler should add BND prefix for all control-transferring
713
   instructions supporting it, even if this prefix wasn't specified
714
   explicitly.  */
715
static int add_bnd_prefix = 0;
716
717
/* 1 if pseudo index register, eiz/riz, is allowed .  */
718
static int allow_index_reg = 0;
719
720
/* 1 if the assembler should ignore LOCK prefix, even if it was
721
   specified explicitly.  */
722
static int omit_lock_prefix = 0;
723
724
/* 1 if the assembler should encode lfence, mfence, and sfence as
725
   "lock addl $0, (%{re}sp)".  */
726
static int avoid_fence = 0;
727
728
/* 1 if lfence should be inserted after every load.  */
729
static int lfence_after_load = 0;
730
731
/* Non-zero if lfence should be inserted before indirect branch.  */
732
static enum lfence_before_indirect_branch_kind
733
  {
734
    lfence_branch_none = 0,
735
    lfence_branch_register,
736
    lfence_branch_memory,
737
    lfence_branch_all
738
  }
739
lfence_before_indirect_branch;
740
741
/* Non-zero if lfence should be inserted before ret.  */
742
static enum lfence_before_ret_kind
743
  {
744
    lfence_before_ret_none = 0,
745
    lfence_before_ret_not,
746
    lfence_before_ret_or,
747
    lfence_before_ret_shl
748
  }
749
lfence_before_ret;
750
751
/* 1 if the assembler should generate relax relocations.  */
752
753
static int generate_relax_relocations
754
  = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS;
755
756
/* 1 if the assembler should check tls relocation.  */
757
static bool tls_check = DEFAULT_X86_TLS_CHECK;
758
759
static enum check_kind
760
  {
761
    check_none = 0,
762
    check_warning,
763
    check_error
764
  }
765
sse_check, operand_check = check_warning;
766
767
/* Non-zero if branches should be aligned within power of 2 boundary.  */
768
static int align_branch_power = 0;
769
770
/* Types of branches to align.  */
771
enum align_branch_kind
772
  {
773
    align_branch_none = 0,
774
    align_branch_jcc = 1,
775
    align_branch_fused = 2,
776
    align_branch_jmp = 3,
777
    align_branch_call = 4,
778
    align_branch_indirect = 5,
779
    align_branch_ret = 6
780
  };
781
782
/* Type bits of branches to align.  */
783
enum align_branch_bit
784
  {
785
    align_branch_jcc_bit = 1 << align_branch_jcc,
786
    align_branch_fused_bit = 1 << align_branch_fused,
787
    align_branch_jmp_bit = 1 << align_branch_jmp,
788
    align_branch_call_bit = 1 << align_branch_call,
789
    align_branch_indirect_bit = 1 << align_branch_indirect,
790
    align_branch_ret_bit = 1 << align_branch_ret
791
  };
792
793
static unsigned int align_branch = (align_branch_jcc_bit
794
            | align_branch_fused_bit
795
            | align_branch_jmp_bit);
796
797
/* Types of condition jump used by macro-fusion.  */
798
enum mf_jcc_kind
799
  {
800
    mf_jcc_jo = 0,  /* base opcode 0x70  */
801
    mf_jcc_jc,      /* base opcode 0x72  */
802
    mf_jcc_je,      /* base opcode 0x74  */
803
    mf_jcc_jna,     /* base opcode 0x76  */
804
    mf_jcc_js,      /* base opcode 0x78  */
805
    mf_jcc_jp,      /* base opcode 0x7a  */
806
    mf_jcc_jl,      /* base opcode 0x7c  */
807
    mf_jcc_jle,     /* base opcode 0x7e  */
808
  };
809
810
/* Types of compare flag-modifying insntructions used by macro-fusion.  */
811
enum mf_cmp_kind
812
  {
813
    mf_cmp_test_and,  /* test/cmp */
814
    mf_cmp_alu_cmp,  /* add/sub/cmp */
815
    mf_cmp_incdec  /* inc/dec */
816
  };
817
818
/* The maximum padding size for fused jcc.  CMP like instruction can
819
   be 9 bytes and jcc can be 6 bytes.  Leave room just in case for
820
   prefixes.   */
821
0
#define MAX_FUSED_JCC_PADDING_SIZE 20
822
823
/* The maximum number of prefixes added for an instruction.  */
824
static unsigned int align_branch_prefix_size = 5;
825
826
/* Optimization:
827
   1. Clear the REX_W bit with register operand if possible.
828
   2. Above plus use 128bit vector instruction to clear the full vector
829
      register.
830
 */
831
static int optimize = 0;
832
833
/* Optimization:
834
   1. Clear the REX_W bit with register operand if possible.
835
   2. Above plus use 128bit vector instruction to clear the full vector
836
      register.
837
   3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
838
      "testb $imm7,%r8".
839
 */
840
static int optimize_for_space = 0;
841
842
/* Register prefix used for error message.  */
843
static const char *register_prefix = "%";
844
845
/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
846
   leave, push, and pop instructions so that gcc has the same stack
847
   frame as in 32 bit mode.  */
848
static char stackop_size = '\0';
849
850
/* Non-zero to optimize code alignment.  */
851
int optimize_align_code = 1;
852
853
/* Non-zero to quieten some warnings.  */
854
static int quiet_warnings = 0;
855
856
/* Guard to avoid repeated warnings about non-16-bit code on 16-bit CPUs.  */
857
static bool pre_386_16bit_warned;
858
859
/* CPU name.  */
860
static const char *cpu_arch_name = NULL;
861
static char *cpu_sub_arch_name = NULL;
862
863
/* CPU feature flags.  */
864
i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
865
866
/* ISA extensions available in 64-bit mode only.  */
867
static const i386_cpu_flags cpu_64_flags = CPU_ANY_64_FLAGS;
868
869
/* If we have selected a cpu we are generating instructions for.  */
870
static int cpu_arch_tune_set = 0;
871
872
/* Cpu we are generating instructions for.  */
873
enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
874
875
/* CPU instruction set architecture used.  */
876
enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
877
878
/* CPU feature flags of instruction set architecture used.  */
879
i386_cpu_flags cpu_arch_isa_flags;
880
881
/* If set, conditional jumps are not automatically promoted to handle
882
   larger than a byte offset.  */
883
static bool no_cond_jump_promotion = false;
884
885
/* This will be set from an expression parser hook if there's any
886
   applicable operator involved in an expression.  */
887
static enum {
888
  expr_operator_none,
889
  expr_operator_present,
890
  expr_large_value,
891
} expr_mode;
892
893
/* Encode SSE instructions with VEX prefix.  */
894
static unsigned int sse2avx;
895
896
/* Encode aligned vector move as unaligned vector move.  */
897
static unsigned int use_unaligned_vector_move;
898
899
/* Maximum permitted vector size. */
900
0
#define VSZ128 0
901
0
#define VSZ256 1
902
0
#define VSZ512 2
903
0
#define VSZ_DEFAULT VSZ512
904
static unsigned int vector_size = VSZ_DEFAULT;
905
906
/* Encode scalar AVX instructions with specific vector length.  */
907
static enum
908
  {
909
    vex128 = 0,
910
    vex256
911
  } avxscalar;
912
913
/* Encode VEX WIG instructions with specific vex.w.  */
914
static enum
915
  {
916
    vexw0 = 0,
917
    vexw1
918
  } vexwig;
919
920
/* Encode scalar EVEX LIG instructions with specific vector length.  */
921
static enum
922
  {
923
    evexl128 = 0,
924
    evexl256,
925
    evexl512
926
  } evexlig;
927
928
/* Encode EVEX WIG instructions with specific evex.w.  */
929
static enum
930
  {
931
    evexw0 = 0,
932
    evexw1
933
  } evexwig;
934
935
/* Value to encode in EVEX RC bits, for SAE-only instructions.  */
936
static enum rc_type evexrcig = rne;
937
938
/* Pre-defined "_GLOBAL_OFFSET_TABLE_".  */
939
static symbolS *GOT_symbol;
940
941
/* The dwarf2 return column, adjusted for 32 or 64 bit.  */
942
unsigned int x86_dwarf2_return_column;
943
944
/* The dwarf2 data alignment, adjusted for 32 or 64 bit.  */
945
int x86_cie_data_alignment;
946
947
/* Interface to relax_segment.
948
   There are 3 major relax states for 386 jump insns because the
949
   different types of jumps add different sizes to frags when we're
950
   figuring out what sort of jump to choose to reach a given label.
951
952
   BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING are used to align
953
   branches which are handled by md_estimate_size_before_relax() and
954
   i386_generic_table_relax_frag().  */
955
956
/* Types.  */
957
0
#define UNCOND_JUMP 0
958
0
#define COND_JUMP 1
959
0
#define COND_JUMP86 2
960
0
#define BRANCH_PADDING 3
961
0
#define BRANCH_PREFIX 4
962
0
#define FUSED_JCC_PADDING 5
963
964
/* Sizes.  */
965
0
#define CODE16  1
966
0
#define SMALL 0
967
#define SMALL16 (SMALL | CODE16)
968
0
#define BIG 2
969
0
#define BIG16 (BIG | CODE16)
970
971
#ifndef INLINE
972
#ifdef __GNUC__
973
#define INLINE __inline__
974
#else
975
#define INLINE
976
#endif
977
#endif
978
979
#define ENCODE_RELAX_STATE(type, size) \
980
0
  ((relax_substateT) (((type) << 2) | (size)))
981
#define TYPE_FROM_RELAX_STATE(s) \
982
0
  ((s) >> 2)
983
#define DISP_SIZE_FROM_RELAX_STATE(s) \
984
0
    ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
985
986
/* This table is used by relax_frag to promote short jumps to long
987
   ones where necessary.  SMALL (short) jumps may be promoted to BIG
988
   (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long).  We
989
   don't allow a short jump in a 32 bit code segment to be promoted to
990
   a 16 bit offset jump because it's slower (requires data size
991
   prefix), and doesn't work, unless the destination is in the bottom
992
   64k of the code segment (The top 16 bits of eip are zeroed).  */
993
994
const relax_typeS md_relax_table[] =
995
{
996
  /* The fields are:
997
     1) most positive reach of this state,
998
     2) most negative reach of this state,
999
     3) how many bytes this mode will have in the variable part of the frag
1000
     4) which index into the table to try if we can't fit into this one.  */
1001
1002
  /* UNCOND_JUMP states.  */
1003
  {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
1004
  {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
1005
  /* dword jmp adds 4 bytes to frag:
1006
     0 extra opcode bytes, 4 displacement bytes.  */
1007
  {0, 0, 4, 0},
1008
  /* word jmp adds 2 byte2 to frag:
1009
     0 extra opcode bytes, 2 displacement bytes.  */
1010
  {0, 0, 2, 0},
1011
1012
  /* COND_JUMP states.  */
1013
  {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
1014
  {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
1015
  /* dword conditionals adds 5 bytes to frag:
1016
     1 extra opcode byte, 4 displacement bytes.  */
1017
  {0, 0, 5, 0},
1018
  /* word conditionals add 3 bytes to frag:
1019
     1 extra opcode byte, 2 displacement bytes.  */
1020
  {0, 0, 3, 0},
1021
1022
  /* COND_JUMP86 states.  */
1023
  {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
1024
  {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
1025
  /* dword conditionals adds 5 bytes to frag:
1026
     1 extra opcode byte, 4 displacement bytes.  */
1027
  {0, 0, 5, 0},
1028
  /* word conditionals add 4 bytes to frag:
1029
     1 displacement byte and a 3 byte long branch insn.  */
1030
  {0, 0, 4, 0}
1031
};
1032
1033
#define ARCH(n, t, f, s) \
1034
  { STRING_COMMA_LEN (#n), s, PROCESSOR_ ## t, vsz_none, CPU_ ## f ## _FLAGS, \
1035
    CPU_NONE_FLAGS }
1036
#define SUBARCH(n, e, d, s) \
1037
  { STRING_COMMA_LEN (#n), s, PROCESSOR_NONE, vsz_none, CPU_ ## e ## _FLAGS, \
1038
    CPU_ ## d ## _FLAGS }
1039
#define VECARCH(n, e, d, v) \
1040
  { STRING_COMMA_LEN (#n), false, PROCESSOR_NONE, vsz_ ## v, \
1041
    CPU_ ## e ## _FLAGS, CPU_ ## d ## _FLAGS }
1042
1043
static const arch_entry cpu_arch[] =
1044
{
1045
  /* Do not replace the first two entries - i386_target_format() and
1046
     set_cpu_arch() rely on them being there in this order.  */
1047
  ARCH (generic32, GENERIC32, GENERIC32, false),
1048
  ARCH (generic64, GENERIC64, GENERIC64, false),
1049
  ARCH (i8086, UNKNOWN, NONE, false),
1050
  ARCH (i186, UNKNOWN, 186, false),
1051
  ARCH (i286, UNKNOWN, 286, false),
1052
  ARCH (i386, I386, 386, false),
1053
  ARCH (i486, I486, 486, false),
1054
  ARCH (i586, PENTIUM, 586, false),
1055
  ARCH (pentium, PENTIUM, 586, false),
1056
  ARCH (i686, I686, 686, false),
1057
  ARCH (pentiumpro, PENTIUMPRO, PENTIUMPRO, false),
1058
  ARCH (pentiumii, PENTIUMPRO, P2, false),
1059
  ARCH (pentiumiii, PENTIUMPRO, P3, false),
1060
  ARCH (pentium4, PENTIUM4, P4, false),
1061
  ARCH (prescott, NOCONA, CORE, false),
1062
  ARCH (nocona, NOCONA, NOCONA, false),
1063
  ARCH (yonah, CORE, CORE, true),
1064
  ARCH (core, CORE, CORE, false),
1065
  ARCH (merom, CORE2, CORE2, true),
1066
  ARCH (core2, CORE2, CORE2, false),
1067
  ARCH (corei7, COREI7, COREI7, false),
1068
  ARCH (iamcu, IAMCU, IAMCU, false),
1069
  ARCH (k6, K6, K6, false),
1070
  ARCH (k6_2, K6, K6_2, false),
1071
  ARCH (athlon, ATHLON, ATHLON, false),
1072
  ARCH (sledgehammer, K8, K8, true),
1073
  ARCH (opteron, K8, K8, false),
1074
  ARCH (k8, K8, K8, false),
1075
  ARCH (amdfam10, AMDFAM10, AMDFAM10, false),
1076
  ARCH (bdver1, BD, BDVER1, false),
1077
  ARCH (bdver2, BD, BDVER2, false),
1078
  ARCH (bdver3, BD, BDVER3, false),
1079
  ARCH (bdver4, BD, BDVER4, false),
1080
  ARCH (znver1, ZNVER, ZNVER1, false),
1081
  ARCH (znver2, ZNVER, ZNVER2, false),
1082
  ARCH (znver3, ZNVER, ZNVER3, false),
1083
  ARCH (znver4, ZNVER, ZNVER4, false),
1084
  ARCH (znver5, ZNVER, ZNVER5, false),
1085
  ARCH (btver1, BT, BTVER1, false),
1086
  ARCH (btver2, BT, BTVER2, false),
1087
1088
  SUBARCH (8087, 8087, ANY_8087, false),
1089
  SUBARCH (87, NONE, ANY_8087, false), /* Disable only!  */
1090
  SUBARCH (287, 287, ANY_287, false),
1091
  SUBARCH (387, 387, ANY_387, false),
1092
  SUBARCH (687, 687, ANY_687, false),
1093
  SUBARCH (cmov, CMOV, CMOV, false),
1094
  SUBARCH (fxsr, FXSR, ANY_FXSR, false),
1095
  SUBARCH (mmx, MMX, ANY_MMX, false),
1096
  SUBARCH (sse, SSE, ANY_SSE, false),
1097
  SUBARCH (sse2, SSE2, ANY_SSE2, false),
1098
  SUBARCH (sse3, SSE3, ANY_SSE3, false),
1099
  SUBARCH (sse4a, SSE4A, ANY_SSE4A, false),
1100
  SUBARCH (ssse3, SSSE3, ANY_SSSE3, false),
1101
  SUBARCH (sse4.1, SSE4_1, ANY_SSE4_1, false),
1102
  SUBARCH (sse4.2, SSE4_2, ANY_SSE4_2, false),
1103
  SUBARCH (sse4, SSE4_2, ANY_SSE4_1, false),
1104
  VECARCH (avx, AVX, ANY_AVX, reset),
1105
  VECARCH (avx2, AVX2, ANY_AVX2, reset),
1106
  VECARCH (avx512f, AVX512F, ANY_AVX512F, reset),
1107
  VECARCH (avx512cd, AVX512CD, ANY_AVX512CD, reset),
1108
  VECARCH (avx512er, AVX512ER, ANY_AVX512ER, reset),
1109
  VECARCH (avx512pf, AVX512PF, ANY_AVX512PF, reset),
1110
  VECARCH (avx512dq, AVX512DQ, ANY_AVX512DQ, reset),
1111
  VECARCH (avx512bw, AVX512BW, ANY_AVX512BW, reset),
1112
  VECARCH (avx512vl, AVX512VL, ANY_AVX512VL, reset),
1113
  SUBARCH (monitor, MONITOR, MONITOR, false),
1114
  SUBARCH (vmx, VMX, ANY_VMX, false),
1115
  SUBARCH (vmfunc, VMFUNC, ANY_VMFUNC, false),
1116
  SUBARCH (smx, SMX, SMX, false),
1117
  SUBARCH (xsave, XSAVE, ANY_XSAVE, false),
1118
  SUBARCH (xsaveopt, XSAVEOPT, ANY_XSAVEOPT, false),
1119
  SUBARCH (xsavec, XSAVEC, ANY_XSAVEC, false),
1120
  SUBARCH (xsaves, XSAVES, ANY_XSAVES, false),
1121
  SUBARCH (aes, AES, ANY_AES, false),
1122
  SUBARCH (pclmul, PCLMULQDQ, ANY_PCLMULQDQ, false),
1123
  SUBARCH (clmul, PCLMULQDQ, ANY_PCLMULQDQ, true),
1124
  SUBARCH (fsgsbase, FSGSBASE, FSGSBASE, false),
1125
  SUBARCH (rdrnd, RDRND, RDRND, false),
1126
  SUBARCH (f16c, F16C, ANY_F16C, false),
1127
  SUBARCH (bmi2, BMI2, BMI2, false),
1128
  SUBARCH (fma, FMA, ANY_FMA, false),
1129
  SUBARCH (fma4, FMA4, ANY_FMA4, false),
1130
  SUBARCH (xop, XOP, ANY_XOP, false),
1131
  SUBARCH (lwp, LWP, ANY_LWP, false),
1132
  SUBARCH (movbe, MOVBE, MOVBE, false),
1133
  SUBARCH (cx16, CX16, CX16, false),
1134
  SUBARCH (lahf_sahf, LAHF_SAHF, LAHF_SAHF, false),
1135
  SUBARCH (ept, EPT, ANY_EPT, false),
1136
  SUBARCH (lzcnt, LZCNT, LZCNT, false),
1137
  SUBARCH (popcnt, POPCNT, POPCNT, false),
1138
  SUBARCH (hle, HLE, HLE, false),
1139
  SUBARCH (rtm, RTM, ANY_RTM, false),
1140
  SUBARCH (tsx, TSX, TSX, false),
1141
  SUBARCH (invpcid, INVPCID, INVPCID, false),
1142
  SUBARCH (clflush, CLFLUSH, CLFLUSH, false),
1143
  SUBARCH (nop, NOP, NOP, false),
1144
  SUBARCH (syscall, SYSCALL, SYSCALL, false),
1145
  SUBARCH (rdtscp, RDTSCP, RDTSCP, false),
1146
  SUBARCH (3dnow, 3DNOW, ANY_3DNOW, false),
1147
  SUBARCH (3dnowa, 3DNOWA, ANY_3DNOWA, false),
1148
  SUBARCH (padlock, PADLOCK, PADLOCK, false),
1149
  SUBARCH (pacifica, SVME, ANY_SVME, true),
1150
  SUBARCH (svme, SVME, ANY_SVME, false),
1151
  SUBARCH (abm, ABM, ABM, false),
1152
  SUBARCH (bmi, BMI, BMI, false),
1153
  SUBARCH (tbm, TBM, TBM, false),
1154
  SUBARCH (adx, ADX, ADX, false),
1155
  SUBARCH (rdseed, RDSEED, RDSEED, false),
1156
  SUBARCH (prfchw, PRFCHW, PRFCHW, false),
1157
  SUBARCH (smap, SMAP, SMAP, false),
1158
  SUBARCH (mpx, MPX, ANY_MPX, false),
1159
  SUBARCH (sha, SHA, ANY_SHA, false),
1160
  SUBARCH (clflushopt, CLFLUSHOPT, CLFLUSHOPT, false),
1161
  SUBARCH (prefetchwt1, PREFETCHWT1, PREFETCHWT1, false),
1162
  SUBARCH (se1, SE1, SE1, false),
1163
  SUBARCH (clwb, CLWB, CLWB, false),
1164
  VECARCH (avx512ifma, AVX512IFMA, ANY_AVX512IFMA, reset),
1165
  VECARCH (avx512vbmi, AVX512VBMI, ANY_AVX512VBMI, reset),
1166
  VECARCH (avx512_4fmaps, AVX512_4FMAPS, ANY_AVX512_4FMAPS, reset),
1167
  VECARCH (avx512_4vnniw, AVX512_4VNNIW, ANY_AVX512_4VNNIW, reset),
1168
  VECARCH (avx512_vpopcntdq, AVX512_VPOPCNTDQ, ANY_AVX512_VPOPCNTDQ, reset),
1169
  VECARCH (avx512_vbmi2, AVX512_VBMI2, ANY_AVX512_VBMI2, reset),
1170
  VECARCH (avx512_vnni, AVX512_VNNI, ANY_AVX512_VNNI, reset),
1171
  VECARCH (avx512_bitalg, AVX512_BITALG, ANY_AVX512_BITALG, reset),
1172
  VECARCH (avx_vnni, AVX_VNNI, ANY_AVX_VNNI, reset),
1173
  SUBARCH (clzero, CLZERO, CLZERO, false),
1174
  SUBARCH (mwaitx, MWAITX, MWAITX, false),
1175
  SUBARCH (ospke, OSPKE, ANY_OSPKE, false),
1176
  SUBARCH (rdpid, RDPID, RDPID, false),
1177
  SUBARCH (ptwrite, PTWRITE, PTWRITE, false),
1178
  SUBARCH (ibt, IBT, IBT, false),
1179
  SUBARCH (shstk, SHSTK, SHSTK, false),
1180
  SUBARCH (gfni, GFNI, ANY_GFNI, false),
1181
  VECARCH (vaes, VAES, ANY_VAES, reset),
1182
  VECARCH (vpclmulqdq, VPCLMULQDQ, ANY_VPCLMULQDQ, reset),
1183
  SUBARCH (wbnoinvd, WBNOINVD, WBNOINVD, false),
1184
  SUBARCH (pconfig, PCONFIG, PCONFIG, false),
1185
  SUBARCH (waitpkg, WAITPKG, WAITPKG, false),
1186
  SUBARCH (cldemote, CLDEMOTE, CLDEMOTE, false),
1187
  SUBARCH (amx_int8, AMX_INT8, ANY_AMX_INT8, false),
1188
  SUBARCH (amx_bf16, AMX_BF16, ANY_AMX_BF16, false),
1189
  SUBARCH (amx_fp16, AMX_FP16, ANY_AMX_FP16, false),
1190
  SUBARCH (amx_complex, AMX_COMPLEX, ANY_AMX_COMPLEX, false),
1191
  SUBARCH (amx_transpose, AMX_TRANSPOSE, ANY_AMX_TRANSPOSE, false),
1192
  SUBARCH (amx_tf32, AMX_TF32, ANY_AMX_TF32, false),
1193
  SUBARCH (amx_fp8, AMX_FP8, ANY_AMX_FP8, false),
1194
  SUBARCH (amx_movrs, AMX_MOVRS, ANY_AMX_MOVRS, false),
1195
  SUBARCH (amx_avx512, AMX_AVX512, ANY_AMX_AVX512, false),
1196
  SUBARCH (amx_tile, AMX_TILE, ANY_AMX_TILE, false),
1197
  SUBARCH (movdiri, MOVDIRI, MOVDIRI, false),
1198
  SUBARCH (movdir64b, MOVDIR64B, MOVDIR64B, false),
1199
  VECARCH (avx512_bf16, AVX512_BF16, ANY_AVX512_BF16, reset),
1200
  VECARCH (avx512_vp2intersect, AVX512_VP2INTERSECT,
1201
     ANY_AVX512_VP2INTERSECT, reset),
1202
  SUBARCH (tdx, TDX, TDX, false),
1203
  SUBARCH (enqcmd, ENQCMD, ENQCMD, false),
1204
  SUBARCH (serialize, SERIALIZE, SERIALIZE, false),
1205
  SUBARCH (rdpru, RDPRU, RDPRU, false),
1206
  SUBARCH (mcommit, MCOMMIT, MCOMMIT, false),
1207
  SUBARCH (sev_es, SEV_ES, ANY_SEV_ES, false),
1208
  SUBARCH (tsxldtrk, TSXLDTRK, ANY_TSXLDTRK, false),
1209
  SUBARCH (kl, KL, ANY_KL, false),
1210
  SUBARCH (widekl, WIDEKL, ANY_WIDEKL, false),
1211
  SUBARCH (uintr, UINTR, UINTR, false),
1212
  SUBARCH (hreset, HRESET, HRESET, false),
1213
  VECARCH (avx512_fp16, AVX512_FP16, ANY_AVX512_FP16, reset),
1214
  SUBARCH (prefetchi, PREFETCHI, PREFETCHI, false),
1215
  VECARCH (avx_ifma, AVX_IFMA, ANY_AVX_IFMA, reset),
1216
  VECARCH (avx_vnni_int8, AVX_VNNI_INT8, ANY_AVX_VNNI_INT8, reset),
1217
  SUBARCH (cmpccxadd, CMPCCXADD, CMPCCXADD, false),
1218
  SUBARCH (wrmsrns, WRMSRNS, WRMSRNS, false),
1219
  SUBARCH (msrlist, MSRLIST, MSRLIST, false),
1220
  VECARCH (avx_ne_convert, AVX_NE_CONVERT, ANY_AVX_NE_CONVERT, reset),
1221
  SUBARCH (rao_int, RAO_INT, RAO_INT, false),
1222
  SUBARCH (rmpquery, RMPQUERY, ANY_RMPQUERY, false),
1223
  SUBARCH (rmpread, RMPREAD, ANY_RMPREAD, false),
1224
  SUBARCH (fred, FRED, ANY_FRED, false),
1225
  SUBARCH (lkgs, LKGS, ANY_LKGS, false),
1226
  VECARCH (avx_vnni_int16, AVX_VNNI_INT16, ANY_AVX_VNNI_INT16, reset),
1227
  VECARCH (sha512, SHA512, ANY_SHA512, reset),
1228
  VECARCH (sm3, SM3, ANY_SM3, reset),
1229
  VECARCH (sm4, SM4, ANY_SM4, reset),
1230
  SUBARCH (pbndkb, PBNDKB, PBNDKB, false),
1231
  VECARCH (avx10.1, AVX10_1, ANY_AVX512F, set),
1232
  SUBARCH (user_msr, USER_MSR, USER_MSR, false),
1233
  SUBARCH (apx_f, APX_F, APX_F, false),
1234
  VECARCH (avx10.2, AVX10_2, ANY_AVX10_2, set),
1235
  SUBARCH (gmism2, GMISM2, GMISM2, false),
1236
  SUBARCH (gmiccs, GMICCS, GMICCS, false),
1237
  SUBARCH (msr_imm, MSR_IMM, MSR_IMM, false),
1238
  SUBARCH (padlockrng2, PADLOCKRNG2, PADLOCKRNG2, false),
1239
  SUBARCH (padlockphe2, PADLOCKPHE2, PADLOCKPHE2, false),
1240
  SUBARCH (padlockxmodx, PADLOCKXMODX, PADLOCKXMODX, false),
1241
  SUBARCH (movrs, MOVRS, MOVRS, false),
1242
};
1243
1244
#undef SUBARCH
1245
#undef ARCH
1246
1247
#ifdef I386COFF
1248
/* Like s_lcomm_internal in gas/read.c but the alignment string
1249
   is allowed to be optional.  */
1250
1251
static symbolS *
1252
pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
1253
{
1254
  addressT align = 0;
1255
1256
  SKIP_WHITESPACE ();
1257
1258
  if (needs_align
1259
      && *input_line_pointer == ',')
1260
    {
1261
      align = parse_align (needs_align - 1);
1262
1263
      if (align == (addressT) -1)
1264
  return NULL;
1265
    }
1266
  else
1267
    {
1268
      if (size >= 8)
1269
  align = 3;
1270
      else if (size >= 4)
1271
  align = 2;
1272
      else if (size >= 2)
1273
  align = 1;
1274
      else
1275
  align = 0;
1276
    }
1277
1278
  bss_alloc (symbolP, size, align);
1279
  return symbolP;
1280
}
1281
1282
static void
1283
pe_lcomm (int needs_align)
1284
{
1285
  s_comm_internal (needs_align * 2, pe_lcomm_internal);
1286
}
1287
#endif
1288
1289
const pseudo_typeS md_pseudo_table[] =
1290
{
1291
#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1292
  {"align", s_align_bytes, 0},
1293
#else
1294
  {"align", s_align_ptwo, 0},
1295
#endif
1296
  {"arch", set_cpu_arch, 0},
1297
#ifdef OBJ_AOUT
1298
  {"bss", s_bss, 0},
1299
#endif
1300
#ifdef I386COFF
1301
  {"lcomm", pe_lcomm, 1},
1302
#endif
1303
  {"ffloat", float_cons, 'f'},
1304
  {"dfloat", float_cons, 'd'},
1305
  {"tfloat", float_cons, 'x'},
1306
  {"hfloat", float_cons, 'h'},
1307
  {"bfloat16", float_cons, 'b'},
1308
  {"value", cons, 2},
1309
  {"slong", signed_cons, 4},
1310
  {"insn", s_insn, 0},
1311
  {"noopt", s_noopt, 0},
1312
  {"optim", s_ignore, 0},
1313
  {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
1314
  {"code16", set_code_flag, CODE_16BIT},
1315
  {"code32", set_code_flag, CODE_32BIT},
1316
#ifdef BFD64
1317
  {"code64", set_code_flag, CODE_64BIT},
1318
#endif
1319
  {"intel_syntax", set_intel_syntax, 1},
1320
  {"att_syntax", set_intel_syntax, 0},
1321
  {"intel_mnemonic", set_intel_mnemonic, 1},
1322
  {"att_mnemonic", set_intel_mnemonic, 0},
1323
  {"allow_index_reg", set_allow_index_reg, 1},
1324
  {"disallow_index_reg", set_allow_index_reg, 0},
1325
  {"sse_check", set_check, 0},
1326
  {"operand_check", set_check, 1},
1327
#ifdef OBJ_ELF
1328
  {"largecomm", handle_large_common, 0},
1329
#else
1330
  {"file", dwarf2_directive_file, 0},
1331
  {"loc", dwarf2_directive_loc, 0},
1332
  {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
1333
#endif
1334
#ifdef TE_PE
1335
  {"secrel32", pe_directive_secrel, 0},
1336
  {"secidx", pe_directive_secidx, 0},
1337
#endif
1338
  {0, 0, 0}
1339
};
1340
1341
/* For interface with expression ().  */
1342
extern char *input_line_pointer;
1343
1344
/* Hash table for instruction mnemonic lookup.  */
1345
static htab_t op_hash;
1346
1347
/* Hash table for register lookup.  */
1348
static htab_t reg_hash;
1349
1350
#if (defined (OBJ_ELF) || defined (OBJ_MACH_O) || defined (TE_PE))
1351
static const struct
1352
{
1353
  const char *str;
1354
  unsigned int len;
1355
  const enum bfd_reloc_code_real rel[2];
1356
  const i386_operand_type types64;
1357
  bool need_GOT_symbol;
1358
}
1359
gotrel[] =
1360
{
1361
#define OPERAND_TYPE_IMM32_32S_DISP32 { .bitfield = \
1362
      { .imm32 = 1, .imm32s = 1, .disp32 = 1 } }
1363
#define OPERAND_TYPE_IMM32_32S_64_DISP32 { .bitfield = \
1364
      { .imm32 = 1, .imm32s = 1, .imm64 = 1, .disp32 = 1 } }
1365
#define OPERAND_TYPE_IMM32_32S_64_DISP32_64 { .bitfield = \
1366
      { .imm32 = 1, .imm32s = 1, .imm64 = 1, .disp32 = 1, .disp64 = 1 } }
1367
#define OPERAND_TYPE_IMM64_DISP64 { .bitfield = \
1368
      { .imm64 = 1, .disp64 = 1 } }
1369
1370
#ifndef TE_PE
1371
#ifdef OBJ_ELF
1372
    { STRING_COMMA_LEN ("SIZE"),      { BFD_RELOC_SIZE32,
1373
          BFD_RELOC_SIZE32 },
1374
    { .bitfield = { .imm32 = 1, .imm64 = 1 } }, false },
1375
#endif
1376
    { STRING_COMMA_LEN ("PLTOFF"),   { _dummy_first_bfd_reloc_code_real,
1377
               BFD_RELOC_X86_64_PLTOFF64 },
1378
    { .bitfield = { .imm64 = 1 } }, true },
1379
    { STRING_COMMA_LEN ("PLT"),      { BFD_RELOC_386_PLT32,
1380
               BFD_RELOC_X86_64_PLT32    },
1381
    OPERAND_TYPE_IMM32_32S_DISP32, false },
1382
    { STRING_COMMA_LEN ("GOTPLT"),   { _dummy_first_bfd_reloc_code_real,
1383
               BFD_RELOC_X86_64_GOTPLT64 },
1384
    OPERAND_TYPE_IMM64_DISP64, true },
1385
    { STRING_COMMA_LEN ("GOTOFF"),   { BFD_RELOC_386_GOTOFF,
1386
               BFD_RELOC_X86_64_GOTOFF64 },
1387
    OPERAND_TYPE_IMM64_DISP64, true },
1388
    { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
1389
               BFD_RELOC_X86_64_GOTPCREL },
1390
    OPERAND_TYPE_IMM32_32S_DISP32, true },
1391
    { STRING_COMMA_LEN ("TLSGD"),    { BFD_RELOC_386_TLS_GD,
1392
               BFD_RELOC_X86_64_TLSGD    },
1393
    OPERAND_TYPE_IMM32_32S_DISP32, true },
1394
    { STRING_COMMA_LEN ("TLSLDM"),   { BFD_RELOC_386_TLS_LDM,
1395
               _dummy_first_bfd_reloc_code_real },
1396
    OPERAND_TYPE_NONE, true },
1397
    { STRING_COMMA_LEN ("TLSLD"),    { _dummy_first_bfd_reloc_code_real,
1398
               BFD_RELOC_X86_64_TLSLD    },
1399
    OPERAND_TYPE_IMM32_32S_DISP32, true },
1400
    { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
1401
               BFD_RELOC_X86_64_GOTTPOFF },
1402
    OPERAND_TYPE_IMM32_32S_DISP32, true },
1403
    { STRING_COMMA_LEN ("TPOFF"),    { BFD_RELOC_386_TLS_LE_32,
1404
               BFD_RELOC_X86_64_TPOFF32  },
1405
    OPERAND_TYPE_IMM32_32S_64_DISP32_64, true },
1406
    { STRING_COMMA_LEN ("NTPOFF"),   { BFD_RELOC_386_TLS_LE,
1407
               _dummy_first_bfd_reloc_code_real },
1408
    OPERAND_TYPE_NONE, true },
1409
    { STRING_COMMA_LEN ("DTPOFF"),   { BFD_RELOC_386_TLS_LDO_32,
1410
               BFD_RELOC_X86_64_DTPOFF32 },
1411
    OPERAND_TYPE_IMM32_32S_64_DISP32_64, true },
1412
    { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
1413
               _dummy_first_bfd_reloc_code_real },
1414
    OPERAND_TYPE_NONE, true },
1415
    { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
1416
               _dummy_first_bfd_reloc_code_real },
1417
    OPERAND_TYPE_NONE, true },
1418
    { STRING_COMMA_LEN ("GOT"),      { BFD_RELOC_386_GOT32,
1419
               BFD_RELOC_X86_64_GOT32    },
1420
    OPERAND_TYPE_IMM32_32S_64_DISP32, true },
1421
    { STRING_COMMA_LEN ("TLSDESC"),  { BFD_RELOC_386_TLS_GOTDESC,
1422
               BFD_RELOC_X86_64_GOTPC32_TLSDESC },
1423
    OPERAND_TYPE_IMM32_32S_DISP32, true },
1424
    { STRING_COMMA_LEN ("TLSCALL"),  { BFD_RELOC_386_TLS_DESC_CALL,
1425
               BFD_RELOC_X86_64_TLSDESC_CALL },
1426
    OPERAND_TYPE_IMM32_32S_DISP32, true },
1427
#else /* TE_PE */
1428
    { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
1429
               BFD_RELOC_32_SECREL },
1430
    OPERAND_TYPE_IMM32_32S_DISP32, false },
1431
    { STRING_COMMA_LEN ("SECIDX16"), { BFD_RELOC_16_SECIDX,
1432
               BFD_RELOC_16_SECIDX },
1433
    { .bitfield = { .imm16 = 1, .disp16 = 1 } }, false },
1434
    { STRING_COMMA_LEN ("RVA"), { BFD_RELOC_RVA,
1435
               BFD_RELOC_RVA },
1436
    OPERAND_TYPE_IMM32_32S_DISP32, false },
1437
    { STRING_COMMA_LEN ("IMGREL"), { BFD_RELOC_RVA,
1438
               BFD_RELOC_RVA },
1439
    OPERAND_TYPE_IMM32_32S_DISP32, false },
1440
#endif
1441
1442
#undef OPERAND_TYPE_IMM32_32S_DISP32
1443
#undef OPERAND_TYPE_IMM32_32S_64_DISP32
1444
#undef OPERAND_TYPE_IMM32_32S_64_DISP32_64
1445
#undef OPERAND_TYPE_IMM64_DISP64
1446
};
1447
#endif
1448

1449
  /* Various efficient no-op patterns for aligning code labels.
1450
     Note: Don't try to assemble the instructions in the comments.
1451
     0L and 0w are not legal.  */
1452
static const unsigned char f32_1[] =
1453
  {0x90};       /* nop      */
1454
static const unsigned char f32_2[] =
1455
  {0x66,0x90};        /* xchg %ax,%ax   */
1456
static const unsigned char f32_3[] =
1457
  {0x8d,0x76,0x00};     /* leal 0(%esi),%esi  */
1458
#define f32_4 (f32_5 + 1) /* leal 0(%esi,%eiz),%esi */
1459
static const unsigned char f32_5[] =
1460
  {0x2e,0x8d,0x74,0x26,0x00};   /* leal %cs:0(%esi,%eiz),%esi */
1461
static const unsigned char f32_6[] =
1462
  {0x8d,0xb6,0x00,0x00,0x00,0x00};  /* leal 0L(%esi),%esi */
1463
#define f32_7 (f32_8 + 1) /* leal 0L(%esi,%eiz),%esi */
1464
static const unsigned char f32_8[] =
1465
  {0x2e,0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal %cs:0L(%esi,%eiz),%esi */
1466
static const unsigned char f64_3[] =
1467
  {0x48,0x89,0xf6};     /* mov %rsi,%rsi  */
1468
static const unsigned char f64_4[] =
1469
  {0x48,0x8d,0x76,0x00};    /* lea 0(%rsi),%rsi */
1470
#define f64_5 (f64_6 + 1)   /* lea 0(%rsi,%riz),%rsi  */
1471
static const unsigned char f64_6[] =
1472
  {0x2e,0x48,0x8d,0x74,0x26,0x00};  /* lea %cs:0(%rsi,%riz),%rsi  */
1473
static const unsigned char f64_7[] =
1474
  {0x48,0x8d,0xb6,0x00,0x00,0x00,0x00}; /* lea 0L(%rsi),%rsi  */
1475
#define f64_8 (f64_9 + 1)   /* lea 0L(%rsi,%riz),%rsi */
1476
static const unsigned char f64_9[] =
1477
  {0x2e,0x48,0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* lea %cs:0L(%rsi,%riz),%rsi */
1478
#define f16_2 (f64_3 + 1)   /* mov %si,%si  */
1479
static const unsigned char f16_3[] =
1480
  {0x8d,0x74,0x00};     /* lea 0(%si),%si */
1481
#define f16_4 (f16_5 + 1)   /* lea 0W(%si),%si */
1482
static const unsigned char f16_5[] =
1483
  {0x2e,0x8d,0xb4,0x00,0x00};   /* lea %cs:0W(%si),%si  */
1484
static const unsigned char jump_disp8[] =
1485
  {0xeb};       /* jmp disp8         */
1486
static const unsigned char jump32_disp32[] =
1487
  {0xe9};       /* jmp disp32        */
1488
static const unsigned char jump16_disp32[] =
1489
  {0x66,0xe9};        /* jmp disp32        */
1490
/* 32-bit NOPs patterns.  */
1491
static const unsigned char *const f32_patt[] = {
1492
  f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8
1493
};
1494
/* 64-bit NOPs patterns.  */
1495
static const unsigned char *const f64_patt[] = {
1496
  f32_1, f32_2, f64_3, f64_4, f64_5, f64_6, f64_7, f64_8, f64_9
1497
};
1498
/* 16-bit NOPs patterns.  */
1499
static const unsigned char *const f16_patt[] = {
1500
  f32_1, f16_2, f16_3, f16_4, f16_5
1501
};
1502
/* nopl (%[re]ax) */
1503
static const unsigned char alt_3[] =
1504
  {0x0f,0x1f,0x00};
1505
/* nopl 0(%[re]ax) */
1506
static const unsigned char alt_4[] =
1507
  {0x0f,0x1f,0x40,0x00};
1508
/* nopl 0(%[re]ax,%[re]ax,1) */
1509
#define alt_5 (alt_6 + 1)
1510
/* nopw 0(%[re]ax,%[re]ax,1) */
1511
static const unsigned char alt_6[] =
1512
  {0x66,0x0f,0x1f,0x44,0x00,0x00};
1513
/* nopl 0L(%[re]ax) */
1514
static const unsigned char alt_7[] =
1515
  {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1516
/* nopl 0L(%[re]ax,%[re]ax,1) */
1517
#define alt_8 (alt_9 + 1)
1518
/* nopw 0L(%[re]ax,%[re]ax,1) */
1519
static const unsigned char alt_9[] =
1520
  {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1521
/* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1522
#define alt_10 (alt_11 + 1)
1523
/* data16 nopw %cs:0L(%eax,%eax,1) */
1524
static const unsigned char alt_11[] =
1525
  {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1526
/* 32-bit and 64-bit NOPs patterns.  */
1527
static const unsigned char *const alt_patt[] = {
1528
  f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1529
  alt_9, alt_10, alt_11
1530
};
1531
#define alt64_9 (alt64_15 + 6)    /* nopq 0L(%rax,%rax,1)  */
1532
#define alt64_10 (alt64_15 + 5)   /* cs nopq 0L(%rax,%rax,1)  */
1533
/* data16 cs nopq 0L(%rax,%rax,1)  */
1534
#define alt64_11 (alt64_15 + 4)
1535
/* data16 data16 cs nopq 0L(%rax,%rax,1)  */
1536
#define alt64_12 (alt64_15 + 3)
1537
/* data16 data16 data16 cs nopq 0L(%rax,%rax,1)  */
1538
#define alt64_13 (alt64_15 + 2)
1539
/* data16 data16 data16 data16 cs nopq 0L(%rax,%rax,1)  */
1540
#define alt64_14 (alt64_15 + 1)
1541
/* data16 data16 data16 data16 data16 cs nopq 0L(%rax,%rax,1)  */
1542
static const unsigned char alt64_15[] =
1543
  {0x66,0x66,0x66,0x66,0x66,0x2e,0x48,
1544
   0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1545
/* Long 64-bit NOPs patterns.  */
1546
static const unsigned char *const alt64_patt[] = {
1547
  f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1548
  alt64_9, alt64_10, alt64_11,alt64_12, alt64_13, alt64_14, alt64_15
1549
};
1550
1551
static INLINE int
1552
fits_in_imm7 (offsetT num)
1553
0
{
1554
0
  return (num & 0x7f) == num;
1555
0
}
1556
1557
static INLINE int
1558
fits_in_imm31 (offsetT num)
1559
0
{
1560
0
  return (num & 0x7fffffff) == num;
1561
0
}
1562
1563
/* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1564
   single NOP instruction LIMIT.  */
1565
1566
void
1567
i386_generate_nops (fragS *fragP, char *where, offsetT count, int limit)
1568
0
{
1569
0
  const unsigned char *const *patt = NULL;
1570
0
  int max_single_nop_size;
1571
  /* Maximum number of NOPs before switching to jump over NOPs.  */
1572
0
  int max_number_of_nops;
1573
1574
0
  switch (fragP->fr_type)
1575
0
    {
1576
0
    case rs_fill_nop:
1577
0
    case rs_align_code:
1578
0
      break;
1579
0
    case rs_machine_dependent:
1580
      /* Allow NOP padding for jumps and calls.  */
1581
0
      if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PADDING
1582
0
    || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == FUSED_JCC_PADDING)
1583
0
  break;
1584
      /* Fall through.  */
1585
0
    default:
1586
0
      return;
1587
0
    }
1588
1589
  /* We need to decide which NOP sequence to use for 32bit and
1590
     64bit. When -mtune= is used:
1591
1592
     1. For PROCESSOR_I?86, PROCESSOR_PENTIUM, PROCESSOR_IAMCU, and
1593
     PROCESSOR_GENERIC32, f32_patt will be used.
1594
     2. For the rest, alt_patt will be used.
1595
1596
     When -mtune= isn't used, alt_patt will be used if
1597
     cpu_arch_isa_flags has CpuNop.  Otherwise, f32_patt/f64_patt will
1598
     be used.
1599
1600
     When -march= or .arch is used, we can't use anything beyond
1601
     cpu_arch_isa_flags.   */
1602
1603
0
  if (fragP->tc_frag_data.code == CODE_16BIT)
1604
0
    {
1605
0
      patt = f16_patt;
1606
0
      max_single_nop_size = sizeof (f16_patt) / sizeof (f16_patt[0]);
1607
      /* Limit number of NOPs to 2 in 16-bit mode.  */
1608
0
      max_number_of_nops = 2;
1609
0
    }
1610
0
  else
1611
0
    {
1612
0
      patt = fragP->tc_frag_data.code == CODE_64BIT ? f64_patt : f32_patt;
1613
0
      if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
1614
0
  {
1615
    /* PROCESSOR_UNKNOWN means that all ISAs may be used, unless
1616
       explicitly disabled.  */
1617
0
    switch (fragP->tc_frag_data.tune)
1618
0
      {
1619
0
      case PROCESSOR_UNKNOWN:
1620
        /* We use cpu_arch_isa_flags to check if we SHOULD
1621
     optimize with nops.  */
1622
0
        if (fragP->tc_frag_data.isanop)
1623
0
    patt = alt_patt;
1624
0
        break;
1625
1626
0
      case PROCESSOR_CORE:
1627
0
      case PROCESSOR_CORE2:
1628
0
      case PROCESSOR_COREI7:
1629
0
        if (fragP->tc_frag_data.cpunop)
1630
0
    {
1631
0
      if (fragP->tc_frag_data.code == CODE_64BIT)
1632
0
        patt = alt64_patt;
1633
0
      else
1634
0
        patt = alt_patt;
1635
0
    }
1636
0
        break;
1637
1638
0
      case PROCESSOR_PENTIUMPRO:
1639
0
      case PROCESSOR_PENTIUM4:
1640
0
      case PROCESSOR_NOCONA:
1641
0
      case PROCESSOR_GENERIC64:
1642
0
      case PROCESSOR_K6:
1643
0
      case PROCESSOR_ATHLON:
1644
0
      case PROCESSOR_K8:
1645
0
      case PROCESSOR_AMDFAM10:
1646
0
      case PROCESSOR_BD:
1647
0
      case PROCESSOR_ZNVER:
1648
0
      case PROCESSOR_BT:
1649
0
        if (fragP->tc_frag_data.cpunop)
1650
0
    patt = alt_patt;
1651
0
        break;
1652
1653
0
      case PROCESSOR_I386:
1654
0
      case PROCESSOR_I486:
1655
0
      case PROCESSOR_PENTIUM:
1656
0
      case PROCESSOR_I686:
1657
0
      case PROCESSOR_IAMCU:
1658
0
      case PROCESSOR_GENERIC32:
1659
0
        break;
1660
0
      case PROCESSOR_NONE:
1661
0
        abort ();
1662
0
      }
1663
0
  }
1664
0
      else
1665
0
  {
1666
0
    switch (fragP->tc_frag_data.tune)
1667
0
      {
1668
0
      case PROCESSOR_UNKNOWN:
1669
        /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1670
     PROCESSOR_UNKNOWN.  */
1671
0
        abort ();
1672
0
        break;
1673
1674
0
      default:
1675
        /* We use cpu_arch_isa_flags to check if we CAN optimize
1676
     with nops.  */
1677
0
        if (fragP->tc_frag_data.isanop)
1678
0
    patt = alt_patt;
1679
0
        break;
1680
1681
0
      case PROCESSOR_NONE:
1682
0
        abort ();
1683
0
      }
1684
0
  }
1685
1686
0
      if (patt != alt_patt && patt != alt64_patt)
1687
0
  {
1688
0
    max_single_nop_size = patt == f32_patt ? ARRAY_SIZE (f32_patt)
1689
0
             : ARRAY_SIZE (f64_patt);
1690
    /* Limit number of NOPs to 2 for older processors.  */
1691
0
    max_number_of_nops = 2;
1692
0
  }
1693
0
      else
1694
0
  {
1695
0
    max_single_nop_size = patt == alt_patt
1696
0
        ? ARRAY_SIZE (alt_patt)
1697
0
        : ARRAY_SIZE (alt64_patt);
1698
    /* Limit number of NOPs to 7 for newer processors.  */
1699
0
    max_number_of_nops = 7;
1700
0
  }
1701
0
    }
1702
1703
0
  if (limit == 0)
1704
0
    limit = max_single_nop_size;
1705
1706
0
  if (limit > max_single_nop_size || limit < 1)
1707
0
    {
1708
0
      as_bad_where (fragP->fr_file, fragP->fr_line,
1709
0
        _("invalid single nop size: %d "
1710
0
          "(expect within [0, %d])"),
1711
0
        limit, max_single_nop_size);
1712
0
      return;
1713
0
    }
1714
1715
  /* Emit a plain NOP first when the last thing we saw may not have been
1716
     a proper instruction (e.g. a stand-alone prefix or .byte).  */
1717
0
  if (!fragP->tc_frag_data.last_insn_normal)
1718
0
    {
1719
0
      *where++ = 0x90;
1720
0
      --count;
1721
0
    }
1722
1723
0
  if ((count / max_single_nop_size) > max_number_of_nops)
1724
0
    {
1725
      /* Generate jump over NOPs.  */
1726
0
      offsetT disp = count - 2;
1727
0
      if (fits_in_imm7 (disp))
1728
0
  {
1729
    /* Use "jmp disp8" if possible.  */
1730
0
    count = disp;
1731
0
    where[0] = jump_disp8[0];
1732
0
    where[1] = count;
1733
0
    where += 2;
1734
0
  }
1735
0
      else
1736
0
  {
1737
0
    unsigned int size_of_jump;
1738
1739
0
    if (flag_code == CODE_16BIT)
1740
0
      {
1741
0
        where[0] = jump16_disp32[0];
1742
0
        where[1] = jump16_disp32[1];
1743
0
        size_of_jump = 2;
1744
0
      }
1745
0
    else
1746
0
      {
1747
0
        where[0] = jump32_disp32[0];
1748
0
        size_of_jump = 1;
1749
0
      }
1750
1751
0
    count -= size_of_jump + 4;
1752
0
    if (!fits_in_imm31 (count))
1753
0
      {
1754
0
        as_bad_where (fragP->fr_file, fragP->fr_line,
1755
0
          _("jump over nop padding out of range"));
1756
0
        return;
1757
0
      }
1758
1759
0
    md_number_to_chars (where + size_of_jump, count, 4);
1760
0
    where += size_of_jump + 4;
1761
0
  }
1762
0
    }
1763
1764
0
  int non_repeat = count % limit;
1765
0
  if (non_repeat)
1766
0
    {
1767
0
      memcpy (where, patt[non_repeat - 1], non_repeat);
1768
0
      where += non_repeat;
1769
0
      count -= non_repeat;
1770
0
    }
1771
1772
0
  if (fragP->fr_type != rs_machine_dependent)
1773
0
    {
1774
      /* Set up the frag so that everything we have emitted so far is
1775
   included in fr_fix.  The repeating larger nop only needs to
1776
   be written once to the frag memory.  */
1777
0
      fragP->fr_fix = where - fragP->fr_literal;
1778
0
      if (count != 0)
1779
0
  {
1780
0
    fragP->fr_var = limit;
1781
0
    count = limit;
1782
0
  }
1783
0
    }
1784
1785
0
  const unsigned char *nops = patt[limit - 1];
1786
0
  while (count)
1787
0
    {
1788
0
      memcpy (where, nops, limit);
1789
0
      where += limit;
1790
0
      count -= limit;
1791
0
    }
1792
0
}
1793
1794
static INLINE int
1795
operand_type_all_zero (const union i386_operand_type *x)
1796
0
{
1797
0
  switch (ARRAY_SIZE(x->array))
1798
0
    {
1799
0
    case 3:
1800
0
      if (x->array[2])
1801
0
  return 0;
1802
      /* Fall through.  */
1803
0
    case 2:
1804
0
      if (x->array[1])
1805
0
  return 0;
1806
      /* Fall through.  */
1807
0
    case 1:
1808
0
      return !x->array[0];
1809
0
    default:
1810
0
      abort ();
1811
0
    }
1812
0
}
1813
1814
static INLINE void
1815
operand_type_set (union i386_operand_type *x, unsigned int v)
1816
0
{
1817
0
  switch (ARRAY_SIZE(x->array))
1818
0
    {
1819
0
    case 3:
1820
0
      x->array[2] = v;
1821
      /* Fall through.  */
1822
0
    case 2:
1823
0
      x->array[1] = v;
1824
      /* Fall through.  */
1825
0
    case 1:
1826
0
      x->array[0] = v;
1827
      /* Fall through.  */
1828
0
      break;
1829
0
    default:
1830
0
      abort ();
1831
0
    }
1832
1833
0
  x->bitfield.class = ClassNone;
1834
0
  x->bitfield.instance = InstanceNone;
1835
0
}
1836
1837
static INLINE int
1838
operand_type_equal (const union i386_operand_type *x,
1839
        const union i386_operand_type *y)
1840
0
{
1841
0
  switch (ARRAY_SIZE(x->array))
1842
0
    {
1843
0
    case 3:
1844
0
      if (x->array[2] != y->array[2])
1845
0
  return 0;
1846
      /* Fall through.  */
1847
0
    case 2:
1848
0
      if (x->array[1] != y->array[1])
1849
0
  return 0;
1850
      /* Fall through.  */
1851
0
    case 1:
1852
0
      return x->array[0] == y->array[0];
1853
0
      break;
1854
0
    default:
1855
0
      abort ();
1856
0
    }
1857
0
}
1858
1859
static INLINE bool
1860
_is_cpu (const i386_cpu_attr *a, enum i386_cpu cpu)
1861
0
{
1862
0
  switch (cpu)
1863
0
    {
1864
0
    case Cpu287:      return a->bitfield.cpu287;
1865
0
    case Cpu387:      return a->bitfield.cpu387;
1866
0
    case Cpu3dnow:    return a->bitfield.cpu3dnow;
1867
0
    case Cpu3dnowA:   return a->bitfield.cpu3dnowa;
1868
0
    case CpuAVX:      return a->bitfield.cpuavx;
1869
0
    case CpuHLE:      return a->bitfield.cpuhle;
1870
0
    case CpuAVX512F:  return a->bitfield.cpuavx512f;
1871
0
    case CpuAVX512VL: return a->bitfield.cpuavx512vl;
1872
0
    case CpuAPX_F:    return a->bitfield.cpuapx_f;
1873
0
    case CpuAVX10_2:  return a->bitfield.cpuavx10_2;
1874
0
    case CpuAMX_TRANSPOSE:  return a->bitfield.cpuamx_transpose;
1875
0
    case Cpu64:       return a->bitfield.cpu64;
1876
0
    case CpuNo64:     return a->bitfield.cpuno64;
1877
0
    default:
1878
0
      gas_assert (cpu < CpuAttrEnums);
1879
0
    }
1880
0
  return a->bitfield.isa == cpu + 1u;
1881
0
}
1882
1883
static INLINE bool
1884
is_cpu (const insn_template *t, enum i386_cpu cpu)
1885
0
{
1886
0
  return _is_cpu(&t->cpu, cpu);
1887
0
}
1888
1889
static INLINE bool
1890
maybe_cpu (const insn_template *t, enum i386_cpu cpu)
1891
0
{
1892
0
  return _is_cpu(&t->cpu_any, cpu);
1893
0
}
1894
1895
static i386_cpu_flags cpu_flags_from_attr (i386_cpu_attr a)
1896
0
{
1897
0
  const unsigned int bps = sizeof (a.array[0]) * CHAR_BIT;
1898
0
  i386_cpu_flags f = { .array[0] = 0 };
1899
1900
0
  switch (ARRAY_SIZE (a.array))
1901
0
    {
1902
0
    case 1:
1903
0
      f.array[CpuAttrEnums / bps]
1904
0
#ifndef WORDS_BIGENDIAN
1905
0
  |= (a.array[0] >> CpuIsaBits) << (CpuAttrEnums % bps);
1906
#else
1907
  |= (a.array[0] << CpuIsaBits) >> (CpuAttrEnums % bps);
1908
#endif
1909
0
      if (CpuMax / bps > CpuAttrEnums / bps)
1910
0
  f.array[CpuAttrEnums / bps + 1]
1911
0
#ifndef WORDS_BIGENDIAN
1912
0
    = (a.array[0] >> CpuIsaBits) >> (bps - CpuAttrEnums % bps);
1913
#else
1914
    = (a.array[0] << CpuIsaBits) << (bps - CpuAttrEnums % bps);
1915
#endif
1916
0
      break;
1917
1918
0
    default:
1919
0
      abort ();
1920
0
    }
1921
1922
0
  if (a.bitfield.isa)
1923
0
#ifndef WORDS_BIGENDIAN
1924
0
    f.array[(a.bitfield.isa - 1) / bps] |= 1u << ((a.bitfield.isa - 1) % bps);
1925
#else
1926
    f.array[(a.bitfield.isa - 1) / bps] |= 1u << (~(a.bitfield.isa - 1) % bps);
1927
#endif
1928
1929
0
  return f;
1930
0
}
1931
1932
static INLINE int
1933
cpu_flags_all_zero (const union i386_cpu_flags *x)
1934
0
{
1935
0
  switch (ARRAY_SIZE(x->array))
1936
0
    {
1937
0
    case 5:
1938
0
      if (x->array[4])
1939
0
  return 0;
1940
      /* Fall through.  */
1941
0
    case 4:
1942
0
      if (x->array[3])
1943
0
  return 0;
1944
      /* Fall through.  */
1945
0
    case 3:
1946
0
      if (x->array[2])
1947
0
  return 0;
1948
      /* Fall through.  */
1949
0
    case 2:
1950
0
      if (x->array[1])
1951
0
  return 0;
1952
      /* Fall through.  */
1953
0
    case 1:
1954
0
      return !x->array[0];
1955
0
    default:
1956
0
      abort ();
1957
0
    }
1958
0
}
1959
1960
static INLINE int
1961
cpu_flags_equal (const union i386_cpu_flags *x,
1962
     const union i386_cpu_flags *y)
1963
0
{
1964
0
  switch (ARRAY_SIZE(x->array))
1965
0
    {
1966
0
    case 5:
1967
0
      if (x->array[4] != y->array[4])
1968
0
  return 0;
1969
      /* Fall through.  */
1970
0
    case 4:
1971
0
      if (x->array[3] != y->array[3])
1972
0
  return 0;
1973
      /* Fall through.  */
1974
0
    case 3:
1975
0
      if (x->array[2] != y->array[2])
1976
0
  return 0;
1977
      /* Fall through.  */
1978
0
    case 2:
1979
0
      if (x->array[1] != y->array[1])
1980
0
  return 0;
1981
      /* Fall through.  */
1982
0
    case 1:
1983
0
      return x->array[0] == y->array[0];
1984
0
      break;
1985
0
    default:
1986
0
      abort ();
1987
0
    }
1988
0
}
1989
1990
static INLINE int
1991
cpu_flags_check_cpu64 (const insn_template *t)
1992
0
{
1993
0
  return flag_code == CODE_64BIT
1994
0
   ? !t->cpu.bitfield.cpuno64
1995
0
   : !t->cpu.bitfield.cpu64;
1996
0
}
1997
1998
static INLINE i386_cpu_flags
1999
cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
2000
0
{
2001
0
  switch (ARRAY_SIZE (x.array))
2002
0
    {
2003
0
    case 5:
2004
0
      x.array [4] &= y.array [4];
2005
      /* Fall through.  */
2006
0
    case 4:
2007
0
      x.array [3] &= y.array [3];
2008
      /* Fall through.  */
2009
0
    case 3:
2010
0
      x.array [2] &= y.array [2];
2011
      /* Fall through.  */
2012
0
    case 2:
2013
0
      x.array [1] &= y.array [1];
2014
      /* Fall through.  */
2015
0
    case 1:
2016
0
      x.array [0] &= y.array [0];
2017
0
      break;
2018
0
    default:
2019
0
      abort ();
2020
0
    }
2021
0
  return x;
2022
0
}
2023
2024
static INLINE i386_cpu_flags
2025
cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
2026
0
{
2027
0
  switch (ARRAY_SIZE (x.array))
2028
0
    {
2029
0
    case 5:
2030
0
      x.array [4] |= y.array [4];
2031
      /* Fall through.  */
2032
0
    case 4:
2033
0
      x.array [3] |= y.array [3];
2034
      /* Fall through.  */
2035
0
    case 3:
2036
0
      x.array [2] |= y.array [2];
2037
      /* Fall through.  */
2038
0
    case 2:
2039
0
      x.array [1] |= y.array [1];
2040
      /* Fall through.  */
2041
0
    case 1:
2042
0
      x.array [0] |= y.array [0];
2043
0
      break;
2044
0
    default:
2045
0
      abort ();
2046
0
    }
2047
0
  return x;
2048
0
}
2049
2050
static INLINE i386_cpu_flags
2051
cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
2052
0
{
2053
0
  switch (ARRAY_SIZE (x.array))
2054
0
    {
2055
0
    case 5:
2056
0
      x.array [4] &= ~y.array [4];
2057
      /* Fall through.  */
2058
0
    case 4:
2059
0
      x.array [3] &= ~y.array [3];
2060
      /* Fall through.  */
2061
0
    case 3:
2062
0
      x.array [2] &= ~y.array [2];
2063
      /* Fall through.  */
2064
0
    case 2:
2065
0
      x.array [1] &= ~y.array [1];
2066
      /* Fall through.  */
2067
0
    case 1:
2068
0
      x.array [0] &= ~y.array [0];
2069
0
      break;
2070
0
    default:
2071
0
      abort ();
2072
0
    }
2073
0
  return x;
2074
0
}
2075
2076
static const i386_cpu_flags avx512 = CPU_ANY_AVX512F_FLAGS;
2077
2078
static INLINE bool need_evex_encoding (const insn_template *t)
2079
0
{
2080
0
  return pp.encoding == encoding_evex
2081
0
  || pp.encoding == encoding_evex512
2082
0
  || pp.has_nf
2083
0
  || (t->opcode_modifier.vex && pp.encoding == encoding_egpr)
2084
0
  || i.mask.reg;
2085
0
}
2086
2087
0
#define CPU_FLAGS_ARCH_MATCH    0x1
2088
0
#define CPU_FLAGS_64BIT_MATCH   0x2
2089
2090
#define CPU_FLAGS_PERFECT_MATCH \
2091
0
  (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
2092
2093
static INLINE bool set_oszc_flags (unsigned int oszc_shift)
2094
0
{
2095
0
  if (i.oszc_flags & oszc_shift)
2096
0
    {
2097
0
      as_bad (_("same oszc flag used twice"));
2098
0
      return false;
2099
0
    }
2100
0
  i.oszc_flags |= oszc_shift;
2101
0
  return true;
2102
0
}
2103
2104
/* Handle SCC OSZC flags.  */
2105
2106
static int
2107
check_Scc_OszcOperations (const char *l)
2108
0
{
2109
0
  const char *suffix_string = l;
2110
2111
0
  while (is_whitespace (*suffix_string))
2112
0
    suffix_string++;
2113
2114
  /* If {oszc flags} is absent, just return.  */
2115
0
  if (*suffix_string != '{')
2116
0
    return 0;
2117
2118
  /* Skip '{'.  */
2119
0
  suffix_string++;
2120
2121
  /* For .insn require 'scc=' as the first element.  */
2122
0
  if (dot_insn ())
2123
0
    {
2124
0
      char *copy;
2125
0
      valueT val;
2126
2127
0
      while (is_whitespace (*suffix_string))
2128
0
  suffix_string++;
2129
2130
0
      if (strncasecmp (suffix_string, "scc", 3) == 0)
2131
0
  suffix_string += 3;
2132
0
      else
2133
0
  {
2134
0
    as_bad (_("unrecognized pseudo-suffix"));
2135
0
    return -1;
2136
0
  }
2137
2138
0
      while (is_whitespace (*suffix_string))
2139
0
  suffix_string++;
2140
2141
0
      if (*suffix_string == '=')
2142
0
  suffix_string++;
2143
0
      else
2144
0
  {
2145
0
    as_bad (_("unrecognized pseudo-suffix"));
2146
0
    return -1;
2147
0
  }
2148
2149
0
      copy = xstrdup (suffix_string);
2150
      /* No need to save/restore input_line_pointer; that's done in the
2151
   caller already.  */
2152
0
      input_line_pointer = copy;
2153
0
      val = get_absolute_expression ();
2154
0
      suffix_string += input_line_pointer - copy;
2155
0
      free (copy);
2156
2157
0
      if (val > 0xf)
2158
0
  {
2159
0
    as_bad (_("scc= value must be between 0 and 15 (decimal)"));
2160
0
    return -1;
2161
0
  }
2162
2163
0
      i.scc = val;
2164
2165
      /* Permit dfv= to be absent (implying all flag values being zero).  */
2166
0
      if (*suffix_string == '}')
2167
0
  return suffix_string + 1 - l;
2168
2169
0
      if (*suffix_string != ',')
2170
0
  goto bad;
2171
0
      suffix_string++;
2172
0
    }
2173
2174
  /* Parse 'dfv='.  */
2175
0
  while (is_whitespace (*suffix_string))
2176
0
    suffix_string++;
2177
2178
0
  if (strncasecmp (suffix_string, "dfv", 3) == 0)
2179
0
    suffix_string += 3;
2180
0
  else
2181
0
    {
2182
0
      as_bad (_("unrecognized pseudo-suffix"));
2183
0
      return -1;
2184
0
    }
2185
2186
0
  while (is_whitespace (*suffix_string))
2187
0
    suffix_string++;
2188
2189
0
  if (*suffix_string == '=')
2190
0
    suffix_string++;
2191
0
  else
2192
0
    {
2193
0
      as_bad (_("unrecognized pseudo-suffix"));
2194
0
      return -1;
2195
0
    }
2196
2197
  /* Parse 'of, sf, zf, cf}'.  */
2198
0
  while (*suffix_string)
2199
0
    {
2200
0
      while (is_whitespace (*suffix_string))
2201
0
  suffix_string++;
2202
2203
      /* Return for '{dfv=}'.  */
2204
0
      if (*suffix_string == '}')
2205
0
  return suffix_string + 1 - l;
2206
2207
0
      if (strncasecmp (suffix_string, "of", 2) == 0)
2208
0
  {
2209
0
    if (!set_oszc_flags (OSZC_OF))
2210
0
      return -1;
2211
0
  }
2212
0
      else if (strncasecmp (suffix_string, "sf", 2) == 0)
2213
0
  {
2214
0
    if (!set_oszc_flags (OSZC_SF))
2215
0
      return -1;
2216
0
  }
2217
0
      else if (strncasecmp (suffix_string, "zf", 2) == 0)
2218
0
  {
2219
0
    if (!set_oszc_flags (OSZC_ZF))
2220
0
      return -1;
2221
0
  }
2222
0
      else if (strncasecmp (suffix_string, "cf", 2) == 0)
2223
0
  {
2224
0
    if (!set_oszc_flags (OSZC_CF))
2225
0
      return -1;
2226
0
  }
2227
0
      else
2228
0
  {
2229
0
    as_bad (_("unrecognized oszc flags or illegal `,' in pseudo-suffix"));
2230
0
    return -1;
2231
0
  }
2232
2233
0
      suffix_string += 2;
2234
2235
0
      while (is_whitespace (*suffix_string))
2236
0
  suffix_string++;
2237
2238
0
      if (*suffix_string == '}')
2239
0
  return ++suffix_string - l;
2240
2241
0
      if (*suffix_string != ',')
2242
0
  break;
2243
0
      suffix_string ++;
2244
0
    }
2245
2246
0
 bad:
2247
0
  as_bad (_("missing `}' or `,' in pseudo-suffix"));
2248
0
  return -1;
2249
0
}
2250
2251
/* Return CPU flags match bits. */
2252
2253
static int
2254
cpu_flags_match (const insn_template *t)
2255
0
{
2256
0
  i386_cpu_flags cpu, active, all = cpu_flags_from_attr (t->cpu);
2257
0
  i386_cpu_flags any = cpu_flags_from_attr (t->cpu_any);
2258
0
  int match = cpu_flags_check_cpu64 (t) ? CPU_FLAGS_64BIT_MATCH : 0;
2259
2260
0
  all.bitfield.cpu64 = 0;
2261
0
  all.bitfield.cpuno64 = 0;
2262
0
  gas_assert (!any.bitfield.cpu64);
2263
0
  gas_assert (!any.bitfield.cpuno64);
2264
2265
0
  if (cpu_flags_all_zero (&all) && cpu_flags_all_zero (&any))
2266
0
    {
2267
      /* This instruction is available on all archs.  */
2268
0
      return match | CPU_FLAGS_ARCH_MATCH;
2269
0
    }
2270
2271
  /* This instruction is available only on some archs.  */
2272
2273
  /* Dual VEX/EVEX templates may need stripping of one of the flags.  */
2274
0
  if (t->opcode_modifier.vex && t->opcode_modifier.evex)
2275
0
    {
2276
      /* Dual AVX/AVX512 templates need to retain AVX512* only if we already
2277
   know that EVEX encoding will be needed.  */
2278
0
      if ((any.bitfield.cpuavx || any.bitfield.cpuavx2 || any.bitfield.cpufma)
2279
0
    && (any.bitfield.cpuavx512f || any.bitfield.cpuavx512vl))
2280
0
  {
2281
0
    if (need_evex_encoding (t))
2282
0
      {
2283
0
        any.bitfield.cpuavx = 0;
2284
0
        any.bitfield.cpuavx2 = 0;
2285
0
        any.bitfield.cpufma = 0;
2286
0
      }
2287
    /* need_evex_encoding(t) isn't reliable before operands were
2288
       parsed.  */
2289
0
    else if (i.operands)
2290
0
      {
2291
0
        any.bitfield.cpuavx512f = 0;
2292
0
        any.bitfield.cpuavx512vl = 0;
2293
0
      }
2294
0
  }
2295
2296
      /* Dual non-APX/APX templates need massaging from what APX_F() in the
2297
         opcode table has produced.  While the direct transformation of the
2298
         incoming cpuid&(cpuid|APX_F) would be to cpuid&(cpuid) / cpuid&(APX_F)
2299
         respectively, it's cheaper to move to just cpuid / cpuid&APX_F
2300
         instead.  */
2301
0
      if (any.bitfield.cpuapx_f
2302
0
    && (any.bitfield.cpubmi || any.bitfield.cpubmi2
2303
0
        || any.bitfield.cpuavx512f || any.bitfield.cpuavx512bw
2304
0
        || any.bitfield.cpuavx512dq || any.bitfield.cpuamx_tile
2305
0
        || any.bitfield.cpucmpccxadd || any.bitfield.cpuuser_msr
2306
0
        || any.bitfield.cpumsr_imm || any.bitfield.cpuamx_transpose
2307
0
        || any.bitfield.cpuamx_movrs))
2308
0
  {
2309
    /* These checks (verifying that APX_F() was properly used in the
2310
       opcode table entry) make sure there's no need for an "else" to
2311
       the "if()" below.  */
2312
0
    gas_assert (!cpu_flags_all_zero (&all));
2313
2314
0
    cpu = cpu_flags_and (all, any);
2315
0
    gas_assert (cpu_flags_equal (&cpu, &all));
2316
2317
0
    if (need_evex_encoding (t))
2318
0
      all = any;
2319
2320
0
    memset (&any, 0, sizeof (any));
2321
0
  }
2322
0
    }
2323
2324
0
  if (flag_code != CODE_64BIT)
2325
0
    active = cpu_flags_and_not (cpu_arch_flags, cpu_64_flags);
2326
0
  else
2327
0
    active = cpu_arch_flags;
2328
0
  cpu = cpu_flags_and (all, active);
2329
0
  if (cpu_flags_equal (&cpu, &all))
2330
0
    {
2331
      /* AVX and AVX2 present at the same time express an operand size
2332
   dependency - strip AVX2 for the purposes here.  The operand size
2333
   dependent check occurs in check_vecOperands().  */
2334
0
      if (any.bitfield.cpuavx && any.bitfield.cpuavx2)
2335
0
  any.bitfield.cpuavx2 = 0;
2336
2337
0
      cpu = cpu_flags_and (any, active);
2338
0
      if (cpu_flags_all_zero (&any) || !cpu_flags_all_zero (&cpu))
2339
0
  match |= CPU_FLAGS_ARCH_MATCH;
2340
0
    }
2341
0
  return match;
2342
0
}
2343
2344
static INLINE i386_operand_type
2345
operand_type_and (i386_operand_type x, i386_operand_type y)
2346
0
{
2347
0
  if (x.bitfield.class != y.bitfield.class)
2348
0
    x.bitfield.class = ClassNone;
2349
0
  if (x.bitfield.instance != y.bitfield.instance)
2350
0
    x.bitfield.instance = InstanceNone;
2351
2352
0
  switch (ARRAY_SIZE (x.array))
2353
0
    {
2354
0
    case 3:
2355
0
      x.array [2] &= y.array [2];
2356
      /* Fall through.  */
2357
0
    case 2:
2358
0
      x.array [1] &= y.array [1];
2359
      /* Fall through.  */
2360
0
    case 1:
2361
0
      x.array [0] &= y.array [0];
2362
0
      break;
2363
0
    default:
2364
0
      abort ();
2365
0
    }
2366
0
  return x;
2367
0
}
2368
2369
static INLINE i386_operand_type
2370
operand_type_and_not (i386_operand_type x, i386_operand_type y)
2371
0
{
2372
0
  gas_assert (y.bitfield.class == ClassNone);
2373
0
  gas_assert (y.bitfield.instance == InstanceNone);
2374
2375
0
  switch (ARRAY_SIZE (x.array))
2376
0
    {
2377
0
    case 3:
2378
0
      x.array [2] &= ~y.array [2];
2379
      /* Fall through.  */
2380
0
    case 2:
2381
0
      x.array [1] &= ~y.array [1];
2382
      /* Fall through.  */
2383
0
    case 1:
2384
0
      x.array [0] &= ~y.array [0];
2385
0
      break;
2386
0
    default:
2387
0
      abort ();
2388
0
    }
2389
0
  return x;
2390
0
}
2391
2392
static INLINE i386_operand_type
2393
operand_type_or (i386_operand_type x, i386_operand_type y)
2394
0
{
2395
0
  gas_assert (x.bitfield.class == ClassNone ||
2396
0
              y.bitfield.class == ClassNone ||
2397
0
              x.bitfield.class == y.bitfield.class);
2398
0
  gas_assert (x.bitfield.instance == InstanceNone ||
2399
0
              y.bitfield.instance == InstanceNone ||
2400
0
              x.bitfield.instance == y.bitfield.instance);
2401
2402
0
  switch (ARRAY_SIZE (x.array))
2403
0
    {
2404
0
    case 3:
2405
0
      x.array [2] |= y.array [2];
2406
      /* Fall through.  */
2407
0
    case 2:
2408
0
      x.array [1] |= y.array [1];
2409
      /* Fall through.  */
2410
0
    case 1:
2411
0
      x.array [0] |= y.array [0];
2412
0
      break;
2413
0
    default:
2414
0
      abort ();
2415
0
    }
2416
0
  return x;
2417
0
}
2418
2419
static INLINE i386_operand_type
2420
operand_type_xor (i386_operand_type x, i386_operand_type y)
2421
0
{
2422
0
  gas_assert (y.bitfield.class == ClassNone);
2423
0
  gas_assert (y.bitfield.instance == InstanceNone);
2424
2425
0
  switch (ARRAY_SIZE (x.array))
2426
0
    {
2427
0
    case 3:
2428
0
      x.array [2] ^= y.array [2];
2429
      /* Fall through.  */
2430
0
    case 2:
2431
0
      x.array [1] ^= y.array [1];
2432
      /* Fall through.  */
2433
0
    case 1:
2434
0
      x.array [0] ^= y.array [0];
2435
0
      break;
2436
0
    default:
2437
0
      abort ();
2438
0
    }
2439
0
  return x;
2440
0
}
2441
2442
static const i386_operand_type anydisp = {
2443
  .bitfield = { .disp8 = 1, .disp16 = 1, .disp32 = 1, .disp64 = 1 }
2444
};
2445
2446
enum operand_type
2447
{
2448
  reg,
2449
  imm,
2450
  disp,
2451
  anymem
2452
};
2453
2454
static INLINE int
2455
operand_type_check (i386_operand_type t, enum operand_type c)
2456
0
{
2457
0
  switch (c)
2458
0
    {
2459
0
    case reg:
2460
0
      return t.bitfield.class == Reg;
2461
2462
0
    case imm:
2463
0
      return (t.bitfield.imm8
2464
0
        || t.bitfield.imm8s
2465
0
        || t.bitfield.imm16
2466
0
        || t.bitfield.imm32
2467
0
        || t.bitfield.imm32s
2468
0
        || t.bitfield.imm64);
2469
2470
0
    case disp:
2471
0
      return (t.bitfield.disp8
2472
0
        || t.bitfield.disp16
2473
0
        || t.bitfield.disp32
2474
0
        || t.bitfield.disp64);
2475
2476
0
    case anymem:
2477
0
      return (t.bitfield.disp8
2478
0
        || t.bitfield.disp16
2479
0
        || t.bitfield.disp32
2480
0
        || t.bitfield.disp64
2481
0
        || t.bitfield.baseindex);
2482
2483
0
    default:
2484
0
      abort ();
2485
0
    }
2486
2487
0
  return 0;
2488
0
}
2489
2490
/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit size
2491
   between operand GIVEN and operand WANTED for instruction template T.  */
2492
2493
static INLINE int
2494
match_operand_size (const insn_template *t, unsigned int wanted,
2495
        unsigned int given)
2496
0
{
2497
0
  return !((i.types[given].bitfield.byte
2498
0
      && !t->operand_types[wanted].bitfield.byte)
2499
0
     || (i.types[given].bitfield.word
2500
0
         && !t->operand_types[wanted].bitfield.word)
2501
0
     || (i.types[given].bitfield.dword
2502
0
         && !t->operand_types[wanted].bitfield.dword)
2503
0
     || (i.types[given].bitfield.qword
2504
0
         && (!t->operand_types[wanted].bitfield.qword
2505
       /* Don't allow 64-bit (memory) operands outside of 64-bit
2506
          mode, when they're used where a 64-bit GPR could also
2507
          be used.  Checking is needed for Intel Syntax only.  */
2508
0
       || (intel_syntax
2509
0
           && flag_code != CODE_64BIT
2510
0
           && (t->operand_types[wanted].bitfield.class == Reg
2511
0
         || t->opcode_modifier.isstring)))));
2512
0
}
2513
2514
/* Return 1 if there is no conflict in 80bit size
2515
   between operand GIVEN and operand WANTED for instruction template T.  */
2516
2517
static INLINE int
2518
match_fp_size (const insn_template *t, unsigned int wanted,
2519
        unsigned int given)
2520
0
{
2521
0
  return !i.types[given].bitfield.tbyte
2522
0
   || t->operand_types[wanted].bitfield.tbyte;
2523
0
}
2524
2525
/* Return 1 if there is no conflict in SIMD register between operand
2526
   GIVEN and operand WANTED for instruction template T.  */
2527
2528
static INLINE int
2529
match_simd_size (const insn_template *t, unsigned int wanted,
2530
     unsigned int given)
2531
0
{
2532
0
  return !((i.types[given].bitfield.xmmword
2533
0
      && !t->operand_types[wanted].bitfield.xmmword)
2534
0
     || (i.types[given].bitfield.ymmword
2535
0
         && !t->operand_types[wanted].bitfield.ymmword)
2536
0
     || (i.types[given].bitfield.zmmword
2537
0
         && !t->operand_types[wanted].bitfield.zmmword)
2538
0
     || (i.types[given].bitfield.tmmword
2539
0
         && !t->operand_types[wanted].bitfield.tmmword));
2540
0
}
2541
2542
/* Return 1 if there is no conflict in any size between operand GIVEN
2543
   and operand WANTED for instruction template T.  */
2544
2545
static INLINE int
2546
match_mem_size (const insn_template *t, unsigned int wanted,
2547
    unsigned int given)
2548
0
{
2549
0
  return (match_operand_size (t, wanted, given)
2550
0
    && (!i.types[given].bitfield.tbyte
2551
0
        || t->operand_types[wanted].bitfield.tbyte)
2552
0
    && !((i.types[given].bitfield.unspecified
2553
0
    && !i.broadcast.type
2554
0
    && !i.broadcast.bytes
2555
0
    && !t->operand_types[wanted].bitfield.unspecified)
2556
0
         || (i.types[given].bitfield.fword
2557
0
       && !t->operand_types[wanted].bitfield.fword)
2558
         /* For scalar opcode templates to allow register and memory
2559
      operands at the same time, some special casing is needed
2560
      here.  Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
2561
      down-conversion vpmov*.  */
2562
0
         || ((t->operand_types[wanted].bitfield.class == RegSIMD
2563
0
        && t->operand_types[wanted].bitfield.byte
2564
0
           + t->operand_types[wanted].bitfield.word
2565
0
           + t->operand_types[wanted].bitfield.dword
2566
0
           + t->operand_types[wanted].bitfield.qword
2567
0
           > !!t->opcode_modifier.broadcast)
2568
0
       ? (i.types[given].bitfield.xmmword
2569
0
          || i.types[given].bitfield.ymmword
2570
0
          || i.types[given].bitfield.zmmword)
2571
0
       : !match_simd_size(t, wanted, given))));
2572
0
}
2573
2574
/* Return value has MATCH_STRAIGHT set if there is no size conflict on any
2575
   operands for instruction template T, and it has MATCH_REVERSE set if there
2576
   is no size conflict on any operands for the template with operands reversed
2577
   (and the template allows for reversing in the first place).  */
2578
2579
0
#define MATCH_STRAIGHT 1
2580
0
#define MATCH_REVERSE  2
2581
2582
static INLINE unsigned int
2583
operand_size_match (const insn_template *t)
2584
0
{
2585
0
  unsigned int j, match = MATCH_STRAIGHT;
2586
2587
  /* Don't check non-absolute jump instructions.  */
2588
0
  if (t->opcode_modifier.jump
2589
0
      && t->opcode_modifier.jump != JUMP_ABSOLUTE)
2590
0
    return match;
2591
2592
0
  for (j = 0; j < i.imm_operands; j++)
2593
    /* Instruction templates with only sign-extended 8-bit immediate
2594
       operand also have a second template with full-operand-size
2595
       immediate operand under a different opcode.  Don't match the
2596
       first template if sign-extended 8-bit immediate operand should
2597
       be excluded.  */
2598
0
    if (pp.no_imm8s
2599
0
        && !t->operand_types[j].bitfield.imm8
2600
0
        && t->operand_types[j].bitfield.imm8s)
2601
0
      {
2602
0
  gas_assert (!t->opcode_modifier.d);
2603
0
  return 0;
2604
0
      }
2605
2606
  /* Check memory and accumulator operand size.  */
2607
0
  for (; j < i.operands; j++)
2608
0
    {
2609
0
      if (i.types[j].bitfield.class == Reg
2610
0
    && (t->operand_types[j].bitfield.class == Reg
2611
0
        || (t->operand_types[j].bitfield.instance == Accum
2612
0
      && (t->operand_types[j].bitfield.byte
2613
0
          || t->operand_types[j].bitfield.word
2614
0
          || t->operand_types[j].bitfield.dword
2615
0
          || t->operand_types[j].bitfield.qword)))
2616
0
    && !match_operand_size (t, j, j))
2617
0
  {
2618
0
    match = 0;
2619
0
    break;
2620
0
  }
2621
2622
0
      if (i.types[j].bitfield.class == RegFP
2623
0
    && (t->operand_types[j].bitfield.class == RegFP
2624
0
        || (t->operand_types[j].bitfield.instance == Accum
2625
0
      && t->operand_types[j].bitfield.tbyte))
2626
0
    && !match_fp_size (t, j, j))
2627
0
  {
2628
0
    match = 0;
2629
0
    break;
2630
0
  }
2631
2632
0
      if (i.types[j].bitfield.class == RegSIMD
2633
0
    && (t->operand_types[j].bitfield.class == RegSIMD
2634
0
        || (t->operand_types[j].bitfield.instance == Accum
2635
      /* Note: %ymm0, %zmm0, and %tmm0 aren't marked Accum.  */
2636
0
      && t->operand_types[j].bitfield.xmmword))
2637
0
    && !match_simd_size (t, j, j))
2638
0
  {
2639
0
    match = 0;
2640
0
    break;
2641
0
  }
2642
2643
0
      if ((i.flags[j] & Operand_Mem)
2644
0
    && operand_type_check (t->operand_types[j], anymem)
2645
0
    && t->opcode_modifier.operandconstraint != ANY_SIZE
2646
0
    && !match_mem_size (t, j, j))
2647
0
  {
2648
0
    match = 0;
2649
0
    break;
2650
0
  }
2651
0
    }
2652
2653
0
  if (!t->opcode_modifier.d)
2654
0
    return match;
2655
2656
  /* Check reverse.  */
2657
0
  gas_assert (i.operands >= 2);
2658
2659
0
  for (j = i.imm_operands; j < i.operands; j++)
2660
0
    {
2661
0
      unsigned int given = i.operands - j - 1;
2662
2663
      /* For FMA4 and XOP insns VEX.W controls just the first two
2664
   register operands. And APX_F insns just swap the two source operands,
2665
   with the 3rd one being the destination.  */
2666
0
      if (is_cpu (t, CpuFMA4) || is_cpu (t, CpuXOP)
2667
0
    || is_cpu (t, CpuAPX_F))
2668
0
  given = j < 2 ? 1 - j : j;
2669
2670
0
      if (i.types[given].bitfield.class == Reg
2671
0
    && (t->operand_types[j].bitfield.class == Reg
2672
0
        || (t->operand_types[j].bitfield.instance == Accum
2673
0
      && (t->operand_types[j].bitfield.byte
2674
0
          || t->operand_types[j].bitfield.word
2675
0
          || t->operand_types[j].bitfield.dword
2676
0
          || t->operand_types[j].bitfield.qword
2677
0
          || t->operand_types[j].bitfield.tbyte)))
2678
0
    && !match_operand_size (t, j, given))
2679
0
  return match;
2680
2681
0
      if (i.types[given].bitfield.class == RegFP
2682
0
    && (t->operand_types[j].bitfield.class == RegFP
2683
0
        || (t->operand_types[j].bitfield.instance == Accum
2684
0
      && t->operand_types[j].bitfield.tbyte))
2685
0
    && !match_fp_size (t, j, given))
2686
0
  return match;
2687
2688
      /* No need to check for Accum here: There are no such templates with D
2689
   set.  */
2690
0
      if (i.types[given].bitfield.class == RegSIMD
2691
0
    && t->operand_types[j].bitfield.class == RegSIMD
2692
0
    && !match_simd_size (t, j, given))
2693
0
  return match;
2694
2695
0
      if ((i.flags[given] & Operand_Mem)
2696
0
    && operand_type_check (t->operand_types[j], anymem)
2697
0
    && !match_mem_size (t, j, given))
2698
0
  return match;
2699
0
    }
2700
2701
0
  return match | MATCH_REVERSE;
2702
0
}
2703
2704
static INLINE int
2705
operand_type_match (i386_operand_type overlap,
2706
        i386_operand_type given)
2707
0
{
2708
0
  i386_operand_type temp = overlap;
2709
2710
0
  temp.bitfield.unspecified = 0;
2711
0
  temp.bitfield.byte = 0;
2712
0
  temp.bitfield.word = 0;
2713
0
  temp.bitfield.dword = 0;
2714
0
  temp.bitfield.fword = 0;
2715
0
  temp.bitfield.qword = 0;
2716
0
  temp.bitfield.tbyte = 0;
2717
0
  temp.bitfield.xmmword = 0;
2718
0
  temp.bitfield.ymmword = 0;
2719
0
  temp.bitfield.zmmword = 0;
2720
0
  temp.bitfield.tmmword = 0;
2721
0
  if (operand_type_all_zero (&temp))
2722
0
    goto mismatch;
2723
2724
  /* When a (register) instance is expected, operand size needs checking
2725
     to disambiguate.  */
2726
0
  if (overlap.bitfield.instance != InstanceNone
2727
0
      && !overlap.bitfield.byte
2728
0
      && !overlap.bitfield.word
2729
0
      && !overlap.bitfield.dword
2730
0
      && !overlap.bitfield.qword
2731
0
      && !overlap.bitfield.tbyte
2732
0
      && !overlap.bitfield.xmmword
2733
0
      && !overlap.bitfield.ymmword
2734
0
      && !overlap.bitfield.zmmword
2735
0
      && !overlap.bitfield.tmmword)
2736
0
    {
2737
0
      gas_assert (overlap.bitfield.class == ClassNone);
2738
0
      goto mismatch;
2739
0
    }
2740
2741
0
  if (given.bitfield.baseindex == overlap.bitfield.baseindex)
2742
0
    return 1;
2743
2744
0
 mismatch:
2745
0
  i.error = operand_type_mismatch;
2746
0
  return 0;
2747
0
}
2748
2749
/* If given types g0 and g1 are registers they must be of the same type
2750
   unless the expected operand type register overlap is null.
2751
   Intel syntax sized memory operands are also checked here.  */
2752
2753
static INLINE int
2754
operand_type_register_match (i386_operand_type g0,
2755
           i386_operand_type t0,
2756
           i386_operand_type g1,
2757
           i386_operand_type t1)
2758
0
{
2759
0
  if (g0.bitfield.class != Reg
2760
0
      && g0.bitfield.class != RegSIMD
2761
0
      && (g0.bitfield.unspecified
2762
0
    || !operand_type_check (g0, anymem)))
2763
0
    return 1;
2764
2765
0
  if (g1.bitfield.class != Reg
2766
0
      && g1.bitfield.class != RegSIMD
2767
0
      && (g1.bitfield.unspecified
2768
0
    || !operand_type_check (g1, anymem)))
2769
0
    return 1;
2770
2771
0
  if (g0.bitfield.byte == g1.bitfield.byte
2772
0
      && g0.bitfield.word == g1.bitfield.word
2773
0
      && g0.bitfield.dword == g1.bitfield.dword
2774
0
      && g0.bitfield.qword == g1.bitfield.qword
2775
0
      && g0.bitfield.xmmword == g1.bitfield.xmmword
2776
0
      && g0.bitfield.ymmword == g1.bitfield.ymmword
2777
0
      && g0.bitfield.zmmword == g1.bitfield.zmmword)
2778
0
    return 1;
2779
2780
  /* If expectations overlap in no more than a single size, all is fine. */
2781
0
  g0 = operand_type_and (t0, t1);
2782
0
  if (g0.bitfield.byte
2783
0
      + g0.bitfield.word
2784
0
      + g0.bitfield.dword
2785
0
      + g0.bitfield.qword
2786
0
      + g0.bitfield.xmmword
2787
0
      + g0.bitfield.ymmword
2788
0
      + g0.bitfield.zmmword <= 1)
2789
0
    return 1;
2790
2791
0
  i.error = register_type_mismatch;
2792
2793
0
  return 0;
2794
0
}
2795
2796
static INLINE unsigned int
2797
register_number (const reg_entry *r)
2798
0
{
2799
0
  unsigned int nr = r->reg_num;
2800
2801
0
  if (r->reg_flags & RegRex)
2802
0
    nr += 8;
2803
2804
0
  if (r->reg_flags & (RegVRex | RegRex2))
2805
0
    nr += 16;
2806
2807
0
  return nr;
2808
0
}
2809
2810
static INLINE unsigned int
2811
mode_from_disp_size (i386_operand_type t)
2812
0
{
2813
0
  if (t.bitfield.disp8)
2814
0
    return 1;
2815
0
  else if (t.bitfield.disp16
2816
0
     || t.bitfield.disp32)
2817
0
    return 2;
2818
0
  else
2819
0
    return 0;
2820
0
}
2821
2822
static INLINE int
2823
fits_in_signed_byte (addressT num)
2824
0
{
2825
0
  return num + 0x80 <= 0xff;
2826
0
}
2827
2828
static INLINE int
2829
fits_in_unsigned_byte (addressT num)
2830
0
{
2831
0
  return num <= 0xff;
2832
0
}
2833
2834
static INLINE int
2835
fits_in_unsigned_word (addressT num)
2836
0
{
2837
0
  return num <= 0xffff;
2838
0
}
2839
2840
static INLINE int
2841
fits_in_signed_word (addressT num)
2842
0
{
2843
0
  return num + 0x8000 <= 0xffff;
2844
0
}
2845
2846
static INLINE int
2847
fits_in_signed_long (addressT num ATTRIBUTE_UNUSED)
2848
0
{
2849
#ifndef BFD64
2850
  return 1;
2851
#else
2852
0
  return num + 0x80000000 <= 0xffffffff;
2853
0
#endif
2854
0
}        /* fits_in_signed_long() */
2855
2856
static INLINE int
2857
fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED)
2858
0
{
2859
#ifndef BFD64
2860
  return 1;
2861
#else
2862
0
  return num <= 0xffffffff;
2863
0
#endif
2864
0
}        /* fits_in_unsigned_long() */
2865
2866
static INLINE valueT extend_to_32bit_address (addressT num)
2867
0
{
2868
0
#ifdef BFD64
2869
0
  if (fits_in_unsigned_long(num))
2870
0
    return (num ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
2871
2872
0
  if (!fits_in_signed_long (num))
2873
0
    return num & 0xffffffff;
2874
0
#endif
2875
2876
0
  return num;
2877
0
}
2878
2879
static INLINE int
2880
fits_in_disp8 (offsetT num)
2881
0
{
2882
0
  int shift = i.memshift;
2883
0
  unsigned int mask;
2884
2885
0
  if (shift == -1)
2886
0
    abort ();
2887
2888
0
  mask = (1 << shift) - 1;
2889
2890
  /* Return 0 if NUM isn't properly aligned.  */
2891
0
  if ((num & mask))
2892
0
    return 0;
2893
2894
  /* Check if NUM will fit in 8bit after shift.  */
2895
0
  return fits_in_signed_byte (num >> shift);
2896
0
}
2897
2898
static INLINE int
2899
fits_in_imm4 (offsetT num)
2900
0
{
2901
  /* Despite the name, check for imm3 if we're dealing with EVEX.  */
2902
0
  return (num & (pp.encoding != encoding_evex
2903
0
     && pp.encoding != encoding_egpr ? 0xf : 7)) == num;
2904
0
}
2905
2906
static i386_operand_type
2907
smallest_imm_type (offsetT num)
2908
0
{
2909
0
  i386_operand_type t;
2910
2911
0
  operand_type_set (&t, 0);
2912
0
  t.bitfield.imm64 = 1;
2913
2914
0
  if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
2915
0
    {
2916
      /* This code is disabled on the 486 because all the Imm1 forms
2917
   in the opcode table are slower on the i486.  They're the
2918
   versions with the implicitly specified single-position
2919
   displacement, which has another syntax if you really want to
2920
   use that form.  */
2921
0
      t.bitfield.imm1 = 1;
2922
0
      t.bitfield.imm8 = 1;
2923
0
      t.bitfield.imm8s = 1;
2924
0
      t.bitfield.imm16 = 1;
2925
0
      t.bitfield.imm32 = 1;
2926
0
      t.bitfield.imm32s = 1;
2927
0
    }
2928
0
  else if (fits_in_signed_byte (num))
2929
0
    {
2930
0
      if (fits_in_unsigned_byte (num))
2931
0
  t.bitfield.imm8 = 1;
2932
0
      t.bitfield.imm8s = 1;
2933
0
      t.bitfield.imm16 = 1;
2934
0
      if (flag_code != CODE_64BIT || fits_in_unsigned_long (num))
2935
0
  t.bitfield.imm32 = 1;
2936
0
      t.bitfield.imm32s = 1;
2937
0
    }
2938
0
  else if (fits_in_unsigned_byte (num))
2939
0
    {
2940
0
      t.bitfield.imm8 = 1;
2941
0
      t.bitfield.imm16 = 1;
2942
0
      t.bitfield.imm32 = 1;
2943
0
      t.bitfield.imm32s = 1;
2944
0
    }
2945
0
  else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
2946
0
    {
2947
0
      t.bitfield.imm16 = 1;
2948
0
      if (flag_code != CODE_64BIT || fits_in_unsigned_long (num))
2949
0
  t.bitfield.imm32 = 1;
2950
0
      t.bitfield.imm32s = 1;
2951
0
    }
2952
0
  else if (fits_in_signed_long (num))
2953
0
    {
2954
0
      if (flag_code != CODE_64BIT || fits_in_unsigned_long (num))
2955
0
  t.bitfield.imm32 = 1;
2956
0
      t.bitfield.imm32s = 1;
2957
0
    }
2958
0
  else if (fits_in_unsigned_long (num))
2959
0
    t.bitfield.imm32 = 1;
2960
2961
0
  return t;
2962
0
}
2963
2964
static offsetT
2965
offset_in_range (offsetT val, int size)
2966
0
{
2967
0
  addressT mask;
2968
2969
0
  switch (size)
2970
0
    {
2971
0
    case 1: mask = ((addressT) 1 <<  8) - 1; break;
2972
0
    case 2: mask = ((addressT) 1 << 16) - 1; break;
2973
0
#ifdef BFD64
2974
0
    case 4: mask = ((addressT) 1 << 32) - 1; break;
2975
0
#endif
2976
0
    case sizeof (val): return val;
2977
0
    default: abort ();
2978
0
    }
2979
2980
0
  if ((val & ~mask) != 0 && (-(addressT) val & ~mask) != 0)
2981
0
    as_warn (_("0x%" PRIx64 " shortened to 0x%" PRIx64),
2982
0
       (uint64_t) val, (uint64_t) (val & mask));
2983
2984
0
  return val & mask;
2985
0
}
2986
2987
static INLINE const char *insn_name (const insn_template *t)
2988
0
{
2989
0
  return &i386_mnemonics[t->mnem_off];
2990
0
}
2991
2992
enum PREFIX_GROUP
2993
{
2994
  PREFIX_EXIST = 0,
2995
  PREFIX_LOCK,
2996
  PREFIX_REP,
2997
  PREFIX_DS,
2998
  PREFIX_OTHER
2999
};
3000
3001
/* Returns
3002
   a. PREFIX_EXIST if attempting to add a prefix where one from the
3003
   same class already exists.
3004
   b. PREFIX_LOCK if lock prefix is added.
3005
   c. PREFIX_REP if rep/repne prefix is added.
3006
   d. PREFIX_DS if ds prefix is added.
3007
   e. PREFIX_OTHER if other prefix is added.
3008
 */
3009
3010
static enum PREFIX_GROUP
3011
add_prefix (unsigned int prefix)
3012
0
{
3013
0
  enum PREFIX_GROUP ret = PREFIX_OTHER;
3014
0
  unsigned int q;
3015
3016
0
  if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
3017
0
      && flag_code == CODE_64BIT)
3018
0
    {
3019
0
      if ((i.prefix[REX_PREFIX] & prefix & REX_W)
3020
0
    || (i.prefix[REX_PREFIX] & prefix & REX_R)
3021
0
    || (i.prefix[REX_PREFIX] & prefix & REX_X)
3022
0
    || (i.prefix[REX_PREFIX] & prefix & REX_B))
3023
0
  ret = PREFIX_EXIST;
3024
0
      q = REX_PREFIX;
3025
0
    }
3026
0
  else
3027
0
    {
3028
0
      switch (prefix)
3029
0
  {
3030
0
  default:
3031
0
    abort ();
3032
3033
0
  case DS_PREFIX_OPCODE:
3034
0
    ret = PREFIX_DS;
3035
    /* Fall through.  */
3036
0
  case CS_PREFIX_OPCODE:
3037
0
  case ES_PREFIX_OPCODE:
3038
0
  case FS_PREFIX_OPCODE:
3039
0
  case GS_PREFIX_OPCODE:
3040
0
  case SS_PREFIX_OPCODE:
3041
0
    q = SEG_PREFIX;
3042
0
    break;
3043
3044
0
  case REPNE_PREFIX_OPCODE:
3045
0
  case REPE_PREFIX_OPCODE:
3046
0
    q = REP_PREFIX;
3047
0
    ret = PREFIX_REP;
3048
0
    break;
3049
3050
0
  case LOCK_PREFIX_OPCODE:
3051
0
    q = LOCK_PREFIX;
3052
0
    ret = PREFIX_LOCK;
3053
0
    break;
3054
3055
0
  case FWAIT_OPCODE:
3056
0
    q = WAIT_PREFIX;
3057
0
    break;
3058
3059
0
  case ADDR_PREFIX_OPCODE:
3060
0
    q = ADDR_PREFIX;
3061
0
    break;
3062
3063
0
  case DATA_PREFIX_OPCODE:
3064
0
    q = DATA_PREFIX;
3065
0
    break;
3066
0
  }
3067
0
      if (i.prefix[q] != 0)
3068
0
  ret = PREFIX_EXIST;
3069
0
    }
3070
3071
0
  if (ret)
3072
0
    {
3073
0
      if (!i.prefix[q])
3074
0
  ++i.prefixes;
3075
0
      i.prefix[q] |= prefix;
3076
0
    }
3077
0
  else
3078
0
    as_bad (_("same type of prefix used twice"));
3079
3080
0
  return ret;
3081
0
}
3082
3083
static void
3084
update_code_flag (int value, int check)
3085
0
{
3086
0
  PRINTF_LIKE ((*as_error)) = check ? as_fatal : as_bad;
3087
3088
0
  if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpu64 )
3089
0
    {
3090
0
      as_error (_("64bit mode not supported on `%s'."),
3091
0
    cpu_arch_name ? cpu_arch_name : default_arch);
3092
0
      return;
3093
0
    }
3094
3095
0
  if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3096
0
    {
3097
0
      as_error (_("32bit mode not supported on `%s'."),
3098
0
    cpu_arch_name ? cpu_arch_name : default_arch);
3099
0
      return;
3100
0
    }
3101
3102
0
  flag_code = (enum flag_code) value;
3103
3104
0
  stackop_size = '\0';
3105
0
}
3106
3107
static void
3108
set_code_flag (int value)
3109
0
{
3110
0
  update_code_flag (value, 0);
3111
0
}
3112
3113
static void
3114
set_16bit_gcc_code_flag (int new_code_flag)
3115
0
{
3116
0
  flag_code = (enum flag_code) new_code_flag;
3117
0
  if (flag_code != CODE_16BIT)
3118
0
    abort ();
3119
0
  stackop_size = LONG_MNEM_SUFFIX;
3120
0
}
3121
3122
static void
3123
_set_intel_syntax (int syntax_flag)
3124
0
{
3125
0
  intel_syntax = syntax_flag;
3126
3127
0
  expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
3128
3129
0
  register_prefix = allow_naked_reg ? "" : "%";
3130
0
}
3131
3132
static void
3133
set_intel_syntax (int syntax_flag)
3134
0
{
3135
  /* Find out if register prefixing is specified.  */
3136
0
  int ask_naked_reg = 0;
3137
3138
0
  SKIP_WHITESPACE ();
3139
0
  if (!is_end_of_stmt (*input_line_pointer))
3140
0
    {
3141
0
      char *string;
3142
0
      int e = get_symbol_name (&string);
3143
3144
0
      if (strcmp (string, "prefix") == 0)
3145
0
  ask_naked_reg = 1;
3146
0
      else if (strcmp (string, "noprefix") == 0)
3147
0
  ask_naked_reg = -1;
3148
0
      else
3149
0
  as_bad (_("bad argument to syntax directive."));
3150
0
      (void) restore_line_pointer (e);
3151
0
    }
3152
0
  demand_empty_rest_of_line ();
3153
3154
0
  if (ask_naked_reg == 0)
3155
0
    allow_naked_reg = (syntax_flag
3156
0
           && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
3157
0
  else
3158
0
    allow_naked_reg = (ask_naked_reg < 0);
3159
3160
0
  _set_intel_syntax (syntax_flag);
3161
0
}
3162
3163
static void
3164
set_intel_mnemonic (int mnemonic_flag)
3165
0
{
3166
0
  intel_mnemonic = mnemonic_flag;
3167
0
}
3168
3169
static void
3170
set_allow_index_reg (int flag)
3171
0
{
3172
0
  allow_index_reg = flag;
3173
0
}
3174
3175
static void
3176
set_check (int what)
3177
0
{
3178
0
  enum check_kind *kind;
3179
0
  const char *str;
3180
3181
0
  if (what)
3182
0
    {
3183
0
      kind = &operand_check;
3184
0
      str = "operand";
3185
0
    }
3186
0
  else
3187
0
    {
3188
0
      kind = &sse_check;
3189
0
      str = "sse";
3190
0
    }
3191
3192
0
  SKIP_WHITESPACE ();
3193
3194
0
  if (!is_end_of_stmt (*input_line_pointer))
3195
0
    {
3196
0
      char *string;
3197
0
      int e = get_symbol_name (&string);
3198
3199
0
      if (strcmp (string, "none") == 0)
3200
0
  *kind = check_none;
3201
0
      else if (strcmp (string, "warning") == 0)
3202
0
  *kind = check_warning;
3203
0
      else if (strcmp (string, "error") == 0)
3204
0
  *kind = check_error;
3205
0
      else
3206
0
  as_bad (_("bad argument to %s_check directive."), str);
3207
0
      (void) restore_line_pointer (e);
3208
0
    }
3209
0
  else
3210
0
    as_bad (_("missing argument for %s_check directive"), str);
3211
3212
0
  demand_empty_rest_of_line ();
3213
0
}
3214
3215
static void
3216
check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
3217
         i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
3218
0
{
3219
  /* Intel MCU is only supported on ELF.  */
3220
0
#ifdef OBJ_ELF
3221
0
  static const char *arch;
3222
3223
0
  if (!arch)
3224
0
    {
3225
      /* Use cpu_arch_name if it is set in md_parse_option.  Otherwise
3226
   use default_arch.  */
3227
0
      arch = cpu_arch_name;
3228
0
      if (!arch)
3229
0
  arch = default_arch;
3230
0
    }
3231
3232
  /* If we are targeting Intel MCU, we must enable it.  */
3233
0
  if ((get_elf_backend_data (stdoutput)->elf_machine_code == EM_IAMCU)
3234
0
      == new_flag.bitfield.cpuiamcu)
3235
0
    return;
3236
3237
0
  as_bad (_("`%s' is not supported on `%s'"), name, arch);
3238
0
#endif
3239
0
}
3240
3241
static void
3242
extend_cpu_sub_arch_name (const char *pfx, const char *name)
3243
0
{
3244
0
  if (cpu_sub_arch_name)
3245
0
    cpu_sub_arch_name = reconcat (cpu_sub_arch_name, cpu_sub_arch_name,
3246
0
          pfx, name, (const char *) NULL);
3247
0
  else
3248
0
    cpu_sub_arch_name = concat (pfx, name, (const char *) NULL);
3249
0
}
3250
3251
static void isa_enable (unsigned int idx)
3252
0
{
3253
0
  i386_cpu_flags flags = cpu_flags_or (cpu_arch_flags, cpu_arch[idx].enable);
3254
3255
0
  if (!cpu_flags_equal (&flags, &cpu_arch_flags))
3256
0
    {
3257
0
      extend_cpu_sub_arch_name (".", cpu_arch[idx].name);
3258
0
      cpu_arch_flags = flags;
3259
0
    }
3260
3261
0
  cpu_arch_isa_flags = cpu_flags_or (cpu_arch_isa_flags, cpu_arch[idx].enable);
3262
0
}
3263
3264
static void isa_disable (unsigned int idx)
3265
0
{
3266
0
  i386_cpu_flags flags
3267
0
    = cpu_flags_and_not (cpu_arch_flags, cpu_arch[idx].disable);
3268
3269
0
  if (!cpu_flags_equal (&flags, &cpu_arch_flags))
3270
0
    {
3271
0
      extend_cpu_sub_arch_name (".no", cpu_arch[idx].name);
3272
0
      cpu_arch_flags = flags;
3273
0
    }
3274
3275
0
  cpu_arch_isa_flags
3276
0
    = cpu_flags_and_not (cpu_arch_isa_flags, cpu_arch[idx].disable);
3277
0
}
3278
3279
static void
3280
set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
3281
0
{
3282
0
  typedef struct arch_stack_entry
3283
0
  {
3284
0
    const struct arch_stack_entry *prev;
3285
0
    const char *name;
3286
0
    char *sub_name;
3287
0
    i386_cpu_flags flags;
3288
0
    i386_cpu_flags isa_flags;
3289
0
    enum processor_type isa;
3290
0
    enum flag_code flag_code;
3291
0
    unsigned int vector_size;
3292
0
    char stackop_size;
3293
0
    bool no_cond_jump_promotion;
3294
0
  } arch_stack_entry;
3295
0
  static const arch_stack_entry *arch_stack_top;
3296
0
  char *s;
3297
0
  int e;
3298
0
  const char *string;
3299
0
  unsigned int j = 0;
3300
3301
0
  SKIP_WHITESPACE ();
3302
3303
0
  if (is_end_of_stmt (*input_line_pointer))
3304
0
    {
3305
0
      as_bad (_("missing cpu architecture"));
3306
0
      input_line_pointer++;
3307
0
      return;
3308
0
    }
3309
3310
0
  e = get_symbol_name (&s);
3311
0
  string = s;
3312
3313
0
  if (strcmp (string, "push") == 0)
3314
0
    {
3315
0
      arch_stack_entry *top = XNEW (arch_stack_entry);
3316
3317
0
      top->name = cpu_arch_name;
3318
0
      if (cpu_sub_arch_name)
3319
0
  top->sub_name = xstrdup (cpu_sub_arch_name);
3320
0
      else
3321
0
  top->sub_name = NULL;
3322
0
      top->flags = cpu_arch_flags;
3323
0
      top->isa = cpu_arch_isa;
3324
0
      top->isa_flags = cpu_arch_isa_flags;
3325
0
      top->flag_code = flag_code;
3326
0
      top->vector_size = vector_size;
3327
0
      top->stackop_size = stackop_size;
3328
0
      top->no_cond_jump_promotion = no_cond_jump_promotion;
3329
3330
0
      top->prev = arch_stack_top;
3331
0
      arch_stack_top = top;
3332
3333
0
      (void) restore_line_pointer (e);
3334
0
      demand_empty_rest_of_line ();
3335
0
      return;
3336
0
    }
3337
3338
0
  if (strcmp (string, "pop") == 0)
3339
0
    {
3340
0
      const arch_stack_entry *top = arch_stack_top;
3341
3342
0
      if (!top)
3343
0
  {
3344
0
    as_bad (_(".arch stack is empty"));
3345
0
  restore_bad:
3346
0
    (void) restore_line_pointer (e);
3347
0
    ignore_rest_of_line ();
3348
0
    return;
3349
0
  }
3350
3351
0
      if (top->flag_code != flag_code
3352
0
    || top->stackop_size != stackop_size)
3353
0
  {
3354
0
    static const unsigned int bits[] = {
3355
0
      [CODE_16BIT] = 16,
3356
0
      [CODE_32BIT] = 32,
3357
0
      [CODE_64BIT] = 64,
3358
0
    };
3359
3360
0
    as_bad (_("this `.arch pop' requires `.code%u%s' to be in effect"),
3361
0
      bits[top->flag_code],
3362
0
      top->stackop_size == LONG_MNEM_SUFFIX ? "gcc" : "");
3363
0
    goto restore_bad;
3364
0
  }
3365
3366
0
      arch_stack_top = top->prev;
3367
3368
0
      cpu_arch_name = top->name;
3369
0
      free (cpu_sub_arch_name);
3370
0
      cpu_sub_arch_name = top->sub_name;
3371
0
      cpu_arch_flags = top->flags;
3372
0
      cpu_arch_isa = top->isa;
3373
0
      cpu_arch_isa_flags = top->isa_flags;
3374
0
      vector_size = top->vector_size;
3375
0
      no_cond_jump_promotion = top->no_cond_jump_promotion;
3376
3377
0
      XDELETE (top);
3378
3379
0
      (void) restore_line_pointer (e);
3380
0
      demand_empty_rest_of_line ();
3381
0
      return;
3382
0
    }
3383
3384
0
  if (strcmp (string, "default") == 0)
3385
0
    {
3386
0
      if (strcmp (default_arch, "iamcu") == 0)
3387
0
  string = default_arch;
3388
0
      else
3389
0
  {
3390
0
    static const i386_cpu_flags cpu_unknown_flags = CPU_UNKNOWN_FLAGS;
3391
3392
0
    cpu_arch_name = NULL;
3393
0
    free (cpu_sub_arch_name);
3394
0
    cpu_sub_arch_name = NULL;
3395
0
    cpu_arch_flags = cpu_unknown_flags;
3396
0
    cpu_arch_isa = PROCESSOR_UNKNOWN;
3397
0
    cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].enable;
3398
0
    if (!cpu_arch_tune_set)
3399
0
      cpu_arch_tune = PROCESSOR_UNKNOWN;
3400
3401
0
    vector_size = VSZ_DEFAULT;
3402
3403
0
    j = ARRAY_SIZE (cpu_arch) + 1;
3404
0
  }
3405
0
    }
3406
3407
0
  for (; j < ARRAY_SIZE (cpu_arch); j++)
3408
0
    {
3409
0
      if (strcmp (string + (*string == '.'), cpu_arch[j].name) == 0
3410
0
    && (*string == '.') == (cpu_arch[j].type == PROCESSOR_NONE))
3411
0
  {
3412
0
    if (*string != '.')
3413
0
      {
3414
0
        check_cpu_arch_compatible (string, cpu_arch[j].enable);
3415
3416
0
        if (flag_code == CODE_64BIT && !cpu_arch[j].enable.bitfield.cpu64 )
3417
0
    {
3418
0
      as_bad (_("64bit mode not supported on `%s'."),
3419
0
        cpu_arch[j].name);
3420
0
      goto restore_bad;
3421
0
    }
3422
3423
0
        if (flag_code == CODE_32BIT && !cpu_arch[j].enable.bitfield.cpui386)
3424
0
    {
3425
0
      as_bad (_("32bit mode not supported on `%s'."),
3426
0
        cpu_arch[j].name);
3427
0
      goto restore_bad;
3428
0
    }
3429
3430
0
        cpu_arch_name = cpu_arch[j].name;
3431
0
        free (cpu_sub_arch_name);
3432
0
        cpu_sub_arch_name = NULL;
3433
0
        cpu_arch_flags = cpu_arch[j].enable;
3434
0
        cpu_arch_isa = cpu_arch[j].type;
3435
0
        cpu_arch_isa_flags = cpu_arch[j].enable;
3436
0
        if (!cpu_arch_tune_set)
3437
0
    cpu_arch_tune = cpu_arch_isa;
3438
3439
0
        vector_size = VSZ_DEFAULT;
3440
3441
0
        pre_386_16bit_warned = false;
3442
0
        break;
3443
0
      }
3444
3445
0
    if (cpu_flags_all_zero (&cpu_arch[j].enable))
3446
0
      continue;
3447
3448
0
    isa_enable (j);
3449
3450
0
    (void) restore_line_pointer (e);
3451
3452
0
    switch (cpu_arch[j].vsz)
3453
0
      {
3454
0
      default:
3455
0
        break;
3456
3457
0
      case vsz_set:
3458
#ifdef SVR4_COMMENT_CHARS
3459
        if (*input_line_pointer == ':' || *input_line_pointer == '/')
3460
#else
3461
0
        if (*input_line_pointer == '/')
3462
0
#endif
3463
0
    {
3464
0
      ++input_line_pointer;
3465
0
      switch (get_absolute_expression ())
3466
0
        {
3467
0
        case 512: vector_size = VSZ512; break;
3468
0
        case 256: vector_size = VSZ256; break;
3469
0
        case 128: vector_size = VSZ128; break;
3470
0
        default:
3471
0
          as_bad (_("Unrecognized vector size specifier"));
3472
0
          ignore_rest_of_line ();
3473
0
          return;
3474
0
        }
3475
0
      break;
3476
0
    }
3477
    /* Fall through.  */
3478
0
      case vsz_reset:
3479
0
        vector_size = VSZ_DEFAULT;
3480
0
        break;
3481
0
      }
3482
3483
0
    demand_empty_rest_of_line ();
3484
0
    return;
3485
0
  }
3486
0
    }
3487
3488
0
  if (startswith (string, ".no") && j >= ARRAY_SIZE (cpu_arch))
3489
0
    {
3490
      /* Disable an ISA extension.  */
3491
0
      for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
3492
0
  if (cpu_arch[j].type == PROCESSOR_NONE
3493
0
      && strcmp (string + 3, cpu_arch[j].name) == 0)
3494
0
    {
3495
0
      isa_disable (j);
3496
3497
0
      if (cpu_arch[j].vsz == vsz_set)
3498
0
        vector_size = VSZ_DEFAULT;
3499
3500
0
      (void) restore_line_pointer (e);
3501
0
      demand_empty_rest_of_line ();
3502
0
      return;
3503
0
    }
3504
0
    }
3505
3506
0
  if (j == ARRAY_SIZE (cpu_arch))
3507
0
    {
3508
0
      as_bad (_("no such architecture: `%s'"), string);
3509
0
      goto restore_bad;
3510
0
    }
3511
3512
0
  no_cond_jump_promotion = 0;
3513
0
  if (restore_line_pointer (e) == ','
3514
0
      && !is_end_of_stmt (input_line_pointer[1]))
3515
0
    {
3516
0
      ++input_line_pointer;
3517
0
      e = get_symbol_name (&s);
3518
0
      string = s;
3519
3520
0
      if (strcmp (string, "nojumps") == 0)
3521
0
  no_cond_jump_promotion = 1;
3522
0
      else if (strcmp (string, "jumps") != 0)
3523
0
  {
3524
0
    as_bad (_("no such architecture modifier: `%s'"), string);
3525
0
    goto restore_bad;
3526
0
  }
3527
3528
0
      (void) restore_line_pointer (e);
3529
0
    }
3530
3531
0
  demand_empty_rest_of_line ();
3532
0
}
3533
3534
enum bfd_architecture
3535
i386_arch (void)
3536
0
{
3537
0
  if (cpu_arch_isa == PROCESSOR_IAMCU)
3538
0
    {
3539
0
      if (!IS_ELF || flag_code == CODE_64BIT)
3540
0
  as_fatal (_("Intel MCU is 32bit ELF only"));
3541
0
      return bfd_arch_iamcu;
3542
0
    }
3543
0
  else
3544
0
    return bfd_arch_i386;
3545
0
}
3546
3547
unsigned long
3548
i386_mach (void)
3549
0
{
3550
0
  if (startswith (default_arch, "x86_64"))
3551
0
    {
3552
0
      if (default_arch[6] == '\0')
3553
0
  return bfd_mach_x86_64;
3554
0
      else
3555
0
  return bfd_mach_x64_32;
3556
0
    }
3557
0
  else if (!strcmp (default_arch, "i386")
3558
0
     || !strcmp (default_arch, "iamcu"))
3559
0
    {
3560
0
      if (cpu_arch_isa == PROCESSOR_IAMCU)
3561
0
  {
3562
0
    if (!IS_ELF)
3563
0
      as_fatal (_("Intel MCU is 32bit ELF only"));
3564
0
    return bfd_mach_i386_iamcu;
3565
0
  }
3566
0
      else
3567
0
  return bfd_mach_i386_i386;
3568
0
    }
3569
0
  else
3570
0
    as_fatal (_("unknown architecture"));
3571
0
}
3572

3573
#include "opcodes/i386-tbl.h"
3574
3575
static void
3576
op_lookup (const char *mnemonic)
3577
0
{
3578
0
   i386_op_off_t *pos = str_hash_find (op_hash, mnemonic);
3579
3580
0
   if (pos != NULL)
3581
0
     {
3582
0
       current_templates.start = &i386_optab[pos[0]];
3583
0
       current_templates.end = &i386_optab[pos[1]];
3584
0
     }
3585
0
   else
3586
0
     current_templates.end = current_templates.start = NULL;
3587
0
}
3588
3589
void
3590
md_begin (void)
3591
0
{
3592
  /* Make sure possible padding space is clear.  */
3593
0
  memset (&pp, 0, sizeof (pp));
3594
3595
  /* Initialize op_hash hash table.  */
3596
0
  op_hash = str_htab_create ();
3597
3598
0
  {
3599
0
    const i386_op_off_t *cur = i386_op_sets;
3600
0
    const i386_op_off_t *end = cur + ARRAY_SIZE (i386_op_sets) - 1;
3601
3602
0
    for (; cur < end; ++cur)
3603
0
      if (str_hash_insert (op_hash, insn_name (&i386_optab[*cur]), cur, 0))
3604
0
  as_fatal (_("duplicate %s"), insn_name (&i386_optab[*cur]));
3605
0
  }
3606
3607
  /* Initialize reg_hash hash table.  */
3608
0
  reg_hash = str_htab_create ();
3609
0
  {
3610
0
    const reg_entry *regtab;
3611
0
    unsigned int regtab_size = i386_regtab_size;
3612
3613
0
    for (regtab = i386_regtab; regtab_size--; regtab++)
3614
0
      {
3615
0
  switch (regtab->reg_type.bitfield.class)
3616
0
    {
3617
0
    case Reg:
3618
0
      if (regtab->reg_type.bitfield.dword)
3619
0
        {
3620
0
    if (regtab->reg_type.bitfield.instance == Accum)
3621
0
      reg_eax = regtab;
3622
0
        }
3623
0
      break;
3624
3625
0
    case RegFP:
3626
      /* There's no point inserting st(<N>) in the hash table, as
3627
         parentheses aren't included in register_chars[] anyway.  */
3628
0
      if (regtab->reg_type.bitfield.instance != Accum)
3629
0
        continue;
3630
0
      reg_st0 = regtab;
3631
0
      break;
3632
3633
0
    case SReg:
3634
0
      switch (regtab->reg_num)
3635
0
        {
3636
0
        case 0: reg_es = regtab; break;
3637
0
        case 2: reg_ss = regtab; break;
3638
0
        case 3: reg_ds = regtab; break;
3639
0
        }
3640
0
      break;
3641
3642
0
    case RegMask:
3643
0
      if (!regtab->reg_num)
3644
0
        reg_k0 = regtab;
3645
0
      break;
3646
0
    }
3647
3648
0
  if (str_hash_insert (reg_hash, regtab->reg_name, regtab, 0) != NULL)
3649
0
    as_fatal (_("duplicate %s"), regtab->reg_name);
3650
0
      }
3651
0
  }
3652
3653
  /* Fill in lexical tables:  mnemonic_chars, operand_chars.  */
3654
0
  {
3655
0
    int c;
3656
0
    const char *p;
3657
3658
0
    for (c = 0; c < 256; c++)
3659
0
      {
3660
0
  if (ISDIGIT (c) || ISLOWER (c))
3661
0
    {
3662
0
      mnemonic_chars[c] = c;
3663
0
      register_chars[c] = c;
3664
0
      operand_chars[c] = c;
3665
0
    }
3666
0
  else if (ISUPPER (c))
3667
0
    {
3668
0
      mnemonic_chars[c] = TOLOWER (c);
3669
0
      register_chars[c] = mnemonic_chars[c];
3670
0
      operand_chars[c] = c;
3671
0
    }
3672
#ifdef SVR4_COMMENT_CHARS
3673
  else if (c == '\\' && strchr (i386_comment_chars, '/'))
3674
    operand_chars[c] = c;
3675
#endif
3676
3677
0
  if (c >= 128)
3678
0
    operand_chars[c] = c;
3679
0
      }
3680
3681
0
    mnemonic_chars['_'] = '_';
3682
0
    mnemonic_chars['-'] = '-';
3683
0
    mnemonic_chars['.'] = '.';
3684
3685
0
    for (p = extra_symbol_chars; *p != '\0'; p++)
3686
0
      operand_chars[(unsigned char) *p] = *p;
3687
0
    for (p = operand_special_chars; *p != '\0'; p++)
3688
0
      operand_chars[(unsigned char) *p] = *p;
3689
0
  }
3690
3691
0
  if (object_64bit)
3692
0
    {
3693
#if defined (OBJ_COFF) && defined (TE_PE)
3694
      x86_dwarf2_return_column = 32;
3695
#else
3696
0
      x86_dwarf2_return_column = REG_RA;
3697
0
#endif
3698
0
      x86_cie_data_alignment = -8;
3699
0
    }
3700
0
  else
3701
0
    {
3702
0
      x86_dwarf2_return_column = 8;
3703
0
      x86_cie_data_alignment = -4;
3704
0
    }
3705
3706
  /* NB: FUSED_JCC_PADDING frag must have sufficient room so that it
3707
     can be turned into BRANCH_PREFIX frag.  */
3708
0
  if (align_branch_prefix_size > MAX_FUSED_JCC_PADDING_SIZE)
3709
0
    abort ();
3710
0
}
3711
3712
void
3713
i386_print_statistics (FILE *file)
3714
0
{
3715
0
  htab_print_statistics (file, "i386 opcode", op_hash);
3716
0
  htab_print_statistics (file, "i386 register", reg_hash);
3717
0
}
3718
3719
void
3720
i386_md_end (void)
3721
0
{
3722
0
  htab_delete (op_hash);
3723
0
  htab_delete (reg_hash);
3724
0
  GOT_symbol = NULL;
3725
0
}
3726

3727
#ifdef DEBUG386
3728
3729
/* Debugging routines for md_assemble.  */
3730
static void pte (insn_template *);
3731
static void pt (i386_operand_type);
3732
static void pe (expressionS *);
3733
static void ps (symbolS *);
3734
3735
static void
3736
pi (const char *line, i386_insn *x)
3737
{
3738
  unsigned int j;
3739
3740
  fprintf (stdout, "%s: template ", line);
3741
  pte (&x->tm);
3742
  fprintf (stdout, "  address: base %s  index %s  scale %x\n",
3743
     x->base_reg ? x->base_reg->reg_name : "none",
3744
     x->index_reg ? x->index_reg->reg_name : "none",
3745
     x->log2_scale_factor);
3746
  fprintf (stdout, "  modrm:  mode %x  reg %x  reg/mem %x\n",
3747
     x->rm.mode, x->rm.reg, x->rm.regmem);
3748
  fprintf (stdout, "  sib:  base %x  index %x  scale %x\n",
3749
     x->sib.base, x->sib.index, x->sib.scale);
3750
  fprintf (stdout, "  rex: 64bit %x  extX %x  extY %x  extZ %x\n",
3751
     (x->rex & REX_W) != 0,
3752
     (x->rex & REX_R) != 0,
3753
     (x->rex & REX_X) != 0,
3754
     (x->rex & REX_B) != 0);
3755
  for (j = 0; j < x->operands; j++)
3756
    {
3757
      fprintf (stdout, "    #%d:  ", j + 1);
3758
      pt (x->types[j]);
3759
      fprintf (stdout, "\n");
3760
      if (x->types[j].bitfield.class == Reg
3761
    || x->types[j].bitfield.class == RegFP
3762
    || x->types[j].bitfield.class == RegMMX
3763
    || x->types[j].bitfield.class == RegSIMD
3764
    || x->types[j].bitfield.class == RegMask
3765
    || x->types[j].bitfield.class == SReg
3766
    || x->types[j].bitfield.class == RegCR
3767
    || x->types[j].bitfield.class == RegDR
3768
    || x->types[j].bitfield.class == RegTR
3769
    || x->types[j].bitfield.class == RegBND)
3770
  fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
3771
      if (operand_type_check (x->types[j], imm))
3772
  pe (x->op[j].imms);
3773
      if (operand_type_check (x->types[j], disp))
3774
  pe (x->op[j].disps);
3775
    }
3776
}
3777
3778
static void
3779
pte (insn_template *t)
3780
{
3781
  static const unsigned char opc_pfx[] = { 0, 0x66, 0xf3, 0xf2 };
3782
  static const char *const opc_spc[] = {
3783
    NULL, "0f", "0f38", "0f3a", NULL, "evexmap5", "evexmap6", NULL,
3784
    "XOP08", "XOP09", "XOP0A",
3785
  };
3786
  unsigned int j;
3787
3788
  fprintf (stdout, " %d operands ", t->operands);
3789
  if (opc_pfx[t->opcode_modifier.opcodeprefix])
3790
    fprintf (stdout, "pfx %x ", opc_pfx[t->opcode_modifier.opcodeprefix]);
3791
  if (opc_spc[t->opcode_space])
3792
    fprintf (stdout, "space %s ", opc_spc[t->opcode_space]);
3793
  fprintf (stdout, "opcode %x ", t->base_opcode);
3794
  if (t->extension_opcode != None)
3795
    fprintf (stdout, "ext %x ", t->extension_opcode);
3796
  if (t->opcode_modifier.d)
3797
    fprintf (stdout, "D");
3798
  if (t->opcode_modifier.w)
3799
    fprintf (stdout, "W");
3800
  fprintf (stdout, "\n");
3801
  for (j = 0; j < t->operands; j++)
3802
    {
3803
      fprintf (stdout, "    #%d type ", j + 1);
3804
      pt (t->operand_types[j]);
3805
      fprintf (stdout, "\n");
3806
    }
3807
}
3808
3809
static void
3810
pe (expressionS *e)
3811
{
3812
  fprintf (stdout, "    operation     %d\n", e->X_op);
3813
  fprintf (stdout, "    add_number    %" PRId64 " (%" PRIx64 ")\n",
3814
     (int64_t) e->X_add_number, (uint64_t) (valueT) e->X_add_number);
3815
  if (e->X_add_symbol)
3816
    {
3817
      fprintf (stdout, "    add_symbol    ");
3818
      ps (e->X_add_symbol);
3819
      fprintf (stdout, "\n");
3820
    }
3821
  if (e->X_op_symbol)
3822
    {
3823
      fprintf (stdout, "    op_symbol    ");
3824
      ps (e->X_op_symbol);
3825
      fprintf (stdout, "\n");
3826
    }
3827
}
3828
3829
static void
3830
ps (symbolS *s)
3831
{
3832
  fprintf (stdout, "%s type %s%s",
3833
     S_GET_NAME (s),
3834
     S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
3835
     segment_name (S_GET_SEGMENT (s)));
3836
}
3837
3838
static struct type_name
3839
  {
3840
    i386_operand_type mask;
3841
    const char *name;
3842
  }
3843
const type_names[] =
3844
{
3845
  { { .bitfield = { .class = Reg, .byte = 1 } }, "r8" },
3846
  { { .bitfield = { .class = Reg, .word = 1 } }, "r16" },
3847
  { { .bitfield = { .class = Reg, .dword = 1 } }, "r32" },
3848
  { { .bitfield = { .class = Reg, .qword = 1 } }, "r64" },
3849
  { { .bitfield = { .instance = Accum, .byte = 1 } }, "acc8" },
3850
  { { .bitfield = { .instance = Accum, .word = 1 } }, "acc16" },
3851
  { { .bitfield = { .instance = Accum, .dword = 1 } }, "acc32" },
3852
  { { .bitfield = { .instance = Accum, .qword = 1 } }, "acc64" },
3853
  { { .bitfield = { .imm8 = 1 } }, "i8" },
3854
  { { .bitfield = { .imm8s = 1 } }, "i8s" },
3855
  { { .bitfield = { .imm16 = 1 } }, "i16" },
3856
  { { .bitfield = { .imm32 = 1 } }, "i32" },
3857
  { { .bitfield = { .imm32s = 1 } }, "i32s" },
3858
  { { .bitfield = { .imm64 = 1 } }, "i64" },
3859
  { { .bitfield = { .imm1 = 1 } }, "i1" },
3860
  { { .bitfield = { .baseindex = 1 } }, "BaseIndex" },
3861
  { { .bitfield = { .disp8 = 1 } }, "d8" },
3862
  { { .bitfield = { .disp16 = 1 } }, "d16" },
3863
  { { .bitfield = { .disp32 = 1 } }, "d32" },
3864
  { { .bitfield = { .disp64 = 1 } }, "d64" },
3865
  { { .bitfield = { .instance = RegD, .word = 1 } }, "InOutPortReg" },
3866
  { { .bitfield = { .instance = RegC, .byte = 1 } }, "ShiftCount" },
3867
  { { .bitfield = { .class = RegCR } }, "control reg" },
3868
  { { .bitfield = { .class = RegTR } }, "test reg" },
3869
  { { .bitfield = { .class = RegDR } }, "debug reg" },
3870
  { { .bitfield = { .class = RegFP, .tbyte = 1 } }, "FReg" },
3871
  { { .bitfield = { .instance = Accum, .tbyte = 1 } }, "FAcc" },
3872
  { { .bitfield = { .class = SReg } }, "SReg" },
3873
  { { .bitfield = { .class = RegMMX } }, "rMMX" },
3874
  { { .bitfield = { .class = RegSIMD, .xmmword = 1 } }, "rXMM" },
3875
  { { .bitfield = { .class = RegSIMD, .ymmword = 1 } }, "rYMM" },
3876
  { { .bitfield = { .class = RegSIMD, .zmmword = 1 } }, "rZMM" },
3877
  { { .bitfield = { .class = RegSIMD, .tmmword = 1 } }, "rTMM" },
3878
  { { .bitfield = { .class = RegMask } }, "Mask reg" },
3879
};
3880
3881
static void
3882
pt (i386_operand_type t)
3883
{
3884
  unsigned int j;
3885
  i386_operand_type a;
3886
3887
  for (j = 0; j < ARRAY_SIZE (type_names); j++)
3888
    {
3889
      a = operand_type_and (t, type_names[j].mask);
3890
      if (operand_type_equal (&a, &type_names[j].mask))
3891
  fprintf (stdout, "%s, ",  type_names[j].name);
3892
    }
3893
  fflush (stdout);
3894
}
3895
3896
#endif /* DEBUG386 */
3897

3898
static bfd_reloc_code_real_type
3899
reloc (unsigned int size,
3900
       int pcrel,
3901
       int sign,
3902
       bfd_reloc_code_real_type other)
3903
0
{
3904
0
  if (other != NO_RELOC)
3905
0
    {
3906
0
      reloc_howto_type *rel;
3907
3908
0
      if (size == 8)
3909
0
  switch (other)
3910
0
    {
3911
0
    case BFD_RELOC_X86_64_GOT32:
3912
0
      return BFD_RELOC_X86_64_GOT64;
3913
0
      break;
3914
0
    case BFD_RELOC_X86_64_GOTPLT64:
3915
0
      return BFD_RELOC_X86_64_GOTPLT64;
3916
0
      break;
3917
0
    case BFD_RELOC_X86_64_PLTOFF64:
3918
0
      return BFD_RELOC_X86_64_PLTOFF64;
3919
0
      break;
3920
0
    case BFD_RELOC_X86_64_GOTPC32:
3921
0
      other = BFD_RELOC_X86_64_GOTPC64;
3922
0
      break;
3923
0
    case BFD_RELOC_X86_64_GOTPCREL:
3924
0
      other = BFD_RELOC_X86_64_GOTPCREL64;
3925
0
      break;
3926
0
    case BFD_RELOC_X86_64_TPOFF32:
3927
0
      other = BFD_RELOC_X86_64_TPOFF64;
3928
0
      break;
3929
0
    case BFD_RELOC_X86_64_DTPOFF32:
3930
0
      other = BFD_RELOC_X86_64_DTPOFF64;
3931
0
      break;
3932
0
    default:
3933
0
      break;
3934
0
    }
3935
3936
0
#ifdef OBJ_ELF
3937
0
      if (other == BFD_RELOC_SIZE32)
3938
0
  {
3939
0
    if (size == 8)
3940
0
      other = BFD_RELOC_SIZE64;
3941
0
    if (pcrel)
3942
0
      {
3943
0
        as_bad (_("there are no pc-relative size relocations"));
3944
0
        return NO_RELOC;
3945
0
      }
3946
0
  }
3947
0
#endif
3948
3949
      /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless.  */
3950
0
      if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
3951
0
  sign = -1;
3952
3953
0
      rel = bfd_reloc_type_lookup (stdoutput, other);
3954
0
      if (!rel)
3955
0
  as_bad (_("unknown relocation (%u)"), other);
3956
0
      else if (size != bfd_get_reloc_size (rel))
3957
0
  as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3958
0
    bfd_get_reloc_size (rel),
3959
0
    size);
3960
0
      else if (pcrel && !rel->pc_relative)
3961
0
  as_bad (_("non-pc-relative relocation for pc-relative field"));
3962
0
      else if ((rel->complain_on_overflow == complain_overflow_signed
3963
0
    && !sign)
3964
0
         || (rel->complain_on_overflow == complain_overflow_unsigned
3965
0
       && sign > 0))
3966
0
  as_bad (_("relocated field and relocation type differ in signedness"));
3967
0
      else
3968
0
  return other;
3969
0
      return NO_RELOC;
3970
0
    }
3971
3972
0
  if (pcrel)
3973
0
    {
3974
0
      if (!sign)
3975
0
  as_bad (_("there are no unsigned pc-relative relocations"));
3976
0
      switch (size)
3977
0
  {
3978
0
  case 1: return BFD_RELOC_8_PCREL;
3979
0
  case 2: return BFD_RELOC_16_PCREL;
3980
0
  case 4: return BFD_RELOC_32_PCREL;
3981
0
  case 8: return BFD_RELOC_64_PCREL;
3982
0
  }
3983
0
      as_bad (_("cannot do %u byte pc-relative relocation"), size);
3984
0
    }
3985
0
  else
3986
0
    {
3987
0
      if (sign > 0)
3988
0
  switch (size)
3989
0
    {
3990
0
    case 4: return BFD_RELOC_X86_64_32S;
3991
0
    }
3992
0
      else
3993
0
  switch (size)
3994
0
    {
3995
0
    case 1: return BFD_RELOC_8;
3996
0
    case 2: return BFD_RELOC_16;
3997
0
    case 4: return BFD_RELOC_32;
3998
0
    case 8: return BFD_RELOC_64;
3999
0
    }
4000
0
      as_bad (_("cannot do %s %u byte relocation"),
4001
0
        sign > 0 ? "signed" : "unsigned", size);
4002
0
    }
4003
4004
0
  return NO_RELOC;
4005
0
}
4006
4007
#ifdef OBJ_ELF
4008
/* Here we decide which fixups can be adjusted to make them relative to
4009
   the beginning of the section instead of the symbol.  Basically we need
4010
   to make sure that the dynamic relocations are done correctly, so in
4011
   some cases we force the original symbol to be used.  */
4012
4013
int
4014
tc_i386_fix_adjustable (fixS *fixP)
4015
0
{
4016
  /* Don't adjust pc-relative references to merge sections in 64-bit
4017
     mode.  */
4018
0
  if (use_rela_relocations
4019
0
      && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
4020
0
      && fixP->fx_pcrel)
4021
0
    return 0;
4022
4023
  /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
4024
     and changed later by validate_fix.  */
4025
0
  if (GOT_symbol && fixP->fx_subsy == GOT_symbol
4026
0
      && fixP->fx_r_type == BFD_RELOC_32_PCREL)
4027
0
    return 0;
4028
4029
  /* Adjust_reloc_syms doesn't know about the GOT.  Need to keep symbol
4030
     for size relocations.  */
4031
0
  if (fixP->fx_r_type == BFD_RELOC_SIZE32
4032
0
      || fixP->fx_r_type == BFD_RELOC_SIZE64
4033
0
      || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
4034
0
      || fixP->fx_r_type == BFD_RELOC_386_GOT32
4035
0
      || fixP->fx_r_type == BFD_RELOC_386_GOT32X
4036
0
      || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
4037
0
      || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
4038
0
      || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
4039
0
      || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
4040
0
      || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
4041
0
      || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
4042
0
      || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
4043
0
      || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
4044
0
      || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
4045
0
      || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
4046
0
      || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
4047
0
      || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
4048
0
      || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX
4049
0
      || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX
4050
0
      || fixP->fx_r_type == BFD_RELOC_X86_64_CODE_4_GOTPCRELX
4051
0
      || fixP->fx_r_type == BFD_RELOC_X86_64_CODE_5_GOTPCRELX
4052
0
      || fixP->fx_r_type == BFD_RELOC_X86_64_CODE_6_GOTPCRELX
4053
0
      || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
4054
0
      || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
4055
0
      || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
4056
0
      || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
4057
0
      || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
4058
0
      || fixP->fx_r_type == BFD_RELOC_X86_64_CODE_4_GOTTPOFF
4059
0
      || fixP->fx_r_type == BFD_RELOC_X86_64_CODE_5_GOTTPOFF
4060
0
      || fixP->fx_r_type == BFD_RELOC_X86_64_CODE_6_GOTTPOFF
4061
0
      || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
4062
0
      || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
4063
0
      || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
4064
0
      || fixP->fx_r_type == BFD_RELOC_X86_64_GOT64
4065
0
      || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
4066
0
      || fixP->fx_r_type == BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC
4067
0
      || fixP->fx_r_type == BFD_RELOC_X86_64_CODE_5_GOTPC32_TLSDESC
4068
0
      || fixP->fx_r_type == BFD_RELOC_X86_64_CODE_6_GOTPC32_TLSDESC
4069
0
      || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
4070
0
      || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4071
0
      || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
4072
0
    return 0;
4073
  /* Resolve PLT32 relocation against local symbol to section only for
4074
     PC-relative relocations.  */
4075
0
  if (fixP->fx_r_type == BFD_RELOC_386_PLT32
4076
0
      || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32)
4077
0
    return fixP->fx_pcrel;
4078
0
  return 1;
4079
0
}
4080
#endif
4081
4082
static INLINE bool
4083
want_disp32 (const insn_template *t)
4084
0
{
4085
0
  return flag_code != CODE_64BIT
4086
0
   || i.prefix[ADDR_PREFIX]
4087
0
   || ((t->mnem_off == MN_lea
4088
0
        || (i.tm.base_opcode == 0x8d && i.tm.opcode_space == SPACE_BASE))
4089
0
       && (!i.types[1].bitfield.qword
4090
0
     || t->opcode_modifier.size == SIZE32));
4091
0
}
4092
4093
static int
4094
intel_float_operand (const char *mnemonic)
4095
0
{
4096
  /* Note that the value returned is meaningful only for opcodes with (memory)
4097
     operands, hence the code here is free to improperly handle opcodes that
4098
     have no operands (for better performance and smaller code). */
4099
4100
0
  if (mnemonic[0] != 'f')
4101
0
    return 0; /* non-math */
4102
4103
0
  switch (mnemonic[1])
4104
0
    {
4105
    /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
4106
       the fs segment override prefix not currently handled because no
4107
       call path can make opcodes without operands get here */
4108
0
    case 'i':
4109
0
      return 2 /* integer op */;
4110
0
    case 'l':
4111
0
      if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
4112
0
  return 3; /* fldcw/fldenv */
4113
0
      break;
4114
0
    case 'n':
4115
0
      if (mnemonic[2] != 'o' /* fnop */)
4116
0
  return 3; /* non-waiting control op */
4117
0
      break;
4118
0
    case 'r':
4119
0
      if (mnemonic[2] == 's')
4120
0
  return 3; /* frstor/frstpm */
4121
0
      break;
4122
0
    case 's':
4123
0
      if (mnemonic[2] == 'a')
4124
0
  return 3; /* fsave */
4125
0
      if (mnemonic[2] == 't')
4126
0
  {
4127
0
    switch (mnemonic[3])
4128
0
      {
4129
0
      case 'c': /* fstcw */
4130
0
      case 'd': /* fstdw */
4131
0
      case 'e': /* fstenv */
4132
0
      case 's': /* fsts[gw] */
4133
0
        return 3;
4134
0
      }
4135
0
  }
4136
0
      break;
4137
0
    case 'x':
4138
0
      if (mnemonic[2] == 'r' || mnemonic[2] == 's')
4139
0
  return 0; /* fxsave/fxrstor are not really math ops */
4140
0
      break;
4141
0
    }
4142
4143
0
  return 1;
4144
0
}
4145
4146
static INLINE void
4147
install_template (const insn_template *t)
4148
0
{
4149
0
  unsigned int l;
4150
4151
0
  i.tm = *t;
4152
4153
  /* Dual VEX/EVEX templates need stripping one of the possible variants.  */
4154
0
  if (t->opcode_modifier.vex && t->opcode_modifier.evex)
4155
0
    {
4156
0
      if ((maybe_cpu (t, CpuAVX) || maybe_cpu (t, CpuAVX2)
4157
0
     || maybe_cpu (t, CpuFMA))
4158
0
    && (maybe_cpu (t, CpuAVX512F) || maybe_cpu (t, CpuAVX512VL)))
4159
0
  {
4160
0
    if (need_evex_encoding (t))
4161
0
      {
4162
0
        i.tm.opcode_modifier.vex = 0;
4163
0
        i.tm.cpu.bitfield.cpuavx512f = i.tm.cpu_any.bitfield.cpuavx512f;
4164
0
        i.tm.cpu.bitfield.cpuavx512vl = i.tm.cpu_any.bitfield.cpuavx512vl;
4165
0
      }
4166
0
    else
4167
0
      {
4168
0
        i.tm.opcode_modifier.evex = 0;
4169
0
        if (i.tm.cpu_any.bitfield.cpuavx)
4170
0
    i.tm.cpu.bitfield.cpuavx = 1;
4171
0
        else if (!i.tm.cpu.bitfield.isa)
4172
0
    i.tm.cpu.bitfield.isa = i.tm.cpu_any.bitfield.isa;
4173
0
        else
4174
0
    gas_assert (i.tm.cpu.bitfield.isa == i.tm.cpu_any.bitfield.isa);
4175
0
      }
4176
0
  }
4177
4178
0
      if ((maybe_cpu (t, CpuCMPCCXADD) || maybe_cpu (t, CpuAMX_TILE)
4179
0
     || maybe_cpu (t, CpuAVX512F) || maybe_cpu (t, CpuAVX512DQ)
4180
0
     || maybe_cpu (t, CpuAVX512BW) || maybe_cpu (t, CpuBMI)
4181
0
     || maybe_cpu (t, CpuBMI2) || maybe_cpu (t, CpuUSER_MSR)
4182
0
     || maybe_cpu (t, CpuMSR_IMM) || maybe_cpu (t, CpuAMX_TRANSPOSE)
4183
0
     || maybe_cpu (t, CpuAMX_MOVRS))
4184
0
    && maybe_cpu (t, CpuAPX_F))
4185
0
  {
4186
0
    if (need_evex_encoding (t))
4187
0
      i.tm.opcode_modifier.vex = 0;
4188
0
    else
4189
0
      i.tm.opcode_modifier.evex = 0;
4190
0
  }
4191
0
    }
4192
4193
  /* For CCMP and CTEST the template has EVEX.SCC in base_opcode. Move it out of
4194
     there, to then adjust base_opcode to obtain its normal meaning.  */
4195
0
  if (i.tm.opcode_modifier.operandconstraint == SCC)
4196
0
    {
4197
      /* Get EVEX.SCC value from the lower 4 bits of base_opcode.  */
4198
0
      i.scc = i.tm.base_opcode & 0xf;
4199
0
      i.tm.base_opcode >>= 8;
4200
0
    }
4201
4202
  /* For CMOVcc having undergone NDD-to-legacy optimization with its source
4203
     operands being swapped, we need to invert the encoded condition.  */
4204
0
  if (i.invert_cond)
4205
0
    i.tm.base_opcode ^= 1;
4206
4207
  /* Note that for pseudo prefixes this produces a length of 1. But for them
4208
     the length isn't interesting at all.  */
4209
0
  for (l = 1; l < 4; ++l)
4210
0
    if (!(i.tm.base_opcode >> (8 * l)))
4211
0
      break;
4212
4213
0
  i.opcode_length = l;
4214
0
}
4215
4216
/* Build the VEX prefix.  */
4217
4218
static void
4219
build_vex_prefix (const insn_template *t)
4220
0
{
4221
0
  unsigned int register_specifier;
4222
0
  unsigned int vector_length;
4223
0
  bool w;
4224
4225
  /* Check register specifier.  */
4226
0
  if (i.vex.register_specifier)
4227
0
    {
4228
0
      register_specifier =
4229
0
  ~register_number (i.vex.register_specifier) & 0xf;
4230
0
      gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0);
4231
0
    }
4232
0
  else
4233
0
    register_specifier = 0xf;
4234
4235
  /* Use 2-byte VEX prefix by swapping destination and source operand
4236
     if there are more than 1 register operand.  */
4237
0
  if (i.reg_operands > 1
4238
0
      && pp.encoding != encoding_vex3
4239
0
      && pp.dir_encoding == dir_encoding_default
4240
0
      && i.operands == i.reg_operands
4241
0
      && operand_type_equal (&i.types[0], &i.types[i.operands - 1])
4242
0
      && i.tm.opcode_space == SPACE_0F
4243
0
      && (i.tm.opcode_modifier.load || i.tm.opcode_modifier.d)
4244
0
      && i.rex == REX_B)
4245
0
    {
4246
0
      unsigned int xchg;
4247
4248
0
      swap_2_operands (0, i.operands - 1);
4249
4250
0
      gas_assert (i.rm.mode == 3);
4251
4252
0
      i.rex = REX_R;
4253
0
      xchg = i.rm.regmem;
4254
0
      i.rm.regmem = i.rm.reg;
4255
0
      i.rm.reg = xchg;
4256
4257
0
      if (i.tm.opcode_modifier.d)
4258
0
  i.tm.base_opcode ^= (i.tm.base_opcode & 0xee) != 0x6e
4259
0
          ? Opcode_ExtD : Opcode_SIMD_IntD;
4260
0
      else /* Use the next insn.  */
4261
0
  install_template (&t[1]);
4262
0
    }
4263
4264
  /* Use 2-byte VEX prefix by swapping commutative source operands if there
4265
     are no memory operands and at least 3 register ones.  */
4266
0
  if (i.reg_operands >= 3
4267
0
      && pp.encoding != encoding_vex3
4268
0
      && i.reg_operands == i.operands - i.imm_operands
4269
0
      && i.tm.opcode_modifier.vex
4270
0
      && i.tm.opcode_modifier.commutative
4271
      /* .commutative aliases .staticrounding; disambiguate.  */
4272
0
      && !i.tm.opcode_modifier.sae
4273
0
      && (i.tm.opcode_modifier.sse2avx
4274
0
    || (optimize > 1 && !pp.no_optimize))
4275
0
      && i.rex == REX_B
4276
0
      && i.vex.register_specifier
4277
0
      && !(i.vex.register_specifier->reg_flags & RegRex))
4278
0
    {
4279
0
      unsigned int xchg = i.operands - i.reg_operands;
4280
4281
0
      gas_assert (i.tm.opcode_space == SPACE_0F);
4282
0
      gas_assert (!i.tm.opcode_modifier.sae);
4283
0
      gas_assert (operand_type_equal (&i.types[i.operands - 2],
4284
0
                                      &i.types[i.operands - 3]));
4285
0
      gas_assert (i.rm.mode == 3);
4286
4287
0
      swap_2_operands (xchg, xchg + 1);
4288
4289
0
      i.rex = 0;
4290
0
      xchg = i.rm.regmem | 8;
4291
0
      i.rm.regmem = ~register_specifier & 0xf;
4292
0
      gas_assert (!(i.rm.regmem & 8));
4293
0
      i.vex.register_specifier += xchg - i.rm.regmem;
4294
0
      register_specifier = ~xchg & 0xf;
4295
0
    }
4296
4297
0
  if (i.tm.opcode_modifier.vex == VEXScalar)
4298
0
    vector_length = avxscalar;
4299
0
  else if (i.tm.opcode_modifier.vex == VEX256)
4300
0
    vector_length = 1;
4301
0
  else if (dot_insn () && i.tm.opcode_modifier.vex == VEX128)
4302
0
    vector_length = 0;
4303
0
  else
4304
0
    {
4305
0
      unsigned int op;
4306
4307
      /* Determine vector length from the last multi-length vector
4308
   operand.  */
4309
0
      vector_length = 0;
4310
0
      for (op = t->operands; op--;)
4311
0
  if (t->operand_types[op].bitfield.xmmword
4312
0
      && t->operand_types[op].bitfield.ymmword
4313
0
      && i.types[op].bitfield.ymmword)
4314
0
    {
4315
0
      vector_length = 1;
4316
0
      break;
4317
0
    }
4318
0
    }
4319
4320
  /* Check the REX.W bit and VEXW.  */
4321
0
  if (i.tm.opcode_modifier.vexw == VEXWIG)
4322
0
    w = vexwig == vexw1 || (i.rex & REX_W);
4323
0
  else if (i.tm.opcode_modifier.vexw && !(i.rex & REX_W))
4324
0
    w = i.tm.opcode_modifier.vexw == VEXW1;
4325
0
  else
4326
0
    w = flag_code == CODE_64BIT ? i.rex & REX_W : vexwig == vexw1;
4327
4328
  /* Use 2-byte VEX prefix if possible.  */
4329
0
  if (w == 0
4330
0
      && pp.encoding != encoding_vex3
4331
0
      && i.tm.opcode_space == SPACE_0F
4332
0
      && (i.rex & (REX_W | REX_X | REX_B)) == 0)
4333
0
    {
4334
      /* 2-byte VEX prefix.  */
4335
0
      bool r;
4336
4337
0
      i.vex.length = 2;
4338
0
      i.vex.bytes[0] = 0xc5;
4339
4340
      /* Check the REX.R bit.  */
4341
0
      r = !(i.rex & REX_R);
4342
0
      i.vex.bytes[1] = (r << 7
4343
0
      | register_specifier << 3
4344
0
      | vector_length << 2
4345
0
      | i.tm.opcode_modifier.opcodeprefix);
4346
0
    }
4347
0
  else
4348
0
    {
4349
      /* 3-byte VEX prefix.  */
4350
0
      i.vex.length = 3;
4351
4352
0
      switch (i.tm.opcode_space)
4353
0
  {
4354
0
  case SPACE_0F:
4355
0
  case SPACE_0F38:
4356
0
  case SPACE_0F3A:
4357
0
  case SPACE_MAP5:
4358
0
  case SPACE_MAP7:
4359
0
    i.vex.bytes[0] = 0xc4;
4360
0
    break;
4361
0
  case SPACE_XOP08:
4362
0
  case SPACE_XOP09:
4363
0
  case SPACE_XOP0A:
4364
0
    i.vex.bytes[0] = 0x8f;
4365
0
    break;
4366
0
  default:
4367
0
    abort ();
4368
0
  }
4369
4370
      /* The high 3 bits of the second VEX byte are 1's compliment
4371
   of RXB bits from REX.  */
4372
0
      i.vex.bytes[1] = ((~i.rex & 7) << 5)
4373
0
           | (!dot_insn () ? i.tm.opcode_space
4374
0
               : i.insn_opcode_space);
4375
4376
0
      i.vex.bytes[2] = (w << 7
4377
0
      | register_specifier << 3
4378
0
      | vector_length << 2
4379
0
      | i.tm.opcode_modifier.opcodeprefix);
4380
0
    }
4381
0
}
4382
4383
static INLINE bool
4384
is_any_vex_encoding (const insn_template *t)
4385
0
{
4386
0
  return t->opcode_modifier.vex || t->opcode_modifier.evex;
4387
0
}
4388
4389
/* We can use this function only when the current encoding is evex.  */
4390
static INLINE bool
4391
is_apx_evex_encoding (void)
4392
0
{
4393
0
  return i.rex2 || i.tm.opcode_space == SPACE_MAP4 || pp.has_nf
4394
0
    || (i.vex.register_specifier
4395
0
  && (i.vex.register_specifier->reg_flags & RegRex2));
4396
0
}
4397
4398
static INLINE bool
4399
is_apx_rex2_encoding (void)
4400
0
{
4401
0
  return i.rex2 || pp.rex2_encoding
4402
0
  || i.tm.opcode_modifier.rex2;
4403
0
}
4404
4405
static unsigned int
4406
get_broadcast_bytes (const insn_template *t, bool diag)
4407
0
{
4408
0
  unsigned int op, bytes;
4409
0
  const i386_operand_type *types;
4410
4411
0
  if (i.broadcast.type)
4412
0
    return (1 << (t->opcode_modifier.broadcast - 1)) * i.broadcast.type;
4413
4414
0
  gas_assert (intel_syntax);
4415
4416
0
  for (op = 0; op < t->operands; ++op)
4417
0
    if (t->operand_types[op].bitfield.baseindex)
4418
0
      break;
4419
4420
0
  gas_assert (op < t->operands);
4421
4422
0
  if (t->opcode_modifier.evex != EVEXDYN)
4423
0
    switch (i.broadcast.bytes)
4424
0
      {
4425
0
      case 1:
4426
0
  if (t->operand_types[op].bitfield.word)
4427
0
    return 2;
4428
      /* Fall through.  */
4429
0
      case 2:
4430
0
  if (t->operand_types[op].bitfield.dword)
4431
0
    return 4;
4432
      /* Fall through.  */
4433
0
      case 4:
4434
0
  if (t->operand_types[op].bitfield.qword)
4435
0
    return 8;
4436
      /* Fall through.  */
4437
0
      case 8:
4438
0
  if (t->operand_types[op].bitfield.xmmword)
4439
0
    return 16;
4440
0
  if (t->operand_types[op].bitfield.ymmword)
4441
0
    return 32;
4442
0
  if (t->operand_types[op].bitfield.zmmword)
4443
0
    return 64;
4444
      /* Fall through.  */
4445
0
      default:
4446
0
        abort ();
4447
0
      }
4448
4449
0
  gas_assert (op + 1 < t->operands);
4450
4451
0
  if (t->operand_types[op + 1].bitfield.xmmword
4452
0
      + t->operand_types[op + 1].bitfield.ymmword
4453
0
      + t->operand_types[op + 1].bitfield.zmmword > 1)
4454
0
    {
4455
0
      types = &i.types[op + 1];
4456
0
      diag = false;
4457
0
    }
4458
0
  else /* Ambiguous - guess with a preference to non-AVX512VL forms.  */
4459
0
    types = &t->operand_types[op];
4460
4461
0
  if (types->bitfield.zmmword)
4462
0
    bytes = 64;
4463
0
  else if (types->bitfield.ymmword)
4464
0
    bytes = 32;
4465
0
  else
4466
0
    bytes = 16;
4467
4468
0
  if (diag)
4469
0
    as_warn (_("ambiguous broadcast for `%s', using %u-bit form"),
4470
0
       insn_name (t), bytes * 8);
4471
4472
0
  return bytes;
4473
0
}
4474
4475
/* Build the EVEX prefix.  */
4476
4477
static void
4478
build_evex_prefix (void)
4479
0
{
4480
0
  unsigned int register_specifier;
4481
0
  bool w;
4482
0
  rex_byte vrex_used = 0;
4483
4484
  /* Check register specifier.  */
4485
0
  if (i.vex.register_specifier)
4486
0
    {
4487
0
      gas_assert ((i.vrex & REX_X) == 0);
4488
4489
0
      register_specifier = i.vex.register_specifier->reg_num;
4490
0
      if ((i.vex.register_specifier->reg_flags & RegRex))
4491
0
  register_specifier += 8;
4492
      /* The upper 16 registers are encoded in the fourth byte of the
4493
   EVEX prefix.  */
4494
0
      if (!(i.vex.register_specifier->reg_flags & RegVRex))
4495
0
  i.vex.bytes[3] = 0x8;
4496
0
      register_specifier = ~register_specifier & 0xf;
4497
0
    }
4498
0
  else
4499
0
    {
4500
0
      register_specifier = 0xf;
4501
4502
      /* Encode upper 16 vector index register in the fourth byte of
4503
   the EVEX prefix.  */
4504
0
      if (!(i.vrex & REX_X))
4505
0
  i.vex.bytes[3] = 0x8;
4506
0
      else
4507
0
  vrex_used |= REX_X;
4508
0
    }
4509
4510
  /* 4 byte EVEX prefix.  */
4511
0
  i.vex.length = 4;
4512
0
  i.vex.bytes[0] = 0x62;
4513
4514
  /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
4515
     bits from REX.  */
4516
0
  gas_assert (i.tm.opcode_space >= SPACE_0F);
4517
0
  gas_assert (i.tm.opcode_space <= SPACE_MAP7);
4518
0
  i.vex.bytes[1] = ((~i.rex & 7) << 5)
4519
0
       | (!dot_insn () ? i.tm.opcode_space
4520
0
           : i.insn_opcode_space);
4521
4522
  /* The fifth bit of the second EVEX byte is 1's compliment of the
4523
     REX_R bit in VREX.  */
4524
0
  if (!(i.vrex & REX_R))
4525
0
    i.vex.bytes[1] |= 0x10;
4526
0
  else
4527
0
    vrex_used |= REX_R;
4528
4529
0
  if ((i.reg_operands + i.imm_operands) == i.operands)
4530
0
    {
4531
      /* When all operands are registers, the REX_X bit in REX is not
4532
   used.  We reuse it to encode the upper 16 registers, which is
4533
   indicated by the REX_B bit in VREX.  The REX_X bit is encoded
4534
   as 1's compliment.  */
4535
0
      if ((i.vrex & REX_B))
4536
0
  {
4537
0
    vrex_used |= REX_B;
4538
0
    i.vex.bytes[1] &= ~0x40;
4539
0
  }
4540
0
    }
4541
4542
  /* EVEX instructions shouldn't need the REX prefix.  */
4543
0
  i.vrex &= ~vrex_used;
4544
0
  gas_assert (i.vrex == 0);
4545
4546
  /* Check the REX.W bit and VEXW.  */
4547
0
  if (i.tm.opcode_modifier.vexw == VEXWIG)
4548
0
    w = evexwig == evexw1 || (i.rex & REX_W);
4549
0
  else if (i.tm.opcode_modifier.vexw && !(i.rex & REX_W))
4550
0
    w = i.tm.opcode_modifier.vexw == VEXW1;
4551
0
  else
4552
0
    w = flag_code == CODE_64BIT ? i.rex & REX_W : evexwig == evexw1;
4553
4554
0
  if (i.tm.opcode_modifier.evex == EVEXDYN)
4555
0
    {
4556
0
      unsigned int op;
4557
4558
      /* Determine vector length from the last multi-length vector operand.  */
4559
0
      for (op = i.operands; op--;)
4560
0
  if (i.tm.operand_types[op].bitfield.xmmword
4561
0
      + i.tm.operand_types[op].bitfield.ymmword
4562
0
      + i.tm.operand_types[op].bitfield.zmmword > 1)
4563
0
    {
4564
0
      if (i.types[op].bitfield.zmmword)
4565
0
        {
4566
0
    i.tm.opcode_modifier.evex = EVEX512;
4567
0
    break;
4568
0
        }
4569
0
      else if (i.types[op].bitfield.ymmword)
4570
0
        {
4571
0
    i.tm.opcode_modifier.evex = EVEX256;
4572
0
    break;
4573
0
        }
4574
0
      else if (i.types[op].bitfield.xmmword)
4575
0
        {
4576
0
    i.tm.opcode_modifier.evex = EVEX128;
4577
0
    break;
4578
0
        }
4579
0
      else if ((i.broadcast.type || i.broadcast.bytes)
4580
0
          && op == i.broadcast.operand)
4581
0
        {
4582
0
    switch (get_broadcast_bytes (&i.tm, true))
4583
0
      {
4584
0
        case 64:
4585
0
          i.tm.opcode_modifier.evex = EVEX512;
4586
0
          break;
4587
0
        case 32:
4588
0
          i.tm.opcode_modifier.evex = EVEX256;
4589
0
          break;
4590
0
        case 16:
4591
0
          i.tm.opcode_modifier.evex = EVEX128;
4592
0
          break;
4593
0
        default:
4594
0
          abort ();
4595
0
      }
4596
0
    break;
4597
0
        }
4598
0
    }
4599
4600
0
      if (op >= MAX_OPERANDS)
4601
0
  abort ();
4602
0
    }
4603
4604
  /* The third byte of the EVEX prefix.  */
4605
0
  i.vex.bytes[2] = ((w << 7)
4606
0
        | (register_specifier << 3)
4607
0
        | 4 /* Encode the U bit.  */
4608
0
        | i.tm.opcode_modifier.opcodeprefix);
4609
4610
  /* The fourth byte of the EVEX prefix.  */
4611
  /* The zeroing-masking bit.  */
4612
0
  if (i.mask.reg && i.mask.zeroing)
4613
0
    i.vex.bytes[3] |= 0x80;
4614
4615
  /* Don't always set the broadcast bit if there is no RC.  */
4616
0
  if (i.rounding.type == rc_none)
4617
0
    {
4618
      /* Encode the vector length.  */
4619
0
      unsigned int vec_length;
4620
4621
0
      switch (i.tm.opcode_modifier.evex)
4622
0
  {
4623
0
  case EVEXLIG: /* LL' is ignored */
4624
0
    vec_length = evexlig << 5;
4625
0
    break;
4626
0
  case EVEX128:
4627
0
    vec_length = 0 << 5;
4628
0
    break;
4629
0
  case EVEX256:
4630
0
    vec_length = 1 << 5;
4631
0
    break;
4632
0
  case EVEX512:
4633
0
    vec_length = 2 << 5;
4634
0
    break;
4635
0
  case EVEX_L3:
4636
0
    if (dot_insn ())
4637
0
      {
4638
0
        vec_length = 3 << 5;
4639
0
        break;
4640
0
      }
4641
    /* Fall through.  */
4642
0
  default:
4643
0
    abort ();
4644
0
    break;
4645
0
  }
4646
0
      i.vex.bytes[3] |= vec_length;
4647
      /* Encode the broadcast bit.  */
4648
0
      if (i.broadcast.type || i.broadcast.bytes)
4649
0
  i.vex.bytes[3] |= 0x10;
4650
0
    }
4651
0
  else if (i.rounding.type != saeonly)
4652
0
    i.vex.bytes[3] |= 0x10 | (i.rounding.type << 5);
4653
0
  else
4654
0
    i.vex.bytes[3] |= 0x10 | (evexrcig << 5);
4655
4656
0
  if (i.mask.reg)
4657
0
    i.vex.bytes[3] |= i.mask.reg->reg_num;
4658
0
}
4659
4660
/* Build (2 bytes) rex2 prefix.
4661
   | D5h |
4662
   | m | R4 X4 B4 | W R X B |
4663
4664
   Rex2 reuses i.vex as they both encode i.tm.opcode_space in their prefixes.
4665
 */
4666
static void
4667
build_rex2_prefix (void)
4668
0
{
4669
0
  i.vex.length = 2;
4670
0
  i.vex.bytes[0] = 0xd5;
4671
  /* For the W R X B bits, the variables of rex prefix will be reused.  */
4672
0
  i.vex.bytes[1] = ((i.tm.opcode_space << 7)
4673
0
        | (i.rex2 << 4)
4674
0
        | ((i.rex | i.prefix[REX_PREFIX]) & 0xf));
4675
0
}
4676
4677
/* Build the EVEX prefix (4-byte) for evex insn
4678
   | 62h |
4679
   | `R`X`B`R' | B'mmm |
4680
   | W | v`v`v`v | `x' | pp |
4681
   | z| L'L | b | `v | aaa |
4682
*/
4683
static bool
4684
build_apx_evex_prefix (bool force_nd)
4685
0
{
4686
  /* To mimic behavior for legacy insns, transform use of DATA16 and REX64 into
4687
     their embedded-prefix representations.  */
4688
0
  if (i.tm.opcode_space == SPACE_MAP4)
4689
0
    {
4690
0
      if (i.prefix[DATA_PREFIX])
4691
0
  {
4692
0
    if (i.tm.opcode_modifier.opcodeprefix)
4693
0
      {
4694
0
        as_bad (i.tm.opcode_modifier.opcodeprefix == PREFIX_0X66
4695
0
          ? _("same type of prefix used twice")
4696
0
          : _("conflicting use of `data16' prefix"));
4697
0
        return false;
4698
0
      }
4699
0
    i.tm.opcode_modifier.opcodeprefix = PREFIX_0X66;
4700
0
    i.prefix[DATA_PREFIX] = 0;
4701
0
  }
4702
0
      if (i.prefix[REX_PREFIX] & REX_W)
4703
0
  {
4704
0
    if (i.suffix == QWORD_MNEM_SUFFIX)
4705
0
      {
4706
0
        as_bad (_("same type of prefix used twice"));
4707
0
        return false;
4708
0
      }
4709
0
    i.tm.opcode_modifier.vexw = VEXW1;
4710
0
    i.prefix[REX_PREFIX] = 0;
4711
0
  }
4712
0
    }
4713
4714
0
  build_evex_prefix ();
4715
0
  if (i.rex2 & REX_R)
4716
0
    i.vex.bytes[1] &= ~0x10;
4717
0
  if (i.rex2 & REX_B)
4718
0
    i.vex.bytes[1] |= 0x08;
4719
0
  if (i.rex2 & REX_X)
4720
0
    {
4721
0
      gas_assert (i.rm.mode != 3);
4722
0
      i.vex.bytes[2] &= ~0x04;
4723
0
    }
4724
0
  if (i.vex.register_specifier
4725
0
      && i.vex.register_specifier->reg_flags & RegRex2)
4726
0
    i.vex.bytes[3] &= ~0x08;
4727
4728
  /* Encode the NDD bit of the instruction promoted from the legacy
4729
     space. ZU shares the same bit with NDD.  */
4730
0
  if ((i.vex.register_specifier && i.tm.opcode_space == SPACE_MAP4)
4731
0
      || i.tm.opcode_modifier.operandconstraint == ZERO_UPPER
4732
0
      || force_nd)
4733
0
    i.vex.bytes[3] |= 0x10;
4734
4735
  /* Encode SCC and oszc flags bits.  */
4736
0
  if (i.tm.opcode_modifier.operandconstraint == SCC)
4737
0
    {
4738
      /* The default value of vvvv is 1111 and needs to be cleared.  */
4739
0
      i.vex.bytes[2] &= ~0x78;
4740
0
      i.vex.bytes[2] |= (i.oszc_flags << 3);
4741
      /* ND and aaa bits shold be 0.  */
4742
0
      know (!(i.vex.bytes[3] & 0x17));
4743
      /* The default value of V' is 1 and needs to be cleared.  */
4744
0
      i.vex.bytes[3] = (i.vex.bytes[3] & ~0x08) | i.scc;
4745
0
    }
4746
4747
  /* Encode the NF bit.  */
4748
0
  if (pp.has_nf || i.tm.opcode_modifier.operandconstraint == EVEX_NF)
4749
0
    i.vex.bytes[3] |= 0x04;
4750
4751
0
  return true;
4752
0
}
4753
4754
static void establish_rex (void)
4755
0
{
4756
  /* Note that legacy encodings have at most 2 non-immediate operands.  */
4757
0
  unsigned int first = i.imm_operands;
4758
0
  unsigned int last = i.operands > first ? i.operands - first - 1 : first;
4759
4760
  /* Respect a user-specified REX prefix.  */
4761
0
  i.rex |= i.prefix[REX_PREFIX] & REX_OPCODE;
4762
4763
  /* For 8 bit RegRex64 registers without a prefix, we need an empty rex prefix.  */
4764
0
  if (((i.types[first].bitfield.class == Reg
4765
0
  && (i.op[first].regs->reg_flags & RegRex64) != 0)
4766
0
       || (i.types[last].bitfield.class == Reg
4767
0
     && (i.op[last].regs->reg_flags & RegRex64) != 0))
4768
0
      && !is_apx_rex2_encoding () && !is_any_vex_encoding (&i.tm))
4769
0
    i.rex |= REX_OPCODE;
4770
4771
  /* For REX/REX2/EVEX prefix instructions, we need to convert old registers
4772
     (AL, CL, DL and BL) to new ones (AXL, CXL, DXL and BXL) and reject AH,
4773
     CH, DH and BH.  */
4774
0
  if (i.rex || i.rex2 || i.tm.opcode_modifier.evex)
4775
0
    {
4776
0
      for (unsigned int x = first; x <= last; x++)
4777
0
  {
4778
    /* Look for 8 bit operand that uses old registers.  */
4779
0
    if (i.types[x].bitfield.class == Reg && i.types[x].bitfield.byte
4780
0
        && !(i.op[x].regs->reg_flags & (RegRex | RegRex2 | RegRex64)))
4781
0
      {
4782
        /* In case it is "hi" register, give up.  */
4783
0
        if (i.op[x].regs->reg_num > 3)
4784
0
    as_bad (_("can't encode register '%s%s' in an "
4785
0
        "instruction requiring %s prefix"),
4786
0
      register_prefix, i.op[x].regs->reg_name,
4787
0
      i.tm.opcode_modifier.evex ? "EVEX" : "REX/REX2");
4788
4789
        /* Otherwise it is equivalent to the extended register.
4790
     Since the encoding doesn't change this is merely
4791
     cosmetic cleanup for debug output.  */
4792
0
        i.op[x].regs += 8;
4793
0
      }
4794
0
  }
4795
0
    }
4796
4797
0
  if (i.rex == 0 && i.rex2 == 0 && (pp.rex_encoding || pp.rex2_encoding))
4798
0
    {
4799
      /* Check if we can add a REX_OPCODE byte.  Look for 8 bit operand
4800
   that uses legacy register.  If it is "hi" register, don't add
4801
   rex and rex2 prefix.  */
4802
0
      unsigned int x;
4803
4804
0
      for (x = first; x <= last; x++)
4805
0
  if (i.types[x].bitfield.class == Reg
4806
0
      && i.types[x].bitfield.byte
4807
0
      && !(i.op[x].regs->reg_flags & (RegRex | RegRex2 | RegRex64))
4808
0
      && i.op[x].regs->reg_num > 3)
4809
0
    {
4810
0
      pp.rex_encoding = false;
4811
0
      pp.rex2_encoding = false;
4812
0
      break;
4813
0
    }
4814
4815
0
      if (pp.rex_encoding)
4816
0
  i.rex = REX_OPCODE;
4817
0
    }
4818
4819
0
  if (is_apx_rex2_encoding ())
4820
0
    {
4821
      /* Most prefixes are not permitted with JMPABS.  */
4822
0
      if (i.tm.mnem_off == MN_jmpabs)
4823
0
  {
4824
0
    if (i.prefix[DATA_PREFIX] || (i.prefix[REX_PREFIX] & REX_W))
4825
0
      {
4826
0
        as_bad (_("size override not allowed with `%s'"),
4827
0
          insn_name (&i.tm));
4828
0
        i.prefix[DATA_PREFIX] = 0;
4829
0
        i.prefix[REX_PREFIX] &= ~REX_W;
4830
0
      }
4831
0
    if (i.prefix[ADDR_PREFIX])
4832
0
      {
4833
0
        as_bad (_("address override not allowed with `%s'"),
4834
0
          insn_name (&i.tm));
4835
0
        i.prefix[ADDR_PREFIX] = 0;
4836
0
      }
4837
0
  }
4838
4839
0
      build_rex2_prefix ();
4840
      /* The individual REX.RXBW bits got consumed.  */
4841
0
      i.rex &= REX_OPCODE;
4842
0
      i.prefix[REX_PREFIX] = 0;
4843
0
    }
4844
0
  else if (i.rex != 0)
4845
0
    add_prefix (REX_OPCODE | i.rex);
4846
0
}
4847
4848
static void
4849
process_immext (void)
4850
0
{
4851
0
  expressionS *exp;
4852
4853
  /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
4854
     which is coded in the same place as an 8-bit immediate field
4855
     would be.  Here we fake an 8-bit immediate operand from the
4856
     opcode suffix stored in tm.extension_opcode.
4857
4858
     AVX instructions also use this encoding, for some of
4859
     3 argument instructions.  */
4860
4861
0
  gas_assert (i.imm_operands <= 1
4862
0
        && (i.operands <= 2
4863
0
      || (is_any_vex_encoding (&i.tm)
4864
0
          && i.operands <= 4)));
4865
4866
0
  exp = &im_expressions[i.imm_operands++];
4867
0
  i.op[i.operands].imms = exp;
4868
0
  i.types[i.operands].bitfield.imm8 = 1;
4869
0
  i.operands++;
4870
0
  exp->X_op = O_constant;
4871
0
  exp->X_add_number = i.tm.extension_opcode;
4872
0
  i.tm.extension_opcode = None;
4873
0
}
4874
4875
4876
static int
4877
check_hle (void)
4878
0
{
4879
0
  switch (i.tm.opcode_modifier.prefixok)
4880
0
    {
4881
0
    default:
4882
0
      abort ();
4883
0
    case PrefixLock:
4884
0
    case PrefixNone:
4885
0
    case PrefixNoTrack:
4886
0
    case PrefixRep:
4887
0
      as_bad (_("invalid instruction `%s' after `%s'"),
4888
0
        insn_name (&i.tm), i.hle_prefix);
4889
0
      return 0;
4890
0
    case PrefixHLELock:
4891
0
      if (i.prefix[LOCK_PREFIX])
4892
0
  return 1;
4893
0
      as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
4894
0
      return 0;
4895
0
    case PrefixHLEAny:
4896
0
      return 1;
4897
0
    case PrefixHLERelease:
4898
0
      if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
4899
0
  {
4900
0
    as_bad (_("instruction `%s' after `xacquire' not allowed"),
4901
0
      insn_name (&i.tm));
4902
0
    return 0;
4903
0
  }
4904
0
      if (i.mem_operands == 0 || !(i.flags[i.operands - 1] & Operand_Mem))
4905
0
  {
4906
0
    as_bad (_("memory destination needed for instruction `%s'"
4907
0
        " after `xrelease'"), insn_name (&i.tm));
4908
0
    return 0;
4909
0
  }
4910
0
      return 1;
4911
0
    }
4912
0
}
4913
4914
/* Helper for optimization (running ahead of process_suffix()), to make sure we
4915
   convert only well-formed insns.  @OP is the sized operand to cross check
4916
   against (typically a register).  Checking against a single operand typically
4917
   suffices, as match_template() has already honored CheckOperandSize.  */
4918
4919
static bool is_plausible_suffix (unsigned int op)
4920
0
{
4921
0
  return !i.suffix
4922
0
   || (i.suffix == BYTE_MNEM_SUFFIX && i.types[op].bitfield.byte)
4923
0
   || (i.suffix == WORD_MNEM_SUFFIX && i.types[op].bitfield.word)
4924
0
   || (i.suffix == LONG_MNEM_SUFFIX && i.types[op].bitfield.dword)
4925
0
   || (i.suffix == QWORD_MNEM_SUFFIX && i.types[op].bitfield.qword);
4926
0
}
4927
4928
/* Encode aligned vector move as unaligned vector move.  */
4929
4930
static void
4931
encode_with_unaligned_vector_move (void)
4932
0
{
4933
0
  switch (i.tm.base_opcode)
4934
0
    {
4935
0
    case 0x28:  /* Load instructions.  */
4936
0
    case 0x29:  /* Store instructions.  */
4937
      /* movaps/movapd/vmovaps/vmovapd.  */
4938
0
      if (i.tm.opcode_space == SPACE_0F
4939
0
    && i.tm.opcode_modifier.opcodeprefix <= PREFIX_0X66)
4940
0
  i.tm.base_opcode = 0x10 | (i.tm.base_opcode & 1);
4941
0
      break;
4942
0
    case 0x6f:  /* Load instructions.  */
4943
0
    case 0x7f:  /* Store instructions.  */
4944
      /* movdqa/vmovdqa/vmovdqa64/vmovdqa32. */
4945
0
      if (i.tm.opcode_space == SPACE_0F
4946
0
    && i.tm.opcode_modifier.opcodeprefix == PREFIX_0X66)
4947
0
  i.tm.opcode_modifier.opcodeprefix = PREFIX_0XF3;
4948
0
      break;
4949
0
    default:
4950
0
      break;
4951
0
    }
4952
0
}
4953
4954
/* Try the shortest encoding by shortening operand size.  */
4955
4956
static void
4957
optimize_encoding (void)
4958
0
{
4959
0
  unsigned int j;
4960
4961
0
  if (i.tm.mnem_off == MN_lea)
4962
0
    {
4963
      /* Optimize: -O:
4964
     lea symbol, %rN    -> mov $symbol, %rN
4965
     lea (%rM), %rN     -> mov %rM, %rN
4966
     lea (,%rM,1), %rN  -> mov %rM, %rN
4967
4968
     and in 32-bit mode for 16-bit addressing
4969
4970
     lea (%rM), %rN     -> movzx %rM, %rN
4971
4972
     and in 64-bit mode zap 32-bit addressing in favor of using a
4973
     32-bit (or less) destination.
4974
       */
4975
0
      if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX])
4976
0
  {
4977
0
    if (!i.op[1].regs->reg_type.bitfield.word)
4978
0
      i.tm.opcode_modifier.size = SIZE32;
4979
0
    i.prefix[ADDR_PREFIX] = 0;
4980
0
  }
4981
4982
0
      if (!i.index_reg && !i.base_reg)
4983
0
  {
4984
    /* Handle:
4985
         lea symbol, %rN    -> mov $symbol, %rN
4986
     */
4987
0
    if (flag_code == CODE_64BIT)
4988
0
      {
4989
        /* Don't transform a relocation to a 16-bit one.  */
4990
0
        if (i.op[0].disps
4991
0
      && i.op[0].disps->X_op != O_constant
4992
0
      && i.op[1].regs->reg_type.bitfield.word)
4993
0
    return;
4994
4995
0
        if (!i.op[1].regs->reg_type.bitfield.qword
4996
0
      || i.tm.opcode_modifier.size == SIZE32)
4997
0
    {
4998
0
      i.tm.base_opcode = 0xb8;
4999
0
      i.tm.opcode_modifier.modrm = 0;
5000
0
      if (!i.op[1].regs->reg_type.bitfield.word)
5001
0
        i.types[0].bitfield.imm32 = 1;
5002
0
      else
5003
0
        {
5004
0
          i.tm.opcode_modifier.size = SIZE16;
5005
0
          i.types[0].bitfield.imm16 = 1;
5006
0
        }
5007
0
    }
5008
0
        else
5009
0
    {
5010
      /* Subject to further optimization below.  */
5011
0
      i.tm.base_opcode = 0xc7;
5012
0
      i.tm.extension_opcode = 0;
5013
0
      i.types[0].bitfield.imm32s = 1;
5014
0
      i.types[0].bitfield.baseindex = 0;
5015
0
    }
5016
0
      }
5017
    /* Outside of 64-bit mode address and operand sizes have to match if
5018
       a relocation is involved, as otherwise we wouldn't (currently) or
5019
       even couldn't express the relocation correctly.  */
5020
0
    else if (i.op[0].disps
5021
0
       && i.op[0].disps->X_op != O_constant
5022
0
       && ((!i.prefix[ADDR_PREFIX])
5023
0
           != (flag_code == CODE_32BIT
5024
0
         ? i.op[1].regs->reg_type.bitfield.dword
5025
0
         : i.op[1].regs->reg_type.bitfield.word)))
5026
0
      return;
5027
    /* In 16-bit mode converting LEA with 16-bit addressing and a 32-bit
5028
       destination is going to grow encoding size.  */
5029
0
    else if (flag_code == CODE_16BIT
5030
0
       && (optimize <= 1 || optimize_for_space)
5031
0
       && !i.prefix[ADDR_PREFIX]
5032
0
       && i.op[1].regs->reg_type.bitfield.dword)
5033
0
      return;
5034
0
    else
5035
0
      {
5036
0
        i.tm.base_opcode = 0xb8;
5037
0
        i.tm.opcode_modifier.modrm = 0;
5038
0
        if (i.op[1].regs->reg_type.bitfield.dword)
5039
0
    i.types[0].bitfield.imm32 = 1;
5040
0
        else
5041
0
    i.types[0].bitfield.imm16 = 1;
5042
5043
0
        if (i.op[0].disps
5044
0
      && i.op[0].disps->X_op == O_constant
5045
0
      && i.op[1].regs->reg_type.bitfield.dword
5046
      /* NB: Add () to !i.prefix[ADDR_PREFIX] to silence
5047
         GCC 5. */
5048
0
      && (!i.prefix[ADDR_PREFIX]) != (flag_code == CODE_32BIT))
5049
0
    i.op[0].disps->X_add_number &= 0xffff;
5050
0
      }
5051
5052
0
    i.tm.operand_types[0] = i.types[0];
5053
0
    i.imm_operands = 1;
5054
0
    if (!i.op[0].imms)
5055
0
      {
5056
0
        i.op[0].imms = &im_expressions[0];
5057
0
        i.op[0].imms->X_op = O_absent;
5058
0
      }
5059
0
  }
5060
0
      else if (i.op[0].disps
5061
0
      && (i.op[0].disps->X_op != O_constant
5062
0
          || i.op[0].disps->X_add_number))
5063
0
  return;
5064
0
      else
5065
0
  {
5066
    /* Handle:
5067
         lea (%rM), %rN     -> mov %rM, %rN
5068
         lea (,%rM,1), %rN  -> mov %rM, %rN
5069
         lea (%rM), %rN     -> movzx %rM, %rN
5070
     */
5071
0
    const reg_entry *addr_reg;
5072
5073
0
    if (!i.index_reg && i.base_reg->reg_num != RegIP)
5074
0
      addr_reg = i.base_reg;
5075
0
    else if (!i.base_reg
5076
0
       && i.index_reg->reg_num != RegIZ
5077
0
       && !i.log2_scale_factor)
5078
0
      addr_reg = i.index_reg;
5079
0
    else
5080
0
      return;
5081
5082
0
    if (addr_reg->reg_type.bitfield.word
5083
0
        && i.op[1].regs->reg_type.bitfield.dword)
5084
0
      {
5085
0
        if (flag_code != CODE_32BIT)
5086
0
    return;
5087
0
        i.tm.opcode_space = SPACE_0F;
5088
0
        i.tm.base_opcode = 0xb7;
5089
0
      }
5090
0
    else
5091
0
      i.tm.base_opcode = 0x8b;
5092
5093
0
    if (addr_reg->reg_type.bitfield.dword
5094
0
        && i.op[1].regs->reg_type.bitfield.qword)
5095
0
      i.tm.opcode_modifier.size = SIZE32;
5096
5097
0
    i.op[0].regs = addr_reg;
5098
0
    i.reg_operands = 2;
5099
0
  }
5100
5101
0
      i.mem_operands = 0;
5102
0
      i.disp_operands = 0;
5103
0
      i.prefix[ADDR_PREFIX] = 0;
5104
0
      i.prefix[SEG_PREFIX] = 0;
5105
0
      i.seg[0] = NULL;
5106
0
    }
5107
5108
0
  if (optimize_for_space
5109
0
      && (i.tm.mnem_off == MN_test
5110
0
          || (i.tm.base_opcode == 0xf6
5111
0
              && i.tm.opcode_space == SPACE_MAP4))
5112
0
      && i.reg_operands == 1
5113
0
      && i.imm_operands == 1
5114
0
      && !i.types[1].bitfield.byte
5115
0
      && is_plausible_suffix (1)
5116
0
      && i.op[0].imms->X_op == O_constant
5117
0
      && fits_in_imm7 (i.op[0].imms->X_add_number))
5118
0
    {
5119
      /* Optimize: -Os:
5120
     test      $imm7, %r64/%r32/%r16  -> test      $imm7, %r8
5121
     ctest<cc> $imm7, %r64/%r32/%r16  -> ctest<cc> $imm7, %r8
5122
       */
5123
0
      unsigned int base_regnum = i.op[1].regs->reg_num;
5124
5125
0
      gas_assert (!i.tm.opcode_modifier.modrm || i.tm.extension_opcode == 0);
5126
5127
0
      if (flag_code == CODE_64BIT || base_regnum < 4)
5128
0
  {
5129
0
    i.types[1].bitfield.byte = 1;
5130
    /* Squash the suffix.  */
5131
0
    i.suffix = 0;
5132
    /* Convert to byte registers. 8-bit registers are special,
5133
       RegRex64 and non-RegRex* each have 8 registers.  */
5134
0
    if (i.types[1].bitfield.word)
5135
      /* 32 (or 40) 8-bit registers.  */
5136
0
      j = 32;
5137
0
    else if (i.types[1].bitfield.dword)
5138
      /* 32 (or 40) 8-bit registers + 32 16-bit registers.  */
5139
0
      j = 64;
5140
0
    else
5141
      /* 32 (or 40) 8-bit registers + 32 16-bit registers
5142
         + 32 32-bit registers.  */
5143
0
      j = 96;
5144
5145
    /* In 64-bit mode, the following byte registers cannot be accessed
5146
       if using the Rex and Rex2 prefix: AH, BH, CH, DH */
5147
0
    if (!(i.op[1].regs->reg_flags & (RegRex | RegRex2)) && base_regnum < 4)
5148
0
      j += 8;
5149
0
    i.op[1].regs -= j;
5150
0
  }
5151
0
    }
5152
0
  else if (flag_code == CODE_64BIT
5153
0
     && i.tm.opcode_space == SPACE_BASE
5154
0
     && i.types[i.operands - 1].bitfield.qword
5155
0
     && ((i.reg_operands == 1
5156
0
    && i.imm_operands == 1
5157
0
    && i.op[0].imms->X_op == O_constant
5158
0
    && ((i.tm.base_opcode == 0xb8
5159
0
         && i.tm.extension_opcode == None
5160
0
         && fits_in_unsigned_long (i.op[0].imms->X_add_number))
5161
0
        || (fits_in_imm31 (i.op[0].imms->X_add_number)
5162
0
      && (i.tm.base_opcode == 0x24
5163
0
          || (((i.tm.base_opcode == 0x80
5164
0
          && i.tm.extension_opcode == 0x4)
5165
0
         || i.tm.mnem_off == MN_test)
5166
0
        && !(i.op[1].regs->reg_flags
5167
0
             & (RegRex | RegRex2)))
5168
0
          || ((i.tm.base_opcode | 1) == 0xc7
5169
0
        && i.tm.extension_opcode == 0x0)))
5170
0
        || (fits_in_imm7 (i.op[0].imms->X_add_number)
5171
0
      && i.tm.base_opcode == 0x83
5172
0
      && i.tm.extension_opcode == 0x4
5173
0
      && !(i.op[1].regs->reg_flags & (RegRex | RegRex2)))))
5174
0
         || ((i.reg_operands == 2
5175
0
        && i.op[0].regs == i.op[1].regs
5176
0
        && (i.tm.mnem_off == MN_xor
5177
0
      || i.tm.mnem_off == MN_sub))
5178
0
       || i.tm.mnem_off == MN_clr)))
5179
0
    {
5180
      /* Optimize: -O:
5181
     andq $imm31, %r64   -> andl $imm31, %r32
5182
     andq $imm7, %r64    -> andl $imm7, %r32
5183
     testq $imm31, %r64  -> testl $imm31, %r32
5184
     xorq %r64, %r64     -> xorl %r32, %r32
5185
     clrq %r64           -> clrl %r32
5186
     subq %r64, %r64     -> subl %r32, %r32
5187
     movq $imm31, %r64   -> movl $imm31, %r32
5188
     movq $imm32, %r64   -> movl $imm32, %r32
5189
        */
5190
0
      i.tm.opcode_modifier.size = SIZE32;
5191
0
      if (i.imm_operands)
5192
0
  {
5193
0
    i.types[0].bitfield.imm32 = 1;
5194
0
    i.types[0].bitfield.imm32s = 0;
5195
0
    i.types[0].bitfield.imm64 = 0;
5196
0
  }
5197
0
      else
5198
0
  {
5199
0
    i.types[0].bitfield.dword = 1;
5200
0
    i.types[0].bitfield.qword = 0;
5201
0
  }
5202
0
      i.types[1].bitfield.dword = 1;
5203
0
      i.types[1].bitfield.qword = 0;
5204
0
      if (i.tm.mnem_off == MN_mov || i.tm.mnem_off == MN_lea)
5205
0
  {
5206
    /* Handle
5207
         movq $imm31, %r64   -> movl $imm31, %r32
5208
         movq $imm32, %r64   -> movl $imm32, %r32
5209
     */
5210
0
    i.tm.operand_types[0].bitfield.imm32 = 1;
5211
0
    i.tm.operand_types[0].bitfield.imm32s = 0;
5212
0
    i.tm.operand_types[0].bitfield.imm64 = 0;
5213
0
    if ((i.tm.base_opcode | 1) == 0xc7)
5214
0
      {
5215
        /* Handle
5216
       movq $imm31, %r64   -> movl $imm31, %r32
5217
         */
5218
0
        i.tm.base_opcode = 0xb8;
5219
0
        i.tm.extension_opcode = None;
5220
0
        i.tm.opcode_modifier.w = 0;
5221
0
        i.tm.opcode_modifier.modrm = 0;
5222
0
      }
5223
0
  }
5224
0
    }
5225
0
  else if (i.reg_operands == 3
5226
0
     && i.op[0].regs == i.op[1].regs
5227
0
     && pp.encoding != encoding_evex
5228
0
     && (i.tm.mnem_off == MN_xor
5229
0
         || i.tm.mnem_off == MN_sub))
5230
0
    {
5231
      /* Optimize: -O:
5232
     xorb %rNb, %rNb, %rMb  -> xorl %rMd, %rMd
5233
     xorw %rNw, %rNw, %rMw  -> xorl %rMd, %rMd
5234
     xorl %rNd, %rNd, %rMd  -> xorl %rMd, %rMd
5235
     xorq %rN,  %rN,  %rM   -> xorl %rMd, %rMd
5236
     subb %rNb, %rNb, %rMb  -> subl %rMd, %rMd
5237
     subw %rNw, %rNw, %rMw  -> subl %rMd, %rMd
5238
     subl %rNd, %rNd, %rMd  -> subl %rMd, %rMd
5239
     subq %rN,  %rN,  %rM   -> subl %rMd, %rMd
5240
        */
5241
0
      i.tm.opcode_space = SPACE_BASE;
5242
0
      i.tm.opcode_modifier.evex = 0;
5243
0
      i.tm.opcode_modifier.size = SIZE32;
5244
0
      i.types[0].bitfield.byte = 0;
5245
0
      i.types[0].bitfield.word = 0;
5246
0
      i.types[0].bitfield.dword = 1;
5247
0
      i.types[0].bitfield.qword = 0;
5248
0
      i.op[0].regs = i.op[2].regs;
5249
0
      i.types[1] = i.types[0];
5250
0
      i.op[1].regs = i.op[2].regs;
5251
0
      i.reg_operands = 2;
5252
0
    }
5253
0
  else if (optimize > 1
5254
0
     && !optimize_for_space
5255
0
     && i.reg_operands == 2
5256
0
     && i.op[0].regs == i.op[1].regs
5257
0
     && (i.tm.mnem_off == MN_and || i.tm.mnem_off == MN_or)
5258
0
     && (flag_code != CODE_64BIT || !i.types[0].bitfield.dword))
5259
0
    {
5260
      /* Optimize: -O2:
5261
     andb %rN, %rN  -> testb %rN, %rN
5262
     andw %rN, %rN  -> testw %rN, %rN
5263
     andq %rN, %rN  -> testq %rN, %rN
5264
     orb %rN, %rN   -> testb %rN, %rN
5265
     orw %rN, %rN   -> testw %rN, %rN
5266
     orq %rN, %rN   -> testq %rN, %rN
5267
5268
     and outside of 64-bit mode
5269
5270
     andl %rN, %rN  -> testl %rN, %rN
5271
     orl %rN, %rN   -> testl %rN, %rN
5272
       */
5273
0
      i.tm.base_opcode = 0x84 | (i.tm.base_opcode & 1);
5274
0
    }
5275
0
  else if (!optimize_for_space
5276
0
     && i.tm.base_opcode == 0xd0
5277
0
     && i.tm.extension_opcode == 4
5278
0
     && (i.tm.opcode_space == SPACE_BASE
5279
0
         || i.tm.opcode_space == SPACE_MAP4)
5280
0
     && !i.mem_operands)
5281
0
    {
5282
      /* Optimize: -O:
5283
     shlb $1, %rN  -> addb %rN, %rN
5284
     shlw $1, %rN  -> addw %rN, %rN
5285
     shll $1, %rN  -> addl %rN, %rN
5286
     shlq $1, %rN  -> addq %rN, %rN
5287
5288
     shlb $1, %rN, %rM  -> addb %rN, %rN, %rM
5289
     shlw $1, %rN, %rM  -> addw %rN, %rN, %rM
5290
     shll $1, %rN, %rM  -> addl %rN, %rN, %rM
5291
     shlq $1, %rN, %rM  -> addq %rN, %rN, %rM
5292
       */
5293
0
      i.tm.base_opcode = 0x00;
5294
0
      i.tm.extension_opcode = None;
5295
0
      if (i.operands >= 2)
5296
0
  copy_operand (0, 1);
5297
0
      else
5298
0
  {
5299
    /* Legacy form with omitted shift count operand.  */
5300
0
    copy_operand (1, 0);
5301
0
    i.operands = 2;
5302
0
  }
5303
0
      i.reg_operands++;
5304
0
      i.imm_operands = 0;
5305
0
    }
5306
0
  else if (i.tm.base_opcode == 0xba
5307
0
     && i.tm.opcode_space == SPACE_0F
5308
0
     && i.reg_operands == 1
5309
0
     && i.op[0].imms->X_op == O_constant
5310
0
     && i.op[0].imms->X_add_number >= 0)
5311
0
    {
5312
      /* Optimize: -O:
5313
     btw $n, %rN -> btl $n, %rN (outside of 16-bit mode, n < 16)
5314
     btq $n, %rN -> btl $n, %rN (in 64-bit mode, n < 32, N < 8)
5315
     btl $n, %rN -> btw $n, %rN (in 16-bit mode, n < 16)
5316
5317
     With <BT> one of bts, btr, and bts also:
5318
     <BT>w $n, %rN -> btl $n, %rN (in 32-bit mode, n < 16)
5319
     <BT>l $n, %rN -> btw $n, %rN (in 16-bit mode, n < 16)
5320
       */
5321
0
      switch (flag_code)
5322
0
  {
5323
0
  case CODE_64BIT:
5324
0
    if (i.tm.extension_opcode != 4)
5325
0
      break;
5326
0
    if (i.types[1].bitfield.qword
5327
0
        && i.op[0].imms->X_add_number < 32
5328
0
        && !(i.op[1].regs->reg_flags & RegRex))
5329
0
      i.tm.opcode_modifier.size = SIZE32;
5330
    /* Fall through.  */
5331
0
  case CODE_32BIT:
5332
0
    if (i.types[1].bitfield.word
5333
0
        && i.op[0].imms->X_add_number < 16)
5334
0
      i.tm.opcode_modifier.size = SIZE32;
5335
0
    break;
5336
0
  case CODE_16BIT:
5337
0
    if (i.op[0].imms->X_add_number < 16)
5338
0
      i.tm.opcode_modifier.size = SIZE16;
5339
0
    break;
5340
0
  }
5341
0
    }
5342
0
  else if (optimize > 1
5343
0
     && (i.tm.base_opcode | 0xf) == 0x4f
5344
0
     && i.tm.opcode_space == SPACE_MAP4
5345
0
     && i.reg_operands == 3
5346
0
     && i.tm.opcode_modifier.operandconstraint == EVEX_NF
5347
0
     && !i.types[0].bitfield.word)
5348
0
    {
5349
      /* Optimize: -O2:
5350
     cfcmov<cc> %rM, %rN, %rN -> cmov<cc> %rM, %rN
5351
     cfcmov<cc> %rM, %rN, %rM -> cmov<!cc> %rN, %rM
5352
     cfcmov<cc> %rN, %rN, %rN -> nop %rN
5353
       */
5354
0
      if (i.op[0].regs == i.op[2].regs)
5355
0
  {
5356
0
    i.tm.base_opcode ^= 1;
5357
0
    i.op[0].regs = i.op[1].regs;
5358
0
    i.op[1].regs = i.op[2].regs;
5359
0
  }
5360
0
      else if (i.op[1].regs != i.op[2].regs)
5361
0
  return;
5362
5363
0
      i.tm.opcode_space = SPACE_0F;
5364
0
      i.tm.opcode_modifier.evex = 0;
5365
0
      i.tm.opcode_modifier.vexvvvv = 0;
5366
0
      i.tm.opcode_modifier.operandconstraint = 0;
5367
0
      i.reg_operands = 2;
5368
5369
      /* While at it, convert to NOP if all three regs match.  */
5370
0
      if (i.op[0].regs == i.op[1].regs)
5371
0
  {
5372
0
    i.tm.base_opcode = 0x1f;
5373
0
    i.tm.extension_opcode = 0;
5374
0
    i.reg_operands = 1;
5375
0
  }
5376
0
    }
5377
0
  else if (i.reg_operands == 3
5378
0
     && i.op[0].regs == i.op[1].regs
5379
0
     && !i.types[2].bitfield.xmmword
5380
0
     && (i.tm.opcode_modifier.vex
5381
0
         || ((!i.mask.reg || i.mask.zeroing)
5382
0
       && i.tm.opcode_modifier.evex
5383
0
       && (pp.encoding != encoding_evex
5384
0
           || cpu_arch_isa_flags.bitfield.cpuavx512vl
5385
0
           || is_cpu (&i.tm, CpuAVX512VL)
5386
0
           || (i.tm.operand_types[2].bitfield.zmmword
5387
0
         && i.types[2].bitfield.ymmword))))
5388
0
     && i.tm.opcode_space == SPACE_0F
5389
0
     && ((i.tm.base_opcode | 2) == 0x57
5390
0
         || i.tm.base_opcode == 0xdf
5391
0
         || i.tm.base_opcode == 0xef
5392
0
         || (i.tm.base_opcode | 3) == 0xfb
5393
0
         || i.tm.base_opcode == 0x42
5394
0
         || i.tm.base_opcode == 0x47))
5395
0
    {
5396
      /* Optimize: -O1:
5397
     VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
5398
     vpsubq and vpsubw:
5399
       EVEX VOP %zmmM, %zmmM, %zmmN
5400
         -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
5401
         -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
5402
       EVEX VOP %ymmM, %ymmM, %ymmN
5403
         -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
5404
         -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
5405
       VEX VOP %ymmM, %ymmM, %ymmN
5406
         -> VEX VOP %xmmM, %xmmM, %xmmN
5407
     VOP, one of vpandn and vpxor:
5408
       VEX VOP %ymmM, %ymmM, %ymmN
5409
         -> VEX VOP %xmmM, %xmmM, %xmmN
5410
     VOP, one of vpandnd and vpandnq:
5411
       EVEX VOP %zmmM, %zmmM, %zmmN
5412
         -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
5413
         -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
5414
       EVEX VOP %ymmM, %ymmM, %ymmN
5415
         -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
5416
         -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
5417
     VOP, one of vpxord and vpxorq:
5418
       EVEX VOP %zmmM, %zmmM, %zmmN
5419
         -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
5420
         -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
5421
       EVEX VOP %ymmM, %ymmM, %ymmN
5422
         -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
5423
         -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
5424
     VOP, one of kxord and kxorq:
5425
       VEX VOP %kM, %kM, %kN
5426
         -> VEX kxorw %kM, %kM, %kN
5427
     VOP, one of kandnd and kandnq:
5428
       VEX VOP %kM, %kM, %kN
5429
         -> VEX kandnw %kM, %kM, %kN
5430
       */
5431
0
      if (i.tm.opcode_modifier.evex)
5432
0
  {
5433
0
    if (pp.encoding != encoding_evex)
5434
0
      {
5435
0
        i.tm.opcode_modifier.vex = VEX128;
5436
0
        i.tm.opcode_modifier.vexw = VEXW0;
5437
0
        i.tm.opcode_modifier.evex = 0;
5438
0
        pp.encoding = encoding_vex;
5439
0
        i.mask.reg = NULL;
5440
0
      }
5441
0
    else if (optimize > 1)
5442
0
      i.tm.opcode_modifier.evex = EVEX128;
5443
0
    else
5444
0
      return;
5445
0
  }
5446
0
      else if (i.tm.operand_types[0].bitfield.class == RegMask)
5447
0
  {
5448
0
    i.tm.opcode_modifier.opcodeprefix = PREFIX_NONE;
5449
0
    i.tm.opcode_modifier.vexw = VEXW0;
5450
0
  }
5451
0
      else
5452
0
  i.tm.opcode_modifier.vex = VEX128;
5453
5454
0
      if (i.tm.opcode_modifier.vex)
5455
0
  for (j = 0; j < 3; j++)
5456
0
    {
5457
0
      i.types[j].bitfield.xmmword = 1;
5458
0
      i.types[j].bitfield.ymmword = 0;
5459
0
    }
5460
0
    }
5461
0
  else if (pp.encoding != encoding_evex
5462
0
     && pp.encoding != encoding_egpr
5463
0
     && !i.types[0].bitfield.zmmword
5464
0
     && !i.types[1].bitfield.zmmword
5465
0
     && !i.mask.reg
5466
0
     && !i.broadcast.type
5467
0
     && !i.broadcast.bytes
5468
0
     && i.tm.opcode_modifier.evex
5469
0
     && ((i.tm.base_opcode & ~Opcode_SIMD_IntD) == 0x6f
5470
0
         || (i.tm.base_opcode & ~4) == 0xdb
5471
0
         || (i.tm.base_opcode & ~4) == 0xeb)
5472
0
     && i.tm.extension_opcode == None)
5473
0
    {
5474
      /* Optimize: -O1:
5475
     VOP, one of vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16,
5476
     vmovdqu32 and vmovdqu64:
5477
       EVEX VOP %xmmM, %xmmN
5478
         -> VEX vmovdqa|vmovdqu %xmmM, %xmmN (M and N < 16)
5479
       EVEX VOP %ymmM, %ymmN
5480
         -> VEX vmovdqa|vmovdqu %ymmM, %ymmN (M and N < 16)
5481
       EVEX VOP %xmmM, mem
5482
         -> VEX vmovdqa|vmovdqu %xmmM, mem (M < 16)
5483
       EVEX VOP %ymmM, mem
5484
         -> VEX vmovdqa|vmovdqu %ymmM, mem (M < 16)
5485
       EVEX VOP mem, %xmmN
5486
         -> VEX mvmovdqa|vmovdquem, %xmmN (N < 16)
5487
       EVEX VOP mem, %ymmN
5488
         -> VEX vmovdqa|vmovdqu mem, %ymmN (N < 16)
5489
     VOP, one of vpand, vpandn, vpor, vpxor:
5490
       EVEX VOP{d,q} %xmmL, %xmmM, %xmmN
5491
         -> VEX VOP %xmmL, %xmmM, %xmmN (L, M, and N < 16)
5492
       EVEX VOP{d,q} %ymmL, %ymmM, %ymmN
5493
         -> VEX VOP %ymmL, %ymmM, %ymmN (L, M, and N < 16)
5494
       EVEX VOP{d,q} mem, %xmmM, %xmmN
5495
         -> VEX VOP mem, %xmmM, %xmmN (M and N < 16)
5496
       EVEX VOP{d,q} mem, %ymmM, %ymmN
5497
         -> VEX VOP mem, %ymmM, %ymmN (M and N < 16)
5498
       */
5499
0
      for (j = 0; j < i.operands; j++)
5500
0
  if (operand_type_check (i.types[j], disp)
5501
0
      && i.op[j].disps->X_op == O_constant)
5502
0
    {
5503
      /* Since the VEX prefix has 2 or 3 bytes, the EVEX prefix
5504
         has 4 bytes, EVEX Disp8 has 1 byte and VEX Disp32 has 4
5505
         bytes, we choose EVEX Disp8 over VEX Disp32.  */
5506
0
      int evex_disp8, vex_disp8;
5507
0
      unsigned int memshift = i.memshift;
5508
0
      offsetT n = i.op[j].disps->X_add_number;
5509
5510
0
      evex_disp8 = fits_in_disp8 (n);
5511
0
      i.memshift = 0;
5512
0
      vex_disp8 = fits_in_disp8 (n);
5513
0
      if (evex_disp8 != vex_disp8)
5514
0
        {
5515
0
    i.memshift = memshift;
5516
0
    return;
5517
0
        }
5518
5519
0
      i.types[j].bitfield.disp8 = vex_disp8;
5520
0
      break;
5521
0
    }
5522
0
      if ((i.tm.base_opcode & ~Opcode_SIMD_IntD) == 0x6f
5523
0
    && i.tm.opcode_modifier.opcodeprefix == PREFIX_0XF2)
5524
0
  i.tm.opcode_modifier.opcodeprefix = PREFIX_0XF3;
5525
0
      i.tm.opcode_modifier.vex
5526
0
  = i.types[0].bitfield.ymmword ? VEX256 : VEX128;
5527
0
      i.tm.opcode_modifier.vexw = VEXW0;
5528
      /* VPAND, VPOR, and VPXOR are commutative.  */
5529
0
      if (i.reg_operands == 3 && i.tm.base_opcode != 0xdf)
5530
0
  i.tm.opcode_modifier.commutative = 1;
5531
0
      i.tm.opcode_modifier.evex = 0;
5532
0
      i.tm.opcode_modifier.masking = 0;
5533
0
      i.tm.opcode_modifier.broadcast = 0;
5534
0
      i.tm.opcode_modifier.disp8memshift = 0;
5535
0
      i.memshift = 0;
5536
0
      if (j < i.operands)
5537
0
  i.types[j].bitfield.disp8
5538
0
    = fits_in_disp8 (i.op[j].disps->X_add_number);
5539
0
    }
5540
0
  else if (optimize_for_space
5541
0
     && i.tm.base_opcode == 0x29
5542
0
     && i.tm.opcode_space == SPACE_0F38
5543
0
     && i.operands == i.reg_operands
5544
0
     && i.op[0].regs == i.op[1].regs
5545
0
     && (!i.tm.opcode_modifier.vex
5546
0
         || !(i.op[0].regs->reg_flags & RegRex))
5547
0
     && !i.tm.opcode_modifier.evex)
5548
0
    {
5549
      /* Optimize: -Os:
5550
         pcmpeqq %xmmN, %xmmN          -> pcmpeqd %xmmN, %xmmN
5551
         vpcmpeqq %xmmN, %xmmN, %xmmM  -> vpcmpeqd %xmmN, %xmmN, %xmmM (N < 8)
5552
         vpcmpeqq %ymmN, %ymmN, %ymmM  -> vpcmpeqd %ymmN, %ymmN, %ymmM (N < 8)
5553
       */
5554
0
      i.tm.opcode_space = SPACE_0F;
5555
0
      i.tm.base_opcode = 0x76;
5556
0
    }
5557
0
  else if (((i.tm.base_opcode >= 0x64
5558
0
       && i.tm.base_opcode <= 0x66
5559
0
       && i.tm.opcode_space == SPACE_0F)
5560
0
      || (i.tm.base_opcode == 0x37
5561
0
    && i.tm.opcode_space == SPACE_0F38))
5562
0
     && i.operands == i.reg_operands
5563
0
     && i.op[0].regs == i.op[1].regs
5564
0
     && !i.tm.opcode_modifier.evex)
5565
0
    {
5566
      /* Optimize: -O:
5567
         pcmpgt[bwd] %mmN, %mmN             -> pxor %mmN, %mmN
5568
         pcmpgt[bwdq] %xmmN, %xmmN          -> pxor %xmmN, %xmmN
5569
         vpcmpgt[bwdq] %xmmN, %xmmN, %xmmM  -> vpxor %xmmN, %xmmN, %xmmM (N < 8)
5570
         vpcmpgt[bwdq] %xmmN, %xmmN, %xmmM  -> vpxor %xmm0, %xmm0, %xmmM (N > 7)
5571
         vpcmpgt[bwdq] %ymmN, %ymmN, %ymmM  -> vpxor %ymmN, %ymmN, %ymmM (N < 8)
5572
         vpcmpgt[bwdq] %ymmN, %ymmN, %ymmM  -> vpxor %ymm0, %ymm0, %ymmM (N > 7)
5573
       */
5574
0
      i.tm.opcode_space = SPACE_0F;
5575
0
      i.tm.base_opcode = 0xef;
5576
0
      if (i.tm.opcode_modifier.vex && (i.op[0].regs->reg_flags & RegRex))
5577
0
  {
5578
0
    if (i.operands == 2)
5579
0
      {
5580
0
        gas_assert (i.tm.opcode_modifier.sse2avx);
5581
5582
0
        i.operands = 3;
5583
0
        i.reg_operands = 3;
5584
0
        i.tm.operands = 3;
5585
5586
0
        copy_operand (2, 0);
5587
5588
0
        i.tm.opcode_modifier.sse2avx = 0;
5589
0
      }
5590
0
    i.op[0].regs -= i.op[0].regs->reg_num + 8;
5591
0
    i.op[1].regs = i.op[0].regs;
5592
0
  }
5593
0
    }
5594
0
  else if (i.tm.extension_opcode == 6
5595
0
     && i.tm.base_opcode >= 0x71
5596
0
     && i.tm.base_opcode <= 0x73
5597
0
     && i.tm.opcode_space == SPACE_0F
5598
0
     && i.op[0].imms->X_op == O_constant
5599
0
     && i.op[0].imms->X_add_number == 1
5600
0
     && !i.mem_operands)
5601
0
    {
5602
      /* Optimize: -O:
5603
     psllw $1, %mmxN          -> paddw %mmxN, %mmxN
5604
     psllw $1, %xmmN          -> paddw %xmmN, %xmmN
5605
     vpsllw $1, %xmmN, %xmmM  -> vpaddw %xmmN, %xmmN, %xmmM
5606
     vpsllw $1, %ymmN, %ymmM  -> vpaddw %ymmN, %ymmN, %ymmM
5607
     vpsllw $1, %zmmN, %zmmM  -> vpaddw %zmmN, %zmmN, %zmmM
5608
5609
     pslld $1, %mmxN          -> paddd %mmxN, %mmxN
5610
     pslld $1, %xmmN          -> paddd %xmmN, %xmmN
5611
     vpslld $1, %xmmN, %xmmM  -> vpaddd %xmmN, %xmmN, %xmmM
5612
     vpslld $1, %ymmN, %ymmM  -> vpaddd %ymmN, %ymmN, %ymmM
5613
     vpslld $1, %zmmN, %zmmM  -> vpaddd %zmmN, %zmmN, %zmmM
5614
5615
     psllq $1, %xmmN          -> paddq %xmmN, %xmmN
5616
     vpsllq $1, %xmmN, %xmmM  -> vpaddq %xmmN, %xmmN, %xmmM
5617
     vpsllq $1, %ymmN, %ymmM  -> vpaddq %ymmN, %ymmN, %ymmM
5618
     vpsllq $1, %zmmN, %zmmM  -> vpaddq %zmmN, %zmmN, %zmmM
5619
    */
5620
0
      if (i.tm.base_opcode != 0x73)
5621
0
  i.tm.base_opcode |= 0xfc; /* {,v}padd{w,d} */
5622
0
      else
5623
0
  {
5624
0
    gas_assert (i.tm.operand_types[1].bitfield.class != RegMMX);
5625
0
    i.tm.base_opcode = 0xd4; /* {,v}paddq */
5626
0
  }
5627
0
      i.tm.extension_opcode = None;
5628
0
      if (i.tm.opcode_modifier.vexvvvv)
5629
0
  i.tm.opcode_modifier.vexvvvv = VexVVVV_SRC1;
5630
0
      copy_operand (0, 1);
5631
0
      i.reg_operands++;
5632
0
      i.imm_operands = 0;
5633
0
    }
5634
0
  else if (optimize_for_space
5635
0
     && i.tm.base_opcode == 0x59
5636
0
     && i.tm.opcode_space == SPACE_0F38
5637
0
     && i.operands == i.reg_operands
5638
0
     && i.tm.opcode_modifier.vex
5639
0
     && !(i.op[0].regs->reg_flags & RegRex)
5640
0
     && i.op[0].regs->reg_type.bitfield.xmmword
5641
0
     && pp.encoding != encoding_vex3)
5642
0
    {
5643
      /* Optimize: -Os:
5644
         vpbroadcastq %xmmN, %xmmM  -> vpunpcklqdq %xmmN, %xmmN, %xmmM (N < 8)
5645
       */
5646
0
      i.tm.opcode_space = SPACE_0F;
5647
0
      i.tm.base_opcode = 0x6c;
5648
0
      i.tm.opcode_modifier.vexvvvv = VexVVVV_SRC1;
5649
5650
0
      ++i.operands;
5651
0
      ++i.reg_operands;
5652
0
      ++i.tm.operands;
5653
5654
0
      copy_operand (2, 0);
5655
0
      swap_2_operands (1, 2);
5656
0
    }
5657
0
  else if (i.tm.base_opcode == 0x16
5658
0
     && i.tm.opcode_space == SPACE_0F3A
5659
0
     && i.op[0].imms->X_op == O_constant
5660
0
     && i.op[0].imms->X_add_number == 0)
5661
0
    {
5662
      /* Optimize: -O:
5663
         pextrd $0, %xmmN, ...   -> movd %xmmN, ...
5664
         pextrq $0, %xmmN, ...   -> movq %xmmN, ...
5665
         vpextrd $0, %xmmN, ...  -> vmovd %xmmN, ...
5666
         vpextrq $0, %xmmN, ...  -> vmovq %xmmN, ...
5667
       */
5668
0
      i.tm.opcode_space = SPACE_0F;
5669
0
      if (!i.mem_operands
5670
0
    || i.tm.opcode_modifier.evex
5671
0
    || (i.tm.opcode_modifier.vexw != VEXW1
5672
0
        && i.tm.opcode_modifier.size != SIZE64))
5673
0
  i.tm.base_opcode = 0x7e;
5674
0
      else
5675
0
  {
5676
0
    i.tm.base_opcode = 0xd6;
5677
0
    i.tm.opcode_modifier.size = 0;
5678
0
    i.tm.opcode_modifier.vexw
5679
0
      = i.tm.opcode_modifier.sse2avx ? VEXW0 : VEXWIG;
5680
0
  }
5681
5682
0
      copy_operand (0, 1);
5683
0
      copy_operand (1, 2);
5684
5685
0
      i.operands = 2;
5686
0
      i.imm_operands = 0;
5687
0
    }
5688
0
  else if (i.tm.base_opcode == 0x17
5689
0
     && i.tm.opcode_space == SPACE_0F3A
5690
0
     && i.op[0].imms->X_op == O_constant
5691
0
     && i.op[0].imms->X_add_number == 0)
5692
0
    {
5693
      /* Optimize: -O:
5694
         extractps $0, %xmmN, %rM   -> movd %xmmN, %rM
5695
         extractps $0, %xmmN, mem   -> movss %xmmN, mem
5696
         vextractps $0, %xmmN, %rM  -> vmovd %xmmN, %rM
5697
         vextractps $0, %xmmN, mem  -> vmovss %xmmN, mem
5698
       */
5699
0
      i.tm.opcode_space = SPACE_0F;
5700
0
      i.tm.opcode_modifier.vexw = VEXW0;
5701
5702
0
      if (!i.mem_operands)
5703
0
  i.tm.base_opcode = 0x7e;
5704
0
      else
5705
0
  {
5706
0
    i.tm.base_opcode = 0x11;
5707
0
    i.tm.opcode_modifier.opcodeprefix = PREFIX_0XF3;
5708
0
  }
5709
5710
0
      copy_operand (0, 1);
5711
0
      copy_operand (1, 2);
5712
5713
0
      i.operands = 2;
5714
0
      i.imm_operands = 0;
5715
0
    }
5716
0
  else if ((i.tm.base_opcode | 0x22) == 0x3b
5717
0
     && i.tm.opcode_space == SPACE_0F3A
5718
0
     && i.op[0].imms->X_op == O_constant
5719
0
     && i.op[0].imms->X_add_number == 0)
5720
0
    {
5721
      /* Optimize: -O:
5722
         vextractf128 $0, %ymmN, %xmmM      -> vmovaps %xmmN, %xmmM
5723
         vextractf128 $0, %ymmN, mem        -> vmovups %xmmN, mem
5724
         vextractf32x4 $0, %[yz]mmN, %xmmM  -> vmovaps %xmmN, %xmmM
5725
         vextractf32x4 $0, %[yz]mmN, mem    -> vmovups %xmmN, mem
5726
         vextractf64x2 $0, %[yz]mmN, %xmmM  -> vmovapd %xmmN, %xmmM
5727
         vextractf64x2 $0, %[yz]mmN, mem    -> vmovupd %xmmN, mem
5728
         vextractf32x8 $0, %zmmN, %ymmM     -> vmovaps %ymmN, %ymmM
5729
         vextractf32x8 $0, %zmmN, mem       -> vmovups %ymmN, mem
5730
         vextractf64x4 $0, %zmmN, %ymmM     -> vmovapd %ymmN, %ymmM
5731
         vextractf64x4 $0, %zmmN, mem       -> vmovupd %ymmN, mem
5732
         vextracti128 $0, %ymmN, %xmmM      -> vmovdqa %xmmN, %xmmM
5733
         vextracti128 $0, %ymmN, mem        -> vmovdqu %xmmN, mem
5734
         vextracti32x4 $0, %[yz]mmN, %xmmM  -> vmovdqa{,32} %xmmN, %xmmM
5735
         vextracti32x4 $0, %[yz]mmN, mem    -> vmovdqu{,32} %xmmN, mem
5736
         vextracti64x2 $0, %[yz]mmN, %xmmM  -> vmovdqa{,64} %xmmN, %xmmM
5737
         vextracti64x2 $0, %[yz]mmN, mem    -> vmovdqu{,64} %xmmN, mem
5738
         vextracti32x8 $0, %zmmN, %ymmM     -> vmovdqa{,32} %ymmN, %ymmM
5739
         vextracti32x8 $0, %zmmN, mem       -> vmovdqu{,32} %ymmN, mem
5740
         vextracti64x4 $0, %zmmN, %ymmM     -> vmovdqa{,64} %ymmN, %ymmM
5741
         vextracti64x4 $0, %zmmN, mem       -> vmovdqu{,64} %ymmN, mem
5742
       */
5743
0
      i.tm.opcode_space = SPACE_0F;
5744
5745
0
      if (!i.mask.reg
5746
0
    && (pp.encoding <= encoding_vex3
5747
0
        || (pp.encoding == encoding_evex512
5748
0
      && (!i.base_reg || !(i.base_reg->reg_flags & RegRex2))
5749
0
      && (!i.index_reg || !(i.index_reg->reg_flags & RegRex2)))))
5750
0
  {
5751
0
    i.tm.opcode_modifier.vex = i.tm.base_opcode & 2 ? VEX256 : VEX128;
5752
0
    i.tm.opcode_modifier.evex = 0;
5753
0
  }
5754
0
      else
5755
0
  i.tm.opcode_modifier.evex = i.tm.base_opcode & 2 ? EVEX256 : EVEX128;
5756
5757
0
      if (i.tm.base_opcode & 0x20)
5758
0
  {
5759
0
    i.tm.base_opcode = 0x7f;
5760
0
    if (i.reg_operands != 2)
5761
0
      i.tm.opcode_modifier.opcodeprefix = PREFIX_0XF3;
5762
0
  }
5763
0
      else
5764
0
  {
5765
0
    if (i.reg_operands == 2)
5766
0
      i.tm.base_opcode = 0x29;
5767
0
    else
5768
0
      i.tm.base_opcode = 0x11;
5769
0
    if (i.tm.opcode_modifier.vexw != VEXW1)
5770
0
      i.tm.opcode_modifier.opcodeprefix = PREFIX_NONE;
5771
0
  }
5772
5773
0
      if (i.tm.opcode_modifier.vex)
5774
0
  i.tm.opcode_modifier.vexw = VEXWIG;
5775
5776
0
      copy_operand (0, 1);
5777
0
      copy_operand (1, 2);
5778
5779
0
      i.operands = 2;
5780
0
      i.imm_operands = 0;
5781
0
    }
5782
0
  else if (i.tm.base_opcode == 0x21
5783
0
     && i.tm.opcode_space == SPACE_0F3A
5784
0
     && i.op[0].imms->X_op == O_constant
5785
0
     && (i.operands == i.reg_operands + 1
5786
0
         ? i.op[0].imms->X_add_number == 0
5787
0
     || (i.op[0].imms->X_add_number & 0xf) == 0xf
5788
0
         : (i.op[0].imms->X_add_number & 0x3f) == 0x0e
5789
0
      && (i.reg_operands == 1 || i.op[2].regs == i.op[3].regs)))
5790
0
    {
5791
      /* Optimize: -O:
5792
         insertps $0b....1111, %xmmN, %xmmM          -> xorps %xmmM, %xmmM
5793
         insertps $0b00000000, %xmmN, %xmmM          -> movss %xmmN, %xmmM
5794
         insertps $0b..001110, mem, %xmmN            -> movss mem, %xmmN
5795
         vinsertps $0b....1111, %xmmN, %xmmM, %xmmK  -> vxorps %xmm?, %xmm?, %xmmK
5796
         vinsertps $0b00000000, %xmmN, %xmmM, %xmmK  -> vmovss %xmmN, %xmmM, %xmmK
5797
         vinsertps $0b..001110, mem, %xmmN, %xmmN    -> vmovss mem, %xmmN
5798
       */
5799
0
      i.tm.opcode_space = SPACE_0F;
5800
0
      if ((i.op[0].imms->X_add_number & 0xf) == 0xf)
5801
0
  {
5802
0
    i.tm.base_opcode = 0x57;
5803
0
    i.tm.opcode_modifier.opcodeprefix = PREFIX_NONE;
5804
5805
0
    --i.operands;
5806
5807
0
    copy_operand (i.operands - 1, i.operands);
5808
0
    copy_operand (1, i.operands - 1);
5809
0
    copy_operand (0, 1);
5810
5811
    /* Switch from EVEX to VEX encoding if possible.  Sadly we can't
5812
       (always) tell use of the {evex} pseudo-prefix (which otherwise
5813
       we'd like to respect) from use of %xmm16-%xmm31.  */
5814
0
    if (pp.encoding == encoding_evex)
5815
0
      pp.encoding = encoding_default;
5816
0
    if (i.tm.opcode_modifier.evex
5817
0
        && pp.encoding <= encoding_vex3
5818
0
        && !(i.op[0].regs->reg_flags & RegVRex))
5819
0
      {
5820
0
        i.tm.opcode_modifier.evex = 0;
5821
0
        i.tm.opcode_modifier.vex = VEX128;
5822
0
      }
5823
5824
    /* Switch from VEX3 to VEX2 encoding if possible.  */
5825
0
    if (i.tm.opcode_modifier.vex
5826
0
        && pp.encoding <= encoding_vex
5827
0
        && (i.op[0].regs->reg_flags & RegRex))
5828
0
      {
5829
0
        i.op[0].regs -= 8;
5830
0
        i.op[1].regs = i.op[0].regs;
5831
0
      }
5832
0
  }
5833
0
      else
5834
0
  {
5835
0
    i.tm.base_opcode = 0x10;
5836
0
    i.tm.opcode_modifier.opcodeprefix = PREFIX_0XF3;
5837
5838
0
    if (i.op[0].imms->X_add_number == 0)
5839
0
      --i.operands;
5840
0
    else
5841
0
      {
5842
0
        i.operands = 2;
5843
0
        i.tm.opcode_modifier.vexvvvv = 0;
5844
0
      }
5845
0
    copy_operand (0, 1);
5846
0
    copy_operand (1, 2);
5847
0
    copy_operand (2, 3);
5848
0
  }
5849
5850
0
      i.imm_operands = 0;
5851
0
    }
5852
0
}
5853
5854
/* Check whether the promoted (to address size) register is usable as index
5855
   register in ModR/M SIB addressing.  */
5856
5857
static bool is_index (const reg_entry *r)
5858
0
{
5859
0
  gas_assert (flag_code == CODE_64BIT);
5860
5861
0
  if (r->reg_type.bitfield.byte)
5862
0
    {
5863
0
      if (!(r->reg_flags & (RegRex | RegRex2 | RegRex64)))
5864
0
  {
5865
0
    if (r->reg_num >= 4)
5866
0
      return false;
5867
0
    r += 8;
5868
0
  }
5869
0
      r += 32;
5870
0
    }
5871
0
  if (r->reg_type.bitfield.word)
5872
0
    r += 32;
5873
  /* No need to further check .dword here.  */
5874
5875
0
  return r->reg_type.bitfield.baseindex;
5876
0
}
5877
5878
/* Try to shorten {nf} encodings, by shortening operand size or switching to
5879
   functionally identical encodings.  */
5880
5881
static void
5882
optimize_nf_encoding (void)
5883
0
{
5884
0
  if (i.tm.base_opcode == 0x80
5885
0
      && (i.tm.extension_opcode == 0 || i.tm.extension_opcode == 5)
5886
0
      && i.suffix != BYTE_MNEM_SUFFIX
5887
0
      && !i.types[1].bitfield.byte
5888
0
      && !i.types[2].bitfield.byte
5889
0
      && i.op[0].imms->X_op == O_constant
5890
0
      && i.op[0].imms->X_add_number == 0x80)
5891
0
    {
5892
      /* Optimize: -O:
5893
     {nf} addw $0x80, ...  -> {nf} subw $-0x80, ...
5894
     {nf} addl $0x80, ...  -> {nf} subl $-0x80, ...
5895
     {nf} addq $0x80, ...  -> {nf} subq $-0x80, ...
5896
5897
     {nf} subw $0x80, ...  -> {nf} addw $-0x80, ...
5898
     {nf} subl $0x80, ...  -> {nf} addl $-0x80, ...
5899
     {nf} subq $0x80, ...  -> {nf} addq $-0x80, ...
5900
       */
5901
0
      i.tm.base_opcode |= 3;
5902
0
      i.tm.extension_opcode ^= 5;
5903
0
      i.tm.opcode_modifier.w = 0;
5904
0
      i.op[0].imms->X_add_number = -i.op[0].imms->X_add_number;
5905
5906
0
      i.tm.operand_types[0].bitfield.imm8 = 0;
5907
0
      i.tm.operand_types[0].bitfield.imm8s = 1;
5908
0
      i.tm.operand_types[0].bitfield.imm16 = 0;
5909
0
      i.tm.operand_types[0].bitfield.imm32 = 0;
5910
0
      i.tm.operand_types[0].bitfield.imm32s = 0;
5911
5912
0
      i.types[0] = i.tm.operand_types[0];
5913
0
    }
5914
0
  else if ((i.tm.base_opcode | 3) == 0x83
5915
0
      && (i.tm.extension_opcode == 0 || i.tm.extension_opcode == 5)
5916
0
      && i.op[0].imms->X_op == O_constant
5917
0
      && (i.op[0].imms->X_add_number == 1
5918
0
    || i.op[0].imms->X_add_number == -1
5919
    /* While for wider than byte operations immediates were suitably
5920
       adjusted earlier on, 0xff in the byte case needs covering
5921
       explicitly.  */
5922
0
    || (i.op[0].imms->X_add_number == 0xff
5923
0
        && (i.suffix == BYTE_MNEM_SUFFIX
5924
0
      || i.types[i.operands - 1].bitfield.byte))))
5925
0
    {
5926
      /* Optimize: -O:
5927
     {nf} add $1, ...        -> {nf} inc ...
5928
     {nf} add $-1, ...       -> {nf} dec ...
5929
     {nf} add $0xf...f, ...  -> {nf} dec ...
5930
5931
     {nf} sub $1, ...        -> {nf} dec ...
5932
     {nf} sub $-1, ...       -> {nf} inc ...
5933
     {nf} sub $0xf...f, ...  -> {nf} inc ...
5934
       */
5935
0
      i.tm.base_opcode = 0xfe;
5936
0
      i.tm.extension_opcode
5937
0
  = (i.op[0].imms->X_add_number == 1) != (i.tm.extension_opcode == 0);
5938
0
      i.tm.opcode_modifier.w = 1;
5939
5940
0
      copy_operand (0, 1);
5941
0
      copy_operand (1, 2);
5942
5943
0
      i.imm_operands = 0;
5944
0
      --i.operands;
5945
0
    }
5946
0
  else if (i.tm.base_opcode == 0xc0
5947
0
     && i.op[0].imms->X_op == O_constant
5948
0
     && i.op[0].imms->X_add_number
5949
0
        == (i.types[i.operands - 1].bitfield.byte
5950
0
      || i.suffix == BYTE_MNEM_SUFFIX
5951
0
      ? 7 : i.types[i.operands - 1].bitfield.word
5952
0
      || i.suffix == WORD_MNEM_SUFFIX
5953
0
      ? 15 : 63 >> (i.types[i.operands - 1].bitfield.dword
5954
0
              || i.suffix == LONG_MNEM_SUFFIX)))
5955
0
    {
5956
      /* Optimize: -O:
5957
     {nf} rol $osz-1, ...   -> {nf} ror $1, ...
5958
     {nf} ror $osz-1, ...   -> {nf} rol $1, ...
5959
       */
5960
0
      gas_assert (i.tm.extension_opcode <= 1);
5961
0
      i.tm.extension_opcode ^= 1;
5962
0
      i.tm.base_opcode = 0xd0;
5963
0
      i.tm.operand_types[0].bitfield.imm1 = 1;
5964
0
      i.imm_operands = 0;
5965
0
    }
5966
0
  else if ((i.tm.base_opcode | 2) == 0x6b
5967
0
     && i.op[0].imms->X_op == O_constant
5968
0
     && (i.op[0].imms->X_add_number > 0
5969
0
         ? !(i.op[0].imms->X_add_number & (i.op[0].imms->X_add_number - 1))
5970
         /* optimize_imm() converts to sign-extended representation where
5971
      possible (and input can also come with these specific numbers).  */
5972
0
         : (i.types[i.operands - 1].bitfield.word
5973
0
      && i.op[0].imms->X_add_number == -0x8000)
5974
0
     || (i.types[i.operands - 1].bitfield.dword
5975
0
         && i.op[0].imms->X_add_number + 1 == -0x7fffffff))
5976
     /* 16-bit 3-operand non-ZU forms need leaviong alone, to prevent
5977
        zero-extension of the result.  Unless, of course, both non-
5978
        immediate operands match (which can be converted to the non-NDD
5979
        form).  */
5980
0
     && (i.operands < 3
5981
0
         || !i.types[2].bitfield.word
5982
0
         || i.tm.mnem_off == MN_imulzu
5983
0
         || i.op[2].regs == i.op[1].regs)
5984
     /* When merely optimizing for size, exclude cases where we'd convert
5985
        from Imm8S to Imm8 encoding, thus not actually reducing size.  */
5986
0
     && (!optimize_for_space
5987
0
         || i.tm.base_opcode == 0x69
5988
0
         || !(i.op[0].imms->X_add_number & 0x7d)))
5989
0
    {
5990
      /* Optimize: -O:
5991
     {nf} imul   $1<<N, ...   -> {nf} shl $N, ...
5992
     {nf} imulzu $1<<N, ...   -> {nf} shl $N, ...
5993
       */
5994
0
      if (i.op[0].imms->X_add_number != 2)
5995
0
  {
5996
0
    i.tm.base_opcode = 0xc0;
5997
0
    i.op[0].imms->X_add_number = ffs (i.op[0].imms->X_add_number) - 1;
5998
0
    i.tm.operand_types[0].bitfield.imm8 = 1;
5999
0
    i.tm.operand_types[0].bitfield.imm16 = 0;
6000
0
    i.tm.operand_types[0].bitfield.imm32 = 0;
6001
0
    i.tm.operand_types[0].bitfield.imm32s = 0;
6002
0
  }
6003
0
      else
6004
0
  {
6005
0
    i.tm.base_opcode = 0xd0;
6006
0
    i.tm.operand_types[0].bitfield.imm1 = 1;
6007
0
  }
6008
0
      i.types[0] = i.tm.operand_types[0];
6009
0
      i.tm.extension_opcode = 4;
6010
0
      i.tm.opcode_modifier.w = 1;
6011
0
      i.tm.opcode_modifier.operandconstraint = 0;
6012
0
      if (i.operands == 3)
6013
0
  {
6014
0
    if (i.op[2].regs == i.op[1].regs && i.tm.mnem_off != MN_imulzu)
6015
0
      {
6016
        /* Convert to non-NDD form.  This is required for 16-bit insns
6017
           (to prevent zero-extension) and benign for others.  */
6018
0
        i.operands = 2;
6019
0
        i.reg_operands = 1;
6020
0
      }
6021
0
    else
6022
0
      i.tm.opcode_modifier.vexvvvv = VexVVVV_DST;
6023
0
  }
6024
0
      else if (i.tm.mnem_off == MN_imulzu)
6025
0
  {
6026
    /* Convert to NDD form, to effect zero-extension of the result.  */
6027
0
    i.tm.opcode_modifier.vexvvvv = VexVVVV_DST;
6028
0
    i.operands = 3;
6029
0
    i.reg_operands = 2;
6030
0
    copy_operand (2, 1);
6031
0
  }
6032
0
    }
6033
6034
0
  if (optimize_for_space
6035
0
      && pp.encoding != encoding_evex
6036
0
      && (i.tm.base_opcode == 0x00
6037
0
    || (i.tm.base_opcode == 0xd0 && i.tm.extension_opcode == 4))
6038
0
      && !i.mem_operands
6039
0
      && !i.types[1].bitfield.byte
6040
      /* 16-bit operand size has extra restrictions: If REX2 was needed,
6041
   no size reduction would be possible.  Plus 3-operand forms zero-
6042
   extend the result, which can't be expressed with LEA.  */
6043
0
      && (!i.types[1].bitfield.word
6044
0
    || (i.operands == 2 && pp.encoding != encoding_egpr))
6045
0
      && is_plausible_suffix (1)
6046
      /* %rsp can't be the index.  */
6047
0
      && (is_index (i.op[1].regs)
6048
0
    || (i.imm_operands == 0 && is_index (i.op[0].regs)))
6049
      /* While %rbp, %r13, %r21, and %r29 can be made the index in order to
6050
   avoid the otherwise necessary Disp8, if the other operand is also
6051
   from that set and REX2 would be required to encode the insn, the
6052
   resulting encoding would be no smaller than the EVEX one.  */
6053
0
      && (i.op[1].regs->reg_num != 5
6054
0
    || pp.encoding != encoding_egpr
6055
0
    || i.imm_operands > 0
6056
0
    || i.op[0].regs->reg_num != 5))
6057
0
    {
6058
      /* Optimize: -Os:
6059
     {nf} addw %N, %M    -> leaw (%rM,%rN), %M
6060
     {nf} addl %eN, %eM  -> leal (%rM,%rN), %eM
6061
     {nf} addq %rN, %rM  -> leaq (%rM,%rN), %rM
6062
6063
     {nf} shlw $1, %N   -> leaw (%rN,%rN), %N
6064
     {nf} shll $1, %eN  -> leal (%rN,%rN), %eN
6065
     {nf} shlq $1, %rN  -> leaq (%rN,%rN), %rN
6066
6067
     {nf} addl %eK, %eN, %eM  -> leal (%rN,%rK), %eM
6068
     {nf} addq %rK, %rN, %rM  -> leaq (%rN,%rK), %rM
6069
6070
     {nf} shll $1, %eN, %eM  -> leal (%rN,%rN), %eM
6071
     {nf} shlq $1, %rN, %rM  -> leaq (%rN,%rN), %rM
6072
       */
6073
0
      i.tm.opcode_space = SPACE_BASE;
6074
0
      i.tm.base_opcode = 0x8d;
6075
0
      i.tm.extension_opcode = None;
6076
0
      i.tm.opcode_modifier.evex = 0;
6077
0
      i.tm.opcode_modifier.vexvvvv = 0;
6078
0
      if (i.imm_operands != 0)
6079
0
  i.index_reg = i.base_reg = i.op[1].regs;
6080
0
      else if (!is_index (i.op[0].regs)
6081
0
         || (i.op[1].regs->reg_num == 5
6082
0
       && i.op[0].regs->reg_num != 5))
6083
0
  {
6084
0
    i.base_reg = i.op[0].regs;
6085
0
    i.index_reg = i.op[1].regs;
6086
0
  }
6087
0
      else
6088
0
  {
6089
0
    i.base_reg = i.op[1].regs;
6090
0
    i.index_reg = i.op[0].regs;
6091
0
  }
6092
0
      if (i.types[1].bitfield.word)
6093
0
  {
6094
    /* NB: No similar adjustment is needed when operand size is 32-bit.  */
6095
0
    i.base_reg += 64;
6096
0
    i.index_reg += 64;
6097
0
  }
6098
0
      i.op[1].regs = i.op[i.operands - 1].regs;
6099
6100
0
      operand_type_set (&i.types[0], 0);
6101
0
      i.types[0].bitfield.baseindex = 1;
6102
0
      i.tm.operand_types[0] = i.types[0];
6103
0
      i.op[0].disps = NULL;
6104
0
      i.flags[0] = Operand_Mem;
6105
6106
0
      i.operands = 2;
6107
0
      i.mem_operands = i.reg_operands = 1;
6108
0
      i.imm_operands = 0;
6109
0
      pp.has_nf = false;
6110
0
    }
6111
0
  else if (optimize_for_space
6112
0
     && pp.encoding != encoding_evex
6113
0
     && (i.tm.base_opcode == 0x80 || i.tm.base_opcode == 0x83)
6114
0
     && (i.tm.extension_opcode == 0
6115
0
         || (i.tm.extension_opcode == 5
6116
0
       && i.op[0].imms->X_op == O_constant
6117
       /* Subtraction of -0x80 will end up smaller only if neither
6118
          operand size nor REX/REX2 prefixes are needed.  */
6119
0
       && (i.op[0].imms->X_add_number != -0x80
6120
0
           || (i.types[1].bitfield.dword
6121
0
               && !(i.op[1].regs->reg_flags & RegRex)
6122
0
               && !(i.op[i.operands - 1].regs->reg_flags & RegRex)
6123
0
               && pp.encoding != encoding_egpr))))
6124
0
     && !i.mem_operands
6125
0
     && !i.types[1].bitfield.byte
6126
     /* 16-bit operand size has extra restrictions: If REX2 was needed,
6127
        no size reduction would be possible.  Plus 3-operand forms zero-
6128
        extend the result, which can't be expressed with LEA.  */
6129
0
     && (!i.types[1].bitfield.word
6130
0
         || (i.operands == 2 && pp.encoding != encoding_egpr))
6131
0
     && is_plausible_suffix (1))
6132
0
    {
6133
      /* Optimize: -Os:
6134
     {nf} addw $N, %M   -> leaw N(%rM), %M
6135
     {nf} addl $N, %eM  -> leal N(%rM), %eM
6136
     {nf} addq $N, %rM  -> leaq N(%rM), %rM
6137
6138
     {nf} subw $N, %M   -> leaw -N(%rM), %M
6139
     {nf} subl $N, %eM  -> leal -N(%rM), %eM
6140
     {nf} subq $N, %rM  -> leaq -N(%rM), %rM
6141
6142
     {nf} addl $N, %eK, %eM  -> leal N(%rK), %eM
6143
     {nf} addq $N, %rK, %rM  -> leaq N(%rK), %rM
6144
6145
     {nf} subl $N, %eK, %eM  -> leal -N(%rK), %eM
6146
     {nf} subq $N, %rK, %rM  -> leaq -N(%rK), %rM
6147
       */
6148
0
      i.tm.opcode_space = SPACE_BASE;
6149
0
      i.tm.base_opcode = 0x8d;
6150
0
      if (i.tm.extension_opcode == 5)
6151
0
  i.op[0].imms->X_add_number = -i.op[0].imms->X_add_number;
6152
0
      i.tm.extension_opcode = None;
6153
0
      i.tm.opcode_modifier.evex = 0;
6154
0
      i.tm.opcode_modifier.vexvvvv = 0;
6155
0
      i.base_reg = i.op[1].regs;
6156
0
      if (i.types[1].bitfield.word)
6157
0
  {
6158
    /* NB: No similar adjustment is needed when operand size is 32-bit.  */
6159
0
    i.base_reg += 64;
6160
0
  }
6161
0
      i.op[1].regs = i.op[i.operands - 1].regs;
6162
6163
0
      operand_type_set (&i.types[0], 0);
6164
0
      i.types[0].bitfield.baseindex = 1;
6165
0
      i.types[0].bitfield.disp32 = 1;
6166
0
      i.op[0].disps = i.op[0].imms;
6167
0
      i.flags[0] = Operand_Mem;
6168
0
      optimize_disp (&i.tm);
6169
0
      i.tm.operand_types[0] = i.types[0];
6170
6171
0
      i.operands = 2;
6172
0
      i.disp_operands = i.mem_operands = i.reg_operands = 1;
6173
0
      i.imm_operands = 0;
6174
0
      pp.has_nf = false;
6175
0
    }
6176
0
  else if (i.tm.base_opcode == 0x6b
6177
0
     && !i.mem_operands
6178
0
     && pp.encoding != encoding_evex
6179
0
     && i.tm.mnem_off != MN_imulzu
6180
0
     && is_plausible_suffix (1)
6181
     /* %rsp can't be the index.  */
6182
0
     && is_index (i.op[1].regs)
6183
     /* There's no reduction in size for 16-bit forms requiring Disp8 and
6184
        REX2.  */
6185
0
     && (!optimize_for_space
6186
0
         || !i.types[1].bitfield.word
6187
0
         || i.op[1].regs->reg_num != 5
6188
0
         || pp.encoding != encoding_egpr)
6189
0
     && i.op[0].imms->X_op == O_constant
6190
0
     && (i.op[0].imms->X_add_number == 3
6191
0
         || i.op[0].imms->X_add_number == 5
6192
0
         || i.op[0].imms->X_add_number == 9))
6193
0
    {
6194
      /* Optimize: -O:
6195
        For n one of 3, 5, or 9
6196
     {nf} imulw $n, %N, %M    -> leaw (%rN,%rN,n-1), %M
6197
     {nf} imull $n, %eN, %eM  -> leal (%rN,%rN,n-1), %eM
6198
     {nf} imulq $n, %rN, %rM  -> leaq (%rN,%rN,n-1), %rM
6199
6200
     {nf} imulw $n, %N   -> leaw (%rN,%rN,s), %N
6201
     {nf} imull $n, %eN  -> leal (%rN,%rN,s), %eN
6202
     {nf} imulq $n, %rN  -> leaq (%rN,%rN,s), %rN
6203
       */
6204
0
      i.tm.opcode_space = SPACE_BASE;
6205
0
      i.tm.base_opcode = 0x8d;
6206
0
      i.tm.extension_opcode = None;
6207
0
      i.tm.opcode_modifier.evex = 0;
6208
0
      i.base_reg = i.op[1].regs;
6209
      /* NB: No similar adjustment is needed when operand size is 32 bits.  */
6210
0
      if (i.types[1].bitfield.word)
6211
0
  i.base_reg += 64;
6212
0
      i.index_reg = i.base_reg;
6213
0
      i.log2_scale_factor = i.op[0].imms->X_add_number == 9
6214
0
          ? 3 : i.op[0].imms->X_add_number >> 1;
6215
6216
0
      operand_type_set (&i.types[0], 0);
6217
0
      i.types[0].bitfield.baseindex = 1;
6218
0
      i.tm.operand_types[0] = i.types[0];
6219
0
      i.op[0].disps = NULL;
6220
0
      i.flags[0] = Operand_Mem;
6221
6222
0
      copy_operand (1, i.operands - 1);
6223
6224
0
      i.operands = 2;
6225
0
      i.mem_operands = i.reg_operands = 1;
6226
0
      i.imm_operands = 0;
6227
0
      pp.has_nf = false;
6228
0
    }
6229
0
  else if (cpu_arch_isa_flags.bitfield.cpubmi2
6230
0
     && pp.encoding == encoding_default
6231
0
     && (i.operands > 2 || !i.mem_operands)
6232
0
     && (i.types[i.operands - 1].bitfield.dword
6233
0
         || i.types[i.operands - 1].bitfield.qword))
6234
0
    {
6235
0
      if (i.tm.base_opcode == 0xd2)
6236
0
  {
6237
    /* Optimize: -O:
6238
         <OP> one of sal, sar, shl, shr:
6239
         {nf} <OP> %cl, %rN       -> <OP>x %{e,r}cx, %rN, %rN (N < 16)
6240
         {nf} <OP> %cl, ..., %rN  -> <OP>x %{e,r}cx, ..., %rN (no eGPR used)
6241
     */
6242
0
    gas_assert (i.tm.extension_opcode & 4);
6243
0
    i.tm.operand_types[0] = i.tm.operand_types[i.operands - 1];
6244
    /* NB: i.op[0].regs specifying %cl is good enough.  */
6245
0
    i.types[0] = i.types[i.operands - 1];
6246
0
    if (i.operands == 2)
6247
0
      {
6248
0
        i.tm.operand_types[0].bitfield.baseindex = 0;
6249
0
        i.tm.operand_types[2] = i.tm.operand_types[0];
6250
0
        i.op[2].regs = i.op[1].regs;
6251
0
        i.types[2] = i.types[1];
6252
0
        i.reg_operands = i.operands = 3;
6253
0
      }
6254
0
    pp.has_nf = false;
6255
0
    i.tm.opcode_modifier.w = 0;
6256
0
    i.tm.opcode_modifier.evex = 0;
6257
0
    i.tm.opcode_modifier.vex = VEX128;
6258
0
    i.tm.opcode_modifier.vexvvvv = VexVVVV_SRC2;
6259
0
    i.tm.opcode_space = SPACE_0F38;
6260
0
    i.tm.base_opcode = 0xf7;
6261
0
    i.tm.opcode_modifier.opcodeprefix
6262
0
      = !(i.tm.extension_opcode & 1)
6263
0
        ? PREFIX_0X66 /* shlx */
6264
0
        : i.tm.extension_opcode & 2
6265
0
    ? PREFIX_0XF3 /* sarx */
6266
0
    : PREFIX_0XF2 /* shrx */;
6267
0
    i.tm.extension_opcode = None;
6268
0
  }
6269
0
      else if (i.tm.base_opcode == 0xc0
6270
0
         && i.tm.extension_opcode <= 1
6271
0
         && i.op[0].imms->X_op == O_constant)
6272
0
  {
6273
    /* Optimize: -O:
6274
         {nf} rol $I, %rN       -> rorx $osz-I, %rN, %rN (I != osz-1, N < 16)
6275
         {nf} rol $I, ..., %rN  -> rorx $osz-I, ..., %rN (I != osz-1, no eGPR used)
6276
         {nf} ror $I, %rN       -> rorx $I, %rN, %rN (I != 1, N < 16)
6277
         {nf} ror $I, ..., %rN  -> rorx $I,..., %rN (I != 1, no eGPR used)
6278
       NB: rol -> ror transformation for I == osz-1 was already handled above.
6279
       NB2: ror with an immediate of 1 uses a different base opcode.
6280
     */
6281
0
    if (i.operands == 2)
6282
0
      {
6283
0
        copy_operand (2, 1);
6284
0
        i.tm.operand_types[2].bitfield.baseindex = 0;
6285
0
        i.reg_operands = 2;
6286
0
        i.operands = 3;
6287
0
      }
6288
0
    pp.has_nf = false;
6289
0
    i.tm.opcode_modifier.w = 0;
6290
0
    i.tm.opcode_modifier.evex = 0;
6291
0
    i.tm.opcode_modifier.vex = VEX128;
6292
0
    i.tm.opcode_modifier.vexvvvv = 0;
6293
0
    i.tm.opcode_space = SPACE_0F3A;
6294
0
    i.tm.base_opcode = 0xf0;
6295
0
    i.tm.opcode_modifier.opcodeprefix = PREFIX_0XF2;
6296
0
    if (!i.tm.extension_opcode)
6297
0
      i.op[0].imms->X_add_number =
6298
0
        (i.types[i.operands - 1].bitfield.byte
6299
0
         ? 8 : i.types[i.operands - 1].bitfield.word
6300
0
         ? 16 : 64 >> i.types[i.operands - 1].bitfield.dword)
6301
0
        - i.op[0].imms->X_add_number;
6302
0
    i.tm.extension_opcode = None;
6303
0
  }
6304
0
      else if (i.tm.base_opcode == 0xf6
6305
0
         && i.tm.extension_opcode == 4
6306
0
         && !i.mem_operands
6307
0
         && i.op[0].regs->reg_num == 2
6308
0
         && !(i.op[0].regs->reg_flags & RegRex) )
6309
0
  {
6310
    /* Optimize: -O:
6311
         {nf} mul %edx  -> mulx %eax, %eax, %edx
6312
         {nf} mul %rdx  -> mulx %rax, %rax, %rdx
6313
     */
6314
0
    i.tm.operand_types[1] = i.tm.operand_types[0];
6315
0
    i.tm.operand_types[1].bitfield.baseindex = 0;
6316
0
    i.tm.operand_types[2] = i.tm.operand_types[1];
6317
0
    i.op[2].regs = i.op[0].regs;
6318
    /* NB: %eax is good enough also for 64-bit operand size.  */
6319
0
    i.op[1].regs = i.op[0].regs = reg_eax;
6320
0
    i.types[2] = i.types[1] = i.types[0];
6321
0
    i.reg_operands = i.operands = 3;
6322
6323
0
    pp.has_nf = false;
6324
0
    i.tm.opcode_modifier.w = 0;
6325
0
    i.tm.opcode_modifier.evex = 0;
6326
0
    i.tm.opcode_modifier.vex = VEX128;
6327
0
    i.tm.opcode_modifier.vexvvvv = VexVVVV_SRC1;
6328
0
    i.tm.opcode_space = SPACE_0F38;
6329
0
    i.tm.base_opcode = 0xf6;
6330
0
    i.tm.opcode_modifier.opcodeprefix = PREFIX_0XF2;
6331
0
    i.tm.extension_opcode = None;
6332
0
  }
6333
0
    }
6334
0
}
6335
6336
static void
6337
s_noopt (int dummy ATTRIBUTE_UNUSED)
6338
0
{
6339
0
  if (!is_it_end_of_statement ())
6340
0
    as_warn (_("`.noopt' arguments ignored"));
6341
6342
0
  optimize = 0;
6343
0
  optimize_for_space = 0;
6344
6345
0
  ignore_rest_of_line ();
6346
0
}
6347
6348
/* Return non-zero for load instruction.  */
6349
6350
static int
6351
load_insn_p (void)
6352
0
{
6353
0
  unsigned int dest;
6354
0
  int any_vex_p = is_any_vex_encoding (&i.tm);
6355
0
  unsigned int base_opcode = i.tm.base_opcode | 1;
6356
6357
0
  if (!any_vex_p)
6358
0
    {
6359
      /* Anysize insns: lea, invlpg, clflush, prefetch*, bndmk, bndcl, bndcu,
6360
   bndcn, bndstx, bndldx, clflushopt, clwb, cldemote.  */
6361
0
      if (i.tm.opcode_modifier.operandconstraint == ANY_SIZE)
6362
0
  return 0;
6363
6364
      /* pop.   */
6365
0
      if (i.tm.mnem_off == MN_pop)
6366
0
  return 1;
6367
0
    }
6368
6369
0
  if (i.tm.opcode_space == SPACE_BASE)
6370
0
    {
6371
      /* popf, popa.   */
6372
0
      if (i.tm.base_opcode == 0x9d
6373
0
    || i.tm.base_opcode == 0x61)
6374
0
  return 1;
6375
6376
      /* movs, cmps, lods, scas.  */
6377
0
      if ((i.tm.base_opcode | 0xb) == 0xaf)
6378
0
  return 1;
6379
6380
      /* outs, xlatb.  */
6381
0
      if (base_opcode == 0x6f
6382
0
    || i.tm.base_opcode == 0xd7)
6383
0
  return 1;
6384
      /* NB: For AMD-specific insns with implicit memory operands,
6385
   they're intentionally not covered.  */
6386
0
    }
6387
6388
  /* No memory operand.  */
6389
0
  if (!i.mem_operands)
6390
0
    return 0;
6391
6392
0
  if (any_vex_p)
6393
0
    {
6394
0
      if (i.tm.mnem_off == MN_vldmxcsr)
6395
0
  return 1;
6396
0
    }
6397
0
  else if (i.tm.opcode_space == SPACE_BASE)
6398
0
    {
6399
      /* test, not, neg, mul, imul, div, idiv.  */
6400
0
      if (base_opcode == 0xf7 && i.tm.extension_opcode != 1)
6401
0
  return 1;
6402
6403
      /* inc, dec.  */
6404
0
      if (base_opcode == 0xff && i.tm.extension_opcode <= 1)
6405
0
  return 1;
6406
6407
      /* add, or, adc, sbb, and, sub, xor, cmp.  */
6408
0
      if (i.tm.base_opcode >= 0x80 && i.tm.base_opcode <= 0x83)
6409
0
  return 1;
6410
6411
      /* rol, ror, rcl, rcr, shl/sal, shr, sar. */
6412
0
      if ((base_opcode == 0xc1 || (base_opcode | 2) == 0xd3)
6413
0
    && i.tm.extension_opcode != 6)
6414
0
  return 1;
6415
6416
      /* Check for x87 instructions.  */
6417
0
      if ((base_opcode | 6) == 0xdf)
6418
0
  {
6419
    /* Skip fst, fstp, fstenv, fstcw.  */
6420
0
    if (i.tm.base_opcode == 0xd9
6421
0
        && (i.tm.extension_opcode == 2
6422
0
      || i.tm.extension_opcode == 3
6423
0
      || i.tm.extension_opcode == 6
6424
0
      || i.tm.extension_opcode == 7))
6425
0
      return 0;
6426
6427
    /* Skip fisttp, fist, fistp, fstp.  */
6428
0
    if (i.tm.base_opcode == 0xdb
6429
0
        && (i.tm.extension_opcode == 1
6430
0
      || i.tm.extension_opcode == 2
6431
0
      || i.tm.extension_opcode == 3
6432
0
      || i.tm.extension_opcode == 7))
6433
0
      return 0;
6434
6435
    /* Skip fisttp, fst, fstp, fsave, fstsw.  */
6436
0
    if (i.tm.base_opcode == 0xdd
6437
0
        && (i.tm.extension_opcode == 1
6438
0
      || i.tm.extension_opcode == 2
6439
0
      || i.tm.extension_opcode == 3
6440
0
      || i.tm.extension_opcode == 6
6441
0
      || i.tm.extension_opcode == 7))
6442
0
      return 0;
6443
6444
    /* Skip fisttp, fist, fistp, fbstp, fistp.  */
6445
0
    if (i.tm.base_opcode == 0xdf
6446
0
        && (i.tm.extension_opcode == 1
6447
0
      || i.tm.extension_opcode == 2
6448
0
      || i.tm.extension_opcode == 3
6449
0
      || i.tm.extension_opcode == 6
6450
0
      || i.tm.extension_opcode == 7))
6451
0
      return 0;
6452
6453
0
    return 1;
6454
0
  }
6455
0
    }
6456
0
  else if (i.tm.opcode_space == SPACE_0F)
6457
0
    {
6458
      /* bt, bts, btr, btc.  */
6459
0
      if (i.tm.base_opcode == 0xba
6460
0
    && (i.tm.extension_opcode | 3) == 7)
6461
0
  return 1;
6462
6463
      /* cmpxchg8b, cmpxchg16b, xrstors, vmptrld.  */
6464
0
      if (i.tm.base_opcode == 0xc7
6465
0
    && i.tm.opcode_modifier.opcodeprefix == PREFIX_NONE
6466
0
    && (i.tm.extension_opcode == 1 || i.tm.extension_opcode == 3
6467
0
        || i.tm.extension_opcode == 6))
6468
0
  return 1;
6469
6470
      /* fxrstor, ldmxcsr, xrstor.  */
6471
0
      if (i.tm.base_opcode == 0xae
6472
0
    && (i.tm.extension_opcode == 1
6473
0
        || i.tm.extension_opcode == 2
6474
0
        || i.tm.extension_opcode == 5))
6475
0
  return 1;
6476
6477
      /* lgdt, lidt, lmsw.  */
6478
0
      if (i.tm.base_opcode == 0x01
6479
0
    && (i.tm.extension_opcode == 2
6480
0
        || i.tm.extension_opcode == 3
6481
0
        || i.tm.extension_opcode == 6))
6482
0
  return 1;
6483
0
    }
6484
6485
0
  dest = i.operands - 1;
6486
6487
  /* Check fake imm8 operand and 3 source operands.  */
6488
0
  if ((i.tm.opcode_modifier.immext
6489
0
       || i.reg_operands + i.mem_operands == 4)
6490
0
      && i.types[dest].bitfield.imm8)
6491
0
    dest--;
6492
6493
  /* add, or, adc, sbb, and, sub, xor, cmp, test, xchg.  */
6494
0
  if (i.tm.opcode_space == SPACE_BASE
6495
0
      && ((base_opcode | 0x38) == 0x39
6496
0
    || (base_opcode | 2) == 0x87))
6497
0
    return 1;
6498
6499
0
  if (i.tm.mnem_off == MN_xadd)
6500
0
    return 1;
6501
6502
  /* Check for load instruction.  */
6503
0
  return (i.types[dest].bitfield.class != ClassNone
6504
0
    || i.types[dest].bitfield.instance == Accum);
6505
0
}
6506
6507
/* Output lfence, 0xfaee8, after instruction.  */
6508
6509
static void
6510
insert_lfence_after (void)
6511
0
{
6512
0
  if (lfence_after_load && load_insn_p ())
6513
0
    {
6514
      /* There are also two REP string instructions that require
6515
   special treatment. Specifically, the compare string (CMPS)
6516
   and scan string (SCAS) instructions set EFLAGS in a manner
6517
   that depends on the data being compared/scanned. When used
6518
   with a REP prefix, the number of iterations may therefore
6519
   vary depending on this data. If the data is a program secret
6520
   chosen by the adversary using an LVI method,
6521
   then this data-dependent behavior may leak some aspect
6522
   of the secret.  */
6523
0
      if (((i.tm.base_opcode | 0x9) == 0xaf)
6524
0
    && i.prefix[REP_PREFIX])
6525
0
  {
6526
0
      as_warn (_("`%s` changes flags which would affect control flow behavior"),
6527
0
         insn_name (&i.tm));
6528
0
  }
6529
0
      char *p = frag_more (3);
6530
0
      *p++ = 0xf;
6531
0
      *p++ = 0xae;
6532
0
      *p = 0xe8;
6533
0
    }
6534
0
}
6535
6536
/* Output lfence, 0xfaee8, before instruction.  */
6537
6538
static void
6539
insert_lfence_before (const struct last_insn *last_insn)
6540
0
{
6541
0
  char *p;
6542
6543
0
  if (i.tm.opcode_space != SPACE_BASE)
6544
0
    return;
6545
6546
0
  if (i.tm.base_opcode == 0xff
6547
0
      && (i.tm.extension_opcode == 2 || i.tm.extension_opcode == 4))
6548
0
    {
6549
      /* Insert lfence before indirect branch if needed.  */
6550
6551
0
      if (lfence_before_indirect_branch == lfence_branch_none)
6552
0
  return;
6553
6554
0
      if (i.operands != 1)
6555
0
  abort ();
6556
6557
0
      if (i.reg_operands == 1)
6558
0
  {
6559
    /* Indirect branch via register.  Don't insert lfence with
6560
       -mlfence-after-load=yes.  */
6561
0
    if (lfence_after_load
6562
0
        || lfence_before_indirect_branch == lfence_branch_memory)
6563
0
      return;
6564
0
  }
6565
0
      else if (i.mem_operands == 1
6566
0
         && lfence_before_indirect_branch != lfence_branch_register)
6567
0
  {
6568
0
    as_warn (_("indirect `%s` with memory operand should be avoided"),
6569
0
       insn_name (&i.tm));
6570
0
    return;
6571
0
  }
6572
0
      else
6573
0
  return;
6574
6575
0
      if (last_insn->kind != last_insn_other)
6576
0
  {
6577
0
    as_warn_where (last_insn->file, last_insn->line,
6578
0
       _("`%s` skips -mlfence-before-indirect-branch on `%s`"),
6579
0
       last_insn->name, insn_name (&i.tm));
6580
0
    return;
6581
0
  }
6582
6583
0
      p = frag_more (3);
6584
0
      *p++ = 0xf;
6585
0
      *p++ = 0xae;
6586
0
      *p = 0xe8;
6587
0
      return;
6588
0
    }
6589
6590
  /* Output or/not/shl and lfence before near ret.  */
6591
0
  if (lfence_before_ret != lfence_before_ret_none
6592
0
      && (i.tm.base_opcode | 1) == 0xc3)
6593
0
    {
6594
0
      if (last_insn->kind != last_insn_other)
6595
0
  {
6596
0
    as_warn_where (last_insn->file, last_insn->line,
6597
0
       _("`%s` skips -mlfence-before-ret on `%s`"),
6598
0
       last_insn->name, insn_name (&i.tm));
6599
0
    return;
6600
0
  }
6601
6602
      /* Near ret ingore operand size override under CPU64.  */
6603
0
      char prefix = flag_code == CODE_64BIT
6604
0
        ? 0x48
6605
0
        : i.prefix[DATA_PREFIX] ? 0x66 : 0x0;
6606
6607
0
      if (lfence_before_ret == lfence_before_ret_not)
6608
0
  {
6609
    /* not: 0xf71424, may add prefix
6610
       for operand size override or 64-bit code.  */
6611
0
    p = frag_more ((prefix ? 2 : 0) + 6 + 3);
6612
0
    if (prefix)
6613
0
      *p++ = prefix;
6614
0
    *p++ = 0xf7;
6615
0
    *p++ = 0x14;
6616
0
    *p++ = 0x24;
6617
0
    if (prefix)
6618
0
      *p++ = prefix;
6619
0
    *p++ = 0xf7;
6620
0
    *p++ = 0x14;
6621
0
    *p++ = 0x24;
6622
0
  }
6623
0
      else
6624
0
  {
6625
0
    p = frag_more ((prefix ? 1 : 0) + 4 + 3);
6626
0
    if (prefix)
6627
0
      *p++ = prefix;
6628
0
    if (lfence_before_ret == lfence_before_ret_or)
6629
0
      {
6630
        /* or: 0x830c2400, may add prefix
6631
     for operand size override or 64-bit code.  */
6632
0
        *p++ = 0x83;
6633
0
        *p++ = 0x0c;
6634
0
      }
6635
0
    else
6636
0
      {
6637
        /* shl: 0xc1242400, may add prefix
6638
     for operand size override or 64-bit code.  */
6639
0
        *p++ = 0xc1;
6640
0
        *p++ = 0x24;
6641
0
      }
6642
6643
0
    *p++ = 0x24;
6644
0
    *p++ = 0x0;
6645
0
  }
6646
6647
0
      *p++ = 0xf;
6648
0
      *p++ = 0xae;
6649
0
      *p = 0xe8;
6650
0
    }
6651
0
}
6652
6653
/* Shared helper for md_assemble() and s_insn().  */
6654
static void init_globals (void)
6655
0
{
6656
0
  unsigned int j;
6657
6658
0
  memset (&i, '\0', sizeof (i));
6659
0
  i.rounding.type = rc_none;
6660
0
  for (j = 0; j < MAX_OPERANDS; j++)
6661
0
    i.reloc[j] = NO_RELOC;
6662
0
  memset (disp_expressions, '\0', sizeof (disp_expressions));
6663
0
  memset (im_expressions, '\0', sizeof (im_expressions));
6664
0
  save_stack_p = save_stack;
6665
0
}
6666
6667
/* Helper for md_assemble() to decide whether to prepare for a possible 2nd
6668
   parsing pass. Instead of introducing a rarely used new insn attribute this
6669
   utilizes a common pattern between affected templates. It is deemed
6670
   acceptable that this will lead to unnecessary pass 2 preparations in a
6671
   limited set of cases.  */
6672
static INLINE bool may_need_pass2 (const insn_template *t)
6673
0
{
6674
0
  return t->opcode_modifier.sse2avx
6675
   /* Note that all SSE2AVX templates have at least one operand.  */
6676
0
   ? t->operand_types[t->operands - 1].bitfield.class == RegSIMD
6677
0
   : (t->opcode_space == SPACE_0F
6678
0
      && (t->base_opcode | 1) == 0xbf)
6679
0
     || (t->opcode_space == SPACE_BASE
6680
0
         && t->base_opcode == 0x63)
6681
0
     || (intel_syntax /* shld / shrd may mean suffixed shl / shr.  */
6682
0
         && t->opcode_space == SPACE_MAP4
6683
0
         && (t->base_opcode | 8) == 0x2c);
6684
0
}
6685
6686
#ifdef OBJ_ELF
6687
static enum x86_tls_error_type
6688
x86_check_tls_relocation (enum bfd_reloc_code_real r_type)
6689
0
{
6690
0
  switch (r_type)
6691
0
    {
6692
0
    case BFD_RELOC_386_TLS_GOTDESC:
6693
      /* Check GDesc access model:
6694
6695
   leal x@tlsdesc(%ebx), %reg32 --> Memory reg must be %ebx and
6696
            SIB is not supported.
6697
       */
6698
0
      if (i.tm.mnem_off != MN_lea)
6699
0
  return x86_tls_error_insn;
6700
0
      if (i.index_reg)
6701
0
  return x86_tls_error_sib;
6702
0
      if (!i.base_reg)
6703
0
  return x86_tls_error_no_base_reg;
6704
0
      if (i.base_reg->reg_type.bitfield.instance != RegB)
6705
0
  return x86_tls_error_ebx;
6706
0
      if (!i.op[1].regs->reg_type.bitfield.dword)
6707
0
  return x86_tls_error_dest_32bit_reg_size;
6708
0
      break;
6709
6710
0
    case BFD_RELOC_386_TLS_GD:
6711
      /* Check GD access model:
6712
6713
   leal foo@tlsgd(,%ebx,1), %eax   --> Only this fixed format is supported.
6714
   leal foo@tlsgd(%reg32), %eax    --> Dest reg must be '%eax'
6715
               Memory reg can't be %eax.
6716
       */
6717
0
      if (i.tm.mnem_off != MN_lea)
6718
0
  return x86_tls_error_insn;
6719
0
      if (i.op[1].regs->reg_type.bitfield.instance != Accum)
6720
0
  return x86_tls_error_dest_eax;
6721
0
      if (!i.op[1].regs->reg_type.bitfield.dword)
6722
0
  return x86_tls_error_dest_32bit_reg_size;
6723
0
      if (i.index_reg)
6724
0
  {
6725
0
    if (i.base_reg)
6726
0
      return x86_tls_error_base_reg;
6727
0
    if (i.index_reg->reg_type.bitfield.instance != RegB)
6728
0
      return x86_tls_error_index_ebx;
6729
0
    if (i.log2_scale_factor)
6730
0
      return x86_tls_error_scale_factor;
6731
0
  }
6732
0
      else
6733
0
  {
6734
0
    if (!i.base_reg)
6735
0
      return x86_tls_error_no_base_reg;
6736
0
    if (i.base_reg->reg_type.bitfield.instance == Accum)
6737
0
      return x86_tls_error_eax;
6738
0
  }
6739
0
      break;
6740
6741
0
    case BFD_RELOC_386_TLS_LDM:
6742
      /*  Check LDM access model:
6743
6744
    leal foo@tlsldm(%reg32), %eax --> Dest reg must be '%eax'
6745
                    Memory reg can't be %eax and SIB
6746
              is not supported.
6747
       */
6748
0
      if (i.tm.mnem_off != MN_lea)
6749
0
  return x86_tls_error_insn;
6750
0
      if (i.index_reg)
6751
0
  return x86_tls_error_sib;
6752
0
      if (!i.base_reg)
6753
0
  return x86_tls_error_no_base_reg;
6754
0
      if (i.base_reg->reg_type.bitfield.instance == Accum)
6755
0
  return x86_tls_error_eax;
6756
0
      if (i.op[1].regs->reg_type.bitfield.instance != Accum)
6757
0
  return x86_tls_error_dest_eax;
6758
0
      if (!i.op[1].regs->reg_type.bitfield.dword)
6759
0
  return x86_tls_error_dest_32bit_reg_size;
6760
0
      break;
6761
6762
0
    case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
6763
      /* Check GOTPC32 TLSDESC access model:
6764
6765
   --- LP64 mode ---
6766
   leaq x@tlsdesc(%rip), %reg64 --> Memory reg must be %rip.
6767
6768
   --- X32 mode ---
6769
   rex/rex2 leal x@tlsdesc(%rip), %reg32 --> Memory reg must be %rip.
6770
6771
   In X32 mode, gas will add rex/rex2 for it later, no need to check
6772
   here.
6773
       */
6774
0
      if (i.tm.mnem_off != MN_lea)
6775
0
  return x86_tls_error_insn;
6776
0
      if (!i.base_reg)
6777
0
  return x86_tls_error_no_base_reg;
6778
0
      if (i.base_reg->reg_num != RegIP
6779
0
    || !i.base_reg->reg_type.bitfield.qword)
6780
0
  return x86_tls_error_rip;
6781
0
      if (x86_elf_abi == X86_64_ABI)
6782
0
  {
6783
0
    if (!i.op[1].regs->reg_type.bitfield.qword)
6784
0
      return x86_tls_error_dest_64bit_reg_size;
6785
0
  }
6786
0
      else if (!i.op[1].regs->reg_type.bitfield.dword
6787
0
         && !i.op[1].regs->reg_type.bitfield.qword)
6788
0
  return x86_tls_error_dest_32bit_or_64bit_reg_size;
6789
0
    break;
6790
6791
0
    case BFD_RELOC_X86_64_TLSGD:
6792
      /* Check GD access model:
6793
6794
   leaq foo@tlsgd(%rip), %rdi --> Only this fixed format is supported.
6795
       */
6796
0
    case BFD_RELOC_X86_64_TLSLD:
6797
      /* Check LD access model:
6798
6799
   leaq foo@tlsld(%rip), %rdi --> Only this fixed format is supported.
6800
       */
6801
0
      if (i.tm.mnem_off != MN_lea)
6802
0
  return x86_tls_error_insn;
6803
0
      if (!i.base_reg)
6804
0
  return x86_tls_error_no_base_reg;
6805
0
      if (i.base_reg->reg_num != RegIP
6806
0
    || !i.base_reg->reg_type.bitfield.qword)
6807
0
  return x86_tls_error_rip;
6808
0
      if (!i.op[1].regs->reg_type.bitfield.qword
6809
0
    || i.op[1].regs->reg_num != EDI_REG_NUM
6810
0
    || i.op[1].regs->reg_flags)
6811
0
  return x86_tls_error_dest_rdi;
6812
0
      break;
6813
6814
0
    case BFD_RELOC_386_TLS_GOTIE:
6815
      /* Check GOTIE access model:
6816
6817
   subl foo@gotntpoff(%reg1), %reg2
6818
   movl foo@gotntpoff(%reg1), %reg2
6819
   addl foo@gotntpoff(%reg1), %reg2
6820
6821
   Memory operand: SIB is not supported.
6822
       */
6823
0
    case BFD_RELOC_386_TLS_IE_32:
6824
      /* Check IE_32 access model:
6825
6826
   subl foo@gottpoff(%reg1), %reg2
6827
   movl foo@gottpoff(%reg1), %reg2
6828
   addl foo@gottpoff(%reg1), %reg2
6829
6830
   Memory operand: SIB is not supported.
6831
       */
6832
0
      if (i.tm.mnem_off != MN_sub
6833
0
    && i.tm.mnem_off != MN_add
6834
0
    && i.tm.mnem_off != MN_mov)
6835
0
  return x86_tls_error_insn;
6836
0
      if (i.imm_operands
6837
0
    || i.disp_operands != 1
6838
0
    || i.reg_operands != 1
6839
0
    || i.types[1].bitfield.class != Reg)
6840
0
  return x86_tls_error_opcode;
6841
0
      if (!i.base_reg)
6842
0
  return x86_tls_error_no_base_reg;
6843
0
      if (i.index_reg)
6844
0
  return x86_tls_error_sib;
6845
0
      if (!i.base_reg->reg_type.bitfield.dword)
6846
0
  return x86_tls_error_base_reg_size;
6847
0
      if (!i.op[1].regs->reg_type.bitfield.dword)
6848
0
  return x86_tls_error_dest_32bit_reg_size;
6849
0
      break;
6850
6851
0
    case BFD_RELOC_386_TLS_IE:
6852
      /* Check IE access model:
6853
6854
   movl foo@indntpoff, %reg32 --> Mod == 00 && r/m == 5
6855
   addl foo@indntpoff, %reg32 --> Mod == 00 && r/m == 5
6856
       */
6857
0
      if (i.tm.mnem_off != MN_add && i.tm.mnem_off != MN_mov)
6858
0
  return x86_tls_error_insn;
6859
0
      if (i.imm_operands
6860
0
    || i.disp_operands != 1
6861
0
    || i.reg_operands != 1
6862
0
    || i.types[1].bitfield.class != Reg)
6863
0
  return x86_tls_error_opcode;
6864
0
      if (i.base_reg || i.index_reg)
6865
0
  return x86_tls_error_require_no_base_index_reg;
6866
0
      if (!i.op[1].regs->reg_type.bitfield.dword)
6867
0
  return x86_tls_error_dest_32bit_reg_size;
6868
0
      break;
6869
6870
0
    case BFD_RELOC_X86_64_GOTTPOFF:
6871
      /* Check GOTTPOFF access model:
6872
6873
   mov foo@gottpoff(%rip), %reg --> Memory Reg must be %rip.
6874
   movrs foo@gottpoff(%rip), %reg --> Memory Reg must be %rip.
6875
   add foo@gottpoff(%rip), %reg --> Memory Reg must be %rip.
6876
   add %reg1, foo@gottpoff(%rip), %reg2 --> Memory Reg must be %rip.
6877
   add foo@gottpoff(%rip), %reg1, %reg2 --> Memory Reg must be %rip.
6878
       */
6879
0
      if (i.tm.mnem_off != MN_add && i.tm.mnem_off != MN_mov
6880
0
    && i.tm.mnem_off != MN_movrs)
6881
0
  return x86_tls_error_insn;
6882
0
      if (i.imm_operands
6883
0
    || i.disp_operands != 1
6884
0
    || i.types[i.operands - 1].bitfield.class != Reg)
6885
0
  return x86_tls_error_opcode;
6886
0
      if (!i.base_reg)
6887
0
  return x86_tls_error_no_base_reg;
6888
0
      if (i.base_reg->reg_num != RegIP
6889
0
    || !i.base_reg->reg_type.bitfield.qword)
6890
0
  return x86_tls_error_rip;
6891
0
      if (x86_elf_abi == X86_64_ABI)
6892
0
  {
6893
0
    if (!i.op[i.operands - 1].regs->reg_type.bitfield.qword)
6894
0
      return x86_tls_error_dest_64bit_reg_size;
6895
0
  }
6896
0
      else if (!i.op[i.operands - 1].regs->reg_type.bitfield.dword
6897
0
         && !i.op[i.operands - 1].regs->reg_type.bitfield.qword)
6898
0
  return x86_tls_error_dest_32bit_or_64bit_reg_size;
6899
0
      break;
6900
6901
0
    case BFD_RELOC_386_TLS_DESC_CALL:
6902
      /* Check GDesc access model:
6903
6904
   call *x@tlscall(%eax) --> Memory reg must be %eax and
6905
           SIB is not supported.
6906
       */
6907
0
    case BFD_RELOC_X86_64_TLSDESC_CALL:
6908
      /* Check GDesc access model:
6909
6910
   call *x@tlscall(%rax) <--- LP64 mode.
6911
   call *x@tlscall(%eax) <--- X32 mode.
6912
6913
   Only these fixed formats are supported.
6914
       */
6915
0
      if (i.tm.mnem_off != MN_call)
6916
0
  return x86_tls_error_insn;
6917
0
      if (i.index_reg)
6918
0
  return x86_tls_error_sib;
6919
0
      if (!i.base_reg)
6920
0
  return x86_tls_error_no_base_reg;
6921
0
      if (i.base_reg->reg_type.bitfield.instance != Accum)
6922
0
  return x86_tls_error_RegA;
6923
0
      break;
6924
6925
0
    case BFD_RELOC_NONE:
6926
      /* This isn't a relocation.  */
6927
0
      return x86_tls_error_continue;
6928
6929
0
    default:
6930
0
      break;
6931
0
    }
6932
6933
  /* This relocation is OK.  */
6934
0
  return x86_tls_error_none;
6935
0
}
6936
6937
static void
6938
x86_report_tls_error (enum x86_tls_error_type tls_error,
6939
          enum bfd_reloc_code_real r_type)
6940
0
{
6941
0
  unsigned int k;
6942
0
  for (k = 0; k < ARRAY_SIZE (gotrel); k++)
6943
0
    if (gotrel[k].rel[object_64bit] == r_type)
6944
0
      break;
6945
6946
0
  switch (tls_error)
6947
0
    {
6948
0
    case x86_tls_error_insn:
6949
0
      as_bad (_("@%s operator cannot be used with `%s'"),
6950
0
        gotrel[k].str, insn_name (&i.tm));
6951
0
      return;
6952
6953
0
    case x86_tls_error_opcode:
6954
0
      as_bad (_("@%s operator can be used with `%s', but format is wrong"),
6955
0
        gotrel[k].str, insn_name (&i.tm));
6956
0
      return;
6957
6958
0
    case x86_tls_error_sib:
6959
0
      as_bad (_("@%s operator requires no SIB"), gotrel[k].str);
6960
0
      return;
6961
6962
0
    case x86_tls_error_no_base_reg:
6963
0
      as_bad (_("@%s operator requires base register"), gotrel[k].str);
6964
0
      return;
6965
6966
0
    case x86_tls_error_require_no_base_index_reg:
6967
0
      as_bad (_("@%s operator requires no base/index register"),
6968
0
        gotrel[k].str);
6969
0
      return;
6970
6971
0
    case x86_tls_error_base_reg:
6972
0
      as_bad (_("@%s operator requires no base register"), gotrel[k].str);
6973
0
      return;
6974
6975
0
    case x86_tls_error_index_ebx:
6976
0
      as_bad (_("@%s operator requires `%sebx' as index register"),
6977
0
        gotrel[k].str, register_prefix);
6978
0
      return;
6979
6980
0
    case x86_tls_error_eax:
6981
0
      as_bad (_("@%s operator requires `%seax' as base register"),
6982
0
        gotrel[k].str, register_prefix);
6983
0
      return;
6984
6985
0
    case x86_tls_error_RegA:
6986
0
      as_bad (_("@%s operator requires `%seax/%srax' as base register"),
6987
0
        gotrel[k].str, register_prefix, register_prefix);
6988
0
      return;
6989
6990
0
    case x86_tls_error_ebx:
6991
0
      as_bad (_("@%s operator requires `%sebx' as base register"),
6992
0
        gotrel[k].str, register_prefix);
6993
0
      return;
6994
6995
0
    case x86_tls_error_rip:
6996
0
      as_bad (_("@%s operator requires `%srip' as base register"),
6997
0
        gotrel[k].str, register_prefix);
6998
0
      return;
6999
7000
0
    case x86_tls_error_dest_eax:
7001
0
      as_bad (_("@%s operator requires `%seax' as dest register"),
7002
0
        gotrel[k].str, register_prefix);
7003
0
      return;
7004
7005
0
    case x86_tls_error_dest_rdi:
7006
0
      as_bad (_("@%s operator requires `%srdi' as dest register"),
7007
0
        gotrel[k].str, register_prefix);
7008
0
      return;
7009
7010
0
    case x86_tls_error_scale_factor:
7011
0
      as_bad (_("@%s operator requires scale factor of 1"),
7012
0
        gotrel[k].str);
7013
0
      return;
7014
7015
0
    case x86_tls_error_base_reg_size:
7016
0
      as_bad (_("@%s operator requires 32-bit base register"),
7017
0
        gotrel[k].str);
7018
0
      return;
7019
7020
0
    case x86_tls_error_dest_32bit_reg_size:
7021
0
      as_bad (_("@%s operator requires 32-bit dest register"),
7022
0
        gotrel[k].str);
7023
0
      return;
7024
7025
0
    case x86_tls_error_dest_64bit_reg_size:
7026
0
      as_bad (_("@%s operator requires 64-bit dest register"),
7027
0
        gotrel[k].str);
7028
0
      return;
7029
7030
0
    case x86_tls_error_dest_32bit_or_64bit_reg_size:
7031
0
      as_bad (_("@%s operator requires 32-bit or 64-bit dest register"),
7032
0
        gotrel[k].str);
7033
0
      return;
7034
7035
0
    default:
7036
0
      abort ();
7037
0
    }
7038
0
}
7039
#endif
7040
7041
/* This is the guts of the machine-dependent assembler.  LINE points to a
7042
   machine dependent instruction.  This function is supposed to emit
7043
   the frags/bytes it assembles to.  */
7044
7045
static void
7046
i386_assemble (char *line)
7047
0
{
7048
0
  unsigned int j;
7049
0
  char mnemonic[MAX_MNEM_SIZE], mnem_suffix = 0, *copy = NULL;
7050
0
  char *xstrdup_copy = NULL;
7051
0
  const char *end, *pass1_mnem = NULL;
7052
0
  enum i386_error pass1_err = 0;
7053
0
  struct pseudo_prefixes orig_pp = pp;
7054
0
  const insn_template *t;
7055
0
  struct last_insn *last_insn
7056
0
    = &seg_info(now_seg)->tc_segment_info_data.last_insn;
7057
7058
  /* Initialize globals.  */
7059
0
  current_templates.end = current_templates.start = NULL;
7060
0
 retry:
7061
0
  init_globals ();
7062
7063
  /* Suppress optimization when the last thing we saw may not have been
7064
     a proper instruction (e.g. a stand-alone prefix or .byte).  */
7065
0
  if (last_insn->kind != last_insn_other)
7066
0
    pp.no_optimize = true;
7067
7068
  /* First parse an instruction mnemonic & call i386_operand for the operands.
7069
     We assume that the scrubber has arranged it so that line[0] is the valid
7070
     start of a (possibly prefixed) mnemonic.  */
7071
7072
0
  end = parse_insn (line, mnemonic, parse_all);
7073
0
  if (end == NULL)
7074
0
    {
7075
0
      if (pass1_mnem != NULL)
7076
0
  goto match_error;
7077
0
      if (i.error != no_error)
7078
0
  {
7079
0
    gas_assert (current_templates.start != NULL);
7080
0
    if (may_need_pass2 (current_templates.start) && !i.suffix)
7081
0
      goto no_match;
7082
    /* No point in trying a 2nd pass - it'll only find the same suffix
7083
       again.  */
7084
0
    mnem_suffix = i.suffix;
7085
0
    goto match_error;
7086
0
  }
7087
0
      return;
7088
0
    }
7089
0
  t = current_templates.start;
7090
  /* NB: LINE may be change to be the same as XSTRDUP_COPY.  */
7091
0
  if (xstrdup_copy != line && may_need_pass2 (t))
7092
0
    {
7093
      /* Make a copy of the full line in case we need to retry.  */
7094
0
      xstrdup_copy = xstrdup (line);
7095
0
      copy = xstrdup_copy;
7096
0
    }
7097
0
  line += end - line;
7098
0
  mnem_suffix = i.suffix;
7099
7100
0
  line = parse_operands (line, mnemonic);
7101
0
  this_operand = -1;
7102
0
  if (line == NULL)
7103
0
    {
7104
0
      free (xstrdup_copy);
7105
0
      return;
7106
0
    }
7107
7108
  /* Now we've parsed the mnemonic into a set of templates, and have the
7109
     operands at hand.  */
7110
7111
  /* All Intel opcodes have reversed operands except for "bound", "enter",
7112
     "invlpg*", "monitor*", "mwait*", "tpause", "umwait", "pvalidate",
7113
     "rmpadjust", "rmpquery", and deprecated forms of "rmpupdate".
7114
     We also don't reverse intersegment "jmp" and "call" instructions with
7115
     2 immediate operands so that the immediate segment precedes the offset
7116
     consistently in Intel and AT&T modes.  */
7117
0
  if (intel_syntax
7118
0
      && i.operands > 1
7119
0
      && (t->mnem_off != MN_bound)
7120
0
      && !startswith (mnemonic, "invlpg")
7121
0
      && !startswith (mnemonic, "monitor")
7122
0
      && !startswith (mnemonic, "mwait")
7123
0
      && (t->mnem_off != MN_pvalidate)
7124
0
      && (!startswith (mnemonic, "rmp") || i.mem_operands)
7125
0
      && (t->mnem_off != MN_tpause)
7126
0
      && (t->mnem_off != MN_umwait)
7127
0
      && !(i.operands == 2
7128
0
     && operand_type_check (i.types[0], imm)
7129
0
     && operand_type_check (i.types[1], imm)))
7130
0
    swap_operands ();
7131
7132
  /* The order of the immediates should be reversed for 2-immediates EXTRQ
7133
     and INSERTQ instructions.  Also OUT, UWRMSR, and WRMSRNS want their
7134
     immediate to be in the "canonical" place (first), despite it appearing
7135
     last (in AT&T syntax, or because of the swapping above) in the incoming
7136
     set of operands.  */
7137
0
  if ((i.imm_operands == 2
7138
0
       && (t->mnem_off == MN_extrq || t->mnem_off == MN_insertq))
7139
0
      || ((t->mnem_off == MN_out || t->mnem_off == MN_uwrmsr
7140
0
     || t->mnem_off == MN_wrmsrns)
7141
0
    && i.imm_operands && i.operands > i.imm_operands))
7142
0
      swap_2_operands (0, 1);
7143
7144
0
  if (i.imm_operands)
7145
0
    {
7146
      /* For USER_MSR and MSR_IMM instructions, imm32 stands for the name of a
7147
   model specific register (MSR). That's an unsigned quantity, whereas all
7148
   other insns with 32-bit immediate and 64-bit operand size use
7149
   sign-extended immediates (imm32s). Therefore these insns are
7150
   special-cased, bypassing the normal handling of immediates here.  */
7151
0
      if (is_cpu(current_templates.start, CpuUSER_MSR)
7152
0
    || t->mnem_off == MN_rdmsr
7153
0
    || t->mnem_off == MN_wrmsrns)
7154
0
  {
7155
0
    for (j = 0; j < i.imm_operands; j++)
7156
0
      i.types[j] = smallest_imm_type (i.op[j].imms->X_add_number);
7157
0
  }
7158
0
      else
7159
0
  optimize_imm ();
7160
0
    }
7161
7162
0
  if (i.disp_operands && !optimize_disp (t))
7163
0
    return;
7164
7165
  /* Next, we find a template that matches the given insn,
7166
     making sure the overlap of the given operands types is consistent
7167
     with the template operand types.  */
7168
7169
0
  if (!(t = match_template (mnem_suffix)))
7170
0
    {
7171
0
      const char *err_msg;
7172
7173
0
      if (copy && !mnem_suffix)
7174
0
  {
7175
0
    line = copy;
7176
0
    copy = NULL;
7177
0
  no_match:
7178
0
    pass1_err = i.error;
7179
0
    pass1_mnem = insn_name (current_templates.start);
7180
0
    pp = orig_pp;
7181
0
    goto retry;
7182
0
  }
7183
7184
      /* If a non-/only-64bit template (group) was found in pass 1, and if
7185
   _some_ template (group) was found in pass 2, squash pass 1's
7186
   error.  */
7187
0
      if (pass1_err == unsupported_64bit)
7188
0
  pass1_mnem = NULL;
7189
7190
0
  match_error:
7191
0
      free (xstrdup_copy);
7192
7193
0
      switch (pass1_mnem ? pass1_err : i.error)
7194
0
  {
7195
0
  default:
7196
0
    abort ();
7197
0
  case operand_size_mismatch:
7198
0
    err_msg = _("operand size mismatch");
7199
0
    break;
7200
0
  case operand_type_mismatch:
7201
0
    err_msg = _("operand type mismatch");
7202
0
    break;
7203
0
  case register_type_mismatch:
7204
0
    err_msg = _("register type mismatch");
7205
0
    break;
7206
0
  case number_of_operands_mismatch:
7207
0
    err_msg = _("number of operands mismatch");
7208
0
    break;
7209
0
  case invalid_instruction_suffix:
7210
0
    err_msg = _("invalid instruction suffix");
7211
0
    break;
7212
0
  case bad_imm4:
7213
0
    err_msg = _("constant doesn't fit in 4 bits");
7214
0
    break;
7215
0
  case unsupported_with_intel_mnemonic:
7216
0
    err_msg = _("unsupported with Intel mnemonic");
7217
0
    break;
7218
0
  case unsupported_syntax:
7219
0
    err_msg = _("unsupported syntax");
7220
0
    break;
7221
0
  case unsupported_EGPR_for_addressing:
7222
0
    err_msg = _("extended GPR cannot be used as base/index");
7223
0
    break;
7224
0
  case unsupported_nf:
7225
0
    err_msg = _("{nf} unsupported");
7226
0
    break;
7227
0
  case unsupported:
7228
0
    as_bad (_("unsupported instruction `%s'"),
7229
0
      pass1_mnem ? pass1_mnem : insn_name (current_templates.start));
7230
0
    return;
7231
0
  case unsupported_on_arch:
7232
0
    as_bad (_("`%s' is not supported on `%s%s'"),
7233
0
      pass1_mnem ? pass1_mnem : insn_name (current_templates.start),
7234
0
      cpu_arch_name ? cpu_arch_name : default_arch,
7235
0
      cpu_sub_arch_name ? cpu_sub_arch_name : "");
7236
0
    return;
7237
0
  case unsupported_64bit:
7238
0
    if (ISLOWER (mnem_suffix))
7239
0
      {
7240
0
        if (flag_code == CODE_64BIT)
7241
0
    as_bad (_("`%s%c' is not supported in 64-bit mode"),
7242
0
      pass1_mnem ? pass1_mnem : insn_name (current_templates.start),
7243
0
      mnem_suffix);
7244
0
        else
7245
0
    as_bad (_("`%s%c' is only supported in 64-bit mode"),
7246
0
      pass1_mnem ? pass1_mnem : insn_name (current_templates.start),
7247
0
      mnem_suffix);
7248
0
      }
7249
0
    else
7250
0
      {
7251
0
        if (flag_code == CODE_64BIT)
7252
0
    as_bad (_("`%s' is not supported in 64-bit mode"),
7253
0
      pass1_mnem ? pass1_mnem : insn_name (current_templates.start));
7254
0
        else
7255
0
    as_bad (_("`%s' is only supported in 64-bit mode"),
7256
0
      pass1_mnem ? pass1_mnem : insn_name (current_templates.start));
7257
0
      }
7258
0
    return;
7259
0
  case no_vex_encoding:
7260
0
    err_msg = _("no VEX/XOP encoding");
7261
0
    break;
7262
0
  case no_evex_encoding:
7263
0
    err_msg = _("no EVEX encoding");
7264
0
    break;
7265
0
  case invalid_sib_address:
7266
0
    err_msg = _("invalid SIB address");
7267
0
    break;
7268
0
  case invalid_vsib_address:
7269
0
    err_msg = _("invalid VSIB address");
7270
0
    break;
7271
0
  case invalid_vector_register_set:
7272
0
    err_msg = _("mask, index, and destination registers must be distinct");
7273
0
    break;
7274
0
  case invalid_tmm_register_set:
7275
0
    err_msg = _("all tmm registers must be distinct");
7276
0
    break;
7277
0
  case invalid_dest_and_src_register_set:
7278
0
    err_msg = _("destination and source registers must be distinct");
7279
0
    break;
7280
0
  case invalid_dest_register_set:
7281
0
    err_msg = _("two dest registers must be distinct");
7282
0
    break;
7283
0
  case invalid_pseudo_prefix:
7284
0
    err_msg = _("rex2 pseudo prefix cannot be used");
7285
0
    break;
7286
0
  case unsupported_vector_index_register:
7287
0
    err_msg = _("unsupported vector index register");
7288
0
    break;
7289
0
  case unsupported_broadcast:
7290
0
    err_msg = _("unsupported broadcast");
7291
0
    break;
7292
0
  case broadcast_needed:
7293
0
    err_msg = _("broadcast is needed for operand of such type");
7294
0
    break;
7295
0
  case unsupported_masking:
7296
0
    err_msg = _("unsupported masking");
7297
0
    break;
7298
0
  case mask_not_on_destination:
7299
0
    err_msg = _("mask not on destination operand");
7300
0
    break;
7301
0
  case no_default_mask:
7302
0
    err_msg = _("default mask isn't allowed");
7303
0
    break;
7304
0
  case unsupported_rc_sae:
7305
0
    err_msg = _("unsupported static rounding/sae");
7306
0
    break;
7307
0
  case unsupported_vector_size:
7308
0
    as_bad (_("vector size above %u required for `%s'"), 128u << vector_size,
7309
0
      pass1_mnem ? pass1_mnem : insn_name (current_templates.start));
7310
0
    return;
7311
0
  case unsupported_rsp_register:
7312
0
    err_msg = _("'rsp' register cannot be used");
7313
0
    break;
7314
0
  case internal_error:
7315
0
    err_msg = _("internal error");
7316
0
    break;
7317
0
  }
7318
0
      as_bad (_("%s for `%s'"), err_msg,
7319
0
        pass1_mnem ? pass1_mnem : insn_name (current_templates.start));
7320
0
      return;
7321
0
    }
7322
7323
0
  free (xstrdup_copy);
7324
7325
0
  if (sse_check != check_none
7326
      /* The opcode space check isn't strictly needed; it's there only to
7327
   bypass the logic below when easily possible.  */
7328
0
      && t->opcode_space >= SPACE_0F
7329
0
      && t->opcode_space <= SPACE_0F3A
7330
0
      && !is_cpu (&i.tm, CpuSSE4a)
7331
0
      && !is_any_vex_encoding (t))
7332
0
    {
7333
      /* Some KL and all WideKL insns have only implicit %xmm operands.  */
7334
0
      bool simd = is_cpu (t, CpuKL) || is_cpu (t, CpuWideKL);
7335
7336
0
      for (j = 0; j < t->operands; ++j)
7337
0
  {
7338
0
    if (t->operand_types[j].bitfield.class == RegMMX)
7339
0
      break;
7340
0
    if (t->operand_types[j].bitfield.class == RegSIMD)
7341
0
      simd = true;
7342
0
  }
7343
7344
0
      if (j >= t->operands && simd)
7345
0
  (sse_check == check_warning
7346
0
   ? as_warn
7347
0
   : as_bad) (_("SSE instruction `%s' is used"), insn_name (&i.tm));
7348
0
    }
7349
7350
0
  if (i.tm.opcode_modifier.fwait)
7351
0
    if (!add_prefix (FWAIT_OPCODE))
7352
0
      return;
7353
7354
  /* Check if REP prefix is OK.  */
7355
0
  if (i.rep_prefix && i.tm.opcode_modifier.prefixok != PrefixRep)
7356
0
    {
7357
0
      as_bad (_("invalid instruction `%s' after `%s'"),
7358
0
    insn_name (&i.tm), i.rep_prefix);
7359
0
      return;
7360
0
    }
7361
7362
  /* Check for lock without a lockable instruction.  Destination operand
7363
     must be memory unless it is xchg (0x86).  */
7364
0
  if (i.prefix[LOCK_PREFIX])
7365
0
    {
7366
0
      if (i.tm.opcode_modifier.prefixok < PrefixLock
7367
0
    || i.mem_operands == 0
7368
0
    || (i.tm.base_opcode != 0x86
7369
0
        && !(i.flags[i.operands - 1] & Operand_Mem)))
7370
0
  {
7371
0
    as_bad (_("expecting lockable instruction after `lock'"));
7372
0
    return;
7373
0
  }
7374
7375
      /* Zap the redundant prefix from XCHG when optimizing.  */
7376
0
      if (i.tm.base_opcode == 0x86 && optimize && !pp.no_optimize)
7377
0
  i.prefix[LOCK_PREFIX] = 0;
7378
0
    }
7379
7380
0
#ifdef OBJ_ELF
7381
0
  if (i.has_gotrel && tls_check)
7382
0
    {
7383
0
      enum x86_tls_error_type tls_error;
7384
0
      for (j = 0; j < i.operands; ++j)
7385
0
  {
7386
0
    tls_error = x86_check_tls_relocation (i.reloc[j]);
7387
0
    if (tls_error == x86_tls_error_continue)
7388
0
      continue;
7389
7390
0
    if (tls_error != x86_tls_error_none)
7391
0
      x86_report_tls_error (tls_error, i.reloc[j]);
7392
0
    break;
7393
0
  }
7394
0
    }
7395
0
#endif
7396
7397
0
  if ((is_any_vex_encoding (&i.tm) && i.tm.opcode_space != SPACE_MAP4)
7398
0
      || i.tm.operand_types[i.imm_operands].bitfield.class >= RegMMX
7399
0
      || i.tm.operand_types[i.imm_operands + 1].bitfield.class >= RegMMX)
7400
0
    {
7401
      /* Check for data size prefix on VEX/XOP/EVEX encoded and SIMD insns.  */
7402
0
      if (i.prefix[DATA_PREFIX])
7403
0
  {
7404
0
    as_bad (_("data size prefix invalid with `%s'"), insn_name (&i.tm));
7405
0
    return;
7406
0
  }
7407
0
    }
7408
7409
  /* Check if HLE prefix is OK.  */
7410
0
  if (i.hle_prefix && !check_hle ())
7411
0
    return;
7412
7413
  /* Check BND prefix.  */
7414
0
  if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
7415
0
    as_bad (_("expecting valid branch instruction after `bnd'"));
7416
7417
  /* Check NOTRACK prefix.  */
7418
0
  if (i.notrack_prefix && i.tm.opcode_modifier.prefixok != PrefixNoTrack)
7419
0
    as_bad (_("expecting indirect branch instruction after `notrack'"));
7420
7421
0
  if (is_cpu (&i.tm, CpuMPX))
7422
0
    {
7423
0
      if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX])
7424
0
  as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
7425
0
      else if (flag_code != CODE_16BIT
7426
0
         ? i.prefix[ADDR_PREFIX]
7427
0
         : i.mem_operands && !i.prefix[ADDR_PREFIX])
7428
0
  as_bad (_("16-bit address isn't allowed in MPX instructions"));
7429
0
    }
7430
7431
  /* Insert BND prefix.  */
7432
0
  if (add_bnd_prefix && i.tm.opcode_modifier.bndprefixok)
7433
0
    {
7434
0
      if (!i.prefix[BND_PREFIX])
7435
0
  add_prefix (BND_PREFIX_OPCODE);
7436
0
      else if (i.prefix[BND_PREFIX] != BND_PREFIX_OPCODE)
7437
0
  {
7438
0
    as_warn (_("replacing `rep'/`repe' prefix by `bnd'"));
7439
0
    i.prefix[BND_PREFIX] = BND_PREFIX_OPCODE;
7440
0
  }
7441
0
    }
7442
7443
  /* Check string instruction segment overrides.  */
7444
0
  if (i.tm.opcode_modifier.isstring >= IS_STRING_ES_OP0)
7445
0
    {
7446
0
      gas_assert (i.mem_operands);
7447
0
      if (!check_string ())
7448
0
  return;
7449
0
      i.disp_operands = 0;
7450
0
    }
7451
7452
  /* The memory operand of (%dx) should be only used with input/output
7453
     instructions (base opcodes: 0x6c, 0x6e, 0xec, 0xee).  */
7454
0
  if (i.input_output_operand
7455
0
      && ((i.tm.base_opcode | 0x82) != 0xee
7456
0
    || i.tm.opcode_space != SPACE_BASE))
7457
0
    {
7458
0
      as_bad (_("input/output port address isn't allowed with `%s'"),
7459
0
        insn_name (&i.tm));
7460
0
      return;
7461
0
    }
7462
7463
0
  if (optimize && !pp.no_optimize && i.tm.opcode_modifier.optimize)
7464
0
    {
7465
0
      if (pp.has_nf)
7466
0
  optimize_nf_encoding ();
7467
0
      optimize_encoding ();
7468
0
    }
7469
7470
  /* Past optimization there's no need to distinguish encoding_evex,
7471
     encoding_evex512, and encoding_egpr anymore.  */
7472
0
  if (pp.encoding == encoding_evex512)
7473
0
    pp.encoding = encoding_evex;
7474
0
  else if (pp.encoding == encoding_egpr)
7475
0
    pp.encoding = is_any_vex_encoding (&i.tm) ? encoding_evex
7476
0
               : encoding_default;
7477
7478
  /* Similarly {nf} can now be taken to imply {evex}.  */
7479
0
  if (pp.has_nf && pp.encoding == encoding_default)
7480
0
    pp.encoding = encoding_evex;
7481
7482
0
  if (use_unaligned_vector_move)
7483
0
    encode_with_unaligned_vector_move ();
7484
7485
0
  if (!process_suffix (t))
7486
0
    return;
7487
7488
  /* Check if IP-relative addressing requirements can be satisfied.  */
7489
0
  if (is_cpu (&i.tm, CpuPREFETCHI)
7490
0
      && !(i.base_reg && i.base_reg->reg_num == RegIP))
7491
0
    as_warn (_("'%s' only supports RIP-relative address"), insn_name (&i.tm));
7492
7493
  /* Update operand types and check extended states.  */
7494
0
  for (j = 0; j < i.operands; j++)
7495
0
    {
7496
0
      enum operand_class class = i.types[j].bitfield.class;
7497
7498
0
      i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
7499
0
      switch (i.tm.operand_types[j].bitfield.class)
7500
0
  {
7501
0
  default:
7502
0
    break;
7503
0
  case RegMMX:
7504
0
    i.xstate |= xstate_mmx;
7505
0
    break;
7506
0
  case RegMask:
7507
0
    i.xstate |= xstate_mask;
7508
0
    break;
7509
0
  case RegSIMD:
7510
0
    if (i.tm.operand_types[j].bitfield.tmmword)
7511
0
      i.xstate |= xstate_tmm;
7512
0
    else if (i.tm.operand_types[j].bitfield.zmmword
7513
0
       && !i.tm.opcode_modifier.vex
7514
0
       && vector_size >= VSZ512)
7515
0
      i.xstate |= xstate_zmm;
7516
0
    else if (i.tm.operand_types[j].bitfield.ymmword
7517
0
       && vector_size >= VSZ256)
7518
0
      i.xstate |= xstate_ymm;
7519
0
    else if (i.tm.operand_types[j].bitfield.xmmword)
7520
0
      i.xstate |= xstate_xmm;
7521
0
    break;
7522
0
  case ClassNone:
7523
0
    i.types[j].bitfield.class = class;
7524
0
    break;
7525
0
  }
7526
0
    }
7527
7528
  /* Make still unresolved immediate matches conform to size of immediate
7529
     given in i.suffix.  */
7530
0
  if (!finalize_imm ())
7531
0
    return;
7532
7533
0
  if (i.types[0].bitfield.imm1)
7534
0
    i.imm_operands = 0; /* kludge for shift insns.  */
7535
7536
  /* For insns with operands there are more diddles to do to the opcode.  */
7537
0
  if (i.operands)
7538
0
    {
7539
0
      if (!process_operands ())
7540
0
  return;
7541
0
    }
7542
0
  else if (!quiet_warnings && i.tm.opcode_modifier.operandconstraint == UGH)
7543
0
    {
7544
      /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc.  */
7545
0
      as_warn (_("translating to `%sp'"), insn_name (&i.tm));
7546
0
    }
7547
7548
0
  if (is_any_vex_encoding (&i.tm))
7549
0
    {
7550
0
      if (!cpu_arch_flags.bitfield.cpui286)
7551
0
  {
7552
0
    as_bad (_("instruction `%s' isn't supported outside of protected mode."),
7553
0
      insn_name (&i.tm));
7554
0
    return;
7555
0
  }
7556
7557
      /* Check for explicit REX prefix.  */
7558
0
      if ((i.prefix[REX_PREFIX]
7559
0
     && (i.tm.opcode_space != SPACE_MAP4
7560
         /* To mimic behavior for legacy insns, permit use of REX64 for promoted
7561
      legacy instructions.  */
7562
0
         || i.prefix[REX_PREFIX] != (REX_OPCODE | REX_W)))
7563
0
    || pp.rex_encoding)
7564
0
  {
7565
0
    as_bad (_("REX prefix invalid with `%s'"), insn_name (&i.tm));
7566
0
    return;
7567
0
  }
7568
7569
      /* Check for explicit REX2 prefix.  */
7570
0
      if (pp.rex2_encoding)
7571
0
  {
7572
0
    as_bad (_("{rex2} prefix invalid with `%s'"), insn_name (&i.tm));
7573
0
    return;
7574
0
  }
7575
7576
0
      if (is_apx_evex_encoding ())
7577
0
  {
7578
0
    if (!build_apx_evex_prefix (false))
7579
0
      return;
7580
0
  }
7581
0
      else if (i.tm.opcode_modifier.vex)
7582
0
  build_vex_prefix (t);
7583
0
      else
7584
0
  build_evex_prefix ();
7585
7586
      /* The individual REX.RXBW bits got consumed.  */
7587
0
      i.rex &= REX_OPCODE;
7588
7589
      /* The rex2 bits got consumed.  */
7590
0
      i.rex2 = 0;
7591
0
    }
7592
7593
  /* Handle conversion of 'int $3' --> special int3 insn.  */
7594
0
  if (i.tm.mnem_off == MN_int
7595
0
      && i.op[0].imms->X_add_number == 3)
7596
0
    {
7597
0
      i.tm.base_opcode = INT3_OPCODE;
7598
0
      i.imm_operands = 0;
7599
0
    }
7600
7601
0
  if ((i.tm.opcode_modifier.jump == JUMP
7602
0
       || i.tm.opcode_modifier.jump == JUMP_BYTE
7603
0
       || i.tm.opcode_modifier.jump == JUMP_DWORD)
7604
0
      && i.op[0].disps->X_op == O_constant)
7605
0
    {
7606
      /* Convert "jmp constant" (and "call constant") to a jump (call) to
7607
   the absolute address given by the constant.  Since ix86 jumps and
7608
   calls are pc relative, we need to generate a reloc.  */
7609
0
      i.op[0].disps->X_add_symbol = &abs_symbol;
7610
0
      i.op[0].disps->X_op = O_symbol;
7611
0
    }
7612
7613
0
  establish_rex ();
7614
7615
0
  insert_lfence_before (last_insn);
7616
7617
  /* We are ready to output the insn.  */
7618
0
  output_insn (last_insn);
7619
7620
0
#ifdef OBJ_ELF
7621
  /* PS: SCFI is enabled only for System V AMD64 ABI.  The ABI check has been
7622
     performed in i386_target_format.  */
7623
0
  if (flag_synth_cfi)
7624
0
    {
7625
0
      ginsnS *ginsn;
7626
0
      ginsn = x86_ginsn_new (symbol_temp_new_now (), frch_ginsn_gen_mode ());
7627
0
      frch_ginsn_data_append (ginsn);
7628
0
    }
7629
0
#endif
7630
7631
0
  insert_lfence_after ();
7632
7633
0
  if (i.tm.opcode_modifier.isprefix)
7634
0
    {
7635
0
      last_insn->kind = last_insn_prefix;
7636
0
      last_insn->name = insn_name (&i.tm);
7637
0
      last_insn->file = as_where (&last_insn->line);
7638
0
    }
7639
0
  else
7640
0
    last_insn->kind = last_insn_other;
7641
0
}
7642
7643
void
7644
md_assemble (char *line)
7645
0
{
7646
0
  i386_assemble (line);
7647
0
  current_templates.start = NULL;
7648
0
  memset (&pp, 0, sizeof (pp));
7649
0
}
7650
7651
/* The Q suffix is generally valid only in 64-bit mode, with very few
7652
   exceptions: fild, fistp, fisttp, and cmpxchg8b.  Note that for fild
7653
   and fisttp only one of their two templates is matched below: That's
7654
   sufficient since other relevant attributes are the same between both
7655
   respective templates.  */
7656
static INLINE bool q_suffix_allowed(const insn_template *t)
7657
0
{
7658
0
  return flag_code == CODE_64BIT
7659
0
   || (t->opcode_space == SPACE_BASE
7660
0
       && t->base_opcode == 0xdf
7661
0
       && (t->extension_opcode & 1)) /* fild / fistp / fisttp */
7662
0
   || t->mnem_off == MN_cmpxchg8b;
7663
0
}
7664
7665
static const char *
7666
parse_insn (const char *line, char *mnemonic, enum parse_mode mode)
7667
0
{
7668
0
  const char *l = line, *token_start = l;
7669
0
  char *mnem_p;
7670
0
  bool pass1 = !current_templates.start;
7671
0
  int supported;
7672
0
  const insn_template *t;
7673
0
  char *dot_p = NULL;
7674
7675
0
  while (1)
7676
0
    {
7677
0
      const char *split;
7678
7679
0
      mnem_p = mnemonic;
7680
      /* Pseudo-prefixes start with an opening figure brace.  */
7681
0
      if ((*mnem_p = *l) == '{')
7682
0
  {
7683
0
    ++mnem_p;
7684
0
    ++l;
7685
0
    if (is_whitespace (*l))
7686
0
      ++l;
7687
0
  }
7688
0
      else if (mode == parse_pseudo_prefix)
7689
0
  break;
7690
0
      while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
7691
0
  {
7692
0
    if (*mnem_p == '.')
7693
0
      dot_p = mnem_p;
7694
0
    mnem_p++;
7695
0
    if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
7696
0
      {
7697
0
      too_long:
7698
0
        as_bad (_("no such instruction: `%s'"), token_start);
7699
0
        return NULL;
7700
0
      }
7701
0
    l++;
7702
0
  }
7703
0
      split = l;
7704
0
      if (is_whitespace (*l))
7705
0
  ++l;
7706
      /* Pseudo-prefixes end with a closing figure brace.  */
7707
0
      if (*mnemonic == '{' && *l == '}')
7708
0
  {
7709
0
    *mnem_p++ = *l++;
7710
0
    if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
7711
0
      goto too_long;
7712
0
    *mnem_p = '\0';
7713
7714
0
    if (is_whitespace (*l))
7715
0
      ++l;
7716
0
  }
7717
0
      else if (l == split
7718
0
         && *l != END_OF_INSN
7719
0
         && (intel_syntax
7720
0
       || (*l != PREFIX_SEPARATOR && *l != ',')))
7721
0
  {
7722
0
    if (mode != parse_all)
7723
0
      break;
7724
0
    as_bad (_("invalid character %s in mnemonic"),
7725
0
      output_invalid (*split));
7726
0
    return NULL;
7727
0
  }
7728
0
      if (token_start == l)
7729
0
  {
7730
0
    if (!intel_syntax && *l == PREFIX_SEPARATOR)
7731
0
      as_bad (_("expecting prefix; got nothing"));
7732
0
    else
7733
0
      as_bad (_("expecting mnemonic; got nothing"));
7734
0
    return NULL;
7735
0
  }
7736
7737
      /* Look up instruction (or prefix) via hash table.  */
7738
0
      op_lookup (mnemonic);
7739
7740
0
      if (*l != END_OF_INSN
7741
0
    && current_templates.start
7742
0
    && current_templates.start->opcode_modifier.isprefix)
7743
0
  {
7744
0
    supported = cpu_flags_match (current_templates.start);
7745
0
    if (!(supported & CPU_FLAGS_64BIT_MATCH))
7746
0
      {
7747
0
        as_bad ((flag_code != CODE_64BIT
7748
0
           ? _("`%s' is only supported in 64-bit mode")
7749
0
           : _("`%s' is not supported in 64-bit mode")),
7750
0
          insn_name (current_templates.start));
7751
0
        return NULL;
7752
0
      }
7753
0
    if (supported != CPU_FLAGS_PERFECT_MATCH)
7754
0
      {
7755
0
        as_bad (_("`%s' is not supported on `%s%s'"),
7756
0
          insn_name (current_templates.start),
7757
0
          cpu_arch_name ? cpu_arch_name : default_arch,
7758
0
          cpu_sub_arch_name ? cpu_sub_arch_name : "");
7759
0
        return NULL;
7760
0
      }
7761
    /* If we are in 16-bit mode, do not allow addr16 or data16.
7762
       Similarly, in 32-bit mode, do not allow addr32 or data32.  */
7763
0
    if ((current_templates.start->opcode_modifier.size == SIZE16
7764
0
         || current_templates.start->opcode_modifier.size == SIZE32)
7765
0
        && flag_code != CODE_64BIT
7766
0
        && ((current_templates.start->opcode_modifier.size == SIZE32)
7767
0
      ^ (flag_code == CODE_16BIT)))
7768
0
      {
7769
0
        as_bad (_("redundant %s prefix"),
7770
0
          insn_name (current_templates.start));
7771
0
        return NULL;
7772
0
      }
7773
7774
0
    if (current_templates.start->base_opcode == PSEUDO_PREFIX)
7775
0
      {
7776
        /* Handle pseudo prefixes.  */
7777
0
        switch (current_templates.start->extension_opcode)
7778
0
    {
7779
0
    case Prefix_Disp8:
7780
      /* {disp8} */
7781
0
      pp.disp_encoding = disp_encoding_8bit;
7782
0
      break;
7783
0
    case Prefix_Disp16:
7784
      /* {disp16} */
7785
0
      pp.disp_encoding = disp_encoding_16bit;
7786
0
      break;
7787
0
    case Prefix_Disp32:
7788
      /* {disp32} */
7789
0
      pp.disp_encoding = disp_encoding_32bit;
7790
0
      break;
7791
0
    case Prefix_Load:
7792
      /* {load} */
7793
0
      pp.dir_encoding = dir_encoding_load;
7794
0
      break;
7795
0
    case Prefix_Store:
7796
      /* {store} */
7797
0
      pp.dir_encoding = dir_encoding_store;
7798
0
      break;
7799
0
    case Prefix_VEX:
7800
      /* {vex} */
7801
0
      pp.encoding = encoding_vex;
7802
0
      break;
7803
0
    case Prefix_VEX3:
7804
      /* {vex3} */
7805
0
      pp.encoding = encoding_vex3;
7806
0
      break;
7807
0
    case Prefix_EVEX:
7808
      /* {evex} */
7809
0
      pp.encoding = encoding_evex;
7810
0
      break;
7811
0
    case Prefix_REX:
7812
      /* {rex} */
7813
0
      pp.rex_encoding = true;
7814
0
      break;
7815
0
    case Prefix_REX2:
7816
      /* {rex2} */
7817
0
      pp.rex2_encoding = true;
7818
0
      break;
7819
0
    case Prefix_NF:
7820
      /* {nf} */
7821
0
      pp.has_nf = true;
7822
0
      break;
7823
0
    case Prefix_NoOptimize:
7824
      /* {nooptimize} */
7825
0
      pp.no_optimize = true;
7826
0
      break;
7827
0
    case Prefix_NoImm8s:
7828
      /* {noimm8s} */
7829
0
      pp.no_imm8s = true;
7830
0
      break;
7831
0
    default:
7832
0
      abort ();
7833
0
    }
7834
0
        if (pp.has_nf
7835
0
      && pp.encoding != encoding_default
7836
0
      && pp.encoding != encoding_evex)
7837
0
    {
7838
0
      as_bad (_("{nf} cannot be combined with {vex}/{vex3}"));
7839
0
      return NULL;
7840
0
    }
7841
0
      }
7842
0
    else
7843
0
      {
7844
        /* Add prefix, checking for repeated prefixes.  */
7845
0
        switch (add_prefix (current_templates.start->base_opcode))
7846
0
    {
7847
0
    case PREFIX_EXIST:
7848
0
      return NULL;
7849
0
    case PREFIX_DS:
7850
0
      if (is_cpu (current_templates.start, CpuIBT))
7851
0
        i.notrack_prefix = insn_name (current_templates.start);
7852
0
      break;
7853
0
    case PREFIX_REP:
7854
0
      if (is_cpu (current_templates.start, CpuHLE))
7855
0
        i.hle_prefix = insn_name (current_templates.start);
7856
0
      else if (is_cpu (current_templates.start, CpuMPX))
7857
0
        i.bnd_prefix = insn_name (current_templates.start);
7858
0
      else
7859
0
        i.rep_prefix = insn_name (current_templates.start);
7860
0
      break;
7861
0
    default:
7862
0
      break;
7863
0
    }
7864
0
      }
7865
    /* Skip past PREFIX_SEPARATOR and reset token_start.  */
7866
0
    l += (!intel_syntax && *l == PREFIX_SEPARATOR);
7867
0
    if (is_whitespace (*l))
7868
0
      ++l;
7869
0
    token_start = l;
7870
0
  }
7871
0
      else
7872
0
  break;
7873
0
    }
7874
7875
0
  if (mode != parse_all)
7876
0
    return token_start;
7877
7878
0
  if (!current_templates.start)
7879
0
    {
7880
#ifdef TE_SOLARIS
7881
      /* Sun specifies an alternative form for CMOVcc: Size suffix (if any)
7882
   first, then a dot, then the condition code mnemonic.  */
7883
      if ((mnemonic + 4 == dot_p && !memcmp (mnemonic, "cmov", 4))
7884
    /* While doc doesn't say so, gcc assumes it: Same for FCMOVcc,
7885
       except that there's no size suffix to care about.  */
7886
    || (mnemonic + 5 == dot_p && !memcmp (mnemonic, "fcmov", 5)))
7887
  {
7888
    /* Simply strip the dot.  */
7889
    memmove (dot_p, dot_p + 1, mnem_p - dot_p);
7890
    dot_p = mnem_p - 1;
7891
  }
7892
      else if (!intel_syntax
7893
         && mnemonic + 5 == dot_p
7894
         && !memcmp (mnemonic, "cmov", 4)
7895
         && strchr ("lqw", TOLOWER (dot_p[-1])))
7896
  {
7897
    /* Strip the dot, while moving the suffix.  */
7898
    char suffix = dot_p[-1];
7899
7900
    memmove (dot_p - 1, dot_p + 1, mnem_p - dot_p);
7901
    mnem_p[-2] = suffix;
7902
    dot_p = mnem_p - 1;
7903
  }
7904
      else
7905
#endif
7906
      /* Deprecated functionality (new code should use pseudo-prefixes instead):
7907
   Check if we should swap operand or force 32bit displacement in
7908
   encoding.  */
7909
0
      if (mnem_p - 2 == dot_p && dot_p[1] == 's')
7910
0
  {
7911
0
    if (pp.dir_encoding == dir_encoding_default)
7912
0
      pp.dir_encoding = dir_encoding_swap;
7913
0
    else
7914
0
      as_warn (_("ignoring `.s' suffix due to earlier `{%s}'"),
7915
0
         pp.dir_encoding == dir_encoding_load ? "load" : "store");
7916
0
  }
7917
0
      else if (mnem_p - 3 == dot_p
7918
0
         && dot_p[1] == 'd'
7919
0
         && dot_p[2] == '8')
7920
0
  {
7921
0
    if (pp.disp_encoding == disp_encoding_default)
7922
0
      pp.disp_encoding = disp_encoding_8bit;
7923
0
    else if (pp.disp_encoding != disp_encoding_8bit)
7924
0
      as_warn (_("ignoring `.d8' suffix due to earlier `{disp<N>}'"));
7925
0
  }
7926
0
      else if (mnem_p - 4 == dot_p
7927
0
         && dot_p[1] == 'd'
7928
0
         && dot_p[2] == '3'
7929
0
         && dot_p[3] == '2')
7930
0
  {
7931
0
    if (pp.disp_encoding == disp_encoding_default)
7932
0
      pp.disp_encoding = disp_encoding_32bit;
7933
0
    else if (pp.disp_encoding != disp_encoding_32bit)
7934
0
      as_warn (_("ignoring `.d32' suffix due to earlier `{disp<N>}'"));
7935
0
  }
7936
0
      else
7937
0
  goto check_suffix;
7938
0
      mnem_p = dot_p;
7939
0
      *dot_p = '\0';
7940
0
      op_lookup (mnemonic);
7941
0
    }
7942
7943
0
  if (!current_templates.start || !pass1)
7944
0
    {
7945
0
      current_templates.start = NULL;
7946
7947
0
    check_suffix:
7948
0
      if (mnem_p > mnemonic)
7949
0
  {
7950
    /* See if we can get a match by trimming off a suffix.  */
7951
0
    switch (mnem_p[-1])
7952
0
      {
7953
0
      case WORD_MNEM_SUFFIX:
7954
0
        if (intel_syntax && (intel_float_operand (mnemonic) & 2))
7955
0
    i.suffix = SHORT_MNEM_SUFFIX;
7956
0
        else
7957
    /* Fall through.  */
7958
0
        case BYTE_MNEM_SUFFIX:
7959
0
        case QWORD_MNEM_SUFFIX:
7960
0
    i.suffix = mnem_p[-1];
7961
0
        mnem_p[-1] = '\0';
7962
0
        op_lookup (mnemonic);
7963
0
        break;
7964
0
      case SHORT_MNEM_SUFFIX:
7965
0
      case LONG_MNEM_SUFFIX:
7966
0
        if (!intel_syntax)
7967
0
    {
7968
0
      i.suffix = mnem_p[-1];
7969
0
      mnem_p[-1] = '\0';
7970
0
      op_lookup (mnemonic);
7971
0
    }
7972
0
        break;
7973
7974
        /* Intel Syntax.  */
7975
0
      case 'd':
7976
0
        if (intel_syntax)
7977
0
    {
7978
0
      if (intel_float_operand (mnemonic) == 1)
7979
0
        i.suffix = SHORT_MNEM_SUFFIX;
7980
0
      else
7981
0
        i.suffix = LONG_MNEM_SUFFIX;
7982
0
      mnem_p[-1] = '\0';
7983
0
      op_lookup (mnemonic);
7984
0
    }
7985
        /* For compatibility reasons accept MOVSD and CMPSD without
7986
           operands even in AT&T mode.  */
7987
0
        else if (*l == END_OF_INSN)
7988
0
    {
7989
0
      mnem_p[-1] = '\0';
7990
0
      op_lookup (mnemonic);
7991
0
      if (current_templates.start != NULL
7992
          /* MOVS or CMPS */
7993
0
          && (current_templates.start->base_opcode | 2) == 0xa6
7994
0
          && current_templates.start->opcode_space
7995
0
       == SPACE_BASE
7996
0
          && mnem_p[-2] == 's')
7997
0
        {
7998
0
          as_warn (_("found `%sd'; assuming `%sl' was meant"),
7999
0
             mnemonic, mnemonic);
8000
0
          i.suffix = LONG_MNEM_SUFFIX;
8001
0
        }
8002
0
      else
8003
0
        {
8004
0
          current_templates.start = NULL;
8005
0
          mnem_p[-1] = 'd';
8006
0
        }
8007
0
    }
8008
0
        break;
8009
0
      }
8010
0
  }
8011
8012
0
      if (!current_templates.start)
8013
0
  {
8014
0
    if (pass1)
8015
0
      as_bad (_("no such instruction: `%s'"), token_start);
8016
0
    return NULL;
8017
0
  }
8018
0
    }
8019
8020
  /* Handle SCC OSZC flgs.  */
8021
0
  if (current_templates.start->opcode_modifier.operandconstraint == SCC)
8022
0
    {
8023
0
      int length = check_Scc_OszcOperations (l);
8024
0
      if (length < 0)
8025
0
  return NULL;
8026
0
      l += length;
8027
0
    }
8028
8029
0
  if ((current_templates.start->opcode_modifier.jump == JUMP
8030
0
       || current_templates.start->opcode_modifier.jump == JUMP_BYTE)
8031
0
      && *l == ',')
8032
0
    {
8033
      /* Check for a branch hint.  We allow ",pt" and ",pn" for
8034
   predict taken and predict not taken respectively.
8035
   I'm not sure that branch hints actually do anything on loop
8036
   and jcxz insns (JumpByte) for current Pentium4 chips.  They
8037
   may work in the future and it doesn't hurt to accept them
8038
   now.  */
8039
0
      token_start = l++;
8040
0
      if (is_whitespace (*l))
8041
0
  ++l;
8042
0
      if (TOLOWER (*l) == 'p' && ISALPHA (l[1])
8043
0
    && (l[2] == END_OF_INSN || is_whitespace (l[2])))
8044
0
  {
8045
0
    if (TOLOWER (l[1]) == 't')
8046
0
      {
8047
0
        if (!add_prefix (DS_PREFIX_OPCODE))
8048
0
    return NULL;
8049
0
        l += 2;
8050
0
      }
8051
0
    else if (TOLOWER (l[1]) == 'n')
8052
0
      {
8053
0
        if (!add_prefix (CS_PREFIX_OPCODE))
8054
0
    return NULL;
8055
0
        l += 2;
8056
0
      }
8057
0
    else
8058
0
      l = token_start;
8059
0
  }
8060
0
      else
8061
0
  l = token_start;
8062
0
    }
8063
  /* Any other comma loses.  */
8064
0
  if (*l == ',')
8065
0
    {
8066
0
      as_bad (_("invalid character %s in mnemonic"),
8067
0
        output_invalid (*l));
8068
0
      return NULL;
8069
0
    }
8070
8071
  /* Check if instruction is supported on specified architecture.  */
8072
0
  supported = 0;
8073
0
  for (t = current_templates.start; t < current_templates.end; ++t)
8074
0
    {
8075
0
      supported |= cpu_flags_match (t);
8076
8077
0
      if (i.suffix == QWORD_MNEM_SUFFIX && !q_suffix_allowed (t))
8078
0
  supported &= ~CPU_FLAGS_64BIT_MATCH;
8079
8080
0
      if (supported == CPU_FLAGS_PERFECT_MATCH)
8081
0
  return l;
8082
0
    }
8083
8084
0
  if (pass1)
8085
0
    {
8086
0
      if (supported & CPU_FLAGS_64BIT_MATCH)
8087
0
        i.error = unsupported_on_arch;
8088
0
      else
8089
0
        i.error = unsupported_64bit;
8090
0
    }
8091
8092
0
  return NULL;
8093
0
}
8094
8095
static char *
8096
parse_operands (char *l, const char *mnemonic)
8097
0
{
8098
0
  char *token_start;
8099
8100
  /* 1 if operand is pending after ','.  */
8101
0
  unsigned int expecting_operand = 0;
8102
8103
0
  while (*l != END_OF_INSN)
8104
0
    {
8105
      /* Non-zero if operand parens not balanced.  */
8106
0
      unsigned int paren_not_balanced = 0;
8107
      /* True if inside double quotes.  */
8108
0
      bool in_quotes = false;
8109
8110
      /* Skip optional white space before operand.  */
8111
0
      if (is_whitespace (*l))
8112
0
  ++l;
8113
0
      if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"')
8114
0
  {
8115
0
    as_bad (_("invalid character %s before operand %d"),
8116
0
      output_invalid (*l),
8117
0
      i.operands + 1);
8118
0
    return NULL;
8119
0
  }
8120
0
      token_start = l;  /* After white space.  */
8121
0
      while (in_quotes || paren_not_balanced || *l != ',')
8122
0
  {
8123
0
    if (*l == END_OF_INSN)
8124
0
      {
8125
0
        if (in_quotes)
8126
0
    {
8127
0
      as_bad (_("unbalanced double quotes in operand %d."),
8128
0
        i.operands + 1);
8129
0
      return NULL;
8130
0
    }
8131
0
        if (paren_not_balanced)
8132
0
    {
8133
0
      know (!intel_syntax);
8134
0
      as_bad (_("unbalanced parenthesis in operand %d."),
8135
0
        i.operands + 1);
8136
0
      return NULL;
8137
0
    }
8138
0
        else
8139
0
    break; /* we are done */
8140
0
      }
8141
0
    else if (*l == '\\' && l[1] == '"')
8142
0
      ++l;
8143
0
    else if (*l == '"')
8144
0
      in_quotes = !in_quotes;
8145
0
    else if (!in_quotes && !is_operand_char (*l) && !is_whitespace (*l))
8146
0
      {
8147
0
        as_bad (_("invalid character %s in operand %d"),
8148
0
          output_invalid (*l),
8149
0
          i.operands + 1);
8150
0
        return NULL;
8151
0
      }
8152
0
    if (!intel_syntax && !in_quotes)
8153
0
      {
8154
0
        if (*l == '(')
8155
0
    ++paren_not_balanced;
8156
0
        if (*l == ')')
8157
0
    --paren_not_balanced;
8158
0
      }
8159
0
    l++;
8160
0
  }
8161
0
      if (l != token_start)
8162
0
  {     /* Yes, we've read in another operand.  */
8163
0
    unsigned int operand_ok;
8164
0
    this_operand = i.operands++;
8165
0
    if (i.operands > MAX_OPERANDS)
8166
0
      {
8167
0
        as_bad (_("spurious operands; (%d operands/instruction max)"),
8168
0
          MAX_OPERANDS);
8169
0
        return NULL;
8170
0
      }
8171
0
    i.types[this_operand].bitfield.unspecified = 1;
8172
    /* Now parse operand adding info to 'i' as we go along.  */
8173
0
    END_STRING_AND_SAVE (l);
8174
8175
0
    if (i.mem_operands > 1)
8176
0
      {
8177
0
        as_bad (_("too many memory references for `%s'"),
8178
0
          mnemonic);
8179
0
        return 0;
8180
0
      }
8181
8182
0
    if (intel_syntax)
8183
0
      operand_ok =
8184
0
        i386_intel_operand (token_start,
8185
0
          intel_float_operand (mnemonic));
8186
0
    else
8187
0
      operand_ok = i386_att_operand (token_start);
8188
8189
0
    RESTORE_END_STRING (l);
8190
0
    if (!operand_ok)
8191
0
      return NULL;
8192
0
  }
8193
0
      else
8194
0
  {
8195
0
    if (expecting_operand)
8196
0
      {
8197
0
      expecting_operand_after_comma:
8198
0
        as_bad (_("expecting operand after ','; got nothing"));
8199
0
        return NULL;
8200
0
      }
8201
0
    if (*l == ',')
8202
0
      {
8203
0
        as_bad (_("expecting operand before ','; got nothing"));
8204
0
        return NULL;
8205
0
      }
8206
0
  }
8207
8208
      /* Now *l must be either ',' or END_OF_INSN.  */
8209
0
      if (*l == ',')
8210
0
  {
8211
0
    if (*++l == END_OF_INSN)
8212
0
      {
8213
        /* Just skip it, if it's \n complain.  */
8214
0
        goto expecting_operand_after_comma;
8215
0
      }
8216
0
    expecting_operand = 1;
8217
0
  }
8218
0
    }
8219
0
  return l;
8220
0
}
8221
8222
static void
8223
copy_operand (unsigned int to, unsigned int from)
8224
0
{
8225
0
  i.types[to] = i.types[from];
8226
0
  i.tm.operand_types[to] = i.tm.operand_types[from];
8227
0
  i.flags[to] = i.flags[from];
8228
0
  i.op[to] = i.op[from];
8229
0
  i.reloc[to] = i.reloc[from];
8230
0
  i.imm_bits[to] = i.imm_bits[from];
8231
  /* Note: i.mask and i.broadcast aren't handled here, as what (if
8232
     anything) to do there depends on context.  */
8233
0
}
8234
8235
static void
8236
swap_2_operands (unsigned int xchg1, unsigned int xchg2)
8237
0
{
8238
0
  union i386_op temp_op;
8239
0
  i386_operand_type temp_type;
8240
0
  unsigned int temp_flags;
8241
0
  enum bfd_reloc_code_real temp_reloc;
8242
8243
0
  temp_type = i.types[xchg2];
8244
0
  i.types[xchg2] = i.types[xchg1];
8245
0
  i.types[xchg1] = temp_type;
8246
8247
0
  temp_flags = i.flags[xchg2];
8248
0
  i.flags[xchg2] = i.flags[xchg1];
8249
0
  i.flags[xchg1] = temp_flags;
8250
8251
0
  temp_op = i.op[xchg2];
8252
0
  i.op[xchg2] = i.op[xchg1];
8253
0
  i.op[xchg1] = temp_op;
8254
8255
0
  temp_reloc = i.reloc[xchg2];
8256
0
  i.reloc[xchg2] = i.reloc[xchg1];
8257
0
  i.reloc[xchg1] = temp_reloc;
8258
8259
0
  temp_flags = i.imm_bits[xchg2];
8260
0
  i.imm_bits[xchg2] = i.imm_bits[xchg1];
8261
0
  i.imm_bits[xchg1] = temp_flags;
8262
8263
0
  if (i.mask.reg)
8264
0
    {
8265
0
      if (i.mask.operand == xchg1)
8266
0
  i.mask.operand = xchg2;
8267
0
      else if (i.mask.operand == xchg2)
8268
0
  i.mask.operand = xchg1;
8269
0
    }
8270
0
  if (i.broadcast.type || i.broadcast.bytes)
8271
0
    {
8272
0
      if (i.broadcast.operand == xchg1)
8273
0
  i.broadcast.operand = xchg2;
8274
0
      else if (i.broadcast.operand == xchg2)
8275
0
  i.broadcast.operand = xchg1;
8276
0
    }
8277
0
}
8278
8279
static void
8280
swap_operands (void)
8281
0
{
8282
0
  switch (i.operands)
8283
0
    {
8284
0
    case 5:
8285
0
    case 4:
8286
0
      swap_2_operands (1, i.operands - 2);
8287
      /* Fall through.  */
8288
0
    case 3:
8289
0
    case 2:
8290
0
      swap_2_operands (0, i.operands - 1);
8291
0
      break;
8292
0
    default:
8293
0
      abort ();
8294
0
    }
8295
8296
0
  if (i.mem_operands == 2)
8297
0
    {
8298
0
      const reg_entry *temp_seg;
8299
0
      temp_seg = i.seg[0];
8300
0
      i.seg[0] = i.seg[1];
8301
0
      i.seg[1] = temp_seg;
8302
0
    }
8303
0
}
8304
8305
/* Try to ensure constant immediates are represented in the smallest
8306
   opcode possible.  */
8307
static void
8308
optimize_imm (void)
8309
0
{
8310
0
  char guess_suffix = 0;
8311
0
  int op;
8312
8313
0
  if (i.suffix)
8314
0
    guess_suffix = i.suffix;
8315
0
  else if (i.reg_operands)
8316
0
    {
8317
      /* Figure out a suffix from the last register operand specified.
8318
   We can't do this properly yet, i.e. excluding special register
8319
   instances, but the following works for instructions with
8320
   immediates.  In any case, we can't set i.suffix yet.  */
8321
0
      for (op = i.operands; --op >= 0;)
8322
0
  if (i.types[op].bitfield.class != Reg)
8323
0
    continue;
8324
0
  else if (i.types[op].bitfield.byte)
8325
0
    {
8326
0
      guess_suffix = BYTE_MNEM_SUFFIX;
8327
0
      break;
8328
0
    }
8329
0
  else if (i.types[op].bitfield.word)
8330
0
    {
8331
0
      guess_suffix = WORD_MNEM_SUFFIX;
8332
0
      break;
8333
0
    }
8334
0
  else if (i.types[op].bitfield.dword)
8335
0
    {
8336
0
      guess_suffix = LONG_MNEM_SUFFIX;
8337
0
      break;
8338
0
    }
8339
0
  else if (i.types[op].bitfield.qword)
8340
0
    {
8341
0
      guess_suffix = QWORD_MNEM_SUFFIX;
8342
0
      break;
8343
0
    }
8344
0
    }
8345
0
  else if ((flag_code == CODE_16BIT)
8346
0
      ^ (i.prefix[DATA_PREFIX] != 0 && !(i.prefix[REX_PREFIX] & REX_W)))
8347
0
    guess_suffix = WORD_MNEM_SUFFIX;
8348
0
  else if (flag_code != CODE_64BIT
8349
0
     || (!(i.prefix[REX_PREFIX] & REX_W)
8350
         /* A more generic (but also more involved) way of dealing
8351
      with the special case(s) would be to go look for
8352
      DefaultSize attributes on any of the templates.  */
8353
0
         && current_templates.start->mnem_off != MN_push
8354
0
         && current_templates.start->mnem_off != MN_jmpabs))
8355
0
    guess_suffix = LONG_MNEM_SUFFIX;
8356
8357
0
  for (op = i.operands; --op >= 0;)
8358
0
    if (operand_type_check (i.types[op], imm))
8359
0
      {
8360
0
  switch (i.op[op].imms->X_op)
8361
0
    {
8362
0
    case O_constant:
8363
      /* If a suffix is given, this operand may be shortened.  */
8364
0
      switch (guess_suffix)
8365
0
        {
8366
0
        case LONG_MNEM_SUFFIX:
8367
0
    i.types[op].bitfield.imm32 = 1;
8368
0
    i.types[op].bitfield.imm64 = 1;
8369
0
    break;
8370
0
        case WORD_MNEM_SUFFIX:
8371
0
    i.types[op].bitfield.imm16 = 1;
8372
0
    i.types[op].bitfield.imm32 = 1;
8373
0
    i.types[op].bitfield.imm32s = 1;
8374
0
    i.types[op].bitfield.imm64 = 1;
8375
0
    break;
8376
0
        case BYTE_MNEM_SUFFIX:
8377
0
    i.types[op].bitfield.imm8 = 1;
8378
0
    i.types[op].bitfield.imm8s = 1;
8379
0
    i.types[op].bitfield.imm16 = 1;
8380
0
    i.types[op].bitfield.imm32 = 1;
8381
0
    i.types[op].bitfield.imm32s = 1;
8382
0
    i.types[op].bitfield.imm64 = 1;
8383
0
    break;
8384
0
        }
8385
8386
      /* If this operand is at most 16 bits, convert it
8387
         to a signed 16 bit number before trying to see
8388
         whether it will fit in an even smaller size.
8389
         This allows a 16-bit operand such as $0xffe0 to
8390
         be recognised as within Imm8S range.  */
8391
0
      if ((i.types[op].bitfield.imm16)
8392
0
    && fits_in_unsigned_word (i.op[op].imms->X_add_number))
8393
0
        {
8394
0
    i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
8395
0
            ^ 0x8000) - 0x8000);
8396
0
        }
8397
0
#ifdef BFD64
8398
      /* Store 32-bit immediate in 64-bit for 64-bit BFD.  */
8399
0
      if ((i.types[op].bitfield.imm32)
8400
0
    && fits_in_unsigned_long (i.op[op].imms->X_add_number))
8401
0
        {
8402
0
    i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
8403
0
            ^ ((offsetT) 1 << 31))
8404
0
                 - ((offsetT) 1 << 31));
8405
0
        }
8406
0
#endif
8407
0
      i.types[op]
8408
0
        = operand_type_or (i.types[op],
8409
0
         smallest_imm_type (i.op[op].imms->X_add_number));
8410
8411
      /* We must avoid matching of Imm32 templates when 64bit
8412
         only immediate is available.  */
8413
0
      if (guess_suffix == QWORD_MNEM_SUFFIX)
8414
0
        i.types[op].bitfield.imm32 = 0;
8415
0
      break;
8416
8417
0
    case O_absent:
8418
0
    case O_register:
8419
0
      abort ();
8420
8421
      /* Symbols and expressions.  */
8422
0
    default:
8423
      /* Convert symbolic operand to proper sizes for matching, but don't
8424
         prevent matching a set of insns that only supports sizes other
8425
         than those matching the insn suffix.  */
8426
0
      {
8427
0
        i386_operand_type mask, allowed;
8428
0
        const insn_template *t = current_templates.start;
8429
8430
0
        operand_type_set (&mask, 0);
8431
0
        switch (guess_suffix)
8432
0
    {
8433
0
    case QWORD_MNEM_SUFFIX:
8434
0
      mask.bitfield.imm64 = 1;
8435
0
      mask.bitfield.imm32s = 1;
8436
0
      break;
8437
0
    case LONG_MNEM_SUFFIX:
8438
0
      mask.bitfield.imm32 = 1;
8439
0
      break;
8440
0
    case WORD_MNEM_SUFFIX:
8441
0
      mask.bitfield.imm16 = 1;
8442
0
      break;
8443
0
    case BYTE_MNEM_SUFFIX:
8444
0
      mask.bitfield.imm8 = 1;
8445
0
      break;
8446
0
    default:
8447
0
      break;
8448
0
    }
8449
8450
0
        allowed = operand_type_and (t->operand_types[op], mask);
8451
0
        while (++t < current_templates.end)
8452
0
    {
8453
0
      allowed = operand_type_or (allowed, t->operand_types[op]);
8454
0
      allowed = operand_type_and (allowed, mask);
8455
0
    }
8456
8457
0
        if (!operand_type_all_zero (&allowed))
8458
0
    i.types[op] = operand_type_and (i.types[op], mask);
8459
0
      }
8460
0
      break;
8461
0
    }
8462
0
      }
8463
0
}
8464
8465
/* Try to use the smallest displacement type too.  */
8466
static bool
8467
optimize_disp (const insn_template *t)
8468
0
{
8469
0
  unsigned int op;
8470
8471
0
  if (!want_disp32 (t)
8472
0
      && (!t->opcode_modifier.jump
8473
0
    || i.jumpabsolute || i.types[0].bitfield.baseindex))
8474
0
    {
8475
0
      for (op = i.imm_operands; op < i.operands; ++op)
8476
0
  {
8477
0
    const expressionS *exp = i.op[op].disps;
8478
8479
0
    if (!operand_type_check (i.types[op], disp))
8480
0
      continue;
8481
8482
0
    if (exp->X_op != O_constant)
8483
0
      continue;
8484
8485
    /* Since displacement is signed extended to 64bit, don't allow
8486
       disp32 if it is out of range.  */
8487
0
    if (fits_in_signed_long (exp->X_add_number))
8488
0
      continue;
8489
8490
0
    i.types[op].bitfield.disp32 = 0;
8491
0
    if (i.types[op].bitfield.baseindex)
8492
0
      {
8493
0
        as_bad (_("0x%" PRIx64 " out of range of signed 32bit displacement"),
8494
0
          (uint64_t) exp->X_add_number);
8495
0
        return false;
8496
0
      }
8497
0
  }
8498
0
    }
8499
8500
  /* Don't optimize displacement for movabs / jmpabs since they only take
8501
     64-bit displacement.  */
8502
0
  if (pp.disp_encoding > disp_encoding_8bit
8503
0
      || t->mnem_off == MN_movabs || t->mnem_off == MN_jmpabs)
8504
0
    return true;
8505
8506
0
  for (op = i.operands; op-- > 0;)
8507
0
    if (operand_type_check (i.types[op], disp))
8508
0
      {
8509
0
  if (i.op[op].disps->X_op == O_constant)
8510
0
    {
8511
0
      offsetT op_disp = i.op[op].disps->X_add_number;
8512
8513
0
      if (!op_disp && i.types[op].bitfield.baseindex)
8514
0
        {
8515
0
    i.types[op] = operand_type_and_not (i.types[op], anydisp);
8516
0
    i.op[op].disps = NULL;
8517
0
    i.disp_operands--;
8518
0
    continue;
8519
0
        }
8520
8521
0
      if (i.types[op].bitfield.disp16
8522
0
    && fits_in_unsigned_word (op_disp))
8523
0
        {
8524
    /* If this operand is at most 16 bits, convert
8525
       to a signed 16 bit number and don't use 64bit
8526
       displacement.  */
8527
0
    op_disp = ((op_disp ^ 0x8000) - 0x8000);
8528
0
    i.types[op].bitfield.disp64 = 0;
8529
0
        }
8530
8531
0
#ifdef BFD64
8532
      /* Optimize 64-bit displacement to 32-bit for 64-bit BFD.  */
8533
0
      if ((flag_code != CODE_64BIT
8534
0
     ? i.types[op].bitfield.disp32
8535
0
     : want_disp32 (t)
8536
0
       && (!t->opcode_modifier.jump
8537
0
           || i.jumpabsolute || i.types[op].bitfield.baseindex))
8538
0
    && fits_in_unsigned_long (op_disp))
8539
0
        {
8540
    /* If this operand is at most 32 bits, convert
8541
       to a signed 32 bit number and don't use 64bit
8542
       displacement.  */
8543
0
    op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
8544
0
    i.types[op].bitfield.disp64 = 0;
8545
0
    i.types[op].bitfield.disp32 = 1;
8546
0
        }
8547
8548
0
      if (flag_code == CODE_64BIT && fits_in_signed_long (op_disp))
8549
0
        {
8550
0
    i.types[op].bitfield.disp64 = 0;
8551
0
    i.types[op].bitfield.disp32 = 1;
8552
0
        }
8553
0
#endif
8554
0
      if ((i.types[op].bitfield.disp32
8555
0
     || i.types[op].bitfield.disp16)
8556
0
    && fits_in_disp8 (op_disp))
8557
0
        i.types[op].bitfield.disp8 = 1;
8558
8559
0
      i.op[op].disps->X_add_number = op_disp;
8560
0
    }
8561
0
  else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
8562
0
     || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
8563
0
    {
8564
0
      fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
8565
0
       i.op[op].disps, 0, i.reloc[op]);
8566
0
      i.types[op] = operand_type_and_not (i.types[op], anydisp);
8567
0
    }
8568
0
  else
8569
    /* We only support 64bit displacement on constants.  */
8570
0
    i.types[op].bitfield.disp64 = 0;
8571
0
      }
8572
8573
0
  return true;
8574
0
}
8575
8576
/* Return 1 if there is a match in broadcast bytes between operand
8577
   GIVEN and instruction template T.   */
8578
8579
static INLINE int
8580
match_broadcast_size (const insn_template *t, unsigned int given)
8581
0
{
8582
0
  return ((t->opcode_modifier.broadcast == BYTE_BROADCAST
8583
0
     && i.types[given].bitfield.byte)
8584
0
    || (t->opcode_modifier.broadcast == WORD_BROADCAST
8585
0
        && i.types[given].bitfield.word)
8586
0
    || (t->opcode_modifier.broadcast == DWORD_BROADCAST
8587
0
        && i.types[given].bitfield.dword)
8588
0
    || (t->opcode_modifier.broadcast == QWORD_BROADCAST
8589
0
        && i.types[given].bitfield.qword));
8590
0
}
8591
8592
/* Check if operands are valid for the instruction.  */
8593
8594
static int
8595
check_VecOperands (const insn_template *t)
8596
0
{
8597
0
  unsigned int op;
8598
0
  i386_cpu_flags cpu;
8599
8600
  /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
8601
     any one operand are implicity requiring AVX512VL support if the actual
8602
     operand size is YMMword or XMMword.  Since this function runs after
8603
     template matching, there's no need to check for YMMword/XMMword in
8604
     the template.  */
8605
0
  cpu = cpu_flags_and (cpu_flags_from_attr (t->cpu), avx512);
8606
0
  if (!cpu_flags_all_zero (&cpu)
8607
0
      && !is_cpu (t, CpuAVX512VL)
8608
0
      && !cpu_arch_flags.bitfield.cpuavx512vl
8609
0
      && (!t->opcode_modifier.vex || need_evex_encoding (t)))
8610
0
    {
8611
0
      for (op = 0; op < t->operands; ++op)
8612
0
  {
8613
0
    if (t->operand_types[op].bitfield.zmmword
8614
0
        && (i.types[op].bitfield.ymmword
8615
0
      || i.types[op].bitfield.xmmword))
8616
0
      {
8617
0
        i.error = operand_size_mismatch;
8618
0
        return 1;
8619
0
      }
8620
0
  }
8621
0
    }
8622
8623
  /* Somewhat similarly, templates specifying both AVX and AVX2 are
8624
     requiring AVX2 support if the actual operand size is YMMword.  */
8625
0
  if (maybe_cpu (t, CpuAVX) && maybe_cpu (t, CpuAVX2)
8626
0
      && !cpu_arch_flags.bitfield.cpuavx2)
8627
0
    {
8628
0
      for (op = 0; op < t->operands; ++op)
8629
0
  {
8630
0
    if (t->operand_types[op].bitfield.xmmword
8631
0
        && i.types[op].bitfield.ymmword)
8632
0
      {
8633
0
        i.error = operand_size_mismatch;
8634
0
        return 1;
8635
0
      }
8636
0
  }
8637
0
    }
8638
8639
  /* Without VSIB byte, we can't have a vector register for index.  */
8640
0
  if (!t->opcode_modifier.sib
8641
0
      && i.index_reg
8642
0
      && (i.index_reg->reg_type.bitfield.xmmword
8643
0
    || i.index_reg->reg_type.bitfield.ymmword
8644
0
    || i.index_reg->reg_type.bitfield.zmmword))
8645
0
    {
8646
0
      i.error = unsupported_vector_index_register;
8647
0
      return 1;
8648
0
    }
8649
8650
  /* Check if default mask is allowed.  */
8651
0
  if (t->opcode_modifier.operandconstraint == NO_DEFAULT_MASK
8652
0
      && (!i.mask.reg || i.mask.reg->reg_num == 0))
8653
0
    {
8654
0
      i.error = no_default_mask;
8655
0
      return 1;
8656
0
    }
8657
8658
  /* For VSIB byte, we need a vector register for index, and all vector
8659
     registers must be distinct.  */
8660
0
  if (t->opcode_modifier.sib && t->opcode_modifier.sib != SIBMEM)
8661
0
    {
8662
0
      if (!i.index_reg
8663
0
    || !((t->opcode_modifier.sib == VECSIB128
8664
0
    && i.index_reg->reg_type.bitfield.xmmword)
8665
0
         || (t->opcode_modifier.sib == VECSIB256
8666
0
       && i.index_reg->reg_type.bitfield.ymmword)
8667
0
         || (t->opcode_modifier.sib == VECSIB512
8668
0
       && i.index_reg->reg_type.bitfield.zmmword)))
8669
0
      {
8670
0
  i.error = invalid_vsib_address;
8671
0
  return 1;
8672
0
      }
8673
8674
0
      gas_assert (i.reg_operands == 2 || i.mask.reg);
8675
0
      if (i.reg_operands == 2 && !i.mask.reg)
8676
0
  {
8677
0
    gas_assert (i.types[0].bitfield.class == RegSIMD);
8678
0
    gas_assert (i.types[0].bitfield.xmmword
8679
0
          || i.types[0].bitfield.ymmword);
8680
0
    gas_assert (i.types[2].bitfield.class == RegSIMD);
8681
0
    gas_assert (i.types[2].bitfield.xmmword
8682
0
          || i.types[2].bitfield.ymmword);
8683
0
    if (operand_check == check_none)
8684
0
      return 0;
8685
0
    if (register_number (i.op[0].regs)
8686
0
        != register_number (i.index_reg)
8687
0
        && register_number (i.op[2].regs)
8688
0
     != register_number (i.index_reg)
8689
0
        && register_number (i.op[0].regs)
8690
0
     != register_number (i.op[2].regs))
8691
0
      return 0;
8692
0
    if (operand_check == check_error)
8693
0
      {
8694
0
        i.error = invalid_vector_register_set;
8695
0
        return 1;
8696
0
      }
8697
0
    as_warn (_("mask, index, and destination registers should be distinct"));
8698
0
  }
8699
0
      else if (i.reg_operands == 1 && i.mask.reg)
8700
0
  {
8701
0
    if (i.types[1].bitfield.class == RegSIMD
8702
0
        && (i.types[1].bitfield.xmmword
8703
0
            || i.types[1].bitfield.ymmword
8704
0
            || i.types[1].bitfield.zmmword)
8705
0
        && (register_number (i.op[1].regs)
8706
0
      == register_number (i.index_reg)))
8707
0
      {
8708
0
        if (operand_check == check_error)
8709
0
    {
8710
0
      i.error = invalid_vector_register_set;
8711
0
      return 1;
8712
0
    }
8713
0
        if (operand_check != check_none)
8714
0
    as_warn (_("index and destination registers should be distinct"));
8715
0
      }
8716
0
  }
8717
0
    }
8718
8719
  /* For AMX instructions with 3 TMM register operands, all operands
8720
      must be distinct.  */
8721
0
  if (i.reg_operands == 3
8722
0
      && t->operand_types[0].bitfield.tmmword
8723
0
      && (i.op[0].regs == i.op[1].regs
8724
0
          || i.op[0].regs == i.op[2].regs
8725
0
          || i.op[1].regs == i.op[2].regs))
8726
0
    {
8727
0
      i.error = invalid_tmm_register_set;
8728
0
      return 1;
8729
0
    }
8730
8731
  /* For some special instructions require that destination must be distinct
8732
     from source registers.  */
8733
0
  if (t->opcode_modifier.operandconstraint == DISTINCT_DEST)
8734
0
    {
8735
0
      unsigned int dest_reg = i.operands - 1;
8736
8737
0
      know (i.operands >= 3);
8738
8739
      /* #UD if dest_reg == src1_reg or dest_reg == src2_reg.  */
8740
0
      if (i.op[dest_reg - 1].regs == i.op[dest_reg].regs
8741
0
    || (i.reg_operands > 2
8742
0
        && i.op[dest_reg - 2].regs == i.op[dest_reg].regs))
8743
0
  {
8744
0
    i.error = invalid_dest_and_src_register_set;
8745
0
    return 1;
8746
0
  }
8747
0
    }
8748
8749
  /* Check if broadcast is supported by the instruction and is applied
8750
     to the memory operand.  */
8751
0
  if (i.broadcast.type || i.broadcast.bytes)
8752
0
    {
8753
0
      i386_operand_type type, overlap;
8754
8755
      /* Check if specified broadcast is supported in this instruction,
8756
   and its broadcast bytes match the memory operand.  */
8757
0
      op = i.broadcast.operand;
8758
0
      if (!t->opcode_modifier.broadcast
8759
0
    || !(i.flags[op] & Operand_Mem)
8760
0
    || (!i.types[op].bitfield.unspecified
8761
0
        && !match_broadcast_size (t, op)))
8762
0
  {
8763
0
  bad_broadcast:
8764
0
    i.error = unsupported_broadcast;
8765
0
    return 1;
8766
0
  }
8767
8768
0
      operand_type_set (&type, 0);
8769
0
      switch (get_broadcast_bytes (t, false))
8770
0
  {
8771
0
  case 2:
8772
0
    type.bitfield.word = 1;
8773
0
    break;
8774
0
  case 4:
8775
0
    type.bitfield.dword = 1;
8776
0
    break;
8777
0
  case 8:
8778
0
    type.bitfield.qword = 1;
8779
0
    break;
8780
0
  case 16:
8781
0
    type.bitfield.xmmword = 1;
8782
0
    break;
8783
0
  case 32:
8784
0
    if (vector_size < VSZ256)
8785
0
      goto bad_broadcast;
8786
0
    type.bitfield.ymmword = 1;
8787
0
    break;
8788
0
  case 64:
8789
0
    if (vector_size < VSZ512)
8790
0
      goto bad_broadcast;
8791
0
    type.bitfield.zmmword = 1;
8792
0
    break;
8793
0
  default:
8794
0
    goto bad_broadcast;
8795
0
  }
8796
8797
0
      overlap = operand_type_and (type, t->operand_types[op]);
8798
0
      if (t->operand_types[op].bitfield.class == RegSIMD
8799
0
    && t->operand_types[op].bitfield.byte
8800
0
       + t->operand_types[op].bitfield.word
8801
0
       + t->operand_types[op].bitfield.dword
8802
0
       + t->operand_types[op].bitfield.qword > 1)
8803
0
  {
8804
0
    overlap.bitfield.xmmword = 0;
8805
0
    overlap.bitfield.ymmword = 0;
8806
0
    overlap.bitfield.zmmword = 0;
8807
0
  }
8808
0
      if (operand_type_all_zero (&overlap))
8809
0
    goto bad_broadcast;
8810
8811
0
      if (t->opcode_modifier.checkoperandsize)
8812
0
  {
8813
0
    unsigned int j;
8814
8815
0
    type.bitfield.baseindex = 1;
8816
0
    for (j = i.imm_operands; j < i.operands; ++j)
8817
0
      {
8818
0
        if (j != op
8819
0
      && !operand_type_register_match(i.types[j],
8820
0
              t->operand_types[j],
8821
0
              type,
8822
0
              t->operand_types[op]))
8823
0
    goto bad_broadcast;
8824
0
      }
8825
0
  }
8826
0
    }
8827
  /* If broadcast is supported in this instruction, we need to check if
8828
     operand of one-element size isn't specified without broadcast.  */
8829
0
  else if (t->opcode_modifier.broadcast && i.mem_operands)
8830
0
    {
8831
      /* Find memory operand.  */
8832
0
      for (op = i.imm_operands; op < i.operands; op++)
8833
0
  if (i.flags[op] & Operand_Mem)
8834
0
    break;
8835
0
      gas_assert (op < i.operands);
8836
      /* Check size of the memory operand.  */
8837
0
      if (match_broadcast_size (t, op))
8838
0
  {
8839
0
    i.error = broadcast_needed;
8840
0
    return 1;
8841
0
  }
8842
0
    }
8843
0
  else
8844
0
    op = MAX_OPERANDS - 1; /* Avoid uninitialized variable warning.  */
8845
8846
  /* Check if requested masking is supported.  */
8847
0
  if (i.mask.reg)
8848
0
    {
8849
0
      if (!t->opcode_modifier.masking)
8850
0
  {
8851
0
    i.error = unsupported_masking;
8852
0
    return 1;
8853
0
  }
8854
8855
      /* Common rules for masking:
8856
   - mask register destinations permit only zeroing-masking, without
8857
     that actually being expressed by a {z} operand suffix or EVEX.z,
8858
   - memory destinations allow only merging-masking,
8859
   - scatter/gather insns (i.e. ones using vSIB) only allow merging-
8860
     masking.  */
8861
0
      if (i.mask.zeroing
8862
0
    && (t->operand_types[t->operands - 1].bitfield.class == RegMask
8863
0
        || (i.flags[t->operands - 1] & Operand_Mem)
8864
0
        || t->opcode_modifier.sib))
8865
0
  {
8866
0
    i.error = unsupported_masking;
8867
0
    return 1;
8868
0
  }
8869
0
    }
8870
8871
  /* Check if masking is applied to dest operand.  */
8872
0
  if (i.mask.reg && (i.mask.operand != i.operands - 1))
8873
0
    {
8874
0
      i.error = mask_not_on_destination;
8875
0
      return 1;
8876
0
    }
8877
8878
  /* Check RC/SAE.  */
8879
0
  if (i.rounding.type != rc_none)
8880
0
    {
8881
0
      if (!t->opcode_modifier.sae
8882
0
    || ((i.rounding.type != saeonly) != t->opcode_modifier.staticrounding)
8883
0
    || i.mem_operands)
8884
0
  {
8885
0
    i.error = unsupported_rc_sae;
8886
0
    return 1;
8887
0
  }
8888
8889
      /* Non-EVEX.{LIG,512} forms need to have a ZMM or YMM register as at
8890
   least one operand.  There's no need to check all operands, though:
8891
   Either of the last two operands will be of the right size in all
8892
   relevant templates.  */
8893
0
      if (t->opcode_modifier.evex != EVEXLIG
8894
0
    && t->opcode_modifier.evex != EVEX512
8895
0
    && !i.types[t->operands - 1].bitfield.zmmword
8896
0
    && !i.types[t->operands - 2].bitfield.zmmword)
8897
0
  {
8898
0
    i.error = operand_size_mismatch;
8899
0
    return 1;
8900
0
  }
8901
0
    }
8902
8903
  /* Check the special Imm4 cases; must be the first operand.  */
8904
0
  if ((is_cpu (t, CpuXOP) && t->operands == 5)
8905
0
      || (t->opcode_space == SPACE_0F3A
8906
0
    && (t->base_opcode | 3) == 0x0b
8907
0
    && (is_cpu (t, CpuAPX_F)
8908
0
     || (t->opcode_modifier.sse2avx && t->opcode_modifier.evex
8909
0
         && (!t->opcode_modifier.vex
8910
0
       || (pp.encoding != encoding_default
8911
0
           && pp.encoding != encoding_vex
8912
0
           && pp.encoding != encoding_vex3))))))
8913
0
    {
8914
0
      if (i.op[0].imms->X_op != O_constant
8915
0
    || !fits_in_imm4 (i.op[0].imms->X_add_number))
8916
0
  {
8917
0
    i.error = bad_imm4;
8918
0
    return 1;
8919
0
  }
8920
8921
      /* Turn off Imm<N> so that update_imm won't complain.  */
8922
0
      if (t->operands == 5)
8923
0
  operand_type_set (&i.types[0], 0);
8924
0
    }
8925
8926
  /* Check vector Disp8 operand.  */
8927
0
  if (t->opcode_modifier.disp8memshift
8928
0
      && (!t->opcode_modifier.vex
8929
0
    || need_evex_encoding (t))
8930
0
      && pp.disp_encoding <= disp_encoding_8bit)
8931
0
    {
8932
0
      if (i.broadcast.type || i.broadcast.bytes)
8933
0
  i.memshift = t->opcode_modifier.broadcast - 1;
8934
0
      else if (t->opcode_modifier.disp8memshift != DISP8_SHIFT_VL)
8935
0
  i.memshift = t->opcode_modifier.disp8memshift;
8936
0
      else
8937
0
  {
8938
0
    const i386_operand_type *type = NULL, *fallback = NULL;
8939
8940
0
    i.memshift = 0;
8941
0
    for (op = i.imm_operands; op < i.operands; op++)
8942
0
      if (i.flags[op] & Operand_Mem)
8943
0
        {
8944
0
    if (t->opcode_modifier.evex == EVEXLIG)
8945
0
      i.memshift = 2 + (i.suffix == QWORD_MNEM_SUFFIX);
8946
0
    else if (t->operand_types[op].bitfield.xmmword
8947
0
       + t->operand_types[op].bitfield.ymmword
8948
0
       + t->operand_types[op].bitfield.zmmword <= 1)
8949
0
      type = &t->operand_types[op];
8950
0
    else if (!i.types[op].bitfield.unspecified)
8951
0
      type = &i.types[op];
8952
0
    else /* Ambiguities get resolved elsewhere.  */
8953
0
      fallback = &t->operand_types[op];
8954
0
        }
8955
0
      else if (i.types[op].bitfield.class == RegSIMD
8956
0
         && t->opcode_modifier.evex != EVEXLIG)
8957
0
        {
8958
0
    if (i.types[op].bitfield.zmmword)
8959
0
      i.memshift = 6;
8960
0
    else if (i.types[op].bitfield.ymmword && i.memshift < 5)
8961
0
      i.memshift = 5;
8962
0
    else if (i.types[op].bitfield.xmmword && i.memshift < 4)
8963
0
      i.memshift = 4;
8964
0
        }
8965
8966
0
    if (!type && !i.memshift)
8967
0
      type = fallback;
8968
0
    if (type)
8969
0
      {
8970
0
        if (type->bitfield.zmmword)
8971
0
    i.memshift = 6;
8972
0
        else if (type->bitfield.ymmword)
8973
0
    i.memshift = 5;
8974
0
        else if (type->bitfield.xmmword)
8975
0
    i.memshift = 4;
8976
0
      }
8977
8978
    /* For the check in fits_in_disp8().  */
8979
0
    if (i.memshift == 0)
8980
0
      i.memshift = -1;
8981
0
  }
8982
8983
0
      for (op = i.imm_operands; op < i.operands; op++)
8984
0
  if (operand_type_check (i.types[op], disp)
8985
0
      && i.op[op].disps->X_op == O_constant)
8986
0
    {
8987
      /* Make sure to leave i.types[op].bitfield.disp8 alone upon
8988
         secondary invocations of match_template().  */
8989
0
      if (fits_in_disp8 (i.op[op].disps->X_add_number))
8990
0
        {
8991
0
    if (!i.tm.mnem_off)
8992
0
      i.types[op].bitfield.disp8 = 1;
8993
0
    return 0;
8994
0
        }
8995
0
      if (!i.tm.mnem_off)
8996
0
        i.types[op].bitfield.disp8 = 0;
8997
0
    }
8998
0
    }
8999
9000
0
  i.memshift = 0;
9001
9002
0
  return 0;
9003
0
}
9004
9005
/* Check if encoding requirements are met by the instruction.  */
9006
9007
static int
9008
VEX_check_encoding (const insn_template *t)
9009
0
{
9010
0
  if (pp.encoding == encoding_error)
9011
0
    {
9012
0
      i.error = unsupported;
9013
0
      return 1;
9014
0
    }
9015
9016
  /* Vector size restrictions.  */
9017
0
  if ((vector_size < VSZ512
9018
0
       && t->opcode_modifier.evex == EVEX512)
9019
0
      || (vector_size < VSZ256
9020
0
    && (t->opcode_modifier.evex == EVEX256
9021
0
        || t->opcode_modifier.vex == VEX256)))
9022
0
    {
9023
0
      i.error = unsupported_vector_size;
9024
0
      return 1;
9025
0
    }
9026
9027
0
  switch (pp.encoding)
9028
0
    {
9029
0
    case encoding_vex:
9030
0
    case encoding_vex3:
9031
      /* This instruction must be encoded with VEX prefix.  */
9032
0
      if (!t->opcode_modifier.vex)
9033
0
  {
9034
0
    i.error = no_vex_encoding;
9035
0
    return 1;
9036
0
  }
9037
0
      break;
9038
9039
0
    case encoding_default:
9040
0
      if (!pp.has_nf)
9041
0
  break;
9042
      /* Fall through.  */
9043
0
    case encoding_evex:
9044
0
    case encoding_evex512:
9045
      /* This instruction must be encoded with EVEX prefix.  */
9046
0
      if (!t->opcode_modifier.evex)
9047
0
  {
9048
0
    i.error = no_evex_encoding;
9049
0
    return 1;
9050
0
  }
9051
0
      break;
9052
9053
0
    case encoding_egpr:
9054
      /* This instruction must be encoded with REX2 or EVEX prefix.  */
9055
0
      if (t->opcode_modifier.vex && !t->opcode_modifier.evex)
9056
0
  {
9057
0
    i.error = no_evex_encoding;
9058
0
    return 1;
9059
0
  }
9060
0
      break;
9061
9062
0
    default:
9063
0
      abort ();
9064
0
    }
9065
9066
0
  return 0;
9067
0
}
9068
9069
/* Check if Egprs operands are valid for the instruction.  */
9070
9071
static bool
9072
check_EgprOperands (const insn_template *t)
9073
0
{
9074
0
  if (!t->opcode_modifier.noegpr)
9075
0
    return false;
9076
9077
0
  for (unsigned int op = i.imm_operands; op < i.operands; op++)
9078
0
    {
9079
0
      if (i.types[op].bitfield.class != Reg)
9080
0
  continue;
9081
9082
0
      if (i.op[op].regs->reg_flags & RegRex2)
9083
0
  {
9084
0
    i.error = register_type_mismatch;
9085
0
    return true;
9086
0
  }
9087
0
    }
9088
9089
0
  if ((i.index_reg && (i.index_reg->reg_flags & RegRex2))
9090
0
      || (i.base_reg && (i.base_reg->reg_flags & RegRex2)))
9091
0
    {
9092
0
      i.error = unsupported_EGPR_for_addressing;
9093
0
      return true;
9094
0
    }
9095
9096
  /* Check if pseudo prefix {rex2} is valid.  */
9097
0
  if (pp.rex2_encoding && !t->opcode_modifier.sse2avx)
9098
0
    {
9099
0
      i.error = invalid_pseudo_prefix;
9100
0
      return true;
9101
0
    }
9102
9103
0
  return false;
9104
0
}
9105
9106
/* Check if APX operands are valid for the instruction.  */
9107
static bool
9108
check_APX_operands (const insn_template *t)
9109
0
{
9110
  /* Push2* and Pop2* cannot use RSP and Pop2* cannot pop two same registers.
9111
   */
9112
0
  switch (t->mnem_off)
9113
0
    {
9114
0
    case MN_pop2:
9115
0
    case MN_pop2p:
9116
0
      if (register_number (i.op[0].regs) == register_number (i.op[1].regs))
9117
0
  {
9118
0
    i.error = invalid_dest_register_set;
9119
0
    return 1;
9120
0
  }
9121
    /* fall through */
9122
0
    case MN_push2:
9123
0
    case MN_push2p:
9124
0
      if (register_number (i.op[0].regs) == 4
9125
0
    || register_number (i.op[1].regs) == 4)
9126
0
  {
9127
0
    i.error = unsupported_rsp_register;
9128
0
    return 1;
9129
0
  }
9130
0
      break;
9131
0
    }
9132
0
  return 0;
9133
0
}
9134
9135
/* Check if the instruction use the REX registers or REX prefix.  */
9136
static bool
9137
check_Rex_required (void)
9138
0
{
9139
0
  for (unsigned int op = i.imm_operands; op < i.operands; op++)
9140
0
    {
9141
0
      if (i.types[op].bitfield.class != Reg)
9142
0
  continue;
9143
9144
0
      if (i.op[op].regs->reg_flags & (RegRex | RegRex64))
9145
0
  return true;
9146
0
    }
9147
9148
0
  if ((i.index_reg && (i.index_reg->reg_flags & RegRex))
9149
0
      || (i.base_reg && (i.base_reg->reg_flags & RegRex)))
9150
0
    return true;
9151
9152
  /* Check pseudo prefix {rex} are valid.  */
9153
0
  return pp.rex_encoding;
9154
0
}
9155
9156
/* Optimize APX NDD insns to legacy insns.  */
9157
static unsigned int
9158
can_convert_NDD_to_legacy (const insn_template *t)
9159
0
{
9160
0
  unsigned int match_dest_op = ~0;
9161
9162
0
  if (!pp.has_nf && i.reg_operands >= 2)
9163
0
    {
9164
0
      unsigned int dest = i.operands - 1;
9165
0
      unsigned int src1 = i.operands - 2;
9166
0
      unsigned int src2 = (i.operands > 3) ? i.operands - 3 : 0;
9167
9168
0
      if (i.types[src1].bitfield.class == Reg
9169
0
    && i.op[src1].regs == i.op[dest].regs)
9170
0
  match_dest_op = src1;
9171
      /* If the first operand is the same as the third operand,
9172
   these instructions need to support the ability to commutative
9173
   the first two operands and still not change the semantics in order
9174
   to be optimized.  */
9175
0
      else if (optimize > 1
9176
0
         && t->opcode_modifier.commutative
9177
0
         && i.types[src2].bitfield.class == Reg
9178
0
         && i.op[src2].regs == i.op[dest].regs)
9179
0
  match_dest_op = src2;
9180
0
    }
9181
0
  return match_dest_op;
9182
0
}
9183
9184
/* Helper function for the progress() macro in match_template().  */
9185
static INLINE enum i386_error progress (enum i386_error new,
9186
          enum i386_error last,
9187
          unsigned int line, unsigned int *line_p)
9188
0
{
9189
0
  if (line <= *line_p)
9190
0
    return last;
9191
0
  *line_p = line;
9192
0
  return new;
9193
0
}
9194
9195
static const insn_template *
9196
match_template (char mnem_suffix)
9197
0
{
9198
  /* Points to template once we've found it.  */
9199
0
  const insn_template *t;
9200
0
  i386_operand_type overlap0, overlap1, overlap2, overlap3;
9201
0
  i386_operand_type overlap4;
9202
0
  unsigned int found_reverse_match;
9203
0
  i386_operand_type operand_types [MAX_OPERANDS];
9204
0
  int addr_prefix_disp;
9205
0
  unsigned int j, size_match, check_register, errline = __LINE__;
9206
0
  enum i386_error specific_error = number_of_operands_mismatch;
9207
0
#define progress(err) progress (err, specific_error, __LINE__, &errline)
9208
9209
#if MAX_OPERANDS != 5
9210
# error "MAX_OPERANDS must be 5."
9211
#endif
9212
9213
0
  found_reverse_match = 0;
9214
0
  addr_prefix_disp = -1;
9215
9216
0
  for (t = current_templates.start; t < current_templates.end; t++)
9217
0
    {
9218
0
      addr_prefix_disp = -1;
9219
0
      found_reverse_match = 0;
9220
9221
      /* Must have right number of operands.  */
9222
0
      if (i.operands != t->operands)
9223
0
  continue;
9224
9225
      /* Skip SSE2AVX templates when inapplicable.  */
9226
0
      if (t->opcode_modifier.sse2avx
9227
0
    && (!sse2avx || i.prefix[DATA_PREFIX]))
9228
0
  {
9229
    /* Another non-SSE2AVX template has to follow.  */
9230
0
    gas_assert (t + 1 < current_templates.end);
9231
0
    continue;
9232
0
  }
9233
9234
      /* Check processor support.  */
9235
0
      specific_error = progress (unsupported);
9236
0
      if (cpu_flags_match (t) != CPU_FLAGS_PERFECT_MATCH)
9237
0
  continue;
9238
9239
      /* Check AT&T mnemonic.   */
9240
0
      specific_error = progress (unsupported_with_intel_mnemonic);
9241
0
      if (!intel_syntax && intel_mnemonic
9242
0
    && t->opcode_modifier.dialect == ATT_MNEMONIC)
9243
0
  continue;
9244
9245
      /* Check AT&T/Intel syntax.  */
9246
0
      specific_error = progress (unsupported_syntax);
9247
0
      if (intel_syntax
9248
0
     ? t->opcode_modifier.dialect >= ATT_SYNTAX
9249
0
     : t->opcode_modifier.dialect == INTEL_SYNTAX)
9250
0
  continue;
9251
9252
      /* Check NF support.  */
9253
0
      specific_error = progress (unsupported_nf);
9254
0
      if (pp.has_nf && !t->opcode_modifier.nf)
9255
0
  continue;
9256
9257
      /* Check Intel64/AMD64 ISA.   */
9258
0
      switch (isa64)
9259
0
  {
9260
0
  default:
9261
    /* Default: Don't accept Intel64.  */
9262
0
    if (t->opcode_modifier.isa64 == INTEL64)
9263
0
      continue;
9264
0
    break;
9265
0
  case amd64:
9266
    /* -mamd64: Don't accept Intel64 and Intel64 only.  */
9267
0
    if (t->opcode_modifier.isa64 >= INTEL64)
9268
0
      continue;
9269
0
    break;
9270
0
  case intel64:
9271
    /* -mintel64: Don't accept AMD64.  */
9272
0
    if (t->opcode_modifier.isa64 == AMD64 && flag_code == CODE_64BIT)
9273
0
      continue;
9274
0
    break;
9275
0
  }
9276
9277
      /* Check the suffix.  */
9278
0
      specific_error = progress (invalid_instruction_suffix);
9279
0
      if ((t->opcode_modifier.no_bsuf && mnem_suffix == BYTE_MNEM_SUFFIX)
9280
0
    || (t->opcode_modifier.no_wsuf && mnem_suffix == WORD_MNEM_SUFFIX)
9281
0
    || (t->opcode_modifier.no_lsuf && mnem_suffix == LONG_MNEM_SUFFIX)
9282
0
    || (t->opcode_modifier.no_ssuf && mnem_suffix == SHORT_MNEM_SUFFIX)
9283
0
    || (t->opcode_modifier.no_qsuf && mnem_suffix == QWORD_MNEM_SUFFIX))
9284
0
  continue;
9285
9286
0
      specific_error = progress (operand_size_mismatch);
9287
0
      size_match = operand_size_match (t);
9288
0
      if (!size_match)
9289
0
  continue;
9290
9291
      /* This is intentionally not
9292
9293
   if (i.jumpabsolute != (t->opcode_modifier.jump == JUMP_ABSOLUTE))
9294
9295
   as the case of a missing * on the operand is accepted (perhaps with
9296
   a warning, issued further down).  */
9297
0
      specific_error = progress (operand_type_mismatch);
9298
0
      if (i.jumpabsolute && t->opcode_modifier.jump != JUMP_ABSOLUTE)
9299
0
  continue;
9300
9301
      /* In Intel syntax, normally we can check for memory operand size when
9302
   there is no mnemonic suffix.  But jmp and call have 2 different
9303
   encodings with Dword memory operand size.  Skip the "near" one
9304
   (permitting a register operand) when "far" was requested.  */
9305
0
      if (i.far_branch
9306
0
    && t->opcode_modifier.jump == JUMP_ABSOLUTE
9307
0
    && t->operand_types[0].bitfield.class == Reg)
9308
0
  continue;
9309
9310
0
      for (j = 0; j < MAX_OPERANDS; j++)
9311
0
  operand_types[j] = t->operand_types[j];
9312
9313
      /* In general, don't allow 32-bit operands on pre-386.  */
9314
0
      specific_error = progress (mnem_suffix ? invalid_instruction_suffix
9315
0
               : operand_size_mismatch);
9316
0
      j = i.imm_operands + (t->operands > i.imm_operands + 1);
9317
0
      if (i.suffix == LONG_MNEM_SUFFIX
9318
0
    && !cpu_arch_flags.bitfield.cpui386
9319
0
    && (intel_syntax
9320
0
        ? (t->opcode_modifier.mnemonicsize != IGNORESIZE
9321
0
     && !intel_float_operand (insn_name (t)))
9322
0
        : intel_float_operand (insn_name (t)) != 2)
9323
0
    && (t->operands == i.imm_operands
9324
0
        || (operand_types[i.imm_operands].bitfield.class != RegMMX
9325
0
         && operand_types[i.imm_operands].bitfield.class != RegSIMD
9326
0
         && operand_types[i.imm_operands].bitfield.class != RegMask)
9327
0
        || (operand_types[j].bitfield.class != RegMMX
9328
0
      && operand_types[j].bitfield.class != RegSIMD
9329
0
      && operand_types[j].bitfield.class != RegMask))
9330
0
    && !t->opcode_modifier.sib)
9331
0
  continue;
9332
9333
      /* Do not verify operands when there are none.  */
9334
0
      if (!t->operands)
9335
0
  {
9336
0
    if (VEX_check_encoding (t))
9337
0
      {
9338
0
        specific_error = progress (i.error);
9339
0
        continue;
9340
0
      }
9341
9342
    /* Check if pseudo prefix {rex2} is valid.  */
9343
0
    if (t->opcode_modifier.noegpr && pp.rex2_encoding)
9344
0
      {
9345
0
        specific_error = progress (invalid_pseudo_prefix);
9346
0
        continue;
9347
0
      }
9348
9349
    /* We've found a match; break out of loop.  */
9350
0
    break;
9351
0
  }
9352
9353
0
      if (!t->opcode_modifier.jump
9354
0
    || t->opcode_modifier.jump == JUMP_ABSOLUTE)
9355
0
  {
9356
    /* There should be only one Disp operand.  */
9357
0
    for (j = 0; j < MAX_OPERANDS; j++)
9358
0
      if (operand_type_check (operand_types[j], disp))
9359
0
        break;
9360
0
    if (j < MAX_OPERANDS)
9361
0
      {
9362
0
        bool override = (i.prefix[ADDR_PREFIX] != 0);
9363
9364
0
        addr_prefix_disp = j;
9365
9366
        /* Address size prefix will turn Disp64 operand into Disp32 and
9367
     Disp32/Disp16 one into Disp16/Disp32 respectively.  */
9368
0
        switch (flag_code)
9369
0
    {
9370
0
    case CODE_16BIT:
9371
0
      override = !override;
9372
      /* Fall through.  */
9373
0
    case CODE_32BIT:
9374
0
      if (operand_types[j].bitfield.disp32
9375
0
          && operand_types[j].bitfield.disp16)
9376
0
        {
9377
0
          operand_types[j].bitfield.disp16 = override;
9378
0
          operand_types[j].bitfield.disp32 = !override;
9379
0
        }
9380
0
      gas_assert (!operand_types[j].bitfield.disp64);
9381
0
      break;
9382
9383
0
    case CODE_64BIT:
9384
0
      if (operand_types[j].bitfield.disp64)
9385
0
        {
9386
0
          gas_assert (!operand_types[j].bitfield.disp32);
9387
0
          operand_types[j].bitfield.disp32 = override;
9388
0
          operand_types[j].bitfield.disp64 = !override;
9389
0
        }
9390
0
      operand_types[j].bitfield.disp16 = 0;
9391
0
      break;
9392
0
    }
9393
0
      }
9394
0
  }
9395
9396
      /* We check register size if needed.  */
9397
0
      if (t->opcode_modifier.checkoperandsize)
9398
0
  {
9399
0
    check_register = (1 << t->operands) - 1;
9400
0
    if (i.broadcast.type || i.broadcast.bytes)
9401
0
      check_register &= ~(1 << i.broadcast.operand);
9402
0
  }
9403
0
      else
9404
0
  check_register = 0;
9405
9406
0
      overlap0 = operand_type_and (i.types[0], operand_types[0]);
9407
0
      switch (t->operands)
9408
0
  {
9409
0
  case 1:
9410
0
    if (!operand_type_match (overlap0, i.types[0]))
9411
0
      {
9412
0
        specific_error = progress (i.error);
9413
0
        continue;
9414
0
      }
9415
9416
    /* Allow the ModR/M encoding to be requested by using the {load} or
9417
       {store} pseudo prefix on an applicable insn.  */
9418
0
    if (!t->opcode_modifier.modrm
9419
0
        && i.reg_operands == 1
9420
0
        && ((pp.dir_encoding == dir_encoding_load
9421
0
       && t->mnem_off != MN_pop)
9422
0
      || (pp.dir_encoding == dir_encoding_store
9423
0
          && t->mnem_off != MN_push))
9424
        /* Avoid BSWAP.  */
9425
0
        && t->mnem_off != MN_bswap)
9426
0
      continue;
9427
0
    break;
9428
9429
0
  case 2:
9430
    /* xchg %eax, %eax is a special case. It is an alias for nop
9431
       only in 32bit mode and we can use opcode 0x90.  In 64bit
9432
       mode, we can't use 0x90 for xchg %eax, %eax since it should
9433
       zero-extend %eax to %rax.  */
9434
0
    if (t->base_opcode == 0x90
9435
0
        && t->opcode_space == SPACE_BASE)
9436
0
      {
9437
0
        if (flag_code == CODE_64BIT
9438
0
      && i.types[0].bitfield.instance == Accum
9439
0
      && i.types[0].bitfield.dword
9440
0
      && i.types[1].bitfield.instance == Accum)
9441
0
    continue;
9442
9443
        /* Allow the ModR/M encoding to be requested by using the
9444
     {load} or {store} pseudo prefix.  */
9445
0
        if (pp.dir_encoding == dir_encoding_load
9446
0
      || pp.dir_encoding == dir_encoding_store)
9447
0
    continue;
9448
0
      }
9449
9450
0
    if (t->base_opcode == MOV_AX_DISP32
9451
0
        && t->opcode_space == SPACE_BASE
9452
0
        && t->mnem_off != MN_movabs)
9453
0
      {
9454
        /* Force 0x8b encoding for "mov foo@GOT, %eax".  */
9455
0
        if (i.reloc[0] == BFD_RELOC_386_GOT32)
9456
0
    continue;
9457
9458
        /* xrelease mov %eax, <disp> is another special case. It must not
9459
     match the accumulator-only encoding of mov.  */
9460
0
        if (i.hle_prefix)
9461
0
    continue;
9462
9463
        /* Allow the ModR/M encoding to be requested by using a suitable
9464
     {load} or {store} pseudo prefix.  */
9465
0
        if (pp.dir_encoding == (i.types[0].bitfield.instance == Accum
9466
0
             ? dir_encoding_store
9467
0
             : dir_encoding_load)
9468
0
      && !i.types[0].bitfield.disp64
9469
0
      && !i.types[1].bitfield.disp64)
9470
0
    continue;
9471
0
      }
9472
9473
    /* Allow the ModR/M encoding to be requested by using the {load} or
9474
       {store} pseudo prefix on an applicable insn.  */
9475
0
    if (!t->opcode_modifier.modrm
9476
0
        && i.reg_operands == 1
9477
0
        && i.imm_operands == 1
9478
0
        && (pp.dir_encoding == dir_encoding_load
9479
0
      || pp.dir_encoding == dir_encoding_store)
9480
0
        && t->opcode_space == SPACE_BASE)
9481
0
      {
9482
0
        if (t->base_opcode == 0xb0 /* mov $imm, %reg */
9483
0
      && pp.dir_encoding == dir_encoding_store)
9484
0
    continue;
9485
9486
0
        if ((t->base_opcode | 0x38) == 0x3c /* <alu> $imm, %acc */
9487
0
      && (t->base_opcode != 0x3c /* cmp $imm, %acc */
9488
0
          || pp.dir_encoding == dir_encoding_load))
9489
0
    continue;
9490
9491
0
        if (t->base_opcode == 0xa8 /* test $imm, %acc */
9492
0
      && pp.dir_encoding == dir_encoding_load)
9493
0
    continue;
9494
0
      }
9495
    /* Fall through.  */
9496
9497
0
  case 3:
9498
0
    if (!(size_match & MATCH_STRAIGHT))
9499
0
      goto check_reverse;
9500
    /* Reverse direction of operands if swapping is possible in the first
9501
       place (operands need to be symmetric) and
9502
       - the load form is requested, and the template is a store form,
9503
       - the store form is requested, and the template is a load form,
9504
       - the non-default (swapped) form is requested.  */
9505
0
    overlap1 = operand_type_and (operand_types[0], operand_types[1]);
9506
9507
0
    j = i.operands - 1 - (t->opcode_space == SPACE_MAP4
9508
0
        && t->opcode_modifier.vexvvvv);
9509
9510
0
    if (t->opcode_modifier.d && i.reg_operands == i.operands
9511
0
        && !operand_type_all_zero (&overlap1))
9512
0
      switch (pp.dir_encoding)
9513
0
        {
9514
0
        case dir_encoding_load:
9515
0
    if (operand_type_check (operand_types[j], anymem)
9516
0
        || t->opcode_modifier.regmem)
9517
0
      goto check_reverse;
9518
0
    break;
9519
9520
0
        case dir_encoding_store:
9521
0
    if (!operand_type_check (operand_types[j], anymem)
9522
0
        && !t->opcode_modifier.regmem)
9523
0
      goto check_reverse;
9524
0
    break;
9525
9526
0
        case dir_encoding_swap:
9527
0
    goto check_reverse;
9528
9529
0
        case dir_encoding_default:
9530
0
    break;
9531
0
        }
9532
9533
    /* If we want store form, we skip the current load.  */
9534
0
    if ((pp.dir_encoding == dir_encoding_store
9535
0
         || pp.dir_encoding == dir_encoding_swap)
9536
0
        && i.mem_operands == 0
9537
0
        && t->opcode_modifier.load)
9538
0
      continue;
9539
    /* Fall through.  */
9540
0
  case 4:
9541
0
  case 5:
9542
0
    overlap1 = operand_type_and (i.types[1], operand_types[1]);
9543
0
    if (!operand_type_match (overlap0, i.types[0])
9544
0
        || !operand_type_match (overlap1, i.types[1])
9545
0
        || ((check_register & 3) == 3
9546
0
      && !operand_type_register_match (i.types[0],
9547
0
               operand_types[0],
9548
0
               i.types[1],
9549
0
               operand_types[1])))
9550
0
      {
9551
0
        specific_error = progress (i.error);
9552
9553
        /* Check if other direction is valid ...  */
9554
0
        if (!t->opcode_modifier.d)
9555
0
    continue;
9556
9557
0
      check_reverse:
9558
0
        if (!(size_match & MATCH_REVERSE))
9559
0
    continue;
9560
        /* Try reversing direction of operands.  */
9561
0
        j = is_cpu (t, CpuFMA4)
9562
0
      || is_cpu (t, CpuXOP)
9563
0
      || is_cpu (t, CpuAPX_F) ? 1 : i.operands - 1;
9564
0
        overlap0 = operand_type_and (i.types[0], operand_types[j]);
9565
0
        overlap1 = operand_type_and (i.types[j], operand_types[0]);
9566
0
        overlap2 = operand_type_and (i.types[1], operand_types[1]);
9567
0
        gas_assert (t->operands != 3 || !check_register
9568
0
        || is_cpu (t, CpuAPX_F));
9569
0
        if (!operand_type_match (overlap0, i.types[0])
9570
0
      || !operand_type_match (overlap1, i.types[j])
9571
0
      || (t->operands == 3
9572
0
          && !operand_type_match (overlap2, i.types[1]))
9573
0
      || (check_register
9574
0
          && !operand_type_register_match (i.types[0],
9575
0
                   operand_types[j],
9576
0
                   i.types[j],
9577
0
                   operand_types[0])))
9578
0
    {
9579
      /* Does not match either direction.  */
9580
0
      specific_error = progress (i.error);
9581
0
      continue;
9582
0
    }
9583
        /* found_reverse_match holds which variant of D
9584
     we've found.  */
9585
0
        if (!t->opcode_modifier.d)
9586
0
    found_reverse_match = 0;
9587
0
        else if (operand_types[0].bitfield.tbyte)
9588
0
    {
9589
0
      if (t->opcode_modifier.operandconstraint != UGH)
9590
0
        found_reverse_match = Opcode_FloatD;
9591
0
      else
9592
0
        found_reverse_match = ~0;
9593
      /* FSUB{,R} and FDIV{,R} may need a 2nd bit flipped.  */
9594
0
      if ((t->extension_opcode & 4)
9595
0
          && (intel_syntax || intel_mnemonic))
9596
0
        found_reverse_match |= Opcode_FloatR;
9597
0
    }
9598
0
        else if (is_cpu (t, CpuFMA4) || is_cpu (t, CpuXOP))
9599
0
    {
9600
0
      found_reverse_match = Opcode_VexW;
9601
0
      goto check_operands_345;
9602
0
    }
9603
0
        else if (t->opcode_space == SPACE_MAP4
9604
0
           && t->operands >= 3)
9605
0
    {
9606
0
      found_reverse_match = Opcode_D;
9607
0
      goto check_operands_345;
9608
0
    }
9609
0
        else if (t->opcode_modifier.commutative
9610
           /* CFCMOVcc also wants its major opcode unaltered.  */
9611
0
           || (t->opcode_space == SPACE_MAP4
9612
0
         && (t->base_opcode | 0xf) == 0x4f))
9613
0
    found_reverse_match = ~0;
9614
0
        else if (t->opcode_space != SPACE_BASE
9615
0
           && (t->opcode_space != SPACE_MAP4
9616
         /* MOVBE, originating from SPACE_0F38, also
9617
            belongs here.  */
9618
0
         || t->mnem_off == MN_movbe)
9619
0
           && (t->opcode_space != SPACE_0F
9620
         /* MOV to/from CR/DR/TR, as an exception, follow
9621
            the base opcode space encoding model.  */
9622
0
         || (t->base_opcode | 7) != 0x27))
9623
0
    found_reverse_match = (t->base_opcode & 0xee) != 0x6e
9624
0
              ? Opcode_ExtD : Opcode_SIMD_IntD;
9625
0
        else
9626
0
    found_reverse_match = Opcode_D;
9627
0
      }
9628
0
    else
9629
0
      {
9630
        /* Found a forward 2 operand match here.  */
9631
0
      check_operands_345:
9632
0
        switch (t->operands)
9633
0
    {
9634
0
    case 5:
9635
0
      overlap4 = operand_type_and (i.types[4], operand_types[4]);
9636
0
      if (!operand_type_match (overlap4, i.types[4])
9637
0
          || !operand_type_register_match (i.types[3],
9638
0
                   operand_types[3],
9639
0
                   i.types[4],
9640
0
                   operand_types[4]))
9641
0
        {
9642
0
          specific_error = progress (i.error);
9643
0
          continue;
9644
0
        }
9645
      /* Fall through.  */
9646
0
    case 4:
9647
0
      overlap3 = operand_type_and (i.types[3], operand_types[3]);
9648
0
      if (!operand_type_match (overlap3, i.types[3])
9649
0
          || ((check_register & 0xa) == 0xa
9650
0
        && !operand_type_register_match (i.types[1],
9651
0
                  operand_types[1],
9652
0
                  i.types[3],
9653
0
                  operand_types[3]))
9654
0
          || ((check_register & 0xc) == 0xc
9655
0
        && !operand_type_register_match (i.types[2],
9656
0
                  operand_types[2],
9657
0
                  i.types[3],
9658
0
                  operand_types[3])))
9659
0
        {
9660
0
          specific_error = progress (i.error);
9661
0
          continue;
9662
0
        }
9663
      /* Fall through.  */
9664
0
    case 3:
9665
0
      overlap2 = operand_type_and (i.types[2], operand_types[2]);
9666
0
      if (!operand_type_match (overlap2, i.types[2])
9667
0
          || ((check_register & 5) == 5
9668
0
        && !operand_type_register_match (i.types[0],
9669
0
                  operand_types[0],
9670
0
                  i.types[2],
9671
0
                  operand_types[2]))
9672
0
          || ((check_register & 6) == 6
9673
0
        && !operand_type_register_match (i.types[1],
9674
0
                  operand_types[1],
9675
0
                  i.types[2],
9676
0
                  operand_types[2])))
9677
0
        {
9678
0
          specific_error = progress (i.error);
9679
0
          continue;
9680
0
        }
9681
0
      break;
9682
0
    }
9683
0
      }
9684
    /* Found either forward/reverse 2, 3 or 4 operand match here:
9685
       slip through to break.  */
9686
0
  }
9687
9688
      /* Check if VEX/EVEX encoding requirements can be satisfied.  */
9689
0
      if (VEX_check_encoding (t))
9690
0
  {
9691
0
    specific_error = progress (i.error);
9692
0
    continue;
9693
0
  }
9694
9695
      /* Check if EGPR operands(r16-r31) are valid.  */
9696
0
      if (check_EgprOperands (t))
9697
0
  {
9698
0
    specific_error = progress (i.error);
9699
0
    continue;
9700
0
  }
9701
9702
      /* Check if vector operands are valid.  */
9703
0
      if (check_VecOperands (t))
9704
0
  {
9705
0
    specific_error = progress (i.error);
9706
0
    continue;
9707
0
  }
9708
9709
      /* Check if APX operands are valid.  */
9710
0
      if (check_APX_operands (t))
9711
0
  {
9712
0
    specific_error = progress (i.error);
9713
0
    continue;
9714
0
  }
9715
9716
      /* Check whether to use the shorter VEX encoding for certain insns where
9717
   the EVEX encoding comes first in the table.  This requires the respective
9718
   AVX-* feature to be explicitly enabled.
9719
9720
   Most of the respective insns have just a single EVEX and a single VEX
9721
   template.  The one that's presently different is generated using the
9722
   Vxy / Exy constructs: There are 3 suffix-less EVEX forms, the latter
9723
   two of which may fall back to their two corresponding VEX forms.  */
9724
0
      j = t->mnem_off != MN_vcvtneps2bf16 ? 1 : 2;
9725
0
      if ((t == current_templates.start || j > 1)
9726
0
    && t->opcode_modifier.disp8memshift
9727
0
    && !t->opcode_modifier.vex
9728
0
    && !need_evex_encoding (t)
9729
0
    && t + j < current_templates.end
9730
0
    && t[j].opcode_modifier.vex)
9731
0
  {
9732
0
    i386_cpu_flags cpu;
9733
0
    unsigned int memshift = i.memshift;
9734
9735
0
    i.memshift = 0;
9736
0
    cpu = cpu_flags_and (cpu_flags_from_attr (t[j].cpu),
9737
0
             cpu_arch_isa_flags);
9738
0
    if (!cpu_flags_all_zero (&cpu)
9739
0
        && (!i.types[0].bitfield.disp8
9740
0
      || !operand_type_check (i.types[0], disp)
9741
0
      || i.op[0].disps->X_op != O_constant
9742
0
      || fits_in_disp8 (i.op[0].disps->X_add_number)))
9743
0
      {
9744
0
        specific_error = progress (internal_error);
9745
0
        t += j - 1;
9746
0
        continue;
9747
0
      }
9748
0
    i.memshift = memshift;
9749
0
  }
9750
9751
      /* If we can optimize a NDD insn to legacy insn, like
9752
   add %r16, %r8, %r8 -> add %r16, %r8,
9753
   add  %r8, %r16, %r8 -> add %r16, %r8, then rematch template.
9754
   Note that the semantics have not been changed.  */
9755
0
      if (optimize
9756
0
    && !pp.no_optimize
9757
0
    && pp.encoding != encoding_evex
9758
0
    && ((t + 1 < current_templates.end
9759
0
         && !t[1].opcode_modifier.evex
9760
0
         && t[1].opcode_space <= SPACE_0F38
9761
0
         && t->opcode_modifier.vexvvvv == VexVVVV_DST)
9762
0
        || t->mnem_off == MN_movbe)
9763
0
    && (i.types[i.operands - 1].bitfield.dword
9764
0
        || i.types[i.operands - 1].bitfield.qword))
9765
0
  {
9766
0
    unsigned int match_dest_op = can_convert_NDD_to_legacy (t);
9767
9768
0
    if (match_dest_op != (unsigned int) ~0)
9769
0
      {
9770
0
        size_match = true;
9771
        /* We ensure that the next template has the same input
9772
     operands as the original matching template by the first
9773
     opernd (ATT). To avoid someone support new NDD insns and
9774
     put it in the wrong position.  */
9775
0
        overlap0 = operand_type_and (i.types[0],
9776
0
             t[1].operand_types[0]);
9777
0
        if (t->opcode_modifier.d)
9778
0
    overlap1 = operand_type_and (i.types[0],
9779
0
               t[1].operand_types[1]);
9780
0
        if (!operand_type_match (overlap0, i.types[0])
9781
0
      && (!t->opcode_modifier.d
9782
0
          || !operand_type_match (overlap1, i.types[0])))
9783
0
    size_match = false;
9784
9785
0
        if (size_match
9786
0
      && (t[1].opcode_space <= SPACE_0F
9787
          /* Some non-legacy-map0/1 insns can be shorter when
9788
       legacy-encoded and when no REX prefix is required.  */
9789
0
          || (!check_EgprOperands (t + 1)
9790
0
        && !check_Rex_required ()
9791
0
        && !i.op[i.operands - 1].regs->reg_type.bitfield.qword)))
9792
0
    {
9793
0
      if (i.operands > 2 && match_dest_op == i.operands - 3)
9794
0
        {
9795
0
          swap_2_operands (match_dest_op, i.operands - 2);
9796
9797
          /* CMOVcc is marked commutative, but then also needs its
9798
       encoded condition inverted.  */
9799
0
          if ((t->base_opcode | 0xf) == 0x4f)
9800
0
      i.invert_cond = true;
9801
0
        }
9802
9803
0
      --i.operands;
9804
0
      --i.reg_operands;
9805
9806
0
      if (t->mnem_off == MN_movbe)
9807
0
        {
9808
0
          gas_assert (t[1].mnem_off == MN_bswap);
9809
0
          ++current_templates.end;
9810
0
        }
9811
9812
0
      specific_error = progress (internal_error);
9813
0
      continue;
9814
0
    }
9815
9816
0
      }
9817
0
  }
9818
9819
      /* We've found a match; break out of loop.  */
9820
0
      break;
9821
0
    }
9822
9823
0
#undef progress
9824
9825
0
  if (t == current_templates.end)
9826
0
    {
9827
      /* We found no match.  */
9828
0
      i.error = specific_error;
9829
0
      return NULL;
9830
0
    }
9831
9832
  /* Don't emit diagnostics or install the template when one was already
9833
     installed, i.e. when called from process_suffix().  */
9834
0
  if (i.tm.mnem_off)
9835
0
    return t;
9836
9837
0
  if (!quiet_warnings)
9838
0
    {
9839
0
      if (!intel_syntax
9840
0
    && (i.jumpabsolute != (t->opcode_modifier.jump == JUMP_ABSOLUTE)))
9841
0
  as_warn (_("indirect %s without `*'"), insn_name (t));
9842
9843
0
      if (t->opcode_modifier.isprefix
9844
0
    && t->opcode_modifier.mnemonicsize == IGNORESIZE)
9845
0
  {
9846
    /* Warn them that a data or address size prefix doesn't
9847
       affect assembly of the next line of code.  */
9848
0
    as_warn (_("stand-alone `%s' prefix"), insn_name (t));
9849
0
  }
9850
9851
0
      if (intel_syntax && mnem_suffix && !t->opcode_modifier.intelsuffix)
9852
0
  {
9853
0
    static bool noticed;
9854
9855
0
    as_warn (_("mnemonic suffix used with `%s'"), insn_name (t));
9856
0
    if (!noticed)
9857
0
      {
9858
0
        noticed = true;
9859
0
        as_warn (_(
9860
0
"NOTE: Such forms are deprecated and will be rejected by a future version of the assembler"));
9861
0
      }
9862
0
  }
9863
0
    }
9864
9865
  /* Copy the template we found.  */
9866
0
  install_template (t);
9867
9868
0
  if (addr_prefix_disp != -1)
9869
0
    i.tm.operand_types[addr_prefix_disp]
9870
0
      = operand_types[addr_prefix_disp];
9871
9872
  /* APX insns acting on byte operands are WIG, yet that can't be expressed
9873
     in the templates (they're also covering word/dword/qword operands).  */
9874
0
  if (t->opcode_space == SPACE_MAP4 && !t->opcode_modifier.vexw &&
9875
0
      i.types[i.operands - 1].bitfield.byte)
9876
0
    {
9877
0
      gas_assert (t->opcode_modifier.w);
9878
0
      i.tm.opcode_modifier.vexw = VEXWIG;
9879
0
    }
9880
9881
0
  switch (found_reverse_match)
9882
0
    {
9883
0
    case 0:
9884
0
      break;
9885
9886
0
    case Opcode_FloatR:
9887
0
    case Opcode_FloatR | Opcode_FloatD:
9888
0
      i.tm.extension_opcode ^= Opcode_FloatR >> 3;
9889
0
      found_reverse_match &= Opcode_FloatD;
9890
9891
      /* Fall through.  */
9892
0
    default:
9893
      /* If we found a reverse match we must alter the opcode direction
9894
   bit and clear/flip the regmem modifier one.  found_reverse_match
9895
   holds bits to change (different for int & float insns).  */
9896
9897
0
      i.tm.base_opcode ^= found_reverse_match;
9898
9899
0
      if (i.tm.opcode_space == SPACE_MAP4)
9900
0
  goto swap_first_2;
9901
9902
      /* Certain SIMD insns have their load forms specified in the opcode
9903
   table, and hence we need to _set_ RegMem instead of clearing it.
9904
   We need to avoid setting the bit though on insns like KMOVW.  */
9905
0
      i.tm.opcode_modifier.regmem
9906
0
  = i.tm.opcode_modifier.modrm && i.tm.opcode_modifier.d
9907
0
    && i.tm.operands > 2U - i.tm.opcode_modifier.sse2avx
9908
0
    && !i.tm.opcode_modifier.regmem;
9909
9910
      /* Fall through.  */
9911
0
    case ~0:
9912
0
      if (i.tm.opcode_space == SPACE_MAP4
9913
0
    && !t->opcode_modifier.commutative)
9914
0
  i.tm.opcode_modifier.operandconstraint = EVEX_NF;
9915
0
      i.tm.operand_types[0] = operand_types[i.operands - 1];
9916
0
      i.tm.operand_types[i.operands - 1] = operand_types[0];
9917
0
      break;
9918
9919
0
    case Opcode_VexW:
9920
      /* Only the first two register operands need reversing, alongside
9921
   flipping VEX.W.  */
9922
0
      i.tm.opcode_modifier.vexw ^= VEXW0 ^ VEXW1;
9923
9924
      /* In 3-operand insns XOP.W changes which operand goes into XOP.vvvv.  */
9925
0
      i.tm.opcode_modifier.vexvvvv = VexVVVV_SRC1;
9926
9927
0
    swap_first_2:
9928
0
      j = i.tm.operand_types[0].bitfield.imm8;
9929
0
      i.tm.operand_types[j] = operand_types[j + 1];
9930
0
      i.tm.operand_types[j + 1] = operand_types[j];
9931
0
      break;
9932
0
    }
9933
9934
0
  return t;
9935
0
}
9936
9937
static int
9938
check_string (void)
9939
0
{
9940
0
  unsigned int es_op = i.tm.opcode_modifier.isstring - IS_STRING_ES_OP0;
9941
0
  unsigned int op = i.tm.operand_types[0].bitfield.baseindex ? es_op : 0;
9942
9943
0
  if (i.seg[op] != NULL && i.seg[op] != reg_es)
9944
0
    {
9945
0
      as_bad (_("`%s' operand %u must use `%ses' segment"),
9946
0
        insn_name (&i.tm),
9947
0
        intel_syntax ? i.tm.operands - es_op : es_op + 1,
9948
0
        register_prefix);
9949
0
      return 0;
9950
0
    }
9951
9952
  /* There's only ever one segment override allowed per instruction.
9953
     This instruction possibly has a legal segment override on the
9954
     second operand, so copy the segment to where non-string
9955
     instructions store it, allowing common code.  */
9956
0
  i.seg[op] = i.seg[1];
9957
9958
0
  return 1;
9959
0
}
9960
9961
static int
9962
process_suffix (const insn_template *t)
9963
0
{
9964
0
  bool is_movx = false;
9965
9966
  /* If matched instruction specifies an explicit instruction mnemonic
9967
     suffix, use it.  */
9968
0
  if (i.tm.opcode_modifier.size == SIZE16)
9969
0
    i.suffix = WORD_MNEM_SUFFIX;
9970
0
  else if (i.tm.opcode_modifier.size == SIZE32)
9971
0
    i.suffix = LONG_MNEM_SUFFIX;
9972
0
  else if (i.tm.opcode_modifier.size == SIZE64)
9973
0
    i.suffix = QWORD_MNEM_SUFFIX;
9974
0
  else if (i.reg_operands
9975
0
     && (i.operands > 1 || i.types[0].bitfield.class == Reg)
9976
0
     && i.tm.opcode_modifier.operandconstraint != ADDR_PREFIX_OP_REG)
9977
0
    {
9978
0
      unsigned int numop = i.operands;
9979
9980
      /* MOVSX/MOVZX */
9981
0
      is_movx = (i.tm.opcode_space == SPACE_0F
9982
0
     && (i.tm.base_opcode | 8) == 0xbe)
9983
0
    || (i.tm.opcode_space == SPACE_BASE
9984
0
        && i.tm.base_opcode == 0x63
9985
0
        && is_cpu (&i.tm, Cpu64));
9986
9987
      /* movsx/movzx want only their source operand considered here, for the
9988
   ambiguity checking below.  The suffix will be replaced afterwards
9989
   to represent the destination (register).  */
9990
0
      if (is_movx && (i.tm.opcode_modifier.w || i.tm.base_opcode == 0x63))
9991
0
  --i.operands;
9992
9993
      /* crc32 needs REX.W set regardless of suffix / source operand size.  */
9994
0
      if (i.tm.mnem_off == MN_crc32 && i.tm.operand_types[1].bitfield.qword)
9995
0
        i.rex |= REX_W;
9996
9997
      /* If there's no instruction mnemonic suffix we try to invent one
9998
   based on GPR operands.  */
9999
0
      if (!i.suffix)
10000
0
  {
10001
    /* We take i.suffix from the last register operand specified,
10002
       Destination register type is more significant than source
10003
       register type.  crc32 in SSE4.2 prefers source register
10004
       type. */
10005
0
    unsigned int op = i.tm.mnem_off == MN_crc32 ? 1 : i.operands;
10006
10007
0
    while (op--)
10008
0
      if (i.tm.operand_types[op].bitfield.instance == InstanceNone
10009
0
    || i.tm.operand_types[op].bitfield.instance == Accum)
10010
0
        {
10011
0
    if (i.types[op].bitfield.class != Reg)
10012
0
      continue;
10013
0
    if (i.types[op].bitfield.byte)
10014
0
      i.suffix = BYTE_MNEM_SUFFIX;
10015
0
    else if (i.types[op].bitfield.word)
10016
0
      i.suffix = WORD_MNEM_SUFFIX;
10017
0
    else if (i.types[op].bitfield.dword)
10018
0
      i.suffix = LONG_MNEM_SUFFIX;
10019
0
    else if (i.types[op].bitfield.qword)
10020
0
      i.suffix = QWORD_MNEM_SUFFIX;
10021
0
    else
10022
0
      continue;
10023
0
    break;
10024
0
        }
10025
10026
    /* As an exception, movsx/movzx silently default to a byte source
10027
       in AT&T mode.  */
10028
0
    if (is_movx && i.tm.opcode_modifier.w && !i.suffix && !intel_syntax)
10029
0
      i.suffix = BYTE_MNEM_SUFFIX;
10030
0
  }
10031
0
      else if (i.suffix == BYTE_MNEM_SUFFIX)
10032
0
  {
10033
0
    if (!check_byte_reg ())
10034
0
      return 0;
10035
0
  }
10036
0
      else if (i.suffix == LONG_MNEM_SUFFIX)
10037
0
  {
10038
0
    if (!check_long_reg ())
10039
0
      return 0;
10040
0
  }
10041
0
      else if (i.suffix == QWORD_MNEM_SUFFIX)
10042
0
  {
10043
0
    if (!check_qword_reg ())
10044
0
      return 0;
10045
0
  }
10046
0
      else if (i.suffix == WORD_MNEM_SUFFIX)
10047
0
  {
10048
0
    if (!check_word_reg ())
10049
0
      return 0;
10050
0
  }
10051
0
      else if (intel_syntax
10052
0
         && i.tm.opcode_modifier.mnemonicsize == IGNORESIZE)
10053
  /* Do nothing if the instruction is going to ignore the prefix.  */
10054
0
  ;
10055
0
      else
10056
0
  abort ();
10057
10058
      /* Undo the movsx/movzx change done above.  */
10059
0
      i.operands = numop;
10060
0
    }
10061
0
  else if (i.tm.opcode_modifier.mnemonicsize == DEFAULTSIZE
10062
0
     && !i.suffix)
10063
0
    {
10064
0
      i.suffix = stackop_size;
10065
0
      if (stackop_size == LONG_MNEM_SUFFIX)
10066
0
  {
10067
    /* stackop_size is set to LONG_MNEM_SUFFIX for the
10068
       .code16gcc directive to support 16-bit mode with
10069
       32-bit address.  For IRET without a suffix, generate
10070
       16-bit IRET (opcode 0xcf) to return from an interrupt
10071
       handler.  */
10072
0
    if (i.tm.base_opcode == 0xcf)
10073
0
      {
10074
0
        i.suffix = WORD_MNEM_SUFFIX;
10075
0
        as_warn (_("generating 16-bit `iret' for .code16gcc directive"));
10076
0
      }
10077
    /* Warn about changed behavior for segment register push/pop.  */
10078
0
    else if ((i.tm.base_opcode | 1) == 0x07)
10079
0
      as_warn (_("generating 32-bit `%s', unlike earlier gas versions"),
10080
0
         insn_name (&i.tm));
10081
0
  }
10082
0
    }
10083
0
  else if (!i.suffix
10084
0
     && (i.tm.opcode_modifier.jump == JUMP_ABSOLUTE
10085
0
         || i.tm.opcode_modifier.jump == JUMP_BYTE
10086
0
         || i.tm.opcode_modifier.jump == JUMP_INTERSEGMENT
10087
0
         || (i.tm.opcode_space == SPACE_0F
10088
0
       && i.tm.base_opcode == 0x01 /* [ls][gi]dt */
10089
0
       && i.tm.extension_opcode <= 3)))
10090
0
    {
10091
0
      switch (flag_code)
10092
0
  {
10093
0
  case CODE_64BIT:
10094
0
    if (!i.tm.opcode_modifier.no_qsuf)
10095
0
      {
10096
0
        if (i.tm.opcode_modifier.jump == JUMP_BYTE
10097
0
      || i.tm.opcode_modifier.no_lsuf)
10098
0
    i.suffix = QWORD_MNEM_SUFFIX;
10099
0
        break;
10100
0
      }
10101
    /* Fall through.  */
10102
0
  case CODE_32BIT:
10103
0
    if (!i.tm.opcode_modifier.no_lsuf)
10104
0
      i.suffix = LONG_MNEM_SUFFIX;
10105
0
    break;
10106
0
  case CODE_16BIT:
10107
0
    if (!i.tm.opcode_modifier.no_wsuf)
10108
0
      i.suffix = WORD_MNEM_SUFFIX;
10109
0
    break;
10110
0
  }
10111
0
    }
10112
10113
0
  if (!i.suffix
10114
0
      && (i.tm.opcode_modifier.mnemonicsize != DEFAULTSIZE
10115
    /* Also cover lret/retf/iret in 64-bit mode.  */
10116
0
    || (flag_code == CODE_64BIT
10117
0
        && !i.tm.opcode_modifier.no_lsuf
10118
0
        && !i.tm.opcode_modifier.no_qsuf))
10119
0
      && i.tm.opcode_modifier.mnemonicsize != IGNORESIZE
10120
      /* Explicit sizing prefixes are assumed to disambiguate insns.  */
10121
0
      && !i.prefix[DATA_PREFIX] && !(i.prefix[REX_PREFIX] & REX_W)
10122
      /* Accept FLDENV et al without suffix.  */
10123
0
      && (i.tm.opcode_modifier.no_ssuf || i.tm.opcode_modifier.floatmf))
10124
0
    {
10125
0
      unsigned int suffixes, evex = 0;
10126
10127
0
      suffixes = !i.tm.opcode_modifier.no_bsuf;
10128
0
      if (!i.tm.opcode_modifier.no_wsuf)
10129
0
  suffixes |= 1 << 1;
10130
0
      if (!i.tm.opcode_modifier.no_lsuf)
10131
0
  suffixes |= 1 << 2;
10132
0
      if (!i.tm.opcode_modifier.no_ssuf)
10133
0
  suffixes |= 1 << 4;
10134
0
      if (flag_code == CODE_64BIT && !i.tm.opcode_modifier.no_qsuf)
10135
0
  suffixes |= 1 << 5;
10136
10137
      /* Operand size may be ambiguous only across multiple templates.  Avoid
10138
   the extra effort though if we already know that multiple suffixes /
10139
   operand sizes are allowed.  Also limit this to non-SIMD operand sizes
10140
   (i.e. ones expressable via suffixes) for now.
10141
   There's one special case though that needs excluding: Insns taking
10142
   Disp<N> operands also match templates permitting BaseIndex.  JMP in
10143
   particular would thus wrongly trigger the check further down.  Cover
10144
   JUMP_DWORD insns here as well, just in case.  */
10145
0
      if (i.tm.opcode_modifier.jump != JUMP
10146
0
    && i.tm.opcode_modifier.jump != JUMP_DWORD)
10147
0
  while (!(suffixes & (suffixes - 1)))
10148
0
    {
10149
      /* Sadly check_VecOperands(), running ahead of install_template(),
10150
         may update i.memshift.  Save and restore the value here.  */
10151
0
      unsigned int memshift = i.memshift;
10152
10153
0
      current_templates.start = t + 1;
10154
0
      t = match_template (0);
10155
0
      i.memshift = memshift;
10156
0
      if (t == NULL)
10157
0
        break;
10158
0
      if (!t->opcode_modifier.no_bsuf)
10159
0
        suffixes |= 1 << 0;
10160
0
      if (!t->opcode_modifier.no_wsuf)
10161
0
        suffixes |= 1 << 1;
10162
0
      if (!t->opcode_modifier.no_lsuf)
10163
0
        suffixes |= 1 << 2;
10164
0
      if (!t->opcode_modifier.no_ssuf)
10165
0
        suffixes |= 1 << 4;
10166
0
      if (flag_code == CODE_64BIT && !t->opcode_modifier.no_qsuf)
10167
0
        suffixes |= 1 << 5;
10168
0
    }
10169
10170
      /* For [XYZ]MMWORD operands inspect operand sizes.  While generally
10171
   also suitable for AT&T syntax mode, it was requested that this be
10172
   restricted to just Intel syntax.  */
10173
0
      if (intel_syntax && is_any_vex_encoding (&i.tm)
10174
0
    && !i.broadcast.type && !i.broadcast.bytes)
10175
0
  {
10176
0
    unsigned int op;
10177
10178
0
    for (op = 0; op < i.tm.operands; ++op)
10179
0
      {
10180
0
        if (vector_size < VSZ512)
10181
0
    {
10182
0
      i.tm.operand_types[op].bitfield.zmmword = 0;
10183
0
      if (vector_size < VSZ256)
10184
0
        {
10185
0
          i.tm.operand_types[op].bitfield.ymmword = 0;
10186
0
          if (i.tm.operand_types[op].bitfield.xmmword
10187
0
        && i.tm.opcode_modifier.evex == EVEXDYN)
10188
0
      i.tm.opcode_modifier.evex = EVEX128;
10189
0
        }
10190
0
      else if (i.tm.operand_types[op].bitfield.ymmword
10191
0
         && !i.tm.operand_types[op].bitfield.xmmword
10192
0
         && i.tm.opcode_modifier.evex == EVEXDYN)
10193
0
        i.tm.opcode_modifier.evex = EVEX256;
10194
0
    }
10195
0
        else if (i.tm.opcode_modifier.evex
10196
0
           && !cpu_arch_flags.bitfield.cpuavx512vl)
10197
0
    {
10198
0
      if (i.tm.operand_types[op].bitfield.ymmword)
10199
0
        i.tm.operand_types[op].bitfield.xmmword = 0;
10200
0
      if (i.tm.operand_types[op].bitfield.zmmword)
10201
0
        i.tm.operand_types[op].bitfield.ymmword = 0;
10202
0
      if (i.tm.opcode_modifier.evex == EVEXDYN)
10203
0
        i.tm.opcode_modifier.evex = EVEX512;
10204
0
    }
10205
10206
0
        if (i.tm.operand_types[op].bitfield.xmmword
10207
0
      + i.tm.operand_types[op].bitfield.ymmword
10208
0
      + i.tm.operand_types[op].bitfield.zmmword < 2)
10209
0
    continue;
10210
10211
        /* Any properly sized operand disambiguates the insn.  */
10212
0
        if (i.types[op].bitfield.xmmword
10213
0
      || i.types[op].bitfield.ymmword
10214
0
      || i.types[op].bitfield.zmmword)
10215
0
    {
10216
0
      suffixes &= ~(7 << 6);
10217
0
      evex = 0;
10218
0
      break;
10219
0
    }
10220
10221
0
        if ((i.flags[op] & Operand_Mem)
10222
0
      && i.tm.operand_types[op].bitfield.unspecified)
10223
0
    {
10224
0
      if (i.tm.operand_types[op].bitfield.xmmword)
10225
0
        suffixes |= 1 << 6;
10226
0
      if (i.tm.operand_types[op].bitfield.ymmword)
10227
0
        suffixes |= 1 << 7;
10228
0
      if (i.tm.operand_types[op].bitfield.zmmword)
10229
0
        suffixes |= 1 << 8;
10230
0
      if (i.tm.opcode_modifier.evex)
10231
0
        evex = EVEX512;
10232
0
    }
10233
0
      }
10234
0
  }
10235
10236
      /* Are multiple suffixes / operand sizes allowed?  */
10237
0
      if (suffixes & (suffixes - 1))
10238
0
  {
10239
0
    if (intel_syntax
10240
0
        && (i.tm.opcode_modifier.mnemonicsize != DEFAULTSIZE
10241
0
      || operand_check == check_error))
10242
0
      {
10243
0
        as_bad (_("ambiguous operand size for `%s'"), insn_name (&i.tm));
10244
0
        return 0;
10245
0
      }
10246
0
    if (operand_check == check_error)
10247
0
      {
10248
0
        as_bad (_("no instruction mnemonic suffix given and "
10249
0
      "no register operands; can't size `%s'"), insn_name (&i.tm));
10250
0
        return 0;
10251
0
      }
10252
0
    if (operand_check == check_warning)
10253
0
      as_warn (_("%s; using default for `%s'"),
10254
0
           intel_syntax
10255
0
           ? _("ambiguous operand size")
10256
0
           : _("no instruction mnemonic suffix given and "
10257
0
         "no register operands"),
10258
0
           insn_name (&i.tm));
10259
10260
0
    if (i.tm.opcode_modifier.floatmf)
10261
0
      i.suffix = SHORT_MNEM_SUFFIX;
10262
0
    else if (is_movx)
10263
0
      /* handled below */;
10264
0
    else if (evex)
10265
0
      i.tm.opcode_modifier.evex = evex;
10266
0
    else if (flag_code == CODE_16BIT)
10267
0
      i.suffix = WORD_MNEM_SUFFIX;
10268
0
    else if (!i.tm.opcode_modifier.no_lsuf)
10269
0
      i.suffix = LONG_MNEM_SUFFIX;
10270
0
    else
10271
0
      i.suffix = QWORD_MNEM_SUFFIX;
10272
0
  }
10273
0
    }
10274
10275
0
  if (is_movx)
10276
0
    {
10277
      /* In Intel syntax, movsx/movzx must have a "suffix" (checked above).
10278
   In AT&T syntax, if there is no suffix (warned about above), the default
10279
   will be byte extension.  */
10280
0
      if (i.tm.opcode_modifier.w && i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
10281
0
  i.tm.base_opcode |= 1;
10282
10283
      /* For further processing, the suffix should represent the destination
10284
   (register).  This is already the case when one was used with
10285
   mov[sz][bw]*, but we need to replace it for mov[sz]x, or if there was
10286
   no suffix to begin with.  */
10287
0
      if (i.tm.opcode_modifier.w || i.tm.base_opcode == 0x63 || !i.suffix)
10288
0
  {
10289
0
    if (i.types[1].bitfield.word)
10290
0
      i.suffix = WORD_MNEM_SUFFIX;
10291
0
    else if (i.types[1].bitfield.qword)
10292
0
      i.suffix = QWORD_MNEM_SUFFIX;
10293
0
    else
10294
0
      i.suffix = LONG_MNEM_SUFFIX;
10295
10296
0
    i.tm.opcode_modifier.w = 0;
10297
0
  }
10298
0
    }
10299
10300
0
  if (!i.tm.opcode_modifier.modrm && i.reg_operands && i.tm.operands < 3)
10301
0
    i.short_form = (i.tm.operand_types[0].bitfield.class == Reg)
10302
0
       != (i.tm.operand_types[1].bitfield.class == Reg);
10303
10304
  /* Change the opcode based on the operand size given by i.suffix.  */
10305
0
  switch (i.suffix)
10306
0
    {
10307
    /* Size floating point instruction.  */
10308
0
    case LONG_MNEM_SUFFIX:
10309
0
      if (i.tm.opcode_modifier.floatmf)
10310
0
  {
10311
0
    i.tm.base_opcode ^= 4;
10312
0
    break;
10313
0
  }
10314
    /* fall through */
10315
0
    case WORD_MNEM_SUFFIX:
10316
0
    case QWORD_MNEM_SUFFIX:
10317
      /* It's not a byte, select word/dword operation.  */
10318
0
      if (i.tm.opcode_modifier.w)
10319
0
  {
10320
0
    if (i.short_form)
10321
0
      i.tm.base_opcode |= 8;
10322
0
    else
10323
0
      i.tm.base_opcode |= 1;
10324
0
  }
10325
10326
      /* Set mode64 for an operand.  */
10327
0
      if (i.suffix == QWORD_MNEM_SUFFIX)
10328
0
  {
10329
0
    if (flag_code == CODE_64BIT
10330
0
        && !i.tm.opcode_modifier.norex64
10331
0
        && !i.tm.opcode_modifier.vexw
10332
        /* Special case for xchg %rax,%rax.  It is NOP and doesn't
10333
     need rex64. */
10334
0
        && ! (i.operands == 2
10335
0
        && i.tm.base_opcode == 0x90
10336
0
        && i.tm.opcode_space == SPACE_BASE
10337
0
        && i.types[0].bitfield.instance == Accum
10338
0
        && i.types[1].bitfield.instance == Accum))
10339
0
      i.rex |= REX_W;
10340
10341
0
    break;
10342
0
  }
10343
10344
    /* fall through */
10345
0
    case SHORT_MNEM_SUFFIX:
10346
      /* Now select between word & dword operations via the operand
10347
   size prefix, except for instructions that will ignore this
10348
   prefix anyway.  */
10349
0
      if (i.tm.opcode_modifier.mnemonicsize != IGNORESIZE
10350
0
    && !i.tm.opcode_modifier.floatmf
10351
0
    && (!is_any_vex_encoding (&i.tm)
10352
0
        || i.tm.opcode_space == SPACE_MAP4)
10353
0
    && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
10354
0
        || (flag_code == CODE_64BIT
10355
0
      && i.tm.opcode_modifier.jump == JUMP_BYTE)))
10356
0
  {
10357
0
    unsigned int prefix = DATA_PREFIX_OPCODE;
10358
10359
0
    if (i.tm.opcode_modifier.jump == JUMP_BYTE) /* jcxz, loop */
10360
0
      prefix = ADDR_PREFIX_OPCODE;
10361
10362
    /* The DATA PREFIX of EVEX promoted from legacy APX instructions
10363
       needs to be adjusted.  */
10364
0
    if (i.tm.opcode_space == SPACE_MAP4)
10365
0
      {
10366
0
        gas_assert (!i.tm.opcode_modifier.opcodeprefix);
10367
0
        i.tm.opcode_modifier.opcodeprefix = PREFIX_0X66;
10368
0
      }
10369
0
    else if (!add_prefix (prefix))
10370
0
      return 0;
10371
0
  }
10372
10373
0
      break;
10374
10375
0
    case 0:
10376
      /* Select word/dword/qword operation with explicit data sizing prefix
10377
   when there are no suitable register operands.  */
10378
0
      if (i.tm.opcode_modifier.w
10379
0
    && (i.prefix[DATA_PREFIX] || (i.prefix[REX_PREFIX] & REX_W))
10380
0
    && (!i.reg_operands
10381
0
        || (i.reg_operands == 1
10382
          /* ShiftCount */
10383
0
      && (i.tm.operand_types[0].bitfield.instance == RegC
10384
          /* InOutPortReg */
10385
0
          || i.tm.operand_types[0].bitfield.instance == RegD
10386
0
          || i.tm.operand_types[1].bitfield.instance == RegD
10387
0
          || i.tm.mnem_off == MN_crc32))))
10388
0
  i.tm.base_opcode |= 1;
10389
0
      break;
10390
0
    }
10391
10392
0
  if (i.tm.opcode_modifier.operandconstraint == ADDR_PREFIX_OP_REG)
10393
0
    {
10394
0
      gas_assert (!i.suffix);
10395
0
      gas_assert (i.reg_operands);
10396
10397
0
      if (i.tm.operand_types[0].bitfield.instance == Accum
10398
0
    || i.operands == 1)
10399
0
  {
10400
    /* The address size override prefix changes the size of the
10401
       first operand.  */
10402
0
    if (flag_code == CODE_64BIT
10403
0
        && i.op[0].regs->reg_type.bitfield.word)
10404
0
      {
10405
0
        as_bad (_("16-bit addressing unavailable for `%s'"),
10406
0
          insn_name (&i.tm));
10407
0
        return 0;
10408
0
      }
10409
10410
0
    if ((flag_code == CODE_32BIT
10411
0
         ? i.op[0].regs->reg_type.bitfield.word
10412
0
         : i.op[0].regs->reg_type.bitfield.dword)
10413
0
        && !add_prefix (ADDR_PREFIX_OPCODE))
10414
0
      return 0;
10415
0
  }
10416
0
      else
10417
0
  {
10418
    /* Check invalid register operand when the address size override
10419
       prefix changes the size of register operands.  */
10420
0
    unsigned int op;
10421
0
    enum { need_word, need_dword, need_qword } need;
10422
10423
    /* Check the register operand for the address size prefix if
10424
       the memory operand has no real registers, like symbol, DISP
10425
       or bogus (x32-only) symbol(%rip) when symbol(%eip) is meant.  */
10426
0
    if (i.mem_operands == 1
10427
0
        && i.reg_operands == 1
10428
0
        && i.operands == 2
10429
0
        && i.types[1].bitfield.class == Reg
10430
0
        && (flag_code == CODE_32BIT
10431
0
      ? i.op[1].regs->reg_type.bitfield.word
10432
0
      : i.op[1].regs->reg_type.bitfield.dword)
10433
0
        && ((i.base_reg == NULL && i.index_reg == NULL)
10434
0
#ifdef OBJ_ELF
10435
0
      || (x86_elf_abi == X86_64_X32_ABI
10436
0
          && i.base_reg
10437
0
          && i.base_reg->reg_num == RegIP
10438
0
          && i.base_reg->reg_type.bitfield.qword))
10439
#else
10440
      || 0)
10441
#endif
10442
0
        && !add_prefix (ADDR_PREFIX_OPCODE))
10443
0
      return 0;
10444
10445
0
    if (flag_code == CODE_32BIT)
10446
0
      need = i.prefix[ADDR_PREFIX] ? need_word : need_dword;
10447
0
    else if (i.prefix[ADDR_PREFIX])
10448
0
      need = need_dword;
10449
0
    else
10450
0
      need = flag_code == CODE_64BIT ? need_qword : need_word;
10451
10452
0
    for (op = i.imm_operands; op < i.operands; op++)
10453
0
      {
10454
0
        if (i.types[op].bitfield.class != Reg)
10455
0
    continue;
10456
10457
0
        switch (need)
10458
0
    {
10459
0
    case need_word:
10460
0
      if (i.op[op].regs->reg_type.bitfield.word)
10461
0
        continue;
10462
0
      break;
10463
0
    case need_dword:
10464
0
      if (i.op[op].regs->reg_type.bitfield.dword)
10465
0
        continue;
10466
0
      break;
10467
0
    case need_qword:
10468
0
      if (i.op[op].regs->reg_type.bitfield.qword)
10469
0
        continue;
10470
0
      break;
10471
0
    }
10472
10473
0
        as_bad (_("invalid register operand size for `%s'"),
10474
0
          insn_name (&i.tm));
10475
0
        return 0;
10476
0
      }
10477
0
  }
10478
0
    }
10479
10480
0
  return 1;
10481
0
}
10482
10483
static int
10484
check_byte_reg (void)
10485
0
{
10486
0
  int op;
10487
10488
0
  for (op = i.operands; --op >= 0;)
10489
0
    {
10490
      /* Skip non-register operands. */
10491
0
      if (i.types[op].bitfield.class != Reg)
10492
0
  continue;
10493
10494
      /* If this is an eight bit register, it's OK.  */
10495
0
      if (i.types[op].bitfield.byte)
10496
0
  {
10497
0
    if (i.tm.opcode_modifier.checkoperandsize)
10498
0
      break;
10499
0
    continue;
10500
0
  }
10501
10502
      /* I/O port address operands are OK too.  */
10503
0
      if (i.tm.operand_types[op].bitfield.instance == RegD
10504
0
    && i.tm.operand_types[op].bitfield.word)
10505
0
  continue;
10506
10507
      /* crc32 only wants its source operand checked here.  */
10508
0
      if (i.tm.mnem_off == MN_crc32 && op != 0)
10509
0
  continue;
10510
10511
      /* Any other register is bad.  */
10512
0
      as_bad (_("`%s%s' not allowed with `%s%c'"),
10513
0
        register_prefix, i.op[op].regs->reg_name,
10514
0
        insn_name (&i.tm), i.suffix);
10515
0
      return 0;
10516
0
    }
10517
0
  return 1;
10518
0
}
10519
10520
static int
10521
check_long_reg (void)
10522
0
{
10523
0
  int op;
10524
10525
0
  for (op = i.operands; --op >= 0;)
10526
    /* Skip non-register operands. */
10527
0
    if (i.types[op].bitfield.class != Reg)
10528
0
      continue;
10529
    /* Reject eight bit registers, except where the template requires
10530
       them. (eg. movzb)  */
10531
0
    else if (i.types[op].bitfield.byte
10532
0
       && (i.tm.operand_types[op].bitfield.word
10533
0
     || i.tm.operand_types[op].bitfield.dword
10534
0
     || i.tm.operand_types[op].bitfield.qword))
10535
0
      {
10536
0
  as_bad (_("`%s%s' not allowed with `%s%c'"),
10537
0
    register_prefix,
10538
0
    i.op[op].regs->reg_name,
10539
0
    insn_name (&i.tm),
10540
0
    i.suffix);
10541
0
  return 0;
10542
0
      }
10543
    /* Error if the e prefix on a general reg is missing, or if the r
10544
       prefix on a general reg is present.  */
10545
0
    else if ((i.types[op].bitfield.word
10546
0
        || i.types[op].bitfield.qword)
10547
0
       && i.tm.operand_types[op].bitfield.dword)
10548
0
      {
10549
0
  as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
10550
0
    register_prefix, i.op[op].regs->reg_name,
10551
0
    i.suffix);
10552
0
  return 0;
10553
0
      }
10554
0
    else if (i.tm.opcode_modifier.checkoperandsize)
10555
0
      break;
10556
10557
0
  return 1;
10558
0
}
10559
10560
static int
10561
check_qword_reg (void)
10562
0
{
10563
0
  int op;
10564
10565
0
  for (op = i.operands; --op >= 0; )
10566
    /* Skip non-register operands. */
10567
0
    if (i.types[op].bitfield.class != Reg)
10568
0
      continue;
10569
    /* Reject eight bit registers, except where the template requires
10570
       them. (eg. movzb)  */
10571
0
    else if (i.types[op].bitfield.byte
10572
0
       && (i.tm.operand_types[op].bitfield.word
10573
0
     || i.tm.operand_types[op].bitfield.dword
10574
0
     || i.tm.operand_types[op].bitfield.qword))
10575
0
      {
10576
0
  as_bad (_("`%s%s' not allowed with `%s%c'"),
10577
0
    register_prefix,
10578
0
    i.op[op].regs->reg_name,
10579
0
    insn_name (&i.tm),
10580
0
    i.suffix);
10581
0
  return 0;
10582
0
      }
10583
    /* Error if the r prefix on a general reg is missing.  */
10584
0
    else if ((i.types[op].bitfield.word
10585
0
        || i.types[op].bitfield.dword)
10586
0
       && i.tm.operand_types[op].bitfield.qword)
10587
0
      {
10588
0
  as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
10589
0
    register_prefix, i.op[op].regs->reg_name, i.suffix);
10590
0
  return 0;
10591
0
      }
10592
0
    else if (i.tm.opcode_modifier.checkoperandsize)
10593
0
      break;
10594
10595
0
  return 1;
10596
0
}
10597
10598
static int
10599
check_word_reg (void)
10600
0
{
10601
0
  int op;
10602
0
  for (op = i.operands; --op >= 0;)
10603
    /* Skip non-register operands. */
10604
0
    if (i.types[op].bitfield.class != Reg)
10605
0
      continue;
10606
    /* Reject eight bit registers, except where the template requires
10607
       them. (eg. movzb)  */
10608
0
    else if (i.types[op].bitfield.byte
10609
0
       && (i.tm.operand_types[op].bitfield.word
10610
0
     || i.tm.operand_types[op].bitfield.dword
10611
0
     || i.tm.operand_types[op].bitfield.qword))
10612
0
      {
10613
0
  as_bad (_("`%s%s' not allowed with `%s%c'"),
10614
0
    register_prefix,
10615
0
    i.op[op].regs->reg_name,
10616
0
    insn_name (&i.tm),
10617
0
    i.suffix);
10618
0
  return 0;
10619
0
      }
10620
    /* Error if the e or r prefix on a general reg is present.  */
10621
0
    else if ((i.types[op].bitfield.dword
10622
0
     || i.types[op].bitfield.qword)
10623
0
       && i.tm.operand_types[op].bitfield.word)
10624
0
      {
10625
0
  as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
10626
0
    register_prefix, i.op[op].regs->reg_name,
10627
0
    i.suffix);
10628
0
  return 0;
10629
0
      }
10630
0
    else if (i.tm.opcode_modifier.checkoperandsize)
10631
0
      break;
10632
10633
0
  return 1;
10634
0
}
10635
10636
static int
10637
update_imm (unsigned int j)
10638
0
{
10639
0
  i386_operand_type overlap = i.types[j];
10640
10641
0
  if (i.tm.operand_types[j].bitfield.imm8
10642
0
      && i.tm.operand_types[j].bitfield.imm8s
10643
0
      && overlap.bitfield.imm8 && overlap.bitfield.imm8s)
10644
0
    {
10645
      /* This combination is used on 8-bit immediates where e.g. $~0 is
10646
   desirable to permit.  We're past operand type matching, so simply
10647
   put things back in the shape they were before introducing the
10648
   distinction between Imm8, Imm8S, and Imm8|Imm8S.  */
10649
0
      overlap.bitfield.imm8s = 0;
10650
0
    }
10651
10652
0
  if (overlap.bitfield.imm8
10653
0
      + overlap.bitfield.imm8s
10654
0
      + overlap.bitfield.imm16
10655
0
      + overlap.bitfield.imm32
10656
0
      + overlap.bitfield.imm32s
10657
0
      + overlap.bitfield.imm64 > 1)
10658
0
    {
10659
0
      static const i386_operand_type imm16 = { .bitfield = { .imm16 = 1 } };
10660
0
      static const i386_operand_type imm32 = { .bitfield = { .imm32 = 1 } };
10661
0
      static const i386_operand_type imm32s = { .bitfield = { .imm32s = 1 } };
10662
0
      static const i386_operand_type imm16_32 = { .bitfield =
10663
0
  { .imm16 = 1, .imm32 = 1 }
10664
0
      };
10665
0
      static const i386_operand_type imm16_32s =  { .bitfield =
10666
0
  { .imm16 = 1, .imm32s = 1 }
10667
0
      };
10668
0
      static const i386_operand_type imm16_32_32s = { .bitfield =
10669
0
  { .imm16 = 1, .imm32 = 1, .imm32s = 1 }
10670
0
      };
10671
10672
0
      if (i.suffix)
10673
0
  {
10674
0
    i386_operand_type temp;
10675
10676
0
    operand_type_set (&temp, 0);
10677
0
    if (i.suffix == BYTE_MNEM_SUFFIX)
10678
0
      {
10679
0
        temp.bitfield.imm8 = overlap.bitfield.imm8;
10680
0
        temp.bitfield.imm8s = overlap.bitfield.imm8s;
10681
0
      }
10682
0
    else if (i.suffix == WORD_MNEM_SUFFIX)
10683
0
      temp.bitfield.imm16 = overlap.bitfield.imm16;
10684
0
    else if (i.suffix == QWORD_MNEM_SUFFIX)
10685
0
      {
10686
0
        temp.bitfield.imm64 = overlap.bitfield.imm64;
10687
0
        temp.bitfield.imm32s = overlap.bitfield.imm32s;
10688
0
      }
10689
0
    else
10690
0
      temp.bitfield.imm32 = overlap.bitfield.imm32;
10691
0
    overlap = temp;
10692
0
  }
10693
0
      else if (operand_type_equal (&overlap, &imm16_32_32s)
10694
0
         || operand_type_equal (&overlap, &imm16_32)
10695
0
         || operand_type_equal (&overlap, &imm16_32s))
10696
0
  {
10697
0
    if ((flag_code == CODE_16BIT)
10698
0
        ^ (i.prefix[DATA_PREFIX] != 0 && !(i.prefix[REX_PREFIX] & REX_W)))
10699
0
      overlap = imm16;
10700
0
    else
10701
0
      overlap = imm32s;
10702
0
  }
10703
0
      else if (i.prefix[REX_PREFIX] & REX_W)
10704
0
  overlap = operand_type_and (overlap, imm32s);
10705
0
      else if (i.prefix[DATA_PREFIX])
10706
0
  overlap = operand_type_and (overlap,
10707
0
            flag_code != CODE_16BIT ? imm16 : imm32);
10708
0
      if (overlap.bitfield.imm8
10709
0
    + overlap.bitfield.imm8s
10710
0
    + overlap.bitfield.imm16
10711
0
    + overlap.bitfield.imm32
10712
0
    + overlap.bitfield.imm32s
10713
0
    + overlap.bitfield.imm64 != 1)
10714
0
  {
10715
0
    as_bad (_("no instruction mnemonic suffix given; "
10716
0
        "can't determine immediate size"));
10717
0
    return 0;
10718
0
  }
10719
0
    }
10720
0
  i.types[j] = overlap;
10721
10722
0
  return 1;
10723
0
}
10724
10725
static int
10726
finalize_imm (void)
10727
0
{
10728
0
  unsigned int j, n;
10729
10730
  /* Update the first 2 immediate operands.  */
10731
0
  n = i.operands > 2 ? 2 : i.operands;
10732
0
  if (n)
10733
0
    {
10734
0
      for (j = 0; j < n; j++)
10735
0
  if (update_imm (j) == 0)
10736
0
    return 0;
10737
10738
      /* The 3rd operand can't be immediate operand.  */
10739
0
      gas_assert (operand_type_check (i.types[2], imm) == 0);
10740
0
    }
10741
10742
0
  return 1;
10743
0
}
10744
10745
static INLINE void set_rex_vrex (const reg_entry *r, unsigned int rex_bit,
10746
         bool do_sse2avx)
10747
0
{
10748
0
  if (r->reg_flags & RegRex)
10749
0
    {
10750
0
      if (i.rex & rex_bit)
10751
0
  as_bad (_("same type of prefix used twice"));
10752
0
      i.rex |= rex_bit;
10753
0
    }
10754
0
  else if (do_sse2avx && (i.rex & rex_bit) && i.vex.register_specifier)
10755
0
    {
10756
0
      gas_assert (i.vex.register_specifier == r);
10757
0
      i.vex.register_specifier += 8;
10758
0
    }
10759
10760
0
  if (r->reg_flags & RegVRex)
10761
0
    i.vrex |= rex_bit;
10762
10763
0
  if (r->reg_flags & RegRex2)
10764
0
    i.rex2 |= rex_bit;
10765
0
}
10766
10767
static INLINE void
10768
set_rex_rex2 (const reg_entry *r, unsigned int rex_bit)
10769
0
{
10770
0
  if ((r->reg_flags & RegRex) != 0)
10771
0
    i.rex |= rex_bit;
10772
0
  if ((r->reg_flags & RegRex2) != 0)
10773
0
    i.rex2 |= rex_bit;
10774
0
}
10775
10776
static int
10777
process_operands (void)
10778
0
{
10779
  /* Default segment register this instruction will use for memory
10780
     accesses.  0 means unknown.  This is only for optimizing out
10781
     unnecessary segment overrides.  */
10782
0
  const reg_entry *default_seg = NULL;
10783
10784
0
  for (unsigned int j = i.imm_operands; j < i.operands; j++)
10785
0
    if (i.types[j].bitfield.instance != InstanceNone)
10786
0
      i.reg_operands--;
10787
10788
0
  if (i.tm.opcode_modifier.sse2avx)
10789
0
    {
10790
      /* Legacy encoded insns allow explicit REX prefixes, so these prefixes
10791
   need converting.  */
10792
0
      i.rex |= i.prefix[REX_PREFIX] & (REX_W | REX_R | REX_X | REX_B);
10793
0
      i.prefix[REX_PREFIX] = 0;
10794
0
      pp.rex_encoding = 0;
10795
0
      pp.rex2_encoding = 0;
10796
0
    }
10797
  /* ImmExt should be processed after SSE2AVX.  */
10798
0
  else if (i.tm.opcode_modifier.immext)
10799
0
    process_immext ();
10800
10801
  /* TILEZERO is unusual in that it has a single operand encoded in ModR/M.reg,
10802
     not ModR/M.rm.  To avoid special casing this in build_modrm_byte(), fake a
10803
     new destination operand here, while converting the source one to register
10804
     number 0.  */
10805
0
  if (i.tm.mnem_off == MN_tilezero)
10806
0
    {
10807
0
      copy_operand (1, 0);
10808
0
      i.op[0].regs -= i.op[0].regs->reg_num;
10809
0
      i.operands++;
10810
0
      i.reg_operands++;
10811
0
      i.tm.operands++;
10812
0
    }
10813
10814
0
  if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
10815
0
    {
10816
0
      static const i386_operand_type regxmm = {
10817
0
        .bitfield = { .class = RegSIMD, .xmmword = 1 }
10818
0
      };
10819
0
      unsigned int dupl = i.operands;
10820
0
      unsigned int dest = dupl - 1;
10821
0
      unsigned int j;
10822
10823
      /* The destination must be an xmm register.  */
10824
0
      gas_assert (i.reg_operands
10825
0
      && MAX_OPERANDS > dupl
10826
0
      && operand_type_equal (&i.types[dest], &regxmm));
10827
10828
0
      if (i.tm.operand_types[0].bitfield.instance == Accum
10829
0
    && i.tm.operand_types[0].bitfield.xmmword)
10830
0
  {
10831
    /* Keep xmm0 for instructions with VEX prefix and 3
10832
       sources.  */
10833
0
    i.tm.operand_types[0].bitfield.instance = InstanceNone;
10834
0
    i.tm.operand_types[0].bitfield.class = RegSIMD;
10835
0
    i.reg_operands++;
10836
0
    goto duplicate;
10837
0
  }
10838
10839
0
      if (i.tm.opcode_modifier.operandconstraint == IMPLICIT_1ST_XMM0)
10840
0
  {
10841
0
    gas_assert ((MAX_OPERANDS - 1) > dupl);
10842
10843
    /* Add the implicit xmm0 for instructions with VEX prefix
10844
       and 3 sources.  */
10845
0
    for (j = i.operands; j > 0; j--)
10846
0
      copy_operand (j, j - 1);
10847
0
    i.op[0].regs = str_hash_find (reg_hash, "xmm0");
10848
0
    i.types[0] = regxmm;
10849
0
    i.tm.operand_types[0] = regxmm;
10850
10851
0
    i.operands += 2;
10852
0
    i.reg_operands += 2;
10853
0
    i.tm.operands += 2;
10854
10855
0
    dupl++;
10856
0
    dest++;
10857
0
  }
10858
0
      else
10859
0
  {
10860
0
  duplicate:
10861
0
    i.operands++;
10862
0
    i.reg_operands++;
10863
0
    i.tm.operands++;
10864
0
  }
10865
10866
0
      copy_operand (dupl, dest);
10867
10868
0
      if (i.tm.opcode_modifier.immext)
10869
0
  process_immext ();
10870
0
    }
10871
0
  else if (i.tm.operand_types[0].bitfield.instance == Accum
10872
0
     && i.tm.opcode_modifier.modrm)
10873
0
    {
10874
0
      unsigned int j;
10875
10876
0
      for (j = 1; j < i.operands; j++)
10877
0
  copy_operand (j - 1, j);
10878
10879
      /* No adjustment to i.reg_operands: This was already done at the top
10880
   of the function.  */
10881
0
      i.operands--;
10882
0
      i.tm.operands--;
10883
0
    }
10884
0
  else if (i.tm.opcode_modifier.operandconstraint == IMPLICIT_GROUP)
10885
0
    {
10886
0
      unsigned int op, extra;
10887
0
      const reg_entry *first;
10888
10889
      /* The second operand must be {x,y,z,t}mmN.  */
10890
0
      gas_assert ((i.operands == 2 || i.operands == 3)
10891
0
      && i.types[1].bitfield.class == RegSIMD);
10892
10893
0
      switch (i.types[i.operands - 1].bitfield.class)
10894
0
  {
10895
0
  case RegSIMD:
10896
0
    op = 1;
10897
0
    if (i.operands == 2)
10898
0
      {
10899
        /* AMX-TRANSPOSE operand 2: N must be a multiple of 2. */
10900
0
        extra = 1;
10901
0
      }
10902
0
    else
10903
0
      {
10904
        /* AVX512-{4FMAPS,4VNNIW} operand 2: N must be a multiple of 4. */
10905
0
        extra = 3;
10906
0
      }
10907
0
    break;
10908
10909
0
  case RegMask:
10910
    /* AVX512-VP2INTERSECT operand 3: N must be a multiple of 2. */
10911
0
    op = 2;
10912
0
    extra = 1;
10913
0
    break;
10914
10915
0
  default:
10916
0
    abort ();
10917
0
  }
10918
10919
0
      first = i.op[op].regs - (register_number (i.op[op].regs) & extra);
10920
0
      if (i.op[op].regs != first)
10921
0
  as_warn (_("operand %u `%s%s' implicitly denotes"
10922
0
       " `%s%s' to `%s%s' group in `%s'"),
10923
0
     intel_syntax ? i.operands - op : op + 1,
10924
0
     register_prefix, i.op[op].regs->reg_name,
10925
0
     register_prefix, first[0].reg_name,
10926
0
     register_prefix, first[extra].reg_name,
10927
0
     insn_name (&i.tm));
10928
0
    }
10929
0
  else if (i.tm.opcode_modifier.operandconstraint == REG_KLUDGE)
10930
0
    {
10931
      /* The imul $imm, %reg instruction is converted into
10932
   imul $imm, %reg, %reg, and the clr %reg instruction
10933
   is converted into xor %reg, %reg.  */
10934
10935
0
      unsigned int first_reg_op;
10936
10937
0
      if (operand_type_check (i.types[0], reg))
10938
0
  first_reg_op = 0;
10939
0
      else
10940
0
  first_reg_op = 1;
10941
      /* Pretend we saw the extra register operand.  */
10942
0
      gas_assert (i.reg_operands == 1
10943
0
      && i.op[first_reg_op + 1].regs == 0);
10944
0
      i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
10945
0
      i.types[first_reg_op + 1] = i.types[first_reg_op];
10946
0
      i.operands++;
10947
0
      i.reg_operands++;
10948
10949
      /* For IMULZU switch around the constraint.  */
10950
0
      if (i.tm.mnem_off == MN_imulzu)
10951
0
  i.tm.opcode_modifier.operandconstraint = ZERO_UPPER;
10952
0
    }
10953
10954
0
  if (i.tm.opcode_modifier.modrm)
10955
0
    {
10956
      /* The opcode is completed (modulo i.tm.extension_opcode which
10957
   must be put into the modrm byte).  Now, we make the modrm and
10958
   index base bytes based on all the info we've collected.  */
10959
10960
0
      default_seg = build_modrm_byte ();
10961
10962
0
      if (!quiet_warnings && i.tm.opcode_modifier.operandconstraint == UGH)
10963
0
  {
10964
    /* Warn about some common errors, but press on regardless.  */
10965
0
    if (i.operands == 2)
10966
0
      {
10967
        /* Reversed arguments on faddp or fmulp.  */
10968
0
        as_warn (_("translating to `%s %s%s,%s%s'"), insn_name (&i.tm),
10969
0
           register_prefix, i.op[!intel_syntax].regs->reg_name,
10970
0
           register_prefix, i.op[intel_syntax].regs->reg_name);
10971
0
      }
10972
0
    else if (i.tm.opcode_modifier.mnemonicsize == IGNORESIZE)
10973
0
      {
10974
        /* Extraneous `l' suffix on fp insn.  */
10975
0
        as_warn (_("translating to `%s %s%s'"), insn_name (&i.tm),
10976
0
           register_prefix, i.op[0].regs->reg_name);
10977
0
      }
10978
0
  }
10979
0
    }
10980
0
  else if (i.types[0].bitfield.class == SReg && !dot_insn ())
10981
0
    {
10982
0
      if (flag_code != CODE_64BIT
10983
0
    ? i.tm.base_opcode == POP_SEG_SHORT
10984
0
      && i.op[0].regs->reg_num == 1
10985
0
    : (i.tm.base_opcode | 1) == (POP_SEG386_SHORT & 0xff)
10986
0
      && i.op[0].regs->reg_num < 4)
10987
0
  {
10988
0
    as_bad (_("you can't `%s %s%s'"),
10989
0
      insn_name (&i.tm), register_prefix, i.op[0].regs->reg_name);
10990
0
    return 0;
10991
0
  }
10992
0
      if (i.op[0].regs->reg_num > 3
10993
0
    && i.tm.opcode_space == SPACE_BASE )
10994
0
  {
10995
0
    i.tm.base_opcode ^= (POP_SEG_SHORT ^ POP_SEG386_SHORT) & 0xff;
10996
0
    i.tm.opcode_space = SPACE_0F;
10997
0
  }
10998
0
      i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
10999
0
    }
11000
0
  else if (i.tm.opcode_space == SPACE_BASE
11001
0
     && (i.tm.base_opcode & ~3) == MOV_AX_DISP32)
11002
0
    {
11003
0
      default_seg = reg_ds;
11004
0
    }
11005
0
  else if (i.tm.opcode_modifier.isstring)
11006
0
    {
11007
      /* For the string instructions that allow a segment override
11008
   on one of their operands, the default segment is ds.  */
11009
0
      default_seg = reg_ds;
11010
0
    }
11011
0
  else if (i.short_form)
11012
0
    {
11013
      /* The register operand is in the 1st or 2nd non-immediate operand.  */
11014
0
      const reg_entry *r = i.op[i.imm_operands].regs;
11015
11016
0
      if (!dot_insn ()
11017
0
    && r->reg_type.bitfield.instance == Accum
11018
0
    && i.op[i.imm_operands + 1].regs)
11019
0
  r = i.op[i.imm_operands + 1].regs;
11020
      /* Register goes in low 3 bits of opcode.  */
11021
0
      i.tm.base_opcode |= r->reg_num;
11022
0
      set_rex_vrex (r, REX_B, false);
11023
11024
0
      if (dot_insn () && i.reg_operands == 2)
11025
0
  {
11026
0
    gas_assert (is_any_vex_encoding (&i.tm)
11027
0
          || pp.encoding != encoding_default);
11028
0
    i.vex.register_specifier = i.op[i.operands - 1].regs;
11029
0
  }
11030
0
    }
11031
0
  else if (i.reg_operands == 1
11032
0
     && !i.flags[i.operands - 1]
11033
0
     && i.tm.operand_types[i.operands - 1].bitfield.instance
11034
0
        == InstanceNone)
11035
0
    {
11036
0
      gas_assert (is_any_vex_encoding (&i.tm)
11037
0
      || pp.encoding != encoding_default);
11038
0
      i.vex.register_specifier = i.op[i.operands - 1].regs;
11039
0
    }
11040
11041
0
  if ((i.seg[0] || i.prefix[SEG_PREFIX])
11042
0
      && i.tm.mnem_off == MN_lea)
11043
0
    {
11044
0
      if (!quiet_warnings)
11045
0
  as_warn (_("segment override on `%s' is ineffectual"), insn_name (&i.tm));
11046
0
      if (optimize && !pp.no_optimize)
11047
0
  {
11048
0
    i.seg[0] = NULL;
11049
0
    i.prefix[SEG_PREFIX] = 0;
11050
0
  }
11051
0
    }
11052
11053
  /* If a segment was explicitly specified, and the specified segment
11054
     is neither the default nor the one already recorded from a prefix,
11055
     use an opcode prefix to select it.  If we never figured out what
11056
     the default segment is, then default_seg will be zero at this
11057
     point, and the specified segment prefix will always be used.  */
11058
0
  if (i.seg[0]
11059
0
      && i.seg[0] != default_seg
11060
0
      && i386_seg_prefixes[i.seg[0]->reg_num] != i.prefix[SEG_PREFIX])
11061
0
    {
11062
0
      if (!add_prefix (i386_seg_prefixes[i.seg[0]->reg_num]))
11063
0
  return 0;
11064
0
    }
11065
0
  return 1;
11066
0
}
11067
11068
static const reg_entry *
11069
build_modrm_byte (void)
11070
0
{
11071
0
  const reg_entry *default_seg = NULL;
11072
0
  unsigned int source = i.imm_operands - i.tm.opcode_modifier.immext
11073
      /* Compensate for kludge in md_assemble().  */
11074
0
      + i.tm.operand_types[0].bitfield.imm1;
11075
0
  unsigned int dest = i.operands - 1 - i.tm.opcode_modifier.immext;
11076
0
  unsigned int v, op, reg_slot;
11077
11078
  /* Accumulator (in particular %st), shift count (%cl), and alike need
11079
     to be skipped just like immediate operands do.  */
11080
0
  if (i.tm.operand_types[source].bitfield.instance)
11081
0
    ++source;
11082
0
  while (i.tm.operand_types[dest].bitfield.instance)
11083
0
    --dest;
11084
11085
0
  for (op = source; op < i.operands; ++op)
11086
0
    if (i.tm.operand_types[op].bitfield.baseindex)
11087
0
      break;
11088
11089
0
  if (i.reg_operands + i.mem_operands + (i.tm.extension_opcode != None)
11090
0
      + (i.tm.opcode_modifier.operandconstraint == SCC) == 4)
11091
0
    {
11092
0
      expressionS *exp;
11093
11094
      /* There are 2 kinds of instructions:
11095
   1. 5 operands: 4 register operands or 3 register operands
11096
   plus 1 memory operand plus one Imm4 operand, VexXDS, and
11097
   VexW0 or VexW1.  The destination must be either XMM, YMM or
11098
   ZMM register.
11099
   2. 4 operands: 4 register operands or 3 register operands
11100
   plus 1 memory operand, with VexXDS.
11101
   3. Other equivalent combinations when coming from s_insn().  */
11102
0
      if (!dot_insn ())
11103
0
  {
11104
0
    gas_assert (i.tm.opcode_modifier.vexvvvv
11105
0
          && i.tm.opcode_modifier.vexw);
11106
0
    gas_assert (i.tm.operand_types[dest].bitfield.class == RegSIMD);
11107
0
  }
11108
11109
      /* Of the first two non-immediate operands the one with the template
11110
   not allowing for a memory one is encoded in the immediate operand.  */
11111
0
      if (source == op)
11112
0
  reg_slot = source + 1;
11113
0
      else
11114
0
  reg_slot = source++;
11115
11116
0
      if (!dot_insn ())
11117
0
  {
11118
0
    gas_assert (i.tm.operand_types[reg_slot].bitfield.class == RegSIMD);
11119
0
    gas_assert (!(i.op[reg_slot].regs->reg_flags & RegVRex));
11120
0
  }
11121
0
      else
11122
0
  gas_assert (i.tm.operand_types[reg_slot].bitfield.class != ClassNone);
11123
11124
0
      if (i.imm_operands == 0)
11125
0
  {
11126
    /* When there is no immediate operand, generate an 8bit
11127
       immediate operand to encode the first operand.  */
11128
0
    exp = &im_expressions[i.imm_operands++];
11129
0
    i.op[i.operands].imms = exp;
11130
0
    i.types[i.operands].bitfield.imm8 = 1;
11131
0
    i.operands++;
11132
11133
0
    exp->X_op = O_constant;
11134
0
  }
11135
0
      else
11136
0
  {
11137
0
    gas_assert (i.imm_operands == 1);
11138
0
    gas_assert (fits_in_imm4 (i.op[0].imms->X_add_number));
11139
0
    gas_assert (!i.tm.opcode_modifier.immext);
11140
11141
    /* Turn on Imm8 again so that output_imm will generate it.  */
11142
0
    i.types[0].bitfield.imm8 = 1;
11143
11144
0
    exp = i.op[0].imms;
11145
0
  }
11146
0
      exp->X_add_number |= register_number (i.op[reg_slot].regs)
11147
0
         << (3 + !(i.tm.opcode_modifier.evex
11148
0
             || pp.encoding == encoding_evex));
11149
0
    }
11150
11151
0
  switch (i.tm.opcode_modifier.vexvvvv)
11152
0
    {
11153
    /* VEX.vvvv encodes the last source register operand.  */
11154
0
    case VexVVVV_SRC2:
11155
0
      v = source++;
11156
0
      break;
11157
    /* VEX.vvvv encodes the first source register operand.  */
11158
0
    case VexVVVV_SRC1:
11159
0
      v =  dest - 1;
11160
0
      break;
11161
    /* VEX.vvvv encodes the destination register operand.  */
11162
0
    case VexVVVV_DST:
11163
0
      v = dest--;
11164
0
      break;
11165
0
    default:
11166
0
      v = ~0;
11167
0
      break;
11168
0
     }
11169
11170
0
  if (dest == source)
11171
0
    dest = ~0;
11172
11173
0
  gas_assert (source < dest);
11174
11175
0
  if (v < MAX_OPERANDS)
11176
0
    {
11177
0
      gas_assert (i.tm.opcode_modifier.vexvvvv);
11178
0
      i.vex.register_specifier = i.op[v].regs;
11179
0
    }
11180
11181
0
  if (op < i.operands)
11182
0
    {
11183
0
      if (i.mem_operands)
11184
0
  {
11185
0
    unsigned int fake_zero_displacement = 0;
11186
11187
0
    gas_assert (i.flags[op] & Operand_Mem);
11188
11189
0
    if (i.tm.opcode_modifier.sib)
11190
0
      {
11191
        /* The index register of VSIB shouldn't be RegIZ.  */
11192
0
        if (i.tm.opcode_modifier.sib != SIBMEM
11193
0
      && i.index_reg->reg_num == RegIZ)
11194
0
    abort ();
11195
11196
0
        i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
11197
0
        if (!i.base_reg)
11198
0
    {
11199
0
      i.sib.base = NO_BASE_REGISTER;
11200
0
      i.sib.scale = i.log2_scale_factor;
11201
0
      i.types[op] = operand_type_and_not (i.types[op], anydisp);
11202
0
      i.types[op].bitfield.disp32 = 1;
11203
0
    }
11204
11205
        /* Since the mandatory SIB always has index register, so
11206
     the code logic remains unchanged. The non-mandatory SIB
11207
     without index register is allowed and will be handled
11208
     later.  */
11209
0
        if (i.index_reg)
11210
0
    {
11211
0
      if (i.index_reg->reg_num == RegIZ)
11212
0
        i.sib.index = NO_INDEX_REGISTER;
11213
0
      else
11214
0
        i.sib.index = i.index_reg->reg_num;
11215
0
      set_rex_vrex (i.index_reg, REX_X, false);
11216
0
    }
11217
0
      }
11218
11219
0
    default_seg = reg_ds;
11220
11221
0
    if (i.base_reg == 0)
11222
0
      {
11223
0
        i.rm.mode = 0;
11224
0
        if (!i.disp_operands)
11225
0
    fake_zero_displacement = 1;
11226
0
        if (i.index_reg == 0)
11227
0
    {
11228
      /* Both check for VSIB and mandatory non-vector SIB. */
11229
0
      gas_assert (!i.tm.opcode_modifier.sib
11230
0
            || i.tm.opcode_modifier.sib == SIBMEM);
11231
      /* Operand is just <disp>  */
11232
0
      i.types[op] = operand_type_and_not (i.types[op], anydisp);
11233
0
      if (flag_code == CODE_64BIT)
11234
0
        {
11235
          /* 64bit mode overwrites the 32bit absolute
11236
       addressing by RIP relative addressing and
11237
       absolute addressing is encoded by one of the
11238
       redundant SIB forms.  */
11239
0
          i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
11240
0
          i.sib.base = NO_BASE_REGISTER;
11241
0
          i.sib.index = NO_INDEX_REGISTER;
11242
0
          i.types[op].bitfield.disp32 = 1;
11243
0
        }
11244
0
      else if ((flag_code == CODE_16BIT)
11245
0
         ^ (i.prefix[ADDR_PREFIX] != 0))
11246
0
        {
11247
0
          i.rm.regmem = NO_BASE_REGISTER_16;
11248
0
          i.types[op].bitfield.disp16 = 1;
11249
0
        }
11250
0
      else
11251
0
        {
11252
0
          i.rm.regmem = NO_BASE_REGISTER;
11253
0
          i.types[op].bitfield.disp32 = 1;
11254
0
        }
11255
0
    }
11256
0
        else if (!i.tm.opcode_modifier.sib)
11257
0
    {
11258
      /* !i.base_reg && i.index_reg  */
11259
0
      if (i.index_reg->reg_num == RegIZ)
11260
0
        i.sib.index = NO_INDEX_REGISTER;
11261
0
      else
11262
0
        i.sib.index = i.index_reg->reg_num;
11263
0
      i.sib.base = NO_BASE_REGISTER;
11264
0
      i.sib.scale = i.log2_scale_factor;
11265
0
      i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
11266
0
      i.types[op] = operand_type_and_not (i.types[op], anydisp);
11267
0
      i.types[op].bitfield.disp32 = 1;
11268
0
      set_rex_rex2 (i.index_reg, REX_X);
11269
0
    }
11270
0
      }
11271
    /* RIP addressing for 64bit mode.  */
11272
0
    else if (i.base_reg->reg_num == RegIP)
11273
0
      {
11274
0
        gas_assert (!i.tm.opcode_modifier.sib);
11275
0
        i.rm.regmem = NO_BASE_REGISTER;
11276
0
        i.types[op].bitfield.disp8 = 0;
11277
0
        i.types[op].bitfield.disp16 = 0;
11278
0
        i.types[op].bitfield.disp32 = 1;
11279
0
        i.types[op].bitfield.disp64 = 0;
11280
0
        i.flags[op] |= Operand_PCrel;
11281
0
        if (! i.disp_operands)
11282
0
    fake_zero_displacement = 1;
11283
0
      }
11284
0
    else if (i.base_reg->reg_type.bitfield.word)
11285
0
      {
11286
0
        gas_assert (!i.tm.opcode_modifier.sib);
11287
0
        switch (i.base_reg->reg_num)
11288
0
    {
11289
0
    case 3: /* (%bx)  */
11290
0
      if (i.index_reg == 0)
11291
0
        i.rm.regmem = 7;
11292
0
      else /* (%bx,%si) -> 0, or (%bx,%di) -> 1  */
11293
0
        i.rm.regmem = i.index_reg->reg_num - 6;
11294
0
      break;
11295
0
    case 5: /* (%bp)  */
11296
0
      default_seg = reg_ss;
11297
0
      if (i.index_reg == 0)
11298
0
        {
11299
0
          i.rm.regmem = 6;
11300
0
          if (operand_type_check (i.types[op], disp) == 0)
11301
0
      {
11302
        /* fake (%bp) into 0(%bp)  */
11303
0
        if (pp.disp_encoding == disp_encoding_16bit)
11304
0
          i.types[op].bitfield.disp16 = 1;
11305
0
        else
11306
0
          i.types[op].bitfield.disp8 = 1;
11307
0
        fake_zero_displacement = 1;
11308
0
      }
11309
0
        }
11310
0
      else /* (%bp,%si) -> 2, or (%bp,%di) -> 3  */
11311
0
        i.rm.regmem = i.index_reg->reg_num - 6 + 2;
11312
0
      break;
11313
0
    default: /* (%si) -> 4 or (%di) -> 5  */
11314
0
      i.rm.regmem = i.base_reg->reg_num - 6 + 4;
11315
0
    }
11316
0
        if (!fake_zero_displacement
11317
0
      && !i.disp_operands
11318
0
      && pp.disp_encoding)
11319
0
    {
11320
0
      fake_zero_displacement = 1;
11321
0
      if (pp.disp_encoding == disp_encoding_8bit)
11322
0
        i.types[op].bitfield.disp8 = 1;
11323
0
      else
11324
0
        i.types[op].bitfield.disp16 = 1;
11325
0
    }
11326
0
        i.rm.mode = mode_from_disp_size (i.types[op]);
11327
0
      }
11328
0
    else /* i.base_reg and 32/64 bit mode  */
11329
0
      {
11330
0
        if (operand_type_check (i.types[op], disp))
11331
0
    {
11332
0
      i.types[op].bitfield.disp16 = 0;
11333
0
      i.types[op].bitfield.disp64 = 0;
11334
0
      i.types[op].bitfield.disp32 = 1;
11335
0
    }
11336
11337
0
        if (!i.tm.opcode_modifier.sib)
11338
0
    i.rm.regmem = i.base_reg->reg_num;
11339
0
        set_rex_rex2 (i.base_reg, REX_B);
11340
0
        i.sib.base = i.base_reg->reg_num;
11341
        /* x86-64 ignores REX prefix bit here to avoid decoder
11342
     complications.  */
11343
0
        if (!(i.base_reg->reg_flags & RegRex)
11344
0
      && (i.base_reg->reg_num == EBP_REG_NUM
11345
0
       || i.base_reg->reg_num == ESP_REG_NUM))
11346
0
      default_seg = reg_ss;
11347
0
        if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
11348
0
    {
11349
0
      fake_zero_displacement = 1;
11350
0
      if (pp.disp_encoding == disp_encoding_32bit)
11351
0
        i.types[op].bitfield.disp32 = 1;
11352
0
      else
11353
0
        i.types[op].bitfield.disp8 = 1;
11354
0
    }
11355
0
        i.sib.scale = i.log2_scale_factor;
11356
0
        if (i.index_reg == 0)
11357
0
    {
11358
      /* Only check for VSIB. */
11359
0
      gas_assert (i.tm.opcode_modifier.sib != VECSIB128
11360
0
            && i.tm.opcode_modifier.sib != VECSIB256
11361
0
            && i.tm.opcode_modifier.sib != VECSIB512);
11362
11363
      /* <disp>(%esp) becomes two byte modrm with no index
11364
         register.  We've already stored the code for esp
11365
         in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
11366
         Any base register besides %esp will not use the
11367
         extra modrm byte.  */
11368
0
      i.sib.index = NO_INDEX_REGISTER;
11369
0
    }
11370
0
        else if (!i.tm.opcode_modifier.sib)
11371
0
    {
11372
0
      if (i.index_reg->reg_num == RegIZ)
11373
0
        i.sib.index = NO_INDEX_REGISTER;
11374
0
      else
11375
0
        i.sib.index = i.index_reg->reg_num;
11376
0
      i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
11377
0
      set_rex_rex2 (i.index_reg, REX_X);
11378
0
    }
11379
11380
0
        if (i.disp_operands
11381
0
      && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
11382
0
          || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
11383
0
    i.rm.mode = 0;
11384
0
        else
11385
0
    {
11386
0
      if (!fake_zero_displacement
11387
0
          && !i.disp_operands
11388
0
          && pp.disp_encoding)
11389
0
        {
11390
0
          fake_zero_displacement = 1;
11391
0
          if (pp.disp_encoding == disp_encoding_8bit)
11392
0
      i.types[op].bitfield.disp8 = 1;
11393
0
          else
11394
0
      i.types[op].bitfield.disp32 = 1;
11395
0
        }
11396
0
      i.rm.mode = mode_from_disp_size (i.types[op]);
11397
0
    }
11398
0
      }
11399
11400
0
    if (fake_zero_displacement)
11401
0
      {
11402
        /* Fakes a zero displacement assuming that i.types[op]
11403
     holds the correct displacement size.  */
11404
0
        expressionS *exp;
11405
11406
0
        gas_assert (i.op[op].disps == 0);
11407
0
        exp = &disp_expressions[i.disp_operands++];
11408
0
        i.op[op].disps = exp;
11409
0
        exp->X_op = O_constant;
11410
0
        exp->X_add_number = 0;
11411
0
        exp->X_add_symbol = (symbolS *) 0;
11412
0
        exp->X_op_symbol = (symbolS *) 0;
11413
0
      }
11414
0
  }
11415
0
    else
11416
0
  {
11417
0
      i.rm.mode = 3;
11418
0
      i.rm.regmem = i.op[op].regs->reg_num;
11419
0
      set_rex_vrex (i.op[op].regs, REX_B, false);
11420
0
  }
11421
11422
0
      if (op == dest)
11423
0
  dest = ~0;
11424
0
      if (op == source)
11425
0
  source = ~0;
11426
0
    }
11427
0
  else
11428
0
    {
11429
0
      i.rm.mode = 3;
11430
0
      if (!i.tm.opcode_modifier.regmem)
11431
0
  {
11432
0
    gas_assert (source < MAX_OPERANDS);
11433
0
    i.rm.regmem = i.op[source].regs->reg_num;
11434
0
    set_rex_vrex (i.op[source].regs, REX_B,
11435
0
      dest >= MAX_OPERANDS && i.tm.opcode_modifier.sse2avx);
11436
0
    source = ~0;
11437
0
  }
11438
0
      else
11439
0
  {
11440
0
    gas_assert (dest < MAX_OPERANDS);
11441
0
    i.rm.regmem = i.op[dest].regs->reg_num;
11442
0
    set_rex_vrex (i.op[dest].regs, REX_B, i.tm.opcode_modifier.sse2avx);
11443
0
    dest = ~0;
11444
0
  }
11445
0
    }
11446
11447
  /* Fill in i.rm.reg field with extension opcode (if any) or the
11448
     appropriate register.  */
11449
0
  if (i.tm.extension_opcode != None)
11450
0
    i.rm.reg = i.tm.extension_opcode;
11451
0
  else if (!i.tm.opcode_modifier.regmem && dest < MAX_OPERANDS)
11452
0
    {
11453
0
      i.rm.reg = i.op[dest].regs->reg_num;
11454
0
      set_rex_vrex (i.op[dest].regs, REX_R, i.tm.opcode_modifier.sse2avx);
11455
0
    }
11456
0
  else
11457
0
    {
11458
0
      gas_assert (source < MAX_OPERANDS);
11459
0
      i.rm.reg = i.op[source].regs->reg_num;
11460
0
      set_rex_vrex (i.op[source].regs, REX_R, false);
11461
0
    }
11462
11463
0
  if (flag_code != CODE_64BIT && (i.rex & REX_R))
11464
0
    {
11465
0
      gas_assert (i.types[!i.tm.opcode_modifier.regmem].bitfield.class == RegCR);
11466
0
      i.rex &= ~REX_R;
11467
0
      add_prefix (LOCK_PREFIX_OPCODE);
11468
0
    }
11469
11470
0
  return default_seg;
11471
0
}
11472
11473
static INLINE void
11474
frag_opcode_byte (unsigned char byte)
11475
0
{
11476
0
  if (now_seg != absolute_section)
11477
0
    FRAG_APPEND_1_CHAR (byte);
11478
0
  else
11479
0
    ++abs_section_offset;
11480
0
}
11481
11482
static unsigned int
11483
flip_code16 (unsigned int code16)
11484
0
{
11485
0
  gas_assert (i.tm.operands == 1);
11486
11487
0
  return !(i.prefix[REX_PREFIX] & REX_W)
11488
0
   && (code16 ? i.tm.operand_types[0].bitfield.disp32
11489
0
        : i.tm.operand_types[0].bitfield.disp16)
11490
0
   ? CODE16 : 0;
11491
0
}
11492
11493
static void
11494
output_branch (void)
11495
0
{
11496
0
  char *p;
11497
0
  int size;
11498
0
  int code16;
11499
0
  int prefix;
11500
0
  relax_substateT subtype;
11501
0
  symbolS *sym;
11502
0
  offsetT off;
11503
11504
0
  if (now_seg == absolute_section)
11505
0
    {
11506
0
      as_bad (_("relaxable branches not supported in absolute section"));
11507
0
      return;
11508
0
    }
11509
11510
0
  code16 = flag_code == CODE_16BIT ? CODE16 : 0;
11511
0
  size = pp.disp_encoding > disp_encoding_8bit ? BIG : SMALL;
11512
11513
0
  prefix = 0;
11514
0
  if (i.prefix[DATA_PREFIX] != 0)
11515
0
    {
11516
0
      prefix = 1;
11517
0
      i.prefixes -= 1;
11518
0
      code16 ^= flip_code16(code16);
11519
0
    }
11520
  /* Pentium4 branch hints.  */
11521
0
  if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
11522
0
      || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
11523
0
    {
11524
0
      prefix++;
11525
0
      i.prefixes--;
11526
0
    }
11527
0
  if (i.prefix[REX_PREFIX] != 0)
11528
0
    {
11529
0
      prefix++;
11530
0
      i.prefixes--;
11531
0
    }
11532
11533
  /* BND prefixed jump.  */
11534
0
  if (i.prefix[BND_PREFIX] != 0)
11535
0
    {
11536
0
      prefix++;
11537
0
      i.prefixes--;
11538
0
    }
11539
11540
0
  if (i.prefixes != 0)
11541
0
    as_warn (_("skipping prefixes on `%s'"), insn_name (&i.tm));
11542
11543
  /* It's always a symbol;  End frag & setup for relax.
11544
     Make sure there is enough room in this frag for the largest
11545
     instruction we may generate in md_convert_frag.  This is 2
11546
     bytes for the opcode and room for the prefix and largest
11547
     displacement.  */
11548
0
  frag_grow (prefix + 2 + 4);
11549
  /* Prefix and 1 opcode byte go in fr_fix.  */
11550
0
  p = frag_more (prefix + 1);
11551
0
  if (i.prefix[DATA_PREFIX] != 0)
11552
0
    *p++ = DATA_PREFIX_OPCODE;
11553
0
  if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
11554
0
      || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
11555
0
    *p++ = i.prefix[SEG_PREFIX];
11556
0
  if (i.prefix[BND_PREFIX] != 0)
11557
0
    *p++ = BND_PREFIX_OPCODE;
11558
0
  if (i.prefix[REX_PREFIX] != 0)
11559
0
    *p++ = i.prefix[REX_PREFIX];
11560
0
  *p = i.tm.base_opcode;
11561
11562
0
  if ((unsigned char) *p == JUMP_PC_RELATIVE)
11563
0
    subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
11564
0
  else if (cpu_arch_flags.bitfield.cpui386)
11565
0
    subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
11566
0
  else
11567
0
    subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
11568
0
  subtype |= code16;
11569
11570
0
  sym = i.op[0].disps->X_add_symbol;
11571
0
  off = i.op[0].disps->X_add_number;
11572
11573
0
  if (i.op[0].disps->X_op != O_constant
11574
0
      && i.op[0].disps->X_op != O_symbol)
11575
0
    {
11576
      /* Handle complex expressions.  */
11577
0
      sym = make_expr_symbol (i.op[0].disps);
11578
0
      off = 0;
11579
0
    }
11580
11581
  /* 1 possible extra opcode + 4 byte displacement go in var part.
11582
     Pass reloc in fr_var.  */
11583
0
  frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
11584
0
}
11585
11586
/* PLT32 relocation is ELF only.  */
11587
#ifdef OBJ_ELF
11588
/* Return TRUE iff PLT32 relocation should be used for branching to
11589
   symbol S.  */
11590
11591
static bool
11592
need_plt32_p (symbolS *s)
11593
0
{
11594
#ifdef TE_SOLARIS
11595
  /* Don't emit PLT32 relocation on Solaris: neither native linker nor
11596
     krtld support it.  */
11597
  return false;
11598
#endif
11599
11600
  /* Since there is no need to prepare for PLT branch on x86-64, we
11601
     can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
11602
     be used as a marker for 32-bit PC-relative branches.  */
11603
0
  if (!object_64bit)
11604
0
    return false;
11605
11606
0
  if (s == NULL)
11607
0
    return false;
11608
11609
  /* Weak or undefined symbol need PLT32 relocation.  */
11610
0
  if (S_IS_WEAK (s) || !S_IS_DEFINED (s))
11611
0
    return true;
11612
11613
  /* Non-global symbol doesn't need PLT32 relocation.  */
11614
0
  if (! S_IS_EXTERNAL (s))
11615
0
    return false;
11616
11617
  /* Other global symbols need PLT32 relocation.  NB: Symbol with
11618
     non-default visibilities are treated as normal global symbol
11619
     so that PLT32 relocation can be used as a marker for 32-bit
11620
     PC-relative branches.  It is useful for linker relaxation.  */
11621
0
  return true;
11622
0
}
11623
#endif
11624
11625
static void
11626
output_jump (void)
11627
0
{
11628
0
  char *p;
11629
0
  int size;
11630
0
  fixS *fixP;
11631
0
  bfd_reloc_code_real_type jump_reloc = i.reloc[0];
11632
11633
0
  if (i.tm.opcode_modifier.jump == JUMP_BYTE)
11634
0
    {
11635
      /* This is a loop or jecxz type instruction.  */
11636
0
      size = 1;
11637
0
      if (i.prefix[ADDR_PREFIX] != 0)
11638
0
  {
11639
0
    frag_opcode_byte (ADDR_PREFIX_OPCODE);
11640
0
    i.prefixes -= 1;
11641
0
  }
11642
      /* Pentium4 branch hints.  */
11643
0
      if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
11644
0
    || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
11645
0
  {
11646
0
    frag_opcode_byte (i.prefix[SEG_PREFIX]);
11647
0
    i.prefixes--;
11648
0
  }
11649
0
    }
11650
0
  else
11651
0
    {
11652
0
      int code16;
11653
11654
0
      code16 = 0;
11655
0
      if (flag_code == CODE_16BIT)
11656
0
  code16 = CODE16;
11657
11658
0
      if (i.prefix[DATA_PREFIX] != 0)
11659
0
  {
11660
0
    frag_opcode_byte (DATA_PREFIX_OPCODE);
11661
0
    i.prefixes -= 1;
11662
0
    code16 ^= flip_code16(code16);
11663
0
  }
11664
11665
0
      size = 4;
11666
0
      if (code16)
11667
0
  size = 2;
11668
0
    }
11669
11670
  /* BND prefixed jump.  */
11671
0
  if (i.prefix[BND_PREFIX] != 0)
11672
0
    {
11673
0
      frag_opcode_byte (i.prefix[BND_PREFIX]);
11674
0
      i.prefixes -= 1;
11675
0
    }
11676
11677
0
  if (i.prefix[REX_PREFIX] != 0)
11678
0
    {
11679
0
      frag_opcode_byte (i.prefix[REX_PREFIX]);
11680
0
      i.prefixes -= 1;
11681
0
    }
11682
11683
0
  if (i.prefixes != 0)
11684
0
    as_warn (_("skipping prefixes on `%s'"), insn_name (&i.tm));
11685
11686
0
  if (now_seg == absolute_section)
11687
0
    {
11688
0
      abs_section_offset += i.opcode_length + size;
11689
0
      return;
11690
0
    }
11691
11692
0
  p = frag_more (i.opcode_length + size);
11693
0
  switch (i.opcode_length)
11694
0
    {
11695
0
    case 2:
11696
0
      *p++ = i.tm.base_opcode >> 8;
11697
      /* Fall through.  */
11698
0
    case 1:
11699
0
      *p++ = i.tm.base_opcode;
11700
0
      break;
11701
0
    default:
11702
0
      abort ();
11703
0
    }
11704
11705
0
#ifdef OBJ_ELF
11706
0
  if (flag_code == CODE_64BIT && size == 4
11707
0
      && jump_reloc == NO_RELOC && i.op[0].disps->X_add_number == 0
11708
0
      && need_plt32_p (i.op[0].disps->X_add_symbol))
11709
0
    jump_reloc = BFD_RELOC_X86_64_PLT32;
11710
0
#endif
11711
11712
0
  jump_reloc = reloc (size, 1, 1, jump_reloc);
11713
11714
0
  fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
11715
0
          i.op[0].disps, 1, jump_reloc);
11716
11717
  /* All jumps handled here are signed, but don't unconditionally use a
11718
     signed limit check for 32 and 16 bit jumps as we want to allow wrap
11719
     around at 4G (outside of 64-bit mode) and 64k (except for XBEGIN)
11720
     respectively.  */
11721
0
  switch (size)
11722
0
    {
11723
0
    case 1:
11724
0
      fixP->fx_signed = 1;
11725
0
      break;
11726
11727
0
    case 2:
11728
0
      if (i.tm.mnem_off == MN_xbegin)
11729
0
  fixP->fx_signed = 1;
11730
0
      break;
11731
11732
0
    case 4:
11733
0
      if (flag_code == CODE_64BIT)
11734
0
  fixP->fx_signed = 1;
11735
0
      break;
11736
0
    }
11737
0
}
11738
11739
static void
11740
output_interseg_jump (void)
11741
0
{
11742
0
  char *p;
11743
0
  int size;
11744
0
  int prefix;
11745
0
  int code16;
11746
11747
0
  code16 = 0;
11748
0
  if (flag_code == CODE_16BIT)
11749
0
    code16 = CODE16;
11750
11751
0
  prefix = 0;
11752
0
  if (i.prefix[DATA_PREFIX] != 0)
11753
0
    {
11754
0
      prefix = 1;
11755
0
      i.prefixes -= 1;
11756
0
      code16 ^= CODE16;
11757
0
    }
11758
11759
0
  gas_assert (!i.prefix[REX_PREFIX]);
11760
11761
0
  size = 4;
11762
0
  if (code16)
11763
0
    size = 2;
11764
11765
0
  if (i.prefixes != 0)
11766
0
    as_warn (_("skipping prefixes on `%s'"), insn_name (&i.tm));
11767
11768
0
  if (now_seg == absolute_section)
11769
0
    {
11770
0
      abs_section_offset += prefix + 1 + 2 + size;
11771
0
      return;
11772
0
    }
11773
11774
  /* 1 opcode; 2 segment; offset  */
11775
0
  p = frag_more (prefix + 1 + 2 + size);
11776
11777
0
  if (i.prefix[DATA_PREFIX] != 0)
11778
0
    *p++ = DATA_PREFIX_OPCODE;
11779
11780
0
  if (i.prefix[REX_PREFIX] != 0)
11781
0
    *p++ = i.prefix[REX_PREFIX];
11782
11783
0
  *p++ = i.tm.base_opcode;
11784
0
  if (i.op[1].imms->X_op == O_constant)
11785
0
    {
11786
0
      offsetT n = i.op[1].imms->X_add_number;
11787
11788
0
      if (size == 2
11789
0
    && !fits_in_unsigned_word (n)
11790
0
    && !fits_in_signed_word (n))
11791
0
  {
11792
0
    as_bad (_("16-bit jump out of range"));
11793
0
    return;
11794
0
  }
11795
0
      md_number_to_chars (p, n, size);
11796
0
    }
11797
0
  else
11798
0
    fix_new_exp (frag_now, p - frag_now->fr_literal, size,
11799
0
     i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
11800
11801
0
  p += size;
11802
0
  if (i.op[0].imms->X_op == O_constant)
11803
0
    md_number_to_chars (p, (valueT) i.op[0].imms->X_add_number, 2);
11804
0
  else
11805
0
    fix_new_exp (frag_now, p - frag_now->fr_literal, 2,
11806
0
     i.op[0].imms, 0, reloc (2, 0, 0, i.reloc[0]));
11807
0
}
11808
11809
/* Hook used to reject pseudo-prefixes misplaced at the start of a line.  */
11810
11811
void i386_start_line (void)
11812
0
{
11813
0
  struct pseudo_prefixes last_pp;
11814
11815
0
  memcpy (&last_pp, &pp, sizeof (pp));
11816
0
  memset (&pp, 0, sizeof (pp));
11817
0
  if (memcmp (&pp, &last_pp, sizeof (pp)))
11818
0
    as_bad_where (frag_now->fr_file, frag_now->fr_line,
11819
0
      _("pseudo prefix without instruction"));
11820
0
}
11821
11822
/* Hook used to warn about pseudo-prefixes ahead of a label.  */
11823
11824
bool i386_check_label (void)
11825
0
{
11826
0
  struct pseudo_prefixes last_pp;
11827
11828
0
  memcpy (&last_pp, &pp, sizeof (pp));
11829
0
  memset (&pp, 0, sizeof (pp));
11830
0
  if (memcmp (&pp, &last_pp, sizeof (pp)))
11831
0
    as_warn (_("pseudo prefix ahead of label; ignoring"));
11832
0
  return true;
11833
0
}
11834
11835
/* Hook used to parse pseudo-prefixes off of the start of a line.  */
11836
11837
int
11838
i386_unrecognized_line (int ch)
11839
0
{
11840
0
  char mnemonic[MAX_MNEM_SIZE];
11841
0
  const char *end;
11842
11843
0
  if (ch != '{')
11844
0
    return 0;
11845
11846
0
  --input_line_pointer;
11847
0
  know (*input_line_pointer == ch);
11848
11849
0
  end = parse_insn (input_line_pointer, mnemonic, parse_pseudo_prefix);
11850
0
  if (end == NULL)
11851
0
    {
11852
      /* Diagnostic was already issued.  */
11853
0
      ignore_rest_of_line ();
11854
0
      memset (&pp, 0, sizeof (pp));
11855
0
      return 1;
11856
0
    }
11857
11858
0
  if (end == input_line_pointer)
11859
0
    {
11860
0
      ++input_line_pointer;
11861
0
      return 0;
11862
0
    }
11863
11864
0
  input_line_pointer += end - input_line_pointer;
11865
0
  return 1;
11866
0
}
11867
11868
#ifdef OBJ_ELF
11869
void
11870
x86_cleanup (void)
11871
0
{
11872
0
  char *p;
11873
0
  asection *seg = now_seg;
11874
0
  subsegT subseg = now_subseg;
11875
0
  asection *sec;
11876
0
  unsigned int alignment, align_size_1;
11877
0
  unsigned int isa_1_descsz, feature_2_descsz, descsz;
11878
0
  unsigned int isa_1_descsz_raw, feature_2_descsz_raw;
11879
0
  unsigned int padding;
11880
11881
0
  if (!x86_used_note)
11882
0
    return;
11883
11884
0
  x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_X86;
11885
11886
  /* The .note.gnu.property section layout:
11887
11888
     Field  Length    Contents
11889
     ---- ----    ----
11890
     n_namsz  4   4
11891
     n_descsz 4   The note descriptor size
11892
     n_type 4   NT_GNU_PROPERTY_TYPE_0
11893
     n_name 4   "GNU"
11894
     n_desc n_descsz  The program property array
11895
     .... ....    ....
11896
   */
11897
11898
  /* Create the .note.gnu.property section.  */
11899
0
  sec = subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME, 0);
11900
0
  bfd_set_section_flags (sec,
11901
0
       (SEC_ALLOC
11902
0
        | SEC_LOAD
11903
0
        | SEC_DATA
11904
0
        | SEC_HAS_CONTENTS
11905
0
        | SEC_READONLY));
11906
11907
0
  if (get_elf_backend_data (stdoutput)->s->elfclass == ELFCLASS64)
11908
0
    {
11909
0
      align_size_1 = 7;
11910
0
      alignment = 3;
11911
0
    }
11912
0
  else
11913
0
    {
11914
0
      align_size_1 = 3;
11915
0
      alignment = 2;
11916
0
    }
11917
11918
0
  bfd_set_section_alignment (sec, alignment);
11919
0
  elf_section_type (sec) = SHT_NOTE;
11920
11921
  /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size
11922
          + 4-byte data  */
11923
0
  isa_1_descsz_raw = 4 + 4 + 4;
11924
  /* Align GNU_PROPERTY_X86_ISA_1_USED.  */
11925
0
  isa_1_descsz = (isa_1_descsz_raw + align_size_1) & ~align_size_1;
11926
11927
0
  feature_2_descsz_raw = isa_1_descsz;
11928
  /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size
11929
              + 4-byte data  */
11930
0
  feature_2_descsz_raw += 4 + 4 + 4;
11931
  /* Align GNU_PROPERTY_X86_FEATURE_2_USED.  */
11932
0
  feature_2_descsz = ((feature_2_descsz_raw + align_size_1)
11933
0
          & ~align_size_1);
11934
11935
0
  descsz = feature_2_descsz;
11936
  /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz.  */
11937
0
  p = frag_more (4 + 4 + 4 + 4 + descsz);
11938
11939
  /* Write n_namsz.  */
11940
0
  md_number_to_chars (p, (valueT) 4, 4);
11941
11942
  /* Write n_descsz.  */
11943
0
  md_number_to_chars (p + 4, (valueT) descsz, 4);
11944
11945
  /* Write n_type.  */
11946
0
  md_number_to_chars (p + 4 * 2, (valueT) NT_GNU_PROPERTY_TYPE_0, 4);
11947
11948
  /* Write n_name.  */
11949
0
  memcpy (p + 4 * 3, "GNU", 4);
11950
11951
  /* Write 4-byte type.  */
11952
0
  md_number_to_chars (p + 4 * 4,
11953
0
          (valueT) GNU_PROPERTY_X86_ISA_1_USED, 4);
11954
11955
  /* Write 4-byte data size.  */
11956
0
  md_number_to_chars (p + 4 * 5, (valueT) 4, 4);
11957
11958
  /* Write 4-byte data.  */
11959
0
  md_number_to_chars (p + 4 * 6, (valueT) x86_isa_1_used, 4);
11960
11961
  /* Zero out paddings.  */
11962
0
  padding = isa_1_descsz - isa_1_descsz_raw;
11963
0
  if (padding)
11964
0
    memset (p + 4 * 7, 0, padding);
11965
11966
  /* Write 4-byte type.  */
11967
0
  md_number_to_chars (p + isa_1_descsz + 4 * 4,
11968
0
          (valueT) GNU_PROPERTY_X86_FEATURE_2_USED, 4);
11969
11970
  /* Write 4-byte data size.  */
11971
0
  md_number_to_chars (p + isa_1_descsz + 4 * 5, (valueT) 4, 4);
11972
11973
  /* Write 4-byte data.  */
11974
0
  md_number_to_chars (p + isa_1_descsz + 4 * 6,
11975
0
          (valueT) x86_feature_2_used, 4);
11976
11977
  /* Zero out paddings.  */
11978
0
  padding = feature_2_descsz - feature_2_descsz_raw;
11979
0
  if (padding)
11980
0
    memset (p + isa_1_descsz + 4 * 7, 0, padding);
11981
11982
  /* We probably can't restore the current segment, for there likely
11983
     isn't one yet...  */
11984
0
  if (seg && subseg)
11985
0
    subseg_set (seg, subseg);
11986
0
}
11987
11988
#include "tc-i386-ginsn.c"
11989
11990
/* Whether SFrame stack trace info is supported.  */
11991
bool
11992
x86_support_sframe_p (void)
11993
0
{
11994
  /* At this time, SFrame stack trace is supported for AMD64 ABI only.  */
11995
0
  return (x86_elf_abi == X86_64_ABI);
11996
0
}
11997
11998
/* Whether SFrame return address tracking is needed.  */
11999
bool
12000
x86_sframe_ra_tracking_p (void)
12001
0
{
12002
  /* In AMD64, return address is always stored on the stack at a fixed offset
12003
     from the CFA (provided via x86_sframe_cfa_ra_offset ()).
12004
     Do not track explicitly via an SFrame Frame Row Entry.  */
12005
0
  return false;
12006
0
}
12007
12008
/* The fixed offset from CFA for SFrame to recover the return address.
12009
   (useful only when SFrame RA tracking is not needed).  */
12010
offsetT
12011
x86_sframe_cfa_ra_offset (void)
12012
0
{
12013
0
  gas_assert (x86_elf_abi == X86_64_ABI);
12014
0
  return (offsetT) -8;
12015
0
}
12016
12017
/* The abi/arch identifier for SFrame.  */
12018
unsigned char
12019
x86_sframe_get_abi_arch (void)
12020
0
{
12021
0
  unsigned char sframe_abi_arch = 0;
12022
12023
0
  if (x86_support_sframe_p ())
12024
0
    {
12025
0
      gas_assert (!target_big_endian);
12026
0
      sframe_abi_arch = SFRAME_ABI_AMD64_ENDIAN_LITTLE;
12027
0
    }
12028
12029
0
  return sframe_abi_arch;
12030
0
}
12031
12032
#endif
12033
12034
static unsigned int
12035
encoding_length (const fragS *start_frag, offsetT start_off,
12036
     const char *frag_now_ptr)
12037
0
{
12038
0
  unsigned int len = 0;
12039
12040
0
  if (start_frag != frag_now)
12041
0
    {
12042
0
      const fragS *fr = start_frag;
12043
12044
0
      do {
12045
0
  len += fr->fr_fix;
12046
0
  fr = fr->fr_next;
12047
0
      } while (fr && fr != frag_now);
12048
0
    }
12049
12050
0
  return len - start_off + (frag_now_ptr - frag_now->fr_literal);
12051
0
}
12052
12053
/* Return 1 for test, and, cmp, add, sub, inc and dec which may
12054
   be macro-fused with conditional jumps.
12055
   NB: If TEST/AND/CMP/ADD/SUB/INC/DEC is of RIP relative address,
12056
   or is one of the following format:
12057
12058
    cmp m, imm
12059
    add m, imm
12060
    sub m, imm
12061
   test m, imm
12062
    and m, imm
12063
    inc m
12064
    dec m
12065
12066
   it is unfusible.  */
12067
12068
static int
12069
maybe_fused_with_jcc_p (enum mf_cmp_kind* mf_cmp_p)
12070
0
{
12071
  /* No RIP address.  */
12072
0
  if (i.base_reg && i.base_reg->reg_num == RegIP)
12073
0
    return 0;
12074
12075
  /* No opcodes outside of base encoding space.  */
12076
0
  if (i.tm.opcode_space != SPACE_BASE)
12077
0
    return 0;
12078
12079
  /* add, sub without add/sub m, imm.  */
12080
0
  if (i.tm.base_opcode <= 5
12081
0
      || (i.tm.base_opcode >= 0x28 && i.tm.base_opcode <= 0x2d)
12082
0
      || ((i.tm.base_opcode | 3) == 0x83
12083
0
    && (i.tm.extension_opcode == 0x5
12084
0
        || i.tm.extension_opcode == 0x0)))
12085
0
    {
12086
0
      *mf_cmp_p = mf_cmp_alu_cmp;
12087
0
      return !(i.mem_operands && i.imm_operands);
12088
0
    }
12089
12090
  /* and without and m, imm.  */
12091
0
  if ((i.tm.base_opcode >= 0x20 && i.tm.base_opcode <= 0x25)
12092
0
      || ((i.tm.base_opcode | 3) == 0x83
12093
0
    && i.tm.extension_opcode == 0x4))
12094
0
    {
12095
0
      *mf_cmp_p = mf_cmp_test_and;
12096
0
      return !(i.mem_operands && i.imm_operands);
12097
0
    }
12098
12099
  /* test without test m imm.  */
12100
0
  if ((i.tm.base_opcode | 1) == 0x85
12101
0
      || (i.tm.base_opcode | 1) == 0xa9
12102
0
      || ((i.tm.base_opcode | 1) == 0xf7
12103
0
    && i.tm.extension_opcode == 0))
12104
0
    {
12105
0
      *mf_cmp_p = mf_cmp_test_and;
12106
0
      return !(i.mem_operands && i.imm_operands);
12107
0
    }
12108
12109
  /* cmp without cmp m, imm.  */
12110
0
  if ((i.tm.base_opcode >= 0x38 && i.tm.base_opcode <= 0x3d)
12111
0
      || ((i.tm.base_opcode | 3) == 0x83
12112
0
    && (i.tm.extension_opcode == 0x7)))
12113
0
    {
12114
0
      *mf_cmp_p = mf_cmp_alu_cmp;
12115
0
      return !(i.mem_operands && i.imm_operands);
12116
0
    }
12117
12118
  /* inc, dec without inc/dec m.   */
12119
0
  if ((is_cpu (&i.tm, CpuNo64)
12120
0
       && (i.tm.base_opcode | 0xf) == 0x4f)
12121
0
      || ((i.tm.base_opcode | 1) == 0xff
12122
0
    && i.tm.extension_opcode <= 0x1))
12123
0
    {
12124
0
      *mf_cmp_p = mf_cmp_incdec;
12125
0
      return !i.mem_operands;
12126
0
    }
12127
12128
0
  return 0;
12129
0
}
12130
12131
/* Return 1 if a FUSED_JCC_PADDING frag should be generated.  */
12132
12133
static int
12134
add_fused_jcc_padding_frag_p (enum mf_cmp_kind *mf_cmp_p,
12135
            const struct last_insn *last_insn)
12136
0
{
12137
  /* NB: Don't work with COND_JUMP86 without i386.  */
12138
0
  if (!align_branch_power
12139
0
      || now_seg == absolute_section
12140
0
      || !cpu_arch_flags.bitfield.cpui386
12141
0
      || !(align_branch & align_branch_fused_bit))
12142
0
    return 0;
12143
12144
0
  if (maybe_fused_with_jcc_p (mf_cmp_p))
12145
0
    {
12146
0
      if (last_insn->kind == last_insn_other)
12147
0
  return 1;
12148
0
      if (flag_debug)
12149
0
  as_warn_where (last_insn->file, last_insn->line,
12150
0
           _("`%s` skips -malign-branch-boundary on `%s`"),
12151
0
           last_insn->name, insn_name (&i.tm));
12152
0
    }
12153
12154
0
  return 0;
12155
0
}
12156
12157
/* Return 1 if a BRANCH_PREFIX frag should be generated.  */
12158
12159
static int
12160
add_branch_prefix_frag_p (const struct last_insn *last_insn)
12161
0
{
12162
  /* NB: Don't work with COND_JUMP86 without i386.  Don't add prefix
12163
     to PadLock instructions since they include prefixes in opcode.  */
12164
0
  if (!align_branch_power
12165
0
      || !align_branch_prefix_size
12166
0
      || now_seg == absolute_section
12167
0
      || is_cpu (&i.tm, CpuPadLock)
12168
0
      || is_cpu (&i.tm, CpuPadLockRNG2)
12169
0
      || is_cpu (&i.tm, CpuPadLockPHE2)
12170
0
      || is_cpu (&i.tm, CpuPadLockXMODX)
12171
0
      || !cpu_arch_flags.bitfield.cpui386)
12172
0
    return 0;
12173
12174
  /* Don't add prefix if it is a prefix or there is no operand in case
12175
     that segment prefix is special.  */
12176
0
  if (!i.operands || i.tm.opcode_modifier.isprefix)
12177
0
    return 0;
12178
12179
0
  if (last_insn->kind == last_insn_other)
12180
0
    return 1;
12181
12182
0
  if (flag_debug)
12183
0
    as_warn_where (last_insn->file, last_insn->line,
12184
0
       _("`%s` skips -malign-branch-boundary on `%s`"),
12185
0
       last_insn->name, insn_name (&i.tm));
12186
12187
0
  return 0;
12188
0
}
12189
12190
/* Return 1 if a BRANCH_PADDING frag should be generated.  */
12191
12192
static int
12193
add_branch_padding_frag_p (enum align_branch_kind *branch_p,
12194
         enum mf_jcc_kind *mf_jcc_p,
12195
         const struct last_insn *last_insn)
12196
0
{
12197
0
  int add_padding;
12198
12199
  /* NB: Don't work with COND_JUMP86 without i386.  */
12200
0
  if (!align_branch_power
12201
0
      || now_seg == absolute_section
12202
0
      || !cpu_arch_flags.bitfield.cpui386
12203
0
      || i.tm.opcode_space != SPACE_BASE)
12204
0
    return 0;
12205
12206
0
  add_padding = 0;
12207
12208
  /* Check for jcc and direct jmp.  */
12209
0
  if (i.tm.opcode_modifier.jump == JUMP)
12210
0
    {
12211
0
      if (i.tm.base_opcode == JUMP_PC_RELATIVE)
12212
0
  {
12213
0
    *branch_p = align_branch_jmp;
12214
0
    add_padding = align_branch & align_branch_jmp_bit;
12215
0
  }
12216
0
      else
12217
0
  {
12218
    /* Because J<cc> and JN<cc> share same group in macro-fusible table,
12219
       igore the lowest bit.  */
12220
0
    *mf_jcc_p = (i.tm.base_opcode & 0x0e) >> 1;
12221
0
    *branch_p = align_branch_jcc;
12222
0
    if ((align_branch & align_branch_jcc_bit))
12223
0
      add_padding = 1;
12224
0
  }
12225
0
    }
12226
0
  else if ((i.tm.base_opcode | 1) == 0xc3)
12227
0
    {
12228
      /* Near ret.  */
12229
0
      *branch_p = align_branch_ret;
12230
0
      if ((align_branch & align_branch_ret_bit))
12231
0
  add_padding = 1;
12232
0
    }
12233
0
  else
12234
0
    {
12235
      /* Check for indirect jmp, direct and indirect calls.  */
12236
0
      if (i.tm.base_opcode == 0xe8)
12237
0
  {
12238
    /* Direct call.  */
12239
0
    *branch_p = align_branch_call;
12240
0
    if ((align_branch & align_branch_call_bit))
12241
0
      add_padding = 1;
12242
0
  }
12243
0
      else if (i.tm.base_opcode == 0xff
12244
0
         && (i.tm.extension_opcode == 2
12245
0
       || i.tm.extension_opcode == 4))
12246
0
  {
12247
    /* Indirect call and jmp.  */
12248
0
    *branch_p = align_branch_indirect;
12249
0
    if ((align_branch & align_branch_indirect_bit))
12250
0
      add_padding = 1;
12251
0
  }
12252
12253
0
      if (add_padding
12254
0
    && i.disp_operands
12255
0
    && tls_get_addr
12256
0
    && (i.op[0].disps->X_op == O_symbol
12257
0
        || (i.op[0].disps->X_op == O_subtract
12258
0
      && i.op[0].disps->X_op_symbol == GOT_symbol)))
12259
0
  {
12260
0
    symbolS *s = i.op[0].disps->X_add_symbol;
12261
    /* No padding to call to global or undefined tls_get_addr.  */
12262
0
    if ((S_IS_EXTERNAL (s) || !S_IS_DEFINED (s))
12263
0
        && strcmp (S_GET_NAME (s), tls_get_addr) == 0)
12264
0
      return 0;
12265
0
  }
12266
0
    }
12267
12268
0
  if (add_padding
12269
0
      && last_insn->kind != last_insn_other)
12270
0
    {
12271
0
      if (flag_debug)
12272
0
  as_warn_where (last_insn->file, last_insn->line,
12273
0
           _("`%s` skips -malign-branch-boundary on `%s`"),
12274
0
           last_insn->name, insn_name (&i.tm));
12275
0
      return 0;
12276
0
    }
12277
12278
0
  return add_padding;
12279
0
}
12280
12281
static void
12282
output_insn (const struct last_insn *last_insn)
12283
0
{
12284
0
  fragS *insn_start_frag;
12285
0
  offsetT insn_start_off;
12286
0
  fragS *fragP = NULL;
12287
0
  enum align_branch_kind branch = align_branch_none;
12288
  /* The initializer is arbitrary just to avoid uninitialized error.
12289
     it's actually either assigned in add_branch_padding_frag_p
12290
     or never be used.  */
12291
0
  enum mf_jcc_kind mf_jcc = mf_jcc_jo;
12292
12293
0
#ifdef OBJ_ELF
12294
0
  if (x86_used_note && now_seg != absolute_section)
12295
0
    {
12296
0
      unsigned int feature_2_used = 0;
12297
12298
0
      if ((i.xstate & xstate_tmm) == xstate_tmm
12299
0
    || is_cpu (&i.tm, CpuAMX_TILE))
12300
0
  feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_TMM;
12301
12302
0
      if (is_cpu (&i.tm, Cpu8087)
12303
0
    || is_cpu (&i.tm, Cpu287)
12304
0
    || is_cpu (&i.tm, Cpu387)
12305
0
    || is_cpu (&i.tm, Cpu687)
12306
0
    || is_cpu (&i.tm, CpuFISTTP))
12307
0
  feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_X87;
12308
12309
0
      if ((i.xstate & xstate_mmx)
12310
0
    || i.tm.mnem_off == MN_emms
12311
0
    || i.tm.mnem_off == MN_femms)
12312
0
  feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_MMX;
12313
12314
0
      if (i.index_reg)
12315
0
  {
12316
0
    if (i.index_reg->reg_type.bitfield.zmmword)
12317
0
      i.xstate |= xstate_zmm;
12318
0
    else if (i.index_reg->reg_type.bitfield.ymmword)
12319
0
      i.xstate |= xstate_ymm;
12320
0
    else if (i.index_reg->reg_type.bitfield.xmmword)
12321
0
      i.xstate |= xstate_xmm;
12322
0
  }
12323
12324
      /* vzeroall / vzeroupper */
12325
0
      if (i.tm.base_opcode == 0x77 && is_cpu (&i.tm, CpuAVX))
12326
0
  i.xstate |= xstate_ymm;
12327
12328
0
      if ((i.xstate & xstate_xmm)
12329
    /* ldmxcsr / stmxcsr / vldmxcsr / vstmxcsr */
12330
0
    || (i.tm.base_opcode == 0xae
12331
0
        && (is_cpu (&i.tm, CpuSSE)
12332
0
      || is_cpu (&i.tm, CpuAVX)))
12333
0
    || is_cpu (&i.tm, CpuWideKL)
12334
0
    || is_cpu (&i.tm, CpuKL))
12335
0
  feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XMM;
12336
12337
0
      if ((i.xstate & xstate_ymm) == xstate_ymm)
12338
0
  feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_YMM;
12339
0
      if ((i.xstate & xstate_zmm) == xstate_zmm)
12340
0
  feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_ZMM;
12341
0
      if (i.mask.reg || (i.xstate & xstate_mask) == xstate_mask)
12342
0
  feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_MASK;
12343
0
      if (is_cpu (&i.tm, CpuFXSR))
12344
0
  feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_FXSR;
12345
0
      if (is_cpu (&i.tm, CpuXsave))
12346
0
  feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XSAVE;
12347
0
      if (is_cpu (&i.tm, CpuXsaveopt))
12348
0
  feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT;
12349
0
      if (is_cpu (&i.tm, CpuXSAVEC))
12350
0
  feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XSAVEC;
12351
12352
0
      x86_feature_2_used |= feature_2_used;
12353
12354
0
      if (object_64bit
12355
0
    || (feature_2_used
12356
0
        & (GNU_PROPERTY_X86_FEATURE_2_XMM
12357
0
     | GNU_PROPERTY_X86_FEATURE_2_FXSR)) != 0
12358
0
    || is_cpu (&i.tm, CpuCMOV)
12359
0
    || is_cpu (&i.tm, CpuSYSCALL)
12360
0
    || i.tm.mnem_off == MN_cmpxchg8b)
12361
0
  x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_BASELINE;
12362
0
      if (is_cpu (&i.tm, CpuSSE3)
12363
0
    || is_cpu (&i.tm, CpuSSSE3)
12364
0
    || is_cpu (&i.tm, CpuSSE4_1)
12365
0
    || is_cpu (&i.tm, CpuSSE4_2)
12366
0
    || is_cpu (&i.tm, CpuCX16)
12367
0
    || is_cpu (&i.tm, CpuPOPCNT)
12368
    /* LAHF-SAHF insns in 64-bit mode.  */
12369
0
    || (flag_code == CODE_64BIT
12370
0
        && (i.tm.base_opcode | 1) == 0x9f
12371
0
        && i.tm.opcode_space == SPACE_BASE))
12372
0
  x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_V2;
12373
0
      if (is_cpu (&i.tm, CpuAVX)
12374
0
    || is_cpu (&i.tm, CpuAVX2)
12375
    /* Any VEX encoded insns execpt for AVX512F, AVX512BW, AVX512DQ,
12376
       XOP, FMA4, LPW, TBM, and AMX.  */
12377
0
    || (i.tm.opcode_modifier.vex
12378
0
        && !is_cpu (&i.tm, CpuAVX512F)
12379
0
        && !is_cpu (&i.tm, CpuAVX512BW)
12380
0
        && !is_cpu (&i.tm, CpuAVX512DQ)
12381
0
        && !is_cpu (&i.tm, CpuXOP)
12382
0
        && !is_cpu (&i.tm, CpuFMA4)
12383
0
        && !is_cpu (&i.tm, CpuLWP)
12384
0
        && !is_cpu (&i.tm, CpuTBM)
12385
0
        && !(feature_2_used & GNU_PROPERTY_X86_FEATURE_2_TMM))
12386
0
    || is_cpu (&i.tm, CpuLZCNT)
12387
0
    || is_cpu (&i.tm, CpuMovbe)
12388
0
    || is_cpu (&i.tm, CpuXSAVES)
12389
0
    || (feature_2_used
12390
0
        & (GNU_PROPERTY_X86_FEATURE_2_XSAVE
12391
0
     | GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
12392
0
     | GNU_PROPERTY_X86_FEATURE_2_XSAVEC)) != 0)
12393
0
  x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_V3;
12394
0
      if (is_cpu (&i.tm, CpuAVX512F)
12395
0
    || is_cpu (&i.tm, CpuAVX512BW)
12396
0
    || is_cpu (&i.tm, CpuAVX512DQ)
12397
0
    || is_cpu (&i.tm, CpuAVX512VL)
12398
    /* Any EVEX encoded insns except for AVX512ER, AVX512PF,
12399
       AVX512-4FMAPS, and AVX512-4VNNIW.  */
12400
0
    || (i.tm.opcode_modifier.evex
12401
0
        && !is_cpu (&i.tm, CpuAVX512ER)
12402
0
        && !is_cpu (&i.tm, CpuAVX512PF)
12403
0
        && !is_cpu (&i.tm, CpuAVX512_4FMAPS)
12404
0
        && !is_cpu (&i.tm, CpuAVX512_4VNNIW)))
12405
0
  x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_V4;
12406
0
    }
12407
0
#endif
12408
12409
  /* Tie dwarf2 debug info to the address at the start of the insn.
12410
     We can't do this after the insn has been output as the current
12411
     frag may have been closed off.  eg. by frag_var.  */
12412
0
  dwarf2_emit_insn (0);
12413
12414
0
  insn_start_frag = frag_now;
12415
0
  insn_start_off = frag_now_fix ();
12416
12417
0
  if (add_branch_padding_frag_p (&branch, &mf_jcc, last_insn))
12418
0
    {
12419
0
      char *p;
12420
      /* Branch can be 8 bytes.  Leave some room for prefixes.  */
12421
0
      unsigned int max_branch_padding_size = 14;
12422
12423
      /* Align section to boundary.  */
12424
0
      record_alignment (now_seg, align_branch_power);
12425
12426
      /* Make room for padding.  */
12427
0
      frag_grow (max_branch_padding_size);
12428
12429
      /* Start of the padding.  */
12430
0
      p = frag_more (0);
12431
12432
0
      fragP = frag_now;
12433
12434
0
      frag_var (rs_machine_dependent, max_branch_padding_size, 0,
12435
0
    ENCODE_RELAX_STATE (BRANCH_PADDING, 0),
12436
0
    NULL, 0, p);
12437
12438
0
      fragP->tc_frag_data.mf_type = mf_jcc;
12439
0
      fragP->tc_frag_data.branch_type = branch;
12440
0
      fragP->tc_frag_data.max_bytes = max_branch_padding_size;
12441
0
    }
12442
12443
0
  if (!cpu_arch_flags.bitfield.cpui386 && (flag_code != CODE_16BIT)
12444
0
      && !pre_386_16bit_warned)
12445
0
    {
12446
0
      as_warn (_("use .code16 to ensure correct addressing mode"));
12447
0
      pre_386_16bit_warned = true;
12448
0
    }
12449
12450
  /* Output jumps.  */
12451
0
  if (i.tm.opcode_modifier.jump == JUMP)
12452
0
    output_branch ();
12453
0
  else if (i.tm.opcode_modifier.jump == JUMP_BYTE
12454
0
     || i.tm.opcode_modifier.jump == JUMP_DWORD)
12455
0
    output_jump ();
12456
0
  else if (i.tm.opcode_modifier.jump == JUMP_INTERSEGMENT)
12457
0
    output_interseg_jump ();
12458
0
  else
12459
0
    {
12460
      /* Output normal instructions here.  */
12461
0
      char *p;
12462
0
      unsigned char *q;
12463
0
      unsigned int j;
12464
0
      enum mf_cmp_kind mf_cmp;
12465
12466
0
      if (avoid_fence
12467
0
    && (i.tm.base_opcode == 0xaee8
12468
0
        || i.tm.base_opcode == 0xaef0
12469
0
        || i.tm.base_opcode == 0xaef8))
12470
0
  {
12471
    /* Encode lfence, mfence, and sfence as
12472
       f0 83 04 24 00   lock addl $0x0, (%{re}sp).  */
12473
0
    if (flag_code == CODE_16BIT)
12474
0
      as_bad (_("Cannot convert `%s' in 16-bit mode"), insn_name (&i.tm));
12475
0
    else if (omit_lock_prefix)
12476
0
      as_bad (_("Cannot convert `%s' with `-momit-lock-prefix=yes' in effect"),
12477
0
        insn_name (&i.tm));
12478
0
    else if (now_seg != absolute_section)
12479
0
      {
12480
0
        offsetT val = 0x240483f0ULL;
12481
12482
0
        p = frag_more (5);
12483
0
        md_number_to_chars (p, val, 5);
12484
0
      }
12485
0
    else
12486
0
      abs_section_offset += 5;
12487
0
    return;
12488
0
  }
12489
12490
      /* Some processors fail on LOCK prefix. This options makes
12491
   assembler ignore LOCK prefix and serves as a workaround.  */
12492
0
      if (omit_lock_prefix)
12493
0
  {
12494
0
    if (i.tm.base_opcode == LOCK_PREFIX_OPCODE
12495
0
        && i.tm.opcode_modifier.isprefix)
12496
0
      return;
12497
0
    i.prefix[LOCK_PREFIX] = 0;
12498
0
  }
12499
12500
0
      if (branch)
12501
  /* Skip if this is a branch.  */
12502
0
  ;
12503
0
      else if (add_fused_jcc_padding_frag_p (&mf_cmp, last_insn))
12504
0
  {
12505
    /* Make room for padding.  */
12506
0
    frag_grow (MAX_FUSED_JCC_PADDING_SIZE);
12507
0
    p = frag_more (0);
12508
12509
0
    fragP = frag_now;
12510
12511
0
    frag_var (rs_machine_dependent, MAX_FUSED_JCC_PADDING_SIZE, 0,
12512
0
        ENCODE_RELAX_STATE (FUSED_JCC_PADDING, 0),
12513
0
        NULL, 0, p);
12514
12515
0
    fragP->tc_frag_data.mf_type = mf_cmp;
12516
0
    fragP->tc_frag_data.branch_type = align_branch_fused;
12517
0
    fragP->tc_frag_data.max_bytes = MAX_FUSED_JCC_PADDING_SIZE;
12518
0
  }
12519
0
      else if (add_branch_prefix_frag_p (last_insn))
12520
0
  {
12521
0
    unsigned int max_prefix_size = align_branch_prefix_size;
12522
12523
    /* Make room for padding.  */
12524
0
    frag_grow (max_prefix_size);
12525
0
    p = frag_more (0);
12526
12527
0
    fragP = frag_now;
12528
12529
0
    frag_var (rs_machine_dependent, max_prefix_size, 0,
12530
0
        ENCODE_RELAX_STATE (BRANCH_PREFIX, 0),
12531
0
        NULL, 0, p);
12532
12533
0
    fragP->tc_frag_data.max_bytes = max_prefix_size;
12534
0
  }
12535
12536
      /* Since the VEX/EVEX prefix contains the implicit prefix, we
12537
   don't need the explicit prefix.  */
12538
0
      if (!is_any_vex_encoding (&i.tm))
12539
0
  {
12540
0
    switch (i.tm.opcode_modifier.opcodeprefix)
12541
0
      {
12542
0
      case PREFIX_0X66:
12543
0
        add_prefix (0x66);
12544
0
        break;
12545
0
      case PREFIX_0XF2:
12546
0
        add_prefix (0xf2);
12547
0
        break;
12548
0
      case PREFIX_0XF3:
12549
0
        if ((!is_cpu (&i.tm, CpuPadLock)
12550
0
       && !is_cpu (&i.tm, CpuPadLockRNG2)
12551
0
       && !is_cpu (&i.tm, CpuPadLockPHE2)
12552
0
       && !is_cpu (&i.tm, CpuPadLockXMODX))
12553
0
      || (i.prefix[REP_PREFIX] != 0xf3))
12554
0
    add_prefix (0xf3);
12555
0
        break;
12556
0
      case PREFIX_NONE:
12557
0
        switch (i.opcode_length)
12558
0
    {
12559
0
    case 2:
12560
0
      break;
12561
0
    case 1:
12562
      /* Check for pseudo prefixes.  */
12563
0
      if (!i.tm.opcode_modifier.isprefix || i.tm.base_opcode)
12564
0
        break;
12565
0
      as_bad_where (insn_start_frag->fr_file,
12566
0
        insn_start_frag->fr_line,
12567
0
        _("pseudo prefix without instruction"));
12568
0
      return;
12569
0
    default:
12570
0
      abort ();
12571
0
    }
12572
0
        break;
12573
0
      default:
12574
0
        abort ();
12575
0
      }
12576
12577
0
#ifdef OBJ_ELF
12578
    /* For x32, add a dummy REX_OPCODE prefix for mov/add with
12579
       R_X86_64_GOTTPOFF relocation so that linker can safely
12580
       perform IE->LE optimization.  A dummy REX_OPCODE prefix
12581
       is also needed for lea with R_X86_64_GOTPC32_TLSDESC
12582
       relocation for GDesc -> IE/LE optimization.  */
12583
0
    if (x86_elf_abi == X86_64_X32_ABI
12584
0
        && !is_apx_rex2_encoding ()
12585
0
        && (dot_insn () ? i.insn_opcode_space
12586
0
            : i.tm.opcode_space) == SPACE_BASE
12587
0
        && i.operands == 2
12588
0
        && (i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF
12589
0
      || i.reloc[0] == BFD_RELOC_X86_64_GOTPC32_TLSDESC)
12590
0
        && i.prefix[REX_PREFIX] == 0)
12591
0
      add_prefix (REX_OPCODE);
12592
0
#endif
12593
12594
    /* The prefix bytes.  */
12595
0
    for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
12596
0
      if (*q)
12597
0
        frag_opcode_byte (*q);
12598
12599
0
    if (is_apx_rex2_encoding ())
12600
0
      {
12601
0
        frag_opcode_byte (i.vex.bytes[0]);
12602
0
        frag_opcode_byte (i.vex.bytes[1]);
12603
0
      }
12604
0
  }
12605
0
      else
12606
0
  {
12607
0
    for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
12608
0
      if (*q)
12609
0
        switch (j)
12610
0
    {
12611
0
    case SEG_PREFIX:
12612
0
    case ADDR_PREFIX:
12613
0
      frag_opcode_byte (*q);
12614
0
      break;
12615
0
    default:
12616
      /* There should be no other prefixes for instructions
12617
         with VEX prefix.  */
12618
0
      abort ();
12619
0
    }
12620
12621
    /* For EVEX instructions i.vrex should become 0 after
12622
       build_evex_prefix.  For VEX instructions upper 16 registers
12623
       aren't available, so VREX should be 0.  */
12624
0
    if (i.vrex)
12625
0
      abort ();
12626
    /* Now the VEX prefix.  */
12627
0
    if (now_seg != absolute_section)
12628
0
      {
12629
0
        p = frag_more (i.vex.length);
12630
0
        for (j = 0; j < i.vex.length; j++)
12631
0
    p[j] = i.vex.bytes[j];
12632
0
      }
12633
0
    else
12634
0
      abs_section_offset += i.vex.length;
12635
0
  }
12636
12637
      /* Now the opcode; be careful about word order here!  */
12638
0
      j = i.opcode_length;
12639
0
      if (!i.vex.length)
12640
0
  switch (i.tm.opcode_space)
12641
0
    {
12642
0
    case SPACE_BASE:
12643
0
      break;
12644
0
    case SPACE_0F:
12645
0
      ++j;
12646
0
      break;
12647
0
    case SPACE_0F38:
12648
0
    case SPACE_0F3A:
12649
0
      j += 2;
12650
0
      break;
12651
0
    default:
12652
0
      abort ();
12653
0
    }
12654
12655
0
      if (now_seg == absolute_section)
12656
0
  abs_section_offset += j;
12657
0
      else if (j == 1)
12658
0
  {
12659
0
    FRAG_APPEND_1_CHAR (i.tm.base_opcode);
12660
0
  }
12661
0
      else
12662
0
  {
12663
0
    p = frag_more (j);
12664
0
    if (!i.vex.length
12665
0
        && i.tm.opcode_space != SPACE_BASE)
12666
0
      {
12667
0
        *p++ = 0x0f;
12668
0
        if (i.tm.opcode_space != SPACE_0F)
12669
0
    *p++ = i.tm.opcode_space == SPACE_0F38
12670
0
           ? 0x38 : 0x3a;
12671
0
      }
12672
12673
0
    switch (i.opcode_length)
12674
0
      {
12675
0
      case 2:
12676
        /* Put out high byte first: can't use md_number_to_chars!  */
12677
0
        *p++ = (i.tm.base_opcode >> 8) & 0xff;
12678
        /* Fall through.  */
12679
0
      case 1:
12680
0
        *p = i.tm.base_opcode & 0xff;
12681
0
        break;
12682
0
      default:
12683
0
        abort ();
12684
0
        break;
12685
0
      }
12686
12687
0
  }
12688
12689
      /* Now the modrm byte and sib byte (if present).  */
12690
0
      if (i.tm.opcode_modifier.modrm)
12691
0
  {
12692
0
    frag_opcode_byte ((i.rm.regmem << 0)
12693
0
           | (i.rm.reg << 3)
12694
0
           | (i.rm.mode << 6));
12695
    /* If i.rm.regmem == ESP (4)
12696
       && i.rm.mode != (Register mode)
12697
       && not 16 bit
12698
       ==> need second modrm byte.  */
12699
0
    if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
12700
0
        && i.rm.mode != 3
12701
0
        && !(i.base_reg && i.base_reg->reg_type.bitfield.word))
12702
0
      frag_opcode_byte ((i.sib.base << 0)
12703
0
            | (i.sib.index << 3)
12704
0
            | (i.sib.scale << 6));
12705
0
  }
12706
12707
0
      if (i.disp_operands)
12708
0
  output_disp (insn_start_frag, insn_start_off);
12709
12710
0
      if (i.imm_operands)
12711
0
  output_imm (insn_start_frag, insn_start_off);
12712
12713
      /*
12714
       * frag_now_fix () returning plain abs_section_offset when we're in the
12715
       * absolute section, and abs_section_offset not getting updated as data
12716
       * gets added to the frag breaks the logic below.
12717
       */
12718
0
      if (now_seg != absolute_section)
12719
0
  {
12720
0
    j = encoding_length (insn_start_frag, insn_start_off, frag_more (0));
12721
0
    if (j > 15)
12722
0
      {
12723
0
        if (dot_insn ())
12724
0
    as_warn (_("instruction length of %u bytes exceeds the limit of 15"),
12725
0
      j);
12726
0
        else
12727
0
    as_bad (_("instruction length of %u bytes exceeds the limit of 15"),
12728
0
      j);
12729
0
      }
12730
0
    else if (fragP)
12731
0
      {
12732
        /* NB: Don't add prefix with GOTPC relocation since
12733
     output_disp() above depends on the fixed encoding
12734
     length.  Can't add prefix with TLS relocation since
12735
     it breaks TLS linker optimization.  */
12736
0
        unsigned int max = i.has_gotpc_tls_reloc ? 0 : 15 - j;
12737
        /* Prefix count on the current instruction.  */
12738
0
        unsigned int count = i.vex.length;
12739
0
        unsigned int k;
12740
0
        for (k = 0; k < ARRAY_SIZE (i.prefix); k++)
12741
    /* REX byte is encoded in VEX/EVEX prefix.  */
12742
0
    if (i.prefix[k] && (k != REX_PREFIX || !i.vex.length))
12743
0
      count++;
12744
12745
        /* Count prefixes for extended opcode maps.  */
12746
0
        if (!i.vex.length)
12747
0
    switch (i.tm.opcode_space)
12748
0
      {
12749
0
      case SPACE_BASE:
12750
0
        break;
12751
0
      case SPACE_0F:
12752
0
        count++;
12753
0
        break;
12754
0
      case SPACE_0F38:
12755
0
      case SPACE_0F3A:
12756
0
        count += 2;
12757
0
        break;
12758
0
      default:
12759
0
        abort ();
12760
0
      }
12761
12762
0
        if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype)
12763
0
      == BRANCH_PREFIX)
12764
0
    {
12765
      /* Set the maximum prefix size in BRANCH_PREFIX
12766
         frag.  */
12767
0
      if (fragP->tc_frag_data.max_bytes > max)
12768
0
        fragP->tc_frag_data.max_bytes = max;
12769
0
      if (fragP->tc_frag_data.max_bytes > count)
12770
0
        fragP->tc_frag_data.max_bytes -= count;
12771
0
      else
12772
0
        fragP->tc_frag_data.max_bytes = 0;
12773
0
    }
12774
0
        else
12775
0
    {
12776
      /* Remember the maximum prefix size in FUSED_JCC_PADDING
12777
         frag.  */
12778
0
      unsigned int max_prefix_size;
12779
0
      if (align_branch_prefix_size > max)
12780
0
        max_prefix_size = max;
12781
0
      else
12782
0
        max_prefix_size = align_branch_prefix_size;
12783
0
      if (max_prefix_size > count)
12784
0
        fragP->tc_frag_data.max_prefix_length
12785
0
          = max_prefix_size - count;
12786
0
    }
12787
12788
        /* Use existing segment prefix if possible.  Use CS
12789
     segment prefix in 64-bit mode.  In 32-bit mode, use SS
12790
     segment prefix with ESP/EBP base register and use DS
12791
     segment prefix without ESP/EBP base register.  */
12792
0
        if (i.prefix[SEG_PREFIX])
12793
0
    fragP->tc_frag_data.default_prefix = i.prefix[SEG_PREFIX];
12794
0
        else if (flag_code == CODE_64BIT)
12795
0
    fragP->tc_frag_data.default_prefix = CS_PREFIX_OPCODE;
12796
0
        else if (i.base_reg
12797
0
           && (i.base_reg->reg_num == 4
12798
0
         || i.base_reg->reg_num == 5))
12799
0
    fragP->tc_frag_data.default_prefix = SS_PREFIX_OPCODE;
12800
0
        else
12801
0
    fragP->tc_frag_data.default_prefix = DS_PREFIX_OPCODE;
12802
0
      }
12803
0
  }
12804
0
    }
12805
12806
  /* NB: Don't work with COND_JUMP86 without i386.  */
12807
0
  if (align_branch_power
12808
0
      && now_seg != absolute_section
12809
0
      && cpu_arch_flags.bitfield.cpui386)
12810
0
    {
12811
      /* Terminate each frag so that we can add prefix and check for
12812
         fused jcc.  */
12813
0
      frag_wane (frag_now);
12814
0
      frag_new (0);
12815
0
    }
12816
12817
#ifdef DEBUG386
12818
  if (flag_debug)
12819
    {
12820
      pi ("" /*line*/, &i);
12821
    }
12822
#endif /* DEBUG386  */
12823
0
}
12824
12825
/* Return the size of the displacement operand N.  */
12826
12827
static int
12828
disp_size (unsigned int n)
12829
0
{
12830
0
  int size = 4;
12831
12832
0
  if (i.types[n].bitfield.disp64)
12833
0
    size = 8;
12834
0
  else if (i.types[n].bitfield.disp8)
12835
0
    size = 1;
12836
0
  else if (i.types[n].bitfield.disp16)
12837
0
    size = 2;
12838
0
  return size;
12839
0
}
12840
12841
/* Return the size of the immediate operand N.  */
12842
12843
static int
12844
imm_size (unsigned int n)
12845
0
{
12846
0
  int size = 4;
12847
0
  if (i.types[n].bitfield.imm64)
12848
0
    size = 8;
12849
0
  else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
12850
0
    size = 1;
12851
0
  else if (i.types[n].bitfield.imm16)
12852
0
    size = 2;
12853
0
  return size;
12854
0
}
12855
12856
static void
12857
output_disp (fragS *insn_start_frag, offsetT insn_start_off)
12858
0
{
12859
0
  char *p;
12860
0
  unsigned int n;
12861
12862
0
  for (n = 0; n < i.operands; n++)
12863
0
    {
12864
0
      if (operand_type_check (i.types[n], disp))
12865
0
  {
12866
0
    int size = disp_size (n);
12867
12868
0
    if (now_seg == absolute_section)
12869
0
      abs_section_offset += size;
12870
0
    else if (i.op[n].disps->X_op == O_constant)
12871
0
      {
12872
0
        offsetT val = i.op[n].disps->X_add_number;
12873
12874
0
        val = offset_in_range (val >> (size == 1 ? i.memshift : 0),
12875
0
             size);
12876
0
        p = frag_more (size);
12877
0
        md_number_to_chars (p, val, size);
12878
0
      }
12879
0
    else
12880
0
      {
12881
0
        enum bfd_reloc_code_real reloc_type;
12882
0
        bool pcrel = (i.flags[n] & Operand_PCrel) != 0;
12883
0
        bool sign = (flag_code == CODE_64BIT && size == 4
12884
0
         && (!want_disp32 (&i.tm)
12885
0
             || (i.tm.opcode_modifier.jump && !i.jumpabsolute
12886
0
           && !i.types[n].bitfield.baseindex)))
12887
0
        || pcrel;
12888
0
        fixS *fixP;
12889
12890
        /* We can't have 8 bit displacement here.  */
12891
0
        gas_assert (!i.types[n].bitfield.disp8);
12892
12893
        /* The PC relative address is computed relative
12894
     to the instruction boundary, so in case immediate
12895
     fields follows, we need to adjust the value.  */
12896
0
        if (pcrel && i.imm_operands)
12897
0
    {
12898
0
      unsigned int n1;
12899
0
      int sz = 0;
12900
12901
0
      for (n1 = 0; n1 < i.operands; n1++)
12902
0
        if (operand_type_check (i.types[n1], imm))
12903
0
          {
12904
      /* Only one immediate is allowed for PC
12905
         relative address, except with .insn.  */
12906
0
      gas_assert (sz == 0 || dot_insn ());
12907
0
      sz += imm_size (n1);
12908
0
          }
12909
      /* We should find at least one immediate.  */
12910
0
      gas_assert (sz != 0);
12911
0
      i.op[n].disps->X_add_number -= sz;
12912
0
    }
12913
12914
0
        p = frag_more (size);
12915
0
        reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
12916
0
        if (GOT_symbol
12917
0
      && GOT_symbol == i.op[n].disps->X_add_symbol
12918
0
      && (((reloc_type == BFD_RELOC_32
12919
0
      || reloc_type == BFD_RELOC_X86_64_32S
12920
0
      || (reloc_type == BFD_RELOC_64
12921
0
          && object_64bit))
12922
0
           && (i.op[n].disps->X_op == O_symbol
12923
0
         || (i.op[n].disps->X_op == O_add
12924
0
             && ((symbol_get_value_expression
12925
0
            (i.op[n].disps->X_op_symbol)->X_op)
12926
0
           == O_subtract))))
12927
0
          || reloc_type == BFD_RELOC_32_PCREL))
12928
0
    {
12929
0
      if (!object_64bit)
12930
0
        {
12931
0
          reloc_type = BFD_RELOC_386_GOTPC;
12932
0
          i.has_gotpc_tls_reloc = true;
12933
0
          i.op[n].disps->X_add_number +=
12934
0
      encoding_length (insn_start_frag, insn_start_off, p);
12935
0
        }
12936
0
      else if (reloc_type == BFD_RELOC_64)
12937
0
        reloc_type = BFD_RELOC_X86_64_GOTPC64;
12938
0
      else
12939
        /* Don't do the adjustment for x86-64, as there
12940
           the pcrel addressing is relative to the _next_
12941
           insn, and that is taken care of in other code.  */
12942
0
        reloc_type = BFD_RELOC_X86_64_GOTPC32;
12943
0
    }
12944
0
        else if (align_branch_power)
12945
0
    {
12946
0
      switch (reloc_type)
12947
0
        {
12948
0
        case BFD_RELOC_386_TLS_GD:
12949
0
        case BFD_RELOC_386_TLS_LDM:
12950
0
        case BFD_RELOC_386_TLS_IE:
12951
0
        case BFD_RELOC_386_TLS_IE_32:
12952
0
        case BFD_RELOC_386_TLS_GOTIE:
12953
0
        case BFD_RELOC_386_TLS_GOTDESC:
12954
0
        case BFD_RELOC_386_TLS_DESC_CALL:
12955
0
        case BFD_RELOC_X86_64_TLSGD:
12956
0
        case BFD_RELOC_X86_64_TLSLD:
12957
0
        case BFD_RELOC_X86_64_GOTTPOFF:
12958
0
        case BFD_RELOC_X86_64_CODE_4_GOTTPOFF:
12959
0
        case BFD_RELOC_X86_64_CODE_5_GOTTPOFF:
12960
0
        case BFD_RELOC_X86_64_CODE_6_GOTTPOFF:
12961
0
        case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
12962
0
        case BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC:
12963
0
        case BFD_RELOC_X86_64_CODE_5_GOTPC32_TLSDESC:
12964
0
        case BFD_RELOC_X86_64_CODE_6_GOTPC32_TLSDESC:
12965
0
        case BFD_RELOC_X86_64_TLSDESC_CALL:
12966
0
          i.has_gotpc_tls_reloc = true;
12967
0
        default:
12968
0
          break;
12969
0
        }
12970
0
    }
12971
0
        fixP = fix_new_exp (frag_now, p - frag_now->fr_literal,
12972
0
          size, i.op[n].disps, pcrel,
12973
0
          reloc_type);
12974
12975
0
        if (flag_code == CODE_64BIT && size == 4 && pcrel
12976
0
      && !i.prefix[ADDR_PREFIX])
12977
0
    fixP->fx_signed = 1;
12978
12979
0
        if (i.base_reg && i.base_reg->reg_num == RegIP)
12980
0
    {
12981
0
      if (reloc_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC)
12982
0
        {
12983
          /* Set fx_tcbit for REX2 prefix.  */
12984
0
          if (is_apx_rex2_encoding ())
12985
0
      fixP->fx_tcbit = 1;
12986
0
          continue;
12987
0
        }
12988
0
    }
12989
        /* In 64-bit, i386_validate_fix updates only (%rip)
12990
     relocations.  */
12991
0
        else if (object_64bit)
12992
0
    continue;
12993
12994
0
#ifdef OBJ_ELF
12995
        /* Check for "call/jmp *mem", "push mem", "mov mem, %reg",
12996
     "movrs mem, %reg", "test %reg, mem" and "binop mem, %reg" where
12997
     binop is one of adc, add, and, cmp, or, sbb, sub, xor, or imul
12998
     instructions without data prefix.  Always generate
12999
     R_386_GOT32X for "sym*GOT" operand in 32-bit mode.  */
13000
0
        unsigned int space = dot_insn () ? i.insn_opcode_space
13001
0
                 : i.tm.opcode_space;
13002
0
        if (i.prefix[DATA_PREFIX] == 0
13003
0
      && (i.rm.mode == 2
13004
0
          || (i.rm.mode == 0 && i.rm.regmem == 5))
13005
0
      && ((space == SPACE_BASE
13006
0
           && i.tm.base_opcode == 0xff
13007
0
           && (i.rm.reg == 2 || i.rm.reg == 4 || i.rm.reg == 6))
13008
0
          || ((space == SPACE_BASE
13009
0
         || space == SPACE_0F38
13010
0
         || space == SPACE_MAP4)
13011
0
        && i.tm.base_opcode == 0x8b)
13012
0
          || ((space == SPACE_BASE
13013
0
         || space == SPACE_MAP4)
13014
0
        && (i.tm.base_opcode == 0x85
13015
0
            || (i.tm.base_opcode
13016
0
          | (i.operands > 2 ? 0x3a : 0x38)) == 0x3b))
13017
0
          || (((space == SPACE_0F
13018
          /* Because of the 0F prefix, no suitable relocation
13019
             exists for this unless it's REX2-encoded.  */
13020
0
          && is_apx_rex2_encoding ())
13021
0
         || space == SPACE_MAP4)
13022
0
        && i.tm.base_opcode == 0xaf)))
13023
0
    {
13024
0
      if (object_64bit)
13025
0
        {
13026
0
          if (reloc_type == BFD_RELOC_X86_64_GOTTPOFF)
13027
0
      {
13028
0
        if (space == SPACE_MAP4)
13029
0
          fixP->fx_tcbit3 = 1;
13030
0
        else if (space == SPACE_0F38 && i.rex)
13031
0
          fixP->fx_tcbit2 = 1;
13032
0
        else if (space == SPACE_0F38 || is_apx_rex2_encoding ())
13033
0
          fixP->fx_tcbit = 1;
13034
0
      }
13035
0
          else if (generate_relax_relocations)
13036
0
      {
13037
0
        if (space == SPACE_MAP4)
13038
0
          {
13039
0
            fixP->fx_tcbit3 = 1;
13040
0
            fixP->fx_tcbit2 = 1;
13041
0
          }
13042
0
        else if (space == SPACE_0F38)
13043
0
          {
13044
0
            fixP->fx_tcbit3 = 1;
13045
0
            if (i.rex)
13046
0
        fixP->fx_tcbit = 1;
13047
0
          }
13048
0
        else if (is_apx_rex2_encoding ())
13049
0
          fixP->fx_tcbit3 = 1;
13050
0
        else if (i.rex)
13051
0
          fixP->fx_tcbit2 = 1;
13052
0
        else
13053
0
          fixP->fx_tcbit = 1;
13054
0
      }
13055
0
        }
13056
0
      else if (generate_relax_relocations
13057
0
         ? (!shared || i.rm.mode != 0 || i.rm.regmem != 5)
13058
0
         : (!shared && i.rm.mode == 0 && i.rm.regmem == 5))
13059
0
        fixP->fx_tcbit2 = 1;
13060
0
    }
13061
0
#endif
13062
0
      }
13063
0
  }
13064
0
    }
13065
0
}
13066
13067
static void
13068
output_imm (fragS *insn_start_frag, offsetT insn_start_off)
13069
0
{
13070
0
  char *p;
13071
0
  unsigned int n;
13072
13073
0
  for (n = 0; n < i.operands; n++)
13074
0
    {
13075
0
      if (operand_type_check (i.types[n], imm))
13076
0
  {
13077
0
    int size = imm_size (n);
13078
13079
0
    if (now_seg == absolute_section)
13080
0
      abs_section_offset += size;
13081
0
    else if (i.op[n].imms->X_op == O_constant)
13082
0
      {
13083
0
        offsetT val;
13084
13085
0
        val = offset_in_range (i.op[n].imms->X_add_number,
13086
0
             size);
13087
0
        p = frag_more (size);
13088
0
        md_number_to_chars (p, val, size);
13089
0
      }
13090
0
    else
13091
0
      {
13092
        /* Not absolute_section.
13093
     Need a 32-bit fixup (don't support 8bit
13094
     non-absolute imms).  Try to support other
13095
     sizes ...  */
13096
0
        enum bfd_reloc_code_real reloc_type;
13097
0
        int sign;
13098
13099
0
        if (i.types[n].bitfield.imm32s
13100
0
      && (i.suffix == QWORD_MNEM_SUFFIX
13101
0
          || (!i.suffix && i.tm.opcode_modifier.no_lsuf)
13102
0
          || (i.prefix[REX_PREFIX] & REX_W)
13103
0
          || dot_insn ()))
13104
0
    sign = 1;
13105
0
        else
13106
0
    sign = 0;
13107
13108
0
        p = frag_more (size);
13109
0
        reloc_type = reloc (size, 0, sign, i.reloc[n]);
13110
13111
        /*   This is tough to explain.  We end up with this one if we
13112
         * have operands that look like
13113
         * "_GLOBAL_OFFSET_TABLE_+[.-.L284]".  The goal here is to
13114
         * obtain the absolute address of the GOT, and it is strongly
13115
         * preferable from a performance point of view to avoid using
13116
         * a runtime relocation for this.  The actual sequence of
13117
         * instructions often look something like:
13118
         *
13119
         *  call  .L66
13120
         * .L66:
13121
         *  popl  %ebx
13122
         *  addl  $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
13123
         *
13124
         *   The call and pop essentially return the absolute address
13125
         * of the label .L66 and store it in %ebx.  The linker itself
13126
         * will ultimately change the first operand of the addl so
13127
         * that %ebx points to the GOT, but to keep things simple, the
13128
         * .o file must have this operand set so that it generates not
13129
         * the absolute address of .L66, but the absolute address of
13130
         * itself.  This allows the linker itself simply treat a GOTPC
13131
         * relocation as asking for a pcrel offset to the GOT to be
13132
         * added in, and the addend of the relocation is stored in the
13133
         * operand field for the instruction itself.
13134
         *
13135
         *   Our job here is to fix the operand so that it would add
13136
         * the correct offset so that %ebx would point to itself.  The
13137
         * thing that is tricky is that .-.L66 will point to the
13138
         * beginning of the instruction, so we need to further modify
13139
         * the operand so that it will point to itself.  There are
13140
         * other cases where you have something like:
13141
         *
13142
         *  .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
13143
         *
13144
         * and here no correction would be required.  Internally in
13145
         * the assembler we treat operands of this form as not being
13146
         * pcrel since the '.' is explicitly mentioned, and I wonder
13147
         * whether it would simplify matters to do it this way.  Who
13148
         * knows.  In earlier versions of the PIC patches, the
13149
         * pcrel_adjust field was used to store the correction, but
13150
         * since the expression is not pcrel, I felt it would be
13151
         * confusing to do it this way.  */
13152
13153
0
        if ((reloc_type == BFD_RELOC_32
13154
0
       || reloc_type == BFD_RELOC_X86_64_32S
13155
0
       || reloc_type == BFD_RELOC_64)
13156
0
      && GOT_symbol
13157
0
      && GOT_symbol == i.op[n].imms->X_add_symbol
13158
0
      && (i.op[n].imms->X_op == O_symbol
13159
0
          || (i.op[n].imms->X_op == O_add
13160
0
        && ((symbol_get_value_expression
13161
0
             (i.op[n].imms->X_op_symbol)->X_op)
13162
0
            == O_subtract))))
13163
0
    {
13164
0
      if (!object_64bit)
13165
0
        reloc_type = BFD_RELOC_386_GOTPC;
13166
0
      else if (size == 4)
13167
0
        reloc_type = BFD_RELOC_X86_64_GOTPC32;
13168
0
      else if (size == 8)
13169
0
        reloc_type = BFD_RELOC_X86_64_GOTPC64;
13170
0
      i.has_gotpc_tls_reloc = true;
13171
0
      i.op[n].imms->X_add_number +=
13172
0
        encoding_length (insn_start_frag, insn_start_off, p);
13173
0
    }
13174
0
        fix_new_exp (frag_now, p - frag_now->fr_literal, size,
13175
0
         i.op[n].imms, 0, reloc_type);
13176
0
      }
13177
0
  }
13178
0
    }
13179
0
}
13180

13181
/* x86_cons_fix_new is called via the expression parsing code when a
13182
   reloc is needed.  We use this hook to get the correct .got reloc.  */
13183
static int cons_sign = -1;
13184
13185
void
13186
x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
13187
      expressionS *exp, bfd_reloc_code_real_type r)
13188
0
{
13189
0
  r = reloc (len, 0, cons_sign, r);
13190
13191
#ifdef TE_PE
13192
  if (exp->X_op == O_secrel)
13193
    {
13194
      exp->X_op = O_symbol;
13195
      r = BFD_RELOC_32_SECREL;
13196
    }
13197
  else if (exp->X_op == O_secidx)
13198
    r = BFD_RELOC_16_SECIDX;
13199
#endif
13200
13201
0
  fix_new_exp (frag, off, len, exp, 0, r);
13202
0
}
13203
13204
/* Export the ABI address size for use by TC_ADDRESS_BYTES for the
13205
   purpose of the `.dc.a' internal pseudo-op.  */
13206
13207
int
13208
x86_address_bytes (void)
13209
0
{
13210
0
  if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
13211
0
    return 4;
13212
0
  return stdoutput->arch_info->bits_per_address / 8;
13213
0
}
13214
13215
#if (defined (OBJ_ELF) || defined (OBJ_MACH_O) || defined (TE_PE))
13216
/* Parse operands of the form
13217
   <symbol>@GOTOFF+<nnn>
13218
   and similar .plt or .got references.
13219
13220
   If we find one, set up the correct relocation in RELOC and copy the
13221
   input string, minus the `@GOTOFF' into a malloc'd buffer for
13222
   parsing by the calling routine.  Return this buffer, and if ADJUST
13223
   is non-null set it to the length of the string we removed from the
13224
   input line.  Otherwise return NULL.  */
13225
static char *
13226
lex_got (enum bfd_reloc_code_real *rel,
13227
   int *adjust,
13228
   i386_operand_type *types)
13229
0
{
13230
  /* Some of the relocations depend on the size of what field is to
13231
     be relocated.  But in our callers i386_immediate and i386_displacement
13232
     we don't yet know the operand size (this will be set by insn
13233
     matching).  Hence we record the word32 relocation here,
13234
     and adjust the reloc according to the real size in reloc().  */
13235
0
  char *cp;
13236
0
  unsigned int j;
13237
13238
0
  for (cp = input_line_pointer; *cp != '@'; cp++)
13239
0
    if (is_end_of_stmt (*cp) || *cp == ',')
13240
0
      return NULL;
13241
13242
0
  for (j = 0; j < ARRAY_SIZE (gotrel); j++)
13243
0
    {
13244
0
      int len = gotrel[j].len;
13245
0
      if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
13246
0
  {
13247
0
    if (gotrel[j].rel[object_64bit] != 0)
13248
0
      {
13249
0
        int first, second;
13250
0
        char *tmpbuf, *past_reloc;
13251
13252
0
        i.has_gotrel = true;
13253
0
        *rel = gotrel[j].rel[object_64bit];
13254
13255
0
        if (types)
13256
0
    {
13257
0
      if (flag_code != CODE_64BIT)
13258
0
        {
13259
0
          types->bitfield.imm32 = 1;
13260
0
          types->bitfield.disp32 = 1;
13261
0
        }
13262
0
      else
13263
0
        *types = gotrel[j].types64;
13264
0
    }
13265
13266
0
        if (gotrel[j].need_GOT_symbol && GOT_symbol == NULL)
13267
0
    GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
13268
13269
        /* The length of the first part of our input line.  */
13270
0
        first = cp - input_line_pointer;
13271
13272
        /* The second part goes from after the reloc token until
13273
     (and including) an end_of_line char or comma.  */
13274
0
        past_reloc = cp + 1 + len;
13275
0
        cp = past_reloc;
13276
0
        while (!is_end_of_stmt (*cp) && *cp != ',')
13277
0
    ++cp;
13278
0
        second = cp + 1 - past_reloc;
13279
13280
        /* Allocate and copy string.  The trailing NUL shouldn't
13281
     be necessary, but be safe.  */
13282
0
        tmpbuf = XNEWVEC (char, first + second + 2);
13283
0
        memcpy (tmpbuf, input_line_pointer, first);
13284
0
        if (second != 0 && !is_whitespace (*past_reloc))
13285
    /* Replace the relocation token with ' ', so that
13286
       errors like foo@GOTOFF1 will be detected.  */
13287
0
    tmpbuf[first++] = ' ';
13288
0
        else
13289
    /* Increment length by 1 if the relocation token is
13290
       removed.  */
13291
0
    len++;
13292
0
        if (adjust)
13293
0
    *adjust = len;
13294
0
        memcpy (tmpbuf + first, past_reloc, second);
13295
0
        tmpbuf[first + second] = '\0';
13296
0
        return tmpbuf;
13297
0
      }
13298
13299
0
    as_bad (_("@%s reloc is not supported with %d-bit output format"),
13300
0
      gotrel[j].str, 1 << (5 + object_64bit));
13301
0
    return NULL;
13302
0
  }
13303
0
    }
13304
13305
  /* Might be a symbol version string.  Don't as_bad here.  */
13306
0
  return NULL;
13307
0
}
13308
#else
13309
# define lex_got(reloc, adjust, types) NULL
13310
#endif
13311
13312
bfd_reloc_code_real_type
13313
x86_cons (expressionS *exp, int size)
13314
0
{
13315
0
  bfd_reloc_code_real_type got_reloc = NO_RELOC;
13316
13317
0
  intel_syntax = -intel_syntax;
13318
0
  exp->X_md = 0;
13319
0
  expr_mode = expr_operator_none;
13320
13321
0
#if defined (OBJ_ELF) || defined (TE_PE)
13322
0
  if (size == 4
13323
# ifdef TE_PE
13324
      || (size == 2)
13325
# endif
13326
0
      || (object_64bit && size == 8))
13327
0
    {
13328
      /* Handle @GOTOFF and the like in an expression.  */
13329
0
      char *save;
13330
0
      char *gotfree_input_line;
13331
0
      int adjust = 0;
13332
13333
0
      save = input_line_pointer;
13334
0
      gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
13335
0
      if (gotfree_input_line)
13336
0
  input_line_pointer = gotfree_input_line;
13337
13338
0
      expression (exp);
13339
13340
0
      if (gotfree_input_line)
13341
0
  {
13342
    /* expression () has merrily parsed up to the end of line,
13343
       or a comma - in the wrong buffer.  Transfer how far
13344
       input_line_pointer has moved to the right buffer.  */
13345
0
    input_line_pointer = (save
13346
0
        + (input_line_pointer - gotfree_input_line)
13347
0
        + adjust);
13348
0
    free (gotfree_input_line);
13349
0
    if (exp->X_op == O_constant
13350
0
        || exp->X_op == O_absent
13351
0
        || exp->X_op == O_illegal
13352
0
        || exp->X_op == O_register
13353
0
        || exp->X_op == O_big)
13354
0
      {
13355
0
        char c = *input_line_pointer;
13356
0
        *input_line_pointer = 0;
13357
0
        as_bad (_("missing or invalid expression `%s'"), save);
13358
0
        *input_line_pointer = c;
13359
0
      }
13360
0
    else if ((got_reloc == BFD_RELOC_386_PLT32
13361
0
        || got_reloc == BFD_RELOC_X86_64_PLT32)
13362
0
       && exp->X_op != O_symbol)
13363
0
      {
13364
0
        char c = *input_line_pointer;
13365
0
        *input_line_pointer = 0;
13366
0
        as_bad (_("invalid PLT expression `%s'"), save);
13367
0
        *input_line_pointer = c;
13368
0
      }
13369
0
  }
13370
0
    }
13371
0
  else
13372
0
#endif
13373
0
    expression (exp);
13374
13375
0
  intel_syntax = -intel_syntax;
13376
13377
0
  if (intel_syntax)
13378
0
    i386_intel_simplify (exp);
13379
13380
  /* If not 64bit, massage value, to account for wraparound when !BFD64.  */
13381
0
  if (size <= 4 && expr_mode == expr_operator_present
13382
0
      && exp->X_op == O_constant && !object_64bit)
13383
0
    exp->X_add_number = extend_to_32bit_address (exp->X_add_number);
13384
13385
0
  return got_reloc;
13386
0
}
13387
13388
static void
13389
signed_cons (int size)
13390
0
{
13391
0
  if (object_64bit)
13392
0
    cons_sign = 1;
13393
0
  cons (size);
13394
0
  cons_sign = -1;
13395
0
}
13396
13397
static void
13398
s_insn (int dummy ATTRIBUTE_UNUSED)
13399
0
{
13400
0
  char mnemonic[MAX_MNEM_SIZE], *line = input_line_pointer, *ptr;
13401
0
  char *saved_ilp = find_end_of_line (line, false), saved_char;
13402
0
  const char *end;
13403
0
  unsigned int j;
13404
0
  valueT val;
13405
0
  bool vex = false, xop = false;
13406
0
  enum { evex_none, evex_basic, evex_nd } evex = evex_none;
13407
0
  struct last_insn *last_insn;
13408
13409
0
  init_globals ();
13410
13411
0
  saved_char = *saved_ilp;
13412
0
  *saved_ilp = 0;
13413
13414
0
  end = parse_insn (line, mnemonic, parse_prefix);
13415
0
  if (end == NULL)
13416
0
    {
13417
0
  bad:
13418
0
      *saved_ilp = saved_char;
13419
0
      ignore_rest_of_line ();
13420
0
      i.tm.mnem_off = 0;
13421
0
      memset (&pp, 0, sizeof (pp));
13422
0
      return;
13423
0
    }
13424
0
  line += end - line;
13425
13426
0
  current_templates.start = &i.tm;
13427
0
  current_templates.end = &i.tm + 1;
13428
0
  i.tm.mnem_off = MN__insn;
13429
0
  i.tm.extension_opcode = None;
13430
13431
0
  if (startswith (line, "VEX")
13432
0
      && (line[3] == '.' || is_whitespace (line[3])))
13433
0
    {
13434
0
      vex = true;
13435
0
      line += 3;
13436
0
    }
13437
0
  else if (startswith (line, "XOP") && ISDIGIT (line[3]))
13438
0
    {
13439
0
      char *e;
13440
0
      unsigned long n = strtoul (line + 3, &e, 16);
13441
13442
0
      if (e == line + 5 && n >= 0x08 && n <= 0x1f
13443
0
    && (*e == '.' || is_whitespace (*e)))
13444
0
  {
13445
0
    xop = true;
13446
    /* Arrange for build_vex_prefix() to emit 0x8f.  */
13447
0
    i.tm.opcode_space = SPACE_XOP08;
13448
0
    i.insn_opcode_space = n;
13449
0
    line = e;
13450
0
  }
13451
0
    }
13452
0
  else if (startswith (line, "EVEX")
13453
0
     && (line[4] == '.' || is_whitespace (line[4])))
13454
0
    {
13455
0
      evex = evex_basic;
13456
0
      line += 4;
13457
0
    }
13458
13459
0
  if (vex || xop
13460
0
      ? pp.encoding == encoding_evex
13461
0
      : evex
13462
0
  ? pp.encoding == encoding_vex
13463
0
    || pp.encoding == encoding_vex3
13464
0
  : pp.encoding != encoding_default)
13465
0
    {
13466
0
      as_bad (_("pseudo-prefix conflicts with encoding specifier"));
13467
0
      goto bad;
13468
0
    }
13469
13470
0
  if (line > end && pp.encoding == encoding_default)
13471
0
    pp.encoding = evex ? encoding_evex : encoding_vex;
13472
13473
0
  if (pp.encoding != encoding_default)
13474
0
    {
13475
      /* Only address size and segment override prefixes are permitted with
13476
         VEX/XOP/EVEX encodings.  */
13477
0
      const unsigned char *p = i.prefix;
13478
13479
0
      for (j = 0; j < ARRAY_SIZE (i.prefix); ++j, ++p)
13480
0
  {
13481
0
    if (!*p)
13482
0
      continue;
13483
13484
0
    switch (j)
13485
0
      {
13486
0
      case SEG_PREFIX:
13487
0
      case ADDR_PREFIX:
13488
0
        break;
13489
0
      default:
13490
0
      as_bad (_("illegal prefix used with VEX/XOP/EVEX"));
13491
0
      goto bad;
13492
0
      }
13493
0
  }
13494
0
    }
13495
13496
0
  if (line > end && *line == '.')
13497
0
    {
13498
      /* Length specifier (VEX.L, XOP.L, EVEX.L'L).  */
13499
0
      switch (line[1])
13500
0
  {
13501
0
  case 'L':
13502
0
    switch (line[2])
13503
0
      {
13504
0
      case '0':
13505
0
        if (evex)
13506
0
    i.tm.opcode_modifier.evex = EVEX128;
13507
0
        else
13508
0
    i.tm.opcode_modifier.vex = VEX128;
13509
0
        break;
13510
13511
0
      case '1':
13512
0
        if (evex)
13513
0
    i.tm.opcode_modifier.evex = EVEX256;
13514
0
        else
13515
0
    i.tm.opcode_modifier.vex = VEX256;
13516
0
        break;
13517
13518
0
      case '2':
13519
0
        if (evex)
13520
0
    i.tm.opcode_modifier.evex = EVEX512;
13521
0
        break;
13522
13523
0
      case '3':
13524
0
        if (evex)
13525
0
    i.tm.opcode_modifier.evex = EVEX_L3;
13526
0
        break;
13527
13528
0
      case 'I':
13529
0
        if (line[3] == 'G')
13530
0
    {
13531
0
      if (evex)
13532
0
        i.tm.opcode_modifier.evex = EVEXLIG;
13533
0
      else
13534
0
        i.tm.opcode_modifier.vex = VEXScalar; /* LIG */
13535
0
      ++line;
13536
0
    }
13537
0
        break;
13538
0
      }
13539
13540
0
    if (i.tm.opcode_modifier.vex || i.tm.opcode_modifier.evex)
13541
0
      line += 3;
13542
0
    break;
13543
13544
0
  case '1':
13545
0
    if (line[2] == '2' && line[3] == '8')
13546
0
      {
13547
0
        if (evex)
13548
0
    i.tm.opcode_modifier.evex = EVEX128;
13549
0
        else
13550
0
    i.tm.opcode_modifier.vex = VEX128;
13551
0
        line += 4;
13552
0
      }
13553
0
    break;
13554
13555
0
  case '2':
13556
0
    if (line[2] == '5' && line[3] == '6')
13557
0
      {
13558
0
        if (evex)
13559
0
    i.tm.opcode_modifier.evex = EVEX256;
13560
0
        else
13561
0
    i.tm.opcode_modifier.vex = VEX256;
13562
0
        line += 4;
13563
0
      }
13564
0
    break;
13565
13566
0
  case '5':
13567
0
    if (evex && line[2] == '1' && line[3] == '2')
13568
0
      {
13569
0
        i.tm.opcode_modifier.evex = EVEX512;
13570
0
        line += 4;
13571
0
      }
13572
0
    break;
13573
0
  }
13574
0
    }
13575
13576
0
  if (line > end && *line == '.')
13577
0
    {
13578
      /* embedded prefix (VEX.pp, XOP.pp, EVEX.pp).  */
13579
0
      switch (line[1])
13580
0
  {
13581
0
  case 'N':
13582
0
    if (line[2] == 'P')
13583
0
      line += 3;
13584
0
    break;
13585
13586
0
  case '6':
13587
0
    if (line[2] == '6')
13588
0
      {
13589
0
        i.tm.opcode_modifier.opcodeprefix = PREFIX_0X66;
13590
0
        line += 3;
13591
0
      }
13592
0
    break;
13593
13594
0
  case 'F': case 'f':
13595
0
    if (line[2] == '3')
13596
0
      {
13597
0
        i.tm.opcode_modifier.opcodeprefix = PREFIX_0XF3;
13598
0
        line += 3;
13599
0
      }
13600
0
    else if (line[2] == '2')
13601
0
      {
13602
0
        i.tm.opcode_modifier.opcodeprefix = PREFIX_0XF2;
13603
0
        line += 3;
13604
0
      }
13605
0
    break;
13606
0
  }
13607
0
    }
13608
13609
0
  if (line > end && !xop && *line == '.')
13610
0
    {
13611
      /* Encoding space (VEX.mmmmm, EVEX.mmmm).  */
13612
0
      switch (line[1])
13613
0
  {
13614
0
  case '0':
13615
0
    if (TOUPPER (line[2]) != 'F')
13616
0
      break;
13617
0
    if (line[3] == '.' || is_whitespace (line[3]))
13618
0
      {
13619
0
        i.insn_opcode_space = SPACE_0F;
13620
0
        line += 3;
13621
0
      }
13622
0
    else if (line[3] == '3'
13623
0
       && (line[4] == '8' || TOUPPER (line[4]) == 'A')
13624
0
       && (line[5] == '.' || is_whitespace (line[5])))
13625
0
      {
13626
0
        i.insn_opcode_space = line[4] == '8' ? SPACE_0F38 : SPACE_0F3A;
13627
0
        line += 5;
13628
0
      }
13629
0
    break;
13630
13631
0
  case 'M':
13632
0
    if (ISDIGIT (line[2]) && line[2] != '0')
13633
0
      {
13634
0
        char *e;
13635
0
        unsigned long n = strtoul (line + 2, &e, 10);
13636
13637
0
        if (n <= (evex ? 15 : 31)
13638
0
      && (*e == '.' || is_whitespace (*e)))
13639
0
    {
13640
0
      i.insn_opcode_space = n;
13641
0
      line = e;
13642
0
    }
13643
0
      }
13644
0
    break;
13645
0
  }
13646
0
    }
13647
13648
0
  if (line > end && *line == '.' && line[1] == 'W')
13649
0
    {
13650
      /* VEX.W, XOP.W, EVEX.W  */
13651
0
      switch (line[2])
13652
0
  {
13653
0
  case '0':
13654
0
    i.tm.opcode_modifier.vexw = VEXW0;
13655
0
    break;
13656
13657
0
  case '1':
13658
0
    i.tm.opcode_modifier.vexw = VEXW1;
13659
0
    break;
13660
13661
0
  case 'I':
13662
0
    if (line[3] == 'G')
13663
0
      {
13664
0
        i.tm.opcode_modifier.vexw = VEXWIG;
13665
0
        ++line;
13666
0
      }
13667
0
    break;
13668
0
  }
13669
13670
0
      if (i.tm.opcode_modifier.vexw)
13671
0
  line += 3;
13672
0
    }
13673
13674
0
  if (line > end && evex && *line == '.')
13675
0
    {
13676
0
      if (line[1] == 'N' && line[2] == 'D')
13677
0
  {
13678
0
    evex = evex_nd;
13679
0
    line += 3;
13680
0
  }
13681
0
      else if (line[1] == 'Z' && line[2] == 'U')
13682
0
  {
13683
0
    i.tm.opcode_modifier.operandconstraint = ZERO_UPPER;
13684
0
    line += 3;
13685
0
  }
13686
0
    }
13687
13688
0
  if (line > end && *line && !is_whitespace (*line))
13689
0
    {
13690
      /* Improve diagnostic a little.  */
13691
0
      if (*line == '.' && line[1] && !is_whitespace (line[1]))
13692
0
  ++line;
13693
0
      goto done;
13694
0
    }
13695
13696
  /* Before processing the opcode expression, find trailing "+r" or
13697
     "/<digit>" specifiers.  */
13698
0
  for (ptr = line; ; ++ptr)
13699
0
    {
13700
0
      unsigned long n;
13701
0
      char *e;
13702
13703
0
      ptr = strpbrk (ptr, "+/,");
13704
0
      if (ptr == NULL || *ptr == ',')
13705
0
  break;
13706
13707
0
      if (*ptr == '+' && ptr[1] == 'r'
13708
0
    && (ptr[2] == ',' || (is_whitespace (ptr[2]) && ptr[3] == ',')))
13709
0
  {
13710
0
    *ptr = ' ';
13711
0
    ptr[1] = ' ';
13712
0
    i.short_form = true;
13713
0
    break;
13714
0
  }
13715
13716
0
      if (*ptr == '/' && ISDIGIT (ptr[1])
13717
0
    && (n = strtoul (ptr + 1, &e, 8)) < 8
13718
0
    && e == ptr + 2
13719
0
    && (ptr[2] == ',' || (is_whitespace (ptr[2]) && ptr[3] == ',')))
13720
0
  {
13721
0
    *ptr = ' ';
13722
0
    ptr[1] = ' ';
13723
0
    i.tm.extension_opcode = n;
13724
0
    i.tm.opcode_modifier.modrm = 1;
13725
0
    break;
13726
0
  }
13727
0
    }
13728
13729
0
  input_line_pointer = line;
13730
0
  val = get_absolute_expression ();
13731
0
  line = input_line_pointer;
13732
13733
0
  if (i.short_form && (val & 7))
13734
0
    as_warn ("`+r' assumes low three opcode bits to be clear");
13735
13736
0
  for (j = 1; j < sizeof(val); ++j)
13737
0
    if (!(val >> (j * 8)))
13738
0
      break;
13739
13740
  /* Trim off a prefix if present.  */
13741
0
  if (j > 1 && !vex && !xop && !evex)
13742
0
    {
13743
0
      uint8_t byte = val >> ((j - 1) * 8);
13744
13745
0
      switch (byte)
13746
0
  {
13747
0
  case DATA_PREFIX_OPCODE:
13748
0
  case REPE_PREFIX_OPCODE:
13749
0
  case REPNE_PREFIX_OPCODE:
13750
0
    if (!add_prefix (byte))
13751
0
      goto bad;
13752
0
    val &= ((uint64_t)1 << (--j * 8)) - 1;
13753
0
    break;
13754
0
  }
13755
0
    }
13756
13757
0
  if (evex == evex_basic && *line == '{')
13758
0
    {
13759
0
      int length = check_Scc_OszcOperations (line);
13760
13761
0
      if (length > 0)
13762
0
  {
13763
0
    line += length;
13764
0
    if (is_whitespace (*line))
13765
0
      ++line;
13766
13767
0
    if (i.tm.opcode_modifier.operandconstraint)
13768
0
      {
13769
0
        as_bad (_("SCC/OSZC specifier cannot be used here"));
13770
0
        goto bad;
13771
0
      }
13772
0
    i.tm.opcode_modifier.operandconstraint = SCC;
13773
0
  }
13774
0
    }
13775
13776
  /* Parse operands, if any, before evaluating encoding space.  */
13777
0
  if (*line == ',')
13778
0
    {
13779
0
      i.memshift = -1;
13780
13781
0
      ptr = parse_operands (line + 1, &i386_mnemonics[MN__insn]);
13782
0
      this_operand = -1;
13783
0
      if (!ptr)
13784
0
  goto bad;
13785
0
      line = ptr;
13786
13787
0
      if (!i.operands)
13788
0
  {
13789
0
    as_bad (_("expecting operand after ','; got nothing"));
13790
0
    goto done;
13791
0
  }
13792
13793
0
      if (i.mem_operands > 1)
13794
0
  {
13795
0
    as_bad (_("too many memory references for `%s'"),
13796
0
      &i386_mnemonics[MN__insn]);
13797
0
    goto done;
13798
0
  }
13799
13800
      /* No need to distinguish encoding_evex and encoding_evex512.  */
13801
0
      if (pp.encoding == encoding_evex512)
13802
0
  pp.encoding = encoding_evex;
13803
0
    }
13804
13805
  /* Trim off encoding space.  */
13806
0
  if (j > 1 && !i.insn_opcode_space && (val >> ((j - 1) * 8)) == 0x0f)
13807
0
    {
13808
0
      uint8_t byte = val >> ((--j - 1) * 8);
13809
13810
0
      i.insn_opcode_space = SPACE_0F;
13811
0
      switch (byte & -(j > 1 && !pp.rex2_encoding
13812
0
           && (pp.encoding != encoding_egpr || evex)))
13813
0
  {
13814
0
  case 0x38:
13815
0
    i.insn_opcode_space = SPACE_0F38;
13816
0
    --j;
13817
0
    break;
13818
0
  case 0x3a:
13819
0
    i.insn_opcode_space = SPACE_0F3A;
13820
0
    --j;
13821
0
    break;
13822
0
  }
13823
0
      i.tm.opcode_space = i.insn_opcode_space;
13824
0
      val &= ((uint64_t)1 << (j * 8)) - 1;
13825
0
    }
13826
0
  if (!i.tm.opcode_space && (vex || evex))
13827
    /* Arrange for build_vex_prefix() to properly emit 0xC4/0xC5.
13828
       Also avoid hitting abort() there or in build_evex_prefix().  */
13829
0
    i.tm.opcode_space = i.insn_opcode_space == SPACE_0F ? SPACE_0F
13830
0
               : SPACE_0F38;
13831
13832
0
  if (j > 2)
13833
0
    {
13834
0
      as_bad (_("opcode residual (%#"PRIx64") too wide"), (uint64_t) val);
13835
0
      goto done;
13836
0
    }
13837
0
  i.opcode_length = j;
13838
13839
  /* Handle operands, if any.  */
13840
0
  if (i.operands)
13841
0
    {
13842
0
      i386_operand_type combined;
13843
0
      expressionS *disp_exp = NULL;
13844
0
      bool changed;
13845
13846
0
      if (pp.encoding == encoding_egpr)
13847
0
  {
13848
0
    if (vex || xop)
13849
0
      {
13850
0
        as_bad (_("eGPR use conflicts with encoding specifier"));
13851
0
        goto done;
13852
0
      }
13853
0
    if (evex)
13854
0
      pp.encoding = encoding_evex;
13855
0
    else
13856
0
      pp.encoding = encoding_default;
13857
0
  }
13858
13859
      /* Are we to emit ModR/M encoding?  */
13860
0
      if (!i.short_form
13861
0
    && (i.mem_operands
13862
0
        || i.reg_operands > (pp.encoding != encoding_default)
13863
0
        || i.tm.extension_opcode != None))
13864
0
  i.tm.opcode_modifier.modrm = 1;
13865
13866
0
      if (!i.tm.opcode_modifier.modrm
13867
0
    && (i.reg_operands
13868
0
        > i.short_form + 0U + (pp.encoding != encoding_default)
13869
0
        || i.mem_operands))
13870
0
  {
13871
0
    as_bad (_("too many register/memory operands"));
13872
0
    goto done;
13873
0
  }
13874
13875
      /* Enforce certain constraints on operands.  */
13876
0
      switch (i.reg_operands + i.mem_operands
13877
0
        + (i.tm.extension_opcode != None)
13878
0
        + (i.tm.opcode_modifier.operandconstraint == SCC))
13879
0
  {
13880
0
  case 0:
13881
0
    if (i.short_form)
13882
0
      {
13883
0
        as_bad (_("too few register/memory operands"));
13884
0
        goto done;
13885
0
      }
13886
    /* Fall through.  */
13887
0
  case 1:
13888
0
    if (i.tm.opcode_modifier.modrm)
13889
0
      {
13890
0
        as_bad (_("too few register/memory operands"));
13891
0
        goto done;
13892
0
      }
13893
    /* Fall through.  */
13894
0
  case 2:
13895
0
    if (evex == evex_nd)
13896
0
      {
13897
0
        as_bad (_("too few register/memory operands"));
13898
0
        goto done;
13899
0
      }
13900
0
    break;
13901
13902
0
  case 4:
13903
0
    if (i.imm_operands
13904
0
        && (i.op[0].imms->X_op != O_constant
13905
0
      || !fits_in_imm4 (i.op[0].imms->X_add_number)))
13906
0
      {
13907
0
        as_bad (_("constant doesn't fit in %d bits"), evex ? 3 : 4);
13908
0
        goto done;
13909
0
      }
13910
    /* Fall through.  */
13911
0
  case 3:
13912
0
    if (i.tm.opcode_modifier.operandconstraint == SCC)
13913
0
      break;
13914
0
    if (pp.encoding != encoding_default)
13915
0
      {
13916
0
        i.tm.opcode_modifier.vexvvvv = (i.tm.extension_opcode == None
13917
0
                && evex != evex_nd)
13918
0
               ? VexVVVV_SRC1 : VexVVVV_DST;
13919
0
        break;
13920
0
      }
13921
    /* Fall through.  */
13922
0
  default:
13923
0
    as_bad (_("too many register/memory operands"));
13924
0
    goto done;
13925
0
  }
13926
13927
      /* Bring operands into canonical order (imm, mem, reg).  */
13928
0
      do
13929
0
  {
13930
0
    changed = false;
13931
13932
0
    for (j = 1; j < i.operands; ++j)
13933
0
      {
13934
0
        if ((!operand_type_check (i.types[j - 1], imm)
13935
0
       && operand_type_check (i.types[j], imm))
13936
0
      || (i.types[j - 1].bitfield.class != ClassNone
13937
0
          && i.types[j].bitfield.class == ClassNone))
13938
0
    {
13939
0
      swap_2_operands (j - 1, j);
13940
0
      changed = true;
13941
0
    }
13942
0
      }
13943
0
  }
13944
0
      while (changed);
13945
13946
      /* For Intel syntax swap the order of register operands.  */
13947
0
      if (intel_syntax)
13948
0
  switch (i.reg_operands)
13949
0
    {
13950
0
    case 0:
13951
0
    case 1:
13952
0
      break;
13953
13954
0
    case 4:
13955
0
      swap_2_operands (i.imm_operands + i.mem_operands + 1, i.operands - 2);
13956
      /* Fall through.  */
13957
0
    case 3:
13958
0
    case 2:
13959
0
      swap_2_operands (i.imm_operands + i.mem_operands, i.operands - 1);
13960
0
      break;
13961
13962
0
    default:
13963
0
      abort ();
13964
0
    }
13965
13966
      /* Enforce constraints when using VSIB.  */
13967
0
      if (i.index_reg
13968
0
    && (i.index_reg->reg_type.bitfield.xmmword
13969
0
        || i.index_reg->reg_type.bitfield.ymmword
13970
0
        || i.index_reg->reg_type.bitfield.zmmword))
13971
0
  {
13972
0
    if (pp.encoding == encoding_default)
13973
0
      {
13974
0
        as_bad (_("VSIB unavailable with legacy encoding"));
13975
0
        goto done;
13976
0
      }
13977
13978
0
    if (pp.encoding == encoding_evex
13979
0
        && i.reg_operands > 1)
13980
0
      {
13981
        /* We could allow two register operands, encoding the 2nd one in
13982
     an 8-bit immediate like for 4-register-operand insns, but that
13983
     would require ugly fiddling with process_operands() and/or
13984
     build_modrm_byte().  */
13985
0
        as_bad (_("too many register operands with VSIB"));
13986
0
        goto done;
13987
0
      }
13988
13989
0
    i.tm.opcode_modifier.sib = 1;
13990
0
  }
13991
13992
      /* Establish operand size encoding.  */
13993
0
      operand_type_set (&combined, 0);
13994
13995
0
      for (j = i.imm_operands; j < i.operands; ++j)
13996
0
  {
13997
    /* Look for 8-bit operands that use old registers.  */
13998
0
    if (pp.encoding != encoding_default
13999
0
        && flag_code == CODE_64BIT
14000
0
        && i.types[j].bitfield.class == Reg
14001
0
        && i.types[j].bitfield.byte
14002
0
        && !(i.op[j].regs->reg_flags & (RegRex | RegRex2 | RegRex64))
14003
0
        && i.op[j].regs->reg_num > 3)
14004
0
      as_bad (_("can't encode register '%s%s' with VEX/XOP/EVEX"),
14005
0
        register_prefix, i.op[j].regs->reg_name);
14006
14007
0
    i.types[j].bitfield.instance = InstanceNone;
14008
14009
0
    if (operand_type_check (i.types[j], disp))
14010
0
      {
14011
0
        i.types[j].bitfield.baseindex = 1;
14012
0
        disp_exp = i.op[j].disps;
14013
0
      }
14014
14015
0
    if (evex && i.types[j].bitfield.baseindex)
14016
0
      {
14017
0
        unsigned int n = i.memshift;
14018
14019
0
        if (i.types[j].bitfield.byte)
14020
0
    n = 0;
14021
0
        else if (i.types[j].bitfield.word)
14022
0
    n = 1;
14023
0
        else if (i.types[j].bitfield.dword)
14024
0
    n = 2;
14025
0
        else if (i.types[j].bitfield.qword)
14026
0
    n = 3;
14027
0
        else if (i.types[j].bitfield.xmmword)
14028
0
    n = 4;
14029
0
        else if (i.types[j].bitfield.ymmword)
14030
0
    n = 5;
14031
0
        else if (i.types[j].bitfield.zmmword)
14032
0
    n = 6;
14033
14034
0
        if (i.memshift < 32 && n != i.memshift)
14035
0
    as_warn ("conflicting memory operand size specifiers");
14036
0
        i.memshift = n;
14037
0
      }
14038
14039
0
    if ((i.broadcast.type || i.broadcast.bytes)
14040
0
        && j == i.broadcast.operand)
14041
0
      continue;
14042
14043
0
    combined = operand_type_or (combined, i.types[j]);
14044
0
    combined.bitfield.class = ClassNone;
14045
0
  }
14046
14047
0
      switch ((i.broadcast.type ? i.broadcast.type : 1)
14048
0
        << (i.memshift < 32 ? i.memshift : 0))
14049
0
  {
14050
0
  case 64: combined.bitfield.zmmword = 1; break;
14051
0
  case 32: combined.bitfield.ymmword = 1; break;
14052
0
  case 16: combined.bitfield.xmmword = 1; break;
14053
0
  case  8: combined.bitfield.qword = 1; break;
14054
0
  case  4: combined.bitfield.dword = 1; break;
14055
0
  }
14056
14057
0
      if (pp.encoding == encoding_default)
14058
0
  {
14059
0
    if (flag_code == CODE_64BIT && combined.bitfield.qword)
14060
0
      i.rex |= REX_W;
14061
0
    else if ((flag_code == CODE_16BIT ? combined.bitfield.dword
14062
0
              : combined.bitfield.word)
14063
0
             && !add_prefix (DATA_PREFIX_OPCODE))
14064
0
      goto done;
14065
0
  }
14066
0
      else if (!i.tm.opcode_modifier.vexw)
14067
0
  {
14068
0
    if (flag_code == CODE_64BIT)
14069
0
      {
14070
0
        if (combined.bitfield.qword)
14071
0
          i.tm.opcode_modifier.vexw = VEXW1;
14072
0
        else if (combined.bitfield.dword)
14073
0
          i.tm.opcode_modifier.vexw = VEXW0;
14074
0
      }
14075
14076
0
    if (!i.tm.opcode_modifier.vexw)
14077
0
      i.tm.opcode_modifier.vexw = VEXWIG;
14078
0
  }
14079
14080
0
      if (vex || xop)
14081
0
  {
14082
0
    if (!i.tm.opcode_modifier.vex)
14083
0
      {
14084
0
        if (combined.bitfield.ymmword)
14085
0
          i.tm.opcode_modifier.vex = VEX256;
14086
0
        else if (combined.bitfield.xmmword)
14087
0
          i.tm.opcode_modifier.vex = VEX128;
14088
0
      }
14089
0
  }
14090
0
      else if (evex)
14091
0
  {
14092
0
    if (!i.tm.opcode_modifier.evex)
14093
0
      {
14094
        /* Do _not_ consider AVX512VL here.  */
14095
0
        if (combined.bitfield.zmmword)
14096
0
          i.tm.opcode_modifier.evex = EVEX512;
14097
0
        else if (combined.bitfield.ymmword)
14098
0
          i.tm.opcode_modifier.evex = EVEX256;
14099
0
        else if (combined.bitfield.xmmword)
14100
0
          i.tm.opcode_modifier.evex = EVEX128;
14101
0
      }
14102
14103
0
    if (i.memshift >= 32)
14104
0
      {
14105
0
        unsigned int n = 0;
14106
14107
0
        switch (i.tm.opcode_modifier.evex)
14108
0
    {
14109
0
    case EVEX512: n = 64; break;
14110
0
    case EVEX256: n = 32; break;
14111
0
    case EVEX128: n = 16; break;
14112
0
    }
14113
14114
0
        if (i.broadcast.type)
14115
0
    n /= i.broadcast.type;
14116
14117
0
        if (n > 0)
14118
0
    for (i.memshift = 0; !(n & 1); n >>= 1)
14119
0
      ++i.memshift;
14120
0
        else if (disp_exp != NULL && disp_exp->X_op == O_constant
14121
0
           && disp_exp->X_add_number != 0
14122
0
           && pp.disp_encoding != disp_encoding_32bit)
14123
0
    {
14124
0
      if (!quiet_warnings)
14125
0
        as_warn ("cannot determine memory operand size");
14126
0
      pp.disp_encoding = disp_encoding_32bit;
14127
0
    }
14128
0
      }
14129
0
  }
14130
14131
0
      if (i.memshift >= 32)
14132
0
  i.memshift = 0;
14133
0
      else if (!evex)
14134
0
  pp.encoding = encoding_error;
14135
14136
0
      if (i.disp_operands && !optimize_disp (&i.tm))
14137
0
  goto done;
14138
14139
      /* Establish size for immediate operands.  */
14140
0
      for (j = 0; j < i.imm_operands; ++j)
14141
0
  {
14142
0
    expressionS *expP = i.op[j].imms;
14143
14144
0
    gas_assert (operand_type_check (i.types[j], imm));
14145
0
    operand_type_set (&i.types[j], 0);
14146
14147
0
    if (i.imm_bits[j] > 32)
14148
0
      i.types[j].bitfield.imm64 = 1;
14149
0
    else if (i.imm_bits[j] > 16)
14150
0
      {
14151
0
        if (flag_code == CODE_64BIT && (i.flags[j] & Operand_Signed))
14152
0
    i.types[j].bitfield.imm32s = 1;
14153
0
        else
14154
0
    i.types[j].bitfield.imm32 = 1;
14155
0
      }
14156
0
    else if (i.imm_bits[j] > 8)
14157
0
      i.types[j].bitfield.imm16 = 1;
14158
0
    else if (i.imm_bits[j] > 0)
14159
0
      {
14160
0
        if (i.flags[j] & Operand_Signed)
14161
0
    i.types[j].bitfield.imm8s = 1;
14162
0
        else
14163
0
    i.types[j].bitfield.imm8 = 1;
14164
0
      }
14165
0
    else if (expP->X_op == O_constant)
14166
0
      {
14167
0
        i.types[j] = smallest_imm_type (expP->X_add_number);
14168
0
        i.types[j].bitfield.imm1 = 0;
14169
        /* Oddly enough imm_size() checks imm64 first, so the bit needs
14170
     zapping since smallest_imm_type() sets it unconditionally.  */
14171
0
        if (flag_code != CODE_64BIT)
14172
0
    {
14173
0
      i.types[j].bitfield.imm64 = 0;
14174
0
      i.types[j].bitfield.imm32s = 0;
14175
0
      i.types[j].bitfield.imm32 = 1;
14176
0
    }
14177
0
        else if (i.types[j].bitfield.imm32 || i.types[j].bitfield.imm32s)
14178
0
    i.types[j].bitfield.imm64 = 0;
14179
0
      }
14180
0
    else
14181
      /* Non-constant expressions are sized heuristically.  */
14182
0
      switch (flag_code)
14183
0
        {
14184
0
        case CODE_64BIT: i.types[j].bitfield.imm32s = 1; break;
14185
0
        case CODE_32BIT: i.types[j].bitfield.imm32 = 1; break;
14186
0
        case CODE_16BIT: i.types[j].bitfield.imm16 = 1; break;
14187
0
        }
14188
0
  }
14189
14190
0
      for (j = 0; j < i.operands; ++j)
14191
0
  i.tm.operand_types[j] = i.types[j];
14192
14193
0
      process_operands ();
14194
0
    }
14195
14196
  /* Don't set opcode until after processing operands, to avoid any
14197
     potential special casing there.  */
14198
0
  i.tm.base_opcode |= val;
14199
14200
0
  if (pp.encoding == encoding_error
14201
0
      || (pp.encoding != encoding_evex
14202
0
    ? i.broadcast.type || i.broadcast.bytes
14203
0
      || i.rounding.type != rc_none
14204
0
      || i.mask.reg
14205
0
    : (i.mem_operands && i.rounding.type != rc_none)
14206
0
      || ((i.broadcast.type || i.broadcast.bytes)
14207
0
    && !(i.flags[i.broadcast.operand] & Operand_Mem))))
14208
0
    {
14209
0
      as_bad (_("conflicting .insn operands"));
14210
0
      goto done;
14211
0
    }
14212
14213
0
  if (vex || xop)
14214
0
    {
14215
0
      if (is_apx_evex_encoding ())
14216
0
  {
14217
0
    as_bad (_("APX functionality cannot be used with %s encodings"),
14218
0
      vex ? "VEX" : "XOP");
14219
0
    goto done;
14220
0
  }
14221
14222
0
      if (!i.tm.opcode_modifier.vex)
14223
0
  i.tm.opcode_modifier.vex = VEXScalar; /* LIG */
14224
14225
0
      build_vex_prefix (NULL);
14226
0
      i.rex &= REX_OPCODE;
14227
0
    }
14228
0
  else if (evex)
14229
0
    {
14230
0
      if (!i.tm.opcode_modifier.evex)
14231
0
  i.tm.opcode_modifier.evex = EVEXLIG;
14232
14233
      /* To keep earlier .insn uses working as far as possible, take the
14234
   legacy path when opcode space is 4 bits wide (impossible to encode in
14235
   extended EVEX), and when no "extended" syntax elements are used.  */
14236
0
      if ((!is_apx_evex_encoding () || i.insn_opcode_space > 7)
14237
0
    && evex == evex_basic
14238
0
    && !i.tm.opcode_modifier.operandconstraint)
14239
0
  build_evex_prefix ();
14240
0
      else if (i.insn_opcode_space > 7)
14241
0
  {
14242
0
    as_bad (_("opcode space cannot be larger than 7"));
14243
0
    goto done;
14244
0
  }
14245
0
      else if (evex == evex_nd && (i.broadcast.type || i.broadcast.bytes))
14246
0
  {
14247
0
    as_bad (_("ND and broadcast cannot be used at the same time"));
14248
0
    goto done;
14249
0
  }
14250
0
      else if (pp.has_nf && i.mask.reg)
14251
0
  {
14252
0
    as_bad (_("{nf} and masking cannot be used at the same time"));
14253
0
    goto done;
14254
0
  }
14255
0
      else if (i.tm.opcode_modifier.operandconstraint == SCC
14256
0
         && (pp.has_nf || i.mask.reg))
14257
0
  {
14258
0
    as_bad (_("SCC cannot be used at the same time {nf} / masking"));
14259
0
    goto done;
14260
0
  }
14261
0
      else if (!build_apx_evex_prefix (evex == evex_nd))
14262
0
  goto done;
14263
0
      i.rex &= REX_OPCODE;
14264
0
    }
14265
0
  else
14266
0
    establish_rex ();
14267
14268
0
  last_insn = &seg_info(now_seg)->tc_segment_info_data.last_insn;
14269
0
  output_insn (last_insn);
14270
0
  last_insn->kind = last_insn_directive;
14271
0
  last_insn->name = ".insn directive";
14272
0
  last_insn->file = as_where (&last_insn->line);
14273
14274
0
#ifdef OBJ_ELF
14275
  /* PS: SCFI is enabled only for System V AMD64 ABI.  The ABI check has been
14276
     performed in i386_target_format.  */
14277
0
  if (flag_synth_cfi)
14278
0
    as_bad (_("SCFI: hand-crafting instructions not supported"));
14279
0
#endif
14280
14281
0
 done:
14282
0
  *saved_ilp = saved_char;
14283
0
  input_line_pointer = line;
14284
14285
0
  demand_empty_rest_of_line ();
14286
14287
  /* Make sure dot_insn() won't yield "true" anymore.  */
14288
0
  i.tm.mnem_off = 0;
14289
14290
0
  current_templates.start = NULL;
14291
0
  memset (&pp, 0, sizeof (pp));
14292
0
}
14293
14294
#ifdef TE_PE
14295
static void
14296
pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
14297
{
14298
  expressionS exp;
14299
14300
  do
14301
    {
14302
      expression (&exp);
14303
      if (exp.X_op == O_symbol)
14304
  exp.X_op = O_secrel;
14305
14306
      emit_expr (&exp, 4);
14307
    }
14308
  while (*input_line_pointer++ == ',');
14309
14310
  input_line_pointer--;
14311
  demand_empty_rest_of_line ();
14312
}
14313
14314
static void
14315
pe_directive_secidx (int dummy ATTRIBUTE_UNUSED)
14316
{
14317
  expressionS exp;
14318
14319
  do
14320
    {
14321
      expression (&exp);
14322
      if (exp.X_op == O_symbol)
14323
  exp.X_op = O_secidx;
14324
14325
      emit_expr (&exp, 2);
14326
    }
14327
  while (*input_line_pointer++ == ',');
14328
14329
  input_line_pointer--;
14330
  demand_empty_rest_of_line ();
14331
}
14332
#endif
14333
14334
/* Handle Rounding Control / SAE specifiers.  */
14335
14336
static char *
14337
RC_SAE_specifier (const char *pstr)
14338
0
{
14339
0
  unsigned int j;
14340
14341
0
  for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++)
14342
0
    {
14343
0
      if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len))
14344
0
  {
14345
0
    if (i.rounding.type != rc_none)
14346
0
      {
14347
0
        as_bad (_("duplicated `{%s}'"), RC_NamesTable[j].name);
14348
0
        return NULL;
14349
0
      }
14350
14351
0
    switch (pp.encoding)
14352
0
      {
14353
0
      case encoding_default:
14354
0
      case encoding_egpr:
14355
0
        pp.encoding = encoding_evex512;
14356
0
        break;
14357
0
      case encoding_evex:
14358
0
      case encoding_evex512:
14359
0
        break;
14360
0
      default:
14361
0
        return NULL;
14362
0
      }
14363
14364
0
    i.rounding.type = RC_NamesTable[j].type;
14365
14366
0
    return (char *)(pstr + RC_NamesTable[j].len);
14367
0
  }
14368
0
    }
14369
14370
0
  return NULL;
14371
0
}
14372
14373
/* Handle Vector operations.  */
14374
14375
static char *
14376
check_VecOperations (char *op_string)
14377
0
{
14378
0
  const reg_entry *mask;
14379
0
  const char *saved;
14380
0
  char *end_op;
14381
14382
0
  while (*op_string)
14383
0
    {
14384
0
      saved = op_string;
14385
0
      if (*op_string == '{')
14386
0
  {
14387
0
    op_string++;
14388
0
    if (is_whitespace (*op_string))
14389
0
      op_string++;
14390
14391
    /* Check broadcasts.  */
14392
0
    if (startswith (op_string, "1to"))
14393
0
      {
14394
0
        unsigned int bcst_type;
14395
14396
0
        if (i.broadcast.type)
14397
0
    goto duplicated_vec_op;
14398
14399
0
        op_string += 3;
14400
0
        if (*op_string == '8')
14401
0
    bcst_type = 8;
14402
0
        else if (*op_string == '4')
14403
0
    bcst_type = 4;
14404
0
        else if (*op_string == '2')
14405
0
    bcst_type = 2;
14406
0
        else if (*op_string == '1'
14407
0
           && *(op_string+1) == '6')
14408
0
    {
14409
0
      bcst_type = 16;
14410
0
      op_string++;
14411
0
    }
14412
0
        else if (*op_string == '3'
14413
0
           && *(op_string+1) == '2')
14414
0
    {
14415
0
      bcst_type = 32;
14416
0
      op_string++;
14417
0
    }
14418
0
        else
14419
0
    {
14420
0
      as_bad (_("Unsupported broadcast: `%s'"), saved);
14421
0
      return NULL;
14422
0
    }
14423
0
        op_string++;
14424
14425
0
        switch (pp.encoding)
14426
0
    {
14427
0
    case encoding_default:
14428
0
    case encoding_egpr:
14429
0
      pp.encoding = encoding_evex;
14430
0
      break;
14431
0
    case encoding_evex:
14432
0
    case encoding_evex512:
14433
0
      break;
14434
0
    default:
14435
0
      goto unknown_vec_op;
14436
0
    }
14437
14438
0
        i.broadcast.type = bcst_type;
14439
0
        i.broadcast.operand = this_operand;
14440
14441
        /* For .insn a data size specifier may be appended.  */
14442
0
        if (dot_insn () && *op_string == ':')
14443
0
    goto dot_insn_modifier;
14444
0
      }
14445
    /* Check .insn special cases.  */
14446
0
    else if (dot_insn () && *op_string == ':')
14447
0
      {
14448
0
      dot_insn_modifier:
14449
0
        switch (op_string[1])
14450
0
    {
14451
0
      unsigned long n;
14452
14453
0
    case 'd':
14454
0
      if (i.memshift < 32)
14455
0
        goto duplicated_vec_op;
14456
14457
0
      n = strtoul (op_string + 2, &end_op, 0);
14458
0
      if (n)
14459
0
        for (i.memshift = 0; !(n & 1); n >>= 1)
14460
0
          ++i.memshift;
14461
0
      if (i.memshift < 32 && n == 1)
14462
0
        op_string = end_op;
14463
0
      break;
14464
14465
0
    case 's': case 'u':
14466
      /* This isn't really a "vector" operation, but a sign/size
14467
         specifier for immediate operands of .insn.  Note that AT&T
14468
         syntax handles the same in i386_immediate().  */
14469
0
      if (!intel_syntax)
14470
0
        break;
14471
14472
0
      if (i.imm_bits[this_operand])
14473
0
        goto duplicated_vec_op;
14474
14475
0
      n = strtoul (op_string + 2, &end_op, 0);
14476
0
      if (n && n <= (flag_code == CODE_64BIT ? 64 : 32))
14477
0
        {
14478
0
          i.imm_bits[this_operand] = n;
14479
0
          if (op_string[1] == 's')
14480
0
      i.flags[this_operand] |= Operand_Signed;
14481
0
          op_string = end_op;
14482
0
        }
14483
0
      break;
14484
0
    }
14485
0
      }
14486
    /* Check masking operation.  */
14487
0
    else if ((mask = parse_register (op_string, &end_op)) != NULL)
14488
0
      {
14489
0
        if (mask == &bad_reg)
14490
0
    return NULL;
14491
14492
        /* k0 can't be used for write mask.  */
14493
0
        if (mask->reg_type.bitfield.class != RegMask || !mask->reg_num)
14494
0
    {
14495
0
      as_bad (_("`%s%s' can't be used for write mask"),
14496
0
        register_prefix, mask->reg_name);
14497
0
      return NULL;
14498
0
    }
14499
14500
0
        if (!i.mask.reg)
14501
0
    {
14502
0
      i.mask.reg = mask;
14503
0
      i.mask.operand = this_operand;
14504
0
    }
14505
0
        else if (i.mask.reg->reg_num)
14506
0
    goto duplicated_vec_op;
14507
0
        else
14508
0
    {
14509
0
      i.mask.reg = mask;
14510
14511
      /* Only "{z}" is allowed here.  No need to check
14512
         zeroing mask explicitly.  */
14513
0
      if (i.mask.operand != (unsigned int) this_operand)
14514
0
        {
14515
0
          as_bad (_("invalid write mask `%s'"), saved);
14516
0
          return NULL;
14517
0
        }
14518
0
    }
14519
14520
0
        op_string = end_op;
14521
0
      }
14522
    /* Check zeroing-flag for masking operation.  */
14523
0
    else if (*op_string == 'z')
14524
0
      {
14525
0
        if (!i.mask.reg)
14526
0
    {
14527
0
      i.mask.reg = reg_k0;
14528
0
      i.mask.zeroing = 1;
14529
0
      i.mask.operand = this_operand;
14530
0
    }
14531
0
        else
14532
0
    {
14533
0
      if (i.mask.zeroing)
14534
0
        {
14535
0
        duplicated_vec_op:
14536
0
          as_bad (_("duplicated `%s'"), saved);
14537
0
          return NULL;
14538
0
        }
14539
14540
0
      i.mask.zeroing = 1;
14541
14542
      /* Only "{%k}" is allowed here.  No need to check mask
14543
         register explicitly.  */
14544
0
      if (i.mask.operand != (unsigned int) this_operand)
14545
0
        {
14546
0
          as_bad (_("invalid zeroing-masking `%s'"),
14547
0
            saved);
14548
0
          return NULL;
14549
0
        }
14550
0
    }
14551
14552
0
        op_string++;
14553
0
      }
14554
0
    else if (intel_syntax
14555
0
       && (op_string = RC_SAE_specifier (op_string)) != NULL)
14556
0
      i.rounding.modifier = true;
14557
0
    else
14558
0
      goto unknown_vec_op;
14559
14560
0
    if (is_whitespace (*op_string))
14561
0
      op_string++;
14562
0
    if (*op_string != '}')
14563
0
      {
14564
0
        as_bad (_("missing `}' in `%s'"), saved);
14565
0
        return NULL;
14566
0
      }
14567
0
    op_string++;
14568
14569
0
    if (is_whitespace (*op_string))
14570
0
      ++op_string;
14571
14572
0
    continue;
14573
0
  }
14574
0
    unknown_vec_op:
14575
      /* We don't know this one.  */
14576
0
      as_bad (_("unknown vector operation: `%s'"), saved);
14577
0
      return NULL;
14578
0
    }
14579
14580
0
  if (i.mask.reg && i.mask.zeroing && !i.mask.reg->reg_num)
14581
0
    {
14582
0
      as_bad (_("zeroing-masking only allowed with write mask"));
14583
0
      return NULL;
14584
0
    }
14585
14586
0
  return op_string;
14587
0
}
14588
14589
static int
14590
i386_immediate (char *imm_start)
14591
0
{
14592
0
  char *save_input_line_pointer;
14593
0
  char *gotfree_input_line;
14594
0
  segT exp_seg = 0;
14595
0
  expressionS *exp;
14596
0
  i386_operand_type types;
14597
14598
0
  operand_type_set (&types, ~0);
14599
14600
0
  if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
14601
0
    {
14602
0
      as_bad (_("at most %d immediate operands are allowed"),
14603
0
        MAX_IMMEDIATE_OPERANDS);
14604
0
      return 0;
14605
0
    }
14606
14607
0
  exp = &im_expressions[i.imm_operands++];
14608
0
  i.op[this_operand].imms = exp;
14609
14610
0
  if (is_whitespace (*imm_start))
14611
0
    ++imm_start;
14612
14613
0
  save_input_line_pointer = input_line_pointer;
14614
0
  input_line_pointer = imm_start;
14615
14616
0
  gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
14617
0
  if (gotfree_input_line)
14618
0
    input_line_pointer = gotfree_input_line;
14619
14620
0
  expr_mode = expr_operator_none;
14621
0
  exp_seg = expression (exp);
14622
14623
  /* For .insn immediates there may be a size specifier.  */
14624
0
  if (dot_insn () && *input_line_pointer == '{' && input_line_pointer[1] == ':'
14625
0
      && (input_line_pointer[2] == 's' || input_line_pointer[2] == 'u'))
14626
0
    {
14627
0
      char *e;
14628
0
      unsigned long n = strtoul (input_line_pointer + 3, &e, 0);
14629
14630
0
      if (*e == '}' && n && n <= (flag_code == CODE_64BIT ? 64 : 32))
14631
0
  {
14632
0
    i.imm_bits[this_operand] = n;
14633
0
    if (input_line_pointer[2] == 's')
14634
0
      i.flags[this_operand] |= Operand_Signed;
14635
0
    input_line_pointer = e + 1;
14636
0
  }
14637
0
    }
14638
14639
0
  SKIP_WHITESPACE ();
14640
0
  if (*input_line_pointer)
14641
0
    as_bad (_("junk `%s' after expression"), input_line_pointer);
14642
14643
0
  input_line_pointer = save_input_line_pointer;
14644
0
  if (gotfree_input_line)
14645
0
    {
14646
0
      free (gotfree_input_line);
14647
14648
0
      if (exp->X_op == O_constant)
14649
0
  exp->X_op = O_illegal;
14650
0
    }
14651
14652
0
  if (exp_seg == reg_section)
14653
0
    {
14654
0
      as_bad (_("illegal immediate register operand %s"), imm_start);
14655
0
      return 0;
14656
0
    }
14657
14658
0
  return i386_finalize_immediate (exp_seg, exp, types, imm_start);
14659
0
}
14660
14661
static int
14662
i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
14663
       i386_operand_type types, const char *imm_start)
14664
0
{
14665
0
  if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
14666
0
    {
14667
0
      if (imm_start)
14668
0
  as_bad (_("missing or invalid immediate expression `%s'"),
14669
0
    imm_start);
14670
0
      return 0;
14671
0
    }
14672
0
  else if (exp->X_op == O_constant)
14673
0
    {
14674
      /* Size it properly later.  */
14675
0
      i.types[this_operand].bitfield.imm64 = 1;
14676
14677
      /* If not 64bit, sign/zero extend val, to account for wraparound
14678
   when !BFD64.  */
14679
0
      if (expr_mode == expr_operator_present
14680
0
    && flag_code != CODE_64BIT && !object_64bit)
14681
0
  exp->X_add_number = extend_to_32bit_address (exp->X_add_number);
14682
0
    }
14683
#ifdef OBJ_AOUT
14684
  else if (exp_seg != absolute_section
14685
     && exp_seg != text_section
14686
     && exp_seg != data_section
14687
     && exp_seg != bss_section
14688
     && exp_seg != undefined_section
14689
     && !bfd_is_com_section (exp_seg))
14690
    {
14691
      as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
14692
      return 0;
14693
    }
14694
#endif
14695
0
  else
14696
0
    {
14697
      /* This is an address.  The size of the address will be
14698
   determined later, depending on destination register,
14699
   suffix, or the default for the section.  */
14700
0
      i.types[this_operand].bitfield.imm8 = 1;
14701
0
      i.types[this_operand].bitfield.imm16 = 1;
14702
0
      i.types[this_operand].bitfield.imm32 = 1;
14703
0
      i.types[this_operand].bitfield.imm32s = 1;
14704
0
      i.types[this_operand].bitfield.imm64 = 1;
14705
0
      i.types[this_operand] = operand_type_and (i.types[this_operand],
14706
0
            types);
14707
0
    }
14708
14709
0
  return 1;
14710
0
}
14711
14712
static char *
14713
i386_scale (char *scale)
14714
0
{
14715
0
  offsetT val;
14716
0
  char *save = input_line_pointer;
14717
14718
0
  input_line_pointer = scale;
14719
0
  val = get_absolute_expression ();
14720
14721
0
  switch (val)
14722
0
    {
14723
0
    case 1:
14724
0
      i.log2_scale_factor = 0;
14725
0
      break;
14726
0
    case 2:
14727
0
      i.log2_scale_factor = 1;
14728
0
      break;
14729
0
    case 4:
14730
0
      i.log2_scale_factor = 2;
14731
0
      break;
14732
0
    case 8:
14733
0
      i.log2_scale_factor = 3;
14734
0
      break;
14735
0
    default:
14736
0
      {
14737
0
  char sep = *input_line_pointer;
14738
14739
0
  *input_line_pointer = '\0';
14740
0
  as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
14741
0
    scale);
14742
0
  *input_line_pointer = sep;
14743
0
  input_line_pointer = save;
14744
0
  return NULL;
14745
0
      }
14746
0
    }
14747
0
  if (i.log2_scale_factor != 0 && i.index_reg == 0)
14748
0
    {
14749
0
      as_warn (_("scale factor of %d without an index register"),
14750
0
         1 << i.log2_scale_factor);
14751
0
      i.log2_scale_factor = 0;
14752
0
    }
14753
0
  scale = input_line_pointer;
14754
0
  input_line_pointer = save;
14755
0
  return scale;
14756
0
}
14757
14758
static int
14759
i386_displacement (char *disp_start, char *disp_end)
14760
0
{
14761
0
  expressionS *exp;
14762
0
  segT exp_seg = 0;
14763
0
  char *save_input_line_pointer;
14764
0
  char *gotfree_input_line;
14765
0
  int override;
14766
0
  i386_operand_type bigdisp, types = anydisp;
14767
0
  int ret;
14768
14769
0
  if (i.disp_operands == MAX_MEMORY_OPERANDS)
14770
0
    {
14771
0
      as_bad (_("at most %d displacement operands are allowed"),
14772
0
        MAX_MEMORY_OPERANDS);
14773
0
      return 0;
14774
0
    }
14775
14776
0
  operand_type_set (&bigdisp, 0);
14777
0
  if (i.jumpabsolute
14778
0
      || i.types[this_operand].bitfield.baseindex
14779
0
      || (current_templates.start->opcode_modifier.jump != JUMP
14780
0
    && current_templates.start->opcode_modifier.jump != JUMP_DWORD))
14781
0
    {
14782
0
      i386_addressing_mode ();
14783
0
      override = (i.prefix[ADDR_PREFIX] != 0);
14784
0
      if (flag_code == CODE_64BIT)
14785
0
  {
14786
0
    bigdisp.bitfield.disp32 = 1;
14787
0
    if (!override)
14788
0
      bigdisp.bitfield.disp64 = 1;
14789
0
  }
14790
0
      else if ((flag_code == CODE_16BIT) ^ override)
14791
0
    bigdisp.bitfield.disp16 = 1;
14792
0
      else
14793
0
    bigdisp.bitfield.disp32 = 1;
14794
0
    }
14795
0
  else
14796
0
    {
14797
      /* For PC-relative branches, the width of the displacement may be
14798
   dependent upon data size, but is never dependent upon address size.
14799
   Also make sure to not unintentionally match against a non-PC-relative
14800
   branch template.  */
14801
0
      const insn_template *t = current_templates.start;
14802
0
      bool has_intel64 = false;
14803
14804
0
      while (++t < current_templates.end)
14805
0
  {
14806
0
    if (t->opcode_modifier.jump
14807
0
        != current_templates.start->opcode_modifier.jump)
14808
0
      break;
14809
0
    if ((t->opcode_modifier.isa64 >= INTEL64))
14810
0
      has_intel64 = true;
14811
0
  }
14812
0
      current_templates.end = t;
14813
14814
0
      override = (i.prefix[DATA_PREFIX] != 0);
14815
0
      if (flag_code == CODE_64BIT)
14816
0
  {
14817
0
    if ((override || i.suffix == WORD_MNEM_SUFFIX)
14818
0
        && (!intel64 || !has_intel64))
14819
0
      bigdisp.bitfield.disp16 = 1;
14820
0
    else
14821
0
      bigdisp.bitfield.disp32 = 1;
14822
0
  }
14823
0
      else
14824
0
  {
14825
0
    if (!override)
14826
0
      override = (i.suffix == (flag_code != CODE_16BIT
14827
0
             ? WORD_MNEM_SUFFIX
14828
0
             : LONG_MNEM_SUFFIX));
14829
0
    bigdisp.bitfield.disp32 = 1;
14830
0
    if ((flag_code == CODE_16BIT) ^ override)
14831
0
      {
14832
0
        bigdisp.bitfield.disp32 = 0;
14833
0
        bigdisp.bitfield.disp16 = 1;
14834
0
      }
14835
0
  }
14836
0
    }
14837
0
  i.types[this_operand] = operand_type_or (i.types[this_operand],
14838
0
             bigdisp);
14839
14840
0
  exp = &disp_expressions[i.disp_operands];
14841
0
  i.op[this_operand].disps = exp;
14842
0
  i.disp_operands++;
14843
0
  save_input_line_pointer = input_line_pointer;
14844
0
  input_line_pointer = disp_start;
14845
0
  END_STRING_AND_SAVE (disp_end);
14846
14847
0
#ifndef GCC_ASM_O_HACK
14848
0
#define GCC_ASM_O_HACK 0
14849
0
#endif
14850
#if GCC_ASM_O_HACK
14851
  END_STRING_AND_SAVE (disp_end + 1);
14852
  if (i.types[this_operand].bitfield.baseIndex
14853
      && displacement_string_end[-1] == '+')
14854
    {
14855
      /* This hack is to avoid a warning when using the "o"
14856
   constraint within gcc asm statements.
14857
   For instance:
14858
14859
   #define _set_tssldt_desc(n,addr,limit,type) \
14860
   __asm__ __volatile__ ( \
14861
   "movw %w2,%0\n\t" \
14862
   "movw %w1,2+%0\n\t" \
14863
   "rorl $16,%1\n\t" \
14864
   "movb %b1,4+%0\n\t" \
14865
   "movb %4,5+%0\n\t" \
14866
   "movb $0,6+%0\n\t" \
14867
   "movb %h1,7+%0\n\t" \
14868
   "rorl $16,%1" \
14869
   : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
14870
14871
   This works great except that the output assembler ends
14872
   up looking a bit weird if it turns out that there is
14873
   no offset.  You end up producing code that looks like:
14874
14875
   #APP
14876
   movw $235,(%eax)
14877
   movw %dx,2+(%eax)
14878
   rorl $16,%edx
14879
   movb %dl,4+(%eax)
14880
   movb $137,5+(%eax)
14881
   movb $0,6+(%eax)
14882
   movb %dh,7+(%eax)
14883
   rorl $16,%edx
14884
   #NO_APP
14885
14886
   So here we provide the missing zero.  */
14887
14888
      *displacement_string_end = '0';
14889
    }
14890
#endif
14891
0
  gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
14892
0
  if (gotfree_input_line)
14893
0
    input_line_pointer = gotfree_input_line;
14894
14895
0
  expr_mode = expr_operator_none;
14896
0
  exp_seg = expression (exp);
14897
14898
0
  SKIP_WHITESPACE ();
14899
0
  if (*input_line_pointer)
14900
0
    as_bad (_("junk `%s' after expression"), input_line_pointer);
14901
#if GCC_ASM_O_HACK
14902
  RESTORE_END_STRING (disp_end + 1);
14903
#endif
14904
0
  input_line_pointer = save_input_line_pointer;
14905
0
  if (gotfree_input_line)
14906
0
    {
14907
0
      free (gotfree_input_line);
14908
14909
0
      if (exp->X_op == O_constant || exp->X_op == O_register)
14910
0
  exp->X_op = O_illegal;
14911
0
    }
14912
14913
0
  ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
14914
14915
0
  RESTORE_END_STRING (disp_end);
14916
14917
0
  return ret;
14918
0
}
14919
14920
static int
14921
i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
14922
          i386_operand_type types, const char *disp_start)
14923
0
{
14924
0
  int ret = 1;
14925
14926
  /* We do this to make sure that the section symbol is in
14927
     the symbol table.  We will ultimately change the relocation
14928
     to be relative to the beginning of the section.  */
14929
0
  if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
14930
0
      || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
14931
0
      || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
14932
0
    {
14933
0
      if (exp->X_op != O_symbol)
14934
0
  goto inv_disp;
14935
14936
0
      if (S_IS_LOCAL (exp->X_add_symbol)
14937
0
    && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
14938
0
    && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
14939
0
  section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
14940
0
      exp->X_op = O_subtract;
14941
0
      exp->X_op_symbol = GOT_symbol;
14942
0
      if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
14943
0
  i.reloc[this_operand] = BFD_RELOC_32_PCREL;
14944
0
      else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
14945
0
  i.reloc[this_operand] = BFD_RELOC_64;
14946
0
      else
14947
0
  i.reloc[this_operand] = BFD_RELOC_32;
14948
0
    }
14949
14950
0
  else if (exp->X_op == O_absent
14951
0
     || exp->X_op == O_illegal
14952
0
     || exp->X_op == O_big)
14953
0
    {
14954
0
    inv_disp:
14955
0
      as_bad (_("missing or invalid displacement expression `%s'"),
14956
0
        disp_start);
14957
0
      ret = 0;
14958
0
    }
14959
14960
0
  else if (exp->X_op == O_constant)
14961
0
    {
14962
      /* Sizing gets taken care of by optimize_disp().
14963
14964
   If not 64bit, sign/zero extend val, to account for wraparound
14965
   when !BFD64.  */
14966
0
      if (expr_mode == expr_operator_present
14967
0
    && flag_code != CODE_64BIT && !object_64bit)
14968
0
  exp->X_add_number = extend_to_32bit_address (exp->X_add_number);
14969
0
    }
14970
14971
#ifdef OBJ_AOUT
14972
  else if (exp_seg != absolute_section
14973
     && exp_seg != text_section
14974
     && exp_seg != data_section
14975
     && exp_seg != bss_section
14976
     && exp_seg != undefined_section
14977
     && !bfd_is_com_section (exp_seg))
14978
    {
14979
      as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
14980
      ret = 0;
14981
    }
14982
#endif
14983
14984
0
  else if (current_templates.start->opcode_modifier.jump == JUMP_BYTE)
14985
0
    i.types[this_operand].bitfield.disp8 = 1;
14986
14987
  /* Check if this is a displacement only operand.  */
14988
0
  if (!i.types[this_operand].bitfield.baseindex)
14989
0
    i.types[this_operand] =
14990
0
      operand_type_or (operand_type_and_not (i.types[this_operand], anydisp),
14991
0
           operand_type_and (i.types[this_operand], types));
14992
14993
0
  return ret;
14994
0
}
14995
14996
/* Return the active addressing mode, taking address override and
14997
   registers forming the address into consideration.  Update the
14998
   address override prefix if necessary.  */
14999
15000
static enum flag_code
15001
i386_addressing_mode (void)
15002
0
{
15003
0
  enum flag_code addr_mode;
15004
15005
0
  if (i.prefix[ADDR_PREFIX])
15006
0
    addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
15007
0
  else if (flag_code == CODE_16BIT
15008
0
     && is_cpu (current_templates.start, CpuMPX)
15009
     /* Avoid replacing the "16-bit addressing not allowed" diagnostic
15010
        from md_assemble() by "is not a valid base/index expression"
15011
        when there is a base and/or index.  */
15012
0
     && !i.types[this_operand].bitfield.baseindex)
15013
0
    {
15014
      /* MPX insn memory operands with neither base nor index must be forced
15015
   to use 32-bit addressing in 16-bit mode.  */
15016
0
      addr_mode = CODE_32BIT;
15017
0
      i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
15018
0
      ++i.prefixes;
15019
0
      gas_assert (!i.types[this_operand].bitfield.disp16);
15020
0
      gas_assert (!i.types[this_operand].bitfield.disp32);
15021
0
    }
15022
0
  else
15023
0
    {
15024
0
      addr_mode = flag_code;
15025
15026
0
#if INFER_ADDR_PREFIX
15027
0
      if (i.mem_operands == 0)
15028
0
  {
15029
    /* Infer address prefix from the first memory operand.  */
15030
0
    const reg_entry *addr_reg = i.base_reg;
15031
15032
0
    if (addr_reg == NULL)
15033
0
      addr_reg = i.index_reg;
15034
15035
0
    if (addr_reg)
15036
0
      {
15037
0
        if (addr_reg->reg_type.bitfield.dword)
15038
0
    addr_mode = CODE_32BIT;
15039
0
        else if (flag_code != CODE_64BIT
15040
0
           && addr_reg->reg_type.bitfield.word)
15041
0
    addr_mode = CODE_16BIT;
15042
15043
0
        if (addr_mode != flag_code)
15044
0
    {
15045
0
      i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
15046
0
      i.prefixes += 1;
15047
      /* Change the size of any displacement too.  At most one
15048
         of Disp16 or Disp32 is set.
15049
         FIXME.  There doesn't seem to be any real need for
15050
         separate Disp16 and Disp32 flags.  The same goes for
15051
         Imm16 and Imm32.  Removing them would probably clean
15052
         up the code quite a lot.  */
15053
0
      if (flag_code != CODE_64BIT
15054
0
          && (i.types[this_operand].bitfield.disp16
15055
0
        || i.types[this_operand].bitfield.disp32))
15056
0
        {
15057
0
          static const i386_operand_type disp16_32 = {
15058
0
      .bitfield = { .disp16 = 1, .disp32 = 1 }
15059
0
          };
15060
15061
0
          i.types[this_operand]
15062
0
      = operand_type_xor (i.types[this_operand], disp16_32);
15063
0
        }
15064
0
    }
15065
0
      }
15066
0
  }
15067
0
#endif
15068
0
    }
15069
15070
0
  return addr_mode;
15071
0
}
15072
15073
/* Make sure the memory operand we've been dealt is valid.
15074
   Return 1 on success, 0 on a failure.  */
15075
15076
static int
15077
i386_index_check (const char *operand_string)
15078
0
{
15079
0
  const char *kind = "base/index";
15080
0
  enum flag_code addr_mode = i386_addressing_mode ();
15081
0
  const insn_template *t = current_templates.end - 1;
15082
15083
0
  if (t->opcode_modifier.isstring)
15084
0
    {
15085
      /* Memory operands of string insns are special in that they only allow
15086
   a single register (rDI or rSI) as their memory address.  */
15087
0
      const reg_entry *expected_reg;
15088
0
      static const char di_si[][2][4] =
15089
0
  {
15090
0
    { "esi", "edi" },
15091
0
    { "si", "di" },
15092
0
    { "rsi", "rdi" }
15093
0
  };
15094
      /* For a few other insns with fixed register addressing we (ab)use the
15095
   IsString attribute as well.  */
15096
0
      static const char loregs[][4][4] =
15097
0
  {
15098
0
    { "eax", "ecx", "edx", "ebx" },
15099
0
    {  "ax",  "cx",  "dx",  "bx" },
15100
0
    { "rax", "rcx", "rdx", "rbx" }
15101
0
  };
15102
15103
0
      kind = "string address";
15104
15105
0
      if (t->opcode_modifier.prefixok == PrefixRep)
15106
0
  {
15107
0
    int es_op = t->opcode_modifier.isstring - IS_STRING_ES_OP0;
15108
0
    int op = 0;
15109
15110
0
    if (!t->operand_types[0].bitfield.baseindex
15111
0
        || ((!i.mem_operands != !intel_syntax)
15112
0
      && t->operand_types[1].bitfield.baseindex))
15113
0
      op = 1;
15114
0
    expected_reg = str_hash_find (reg_hash,
15115
0
          di_si[addr_mode][op == es_op]);
15116
0
  }
15117
0
      else
15118
0
  {
15119
0
    unsigned int op = t->operand_types[0].bitfield.baseindex ? 0 : 1;
15120
15121
0
    if (!t->operand_types[op].bitfield.instance)
15122
0
      return 1; /* Operand mismatch will be detected elsewhere.  */
15123
0
    expected_reg
15124
0
      = str_hash_find (reg_hash,
15125
0
           loregs[addr_mode][t->operand_types[op]
15126
0
                 .bitfield.instance - 1]);
15127
0
  }
15128
15129
0
      if (i.base_reg != expected_reg
15130
0
    || i.index_reg
15131
0
    || operand_type_check (i.types[this_operand], disp))
15132
0
  {
15133
    /* The second memory operand must have the same size as
15134
       the first one.  */
15135
0
    if (i.mem_operands
15136
0
        && i.base_reg
15137
0
        && !((addr_mode == CODE_64BIT
15138
0
        && i.base_reg->reg_type.bitfield.qword)
15139
0
       || (addr_mode == CODE_32BIT
15140
0
           ? i.base_reg->reg_type.bitfield.dword
15141
0
           : i.base_reg->reg_type.bitfield.word)))
15142
0
      goto bad_address;
15143
15144
0
    as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
15145
0
       operand_string,
15146
0
       intel_syntax ? '[' : '(',
15147
0
       register_prefix,
15148
0
       expected_reg->reg_name,
15149
0
       intel_syntax ? ']' : ')');
15150
0
    return 1;
15151
0
  }
15152
0
      else
15153
0
  return 1;
15154
15155
0
    bad_address:
15156
0
      as_bad (_("`%s' is not a valid %s expression"),
15157
0
        operand_string, kind);
15158
0
      return 0;
15159
0
    }
15160
0
  else
15161
0
    {
15162
0
      t = current_templates.start;
15163
15164
0
      if (addr_mode != CODE_16BIT)
15165
0
  {
15166
    /* 32-bit/64-bit checks.  */
15167
0
    if (pp.disp_encoding == disp_encoding_16bit)
15168
0
      {
15169
0
      bad_disp:
15170
0
        as_bad (_("invalid `%s' prefix"),
15171
0
          addr_mode == CODE_16BIT ? "{disp32}" : "{disp16}");
15172
0
        return 0;
15173
0
      }
15174
15175
0
    if ((i.base_reg
15176
0
         && ((addr_mode == CODE_64BIT
15177
0
        ? !i.base_reg->reg_type.bitfield.qword
15178
0
        : !i.base_reg->reg_type.bitfield.dword)
15179
0
       || (i.index_reg && i.base_reg->reg_num == RegIP)
15180
0
       || i.base_reg->reg_num == RegIZ))
15181
0
        || (i.index_reg
15182
0
      && !i.index_reg->reg_type.bitfield.xmmword
15183
0
      && !i.index_reg->reg_type.bitfield.ymmword
15184
0
      && !i.index_reg->reg_type.bitfield.zmmword
15185
0
      && ((addr_mode == CODE_64BIT
15186
0
           ? !i.index_reg->reg_type.bitfield.qword
15187
0
           : !i.index_reg->reg_type.bitfield.dword)
15188
0
          || !i.index_reg->reg_type.bitfield.baseindex)))
15189
0
      goto bad_address;
15190
15191
    /* bndmk, bndldx, bndstx and mandatory non-vector SIB have special restrictions. */
15192
0
    if (t->mnem_off == MN_bndmk
15193
0
        || t->mnem_off == MN_bndldx
15194
0
        || t->mnem_off == MN_bndstx
15195
0
        || t->opcode_modifier.sib == SIBMEM)
15196
0
      {
15197
        /* They cannot use RIP-relative addressing. */
15198
0
        if (i.base_reg && i.base_reg->reg_num == RegIP)
15199
0
    {
15200
0
      as_bad (_("`%s' cannot be used here"), operand_string);
15201
0
      return 0;
15202
0
    }
15203
15204
        /* bndldx and bndstx ignore their scale factor. */
15205
0
        if ((t->mnem_off == MN_bndldx || t->mnem_off == MN_bndstx)
15206
0
      && i.log2_scale_factor)
15207
0
    as_warn (_("register scaling is being ignored here"));
15208
0
      }
15209
0
  }
15210
0
      else
15211
0
  {
15212
    /* 16-bit checks.  */
15213
0
    if (pp.disp_encoding == disp_encoding_32bit)
15214
0
      goto bad_disp;
15215
15216
0
    if ((i.base_reg
15217
0
         && (!i.base_reg->reg_type.bitfield.word
15218
0
       || !i.base_reg->reg_type.bitfield.baseindex))
15219
0
        || (i.index_reg
15220
0
      && (!i.index_reg->reg_type.bitfield.word
15221
0
          || !i.index_reg->reg_type.bitfield.baseindex
15222
0
          || !(i.base_reg
15223
0
         && i.base_reg->reg_num < 6
15224
0
         && i.index_reg->reg_num >= 6
15225
0
         && i.log2_scale_factor == 0))))
15226
0
      goto bad_address;
15227
0
  }
15228
0
    }
15229
0
  return 1;
15230
0
}
15231
15232
/* Handle vector immediates.  */
15233
15234
static int
15235
RC_SAE_immediate (const char *imm_start)
15236
0
{
15237
0
  const char *pstr = imm_start;
15238
15239
0
  if (*pstr != '{')
15240
0
    return 0;
15241
15242
0
  pstr++;
15243
0
  if (is_whitespace (*pstr))
15244
0
    pstr++;
15245
15246
0
  pstr = RC_SAE_specifier (pstr);
15247
0
  if (pstr == NULL)
15248
0
    return 0;
15249
15250
0
  if (is_whitespace (*pstr))
15251
0
    pstr++;
15252
15253
0
  if (*pstr++ != '}')
15254
0
    {
15255
0
      as_bad (_("Missing '}': '%s'"), imm_start);
15256
0
      return 0;
15257
0
    }
15258
0
  /* RC/SAE immediate string should contain nothing more.  */;
15259
0
  if (*pstr != 0)
15260
0
    {
15261
0
      as_bad (_("Junk after '}': '%s'"), imm_start);
15262
0
      return 0;
15263
0
    }
15264
15265
  /* Internally this doesn't count as an operand.  */
15266
0
  --i.operands;
15267
15268
0
  return 1;
15269
0
}
15270
15271
static INLINE bool starts_memory_operand (char c)
15272
0
{
15273
0
  return ISDIGIT (c)
15274
0
   || is_name_beginner (c)
15275
0
   || strchr ("([\"+-!~", c);
15276
0
}
15277
15278
/* Parse OPERAND_STRING into the i386_insn structure I.  Returns zero
15279
   on error.  */
15280
15281
static int
15282
i386_att_operand (char *operand_string)
15283
0
{
15284
0
  const reg_entry *r;
15285
0
  char *end_op;
15286
0
  char *op_string = operand_string;
15287
15288
0
  if (is_whitespace (*op_string))
15289
0
    ++op_string;
15290
15291
  /* We check for an absolute prefix (differentiating,
15292
     for example, 'jmp pc_relative_label' from 'jmp *absolute_label'.  */
15293
0
  if (*op_string == ABSOLUTE_PREFIX
15294
0
      && current_templates.start->opcode_modifier.jump)
15295
0
    {
15296
0
      ++op_string;
15297
0
      if (is_whitespace (*op_string))
15298
0
  ++op_string;
15299
0
      i.jumpabsolute = true;
15300
0
    }
15301
15302
  /* Check if operand is a register.  */
15303
0
  if ((r = parse_register (op_string, &end_op)) != NULL)
15304
0
    {
15305
0
      i386_operand_type temp;
15306
15307
0
      if (r == &bad_reg)
15308
0
  return 0;
15309
15310
      /* Check for a segment override by searching for ':' after a
15311
   segment register.  */
15312
0
      op_string = end_op;
15313
0
      if (is_whitespace (*op_string))
15314
0
  ++op_string;
15315
0
      if (*op_string == ':' && r->reg_type.bitfield.class == SReg)
15316
0
  {
15317
0
    i.seg[i.mem_operands] = r;
15318
15319
    /* Skip the ':' and whitespace.  */
15320
0
    ++op_string;
15321
0
    if (is_whitespace (*op_string))
15322
0
      ++op_string;
15323
15324
    /* Handle case of %es:*foo.  */
15325
0
    if (!i.jumpabsolute && *op_string == ABSOLUTE_PREFIX
15326
0
        && current_templates.start->opcode_modifier.jump)
15327
0
      {
15328
0
        ++op_string;
15329
0
        if (is_whitespace (*op_string))
15330
0
    ++op_string;
15331
0
        i.jumpabsolute = true;
15332
0
      }
15333
15334
0
    if (!starts_memory_operand (*op_string))
15335
0
      {
15336
0
        as_bad (_("bad memory operand `%s'"), op_string);
15337
0
        return 0;
15338
0
      }
15339
0
    goto do_memory_reference;
15340
0
  }
15341
15342
      /* Handle vector operations.  */
15343
0
      if (*op_string == '{')
15344
0
  {
15345
0
    op_string = check_VecOperations (op_string);
15346
0
    if (op_string == NULL)
15347
0
      return 0;
15348
0
  }
15349
15350
0
      if (*op_string)
15351
0
  {
15352
0
    as_bad (_("junk `%s' after register"), op_string);
15353
0
    return 0;
15354
0
  }
15355
15356
       /* Reject pseudo registers for .insn.  */
15357
0
      if (dot_insn () && r->reg_type.bitfield.class == ClassNone)
15358
0
  {
15359
0
    as_bad (_("`%s%s' cannot be used here"),
15360
0
      register_prefix, r->reg_name);
15361
0
    return 0;
15362
0
  }
15363
15364
0
      temp = r->reg_type;
15365
0
      temp.bitfield.baseindex = 0;
15366
0
      i.types[this_operand] = operand_type_or (i.types[this_operand],
15367
0
                 temp);
15368
0
      i.types[this_operand].bitfield.unspecified = 0;
15369
0
      i.op[this_operand].regs = r;
15370
0
      i.reg_operands++;
15371
15372
      /* A GPR may follow an RC or SAE immediate only if a (vector) register
15373
         operand was also present earlier on.  */
15374
0
      if (i.rounding.type != rc_none && temp.bitfield.class == Reg
15375
0
          && i.reg_operands == 1)
15376
0
  {
15377
0
    unsigned int j;
15378
15379
0
    for (j = 0; j < ARRAY_SIZE (RC_NamesTable); ++j)
15380
0
      if (i.rounding.type == RC_NamesTable[j].type)
15381
0
        break;
15382
0
    as_bad (_("`%s': misplaced `{%s}'"),
15383
0
      insn_name (current_templates.start), RC_NamesTable[j].name);
15384
0
    return 0;
15385
0
  }
15386
0
    }
15387
0
  else if (*op_string == REGISTER_PREFIX)
15388
0
    {
15389
0
      as_bad (_("bad register name `%s'"), op_string);
15390
0
      return 0;
15391
0
    }
15392
0
  else if (*op_string == IMMEDIATE_PREFIX)
15393
0
    {
15394
0
      ++op_string;
15395
0
      if (i.jumpabsolute)
15396
0
  {
15397
0
    as_bad (_("immediate operand illegal with absolute jump"));
15398
0
    return 0;
15399
0
  }
15400
0
      if (!i386_immediate (op_string))
15401
0
  return 0;
15402
0
      if (i.rounding.type != rc_none)
15403
0
  {
15404
0
    as_bad (_("`%s': RC/SAE operand must follow immediate operands"),
15405
0
      insn_name (current_templates.start));
15406
0
    return 0;
15407
0
  }
15408
0
    }
15409
0
  else if (RC_SAE_immediate (operand_string))
15410
0
    {
15411
      /* If it is a RC or SAE immediate, do the necessary placement check:
15412
   Only another immediate or a GPR may precede it.  */
15413
0
      if (i.mem_operands || i.reg_operands + i.imm_operands > 1
15414
0
    || (i.reg_operands == 1
15415
0
        && i.op[0].regs->reg_type.bitfield.class != Reg))
15416
0
  {
15417
0
    as_bad (_("`%s': misplaced `%s'"),
15418
0
      insn_name (current_templates.start), operand_string);
15419
0
    return 0;
15420
0
  }
15421
0
    }
15422
0
  else if (starts_memory_operand (*op_string))
15423
0
    {
15424
      /* This is a memory reference of some sort.  */
15425
0
      char *base_string;
15426
15427
      /* Start and end of displacement string expression (if found).  */
15428
0
      char *displacement_string_start;
15429
0
      char *displacement_string_end;
15430
15431
0
    do_memory_reference:
15432
      /* Check for base index form.  We detect the base index form by
15433
   looking for an ')' at the end of the operand, searching
15434
   for the '(' matching it, and finding a REGISTER_PREFIX or ','
15435
   after the '('.  */
15436
0
      base_string = op_string + strlen (op_string);
15437
15438
      /* Handle vector operations.  */
15439
0
      --base_string;
15440
0
      if (is_whitespace (*base_string))
15441
0
  --base_string;
15442
15443
0
      if (*base_string == '}')
15444
0
  {
15445
0
    char *vop_start = NULL;
15446
15447
0
    while (base_string-- > op_string)
15448
0
      {
15449
0
        if (*base_string == '"')
15450
0
    break;
15451
0
        if (*base_string != '{')
15452
0
    continue;
15453
15454
0
        vop_start = base_string;
15455
15456
0
        --base_string;
15457
0
        if (is_whitespace (*base_string))
15458
0
    --base_string;
15459
15460
0
        if (*base_string != '}')
15461
0
    break;
15462
15463
0
        vop_start = NULL;
15464
0
      }
15465
15466
0
    if (!vop_start)
15467
0
      {
15468
0
        as_bad (_("unbalanced figure braces"));
15469
0
        return 0;
15470
0
      }
15471
15472
0
    if (check_VecOperations (vop_start) == NULL)
15473
0
      return 0;
15474
0
  }
15475
15476
      /* If we only have a displacement, set-up for it to be parsed later.  */
15477
0
      displacement_string_start = op_string;
15478
0
      displacement_string_end = base_string + 1;
15479
15480
0
      if (*base_string == ')')
15481
0
  {
15482
0
    char *temp_string;
15483
0
    unsigned int parens_not_balanced = 0;
15484
0
    bool in_quotes = false;
15485
15486
    /* We've already checked that the number of left & right ()'s are
15487
       equal, and that there's a matching set of double quotes.  */
15488
0
    end_op = base_string;
15489
0
    for (temp_string = op_string; temp_string < end_op; temp_string++)
15490
0
      {
15491
0
        if (*temp_string == '\\' && temp_string[1] == '"')
15492
0
    ++temp_string;
15493
0
        else if (*temp_string == '"')
15494
0
    in_quotes = !in_quotes;
15495
0
        else if (!in_quotes)
15496
0
    {
15497
0
      if (*temp_string == '(' && !parens_not_balanced++)
15498
0
        base_string = temp_string;
15499
0
      if (*temp_string == ')')
15500
0
        --parens_not_balanced;
15501
0
    }
15502
0
      }
15503
15504
0
    temp_string = base_string;
15505
15506
    /* Skip past '(' and whitespace.  */
15507
0
    gas_assert (*base_string == '(');
15508
0
    ++base_string;
15509
0
    if (is_whitespace (*base_string))
15510
0
      ++base_string;
15511
15512
0
    if (*base_string == ','
15513
0
        || ((i.base_reg = parse_register (base_string, &end_op))
15514
0
      != NULL))
15515
0
      {
15516
0
        displacement_string_end = temp_string;
15517
15518
0
        i.types[this_operand].bitfield.baseindex = 1;
15519
15520
0
        if (i.base_reg)
15521
0
    {
15522
0
      if (i.base_reg == &bad_reg)
15523
0
        return 0;
15524
0
      base_string = end_op;
15525
0
      if (is_whitespace (*base_string))
15526
0
        ++base_string;
15527
0
    }
15528
15529
        /* There may be an index reg or scale factor here.  */
15530
0
        if (*base_string == ',')
15531
0
    {
15532
0
      ++base_string;
15533
0
      if (is_whitespace (*base_string))
15534
0
        ++base_string;
15535
15536
0
      if ((i.index_reg = parse_register (base_string, &end_op))
15537
0
          != NULL)
15538
0
        {
15539
0
          if (i.index_reg == &bad_reg)
15540
0
      return 0;
15541
0
          base_string = end_op;
15542
0
          if (is_whitespace (*base_string))
15543
0
      ++base_string;
15544
0
          if (*base_string == ',')
15545
0
      {
15546
0
        ++base_string;
15547
0
        if (is_whitespace (*base_string))
15548
0
          ++base_string;
15549
0
      }
15550
0
          else if (*base_string != ')')
15551
0
      {
15552
0
        as_bad (_("expecting `,' or `)' "
15553
0
            "after index register in `%s'"),
15554
0
          operand_string);
15555
0
        return 0;
15556
0
      }
15557
0
        }
15558
0
      else if (*base_string == REGISTER_PREFIX)
15559
0
        {
15560
0
          end_op = strchr (base_string, ',');
15561
0
          if (end_op)
15562
0
      *end_op = '\0';
15563
0
          as_bad (_("bad register name `%s'"), base_string);
15564
0
          return 0;
15565
0
        }
15566
15567
      /* Check for scale factor.  */
15568
0
      if (*base_string != ')')
15569
0
        {
15570
0
          char *end_scale = i386_scale (base_string);
15571
15572
0
          if (!end_scale)
15573
0
      return 0;
15574
15575
0
          base_string = end_scale;
15576
0
          if (is_whitespace (*base_string))
15577
0
      ++base_string;
15578
0
          if (*base_string != ')')
15579
0
      {
15580
0
        as_bad (_("expecting `)' "
15581
0
            "after scale factor in `%s'"),
15582
0
          operand_string);
15583
0
        return 0;
15584
0
      }
15585
0
        }
15586
0
      else if (!i.index_reg)
15587
0
        {
15588
0
          as_bad (_("expecting index register or scale factor "
15589
0
        "after `,'; got '%c'"),
15590
0
            *base_string);
15591
0
          return 0;
15592
0
        }
15593
0
    }
15594
0
        else if (*base_string != ')')
15595
0
    {
15596
0
      as_bad (_("expecting `,' or `)' "
15597
0
          "after base register in `%s'"),
15598
0
        operand_string);
15599
0
      return 0;
15600
0
    }
15601
0
      }
15602
0
    else if (*base_string == REGISTER_PREFIX)
15603
0
      {
15604
0
        end_op = strchr (base_string, ',');
15605
0
        if (end_op)
15606
0
    *end_op = '\0';
15607
0
        as_bad (_("bad register name `%s'"), base_string);
15608
0
        return 0;
15609
0
      }
15610
0
  }
15611
15612
      /* If there's an expression beginning the operand, parse it,
15613
   assuming displacement_string_start and
15614
   displacement_string_end are meaningful.  */
15615
0
      if (displacement_string_start != displacement_string_end)
15616
0
  {
15617
0
    if (!i386_displacement (displacement_string_start,
15618
0
          displacement_string_end))
15619
0
      return 0;
15620
0
  }
15621
15622
      /* Special case for (%dx) while doing input/output op.  */
15623
0
      if (i.base_reg
15624
0
    && i.base_reg->reg_type.bitfield.instance == RegD
15625
0
    && i.base_reg->reg_type.bitfield.word
15626
0
    && i.index_reg == 0
15627
0
    && i.log2_scale_factor == 0
15628
0
    && i.seg[i.mem_operands] == 0
15629
0
    && !operand_type_check (i.types[this_operand], disp))
15630
0
  {
15631
0
    i.types[this_operand] = i.base_reg->reg_type;
15632
0
    i.op[this_operand].regs = i.base_reg;
15633
0
    i.base_reg = NULL;
15634
0
    i.input_output_operand = true;
15635
0
    return 1;
15636
0
  }
15637
15638
0
      if (i386_index_check (operand_string) == 0)
15639
0
  return 0;
15640
0
      i.flags[this_operand] |= Operand_Mem;
15641
0
      i.mem_operands++;
15642
0
    }
15643
0
  else
15644
0
    {
15645
      /* It's not a memory operand; argh!  */
15646
0
      as_bad (_("invalid char %s beginning operand %d `%s'"),
15647
0
        output_invalid (*op_string),
15648
0
        this_operand + 1,
15649
0
        op_string);
15650
0
      return 0;
15651
0
    }
15652
0
  return 1;     /* Normal return.  */
15653
0
}
15654

15655
/* Calculate the maximum variable size (i.e., excluding fr_fix)
15656
   that an rs_machine_dependent frag may reach.  */
15657
15658
unsigned int
15659
i386_frag_max_var (fragS *frag)
15660
0
{
15661
  /* The only relaxable frags are for jumps.
15662
     Unconditional jumps can grow by 4 bytes and others by 5 bytes.  */
15663
0
  gas_assert (frag->fr_type == rs_machine_dependent);
15664
0
  return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
15665
0
}
15666
15667
#ifdef OBJ_ELF
15668
static int
15669
elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var)
15670
0
{
15671
  /* STT_GNU_IFUNC symbol must go through PLT.  */
15672
0
  if ((symbol_get_bfdsym (fr_symbol)->flags
15673
0
       & BSF_GNU_INDIRECT_FUNCTION) != 0)
15674
0
    return 0;
15675
15676
0
  if (!S_IS_EXTERNAL (fr_symbol))
15677
    /* Symbol may be weak or local.  */
15678
0
    return !S_IS_WEAK (fr_symbol);
15679
15680
  /* Global symbols with non-default visibility can't be preempted. */
15681
0
  if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT)
15682
0
    return 1;
15683
15684
0
  if (fr_var != NO_RELOC)
15685
0
    switch ((enum bfd_reloc_code_real) fr_var)
15686
0
      {
15687
0
      case BFD_RELOC_386_PLT32:
15688
0
      case BFD_RELOC_X86_64_PLT32:
15689
  /* Symbol with PLT relocation may be preempted. */
15690
0
  return 0;
15691
0
      default:
15692
0
  abort ();
15693
0
      }
15694
15695
  /* Global symbols with default visibility in a shared library may be
15696
     preempted by another definition.  */
15697
0
  return !shared;
15698
0
}
15699
#endif
15700
15701
/* Table 3-2. Macro-Fusible Instructions in Haswell Microarchitecture
15702
   Note also work for Skylake and Cascadelake.
15703
---------------------------------------------------------------------
15704
|   JCC   | ADD/SUB/CMP | INC/DEC | TEST/AND |
15705
| ------  | ----------- | ------- | -------- |
15706
|   Jo    |      N      |    N    |     Y    |
15707
|   Jno   |      N      |    N    |     Y    |
15708
|  Jc/Jb  |      Y      |    N    |     Y    |
15709
| Jae/Jnb |      Y      |    N    |     Y    |
15710
|  Je/Jz  |      Y      |    Y    |     Y    |
15711
| Jne/Jnz |      Y      |    Y    |     Y    |
15712
| Jna/Jbe |      Y      |    N    |     Y    |
15713
| Ja/Jnbe |      Y      |    N    |     Y    |
15714
|   Js    |      N      |    N    |     Y    |
15715
|   Jns   |      N      |    N    |     Y    |
15716
|  Jp/Jpe |      N      |    N    |     Y    |
15717
| Jnp/Jpo |      N      |    N    |     Y    |
15718
| Jl/Jnge |      Y      |    Y    |     Y    |
15719
| Jge/Jnl |      Y      |    Y    |     Y    |
15720
| Jle/Jng |      Y      |    Y    |     Y    |
15721
| Jg/Jnle |      Y      |    Y    |     Y    |
15722
---------------------------------------------------------------------  */
15723
static int
15724
i386_macro_fusible_p (enum mf_cmp_kind mf_cmp, enum mf_jcc_kind mf_jcc)
15725
0
{
15726
0
  if (mf_cmp == mf_cmp_alu_cmp)
15727
0
    return ((mf_jcc >= mf_jcc_jc && mf_jcc <= mf_jcc_jna)
15728
0
      || mf_jcc == mf_jcc_jl || mf_jcc == mf_jcc_jle);
15729
0
  if (mf_cmp == mf_cmp_incdec)
15730
0
    return (mf_jcc == mf_jcc_je || mf_jcc == mf_jcc_jl
15731
0
      || mf_jcc == mf_jcc_jle);
15732
0
  if (mf_cmp == mf_cmp_test_and)
15733
0
    return 1;
15734
0
  return 0;
15735
0
}
15736
15737
/* Return the next non-empty frag.  */
15738
15739
static fragS *
15740
i386_next_non_empty_frag (fragS *fragP)
15741
0
{
15742
  /* There may be a frag with a ".fill 0" when there is no room in
15743
     the current frag for frag_grow in output_insn.  */
15744
0
  for (fragP = fragP->fr_next;
15745
0
       (fragP != NULL
15746
0
  && fragP->fr_type == rs_fill
15747
0
  && fragP->fr_fix == 0);
15748
0
       fragP = fragP->fr_next)
15749
0
    ;
15750
0
  return fragP;
15751
0
}
15752
15753
/* Return the next jcc frag after BRANCH_PADDING.  */
15754
15755
static fragS *
15756
i386_next_fusible_jcc_frag (fragS *maybe_cmp_fragP, fragS *pad_fragP)
15757
0
{
15758
0
  fragS *branch_fragP;
15759
0
  if (!pad_fragP)
15760
0
    return NULL;
15761
15762
0
  if (pad_fragP->fr_type == rs_machine_dependent
15763
0
      && (TYPE_FROM_RELAX_STATE (pad_fragP->fr_subtype)
15764
0
    == BRANCH_PADDING))
15765
0
    {
15766
0
      branch_fragP = i386_next_non_empty_frag (pad_fragP);
15767
0
      if (branch_fragP->fr_type != rs_machine_dependent)
15768
0
  return NULL;
15769
0
      if (TYPE_FROM_RELAX_STATE (branch_fragP->fr_subtype) == COND_JUMP
15770
0
    && i386_macro_fusible_p (maybe_cmp_fragP->tc_frag_data.mf_type,
15771
0
           pad_fragP->tc_frag_data.mf_type))
15772
0
  return branch_fragP;
15773
0
    }
15774
15775
0
  return NULL;
15776
0
}
15777
15778
/* Classify BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags.  */
15779
15780
static void
15781
i386_classify_machine_dependent_frag (fragS *fragP)
15782
0
{
15783
0
  fragS *cmp_fragP;
15784
0
  fragS *pad_fragP;
15785
0
  fragS *branch_fragP;
15786
0
  fragS *next_fragP;
15787
0
  unsigned int max_prefix_length;
15788
15789
0
  if (fragP->tc_frag_data.classified)
15790
0
    return;
15791
15792
  /* First scan for BRANCH_PADDING and FUSED_JCC_PADDING.  Convert
15793
     FUSED_JCC_PADDING and merge BRANCH_PADDING.  */
15794
0
  for (next_fragP = fragP;
15795
0
       next_fragP != NULL;
15796
0
       next_fragP = next_fragP->fr_next)
15797
0
    {
15798
0
      next_fragP->tc_frag_data.classified = 1;
15799
0
      if (next_fragP->fr_type == rs_machine_dependent)
15800
0
  switch (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype))
15801
0
    {
15802
0
    case BRANCH_PADDING:
15803
      /* The BRANCH_PADDING frag must be followed by a branch
15804
         frag.  */
15805
0
      branch_fragP = i386_next_non_empty_frag (next_fragP);
15806
0
      next_fragP->tc_frag_data.u.branch_fragP = branch_fragP;
15807
0
      break;
15808
0
    case FUSED_JCC_PADDING:
15809
      /* Check if this is a fused jcc:
15810
         FUSED_JCC_PADDING
15811
         CMP like instruction
15812
         BRANCH_PADDING
15813
         COND_JUMP
15814
         */
15815
0
      cmp_fragP = i386_next_non_empty_frag (next_fragP);
15816
0
      pad_fragP = i386_next_non_empty_frag (cmp_fragP);
15817
0
      branch_fragP = i386_next_fusible_jcc_frag (next_fragP, pad_fragP);
15818
0
      if (branch_fragP)
15819
0
        {
15820
    /* The BRANCH_PADDING frag is merged with the
15821
       FUSED_JCC_PADDING frag.  */
15822
0
    next_fragP->tc_frag_data.u.branch_fragP = branch_fragP;
15823
    /* CMP like instruction size.  */
15824
0
    next_fragP->tc_frag_data.cmp_size = cmp_fragP->fr_fix;
15825
0
    frag_wane (pad_fragP);
15826
    /* Skip to branch_fragP.  */
15827
0
    next_fragP = branch_fragP;
15828
0
        }
15829
0
      else if (next_fragP->tc_frag_data.max_prefix_length)
15830
0
        {
15831
    /* Turn FUSED_JCC_PADDING into BRANCH_PREFIX if it isn't
15832
       a fused jcc.  */
15833
0
    next_fragP->fr_subtype
15834
0
      = ENCODE_RELAX_STATE (BRANCH_PREFIX, 0);
15835
0
    next_fragP->tc_frag_data.max_bytes
15836
0
      = next_fragP->tc_frag_data.max_prefix_length;
15837
    /* This will be updated in the BRANCH_PREFIX scan.  */
15838
0
    next_fragP->tc_frag_data.max_prefix_length = 0;
15839
0
        }
15840
0
      else
15841
0
        frag_wane (next_fragP);
15842
0
      break;
15843
0
    }
15844
0
    }
15845
15846
  /* Stop if there is no BRANCH_PREFIX.  */
15847
0
  if (!align_branch_prefix_size)
15848
0
    return;
15849
15850
  /* Scan for BRANCH_PREFIX.  */
15851
0
  for (; fragP != NULL; fragP = fragP->fr_next)
15852
0
    {
15853
0
      if (fragP->fr_type != rs_machine_dependent
15854
0
    || (TYPE_FROM_RELAX_STATE (fragP->fr_subtype)
15855
0
        != BRANCH_PREFIX))
15856
0
  continue;
15857
15858
      /* Count all BRANCH_PREFIX frags before BRANCH_PADDING and
15859
   COND_JUMP_PREFIX.  */
15860
0
      max_prefix_length = 0;
15861
0
      for (next_fragP = fragP;
15862
0
     next_fragP != NULL;
15863
0
     next_fragP = next_fragP->fr_next)
15864
0
  {
15865
0
    if (next_fragP->fr_type == rs_fill)
15866
      /* Skip rs_fill frags.  */
15867
0
      continue;
15868
0
    else if (next_fragP->fr_type != rs_machine_dependent)
15869
      /* Stop for all other frags.  */
15870
0
      break;
15871
15872
    /* rs_machine_dependent frags.  */
15873
0
    if (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype)
15874
0
        == BRANCH_PREFIX)
15875
0
      {
15876
        /* Count BRANCH_PREFIX frags.  */
15877
0
        if (max_prefix_length >= MAX_FUSED_JCC_PADDING_SIZE)
15878
0
    {
15879
0
      max_prefix_length = MAX_FUSED_JCC_PADDING_SIZE;
15880
0
      frag_wane (next_fragP);
15881
0
    }
15882
0
        else
15883
0
    max_prefix_length
15884
0
      += next_fragP->tc_frag_data.max_bytes;
15885
0
      }
15886
0
    else if ((TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype)
15887
0
        == BRANCH_PADDING)
15888
0
       || (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype)
15889
0
           == FUSED_JCC_PADDING))
15890
0
      {
15891
        /* Stop at BRANCH_PADDING and FUSED_JCC_PADDING.  */
15892
0
        fragP->tc_frag_data.u.padding_fragP = next_fragP;
15893
0
        break;
15894
0
      }
15895
0
    else
15896
      /* Stop for other rs_machine_dependent frags.  */
15897
0
      break;
15898
0
  }
15899
15900
0
      fragP->tc_frag_data.max_prefix_length = max_prefix_length;
15901
15902
      /* Skip to the next frag.  */
15903
0
      fragP = next_fragP;
15904
0
    }
15905
0
}
15906
15907
/* Compute padding size for
15908
15909
  FUSED_JCC_PADDING
15910
  CMP like instruction
15911
  BRANCH_PADDING
15912
  COND_JUMP/UNCOND_JUMP
15913
15914
   or
15915
15916
  BRANCH_PADDING
15917
  COND_JUMP/UNCOND_JUMP
15918
 */
15919
15920
static int
15921
i386_branch_padding_size (fragS *fragP, offsetT address)
15922
0
{
15923
0
  unsigned int offset, size, padding_size;
15924
0
  fragS *branch_fragP = fragP->tc_frag_data.u.branch_fragP;
15925
15926
  /* The start address of the BRANCH_PADDING or FUSED_JCC_PADDING frag.  */
15927
0
  if (!address)
15928
0
    address = fragP->fr_address;
15929
0
  address += fragP->fr_fix;
15930
15931
  /* CMP like instrunction size.  */
15932
0
  size = fragP->tc_frag_data.cmp_size;
15933
15934
  /* The base size of the branch frag.  */
15935
0
  size += branch_fragP->fr_fix;
15936
15937
  /* Add opcode and displacement bytes for the rs_machine_dependent
15938
     branch frag.  */
15939
0
  if (branch_fragP->fr_type == rs_machine_dependent)
15940
0
    size += md_relax_table[branch_fragP->fr_subtype].rlx_length;
15941
15942
  /* Check if branch is within boundary and doesn't end at the last
15943
     byte.  */
15944
0
  offset = address & ((1U << align_branch_power) - 1);
15945
0
  if ((offset + size) >= (1U << align_branch_power))
15946
    /* Padding needed to avoid crossing boundary.  */
15947
0
    padding_size = (1U << align_branch_power) - offset;
15948
0
  else
15949
    /* No padding needed.  */
15950
0
    padding_size = 0;
15951
15952
  /* The return value may be saved in tc_frag_data.length which is
15953
     unsigned byte.  */
15954
0
  if (!fits_in_unsigned_byte (padding_size))
15955
0
    abort ();
15956
15957
0
  return padding_size;
15958
0
}
15959
15960
/* i386_generic_table_relax_frag()
15961
15962
   Handle BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags to
15963
   grow/shrink padding to align branch frags.  Hand others to
15964
   relax_frag().  */
15965
15966
long
15967
i386_generic_table_relax_frag (segT segment, fragS *fragP, long stretch)
15968
0
{
15969
0
  if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PADDING
15970
0
      || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == FUSED_JCC_PADDING)
15971
0
    {
15972
0
      long padding_size = i386_branch_padding_size (fragP, 0);
15973
0
      long grow = padding_size - fragP->tc_frag_data.length;
15974
15975
      /* When the BRANCH_PREFIX frag is used, the computed address
15976
         must match the actual address and there should be no padding.  */
15977
0
      if (fragP->tc_frag_data.padding_address
15978
0
    && (fragP->tc_frag_data.padding_address != fragP->fr_address
15979
0
        || padding_size))
15980
0
  abort ();
15981
15982
      /* Update the padding size.  */
15983
0
      if (grow)
15984
0
  fragP->tc_frag_data.length = padding_size;
15985
15986
0
      return grow;
15987
0
    }
15988
0
  else if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PREFIX)
15989
0
    {
15990
0
      fragS *padding_fragP, *next_fragP;
15991
0
      long padding_size, left_size, last_size;
15992
15993
0
      padding_fragP = fragP->tc_frag_data.u.padding_fragP;
15994
0
      if (!padding_fragP)
15995
  /* Use the padding set by the leading BRANCH_PREFIX frag.  */
15996
0
  return (fragP->tc_frag_data.length
15997
0
    - fragP->tc_frag_data.last_length);
15998
15999
      /* Compute the relative address of the padding frag in the very
16000
        first time where the BRANCH_PREFIX frag sizes are zero.  */
16001
0
      if (!fragP->tc_frag_data.padding_address)
16002
0
  fragP->tc_frag_data.padding_address
16003
0
    = padding_fragP->fr_address - (fragP->fr_address - stretch);
16004
16005
      /* First update the last length from the previous interation.  */
16006
0
      left_size = fragP->tc_frag_data.prefix_length;
16007
0
      for (next_fragP = fragP;
16008
0
     next_fragP != padding_fragP;
16009
0
     next_fragP = next_fragP->fr_next)
16010
0
  if (next_fragP->fr_type == rs_machine_dependent
16011
0
      && (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype)
16012
0
    == BRANCH_PREFIX))
16013
0
    {
16014
0
      if (left_size)
16015
0
        {
16016
0
    int max = next_fragP->tc_frag_data.max_bytes;
16017
0
    if (max)
16018
0
      {
16019
0
        int size;
16020
0
        if (max > left_size)
16021
0
          size = left_size;
16022
0
        else
16023
0
          size = max;
16024
0
        left_size -= size;
16025
0
        next_fragP->tc_frag_data.last_length = size;
16026
0
      }
16027
0
        }
16028
0
      else
16029
0
        next_fragP->tc_frag_data.last_length = 0;
16030
0
    }
16031
16032
      /* Check the padding size for the padding frag.  */
16033
0
      padding_size = i386_branch_padding_size
16034
0
  (padding_fragP, (fragP->fr_address
16035
0
       + fragP->tc_frag_data.padding_address));
16036
16037
0
      last_size = fragP->tc_frag_data.prefix_length;
16038
      /* Check if there is change from the last interation.  */
16039
0
      if (padding_size == last_size)
16040
0
  {
16041
    /* Update the expected address of the padding frag.  */
16042
0
    padding_fragP->tc_frag_data.padding_address
16043
0
      = (fragP->fr_address + padding_size
16044
0
         + fragP->tc_frag_data.padding_address);
16045
0
    return 0;
16046
0
  }
16047
16048
0
      if (padding_size > fragP->tc_frag_data.max_prefix_length)
16049
0
  {
16050
    /* No padding if there is no sufficient room.  Clear the
16051
       expected address of the padding frag.  */
16052
0
    padding_fragP->tc_frag_data.padding_address = 0;
16053
0
    padding_size = 0;
16054
0
  }
16055
0
      else
16056
  /* Store the expected address of the padding frag.  */
16057
0
  padding_fragP->tc_frag_data.padding_address
16058
0
    = (fragP->fr_address + padding_size
16059
0
       + fragP->tc_frag_data.padding_address);
16060
16061
0
      fragP->tc_frag_data.prefix_length = padding_size;
16062
16063
      /* Update the length for the current interation.  */
16064
0
      left_size = padding_size;
16065
0
      for (next_fragP = fragP;
16066
0
     next_fragP != padding_fragP;
16067
0
     next_fragP = next_fragP->fr_next)
16068
0
  if (next_fragP->fr_type == rs_machine_dependent
16069
0
      && (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype)
16070
0
    == BRANCH_PREFIX))
16071
0
    {
16072
0
      if (left_size)
16073
0
        {
16074
0
    int max = next_fragP->tc_frag_data.max_bytes;
16075
0
    if (max)
16076
0
      {
16077
0
        int size;
16078
0
        if (max > left_size)
16079
0
          size = left_size;
16080
0
        else
16081
0
          size = max;
16082
0
        left_size -= size;
16083
0
        next_fragP->tc_frag_data.length = size;
16084
0
      }
16085
0
        }
16086
0
      else
16087
0
        next_fragP->tc_frag_data.length = 0;
16088
0
    }
16089
16090
0
      return (fragP->tc_frag_data.length
16091
0
        - fragP->tc_frag_data.last_length);
16092
0
    }
16093
0
  return relax_frag (segment, fragP, stretch);
16094
0
}
16095
16096
/* md_estimate_size_before_relax()
16097
16098
   Called just before relax() for rs_machine_dependent frags.  The x86
16099
   assembler uses these frags to handle variable size jump
16100
   instructions.
16101
16102
   Any symbol that is now undefined will not become defined.
16103
   Return the correct fr_subtype in the frag.
16104
   Return the initial "guess for variable size of frag" to caller.
16105
   The guess is actually the growth beyond the fixed part.  Whatever
16106
   we do to grow the fixed or variable part contributes to our
16107
   returned value.  */
16108
16109
int
16110
md_estimate_size_before_relax (fragS *fragP, segT segment)
16111
0
{
16112
0
  if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PADDING
16113
0
      || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PREFIX
16114
0
      || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == FUSED_JCC_PADDING)
16115
0
    {
16116
0
      i386_classify_machine_dependent_frag (fragP);
16117
0
      return fragP->tc_frag_data.length;
16118
0
    }
16119
16120
  /* We've already got fragP->fr_subtype right;  all we have to do is
16121
     check for un-relaxable symbols.  On an ELF system, we can't relax
16122
     an externally visible symbol, because it may be overridden by a
16123
     shared library.  */
16124
0
  if (S_GET_SEGMENT (fragP->fr_symbol) != segment
16125
0
#ifdef OBJ_ELF
16126
0
      || !elf_symbol_resolved_in_segment_p (fragP->fr_symbol,
16127
0
              fragP->fr_var)
16128
0
#endif
16129
#if defined (OBJ_COFF) && defined (TE_PE)
16130
      || S_IS_WEAK (fragP->fr_symbol)
16131
#endif
16132
0
      )
16133
0
    {
16134
      /* Symbol is undefined in this segment, or we need to keep a
16135
   reloc so that weak symbols can be overridden.  */
16136
0
      int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
16137
0
      enum bfd_reloc_code_real reloc_type;
16138
0
      unsigned char *opcode;
16139
0
      int old_fr_fix;
16140
0
      fixS *fixP = NULL;
16141
16142
0
      if (fragP->fr_var != NO_RELOC)
16143
0
  reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
16144
0
      else if (size == 2)
16145
0
  reloc_type = BFD_RELOC_16_PCREL;
16146
0
#ifdef OBJ_ELF
16147
0
      else if (fragP->tc_frag_data.code == CODE_64BIT
16148
0
         && fragP->fr_offset == 0
16149
0
         && need_plt32_p (fragP->fr_symbol))
16150
0
  reloc_type = BFD_RELOC_X86_64_PLT32;
16151
0
#endif
16152
0
      else
16153
0
  reloc_type = BFD_RELOC_32_PCREL;
16154
16155
0
      old_fr_fix = fragP->fr_fix;
16156
0
      opcode = (unsigned char *) fragP->fr_opcode;
16157
16158
0
      switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
16159
0
  {
16160
0
  case UNCOND_JUMP:
16161
    /* Make jmp (0xeb) a (d)word displacement jump.  */
16162
0
    opcode[0] = 0xe9;
16163
0
    fragP->fr_fix += size;
16164
0
    fixP = fix_new (fragP, old_fr_fix, size,
16165
0
        fragP->fr_symbol,
16166
0
        fragP->fr_offset, 1,
16167
0
        reloc_type);
16168
0
    break;
16169
16170
0
  case COND_JUMP86:
16171
0
    if (size == 2
16172
0
        && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
16173
0
      {
16174
        /* Negate the condition, and branch past an
16175
     unconditional jump.  */
16176
0
        opcode[0] ^= 1;
16177
0
        opcode[1] = 3;
16178
        /* Insert an unconditional jump.  */
16179
0
        opcode[2] = 0xe9;
16180
        /* We added two extra opcode bytes, and have a two byte
16181
     offset.  */
16182
0
        fragP->fr_fix += 2 + 2;
16183
0
        fix_new (fragP, old_fr_fix + 2, 2,
16184
0
           fragP->fr_symbol,
16185
0
           fragP->fr_offset, 1,
16186
0
           reloc_type);
16187
0
        break;
16188
0
      }
16189
    /* Fall through.  */
16190
16191
0
  case COND_JUMP:
16192
0
    if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
16193
0
      {
16194
0
        fragP->fr_fix += 1;
16195
0
        fixP = fix_new (fragP, old_fr_fix, 1,
16196
0
            fragP->fr_symbol,
16197
0
            fragP->fr_offset, 1,
16198
0
            BFD_RELOC_8_PCREL);
16199
0
        fixP->fx_signed = 1;
16200
0
        break;
16201
0
      }
16202
16203
    /* This changes the byte-displacement jump 0x7N
16204
       to the (d)word-displacement jump 0x0f,0x8N.  */
16205
0
    opcode[1] = opcode[0] + 0x10;
16206
0
    opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
16207
    /* We've added an opcode byte.  */
16208
0
    fragP->fr_fix += 1 + size;
16209
0
    fixP = fix_new (fragP, old_fr_fix + 1, size,
16210
0
        fragP->fr_symbol,
16211
0
        fragP->fr_offset, 1,
16212
0
        reloc_type);
16213
0
    break;
16214
16215
0
  default:
16216
0
    BAD_CASE (fragP->fr_subtype);
16217
0
    break;
16218
0
  }
16219
16220
      /* All jumps handled here are signed, but don't unconditionally use a
16221
   signed limit check for 32 and 16 bit jumps as we want to allow wrap
16222
   around at 4G (outside of 64-bit mode) and 64k.  */
16223
0
      if (size == 4 && flag_code == CODE_64BIT)
16224
0
  fixP->fx_signed = 1;
16225
16226
0
      frag_wane (fragP);
16227
0
      return fragP->fr_fix - old_fr_fix;
16228
0
    }
16229
16230
  /* Guess size depending on current relax state.  Initially the relax
16231
     state will correspond to a short jump and we return 1, because
16232
     the variable part of the frag (the branch offset) is one byte
16233
     long.  However, we can relax a section more than once and in that
16234
     case we must either set fr_subtype back to the unrelaxed state,
16235
     or return the value for the appropriate branch.  */
16236
0
  return md_relax_table[fragP->fr_subtype].rlx_length;
16237
0
}
16238
16239
/* Called after relax() is finished.
16240
16241
   In:  Address of frag.
16242
  fr_type == rs_machine_dependent.
16243
  fr_subtype is what the address relaxed to.
16244
16245
   Out: Any fixSs and constants are set up.
16246
  Caller will turn frag into a ".space 0".  */
16247
16248
void
16249
md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
16250
                 fragS *fragP)
16251
0
{
16252
0
  unsigned char *opcode;
16253
0
  unsigned char *where_to_put_displacement = NULL;
16254
0
  offsetT target_address;
16255
0
  offsetT opcode_address;
16256
0
  unsigned int extension = 0;
16257
0
  offsetT displacement_from_opcode_start;
16258
16259
0
  if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PADDING
16260
0
      || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == FUSED_JCC_PADDING
16261
0
      || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PREFIX)
16262
0
    {
16263
      /* Generate nop padding.  */
16264
0
      unsigned int size = fragP->tc_frag_data.length;
16265
0
      if (size)
16266
0
  {
16267
0
    if (size > fragP->tc_frag_data.max_bytes)
16268
0
      abort ();
16269
16270
0
    if (flag_debug)
16271
0
      {
16272
0
        const char *msg;
16273
0
        const char *branch = "branch";
16274
0
        const char *prefix = "";
16275
0
        fragS *padding_fragP;
16276
0
        if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype)
16277
0
      == BRANCH_PREFIX)
16278
0
    {
16279
0
      padding_fragP = fragP->tc_frag_data.u.padding_fragP;
16280
0
      switch (fragP->tc_frag_data.default_prefix)
16281
0
        {
16282
0
        default:
16283
0
          abort ();
16284
0
          break;
16285
0
        case CS_PREFIX_OPCODE:
16286
0
          prefix = " cs";
16287
0
          break;
16288
0
        case DS_PREFIX_OPCODE:
16289
0
          prefix = " ds";
16290
0
          break;
16291
0
        case ES_PREFIX_OPCODE:
16292
0
          prefix = " es";
16293
0
          break;
16294
0
        case FS_PREFIX_OPCODE:
16295
0
          prefix = " fs";
16296
0
          break;
16297
0
        case GS_PREFIX_OPCODE:
16298
0
          prefix = " gs";
16299
0
          break;
16300
0
        case SS_PREFIX_OPCODE:
16301
0
          prefix = " ss";
16302
0
          break;
16303
0
        }
16304
0
      if (padding_fragP)
16305
0
        msg = _("%s:%u: add %d%s at 0x%llx to align "
16306
0
          "%s within %d-byte boundary\n");
16307
0
      else
16308
0
        msg = _("%s:%u: add additional %d%s at 0x%llx to "
16309
0
          "align %s within %d-byte boundary\n");
16310
0
    }
16311
0
        else
16312
0
    {
16313
0
      padding_fragP = fragP;
16314
0
      msg = _("%s:%u: add %d%s-byte nop at 0x%llx to align "
16315
0
        "%s within %d-byte boundary\n");
16316
0
    }
16317
16318
0
        if (padding_fragP)
16319
0
    switch (padding_fragP->tc_frag_data.branch_type)
16320
0
      {
16321
0
      case align_branch_jcc:
16322
0
        branch = "jcc";
16323
0
        break;
16324
0
      case align_branch_fused:
16325
0
        branch = "fused jcc";
16326
0
        break;
16327
0
      case align_branch_jmp:
16328
0
        branch = "jmp";
16329
0
        break;
16330
0
      case align_branch_call:
16331
0
        branch = "call";
16332
0
        break;
16333
0
      case align_branch_indirect:
16334
0
        branch = "indiret branch";
16335
0
        break;
16336
0
      case align_branch_ret:
16337
0
        branch = "ret";
16338
0
        break;
16339
0
      default:
16340
0
        break;
16341
0
      }
16342
16343
0
        fprintf (stdout, msg,
16344
0
           fragP->fr_file, fragP->fr_line, size, prefix,
16345
0
           (long long) fragP->fr_address, branch,
16346
0
           1 << align_branch_power);
16347
0
      }
16348
0
    if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PREFIX)
16349
0
      memset (fragP->fr_opcode,
16350
0
        fragP->tc_frag_data.default_prefix, size);
16351
0
    else
16352
0
      i386_generate_nops (fragP, (char *) fragP->fr_opcode,
16353
0
        size, 0);
16354
0
    fragP->fr_fix += size;
16355
0
  }
16356
0
      return;
16357
0
    }
16358
16359
0
  opcode = (unsigned char *) fragP->fr_opcode;
16360
16361
  /* Address we want to reach in file space.  */
16362
0
  target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
16363
16364
  /* Address opcode resides at in file space.  */
16365
0
  opcode_address = fragP->fr_address + fragP->fr_fix;
16366
16367
  /* Displacement from opcode start to fill into instruction.  */
16368
0
  displacement_from_opcode_start = target_address - opcode_address;
16369
16370
0
  if ((fragP->fr_subtype & BIG) == 0)
16371
0
    {
16372
      /* Don't have to change opcode.  */
16373
0
      extension = 1;    /* 1 opcode + 1 displacement  */
16374
0
      where_to_put_displacement = &opcode[1];
16375
0
    }
16376
0
  else
16377
0
    {
16378
0
      if (no_cond_jump_promotion
16379
0
    && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
16380
0
  as_warn_where (fragP->fr_file, fragP->fr_line,
16381
0
           _("long jump required"));
16382
16383
0
      switch (fragP->fr_subtype)
16384
0
  {
16385
0
  case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
16386
0
    extension = 4;    /* 1 opcode + 4 displacement  */
16387
0
    opcode[0] = 0xe9;
16388
0
    where_to_put_displacement = &opcode[1];
16389
0
    break;
16390
16391
0
  case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
16392
0
    extension = 2;    /* 1 opcode + 2 displacement  */
16393
0
    opcode[0] = 0xe9;
16394
0
    where_to_put_displacement = &opcode[1];
16395
0
    break;
16396
16397
0
  case ENCODE_RELAX_STATE (COND_JUMP, BIG):
16398
0
  case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
16399
0
    extension = 5;    /* 2 opcode + 4 displacement  */
16400
0
    opcode[1] = opcode[0] + 0x10;
16401
0
    opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
16402
0
    where_to_put_displacement = &opcode[2];
16403
0
    break;
16404
16405
0
  case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
16406
0
    extension = 3;    /* 2 opcode + 2 displacement  */
16407
0
    opcode[1] = opcode[0] + 0x10;
16408
0
    opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
16409
0
    where_to_put_displacement = &opcode[2];
16410
0
    break;
16411
16412
0
  case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
16413
0
    extension = 4;
16414
0
    opcode[0] ^= 1;
16415
0
    opcode[1] = 3;
16416
0
    opcode[2] = 0xe9;
16417
0
    where_to_put_displacement = &opcode[3];
16418
0
    break;
16419
16420
0
  default:
16421
0
    BAD_CASE (fragP->fr_subtype);
16422
0
    break;
16423
0
  }
16424
0
    }
16425
16426
  /* If size if less then four we are sure that the operand fits,
16427
     but if it's 4, then it could be that the displacement is larger
16428
     then -/+ 2GB.  */
16429
0
  if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
16430
0
      && object_64bit
16431
0
      && ((addressT) (displacement_from_opcode_start - extension
16432
0
          + ((addressT) 1 << 31))
16433
0
    > (((addressT) 2 << 31) - 1)))
16434
0
    {
16435
0
      as_bad_where (fragP->fr_file, fragP->fr_line,
16436
0
        _("jump target out of range"));
16437
      /* Make us emit 0.  */
16438
0
      displacement_from_opcode_start = extension;
16439
0
    }
16440
  /* Now put displacement after opcode.  */
16441
0
  md_number_to_chars ((char *) where_to_put_displacement,
16442
0
          (valueT) (displacement_from_opcode_start - extension),
16443
0
          DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
16444
0
  fragP->fr_fix += extension;
16445
0
}
16446

16447
/* Apply a fixup (fixP) to segment data, once it has been determined
16448
   by our caller that we have all the info we need to fix it up.
16449
16450
   Parameter valP is the pointer to the value of the bits.
16451
16452
   On the 386, immediates, displacements, and data pointers are all in
16453
   the same (little-endian) format, so we don't need to care about which
16454
   we are handling.  */
16455
16456
void
16457
md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
16458
0
{
16459
0
  char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
16460
0
  valueT value = *valP;
16461
16462
0
#if !defined (TE_Mach)
16463
0
  if (fixP->fx_pcrel)
16464
0
    {
16465
0
      switch (fixP->fx_r_type)
16466
0
  {
16467
0
  default:
16468
0
    break;
16469
16470
0
  case BFD_RELOC_64:
16471
0
    fixP->fx_r_type = BFD_RELOC_64_PCREL;
16472
0
    break;
16473
0
  case BFD_RELOC_32:
16474
0
  case BFD_RELOC_X86_64_32S:
16475
0
    fixP->fx_r_type = BFD_RELOC_32_PCREL;
16476
0
    break;
16477
0
  case BFD_RELOC_16:
16478
0
    fixP->fx_r_type = BFD_RELOC_16_PCREL;
16479
0
    break;
16480
0
  case BFD_RELOC_8:
16481
0
    fixP->fx_r_type = BFD_RELOC_8_PCREL;
16482
0
    break;
16483
0
  }
16484
0
    }
16485
16486
0
  if (fixP->fx_addsy != NULL
16487
0
      && (fixP->fx_r_type == BFD_RELOC_32_PCREL
16488
0
    || fixP->fx_r_type == BFD_RELOC_64_PCREL
16489
0
    || fixP->fx_r_type == BFD_RELOC_16_PCREL
16490
0
    || fixP->fx_r_type == BFD_RELOC_8_PCREL)
16491
0
      && !use_rela_relocations)
16492
0
    {
16493
      /* This is a hack.  There should be a better way to handle this.
16494
   This covers for the fact that bfd_install_relocation will
16495
   subtract the current location (for partial_inplace, PC relative
16496
   relocations); see more below.  */
16497
0
#if defined (OBJ_ELF) || defined (TE_PE)
16498
0
      value += fixP->fx_where + fixP->fx_frag->fr_address;
16499
0
#endif
16500
0
#ifdef OBJ_ELF
16501
0
      segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
16502
16503
0
      if ((sym_seg == seg
16504
0
     || (symbol_section_p (fixP->fx_addsy)
16505
0
         && sym_seg != absolute_section))
16506
0
    && !generic_force_reloc (fixP))
16507
0
  {
16508
    /* Yes, we add the values in twice.  This is because
16509
       bfd_install_relocation subtracts them out again.  I think
16510
       bfd_install_relocation is broken, but I don't dare change
16511
       it.  FIXME.  */
16512
0
    value += fixP->fx_where + fixP->fx_frag->fr_address;
16513
0
  }
16514
0
#endif
16515
#if defined (OBJ_COFF) && defined (TE_PE)
16516
      /* For some reason, the PE format does not store a
16517
   section address offset for a PC relative symbol.  */
16518
      if (S_GET_SEGMENT (fixP->fx_addsy) != seg
16519
    || S_IS_WEAK (fixP->fx_addsy))
16520
  value += md_pcrel_from (fixP);
16521
#endif
16522
0
    }
16523
#if defined (OBJ_COFF) && defined (TE_PE)
16524
  if (fixP->fx_addsy != NULL
16525
      && S_IS_WEAK (fixP->fx_addsy)
16526
      /* PR 16858: Do not modify weak function references.  */
16527
      && ! fixP->fx_pcrel)
16528
    {
16529
#if !defined (TE_PEP)
16530
      /* For x86 PE weak function symbols are neither PC-relative
16531
   nor do they set S_IS_FUNCTION.  So the only reliable way
16532
   to detect them is to check the flags of their containing
16533
   section.  */
16534
      if (S_GET_SEGMENT (fixP->fx_addsy) != NULL
16535
    && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE)
16536
  ;
16537
      else
16538
#endif
16539
      value -= S_GET_VALUE (fixP->fx_addsy);
16540
    }
16541
#endif
16542
16543
  /* Fix a few things - the dynamic linker expects certain values here,
16544
     and we must not disappoint it.  */
16545
0
#ifdef OBJ_ELF
16546
0
  if (fixP->fx_addsy)
16547
0
    switch (fixP->fx_r_type)
16548
0
      {
16549
0
      case BFD_RELOC_386_PLT32:
16550
0
      case BFD_RELOC_X86_64_PLT32:
16551
  /* Make the jump instruction point to the address of the operand.
16552
     At runtime we merely add the offset to the actual PLT entry.
16553
     NB: Subtract the offset size only for jump instructions.  */
16554
0
  if (fixP->fx_pcrel)
16555
0
    value = -4;
16556
0
  break;
16557
16558
0
      case BFD_RELOC_386_TLS_GD:
16559
0
      case BFD_RELOC_386_TLS_LDM:
16560
0
      case BFD_RELOC_386_TLS_IE_32:
16561
0
      case BFD_RELOC_386_TLS_IE:
16562
0
      case BFD_RELOC_386_TLS_GOTIE:
16563
0
      case BFD_RELOC_386_TLS_GOTDESC:
16564
0
      case BFD_RELOC_X86_64_TLSGD:
16565
0
      case BFD_RELOC_X86_64_TLSLD:
16566
0
      case BFD_RELOC_X86_64_GOTTPOFF:
16567
0
      case BFD_RELOC_X86_64_CODE_4_GOTTPOFF:
16568
0
      case BFD_RELOC_X86_64_CODE_5_GOTTPOFF:
16569
0
      case BFD_RELOC_X86_64_CODE_6_GOTTPOFF:
16570
0
      case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
16571
0
      case BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC:
16572
0
      case BFD_RELOC_X86_64_CODE_5_GOTPC32_TLSDESC:
16573
0
      case BFD_RELOC_X86_64_CODE_6_GOTPC32_TLSDESC:
16574
0
  value = 0; /* Fully resolved at runtime.  No addend.  */
16575
  /* Fallthrough */
16576
0
      case BFD_RELOC_386_TLS_LE:
16577
0
      case BFD_RELOC_386_TLS_LDO_32:
16578
0
      case BFD_RELOC_386_TLS_LE_32:
16579
0
      case BFD_RELOC_X86_64_DTPOFF32:
16580
0
      case BFD_RELOC_X86_64_DTPOFF64:
16581
0
      case BFD_RELOC_X86_64_TPOFF32:
16582
0
      case BFD_RELOC_X86_64_TPOFF64:
16583
0
  S_SET_THREAD_LOCAL (fixP->fx_addsy);
16584
0
  break;
16585
16586
0
      case BFD_RELOC_386_TLS_DESC_CALL:
16587
0
      case BFD_RELOC_X86_64_TLSDESC_CALL:
16588
0
  value = 0; /* Fully resolved at runtime.  No addend.  */
16589
0
  S_SET_THREAD_LOCAL (fixP->fx_addsy);
16590
0
  fixP->fx_done = 0;
16591
0
  return;
16592
16593
0
      case BFD_RELOC_VTABLE_INHERIT:
16594
0
      case BFD_RELOC_VTABLE_ENTRY:
16595
0
  fixP->fx_done = 0;
16596
0
  return;
16597
16598
0
      default:
16599
0
  break;
16600
0
      }
16601
0
#endif /* OBJ_ELF  */
16602
16603
  /* If not 64bit, massage value, to account for wraparound when !BFD64.  */
16604
0
  if (!object_64bit)
16605
0
    value = extend_to_32bit_address (value);
16606
16607
0
  *valP = value;
16608
0
#endif /* !defined (TE_Mach)  */
16609
16610
  /* Are we finished with this relocation now?  */
16611
0
  if (fixP->fx_addsy == NULL)
16612
0
    {
16613
0
      fixP->fx_done = 1;
16614
0
      switch (fixP->fx_r_type)
16615
0
  {
16616
0
  case BFD_RELOC_X86_64_32S:
16617
0
    fixP->fx_signed = 1;
16618
0
    break;
16619
16620
0
  default:
16621
0
    break;
16622
0
  }
16623
0
    }
16624
#if defined (OBJ_COFF) && defined (TE_PE)
16625
  else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
16626
    {
16627
      fixP->fx_done = 0;
16628
      /* Remember value for tc_gen_reloc.  */
16629
      fixP->fx_addnumber = value;
16630
      /* Clear out the frag for now.  */
16631
      value = 0;
16632
    }
16633
#endif
16634
0
  else if (use_rela_relocations)
16635
0
    {
16636
0
      if (!disallow_64bit_reloc || fixP->fx_r_type == NO_RELOC)
16637
0
  fixP->fx_no_overflow = 1;
16638
      /* Remember value for tc_gen_reloc.  */
16639
0
      fixP->fx_addnumber = value;
16640
0
      value = 0;
16641
0
    }
16642
16643
0
  md_number_to_chars (p, value, fixP->fx_size);
16644
0
}
16645

16646
const char *
16647
md_atof (int type, char *litP, int *sizeP)
16648
0
{
16649
  /* This outputs the LITTLENUMs in REVERSE order;
16650
     in accord with the bigendian 386.  */
16651
0
  return ieee_md_atof (type, litP, sizeP, false);
16652
0
}
16653

16654
static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
16655
16656
static char *
16657
output_invalid (int c)
16658
0
{
16659
0
  if (ISPRINT (c))
16660
0
    snprintf (output_invalid_buf, sizeof (output_invalid_buf),
16661
0
        "'%c'", c);
16662
0
  else
16663
0
    snprintf (output_invalid_buf, sizeof (output_invalid_buf),
16664
0
        "(0x%x)", (unsigned char) c);
16665
0
  return output_invalid_buf;
16666
0
}
16667
16668
/* Verify that @r can be used in the current context.  */
16669
16670
static bool check_register (const reg_entry *r)
16671
0
{
16672
0
  if (allow_pseudo_reg)
16673
0
    return true;
16674
16675
0
  if (operand_type_all_zero (&r->reg_type))
16676
0
    return false;
16677
16678
0
  if ((r->reg_type.bitfield.dword
16679
0
       || (r->reg_type.bitfield.class == SReg && r->reg_num > 3)
16680
0
       || r->reg_type.bitfield.class == RegCR
16681
0
       || r->reg_type.bitfield.class == RegDR)
16682
0
      && !cpu_arch_flags.bitfield.cpui386)
16683
0
    return false;
16684
16685
0
  if (r->reg_type.bitfield.class == RegTR
16686
0
      && (flag_code == CODE_64BIT
16687
0
    || !cpu_arch_flags.bitfield.cpui386
16688
0
    || cpu_arch_isa_flags.bitfield.cpui586
16689
0
    || cpu_arch_isa_flags.bitfield.cpui686))
16690
0
    return false;
16691
16692
0
  if (r->reg_type.bitfield.class == RegMMX && !cpu_arch_flags.bitfield.cpummx)
16693
0
    return false;
16694
16695
0
  if (!cpu_arch_flags.bitfield.cpuavx512f)
16696
0
    {
16697
0
      if (r->reg_type.bitfield.zmmword
16698
0
    || r->reg_type.bitfield.class == RegMask)
16699
0
  return false;
16700
16701
0
      if (!cpu_arch_flags.bitfield.cpuavx)
16702
0
  {
16703
0
    if (r->reg_type.bitfield.ymmword)
16704
0
      return false;
16705
16706
0
    if (!cpu_arch_flags.bitfield.cpusse && r->reg_type.bitfield.xmmword)
16707
0
      return false;
16708
0
  }
16709
0
    }
16710
16711
0
  if (r->reg_type.bitfield.zmmword)
16712
0
    {
16713
0
      if (vector_size < VSZ512)
16714
0
  return false;
16715
16716
      /* Don't update pp when not dealing with insn operands.  */
16717
0
      switch (current_templates.start ? pp.encoding : encoding_evex)
16718
0
  {
16719
0
  case encoding_default:
16720
0
  case encoding_egpr:
16721
0
    pp.encoding = encoding_evex512;
16722
0
    break;
16723
0
  case encoding_evex:
16724
0
  case encoding_evex512:
16725
0
    break;
16726
0
  default:
16727
0
    pp.encoding = encoding_error;
16728
0
    break;
16729
0
  }
16730
0
    }
16731
16732
0
  if (vector_size < VSZ256 && r->reg_type.bitfield.ymmword)
16733
0
    return false;
16734
16735
0
  if (r->reg_type.bitfield.tmmword
16736
0
      && (!cpu_arch_flags.bitfield.cpuamx_tile
16737
0
          || flag_code != CODE_64BIT))
16738
0
    return false;
16739
16740
0
  if (r->reg_type.bitfield.class == RegBND && !cpu_arch_flags.bitfield.cpumpx)
16741
0
    return false;
16742
16743
  /* Don't allow fake index register unless allow_index_reg isn't 0. */
16744
0
  if (!allow_index_reg && r->reg_num == RegIZ)
16745
0
    return false;
16746
16747
  /* Upper 16 vector registers are only available with VREX in 64bit
16748
     mode, and require EVEX encoding.  */
16749
0
  if (r->reg_flags & RegVRex)
16750
0
    {
16751
0
      if (!cpu_arch_flags.bitfield.cpuavx512f
16752
0
    || flag_code != CODE_64BIT)
16753
0
  return false;
16754
16755
      /* Don't update pp when not dealing with insn operands.  */
16756
0
      switch (current_templates.start ? pp.encoding : encoding_evex)
16757
0
  {
16758
0
    case encoding_default:
16759
0
    case encoding_egpr:
16760
0
    case encoding_evex512:
16761
0
      pp.encoding = encoding_evex;
16762
0
      break;
16763
0
    case encoding_evex:
16764
0
      break;
16765
0
    default:
16766
0
      pp.encoding = encoding_error;
16767
0
      break;
16768
0
  }
16769
0
    }
16770
16771
0
  if (r->reg_flags & RegRex2)
16772
0
    {
16773
0
      if (!cpu_arch_flags.bitfield.cpuapx_f
16774
0
    || flag_code != CODE_64BIT)
16775
0
  return false;
16776
16777
      /* Don't update pp when not dealing with insn operands.  */
16778
0
      switch (current_templates.start ? pp.encoding : encoding_egpr)
16779
0
  {
16780
0
  case encoding_default:
16781
0
    pp.encoding = encoding_egpr;
16782
0
    break;
16783
0
  case encoding_egpr:
16784
0
  case encoding_evex:
16785
0
  case encoding_evex512:
16786
0
    break;
16787
0
  default:
16788
0
    pp.encoding = encoding_error;
16789
0
    break;
16790
0
  }
16791
0
    }
16792
16793
0
  if (((r->reg_flags & (RegRex64 | RegRex)) || r->reg_type.bitfield.qword)
16794
0
      && (!cpu_arch_flags.bitfield.cpu64
16795
0
    || r->reg_type.bitfield.class != RegCR
16796
0
    || dot_insn ())
16797
0
      && flag_code != CODE_64BIT)
16798
0
    return false;
16799
16800
0
  if (r->reg_type.bitfield.class == SReg && r->reg_num == RegFlat
16801
0
      && !intel_syntax)
16802
0
    return false;
16803
16804
0
  return true;
16805
0
}
16806
16807
/* REG_STRING starts *before* REGISTER_PREFIX.  */
16808
16809
static const reg_entry *
16810
parse_real_register (const char *reg_string, char **end_op)
16811
0
{
16812
0
  const char *s = reg_string;
16813
0
  char *p;
16814
0
  char reg_name_given[MAX_REG_NAME_SIZE + 1];
16815
0
  const reg_entry *r;
16816
16817
  /* Skip possible REGISTER_PREFIX and possible whitespace.  */
16818
0
  if (*s == REGISTER_PREFIX)
16819
0
    ++s;
16820
16821
0
  if (is_whitespace (*s))
16822
0
    ++s;
16823
16824
0
  p = reg_name_given;
16825
0
  while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
16826
0
    {
16827
0
      if (p >= reg_name_given + MAX_REG_NAME_SIZE)
16828
0
  return (const reg_entry *) NULL;
16829
0
      s++;
16830
0
    }
16831
16832
0
  if (is_part_of_name (*s))
16833
0
    return (const reg_entry *) NULL;
16834
16835
0
  *end_op = (char *) s;
16836
16837
0
  r = str_hash_find (reg_hash, reg_name_given);
16838
16839
  /* Handle floating point regs, allowing spaces in the (i) part.  */
16840
0
  if (r == reg_st0)
16841
0
    {
16842
0
      if (!cpu_arch_flags.bitfield.cpu8087
16843
0
    && !cpu_arch_flags.bitfield.cpu287
16844
0
    && !cpu_arch_flags.bitfield.cpu387
16845
0
    && !allow_pseudo_reg)
16846
0
  return (const reg_entry *) NULL;
16847
16848
0
      if (is_whitespace (*s))
16849
0
  ++s;
16850
0
      if (*s == '(')
16851
0
  {
16852
0
    ++s;
16853
0
    if (is_whitespace (*s))
16854
0
      ++s;
16855
0
    if (*s >= '0' && *s <= '7')
16856
0
      {
16857
0
        int fpr = *s - '0';
16858
0
        ++s;
16859
0
        if (is_whitespace (*s))
16860
0
    ++s;
16861
0
        if (*s == ')')
16862
0
    {
16863
0
      *end_op = (char *) s + 1;
16864
0
      know (r[fpr].reg_num == fpr);
16865
0
      return r + fpr;
16866
0
    }
16867
0
      }
16868
    /* We have "%st(" then garbage.  */
16869
0
    return (const reg_entry *) NULL;
16870
0
  }
16871
0
    }
16872
16873
0
  return r && check_register (r) ? r : NULL;
16874
0
}
16875
16876
/* REG_STRING starts *before* REGISTER_PREFIX.  */
16877
16878
static const reg_entry *
16879
parse_register (const char *reg_string, char **end_op)
16880
0
{
16881
0
  const reg_entry *r;
16882
16883
0
  if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
16884
0
    r = parse_real_register (reg_string, end_op);
16885
0
  else
16886
0
    r = NULL;
16887
0
  if (!r)
16888
0
    {
16889
0
      char *save = input_line_pointer;
16890
0
      char *buf = xstrdup (reg_string), *name;
16891
0
      symbolS *symbolP;
16892
16893
0
      input_line_pointer = buf;
16894
0
      get_symbol_name (&name);
16895
0
      symbolP = symbol_find (name);
16896
0
      while (symbolP && symbol_equated_p (symbolP))
16897
0
  {
16898
0
    const expressionS *e = symbol_get_value_expression(symbolP);
16899
16900
0
    if (e->X_add_number)
16901
0
      break;
16902
0
    symbolP = e->X_add_symbol;
16903
0
  }
16904
0
      if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
16905
0
  {
16906
0
    const expressionS *e = symbol_get_value_expression (symbolP);
16907
16908
0
    if (e->X_op == O_register)
16909
0
      {
16910
0
        know ((valueT) e->X_add_number < i386_regtab_size);
16911
0
        r = i386_regtab + e->X_add_number;
16912
0
        *end_op = (char *) reg_string + (input_line_pointer - buf);
16913
0
      }
16914
0
    if (r && !check_register (r))
16915
0
      {
16916
0
        as_bad (_("register '%s%s' cannot be used here"),
16917
0
          register_prefix, r->reg_name);
16918
0
        r = &bad_reg;
16919
0
      }
16920
0
  }
16921
0
      input_line_pointer = save;
16922
0
      free (buf);
16923
0
    }
16924
0
  return r;
16925
0
}
16926
16927
int
16928
i386_parse_name (char *name,
16929
     expressionS *e,
16930
     enum expr_mode mode,
16931
     char *nextcharP)
16932
0
{
16933
0
  const reg_entry *r = NULL;
16934
0
  char *end = input_line_pointer;
16935
16936
  /* We only know the terminating character here.  It being double quote could
16937
     be the closing one of a quoted symbol name, or an opening one from a
16938
     following string (or another quoted symbol name).  Since the latter can't
16939
     be valid syntax for anything, bailing in either case is good enough.  */
16940
0
  if (*nextcharP == '"')
16941
0
    return 0;
16942
16943
0
  *end = *nextcharP;
16944
0
  if (*name == REGISTER_PREFIX || allow_naked_reg)
16945
0
    r = parse_real_register (name, &input_line_pointer);
16946
0
  if (r && end <= input_line_pointer)
16947
0
    {
16948
0
      *nextcharP = *input_line_pointer;
16949
0
      *input_line_pointer = 0;
16950
0
      e->X_op = O_register;
16951
0
      e->X_add_number = r - i386_regtab;
16952
0
      return 1;
16953
0
    }
16954
0
  input_line_pointer = end;
16955
0
  *end = 0;
16956
0
  return intel_syntax ? i386_intel_parse_name (name, e, mode) : 0;
16957
0
}
16958
16959
void
16960
md_operand (expressionS *e)
16961
0
{
16962
0
  char *end;
16963
0
  const reg_entry *r;
16964
16965
0
  switch (*input_line_pointer)
16966
0
    {
16967
0
    case REGISTER_PREFIX:
16968
0
      r = parse_real_register (input_line_pointer, &end);
16969
0
      if (r)
16970
0
  {
16971
0
    e->X_op = O_register;
16972
0
    e->X_add_number = r - i386_regtab;
16973
0
    input_line_pointer = end;
16974
0
  }
16975
0
      break;
16976
16977
0
    case '[':
16978
0
      gas_assert (intel_syntax);
16979
0
      end = input_line_pointer++;
16980
0
      expression (e);
16981
0
      if (*input_line_pointer == ']')
16982
0
  {
16983
0
    ++input_line_pointer;
16984
0
    e->X_op_symbol = make_expr_symbol (e);
16985
0
    e->X_add_symbol = NULL;
16986
0
    e->X_add_number = 0;
16987
0
    e->X_op = O_index;
16988
0
  }
16989
0
      else
16990
0
  {
16991
0
    e->X_op = O_absent;
16992
0
    input_line_pointer = end;
16993
0
  }
16994
0
      break;
16995
0
    }
16996
0
}
16997
16998
#ifdef BFD64
16999
/* To maintain consistency with !BFD64 builds of gas record, whether any
17000
   (binary) operator was involved in an expression.  As expressions are
17001
   evaluated in only 32 bits when !BFD64, we use this to decide whether to
17002
   truncate results.  */
17003
bool i386_record_operator (operatorT op,
17004
         const expressionS *left,
17005
         const expressionS *right)
17006
0
{
17007
0
  if (op == O_absent)
17008
0
    return false;
17009
17010
0
  if (!left)
17011
0
    {
17012
      /* Since the expression parser applies unary operators fine to bignum
17013
   operands, we don't need to be concerned of respective operands not
17014
   fitting in 32 bits.  */
17015
0
      if (right->X_op == O_constant && right->X_unsigned
17016
0
    && !fits_in_unsigned_long (right->X_add_number))
17017
0
  return false;
17018
0
    }
17019
  /* This isn't entirely right: The pattern can also result when constant
17020
     expressions are folded (e.g. 0xffffffff + 1).  */
17021
0
  else if ((left->X_op == O_constant && left->X_unsigned
17022
0
      && !fits_in_unsigned_long (left->X_add_number))
17023
0
     || (right->X_op == O_constant && right->X_unsigned
17024
0
         && !fits_in_unsigned_long (right->X_add_number)))
17025
0
    expr_mode = expr_large_value;
17026
17027
0
  if (expr_mode != expr_large_value)
17028
0
    expr_mode = expr_operator_present;
17029
17030
0
  return false;
17031
0
}
17032
#endif
17033

17034
const char md_shortopts[] =
17035
#ifdef OBJ_ELF
17036
  "kVQ:"
17037
# ifdef TE_SOLARIS
17038
  "s"
17039
# endif
17040
#endif
17041
  "qnO::";
17042
17043
0
#define OPTION_32 (OPTION_MD_BASE + 0)
17044
0
#define OPTION_64 (OPTION_MD_BASE + 1)
17045
0
#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
17046
0
#define OPTION_MARCH (OPTION_MD_BASE + 3)
17047
0
#define OPTION_MTUNE (OPTION_MD_BASE + 4)
17048
0
#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
17049
0
#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
17050
0
#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
17051
0
#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
17052
0
#define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
17053
0
#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
17054
0
#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
17055
0
#define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
17056
0
#define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
17057
0
#define OPTION_X32 (OPTION_MD_BASE + 14)
17058
0
#define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
17059
0
#define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
17060
0
#define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
17061
#define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
17062
0
#define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
17063
0
#define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
17064
0
#define OPTION_MSHARED (OPTION_MD_BASE + 21)
17065
0
#define OPTION_MAMD64 (OPTION_MD_BASE + 22)
17066
0
#define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
17067
0
#define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
17068
0
#define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25)
17069
0
#define OPTION_MVEXWIG (OPTION_MD_BASE + 26)
17070
0
#define OPTION_MALIGN_BRANCH_BOUNDARY (OPTION_MD_BASE + 27)
17071
0
#define OPTION_MALIGN_BRANCH_PREFIX_SIZE (OPTION_MD_BASE + 28)
17072
0
#define OPTION_MALIGN_BRANCH (OPTION_MD_BASE + 29)
17073
0
#define OPTION_MBRANCHES_WITH_32B_BOUNDARIES (OPTION_MD_BASE + 30)
17074
0
#define OPTION_MLFENCE_AFTER_LOAD (OPTION_MD_BASE + 31)
17075
0
#define OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH (OPTION_MD_BASE + 32)
17076
0
#define OPTION_MLFENCE_BEFORE_RET (OPTION_MD_BASE + 33)
17077
0
#define OPTION_MUSE_UNALIGNED_VECTOR_MOVE (OPTION_MD_BASE + 34)
17078
0
#define OPTION_MTLS_CHECK (OPTION_MD_BASE + 35)
17079
17080
const struct option md_longopts[] =
17081
{
17082
  {"32", no_argument, NULL, OPTION_32},
17083
#if (defined (OBJ_ELF) || defined (TE_PE) || defined (OBJ_MACH_O)) \
17084
    && defined (BFD64)
17085
  {"64", no_argument, NULL, OPTION_64},
17086
#endif
17087
#ifdef OBJ_ELF
17088
# ifdef BFD64
17089
  {"x32", no_argument, NULL, OPTION_X32},
17090
# endif
17091
  {"mshared", no_argument, NULL, OPTION_MSHARED},
17092
  {"mx86-used-note", required_argument, NULL, OPTION_X86_USED_NOTE},
17093
#endif
17094
  {"divide", no_argument, NULL, OPTION_DIVIDE},
17095
  {"march", required_argument, NULL, OPTION_MARCH},
17096
  {"mtune", required_argument, NULL, OPTION_MTUNE},
17097
  {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
17098
  {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
17099
  {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
17100
  {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
17101
  {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
17102
  {"muse-unaligned-vector-move", no_argument, NULL, OPTION_MUSE_UNALIGNED_VECTOR_MOVE},
17103
  {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
17104
  {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
17105
  {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
17106
  {"mvexwig", required_argument, NULL, OPTION_MVEXWIG},
17107
  {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
17108
  {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG},
17109
  {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG},
17110
# if defined (TE_PE) || defined (TE_PEP)
17111
  {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ},
17112
#endif
17113
  {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX},
17114
  {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD},
17115
  {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS},
17116
  {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG},
17117
  {"malign-branch-boundary", required_argument, NULL, OPTION_MALIGN_BRANCH_BOUNDARY},
17118
  {"malign-branch-prefix-size", required_argument, NULL, OPTION_MALIGN_BRANCH_PREFIX_SIZE},
17119
  {"malign-branch", required_argument, NULL, OPTION_MALIGN_BRANCH},
17120
  {"mbranches-within-32B-boundaries", no_argument, NULL, OPTION_MBRANCHES_WITH_32B_BOUNDARIES},
17121
  {"mlfence-after-load", required_argument, NULL, OPTION_MLFENCE_AFTER_LOAD},
17122
  {"mlfence-before-indirect-branch", required_argument, NULL,
17123
   OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH},
17124
  {"mlfence-before-ret", required_argument, NULL, OPTION_MLFENCE_BEFORE_RET},
17125
  {"mamd64", no_argument, NULL, OPTION_MAMD64},
17126
  {"mintel64", no_argument, NULL, OPTION_MINTEL64},
17127
  {"mtls-check", required_argument, NULL, OPTION_MTLS_CHECK},
17128
  {NULL, no_argument, NULL, 0}
17129
};
17130
const size_t md_longopts_size = sizeof (md_longopts);
17131
17132
int
17133
md_parse_option (int c, const char *arg)
17134
0
{
17135
0
  unsigned int j;
17136
0
  char *arch, *next, *saved, *type;
17137
17138
0
  switch (c)
17139
0
    {
17140
0
    case 'n':
17141
0
      optimize_align_code = 0;
17142
0
      break;
17143
17144
0
    case 'q':
17145
0
      quiet_warnings = 1;
17146
0
      break;
17147
17148
0
#ifdef OBJ_ELF
17149
      /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
17150
   should be emitted or not.  FIXME: Not implemented.  */
17151
0
    case 'Q':
17152
0
      if ((arg[0] != 'y' && arg[0] != 'n') || arg[1])
17153
0
  return 0;
17154
0
      break;
17155
17156
      /* -V: SVR4 argument to print version ID.  */
17157
0
    case 'V':
17158
0
      print_version_id ();
17159
0
      break;
17160
17161
      /* -k: Ignore for FreeBSD compatibility.  */
17162
0
    case 'k':
17163
0
      break;
17164
17165
# ifdef TE_SOLARIS
17166
    case 's':
17167
      /* -s: On i386 Solaris, this tells the native assembler to use
17168
   .stab instead of .stab.excl.  We always use .stab anyhow.  */
17169
      break;
17170
# endif
17171
17172
0
    case OPTION_MSHARED:
17173
0
      shared = 1;
17174
0
      break;
17175
17176
0
    case OPTION_X86_USED_NOTE:
17177
0
      if (strcasecmp (arg, "yes") == 0)
17178
0
        x86_used_note = 1;
17179
0
      else if (strcasecmp (arg, "no") == 0)
17180
0
        x86_used_note = 0;
17181
0
      else
17182
0
        as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg);
17183
0
      break;
17184
0
#endif
17185
17186
0
#ifdef BFD64
17187
17188
0
#if (defined (OBJ_ELF) || defined (TE_PE) || defined (OBJ_MACH_O))
17189
0
    case OPTION_64:
17190
0
      {
17191
0
  const char **list, **l;
17192
17193
0
  list = bfd_target_list ();
17194
0
  for (l = list; *l != NULL; l++)
17195
0
    if (startswith (*l, "elf64-x86-64")
17196
0
        || strcmp (*l, "coff-x86-64") == 0
17197
0
        || strcmp (*l, "pe-x86-64") == 0
17198
0
        || strcmp (*l, "pei-x86-64") == 0
17199
0
        || strcmp (*l, "mach-o-x86-64") == 0)
17200
0
      {
17201
0
        default_arch = "x86_64";
17202
0
        break;
17203
0
      }
17204
0
  if (*l == NULL)
17205
0
    as_fatal (_("no compiled in support for x86_64"));
17206
0
  free (list);
17207
0
      }
17208
0
      break;
17209
0
#endif
17210
17211
0
#ifdef OBJ_ELF
17212
0
    case OPTION_X32:
17213
0
      {
17214
0
  const char **list, **l;
17215
17216
0
  list = bfd_target_list ();
17217
0
  for (l = list; *l != NULL; l++)
17218
0
    if (startswith (*l, "elf32-x86-64"))
17219
0
      {
17220
0
        default_arch = "x86_64:32";
17221
0
        break;
17222
0
      }
17223
0
  if (*l == NULL)
17224
0
    as_fatal (_("no compiled in support for 32bit x86_64"));
17225
0
  free (list);
17226
0
      }
17227
0
      break;
17228
0
#endif
17229
17230
0
#endif /* BFD64 */
17231
17232
0
    case OPTION_32:
17233
0
      {
17234
0
  const char **list, **l;
17235
17236
0
  list = bfd_target_list ();
17237
0
  for (l = list; *l != NULL; l++)
17238
0
    if (strstr (*l, "-i386")
17239
0
        || strstr (*l, "-go32"))
17240
0
      {
17241
0
        default_arch = "i386";
17242
0
        break;
17243
0
      }
17244
0
  if (*l == NULL)
17245
0
    as_fatal (_("no compiled in support for ix86"));
17246
0
  free (list);
17247
0
      }
17248
0
      break;
17249
17250
0
    case OPTION_DIVIDE:
17251
#ifdef SVR4_COMMENT_CHARS
17252
      {
17253
  char *n, *t;
17254
  const char *s;
17255
17256
  n = XNEWVEC (char, strlen (i386_comment_chars) + 1);
17257
  t = n;
17258
  for (s = i386_comment_chars; *s != '\0'; s++)
17259
    if (*s != '/')
17260
      *t++ = *s;
17261
  *t = '\0';
17262
  i386_comment_chars = n;
17263
      }
17264
#endif
17265
0
      break;
17266
17267
0
    case OPTION_MARCH:
17268
0
      saved = xstrdup (arg);
17269
0
      arch = saved;
17270
      /* Allow -march=+nosse.  */
17271
0
      if (*arch == '+')
17272
0
  arch++;
17273
0
      do
17274
0
  {
17275
0
    char *vsz;
17276
17277
0
    if (*arch == '.')
17278
0
      as_fatal (_("invalid -march= option: `%s'"), arg);
17279
0
    next = strchr (arch, '+');
17280
0
    if (next)
17281
0
      *next++ = '\0';
17282
0
    vsz = strchr (arch, '/');
17283
0
    if (vsz)
17284
0
      *vsz++ = '\0';
17285
0
    for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
17286
0
      {
17287
0
        if (vsz && cpu_arch[j].vsz != vsz_set)
17288
0
    continue;
17289
17290
0
        if (arch == saved && cpu_arch[j].type != PROCESSOR_NONE
17291
0
            && strcmp (arch, cpu_arch[j].name) == 0)
17292
0
    {
17293
      /* Processor.  */
17294
0
      if (! cpu_arch[j].enable.bitfield.cpui386)
17295
0
        continue;
17296
17297
0
      cpu_arch_name = cpu_arch[j].name;
17298
0
      free (cpu_sub_arch_name);
17299
0
      cpu_sub_arch_name = NULL;
17300
0
      cpu_arch_flags = cpu_arch[j].enable;
17301
0
      cpu_arch_isa = cpu_arch[j].type;
17302
0
      cpu_arch_isa_flags = cpu_arch[j].enable;
17303
0
      if (!cpu_arch_tune_set)
17304
0
        cpu_arch_tune = cpu_arch_isa;
17305
0
      vector_size = VSZ_DEFAULT;
17306
0
      break;
17307
0
    }
17308
0
        else if (cpu_arch[j].type == PROCESSOR_NONE
17309
0
           && strcmp (arch, cpu_arch[j].name) == 0
17310
0
           && !cpu_flags_all_zero (&cpu_arch[j].enable))
17311
0
    {
17312
      /* ISA extension.  */
17313
0
      isa_enable (j);
17314
17315
0
      switch (cpu_arch[j].vsz)
17316
0
        {
17317
0
        default:
17318
0
          break;
17319
17320
0
        case vsz_set:
17321
0
          if (vsz)
17322
0
      {
17323
0
        char *end;
17324
0
        unsigned long val = strtoul (vsz, &end, 0);
17325
17326
0
        if (*end)
17327
0
          val = 0;
17328
0
        switch (val)
17329
0
          {
17330
0
          case 512: vector_size = VSZ512; break;
17331
0
          case 256: vector_size = VSZ256; break;
17332
0
          case 128: vector_size = VSZ128; break;
17333
0
          default:
17334
0
            as_warn (_("Unrecognized vector size specifier ignored"));
17335
0
            break;
17336
0
          }
17337
0
        break;
17338
0
      }
17339
      /* Fall through.  */
17340
0
        case vsz_reset:
17341
0
          vector_size = VSZ_DEFAULT;
17342
0
          break;
17343
0
        }
17344
17345
0
      break;
17346
0
    }
17347
0
      }
17348
17349
0
    if (j >= ARRAY_SIZE (cpu_arch) && startswith (arch, "no"))
17350
0
      {
17351
        /* Disable an ISA extension.  */
17352
0
        for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
17353
0
    if (cpu_arch[j].type == PROCESSOR_NONE
17354
0
        && strcmp (arch + 2, cpu_arch[j].name) == 0)
17355
0
      {
17356
0
        isa_disable (j);
17357
0
        if (cpu_arch[j].vsz == vsz_set)
17358
0
          vector_size = VSZ_DEFAULT;
17359
0
        break;
17360
0
      }
17361
0
      }
17362
17363
0
    if (j >= ARRAY_SIZE (cpu_arch))
17364
0
      as_fatal (_("invalid -march= option: `%s'"), arg);
17365
17366
0
    arch = next;
17367
0
  }
17368
0
      while (next != NULL);
17369
0
      free (saved);
17370
0
      break;
17371
17372
0
    case OPTION_MTUNE:
17373
0
      if (*arg == '.')
17374
0
  as_fatal (_("invalid -mtune= option: `%s'"), arg);
17375
0
      for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
17376
0
  {
17377
0
    if (cpu_arch[j].type != PROCESSOR_NONE
17378
0
        && strcmp (arg, cpu_arch[j].name) == 0)
17379
0
      {
17380
0
        cpu_arch_tune_set = 1;
17381
0
        cpu_arch_tune = cpu_arch [j].type;
17382
0
        break;
17383
0
      }
17384
0
  }
17385
0
      if (j >= ARRAY_SIZE (cpu_arch))
17386
0
  as_fatal (_("invalid -mtune= option: `%s'"), arg);
17387
0
      break;
17388
17389
0
    case OPTION_MMNEMONIC:
17390
0
      if (strcasecmp (arg, "att") == 0)
17391
0
  intel_mnemonic = 0;
17392
0
      else if (strcasecmp (arg, "intel") == 0)
17393
0
  intel_mnemonic = 1;
17394
0
      else
17395
0
  as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
17396
0
      break;
17397
17398
0
    case OPTION_MSYNTAX:
17399
0
      if (strcasecmp (arg, "att") == 0)
17400
0
  _set_intel_syntax (0);
17401
0
      else if (strcasecmp (arg, "intel") == 0)
17402
0
  _set_intel_syntax (1);
17403
0
      else
17404
0
  as_fatal (_("invalid -msyntax= option: `%s'"), arg);
17405
0
      break;
17406
17407
0
    case OPTION_MINDEX_REG:
17408
0
      allow_index_reg = 1;
17409
0
      break;
17410
17411
0
    case OPTION_MNAKED_REG:
17412
0
      allow_naked_reg = 1;
17413
0
      register_prefix = "";
17414
0
      break;
17415
17416
0
    case OPTION_MSSE2AVX:
17417
0
      sse2avx = 1;
17418
0
      break;
17419
17420
0
    case OPTION_MUSE_UNALIGNED_VECTOR_MOVE:
17421
0
      use_unaligned_vector_move = 1;
17422
0
      break;
17423
17424
0
    case OPTION_MSSE_CHECK:
17425
0
      if (strcasecmp (arg, "error") == 0)
17426
0
  sse_check = check_error;
17427
0
      else if (strcasecmp (arg, "warning") == 0)
17428
0
  sse_check = check_warning;
17429
0
      else if (strcasecmp (arg, "none") == 0)
17430
0
  sse_check = check_none;
17431
0
      else
17432
0
  as_fatal (_("invalid -msse-check= option: `%s'"), arg);
17433
0
      break;
17434
17435
0
    case OPTION_MOPERAND_CHECK:
17436
0
      if (strcasecmp (arg, "error") == 0)
17437
0
  operand_check = check_error;
17438
0
      else if (strcasecmp (arg, "warning") == 0)
17439
0
  operand_check = check_warning;
17440
0
      else if (strcasecmp (arg, "none") == 0)
17441
0
  operand_check = check_none;
17442
0
      else
17443
0
  as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
17444
0
      break;
17445
17446
0
    case OPTION_MAVXSCALAR:
17447
0
      if (strcasecmp (arg, "128") == 0)
17448
0
  avxscalar = vex128;
17449
0
      else if (strcasecmp (arg, "256") == 0)
17450
0
  avxscalar = vex256;
17451
0
      else
17452
0
  as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
17453
0
      break;
17454
17455
0
    case OPTION_MVEXWIG:
17456
0
      if (strcmp (arg, "0") == 0)
17457
0
  vexwig = vexw0;
17458
0
      else if (strcmp (arg, "1") == 0)
17459
0
  vexwig = vexw1;
17460
0
      else
17461
0
  as_fatal (_("invalid -mvexwig= option: `%s'"), arg);
17462
0
      break;
17463
17464
0
    case OPTION_MADD_BND_PREFIX:
17465
0
      add_bnd_prefix = 1;
17466
0
      break;
17467
17468
0
    case OPTION_MEVEXLIG:
17469
0
      if (strcmp (arg, "128") == 0)
17470
0
  evexlig = evexl128;
17471
0
      else if (strcmp (arg, "256") == 0)
17472
0
  evexlig = evexl256;
17473
0
      else  if (strcmp (arg, "512") == 0)
17474
0
  evexlig = evexl512;
17475
0
      else
17476
0
  as_fatal (_("invalid -mevexlig= option: `%s'"), arg);
17477
0
      break;
17478
17479
0
    case OPTION_MEVEXRCIG:
17480
0
      if (strcmp (arg, "rne") == 0)
17481
0
  evexrcig = rne;
17482
0
      else if (strcmp (arg, "rd") == 0)
17483
0
  evexrcig = rd;
17484
0
      else if (strcmp (arg, "ru") == 0)
17485
0
  evexrcig = ru;
17486
0
      else if (strcmp (arg, "rz") == 0)
17487
0
  evexrcig = rz;
17488
0
      else
17489
0
  as_fatal (_("invalid -mevexrcig= option: `%s'"), arg);
17490
0
      break;
17491
17492
0
    case OPTION_MEVEXWIG:
17493
0
      if (strcmp (arg, "0") == 0)
17494
0
  evexwig = evexw0;
17495
0
      else if (strcmp (arg, "1") == 0)
17496
0
  evexwig = evexw1;
17497
0
      else
17498
0
  as_fatal (_("invalid -mevexwig= option: `%s'"), arg);
17499
0
      break;
17500
17501
# if defined (TE_PE) || defined (TE_PEP)
17502
    case OPTION_MBIG_OBJ:
17503
      use_big_obj = 1;
17504
      break;
17505
#endif
17506
17507
0
    case OPTION_MOMIT_LOCK_PREFIX:
17508
0
      if (strcasecmp (arg, "yes") == 0)
17509
0
        omit_lock_prefix = 1;
17510
0
      else if (strcasecmp (arg, "no") == 0)
17511
0
        omit_lock_prefix = 0;
17512
0
      else
17513
0
        as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg);
17514
0
      break;
17515
17516
0
    case OPTION_MFENCE_AS_LOCK_ADD:
17517
0
      if (strcasecmp (arg, "yes") == 0)
17518
0
        avoid_fence = 1;
17519
0
      else if (strcasecmp (arg, "no") == 0)
17520
0
        avoid_fence = 0;
17521
0
      else
17522
0
        as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg);
17523
0
      break;
17524
17525
0
    case OPTION_MLFENCE_AFTER_LOAD:
17526
0
      if (strcasecmp (arg, "yes") == 0)
17527
0
  lfence_after_load = 1;
17528
0
      else if (strcasecmp (arg, "no") == 0)
17529
0
  lfence_after_load = 0;
17530
0
      else
17531
0
        as_fatal (_("invalid -mlfence-after-load= option: `%s'"), arg);
17532
0
      break;
17533
17534
0
    case OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH:
17535
0
      if (strcasecmp (arg, "all") == 0)
17536
0
  {
17537
0
    lfence_before_indirect_branch = lfence_branch_all;
17538
0
    if (lfence_before_ret == lfence_before_ret_none)
17539
0
      lfence_before_ret = lfence_before_ret_shl;
17540
0
  }
17541
0
      else if (strcasecmp (arg, "memory") == 0)
17542
0
  lfence_before_indirect_branch = lfence_branch_memory;
17543
0
      else if (strcasecmp (arg, "register") == 0)
17544
0
  lfence_before_indirect_branch = lfence_branch_register;
17545
0
      else if (strcasecmp (arg, "none") == 0)
17546
0
  lfence_before_indirect_branch = lfence_branch_none;
17547
0
      else
17548
0
        as_fatal (_("invalid -mlfence-before-indirect-branch= option: `%s'"),
17549
0
      arg);
17550
0
      break;
17551
17552
0
    case OPTION_MLFENCE_BEFORE_RET:
17553
0
      if (strcasecmp (arg, "or") == 0)
17554
0
  lfence_before_ret = lfence_before_ret_or;
17555
0
      else if (strcasecmp (arg, "not") == 0)
17556
0
  lfence_before_ret = lfence_before_ret_not;
17557
0
      else if (strcasecmp (arg, "shl") == 0 || strcasecmp (arg, "yes") == 0)
17558
0
  lfence_before_ret = lfence_before_ret_shl;
17559
0
      else if (strcasecmp (arg, "none") == 0)
17560
0
  lfence_before_ret = lfence_before_ret_none;
17561
0
      else
17562
0
        as_fatal (_("invalid -mlfence-before-ret= option: `%s'"),
17563
0
      arg);
17564
0
      break;
17565
17566
0
    case OPTION_MRELAX_RELOCATIONS:
17567
0
      if (strcasecmp (arg, "yes") == 0)
17568
0
        generate_relax_relocations = 1;
17569
0
      else if (strcasecmp (arg, "no") == 0)
17570
0
        generate_relax_relocations = 0;
17571
0
      else
17572
0
        as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg);
17573
0
      break;
17574
17575
0
    case OPTION_MALIGN_BRANCH_BOUNDARY:
17576
0
      {
17577
0
  char *end;
17578
0
  long int align = strtoul (arg, &end, 0);
17579
0
  if (*end == '\0')
17580
0
    {
17581
0
      if (align == 0)
17582
0
        {
17583
0
    align_branch_power = 0;
17584
0
    break;
17585
0
        }
17586
0
      else if (align >= 16)
17587
0
        {
17588
0
    int align_power;
17589
0
    for (align_power = 0;
17590
0
         (align & 1) == 0;
17591
0
         align >>= 1, align_power++)
17592
0
      continue;
17593
    /* Limit alignment power to 31.  */
17594
0
    if (align == 1 && align_power < 32)
17595
0
      {
17596
0
        align_branch_power = align_power;
17597
0
        break;
17598
0
      }
17599
0
        }
17600
0
    }
17601
0
  as_fatal (_("invalid -malign-branch-boundary= value: %s"), arg);
17602
0
      }
17603
0
      break;
17604
17605
0
    case OPTION_MALIGN_BRANCH_PREFIX_SIZE:
17606
0
      {
17607
0
  char *end;
17608
0
  int align = strtoul (arg, &end, 0);
17609
  /* Some processors only support 5 prefixes.  */
17610
0
  if (*end == '\0' && align >= 0 && align < 6)
17611
0
    {
17612
0
      align_branch_prefix_size = align;
17613
0
      break;
17614
0
    }
17615
0
  as_fatal (_("invalid -malign-branch-prefix-size= value: %s"),
17616
0
      arg);
17617
0
      }
17618
0
      break;
17619
17620
0
    case OPTION_MALIGN_BRANCH:
17621
0
      align_branch = 0;
17622
0
      saved = xstrdup (arg);
17623
0
      type = saved;
17624
0
      do
17625
0
  {
17626
0
    next = strchr (type, '+');
17627
0
    if (next)
17628
0
      *next++ = '\0';
17629
0
    if (strcasecmp (type, "jcc") == 0)
17630
0
      align_branch |= align_branch_jcc_bit;
17631
0
    else if (strcasecmp (type, "fused") == 0)
17632
0
      align_branch |= align_branch_fused_bit;
17633
0
    else if (strcasecmp (type, "jmp") == 0)
17634
0
      align_branch |= align_branch_jmp_bit;
17635
0
    else if (strcasecmp (type, "call") == 0)
17636
0
      align_branch |= align_branch_call_bit;
17637
0
    else if (strcasecmp (type, "ret") == 0)
17638
0
      align_branch |= align_branch_ret_bit;
17639
0
    else if (strcasecmp (type, "indirect") == 0)
17640
0
      align_branch |= align_branch_indirect_bit;
17641
0
    else
17642
0
      as_fatal (_("invalid -malign-branch= option: `%s'"), arg);
17643
0
    type = next;
17644
0
  }
17645
0
      while (next != NULL);
17646
0
      free (saved);
17647
0
      break;
17648
17649
0
    case OPTION_MBRANCHES_WITH_32B_BOUNDARIES:
17650
0
      align_branch_power = 5;
17651
0
      align_branch_prefix_size = 5;
17652
0
      align_branch = (align_branch_jcc_bit
17653
0
          | align_branch_fused_bit
17654
0
          | align_branch_jmp_bit);
17655
0
      break;
17656
17657
0
    case OPTION_MAMD64:
17658
0
      isa64 = amd64;
17659
0
      break;
17660
17661
0
    case OPTION_MINTEL64:
17662
0
      isa64 = intel64;
17663
0
      break;
17664
17665
0
    case 'O':
17666
0
      if (arg == NULL)
17667
0
  {
17668
0
    optimize = 1;
17669
    /* Turn off -Os.  */
17670
0
    optimize_for_space = 0;
17671
0
  }
17672
0
      else if (*arg == 's')
17673
0
  {
17674
0
    optimize_for_space = 1;
17675
    /* Turn on all encoding optimizations.  */
17676
0
    optimize = INT_MAX;
17677
0
  }
17678
0
      else
17679
0
  {
17680
0
    optimize = atoi (arg);
17681
    /* Turn off -Os.  */
17682
0
    optimize_for_space = 0;
17683
0
  }
17684
0
      break;
17685
0
    case OPTION_MTLS_CHECK:
17686
0
      if (strcasecmp (arg, "yes") == 0)
17687
0
  tls_check = true;
17688
0
      else if (strcasecmp (arg, "no") == 0)
17689
0
  tls_check = false;
17690
0
      else
17691
0
  as_fatal (_("invalid -mtls-check= option: `%s'"), arg);
17692
0
      break;
17693
17694
0
    default:
17695
0
      return 0;
17696
0
    }
17697
0
  return 1;
17698
0
}
17699
17700
0
#define MESSAGE_TEMPLATE \
17701
0
"                                                                                "
17702
17703
static char *
17704
output_message (FILE *stream, char *p, char *message, char *start,
17705
    int *left_p, const char *name, int len)
17706
0
{
17707
0
  int size = sizeof (MESSAGE_TEMPLATE);
17708
0
  int left = *left_p;
17709
17710
  /* Reserve 2 spaces for ", " or ",\0" */
17711
0
  left -= len + 2;
17712
17713
  /* Check if there is any room.  */
17714
0
  if (left >= 0)
17715
0
    {
17716
0
      if (p != start)
17717
0
  {
17718
0
    *p++ = ',';
17719
0
    *p++ = ' ';
17720
0
  }
17721
0
      p = mempcpy (p, name, len);
17722
0
    }
17723
0
  else
17724
0
    {
17725
      /* Output the current message now and start a new one.  */
17726
0
      *p++ = ',';
17727
0
      *p = '\0';
17728
0
      fprintf (stream, "%s\n", message);
17729
0
      p = start;
17730
0
      left = size - (start - message) - len - 2;
17731
17732
0
      gas_assert (left >= 0);
17733
17734
0
      p = mempcpy (p, name, len);
17735
0
    }
17736
17737
0
  *left_p = left;
17738
0
  return p;
17739
0
}
17740
17741
static void
17742
show_arch (FILE *stream, int ext, int check)
17743
0
{
17744
0
  static char message[] = MESSAGE_TEMPLATE;
17745
0
  char *start = message + 27;
17746
0
  char *p;
17747
0
  int size = sizeof (MESSAGE_TEMPLATE);
17748
0
  int left;
17749
0
  const char *name;
17750
0
  int len;
17751
0
  unsigned int j;
17752
17753
0
  p = start;
17754
0
  left = size - (start - message);
17755
17756
0
  if (!ext && check)
17757
0
    {
17758
0
      p = output_message (stream, p, message, start, &left,
17759
0
        STRING_COMMA_LEN ("default"));
17760
0
      p = output_message (stream, p, message, start, &left,
17761
0
        STRING_COMMA_LEN ("push"));
17762
0
      p = output_message (stream, p, message, start, &left,
17763
0
        STRING_COMMA_LEN ("pop"));
17764
0
    }
17765
17766
0
  for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
17767
0
    {
17768
      /* Should it be skipped?  */
17769
0
      if (cpu_arch [j].skip)
17770
0
  continue;
17771
17772
0
      name = cpu_arch [j].name;
17773
0
      len = cpu_arch [j].len;
17774
0
      if (cpu_arch[j].type == PROCESSOR_NONE)
17775
0
  {
17776
    /* It is an extension.  Skip if we aren't asked to show it.  */
17777
0
    if (!ext || cpu_flags_all_zero (&cpu_arch[j].enable))
17778
0
      continue;
17779
0
  }
17780
0
      else if (ext)
17781
0
  {
17782
    /* It is an processor.  Skip if we show only extension.  */
17783
0
    continue;
17784
0
  }
17785
0
      else if (check && ! cpu_arch[j].enable.bitfield.cpui386)
17786
0
  {
17787
    /* It is an impossible processor - skip.  */
17788
0
    continue;
17789
0
  }
17790
17791
0
      p = output_message (stream, p, message, start, &left, name, len);
17792
0
    }
17793
17794
  /* Display disabled extensions.  */
17795
0
  if (ext)
17796
0
    for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
17797
0
      {
17798
0
  char *str;
17799
17800
0
  if (cpu_arch[j].type != PROCESSOR_NONE
17801
0
      || !cpu_flags_all_zero (&cpu_arch[j].enable))
17802
0
    continue;
17803
0
  str = xasprintf ("no%s", cpu_arch[j].name);
17804
0
  p = output_message (stream, p, message, start, &left, str,
17805
0
          strlen (str));
17806
0
  free (str);
17807
0
      }
17808
17809
0
  *p = '\0';
17810
0
  fprintf (stream, "%s\n", message);
17811
0
}
17812
17813
void
17814
md_show_usage (FILE *stream)
17815
0
{
17816
0
#ifdef OBJ_ELF
17817
0
  fprintf (stream, _("\
17818
0
  -Qy, -Qn                ignored\n\
17819
0
  -V                      print assembler version number\n\
17820
0
  -k                      ignored\n"));
17821
0
#endif
17822
0
  fprintf (stream, _("\
17823
0
  -n                      do not optimize code alignment\n\
17824
0
  -O{012s}                attempt some code optimizations\n\
17825
0
  -q                      quieten some warnings\n"));
17826
0
#ifdef OBJ_ELF
17827
0
  fprintf (stream, _("\
17828
0
  -s                      ignored\n"));
17829
0
#endif
17830
0
#ifdef BFD64
17831
0
# ifdef OBJ_ELF
17832
0
  fprintf (stream, _("\
17833
0
  --32/--64/--x32         generate 32bit/64bit/x32 object\n"));
17834
# elif defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)
17835
  fprintf (stream, _("\
17836
  --32/--64               generate 32bit/64bit object\n"));
17837
# endif
17838
0
#endif
17839
#ifdef SVR4_COMMENT_CHARS
17840
  fprintf (stream, _("\
17841
  --divide                do not treat `/' as a comment character\n"));
17842
#else
17843
0
  fprintf (stream, _("\
17844
0
  --divide                ignored\n"));
17845
0
#endif
17846
0
  fprintf (stream, _("\
17847
0
  -march=CPU[,+EXTENSION...]\n\
17848
0
                          generate code for CPU and EXTENSION, CPU is one of:\n"));
17849
0
  show_arch (stream, 0, 1);
17850
0
  fprintf (stream, _("\
17851
0
                          EXTENSION is combination of (possibly \"no\"-prefixed):\n"));
17852
0
  show_arch (stream, 1, 0);
17853
0
  fprintf (stream, _("\
17854
0
  -mtune=CPU              optimize for CPU, CPU is one of:\n"));
17855
0
  show_arch (stream, 0, 0);
17856
0
  fprintf (stream, _("\
17857
0
  -msse2avx               encode SSE instructions with VEX prefix\n"));
17858
0
  fprintf (stream, _("\
17859
0
  -muse-unaligned-vector-move\n\
17860
0
                          encode aligned vector move as unaligned vector move\n"));
17861
0
  fprintf (stream, _("\
17862
0
  -msse-check=[none|error|warning] (default: none)\n\
17863
0
                          check SSE instructions\n"));
17864
0
  fprintf (stream, _("\
17865
0
  -moperand-check=[none|error|warning] (default: warning)\n\
17866
0
                          check operand combinations for validity\n"));
17867
0
  fprintf (stream, _("\
17868
0
  -mavxscalar=[128|256] (default: 128)\n\
17869
0
                          encode scalar AVX instructions with specific vector\n\
17870
0
                           length\n"));
17871
0
  fprintf (stream, _("\
17872
0
  -mvexwig=[0|1] (default: 0)\n\
17873
0
                          encode VEX instructions with specific VEX.W value\n\
17874
0
                           for VEX.W bit ignored instructions\n"));
17875
0
  fprintf (stream, _("\
17876
0
  -mevexlig=[128|256|512] (default: 128)\n\
17877
0
                          encode scalar EVEX instructions with specific vector\n\
17878
0
                           length\n"));
17879
0
  fprintf (stream, _("\
17880
0
  -mevexwig=[0|1] (default: 0)\n\
17881
0
                          encode EVEX instructions with specific EVEX.W value\n\
17882
0
                           for EVEX.W bit ignored instructions\n"));
17883
0
  fprintf (stream, _("\
17884
0
  -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\
17885
0
                          encode EVEX instructions with specific EVEX.RC value\n\
17886
0
                           for SAE-only ignored instructions\n"));
17887
0
  fprintf (stream, _("\
17888
0
  -mmnemonic=[att|intel] "));
17889
0
  if (SYSV386_COMPAT)
17890
0
    fprintf (stream, _("(default: att)\n"));
17891
0
  else
17892
0
    fprintf (stream, _("(default: intel)\n"));
17893
0
  fprintf (stream, _("\
17894
0
                          use AT&T/Intel mnemonic (AT&T syntax only)\n"));
17895
0
  fprintf (stream, _("\
17896
0
  -msyntax=[att|intel] (default: att)\n\
17897
0
                          use AT&T/Intel syntax\n"));
17898
0
  fprintf (stream, _("\
17899
0
  -mindex-reg             support pseudo index registers\n"));
17900
0
  fprintf (stream, _("\
17901
0
  -mnaked-reg             don't require `%%' prefix for registers\n"));
17902
0
  fprintf (stream, _("\
17903
0
  -madd-bnd-prefix        add BND prefix for all valid branches\n"));
17904
0
#ifdef OBJ_ELF
17905
0
  fprintf (stream, _("\
17906
0
  -mshared                disable branch optimization for shared code\n"));
17907
0
  fprintf (stream, _("\
17908
0
  -mx86-used-note=[no|yes] "));
17909
0
  if (DEFAULT_X86_USED_NOTE)
17910
0
    fprintf (stream, _("(default: yes)\n"));
17911
0
  else
17912
0
    fprintf (stream, _("(default: no)\n"));
17913
0
  fprintf (stream, _("\
17914
0
                          generate x86 used ISA and feature properties\n"));
17915
0
#endif
17916
#if defined (TE_PE) || defined (TE_PEP)
17917
  fprintf (stream, _("\
17918
  -mbig-obj               generate big object files\n"));
17919
#endif
17920
0
  fprintf (stream, _("\
17921
0
  -momit-lock-prefix=[no|yes] (default: no)\n\
17922
0
                          strip all lock prefixes\n"));
17923
0
  fprintf (stream, _("\
17924
0
  -mfence-as-lock-add=[no|yes] (default: no)\n\
17925
0
                          encode lfence, mfence and sfence as\n\
17926
0
                           lock addl $0x0, (%%{re}sp)\n"));
17927
0
  fprintf (stream, _("\
17928
0
  -mrelax-relocations=[no|yes] "));
17929
0
  if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS)
17930
0
    fprintf (stream, _("(default: yes)\n"));
17931
0
  else
17932
0
    fprintf (stream, _("(default: no)\n"));
17933
0
  fprintf (stream, _("\
17934
0
                          generate relax relocations\n"));
17935
0
#ifdef OBJ_ELF
17936
0
  fprintf (stream, _("\
17937
0
  -mtls-check=[no|yes] "));
17938
0
  if (DEFAULT_X86_TLS_CHECK)
17939
0
    fprintf (stream, _("(default: yes)\n"));
17940
0
  else
17941
0
    fprintf (stream, _("(default: no)\n"));
17942
0
  fprintf (stream, _("\
17943
0
                          check TLS relocation\n"));
17944
0
#endif
17945
0
  fprintf (stream, _("\
17946
0
  -malign-branch-boundary=NUM (default: 0)\n\
17947
0
                          align branches within NUM byte boundary\n"));
17948
0
  fprintf (stream, _("\
17949
0
  -malign-branch=TYPE[+TYPE...] (default: jcc+fused+jmp)\n\
17950
0
                          TYPE is combination of jcc, fused, jmp, call, ret,\n\
17951
0
                           indirect\n\
17952
0
                          specify types of branches to align\n"));
17953
0
  fprintf (stream, _("\
17954
0
  -malign-branch-prefix-size=NUM (default: 5)\n\
17955
0
                          align branches with NUM prefixes per instruction\n"));
17956
0
  fprintf (stream, _("\
17957
0
  -mbranches-within-32B-boundaries\n\
17958
0
                          align branches within 32 byte boundary\n"));
17959
0
  fprintf (stream, _("\
17960
0
  -mlfence-after-load=[no|yes] (default: no)\n\
17961
0
                          generate lfence after load\n"));
17962
0
  fprintf (stream, _("\
17963
0
  -mlfence-before-indirect-branch=[none|all|register|memory] (default: none)\n\
17964
0
                          generate lfence before indirect near branch\n"));
17965
0
  fprintf (stream, _("\
17966
0
  -mlfence-before-ret=[none|or|not|shl|yes] (default: none)\n\
17967
0
                          generate lfence before ret\n"));
17968
0
  fprintf (stream, _("\
17969
0
  -mamd64                 accept only AMD64 ISA [default]\n"));
17970
0
  fprintf (stream, _("\
17971
0
  -mintel64               accept only Intel64 ISA\n"));
17972
0
}
17973
17974
#if (defined (OBJ_ELF) || defined (TE_PE) || defined (OBJ_MACH_O))
17975
17976
/* Pick the target format to use.  */
17977
17978
const char *
17979
i386_target_format (void)
17980
0
{
17981
0
  if (startswith (default_arch, "x86_64"))
17982
0
    {
17983
0
      update_code_flag (CODE_64BIT, 1);
17984
0
#ifdef OBJ_ELF
17985
0
      if (default_arch[6] == '\0')
17986
0
  x86_elf_abi = X86_64_ABI;
17987
0
      else
17988
0
  x86_elf_abi = X86_64_X32_ABI;
17989
0
#endif
17990
0
    }
17991
0
  else if (!strcmp (default_arch, "i386"))
17992
0
    update_code_flag (CODE_32BIT, 1);
17993
0
  else if (!strcmp (default_arch, "iamcu"))
17994
0
    {
17995
0
      update_code_flag (CODE_32BIT, 1);
17996
0
      if (cpu_arch_isa == PROCESSOR_UNKNOWN)
17997
0
  {
17998
0
    static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS;
17999
0
    cpu_arch_name = "iamcu";
18000
0
    free (cpu_sub_arch_name);
18001
0
    cpu_sub_arch_name = NULL;
18002
0
    cpu_arch_flags = iamcu_flags;
18003
0
    cpu_arch_isa = PROCESSOR_IAMCU;
18004
0
    cpu_arch_isa_flags = iamcu_flags;
18005
0
    if (!cpu_arch_tune_set)
18006
0
      cpu_arch_tune = PROCESSOR_IAMCU;
18007
0
  }
18008
0
      else if (cpu_arch_isa != PROCESSOR_IAMCU)
18009
0
  as_fatal (_("Intel MCU doesn't support `%s' architecture"),
18010
0
      cpu_arch_name);
18011
0
    }
18012
0
  else
18013
0
    as_fatal (_("unknown architecture"));
18014
18015
0
#ifdef OBJ_ELF
18016
0
  if (flag_synth_cfi && x86_elf_abi != X86_64_ABI)
18017
0
    as_fatal (_("SCFI is not supported for this ABI"));
18018
0
#endif
18019
18020
0
  if (cpu_flags_all_zero (&cpu_arch_isa_flags))
18021
0
    cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].enable;
18022
18023
0
  switch (OUTPUT_FLAVOR)
18024
0
    {
18025
#ifdef TE_PE
18026
    case bfd_target_coff_flavour:
18027
      if (flag_code == CODE_64BIT)
18028
  {
18029
    object_64bit = 1;
18030
    return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64";
18031
  }
18032
      return use_big_obj ? "pe-bigobj-i386" : "pe-i386";
18033
#endif
18034
0
#ifdef OBJ_ELF
18035
0
    case bfd_target_elf_flavour:
18036
0
      {
18037
0
  const char *format;
18038
18039
0
  switch (x86_elf_abi)
18040
0
    {
18041
0
    default:
18042
0
      format = ELF_TARGET_FORMAT;
18043
0
#ifndef TE_SOLARIS
18044
0
      tls_get_addr = "___tls_get_addr";
18045
0
#endif
18046
0
      break;
18047
0
    case X86_64_ABI:
18048
0
      use_rela_relocations = 1;
18049
0
      object_64bit = 1;
18050
0
#ifndef TE_SOLARIS
18051
0
      tls_get_addr = "__tls_get_addr";
18052
0
#endif
18053
0
      format = ELF_TARGET_FORMAT64;
18054
0
      break;
18055
0
    case X86_64_X32_ABI:
18056
0
      use_rela_relocations = 1;
18057
0
      object_64bit = 1;
18058
0
#ifndef TE_SOLARIS
18059
0
      tls_get_addr = "__tls_get_addr";
18060
0
#endif
18061
0
      disallow_64bit_reloc = 1;
18062
0
      format = ELF_TARGET_FORMAT32;
18063
0
      break;
18064
0
    }
18065
0
  if (cpu_arch_isa == PROCESSOR_IAMCU)
18066
0
    {
18067
0
      if (x86_elf_abi != I386_ABI)
18068
0
        as_fatal (_("Intel MCU is 32bit only"));
18069
0
      return ELF_TARGET_IAMCU_FORMAT;
18070
0
    }
18071
0
  else
18072
0
    return format;
18073
0
      }
18074
0
#endif
18075
#if defined (OBJ_MACH_O)
18076
    case bfd_target_mach_o_flavour:
18077
      if (flag_code == CODE_64BIT)
18078
  {
18079
    use_rela_relocations = 1;
18080
    object_64bit = 1;
18081
    return "mach-o-x86-64";
18082
  }
18083
      else
18084
  return "mach-o-i386";
18085
#endif
18086
0
    default:
18087
0
      abort ();
18088
0
      return NULL;
18089
0
    }
18090
0
}
18091
18092
#endif /* ELF / PE / MACH_O  */
18093

18094
#ifdef OBJ_ELF
18095
symbolS *
18096
md_undefined_symbol (char *name)
18097
0
{
18098
0
  if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
18099
0
      && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
18100
0
      && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
18101
0
      && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
18102
0
    {
18103
0
      if (!GOT_symbol)
18104
0
  {
18105
0
    if (symbol_find (name))
18106
0
      as_bad (_("GOT already in symbol table"));
18107
0
    GOT_symbol = symbol_new (name, undefined_section,
18108
0
           &zero_address_frag, 0);
18109
0
  };
18110
0
      return GOT_symbol;
18111
0
    }
18112
0
  return NULL;
18113
0
}
18114
#endif
18115
18116
#ifdef OBJ_AOUT
18117
/* Round up a section size to the appropriate boundary.  */
18118
18119
valueT
18120
md_section_align (segT segment, valueT size)
18121
{
18122
  /* For a.out, force the section size to be aligned.  If we don't do
18123
     this, BFD will align it for us, but it will not write out the
18124
     final bytes of the section.  This may be a bug in BFD, but it is
18125
     easier to fix it here since that is how the other a.out targets
18126
     work.  */
18127
  int align = bfd_section_alignment (segment);
18128
18129
  return ((size + (1 << align) - 1) & (-((valueT) 1 << align)));
18130
}
18131
#endif
18132
18133
/* On the i386, PC-relative offsets are relative to the start of the
18134
   next instruction.  That is, the address of the offset, plus its
18135
   size, since the offset is always the last part of the insn.  */
18136
18137
long
18138
md_pcrel_from (fixS *fixP)
18139
0
{
18140
0
  return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
18141
0
}
18142
18143
#ifdef OBJ_AOUT
18144
18145
static void
18146
s_bss (int ignore ATTRIBUTE_UNUSED)
18147
{
18148
  int temp;
18149
18150
  temp = get_absolute_expression ();
18151
  subseg_set (bss_section, (subsegT) temp);
18152
  demand_empty_rest_of_line ();
18153
}
18154
18155
#endif
18156
18157
/* Remember constant directive.  */
18158
18159
void
18160
i386_cons_align (int ignore ATTRIBUTE_UNUSED)
18161
0
{
18162
0
  struct last_insn *last_insn
18163
0
    = &seg_info(now_seg)->tc_segment_info_data.last_insn;
18164
18165
0
  if (bfd_section_flags (now_seg) & SEC_CODE)
18166
0
    {
18167
0
      last_insn->kind = last_insn_directive;
18168
0
      last_insn->name = "constant directive";
18169
0
      last_insn->file = as_where (&last_insn->line);
18170
0
    }
18171
0
}
18172
18173
int
18174
i386_validate_fix (fixS *fixp)
18175
0
{
18176
0
  if (fixp->fx_addsy && S_GET_SEGMENT(fixp->fx_addsy) == reg_section)
18177
0
    {
18178
0
      reloc_howto_type *howto;
18179
18180
0
      howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
18181
0
      as_bad_where (fixp->fx_file, fixp->fx_line,
18182
0
        _("invalid %s relocation against register"),
18183
0
        howto ? howto->name : "<unknown>");
18184
0
      return 0;
18185
0
    }
18186
18187
0
#ifdef OBJ_ELF
18188
0
  if (fixp->fx_r_type == BFD_RELOC_SIZE32
18189
0
      || fixp->fx_r_type == BFD_RELOC_SIZE64)
18190
0
    return fixp->fx_addsy
18191
0
     && (!S_IS_DEFINED (fixp->fx_addsy)
18192
0
         || S_IS_EXTERNAL (fixp->fx_addsy));
18193
18194
  /* BFD_RELOC_X86_64_GOTTPOFF:
18195
      1. fx_tcbit -> BFD_RELOC_X86_64_CODE_4_GOTTPOFF
18196
      2. fx_tcbit2 -> BFD_RELOC_X86_64_CODE_5_GOTTPOFF
18197
      3. fx_tcbit3 -> BFD_RELOC_X86_64_CODE_6_GOTTPOFF
18198
    BFD_RELOC_X86_64_GOTPC32_TLSDESC:
18199
      1. fx_tcbit -> BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC
18200
    BFD_RELOC_32_PCREL:
18201
      1. fx_tcbit && fx_tcbit3 -> BFD_RELOC_X86_64_CODE_5_GOTPCRELX
18202
      2. fx_tcbit -> BFD_RELOC_X86_64_GOTPCRELX
18203
      3. fx_tcbit2 && fx_tcbit3 -> BFD_RELOC_X86_64_CODE_6_GOTPCRELX
18204
      4. fx_tcbit2 -> BFD_RELOC_X86_64_REX_GOTPCRELX
18205
      5. fx_tcbit3 -> BFD_RELOC_X86_64_CODE_4_GOTPCRELX
18206
      6. else -> BFD_RELOC_X86_64_GOTPCREL
18207
   */
18208
0
  if (fixp->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF)
18209
0
    {
18210
0
      if (fixp->fx_tcbit)
18211
0
  fixp->fx_r_type = BFD_RELOC_X86_64_CODE_4_GOTTPOFF;
18212
0
      else if (fixp->fx_tcbit2)
18213
0
  fixp->fx_r_type = BFD_RELOC_X86_64_CODE_5_GOTTPOFF;
18214
0
      else if (fixp->fx_tcbit3)
18215
0
  fixp->fx_r_type = BFD_RELOC_X86_64_CODE_6_GOTTPOFF;
18216
0
    }
18217
0
  else if (fixp->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
18218
0
     && fixp->fx_tcbit)
18219
0
    fixp->fx_r_type = BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC;
18220
0
#endif
18221
18222
0
  if (fixp->fx_subsy)
18223
0
    {
18224
0
      if (fixp->fx_subsy == GOT_symbol)
18225
0
  {
18226
0
    if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
18227
0
      {
18228
0
        if (!object_64bit)
18229
0
    abort ();
18230
0
#ifdef OBJ_ELF
18231
0
        if (fixp->fx_tcbit)
18232
0
    fixp->fx_r_type = fixp->fx_tcbit3
18233
0
          ? BFD_RELOC_X86_64_CODE_5_GOTPCRELX
18234
0
          : BFD_RELOC_X86_64_GOTPCRELX;
18235
0
        else if (fixp->fx_tcbit2)
18236
0
    fixp->fx_r_type = fixp->fx_tcbit3
18237
0
          ? BFD_RELOC_X86_64_CODE_6_GOTPCRELX
18238
0
          : BFD_RELOC_X86_64_REX_GOTPCRELX;
18239
0
        else if (fixp->fx_tcbit3)
18240
0
    fixp->fx_r_type = BFD_RELOC_X86_64_CODE_4_GOTPCRELX;
18241
0
        else
18242
0
#endif
18243
0
    fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
18244
0
      }
18245
0
    else
18246
0
      {
18247
0
        if (!object_64bit)
18248
0
    fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
18249
0
        else
18250
0
    fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
18251
0
      }
18252
0
    fixp->fx_subsy = 0;
18253
0
  }
18254
0
    }
18255
0
#ifdef OBJ_ELF
18256
0
  else
18257
0
    {
18258
      /* NB: Commit 292676c1 resolved PLT32 reloc aganst local symbol
18259
   to section.  Since PLT32 relocation must be against symbols,
18260
   turn such PLT32 relocation into PC32 relocation.  NB: We can
18261
   turn PLT32 relocation into PC32 relocation only for PC-relative
18262
   relocations since non-PC-relative relocations need PLT entries.
18263
       */
18264
0
      if (fixp->fx_addsy
18265
0
    && fixp->fx_pcrel
18266
0
    && (fixp->fx_r_type == BFD_RELOC_386_PLT32
18267
0
        || fixp->fx_r_type == BFD_RELOC_X86_64_PLT32)
18268
0
    && symbol_section_p (fixp->fx_addsy))
18269
0
  fixp->fx_r_type = BFD_RELOC_32_PCREL;
18270
0
      if (!object_64bit)
18271
0
  {
18272
0
    if (fixp->fx_r_type == BFD_RELOC_386_GOT32
18273
0
        && fixp->fx_tcbit2)
18274
0
      fixp->fx_r_type = BFD_RELOC_386_GOT32X;
18275
0
  }
18276
0
    }
18277
0
#endif
18278
18279
0
  return 1;
18280
0
}
18281
18282
arelent *
18283
tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
18284
0
{
18285
0
  arelent *rel;
18286
0
  bfd_reloc_code_real_type code;
18287
18288
0
  switch (fixp->fx_r_type)
18289
0
    {
18290
0
#ifdef OBJ_ELF
18291
0
      symbolS *sym;
18292
18293
0
    case BFD_RELOC_SIZE32:
18294
0
    case BFD_RELOC_SIZE64:
18295
0
      if (fixp->fx_addsy
18296
0
    && !bfd_is_abs_section (S_GET_SEGMENT (fixp->fx_addsy))
18297
0
    && (!fixp->fx_subsy
18298
0
        || bfd_is_abs_section (S_GET_SEGMENT (fixp->fx_subsy))))
18299
0
  sym = fixp->fx_addsy;
18300
0
      else if (fixp->fx_subsy
18301
0
         && !bfd_is_abs_section (S_GET_SEGMENT (fixp->fx_subsy))
18302
0
         && (!fixp->fx_addsy
18303
0
       || bfd_is_abs_section (S_GET_SEGMENT (fixp->fx_addsy))))
18304
0
  sym = fixp->fx_subsy;
18305
0
      else
18306
0
  sym = NULL;
18307
0
      if (sym && S_IS_DEFINED (sym) && !S_IS_EXTERNAL (sym))
18308
0
  {
18309
    /* Resolve size relocation against local symbol to size of
18310
       the symbol plus addend.  */
18311
0
    valueT value = S_GET_SIZE (sym);
18312
18313
0
    if (symbol_get_bfdsym (sym)->flags & BSF_SECTION_SYM)
18314
0
      value = bfd_section_size (S_GET_SEGMENT (sym));
18315
0
    if (sym == fixp->fx_subsy)
18316
0
      {
18317
0
        value = -value;
18318
0
        if (fixp->fx_addsy)
18319
0
          value += S_GET_VALUE (fixp->fx_addsy);
18320
0
      }
18321
0
    else if (fixp->fx_subsy)
18322
0
      value -= S_GET_VALUE (fixp->fx_subsy);
18323
0
    value += fixp->fx_offset;
18324
0
    if (fixp->fx_r_type == BFD_RELOC_SIZE32
18325
0
        && object_64bit
18326
0
        && !fits_in_unsigned_long (value))
18327
0
      as_bad_where (fixp->fx_file, fixp->fx_line,
18328
0
        _("symbol size computation overflow"));
18329
0
    fixp->fx_addsy = NULL;
18330
0
    fixp->fx_subsy = NULL;
18331
0
    md_apply_fix (fixp, (valueT *) &value, NULL);
18332
0
    return NULL;
18333
0
  }
18334
0
      if (!fixp->fx_addsy || fixp->fx_subsy)
18335
0
  {
18336
0
    as_bad_where (fixp->fx_file, fixp->fx_line,
18337
0
      "unsupported expression involving @size");
18338
0
    return NULL;
18339
0
  }
18340
0
#endif
18341
      /* Fall through.  */
18342
18343
0
    case BFD_RELOC_X86_64_PLT32:
18344
0
    case BFD_RELOC_X86_64_GOT32:
18345
0
    case BFD_RELOC_X86_64_GOTPCREL:
18346
0
    case BFD_RELOC_X86_64_GOTPCRELX:
18347
0
    case BFD_RELOC_X86_64_REX_GOTPCRELX:
18348
0
    case BFD_RELOC_X86_64_CODE_4_GOTPCRELX:
18349
0
    case BFD_RELOC_X86_64_CODE_5_GOTPCRELX:
18350
0
    case BFD_RELOC_X86_64_CODE_6_GOTPCRELX:
18351
0
    case BFD_RELOC_386_PLT32:
18352
0
    case BFD_RELOC_386_GOT32:
18353
0
    case BFD_RELOC_386_GOT32X:
18354
0
    case BFD_RELOC_386_GOTOFF:
18355
0
    case BFD_RELOC_386_GOTPC:
18356
0
    case BFD_RELOC_386_TLS_GD:
18357
0
    case BFD_RELOC_386_TLS_LDM:
18358
0
    case BFD_RELOC_386_TLS_LDO_32:
18359
0
    case BFD_RELOC_386_TLS_IE_32:
18360
0
    case BFD_RELOC_386_TLS_IE:
18361
0
    case BFD_RELOC_386_TLS_GOTIE:
18362
0
    case BFD_RELOC_386_TLS_LE_32:
18363
0
    case BFD_RELOC_386_TLS_LE:
18364
0
    case BFD_RELOC_386_TLS_GOTDESC:
18365
0
    case BFD_RELOC_386_TLS_DESC_CALL:
18366
0
    case BFD_RELOC_X86_64_TLSGD:
18367
0
    case BFD_RELOC_X86_64_TLSLD:
18368
0
    case BFD_RELOC_X86_64_DTPOFF32:
18369
0
    case BFD_RELOC_X86_64_DTPOFF64:
18370
0
    case BFD_RELOC_X86_64_GOTTPOFF:
18371
0
    case BFD_RELOC_X86_64_CODE_4_GOTTPOFF:
18372
0
    case BFD_RELOC_X86_64_CODE_5_GOTTPOFF:
18373
0
    case BFD_RELOC_X86_64_CODE_6_GOTTPOFF:
18374
0
    case BFD_RELOC_X86_64_TPOFF32:
18375
0
    case BFD_RELOC_X86_64_TPOFF64:
18376
0
    case BFD_RELOC_X86_64_GOTOFF64:
18377
0
    case BFD_RELOC_X86_64_GOTPC32:
18378
0
    case BFD_RELOC_X86_64_GOT64:
18379
0
    case BFD_RELOC_X86_64_GOTPCREL64:
18380
0
    case BFD_RELOC_X86_64_GOTPC64:
18381
0
    case BFD_RELOC_X86_64_GOTPLT64:
18382
0
    case BFD_RELOC_X86_64_PLTOFF64:
18383
0
    case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
18384
0
    case BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC:
18385
0
    case BFD_RELOC_X86_64_CODE_5_GOTPC32_TLSDESC:
18386
0
    case BFD_RELOC_X86_64_CODE_6_GOTPC32_TLSDESC:
18387
0
    case BFD_RELOC_X86_64_TLSDESC_CALL:
18388
0
    case BFD_RELOC_RVA:
18389
0
    case BFD_RELOC_VTABLE_ENTRY:
18390
0
    case BFD_RELOC_VTABLE_INHERIT:
18391
#ifdef TE_PE
18392
    case BFD_RELOC_32_SECREL:
18393
    case BFD_RELOC_16_SECIDX:
18394
#endif
18395
0
      code = fixp->fx_r_type;
18396
0
      break;
18397
0
    case BFD_RELOC_X86_64_32S:
18398
0
      if (!fixp->fx_pcrel)
18399
0
  {
18400
    /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32.  */
18401
0
    code = fixp->fx_r_type;
18402
0
    break;
18403
0
  }
18404
      /* Fall through.  */
18405
0
    default:
18406
0
      if (fixp->fx_pcrel)
18407
0
  {
18408
0
    switch (fixp->fx_size)
18409
0
      {
18410
0
      default:
18411
0
        as_bad_where (fixp->fx_file, fixp->fx_line,
18412
0
          _("can not do %d byte pc-relative relocation"),
18413
0
          fixp->fx_size);
18414
0
        code = BFD_RELOC_32_PCREL;
18415
0
        break;
18416
0
      case 1: code = BFD_RELOC_8_PCREL;  break;
18417
0
      case 2: code = BFD_RELOC_16_PCREL; break;
18418
0
      case 4: code = BFD_RELOC_32_PCREL; break;
18419
0
#ifdef BFD64
18420
0
      case 8: code = BFD_RELOC_64_PCREL; break;
18421
0
#endif
18422
0
      }
18423
0
  }
18424
0
      else
18425
0
  {
18426
0
    switch (fixp->fx_size)
18427
0
      {
18428
0
      default:
18429
0
        as_bad_where (fixp->fx_file, fixp->fx_line,
18430
0
          _("can not do %d byte relocation"),
18431
0
          fixp->fx_size);
18432
0
        code = BFD_RELOC_32;
18433
0
        break;
18434
0
      case 1: code = BFD_RELOC_8;  break;
18435
0
      case 2: code = BFD_RELOC_16; break;
18436
0
      case 4: code = BFD_RELOC_32; break;
18437
0
#ifdef BFD64
18438
0
      case 8: code = BFD_RELOC_64; break;
18439
0
#endif
18440
0
      }
18441
0
  }
18442
0
      break;
18443
0
    }
18444
18445
0
  if ((code == BFD_RELOC_32
18446
0
       || code == BFD_RELOC_32_PCREL
18447
0
       || code == BFD_RELOC_X86_64_32S)
18448
0
      && GOT_symbol
18449
0
      && fixp->fx_addsy == GOT_symbol)
18450
0
    {
18451
0
      if (!object_64bit)
18452
0
  code = BFD_RELOC_386_GOTPC;
18453
0
      else
18454
0
  code = BFD_RELOC_X86_64_GOTPC32;
18455
0
    }
18456
0
  if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
18457
0
      && GOT_symbol
18458
0
      && fixp->fx_addsy == GOT_symbol)
18459
0
    {
18460
0
      code = BFD_RELOC_X86_64_GOTPC64;
18461
0
    }
18462
18463
0
  rel = notes_alloc (sizeof (arelent));
18464
0
  rel->sym_ptr_ptr = notes_alloc (sizeof (asymbol *));
18465
0
  *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
18466
18467
0
  rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
18468
18469
0
  if (!use_rela_relocations)
18470
0
    {
18471
      /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
18472
   vtable entry to be used in the relocation's section offset.  */
18473
0
      if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
18474
0
  rel->address = fixp->fx_offset;
18475
#if defined (OBJ_COFF) && defined (TE_PE)
18476
      else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
18477
  rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
18478
      else
18479
#endif
18480
0
      rel->addend = 0;
18481
0
    }
18482
  /* Use the rela in 64bit mode.  */
18483
0
  else
18484
0
    {
18485
0
      if (disallow_64bit_reloc)
18486
0
  switch (code)
18487
0
    {
18488
0
    case BFD_RELOC_X86_64_DTPOFF64:
18489
0
    case BFD_RELOC_X86_64_TPOFF64:
18490
0
    case BFD_RELOC_64_PCREL:
18491
0
    case BFD_RELOC_X86_64_GOTOFF64:
18492
0
    case BFD_RELOC_X86_64_GOT64:
18493
0
    case BFD_RELOC_X86_64_GOTPCREL64:
18494
0
    case BFD_RELOC_X86_64_GOTPC64:
18495
0
    case BFD_RELOC_X86_64_GOTPLT64:
18496
0
    case BFD_RELOC_X86_64_PLTOFF64:
18497
0
      as_bad_where (fixp->fx_file, fixp->fx_line,
18498
0
        _("cannot represent relocation type %s in x32 mode"),
18499
0
        bfd_get_reloc_code_name (code));
18500
0
      break;
18501
0
    default:
18502
0
      break;
18503
0
    }
18504
18505
0
      if (!fixp->fx_pcrel)
18506
0
  rel->addend = fixp->fx_offset;
18507
0
      else
18508
0
  switch (code)
18509
0
    {
18510
0
    case BFD_RELOC_X86_64_PLT32:
18511
0
    case BFD_RELOC_X86_64_GOT32:
18512
0
    case BFD_RELOC_X86_64_GOTPCREL:
18513
0
    case BFD_RELOC_X86_64_GOTPCRELX:
18514
0
    case BFD_RELOC_X86_64_REX_GOTPCRELX:
18515
0
    case BFD_RELOC_X86_64_CODE_4_GOTPCRELX:
18516
0
    case BFD_RELOC_X86_64_CODE_5_GOTPCRELX:
18517
0
    case BFD_RELOC_X86_64_CODE_6_GOTPCRELX:
18518
0
    case BFD_RELOC_X86_64_TLSGD:
18519
0
    case BFD_RELOC_X86_64_TLSLD:
18520
0
    case BFD_RELOC_X86_64_GOTTPOFF:
18521
0
    case BFD_RELOC_X86_64_CODE_4_GOTTPOFF:
18522
0
    case BFD_RELOC_X86_64_CODE_5_GOTTPOFF:
18523
0
    case BFD_RELOC_X86_64_CODE_6_GOTTPOFF:
18524
0
    case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
18525
0
    case BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC:
18526
0
    case BFD_RELOC_X86_64_CODE_5_GOTPC32_TLSDESC:
18527
0
    case BFD_RELOC_X86_64_CODE_6_GOTPC32_TLSDESC:
18528
0
    case BFD_RELOC_X86_64_TLSDESC_CALL:
18529
0
      rel->addend = fixp->fx_offset - fixp->fx_size;
18530
0
      break;
18531
0
    default:
18532
0
      rel->addend = (section->vma
18533
0
         - fixp->fx_size
18534
0
         + fixp->fx_addnumber
18535
0
         + md_pcrel_from (fixp));
18536
0
      break;
18537
0
    }
18538
0
    }
18539
18540
0
  rel->howto = bfd_reloc_type_lookup (stdoutput, code);
18541
0
  if (rel->howto == NULL)
18542
0
    {
18543
0
      as_bad_where (fixp->fx_file, fixp->fx_line,
18544
0
        _("cannot represent relocation type %s"),
18545
0
        bfd_get_reloc_code_name (code));
18546
      /* Set howto to a garbage value so that we can keep going.  */
18547
0
      rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
18548
0
      gas_assert (rel->howto != NULL);
18549
0
    }
18550
18551
0
  return rel;
18552
0
}
18553
18554
#include "tc-i386-intel.c"
18555
18556
void
18557
tc_x86_parse_to_dw2regnum (expressionS *exp)
18558
0
{
18559
0
  int saved_naked_reg;
18560
0
  char saved_register_dot;
18561
18562
0
  saved_naked_reg = allow_naked_reg;
18563
0
  allow_naked_reg = 1;
18564
0
  saved_register_dot = register_chars['.'];
18565
0
  register_chars['.'] = '.';
18566
0
  allow_pseudo_reg = 1;
18567
0
  expression_and_evaluate (exp);
18568
0
  allow_pseudo_reg = 0;
18569
0
  register_chars['.'] = saved_register_dot;
18570
0
  allow_naked_reg = saved_naked_reg;
18571
18572
0
  if (exp->X_op == O_register && exp->X_add_number >= 0)
18573
0
    {
18574
0
      exp->X_op = O_illegal;
18575
0
      if ((addressT) exp->X_add_number < i386_regtab_size)
18576
0
  {
18577
0
    exp->X_add_number = i386_regtab[exp->X_add_number]
18578
0
            .dw2_regnum[object_64bit];
18579
0
    if (exp->X_add_number != Dw2Inval)
18580
0
      exp->X_op = O_constant;
18581
0
  }
18582
0
    }
18583
0
}
18584
18585
void
18586
tc_x86_frame_initial_instructions (void)
18587
0
{
18588
0
  cfi_add_CFA_def_cfa (object_64bit ? REG_SP : 4, -x86_cie_data_alignment);
18589
0
  cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
18590
0
}
18591
18592
int
18593
x86_dwarf2_addr_size (void)
18594
0
{
18595
0
#ifdef OBJ_ELF
18596
0
  if (x86_elf_abi == X86_64_X32_ABI)
18597
0
    return 4;
18598
0
#endif
18599
0
  return bfd_arch_bits_per_address (stdoutput) / 8;
18600
0
}
18601
18602
#ifdef TE_PE
18603
void
18604
tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
18605
{
18606
  expressionS exp;
18607
18608
  exp.X_op = O_secrel;
18609
  exp.X_add_symbol = symbol;
18610
  exp.X_add_number = 0;
18611
  emit_expr (&exp, size);
18612
}
18613
#endif
18614
18615
#ifdef OBJ_ELF
18616
int
18617
i386_elf_section_type (const char *str, size_t len)
18618
0
{
18619
0
  if (flag_code == CODE_64BIT
18620
0
      && len == sizeof ("unwind") - 1
18621
0
      && startswith (str, "unwind"))
18622
0
    return SHT_X86_64_UNWIND;
18623
18624
0
  return -1;
18625
0
}
18626
18627
void
18628
i386_elf_section_change_hook (void)
18629
0
{
18630
0
  struct i386_segment_info *info = &seg_info(now_seg)->tc_segment_info_data;
18631
0
  struct i386_segment_info *curr, *prev;
18632
18633
0
  if (info->subseg == now_subseg)
18634
0
    return;
18635
18636
  /* Find the (or make a) list entry to save state into.  */
18637
0
  for (prev = info; (curr = prev->next) != NULL; prev = curr)
18638
0
    if (curr->subseg == info->subseg)
18639
0
      break;
18640
0
  if (!curr)
18641
0
    {
18642
0
      curr = notes_alloc (sizeof (*curr));
18643
0
      curr->subseg = info->subseg;
18644
0
      curr->next = NULL;
18645
0
      prev->next = curr;
18646
0
    }
18647
0
  curr->last_insn = info->last_insn;
18648
18649
  /* Find the list entry to load state from.  */
18650
0
  for (curr = info->next; curr; curr = curr->next)
18651
0
    if (curr->subseg == now_subseg)
18652
0
      break;
18653
0
  if (curr)
18654
0
    info->last_insn = curr->last_insn;
18655
0
  else
18656
0
    memset (&info->last_insn, 0, sizeof (info->last_insn));
18657
0
  info->subseg = now_subseg;
18658
0
}
18659
18660
#ifdef TE_SOLARIS
18661
void
18662
i386_solaris_fix_up_eh_frame (segT sec)
18663
{
18664
  if (flag_code == CODE_64BIT)
18665
    elf_section_type (sec) = SHT_X86_64_UNWIND;
18666
}
18667
#endif
18668
18669
/* For ELF on x86-64, add support for SHF_X86_64_LARGE.  */
18670
18671
bfd_vma
18672
x86_64_section_letter (int letter, const char **ptr_msg)
18673
0
{
18674
0
  if (flag_code == CODE_64BIT)
18675
0
    {
18676
0
      if (letter == 'l')
18677
0
  return SHF_X86_64_LARGE;
18678
18679
0
      *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
18680
0
    }
18681
0
  else
18682
0
    *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
18683
0
  return -1;
18684
0
}
18685
18686
static void
18687
handle_large_common (int small ATTRIBUTE_UNUSED)
18688
0
{
18689
0
  if (flag_code != CODE_64BIT)
18690
0
    {
18691
0
      s_comm_internal (0, elf_common_parse);
18692
0
      as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
18693
0
    }
18694
0
  else
18695
0
    {
18696
0
      static segT lbss_section;
18697
0
      asection *saved_com_section_ptr = elf_com_section_ptr;
18698
0
      asection *saved_bss_section = bss_section;
18699
18700
0
      if (lbss_section == NULL)
18701
0
  {
18702
0
    flagword applicable;
18703
0
    segT seg = now_seg;
18704
0
    subsegT subseg = now_subseg;
18705
18706
    /* The .lbss section is for local .largecomm symbols.  */
18707
0
    lbss_section = subseg_new (".lbss", 0);
18708
0
    applicable = bfd_applicable_section_flags (stdoutput);
18709
0
    bfd_set_section_flags (lbss_section, applicable & SEC_ALLOC);
18710
0
    seg_info (lbss_section)->bss = 1;
18711
18712
0
    subseg_set (seg, subseg);
18713
0
  }
18714
18715
0
      elf_com_section_ptr = &_bfd_elf_large_com_section;
18716
0
      bss_section = lbss_section;
18717
18718
0
      s_comm_internal (0, elf_common_parse);
18719
18720
0
      elf_com_section_ptr = saved_com_section_ptr;
18721
0
      bss_section = saved_bss_section;
18722
0
    }
18723
0
}
18724
#endif /* OBJ_ELF */