Coverage Report

Created: 2025-07-08 11:15

/src/binutils-gdb/opcodes/aarch64-dis.c
Line
Count
Source (jump to first uncovered line)
1
/* aarch64-dis.c -- AArch64 disassembler.
2
   Copyright (C) 2009-2025 Free Software Foundation, Inc.
3
   Contributed by ARM Ltd.
4
5
   This file is part of the GNU opcodes library.
6
7
   This library is free software; you can redistribute it and/or modify
8
   it under the terms of the GNU General Public License as published by
9
   the Free Software Foundation; either version 3, or (at your option)
10
   any later version.
11
12
   It is distributed in the hope that it will be useful, but WITHOUT
13
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
15
   License for more details.
16
17
   You should have received a copy of the GNU General Public License
18
   along with this program; see the file COPYING3. If not,
19
   see <http://www.gnu.org/licenses/>.  */
20
21
#include "sysdep.h"
22
#include <stdint.h>
23
#include "disassemble.h"
24
#include "libiberty.h"
25
#include "opintl.h"
26
#include "aarch64-dis.h"
27
#include "elf-bfd.h"
28
#include "safe-ctype.h"
29
#include "obstack.h"
30
31
#define obstack_chunk_alloc xmalloc
32
#define obstack_chunk_free free
33
34
35.1M
#define INSNLEN 4
35
36
/* This character is used to encode style information within the output
37
   buffers.  See get_style_text and print_operands for more details.  */
38
510M
#define STYLE_MARKER_CHAR '\002'
39
40
/* Cached mapping symbol state.  */
41
enum map_type
42
{
43
  MAP_INSN,
44
  MAP_DATA
45
};
46
47
static aarch64_feature_set arch_variant; /* See select_aarch64_variant.  */
48
static enum map_type last_type;
49
static int last_mapping_sym = -1;
50
static bfd_vma last_stop_offset = 0;
51
static bfd_vma last_mapping_addr = 0;
52
53
/* Other options */
54
static int no_aliases = 0;  /* If set disassemble as most general inst.  */
55
static int no_notes = 1; /* If set do not print disassemble notes in the
56
          output as comments.  */
57
58
/* Currently active instruction sequence.  */
59
static aarch64_instr_sequence insn_sequence;
60
61
static void
62
set_default_aarch64_dis_options (struct disassemble_info *info ATTRIBUTE_UNUSED)
63
0
{
64
0
}
65
66
static void
67
parse_aarch64_dis_option (const char *option, unsigned int len ATTRIBUTE_UNUSED)
68
0
{
69
  /* Try to match options that are simple flags */
70
0
  if (startswith (option, "no-aliases"))
71
0
    {
72
0
      no_aliases = 1;
73
0
      return;
74
0
    }
75
76
0
  if (startswith (option, "aliases"))
77
0
    {
78
0
      no_aliases = 0;
79
0
      return;
80
0
    }
81
82
0
  if (startswith (option, "no-notes"))
83
0
    {
84
0
      no_notes = 1;
85
0
      return;
86
0
    }
87
88
0
  if (startswith (option, "notes"))
89
0
    {
90
0
      no_notes = 0;
91
0
      return;
92
0
    }
93
94
#ifdef DEBUG_AARCH64
95
  if (startswith (option, "debug_dump"))
96
    {
97
      debug_dump = 1;
98
      return;
99
    }
100
#endif /* DEBUG_AARCH64 */
101
102
  /* Invalid option.  */
103
0
  opcodes_error_handler (_("unrecognised disassembler option: %s"), option);
104
0
}
105
106
static void
107
parse_aarch64_dis_options (const char *options)
108
0
{
109
0
  const char *option_end;
110
111
0
  if (options == NULL)
112
0
    return;
113
114
0
  while (*options != '\0')
115
0
    {
116
      /* Skip empty options.  */
117
0
      if (*options == ',')
118
0
  {
119
0
    options++;
120
0
    continue;
121
0
  }
122
123
      /* We know that *options is neither NUL or a comma.  */
124
0
      option_end = options + 1;
125
0
      while (*option_end != ',' && *option_end != '\0')
126
0
  option_end++;
127
128
0
      parse_aarch64_dis_option (options, option_end - options);
129
130
      /* Go on to the next one.  If option_end points to a comma, it
131
   will be skipped above.  */
132
0
      options = option_end;
133
0
    }
134
0
}
135

136
/* Functions doing the instruction disassembling.  */
137
138
/* The unnamed arguments consist of the number of fields and information about
139
   these fields where the VALUE will be extracted from CODE and returned.
140
   MASK can be zero or the base mask of the opcode.
141
142
   N.B. the fields are required to be in such an order than the most signficant
143
   field for VALUE comes the first, e.g. the <index> in
144
    SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>]
145
   is encoded in H:L:M in some cases, the fields H:L:M should be passed in
146
   the order of H, L, M.  */
147
148
aarch64_insn
149
extract_fields (aarch64_insn code, aarch64_insn mask, ...)
150
3.28M
{
151
3.28M
  uint32_t num;
152
3.28M
  const aarch64_field *field;
153
3.28M
  enum aarch64_field_kind kind;
154
3.28M
  va_list va;
155
156
3.28M
  va_start (va, mask);
157
3.28M
  num = va_arg (va, uint32_t);
158
3.28M
  assert (num <= 5);
159
3.28M
  aarch64_insn value = 0x0;
160
10.8M
  while (num--)
161
7.53M
    {
162
7.53M
      kind = va_arg (va, enum aarch64_field_kind);
163
7.53M
      field = &fields[kind];
164
7.53M
      value <<= field->width;
165
7.53M
      value |= extract_field (kind, code, mask);
166
7.53M
    }
167
3.28M
  va_end (va);
168
3.28M
  return value;
169
3.28M
}
170
171
/* Extract the value of all fields in SELF->fields after START from
172
   instruction CODE.  The least significant bit comes from the final field.  */
173
174
static aarch64_insn
175
extract_all_fields_after (const aarch64_operand *self, unsigned int start,
176
        aarch64_insn code)
177
9.32M
{
178
9.32M
  aarch64_insn value;
179
9.32M
  unsigned int i;
180
9.32M
  enum aarch64_field_kind kind;
181
182
9.32M
  value = 0;
183
9.32M
  for (i = start;
184
20.1M
       i < ARRAY_SIZE (self->fields) && self->fields[i] != FLD_NIL; ++i)
185
10.8M
    {
186
10.8M
      kind = self->fields[i];
187
10.8M
      value <<= fields[kind].width;
188
10.8M
      value |= extract_field (kind, code, 0);
189
10.8M
    }
190
9.32M
  return value;
191
9.32M
}
192
193
/* Extract the value of all fields in SELF->fields from instruction CODE.
194
   The least significant bit comes from the final field.  */
195
196
static aarch64_insn
197
extract_all_fields (const aarch64_operand *self, aarch64_insn code)
198
9.24M
{
199
9.24M
  return extract_all_fields_after (self, 0, code);
200
9.24M
}
201
202
/* Sign-extend bit I of VALUE.  */
203
static inline uint64_t
204
sign_extend (aarch64_insn value, unsigned i)
205
4.74M
{
206
4.74M
  uint64_t ret, sign;
207
208
4.74M
  assert (i < 32);
209
4.74M
  ret = value;
210
4.74M
  sign = (uint64_t) 1 << i;
211
4.74M
  return ((ret & (sign + sign - 1)) ^ sign) - sign;
212
4.74M
}
213
214
/* N.B. the following inline helpfer functions create a dependency on the
215
   order of operand qualifier enumerators.  */
216
217
/* Given VALUE, return qualifier for a general purpose register.  */
218
static inline enum aarch64_opnd_qualifier
219
get_greg_qualifier_from_value (aarch64_insn value)
220
6.77M
{
221
6.77M
  enum aarch64_opnd_qualifier qualifier = AARCH64_OPND_QLF_W + value;
222
6.77M
  if (value <= 0x1
223
6.77M
      && aarch64_get_qualifier_standard_value (qualifier) == value)
224
6.77M
    return qualifier;
225
0
  return AARCH64_OPND_QLF_ERR;
226
6.77M
}
227
228
/* Given VALUE, return qualifier for a vector register.  This does not support
229
   decoding instructions that accept the 2H vector type.  */
230
231
static inline enum aarch64_opnd_qualifier
232
get_vreg_qualifier_from_value (aarch64_insn value)
233
525k
{
234
525k
  enum aarch64_opnd_qualifier qualifier = AARCH64_OPND_QLF_V_8B + value;
235
236
  /* Instructions using vector type 2H should not call this function.  Skip over
237
     the 2H qualifier.  */
238
525k
  if (qualifier >= AARCH64_OPND_QLF_V_2H)
239
350k
    qualifier += 1;
240
241
525k
  if (value <= 0x8
242
525k
      && aarch64_get_qualifier_standard_value (qualifier) == value)
243
525k
    return qualifier;
244
0
  return AARCH64_OPND_QLF_ERR;
245
525k
}
246
247
/* Given VALUE, return qualifier for an FP or AdvSIMD scalar register.  */
248
static inline enum aarch64_opnd_qualifier
249
get_sreg_qualifier_from_value (aarch64_insn value)
250
349k
{
251
349k
  enum aarch64_opnd_qualifier qualifier = AARCH64_OPND_QLF_S_B + value;
252
253
349k
  if (value <= 0x4
254
349k
      && aarch64_get_qualifier_standard_value (qualifier) == value)
255
344k
    return qualifier;
256
5.78k
  return AARCH64_OPND_QLF_ERR;
257
349k
}
258
259
/* Given the instruction in *INST which is probably half way through the
260
   decoding and our caller wants to know the expected qualifier for operand
261
   I.  Return such a qualifier if we can establish it; otherwise return
262
   AARCH64_OPND_QLF_NIL.  */
263
264
static aarch64_opnd_qualifier_t
265
get_expected_qualifier (const aarch64_inst *inst, int i)
266
2.55M
{
267
2.55M
  aarch64_opnd_qualifier_seq_t qualifiers;
268
  /* Should not be called if the qualifier is known.  */
269
2.55M
  if (inst->operands[i].qualifier == AARCH64_OPND_QLF_NIL)
270
2.55M
    {
271
2.55M
      int invalid_count;
272
2.55M
      if (aarch64_find_best_match (inst, inst->opcode->qualifiers_list,
273
2.55M
           i, qualifiers, &invalid_count))
274
2.49M
  return qualifiers[i];
275
60.4k
      else
276
60.4k
  return AARCH64_OPND_QLF_NIL;
277
2.55M
    }
278
0
  else
279
0
    return AARCH64_OPND_QLF_ERR;
280
2.55M
}
281
282
/* Operand extractors.  */
283
284
bool
285
aarch64_ext_none (const aarch64_operand *self ATTRIBUTE_UNUSED,
286
      aarch64_opnd_info *info ATTRIBUTE_UNUSED,
287
      const aarch64_insn code ATTRIBUTE_UNUSED,
288
      const aarch64_inst *inst ATTRIBUTE_UNUSED,
289
      aarch64_operand_error *errors ATTRIBUTE_UNUSED)
290
1.55k
{
291
1.55k
  return true;
292
1.55k
}
293
294
bool
295
aarch64_ext_regno (const aarch64_operand *self, aarch64_opnd_info *info,
296
       const aarch64_insn code,
297
       const aarch64_inst *inst ATTRIBUTE_UNUSED,
298
       aarch64_operand_error *errors ATTRIBUTE_UNUSED)
299
22.0M
{
300
22.0M
  info->reg.regno = (extract_field (self->fields[0], code, 0)
301
22.0M
         + get_operand_specific_data (self));
302
22.0M
  return true;
303
22.0M
}
304
305
bool
306
aarch64_ext_regno_pair (const aarch64_operand *self ATTRIBUTE_UNUSED, aarch64_opnd_info *info,
307
       const aarch64_insn code ATTRIBUTE_UNUSED,
308
       const aarch64_inst *inst ATTRIBUTE_UNUSED,
309
       aarch64_operand_error *errors ATTRIBUTE_UNUSED)
310
39.0k
{
311
39.0k
  assert (info->idx == 1
312
39.0k
    || info->idx == 2
313
39.0k
    || info->idx == 3
314
39.0k
    || info->idx == 5);
315
316
39.0k
  unsigned prev_regno = inst->operands[info->idx - 1].reg.regno;
317
39.0k
  info->reg.regno = (prev_regno == 0x1f) ? 0x1f
318
39.0k
           : prev_regno + 1;
319
39.0k
  return true;
320
39.0k
}
321
322
/* e.g. IC <ic_op>{, <Xt>}.  */
323
bool
324
aarch64_ext_regrt_sysins (const aarch64_operand *self, aarch64_opnd_info *info,
325
        const aarch64_insn code,
326
        const aarch64_inst *inst ATTRIBUTE_UNUSED,
327
        aarch64_operand_error *errors ATTRIBUTE_UNUSED)
328
178
{
329
178
  info->reg.regno = extract_field (self->fields[0], code, 0);
330
178
  assert (info->idx == 1
331
178
    && (aarch64_get_operand_class (inst->operands[0].type)
332
178
        == AARCH64_OPND_CLASS_SYSTEM));
333
  /* This will make the constraint checking happy and more importantly will
334
     help the disassembler determine whether this operand is optional or
335
     not.  */
336
178
  info->present = aarch64_sys_ins_reg_has_xt (inst->operands[0].sysins_op);
337
338
178
  return true;
339
178
}
340
341
/* e.g. SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>].  */
342
bool
343
aarch64_ext_reglane (const aarch64_operand *self, aarch64_opnd_info *info,
344
         const aarch64_insn code,
345
         const aarch64_inst *inst ATTRIBUTE_UNUSED,
346
         aarch64_operand_error *errors ATTRIBUTE_UNUSED)
347
238k
{
348
  /* regno */
349
238k
  info->reglane.regno = extract_field (self->fields[0], code,
350
238k
               inst->opcode->mask);
351
352
  /* Index and/or type.  */
353
238k
  if (inst->opcode->iclass == asisdone
354
238k
    || inst->opcode->iclass == asimdins)
355
15.5k
    {
356
15.5k
      if (info->type == AARCH64_OPND_En
357
15.5k
    && inst->opcode->operands[0] == AARCH64_OPND_Ed)
358
4.17k
  {
359
4.17k
    unsigned shift;
360
    /* index2 for e.g. INS <Vd>.<Ts>[<index1>], <Vn>.<Ts>[<index2>].  */
361
4.17k
    assert (info->idx == 1);  /* Vn */
362
4.17k
    aarch64_insn value = extract_field (FLD_imm4_11, code, 0);
363
    /* Depend on AARCH64_OPND_Ed to determine the qualifier.  */
364
4.17k
    info->qualifier = get_expected_qualifier (inst, info->idx);
365
4.17k
    if (info->qualifier == AARCH64_OPND_QLF_ERR)
366
0
      return 0;
367
4.17k
    shift = get_logsz (aarch64_get_qualifier_esize (info->qualifier));
368
4.17k
    info->reglane.index = value >> shift;
369
4.17k
  }
370
11.3k
      else
371
11.3k
  {
372
    /* index and type for e.g. DUP <V><d>, <Vn>.<T>[<index>].
373
       imm5<3:0>  <V>
374
       0000 RESERVED
375
       xxx1 B
376
       xx10 H
377
       x100 S
378
       1000 D  */
379
11.3k
    int pos = -1;
380
11.3k
    aarch64_insn value = extract_field (FLD_imm5, code, 0);
381
24.7k
    while (++pos <= 3 && (value & 0x1) == 0)
382
13.3k
      value >>= 1;
383
11.3k
    if (pos > 3)
384
1.11k
      return false;
385
10.2k
    info->qualifier = get_sreg_qualifier_from_value (pos);
386
10.2k
    if (info->qualifier == AARCH64_OPND_QLF_ERR)
387
0
      return 0;
388
10.2k
    info->reglane.index = (unsigned) (value >> 1);
389
10.2k
  }
390
15.5k
    }
391
223k
  else if (inst->opcode->iclass == dotproduct)
392
61.4k
    {
393
      /* Need information in other operand(s) to help decoding.  */
394
61.4k
      info->qualifier = get_expected_qualifier (inst, info->idx);
395
61.4k
      if (info->qualifier == AARCH64_OPND_QLF_ERR)
396
0
  return 0;
397
61.4k
      switch (info->qualifier)
398
61.4k
  {
399
31.2k
  case AARCH64_OPND_QLF_S_4B:
400
32.8k
  case AARCH64_OPND_QLF_S_2H:
401
    /* L:H */
402
32.8k
    info->reglane.index = extract_fields (code, 0, 2, FLD_H, FLD_L);
403
32.8k
    info->reglane.regno &= 0x1f;
404
32.8k
    break;
405
13.2k
  case AARCH64_OPND_QLF_S_2B:
406
    /* h:l:m */
407
13.2k
    info->reglane.index = extract_fields (code, 0, 3, FLD_H, FLD_L,
408
13.2k
            FLD_M);
409
13.2k
    info->reglane.regno &= 0xf;
410
13.2k
    break;
411
15.3k
  default:
412
15.3k
    return false;
413
61.4k
  }
414
61.4k
    }
415
161k
  else if (inst->opcode->iclass == cryptosm3)
416
1.50k
    {
417
      /* index for e.g. SM3TT2A <Vd>.4S, <Vn>.4S, <Vm>S[<imm2>].  */
418
1.50k
      info->reglane.index = extract_field (FLD_SM3_imm2, code, 0);
419
1.50k
    }
420
160k
  else
421
160k
    {
422
      /* Index only for e.g. SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>]
423
         or SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>].  */
424
425
      /* Need information in other operand(s) to help decoding.  */
426
160k
      info->qualifier = get_expected_qualifier (inst, info->idx);
427
160k
      if (info->qualifier == AARCH64_OPND_QLF_ERR)
428
0
  return 0;
429
160k
      switch (info->qualifier)
430
160k
  {
431
5.81k
  case AARCH64_OPND_QLF_S_B:
432
    /* H:imm3 */
433
5.81k
    info->reglane.index = extract_fields (code, 0, 2, FLD_H,
434
5.81k
            FLD_imm3_19);
435
5.81k
    info->reglane.regno &= 0x7;
436
5.81k
    break;
437
438
86.4k
  case AARCH64_OPND_QLF_S_H:
439
86.4k
  case AARCH64_OPND_QLF_S_2B:
440
86.4k
    if (info->type == AARCH64_OPND_Em16)
441
71.9k
      {
442
        /* h:l:m */
443
71.9k
        info->reglane.index = extract_fields (code, 0, 3, FLD_H, FLD_L,
444
71.9k
                FLD_M);
445
71.9k
        info->reglane.regno &= 0xf;
446
71.9k
      }
447
14.4k
    else
448
14.4k
      {
449
        /* h:l */
450
14.4k
        info->reglane.index = extract_fields (code, 0, 2, FLD_H, FLD_L);
451
14.4k
      }
452
86.4k
    break;
453
21.1k
  case AARCH64_OPND_QLF_S_S:
454
21.1k
  case AARCH64_OPND_QLF_S_4B:
455
    /* h:l */
456
21.1k
    info->reglane.index = extract_fields (code, 0, 2, FLD_H, FLD_L);
457
21.1k
    break;
458
1.93k
  case AARCH64_OPND_QLF_S_D:
459
    /* H */
460
1.93k
    info->reglane.index = extract_field (FLD_H, code, 0);
461
1.93k
    break;
462
45.1k
  default:
463
45.1k
    return false;
464
160k
  }
465
466
115k
      if (inst->opcode->op == OP_FCMLA_ELEM
467
115k
    && info->qualifier != AARCH64_OPND_QLF_S_H)
468
1.63k
  {
469
    /* Complex operand takes two elements.  */
470
1.63k
    if (info->reglane.index & 1)
471
837
      return false;
472
798
    info->reglane.index /= 2;
473
798
  }
474
115k
    }
475
476
176k
  return true;
477
238k
}
478
479
bool
480
aarch64_ext_reglist (const aarch64_operand *self, aarch64_opnd_info *info,
481
         const aarch64_insn code,
482
         const aarch64_inst *inst ATTRIBUTE_UNUSED,
483
         aarch64_operand_error *errors ATTRIBUTE_UNUSED)
484
17.3k
{
485
  /* R */
486
17.3k
  info->reglist.first_regno = extract_field (self->fields[0], code, 0);
487
  /* len */
488
17.3k
  info->reglist.num_regs = extract_field (FLD_len, code, 0) + 1;
489
17.3k
  info->reglist.stride = 1;
490
17.3k
  return true;
491
17.3k
}
492
493
/* Decode Rt and opcode fields of Vt in AdvSIMD load/store instructions.  */
494
bool
495
aarch64_ext_ldst_reglist (const aarch64_operand *self ATTRIBUTE_UNUSED,
496
        aarch64_opnd_info *info, const aarch64_insn code,
497
        const aarch64_inst *inst,
498
        aarch64_operand_error *errors ATTRIBUTE_UNUSED)
499
223k
{
500
223k
  aarch64_insn value;
501
  /* Number of elements in each structure to be loaded/stored.  */
502
223k
  unsigned expected_num = get_opcode_dependent_value (inst->opcode);
503
504
223k
  struct
505
223k
    {
506
223k
      unsigned is_reserved;
507
223k
      unsigned num_regs;
508
223k
      unsigned num_elements;
509
223k
    } data [] =
510
223k
  {   {0, 4, 4},
511
223k
      {1, 4, 4},
512
223k
      {0, 4, 1},
513
223k
      {0, 4, 2},
514
223k
      {0, 3, 3},
515
223k
      {1, 3, 3},
516
223k
      {0, 3, 1},
517
223k
      {0, 1, 1},
518
223k
      {0, 2, 2},
519
223k
      {1, 2, 2},
520
223k
      {0, 2, 1},
521
223k
  };
522
523
  /* Rt */
524
223k
  info->reglist.first_regno = extract_field (FLD_Rt, code, 0);
525
  /* opcode */
526
223k
  value = extract_field (FLD_opcode, code, 0);
527
  /* PR 21595: Check for a bogus value.  */
528
223k
  if (value >= ARRAY_SIZE (data))
529
36.2k
    return false;
530
187k
  if (expected_num != data[value].num_elements || data[value].is_reserved)
531
81.1k
    return false;
532
105k
  info->reglist.num_regs = data[value].num_regs;
533
105k
  info->reglist.stride = 1;
534
535
105k
  return true;
536
187k
}
537
538
/* Decode Rt and S fields of Vt in AdvSIMD load single structure to all
539
   lanes instructions.  */
540
bool
541
aarch64_ext_ldst_reglist_r (const aarch64_operand *self ATTRIBUTE_UNUSED,
542
          aarch64_opnd_info *info, const aarch64_insn code,
543
          const aarch64_inst *inst,
544
          aarch64_operand_error *errors ATTRIBUTE_UNUSED)
545
3.20k
{
546
3.20k
  aarch64_insn value;
547
548
  /* Rt */
549
3.20k
  info->reglist.first_regno = extract_field (FLD_Rt, code, 0);
550
  /* S */
551
3.20k
  value = extract_field (FLD_S, code, 0);
552
553
  /* Number of registers is equal to the number of elements in
554
     each structure to be loaded/stored.  */
555
3.20k
  info->reglist.num_regs = get_opcode_dependent_value (inst->opcode);
556
3.20k
  assert (info->reglist.num_regs >= 1 && info->reglist.num_regs <= 4);
557
558
  /* Except when it is LD1R.  */
559
3.20k
  if (info->reglist.num_regs == 1 && value == (aarch64_insn) 1)
560
0
    info->reglist.num_regs = 2;
561
562
3.20k
  info->reglist.stride = 1;
563
3.20k
  return true;
564
3.20k
}
565
566
/* Decode AdvSIMD vector register list for AdvSIMD lut instructions.
567
   The number of of registers in the list is determined by the opcode
568
   flag.  */
569
bool
570
aarch64_ext_lut_reglist (const aarch64_operand *self, aarch64_opnd_info *info,
571
         const aarch64_insn code,
572
         const aarch64_inst *inst ATTRIBUTE_UNUSED,
573
         aarch64_operand_error *errors ATTRIBUTE_UNUSED)
574
3.17k
{
575
3.17k
  info->reglist.first_regno = extract_field (self->fields[0], code, 0);
576
3.17k
  info->reglist.num_regs = get_opcode_dependent_value (inst->opcode);
577
3.17k
  info->reglist.stride = 1;
578
3.17k
  return true;
579
3.17k
}
580
581
/* Decode Q, opcode<2:1>, S, size and Rt fields of Vt in AdvSIMD
582
   load/store single element instructions.  */
583
bool
584
aarch64_ext_ldst_elemlist (const aarch64_operand *self ATTRIBUTE_UNUSED,
585
         aarch64_opnd_info *info, const aarch64_insn code,
586
         const aarch64_inst *inst ATTRIBUTE_UNUSED,
587
         aarch64_operand_error *errors ATTRIBUTE_UNUSED)
588
89.5k
{
589
89.5k
  aarch64_field field = {0, 0};
590
89.5k
  aarch64_insn QSsize;    /* fields Q:S:size.  */
591
89.5k
  aarch64_insn opcodeh2;  /* opcode<2:1> */
592
593
  /* Rt */
594
89.5k
  info->reglist.first_regno = extract_field (FLD_Rt, code, 0);
595
596
  /* Decode the index, opcode<2:1> and size.  */
597
89.5k
  gen_sub_field (FLD_asisdlso_opcode, 1, 2, &field);
598
89.5k
  opcodeh2 = extract_field_2 (&field, code, 0);
599
89.5k
  QSsize = extract_fields (code, 0, 3, FLD_Q, FLD_S, FLD_vldst_size);
600
89.5k
  switch (opcodeh2)
601
89.5k
    {
602
43.5k
    case 0x0:
603
43.5k
      info->qualifier = AARCH64_OPND_QLF_S_B;
604
      /* Index encoded in "Q:S:size".  */
605
43.5k
      info->reglist.index = QSsize;
606
43.5k
      break;
607
21.9k
    case 0x1:
608
21.9k
      if (QSsize & 0x1)
609
  /* UND.  */
610
8.50k
  return false;
611
13.4k
      info->qualifier = AARCH64_OPND_QLF_S_H;
612
      /* Index encoded in "Q:S:size<1>".  */
613
13.4k
      info->reglist.index = QSsize >> 1;
614
13.4k
      break;
615
12.7k
    case 0x2:
616
12.7k
      if ((QSsize >> 1) & 0x1)
617
  /* UND.  */
618
6.99k
  return false;
619
5.77k
      if ((QSsize & 0x1) == 0)
620
2.84k
  {
621
2.84k
    info->qualifier = AARCH64_OPND_QLF_S_S;
622
    /* Index encoded in "Q:S".  */
623
2.84k
    info->reglist.index = QSsize >> 2;
624
2.84k
  }
625
2.92k
      else
626
2.92k
  {
627
2.92k
    if (extract_field (FLD_S, code, 0))
628
      /* UND */
629
1.07k
      return false;
630
1.85k
    info->qualifier = AARCH64_OPND_QLF_S_D;
631
    /* Index encoded in "Q".  */
632
1.85k
    info->reglist.index = QSsize >> 3;
633
1.85k
  }
634
4.69k
      break;
635
11.2k
    default:
636
11.2k
      return false;
637
89.5k
    }
638
639
61.7k
  info->reglist.has_index = 1;
640
61.7k
  info->reglist.num_regs = 0;
641
61.7k
  info->reglist.stride = 1;
642
  /* Number of registers is equal to the number of elements in
643
     each structure to be loaded/stored.  */
644
61.7k
  info->reglist.num_regs = get_opcode_dependent_value (inst->opcode);
645
61.7k
  assert (info->reglist.num_regs >= 1 && info->reglist.num_regs <= 4);
646
647
61.7k
  return true;
648
61.7k
}
649
650
/* Decode fields immh:immb and/or Q for e.g.
651
   SSHR <Vd>.<T>, <Vn>.<T>, #<shift>
652
   or SSHR <V><d>, <V><n>, #<shift>.  */
653
654
bool
655
aarch64_ext_advsimd_imm_shift (const aarch64_operand *self ATTRIBUTE_UNUSED,
656
             aarch64_opnd_info *info, const aarch64_insn code,
657
             const aarch64_inst *inst,
658
             aarch64_operand_error *errors ATTRIBUTE_UNUSED)
659
73.5k
{
660
73.5k
  int pos;
661
73.5k
  aarch64_insn Q, imm, immh;
662
73.5k
  enum aarch64_insn_class iclass = inst->opcode->iclass;
663
664
73.5k
  immh = extract_field (FLD_immh, code, 0);
665
73.5k
  if (immh == 0)
666
4.47k
    return false;
667
69.1k
  imm = extract_fields (code, 0, 2, FLD_immh, FLD_immb);
668
69.1k
  pos = 4;
669
  /* Get highest set bit in immh.  */
670
112k
  while (--pos >= 0 && (immh & 0x8) == 0)
671
42.9k
    immh <<= 1;
672
673
69.1k
  assert ((iclass == asimdshf || iclass == asisdshf)
674
69.1k
    && (info->type == AARCH64_OPND_IMM_VLSR
675
69.1k
        || info->type == AARCH64_OPND_IMM_VLSL));
676
677
69.1k
  if (iclass == asimdshf)
678
53.2k
    {
679
53.2k
      Q = extract_field (FLD_Q, code, 0);
680
      /* immh Q <T>
681
   0000 x SEE AdvSIMD modified immediate
682
   0001 0 8B
683
   0001 1 16B
684
   001x 0 4H
685
   001x 1 8H
686
   01xx 0 2S
687
   01xx 1 4S
688
   1xxx 0 RESERVED
689
   1xxx 1 2D  */
690
53.2k
      info->qualifier =
691
53.2k
  get_vreg_qualifier_from_value ((pos << 1) | (int) Q);
692
53.2k
      if (info->qualifier == AARCH64_OPND_QLF_ERR)
693
0
  return false;
694
53.2k
    }
695
15.9k
  else
696
15.9k
    {
697
15.9k
      info->qualifier = get_sreg_qualifier_from_value (pos);
698
15.9k
      if (info->qualifier == AARCH64_OPND_QLF_ERR)
699
0
  return 0;
700
15.9k
    }
701
702
69.1k
  if (info->type == AARCH64_OPND_IMM_VLSR)
703
    /* immh <shift>
704
       0000 SEE AdvSIMD modified immediate
705
       0001 (16-UInt(immh:immb))
706
       001x (32-UInt(immh:immb))
707
       01xx (64-UInt(immh:immb))
708
       1xxx (128-UInt(immh:immb))  */
709
38.1k
    info->imm.value = (16 << pos) - imm;
710
30.9k
  else
711
    /* immh:immb
712
       immh <shift>
713
       0000 SEE AdvSIMD modified immediate
714
       0001 (UInt(immh:immb)-8)
715
       001x (UInt(immh:immb)-16)
716
       01xx (UInt(immh:immb)-32)
717
       1xxx (UInt(immh:immb)-64)  */
718
30.9k
    info->imm.value = imm - (8 << pos);
719
720
69.1k
  return true;
721
69.1k
}
722
723
/* Decode shift immediate for e.g. sshr (imm).  */
724
bool
725
aarch64_ext_shll_imm (const aarch64_operand *self ATTRIBUTE_UNUSED,
726
          aarch64_opnd_info *info, const aarch64_insn code,
727
          const aarch64_inst *inst ATTRIBUTE_UNUSED,
728
          aarch64_operand_error *errors ATTRIBUTE_UNUSED)
729
95
{
730
95
  int64_t imm;
731
95
  aarch64_insn val;
732
95
  val = extract_field (FLD_size, code, 0);
733
95
  switch (val)
734
95
    {
735
1
    case 0: imm = 8; break;
736
87
    case 1: imm = 16; break;
737
7
    case 2: imm = 32; break;
738
0
    default: return false;
739
95
    }
740
95
  info->imm.value = imm;
741
95
  return true;
742
95
}
743
744
/* Decode imm for e.g. BFM <Wd>, <Wn>, #<immr>, #<imms>.
745
   value in the field(s) will be extracted as unsigned immediate value.  */
746
bool
747
aarch64_ext_imm (const aarch64_operand *self, aarch64_opnd_info *info,
748
     const aarch64_insn code,
749
     const aarch64_inst *inst,
750
     aarch64_operand_error *errors ATTRIBUTE_UNUSED)
751
9.20M
{
752
9.20M
  uint64_t imm;
753
754
9.20M
  imm = extract_all_fields (self, code);
755
756
9.20M
  if (operand_need_sign_extension (self))
757
3.38M
    imm = sign_extend (imm, get_operand_fields_width (self) - 1);
758
759
9.20M
  if (operand_need_shift_by_two (self))
760
2.31M
    imm <<= 2;
761
6.88M
  else if (operand_need_shift_by_three (self))
762
25
    imm <<= 3;
763
6.88M
  else if (operand_need_shift_by_four (self))
764
8.48k
    imm <<= 4;
765
766
9.20M
  if (info->type == AARCH64_OPND_ADDR_ADRP)
767
410k
    imm <<= 12;
768
769
9.20M
  if (inst->operands[0].type == AARCH64_OPND_PSTATEFIELD
770
9.20M
      && inst->operands[0].sysreg.flags & F_IMM_IN_CRM)
771
0
    imm &= PSTATE_DECODE_CRM_IMM (inst->operands[0].sysreg.flags);
772
773
9.20M
  info->imm.value = imm;
774
9.20M
  return true;
775
9.20M
}
776
777
/* Decode imm and its shifter for e.g. MOVZ <Wd>, #<imm16>{, LSL #<shift>}.  */
778
bool
779
aarch64_ext_imm_half (const aarch64_operand *self, aarch64_opnd_info *info,
780
          const aarch64_insn code,
781
          const aarch64_inst *inst ATTRIBUTE_UNUSED,
782
          aarch64_operand_error *errors)
783
335k
{
784
335k
  aarch64_ext_imm (self, info, code, inst, errors);
785
335k
  info->shifter.kind = AARCH64_MOD_LSL;
786
335k
  info->shifter.amount = extract_field (FLD_hw, code, 0) << 4;
787
335k
  return true;
788
335k
}
789
790
/* Decode cmode and "a:b:c:d:e:f:g:h" for e.g.
791
     MOVI <Vd>.<T>, #<imm8> {, LSL #<amount>}.  */
792
bool
793
aarch64_ext_advsimd_imm_modified (const aarch64_operand *self ATTRIBUTE_UNUSED,
794
          aarch64_opnd_info *info,
795
          const aarch64_insn code,
796
          const aarch64_inst *inst ATTRIBUTE_UNUSED,
797
          aarch64_operand_error *errors ATTRIBUTE_UNUSED)
798
10.1k
{
799
10.1k
  uint64_t imm;
800
10.1k
  enum aarch64_opnd_qualifier opnd0_qualifier = inst->operands[0].qualifier;
801
10.1k
  aarch64_field field = {0, 0};
802
803
10.1k
  assert (info->idx == 1);
804
805
10.1k
  if (info->type == AARCH64_OPND_SIMD_FPIMM)
806
4.46k
    info->imm.is_fp = 1;
807
808
  /* a:b:c:d:e:f:g:h */
809
10.1k
  imm = extract_fields (code, 0, 2, FLD_abc, FLD_defgh);
810
10.1k
  if (!info->imm.is_fp && aarch64_get_qualifier_esize (opnd0_qualifier) == 8)
811
1.03k
    {
812
      /* Either MOVI <Dd>, #<imm>
813
   or     MOVI <Vd>.2D, #<imm>.
814
   <imm> is a 64-bit immediate
815
   'aaaaaaaabbbbbbbbccccccccddddddddeeeeeeeeffffffffgggggggghhhhhhhh',
816
   encoded in "a:b:c:d:e:f:g:h".  */
817
1.03k
      int i;
818
1.03k
      unsigned abcdefgh = imm;
819
9.35k
      for (imm = 0ull, i = 0; i < 8; i++)
820
8.31k
  if (((abcdefgh >> i) & 0x1) != 0)
821
5.52k
    imm |= 0xffull << (8 * i);
822
1.03k
    }
823
10.1k
  info->imm.value = imm;
824
825
  /* cmode */
826
10.1k
  info->qualifier = get_expected_qualifier (inst, info->idx);
827
10.1k
  if (info->qualifier == AARCH64_OPND_QLF_ERR)
828
0
    return 0;
829
10.1k
  switch (info->qualifier)
830
10.1k
    {
831
5.50k
    case AARCH64_OPND_QLF_NIL:
832
      /* no shift */
833
5.50k
      info->shifter.kind = AARCH64_MOD_NONE;
834
5.50k
      return 1;
835
4.37k
    case AARCH64_OPND_QLF_LSL:
836
      /* shift zeros */
837
4.37k
      info->shifter.kind = AARCH64_MOD_LSL;
838
4.37k
      switch (aarch64_get_qualifier_esize (opnd0_qualifier))
839
4.37k
  {
840
3.69k
  case 4: gen_sub_field (FLD_cmode, 1, 2, &field); break; /* per word */
841
482
  case 2: gen_sub_field (FLD_cmode, 1, 1, &field); break; /* per half */
842
195
  case 1: gen_sub_field (FLD_cmode, 1, 0, &field); break; /* per byte */
843
0
  default: return false;
844
4.37k
  }
845
      /* 00: 0; 01: 8; 10:16; 11:24.  */
846
4.37k
      info->shifter.amount = extract_field_2 (&field, code, 0) << 3;
847
4.37k
      break;
848
298
    case AARCH64_OPND_QLF_MSL:
849
      /* shift ones */
850
298
      info->shifter.kind = AARCH64_MOD_MSL;
851
298
      gen_sub_field (FLD_cmode, 0, 1, &field);    /* per word */
852
298
      info->shifter.amount = extract_field_2 (&field, code, 0) ? 16 : 8;
853
298
      break;
854
0
    default:
855
0
      return false;
856
10.1k
    }
857
858
4.67k
  return true;
859
10.1k
}
860
861
/* Decode an 8-bit floating-point immediate.  */
862
bool
863
aarch64_ext_fpimm (const aarch64_operand *self, aarch64_opnd_info *info,
864
       const aarch64_insn code,
865
       const aarch64_inst *inst ATTRIBUTE_UNUSED,
866
       aarch64_operand_error *errors ATTRIBUTE_UNUSED)
867
2.20k
{
868
2.20k
  info->imm.value = extract_all_fields (self, code);
869
2.20k
  info->imm.is_fp = 1;
870
2.20k
  return true;
871
2.20k
}
872
873
/* Decode a 1-bit rotate immediate (#90 or #270).  */
874
bool
875
aarch64_ext_imm_rotate1 (const aarch64_operand *self, aarch64_opnd_info *info,
876
       const aarch64_insn code,
877
       const aarch64_inst *inst ATTRIBUTE_UNUSED,
878
       aarch64_operand_error *errors ATTRIBUTE_UNUSED)
879
1.95k
{
880
1.95k
  uint64_t rot = extract_field (self->fields[0], code, 0);
881
1.95k
  assert (rot < 2U);
882
1.95k
  info->imm.value = rot * 180 + 90;
883
1.95k
  return true;
884
1.95k
}
885
886
/* Decode a 2-bit rotate immediate (#0, #90, #180 or #270).  */
887
bool
888
aarch64_ext_imm_rotate2 (const aarch64_operand *self, aarch64_opnd_info *info,
889
       const aarch64_insn code,
890
       const aarch64_inst *inst ATTRIBUTE_UNUSED,
891
       aarch64_operand_error *errors ATTRIBUTE_UNUSED)
892
43.5k
{
893
43.5k
  uint64_t rot = extract_field (self->fields[0], code, 0);
894
43.5k
  assert (rot < 4U);
895
43.5k
  info->imm.value = rot * 90;
896
43.5k
  return true;
897
43.5k
}
898
899
/* Decode scale for e.g. SCVTF <Dd>, <Wn>, #<fbits>.  */
900
bool
901
aarch64_ext_fbits (const aarch64_operand *self ATTRIBUTE_UNUSED,
902
       aarch64_opnd_info *info, const aarch64_insn code,
903
       const aarch64_inst *inst ATTRIBUTE_UNUSED,
904
       aarch64_operand_error *errors ATTRIBUTE_UNUSED)
905
4.74k
{
906
4.74k
  info->imm.value = 64- extract_field (FLD_scale, code, 0);
907
4.74k
  return true;
908
4.74k
}
909
910
/* Decode arithmetic immediate for e.g.
911
     SUBS <Wd>, <Wn|WSP>, #<imm> {, <shift>}.  */
912
bool
913
aarch64_ext_aimm (const aarch64_operand *self ATTRIBUTE_UNUSED,
914
      aarch64_opnd_info *info, const aarch64_insn code,
915
      const aarch64_inst *inst ATTRIBUTE_UNUSED,
916
      aarch64_operand_error *errors ATTRIBUTE_UNUSED)
917
1.41M
{
918
1.41M
  aarch64_insn value;
919
920
1.41M
  info->shifter.kind = AARCH64_MOD_LSL;
921
  /* shift */
922
1.41M
  value = extract_field (FLD_shift, code, 0);
923
1.41M
  if (value >= 2)
924
229k
    return false;
925
1.18M
  info->shifter.amount = value ? 12 : 0;
926
  /* imm12 (unsigned) */
927
1.18M
  info->imm.value = extract_field (FLD_imm12, code, 0);
928
929
1.18M
  return true;
930
1.41M
}
931
932
/* Return true if VALUE is a valid logical immediate encoding, storing the
933
   decoded value in *RESULT if so.  ESIZE is the number of bytes in the
934
   decoded immediate.  */
935
static bool
936
decode_limm (uint32_t esize, aarch64_insn value, int64_t *result)
937
770k
{
938
770k
  uint64_t imm, mask;
939
770k
  uint32_t N, R, S;
940
770k
  unsigned simd_size;
941
942
  /* value is N:immr:imms.  */
943
770k
  S = value & 0x3f;
944
770k
  R = (value >> 6) & 0x3f;
945
770k
  N = (value >> 12) & 0x1;
946
947
  /* The immediate value is S+1 bits to 1, left rotated by SIMDsize - R
948
     (in other words, right rotated by R), then replicated.  */
949
770k
  if (N != 0)
950
246k
    {
951
246k
      simd_size = 64;
952
246k
      mask = 0xffffffffffffffffull;
953
246k
    }
954
523k
  else
955
523k
    {
956
523k
      switch (S)
957
523k
  {
958
404k
  case 0x00 ... 0x1f: /* 0xxxxx */ simd_size = 32;           break;
959
56.0k
  case 0x20 ... 0x2f: /* 10xxxx */ simd_size = 16; S &= 0xf; break;
960
26.5k
  case 0x30 ... 0x37: /* 110xxx */ simd_size =  8; S &= 0x7; break;
961
13.4k
  case 0x38 ... 0x3b: /* 1110xx */ simd_size =  4; S &= 0x3; break;
962
6.45k
  case 0x3c ... 0x3d: /* 11110x */ simd_size =  2; S &= 0x1; break;
963
16.7k
  default: return false;
964
523k
  }
965
506k
      mask = (1ull << simd_size) - 1;
966
      /* Top bits are IGNORED.  */
967
506k
      R &= simd_size - 1;
968
506k
    }
969
970
753k
  if (simd_size > esize * 8)
971
149k
    return false;
972
973
  /* NOTE: if S = simd_size - 1 we get 0xf..f which is rejected.  */
974
604k
  if (S == simd_size - 1)
975
14.5k
    return false;
976
  /* S+1 consecutive bits to 1.  */
977
  /* NOTE: S can't be 63 due to detection above.  */
978
590k
  imm = (1ull << (S + 1)) - 1;
979
  /* Rotate to the left by simd_size - R.  */
980
590k
  if (R != 0)
981
424k
    imm = ((imm << (simd_size - R)) & mask) | (imm >> R);
982
  /* Replicate the value according to SIMD size.  */
983
590k
  switch (simd_size)
984
590k
    {
985
4.49k
    case  2: imm = (imm <<  2) | imm;
986
      /* Fall through.  */
987
14.6k
    case  4: imm = (imm <<  4) | imm;
988
      /* Fall through.  */
989
38.7k
    case  8: imm = (imm <<  8) | imm;
990
      /* Fall through.  */
991
93.0k
    case 16: imm = (imm << 16) | imm;
992
      /* Fall through.  */
993
494k
    case 32: imm = (imm << 32) | imm;
994
      /* Fall through.  */
995
590k
    case 64: break;
996
0
    default: return 0;
997
590k
    }
998
999
590k
  *result = imm & ~((uint64_t) -1 << (esize * 4) << (esize * 4));
1000
1001
590k
  return true;
1002
590k
}
1003
1004
/* Decode a logical immediate for e.g. ORR <Wd|WSP>, <Wn>, #<imm>.  */
1005
bool
1006
aarch64_ext_limm (const aarch64_operand *self,
1007
      aarch64_opnd_info *info, const aarch64_insn code,
1008
      const aarch64_inst *inst,
1009
      aarch64_operand_error *errors ATTRIBUTE_UNUSED)
1010
770k
{
1011
770k
  uint32_t esize;
1012
770k
  aarch64_insn value;
1013
1014
770k
  value = extract_fields (code, 0, 3, self->fields[0], self->fields[1],
1015
770k
        self->fields[2]);
1016
770k
  esize = aarch64_get_qualifier_esize (inst->operands[0].qualifier);
1017
770k
  return decode_limm (esize, value, &info->imm.value);
1018
770k
}
1019
1020
/* Decode a logical immediate for the BIC alias of AND (etc.).  */
1021
bool
1022
aarch64_ext_inv_limm (const aarch64_operand *self,
1023
          aarch64_opnd_info *info, const aarch64_insn code,
1024
          const aarch64_inst *inst,
1025
          aarch64_operand_error *errors)
1026
0
{
1027
0
  if (!aarch64_ext_limm (self, info, code, inst, errors))
1028
0
    return false;
1029
0
  info->imm.value = ~info->imm.value;
1030
0
  return true;
1031
0
}
1032
1033
/* Decode Ft for e.g. STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]
1034
   or LDP <Qt1>, <Qt2>, [<Xn|SP>], #<imm>.  */
1035
bool
1036
aarch64_ext_ft (const aarch64_operand *self ATTRIBUTE_UNUSED,
1037
    aarch64_opnd_info *info,
1038
    const aarch64_insn code, const aarch64_inst *inst,
1039
    aarch64_operand_error *errors ATTRIBUTE_UNUSED)
1040
1.15M
{
1041
1.15M
  aarch64_insn value;
1042
1043
  /* Rt */
1044
1.15M
  info->reg.regno = extract_field (FLD_Rt, code, 0);
1045
1046
  /* size */
1047
1.15M
  value = extract_field (FLD_ldst_size, code, 0);
1048
1.15M
  if (inst->opcode->iclass == ldstpair_indexed
1049
1.15M
      || inst->opcode->iclass == ldstnapair_offs
1050
1.15M
      || inst->opcode->iclass == ldstpair_off
1051
1.15M
      || inst->opcode->iclass == loadlit)
1052
749k
    {
1053
749k
      enum aarch64_opnd_qualifier qualifier;
1054
749k
      switch (value)
1055
749k
  {
1056
175k
  case 0: qualifier = AARCH64_OPND_QLF_S_S; break;
1057
283k
  case 1: qualifier = AARCH64_OPND_QLF_S_D; break;
1058
117k
  case 2: qualifier = AARCH64_OPND_QLF_S_Q; break;
1059
171k
  default: return false;
1060
749k
  }
1061
577k
      info->qualifier = qualifier;
1062
577k
    }
1063
404k
  else
1064
404k
    {
1065
      /* opc1:size */
1066
404k
      value = extract_fields (code, 0, 2, FLD_opc1, FLD_ldst_size);
1067
404k
      if (value > 0x4)
1068
164k
  return false;
1069
239k
      info->qualifier = get_sreg_qualifier_from_value (value);
1070
239k
      if (info->qualifier == AARCH64_OPND_QLF_ERR)
1071
0
  return false;
1072
239k
    }
1073
1074
816k
  return true;
1075
1.15M
}
1076
1077
/* Decode the address operand for e.g. STXRB <Ws>, <Wt>, [<Xn|SP>{,#0}].  */
1078
bool
1079
aarch64_ext_addr_simple (const aarch64_operand *self ATTRIBUTE_UNUSED,
1080
       aarch64_opnd_info *info,
1081
       aarch64_insn code,
1082
       const aarch64_inst *inst ATTRIBUTE_UNUSED,
1083
       aarch64_operand_error *errors ATTRIBUTE_UNUSED)
1084
812k
{
1085
  /* Rn */
1086
812k
  info->addr.base_regno = extract_field (FLD_Rn, code, 0);
1087
812k
  return true;
1088
812k
}
1089
1090
/* Decode the address operand for rcpc3 instructions with optional load/store
1091
   datasize offset, e.g. STILPP <Xs>, <Xt>, [<Xn|SP>{,#-16}]! and
1092
   LIDAP <Xs>, <Xt>, [<Xn|SP>]{,#-16}.  */
1093
bool
1094
aarch64_ext_rcpc3_addr_opt_offset (const aarch64_operand *self ATTRIBUTE_UNUSED,
1095
           aarch64_opnd_info *info,
1096
           aarch64_insn code,
1097
           const aarch64_inst *inst ATTRIBUTE_UNUSED,
1098
           aarch64_operand_error *err ATTRIBUTE_UNUSED)
1099
13.1k
{
1100
13.1k
  info->addr.base_regno = extract_field (FLD_Rn, code, 0);
1101
13.1k
  if (!extract_field (FLD_opc2, code, 0))
1102
1.23k
    {
1103
1.23k
      info->addr.writeback = 1;
1104
1105
1.23k
      enum aarch64_opnd type;
1106
1.23k
      for (int i = 0; i < AARCH64_MAX_OPND_NUM; i++)
1107
1.23k
  {
1108
1.23k
    aarch64_opnd_info opnd = info[i];
1109
1.23k
    type = opnd.type;
1110
1.23k
    if (aarch64_operands[type].op_class == AARCH64_OPND_CLASS_ADDRESS)
1111
1.23k
      break;
1112
1.23k
  }
1113
1114
1.23k
      assert (aarch64_operands[type].op_class == AARCH64_OPND_CLASS_ADDRESS);
1115
1.23k
      int offset = calc_ldst_datasize (inst->operands);
1116
1117
1.23k
      switch (type)
1118
1.23k
  {
1119
552
  case AARCH64_OPND_RCPC3_ADDR_OPT_PREIND_WB:
1120
629
  case AARCH64_OPND_RCPC3_ADDR_PREIND_WB:
1121
629
    info->addr.offset.imm = -offset;
1122
629
    info->addr.preind = 1;
1123
629
    break;
1124
521
  case AARCH64_OPND_RCPC3_ADDR_OPT_POSTIND:
1125
606
  case AARCH64_OPND_RCPC3_ADDR_POSTIND:
1126
606
    info->addr.offset.imm = offset;
1127
606
    info->addr.postind = 1;
1128
606
    break;
1129
0
  default:
1130
0
    return false;
1131
1.23k
  }
1132
1.23k
    }
1133
13.1k
  return true;
1134
13.1k
}
1135
1136
bool
1137
aarch64_ext_rcpc3_addr_offset (const aarch64_operand *self ATTRIBUTE_UNUSED,
1138
             aarch64_opnd_info *info,
1139
             aarch64_insn code,
1140
             const aarch64_inst *inst ATTRIBUTE_UNUSED,
1141
             aarch64_operand_error *errors ATTRIBUTE_UNUSED)
1142
12.5k
{
1143
12.5k
  info->qualifier = get_expected_qualifier (inst, info->idx);
1144
12.5k
  if (info->qualifier == AARCH64_OPND_QLF_ERR)
1145
0
    return 0;
1146
1147
  /* Rn */
1148
12.5k
  info->addr.base_regno = extract_field (self->fields[0], code, 0);
1149
1150
  /* simm9 */
1151
12.5k
  aarch64_insn imm = extract_fields (code, 0, 1, self->fields[1]);
1152
12.5k
  info->addr.offset.imm = sign_extend (imm, 8);
1153
12.5k
  return true;
1154
12.5k
}
1155
1156
/* Decode the address operand for e.g.
1157
     stlur <Xt>, [<Xn|SP>{, <amount>}].  */
1158
bool
1159
aarch64_ext_addr_offset (const aarch64_operand *self ATTRIBUTE_UNUSED,
1160
       aarch64_opnd_info *info,
1161
       aarch64_insn code, const aarch64_inst *inst,
1162
       aarch64_operand_error *errors ATTRIBUTE_UNUSED)
1163
26.0k
{
1164
26.0k
  info->qualifier = get_expected_qualifier (inst, info->idx);
1165
26.0k
  if (info->qualifier == AARCH64_OPND_QLF_ERR)
1166
0
    return 0;
1167
1168
  /* Rn */
1169
26.0k
  info->addr.base_regno = extract_field (self->fields[0], code, 0);
1170
1171
  /* simm9 */
1172
26.0k
  aarch64_insn imm = extract_fields (code, 0, 1, self->fields[1]);
1173
26.0k
  info->addr.offset.imm = sign_extend (imm, 8);
1174
26.0k
  if (extract_field (self->fields[2], code, 0) == 1) {
1175
0
    info->addr.writeback = 1;
1176
0
    info->addr.preind = 1;
1177
0
  }
1178
26.0k
  return true;
1179
26.0k
}
1180
1181
/* Decode the address operand for e.g.
1182
     STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}].  */
1183
bool
1184
aarch64_ext_addr_regoff (const aarch64_operand *self ATTRIBUTE_UNUSED,
1185
       aarch64_opnd_info *info,
1186
       aarch64_insn code, const aarch64_inst *inst,
1187
       aarch64_operand_error *errors ATTRIBUTE_UNUSED)
1188
106k
{
1189
106k
  aarch64_insn S, value;
1190
1191
  /* Rn */
1192
106k
  info->addr.base_regno = extract_field (FLD_Rn, code, 0);
1193
  /* Rm */
1194
106k
  info->addr.offset.regno = extract_field (FLD_Rm, code, 0);
1195
  /* option */
1196
106k
  value = extract_field (FLD_option, code, 0);
1197
106k
  info->shifter.kind =
1198
106k
    aarch64_get_operand_modifier_from_value (value, true /* extend_p */);
1199
  /* Fix-up the shifter kind; although the table-driven approach is
1200
     efficient, it is slightly inflexible, thus needing this fix-up.  */
1201
106k
  if (info->shifter.kind == AARCH64_MOD_UXTX)
1202
34.5k
    info->shifter.kind = AARCH64_MOD_LSL;
1203
  /* S */
1204
106k
  S = extract_field (FLD_S, code, 0);
1205
106k
  if (S == 0)
1206
51.8k
    {
1207
51.8k
      info->shifter.amount = 0;
1208
51.8k
      info->shifter.amount_present = 0;
1209
51.8k
    }
1210
54.2k
  else
1211
54.2k
    {
1212
54.2k
      int size;
1213
      /* Need information in other operand(s) to help achieve the decoding
1214
   from 'S' field.  */
1215
54.2k
      info->qualifier = get_expected_qualifier (inst, info->idx);
1216
54.2k
      if (info->qualifier == AARCH64_OPND_QLF_ERR)
1217
0
  return 0;
1218
      /* Get the size of the data element that is accessed, which may be
1219
   different from that of the source register size, e.g. in strb/ldrb.  */
1220
54.2k
      size = aarch64_get_qualifier_esize (info->qualifier);
1221
54.2k
      info->shifter.amount = get_logsz (size);
1222
54.2k
      info->shifter.amount_present = 1;
1223
54.2k
    }
1224
1225
106k
  return true;
1226
106k
}
1227
1228
/* Decode the address operand for e.g. LDRSW <Xt>, [<Xn|SP>], #<simm>.  */
1229
bool
1230
aarch64_ext_addr_simm (const aarch64_operand *self, aarch64_opnd_info *info,
1231
           aarch64_insn code, const aarch64_inst *inst,
1232
           aarch64_operand_error *errors ATTRIBUTE_UNUSED)
1233
1.29M
{
1234
1.29M
  aarch64_insn imm;
1235
1.29M
  info->qualifier = get_expected_qualifier (inst, info->idx);
1236
1.29M
  if (info->qualifier == AARCH64_OPND_QLF_ERR)
1237
0
    return 0;
1238
1239
  /* Rn */
1240
1.29M
  info->addr.base_regno = extract_field (FLD_Rn, code, 0);
1241
  /* simm (imm9 or imm7)  */
1242
1.29M
  imm = extract_field (self->fields[0], code, 0);
1243
1.29M
  info->addr.offset.imm = sign_extend (imm, fields[self->fields[0]].width - 1);
1244
1.29M
  if (self->fields[0] == FLD_imm7
1245
1.29M
      || info->qualifier == AARCH64_OPND_QLF_imm_tag)
1246
    /* scaled immediate in ld/st pair instructions.  */
1247
995k
    info->addr.offset.imm *= aarch64_get_qualifier_esize (info->qualifier);
1248
  /* qualifier */
1249
1.29M
  if (inst->opcode->iclass == ldst_unscaled
1250
1.29M
      || inst->opcode->iclass == ldstnapair_offs
1251
1.29M
      || inst->opcode->iclass == ldstpair_off
1252
1.29M
      || inst->opcode->iclass == ldst_unpriv)
1253
884k
    info->addr.writeback = 0;
1254
413k
  else
1255
413k
    {
1256
      /* pre/post- index */
1257
413k
      info->addr.writeback = 1;
1258
413k
      if (extract_field (self->fields[1], code, 0) == 1)
1259
192k
  info->addr.preind = 1;
1260
220k
      else
1261
220k
  info->addr.postind = 1;
1262
413k
    }
1263
1264
1.29M
  return true;
1265
1.29M
}
1266
1267
/* Decode the address operand for e.g. LDRSW <Xt>, [<Xn|SP>{, #<simm>}].  */
1268
bool
1269
aarch64_ext_addr_uimm12 (const aarch64_operand *self, aarch64_opnd_info *info,
1270
       aarch64_insn code,
1271
       const aarch64_inst *inst ATTRIBUTE_UNUSED,
1272
       aarch64_operand_error *errors ATTRIBUTE_UNUSED)
1273
903k
{
1274
903k
  int shift;
1275
903k
  info->qualifier = get_expected_qualifier (inst, info->idx);
1276
903k
  if (info->qualifier == AARCH64_OPND_QLF_ERR)
1277
0
    return 0;
1278
903k
  shift = get_logsz (aarch64_get_qualifier_esize (info->qualifier));
1279
  /* Rn */
1280
903k
  info->addr.base_regno = extract_field (self->fields[0], code, 0);
1281
  /* uimm12 */
1282
903k
  info->addr.offset.imm = extract_field (self->fields[1], code, 0) << shift;
1283
903k
  return true;
1284
903k
}
1285
1286
/* Decode the address operand for e.g. LDRAA <Xt>, [<Xn|SP>{, #<simm>}].  */
1287
bool
1288
aarch64_ext_addr_simm10 (const aarch64_operand *self, aarch64_opnd_info *info,
1289
       aarch64_insn code,
1290
       const aarch64_inst *inst ATTRIBUTE_UNUSED,
1291
       aarch64_operand_error *errors ATTRIBUTE_UNUSED)
1292
22.8k
{
1293
22.8k
  aarch64_insn imm;
1294
1295
22.8k
  info->qualifier = get_expected_qualifier (inst, info->idx);
1296
22.8k
  if (info->qualifier == AARCH64_OPND_QLF_ERR)
1297
0
    return 0;
1298
  /* Rn */
1299
22.8k
  info->addr.base_regno = extract_field (self->fields[0], code, 0);
1300
  /* simm10 */
1301
22.8k
  imm = extract_fields (code, 0, 2, self->fields[1], self->fields[2]);
1302
22.8k
  info->addr.offset.imm = sign_extend (imm, 9) << 3;
1303
22.8k
  if (extract_field (self->fields[3], code, 0) == 1) {
1304
13.9k
    info->addr.writeback = 1;
1305
13.9k
    info->addr.preind = 1;
1306
13.9k
  }
1307
22.8k
  return true;
1308
22.8k
}
1309
1310
/* Decode the address operand for e.g.
1311
     LD1 {<Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>}, [<Xn|SP>], <Xm|#<amount>>.  */
1312
bool
1313
aarch64_ext_simd_addr_post (const aarch64_operand *self ATTRIBUTE_UNUSED,
1314
          aarch64_opnd_info *info,
1315
          aarch64_insn code, const aarch64_inst *inst,
1316
          aarch64_operand_error *errors ATTRIBUTE_UNUSED)
1317
64.8k
{
1318
  /* The opcode dependent area stores the number of elements in
1319
     each structure to be loaded/stored.  */
1320
64.8k
  int is_ld1r = get_opcode_dependent_value (inst->opcode) == 1;
1321
1322
  /* Rn */
1323
64.8k
  info->addr.base_regno = extract_field (FLD_Rn, code, 0);
1324
  /* Rm | #<amount>  */
1325
64.8k
  info->addr.offset.regno = extract_field (FLD_Rm, code, 0);
1326
64.8k
  if (info->addr.offset.regno == 31)
1327
3.86k
    {
1328
3.86k
      if (inst->opcode->operands[0] == AARCH64_OPND_LVt_AL)
1329
  /* Special handling of loading single structure to all lane.  */
1330
649
  info->addr.offset.imm = (is_ld1r ? 1
1331
649
         : inst->operands[0].reglist.num_regs)
1332
649
    * aarch64_get_qualifier_esize (inst->operands[0].qualifier);
1333
3.21k
      else
1334
3.21k
  info->addr.offset.imm = inst->operands[0].reglist.num_regs
1335
3.21k
    * aarch64_get_qualifier_esize (inst->operands[0].qualifier)
1336
3.21k
    * aarch64_get_qualifier_nelem (inst->operands[0].qualifier);
1337
3.86k
    }
1338
60.9k
  else
1339
60.9k
    info->addr.offset.is_reg = 1;
1340
64.8k
  info->addr.writeback = 1;
1341
1342
64.8k
  return true;
1343
64.8k
}
1344
1345
/* Decode the condition operand for e.g. CSEL <Xd>, <Xn>, <Xm>, <cond>.  */
1346
bool
1347
aarch64_ext_cond (const aarch64_operand *self ATTRIBUTE_UNUSED,
1348
      aarch64_opnd_info *info,
1349
      aarch64_insn code, const aarch64_inst *inst ATTRIBUTE_UNUSED,
1350
      aarch64_operand_error *errors ATTRIBUTE_UNUSED)
1351
49.2k
{
1352
49.2k
  aarch64_insn value;
1353
  /* cond */
1354
49.2k
  value = extract_field (FLD_cond, code, 0);
1355
49.2k
  info->cond = get_cond_from_value (value);
1356
49.2k
  return true;
1357
49.2k
}
1358
1359
/* Decode the system register operand for e.g. MRS <Xt>, <systemreg>.  */
1360
bool
1361
aarch64_ext_sysreg (const aarch64_operand *self ATTRIBUTE_UNUSED,
1362
        aarch64_opnd_info *info,
1363
        aarch64_insn code,
1364
        const aarch64_inst *inst ATTRIBUTE_UNUSED,
1365
        aarch64_operand_error *errors ATTRIBUTE_UNUSED)
1366
14.0k
{
1367
  /* op0:op1:CRn:CRm:op2 */
1368
14.0k
  info->sysreg.value = extract_fields (code, 0, 5, FLD_op0, FLD_op1, FLD_CRn,
1369
14.0k
               FLD_CRm, FLD_op2);
1370
14.0k
  info->sysreg.flags = 0;
1371
1372
  /* If a system instruction, check which restrictions should be on the register
1373
     value during decoding, these will be enforced then.  */
1374
14.0k
  if (inst->opcode->iclass == ic_system)
1375
14.0k
    {
1376
      /* Check to see if it's read-only, else check if it's write only.
1377
   if it's both or unspecified don't care.  */
1378
14.0k
      if ((inst->opcode->flags & (F_SYS_READ | F_SYS_WRITE)) == F_SYS_READ)
1379
5.58k
  info->sysreg.flags = F_REG_READ;
1380
8.47k
      else if ((inst->opcode->flags & (F_SYS_READ | F_SYS_WRITE))
1381
8.47k
         == F_SYS_WRITE)
1382
8.47k
  info->sysreg.flags = F_REG_WRITE;
1383
14.0k
    }
1384
1385
14.0k
  return true;
1386
14.0k
}
1387
1388
/* Decode the PSTATE field operand for e.g. MSR <pstatefield>, #<imm>.  */
1389
bool
1390
aarch64_ext_pstatefield (const aarch64_operand *self ATTRIBUTE_UNUSED,
1391
       aarch64_opnd_info *info, aarch64_insn code,
1392
       const aarch64_inst *inst ATTRIBUTE_UNUSED,
1393
       aarch64_operand_error *errors ATTRIBUTE_UNUSED)
1394
184
{
1395
184
  int i;
1396
184
  aarch64_insn fld_crm = extract_field (FLD_CRm, code, 0);
1397
  /* op1:op2 */
1398
184
  info->pstatefield = extract_fields (code, 0, 2, FLD_op1, FLD_op2);
1399
1.16k
  for (i = 0; aarch64_pstatefields[i].name != NULL; ++i)
1400
1.11k
    if (aarch64_pstatefields[i].value == (aarch64_insn)info->pstatefield)
1401
282
      {
1402
        /* PSTATEFIELD name can be encoded partially in CRm[3:1].  */
1403
282
        uint32_t flags = aarch64_pstatefields[i].flags;
1404
282
        if ((flags & F_REG_IN_CRM)
1405
282
            && ((fld_crm & 0xe) != PSTATE_DECODE_CRM (flags)))
1406
153
          continue;
1407
129
        info->sysreg.flags = flags;
1408
129
        return true;
1409
282
      }
1410
  /* Reserved value in <pstatefield>.  */
1411
55
  return false;
1412
184
}
1413
1414
/* Decode the system instruction op operand for e.g. AT <at_op>, <Xt>.  */
1415
bool
1416
aarch64_ext_sysins_op (const aarch64_operand *self ATTRIBUTE_UNUSED,
1417
           aarch64_opnd_info *info,
1418
           aarch64_insn code,
1419
           const aarch64_inst *inst ATTRIBUTE_UNUSED,
1420
           aarch64_operand_error *errors ATTRIBUTE_UNUSED)
1421
7.93k
{
1422
7.93k
  int i;
1423
7.93k
  aarch64_insn value;
1424
7.93k
  const aarch64_sys_ins_reg *sysins_ops;
1425
  /* op0:op1:CRn:CRm:op2 */
1426
7.93k
  value = extract_fields (code, 0, 5,
1427
7.93k
        FLD_op0, FLD_op1, FLD_CRn,
1428
7.93k
        FLD_CRm, FLD_op2);
1429
1430
7.93k
  switch (info->type)
1431
7.93k
    {
1432
1.60k
    case AARCH64_OPND_SYSREG_AT: sysins_ops = aarch64_sys_regs_at; break;
1433
1.63k
    case AARCH64_OPND_SYSREG_DC: sysins_ops = aarch64_sys_regs_dc; break;
1434
1.66k
    case AARCH64_OPND_SYSREG_IC: sysins_ops = aarch64_sys_regs_ic; break;
1435
1.80k
    case AARCH64_OPND_SYSREG_TLBI: sysins_ops = aarch64_sys_regs_tlbi; break;
1436
1.22k
    case AARCH64_OPND_SYSREG_TLBIP: sysins_ops = aarch64_sys_regs_tlbi; break;
1437
0
    case AARCH64_OPND_SYSREG_SR:
1438
0
  sysins_ops = aarch64_sys_regs_sr;
1439
   /* Let's remove op2 for rctx.  Refer to comments in the definition of
1440
      aarch64_sys_regs_sr[].  */
1441
0
  value = value & ~(0x7);
1442
0
  break;
1443
0
    default: return false;
1444
7.93k
    }
1445
1446
576k
  for (i = 0; sysins_ops[i].name != NULL; ++i)
1447
569k
    if (sysins_ops[i].value == value)
1448
256
      {
1449
256
  info->sysins_op = sysins_ops + i;
1450
256
  DEBUG_TRACE ("%s found value: %x, has_xt: %d, i: %d.",
1451
256
         info->sysins_op->name,
1452
256
         (unsigned)info->sysins_op->value,
1453
256
         aarch64_sys_ins_reg_has_xt (info->sysins_op), i);
1454
256
  return true;
1455
256
      }
1456
1457
7.68k
  return false;
1458
7.93k
}
1459
1460
/* Decode the memory barrier option operand for e.g. DMB <option>|#<imm>.  */
1461
1462
bool
1463
aarch64_ext_barrier (const aarch64_operand *self ATTRIBUTE_UNUSED,
1464
         aarch64_opnd_info *info,
1465
         aarch64_insn code,
1466
         const aarch64_inst *inst ATTRIBUTE_UNUSED,
1467
         aarch64_operand_error *errors ATTRIBUTE_UNUSED)
1468
247
{
1469
  /* CRm */
1470
247
  info->barrier = aarch64_barrier_options + extract_field (FLD_CRm, code, 0);
1471
247
  return true;
1472
247
}
1473
1474
/* Decode the memory barrier option operand for DSB <option>nXS|#<imm>.  */
1475
1476
bool
1477
aarch64_ext_barrier_dsb_nxs (const aarch64_operand *self ATTRIBUTE_UNUSED,
1478
         aarch64_opnd_info *info,
1479
         aarch64_insn code,
1480
         const aarch64_inst *inst ATTRIBUTE_UNUSED,
1481
         aarch64_operand_error *errors ATTRIBUTE_UNUSED)
1482
60
{
1483
  /* For the DSB nXS barrier variant immediate is encoded in 2-bit field.  */
1484
60
  aarch64_insn field = extract_field (FLD_CRm_dsb_nxs, code, 0);
1485
60
  info->barrier = aarch64_barrier_dsb_nxs_options + field;
1486
60
  return true;
1487
60
}
1488
1489
/* Decode the prefetch operation option operand for e.g.
1490
     PRFM <prfop>, [<Xn|SP>{, #<pimm>}].  */
1491
1492
bool
1493
aarch64_ext_prfop (const aarch64_operand *self ATTRIBUTE_UNUSED,
1494
       aarch64_opnd_info *info,
1495
       aarch64_insn code, const aarch64_inst *inst ATTRIBUTE_UNUSED,
1496
       aarch64_operand_error *errors ATTRIBUTE_UNUSED)
1497
101k
{
1498
  /* prfop in Rt */
1499
101k
  info->prfop = aarch64_prfops + extract_field (FLD_Rt, code, 0);
1500
101k
  return true;
1501
101k
}
1502
1503
/* Decode the hint number for an alias taking an operand.  Set info->hint_option
1504
   to the matching name/value pair in aarch64_hint_options.  */
1505
1506
bool
1507
aarch64_ext_hint (const aarch64_operand *self ATTRIBUTE_UNUSED,
1508
      aarch64_opnd_info *info,
1509
      aarch64_insn code,
1510
      const aarch64_inst *inst ATTRIBUTE_UNUSED,
1511
      aarch64_operand_error *errors ATTRIBUTE_UNUSED)
1512
207
{
1513
  /* CRm:op2.  */
1514
207
  unsigned hint_number;
1515
207
  int i;
1516
1517
207
  hint_number = extract_fields (code, 0, 2, FLD_CRm, FLD_op2);
1518
1519
1.23k
  for (i = 0; aarch64_hint_options[i].name != NULL; i++)
1520
1.23k
    {
1521
1.23k
      if (hint_number == HINT_VAL (aarch64_hint_options[i].value))
1522
207
  {
1523
207
    info->hint_option = &(aarch64_hint_options[i]);
1524
207
    return true;
1525
207
  }
1526
1.23k
    }
1527
1528
0
  return false;
1529
207
}
1530
1531
/* Decode the extended register operand for e.g.
1532
     STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}].  */
1533
bool
1534
aarch64_ext_reg_extended (const aarch64_operand *self ATTRIBUTE_UNUSED,
1535
        aarch64_opnd_info *info,
1536
        aarch64_insn code,
1537
        const aarch64_inst *inst ATTRIBUTE_UNUSED,
1538
        aarch64_operand_error *errors ATTRIBUTE_UNUSED)
1539
88.1k
{
1540
88.1k
  aarch64_insn value;
1541
1542
  /* Rm */
1543
88.1k
  info->reg.regno = extract_field (FLD_Rm, code, 0);
1544
  /* option */
1545
88.1k
  value = extract_field (FLD_option, code, 0);
1546
88.1k
  info->shifter.kind =
1547
88.1k
    aarch64_get_operand_modifier_from_value (value, true /* extend_p */);
1548
  /* imm3 */
1549
88.1k
  info->shifter.amount = extract_field (FLD_imm3_10, code,  0);
1550
1551
  /* This makes the constraint checking happy.  */
1552
88.1k
  info->shifter.operator_present = 1;
1553
1554
  /* Assume inst->operands[0].qualifier has been resolved.  */
1555
88.1k
  assert (inst->operands[0].qualifier != AARCH64_OPND_QLF_NIL);
1556
88.1k
  info->qualifier = AARCH64_OPND_QLF_W;
1557
88.1k
  if (inst->operands[0].qualifier == AARCH64_OPND_QLF_X
1558
88.1k
      && (info->shifter.kind == AARCH64_MOD_UXTX
1559
33.4k
    || info->shifter.kind == AARCH64_MOD_SXTX))
1560
8.65k
    info->qualifier = AARCH64_OPND_QLF_X;
1561
1562
88.1k
  return true;
1563
88.1k
}
1564
1565
/* Decode the shifted register operand for e.g.
1566
     SUBS <Xd>, <Xn>, <Xm> {, <shift> #<amount>}.  */
1567
bool
1568
aarch64_ext_reg_shifted (const aarch64_operand *self ATTRIBUTE_UNUSED,
1569
       aarch64_opnd_info *info,
1570
       aarch64_insn code,
1571
       const aarch64_inst *inst ATTRIBUTE_UNUSED,
1572
       aarch64_operand_error *errors ATTRIBUTE_UNUSED)
1573
1.89M
{
1574
1.89M
  aarch64_insn value;
1575
1576
  /* Rm */
1577
1.89M
  info->reg.regno = extract_field (FLD_Rm, code, 0);
1578
  /* shift */
1579
1.89M
  value = extract_field (FLD_shift, code, 0);
1580
1.89M
  info->shifter.kind =
1581
1.89M
    aarch64_get_operand_modifier_from_value (value, false /* extend_p */);
1582
1.89M
  if (info->shifter.kind == AARCH64_MOD_ROR
1583
1.89M
      && inst->opcode->iclass != log_shift)
1584
    /* ROR is not available for the shifted register operand in arithmetic
1585
       instructions.  */
1586
42.5k
    return false;
1587
  /* imm6 */
1588
1.85M
  info->shifter.amount = extract_field (FLD_imm6_10, code,  0);
1589
1590
  /* This makes the constraint checking happy.  */
1591
1.85M
  info->shifter.operator_present = 1;
1592
1593
1.85M
  return true;
1594
1.89M
}
1595
1596
/* Decode the LSL-shifted register operand for e.g.
1597
     ADDPT <Xd|SP>, <Xn|SP>, <Xm>{, LSL #<amount>}.  */
1598
bool
1599
aarch64_ext_reg_lsl_shifted (const aarch64_operand *self ATTRIBUTE_UNUSED,
1600
           aarch64_opnd_info *info,
1601
           aarch64_insn code,
1602
           const aarch64_inst *inst ATTRIBUTE_UNUSED,
1603
           aarch64_operand_error *errors ATTRIBUTE_UNUSED)
1604
1.33k
{
1605
  /* Rm */
1606
1.33k
  info->reg.regno = extract_field (FLD_Rm, code, 0);
1607
  /* imm3 */
1608
1.33k
  info->shifter.kind = AARCH64_MOD_LSL;
1609
1.33k
  info->shifter.amount = extract_field (FLD_imm3_10, code,  0);
1610
1.33k
  return true;
1611
1.33k
}
1612
1613
/* Decode an SVE address [<base>, #<offset>*<factor>, MUL VL],
1614
   where <offset> is given by the OFFSET parameter and where <factor> is
1615
   1 plus SELF's operand-dependent value.  fields[0] specifies the field
1616
   that holds <base>.  */
1617
static bool
1618
aarch64_ext_sve_addr_reg_mul_vl (const aarch64_operand *self,
1619
         aarch64_opnd_info *info, aarch64_insn code,
1620
         int64_t offset)
1621
98.4k
{
1622
98.4k
  info->addr.base_regno = extract_field (self->fields[0], code, 0);
1623
98.4k
  info->addr.offset.imm = offset * (1 + get_operand_specific_data (self));
1624
98.4k
  info->addr.offset.is_reg = false;
1625
98.4k
  info->addr.writeback = false;
1626
98.4k
  info->addr.preind = true;
1627
98.4k
  if (offset != 0)
1628
94.2k
    info->shifter.kind = AARCH64_MOD_MUL_VL;
1629
98.4k
  info->shifter.amount = 1;
1630
98.4k
  info->shifter.operator_present = (info->addr.offset.imm != 0);
1631
98.4k
  info->shifter.amount_present = false;
1632
98.4k
  return true;
1633
98.4k
}
1634
1635
/* Decode an SVE address [<base>, #<simm4>*<factor>, MUL VL],
1636
   where <simm4> is a 4-bit signed value and where <factor> is 1 plus
1637
   SELF's operand-dependent value.  fields[0] specifies the field that
1638
   holds <base>.  <simm4> is encoded in the SVE_imm4 field.  */
1639
bool
1640
aarch64_ext_sve_addr_ri_s4xvl (const aarch64_operand *self,
1641
             aarch64_opnd_info *info, aarch64_insn code,
1642
             const aarch64_inst *inst ATTRIBUTE_UNUSED,
1643
             aarch64_operand_error *errors ATTRIBUTE_UNUSED)
1644
71.2k
{
1645
71.2k
  int offset;
1646
1647
71.2k
  offset = extract_field (FLD_SVE_imm4, code, 0);
1648
71.2k
  offset = ((offset + 8) & 15) - 8;
1649
71.2k
  return aarch64_ext_sve_addr_reg_mul_vl (self, info, code, offset);
1650
71.2k
}
1651
1652
/* Decode an SVE address [<base>, #<simm6>*<factor>, MUL VL],
1653
   where <simm6> is a 6-bit signed value and where <factor> is 1 plus
1654
   SELF's operand-dependent value.  fields[0] specifies the field that
1655
   holds <base>.  <simm6> is encoded in the SVE_imm6 field.  */
1656
bool
1657
aarch64_ext_sve_addr_ri_s6xvl (const aarch64_operand *self,
1658
             aarch64_opnd_info *info, aarch64_insn code,
1659
             const aarch64_inst *inst ATTRIBUTE_UNUSED,
1660
             aarch64_operand_error *errors ATTRIBUTE_UNUSED)
1661
4.70k
{
1662
4.70k
  int offset;
1663
1664
4.70k
  offset = extract_field (FLD_SVE_imm6, code, 0);
1665
4.70k
  offset = (((offset + 32) & 63) - 32);
1666
4.70k
  return aarch64_ext_sve_addr_reg_mul_vl (self, info, code, offset);
1667
4.70k
}
1668
1669
/* Decode an SVE address [<base>, #<simm9>*<factor>, MUL VL],
1670
   where <simm9> is a 9-bit signed value and where <factor> is 1 plus
1671
   SELF's operand-dependent value.  fields[0] specifies the field that
1672
   holds <base>.  <simm9> is encoded in the concatenation of the SVE_imm6
1673
   and imm3 fields, with imm3 being the less-significant part.  */
1674
bool
1675
aarch64_ext_sve_addr_ri_s9xvl (const aarch64_operand *self,
1676
             aarch64_opnd_info *info,
1677
             aarch64_insn code,
1678
             const aarch64_inst *inst ATTRIBUTE_UNUSED,
1679
             aarch64_operand_error *errors ATTRIBUTE_UNUSED)
1680
22.4k
{
1681
22.4k
  int offset;
1682
1683
22.4k
  offset = extract_fields (code, 0, 2, FLD_SVE_imm6, FLD_imm3_10);
1684
22.4k
  offset = (((offset + 256) & 511) - 256);
1685
22.4k
  return aarch64_ext_sve_addr_reg_mul_vl (self, info, code, offset);
1686
22.4k
}
1687
1688
/* Decode an SVE address [<base>, #<offset> << <shift>], where <offset>
1689
   is given by the OFFSET parameter and where <shift> is SELF's operand-
1690
   dependent value.  fields[0] specifies the base register field <base>.  */
1691
static bool
1692
aarch64_ext_sve_addr_reg_imm (const aarch64_operand *self,
1693
            aarch64_opnd_info *info, aarch64_insn code,
1694
            int64_t offset)
1695
94.1k
{
1696
94.1k
  info->addr.base_regno = extract_field (self->fields[0], code, 0);
1697
94.1k
  info->addr.offset.imm = offset * (1 << get_operand_specific_data (self));
1698
94.1k
  info->addr.offset.is_reg = false;
1699
94.1k
  info->addr.writeback = false;
1700
94.1k
  info->addr.preind = true;
1701
94.1k
  info->shifter.operator_present = false;
1702
94.1k
  info->shifter.amount_present = false;
1703
94.1k
  return true;
1704
94.1k
}
1705
1706
/* Decode an SVE address [X<n>, #<SVE_imm4> << <shift>], where <SVE_imm4>
1707
   is a 4-bit signed number and where <shift> is SELF's operand-dependent
1708
   value.  fields[0] specifies the base register field.  */
1709
bool
1710
aarch64_ext_sve_addr_ri_s4 (const aarch64_operand *self,
1711
          aarch64_opnd_info *info, aarch64_insn code,
1712
          const aarch64_inst *inst ATTRIBUTE_UNUSED,
1713
          aarch64_operand_error *errors ATTRIBUTE_UNUSED)
1714
4.05k
{
1715
4.05k
  int offset = sign_extend (extract_field (FLD_SVE_imm4, code, 0), 3);
1716
4.05k
  return aarch64_ext_sve_addr_reg_imm (self, info, code, offset);
1717
4.05k
}
1718
1719
/* Decode an SVE address [X<n>, #<SVE_imm6> << <shift>], where <SVE_imm6>
1720
   is a 6-bit unsigned number and where <shift> is SELF's operand-dependent
1721
   value.  fields[0] specifies the base register field.  */
1722
bool
1723
aarch64_ext_sve_addr_ri_u6 (const aarch64_operand *self,
1724
          aarch64_opnd_info *info, aarch64_insn code,
1725
          const aarch64_inst *inst ATTRIBUTE_UNUSED,
1726
          aarch64_operand_error *errors ATTRIBUTE_UNUSED)
1727
54.6k
{
1728
54.6k
  int offset = extract_field (FLD_SVE_imm6, code, 0);
1729
54.6k
  return aarch64_ext_sve_addr_reg_imm (self, info, code, offset);
1730
54.6k
}
1731
1732
/* Decode an SVE address [X<n>, X<m>{, LSL #<shift>}], where <shift>
1733
   is SELF's operand-dependent value.  fields[0] specifies the base
1734
   register field and fields[1] specifies the offset register field.  */
1735
bool
1736
aarch64_ext_sve_addr_rr_lsl (const aarch64_operand *self,
1737
           aarch64_opnd_info *info, aarch64_insn code,
1738
           const aarch64_inst *inst ATTRIBUTE_UNUSED,
1739
           aarch64_operand_error *errors ATTRIBUTE_UNUSED)
1740
287k
{
1741
287k
  int index_regno;
1742
1743
287k
  index_regno = extract_field (self->fields[1], code, 0);
1744
287k
  if (index_regno == 31 && (self->flags & OPD_F_NO_ZR) != 0)
1745
1.74k
    return false;
1746
1747
285k
  info->addr.base_regno = extract_field (self->fields[0], code, 0);
1748
285k
  info->addr.offset.regno = index_regno;
1749
285k
  info->addr.offset.is_reg = true;
1750
285k
  info->addr.writeback = false;
1751
285k
  info->addr.preind = true;
1752
285k
  info->shifter.kind = AARCH64_MOD_LSL;
1753
285k
  info->shifter.amount = get_operand_specific_data (self);
1754
285k
  info->shifter.operator_present = (info->shifter.amount != 0);
1755
285k
  info->shifter.amount_present = (info->shifter.amount != 0);
1756
285k
  return true;
1757
287k
}
1758
1759
/* Decode an SVE address [X<n>, Z<m>.<T>, (S|U)XTW {#<shift>}], where
1760
   <shift> is SELF's operand-dependent value.  fields[0] specifies the
1761
   base register field, fields[1] specifies the offset register field and
1762
   fields[2] is a single-bit field that selects SXTW over UXTW.  */
1763
bool
1764
aarch64_ext_sve_addr_rz_xtw (const aarch64_operand *self,
1765
           aarch64_opnd_info *info, aarch64_insn code,
1766
           const aarch64_inst *inst ATTRIBUTE_UNUSED,
1767
           aarch64_operand_error *errors ATTRIBUTE_UNUSED)
1768
149k
{
1769
149k
  info->addr.base_regno = extract_field (self->fields[0], code, 0);
1770
149k
  info->addr.offset.regno = extract_field (self->fields[1], code, 0);
1771
149k
  info->addr.offset.is_reg = true;
1772
149k
  info->addr.writeback = false;
1773
149k
  info->addr.preind = true;
1774
149k
  if (extract_field (self->fields[2], code, 0))
1775
57.2k
    info->shifter.kind = AARCH64_MOD_SXTW;
1776
91.8k
  else
1777
91.8k
    info->shifter.kind = AARCH64_MOD_UXTW;
1778
149k
  info->shifter.amount = get_operand_specific_data (self);
1779
149k
  info->shifter.operator_present = true;
1780
149k
  info->shifter.amount_present = (info->shifter.amount != 0);
1781
149k
  return true;
1782
149k
}
1783
1784
/* Decode an SVE address [Z<n>.<T>, #<imm5> << <shift>], where <imm5> is a
1785
   5-bit unsigned number and where <shift> is SELF's operand-dependent value.
1786
   fields[0] specifies the base register field.  */
1787
bool
1788
aarch64_ext_sve_addr_zi_u5 (const aarch64_operand *self,
1789
          aarch64_opnd_info *info, aarch64_insn code,
1790
          const aarch64_inst *inst ATTRIBUTE_UNUSED,
1791
          aarch64_operand_error *errors ATTRIBUTE_UNUSED)
1792
35.4k
{
1793
35.4k
  int offset = extract_field (FLD_imm5, code, 0);
1794
35.4k
  return aarch64_ext_sve_addr_reg_imm (self, info, code, offset);
1795
35.4k
}
1796
1797
/* Decode an SVE address [Z<n>.<T>, Z<m>.<T>{, <modifier> {#<msz>}}],
1798
   where <modifier> is given by KIND and where <msz> is a 2-bit unsigned
1799
   number.  fields[0] specifies the base register field and fields[1]
1800
   specifies the offset register field.  */
1801
static bool
1802
aarch64_ext_sve_addr_zz (const aarch64_operand *self, aarch64_opnd_info *info,
1803
       aarch64_insn code, enum aarch64_modifier_kind kind)
1804
1.93k
{
1805
1.93k
  info->addr.base_regno = extract_field (self->fields[0], code, 0);
1806
1.93k
  info->addr.offset.regno = extract_field (self->fields[1], code, 0);
1807
1.93k
  info->addr.offset.is_reg = true;
1808
1.93k
  info->addr.writeback = false;
1809
1.93k
  info->addr.preind = true;
1810
1.93k
  info->shifter.kind = kind;
1811
1.93k
  info->shifter.amount = extract_field (FLD_SVE_msz, code, 0);
1812
1.93k
  info->shifter.operator_present = (kind != AARCH64_MOD_LSL
1813
1.93k
            || info->shifter.amount != 0);
1814
1.93k
  info->shifter.amount_present = (info->shifter.amount != 0);
1815
1.93k
  return true;
1816
1.93k
}
1817
1818
/* Decode an SVE address [Z<n>.<T>, Z<m>.<T>{, LSL #<msz>}], where
1819
   <msz> is a 2-bit unsigned number.  fields[0] specifies the base register
1820
   field and fields[1] specifies the offset register field.  */
1821
bool
1822
aarch64_ext_sve_addr_zz_lsl (const aarch64_operand *self,
1823
           aarch64_opnd_info *info, aarch64_insn code,
1824
           const aarch64_inst *inst ATTRIBUTE_UNUSED,
1825
           aarch64_operand_error *errors ATTRIBUTE_UNUSED)
1826
1.12k
{
1827
1.12k
  return aarch64_ext_sve_addr_zz (self, info, code, AARCH64_MOD_LSL);
1828
1.12k
}
1829
1830
/* Decode an SVE address [Z<n>.<T>, Z<m>.<T>, SXTW {#<msz>}], where
1831
   <msz> is a 2-bit unsigned number.  fields[0] specifies the base register
1832
   field and fields[1] specifies the offset register field.  */
1833
bool
1834
aarch64_ext_sve_addr_zz_sxtw (const aarch64_operand *self,
1835
            aarch64_opnd_info *info, aarch64_insn code,
1836
            const aarch64_inst *inst ATTRIBUTE_UNUSED,
1837
            aarch64_operand_error *errors ATTRIBUTE_UNUSED)
1838
305
{
1839
305
  return aarch64_ext_sve_addr_zz (self, info, code, AARCH64_MOD_SXTW);
1840
305
}
1841
1842
/* Decode an SVE address [Z<n>.<T>, Z<m>.<T>, UXTW {#<msz>}], where
1843
   <msz> is a 2-bit unsigned number.  fields[0] specifies the base register
1844
   field and fields[1] specifies the offset register field.  */
1845
bool
1846
aarch64_ext_sve_addr_zz_uxtw (const aarch64_operand *self,
1847
            aarch64_opnd_info *info, aarch64_insn code,
1848
            const aarch64_inst *inst ATTRIBUTE_UNUSED,
1849
            aarch64_operand_error *errors ATTRIBUTE_UNUSED)
1850
504
{
1851
504
  return aarch64_ext_sve_addr_zz (self, info, code, AARCH64_MOD_UXTW);
1852
504
}
1853
1854
/* Finish decoding an SVE arithmetic immediate, given that INFO already
1855
   has the raw field value and that the low 8 bits decode to VALUE.  */
1856
static bool
1857
decode_sve_aimm (aarch64_opnd_info *info, int64_t value)
1858
51.4k
{
1859
51.4k
  info->shifter.kind = AARCH64_MOD_LSL;
1860
51.4k
  info->shifter.amount = 0;
1861
51.4k
  if (info->imm.value & 0x100)
1862
12.5k
    {
1863
12.5k
      if (value == 0)
1864
  /* Decode 0x100 as #0, LSL #8.  */
1865
343
  info->shifter.amount = 8;
1866
12.2k
      else
1867
12.2k
  value *= 256;
1868
12.5k
    }
1869
51.4k
  info->shifter.operator_present = (info->shifter.amount != 0);
1870
51.4k
  info->shifter.amount_present = (info->shifter.amount != 0);
1871
51.4k
  info->imm.value = value;
1872
51.4k
  return true;
1873
51.4k
}
1874
1875
/* Decode an SVE ADD/SUB immediate.  */
1876
bool
1877
aarch64_ext_sve_aimm (const aarch64_operand *self,
1878
          aarch64_opnd_info *info, const aarch64_insn code,
1879
          const aarch64_inst *inst,
1880
          aarch64_operand_error *errors)
1881
1.54k
{
1882
1.54k
  return (aarch64_ext_imm (self, info, code, inst, errors)
1883
1.54k
    && decode_sve_aimm (info, (uint8_t) info->imm.value));
1884
1.54k
}
1885
1886
bool
1887
aarch64_ext_sve_aligned_reglist (const aarch64_operand *self,
1888
         aarch64_opnd_info *info, aarch64_insn code,
1889
         const aarch64_inst *inst ATTRIBUTE_UNUSED,
1890
         aarch64_operand_error *errors ATTRIBUTE_UNUSED)
1891
48.5k
{
1892
48.5k
  unsigned int num_regs = get_operand_specific_data (self);
1893
48.5k
  unsigned int val = extract_field (self->fields[0], code, 0);
1894
48.5k
  info->reglist.first_regno = val * num_regs;
1895
48.5k
  info->reglist.num_regs = num_regs;
1896
48.5k
  info->reglist.stride = 1;
1897
48.5k
  return true;
1898
48.5k
}
1899
1900
/* Decode an SVE CPY/DUP immediate.  */
1901
bool
1902
aarch64_ext_sve_asimm (const aarch64_operand *self,
1903
           aarch64_opnd_info *info, const aarch64_insn code,
1904
           const aarch64_inst *inst,
1905
           aarch64_operand_error *errors)
1906
49.9k
{
1907
49.9k
  return (aarch64_ext_imm (self, info, code, inst, errors)
1908
49.9k
    && decode_sve_aimm (info, (int8_t) info->imm.value));
1909
49.9k
}
1910
1911
/* Decode a single-bit immediate that selects between #0.5 and #1.0.
1912
   The fields array specifies which field to use.  */
1913
bool
1914
aarch64_ext_sve_float_half_one (const aarch64_operand *self,
1915
        aarch64_opnd_info *info, aarch64_insn code,
1916
        const aarch64_inst *inst ATTRIBUTE_UNUSED,
1917
        aarch64_operand_error *errors ATTRIBUTE_UNUSED)
1918
97
{
1919
97
  if (extract_field (self->fields[0], code, 0))
1920
77
    info->imm.value = 0x3f800000;
1921
20
  else
1922
20
    info->imm.value = 0x3f000000;
1923
97
  info->imm.is_fp = true;
1924
97
  return true;
1925
97
}
1926
1927
/* Decode a single-bit immediate that selects between #0.5 and #2.0.
1928
   The fields array specifies which field to use.  */
1929
bool
1930
aarch64_ext_sve_float_half_two (const aarch64_operand *self,
1931
        aarch64_opnd_info *info, aarch64_insn code,
1932
        const aarch64_inst *inst ATTRIBUTE_UNUSED,
1933
        aarch64_operand_error *errors ATTRIBUTE_UNUSED)
1934
80
{
1935
80
  if (extract_field (self->fields[0], code, 0))
1936
7
    info->imm.value = 0x40000000;
1937
73
  else
1938
73
    info->imm.value = 0x3f000000;
1939
80
  info->imm.is_fp = true;
1940
80
  return true;
1941
80
}
1942
1943
/* Decode a single-bit immediate that selects between #0.0 and #1.0.
1944
   The fields array specifies which field to use.  */
1945
bool
1946
aarch64_ext_sve_float_zero_one (const aarch64_operand *self,
1947
        aarch64_opnd_info *info, aarch64_insn code,
1948
        const aarch64_inst *inst ATTRIBUTE_UNUSED,
1949
        aarch64_operand_error *errors ATTRIBUTE_UNUSED)
1950
894
{
1951
894
  if (extract_field (self->fields[0], code, 0))
1952
62
    info->imm.value = 0x3f800000;
1953
832
  else
1954
832
    info->imm.value = 0x0;
1955
894
  info->imm.is_fp = true;
1956
894
  return true;
1957
894
}
1958
1959
/* Decode SME instruction such as MOVZA ZA tile slice to vector.  */
1960
bool
1961
aarch64_ext_sme_za_tile_to_vec (const aarch64_operand *self,
1962
        aarch64_opnd_info *info, aarch64_insn code,
1963
        const aarch64_inst *inst ATTRIBUTE_UNUSED,
1964
        aarch64_operand_error *errors ATTRIBUTE_UNUSED)
1965
365
{
1966
365
  aarch64_insn Qsize;   /* fields Q:S:size.  */
1967
365
  int fld_v = extract_field (self->fields[0], code, 0);
1968
365
  int fld_rv = extract_field (self->fields[1], code, 0);
1969
365
  int fld_zan_imm =  extract_field (FLD_imm4_5, code, 0);
1970
1971
365
  Qsize = extract_fields (inst->value, 0, 2, FLD_SME_size_22, FLD_SME_Q);
1972
365
  switch (Qsize)
1973
365
    {
1974
222
    case 0x0:
1975
222
      info->qualifier = AARCH64_OPND_QLF_S_B;
1976
222
      info->indexed_za.regno = 0;
1977
222
      info->indexed_za.index.imm = fld_zan_imm;
1978
222
      break;
1979
55
    case 0x2:
1980
55
      info->qualifier = AARCH64_OPND_QLF_S_H;
1981
55
      info->indexed_za.regno = fld_zan_imm >> 3;
1982
55
      info->indexed_za.index.imm = fld_zan_imm & 0x07;
1983
55
      break;
1984
10
    case 0x4:
1985
10
      info->qualifier = AARCH64_OPND_QLF_S_S;
1986
10
      info->indexed_za.regno = fld_zan_imm >> 2;
1987
10
      info->indexed_za.index.imm = fld_zan_imm & 0x03;
1988
10
      break;
1989
37
    case 0x6:
1990
37
      info->qualifier = AARCH64_OPND_QLF_S_D;
1991
37
      info->indexed_za.regno = fld_zan_imm >> 1;
1992
37
      info->indexed_za.index.imm = fld_zan_imm & 0x01;
1993
37
      break;
1994
41
    case 0x7:
1995
41
      info->qualifier = AARCH64_OPND_QLF_S_Q;
1996
41
      info->indexed_za.regno = fld_zan_imm;
1997
41
      break;
1998
0
    default:
1999
0
      return false;
2000
365
    }
2001
2002
365
  info->indexed_za.index.regno = fld_rv + 12;
2003
365
  info->indexed_za.v = fld_v;
2004
2005
365
  return true;
2006
365
}
2007
2008
/* Decode ZA tile vector, vector indicator, vector selector, qualifier and
2009
   immediate on numerous SME instruction fields such as MOVA.  */
2010
bool
2011
aarch64_ext_sme_za_hv_tiles (const aarch64_operand *self,
2012
                             aarch64_opnd_info *info, aarch64_insn code,
2013
                             const aarch64_inst *inst ATTRIBUTE_UNUSED,
2014
                             aarch64_operand_error *errors ATTRIBUTE_UNUSED)
2015
142k
{
2016
142k
  int fld_size = extract_field (self->fields[0], code, 0);
2017
142k
  int fld_q = extract_field (self->fields[1], code, 0);
2018
142k
  int fld_v = extract_field (self->fields[2], code, 0);
2019
142k
  int fld_rv = extract_field (self->fields[3], code, 0);
2020
142k
  int fld_zan_imm = extract_field (self->fields[4], code, 0);
2021
2022
  /* Deduce qualifier encoded in size and Q fields.  */
2023
142k
  if (fld_size == 0)
2024
33.6k
    {
2025
33.6k
      info->indexed_za.regno = 0;
2026
33.6k
      info->indexed_za.index.imm = fld_zan_imm;
2027
33.6k
    }
2028
109k
  else if (fld_size == 1)
2029
9.87k
    {
2030
9.87k
      info->indexed_za.regno = fld_zan_imm >> 3;
2031
9.87k
      info->indexed_za.index.imm = fld_zan_imm & 0x07;
2032
9.87k
    }
2033
99.2k
  else if (fld_size == 2)
2034
15.6k
    {
2035
15.6k
      info->indexed_za.regno = fld_zan_imm >> 2;
2036
15.6k
      info->indexed_za.index.imm = fld_zan_imm & 0x03;
2037
15.6k
    }
2038
83.5k
  else if (fld_size == 3 && fld_q == 0)
2039
64.2k
    {
2040
64.2k
      info->indexed_za.regno = fld_zan_imm >> 1;
2041
64.2k
      info->indexed_za.index.imm = fld_zan_imm & 0x01;
2042
64.2k
    }
2043
19.2k
  else if (fld_size == 3 && fld_q == 1)
2044
19.2k
    {
2045
19.2k
      info->indexed_za.regno = fld_zan_imm;
2046
19.2k
      info->indexed_za.index.imm = 0;
2047
19.2k
    }
2048
0
  else
2049
0
    return false;
2050
2051
142k
  info->indexed_za.index.regno = fld_rv + 12;
2052
142k
  info->indexed_za.v = fld_v;
2053
2054
142k
  return true;
2055
142k
}
2056
2057
bool
2058
aarch64_ext_sme_za_hv_tiles_range (const aarch64_operand *self,
2059
           aarch64_opnd_info *info, aarch64_insn code,
2060
           const aarch64_inst *inst ATTRIBUTE_UNUSED,
2061
           aarch64_operand_error *errors
2062
             ATTRIBUTE_UNUSED)
2063
1.88k
{
2064
1.88k
  int ebytes = aarch64_get_qualifier_esize (info->qualifier);
2065
1.88k
  int range_size = get_opcode_dependent_value (inst->opcode);
2066
1.88k
  int fld_v = extract_field (self->fields[0], code, 0);
2067
1.88k
  int fld_rv = extract_field (self->fields[1], code, 0);
2068
1.88k
  int fld_zan_imm = extract_field (self->fields[2], code, 0);
2069
1.88k
  int max_value = 16 / range_size / ebytes;
2070
2071
1.88k
  if (max_value == 0)
2072
80
    max_value = 1;
2073
2074
1.88k
  int regno = fld_zan_imm / max_value;
2075
1.88k
  if (regno >= ebytes)
2076
31
    return false;
2077
2078
1.85k
  info->indexed_za.regno = regno;
2079
1.85k
  info->indexed_za.index.imm = (fld_zan_imm % max_value) * range_size;
2080
1.85k
  info->indexed_za.index.countm1 = range_size - 1;
2081
1.85k
  info->indexed_za.index.regno = fld_rv + 12;
2082
1.85k
  info->indexed_za.v = fld_v;
2083
2084
1.85k
  return true;
2085
1.88k
}
2086
2087
/* Decode in SME instruction ZERO list of up to eight 64-bit element tile names
2088
   separated by commas, encoded in the "imm8" field.
2089
2090
   For programmer convenience an assembler must also accept the names of
2091
   32-bit, 16-bit and 8-bit element tiles which are converted into the
2092
   corresponding set of 64-bit element tiles.
2093
*/
2094
bool
2095
aarch64_ext_sme_za_list (const aarch64_operand *self,
2096
                         aarch64_opnd_info *info, aarch64_insn code,
2097
                         const aarch64_inst *inst ATTRIBUTE_UNUSED,
2098
                         aarch64_operand_error *errors ATTRIBUTE_UNUSED)
2099
0
{
2100
0
  int mask = extract_field (self->fields[0], code, 0);
2101
0
  info->imm.value = mask;
2102
0
  return true;
2103
0
}
2104
2105
/* Decode ZA array vector select register (Rv field), optional vector and
2106
   memory offset (imm4_11 field).
2107
*/
2108
bool
2109
aarch64_ext_sme_za_array (const aarch64_operand *self,
2110
                          aarch64_opnd_info *info, aarch64_insn code,
2111
                          const aarch64_inst *inst,
2112
                          aarch64_operand_error *errors ATTRIBUTE_UNUSED)
2113
93.2k
{
2114
93.2k
  int regno = extract_field (self->fields[0], code, 0);
2115
93.2k
  if (info->type == AARCH64_OPND_SME_ZA_array_off4)
2116
1.01k
    regno += 12;
2117
92.2k
  else
2118
92.2k
    regno += 8;
2119
93.2k
  int imm = extract_field (self->fields[1], code, 0);
2120
93.2k
  int num_offsets = get_operand_specific_data (self);
2121
93.2k
  if (num_offsets == 0)
2122
10.3k
    num_offsets = 1;
2123
93.2k
  info->indexed_za.index.regno = regno;
2124
93.2k
  info->indexed_za.index.imm = imm * num_offsets;
2125
93.2k
  info->indexed_za.index.countm1 = num_offsets - 1;
2126
93.2k
  info->indexed_za.group_size = get_opcode_dependent_value (inst->opcode);
2127
93.2k
  return true;
2128
93.2k
}
2129
2130
/* Decode two ZA tile slice (V, Rv, off3| ZAn ,off2 | ZAn, ol| ZAn) feilds.  */
2131
bool
2132
aarch64_ext_sme_za_vrs1 (const aarch64_operand *self,
2133
        aarch64_opnd_info *info, aarch64_insn code,
2134
        const aarch64_inst *inst,
2135
        aarch64_operand_error *errors ATTRIBUTE_UNUSED)
2136
79
{
2137
79
  int v = extract_field (self->fields[0], code, 0);
2138
79
  int regno = 12 + extract_field (self->fields[1], code, 0);
2139
79
  int imm, za_reg, num_offset = 2;
2140
2141
79
  switch (info->qualifier)
2142
79
    {
2143
12
    case AARCH64_OPND_QLF_S_B:
2144
12
      imm = extract_field (self->fields[2], code, 0);
2145
12
      info->indexed_za.index.imm = imm * num_offset;
2146
12
      break;
2147
64
    case AARCH64_OPND_QLF_S_H:
2148
67
    case AARCH64_OPND_QLF_S_S:
2149
67
      za_reg = extract_field (self->fields[2], code, 0);
2150
67
      imm = extract_field (self->fields[3], code, 0);
2151
67
      info->indexed_za.index.imm = imm * num_offset;
2152
67
      info->indexed_za.regno = za_reg;
2153
67
      break;
2154
0
    case AARCH64_OPND_QLF_S_D:
2155
0
      za_reg = extract_field (self->fields[2], code, 0);
2156
0
      info->indexed_za.regno = za_reg;
2157
0
      break;
2158
0
    default:
2159
0
      return false;
2160
79
    }
2161
2162
79
  info->indexed_za.index.regno = regno;
2163
79
  info->indexed_za.index.countm1 = num_offset - 1;
2164
79
  info->indexed_za.v = v;
2165
79
  info->indexed_za.group_size = get_opcode_dependent_value (inst->opcode);
2166
79
  return true;
2167
79
}
2168
2169
/* Decode four ZA tile slice (V, Rv, off3| ZAn ,off2 | ZAn, ol| ZAn) feilds.  */
2170
bool
2171
aarch64_ext_sme_za_vrs2 (const aarch64_operand *self,
2172
        aarch64_opnd_info *info, aarch64_insn code,
2173
        const aarch64_inst *inst,
2174
        aarch64_operand_error *errors ATTRIBUTE_UNUSED)
2175
340
{
2176
340
  int v = extract_field (self->fields[0], code, 0);
2177
340
  int regno = 12 + extract_field (self->fields[1], code, 0);
2178
340
  int imm, za_reg, num_offset =4;
2179
2180
340
  switch (info->qualifier)
2181
340
    {
2182
267
    case AARCH64_OPND_QLF_S_B:
2183
267
      imm = extract_field (self->fields[2], code, 0);
2184
267
      info->indexed_za.index.imm = imm * num_offset;
2185
267
      break;
2186
6
    case AARCH64_OPND_QLF_S_H:
2187
6
      za_reg = extract_field (self->fields[2], code, 0);
2188
6
      imm = extract_field (self->fields[3], code, 0);
2189
6
      info->indexed_za.index.imm = imm * num_offset;
2190
6
      info->indexed_za.regno = za_reg;
2191
6
      break;
2192
53
    case AARCH64_OPND_QLF_S_S:
2193
67
    case AARCH64_OPND_QLF_S_D:
2194
67
      za_reg = extract_field (self->fields[2], code, 0);
2195
67
      info->indexed_za.regno = za_reg;
2196
67
      break;
2197
0
    default:
2198
0
      return false;
2199
340
    }
2200
2201
340
  info->indexed_za.index.regno = regno;
2202
340
  info->indexed_za.index.countm1 = num_offset - 1;
2203
340
  info->indexed_za.v = v;
2204
340
  info->indexed_za.group_size = get_opcode_dependent_value (inst->opcode);
2205
340
  return true;
2206
340
}
2207
2208
bool
2209
aarch64_ext_sme_addr_ri_u4xvl (const aarch64_operand *self,
2210
                               aarch64_opnd_info *info, aarch64_insn code,
2211
                               const aarch64_inst *inst ATTRIBUTE_UNUSED,
2212
                               aarch64_operand_error *errors ATTRIBUTE_UNUSED)
2213
1.01k
{
2214
1.01k
  int regno = extract_field (self->fields[0], code, 0);
2215
1.01k
  int imm = extract_field (self->fields[1], code, 0);
2216
1.01k
  info->addr.base_regno = regno;
2217
1.01k
  info->addr.offset.imm = imm;
2218
  /* MUL VL operator is always present for this operand.  */
2219
1.01k
  info->shifter.kind = AARCH64_MOD_MUL_VL;
2220
1.01k
  info->shifter.operator_present = (imm != 0);
2221
1.01k
  return true;
2222
1.01k
}
2223
2224
/* Decode {SM|ZA} filed for SMSTART and SMSTOP instructions.  */
2225
bool
2226
aarch64_ext_sme_sm_za (const aarch64_operand *self,
2227
                       aarch64_opnd_info *info, aarch64_insn code,
2228
                       const aarch64_inst *inst ATTRIBUTE_UNUSED,
2229
                       aarch64_operand_error *errors ATTRIBUTE_UNUSED)
2230
55
{
2231
55
  info->pstatefield = 0x1b;
2232
55
  aarch64_insn fld_crm = extract_field (self->fields[0], code, 0);
2233
55
  fld_crm >>= 1;    /* CRm[3:1].  */
2234
2235
55
  if (fld_crm == 0x1)
2236
4
    info->reg.regno = 's';
2237
51
  else if (fld_crm == 0x2)
2238
0
    info->reg.regno = 'z';
2239
51
  else
2240
51
    return false;
2241
2242
4
  return true;
2243
55
}
2244
2245
bool
2246
aarch64_ext_sme_pred_reg_with_index (const aarch64_operand *self,
2247
             aarch64_opnd_info *info, aarch64_insn code,
2248
             const aarch64_inst *inst ATTRIBUTE_UNUSED,
2249
             aarch64_operand_error *errors ATTRIBUTE_UNUSED)
2250
3.43k
{
2251
3.43k
  aarch64_insn fld_rm = extract_field (self->fields[0], code, 0);
2252
3.43k
  aarch64_insn fld_pn = extract_field (self->fields[1], code, 0);
2253
3.43k
  aarch64_insn fld_i1 = extract_field (self->fields[2], code, 0);
2254
3.43k
  aarch64_insn fld_tszh = extract_field (self->fields[3], code, 0);
2255
3.43k
  aarch64_insn fld_tszl = extract_field (self->fields[4], code, 0);
2256
3.43k
  int imm;
2257
2258
3.43k
  info->indexed_za.regno = fld_pn;
2259
3.43k
  info->indexed_za.index.regno = fld_rm + 12;
2260
2261
3.43k
  if (fld_tszl & 0x1)
2262
1.37k
    imm = (fld_i1 << 3) | (fld_tszh << 2) | (fld_tszl >> 1);
2263
2.05k
  else if (fld_tszl & 0x2)
2264
1.29k
    imm = (fld_i1 << 2) | (fld_tszh << 1) | (fld_tszl >> 2);
2265
758
  else if (fld_tszl & 0x4)
2266
548
    imm = (fld_i1 << 1) | fld_tszh;
2267
210
  else if (fld_tszh)
2268
210
    imm = fld_i1;
2269
0
  else
2270
0
    return false;
2271
2272
3.43k
  info->indexed_za.index.imm = imm;
2273
3.43k
  return true;
2274
3.43k
}
2275
2276
/* Decode Zn[MM], where MM has a 7-bit triangular encoding.  The fields
2277
   array specifies which field to use for Zn.  MM is encoded in the
2278
   concatenation of imm5 and SVE_tszh, with imm5 being the less
2279
   significant part.  */
2280
bool
2281
aarch64_ext_sve_index (const aarch64_operand *self,
2282
           aarch64_opnd_info *info, aarch64_insn code,
2283
           const aarch64_inst *inst ATTRIBUTE_UNUSED,
2284
           aarch64_operand_error *errors ATTRIBUTE_UNUSED)
2285
1.27k
{
2286
1.27k
  int val;
2287
2288
1.27k
  info->reglane.regno = extract_field (self->fields[0], code, 0);
2289
1.27k
  val = extract_all_fields_after (self, 1, code);
2290
1.27k
  if ((val & 31) == 0)
2291
0
    return 0;
2292
2.29k
  while ((val & 1) == 0)
2293
1.01k
    val /= 2;
2294
1.27k
  info->reglane.index = val / 2;
2295
1.27k
  return true;
2296
1.27k
}
2297
2298
/* Decode a logical immediate for the MOV alias of SVE DUPM.  */
2299
bool
2300
aarch64_ext_sve_limm_mov (const aarch64_operand *self,
2301
        aarch64_opnd_info *info, const aarch64_insn code,
2302
        const aarch64_inst *inst,
2303
        aarch64_operand_error *errors)
2304
3.86k
{
2305
3.86k
  int esize = aarch64_get_qualifier_esize (inst->operands[0].qualifier);
2306
3.86k
  return (aarch64_ext_limm (self, info, code, inst, errors)
2307
3.86k
    && aarch64_sve_dupm_mov_immediate_p (info->imm.value, esize));
2308
3.86k
}
2309
2310
/* Decode Zn[MM], where Zn occupies the least-significant part of the field
2311
   and where MM occupies the most-significant part.  The operand-dependent
2312
   value specifies the number of bits in Zn.  */
2313
bool
2314
aarch64_ext_sve_quad_index (const aarch64_operand *self,
2315
          aarch64_opnd_info *info, aarch64_insn code,
2316
          const aarch64_inst *inst ATTRIBUTE_UNUSED,
2317
          aarch64_operand_error *errors ATTRIBUTE_UNUSED)
2318
45.0k
{
2319
45.0k
  unsigned int reg_bits = get_operand_specific_data (self);
2320
45.0k
  unsigned int val = extract_all_fields (self, code);
2321
45.0k
  info->reglane.regno = val & ((1 << reg_bits) - 1);
2322
45.0k
  info->reglane.index = val >> reg_bits;
2323
45.0k
  return true;
2324
45.0k
}
2325
2326
/* Decode {Zn.<T> - Zm.<T>}.  The fields array specifies which field
2327
   to use for Zn.  The opcode-dependent value specifies the number
2328
   of registers in the list.  */
2329
bool
2330
aarch64_ext_sve_reglist (const aarch64_operand *self,
2331
       aarch64_opnd_info *info, aarch64_insn code,
2332
       const aarch64_inst *inst ATTRIBUTE_UNUSED,
2333
       aarch64_operand_error *errors ATTRIBUTE_UNUSED)
2334
437k
{
2335
437k
  info->reglist.first_regno = extract_field (self->fields[0], code, 0);
2336
437k
  info->reglist.num_regs = get_opcode_dependent_value (inst->opcode);
2337
437k
  info->reglist.stride = 1;
2338
437k
  return true;
2339
437k
}
2340
2341
/* Decode {Zn.<T> , Zm.<T>}.  The fields array specifies which field
2342
   to use for Zn.  The opcode-dependent value specifies the number
2343
   of registers in the list.  */
2344
bool
2345
aarch64_ext_sve_reglist_zt (const aarch64_operand *self,
2346
          aarch64_opnd_info *info, aarch64_insn code,
2347
          const aarch64_inst *inst ATTRIBUTE_UNUSED,
2348
          aarch64_operand_error *errors ATTRIBUTE_UNUSED)
2349
0
{
2350
0
  info->reglist.first_regno = extract_field (self->fields[0], code, 0);
2351
0
  info->reglist.num_regs = get_operand_specific_data (self);
2352
0
  info->reglist.stride = 1;
2353
0
  return true;
2354
0
}
2355
2356
/* Decode a strided register list.  The first field holds the top bit
2357
   (0 or 16) and the second field holds the lower bits.  The stride is
2358
   16 divided by the list length.  */
2359
bool
2360
aarch64_ext_sve_strided_reglist (const aarch64_operand *self,
2361
         aarch64_opnd_info *info, aarch64_insn code,
2362
         const aarch64_inst *inst ATTRIBUTE_UNUSED,
2363
         aarch64_operand_error *errors
2364
           ATTRIBUTE_UNUSED)
2365
14.7k
{
2366
14.7k
  unsigned int upper = extract_field (self->fields[0], code, 0);
2367
14.7k
  unsigned int lower = extract_field (self->fields[1], code, 0);
2368
14.7k
  info->reglist.first_regno = upper * 16 + lower;
2369
14.7k
  info->reglist.num_regs = get_operand_specific_data (self);
2370
14.7k
  info->reglist.stride = 16 / info->reglist.num_regs;
2371
14.7k
  return true;
2372
14.7k
}
2373
2374
/* Decode <pattern>{, MUL #<amount>}.  The fields array specifies which
2375
   fields to use for <pattern>.  <amount> - 1 is encoded in the SVE_imm4
2376
   field.  */
2377
bool
2378
aarch64_ext_sve_scale (const aarch64_operand *self,
2379
           aarch64_opnd_info *info, aarch64_insn code,
2380
           const aarch64_inst *inst, aarch64_operand_error *errors)
2381
8.55k
{
2382
8.55k
  int val;
2383
2384
8.55k
  if (!aarch64_ext_imm (self, info, code, inst, errors))
2385
0
    return false;
2386
8.55k
  val = extract_field (FLD_SVE_imm4, code, 0);
2387
8.55k
  info->shifter.kind = AARCH64_MOD_MUL;
2388
8.55k
  info->shifter.amount = val + 1;
2389
8.55k
  info->shifter.operator_present = (val != 0);
2390
8.55k
  info->shifter.amount_present = (val != 0);
2391
8.55k
  return true;
2392
8.55k
}
2393
2394
/* Return the top set bit in VALUE, which is expected to be relatively
2395
   small.  */
2396
static uint64_t
2397
get_top_bit (uint64_t value)
2398
18.2k
{
2399
67.7k
  while ((value & -value) != value)
2400
49.5k
    value -= value & -value;
2401
18.2k
  return value;
2402
18.2k
}
2403
2404
/* Decode an SVE shift-left immediate.  */
2405
bool
2406
aarch64_ext_sve_shlimm (const aarch64_operand *self,
2407
      aarch64_opnd_info *info, const aarch64_insn code,
2408
      const aarch64_inst *inst, aarch64_operand_error *errors)
2409
4.26k
{
2410
4.26k
  if (!aarch64_ext_imm (self, info, code, inst, errors)
2411
4.26k
      || info->imm.value == 0)
2412
0
    return false;
2413
2414
4.26k
  info->imm.value -= get_top_bit (info->imm.value);
2415
4.26k
  return true;
2416
4.26k
}
2417
2418
/* Decode an SVE shift-right immediate.  */
2419
bool
2420
aarch64_ext_sve_shrimm (const aarch64_operand *self,
2421
      aarch64_opnd_info *info, const aarch64_insn code,
2422
      const aarch64_inst *inst, aarch64_operand_error *errors)
2423
13.9k
{
2424
13.9k
  if (!aarch64_ext_imm (self, info, code, inst, errors)
2425
13.9k
      || info->imm.value == 0)
2426
0
    return false;
2427
2428
13.9k
  info->imm.value = get_top_bit (info->imm.value) * 2 - info->imm.value;
2429
13.9k
  return true;
2430
13.9k
}
2431
2432
/* Decode X0-X30.  Register 31 is unallocated.  */
2433
bool
2434
aarch64_ext_x0_to_x30 (const aarch64_operand *self, aarch64_opnd_info *info,
2435
           const aarch64_insn code,
2436
           const aarch64_inst *inst ATTRIBUTE_UNUSED,
2437
           aarch64_operand_error *errors ATTRIBUTE_UNUSED)
2438
31.5k
{
2439
31.5k
  info->reg.regno = extract_field (self->fields[0], code, 0);
2440
31.5k
  return info->reg.regno <= 30;
2441
31.5k
}
2442
2443
/* Decode an indexed register, with the first field being the register
2444
   number and the remaining fields being the index.  */
2445
bool
2446
aarch64_ext_simple_index (const aarch64_operand *self, aarch64_opnd_info *info,
2447
        const aarch64_insn code,
2448
        const aarch64_inst *inst ATTRIBUTE_UNUSED,
2449
        aarch64_operand_error *errors ATTRIBUTE_UNUSED)
2450
71.8k
{
2451
71.8k
  int bias = get_operand_specific_data (self);
2452
71.8k
  info->reglane.regno = extract_field (self->fields[0], code, 0) + bias;
2453
71.8k
  info->reglane.index = extract_all_fields_after (self, 1, code);
2454
71.8k
  return true;
2455
71.8k
}
2456
2457
/* Decode a plain shift-right immediate, when there is only a single
2458
   element size.  */
2459
bool
2460
aarch64_ext_plain_shrimm (const aarch64_operand *self, aarch64_opnd_info *info,
2461
        const aarch64_insn code,
2462
        const aarch64_inst *inst ATTRIBUTE_UNUSED,
2463
        aarch64_operand_error *errors ATTRIBUTE_UNUSED)
2464
140
{
2465
140
  unsigned int base = 1 << get_operand_field_width (self, 0);
2466
140
  info->imm.value = base - extract_field (self->fields[0], code, 0);
2467
140
  return true;
2468
140
}
2469

2470
/* Bitfields that are commonly used to encode certain operands' information
2471
   may be partially used as part of the base opcode in some instructions.
2472
   For example, the bit 1 of the field 'size' in
2473
     FCVTXN <Vb><d>, <Va><n>
2474
   is actually part of the base opcode, while only size<0> is available
2475
   for encoding the register type.  Another example is the AdvSIMD
2476
   instruction ORR (register), in which the field 'size' is also used for
2477
   the base opcode, leaving only the field 'Q' available to encode the
2478
   vector register arrangement specifier '8B' or '16B'.
2479
2480
   This function tries to deduce the qualifier from the value of partially
2481
   constrained field(s).  Given the VALUE of such a field or fields, the
2482
   qualifiers CANDIDATES and the MASK (indicating which bits are valid for
2483
   operand encoding), the function returns the matching qualifier or
2484
   AARCH64_OPND_QLF_NIL if nothing matches.
2485
2486
   N.B. CANDIDATES is a group of possible qualifiers that are valid for
2487
   one operand; it has a maximum of AARCH64_MAX_QLF_SEQ_NUM qualifiers and
2488
   may end with AARCH64_OPND_QLF_NIL.  */
2489
2490
static enum aarch64_opnd_qualifier
2491
get_qualifier_from_partial_encoding (aarch64_insn value,
2492
             const enum aarch64_opnd_qualifier* \
2493
             candidates,
2494
             aarch64_insn mask)
2495
308k
{
2496
308k
  int i;
2497
308k
  DEBUG_TRACE ("enter with value: %d, mask: %d", (int)value, (int)mask);
2498
566k
  for (i = 0; i < AARCH64_MAX_QLF_SEQ_NUM; ++i)
2499
566k
    {
2500
566k
      aarch64_insn standard_value;
2501
566k
      if (candidates[i] == AARCH64_OPND_QLF_NIL)
2502
70.2k
  break;
2503
495k
      standard_value = aarch64_get_qualifier_standard_value (candidates[i]);
2504
495k
      if ((standard_value & mask) == (value & mask))
2505
237k
  return candidates[i];
2506
495k
    }
2507
70.2k
  return AARCH64_OPND_QLF_NIL;
2508
308k
}
2509
2510
/* Given a list of qualifier sequences, return all possible valid qualifiers
2511
   for operand IDX in QUALIFIERS.
2512
   Assume QUALIFIERS is an array whose length is large enough.  */
2513
2514
static void
2515
get_operand_possible_qualifiers (int idx,
2516
         const aarch64_opnd_qualifier_seq_t *list,
2517
         enum aarch64_opnd_qualifier *qualifiers)
2518
308k
{
2519
308k
  int i;
2520
1.00M
  for (i = 0; i < AARCH64_MAX_QLF_SEQ_NUM; ++i)
2521
1.00M
    if ((qualifiers[i] = list[i][idx]) == AARCH64_OPND_QLF_NIL)
2522
308k
      break;
2523
308k
}
2524
2525
/* Decode the size Q field for e.g. SHADD.
2526
   We tag one operand with the qualifer according to the code;
2527
   whether the qualifier is valid for this opcode or not, it is the
2528
   duty of the semantic checking.  */
2529
2530
static int
2531
decode_sizeq (aarch64_inst *inst)
2532
761k
{
2533
761k
  int idx;
2534
761k
  enum aarch64_opnd_qualifier qualifier;
2535
761k
  aarch64_insn code;
2536
761k
  aarch64_insn value, mask;
2537
761k
  enum aarch64_field_kind fld_sz;
2538
761k
  enum aarch64_opnd_qualifier candidates[AARCH64_MAX_QLF_SEQ_NUM];
2539
2540
761k
  if (inst->opcode->iclass == asisdlse
2541
761k
     || inst->opcode->iclass == asisdlsep
2542
761k
     || inst->opcode->iclass == asisdlso
2543
761k
     || inst->opcode->iclass == asisdlsop)
2544
226k
    fld_sz = FLD_vldst_size;
2545
534k
  else
2546
534k
    fld_sz = FLD_size;
2547
2548
761k
  code = inst->value;
2549
761k
  value = extract_fields (code, inst->opcode->mask, 2, fld_sz, FLD_Q);
2550
  /* Obtain the info that which bits of fields Q and size are actually
2551
     available for operand encoding.  Opcodes like FMAXNM and FMLA have
2552
     size[1] unavailable.  */
2553
761k
  mask = extract_fields (~inst->opcode->mask, 0, 2, fld_sz, FLD_Q);
2554
2555
  /* The index of the operand we are going to tag a qualifier and the qualifer
2556
     itself are reasoned from the value of the size and Q fields and the
2557
     possible valid qualifier lists.  */
2558
761k
  idx = aarch64_select_operand_for_sizeq_field_coding (inst->opcode);
2559
761k
  DEBUG_TRACE ("key idx: %d", idx);
2560
2561
  /* For most related instruciton, size:Q are fully available for operand
2562
     encoding.  */
2563
761k
  if (mask == 0x7)
2564
461k
    {
2565
461k
      inst->operands[idx].qualifier = get_vreg_qualifier_from_value (value);
2566
461k
      if (inst->operands[idx].qualifier == AARCH64_OPND_QLF_ERR)
2567
0
  return 0;
2568
461k
      return 1;
2569
461k
    }
2570
2571
299k
  get_operand_possible_qualifiers (idx, inst->opcode->qualifiers_list,
2572
299k
           candidates);
2573
#ifdef DEBUG_AARCH64
2574
  if (debug_dump)
2575
    {
2576
      int i;
2577
      for (i = 0; candidates[i] != AARCH64_OPND_QLF_NIL
2578
     && i < AARCH64_MAX_QLF_SEQ_NUM; ++i)
2579
  DEBUG_TRACE ("qualifier %d: %s", i,
2580
         aarch64_get_qualifier_name(candidates[i]));
2581
      DEBUG_TRACE ("%d, %d", (int)value, (int)mask);
2582
    }
2583
#endif /* DEBUG_AARCH64 */
2584
2585
299k
  qualifier = get_qualifier_from_partial_encoding (value, candidates, mask);
2586
2587
299k
  if (qualifier == AARCH64_OPND_QLF_NIL)
2588
70.2k
    return 0;
2589
2590
228k
  inst->operands[idx].qualifier = qualifier;
2591
228k
  return 1;
2592
299k
}
2593
2594
/* Decode size[0]:Q, i.e. bit 22 and bit 30, for
2595
     e.g. FCVTN<Q> <Vd>.<Tb>, <Vn>.<Ta>.  */
2596
2597
static int
2598
decode_asimd_fcvt (aarch64_inst *inst)
2599
240
{
2600
240
  aarch64_field field = {0, 0};
2601
240
  aarch64_insn value;
2602
240
  enum aarch64_opnd_qualifier qualifier;
2603
2604
240
  gen_sub_field (FLD_size, 0, 1, &field);
2605
240
  value = extract_field_2 (&field, inst->value, 0);
2606
240
  qualifier = value == 0 ? AARCH64_OPND_QLF_V_4S
2607
240
    : AARCH64_OPND_QLF_V_2D;
2608
240
  switch (inst->opcode->op)
2609
240
    {
2610
174
    case OP_FCVTN:
2611
193
    case OP_FCVTN2:
2612
      /* FCVTN<Q> <Vd>.<Tb>, <Vn>.<Ta>.  */
2613
193
      inst->operands[1].qualifier = qualifier;
2614
193
      break;
2615
36
    case OP_FCVTL:
2616
47
    case OP_FCVTL2:
2617
      /* FCVTL<Q> <Vd>.<Ta>, <Vn>.<Tb>.  */
2618
47
      inst->operands[0].qualifier = qualifier;
2619
47
      break;
2620
0
    default:
2621
0
      return 0;
2622
240
    }
2623
2624
240
  return 1;
2625
240
}
2626
2627
/* Decode size[0], i.e. bit 22, for
2628
     e.g. FCVTXN <Vb><d>, <Va><n>.  */
2629
2630
static int
2631
decode_asisd_fcvtxn (aarch64_inst *inst)
2632
68
{
2633
68
  aarch64_field field = {0, 0};
2634
68
  gen_sub_field (FLD_size, 0, 1, &field);
2635
68
  if (!extract_field_2 (&field, inst->value, 0))
2636
37
    return 0;
2637
31
  inst->operands[0].qualifier = AARCH64_OPND_QLF_S_S;
2638
31
  return 1;
2639
68
}
2640
2641
/* Decode the 'opc' field for e.g. FCVT <Dd>, <Sn>.  */
2642
static int
2643
decode_fcvt (aarch64_inst *inst)
2644
94
{
2645
94
  enum aarch64_opnd_qualifier qualifier;
2646
94
  aarch64_insn value;
2647
94
  const aarch64_field field = {15, 2};
2648
2649
  /* opc dstsize */
2650
94
  value = extract_field_2 (&field, inst->value, 0);
2651
94
  switch (value)
2652
94
    {
2653
59
    case 0: qualifier = AARCH64_OPND_QLF_S_S; break;
2654
12
    case 1: qualifier = AARCH64_OPND_QLF_S_D; break;
2655
12
    case 3: qualifier = AARCH64_OPND_QLF_S_H; break;
2656
11
    default: return 0;
2657
94
    }
2658
83
  inst->operands[0].qualifier = qualifier;
2659
2660
83
  return 1;
2661
94
}
2662
2663
/* Do miscellaneous decodings that are not common enough to be driven by
2664
   flags.  */
2665
2666
static int
2667
do_misc_decoding (aarch64_inst *inst)
2668
23.3k
{
2669
23.3k
  unsigned int value;
2670
23.3k
  switch (inst->opcode->op)
2671
23.3k
    {
2672
94
    case OP_FCVT:
2673
94
      return decode_fcvt (inst);
2674
2675
174
    case OP_FCVTN:
2676
193
    case OP_FCVTN2:
2677
229
    case OP_FCVTL:
2678
240
    case OP_FCVTL2:
2679
240
      return decode_asimd_fcvt (inst);
2680
2681
68
    case OP_FCVTXN_S:
2682
68
      return decode_asisd_fcvtxn (inst);
2683
2684
1.14k
    case OP_MOV_P_P:
2685
1.54k
    case OP_MOVS_P_P:
2686
1.54k
      value = extract_field (FLD_SVE_Pn, inst->value, 0);
2687
1.54k
      return (value == extract_field (FLD_SVE_Pm, inst->value, 0)
2688
1.54k
        && value == extract_field (FLD_SVE_Pg4_10, inst->value, 0));
2689
2690
17.7k
    case OP_MOV_Z_P_Z:
2691
17.7k
      return (extract_field (FLD_SVE_Zd, inst->value, 0)
2692
17.7k
        == extract_field (FLD_SVE_Zm_16, inst->value, 0));
2693
2694
28
    case OP_MOV_Z_V:
2695
      /* Index must be zero.  */
2696
28
      value = extract_fields (inst->value, 0, 2, FLD_SVE_tszh, FLD_imm5);
2697
28
      return value > 0 && value <= 16 && value == (value & -value);
2698
2699
433
    case OP_MOV_Z_Z:
2700
433
      return (extract_field (FLD_SVE_Zn, inst->value, 0)
2701
433
        == extract_field (FLD_SVE_Zm_16, inst->value, 0));
2702
2703
602
    case OP_MOV_Z_Zi:
2704
      /* Index must be nonzero.  */
2705
602
      value = extract_fields (inst->value, 0, 2, FLD_SVE_tszh, FLD_imm5);
2706
602
      return value > 0 && value != (value & -value);
2707
2708
437
    case OP_MOVM_P_P_P:
2709
437
      return (extract_field (FLD_SVE_Pd, inst->value, 0)
2710
437
        == extract_field (FLD_SVE_Pm, inst->value, 0));
2711
2712
328
    case OP_MOVZS_P_P_P:
2713
765
    case OP_MOVZ_P_P_P:
2714
765
      return (extract_field (FLD_SVE_Pn, inst->value, 0)
2715
765
        == extract_field (FLD_SVE_Pm, inst->value, 0));
2716
2717
173
    case OP_NOTS_P_P_P_Z:
2718
1.34k
    case OP_NOT_P_P_P_Z:
2719
1.34k
      return (extract_field (FLD_SVE_Pm, inst->value, 0)
2720
1.34k
        == extract_field (FLD_SVE_Pg4_10, inst->value, 0));
2721
2722
0
    default:
2723
0
      return 0;
2724
23.3k
    }
2725
23.3k
}
2726
2727
/* Opcodes that have fields shared by multiple operands are usually flagged
2728
   with flags.  In this function, we detect such flags, decode the related
2729
   field(s) and store the information in one of the related operands.  The
2730
   'one' operand is not any operand but one of the operands that can
2731
   accommadate all the information that has been decoded.  */
2732
2733
static int
2734
do_special_decoding (aarch64_inst *inst)
2735
8.03M
{
2736
8.03M
  int idx;
2737
8.03M
  aarch64_insn value;
2738
  /* Condition for truly conditional executed instructions, e.g. b.cond.  */
2739
8.03M
  if (inst->opcode->flags & F_COND)
2740
179k
    {
2741
179k
      value = extract_field (FLD_cond2, inst->value, 0);
2742
179k
      inst->cond = get_cond_from_value (value);
2743
179k
    }
2744
  /* 'sf' field.  */
2745
8.03M
  if (inst->opcode->flags & F_SF)
2746
5.84M
    {
2747
5.84M
      idx = select_operand_for_sf_field_coding (inst->opcode);
2748
5.84M
      value = extract_field (FLD_sf, inst->value, 0);
2749
5.84M
      if (inst->opcode->iclass == fprcvtfloat2int
2750
5.84M
    || inst->opcode->iclass == fprcvtint2float)
2751
495
  {
2752
495
    if (value == 0)
2753
304
      inst->operands[idx].qualifier = AARCH64_OPND_QLF_S_S;
2754
191
    else
2755
191
      inst->operands[idx].qualifier = AARCH64_OPND_QLF_S_D;
2756
495
  }
2757
5.84M
      else
2758
5.84M
  inst->operands[idx].qualifier = get_greg_qualifier_from_value (value);
2759
5.84M
      if (inst->operands[idx].qualifier == AARCH64_OPND_QLF_ERR)
2760
0
  return 0;
2761
5.84M
      if ((inst->opcode->flags & F_N)
2762
5.84M
    && extract_field (FLD_N, inst->value, 0) != value)
2763
137k
  return 0;
2764
5.84M
    }
2765
  /* 'sf' field.  */
2766
7.89M
  if (inst->opcode->flags & F_LSE_SZ)
2767
45.1k
    {
2768
45.1k
      idx = select_operand_for_sf_field_coding (inst->opcode);
2769
45.1k
      value = extract_field (FLD_lse_sz, inst->value, 0);
2770
45.1k
      inst->operands[idx].qualifier = get_greg_qualifier_from_value (value);
2771
45.1k
      if (inst->operands[idx].qualifier == AARCH64_OPND_QLF_ERR)
2772
0
  return 0;
2773
45.1k
    }
2774
  /* rcpc3 'size' field.  */
2775
7.89M
  if (inst->opcode->flags & F_RCPC3_SIZE)
2776
31.4k
    {
2777
31.4k
      value = extract_field (FLD_rcpc3_size, inst->value, 0);
2778
31.4k
      for (int i = 0;
2779
70.2k
     aarch64_operands[inst->operands[i].type].op_class != AARCH64_OPND_CLASS_ADDRESS;
2780
38.7k
     i++)
2781
44.5k
  {
2782
44.5k
    if (aarch64_operands[inst->operands[i].type].op_class
2783
44.5k
        == AARCH64_OPND_CLASS_INT_REG)
2784
26.2k
      {
2785
26.2k
        inst->operands[i].qualifier = get_greg_qualifier_from_value (value & 1);
2786
26.2k
        if (inst->operands[i].qualifier == AARCH64_OPND_QLF_ERR)
2787
0
    return 0;
2788
26.2k
      }
2789
18.2k
    else if (aarch64_operands[inst->operands[i].type].op_class
2790
18.2k
        == AARCH64_OPND_CLASS_FP_REG)
2791
18.2k
      {
2792
18.2k
        value += (extract_field (FLD_opc1, inst->value, 0) << 2);
2793
18.2k
        inst->operands[i].qualifier = get_sreg_qualifier_from_value (value);
2794
18.2k
        if (inst->operands[i].qualifier == AARCH64_OPND_QLF_ERR)
2795
5.78k
    return 0;
2796
18.2k
      }
2797
44.5k
  }
2798
31.4k
    }
2799
2800
  /* size:Q fields.  */
2801
7.88M
  if (inst->opcode->flags & F_SIZEQ)
2802
761k
    return decode_sizeq (inst);
2803
2804
7.12M
  if (inst->opcode->flags & F_FPTYPE)
2805
147k
    {
2806
147k
      idx = select_operand_for_fptype_field_coding (inst->opcode);
2807
147k
      value = extract_field (FLD_type, inst->value, 0);
2808
147k
      switch (value)
2809
147k
  {
2810
53.1k
  case 0: inst->operands[idx].qualifier = AARCH64_OPND_QLF_S_S; break;
2811
13.2k
  case 1: inst->operands[idx].qualifier = AARCH64_OPND_QLF_S_D; break;
2812
40.8k
  case 3: inst->operands[idx].qualifier = AARCH64_OPND_QLF_S_H; break;
2813
40.6k
  default: return 0;
2814
147k
  }
2815
147k
    }
2816
2817
7.08M
  if (inst->opcode->flags & F_SSIZE)
2818
39.9k
    {
2819
      /* N.B. some opcodes like FCMGT <V><d>, <V><n>, #0 have the size[1] as part
2820
   of the base opcode.  */
2821
39.9k
      aarch64_insn mask;
2822
39.9k
      enum aarch64_opnd_qualifier candidates[AARCH64_MAX_QLF_SEQ_NUM];
2823
39.9k
      idx = select_operand_for_scalar_size_field_coding (inst->opcode);
2824
39.9k
      value = extract_field (FLD_size, inst->value, inst->opcode->mask);
2825
39.9k
      mask = extract_field (FLD_size, ~inst->opcode->mask, 0);
2826
      /* For most related instruciton, the 'size' field is fully available for
2827
   operand encoding.  */
2828
39.9k
      if (mask == 0x3)
2829
30.9k
  {
2830
30.9k
    inst->operands[idx].qualifier = get_sreg_qualifier_from_value (value);
2831
30.9k
    if (inst->operands[idx].qualifier == AARCH64_OPND_QLF_ERR)
2832
0
      return 0;
2833
30.9k
  }
2834
9.00k
      else
2835
9.00k
  {
2836
9.00k
    get_operand_possible_qualifiers (idx, inst->opcode->qualifiers_list,
2837
9.00k
             candidates);
2838
9.00k
    inst->operands[idx].qualifier
2839
9.00k
      = get_qualifier_from_partial_encoding (value, candidates, mask);
2840
9.00k
  }
2841
39.9k
    }
2842
2843
7.08M
  if (inst->opcode->flags & F_LSFE_SZ)
2844
16.9k
    {
2845
16.9k
      value = extract_field (FLD_ldst_size, inst->value, 0);
2846
2847
16.9k
      if (value > 0x3)
2848
0
  return 0;
2849
2850
16.9k
      for (int i = 0;
2851
50.9k
     aarch64_operands[inst->operands[i].type].op_class != AARCH64_OPND_CLASS_ADDRESS;
2852
33.9k
     i++)
2853
33.9k
  {
2854
33.9k
    inst->operands[i].qualifier = get_sreg_qualifier_from_value (value);
2855
33.9k
    if (inst->operands[i].qualifier == AARCH64_OPND_QLF_ERR)
2856
0
      return 0;
2857
33.9k
  }
2858
16.9k
    }
2859
2860
7.08M
  if (inst->opcode->flags & F_T)
2861
10.8k
    {
2862
      /* Num of consecutive '0's on the right side of imm5<3:0>.  */
2863
10.8k
      int num = 0;
2864
10.8k
      unsigned val, Q;
2865
10.8k
      assert (aarch64_get_operand_class (inst->opcode->operands[0])
2866
10.8k
        == AARCH64_OPND_CLASS_SIMD_REG);
2867
      /* imm5<3:0>  q <t>
2868
   0000   x reserved
2869
   xxx1   0 8b
2870
   xxx1   1 16b
2871
   xx10   0 4h
2872
   xx10   1 8h
2873
   x100   0 2s
2874
   x100   1 4s
2875
   1000   0 reserved
2876
   1000   1 2d  */
2877
10.8k
      val = extract_field (FLD_imm5, inst->value, 0);
2878
24.3k
      while ((val & 0x1) == 0 && ++num <= 3)
2879
13.4k
  val >>= 1;
2880
10.8k
      if (num > 3)
2881
1.35k
  return 0;
2882
9.52k
      Q = (unsigned) extract_field (FLD_Q, inst->value, inst->opcode->mask);
2883
9.52k
      inst->operands[0].qualifier =
2884
9.52k
  get_vreg_qualifier_from_value ((num << 1) | Q);
2885
9.52k
      if (inst->operands[0].qualifier == AARCH64_OPND_QLF_ERR)
2886
0
  return 0;
2887
2888
9.52k
    }
2889
2890
7.08M
  if ((inst->opcode->flags & F_OPD_SIZE) && inst->opcode->iclass == sve2_urqvs)
2891
1.25k
    {
2892
1.25k
      unsigned size;
2893
1.25k
      size = (unsigned) extract_field (FLD_size, inst->value,
2894
1.25k
               inst->opcode->mask);
2895
1.25k
      inst->operands[0].qualifier
2896
1.25k
  = get_vreg_qualifier_from_value (1 + (size << 1));
2897
1.25k
      if (inst->operands[0].qualifier == AARCH64_OPND_QLF_ERR)
2898
0
  return 0;
2899
1.25k
      inst->operands[2].qualifier = get_sreg_qualifier_from_value (size);
2900
1.25k
      if (inst->operands[2].qualifier == AARCH64_OPND_QLF_ERR)
2901
0
  return 0;
2902
1.25k
    }
2903
2904
7.08M
  if (inst->opcode->flags & F_GPRSIZE_IN_Q)
2905
864k
    {
2906
      /* Use Rt to encode in the case of e.g.
2907
   STXP <Ws>, <Xt1>, <Xt2>, [<Xn|SP>{,#0}].  */
2908
864k
      idx = aarch64_operand_index (inst->opcode->operands, AARCH64_OPND_Rt);
2909
864k
      if (idx == -1)
2910
4.10k
  {
2911
    /* Otherwise use the result operand, which has to be a integer
2912
       register.  */
2913
4.10k
    assert (aarch64_get_operand_class (inst->opcode->operands[0])
2914
4.10k
      == AARCH64_OPND_CLASS_INT_REG);
2915
4.10k
    idx = 0;
2916
4.10k
  }
2917
864k
      assert (idx == 0 || idx == 1);
2918
864k
      value = extract_field (FLD_Q, inst->value, 0);
2919
864k
      inst->operands[idx].qualifier = get_greg_qualifier_from_value (value);
2920
864k
      if (inst->operands[idx].qualifier == AARCH64_OPND_QLF_ERR)
2921
0
  return 0;
2922
864k
    }
2923
2924
7.08M
  if (inst->opcode->flags & F_LDS_SIZE)
2925
73.9k
    {
2926
73.9k
      aarch64_field field = {0, 0};
2927
73.9k
      assert (aarch64_get_operand_class (inst->opcode->operands[0])
2928
73.9k
        == AARCH64_OPND_CLASS_INT_REG);
2929
73.9k
      gen_sub_field (FLD_opc, 0, 1, &field);
2930
73.9k
      value = extract_field_2 (&field, inst->value, 0);
2931
73.9k
      inst->operands[0].qualifier
2932
73.9k
  = value ? AARCH64_OPND_QLF_W : AARCH64_OPND_QLF_X;
2933
73.9k
    }
2934
2935
  /* Miscellaneous decoding; done as the last step.  */
2936
7.08M
  if (inst->opcode->flags & F_MISC)
2937
23.3k
    return do_misc_decoding (inst);
2938
2939
7.06M
  return 1;
2940
7.08M
}
2941
2942
/* Converters converting a real opcode instruction to its alias form.  */
2943
2944
/* ROR <Wd>, <Ws>, #<shift>
2945
     is equivalent to:
2946
   EXTR <Wd>, <Ws>, <Ws>, #<shift>.  */
2947
static int
2948
convert_extr_to_ror (aarch64_inst *inst)
2949
9.15k
{
2950
9.15k
  if (inst->operands[1].reg.regno == inst->operands[2].reg.regno)
2951
246
    {
2952
246
      copy_operand_info (inst, 2, 3);
2953
246
      inst->operands[3].type = AARCH64_OPND_NIL;
2954
246
      return 1;
2955
246
    }
2956
8.90k
  return 0;
2957
9.15k
}
2958
2959
/* UXTL<Q> <Vd>.<Ta>, <Vn>.<Tb>
2960
     is equivalent to:
2961
   USHLL<Q> <Vd>.<Ta>, <Vn>.<Tb>, #0.  */
2962
static int
2963
convert_shll_to_xtl (aarch64_inst *inst)
2964
283
{
2965
283
  if (inst->operands[2].imm.value == 0)
2966
240
    {
2967
240
      inst->operands[2].type = AARCH64_OPND_NIL;
2968
240
      return 1;
2969
240
    }
2970
43
  return 0;
2971
283
}
2972
2973
/* Convert
2974
     UBFM <Xd>, <Xn>, #<shift>, #63.
2975
   to
2976
     LSR <Xd>, <Xn>, #<shift>.  */
2977
static int
2978
convert_bfm_to_sr (aarch64_inst *inst)
2979
53.5k
{
2980
53.5k
  int64_t imms, val;
2981
2982
53.5k
  imms = inst->operands[3].imm.value;
2983
53.5k
  val = inst->operands[2].qualifier == AARCH64_OPND_QLF_imm_0_31 ? 31 : 63;
2984
53.5k
  if (imms == val)
2985
3.54k
    {
2986
3.54k
      inst->operands[3].type = AARCH64_OPND_NIL;
2987
3.54k
      return 1;
2988
3.54k
    }
2989
2990
49.9k
  return 0;
2991
53.5k
}
2992
2993
/* Convert MOV to ORR.  */
2994
static int
2995
convert_orr_to_mov (aarch64_inst *inst)
2996
467
{
2997
  /* MOV <Vd>.<T>, <Vn>.<T>
2998
     is equivalent to:
2999
     ORR <Vd>.<T>, <Vn>.<T>, <Vn>.<T>.  */
3000
467
  if (inst->operands[1].reg.regno == inst->operands[2].reg.regno)
3001
113
    {
3002
113
      inst->operands[2].type = AARCH64_OPND_NIL;
3003
113
      return 1;
3004
113
    }
3005
354
  return 0;
3006
467
}
3007
3008
/* When <imms> >= <immr>, the instruction written:
3009
     SBFX <Xd>, <Xn>, #<lsb>, #<width>
3010
   is equivalent to:
3011
     SBFM <Xd>, <Xn>, #<lsb>, #(<lsb>+<width>-1).  */
3012
3013
static int
3014
convert_bfm_to_bfx (aarch64_inst *inst)
3015
61.6k
{
3016
61.6k
  int64_t immr, imms;
3017
3018
61.6k
  immr = inst->operands[2].imm.value;
3019
61.6k
  imms = inst->operands[3].imm.value;
3020
61.6k
  if (imms >= immr)
3021
31.3k
    {
3022
31.3k
      int64_t lsb = immr;
3023
31.3k
      inst->operands[2].imm.value = lsb;
3024
31.3k
      inst->operands[3].imm.value = imms + 1 - lsb;
3025
      /* The two opcodes have different qualifiers for
3026
   the immediate operands; reset to help the checking.  */
3027
31.3k
      reset_operand_qualifier (inst, 2);
3028
31.3k
      reset_operand_qualifier (inst, 3);
3029
31.3k
      return 1;
3030
31.3k
    }
3031
3032
30.2k
  return 0;
3033
61.6k
}
3034
3035
/* When <imms> < <immr>, the instruction written:
3036
     SBFIZ <Xd>, <Xn>, #<lsb>, #<width>
3037
   is equivalent to:
3038
     SBFM <Xd>, <Xn>, #((64-<lsb>)&0x3f), #(<width>-1).  */
3039
3040
static int
3041
convert_bfm_to_bfi (aarch64_inst *inst)
3042
30.2k
{
3043
30.2k
  int64_t immr, imms, val;
3044
3045
30.2k
  immr = inst->operands[2].imm.value;
3046
30.2k
  imms = inst->operands[3].imm.value;
3047
30.2k
  val = inst->operands[2].qualifier == AARCH64_OPND_QLF_imm_0_31 ? 32 : 64;
3048
30.2k
  if (imms < immr)
3049
30.2k
    {
3050
30.2k
      inst->operands[2].imm.value = (val - immr) & (val - 1);
3051
30.2k
      inst->operands[3].imm.value = imms + 1;
3052
      /* The two opcodes have different qualifiers for
3053
   the immediate operands; reset to help the checking.  */
3054
30.2k
      reset_operand_qualifier (inst, 2);
3055
30.2k
      reset_operand_qualifier (inst, 3);
3056
30.2k
      return 1;
3057
30.2k
    }
3058
3059
0
  return 0;
3060
30.2k
}
3061
3062
/* The instruction written:
3063
     BFC <Xd>, #<lsb>, #<width>
3064
   is equivalent to:
3065
     BFM <Xd>, XZR, #((64-<lsb>)&0x3f), #(<width>-1).  */
3066
3067
static int
3068
convert_bfm_to_bfc (aarch64_inst *inst)
3069
546
{
3070
546
  int64_t immr, imms, val;
3071
3072
  /* Should have been assured by the base opcode value.  */
3073
546
  assert (inst->operands[1].reg.regno == 0x1f);
3074
3075
546
  immr = inst->operands[2].imm.value;
3076
546
  imms = inst->operands[3].imm.value;
3077
546
  val = inst->operands[2].qualifier == AARCH64_OPND_QLF_imm_0_31 ? 32 : 64;
3078
546
  if (imms < immr)
3079
119
    {
3080
      /* Drop XZR from the second operand.  */
3081
119
      copy_operand_info (inst, 1, 2);
3082
119
      copy_operand_info (inst, 2, 3);
3083
119
      inst->operands[3].type = AARCH64_OPND_NIL;
3084
3085
      /* Recalculate the immediates.  */
3086
119
      inst->operands[1].imm.value = (val - immr) & (val - 1);
3087
119
      inst->operands[2].imm.value = imms + 1;
3088
3089
      /* The two opcodes have different qualifiers for the operands; reset to
3090
   help the checking.  */
3091
119
      reset_operand_qualifier (inst, 1);
3092
119
      reset_operand_qualifier (inst, 2);
3093
119
      reset_operand_qualifier (inst, 3);
3094
3095
119
      return 1;
3096
119
    }
3097
3098
427
  return 0;
3099
546
}
3100
3101
/* The instruction written:
3102
     LSL <Xd>, <Xn>, #<shift>
3103
   is equivalent to:
3104
     UBFM <Xd>, <Xn>, #((64-<shift>)&0x3f), #(63-<shift>).  */
3105
3106
static int
3107
convert_ubfm_to_lsl (aarch64_inst *inst)
3108
18.5k
{
3109
18.5k
  int64_t immr = inst->operands[2].imm.value;
3110
18.5k
  int64_t imms = inst->operands[3].imm.value;
3111
18.5k
  int64_t val
3112
18.5k
    = inst->operands[2].qualifier == AARCH64_OPND_QLF_imm_0_31 ? 31 : 63;
3113
3114
18.5k
  if ((immr == 0 && imms == val) || immr == imms + 1)
3115
3.23k
    {
3116
3.23k
      inst->operands[3].type = AARCH64_OPND_NIL;
3117
3.23k
      inst->operands[2].imm.value = val - imms;
3118
3.23k
      return 1;
3119
3.23k
    }
3120
3121
15.3k
  return 0;
3122
18.5k
}
3123
3124
/* CINC <Wd>, <Wn>, <cond>
3125
     is equivalent to:
3126
   CSINC <Wd>, <Wn>, <Wn>, invert(<cond>)
3127
     where <cond> is not AL or NV.  */
3128
3129
static int
3130
convert_from_csel (aarch64_inst *inst)
3131
8.13k
{
3132
8.13k
  if (inst->operands[1].reg.regno == inst->operands[2].reg.regno
3133
8.13k
      && (inst->operands[3].cond->value & 0xe) != 0xe)
3134
952
    {
3135
952
      copy_operand_info (inst, 2, 3);
3136
952
      inst->operands[2].cond = get_inverted_cond (inst->operands[3].cond);
3137
952
      inst->operands[3].type = AARCH64_OPND_NIL;
3138
952
      return 1;
3139
952
    }
3140
7.18k
  return 0;
3141
8.13k
}
3142
3143
/* CSET <Wd>, <cond>
3144
     is equivalent to:
3145
   CSINC <Wd>, WZR, WZR, invert(<cond>)
3146
     where <cond> is not AL or NV.  */
3147
3148
static int
3149
convert_csinc_to_cset (aarch64_inst *inst)
3150
8.05k
{
3151
8.05k
  if (inst->operands[1].reg.regno == 0x1f
3152
8.05k
      && inst->operands[2].reg.regno == 0x1f
3153
8.05k
      && (inst->operands[3].cond->value & 0xe) != 0xe)
3154
7.93k
    {
3155
7.93k
      copy_operand_info (inst, 1, 3);
3156
7.93k
      inst->operands[1].cond = get_inverted_cond (inst->operands[3].cond);
3157
7.93k
      inst->operands[3].type = AARCH64_OPND_NIL;
3158
7.93k
      inst->operands[2].type = AARCH64_OPND_NIL;
3159
7.93k
      return 1;
3160
7.93k
    }
3161
120
  return 0;
3162
8.05k
}
3163
3164
/* MOV <Wd>, #<imm>
3165
     is equivalent to:
3166
   MOVZ <Wd>, #<imm16_5>, LSL #<shift>.
3167
3168
   A disassembler may output ORR, MOVZ and MOVN as a MOV mnemonic, except when
3169
   ORR has an immediate that could be generated by a MOVZ or MOVN instruction,
3170
   or where a MOVN has an immediate that could be encoded by MOVZ, or where
3171
   MOVZ/MOVN #0 have a shift amount other than LSL #0, in which case the
3172
   machine-instruction mnemonic must be used.  */
3173
3174
static int
3175
convert_movewide_to_mov (aarch64_inst *inst)
3176
243k
{
3177
243k
  uint64_t value = inst->operands[1].imm.value;
3178
  /* MOVZ/MOVN #0 have a shift amount other than LSL #0.  */
3179
243k
  if (value == 0 && inst->operands[1].shifter.amount != 0)
3180
77
    return 0;
3181
243k
  inst->operands[1].type = AARCH64_OPND_IMM_MOV;
3182
243k
  inst->operands[1].shifter.kind = AARCH64_MOD_NONE;
3183
243k
  value <<= inst->operands[1].shifter.amount;
3184
  /* As an alias convertor, it has to be clear that the INST->OPCODE
3185
     is the opcode of the real instruction.  */
3186
243k
  if (inst->opcode->op == OP_MOVN)
3187
51.1k
    {
3188
51.1k
      int is32 = inst->operands[0].qualifier == AARCH64_OPND_QLF_W;
3189
51.1k
      value = ~value;
3190
      /* A MOVN has an immediate that could be encoded by MOVZ.  */
3191
51.1k
      if (aarch64_wide_constant_p (value, is32, NULL))
3192
61
  return 0;
3193
51.1k
    }
3194
243k
  inst->operands[1].imm.value = value;
3195
243k
  inst->operands[1].shifter.amount = 0;
3196
243k
  return 1;
3197
243k
}
3198
3199
/* MOV <Wd>, #<imm>
3200
     is equivalent to:
3201
   ORR <Wd>, WZR, #<imm>.
3202
3203
   A disassembler may output ORR, MOVZ and MOVN as a MOV mnemonic, except when
3204
   ORR has an immediate that could be generated by a MOVZ or MOVN instruction,
3205
   or where a MOVN has an immediate that could be encoded by MOVZ, or where
3206
   MOVZ/MOVN #0 have a shift amount other than LSL #0, in which case the
3207
   machine-instruction mnemonic must be used.  */
3208
3209
static int
3210
convert_movebitmask_to_mov (aarch64_inst *inst)
3211
2.04k
{
3212
2.04k
  int is32;
3213
2.04k
  uint64_t value;
3214
3215
  /* Should have been assured by the base opcode value.  */
3216
2.04k
  assert (inst->operands[1].reg.regno == 0x1f);
3217
2.04k
  copy_operand_info (inst, 1, 2);
3218
2.04k
  is32 = inst->operands[0].qualifier == AARCH64_OPND_QLF_W;
3219
2.04k
  inst->operands[1].type = AARCH64_OPND_IMM_MOV;
3220
2.04k
  value = inst->operands[1].imm.value;
3221
  /* ORR has an immediate that could be generated by a MOVZ or MOVN
3222
     instruction.  */
3223
2.04k
  if (inst->operands[0].reg.regno != 0x1f
3224
2.04k
      && (aarch64_wide_constant_p (value, is32, NULL)
3225
1.85k
    || aarch64_wide_constant_p (~value, is32, NULL)))
3226
1.05k
    return 0;
3227
3228
987
  inst->operands[2].type = AARCH64_OPND_NIL;
3229
987
  return 1;
3230
2.04k
}
3231
3232
/* Some alias opcodes are disassembled by being converted from their real-form.
3233
   N.B. INST->OPCODE is the real opcode rather than the alias.  */
3234
3235
static int
3236
convert_to_alias (aarch64_inst *inst, const aarch64_opcode *alias)
3237
436k
{
3238
436k
  switch (alias->op)
3239
436k
    {
3240
32.6k
    case OP_ASR_IMM:
3241
53.5k
    case OP_LSR_IMM:
3242
53.5k
      return convert_bfm_to_sr (inst);
3243
18.5k
    case OP_LSL_IMM:
3244
18.5k
      return convert_ubfm_to_lsl (inst);
3245
3.18k
    case OP_CINC:
3246
6.46k
    case OP_CINV:
3247
8.13k
    case OP_CNEG:
3248
8.13k
      return convert_from_csel (inst);
3249
7.83k
    case OP_CSET:
3250
8.05k
    case OP_CSETM:
3251
8.05k
      return convert_csinc_to_cset (inst);
3252
15.3k
    case OP_UBFX:
3253
30.2k
    case OP_BFXIL:
3254
61.6k
    case OP_SBFX:
3255
61.6k
      return convert_bfm_to_bfx (inst);
3256
18.4k
    case OP_SBFIZ:
3257
23.7k
    case OP_BFI:
3258
30.2k
    case OP_UBFIZ:
3259
30.2k
      return convert_bfm_to_bfi (inst);
3260
546
    case OP_BFC:
3261
546
      return convert_bfm_to_bfc (inst);
3262
467
    case OP_MOV_V:
3263
467
      return convert_orr_to_mov (inst);
3264
192k
    case OP_MOV_IMM_WIDE:
3265
243k
    case OP_MOV_IMM_WIDEN:
3266
243k
      return convert_movewide_to_mov (inst);
3267
2.04k
    case OP_MOV_IMM_LOG:
3268
2.04k
      return convert_movebitmask_to_mov (inst);
3269
9.15k
    case OP_ROR_IMM:
3270
9.15k
      return convert_extr_to_ror (inst);
3271
11
    case OP_SXTL:
3272
45
    case OP_SXTL2:
3273
280
    case OP_UXTL:
3274
283
    case OP_UXTL2:
3275
283
      return convert_shll_to_xtl (inst);
3276
0
    default:
3277
0
      return 0;
3278
436k
    }
3279
436k
}
3280
3281
static bool
3282
aarch64_opcode_decode (const aarch64_opcode *, const aarch64_insn,
3283
           aarch64_inst *, int, aarch64_operand_error *errors);
3284
3285
/* Given the instruction information in *INST, check if the instruction has
3286
   any alias form that can be used to represent *INST.  If the answer is yes,
3287
   update *INST to be in the form of the determined alias.  */
3288
3289
/* In the opcode description table, the following flags are used in opcode
3290
   entries to help establish the relations between the real and alias opcodes:
3291
3292
  F_ALIAS:  opcode is an alias
3293
  F_HAS_ALIAS:  opcode has alias(es)
3294
  F_P1
3295
  F_P2
3296
  F_P3:   Disassembly preference priority 1-3 (the larger the
3297
      higher).  If nothing is specified, it is the priority
3298
      0 by default, i.e. the lowest priority.
3299
3300
   Although the relation between the machine and the alias instructions are not
3301
   explicitly described, it can be easily determined from the base opcode
3302
   values, masks and the flags F_ALIAS and F_HAS_ALIAS in their opcode
3303
   description entries:
3304
3305
   The mask of an alias opcode must be equal to or a super-set (i.e. more
3306
   constrained) of that of the aliased opcode; so is the base opcode value.
3307
3308
   if (opcode_has_alias (real) && alias_opcode_p (opcode)
3309
       && (opcode->mask & real->mask) == real->mask
3310
       && (real->mask & opcode->opcode) == (real->mask & real->opcode))
3311
   then OPCODE is an alias of, and only of, the REAL instruction
3312
3313
   The alias relationship is forced flat-structured to keep related algorithm
3314
   simple; an opcode entry cannot be flagged with both F_ALIAS and F_HAS_ALIAS.
3315
3316
   During the disassembling, the decoding decision tree (in
3317
   opcodes/aarch64-dis-2.c) always returns an machine instruction opcode entry;
3318
   if the decoding of such a machine instruction succeeds (and -Mno-aliases is
3319
   not specified), the disassembler will check whether there is any alias
3320
   instruction exists for this real instruction.  If there is, the disassembler
3321
   will try to disassemble the 32-bit binary again using the alias's rule, or
3322
   try to convert the IR to the form of the alias.  In the case of the multiple
3323
   aliases, the aliases are tried one by one from the highest priority
3324
   (currently the flag F_P3) to the lowest priority (no priority flag), and the
3325
   first succeeds first adopted.
3326
3327
   You may ask why there is a need for the conversion of IR from one form to
3328
   another in handling certain aliases.  This is because on one hand it avoids
3329
   adding more operand code to handle unusual encoding/decoding; on other
3330
   hand, during the disassembling, the conversion is an effective approach to
3331
   check the condition of an alias (as an alias may be adopted only if certain
3332
   conditions are met).
3333
3334
   In order to speed up the alias opcode lookup, aarch64-gen has preprocessed
3335
   aarch64_opcode_table and generated aarch64_find_alias_opcode and
3336
   aarch64_find_next_alias_opcode (in opcodes/aarch64-dis-2.c) to help.  */
3337
3338
static void
3339
determine_disassembling_preference (struct aarch64_inst *inst,
3340
            aarch64_operand_error *errors)
3341
15.7M
{
3342
15.7M
  const aarch64_opcode *opcode;
3343
15.7M
  const aarch64_opcode *alias;
3344
3345
15.7M
  opcode = inst->opcode;
3346
3347
  /* This opcode does not have an alias, so use itself.  */
3348
15.7M
  if (!opcode_has_alias (opcode))
3349
13.5M
    return;
3350
3351
2.15M
  alias = aarch64_find_alias_opcode (opcode);
3352
2.15M
  assert (alias);
3353
3354
#ifdef DEBUG_AARCH64
3355
  if (debug_dump)
3356
    {
3357
      const aarch64_opcode *tmp = alias;
3358
      printf ("####   LIST    orderd: ");
3359
      while (tmp)
3360
  {
3361
    printf ("%s, ", tmp->name);
3362
    tmp = aarch64_find_next_alias_opcode (tmp);
3363
  }
3364
      printf ("\n");
3365
    }
3366
#endif /* DEBUG_AARCH64 */
3367
3368
4.14M
  for (; alias; alias = aarch64_find_next_alias_opcode (alias))
3369
4.14M
    {
3370
4.14M
      DEBUG_TRACE ("try %s", alias->name);
3371
4.14M
      assert (alias_opcode_p (alias) || opcode_has_alias (opcode));
3372
3373
      /* An alias can be a pseudo opcode which will never be used in the
3374
   disassembly, e.g. BIC logical immediate is such a pseudo opcode
3375
   aliasing AND.  */
3376
4.14M
      if (pseudo_opcode_p (alias))
3377
609k
  {
3378
609k
    DEBUG_TRACE ("skip pseudo %s", alias->name);
3379
609k
    continue;
3380
609k
  }
3381
3382
3.53M
      if ((inst->value & alias->mask) != alias->opcode)
3383
1.23M
  {
3384
1.23M
    DEBUG_TRACE ("skip %s as base opcode not match", alias->name);
3385
1.23M
    continue;
3386
1.23M
  }
3387
3388
2.30M
      if (!AARCH64_CPU_HAS_ALL_FEATURES (arch_variant, *alias->avariant))
3389
21
  {
3390
21
    DEBUG_TRACE ("skip %s: we're missing features", alias->name);
3391
21
    continue;
3392
21
  }
3393
3394
      /* No need to do any complicated transformation on operands, if the alias
3395
   opcode does not have any operand.  */
3396
2.30M
      if (aarch64_num_of_operands (alias) == 0 && alias->opcode == inst->value)
3397
351
  {
3398
351
    DEBUG_TRACE ("succeed with 0-operand opcode %s", alias->name);
3399
351
    aarch64_replace_opcode (inst, alias);
3400
351
    return;
3401
351
  }
3402
2.30M
      if (alias->flags & F_CONV)
3403
436k
  {
3404
436k
    aarch64_inst copy;
3405
436k
    memcpy (&copy, inst, sizeof (aarch64_inst));
3406
    /* ALIAS is the preference as long as the instruction can be
3407
       successfully converted to the form of ALIAS.  */
3408
436k
    if (convert_to_alias (&copy, alias) == 1)
3409
322k
      {
3410
322k
        aarch64_replace_opcode (&copy, alias);
3411
322k
        if (aarch64_match_operands_constraint (&copy, NULL) != 1)
3412
0
    {
3413
0
      DEBUG_TRACE ("FAILED with alias %s ", alias->name);
3414
0
    }
3415
322k
        else
3416
322k
    {
3417
322k
      DEBUG_TRACE ("succeed with %s via conversion", alias->name);
3418
322k
      memcpy (inst, &copy, sizeof (aarch64_inst));
3419
322k
    }
3420
322k
        return;
3421
322k
      }
3422
436k
  }
3423
1.86M
      else
3424
1.86M
  {
3425
    /* Directly decode the alias opcode.  */
3426
1.86M
    aarch64_inst temp;
3427
1.86M
    memset (&temp, '\0', sizeof (aarch64_inst));
3428
1.86M
    if (aarch64_opcode_decode (alias, inst->value, &temp, 1, errors) == 1)
3429
1.83M
      {
3430
1.83M
        DEBUG_TRACE ("succeed with %s via direct decoding", alias->name);
3431
1.83M
        memcpy (inst, &temp, sizeof (aarch64_inst));
3432
1.83M
        return;
3433
1.83M
      }
3434
1.86M
  }
3435
2.30M
    }
3436
2.15M
}
3437
3438
/* Some instructions (including all SVE ones) use the instruction class
3439
   to describe how a qualifiers_list index is represented in the instruction
3440
   encoding.  If INST is such an instruction, decode the appropriate fields
3441
   and fill in the operand qualifiers accordingly.  Return true if no
3442
   problems are found.  */
3443
3444
static bool
3445
aarch64_decode_variant_using_iclass (aarch64_inst *inst)
3446
19.1M
{
3447
19.1M
  int i, variant;
3448
3449
19.1M
  variant = 0;
3450
19.1M
  switch (inst->opcode->iclass)
3451
19.1M
    {
3452
61.6k
    case sme_mov:
3453
61.6k
      variant = extract_fields (inst->value, 0, 2, FLD_SME_Q, FLD_SME_size_22);
3454
61.6k
      if (variant >= 4 && variant < 7)
3455
7.28k
  return false;
3456
54.3k
      if (variant == 7)
3457
546
  variant = 4;
3458
54.3k
      break;
3459
3460
4.47k
    case sme_psel:
3461
4.47k
      i = extract_fields (inst->value, 0, 2, FLD_SME_tszh, FLD_SME_tszl);
3462
4.47k
      if (i == 0)
3463
1.04k
  return false;
3464
6.45k
      while ((i & 1) == 0)
3465
3.02k
  {
3466
3.02k
    i >>= 1;
3467
3.02k
    variant += 1;
3468
3.02k
  }
3469
3.43k
      break;
3470
3471
1.08k
    case sme_shift:
3472
1.08k
      i = extract_field (FLD_SVE_tszh, inst->value, 0);
3473
1.08k
      goto sve_shift;
3474
3475
143
    case sme_size_12_bh:
3476
143
      variant = extract_field (FLD_S, inst->value, 0);
3477
143
      if (variant > 1)
3478
0
  return false;
3479
143
      break;
3480
3481
1.36k
    case sme_size_12_bhs:
3482
1.36k
      variant = extract_field (FLD_SME_size_12, inst->value, 0);
3483
1.36k
      if (variant >= 3)
3484
55
  return false;
3485
1.30k
      break;
3486
3487
1.30k
    case sme_size_12_hs:
3488
127
      variant = extract_field (FLD_SME_size_12, inst->value, 0);
3489
127
      if (variant != 1 && variant != 2)
3490
109
  return false;
3491
18
      variant -= 1;
3492
18
      break;
3493
3494
115
    case sme_size_12_b:
3495
115
      variant = extract_field (FLD_SME_size_12, inst->value, 0);
3496
115
      if (variant != 0)
3497
97
  return false;
3498
18
      break;
3499
3500
7.04k
    case sme_size_22:
3501
7.04k
      variant = extract_field (FLD_SME_size_22, inst->value, 0);
3502
7.04k
      break;
3503
3504
1.85k
    case sme_size_22_hsd:
3505
1.85k
      variant = extract_field (FLD_SME_size_22, inst->value, 0);
3506
1.85k
      if (variant < 1)
3507
736
  return false;
3508
1.12k
      variant -= 1;
3509
1.12k
      break;
3510
3511
42
    case sme_sz_23:
3512
42
      variant = extract_field (FLD_SME_sz_23, inst->value, 0);
3513
42
      break;
3514
3515
49.5k
    case sve_cpy:
3516
49.5k
      variant = extract_fields (inst->value, 0, 2, FLD_size, FLD_SVE_M_14);
3517
49.5k
      break;
3518
3519
1.75k
    case sve_index:
3520
1.75k
      i = extract_field (FLD_imm5, inst->value, 0);
3521
3522
1.75k
      if ((i & 31) == 0)
3523
447
  return false;
3524
2.39k
      while ((i & 1) == 0)
3525
1.08k
  {
3526
1.08k
    i >>= 1;
3527
1.08k
    variant += 1;
3528
1.08k
  }
3529
1.30k
      break;
3530
3531
185k
    case sve_limm:
3532
      /* Pick the smallest applicable element size.  */
3533
185k
      if ((inst->value & 0x20600) == 0x600)
3534
25.0k
  variant = 0;
3535
160k
      else if ((inst->value & 0x20400) == 0x400)
3536
18.4k
  variant = 1;
3537
141k
      else if ((inst->value & 0x20000) == 0)
3538
121k
  variant = 2;
3539
20.6k
      else
3540
20.6k
  variant = 3;
3541
185k
      break;
3542
3543
84
    case sme2_mov:
3544
      /* .D is preferred over the other sizes in disassembly.  */
3545
84
      variant = 3;
3546
84
      break;
3547
3548
980
    case sme2_movaz:
3549
206k
    case sme_misc:
3550
944k
    case sve_misc:
3551
      /* These instructions have only a single variant.  */
3552
944k
      break;
3553
3554
2.18k
    case sve_movprfx:
3555
2.18k
      variant = extract_fields (inst->value, 0, 2, FLD_size, FLD_SVE_M_16);
3556
2.18k
      break;
3557
3558
161
    case sve_pred_zm:
3559
161
      variant = extract_field (FLD_SVE_M_4, inst->value, 0);
3560
161
      break;
3561
3562
8.73k
    case sve_shift_pred:
3563
8.73k
      i = extract_fields (inst->value, 0, 2, FLD_SVE_tszh, FLD_SVE_tszl_8);
3564
11.0k
    sve_shift:
3565
11.0k
      if (i == 0)
3566
2.14k
  return false;
3567
26.5k
      while (i != 1)
3568
17.6k
  {
3569
17.6k
    i >>= 1;
3570
17.6k
    variant += 1;
3571
17.6k
  }
3572
8.95k
      break;
3573
3574
1.28k
    case sve_shift_unpred:
3575
1.28k
      i = extract_fields (inst->value, 0, 2, FLD_SVE_tszh, FLD_SVE_tszl_19);
3576
1.28k
      goto sve_shift;
3577
3578
32.6k
    case sve_size_bhs:
3579
32.6k
      variant = extract_field (FLD_size, inst->value, 0);
3580
32.6k
      if (variant >= 3)
3581
5.59k
  return false;
3582
27.0k
      break;
3583
3584
340k
    case sve_size_bhsd:
3585
340k
      variant = extract_field (FLD_size, inst->value, 0);
3586
340k
      break;
3587
3588
368k
    case sve_size_hsd:
3589
368k
      i = extract_field (FLD_size, inst->value, 0);
3590
368k
      if (i < 1)
3591
90.8k
  return false;
3592
277k
      variant = i - 1;
3593
277k
      break;
3594
3595
586
    case sme_fp_sd:
3596
9.69k
    case sme_int_sd:
3597
11.8k
    case sve_size_bh:
3598
19.0k
    case sve_size_sd:
3599
19.0k
      variant = extract_field (FLD_SVE_sz, inst->value, 0);
3600
19.0k
      break;
3601
3602
14.6k
    case sve_size_sd2:
3603
14.6k
      variant = extract_field (FLD_SVE_sz2, inst->value, 0);
3604
14.6k
      break;
3605
3606
120
    case sve_size_hsd2:
3607
120
      i = extract_field (FLD_SVE_size, inst->value, 0);
3608
120
      if (i < 1)
3609
45
  return false;
3610
75
      variant = i - 1;
3611
75
      break;
3612
3613
2.54k
    case sve_size_13:
3614
      /* Ignore low bit of this field since that is set in the opcode for
3615
   instructions of this iclass.  */
3616
2.54k
      i = (extract_field (FLD_size, inst->value, 0) & 2);
3617
2.54k
      variant = (i >> 1);
3618
2.54k
      break;
3619
3620
4.01k
    case sve_shift_tsz_bhsd:
3621
4.01k
      i = extract_fields (inst->value, 0, 2, FLD_SVE_tszh, FLD_SVE_tszl_19);
3622
4.01k
      if (i == 0)
3623
1.88k
  return false;
3624
7.12k
      while (i != 1)
3625
4.99k
  {
3626
4.99k
    i >>= 1;
3627
4.99k
    variant += 1;
3628
4.99k
  }
3629
2.13k
      break;
3630
3631
931
    case sve_size_tsz_bhs:
3632
931
      i = extract_fields (inst->value, 0, 2, FLD_SVE_sz, FLD_SVE_tszl_19);
3633
931
      if (i == 0)
3634
168
  return false;
3635
1.06k
      while (i != 1)
3636
633
  {
3637
633
    if (i & 1)
3638
335
      return false;
3639
298
    i >>= 1;
3640
298
    variant += 1;
3641
298
  }
3642
428
      break;
3643
3644
9.32k
    case sve_shift_tsz_hsd:
3645
9.32k
      i = extract_fields (inst->value, 0, 2, FLD_SVE_sz, FLD_SVE_tszl_19);
3646
9.32k
      if (i == 0)
3647
2.21k
  return false;
3648
17.6k
      while (i != 1)
3649
10.5k
  {
3650
10.5k
    i >>= 1;
3651
10.5k
    variant += 1;
3652
10.5k
  }
3653
7.11k
      break;
3654
3655
17.0M
    default:
3656
      /* No mapping between instruction class and qualifiers.  */
3657
17.0M
      return true;
3658
19.1M
    }
3659
3660
15.6M
  for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
3661
13.6M
    inst->operands[i].qualifier = inst->opcode->qualifiers_list[variant][i];
3662
1.95M
  return true;
3663
19.1M
}
3664
/* Decode the CODE according to OPCODE; fill INST.  Return 0 if the decoding
3665
   fails, which meanes that CODE is not an instruction of OPCODE; otherwise
3666
   return 1.
3667
3668
   If OPCODE has alias(es) and NOALIASES_P is 0, an alias opcode may be
3669
   determined and used to disassemble CODE; this is done just before the
3670
   return.  */
3671
3672
static bool
3673
aarch64_opcode_decode (const aarch64_opcode *opcode, const aarch64_insn code,
3674
           aarch64_inst *inst, int noaliases_p,
3675
           aarch64_operand_error *errors)
3676
41.8M
{
3677
41.8M
  int i;
3678
3679
41.8M
  DEBUG_TRACE ("enter with %s", opcode->name);
3680
3681
41.8M
  assert (opcode && inst);
3682
3683
  /* Clear inst.  */
3684
41.8M
  memset (inst, '\0', sizeof (aarch64_inst));
3685
3686
  /* Check the base opcode.  */
3687
41.8M
  if ((code & opcode->mask) != (opcode->opcode & opcode->mask))
3688
22.4M
    {
3689
22.4M
      DEBUG_TRACE ("base opcode match FAIL");
3690
22.4M
      goto decode_fail;
3691
22.4M
    }
3692
3693
19.3M
  inst->opcode = opcode;
3694
19.3M
  inst->value = code;
3695
3696
  /* Assign operand codes and indexes.  */
3697
63.7M
  for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
3698
63.7M
    {
3699
63.7M
      if (opcode->operands[i] == AARCH64_OPND_NIL)
3700
19.3M
  break;
3701
44.3M
      inst->operands[i].type = opcode->operands[i];
3702
44.3M
      inst->operands[i].idx = i;
3703
44.3M
    }
3704
3705
  /* Call the opcode decoder indicated by flags.  */
3706
19.3M
  if (opcode_has_special_coder (opcode) && do_special_decoding (inst) == 0)
3707
276k
    {
3708
276k
      DEBUG_TRACE ("opcode flag-based decoder FAIL");
3709
276k
      goto decode_fail;
3710
276k
    }
3711
3712
  /* Possibly use the instruction class to determine the correct
3713
     qualifier.  */
3714
19.1M
  if (!aarch64_decode_variant_using_iclass (inst))
3715
112k
    {
3716
112k
      DEBUG_TRACE ("iclass-based decoder FAIL");
3717
112k
      goto decode_fail;
3718
112k
    }
3719
3720
  /* Call operand decoders.  */
3721
60.2M
  for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
3722
60.2M
    {
3723
60.2M
      const aarch64_operand *opnd;
3724
60.2M
      enum aarch64_opnd type;
3725
3726
60.2M
      type = opcode->operands[i];
3727
60.2M
      if (type == AARCH64_OPND_NIL)
3728
17.9M
  break;
3729
42.2M
      opnd = &aarch64_operands[type];
3730
42.2M
      if (operand_has_extractor (opnd)
3731
42.2M
    && (! aarch64_extract_operand (opnd, &inst->operands[i], code, inst,
3732
42.2M
           errors)))
3733
1.01M
  {
3734
1.01M
    DEBUG_TRACE ("operand decoder FAIL at operand %d", i);
3735
1.01M
    goto decode_fail;
3736
1.01M
  }
3737
42.2M
    }
3738
3739
  /* If the opcode has a verifier, then check it now.  */
3740
17.9M
  if (opcode->verifier
3741
17.9M
      && opcode->verifier (inst, code, 0, false, errors, NULL) != ERR_OK)
3742
9.36k
    {
3743
9.36k
      DEBUG_TRACE ("operand verifier FAIL");
3744
9.36k
      goto decode_fail;
3745
9.36k
    }
3746
3747
  /* Match the qualifiers.  */
3748
17.9M
  if (aarch64_match_operands_constraint (inst, NULL) == 1)
3749
17.5M
    {
3750
      /* Arriving here, the CODE has been determined as a valid instruction
3751
   of OPCODE and *INST has been filled with information of this OPCODE
3752
   instruction.  Before the return, check if the instruction has any
3753
   alias and should be disassembled in the form of its alias instead.
3754
   If the answer is yes, *INST will be updated.  */
3755
17.5M
      if (!noaliases_p)
3756
15.7M
  determine_disassembling_preference (inst, errors);
3757
17.5M
      DEBUG_TRACE ("SUCCESS");
3758
17.5M
      return true;
3759
17.5M
    }
3760
413k
  else
3761
413k
    {
3762
413k
      DEBUG_TRACE ("constraint matching FAIL");
3763
413k
    }
3764
3765
24.3M
 decode_fail:
3766
24.3M
  return false;
3767
17.9M
}
3768

3769
/* This does some user-friendly fix-up to *INST.  It is currently focus on
3770
   the adjustment of qualifiers to help the printed instruction
3771
   recognized/understood more easily.  */
3772
3773
static void
3774
user_friendly_fixup (aarch64_inst *inst)
3775
15.7M
{
3776
15.7M
  switch (inst->opcode->iclass)
3777
15.7M
    {
3778
300k
    case testbranch:
3779
      /* TBNZ Xn|Wn, #uimm6, label
3780
   Test and Branch Not Zero: conditionally jumps to label if bit number
3781
   uimm6 in register Xn is not zero.  The bit number implies the width of
3782
   the register, which may be written and should be disassembled as Wn if
3783
   uimm is less than 32. Limited to a branch offset range of +/- 32KiB.
3784
   */
3785
300k
      if (inst->operands[1].imm.value < 32)
3786
188k
  inst->operands[0].qualifier = AARCH64_OPND_QLF_W;
3787
300k
      break;
3788
15.4M
    default: break;
3789
15.7M
    }
3790
15.7M
}
3791
3792
/* Decode INSN and fill in *INST the instruction information.  An alias
3793
   opcode may be filled in *INSN if NOALIASES_P is FALSE.  Return zero on
3794
   success.  */
3795
3796
enum err_type
3797
aarch64_decode_insn (aarch64_insn insn, aarch64_inst *inst,
3798
         bool noaliases_p,
3799
         aarch64_operand_error *errors)
3800
35.1M
{
3801
35.1M
  const aarch64_opcode *opcode = aarch64_opcode_lookup (insn);
3802
3803
#ifdef DEBUG_AARCH64
3804
  if (debug_dump)
3805
    {
3806
      const aarch64_opcode *tmp = opcode;
3807
      printf ("\n");
3808
      DEBUG_TRACE ("opcode lookup:");
3809
      while (tmp != NULL)
3810
  {
3811
    aarch64_verbose ("  %s", tmp->name);
3812
    tmp = aarch64_find_next_opcode (tmp);
3813
  }
3814
    }
3815
#endif /* DEBUG_AARCH64 */
3816
3817
  /* A list of opcodes may have been found, as aarch64_opcode_lookup cannot
3818
     distinguish some opcodes, e.g. SSHR and MOVI, which almost share the same
3819
     opcode field and value, apart from the difference that one of them has an
3820
     extra field as part of the opcode, but such a field is used for operand
3821
     encoding in other opcode(s) ('immh' in the case of the example).  */
3822
59.4M
  while (opcode != NULL)
3823
40.0M
    {
3824
      /* But only one opcode can be decoded successfully for, as the
3825
   decoding routine will check the constraint carefully.  */
3826
40.0M
      if (aarch64_opcode_decode (opcode, insn, inst, noaliases_p, errors) == 1)
3827
15.7M
  return ERR_OK;
3828
24.2M
      opcode = aarch64_find_next_opcode (opcode);
3829
24.2M
    }
3830
3831
19.3M
  return ERR_UND;
3832
35.1M
}
3833
3834
/* Return a short string to indicate a switch to STYLE.  These strings
3835
   will be embedded into the disassembled operand text (as produced by
3836
   aarch64_print_operand), and then spotted in the print_operands function
3837
   so that the disassembler output can be split by style.  */
3838
3839
static const char *
3840
get_style_text (enum disassembler_style style)
3841
79.2M
{
3842
79.2M
  static bool init = false;
3843
79.2M
  static char formats[16][4];
3844
79.2M
  unsigned num;
3845
3846
  /* First time through we build a string for every possible format.  This
3847
     code relies on there being no more than 16 different styles (there's
3848
     an assert below for this).  */
3849
79.2M
  if (!init)
3850
2
    {
3851
2
      int i;
3852
3853
34
      for (i = 0; i <= 0xf; ++i)
3854
32
  {
3855
32
    int res ATTRIBUTE_UNUSED
3856
32
      = snprintf (&formats[i][0], sizeof (formats[i]), "%c%x%c",
3857
32
      STYLE_MARKER_CHAR, i, STYLE_MARKER_CHAR);
3858
32
    assert (res == 3);
3859
32
  }
3860
3861
2
      init = true;
3862
2
    }
3863
3864
  /* Return the string that marks switching to STYLE.  */
3865
79.2M
  num = (unsigned) style;
3866
79.2M
  assert (style <= 0xf);
3867
79.2M
  return formats[num];
3868
79.2M
}
3869
3870
/* Callback used by aarch64_print_operand to apply STYLE to the
3871
   disassembler output created from FMT and ARGS.  The STYLER object holds
3872
   any required state.  Must return a pointer to a string (created from FMT
3873
   and ARGS) that will continue to be valid until the complete disassembled
3874
   instruction has been printed.
3875
3876
   We return a string that includes two embedded style markers, the first,
3877
   places at the start of the string, indicates a switch to STYLE, and the
3878
   second, placed at the end of the string, indicates a switch back to the
3879
   default text style.
3880
3881
   Later, when we print the operand text we take care to collapse any
3882
   adjacent style markers, and to ignore any style markers that appear at
3883
   the very end of a complete operand string.  */
3884
3885
static const char *aarch64_apply_style (struct aarch64_styler *styler,
3886
          enum disassembler_style style,
3887
          const char *fmt,
3888
          va_list args)
3889
39.6M
{
3890
39.6M
  int res;
3891
39.6M
  char *ptr, *tmp;
3892
39.6M
  struct obstack *stack = (struct obstack *) styler->state;
3893
39.6M
  va_list ap;
3894
3895
  /* These are the two strings for switching styles.  */
3896
39.6M
  const char *style_on = get_style_text (style);
3897
39.6M
  const char *style_off = get_style_text (dis_style_text);
3898
3899
  /* Calculate space needed once FMT and ARGS are expanded.  */
3900
39.6M
  va_copy (ap, args);
3901
39.6M
  res = vsnprintf (NULL, 0, fmt, ap);
3902
39.6M
  va_end (ap);
3903
39.6M
  assert (res >= 0);
3904
3905
  /* Allocate space on the obstack for the expanded FMT and ARGS, as well
3906
     as the two strings for switching styles, then write all of these
3907
     strings onto the obstack.  */
3908
39.6M
  ptr = (char *) obstack_alloc (stack, res + strlen (style_on)
3909
39.6M
        + strlen (style_off) + 1);
3910
39.6M
  tmp = stpcpy (ptr, style_on);
3911
39.6M
  res = vsnprintf (tmp, (res + 1), fmt, args);
3912
39.6M
  assert (res >= 0);
3913
39.6M
  tmp += res;
3914
39.6M
  strcpy (tmp, style_off);
3915
3916
39.6M
  return ptr;
3917
39.6M
}
3918
3919
/* Print operands.  */
3920
3921
static void
3922
print_operands (bfd_vma pc, const aarch64_opcode *opcode,
3923
    const aarch64_opnd_info *opnds, struct disassemble_info *info,
3924
    bool *has_notes)
3925
15.7M
{
3926
15.7M
  char *notes = NULL;
3927
15.7M
  int i, pcrel_p, num_printed;
3928
15.7M
  struct aarch64_styler styler;
3929
15.7M
  struct obstack content;
3930
15.7M
  obstack_init (&content);
3931
3932
15.7M
  styler.apply_style = aarch64_apply_style;
3933
15.7M
  styler.state = (void *) &content;
3934
3935
48.9M
  for (i = 0, num_printed = 0; i < AARCH64_MAX_OPND_NUM; ++i)
3936
48.9M
    {
3937
48.9M
      char str[128];
3938
48.9M
      char cmt[128];
3939
3940
      /* We regard the opcode operand info more, however we also look into
3941
   the inst->operands to support the disassembling of the optional
3942
   operand.
3943
   The two operand code should be the same in all cases, apart from
3944
   when the operand can be optional.  */
3945
48.9M
      if (opcode->operands[i] == AARCH64_OPND_NIL
3946
48.9M
    || opnds[i].type == AARCH64_OPND_NIL)
3947
15.7M
  break;
3948
3949
      /* Generate the operand string in STR.  */
3950
33.2M
      aarch64_print_operand (str, sizeof (str), pc, opcode, opnds, i, &pcrel_p,
3951
33.2M
           &info->target, &notes, cmt, sizeof (cmt),
3952
33.2M
           arch_variant, &styler);
3953
3954
      /* Print the delimiter (taking account of omitted operand(s)).  */
3955
33.2M
      if (str[0] != '\0')
3956
33.1M
  (*info->fprintf_styled_func) (info->stream, dis_style_text, "%s",
3957
33.1M
              num_printed++ == 0 ? "\t" : ", ");
3958
3959
      /* Print the operand.  */
3960
33.2M
      if (pcrel_p)
3961
3.25M
  (*info->print_address_func) (info->target, info);
3962
29.9M
      else
3963
29.9M
  {
3964
    /* This operand came from aarch64_print_operand, and will include
3965
       embedded strings indicating which style each character should
3966
       have.  In the following code we split the text based on
3967
       CURR_STYLE, and call the styled print callback to print each
3968
       block of text in the appropriate style.  */
3969
29.9M
    char *start, *curr;
3970
29.9M
    enum disassembler_style curr_style = dis_style_text;
3971
3972
29.9M
    start = curr = str;
3973
29.9M
    do
3974
248M
      {
3975
248M
        if (*curr == '\0'
3976
248M
      || (*curr == STYLE_MARKER_CHAR
3977
218M
          && ISXDIGIT (*(curr + 1))
3978
218M
          && *(curr + 2) == STYLE_MARKER_CHAR))
3979
102M
    {
3980
      /* Output content between our START position and CURR.  */
3981
102M
      int len = curr - start;
3982
102M
      if (len > 0)
3983
52.1M
        {
3984
52.1M
          if ((*info->fprintf_styled_func) (info->stream,
3985
52.1M
              curr_style,
3986
52.1M
              "%.*s",
3987
52.1M
              len, start) < 0)
3988
0
      break;
3989
52.1M
        }
3990
3991
102M
      if (*curr == '\0')
3992
29.9M
        break;
3993
3994
      /* Skip over the initial STYLE_MARKER_CHAR.  */
3995
72.7M
      ++curr;
3996
3997
      /* Update the CURR_STYLE.  As there are less than 16
3998
         styles, it is possible, that if the input is corrupted
3999
         in some way, that we might set CURR_STYLE to an
4000
         invalid value.  Don't worry though, we check for this
4001
         situation.  */
4002
72.7M
      if (*curr >= '0' && *curr <= '9')
4003
72.7M
        curr_style = (enum disassembler_style) (*curr - '0');
4004
0
      else if (*curr >= 'a' && *curr <= 'f')
4005
0
        curr_style = (enum disassembler_style) (*curr - 'a' + 10);
4006
0
      else
4007
0
        curr_style = dis_style_text;
4008
4009
      /* Check for an invalid style having been selected.  This
4010
         should never happen, but it doesn't hurt to be a
4011
         little paranoid.  */
4012
72.7M
      if (curr_style > dis_style_comment_start)
4013
0
        curr_style = dis_style_text;
4014
4015
      /* Skip the hex character, and the closing STYLE_MARKER_CHAR.  */
4016
72.7M
      curr += 2;
4017
4018
      /* Reset the START to after the style marker.  */
4019
72.7M
      start = curr;
4020
72.7M
    }
4021
145M
        else
4022
145M
    ++curr;
4023
248M
      }
4024
29.9M
    while (true);
4025
29.9M
  }
4026
4027
      /* Print the comment.  This works because only the last operand ever
4028
   adds a comment.  If that ever changes then we'll need to be
4029
   smarter here.  */
4030
33.2M
      if (cmt[0] != '\0')
4031
276k
  (*info->fprintf_styled_func) (info->stream, dis_style_comment_start,
4032
276k
              "\t// %s", cmt);
4033
33.2M
    }
4034
4035
15.7M
    if (notes && !no_notes)
4036
0
      {
4037
0
  *has_notes = true;
4038
0
  (*info->fprintf_styled_func) (info->stream, dis_style_comment_start,
4039
0
              "  // note: %s", notes);
4040
0
      }
4041
4042
15.7M
    obstack_free (&content, NULL);
4043
15.7M
}
4044
4045
/* Set NAME to a copy of INST's mnemonic with the "." suffix removed.  */
4046
4047
static void
4048
remove_dot_suffix (char *name, const aarch64_inst *inst)
4049
358k
{
4050
358k
  char *ptr;
4051
358k
  size_t len;
4052
4053
358k
  ptr = strchr (inst->opcode->name, '.');
4054
358k
  assert (ptr && inst->cond);
4055
358k
  len = ptr - inst->opcode->name;
4056
358k
  assert (len < 8);
4057
358k
  strncpy (name, inst->opcode->name, len);
4058
358k
  name[len] = '\0';
4059
358k
}
4060
4061
/* Print the instruction mnemonic name.  */
4062
4063
static void
4064
print_mnemonic_name (const aarch64_inst *inst, struct disassemble_info *info)
4065
15.7M
{
4066
15.7M
  if (inst->opcode->flags & F_COND)
4067
179k
    {
4068
      /* For instructions that are truly conditionally executed, e.g. b.cond,
4069
   prepare the full mnemonic name with the corresponding condition
4070
   suffix.  */
4071
179k
      char name[8];
4072
4073
179k
      remove_dot_suffix (name, inst);
4074
179k
      (*info->fprintf_styled_func) (info->stream, dis_style_mnemonic,
4075
179k
            "%s.%s", name, inst->cond->names[0]);
4076
179k
    }
4077
15.5M
  else
4078
15.5M
    (*info->fprintf_styled_func) (info->stream, dis_style_mnemonic,
4079
15.5M
          "%s", inst->opcode->name);
4080
15.7M
}
4081
4082
/* Decide whether we need to print a comment after the operands of
4083
   instruction INST.  */
4084
4085
static void
4086
print_comment (const aarch64_inst *inst, struct disassemble_info *info)
4087
15.7M
{
4088
15.7M
  if (inst->opcode->flags & F_COND)
4089
179k
    {
4090
179k
      char name[8];
4091
179k
      unsigned int i, num_conds;
4092
4093
179k
      remove_dot_suffix (name, inst);
4094
179k
      num_conds = ARRAY_SIZE (inst->cond->names);
4095
337k
      for (i = 1; i < num_conds && inst->cond->names[i]; ++i)
4096
158k
  (*info->fprintf_styled_func) (info->stream, dis_style_comment_start,
4097
158k
              "%s %s.%s",
4098
158k
              i == 1 ? "  //" : ",",
4099
158k
              name, inst->cond->names[i]);
4100
179k
    }
4101
15.7M
}
4102
4103
/* Build notes from verifiers into a string for printing.  */
4104
4105
static void
4106
print_verifier_notes (aarch64_operand_error *detail,
4107
          struct disassemble_info *info)
4108
11.6k
{
4109
11.6k
  if (no_notes)
4110
11.6k
    return;
4111
4112
  /* The output of the verifier cannot be a fatal error, otherwise the assembly
4113
     would not have succeeded.  We can safely ignore these.  */
4114
0
  assert (detail->non_fatal);
4115
4116
0
  (*info->fprintf_styled_func) (info->stream, dis_style_comment_start,
4117
0
        "  // note: ");
4118
0
  switch (detail->kind)
4119
0
    {
4120
0
    case AARCH64_OPDE_A_SHOULD_FOLLOW_B:
4121
0
      (*info->fprintf_styled_func) (info->stream, dis_style_text,
4122
0
            _("this `%s' should have an immediately"
4123
0
              " preceding `%s'"),
4124
0
            detail->data[0].s, detail->data[1].s);
4125
0
      break;
4126
4127
0
    case AARCH64_OPDE_EXPECTED_A_AFTER_B:
4128
0
      (*info->fprintf_styled_func) (info->stream, dis_style_text,
4129
0
            _("expected `%s' after previous `%s'"),
4130
0
            detail->data[0].s, detail->data[1].s);
4131
0
      break;
4132
4133
0
    default:
4134
0
      assert (detail->error);
4135
0
      (*info->fprintf_styled_func) (info->stream, dis_style_text,
4136
0
            "%s", detail->error);
4137
0
      if (detail->index >= 0)
4138
0
  (*info->fprintf_styled_func) (info->stream, dis_style_text,
4139
0
              " at operand %d", detail->index + 1);
4140
0
      break;
4141
0
    }
4142
0
}
4143
4144
/* Print the instruction according to *INST.  */
4145
4146
static void
4147
print_aarch64_insn (bfd_vma pc, const aarch64_inst *inst,
4148
        const aarch64_insn code,
4149
        struct disassemble_info *info,
4150
        aarch64_operand_error *mismatch_details)
4151
15.7M
{
4152
15.7M
  bool has_notes = false;
4153
4154
15.7M
  print_mnemonic_name (inst, info);
4155
15.7M
  print_operands (pc, inst->opcode, inst->operands, info, &has_notes);
4156
15.7M
  print_comment (inst, info);
4157
4158
  /* We've already printed a note, not enough space to print more so exit.
4159
     Usually notes shouldn't overlap so it shouldn't happen that we have a note
4160
     from a register and instruction at the same time.  */
4161
15.7M
  if (has_notes)
4162
0
    return;
4163
4164
  /* Always run constraint verifiers, this is needed because constraints need to
4165
     maintain a global state regardless of whether the instruction has the flag
4166
     set or not.  */
4167
15.7M
  enum err_type result = verify_constraints (inst, code, pc, false,
4168
15.7M
               mismatch_details, &insn_sequence);
4169
15.7M
  switch (result)
4170
15.7M
    {
4171
11.6k
    case ERR_VFI:
4172
11.6k
      print_verifier_notes (mismatch_details, info);
4173
11.6k
      break;
4174
0
    case ERR_UND:
4175
0
    case ERR_UNP:
4176
0
    case ERR_NYI:
4177
15.7M
    default:
4178
15.7M
      break;
4179
15.7M
    }
4180
15.7M
}
4181
4182
/* Entry-point of the instruction disassembler and printer.  */
4183
4184
static void
4185
print_insn_aarch64_word (bfd_vma pc,
4186
       uint32_t word,
4187
       struct disassemble_info *info,
4188
       aarch64_operand_error *errors)
4189
35.1M
{
4190
35.1M
  static const char *err_msg[ERR_NR_ENTRIES+1] =
4191
35.1M
    {
4192
35.1M
      [ERR_OK]  = "_",
4193
35.1M
      [ERR_UND] = "undefined",
4194
35.1M
      [ERR_UNP] = "unpredictable",
4195
35.1M
      [ERR_NYI] = "NYI"
4196
35.1M
    };
4197
4198
35.1M
  enum err_type ret;
4199
35.1M
  aarch64_inst inst;
4200
4201
35.1M
  info->insn_info_valid = 1;
4202
35.1M
  info->branch_delay_insns = 0;
4203
35.1M
  info->data_size = 0;
4204
35.1M
  info->target = 0;
4205
35.1M
  info->target2 = 0;
4206
4207
35.1M
  if (info->flags & INSN_HAS_RELOC)
4208
    /* If the instruction has a reloc associated with it, then
4209
       the offset field in the instruction will actually be the
4210
       addend for the reloc.  (If we are using REL type relocs).
4211
       In such cases, we can ignore the pc when computing
4212
       addresses, since the addend is not currently pc-relative.  */
4213
0
    pc = 0;
4214
4215
35.1M
  ret = aarch64_decode_insn (word, &inst, no_aliases, errors);
4216
4217
35.1M
  if (((word >> 21) & 0x3ff) == 1)
4218
268k
    {
4219
      /* RESERVED for ALES.  */
4220
268k
      assert (ret != ERR_OK);
4221
268k
      ret = ERR_NYI;
4222
268k
    }
4223
4224
35.1M
  switch (ret)
4225
35.1M
    {
4226
19.1M
    case ERR_UND:
4227
19.1M
    case ERR_UNP:
4228
19.3M
    case ERR_NYI:
4229
      /* Handle undefined instructions.  */
4230
19.3M
      info->insn_type = dis_noninsn;
4231
19.3M
      (*info->fprintf_styled_func) (info->stream,
4232
19.3M
            dis_style_assembler_directive,
4233
19.3M
            ".inst\t");
4234
19.3M
      (*info->fprintf_styled_func) (info->stream, dis_style_immediate,
4235
19.3M
            "0x%08x", word);
4236
19.3M
      (*info->fprintf_styled_func) (info->stream, dis_style_comment_start,
4237
19.3M
            " ; %s", err_msg[ret]);
4238
19.3M
      break;
4239
15.7M
    case ERR_OK:
4240
15.7M
      user_friendly_fixup (&inst);
4241
15.7M
      if (inst.opcode->iclass == condbranch
4242
15.7M
    || inst.opcode->iclass == testbranch
4243
15.7M
    || inst.opcode->iclass == compbranch)
4244
1.01M
        info->insn_type = dis_condbranch;
4245
14.7M
      else if (inst.opcode->iclass == branch_imm)
4246
761k
        info->insn_type = dis_jsr;
4247
15.7M
      print_aarch64_insn (pc, &inst, word, info, errors);
4248
15.7M
      break;
4249
0
    default:
4250
0
      abort ();
4251
35.1M
    }
4252
35.1M
}
4253
4254
/* Disallow mapping symbols ($x, $d etc) from
4255
   being displayed in symbol relative addresses.  */
4256
4257
bool
4258
aarch64_symbol_is_valid (asymbol * sym,
4259
       struct disassemble_info * info ATTRIBUTE_UNUSED)
4260
554k
{
4261
554k
  const char * name;
4262
4263
554k
  if (sym == NULL)
4264
0
    return false;
4265
4266
554k
  name = bfd_asymbol_name (sym);
4267
4268
554k
  return name
4269
554k
    && (name[0] != '$'
4270
554k
  || (name[1] != 'x' && name[1] != 'd')
4271
554k
  || (name[2] != '\0' && name[2] != '.'));
4272
554k
}
4273
4274
/* Print data bytes on INFO->STREAM.  */
4275
4276
static void
4277
print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED,
4278
     uint32_t word,
4279
     struct disassemble_info *info,
4280
     aarch64_operand_error *errors ATTRIBUTE_UNUSED)
4281
0
{
4282
0
  switch (info->bytes_per_chunk)
4283
0
    {
4284
0
    case 1:
4285
0
      info->fprintf_styled_func (info->stream, dis_style_assembler_directive,
4286
0
         ".byte\t");
4287
0
      info->fprintf_styled_func (info->stream, dis_style_immediate,
4288
0
         "0x%02x", word);
4289
0
      break;
4290
0
    case 2:
4291
0
      info->fprintf_styled_func (info->stream, dis_style_assembler_directive,
4292
0
         ".short\t");
4293
0
      info->fprintf_styled_func (info->stream, dis_style_immediate,
4294
0
         "0x%04x", word);
4295
0
      break;
4296
0
    case 4:
4297
0
      info->fprintf_styled_func (info->stream, dis_style_assembler_directive,
4298
0
         ".word\t");
4299
0
      info->fprintf_styled_func (info->stream, dis_style_immediate,
4300
0
         "0x%08x", word);
4301
0
      break;
4302
0
    default:
4303
0
      abort ();
4304
0
    }
4305
0
}
4306
4307
/* Try to infer the code or data type from a symbol.
4308
   Returns nonzero if *MAP_TYPE was set.  */
4309
4310
static int
4311
get_sym_code_type (struct disassemble_info *info, int n,
4312
       enum map_type *map_type)
4313
46.6M
{
4314
46.6M
  asymbol * as;
4315
46.6M
  elf_symbol_type *es;
4316
46.6M
  unsigned int type;
4317
46.6M
  const char *name;
4318
4319
  /* If the symbol is in a different section, ignore it.  */
4320
46.6M
  if (info->section != NULL && info->section != info->symtab[n]->section)
4321
12.9M
    return false;
4322
4323
33.6M
  if (n >= info->symtab_size)
4324
0
    return false;
4325
4326
33.6M
  as = info->symtab[n];
4327
33.6M
  if (bfd_asymbol_flavour (as) != bfd_target_elf_flavour)
4328
1.14M
    return false;
4329
32.5M
  es = (elf_symbol_type *) as;
4330
4331
32.5M
  type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
4332
4333
  /* If the symbol has function type then use that.  */
4334
32.5M
  if (type == STT_FUNC)
4335
1.97M
    {
4336
1.97M
      *map_type = MAP_INSN;
4337
1.97M
      return true;
4338
1.97M
    }
4339
4340
  /* Check for mapping symbols.  */
4341
30.5M
  name = bfd_asymbol_name(info->symtab[n]);
4342
30.5M
  if (name[0] == '$'
4343
30.5M
      && (name[1] == 'x' || name[1] == 'd')
4344
30.5M
      && (name[2] == '\0' || name[2] == '.'))
4345
0
    {
4346
0
      *map_type = (name[1] == 'x' ? MAP_INSN : MAP_DATA);
4347
0
      return true;
4348
0
    }
4349
4350
30.5M
  return false;
4351
30.5M
}
4352
4353
/* Set the feature bits in arch_variant in order to get the correct disassembly
4354
   for the chosen architecture variant.
4355
4356
   Currently we only restrict disassembly for Armv8-R and otherwise enable all
4357
   non-R-profile features.  */
4358
static void
4359
select_aarch64_variant (unsigned mach)
4360
2
{
4361
2
  switch (mach)
4362
2
    {
4363
0
    case bfd_mach_aarch64_8R:
4364
0
      AARCH64_SET_FEATURE (arch_variant, AARCH64_ARCH_V8R);
4365
0
      break;
4366
2
    default:
4367
2
      arch_variant = (aarch64_feature_set) AARCH64_ALL_FEATURES;
4368
2
      AARCH64_CLEAR_FEATURE (arch_variant, arch_variant, V8R);
4369
2
    }
4370
2
}
4371
4372
/* Entry-point of the AArch64 disassembler.  */
4373
4374
int
4375
print_insn_aarch64 (bfd_vma pc,
4376
        struct disassemble_info *info)
4377
35.1M
{
4378
35.1M
  bfd_byte  buffer[INSNLEN];
4379
35.1M
  int   status;
4380
35.1M
  void    (*printer) (bfd_vma, uint32_t, struct disassemble_info *,
4381
35.1M
          aarch64_operand_error *);
4382
35.1M
  bool   found = false;
4383
35.1M
  unsigned int  size = 4;
4384
35.1M
  unsigned long data;
4385
35.1M
  aarch64_operand_error errors;
4386
35.1M
  static bool set_features;
4387
4388
35.1M
  if (info->disassembler_options)
4389
0
    {
4390
0
      set_default_aarch64_dis_options (info);
4391
4392
0
      parse_aarch64_dis_options (info->disassembler_options);
4393
4394
      /* To avoid repeated parsing of these options, we remove them here.  */
4395
0
      info->disassembler_options = NULL;
4396
0
    }
4397
4398
35.1M
  if (!set_features)
4399
2
    {
4400
2
      select_aarch64_variant (info->mach);
4401
2
      set_features = true;
4402
2
    }
4403
4404
  /* Aarch64 instructions are always little-endian */
4405
35.1M
  info->endian_code = BFD_ENDIAN_LITTLE;
4406
4407
  /* Default to DATA.  A text section is required by the ABI to contain an
4408
     INSN mapping symbol at the start.  A data section has no such
4409
     requirement, hence if no mapping symbol is found the section must
4410
     contain only data.  This however isn't very useful if the user has
4411
     fully stripped the binaries.  If this is the case use the section
4412
     attributes to determine the default.  If we have no section default to
4413
     INSN as well, as we may be disassembling some raw bytes on a baremetal
4414
     HEX file or similar.  */
4415
35.1M
  enum map_type type = MAP_DATA;
4416
35.1M
  if ((info->section && info->section->flags & SEC_CODE) || !info->section)
4417
20.5M
    type = MAP_INSN;
4418
4419
  /* First check the full symtab for a mapping symbol, even if there
4420
     are no usable non-mapping symbols for this address.  */
4421
35.1M
  if (info->symtab_size != 0
4422
35.1M
      && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour)
4423
2.81M
    {
4424
2.81M
      int last_sym = -1;
4425
2.81M
      bfd_vma addr, section_vma = 0;
4426
2.81M
      bool can_use_search_opt_p;
4427
2.81M
      int n;
4428
4429
2.81M
      if (pc <= last_mapping_addr)
4430
14
  last_mapping_sym = -1;
4431
4432
      /* Start scanning at the start of the function, or wherever
4433
   we finished last time.  */
4434
2.81M
      n = info->symtab_pos + 1;
4435
4436
      /* If the last stop offset is different from the current one it means we
4437
   are disassembling a different glob of bytes.  As such the optimization
4438
   would not be safe and we should start over.  */
4439
2.81M
      can_use_search_opt_p = last_mapping_sym >= 0
4440
2.81M
           && info->stop_offset == last_stop_offset;
4441
4442
2.81M
      if (n >= last_mapping_sym && can_use_search_opt_p)
4443
1.96M
  n = last_mapping_sym;
4444
4445
      /* Look down while we haven't passed the location being disassembled.
4446
   The reason for this is that there's no defined order between a symbol
4447
   and an mapping symbol that may be at the same address.  We may have to
4448
   look at least one position ahead.  */
4449
17.7M
      for (; n < info->symtab_size; n++)
4450
17.7M
  {
4451
17.7M
    addr = bfd_asymbol_value (info->symtab[n]);
4452
17.7M
    if (addr > pc)
4453
2.81M
      break;
4454
14.9M
    if (get_sym_code_type (info, n, &type))
4455
1.96M
      {
4456
1.96M
        last_sym = n;
4457
1.96M
        found = true;
4458
1.96M
      }
4459
14.9M
  }
4460
4461
2.81M
      if (!found)
4462
849k
  {
4463
849k
    n = info->symtab_pos;
4464
849k
    if (n >= last_mapping_sym && can_use_search_opt_p)
4465
0
      n = last_mapping_sym;
4466
4467
    /* No mapping symbol found at this address.  Look backwards
4468
       for a preceeding one, but don't go pass the section start
4469
       otherwise a data section with no mapping symbol can pick up
4470
       a text mapping symbol of a preceeding section.  The documentation
4471
       says section can be NULL, in which case we will seek up all the
4472
       way to the top.  */
4473
849k
    if (info->section)
4474
849k
      section_vma = info->section->vma;
4475
4476
32.5M
    for (; n >= 0; n--)
4477
32.1M
      {
4478
32.1M
        addr = bfd_asymbol_value (info->symtab[n]);
4479
32.1M
        if (addr < section_vma)
4480
440k
    break;
4481
4482
31.7M
        if (get_sym_code_type (info, n, &type))
4483
19.0k
    {
4484
19.0k
      last_sym = n;
4485
19.0k
      found = true;
4486
19.0k
      break;
4487
19.0k
    }
4488
31.7M
      }
4489
849k
  }
4490
4491
2.81M
      last_mapping_sym = last_sym;
4492
2.81M
      last_type = type;
4493
2.81M
      last_stop_offset = info->stop_offset;
4494
4495
      /* Look a little bit ahead to see if we should print out
4496
   less than four bytes of data.  If there's a symbol,
4497
   mapping or otherwise, after two bytes then don't
4498
   print more.  */
4499
2.81M
      if (last_type == MAP_DATA)
4500
817k
  {
4501
817k
    size = 4 - (pc & 3);
4502
734M
    for (n = last_sym + 1; n < info->symtab_size; n++)
4503
734M
      {
4504
734M
        addr = bfd_asymbol_value (info->symtab[n]);
4505
734M
        if (addr > pc)
4506
817k
    {
4507
817k
      if (addr - pc < size)
4508
14
        size = addr - pc;
4509
817k
      break;
4510
817k
    }
4511
734M
      }
4512
    /* If the next symbol is after three bytes, we need to
4513
       print only part of the data, so that we can use either
4514
       .byte or .short.  */
4515
817k
    if (size == 3)
4516
28
      size = (pc & 1) ? 1 : 2;
4517
817k
  }
4518
2.81M
    }
4519
32.3M
  else
4520
32.3M
    last_type = type;
4521
4522
  /* PR 10263: Disassemble data if requested to do so by the user.  */
4523
35.1M
  if (last_type == MAP_DATA && ((info->flags & DISASSEMBLE_DATA) == 0))
4524
0
    {
4525
      /* size was set above.  */
4526
0
      info->bytes_per_chunk = size;
4527
0
      info->display_endian = info->endian;
4528
0
      printer = print_insn_data;
4529
0
    }
4530
35.1M
  else
4531
35.1M
    {
4532
35.1M
      info->bytes_per_chunk = size = INSNLEN;
4533
35.1M
      info->display_endian = info->endian_code;
4534
35.1M
      printer = print_insn_aarch64_word;
4535
35.1M
    }
4536
4537
35.1M
  status = (*info->read_memory_func) (pc, buffer, size, info);
4538
35.1M
  if (status != 0)
4539
12.1k
    {
4540
12.1k
      (*info->memory_error_func) (status, pc, info);
4541
12.1k
      return -1;
4542
12.1k
    }
4543
4544
35.1M
  data = bfd_get_bits (buffer, size * 8,
4545
35.1M
           info->display_endian == BFD_ENDIAN_BIG);
4546
4547
35.1M
  (*printer) (pc, data, info, &errors);
4548
4549
35.1M
  return size;
4550
35.1M
}
4551

4552
void
4553
print_aarch64_disassembler_options (FILE *stream)
4554
0
{
4555
0
  fprintf (stream, _("\n\
4556
0
The following AARCH64 specific disassembler options are supported for use\n\
4557
0
with the -M switch (multiple options should be separated by commas):\n"));
4558
4559
0
  fprintf (stream, _("\n\
4560
0
  no-aliases         Don't print instruction aliases.\n"));
4561
4562
0
  fprintf (stream, _("\n\
4563
0
  aliases            Do print instruction aliases.\n"));
4564
4565
0
  fprintf (stream, _("\n\
4566
0
  no-notes         Don't print instruction notes.\n"));
4567
4568
0
  fprintf (stream, _("\n\
4569
0
  notes            Do print instruction notes.\n"));
4570
4571
#ifdef DEBUG_AARCH64
4572
  fprintf (stream, _("\n\
4573
  debug_dump         Temp switch for debug trace.\n"));
4574
#endif /* DEBUG_AARCH64 */
4575
4576
0
  fprintf (stream, _("\n"));
4577
0
}