Coverage Report

Created: 2025-07-08 11:15

/src/binutils-gdb/opcodes/i386-dis.c
Line
Count
Source (jump to first uncovered line)
1
/* Print i386 instructions for GDB, the GNU debugger.
2
   Copyright (C) 1988-2025 Free Software Foundation, Inc.
3
4
   This file is part of the GNU opcodes library.
5
6
   This library is free software; you can redistribute it and/or modify
7
   it under the terms of the GNU General Public License as published by
8
   the Free Software Foundation; either version 3, or (at your option)
9
   any later version.
10
11
   It is distributed in the hope that it will be useful, but WITHOUT
12
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
14
   License for more details.
15
16
   You should have received a copy of the GNU General Public License
17
   along with this program; if not, write to the Free Software
18
   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19
   MA 02110-1301, USA.  */
20
21
22
/* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
23
   July 1988
24
    modified by John Hassey (hassey@dg-rtp.dg.com)
25
    x86-64 support added by Jan Hubicka (jh@suse.cz)
26
    VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
27
28
/* The main tables describing the instructions is essentially a copy
29
   of the "Opcode Map" chapter (Appendix A) of the Intel 80386
30
   Programmers Manual.  Usually, there is a capital letter, followed
31
   by a small letter.  The capital letter tell the addressing mode,
32
   and the small letter tells about the operand size.  Refer to
33
   the Intel manual for details.  */
34
35
#include "sysdep.h"
36
#include "disassemble.h"
37
#include "opintl.h"
38
#include "opcode/i386.h"
39
#include "libiberty.h"
40
#include "safe-ctype.h"
41
42
typedef struct instr_info instr_info;
43
44
static bool dofloat (instr_info *, int);
45
static int putop (instr_info *, const char *, int);
46
static void oappend_with_style (instr_info *, const char *,
47
        enum disassembler_style);
48
49
static bool OP_E (instr_info *, int, int);
50
static bool OP_E_memory (instr_info *, int, int);
51
static bool OP_indirE (instr_info *, int, int);
52
static bool OP_G (instr_info *, int, int);
53
static bool OP_ST (instr_info *, int, int);
54
static bool OP_STi (instr_info *, int, int);
55
static bool OP_Skip_MODRM (instr_info *, int, int);
56
static bool OP_REG (instr_info *, int, int);
57
static bool OP_IMREG (instr_info *, int, int);
58
static bool OP_I (instr_info *, int, int);
59
static bool OP_I64 (instr_info *, int, int);
60
static bool OP_sI (instr_info *, int, int);
61
static bool OP_J (instr_info *, int, int);
62
static bool OP_SEG (instr_info *, int, int);
63
static bool OP_DIR (instr_info *, int, int);
64
static bool OP_OFF (instr_info *, int, int);
65
static bool OP_OFF64 (instr_info *, int, int);
66
static bool OP_ESreg (instr_info *, int, int);
67
static bool OP_DSreg (instr_info *, int, int);
68
static bool OP_C (instr_info *, int, int);
69
static bool OP_D (instr_info *, int, int);
70
static bool OP_T (instr_info *, int, int);
71
static bool OP_MMX (instr_info *, int, int);
72
static bool OP_XMM (instr_info *, int, int);
73
static bool OP_EM (instr_info *, int, int);
74
static bool OP_EX (instr_info *, int, int);
75
static bool OP_EMC (instr_info *, int,int);
76
static bool OP_MXC (instr_info *, int,int);
77
static bool OP_R (instr_info *, int, int);
78
static bool OP_M (instr_info *, int, int);
79
static bool OP_VEX (instr_info *, int, int);
80
static bool OP_VexR (instr_info *, int, int);
81
static bool OP_VexW (instr_info *, int, int);
82
static bool OP_Rounding (instr_info *, int, int);
83
static bool OP_REG_VexI4 (instr_info *, int, int);
84
static bool OP_VexI4 (instr_info *, int, int);
85
static bool OP_0f07 (instr_info *, int, int);
86
static bool OP_Monitor (instr_info *, int, int);
87
static bool OP_Mwait (instr_info *, int, int);
88
89
static bool PCLMUL_Fixup (instr_info *, int, int);
90
static bool VPCMP_Fixup (instr_info *, int, int);
91
static bool VPCOM_Fixup (instr_info *, int, int);
92
static bool NOP_Fixup (instr_info *, int, int);
93
static bool MONTMUL_Fixup (instr_info *, int, int);
94
static bool OP_3DNowSuffix (instr_info *, int, int);
95
static bool CMP_Fixup (instr_info *, int, int);
96
static bool REP_Fixup (instr_info *, int, int);
97
static bool SEP_Fixup (instr_info *, int, int);
98
static bool BND_Fixup (instr_info *, int, int);
99
static bool NOTRACK_Fixup (instr_info *, int, int);
100
static bool HLE_Fixup1 (instr_info *, int, int);
101
static bool HLE_Fixup2 (instr_info *, int, int);
102
static bool HLE_Fixup3 (instr_info *, int, int);
103
static bool CMPXCHG8B_Fixup (instr_info *, int, int);
104
static bool XMM_Fixup (instr_info *, int, int);
105
static bool FXSAVE_Fixup (instr_info *, int, int);
106
static bool MOVSXD_Fixup (instr_info *, int, int);
107
static bool DistinctDest_Fixup (instr_info *, int, int);
108
static bool PREFETCHI_Fixup (instr_info *, int, int);
109
static bool PUSH2_POP2_Fixup (instr_info *, int, int);
110
static bool JMPABS_Fixup (instr_info *, int, int);
111
static bool CFCMOV_Fixup (instr_info *, int, int);
112
113
static void ATTRIBUTE_PRINTF_3 i386_dis_printf (const disassemble_info *,
114
            enum disassembler_style,
115
            const char *, ...);
116
117
/* This character is used to encode style information within the output
118
   buffers.  See oappend_insert_style for more details.  */
119
2.00G
#define STYLE_MARKER_CHAR '\002'
120
121
/* The maximum operand buffer size.  */
122
#define MAX_OPERAND_BUFFER_SIZE 128
123
124
enum address_mode
125
{
126
  mode_16bit,
127
  mode_32bit,
128
  mode_64bit
129
};
130
131
static const char *prefix_name (enum address_mode, uint8_t, int);
132
133
enum x86_64_isa
134
{
135
  amd64 = 1,
136
  intel64
137
};
138
139
enum evex_type
140
{
141
  evex_default = 0,
142
  evex_from_legacy,
143
  evex_from_vex,
144
};
145
146
struct instr_info
147
{
148
  enum address_mode address_mode;
149
150
  /* Flags for the prefixes for the current instruction.  See below.  */
151
  int prefixes;
152
153
  /* REX prefix the current instruction.  See below.  */
154
  uint8_t rex;
155
  /* Bits of REX we've already used.  */
156
  uint8_t rex_used;
157
158
  /* Record W R4 X4 B4 bits for rex2.  */
159
  unsigned char rex2;
160
  /* Bits of rex2 we've already used.  */
161
  unsigned char rex2_used;
162
  unsigned char rex2_payload;
163
164
  bool need_modrm;
165
  unsigned char condition_code;
166
  unsigned char need_vex;
167
  bool has_sib;
168
169
  /* Flags for ins->prefixes which we somehow handled when printing the
170
     current instruction.  */
171
  int used_prefixes;
172
173
  /* Flags for EVEX bits which we somehow handled when printing the
174
     current instruction.  */
175
  int evex_used;
176
177
  char obuf[MAX_OPERAND_BUFFER_SIZE];
178
  char *obufp;
179
  char *mnemonicendp;
180
  const uint8_t *start_codep;
181
  uint8_t *codep;
182
  const uint8_t *end_codep;
183
  unsigned char nr_prefixes;
184
  signed char last_lock_prefix;
185
  signed char last_repz_prefix;
186
  signed char last_repnz_prefix;
187
  signed char last_data_prefix;
188
  signed char last_addr_prefix;
189
  signed char last_rex_prefix;
190
  signed char last_rex2_prefix;
191
  signed char last_seg_prefix;
192
  signed char fwait_prefix;
193
  /* The active segment register prefix.  */
194
  unsigned char active_seg_prefix;
195
196
94.9M
#define MAX_CODE_LENGTH 15
197
  /* We can up to 14 ins->prefixes since the maximum instruction length is
198
     15bytes.  */
199
  uint8_t all_prefixes[MAX_CODE_LENGTH - 1];
200
  disassemble_info *info;
201
202
  struct
203
  {
204
    int mod;
205
    int reg;
206
    int rm;
207
  }
208
  modrm;
209
210
  struct
211
  {
212
    int scale;
213
    int index;
214
    int base;
215
  }
216
  sib;
217
218
  struct
219
  {
220
    int register_specifier;
221
    int length;
222
    int prefix;
223
    int mask_register_specifier;
224
    int scc;
225
    int ll;
226
    bool w;
227
    bool evex;
228
    bool v;
229
    bool zeroing;
230
    bool b;
231
    bool no_broadcast;
232
    bool nf;
233
  }
234
  vex;
235
236
/* For APX EVEX-promoted prefix, EVEX.ND shares the same bit as vex.b.  */
237
131M
#define nd b
238
239
  enum evex_type evex_type;
240
241
  /* Remember if the current op is a jump instruction.  */
242
  bool op_is_jump;
243
244
  bool two_source_ops;
245
246
  /* Record whether EVEX masking is used incorrectly.  */
247
  bool illegal_masking;
248
249
  /* Record whether the modrm byte has been skipped.  */
250
  bool has_skipped_modrm;
251
252
  unsigned char op_ad;
253
  signed char op_index[MAX_OPERANDS];
254
  bool op_riprel[MAX_OPERANDS];
255
  char *op_out[MAX_OPERANDS];
256
  bfd_vma op_address[MAX_OPERANDS];
257
  bfd_vma start_pc;
258
259
  /* On the 386's of 1988, the maximum length of an instruction is 15 bytes.
260
   *   (see topic "Redundant ins->prefixes" in the "Differences from 8086"
261
   *   section of the "Virtual 8086 Mode" chapter.)
262
   * 'pc' should be the address of this instruction, it will
263
   *   be used to print the target address if this is a relative jump or call
264
   * The function returns the length of this instruction in bytes.
265
   */
266
  char intel_syntax;
267
  bool intel_mnemonic;
268
  char open_char;
269
  char close_char;
270
  char separator_char;
271
  char scale_char;
272
273
  enum x86_64_isa isa64;
274
};
275
276
struct dis_private {
277
  bfd_vma insn_start;
278
  int orig_sizeflag;
279
280
  /* Indexes first byte not fetched.  */
281
  unsigned int fetched;
282
  uint8_t the_buffer[2 * MAX_CODE_LENGTH - 1];
283
};
284
285
/* Mark parts used in the REX prefix.  When we are testing for
286
   empty prefix (for 8bit register REX extension), just mask it
287
   out.  Otherwise test for REX bit is excuse for existence of REX
288
   only in case value is nonzero.  */
289
#define USED_REX(value)         \
290
75.2M
  {             \
291
75.2M
    if (value)           \
292
75.2M
      {             \
293
72.2M
  if (ins->rex & value)       \
294
72.2M
    ins->rex_used |= (value) | REX_OPCODE; \
295
72.2M
  if (ins->rex2 & value)       \
296
72.2M
    {           \
297
77.7k
      ins->rex2_used |= (value);      \
298
77.7k
      ins->rex_used |= REX_OPCODE;   \
299
77.7k
    }            \
300
72.2M
      }              \
301
75.2M
    else            \
302
75.2M
      ins->rex_used |= REX_OPCODE;     \
303
75.2M
  }
304
305
306
47.6k
#define EVEX_b_used 1
307
112k
#define EVEX_len_used 2
308
309
310
/* {rex2} is not printed when the REX2_SPECIAL is set.  */
311
40.2k
#define REX2_SPECIAL 16
312
313
/* Flags stored in PREFIXES.  */
314
2.41M
#define PREFIX_REPZ 1
315
6.87M
#define PREFIX_REPNZ 2
316
57.7M
#define PREFIX_CS 4
317
43.7M
#define PREFIX_SS 8
318
55.0M
#define PREFIX_DS 0x10
319
43.6M
#define PREFIX_ES 0x20
320
44.2M
#define PREFIX_FS 0x40
321
44.5M
#define PREFIX_GS 0x80
322
11.9M
#define PREFIX_LOCK 0x100
323
113M
#define PREFIX_DATA 0x200
324
108M
#define PREFIX_ADDR 0x400
325
43.9M
#define PREFIX_FWAIT 0x800
326
87.2M
#define PREFIX_REX2 0x1000
327
263k
#define PREFIX_NP_OR_DATA 0x2000
328
205k
#define NO_PREFIX   0x4000
329
330
/* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
331
   to ADDR (exclusive) are valid.  Returns true for success, false
332
   on error.  */
333
static bool
334
fetch_code (struct disassemble_info *info, const uint8_t *until)
335
144M
{
336
144M
  int status = -1;
337
144M
  struct dis_private *priv = info->private_data;
338
144M
  bfd_vma start = priv->insn_start + priv->fetched;
339
144M
  uint8_t *fetch_end = priv->the_buffer + priv->fetched;
340
144M
  ptrdiff_t needed = until - fetch_end;
341
342
144M
  if (needed <= 0)
343
43.8M
    return true;
344
345
100M
  if (priv->fetched + (size_t) needed <= ARRAY_SIZE (priv->the_buffer))
346
100M
    status = (*info->read_memory_func) (start, fetch_end, needed, info);
347
100M
  if (status != 0)
348
56.4k
    {
349
      /* If we did manage to read at least one byte, then
350
   print_insn_i386 will do something sensible.  Otherwise, print
351
   an error.  We do that here because this is where we know
352
   STATUS.  */
353
56.4k
      if (!priv->fetched)
354
768
  (*info->memory_error_func) (status, start, info);
355
56.4k
      return false;
356
56.4k
    }
357
358
100M
  priv->fetched += needed;
359
100M
  return true;
360
100M
}
361
362
static bool
363
fetch_modrm (instr_info *ins)
364
26.4M
{
365
26.4M
  if (!fetch_code (ins->info, ins->codep + 1))
366
9.27k
    return false;
367
368
26.4M
  ins->modrm.mod = (*ins->codep >> 6) & 3;
369
26.4M
  ins->modrm.reg = (*ins->codep >> 3) & 7;
370
26.4M
  ins->modrm.rm = *ins->codep & 7;
371
372
26.4M
  return true;
373
26.4M
}
374
375
static int
376
fetch_error (const instr_info *ins)
377
57.2k
{
378
  /* Getting here means we tried for data but didn't get it.  That
379
     means we have an incomplete instruction of some sort.  Just
380
     print the first byte as a prefix or a .byte pseudo-op.  */
381
57.2k
  const struct dis_private *priv = ins->info->private_data;
382
57.2k
  const char *name = NULL;
383
384
57.2k
  if (ins->codep <= priv->the_buffer)
385
768
    return -1;
386
387
56.4k
  if (ins->prefixes || ins->fwait_prefix >= 0 || (ins->rex & REX_OPCODE))
388
31.6k
    name = prefix_name (ins->address_mode, priv->the_buffer[0],
389
31.6k
      priv->orig_sizeflag);
390
56.4k
  if (name != NULL)
391
31.3k
    i386_dis_printf (ins->info, dis_style_mnemonic, "%s", name);
392
25.1k
  else
393
25.1k
    {
394
      /* Just print the first byte as a .byte instruction.  */
395
25.1k
      i386_dis_printf (ins->info, dis_style_assembler_directive, ".byte ");
396
25.1k
      i386_dis_printf (ins->info, dis_style_immediate, "%#x",
397
25.1k
           (unsigned int) priv->the_buffer[0]);
398
25.1k
    }
399
400
56.4k
  return 1;
401
57.2k
}
402
403
/* Possible values for prefix requirement.  */
404
87.3M
#define PREFIX_IGNORED_SHIFT  16
405
22.2k
#define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
406
22.2k
#define PREFIX_IGNORED_REPNZ  (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
407
22.2k
#define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
408
#define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
409
#define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
410
87.2M
#define PREFIX_REX2_ILLEGAL (PREFIX_REX2 << PREFIX_IGNORED_SHIFT)
411
412
/* Opcode prefixes.  */
413
89.8k
#define PREFIX_OPCODE   (PREFIX_REPZ \
414
89.8k
         | PREFIX_REPNZ \
415
89.8k
         | PREFIX_DATA)
416
417
/* Prefixes ignored.  */
418
22.2k
#define PREFIX_IGNORED    (PREFIX_IGNORED_REPZ \
419
22.2k
         | PREFIX_IGNORED_REPNZ \
420
22.2k
         | PREFIX_IGNORED_DATA)
421
422
#define XX { NULL, 0 }
423
#define Bad_Opcode NULL, { { NULL, 0 } }, 0
424
425
#define Eb { OP_E, b_mode }
426
#define Ebnd { OP_E, bnd_mode }
427
#define EbS { OP_E, b_swap_mode }
428
#define EbndS { OP_E, bnd_swap_mode }
429
#define Ev { OP_E, v_mode }
430
#define Eva { OP_E, va_mode }
431
#define Ev_bnd { OP_E, v_bnd_mode }
432
#define EvS { OP_E, v_swap_mode }
433
#define Ed { OP_E, d_mode }
434
#define Edq { OP_E, dq_mode }
435
#define Edb { OP_E, db_mode }
436
#define Edw { OP_E, dw_mode }
437
#define Eq { OP_E, q_mode }
438
#define indirEv { OP_indirE, indir_v_mode }
439
#define indirEp { OP_indirE, f_mode }
440
#define stackEv { OP_E, stack_v_mode }
441
#define Em { OP_E, m_mode }
442
#define Ew { OP_E, w_mode }
443
#define M { OP_M, 0 }   /* lea, lgdt, etc. */
444
#define Ma { OP_M, a_mode }
445
#define Mb { OP_M, b_mode }
446
#define Md { OP_M, d_mode }
447
#define Mdq { OP_M, dq_mode }
448
#define Mo { OP_M, o_mode }
449
#define Mp { OP_M, f_mode }   /* 32 or 48 bit memory operand for LDS, LES etc */
450
#define Mq { OP_M, q_mode }
451
#define Mv { OP_M, v_mode }
452
#define Mv_bnd { OP_M, v_bndmk_mode }
453
#define Mw { OP_M, w_mode }
454
#define Mx { OP_M, x_mode }
455
#define Mxmm { OP_M, xmm_mode }
456
#define Mymm { OP_M, ymm_mode }
457
#define Gb { OP_G, b_mode }
458
#define Gbnd { OP_G, bnd_mode }
459
#define Gv { OP_G, v_mode }
460
#define Gd { OP_G, d_mode }
461
#define Gdq { OP_G, dq_mode }
462
#define Gq { OP_G, q_mode }
463
#define Gm { OP_G, m_mode }
464
#define Gva { OP_G, va_mode }
465
#define Gw { OP_G, w_mode }
466
#define Ib { OP_I, b_mode }
467
#define sIb { OP_sI, b_mode } /* sign extened byte */
468
#define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
469
#define Iv { OP_I, v_mode }
470
#define sIv { OP_sI, v_mode }
471
#define Iv64 { OP_I64, v_mode }
472
#define Id { OP_I, d_mode }
473
#define Iw { OP_I, w_mode }
474
#define I1 { OP_I, const_1_mode }
475
#define Jb { OP_J, b_mode }
476
#define Jv { OP_J, v_mode }
477
#define Jdqw { OP_J, dqw_mode }
478
#define Cm { OP_C, m_mode }
479
#define Dm { OP_D, m_mode }
480
#define Td { OP_T, d_mode }
481
#define Skip_MODRM { OP_Skip_MODRM, 0 }
482
483
#define RMeAX { OP_REG, eAX_reg }
484
#define RMeBX { OP_REG, eBX_reg }
485
#define RMeCX { OP_REG, eCX_reg }
486
#define RMeDX { OP_REG, eDX_reg }
487
#define RMeSP { OP_REG, eSP_reg }
488
#define RMeBP { OP_REG, eBP_reg }
489
#define RMeSI { OP_REG, eSI_reg }
490
#define RMeDI { OP_REG, eDI_reg }
491
#define RMrAX { OP_REG, rAX_reg }
492
#define RMrBX { OP_REG, rBX_reg }
493
#define RMrCX { OP_REG, rCX_reg }
494
#define RMrDX { OP_REG, rDX_reg }
495
#define RMrSP { OP_REG, rSP_reg }
496
#define RMrBP { OP_REG, rBP_reg }
497
#define RMrSI { OP_REG, rSI_reg }
498
#define RMrDI { OP_REG, rDI_reg }
499
#define RMAL { OP_REG, al_reg }
500
#define RMCL { OP_REG, cl_reg }
501
#define RMDL { OP_REG, dl_reg }
502
#define RMBL { OP_REG, bl_reg }
503
#define RMAH { OP_REG, ah_reg }
504
#define RMCH { OP_REG, ch_reg }
505
#define RMDH { OP_REG, dh_reg }
506
#define RMBH { OP_REG, bh_reg }
507
#define RMAX { OP_REG, ax_reg }
508
#define RMDX { OP_REG, dx_reg }
509
510
#define eAX { OP_IMREG, eAX_reg }
511
#define AL { OP_IMREG, al_reg }
512
#define CL { OP_IMREG, cl_reg }
513
#define zAX { OP_IMREG, z_mode_ax_reg }
514
#define indirDX { OP_IMREG, indir_dx_reg }
515
516
#define Sw { OP_SEG, w_mode }
517
#define Sv { OP_SEG, v_mode }
518
#define Ap { OP_DIR, 0 }
519
#define Ob { OP_OFF64, b_mode }
520
#define Ov { OP_OFF64, v_mode }
521
#define Xb { OP_DSreg, eSI_reg }
522
#define Xv { OP_DSreg, eSI_reg }
523
#define Xz { OP_DSreg, eSI_reg }
524
#define Yb { OP_ESreg, eDI_reg }
525
#define Yv { OP_ESreg, eDI_reg }
526
#define DSCX { OP_DSreg, eCX_reg }
527
#define DSBX { OP_DSreg, eBX_reg }
528
529
#define es { OP_REG, es_reg }
530
#define ss { OP_REG, ss_reg }
531
#define cs { OP_REG, cs_reg }
532
#define ds { OP_REG, ds_reg }
533
#define fs { OP_REG, fs_reg }
534
#define gs { OP_REG, gs_reg }
535
536
#define MX { OP_MMX, 0 }
537
#define XM { OP_XMM, 0 }
538
#define XMScalar { OP_XMM, scalar_mode }
539
#define XMGatherD { OP_XMM, vex_vsib_d_w_dq_mode }
540
#define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
541
#define XMM { OP_XMM, xmm_mode }
542
#define TMM { OP_XMM, tmm_mode }
543
#define XMxmmq { OP_XMM, xmmq_mode }
544
#define EM { OP_EM, v_mode }
545
#define EMS { OP_EM, v_swap_mode }
546
#define EMd { OP_EM, d_mode }
547
#define EMx { OP_EM, x_mode }
548
#define EXbwUnit { OP_EX, bw_unit_mode }
549
#define EXb { OP_EX, b_mode }
550
#define EXw { OP_EX, w_mode }
551
#define EXd { OP_EX, d_mode }
552
#define EXdS { OP_EX, d_swap_mode }
553
#define EXwS { OP_EX, w_swap_mode }
554
#define EXq { OP_EX, q_mode }
555
#define EXqS { OP_EX, q_swap_mode }
556
#define EXdq { OP_EX, dq_mode }
557
#define EXx { OP_EX, x_mode }
558
#define EXxh { OP_EX, xh_mode }
559
#define EXxS { OP_EX, x_swap_mode }
560
#define EXxmm { OP_EX, xmm_mode }
561
#define EXymm { OP_EX, ymm_mode }
562
#define EXxmmq { OP_EX, xmmq_mode }
563
#define EXxmmqh { OP_EX, evex_half_bcst_xmmqh_mode }
564
#define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
565
#define EXxmmdw { OP_EX, xmmdw_mode }
566
#define EXxmmqd { OP_EX, xmmqd_mode }
567
#define EXxmmqdh { OP_EX, evex_half_bcst_xmmqdh_mode }
568
#define EXymmq { OP_EX, ymmq_mode }
569
#define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
570
#define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
571
#define Rd { OP_R, d_mode }
572
#define Rdq { OP_R, dq_mode }
573
#define Rq { OP_R, q_mode }
574
#define Nq { OP_R, q_mm_mode }
575
#define Ux { OP_R, x_mode }
576
#define Uxmm { OP_R, xmm_mode }
577
#define Rxmmq { OP_R, xmmq_mode }
578
#define Rymm { OP_R, ymm_mode }
579
#define Rtmm { OP_R, tmm_mode }
580
#define EMCq { OP_EMC, q_mode }
581
#define MXC { OP_MXC, 0 }
582
#define OPSUF { OP_3DNowSuffix, 0 }
583
#define SEP { SEP_Fixup, 0 }
584
#define CMP { CMP_Fixup, 0 }
585
#define XMM0 { XMM_Fixup, 0 }
586
#define FXSAVE { FXSAVE_Fixup, 0 }
587
588
#define Vex { OP_VEX, x_mode }
589
#define VexW { OP_VexW, x_mode }
590
#define VexScalar { OP_VEX, scalar_mode }
591
#define VexScalarR { OP_VexR, scalar_mode }
592
#define VexGatherD { OP_VEX, vex_vsib_d_w_dq_mode }
593
#define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
594
#define VexGdq { OP_VEX, dq_mode }
595
#define VexGb { OP_VEX, b_mode }
596
#define VexGv { OP_VEX, v_mode }
597
#define VexTmm { OP_VEX, tmm_mode }
598
#define XMVexI4 { OP_REG_VexI4, x_mode }
599
#define XMVexScalarI4 { OP_REG_VexI4, scalar_mode }
600
#define VexI4 { OP_VexI4, 0 }
601
#define PCLMUL { PCLMUL_Fixup, 0 }
602
#define VPCMP { VPCMP_Fixup, 0 }
603
#define VPCOM { VPCOM_Fixup, 0 }
604
605
#define EXxEVexR { OP_Rounding, evex_rounding_mode }
606
#define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
607
#define EXxEVexS { OP_Rounding, evex_sae_mode }
608
609
#define MaskG { OP_G, mask_mode }
610
#define MaskE { OP_E, mask_mode }
611
#define MaskR { OP_R, mask_mode }
612
#define MaskBDE { OP_E, mask_bd_mode }
613
#define MaskVex { OP_VEX, mask_mode }
614
615
#define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
616
#define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
617
618
#define MVexSIBMEM { OP_M, vex_sibmem_mode }
619
620
/* Used handle "rep" prefix for string instructions.  */
621
#define Xbr { REP_Fixup, eSI_reg }
622
#define Xvr { REP_Fixup, eSI_reg }
623
#define Ybr { REP_Fixup, eDI_reg }
624
#define Yvr { REP_Fixup, eDI_reg }
625
#define Yzr { REP_Fixup, eDI_reg }
626
#define indirDXr { REP_Fixup, indir_dx_reg }
627
#define ALr { REP_Fixup, al_reg }
628
#define eAXr { REP_Fixup, eAX_reg }
629
630
/* Used handle HLE prefix for lockable instructions.  */
631
#define Ebh1 { HLE_Fixup1, b_mode }
632
#define Evh1 { HLE_Fixup1, v_mode }
633
#define Ebh2 { HLE_Fixup2, b_mode }
634
#define Evh2 { HLE_Fixup2, v_mode }
635
#define Ebh3 { HLE_Fixup3, b_mode }
636
#define Evh3 { HLE_Fixup3, v_mode }
637
638
#define BND { BND_Fixup, 0 }
639
#define NOTRACK { NOTRACK_Fixup, 0 }
640
641
#define cond_jump_flag { NULL, cond_jump_mode }
642
#define loop_jcxz_flag { NULL, loop_jcxz_mode }
643
644
/* bits in sizeflag */
645
38.8M
#define SUFFIX_ALWAYS 4
646
110M
#define AFLAG 2
647
66.2M
#define DFLAG 1
648
649
enum
650
{
651
  /* byte operand */
652
  b_mode = 1,
653
  /* byte operand with operand swapped */
654
  b_swap_mode,
655
  /* byte operand, sign extend like 'T' suffix */
656
  b_T_mode,
657
  /* operand size depends on prefixes */
658
  v_mode,
659
  /* operand size depends on prefixes with operand swapped */
660
  v_swap_mode,
661
  /* operand size depends on address prefix */
662
  va_mode,
663
  /* word operand */
664
  w_mode,
665
  /* double word operand  */
666
  d_mode,
667
  /* word operand with operand swapped  */
668
  w_swap_mode,
669
  /* double word operand with operand swapped */
670
  d_swap_mode,
671
  /* quad word operand */
672
  q_mode,
673
  /* 8-byte MM operand */
674
  q_mm_mode,
675
  /* quad word operand with operand swapped */
676
  q_swap_mode,
677
  /* ten-byte operand */
678
  t_mode,
679
  /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
680
     broadcast enabled.  */
681
  x_mode,
682
  /* Similar to x_mode, but with different EVEX mem shifts.  */
683
  evex_x_gscat_mode,
684
  /* Similar to x_mode, but with yet different EVEX mem shifts.  */
685
  bw_unit_mode,
686
  /* Similar to x_mode, but with disabled broadcast.  */
687
  evex_x_nobcst_mode,
688
  /* Similar to x_mode, but with operands swapped and disabled broadcast
689
     in EVEX.  */
690
  x_swap_mode,
691
  /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
692
     broadcast of 16bit enabled.  */
693
  xh_mode,
694
  /* 16-byte XMM operand */
695
  xmm_mode,
696
  /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
697
     memory operand (depending on vector length).  Broadcast isn't
698
     allowed.  */
699
  xmmq_mode,
700
  /* Same as xmmq_mode, but broadcast is allowed.  */
701
  evex_half_bcst_xmmq_mode,
702
  /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
703
     memory operand (depending on vector length).  16bit broadcast.  */
704
  evex_half_bcst_xmmqh_mode,
705
  /* 16-byte XMM, word, double word or quad word operand.  */
706
  xmmdw_mode,
707
  /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
708
  xmmqd_mode,
709
  /* 16-byte XMM, double word, quad word operand or xmm word operand.
710
     16bit broadcast.  */
711
  evex_half_bcst_xmmqdh_mode,
712
  /* 32-byte YMM operand */
713
  ymm_mode,
714
  /* quad word, ymmword or zmmword memory operand.  */
715
  ymmq_mode,
716
  /* TMM operand */
717
  tmm_mode,
718
  /* d_mode in 32bit, q_mode in 64bit mode.  */
719
  m_mode,
720
  /* pair of v_mode operands */
721
  a_mode,
722
  cond_jump_mode,
723
  loop_jcxz_mode,
724
  movsxd_mode,
725
  v_bnd_mode,
726
  /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode.  */
727
  v_bndmk_mode,
728
  /* operand size depends on REX.W / VEX.W.  */
729
  dq_mode,
730
  /* Displacements like v_mode without considering Intel64 ISA.  */
731
  dqw_mode,
732
  /* bounds operand */
733
  bnd_mode,
734
  /* bounds operand with operand swapped */
735
  bnd_swap_mode,
736
  /* 4- or 6-byte pointer operand */
737
  f_mode,
738
  const_1_mode,
739
  /* v_mode for indirect branch opcodes.  */
740
  indir_v_mode,
741
  /* v_mode for stack-related opcodes.  */
742
  stack_v_mode,
743
  /* non-quad operand size depends on prefixes */
744
  z_mode,
745
  /* 16-byte operand */
746
  o_mode,
747
  /* registers like d_mode, memory like b_mode.  */
748
  db_mode,
749
  /* registers like d_mode, memory like w_mode.  */
750
  dw_mode,
751
752
  /* Operand size depends on the VEX.W bit, with VSIB dword indices.  */
753
  vex_vsib_d_w_dq_mode,
754
  /* Operand size depends on the VEX.W bit, with VSIB qword indices.  */
755
  vex_vsib_q_w_dq_mode,
756
  /* mandatory non-vector SIB.  */
757
  vex_sibmem_mode,
758
759
  /* scalar, ignore vector length.  */
760
  scalar_mode,
761
762
  /* Static rounding.  */
763
  evex_rounding_mode,
764
  /* Static rounding, 64-bit mode only.  */
765
  evex_rounding_64_mode,
766
  /* Supress all exceptions.  */
767
  evex_sae_mode,
768
769
  /* Mask register operand.  */
770
  mask_mode,
771
  /* Mask register operand.  */
772
  mask_bd_mode,
773
774
  es_reg,
775
  cs_reg,
776
  ss_reg,
777
  ds_reg,
778
  fs_reg,
779
  gs_reg,
780
781
  eAX_reg,
782
  eCX_reg,
783
  eDX_reg,
784
  eBX_reg,
785
  eSP_reg,
786
  eBP_reg,
787
  eSI_reg,
788
  eDI_reg,
789
790
  al_reg,
791
  cl_reg,
792
  dl_reg,
793
  bl_reg,
794
  ah_reg,
795
  ch_reg,
796
  dh_reg,
797
  bh_reg,
798
799
  ax_reg,
800
  cx_reg,
801
  dx_reg,
802
  bx_reg,
803
  sp_reg,
804
  bp_reg,
805
  si_reg,
806
  di_reg,
807
808
  rAX_reg,
809
  rCX_reg,
810
  rDX_reg,
811
  rBX_reg,
812
  rSP_reg,
813
  rBP_reg,
814
  rSI_reg,
815
  rDI_reg,
816
817
  z_mode_ax_reg,
818
  indir_dx_reg
819
};
820
821
enum
822
{
823
  FLOATCODE = 1,
824
  USE_REG_TABLE,
825
  USE_MOD_TABLE,
826
  USE_RM_TABLE,
827
  USE_PREFIX_TABLE,
828
  USE_X86_64_TABLE,
829
  USE_X86_64_EVEX_FROM_VEX_TABLE,
830
  USE_X86_64_EVEX_PFX_TABLE,
831
  USE_X86_64_EVEX_W_TABLE,
832
  USE_X86_64_EVEX_MEM_W_TABLE,
833
  USE_3BYTE_TABLE,
834
  USE_XOP_8F_TABLE,
835
  USE_VEX_C4_TABLE,
836
  USE_VEX_C5_TABLE,
837
  USE_VEX_LEN_TABLE,
838
  USE_VEX_W_TABLE,
839
  USE_EVEX_TABLE,
840
  USE_EVEX_LEN_TABLE
841
};
842
843
#define FLOAT     NULL, { { NULL, FLOATCODE } }, 0
844
845
#define DIS386(T, I)    NULL, { { NULL, (T)}, { NULL,  (I) } }, 0
846
#define REG_TABLE(I)    DIS386 (USE_REG_TABLE, (I))
847
#define MOD_TABLE(I)    DIS386 (USE_MOD_TABLE, (I))
848
#define RM_TABLE(I)   DIS386 (USE_RM_TABLE, (I))
849
#define PREFIX_TABLE(I)   DIS386 (USE_PREFIX_TABLE, (I))
850
#define X86_64_TABLE(I)   DIS386 (USE_X86_64_TABLE, (I))
851
#define X86_64_EVEX_FROM_VEX_TABLE(I) \
852
  DIS386 (USE_X86_64_EVEX_FROM_VEX_TABLE, (I))
853
#define X86_64_EVEX_PFX_TABLE(I) DIS386 (USE_X86_64_EVEX_PFX_TABLE, (I))
854
#define X86_64_EVEX_W_TABLE(I) DIS386 (USE_X86_64_EVEX_W_TABLE, (I))
855
#define X86_64_EVEX_MEM_W_TABLE(I) DIS386 (USE_X86_64_EVEX_MEM_W_TABLE, (I))
856
#define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
857
#define XOP_8F_TABLE()    DIS386 (USE_XOP_8F_TABLE, 0)
858
#define VEX_C4_TABLE()    DIS386 (USE_VEX_C4_TABLE, 0)
859
#define VEX_C5_TABLE()    DIS386 (USE_VEX_C5_TABLE, 0)
860
#define VEX_LEN_TABLE(I)  DIS386 (USE_VEX_LEN_TABLE, (I))
861
#define VEX_W_TABLE(I)    DIS386 (USE_VEX_W_TABLE, (I))
862
#define EVEX_TABLE()    DIS386 (USE_EVEX_TABLE, 0)
863
#define EVEX_LEN_TABLE(I) DIS386 (USE_EVEX_LEN_TABLE, (I))
864
865
enum
866
{
867
  REG_80 = 0,
868
  REG_81,
869
  REG_83,
870
  REG_8F,
871
  REG_C0,
872
  REG_C1,
873
  REG_C6,
874
  REG_C7,
875
  REG_D0,
876
  REG_D1,
877
  REG_D2,
878
  REG_D3,
879
  REG_F6,
880
  REG_F7,
881
  REG_FE,
882
  REG_FF,
883
  REG_0F00,
884
  REG_0F01,
885
  REG_0F0D,
886
  REG_0F18,
887
  REG_0F1C_P_0_MOD_0,
888
  REG_0F1E_P_1_MOD_3,
889
  REG_0F38D8_PREFIX_1,
890
  REG_0F3A0F_P_1,
891
  REG_0F71,
892
  REG_0F72,
893
  REG_0F73,
894
  REG_0FA6,
895
  REG_0FA7,
896
  REG_0FAE,
897
  REG_0FBA,
898
  REG_0FC7,
899
  REG_VEX_0F71,
900
  REG_VEX_0F72,
901
  REG_VEX_0F73,
902
  REG_VEX_0FAE,
903
  REG_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0,
904
  REG_VEX_0F38F3_L_0_P_0,
905
  REG_VEX_MAP7_F6_L_0_W_0,
906
  REG_VEX_MAP7_F8_L_0_W_0,
907
908
  REG_XOP_09_01_L_0,
909
  REG_XOP_09_02_L_0,
910
  REG_XOP_09_12_L_0,
911
  REG_XOP_0A_12_L_0,
912
913
  REG_EVEX_0F71,
914
  REG_EVEX_0F72,
915
  REG_EVEX_0F73,
916
  REG_EVEX_0F38C6_L_2,
917
  REG_EVEX_0F38C7_L_2,
918
  REG_EVEX_MAP4_80,
919
  REG_EVEX_MAP4_81,
920
  REG_EVEX_MAP4_83,
921
  REG_EVEX_MAP4_8F,
922
  REG_EVEX_MAP4_F6,
923
  REG_EVEX_MAP4_F7,
924
  REG_EVEX_MAP4_FE,
925
  REG_EVEX_MAP4_FF,
926
};
927
928
enum
929
{
930
  MOD_62_32BIT = 0,
931
  MOD_C4_32BIT,
932
  MOD_C5_32BIT,
933
  MOD_0F01_REG_0,
934
  MOD_0F01_REG_1,
935
  MOD_0F01_REG_2,
936
  MOD_0F01_REG_3,
937
  MOD_0F01_REG_5,
938
  MOD_0F01_REG_7,
939
  MOD_0F12_PREFIX_0,
940
  MOD_0F16_PREFIX_0,
941
  MOD_0F18_REG_0,
942
  MOD_0F18_REG_1,
943
  MOD_0F18_REG_2,
944
  MOD_0F18_REG_3,
945
  MOD_0F18_REG_4,
946
  MOD_0F18_REG_6,
947
  MOD_0F18_REG_7,
948
  MOD_0F1A_PREFIX_0,
949
  MOD_0F1B_PREFIX_0,
950
  MOD_0F1B_PREFIX_1,
951
  MOD_0F1C_PREFIX_0,
952
  MOD_0F1E_PREFIX_1,
953
  MOD_0FAE_REG_0,
954
  MOD_0FAE_REG_1,
955
  MOD_0FAE_REG_2,
956
  MOD_0FAE_REG_3,
957
  MOD_0FAE_REG_4,
958
  MOD_0FAE_REG_5,
959
  MOD_0FAE_REG_6,
960
  MOD_0FAE_REG_7,
961
  MOD_0FC7_REG_6,
962
  MOD_0FC7_REG_7,
963
  MOD_0F38DC_PREFIX_1,
964
  MOD_0F38F8,
965
966
  MOD_VEX_0F3849_X86_64_L_0_W_0,
967
968
  MOD_EVEX_MAP4_60,
969
  MOD_EVEX_MAP4_61,
970
  MOD_EVEX_MAP4_F8_P_1,
971
  MOD_EVEX_MAP4_F8_P_3,
972
};
973
974
enum
975
{
976
  RM_C6_REG_7 = 0,
977
  RM_C7_REG_7,
978
  RM_0F01_REG_0,
979
  RM_0F01_REG_1,
980
  RM_0F01_REG_2,
981
  RM_0F01_REG_3,
982
  RM_0F01_REG_5_MOD_3,
983
  RM_0F01_REG_7_MOD_3,
984
  RM_0F1E_P_1_MOD_3_REG_7,
985
  RM_0FAE_REG_6_MOD_3_P_0,
986
  RM_0FAE_REG_7_MOD_3,
987
  RM_0F3A0F_P_1_R_0,
988
989
  RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0_R_0,
990
  RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_3,
991
};
992
993
enum
994
{
995
  PREFIX_90 = 0,
996
  PREFIX_0F00_REG_6_X86_64,
997
  PREFIX_0F01_REG_0_MOD_3_RM_6,
998
  PREFIX_0F01_REG_0_MOD_3_RM_7,
999
  PREFIX_0F01_REG_1_RM_2,
1000
  PREFIX_0F01_REG_1_RM_4,
1001
  PREFIX_0F01_REG_1_RM_5,
1002
  PREFIX_0F01_REG_1_RM_6,
1003
  PREFIX_0F01_REG_1_RM_7,
1004
  PREFIX_0F01_REG_3_RM_1,
1005
  PREFIX_0F01_REG_5_MOD_0,
1006
  PREFIX_0F01_REG_5_MOD_3_RM_0,
1007
  PREFIX_0F01_REG_5_MOD_3_RM_1,
1008
  PREFIX_0F01_REG_5_MOD_3_RM_2,
1009
  PREFIX_0F01_REG_5_MOD_3_RM_4,
1010
  PREFIX_0F01_REG_5_MOD_3_RM_5,
1011
  PREFIX_0F01_REG_5_MOD_3_RM_6,
1012
  PREFIX_0F01_REG_5_MOD_3_RM_7,
1013
  PREFIX_0F01_REG_7_MOD_3_RM_2,
1014
  PREFIX_0F01_REG_7_MOD_3_RM_5,
1015
  PREFIX_0F01_REG_7_MOD_3_RM_6,
1016
  PREFIX_0F01_REG_7_MOD_3_RM_7,
1017
  PREFIX_0F09,
1018
  PREFIX_0F10,
1019
  PREFIX_0F11,
1020
  PREFIX_0F12,
1021
  PREFIX_0F16,
1022
  PREFIX_0F18_REG_6_MOD_0_X86_64,
1023
  PREFIX_0F18_REG_7_MOD_0_X86_64,
1024
  PREFIX_0F1A,
1025
  PREFIX_0F1B,
1026
  PREFIX_0F1C,
1027
  PREFIX_0F1E,
1028
  PREFIX_0F2A,
1029
  PREFIX_0F2B,
1030
  PREFIX_0F2C,
1031
  PREFIX_0F2D,
1032
  PREFIX_0F2E,
1033
  PREFIX_0F2F,
1034
  PREFIX_0F51,
1035
  PREFIX_0F52,
1036
  PREFIX_0F53,
1037
  PREFIX_0F58,
1038
  PREFIX_0F59,
1039
  PREFIX_0F5A,
1040
  PREFIX_0F5B,
1041
  PREFIX_0F5C,
1042
  PREFIX_0F5D,
1043
  PREFIX_0F5E,
1044
  PREFIX_0F5F,
1045
  PREFIX_0F60,
1046
  PREFIX_0F61,
1047
  PREFIX_0F62,
1048
  PREFIX_0F6F,
1049
  PREFIX_0F70,
1050
  PREFIX_0F78,
1051
  PREFIX_0F79,
1052
  PREFIX_0F7C,
1053
  PREFIX_0F7D,
1054
  PREFIX_0F7E,
1055
  PREFIX_0F7F,
1056
  PREFIX_0FA6_REG_0,
1057
  PREFIX_0FA6_REG_5,
1058
  PREFIX_0FA7_REG_6,
1059
  PREFIX_0FAE_REG_0_MOD_3,
1060
  PREFIX_0FAE_REG_1_MOD_3,
1061
  PREFIX_0FAE_REG_2_MOD_3,
1062
  PREFIX_0FAE_REG_3_MOD_3,
1063
  PREFIX_0FAE_REG_4_MOD_0,
1064
  PREFIX_0FAE_REG_4_MOD_3,
1065
  PREFIX_0FAE_REG_5_MOD_3,
1066
  PREFIX_0FAE_REG_6_MOD_0,
1067
  PREFIX_0FAE_REG_6_MOD_3,
1068
  PREFIX_0FAE_REG_7_MOD_0,
1069
  PREFIX_0FB8,
1070
  PREFIX_0FBC,
1071
  PREFIX_0FBD,
1072
  PREFIX_0FC2,
1073
  PREFIX_0FC7_REG_6_MOD_0,
1074
  PREFIX_0FC7_REG_6_MOD_3,
1075
  PREFIX_0FC7_REG_7_MOD_3,
1076
  PREFIX_0FD0,
1077
  PREFIX_0FD6,
1078
  PREFIX_0FE6,
1079
  PREFIX_0FE7,
1080
  PREFIX_0FF0,
1081
  PREFIX_0FF7,
1082
  PREFIX_0F38D8,
1083
  PREFIX_0F38DC,
1084
  PREFIX_0F38DD,
1085
  PREFIX_0F38DE,
1086
  PREFIX_0F38DF,
1087
  PREFIX_0F38F0,
1088
  PREFIX_0F38F1,
1089
  PREFIX_0F38F6,
1090
  PREFIX_0F38F8_M_0,
1091
  PREFIX_0F38F8_M_1_X86_64,
1092
  PREFIX_0F38FA,
1093
  PREFIX_0F38FB,
1094
  PREFIX_0F38FC,
1095
  PREFIX_0F3A0F,
1096
  PREFIX_VEX_0F12,
1097
  PREFIX_VEX_0F16,
1098
  PREFIX_VEX_0F2A,
1099
  PREFIX_VEX_0F2C,
1100
  PREFIX_VEX_0F2D,
1101
  PREFIX_VEX_0F41_L_1_W_0,
1102
  PREFIX_VEX_0F41_L_1_W_1,
1103
  PREFIX_VEX_0F42_L_1_W_0,
1104
  PREFIX_VEX_0F42_L_1_W_1,
1105
  PREFIX_VEX_0F44_L_0_W_0,
1106
  PREFIX_VEX_0F44_L_0_W_1,
1107
  PREFIX_VEX_0F45_L_1_W_0,
1108
  PREFIX_VEX_0F45_L_1_W_1,
1109
  PREFIX_VEX_0F46_L_1_W_0,
1110
  PREFIX_VEX_0F46_L_1_W_1,
1111
  PREFIX_VEX_0F47_L_1_W_0,
1112
  PREFIX_VEX_0F47_L_1_W_1,
1113
  PREFIX_VEX_0F4A_L_1_W_0,
1114
  PREFIX_VEX_0F4A_L_1_W_1,
1115
  PREFIX_VEX_0F4B_L_1_W_0,
1116
  PREFIX_VEX_0F4B_L_1_W_1,
1117
  PREFIX_VEX_0F6F,
1118
  PREFIX_VEX_0F70,
1119
  PREFIX_VEX_0F7E,
1120
  PREFIX_VEX_0F7F,
1121
  PREFIX_VEX_0F90_L_0_W_0,
1122
  PREFIX_VEX_0F90_L_0_W_1,
1123
  PREFIX_VEX_0F91_L_0_W_0,
1124
  PREFIX_VEX_0F91_L_0_W_1,
1125
  PREFIX_VEX_0F92_L_0_W_0,
1126
  PREFIX_VEX_0F92_L_0_W_1,
1127
  PREFIX_VEX_0F93_L_0_W_0,
1128
  PREFIX_VEX_0F93_L_0_W_1,
1129
  PREFIX_VEX_0F98_L_0_W_0,
1130
  PREFIX_VEX_0F98_L_0_W_1,
1131
  PREFIX_VEX_0F99_L_0_W_0,
1132
  PREFIX_VEX_0F99_L_0_W_1,
1133
  PREFIX_VEX_0F3848_X86_64_L_0_W_0,
1134
  PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_0,
1135
  PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_1,
1136
  PREFIX_VEX_0F384A_X86_64_W_0_L_0,
1137
  PREFIX_VEX_0F384B_X86_64_L_0_W_0,
1138
  PREFIX_VEX_0F3850_W_0,
1139
  PREFIX_VEX_0F3851_W_0,
1140
  PREFIX_VEX_0F385C_X86_64_L_0_W_0,
1141
  PREFIX_VEX_0F385E_X86_64_L_0_W_0,
1142
  PREFIX_VEX_0F385F_X86_64_L_0_W_0,
1143
  PREFIX_VEX_0F386B_X86_64_L_0_W_0,
1144
  PREFIX_VEX_0F386C_X86_64_L_0_W_0,
1145
  PREFIX_VEX_0F386E_X86_64_L_0_W_0,
1146
  PREFIX_VEX_0F386F_X86_64_L_0_W_0,
1147
  PREFIX_VEX_0F3872,
1148
  PREFIX_VEX_0F38B0_W_0,
1149
  PREFIX_VEX_0F38B1_W_0,
1150
  PREFIX_VEX_0F38D2_W_0,
1151
  PREFIX_VEX_0F38D3_W_0,
1152
  PREFIX_VEX_0F38CB,
1153
  PREFIX_VEX_0F38CC,
1154
  PREFIX_VEX_0F38CD,
1155
  PREFIX_VEX_0F38DA_W_0,
1156
  PREFIX_VEX_0F38F2_L_0,
1157
  PREFIX_VEX_0F38F3_L_0,
1158
  PREFIX_VEX_0F38F5_L_0,
1159
  PREFIX_VEX_0F38F6_L_0,
1160
  PREFIX_VEX_0F38F7_L_0,
1161
  PREFIX_VEX_0F3AF0_L_0,
1162
  PREFIX_VEX_MAP5_F8_X86_64_L_0_W_0,
1163
  PREFIX_VEX_MAP5_F9_X86_64_L_0_W_0,
1164
  PREFIX_VEX_MAP5_FD_X86_64_L_0_W_0,
1165
  PREFIX_VEX_MAP7_F6_L_0_W_0_R_0_X86_64,
1166
  PREFIX_VEX_MAP7_F8_L_0_W_0_R_0_X86_64,
1167
1168
  PREFIX_EVEX_0F2E,
1169
  PREFIX_EVEX_0F2F,
1170
  PREFIX_EVEX_0F5B,
1171
  PREFIX_EVEX_0F6F,
1172
  PREFIX_EVEX_0F70,
1173
  PREFIX_EVEX_0F78,
1174
  PREFIX_EVEX_0F79,
1175
  PREFIX_EVEX_0F7A,
1176
  PREFIX_EVEX_0F7B,
1177
  PREFIX_EVEX_0F7E,
1178
  PREFIX_EVEX_0F7F,
1179
  PREFIX_EVEX_0FC2,
1180
  PREFIX_EVEX_0FE6,
1181
  PREFIX_EVEX_0F3810,
1182
  PREFIX_EVEX_0F3811,
1183
  PREFIX_EVEX_0F3812,
1184
  PREFIX_EVEX_0F3813,
1185
  PREFIX_EVEX_0F3814,
1186
  PREFIX_EVEX_0F3815,
1187
  PREFIX_EVEX_0F3820,
1188
  PREFIX_EVEX_0F3821,
1189
  PREFIX_EVEX_0F3822,
1190
  PREFIX_EVEX_0F3823,
1191
  PREFIX_EVEX_0F3824,
1192
  PREFIX_EVEX_0F3825,
1193
  PREFIX_EVEX_0F3826,
1194
  PREFIX_EVEX_0F3827,
1195
  PREFIX_EVEX_0F3828,
1196
  PREFIX_EVEX_0F3829,
1197
  PREFIX_EVEX_0F382A,
1198
  PREFIX_EVEX_0F3830,
1199
  PREFIX_EVEX_0F3831,
1200
  PREFIX_EVEX_0F3832,
1201
  PREFIX_EVEX_0F3833,
1202
  PREFIX_EVEX_0F3834,
1203
  PREFIX_EVEX_0F3835,
1204
  PREFIX_EVEX_0F3838,
1205
  PREFIX_EVEX_0F3839,
1206
  PREFIX_EVEX_0F383A,
1207
  PREFIX_EVEX_0F384A_X86_64_W_0_L_2,
1208
  PREFIX_EVEX_0F3852,
1209
  PREFIX_EVEX_0F3853,
1210
  PREFIX_EVEX_0F3868,
1211
  PREFIX_EVEX_0F386D_X86_64_W_0_L_2,
1212
  PREFIX_EVEX_0F3872,
1213
  PREFIX_EVEX_0F3874,
1214
  PREFIX_EVEX_0F389A,
1215
  PREFIX_EVEX_0F389B,
1216
  PREFIX_EVEX_0F38AA,
1217
  PREFIX_EVEX_0F38AB,
1218
1219
  PREFIX_EVEX_0F3A07_X86_64_W_0_L_2,
1220
  PREFIX_EVEX_0F3A08,
1221
  PREFIX_EVEX_0F3A0A,
1222
  PREFIX_EVEX_0F3A26,
1223
  PREFIX_EVEX_0F3A27,
1224
  PREFIX_EVEX_0F3A42_W_0,
1225
  PREFIX_EVEX_0F3A52,
1226
  PREFIX_EVEX_0F3A53,
1227
  PREFIX_EVEX_0F3A56,
1228
  PREFIX_EVEX_0F3A57,
1229
  PREFIX_EVEX_0F3A66,
1230
  PREFIX_EVEX_0F3A67,
1231
  PREFIX_EVEX_0F3A77_X86_64_W_0_L_2,
1232
  PREFIX_EVEX_0F3AC2,
1233
1234
  PREFIX_EVEX_MAP4_4x,
1235
  PREFIX_EVEX_MAP4_F0,
1236
  PREFIX_EVEX_MAP4_F1,
1237
  PREFIX_EVEX_MAP4_F2,
1238
  PREFIX_EVEX_MAP4_F8,
1239
1240
  PREFIX_EVEX_MAP5_10,
1241
  PREFIX_EVEX_MAP5_11,
1242
  PREFIX_EVEX_MAP5_18,
1243
  PREFIX_EVEX_MAP5_1B,
1244
  PREFIX_EVEX_MAP5_1D,
1245
  PREFIX_EVEX_MAP5_1E,
1246
  PREFIX_EVEX_MAP5_2A,
1247
  PREFIX_EVEX_MAP5_2C,
1248
  PREFIX_EVEX_MAP5_2D,
1249
  PREFIX_EVEX_MAP5_2E,
1250
  PREFIX_EVEX_MAP5_2F,
1251
  PREFIX_EVEX_MAP5_51,
1252
  PREFIX_EVEX_MAP5_58,
1253
  PREFIX_EVEX_MAP5_59,
1254
  PREFIX_EVEX_MAP5_5A,
1255
  PREFIX_EVEX_MAP5_5B,
1256
  PREFIX_EVEX_MAP5_5C,
1257
  PREFIX_EVEX_MAP5_5D,
1258
  PREFIX_EVEX_MAP5_5E,
1259
  PREFIX_EVEX_MAP5_5F,
1260
  PREFIX_EVEX_MAP5_68,
1261
  PREFIX_EVEX_MAP5_69,
1262
  PREFIX_EVEX_MAP5_6A,
1263
  PREFIX_EVEX_MAP5_6B,
1264
  PREFIX_EVEX_MAP5_6C,
1265
  PREFIX_EVEX_MAP5_6D,
1266
  PREFIX_EVEX_MAP5_6E_L_0,
1267
  PREFIX_EVEX_MAP5_6F_X86_64,
1268
  PREFIX_EVEX_MAP5_74,
1269
  PREFIX_EVEX_MAP5_78,
1270
  PREFIX_EVEX_MAP5_79,
1271
  PREFIX_EVEX_MAP5_7A,
1272
  PREFIX_EVEX_MAP5_7B,
1273
  PREFIX_EVEX_MAP5_7C,
1274
  PREFIX_EVEX_MAP5_7D,
1275
  PREFIX_EVEX_MAP5_7E_L_0,
1276
1277
  PREFIX_EVEX_MAP6_13,
1278
  PREFIX_EVEX_MAP6_2C,
1279
  PREFIX_EVEX_MAP6_42,
1280
  PREFIX_EVEX_MAP6_4C,
1281
  PREFIX_EVEX_MAP6_4E,
1282
  PREFIX_EVEX_MAP6_56,
1283
  PREFIX_EVEX_MAP6_57,
1284
  PREFIX_EVEX_MAP6_98,
1285
  PREFIX_EVEX_MAP6_9A,
1286
  PREFIX_EVEX_MAP6_9C,
1287
  PREFIX_EVEX_MAP6_9E,
1288
  PREFIX_EVEX_MAP6_A8,
1289
  PREFIX_EVEX_MAP6_AA,
1290
  PREFIX_EVEX_MAP6_AC,
1291
  PREFIX_EVEX_MAP6_AE,
1292
  PREFIX_EVEX_MAP6_B8,
1293
  PREFIX_EVEX_MAP6_BA,
1294
  PREFIX_EVEX_MAP6_BC,
1295
  PREFIX_EVEX_MAP6_BE,
1296
  PREFIX_EVEX_MAP6_D6,
1297
  PREFIX_EVEX_MAP6_D7,
1298
};
1299
1300
enum
1301
{
1302
  X86_64_06 = 0,
1303
  X86_64_07,
1304
  X86_64_0E,
1305
  X86_64_16,
1306
  X86_64_17,
1307
  X86_64_1E,
1308
  X86_64_1F,
1309
  X86_64_27,
1310
  X86_64_2F,
1311
  X86_64_37,
1312
  X86_64_3F,
1313
  X86_64_60,
1314
  X86_64_61,
1315
  X86_64_62,
1316
  X86_64_63,
1317
  X86_64_6D,
1318
  X86_64_6F,
1319
  X86_64_82,
1320
  X86_64_9A,
1321
  X86_64_C2,
1322
  X86_64_C3,
1323
  X86_64_C4,
1324
  X86_64_C5,
1325
  X86_64_CE,
1326
  X86_64_D4,
1327
  X86_64_D5,
1328
  X86_64_E8,
1329
  X86_64_E9,
1330
  X86_64_EA,
1331
  X86_64_0F00_REG_6,
1332
  X86_64_0F01_REG_0,
1333
  X86_64_0F01_REG_0_MOD_3_RM_6_P_1,
1334
  X86_64_0F01_REG_0_MOD_3_RM_6_P_3,
1335
  X86_64_0F01_REG_0_MOD_3_RM_7_P_0,
1336
  X86_64_0F01_REG_1,
1337
  X86_64_0F01_REG_1_RM_2_PREFIX_1,
1338
  X86_64_0F01_REG_1_RM_2_PREFIX_3,
1339
  X86_64_0F01_REG_1_RM_5_PREFIX_2,
1340
  X86_64_0F01_REG_1_RM_6_PREFIX_2,
1341
  X86_64_0F01_REG_1_RM_7_PREFIX_2,
1342
  X86_64_0F01_REG_2,
1343
  X86_64_0F01_REG_3,
1344
  X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1,
1345
  X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1,
1346
  X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1,
1347
  X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1,
1348
  X86_64_0F01_REG_7_MOD_3_RM_5_PREFIX_1,
1349
  X86_64_0F01_REG_7_MOD_3_RM_5_PREFIX_3,
1350
  X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1,
1351
  X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3,
1352
  X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1,
1353
  X86_64_0F18_REG_6_MOD_0,
1354
  X86_64_0F18_REG_7_MOD_0,
1355
  X86_64_0F24,
1356
  X86_64_0F26,
1357
  X86_64_0F388A,
1358
  X86_64_0F388B,
1359
  X86_64_0F38F8_M_1,
1360
  X86_64_0FC7_REG_6_MOD_3_PREFIX_1,
1361
1362
  X86_64_VEX_0F3848,
1363
  X86_64_VEX_0F3849,
1364
  X86_64_VEX_0F384A,
1365
  X86_64_VEX_0F384B,
1366
  X86_64_VEX_0F385C,
1367
  X86_64_VEX_0F385E,
1368
  X86_64_VEX_0F385F,
1369
  X86_64_VEX_0F386B,
1370
  X86_64_VEX_0F386C,
1371
  X86_64_VEX_0F386E,
1372
  X86_64_VEX_0F386F,
1373
  X86_64_VEX_0F38Ex,
1374
1375
  X86_64_VEX_MAP5_F8,
1376
  X86_64_VEX_MAP5_F9,
1377
  X86_64_VEX_MAP5_FD,
1378
  X86_64_VEX_MAP7_F6_L_0_W_0_R_0,
1379
  X86_64_VEX_MAP7_F8_L_0_W_0_R_0,
1380
1381
  X86_64_EVEX_0F384A,
1382
  X86_64_EVEX_0F386D,
1383
  X86_64_EVEX_0F3A07,
1384
  X86_64_EVEX_0F3A77,
1385
1386
  X86_64_EVEX_MAP5_6F,
1387
};
1388
1389
enum
1390
{
1391
  THREE_BYTE_0F38 = 0,
1392
  THREE_BYTE_0F3A
1393
};
1394
1395
enum
1396
{
1397
  XOP_08 = 0,
1398
  XOP_09,
1399
  XOP_0A
1400
};
1401
1402
enum
1403
{
1404
  VEX_0F = 0,
1405
  VEX_0F38,
1406
  VEX_0F3A,
1407
  VEX_MAP5,
1408
  VEX_MAP7,
1409
};
1410
1411
enum
1412
{
1413
  EVEX_0F = 0,
1414
  EVEX_0F38,
1415
  EVEX_0F3A,
1416
  EVEX_MAP4,
1417
  EVEX_MAP5,
1418
  EVEX_MAP6,
1419
  EVEX_MAP7,
1420
};
1421
1422
enum
1423
{
1424
  VEX_LEN_0F12_P_0 = 0,
1425
  VEX_LEN_0F12_P_2,
1426
  VEX_LEN_0F13,
1427
  VEX_LEN_0F16_P_0,
1428
  VEX_LEN_0F16_P_2,
1429
  VEX_LEN_0F17,
1430
  VEX_LEN_0F41,
1431
  VEX_LEN_0F42,
1432
  VEX_LEN_0F44,
1433
  VEX_LEN_0F45,
1434
  VEX_LEN_0F46,
1435
  VEX_LEN_0F47,
1436
  VEX_LEN_0F4A,
1437
  VEX_LEN_0F4B,
1438
  VEX_LEN_0F6E,
1439
  VEX_LEN_0F77,
1440
  VEX_LEN_0F7E_P_1,
1441
  VEX_LEN_0F7E_P_2,
1442
  VEX_LEN_0F90,
1443
  VEX_LEN_0F91,
1444
  VEX_LEN_0F92,
1445
  VEX_LEN_0F93,
1446
  VEX_LEN_0F98,
1447
  VEX_LEN_0F99,
1448
  VEX_LEN_0FAE_R_2,
1449
  VEX_LEN_0FAE_R_3,
1450
  VEX_LEN_0FC4,
1451
  VEX_LEN_0FD6,
1452
  VEX_LEN_0F3816,
1453
  VEX_LEN_0F3819,
1454
  VEX_LEN_0F381A,
1455
  VEX_LEN_0F3836,
1456
  VEX_LEN_0F3841,
1457
  VEX_LEN_0F3848_X86_64,
1458
  VEX_LEN_0F3849_X86_64,
1459
  VEX_LEN_0F384A_X86_64_W_0,
1460
  VEX_LEN_0F384B_X86_64,
1461
  VEX_LEN_0F385A,
1462
  VEX_LEN_0F385C_X86_64,
1463
  VEX_LEN_0F385E_X86_64,
1464
  VEX_LEN_0F385F_X86_64,
1465
  VEX_LEN_0F386B_X86_64,
1466
  VEX_LEN_0F386C_X86_64,
1467
  VEX_LEN_0F386E_X86_64,
1468
  VEX_LEN_0F386F_X86_64,
1469
  VEX_LEN_0F38CB_P_3_W_0,
1470
  VEX_LEN_0F38CC_P_3_W_0,
1471
  VEX_LEN_0F38CD_P_3_W_0,
1472
  VEX_LEN_0F38DA_W_0_P_0,
1473
  VEX_LEN_0F38DA_W_0_P_2,
1474
  VEX_LEN_0F38DB,
1475
  VEX_LEN_0F38F2,
1476
  VEX_LEN_0F38F3,
1477
  VEX_LEN_0F38F5,
1478
  VEX_LEN_0F38F6,
1479
  VEX_LEN_0F38F7,
1480
  VEX_LEN_0F3A00,
1481
  VEX_LEN_0F3A01,
1482
  VEX_LEN_0F3A06,
1483
  VEX_LEN_0F3A14,
1484
  VEX_LEN_0F3A15,
1485
  VEX_LEN_0F3A16,
1486
  VEX_LEN_0F3A17,
1487
  VEX_LEN_0F3A18,
1488
  VEX_LEN_0F3A19,
1489
  VEX_LEN_0F3A20,
1490
  VEX_LEN_0F3A21,
1491
  VEX_LEN_0F3A22,
1492
  VEX_LEN_0F3A30,
1493
  VEX_LEN_0F3A31,
1494
  VEX_LEN_0F3A32,
1495
  VEX_LEN_0F3A33,
1496
  VEX_LEN_0F3A38,
1497
  VEX_LEN_0F3A39,
1498
  VEX_LEN_0F3A41,
1499
  VEX_LEN_0F3A46,
1500
  VEX_LEN_0F3A60,
1501
  VEX_LEN_0F3A61,
1502
  VEX_LEN_0F3A62,
1503
  VEX_LEN_0F3A63,
1504
  VEX_LEN_0F3ADE_W_0,
1505
  VEX_LEN_0F3ADF,
1506
  VEX_LEN_0F3AF0,
1507
  VEX_LEN_MAP5_F8_X86_64,
1508
  VEX_LEN_MAP5_F9_X86_64,
1509
  VEX_LEN_MAP5_FD_X86_64,
1510
  VEX_LEN_MAP7_F6,
1511
  VEX_LEN_MAP7_F8,
1512
  VEX_LEN_XOP_08_85,
1513
  VEX_LEN_XOP_08_86,
1514
  VEX_LEN_XOP_08_87,
1515
  VEX_LEN_XOP_08_8E,
1516
  VEX_LEN_XOP_08_8F,
1517
  VEX_LEN_XOP_08_95,
1518
  VEX_LEN_XOP_08_96,
1519
  VEX_LEN_XOP_08_97,
1520
  VEX_LEN_XOP_08_9E,
1521
  VEX_LEN_XOP_08_9F,
1522
  VEX_LEN_XOP_08_A3,
1523
  VEX_LEN_XOP_08_A6,
1524
  VEX_LEN_XOP_08_B6,
1525
  VEX_LEN_XOP_08_C0,
1526
  VEX_LEN_XOP_08_C1,
1527
  VEX_LEN_XOP_08_C2,
1528
  VEX_LEN_XOP_08_C3,
1529
  VEX_LEN_XOP_08_CC,
1530
  VEX_LEN_XOP_08_CD,
1531
  VEX_LEN_XOP_08_CE,
1532
  VEX_LEN_XOP_08_CF,
1533
  VEX_LEN_XOP_08_EC,
1534
  VEX_LEN_XOP_08_ED,
1535
  VEX_LEN_XOP_08_EE,
1536
  VEX_LEN_XOP_08_EF,
1537
  VEX_LEN_XOP_09_01,
1538
  VEX_LEN_XOP_09_02,
1539
  VEX_LEN_XOP_09_12,
1540
  VEX_LEN_XOP_09_82_W_0,
1541
  VEX_LEN_XOP_09_83_W_0,
1542
  VEX_LEN_XOP_09_90,
1543
  VEX_LEN_XOP_09_91,
1544
  VEX_LEN_XOP_09_92,
1545
  VEX_LEN_XOP_09_93,
1546
  VEX_LEN_XOP_09_94,
1547
  VEX_LEN_XOP_09_95,
1548
  VEX_LEN_XOP_09_96,
1549
  VEX_LEN_XOP_09_97,
1550
  VEX_LEN_XOP_09_98,
1551
  VEX_LEN_XOP_09_99,
1552
  VEX_LEN_XOP_09_9A,
1553
  VEX_LEN_XOP_09_9B,
1554
  VEX_LEN_XOP_09_C1,
1555
  VEX_LEN_XOP_09_C2,
1556
  VEX_LEN_XOP_09_C3,
1557
  VEX_LEN_XOP_09_C6,
1558
  VEX_LEN_XOP_09_C7,
1559
  VEX_LEN_XOP_09_CB,
1560
  VEX_LEN_XOP_09_D1,
1561
  VEX_LEN_XOP_09_D2,
1562
  VEX_LEN_XOP_09_D3,
1563
  VEX_LEN_XOP_09_D6,
1564
  VEX_LEN_XOP_09_D7,
1565
  VEX_LEN_XOP_09_DB,
1566
  VEX_LEN_XOP_09_E1,
1567
  VEX_LEN_XOP_09_E2,
1568
  VEX_LEN_XOP_09_E3,
1569
  VEX_LEN_XOP_0A_12,
1570
};
1571
1572
enum
1573
{
1574
  EVEX_LEN_0F7E_P_1_W_0 = 0,
1575
  EVEX_LEN_0FD6_P_2_W_0,
1576
  EVEX_LEN_0F3816,
1577
  EVEX_LEN_0F3819,
1578
  EVEX_LEN_0F381A,
1579
  EVEX_LEN_0F381B,
1580
  EVEX_LEN_0F3836,
1581
  EVEX_LEN_0F384A_X86_64_W_0,
1582
  EVEX_LEN_0F385A,
1583
  EVEX_LEN_0F385B,
1584
  EVEX_LEN_0F386D_X86_64_W_0,
1585
  EVEX_LEN_0F38C6,
1586
  EVEX_LEN_0F38C7,
1587
  EVEX_LEN_0F3A00,
1588
  EVEX_LEN_0F3A01,
1589
  EVEX_LEN_0F3A07_X86_64_W_0,
1590
  EVEX_LEN_0F3A18,
1591
  EVEX_LEN_0F3A19,
1592
  EVEX_LEN_0F3A1A,
1593
  EVEX_LEN_0F3A1B,
1594
  EVEX_LEN_0F3A23,
1595
  EVEX_LEN_0F3A38,
1596
  EVEX_LEN_0F3A39,
1597
  EVEX_LEN_0F3A3A,
1598
  EVEX_LEN_0F3A3B,
1599
  EVEX_LEN_0F3A43,
1600
  EVEX_LEN_0F3A77_X86_64_W_0,
1601
1602
  EVEX_LEN_MAP5_6E,
1603
  EVEX_LEN_MAP5_7E,
1604
};
1605
1606
enum
1607
{
1608
  VEX_W_0F41_L_1 = 0,
1609
  VEX_W_0F42_L_1,
1610
  VEX_W_0F44_L_0,
1611
  VEX_W_0F45_L_1,
1612
  VEX_W_0F46_L_1,
1613
  VEX_W_0F47_L_1,
1614
  VEX_W_0F4A_L_1,
1615
  VEX_W_0F4B_L_1,
1616
  VEX_W_0F90_L_0,
1617
  VEX_W_0F91_L_0,
1618
  VEX_W_0F92_L_0,
1619
  VEX_W_0F93_L_0,
1620
  VEX_W_0F98_L_0,
1621
  VEX_W_0F99_L_0,
1622
  VEX_W_0F380C,
1623
  VEX_W_0F380D,
1624
  VEX_W_0F380E,
1625
  VEX_W_0F380F,
1626
  VEX_W_0F3813,
1627
  VEX_W_0F3816_L_1,
1628
  VEX_W_0F3818,
1629
  VEX_W_0F3819_L_1,
1630
  VEX_W_0F381A_L_1,
1631
  VEX_W_0F382C,
1632
  VEX_W_0F382D,
1633
  VEX_W_0F382E,
1634
  VEX_W_0F382F,
1635
  VEX_W_0F3836,
1636
  VEX_W_0F3846,
1637
  VEX_W_0F3848_X86_64_L_0,
1638
  VEX_W_0F3849_X86_64_L_0,
1639
  VEX_W_0F384A_X86_64,
1640
  VEX_W_0F384B_X86_64_L_0,
1641
  VEX_W_0F3850,
1642
  VEX_W_0F3851,
1643
  VEX_W_0F3852,
1644
  VEX_W_0F3853,
1645
  VEX_W_0F3858,
1646
  VEX_W_0F3859,
1647
  VEX_W_0F385A_L_0,
1648
  VEX_W_0F385C_X86_64_L_0,
1649
  VEX_W_0F385E_X86_64_L_0,
1650
  VEX_W_0F385F_X86_64_L_0,
1651
  VEX_W_0F386B_X86_64_L_0,
1652
  VEX_W_0F386C_X86_64_L_0,
1653
  VEX_W_0F386E_X86_64_L_0,
1654
  VEX_W_0F386F_X86_64_L_0,
1655
  VEX_W_0F3872_P_1,
1656
  VEX_W_0F3878,
1657
  VEX_W_0F3879,
1658
  VEX_W_0F38B0,
1659
  VEX_W_0F38B1,
1660
  VEX_W_0F38B4,
1661
  VEX_W_0F38B5,
1662
  VEX_W_0F38CB_P_3,
1663
  VEX_W_0F38CC_P_3,
1664
  VEX_W_0F38CD_P_3,
1665
  VEX_W_0F38CF,
1666
  VEX_W_0F38D2,
1667
  VEX_W_0F38D3,
1668
  VEX_W_0F38DA,
1669
  VEX_W_0F3A00_L_1,
1670
  VEX_W_0F3A01_L_1,
1671
  VEX_W_0F3A02,
1672
  VEX_W_0F3A04,
1673
  VEX_W_0F3A05,
1674
  VEX_W_0F3A06_L_1,
1675
  VEX_W_0F3A18_L_1,
1676
  VEX_W_0F3A19_L_1,
1677
  VEX_W_0F3A1D,
1678
  VEX_W_0F3A38_L_1,
1679
  VEX_W_0F3A39_L_1,
1680
  VEX_W_0F3A46_L_1,
1681
  VEX_W_0F3A4A,
1682
  VEX_W_0F3A4B,
1683
  VEX_W_0F3A4C,
1684
  VEX_W_0F3ACE,
1685
  VEX_W_0F3ACF,
1686
  VEX_W_0F3ADE,
1687
  VEX_W_MAP5_F8_X86_64_L_0,
1688
  VEX_W_MAP5_F9_X86_64_L_0,
1689
  VEX_W_MAP5_FD_X86_64_L_0,
1690
  VEX_W_MAP7_F6_L_0,
1691
  VEX_W_MAP7_F8_L_0,
1692
1693
  VEX_W_XOP_08_85_L_0,
1694
  VEX_W_XOP_08_86_L_0,
1695
  VEX_W_XOP_08_87_L_0,
1696
  VEX_W_XOP_08_8E_L_0,
1697
  VEX_W_XOP_08_8F_L_0,
1698
  VEX_W_XOP_08_95_L_0,
1699
  VEX_W_XOP_08_96_L_0,
1700
  VEX_W_XOP_08_97_L_0,
1701
  VEX_W_XOP_08_9E_L_0,
1702
  VEX_W_XOP_08_9F_L_0,
1703
  VEX_W_XOP_08_A6_L_0,
1704
  VEX_W_XOP_08_B6_L_0,
1705
  VEX_W_XOP_08_C0_L_0,
1706
  VEX_W_XOP_08_C1_L_0,
1707
  VEX_W_XOP_08_C2_L_0,
1708
  VEX_W_XOP_08_C3_L_0,
1709
  VEX_W_XOP_08_CC_L_0,
1710
  VEX_W_XOP_08_CD_L_0,
1711
  VEX_W_XOP_08_CE_L_0,
1712
  VEX_W_XOP_08_CF_L_0,
1713
  VEX_W_XOP_08_EC_L_0,
1714
  VEX_W_XOP_08_ED_L_0,
1715
  VEX_W_XOP_08_EE_L_0,
1716
  VEX_W_XOP_08_EF_L_0,
1717
1718
  VEX_W_XOP_09_80,
1719
  VEX_W_XOP_09_81,
1720
  VEX_W_XOP_09_82,
1721
  VEX_W_XOP_09_83,
1722
  VEX_W_XOP_09_C1_L_0,
1723
  VEX_W_XOP_09_C2_L_0,
1724
  VEX_W_XOP_09_C3_L_0,
1725
  VEX_W_XOP_09_C6_L_0,
1726
  VEX_W_XOP_09_C7_L_0,
1727
  VEX_W_XOP_09_CB_L_0,
1728
  VEX_W_XOP_09_D1_L_0,
1729
  VEX_W_XOP_09_D2_L_0,
1730
  VEX_W_XOP_09_D3_L_0,
1731
  VEX_W_XOP_09_D6_L_0,
1732
  VEX_W_XOP_09_D7_L_0,
1733
  VEX_W_XOP_09_DB_L_0,
1734
  VEX_W_XOP_09_E1_L_0,
1735
  VEX_W_XOP_09_E2_L_0,
1736
  VEX_W_XOP_09_E3_L_0,
1737
1738
  EVEX_W_0F5B_P_0,
1739
  EVEX_W_0F62,
1740
  EVEX_W_0F66,
1741
  EVEX_W_0F6A,
1742
  EVEX_W_0F6B,
1743
  EVEX_W_0F6C,
1744
  EVEX_W_0F6D,
1745
  EVEX_W_0F6F_P_1,
1746
  EVEX_W_0F6F_P_2,
1747
  EVEX_W_0F6F_P_3,
1748
  EVEX_W_0F70_P_2,
1749
  EVEX_W_0F72_R_2,
1750
  EVEX_W_0F72_R_4,
1751
  EVEX_W_0F72_R_6,
1752
  EVEX_W_0F73_R_2,
1753
  EVEX_W_0F73_R_6,
1754
  EVEX_W_0F76,
1755
  EVEX_W_0F78_P_0,
1756
  EVEX_W_0F78_P_2,
1757
  EVEX_W_0F79_P_0,
1758
  EVEX_W_0F79_P_2,
1759
  EVEX_W_0F7A_P_1,
1760
  EVEX_W_0F7A_P_2,
1761
  EVEX_W_0F7A_P_3,
1762
  EVEX_W_0F7B_P_2,
1763
  EVEX_W_0F7E_P_1,
1764
  EVEX_W_0F7F_P_1,
1765
  EVEX_W_0F7F_P_2,
1766
  EVEX_W_0F7F_P_3,
1767
  EVEX_W_0FD2,
1768
  EVEX_W_0FD3,
1769
  EVEX_W_0FD4,
1770
  EVEX_W_0FD6,
1771
  EVEX_W_0FE2,
1772
  EVEX_W_0FE6_P_1,
1773
  EVEX_W_0FE7,
1774
  EVEX_W_0FF2,
1775
  EVEX_W_0FF3,
1776
  EVEX_W_0FF4,
1777
  EVEX_W_0FFA,
1778
  EVEX_W_0FFB,
1779
  EVEX_W_0FFE,
1780
1781
  EVEX_W_0F3810_P_1,
1782
  EVEX_W_0F3810_P_2,
1783
  EVEX_W_0F3811_P_1,
1784
  EVEX_W_0F3811_P_2,
1785
  EVEX_W_0F3812_P_1,
1786
  EVEX_W_0F3812_P_2,
1787
  EVEX_W_0F3813_P_1,
1788
  EVEX_W_0F3814_P_1,
1789
  EVEX_W_0F3815_P_1,
1790
  EVEX_W_0F3819_L_n,
1791
  EVEX_W_0F381A_L_n,
1792
  EVEX_W_0F381B_L_2,
1793
  EVEX_W_0F381E,
1794
  EVEX_W_0F381F,
1795
  EVEX_W_0F3820_P_1,
1796
  EVEX_W_0F3821_P_1,
1797
  EVEX_W_0F3822_P_1,
1798
  EVEX_W_0F3823_P_1,
1799
  EVEX_W_0F3824_P_1,
1800
  EVEX_W_0F3825_P_1,
1801
  EVEX_W_0F3825_P_2,
1802
  EVEX_W_0F3828_P_2,
1803
  EVEX_W_0F3829_P_2,
1804
  EVEX_W_0F382A_P_1,
1805
  EVEX_W_0F382A_P_2,
1806
  EVEX_W_0F382B,
1807
  EVEX_W_0F3830_P_1,
1808
  EVEX_W_0F3831_P_1,
1809
  EVEX_W_0F3832_P_1,
1810
  EVEX_W_0F3833_P_1,
1811
  EVEX_W_0F3834_P_1,
1812
  EVEX_W_0F3835_P_1,
1813
  EVEX_W_0F3835_P_2,
1814
  EVEX_W_0F3837,
1815
  EVEX_W_0F383A_P_1,
1816
  EVEX_W_0F384A_X86_64,
1817
  EVEX_W_0F3859,
1818
  EVEX_W_0F385A_L_n,
1819
  EVEX_W_0F385B_L_2,
1820
  EVEX_W_0F386D_X86_64,
1821
  EVEX_W_0F3870,
1822
  EVEX_W_0F3872_P_2,
1823
  EVEX_W_0F387A,
1824
  EVEX_W_0F387B,
1825
  EVEX_W_0F3883,
1826
1827
  EVEX_W_0F3A07_X86_64,
1828
  EVEX_W_0F3A18_L_n,
1829
  EVEX_W_0F3A19_L_n,
1830
  EVEX_W_0F3A1A_L_2,
1831
  EVEX_W_0F3A1B_L_2,
1832
  EVEX_W_0F3A21,
1833
  EVEX_W_0F3A23_L_n,
1834
  EVEX_W_0F3A38_L_n,
1835
  EVEX_W_0F3A39_L_n,
1836
  EVEX_W_0F3A3A_L_2,
1837
  EVEX_W_0F3A3B_L_2,
1838
  EVEX_W_0F3A42,
1839
  EVEX_W_0F3A43_L_n,
1840
  EVEX_W_0F3A70,
1841
  EVEX_W_0F3A72,
1842
  EVEX_W_0F3A77_X86_64,
1843
1844
  EVEX_W_MAP4_8F_R_0,
1845
  EVEX_W_MAP4_F8_P1_M_1,
1846
  EVEX_W_MAP4_F8_P3_M_1,
1847
  EVEX_W_MAP4_FF_R_6,
1848
1849
  EVEX_W_MAP5_5B_P_0,
1850
  EVEX_W_MAP5_6C_P_0,
1851
  EVEX_W_MAP5_6C_P_2,
1852
  EVEX_W_MAP5_6D_P_0,
1853
  EVEX_W_MAP5_6D_P_2,
1854
  EVEX_W_MAP5_6E_P_1,
1855
  EVEX_W_MAP5_7A_P_3,
1856
  EVEX_W_MAP5_7E_P_1,
1857
};
1858
1859
typedef bool (*op_rtn) (instr_info *ins, int bytemode, int sizeflag);
1860
1861
struct dis386 {
1862
  const char *name;
1863
  struct
1864
    {
1865
      op_rtn rtn;
1866
      int bytemode;
1867
    } op[MAX_OPERANDS];
1868
  unsigned int prefix_requirement;
1869
};
1870
1871
/* Upper case letters in the instruction names here are macros.
1872
   'A' => print 'b' if no (suitable) register operand or suffix_always is true
1873
   'B' => print 'b' if suffix_always is true
1874
   'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
1875
    size prefix
1876
   'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
1877
    suffix_always is true
1878
   'E' => print 'e' if 32-bit form of jcxz
1879
   'F' => print 'w' or 'l' depending on address size prefix (loop insns)
1880
   'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
1881
   'H' => print ",pt" or ",pn" branch hint
1882
   'I' unused.
1883
   'J' unused.
1884
   'K' => print 'd' or 'q' if rex prefix is present.
1885
   'L' => print 'l' or 'q' if suffix_always is true
1886
   'M' => print 'r' if intel_mnemonic is false.
1887
   'N' => print 'n' if instruction has no wait "prefix"
1888
   'O' => print 'd' or 'o' (or 'q' in Intel mode)
1889
   'P' => behave as 'T' except with register operand outside of suffix_always
1890
    mode
1891
   'Q' => print 'w', 'l' or 'q' if no (suitable) register operand or
1892
    suffix_always is true
1893
   'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
1894
   'S' => print 'w', 'l' or 'q' if suffix_always is true
1895
   'T' => print 'w', 'l'/'d', or 'q' if instruction has an operand size
1896
    prefix or if suffix_always is true.
1897
   'U' unused.
1898
   'V' => print 'v' for VEX/EVEX and nothing for legacy encodings.
1899
   'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
1900
   'X' => print 's', 'd' depending on data16 prefix (for XMM)
1901
   'Y' => no output, mark EVEX.aaa != 0 as bad.
1902
   'Z' => print 'q' in 64bit mode and 'l' otherwise, if suffix_always is true.
1903
   '!' => change condition from true to false or from false to true.
1904
   '%' => add 1 upper case letter to the macro.
1905
   '^' => print 'w', 'l', or 'q' (Intel64 ISA only) depending on operand size
1906
    prefix or suffix_always is true (lcall/ljmp).
1907
   '@' => in 64bit mode for Intel64 ISA or if instruction
1908
    has no operand sizing prefix, print 'q' if suffix_always is true or
1909
    nothing otherwise; behave as 'P' in all other cases
1910
1911
   2 upper case letter macros:
1912
   "CC" => print condition code
1913
   "XY" => print 'x' or 'y' if suffix_always is true or no register
1914
     operands and no broadcast.
1915
   "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
1916
     register operands and no broadcast.
1917
   "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
1918
   "XD" => print 'd' if !EVEX or EVEX.W=1, EVEX.W=0 is not a valid encoding
1919
   "XH" => print 'h' if EVEX.W=0, EVEX.W=1 is not a valid encoding (for FP16)
1920
   "XB" => print 'bf16' if EVEX.W=0, EVEX.W=1 is not a valid encoding
1921
     (for BF16)
1922
   "XS" => print 's' if !EVEX or EVEX.W=0, EVEX.W=1 is not a valid encoding
1923
   "XV" => print "{vex} " pseudo prefix
1924
   "XE" => print "{evex} " pseudo prefix if no EVEX-specific functionality is
1925
     is used by an EVEX-encoded (AVX512VL) instruction.
1926
   "ME" => Similar to "XE", but only print "{evex} " when there is no
1927
     memory operand.
1928
   "NF" => print "{nf} " pseudo prefix when EVEX.NF = 1 and print "{evex} "
1929
     pseudo prefix when instructions without NF, EGPR and VVVV,
1930
   "NE" => don't print "{evex} " pseudo prefix for some special instructions
1931
     in MAP4.
1932
   "ZU" => print 'zu' if EVEX.ZU=1.
1933
   "SC" => print suffix SCC for SCC insns
1934
   "YK" keep unused, to avoid ambiguity with the combined use of Y and K.
1935
   "YX" keep unused, to avoid ambiguity with the combined use of Y and X.
1936
   "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand, cond
1937
     being false, or no operand at all in 64bit mode, or if suffix_always
1938
     is true.
1939
   "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
1940
   "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
1941
   "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
1942
   "DQ" => print 'd' or 'q' depending on the VEX.W bit
1943
   "DF" => print default flag value for SCC insns
1944
   "BW" => print 'b' or 'w' depending on the VEX.W bit
1945
   "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
1946
     an operand size prefix, or suffix_always is true.  print
1947
     'q' if rex prefix is present.
1948
1949
   Many of the above letters print nothing in Intel mode.  See "putop"
1950
   for the details.
1951
1952
   Braces '{' and '}', and vertical bars '|', indicate alternative
1953
   mnemonic strings for AT&T and Intel.  */
1954
1955
static const struct dis386 dis386[] = {
1956
  /* 00 */
1957
  { "addB",   { Ebh1, Gb }, 0 },
1958
  { "addS",   { Evh1, Gv }, 0 },
1959
  { "addB",   { Gb, EbS }, 0 },
1960
  { "addS",   { Gv, EvS }, 0 },
1961
  { "addB",   { AL, Ib }, 0 },
1962
  { "addS",   { eAX, Iv }, 0 },
1963
  { X86_64_TABLE (X86_64_06) },
1964
  { X86_64_TABLE (X86_64_07) },
1965
  /* 08 */
1966
  { "orB",    { Ebh1, Gb }, 0 },
1967
  { "orS",    { Evh1, Gv }, 0 },
1968
  { "orB",    { Gb, EbS }, 0 },
1969
  { "orS",    { Gv, EvS }, 0 },
1970
  { "orB",    { AL, Ib }, 0 },
1971
  { "orS",    { eAX, Iv }, 0 },
1972
  { X86_64_TABLE (X86_64_0E) },
1973
  { Bad_Opcode }, /* 0x0f extended opcode escape */
1974
  /* 10 */
1975
  { "adcB",   { Ebh1, Gb }, 0 },
1976
  { "adcS",   { Evh1, Gv }, 0 },
1977
  { "adcB",   { Gb, EbS }, 0 },
1978
  { "adcS",   { Gv, EvS }, 0 },
1979
  { "adcB",   { AL, Ib }, 0 },
1980
  { "adcS",   { eAX, Iv }, 0 },
1981
  { X86_64_TABLE (X86_64_16) },
1982
  { X86_64_TABLE (X86_64_17) },
1983
  /* 18 */
1984
  { "sbbB",   { Ebh1, Gb }, 0 },
1985
  { "sbbS",   { Evh1, Gv }, 0 },
1986
  { "sbbB",   { Gb, EbS }, 0 },
1987
  { "sbbS",   { Gv, EvS }, 0 },
1988
  { "sbbB",   { AL, Ib }, 0 },
1989
  { "sbbS",   { eAX, Iv }, 0 },
1990
  { X86_64_TABLE (X86_64_1E) },
1991
  { X86_64_TABLE (X86_64_1F) },
1992
  /* 20 */
1993
  { "andB",   { Ebh1, Gb }, 0 },
1994
  { "andS",   { Evh1, Gv }, 0 },
1995
  { "andB",   { Gb, EbS }, 0 },
1996
  { "andS",   { Gv, EvS }, 0 },
1997
  { "andB",   { AL, Ib }, 0 },
1998
  { "andS",   { eAX, Iv }, 0 },
1999
  { Bad_Opcode }, /* SEG ES prefix */
2000
  { X86_64_TABLE (X86_64_27) },
2001
  /* 28 */
2002
  { "subB",   { Ebh1, Gb }, 0 },
2003
  { "subS",   { Evh1, Gv }, 0 },
2004
  { "subB",   { Gb, EbS }, 0 },
2005
  { "subS",   { Gv, EvS }, 0 },
2006
  { "subB",   { AL, Ib }, 0 },
2007
  { "subS",   { eAX, Iv }, 0 },
2008
  { Bad_Opcode }, /* SEG CS prefix */
2009
  { X86_64_TABLE (X86_64_2F) },
2010
  /* 30 */
2011
  { "xorB",   { Ebh1, Gb }, 0 },
2012
  { "xorS",   { Evh1, Gv }, 0 },
2013
  { "xorB",   { Gb, EbS }, 0 },
2014
  { "xorS",   { Gv, EvS }, 0 },
2015
  { "xorB",   { AL, Ib }, 0 },
2016
  { "xorS",   { eAX, Iv }, 0 },
2017
  { Bad_Opcode }, /* SEG SS prefix */
2018
  { X86_64_TABLE (X86_64_37) },
2019
  /* 38 */
2020
  { "cmpB",   { Eb, Gb }, 0 },
2021
  { "cmpS",   { Ev, Gv }, 0 },
2022
  { "cmpB",   { Gb, EbS }, 0 },
2023
  { "cmpS",   { Gv, EvS }, 0 },
2024
  { "cmpB",   { AL, Ib }, 0 },
2025
  { "cmpS",   { eAX, Iv }, 0 },
2026
  { Bad_Opcode }, /* SEG DS prefix */
2027
  { X86_64_TABLE (X86_64_3F) },
2028
  /* 40 */
2029
  { "inc{S|}",    { RMeAX }, 0 },
2030
  { "inc{S|}",    { RMeCX }, 0 },
2031
  { "inc{S|}",    { RMeDX }, 0 },
2032
  { "inc{S|}",    { RMeBX }, 0 },
2033
  { "inc{S|}",    { RMeSP }, 0 },
2034
  { "inc{S|}",    { RMeBP }, 0 },
2035
  { "inc{S|}",    { RMeSI }, 0 },
2036
  { "inc{S|}",    { RMeDI }, 0 },
2037
  /* 48 */
2038
  { "dec{S|}",    { RMeAX }, 0 },
2039
  { "dec{S|}",    { RMeCX }, 0 },
2040
  { "dec{S|}",    { RMeDX }, 0 },
2041
  { "dec{S|}",    { RMeBX }, 0 },
2042
  { "dec{S|}",    { RMeSP }, 0 },
2043
  { "dec{S|}",    { RMeBP }, 0 },
2044
  { "dec{S|}",    { RMeSI }, 0 },
2045
  { "dec{S|}",    { RMeDI }, 0 },
2046
  /* 50 */
2047
  { "push!P",   { RMrAX }, 0 },
2048
  { "push!P",   { RMrCX }, 0 },
2049
  { "push!P",   { RMrDX }, 0 },
2050
  { "push!P",   { RMrBX }, 0 },
2051
  { "push!P",   { RMrSP }, 0 },
2052
  { "push!P",   { RMrBP }, 0 },
2053
  { "push!P",   { RMrSI }, 0 },
2054
  { "push!P",   { RMrDI }, 0 },
2055
  /* 58 */
2056
  { "pop!P",    { RMrAX }, 0 },
2057
  { "pop!P",    { RMrCX }, 0 },
2058
  { "pop!P",    { RMrDX }, 0 },
2059
  { "pop!P",    { RMrBX }, 0 },
2060
  { "pop!P",    { RMrSP }, 0 },
2061
  { "pop!P",    { RMrBP }, 0 },
2062
  { "pop!P",    { RMrSI }, 0 },
2063
  { "pop!P",    { RMrDI }, 0 },
2064
  /* 60 */
2065
  { X86_64_TABLE (X86_64_60) },
2066
  { X86_64_TABLE (X86_64_61) },
2067
  { X86_64_TABLE (X86_64_62) },
2068
  { X86_64_TABLE (X86_64_63) },
2069
  { Bad_Opcode }, /* seg fs */
2070
  { Bad_Opcode }, /* seg gs */
2071
  { Bad_Opcode }, /* op size prefix */
2072
  { Bad_Opcode }, /* adr size prefix */
2073
  /* 68 */
2074
  { "pushP",    { sIv }, 0 },
2075
  { "imulS",    { Gv, Ev, Iv }, 0 },
2076
  { "pushP",    { sIbT }, 0 },
2077
  { "imulS",    { Gv, Ev, sIb }, 0 },
2078
  { "ins{b|}",    { Ybr, indirDX }, 0 },
2079
  { X86_64_TABLE (X86_64_6D) },
2080
  { "outs{b|}",   { indirDXr, Xb }, 0 },
2081
  { X86_64_TABLE (X86_64_6F) },
2082
  /* 70 */
2083
  { "joH",    { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2084
  { "jnoH",   { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2085
  { "jbH",    { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2086
  { "jaeH",   { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2087
  { "jeH",    { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2088
  { "jneH",   { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2089
  { "jbeH",   { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2090
  { "jaH",    { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2091
  /* 78 */
2092
  { "jsH",    { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2093
  { "jnsH",   { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2094
  { "jpH",    { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2095
  { "jnpH",   { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2096
  { "jlH",    { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2097
  { "jgeH",   { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2098
  { "jleH",   { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2099
  { "jgH",    { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2100
  /* 80 */
2101
  { REG_TABLE (REG_80) },
2102
  { REG_TABLE (REG_81) },
2103
  { X86_64_TABLE (X86_64_82) },
2104
  { REG_TABLE (REG_83) },
2105
  { "testB",    { Eb, Gb }, 0 },
2106
  { "testS",    { Ev, Gv }, 0 },
2107
  { "xchgB",    { Ebh2, Gb }, 0 },
2108
  { "xchgS",    { Evh2, Gv }, 0 },
2109
  /* 88 */
2110
  { "movB",   { Ebh3, Gb }, 0 },
2111
  { "movS",   { Evh3, Gv }, 0 },
2112
  { "movB",   { Gb, EbS }, 0 },
2113
  { "movS",   { Gv, EvS }, 0 },
2114
  { "movD",   { Sv, Sw }, 0 },
2115
  { "leaS",   { Gv, M }, 0 },
2116
  { "movD",   { Sw, Sv }, 0 },
2117
  { REG_TABLE (REG_8F) },
2118
  /* 90 */
2119
  { PREFIX_TABLE (PREFIX_90) },
2120
  { "xchgS",    { RMeCX, eAX }, 0 },
2121
  { "xchgS",    { RMeDX, eAX }, 0 },
2122
  { "xchgS",    { RMeBX, eAX }, 0 },
2123
  { "xchgS",    { RMeSP, eAX }, 0 },
2124
  { "xchgS",    { RMeBP, eAX }, 0 },
2125
  { "xchgS",    { RMeSI, eAX }, 0 },
2126
  { "xchgS",    { RMeDI, eAX }, 0 },
2127
  /* 98 */
2128
  { "cW{t|}R",    { XX }, 0 },
2129
  { "cR{t|}O",    { XX }, 0 },
2130
  { X86_64_TABLE (X86_64_9A) },
2131
  { Bad_Opcode }, /* fwait */
2132
  { "pushfP",   { XX }, 0 },
2133
  { "popfP",    { XX }, 0 },
2134
  { "sahf",   { XX }, 0 },
2135
  { "lahf",   { XX }, 0 },
2136
  /* a0 */
2137
  { "mov%LB",   { AL, Ob }, PREFIX_REX2_ILLEGAL },
2138
  { "mov%LS",   { { JMPABS_Fixup, eAX_reg }, { JMPABS_Fixup, v_mode } }, PREFIX_REX2_ILLEGAL },
2139
  { "mov%LB",   { Ob, AL }, PREFIX_REX2_ILLEGAL },
2140
  { "mov%LS",   { Ov, eAX }, PREFIX_REX2_ILLEGAL },
2141
  { "movs{b|}",   { Ybr, Xb }, PREFIX_REX2_ILLEGAL },
2142
  { "movs{R|}",   { Yvr, Xv }, PREFIX_REX2_ILLEGAL },
2143
  { "cmps{b|}",   { Xb, Yb }, PREFIX_REX2_ILLEGAL },
2144
  { "cmps{R|}",   { Xv, Yv }, PREFIX_REX2_ILLEGAL },
2145
  /* a8 */
2146
  { "testB",    { AL, Ib }, PREFIX_REX2_ILLEGAL },
2147
  { "testS",    { eAX, Iv }, PREFIX_REX2_ILLEGAL },
2148
  { "stosB",    { Ybr, AL }, PREFIX_REX2_ILLEGAL },
2149
  { "stosS",    { Yvr, eAX }, PREFIX_REX2_ILLEGAL },
2150
  { "lodsB",    { ALr, Xb }, PREFIX_REX2_ILLEGAL },
2151
  { "lodsS",    { eAXr, Xv }, PREFIX_REX2_ILLEGAL },
2152
  { "scasB",    { AL, Yb }, PREFIX_REX2_ILLEGAL },
2153
  { "scasS",    { eAX, Yv }, PREFIX_REX2_ILLEGAL },
2154
  /* b0 */
2155
  { "movB",   { RMAL, Ib }, 0 },
2156
  { "movB",   { RMCL, Ib }, 0 },
2157
  { "movB",   { RMDL, Ib }, 0 },
2158
  { "movB",   { RMBL, Ib }, 0 },
2159
  { "movB",   { RMAH, Ib }, 0 },
2160
  { "movB",   { RMCH, Ib }, 0 },
2161
  { "movB",   { RMDH, Ib }, 0 },
2162
  { "movB",   { RMBH, Ib }, 0 },
2163
  /* b8 */
2164
  { "mov%LV",   { RMeAX, Iv64 }, 0 },
2165
  { "mov%LV",   { RMeCX, Iv64 }, 0 },
2166
  { "mov%LV",   { RMeDX, Iv64 }, 0 },
2167
  { "mov%LV",   { RMeBX, Iv64 }, 0 },
2168
  { "mov%LV",   { RMeSP, Iv64 }, 0 },
2169
  { "mov%LV",   { RMeBP, Iv64 }, 0 },
2170
  { "mov%LV",   { RMeSI, Iv64 }, 0 },
2171
  { "mov%LV",   { RMeDI, Iv64 }, 0 },
2172
  /* c0 */
2173
  { REG_TABLE (REG_C0) },
2174
  { REG_TABLE (REG_C1) },
2175
  { X86_64_TABLE (X86_64_C2) },
2176
  { X86_64_TABLE (X86_64_C3) },
2177
  { X86_64_TABLE (X86_64_C4) },
2178
  { X86_64_TABLE (X86_64_C5) },
2179
  { REG_TABLE (REG_C6) },
2180
  { REG_TABLE (REG_C7) },
2181
  /* c8 */
2182
  { "enterP",   { Iw, Ib }, 0 },
2183
  { "leaveP",   { XX }, 0 },
2184
  { "{l|}ret{|f}%LP", { Iw }, 0 },
2185
  { "{l|}ret{|f}%LP", { XX }, 0 },
2186
  { "int3",   { XX }, 0 },
2187
  { "int",    { Ib }, 0 },
2188
  { X86_64_TABLE (X86_64_CE) },
2189
  { "iret%LP",    { XX }, 0 },
2190
  /* d0 */
2191
  { REG_TABLE (REG_D0) },
2192
  { REG_TABLE (REG_D1) },
2193
  { REG_TABLE (REG_D2) },
2194
  { REG_TABLE (REG_D3) },
2195
  { X86_64_TABLE (X86_64_D4) },
2196
  { X86_64_TABLE (X86_64_D5) },
2197
  { Bad_Opcode },
2198
  { "xlat",   { DSBX }, 0 },
2199
  /* d8 */
2200
  { FLOAT },
2201
  { FLOAT },
2202
  { FLOAT },
2203
  { FLOAT },
2204
  { FLOAT },
2205
  { FLOAT },
2206
  { FLOAT },
2207
  { FLOAT },
2208
  /* e0 */
2209
  { "loopneFH",   { Jb, XX, loop_jcxz_flag }, PREFIX_REX2_ILLEGAL },
2210
  { "loopeFH",    { Jb, XX, loop_jcxz_flag }, PREFIX_REX2_ILLEGAL },
2211
  { "loopFH",   { Jb, XX, loop_jcxz_flag }, PREFIX_REX2_ILLEGAL },
2212
  { "jEcxzH",   { Jb, XX, loop_jcxz_flag }, PREFIX_REX2_ILLEGAL },
2213
  { "inB",    { AL, Ib }, PREFIX_REX2_ILLEGAL },
2214
  { "inG",    { zAX, Ib }, PREFIX_REX2_ILLEGAL },
2215
  { "outB",   { Ib, AL }, PREFIX_REX2_ILLEGAL },
2216
  { "outG",   { Ib, zAX }, PREFIX_REX2_ILLEGAL },
2217
  /* e8 */
2218
  { X86_64_TABLE (X86_64_E8) },
2219
  { X86_64_TABLE (X86_64_E9) },
2220
  { X86_64_TABLE (X86_64_EA) },
2221
  { "jmp",    { Jb, BND }, PREFIX_REX2_ILLEGAL },
2222
  { "inB",    { AL, indirDX }, PREFIX_REX2_ILLEGAL },
2223
  { "inG",    { zAX, indirDX }, PREFIX_REX2_ILLEGAL },
2224
  { "outB",   { indirDX, AL }, PREFIX_REX2_ILLEGAL },
2225
  { "outG",   { indirDX, zAX }, PREFIX_REX2_ILLEGAL },
2226
  /* f0 */
2227
  { Bad_Opcode }, /* lock prefix */
2228
  { "int1",   { XX }, 0 },
2229
  { Bad_Opcode }, /* repne */
2230
  { Bad_Opcode }, /* repz */
2231
  { "hlt",    { XX }, 0 },
2232
  { "cmc",    { XX }, 0 },
2233
  { REG_TABLE (REG_F6) },
2234
  { REG_TABLE (REG_F7) },
2235
  /* f8 */
2236
  { "clc",    { XX }, 0 },
2237
  { "stc",    { XX }, 0 },
2238
  { "cli",    { XX }, 0 },
2239
  { "sti",    { XX }, 0 },
2240
  { "cld",    { XX }, 0 },
2241
  { "std",    { XX }, 0 },
2242
  { REG_TABLE (REG_FE) },
2243
  { REG_TABLE (REG_FF) },
2244
};
2245
2246
static const struct dis386 dis386_twobyte[] = {
2247
  /* 00 */
2248
  { REG_TABLE (REG_0F00 ) },
2249
  { REG_TABLE (REG_0F01 ) },
2250
  { "larS",   { Gv, Sv }, 0 },
2251
  { "lslS",   { Gv, Sv }, 0 },
2252
  { Bad_Opcode },
2253
  { "syscall",    { XX }, 0 },
2254
  { "clts",   { XX }, 0 },
2255
  { "sysret%LQ",    { XX }, 0 },
2256
  /* 08 */
2257
  { "invd",   { XX }, 0 },
2258
  { PREFIX_TABLE (PREFIX_0F09) },
2259
  { Bad_Opcode },
2260
  { "ud2",    { XX }, 0 },
2261
  { Bad_Opcode },
2262
  { REG_TABLE (REG_0F0D) },
2263
  { "femms",    { XX }, 0 },
2264
  { "",     { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix.  */
2265
  /* 10 */
2266
  { PREFIX_TABLE (PREFIX_0F10) },
2267
  { PREFIX_TABLE (PREFIX_0F11) },
2268
  { PREFIX_TABLE (PREFIX_0F12) },
2269
  { "movlpX",   { Mq, XM }, PREFIX_OPCODE },
2270
  { "unpcklpX",   { XM, EXx }, PREFIX_OPCODE },
2271
  { "unpckhpX",   { XM, EXx }, PREFIX_OPCODE },
2272
  { PREFIX_TABLE (PREFIX_0F16) },
2273
  { "movhpX",   { Mq, XM }, PREFIX_OPCODE },
2274
  /* 18 */
2275
  { REG_TABLE (REG_0F18) },
2276
  { "nopQ",   { Ev }, 0 },
2277
  { PREFIX_TABLE (PREFIX_0F1A) },
2278
  { PREFIX_TABLE (PREFIX_0F1B) },
2279
  { PREFIX_TABLE (PREFIX_0F1C) },
2280
  { "nopQ",   { Ev }, 0 },
2281
  { PREFIX_TABLE (PREFIX_0F1E) },
2282
  { "nopQ",   { Ev }, 0 },
2283
  /* 20 */
2284
  { "movZ",   { Em, Cm }, 0 },
2285
  { "movZ",   { Em, Dm }, 0 },
2286
  { "movZ",   { Cm, Em }, 0 },
2287
  { "movZ",   { Dm, Em }, 0 },
2288
  { X86_64_TABLE (X86_64_0F24) },
2289
  { Bad_Opcode },
2290
  { X86_64_TABLE (X86_64_0F26) },
2291
  { Bad_Opcode },
2292
  /* 28 */
2293
  { "movapX",   { XM, EXx }, PREFIX_OPCODE },
2294
  { "movapX",   { EXxS, XM }, PREFIX_OPCODE },
2295
  { PREFIX_TABLE (PREFIX_0F2A) },
2296
  { PREFIX_TABLE (PREFIX_0F2B) },
2297
  { PREFIX_TABLE (PREFIX_0F2C) },
2298
  { PREFIX_TABLE (PREFIX_0F2D) },
2299
  { PREFIX_TABLE (PREFIX_0F2E) },
2300
  { PREFIX_TABLE (PREFIX_0F2F) },
2301
  /* 30 */
2302
  { "wrmsr",    { XX }, PREFIX_REX2_ILLEGAL },
2303
  { "rdtsc",    { XX }, PREFIX_REX2_ILLEGAL },
2304
  { "rdmsr",    { XX }, PREFIX_REX2_ILLEGAL },
2305
  { "rdpmc",    { XX }, PREFIX_REX2_ILLEGAL },
2306
  { "sysenter",   { SEP }, PREFIX_REX2_ILLEGAL },
2307
  { "sysexit%LQ", { SEP }, PREFIX_REX2_ILLEGAL },
2308
  { Bad_Opcode },
2309
  { "getsec",   { XX }, PREFIX_REX2_ILLEGAL },
2310
  /* 38 */
2311
  { THREE_BYTE_TABLE (THREE_BYTE_0F38) },
2312
  { Bad_Opcode },
2313
  { THREE_BYTE_TABLE (THREE_BYTE_0F3A) },
2314
  { Bad_Opcode },
2315
  { Bad_Opcode },
2316
  { Bad_Opcode },
2317
  { Bad_Opcode },
2318
  { Bad_Opcode },
2319
  /* 40 */
2320
  { "cmovoS",   { Gv, Ev }, 0 },
2321
  { "cmovnoS",    { Gv, Ev }, 0 },
2322
  { "cmovbS",   { Gv, Ev }, 0 },
2323
  { "cmovaeS",    { Gv, Ev }, 0 },
2324
  { "cmoveS",   { Gv, Ev }, 0 },
2325
  { "cmovneS",    { Gv, Ev }, 0 },
2326
  { "cmovbeS",    { Gv, Ev }, 0 },
2327
  { "cmovaS",   { Gv, Ev }, 0 },
2328
  /* 48 */
2329
  { "cmovsS",   { Gv, Ev }, 0 },
2330
  { "cmovnsS",    { Gv, Ev }, 0 },
2331
  { "cmovpS",   { Gv, Ev }, 0 },
2332
  { "cmovnpS",    { Gv, Ev }, 0 },
2333
  { "cmovlS",   { Gv, Ev }, 0 },
2334
  { "cmovgeS",    { Gv, Ev }, 0 },
2335
  { "cmovleS",    { Gv, Ev }, 0 },
2336
  { "cmovgS",   { Gv, Ev }, 0 },
2337
  /* 50 */
2338
  { "movmskpX",   { Gdq, Ux }, PREFIX_OPCODE },
2339
  { PREFIX_TABLE (PREFIX_0F51) },
2340
  { PREFIX_TABLE (PREFIX_0F52) },
2341
  { PREFIX_TABLE (PREFIX_0F53) },
2342
  { "andpX",    { XM, EXx }, PREFIX_OPCODE },
2343
  { "andnpX",   { XM, EXx }, PREFIX_OPCODE },
2344
  { "orpX",   { XM, EXx }, PREFIX_OPCODE },
2345
  { "xorpX",    { XM, EXx }, PREFIX_OPCODE },
2346
  /* 58 */
2347
  { PREFIX_TABLE (PREFIX_0F58) },
2348
  { PREFIX_TABLE (PREFIX_0F59) },
2349
  { PREFIX_TABLE (PREFIX_0F5A) },
2350
  { PREFIX_TABLE (PREFIX_0F5B) },
2351
  { PREFIX_TABLE (PREFIX_0F5C) },
2352
  { PREFIX_TABLE (PREFIX_0F5D) },
2353
  { PREFIX_TABLE (PREFIX_0F5E) },
2354
  { PREFIX_TABLE (PREFIX_0F5F) },
2355
  /* 60 */
2356
  { PREFIX_TABLE (PREFIX_0F60) },
2357
  { PREFIX_TABLE (PREFIX_0F61) },
2358
  { PREFIX_TABLE (PREFIX_0F62) },
2359
  { "packsswb",   { MX, EM }, PREFIX_OPCODE },
2360
  { "pcmpgtb",    { MX, EM }, PREFIX_OPCODE },
2361
  { "pcmpgtw",    { MX, EM }, PREFIX_OPCODE },
2362
  { "pcmpgtd",    { MX, EM }, PREFIX_OPCODE },
2363
  { "packuswb",   { MX, EM }, PREFIX_OPCODE },
2364
  /* 68 */
2365
  { "punpckhbw",  { MX, EM }, PREFIX_OPCODE },
2366
  { "punpckhwd",  { MX, EM }, PREFIX_OPCODE },
2367
  { "punpckhdq",  { MX, EM }, PREFIX_OPCODE },
2368
  { "packssdw",   { MX, EM }, PREFIX_OPCODE },
2369
  { "punpcklqdq", { XM, EXx }, PREFIX_DATA },
2370
  { "punpckhqdq", { XM, EXx }, PREFIX_DATA },
2371
  { "movK",   { MX, Edq }, PREFIX_OPCODE },
2372
  { PREFIX_TABLE (PREFIX_0F6F) },
2373
  /* 70 */
2374
  { PREFIX_TABLE (PREFIX_0F70) },
2375
  { REG_TABLE (REG_0F71) },
2376
  { REG_TABLE (REG_0F72) },
2377
  { REG_TABLE (REG_0F73) },
2378
  { "pcmpeqb",    { MX, EM }, PREFIX_OPCODE },
2379
  { "pcmpeqw",    { MX, EM }, PREFIX_OPCODE },
2380
  { "pcmpeqd",    { MX, EM }, PREFIX_OPCODE },
2381
  { "emms",   { XX }, PREFIX_OPCODE },
2382
  /* 78 */
2383
  { PREFIX_TABLE (PREFIX_0F78) },
2384
  { PREFIX_TABLE (PREFIX_0F79) },
2385
  { Bad_Opcode },
2386
  { Bad_Opcode },
2387
  { PREFIX_TABLE (PREFIX_0F7C) },
2388
  { PREFIX_TABLE (PREFIX_0F7D) },
2389
  { PREFIX_TABLE (PREFIX_0F7E) },
2390
  { PREFIX_TABLE (PREFIX_0F7F) },
2391
  /* 80 */
2392
  { "joH",    { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2393
  { "jnoH",   { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2394
  { "jbH",    { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2395
  { "jaeH",   { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2396
  { "jeH",    { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2397
  { "jneH",   { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2398
  { "jbeH",   { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2399
  { "jaH",    { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2400
  /* 88 */
2401
  { "jsH",    { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2402
  { "jnsH",   { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2403
  { "jpH",    { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2404
  { "jnpH",   { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2405
  { "jlH",    { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2406
  { "jgeH",   { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2407
  { "jleH",   { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2408
  { "jgH",    { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2409
  /* 90 */
2410
  { "seto",   { Eb }, 0 },
2411
  { "setno",    { Eb }, 0 },
2412
  { "setb",   { Eb }, 0 },
2413
  { "setae",    { Eb }, 0 },
2414
  { "sete",   { Eb }, 0 },
2415
  { "setne",    { Eb }, 0 },
2416
  { "setbe",    { Eb }, 0 },
2417
  { "seta",   { Eb }, 0 },
2418
  /* 98 */
2419
  { "sets",   { Eb }, 0 },
2420
  { "setns",    { Eb }, 0 },
2421
  { "setp",   { Eb }, 0 },
2422
  { "setnp",    { Eb }, 0 },
2423
  { "setl",   { Eb }, 0 },
2424
  { "setge",    { Eb }, 0 },
2425
  { "setle",    { Eb }, 0 },
2426
  { "setg",   { Eb }, 0 },
2427
  /* a0 */
2428
  { "pushP",    { fs }, 0 },
2429
  { "popP",   { fs }, 0 },
2430
  { "cpuid",    { XX }, 0 },
2431
  { "btS",    { Ev, Gv }, 0 },
2432
  { "shldS",    { Ev, Gv, Ib }, 0 },
2433
  { "shldS",    { Ev, Gv, CL }, 0 },
2434
  { REG_TABLE (REG_0FA6) },
2435
  { REG_TABLE (REG_0FA7) },
2436
  /* a8 */
2437
  { "pushP",    { gs }, 0 },
2438
  { "popP",   { gs }, 0 },
2439
  { "rsm",    { XX }, 0 },
2440
  { "btsS",   { Evh1, Gv }, 0 },
2441
  { "shrdS",    { Ev, Gv, Ib }, 0 },
2442
  { "shrdS",    { Ev, Gv, CL }, 0 },
2443
  { REG_TABLE (REG_0FAE) },
2444
  { "imulS",    { Gv, Ev }, 0 },
2445
  /* b0 */
2446
  { "cmpxchgB",   { Ebh1, Gb }, 0 },
2447
  { "cmpxchgS",   { Evh1, Gv }, 0 },
2448
  { "lssS",   { Gv, Mp }, 0 },
2449
  { "btrS",   { Evh1, Gv }, 0 },
2450
  { "lfsS",   { Gv, Mp }, 0 },
2451
  { "lgsS",   { Gv, Mp }, 0 },
2452
  { "movz{bR|x}", { Gv, Eb }, 0 },
2453
  { "movz{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
2454
  /* b8 */
2455
  { PREFIX_TABLE (PREFIX_0FB8) },
2456
  { "ud1S",   { Gv, Ev }, 0 },
2457
  { REG_TABLE (REG_0FBA) },
2458
  { "btcS",   { Evh1, Gv }, 0 },
2459
  { PREFIX_TABLE (PREFIX_0FBC) },
2460
  { PREFIX_TABLE (PREFIX_0FBD) },
2461
  { "movs{bR|x}", { Gv, Eb }, 0 },
2462
  { "movs{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
2463
  /* c0 */
2464
  { "xaddB",    { Ebh1, Gb }, 0 },
2465
  { "xaddS",    { Evh1, Gv }, 0 },
2466
  { PREFIX_TABLE (PREFIX_0FC2) },
2467
  { "movntiS",    { Mdq, Gdq }, PREFIX_OPCODE },
2468
  { "pinsrw",   { MX, Edw, Ib }, PREFIX_OPCODE },
2469
  { "pextrw",   { Gd, Nq, Ib }, PREFIX_OPCODE },
2470
  { "shufpX",   { XM, EXx, Ib }, PREFIX_OPCODE },
2471
  { REG_TABLE (REG_0FC7) },
2472
  /* c8 */
2473
  { "bswap",    { RMeAX }, 0 },
2474
  { "bswap",    { RMeCX }, 0 },
2475
  { "bswap",    { RMeDX }, 0 },
2476
  { "bswap",    { RMeBX }, 0 },
2477
  { "bswap",    { RMeSP }, 0 },
2478
  { "bswap",    { RMeBP }, 0 },
2479
  { "bswap",    { RMeSI }, 0 },
2480
  { "bswap",    { RMeDI }, 0 },
2481
  /* d0 */
2482
  { PREFIX_TABLE (PREFIX_0FD0) },
2483
  { "psrlw",    { MX, EM }, PREFIX_OPCODE },
2484
  { "psrld",    { MX, EM }, PREFIX_OPCODE },
2485
  { "psrlq",    { MX, EM }, PREFIX_OPCODE },
2486
  { "paddq",    { MX, EM }, PREFIX_OPCODE },
2487
  { "pmullw",   { MX, EM }, PREFIX_OPCODE },
2488
  { PREFIX_TABLE (PREFIX_0FD6) },
2489
  { "pmovmskb",   { Gdq, Nq }, PREFIX_OPCODE },
2490
  /* d8 */
2491
  { "psubusb",    { MX, EM }, PREFIX_OPCODE },
2492
  { "psubusw",    { MX, EM }, PREFIX_OPCODE },
2493
  { "pminub",   { MX, EM }, PREFIX_OPCODE },
2494
  { "pand",   { MX, EM }, PREFIX_OPCODE },
2495
  { "paddusb",    { MX, EM }, PREFIX_OPCODE },
2496
  { "paddusw",    { MX, EM }, PREFIX_OPCODE },
2497
  { "pmaxub",   { MX, EM }, PREFIX_OPCODE },
2498
  { "pandn",    { MX, EM }, PREFIX_OPCODE },
2499
  /* e0 */
2500
  { "pavgb",    { MX, EM }, PREFIX_OPCODE },
2501
  { "psraw",    { MX, EM }, PREFIX_OPCODE },
2502
  { "psrad",    { MX, EM }, PREFIX_OPCODE },
2503
  { "pavgw",    { MX, EM }, PREFIX_OPCODE },
2504
  { "pmulhuw",    { MX, EM }, PREFIX_OPCODE },
2505
  { "pmulhw",   { MX, EM }, PREFIX_OPCODE },
2506
  { PREFIX_TABLE (PREFIX_0FE6) },
2507
  { PREFIX_TABLE (PREFIX_0FE7) },
2508
  /* e8 */
2509
  { "psubsb",   { MX, EM }, PREFIX_OPCODE },
2510
  { "psubsw",   { MX, EM }, PREFIX_OPCODE },
2511
  { "pminsw",   { MX, EM }, PREFIX_OPCODE },
2512
  { "por",    { MX, EM }, PREFIX_OPCODE },
2513
  { "paddsb",   { MX, EM }, PREFIX_OPCODE },
2514
  { "paddsw",   { MX, EM }, PREFIX_OPCODE },
2515
  { "pmaxsw",   { MX, EM }, PREFIX_OPCODE },
2516
  { "pxor",   { MX, EM }, PREFIX_OPCODE },
2517
  /* f0 */
2518
  { PREFIX_TABLE (PREFIX_0FF0) },
2519
  { "psllw",    { MX, EM }, PREFIX_OPCODE },
2520
  { "pslld",    { MX, EM }, PREFIX_OPCODE },
2521
  { "psllq",    { MX, EM }, PREFIX_OPCODE },
2522
  { "pmuludq",    { MX, EM }, PREFIX_OPCODE },
2523
  { "pmaddwd",    { MX, EM }, PREFIX_OPCODE },
2524
  { "psadbw",   { MX, EM }, PREFIX_OPCODE },
2525
  { PREFIX_TABLE (PREFIX_0FF7) },
2526
  /* f8 */
2527
  { "psubb",    { MX, EM }, PREFIX_OPCODE },
2528
  { "psubw",    { MX, EM }, PREFIX_OPCODE },
2529
  { "psubd",    { MX, EM }, PREFIX_OPCODE },
2530
  { "psubq",    { MX, EM }, PREFIX_OPCODE },
2531
  { "paddb",    { MX, EM }, PREFIX_OPCODE },
2532
  { "paddw",    { MX, EM }, PREFIX_OPCODE },
2533
  { "paddd",    { MX, EM }, PREFIX_OPCODE },
2534
  { "ud0S",   { Gv, Ev }, 0 },
2535
};
2536
2537
static const bool onebyte_has_modrm[256] = {
2538
  /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2539
  /*       -------------------------------        */
2540
  /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2541
  /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2542
  /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2543
  /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2544
  /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2545
  /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2546
  /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2547
  /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2548
  /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2549
  /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2550
  /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2551
  /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2552
  /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2553
  /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2554
  /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2555
  /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
2556
  /*       -------------------------------        */
2557
  /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2558
};
2559
2560
static const bool twobyte_has_modrm[256] = {
2561
  /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2562
  /*       -------------------------------        */
2563
  /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2564
  /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2565
  /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2566
  /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2567
  /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2568
  /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2569
  /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2570
  /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2571
  /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2572
  /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2573
  /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2574
  /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2575
  /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2576
  /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2577
  /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2578
  /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1  /* ff */
2579
  /*       -------------------------------        */
2580
  /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2581
};
2582
2583
2584
struct op
2585
  {
2586
    const char *name;
2587
    unsigned int len;
2588
  };
2589
2590
/* If we are accessing mod/rm/reg without need_modrm set, then the
2591
   values are stale.  Hitting this abort likely indicates that you
2592
   need to update onebyte_has_modrm or twobyte_has_modrm.  */
2593
24.3M
#define MODRM_CHECK  if (!ins->need_modrm) abort ()
2594
2595
static const char intel_index16[][6] = {
2596
  "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2597
};
2598
2599
static const char att_names64[][8] = {
2600
  "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2601
  "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
2602
  "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
2603
  "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
2604
};
2605
static const char att_names32[][8] = {
2606
  "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2607
  "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d",
2608
  "%r16d", "%r17d", "%r18d", "%r19d", "%r20d", "%r21d", "%r22d", "%r23d",
2609
  "%r24d", "%r25d", "%r26d", "%r27d", "%r28d", "%r29d", "%r30d", "%r31d",
2610
};
2611
static const char att_names16[][8] = {
2612
  "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2613
  "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w",
2614
  "%r16w", "%r17w", "%r18w", "%r19w", "%r20w", "%r21w", "%r22w", "%r23w",
2615
  "%r24w", "%r25w", "%r26w", "%r27w", "%r28w", "%r29w", "%r30w", "%r31w",
2616
};
2617
static const char att_names8[][8] = {
2618
  "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2619
};
2620
static const char att_names8rex[][8] = {
2621
  "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2622
  "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b",
2623
  "%r16b", "%r17b", "%r18b", "%r19b", "%r20b", "%r21b", "%r22b", "%r23b",
2624
  "%r24b", "%r25b", "%r26b", "%r27b", "%r28b", "%r29b", "%r30b", "%r31b",
2625
};
2626
static const char att_names_seg[][4] = {
2627
  "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2628
};
2629
static const char att_index64[] = "%riz";
2630
static const char att_index32[] = "%eiz";
2631
static const char att_index16[][8] = {
2632
  "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2633
};
2634
2635
static const char att_names_mm[][8] = {
2636
  "%mm0", "%mm1", "%mm2", "%mm3",
2637
  "%mm4", "%mm5", "%mm6", "%mm7"
2638
};
2639
2640
static const char att_names_bnd[][8] = {
2641
  "%bnd0", "%bnd1", "%bnd2", "%bnd3"
2642
};
2643
2644
static const char att_names_xmm[][8] = {
2645
  "%xmm0", "%xmm1", "%xmm2", "%xmm3",
2646
  "%xmm4", "%xmm5", "%xmm6", "%xmm7",
2647
  "%xmm8", "%xmm9", "%xmm10", "%xmm11",
2648
  "%xmm12", "%xmm13", "%xmm14", "%xmm15",
2649
  "%xmm16", "%xmm17", "%xmm18", "%xmm19",
2650
  "%xmm20", "%xmm21", "%xmm22", "%xmm23",
2651
  "%xmm24", "%xmm25", "%xmm26", "%xmm27",
2652
  "%xmm28", "%xmm29", "%xmm30", "%xmm31"
2653
};
2654
2655
static const char att_names_ymm[][8] = {
2656
  "%ymm0", "%ymm1", "%ymm2", "%ymm3",
2657
  "%ymm4", "%ymm5", "%ymm6", "%ymm7",
2658
  "%ymm8", "%ymm9", "%ymm10", "%ymm11",
2659
  "%ymm12", "%ymm13", "%ymm14", "%ymm15",
2660
  "%ymm16", "%ymm17", "%ymm18", "%ymm19",
2661
  "%ymm20", "%ymm21", "%ymm22", "%ymm23",
2662
  "%ymm24", "%ymm25", "%ymm26", "%ymm27",
2663
  "%ymm28", "%ymm29", "%ymm30", "%ymm31"
2664
};
2665
2666
static const char att_names_zmm[][8] = {
2667
  "%zmm0", "%zmm1", "%zmm2", "%zmm3",
2668
  "%zmm4", "%zmm5", "%zmm6", "%zmm7",
2669
  "%zmm8", "%zmm9", "%zmm10", "%zmm11",
2670
  "%zmm12", "%zmm13", "%zmm14", "%zmm15",
2671
  "%zmm16", "%zmm17", "%zmm18", "%zmm19",
2672
  "%zmm20", "%zmm21", "%zmm22", "%zmm23",
2673
  "%zmm24", "%zmm25", "%zmm26", "%zmm27",
2674
  "%zmm28", "%zmm29", "%zmm30", "%zmm31"
2675
};
2676
2677
static const char att_names_tmm[][8] = {
2678
  "%tmm0", "%tmm1", "%tmm2", "%tmm3",
2679
  "%tmm4", "%tmm5", "%tmm6", "%tmm7"
2680
};
2681
2682
static const char att_names_mask[][8] = {
2683
  "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
2684
};
2685
2686
static const char *const names_rounding[] =
2687
{
2688
  "{rn-",
2689
  "{rd-",
2690
  "{ru-",
2691
  "{rz-"
2692
};
2693
2694
static const struct dis386 reg_table[][8] = {
2695
  /* REG_80 */
2696
  {
2697
    { "addA", { Ebh1, Ib }, 0 },
2698
    { "orA",  { Ebh1, Ib }, 0 },
2699
    { "adcA", { Ebh1, Ib }, 0 },
2700
    { "sbbA", { Ebh1, Ib }, 0 },
2701
    { "andA", { Ebh1, Ib }, 0 },
2702
    { "subA", { Ebh1, Ib }, 0 },
2703
    { "xorA", { Ebh1, Ib }, 0 },
2704
    { "cmpA", { Eb, Ib }, 0 },
2705
  },
2706
  /* REG_81 */
2707
  {
2708
    { "addQ", { Evh1, Iv }, 0 },
2709
    { "orQ",  { Evh1, Iv }, 0 },
2710
    { "adcQ", { Evh1, Iv }, 0 },
2711
    { "sbbQ", { Evh1, Iv }, 0 },
2712
    { "andQ", { Evh1, Iv }, 0 },
2713
    { "subQ", { Evh1, Iv }, 0 },
2714
    { "xorQ", { Evh1, Iv }, 0 },
2715
    { "cmpQ", { Ev, Iv }, 0 },
2716
  },
2717
  /* REG_83 */
2718
  {
2719
    { "addQ", { Evh1, sIb }, 0 },
2720
    { "orQ",  { Evh1, sIb }, 0 },
2721
    { "adcQ", { Evh1, sIb }, 0 },
2722
    { "sbbQ", { Evh1, sIb }, 0 },
2723
    { "andQ", { Evh1, sIb }, 0 },
2724
    { "subQ", { Evh1, sIb }, 0 },
2725
    { "xorQ", { Evh1, sIb }, 0 },
2726
    { "cmpQ", { Ev, sIb }, 0 },
2727
  },
2728
  /* REG_8F */
2729
  {
2730
    { "pop{P|}", { stackEv }, 0 },
2731
    { XOP_8F_TABLE () },
2732
    { Bad_Opcode },
2733
    { Bad_Opcode },
2734
    { Bad_Opcode },
2735
    { XOP_8F_TABLE () },
2736
  },
2737
  /* REG_C0 */
2738
  {
2739
    { "%NFrolA",  { VexGb, Eb, Ib }, NO_PREFIX },
2740
    { "%NFrorA",  { VexGb, Eb, Ib }, NO_PREFIX },
2741
    { "rclA", { VexGb, Eb, Ib }, NO_PREFIX },
2742
    { "rcrA", { VexGb, Eb, Ib }, NO_PREFIX },
2743
    { "%NFshlA",  { VexGb, Eb, Ib }, NO_PREFIX },
2744
    { "%NFshrA",  { VexGb, Eb, Ib }, NO_PREFIX },
2745
    { "%NFshlA",  { VexGb, Eb, Ib }, NO_PREFIX },
2746
    { "%NFsarA",  { VexGb, Eb, Ib }, NO_PREFIX },
2747
  },
2748
  /* REG_C1 */
2749
  {
2750
    { "%NFrolQ",  { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA },
2751
    { "%NFrorQ",  { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA },
2752
    { "rclQ", { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA },
2753
    { "rcrQ", { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA },
2754
    { "%NFshlQ",  { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA },
2755
    { "%NFshrQ",  { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA },
2756
    { "%NFshlQ",  { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA },
2757
    { "%NFsarQ",  { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA },
2758
  },
2759
  /* REG_C6 */
2760
  {
2761
    { "movA", { Ebh3, Ib }, 0 },
2762
    { Bad_Opcode },
2763
    { Bad_Opcode },
2764
    { Bad_Opcode },
2765
    { Bad_Opcode },
2766
    { Bad_Opcode },
2767
    { Bad_Opcode },
2768
    { RM_TABLE (RM_C6_REG_7) },
2769
  },
2770
  /* REG_C7 */
2771
  {
2772
    { "movQ", { Evh3, Iv }, 0 },
2773
    { Bad_Opcode },
2774
    { Bad_Opcode },
2775
    { Bad_Opcode },
2776
    { Bad_Opcode },
2777
    { Bad_Opcode },
2778
    { Bad_Opcode },
2779
    { RM_TABLE (RM_C7_REG_7) },
2780
  },
2781
  /* REG_D0 */
2782
  {
2783
    { "%NFrolA",  { VexGb, Eb, I1 }, NO_PREFIX },
2784
    { "%NFrorA",  { VexGb, Eb, I1 }, NO_PREFIX },
2785
    { "rclA", { VexGb, Eb, I1 }, NO_PREFIX },
2786
    { "rcrA", { VexGb, Eb, I1 }, NO_PREFIX },
2787
    { "%NFshlA",  { VexGb, Eb, I1 }, NO_PREFIX },
2788
    { "%NFshrA",  { VexGb, Eb, I1 }, NO_PREFIX },
2789
    { "%NFshlA",  { VexGb, Eb, I1 }, NO_PREFIX },
2790
    { "%NFsarA",  { VexGb, Eb, I1 }, NO_PREFIX },
2791
  },
2792
  /* REG_D1 */
2793
  {
2794
    { "%NFrolQ",  { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA },
2795
    { "%NFrorQ",  { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA },
2796
    { "rclQ", { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA },
2797
    { "rcrQ", { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA },
2798
    { "%NFshlQ",  { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA },
2799
    { "%NFshrQ",  { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA },
2800
    { "%NFshlQ",  { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA },
2801
    { "%NFsarQ",  { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA },
2802
  },
2803
  /* REG_D2 */
2804
  {
2805
    { "%NFrolA",  { VexGb, Eb, CL }, NO_PREFIX },
2806
    { "%NFrorA",  { VexGb, Eb, CL }, NO_PREFIX },
2807
    { "rclA", { VexGb, Eb, CL }, NO_PREFIX },
2808
    { "rcrA", { VexGb, Eb, CL }, NO_PREFIX },
2809
    { "%NFshlA",  { VexGb, Eb, CL }, NO_PREFIX },
2810
    { "%NFshrA",  { VexGb, Eb, CL }, NO_PREFIX },
2811
    { "%NFshlA",  { VexGb, Eb, CL }, NO_PREFIX },
2812
    { "%NFsarA",  { VexGb, Eb, CL }, NO_PREFIX },
2813
  },
2814
  /* REG_D3 */
2815
  {
2816
    { "%NFrolQ",  { VexGv, Ev, CL }, PREFIX_NP_OR_DATA },
2817
    { "%NFrorQ",  { VexGv, Ev, CL }, PREFIX_NP_OR_DATA },
2818
    { "rclQ", { VexGv, Ev, CL }, PREFIX_NP_OR_DATA },
2819
    { "rcrQ", { VexGv, Ev, CL }, PREFIX_NP_OR_DATA },
2820
    { "%NFshlQ",  { VexGv, Ev, CL }, PREFIX_NP_OR_DATA },
2821
    { "%NFshrQ",  { VexGv, Ev, CL }, PREFIX_NP_OR_DATA },
2822
    { "%NFshlQ",  { VexGv, Ev, CL }, PREFIX_NP_OR_DATA },
2823
    { "%NFsarQ",  { VexGv, Ev, CL }, PREFIX_NP_OR_DATA },
2824
  },
2825
  /* REG_F6 */
2826
  {
2827
    { "testA",  { Eb, Ib }, 0 },
2828
    { "testA",  { Eb, Ib }, 0 },
2829
    { "notA", { Ebh1 }, 0 },
2830
    { "negA", { Ebh1 }, 0 },
2831
    { "mulA", { Eb }, 0 },  /* Don't print the implicit %al register,  */
2832
    { "imulA",  { Eb }, 0 },  /* to distinguish these opcodes from other */
2833
    { "divA", { Eb }, 0 },  /* mul/imul opcodes.  Do the same for div  */
2834
    { "idivA",  { Eb }, 0 },  /* and idiv for consistency.       */
2835
  },
2836
  /* REG_F7 */
2837
  {
2838
    { "testQ",  { Ev, Iv }, 0 },
2839
    { "testQ",  { Ev, Iv }, 0 },
2840
    { "notQ", { Evh1 }, 0 },
2841
    { "negQ", { Evh1 }, 0 },
2842
    { "mulQ", { Ev }, 0 },  /* Don't print the implicit register.  */
2843
    { "imulQ",  { Ev }, 0 },
2844
    { "divQ", { Ev }, 0 },
2845
    { "idivQ",  { Ev }, 0 },
2846
  },
2847
  /* REG_FE */
2848
  {
2849
    { "incA", { Ebh1 }, 0 },
2850
    { "decA", { Ebh1 }, 0 },
2851
  },
2852
  /* REG_FF */
2853
  {
2854
    { "incQ", { Evh1 }, 0 },
2855
    { "decQ", { Evh1 }, 0 },
2856
    { "call{@|}", { NOTRACK, indirEv, BND }, 0 },
2857
    { "{l|}call^", { indirEp }, 0 },
2858
    { "jmp{@|}", { NOTRACK, indirEv, BND }, 0 },
2859
    { "{l|}jmp^", { indirEp }, 0 },
2860
    { "push{P|}", { stackEv }, 0 },
2861
    { Bad_Opcode },
2862
  },
2863
  /* REG_0F00 */
2864
  {
2865
    { "sldtD",  { Sv }, 0 },
2866
    { "strD", { Sv }, 0 },
2867
    { "lldtD",  { Sv }, 0 },
2868
    { "ltrD", { Sv }, 0 },
2869
    { "verrD",  { Sv }, 0 },
2870
    { "verwD",  { Sv }, 0 },
2871
    { X86_64_TABLE (X86_64_0F00_REG_6) },
2872
    { Bad_Opcode },
2873
  },
2874
  /* REG_0F01 */
2875
  {
2876
    { MOD_TABLE (MOD_0F01_REG_0) },
2877
    { MOD_TABLE (MOD_0F01_REG_1) },
2878
    { MOD_TABLE (MOD_0F01_REG_2) },
2879
    { MOD_TABLE (MOD_0F01_REG_3) },
2880
    { "smswD",  { Sv }, 0 },
2881
    { MOD_TABLE (MOD_0F01_REG_5) },
2882
    { "lmsw", { Ew }, 0 },
2883
    { MOD_TABLE (MOD_0F01_REG_7) },
2884
  },
2885
  /* REG_0F0D */
2886
  {
2887
    { "prefetch", { Mb }, 0 },
2888
    { "prefetchw",  { Mb }, 0 },
2889
    { "prefetchwt1",  { Mb }, 0 },
2890
    { "prefetch", { Mb }, 0 },
2891
    { "prefetch", { Mb }, 0 },
2892
    { "prefetch", { Mb }, 0 },
2893
    { "prefetch", { Mb }, 0 },
2894
    { "prefetch", { Mb }, 0 },
2895
  },
2896
  /* REG_0F18 */
2897
  {
2898
    { MOD_TABLE (MOD_0F18_REG_0) },
2899
    { MOD_TABLE (MOD_0F18_REG_1) },
2900
    { MOD_TABLE (MOD_0F18_REG_2) },
2901
    { MOD_TABLE (MOD_0F18_REG_3) },
2902
    { MOD_TABLE (MOD_0F18_REG_4) },
2903
    { "nopQ",   { Ev }, 0 },
2904
    { MOD_TABLE (MOD_0F18_REG_6) },
2905
    { MOD_TABLE (MOD_0F18_REG_7) },
2906
  },
2907
  /* REG_0F1C_P_0_MOD_0 */
2908
  {
2909
    { "cldemote", { Mb }, 0 },
2910
    { "nopQ",   { Ev }, 0 },
2911
    { "nopQ",   { Ev }, 0 },
2912
    { "nopQ",   { Ev }, 0 },
2913
    { "nopQ",   { Ev }, 0 },
2914
    { "nopQ",   { Ev }, 0 },
2915
    { "nopQ",   { Ev }, 0 },
2916
    { "nopQ",   { Ev }, 0 },
2917
  },
2918
  /* REG_0F1E_P_1_MOD_3 */
2919
  {
2920
    { "nopQ",   { Ev }, PREFIX_IGNORED },
2921
    { "rdsspK",   { Edq }, 0 },
2922
    { "nopQ",   { Ev }, PREFIX_IGNORED },
2923
    { "nopQ",   { Ev }, PREFIX_IGNORED },
2924
    { "nopQ",   { Ev }, PREFIX_IGNORED },
2925
    { "nopQ",   { Ev }, PREFIX_IGNORED },
2926
    { "nopQ",   { Ev }, PREFIX_IGNORED },
2927
    { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7) },
2928
  },
2929
  /* REG_0F38D8_PREFIX_1 */
2930
  {
2931
    { "aesencwide128kl",  { M }, 0 },
2932
    { "aesdecwide128kl",  { M }, 0 },
2933
    { "aesencwide256kl",  { M }, 0 },
2934
    { "aesdecwide256kl",  { M }, 0 },
2935
  },
2936
  /* REG_0F3A0F_P_1 */
2937
  {
2938
    { RM_TABLE (RM_0F3A0F_P_1_R_0) },
2939
  },
2940
  /* REG_0F71 */
2941
  {
2942
    { Bad_Opcode },
2943
    { Bad_Opcode },
2944
    { "psrlw",    { Nq, Ib }, PREFIX_OPCODE },
2945
    { Bad_Opcode },
2946
    { "psraw",    { Nq, Ib }, PREFIX_OPCODE },
2947
    { Bad_Opcode },
2948
    { "psllw",    { Nq, Ib }, PREFIX_OPCODE },
2949
  },
2950
  /* REG_0F72 */
2951
  {
2952
    { Bad_Opcode },
2953
    { Bad_Opcode },
2954
    { "psrld",    { Nq, Ib }, PREFIX_OPCODE },
2955
    { Bad_Opcode },
2956
    { "psrad",    { Nq, Ib }, PREFIX_OPCODE },
2957
    { Bad_Opcode },
2958
    { "pslld",    { Nq, Ib }, PREFIX_OPCODE },
2959
  },
2960
  /* REG_0F73 */
2961
  {
2962
    { Bad_Opcode },
2963
    { Bad_Opcode },
2964
    { "psrlq",    { Nq, Ib }, PREFIX_OPCODE },
2965
    { "psrldq",   { Ux, Ib }, PREFIX_DATA },
2966
    { Bad_Opcode },
2967
    { Bad_Opcode },
2968
    { "psllq",    { Nq, Ib }, PREFIX_OPCODE },
2969
    { "pslldq",   { Ux, Ib }, PREFIX_DATA },
2970
  },
2971
  /* REG_0FA6 */
2972
  {
2973
    { PREFIX_TABLE (PREFIX_0FA6_REG_0) },
2974
    { "xsha1",    { { OP_0f07, 0 } }, 0 },
2975
    { "xsha256",  { { OP_0f07, 0 } }, 0 },
2976
    { "xsha384",  { { OP_0f07, 0 } }, 0 },
2977
    { "xsha512",  { { OP_0f07, 0 } }, 0 },
2978
    { PREFIX_TABLE (PREFIX_0FA6_REG_5) },
2979
    { "montmul2", { { OP_0f07, 0 } }, 0 },
2980
    { "xmodexp",  { { OP_0f07, 0 } }, 0 },
2981
  },
2982
  /* REG_0FA7 */
2983
  {
2984
    { "xstore-rng", { { OP_0f07, 0 } }, 0 },
2985
    { "xcrypt-ecb", { { OP_0f07, 0 } }, 0 },
2986
    { "xcrypt-cbc", { { OP_0f07, 0 } }, 0 },
2987
    { "xcrypt-ctr", { { OP_0f07, 0 } }, 0 },
2988
    { "xcrypt-cfb", { { OP_0f07, 0 } }, 0 },
2989
    { "xcrypt-ofb", { { OP_0f07, 0 } }, 0 },
2990
    { PREFIX_TABLE (PREFIX_0FA7_REG_6) },
2991
    { "xrng2",    { { OP_0f07, 0 } }, 0 },
2992
  },
2993
  /* REG_0FAE */
2994
  {
2995
    { MOD_TABLE (MOD_0FAE_REG_0) },
2996
    { MOD_TABLE (MOD_0FAE_REG_1) },
2997
    { MOD_TABLE (MOD_0FAE_REG_2) },
2998
    { MOD_TABLE (MOD_0FAE_REG_3) },
2999
    { MOD_TABLE (MOD_0FAE_REG_4) },
3000
    { MOD_TABLE (MOD_0FAE_REG_5) },
3001
    { MOD_TABLE (MOD_0FAE_REG_6) },
3002
    { MOD_TABLE (MOD_0FAE_REG_7) },
3003
  },
3004
  /* REG_0FBA */
3005
  {
3006
    { Bad_Opcode },
3007
    { Bad_Opcode },
3008
    { Bad_Opcode },
3009
    { Bad_Opcode },
3010
    { "btQ",  { Ev, Ib }, 0 },
3011
    { "btsQ", { Evh1, Ib }, 0 },
3012
    { "btrQ", { Evh1, Ib }, 0 },
3013
    { "btcQ", { Evh1, Ib }, 0 },
3014
  },
3015
  /* REG_0FC7 */
3016
  {
3017
    { Bad_Opcode },
3018
    { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
3019
    { Bad_Opcode },
3020
    { "xrstors", { FXSAVE }, PREFIX_REX2_ILLEGAL },
3021
    { "xsavec", { FXSAVE }, PREFIX_REX2_ILLEGAL },
3022
    { "xsaves", { FXSAVE }, PREFIX_REX2_ILLEGAL },
3023
    { MOD_TABLE (MOD_0FC7_REG_6) },
3024
    { MOD_TABLE (MOD_0FC7_REG_7) },
3025
  },
3026
  /* REG_VEX_0F71 */
3027
  {
3028
    { Bad_Opcode },
3029
    { Bad_Opcode },
3030
    { "vpsrlw",   { Vex, Ux, Ib }, PREFIX_DATA },
3031
    { Bad_Opcode },
3032
    { "vpsraw",   { Vex, Ux, Ib }, PREFIX_DATA },
3033
    { Bad_Opcode },
3034
    { "vpsllw",   { Vex, Ux, Ib }, PREFIX_DATA },
3035
  },
3036
  /* REG_VEX_0F72 */
3037
  {
3038
    { Bad_Opcode },
3039
    { Bad_Opcode },
3040
    { "vpsrld",   { Vex, Ux, Ib }, PREFIX_DATA },
3041
    { Bad_Opcode },
3042
    { "vpsrad",   { Vex, Ux, Ib }, PREFIX_DATA },
3043
    { Bad_Opcode },
3044
    { "vpslld",   { Vex, Ux, Ib }, PREFIX_DATA },
3045
  },
3046
  /* REG_VEX_0F73 */
3047
  {
3048
    { Bad_Opcode },
3049
    { Bad_Opcode },
3050
    { "vpsrlq",   { Vex, Ux, Ib }, PREFIX_DATA },
3051
    { "vpsrldq",  { Vex, Ux, Ib }, PREFIX_DATA },
3052
    { Bad_Opcode },
3053
    { Bad_Opcode },
3054
    { "vpsllq",   { Vex, Ux, Ib }, PREFIX_DATA },
3055
    { "vpslldq",  { Vex, Ux, Ib }, PREFIX_DATA },
3056
  },
3057
  /* REG_VEX_0FAE */
3058
  {
3059
    { Bad_Opcode },
3060
    { Bad_Opcode },
3061
    { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2) },
3062
    { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3) },
3063
  },
3064
  /* REG_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0 */
3065
  {
3066
    { RM_TABLE (RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0_R_0) },
3067
  },
3068
  /* REG_VEX_0F38F3_L_0_P_0 */
3069
  {
3070
    { Bad_Opcode },
3071
    { "%NFblsrS",   { VexGdq, Edq }, 0 },
3072
    { "%NFblsmskS",   { VexGdq, Edq }, 0 },
3073
    { "%NFblsiS",   { VexGdq, Edq }, 0 },
3074
  },
3075
  /* REG_VEX_MAP7_F6_L_0_W_0 */
3076
  {
3077
    { X86_64_TABLE (X86_64_VEX_MAP7_F6_L_0_W_0_R_0) },
3078
  },
3079
  /* REG_VEX_MAP7_F8_L_0_W_0 */
3080
  {
3081
    { X86_64_TABLE (X86_64_VEX_MAP7_F8_L_0_W_0_R_0) },
3082
  },
3083
  /* REG_XOP_09_01_L_0 */
3084
  {
3085
    { Bad_Opcode },
3086
    { "blcfill",  { VexGdq, Edq }, 0 },
3087
    { "blsfill",  { VexGdq, Edq }, 0 },
3088
    { "blcs", { VexGdq, Edq }, 0 },
3089
    { "tzmsk",  { VexGdq, Edq }, 0 },
3090
    { "blcic",  { VexGdq, Edq }, 0 },
3091
    { "blsic",  { VexGdq, Edq }, 0 },
3092
    { "t1mskc", { VexGdq, Edq }, 0 },
3093
  },
3094
  /* REG_XOP_09_02_L_0 */
3095
  {
3096
    { Bad_Opcode },
3097
    { "blcmsk", { VexGdq, Edq }, 0 },
3098
    { Bad_Opcode },
3099
    { Bad_Opcode },
3100
    { Bad_Opcode },
3101
    { Bad_Opcode },
3102
    { "blci", { VexGdq, Edq }, 0 },
3103
  },
3104
  /* REG_XOP_09_12_L_0 */
3105
  {
3106
    { "llwpcb", { Rdq }, 0 },
3107
    { "slwpcb", { Rdq }, 0 },
3108
  },
3109
  /* REG_XOP_0A_12_L_0 */
3110
  {
3111
    { "lwpins", { VexGdq, Ed, Id }, 0 },
3112
    { "lwpval", { VexGdq, Ed, Id }, 0 },
3113
  },
3114
3115
#include "i386-dis-evex-reg.h"
3116
};
3117
3118
static const struct dis386 prefix_table[][4] = {
3119
  /* PREFIX_90 */
3120
  {
3121
    { "xchgS", { { NOP_Fixup, 0 }, { NOP_Fixup, 1 } }, 0 },
3122
    { "pause", { XX }, 0 },
3123
    { "xchgS", { { NOP_Fixup, 0 }, { NOP_Fixup, 1 } }, 0 },
3124
    { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3125
  },
3126
3127
  /* PREFIX_0F00_REG_6_X86_64 */
3128
  {
3129
    { Bad_Opcode },
3130
    { Bad_Opcode },
3131
    { Bad_Opcode },
3132
    { "lkgsD", { Sv }, 0 },
3133
  },
3134
3135
  /* PREFIX_0F01_REG_0_MOD_3_RM_6 */
3136
  {
3137
    { "wrmsrns",        { Skip_MODRM }, 0 },
3138
    { X86_64_TABLE (X86_64_0F01_REG_0_MOD_3_RM_6_P_1) },
3139
    { Bad_Opcode },
3140
    { X86_64_TABLE (X86_64_0F01_REG_0_MOD_3_RM_6_P_3) },
3141
  },
3142
3143
  /* PREFIX_0F01_REG_0_MOD_3_RM_7 */
3144
  {
3145
    { X86_64_TABLE (X86_64_0F01_REG_0_MOD_3_RM_7_P_0) },
3146
  },
3147
3148
  /* PREFIX_0F01_REG_1_RM_2 */
3149
  {
3150
    { "clac",   { Skip_MODRM }, 0 },
3151
    { X86_64_TABLE (X86_64_0F01_REG_1_RM_2_PREFIX_1) },
3152
    { Bad_Opcode },
3153
    { X86_64_TABLE (X86_64_0F01_REG_1_RM_2_PREFIX_3)},
3154
  },
3155
3156
  /* PREFIX_0F01_REG_1_RM_4 */
3157
  {
3158
    { Bad_Opcode },
3159
    { Bad_Opcode },
3160
    { "tdcall",   { Skip_MODRM }, 0 },
3161
    { Bad_Opcode },
3162
  },
3163
3164
  /* PREFIX_0F01_REG_1_RM_5 */
3165
  {
3166
    { Bad_Opcode },
3167
    { Bad_Opcode },
3168
    { X86_64_TABLE (X86_64_0F01_REG_1_RM_5_PREFIX_2) },
3169
    { Bad_Opcode },
3170
  },
3171
3172
  /* PREFIX_0F01_REG_1_RM_6 */
3173
  {
3174
    { Bad_Opcode },
3175
    { Bad_Opcode },
3176
    { X86_64_TABLE (X86_64_0F01_REG_1_RM_6_PREFIX_2) },
3177
    { Bad_Opcode },
3178
  },
3179
3180
  /* PREFIX_0F01_REG_1_RM_7 */
3181
  {
3182
    { "encls",    { Skip_MODRM }, 0 },
3183
    { Bad_Opcode },
3184
    { X86_64_TABLE (X86_64_0F01_REG_1_RM_7_PREFIX_2) },
3185
    { Bad_Opcode },
3186
  },
3187
3188
  /* PREFIX_0F01_REG_3_RM_1 */
3189
  {
3190
    { "vmmcall",  { Skip_MODRM }, 0 },
3191
    { "vmgexit",  { Skip_MODRM }, 0 },
3192
    { Bad_Opcode },
3193
    { "vmgexit",  { Skip_MODRM }, 0 },
3194
  },
3195
3196
  /* PREFIX_0F01_REG_5_MOD_0 */
3197
  {
3198
    { Bad_Opcode },
3199
    { "rstorssp", { Mq }, PREFIX_OPCODE },
3200
  },
3201
3202
  /* PREFIX_0F01_REG_5_MOD_3_RM_0 */
3203
  {
3204
    { "serialize",  { Skip_MODRM }, PREFIX_OPCODE },
3205
    { "setssbsy", { Skip_MODRM }, PREFIX_OPCODE },
3206
    { Bad_Opcode },
3207
    { "xsusldtrk",  { Skip_MODRM }, PREFIX_OPCODE },
3208
  },
3209
3210
  /* PREFIX_0F01_REG_5_MOD_3_RM_1 */
3211
  {
3212
    { Bad_Opcode },
3213
    { Bad_Opcode },
3214
    { Bad_Opcode },
3215
    { "xresldtrk",     { Skip_MODRM }, PREFIX_OPCODE },
3216
  },
3217
3218
  /* PREFIX_0F01_REG_5_MOD_3_RM_2 */
3219
  {
3220
    { Bad_Opcode },
3221
    { "saveprevssp",  { Skip_MODRM }, PREFIX_OPCODE },
3222
  },
3223
3224
  /* PREFIX_0F01_REG_5_MOD_3_RM_4 */
3225
  {
3226
    { Bad_Opcode },
3227
    { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1) },
3228
  },
3229
3230
  /* PREFIX_0F01_REG_5_MOD_3_RM_5 */
3231
  {
3232
    { Bad_Opcode },
3233
    { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1) },
3234
  },
3235
3236
  /* PREFIX_0F01_REG_5_MOD_3_RM_6 */
3237
  {
3238
    { "rdpkru", { Skip_MODRM }, 0 },
3239
    { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1) },
3240
  },
3241
3242
  /* PREFIX_0F01_REG_5_MOD_3_RM_7 */
3243
  {
3244
    { "wrpkru", { Skip_MODRM }, 0 },
3245
    { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1) },
3246
  },
3247
3248
  /* PREFIX_0F01_REG_7_MOD_3_RM_2 */
3249
  {
3250
    { "monitorx", { { OP_Monitor, 0 } }, 0  },
3251
    { "mcommit",  { Skip_MODRM }, 0 },
3252
  },
3253
3254
  /* PREFIX_0F01_REG_7_MOD_3_RM_5 */
3255
  {
3256
    { "rdpru", { Skip_MODRM }, 0 },
3257
    { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_5_PREFIX_1) },
3258
    { Bad_Opcode },
3259
    { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_5_PREFIX_3) },
3260
  },
3261
3262
  /* PREFIX_0F01_REG_7_MOD_3_RM_6 */
3263
  {
3264
    { "invlpgb",        { Skip_MODRM }, 0 },
3265
    { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1) },
3266
    { Bad_Opcode },
3267
    { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3) },
3268
  },
3269
3270
  /* PREFIX_0F01_REG_7_MOD_3_RM_7 */
3271
  {
3272
    { "tlbsync",        { Skip_MODRM }, 0 },
3273
    { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1) },
3274
    { Bad_Opcode },
3275
    { "pvalidate",      { Skip_MODRM }, 0 },
3276
  },
3277
3278
  /* PREFIX_0F09 */
3279
  {
3280
    { "wbinvd",   { XX }, 0 },
3281
    { "wbnoinvd", { XX }, 0 },
3282
  },
3283
3284
  /* PREFIX_0F10 */
3285
  {
3286
    { "%XEVmovupX", { XM, EXEvexXNoBcst }, 0 },
3287
    { "%XEVmovs%XS",  { XMScalar, VexScalarR, EXd }, 0 },
3288
    { "%XEVmovupX", { XM, EXEvexXNoBcst }, 0 },
3289
    { "%XEVmovs%XD",  { XMScalar, VexScalarR, EXq }, 0 },
3290
  },
3291
3292
  /* PREFIX_0F11 */
3293
  {
3294
    { "%XEVmovupX", { EXxS, XM }, 0 },
3295
    { "%XEVmovs%XS",  { EXdS, VexScalarR, XMScalar }, 0 },
3296
    { "%XEVmovupX", { EXxS, XM }, 0 },
3297
    { "%XEVmovs%XD",  { EXqS, VexScalarR, XMScalar }, 0 },
3298
  },
3299
3300
  /* PREFIX_0F12 */
3301
  {
3302
    { MOD_TABLE (MOD_0F12_PREFIX_0) },
3303
    { "movsldup", { XM, EXx }, 0 },
3304
    { "%XEVmovlpYX",  { XM, Vex, Mq }, 0 },
3305
    { "movddup",  { XM, EXq }, 0 },
3306
  },
3307
3308
  /* PREFIX_0F16 */
3309
  {
3310
    { MOD_TABLE (MOD_0F16_PREFIX_0) },
3311
    { "movshdup", { XM, EXx }, 0 },
3312
    { "%XEVmovhpYX",  { XM, Vex, Mq }, 0 },
3313
  },
3314
3315
  /* PREFIX_0F18_REG_6_MOD_0_X86_64 */
3316
  {
3317
    { "prefetchit1",  { { PREFETCHI_Fixup, b_mode } }, 0 },
3318
    { "nopQ",   { Ev }, 0 },
3319
    { "nopQ",   { Ev }, 0 },
3320
    { "nopQ",   { Ev }, 0 },
3321
  },
3322
3323
  /* PREFIX_0F18_REG_7_MOD_0_X86_64 */
3324
  {
3325
    { "prefetchit0",  { { PREFETCHI_Fixup, b_mode } }, 0 },
3326
    { "nopQ",   { Ev }, 0 },
3327
    { "nopQ",   { Ev }, 0 },
3328
    { "nopQ",   { Ev }, 0 },
3329
  },
3330
3331
  /* PREFIX_0F1A */
3332
  {
3333
    { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3334
    { "bndcl",  { Gbnd, Ev_bnd }, 0 },
3335
    { "bndmov", { Gbnd, Ebnd }, 0 },
3336
    { "bndcu",  { Gbnd, Ev_bnd }, 0 },
3337
  },
3338
3339
  /* PREFIX_0F1B */
3340
  {
3341
    { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3342
    { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3343
    { "bndmov", { EbndS, Gbnd }, 0 },
3344
    { "bndcn",  { Gbnd, Ev_bnd }, 0 },
3345
  },
3346
3347
  /* PREFIX_0F1C */
3348
  {
3349
    { MOD_TABLE (MOD_0F1C_PREFIX_0) },
3350
    { "nopQ", { Ev }, PREFIX_IGNORED },
3351
    { "nopQ", { Ev }, 0 },
3352
    { "nopQ", { Ev }, PREFIX_IGNORED },
3353
  },
3354
3355
  /* PREFIX_0F1E */
3356
  {
3357
    { "nopQ", { Ev }, 0 },
3358
    { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3359
    { "nopQ", { Ev }, 0 },
3360
    { NULL, { XX }, PREFIX_IGNORED },
3361
  },
3362
3363
  /* PREFIX_0F2A */
3364
  {
3365
    { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3366
    { "cvtsi2ss{%LQ|}", { XM, Edq }, PREFIX_OPCODE },
3367
    { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3368
    { "cvtsi2sd{%LQ|}", { XM, Edq }, 0 },
3369
  },
3370
3371
  /* PREFIX_0F2B */
3372
  {
3373
    { "movntps", { Mx, XM }, 0 },
3374
    { "movntss", { Md, XM }, 0 },
3375
    { "movntpd", { Mx, XM }, 0 },
3376
    { "movntsd", { Mq, XM }, 0 },
3377
  },
3378
3379
  /* PREFIX_0F2C */
3380
  {
3381
    { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3382
    { "cvttss2si", { Gdq, EXd }, PREFIX_OPCODE },
3383
    { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3384
    { "cvttsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3385
  },
3386
3387
  /* PREFIX_0F2D */
3388
  {
3389
    { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3390
    { "cvtss2si", { Gdq, EXd }, PREFIX_OPCODE },
3391
    { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3392
    { "cvtsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3393
  },
3394
3395
  /* PREFIX_0F2E */
3396
  {
3397
    { "VucomisYX",  { XMScalar, EXd, EXxEVexS }, 0 },
3398
    { Bad_Opcode },
3399
    { "VucomisYX",  { XMScalar, EXq, EXxEVexS }, 0 },
3400
  },
3401
3402
  /* PREFIX_0F2F */
3403
  {
3404
    { "VcomisYX", { XMScalar, EXd, EXxEVexS }, 0 },
3405
    { Bad_Opcode },
3406
    { "VcomisYX", { XMScalar, EXq, EXxEVexS }, 0 },
3407
  },
3408
3409
  /* PREFIX_0F51 */
3410
  {
3411
    { "%XEVsqrtpX", { XM, EXx, EXxEVexR }, 0 },
3412
    { "%XEVsqrts%XS", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3413
    { "%XEVsqrtpX", { XM, EXx, EXxEVexR }, 0 },
3414
    { "%XEVsqrts%XD", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3415
  },
3416
3417
  /* PREFIX_0F52 */
3418
  {
3419
    { "Vrsqrtps", { XM, EXx }, 0 },
3420
    { "Vrsqrtss", { XMScalar, VexScalar, EXd }, 0 },
3421
  },
3422
3423
  /* PREFIX_0F53 */
3424
  {
3425
    { "Vrcpps",   { XM, EXx }, 0 },
3426
    { "Vrcpss",   { XMScalar, VexScalar, EXd }, 0 },
3427
  },
3428
3429
  /* PREFIX_0F58 */
3430
  {
3431
    { "%XEVaddpX",  { XM, Vex, EXx, EXxEVexR }, 0 },
3432
    { "%XEVadds%XS",  { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3433
    { "%XEVaddpX",  { XM, Vex, EXx, EXxEVexR }, 0 },
3434
    { "%XEVadds%XD",  { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3435
  },
3436
3437
  /* PREFIX_0F59 */
3438
  {
3439
    { "%XEVmulpX",  { XM, Vex, EXx, EXxEVexR }, 0 },
3440
    { "%XEVmuls%XS",  { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3441
    { "%XEVmulpX",  { XM, Vex, EXx, EXxEVexR }, 0 },
3442
    { "%XEVmuls%XD",  { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3443
  },
3444
3445
  /* PREFIX_0F5A */
3446
  {
3447
    { "%XEVcvtp%XS2pd", { XM, EXEvexHalfBcstXmmq, EXxEVexS }, 0 },
3448
    { "%XEVcvts%XS2sd", { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
3449
    { "%XEVcvtp%XD2ps%XY", { XMxmmq, EXx, EXxEVexR }, 0 },
3450
    { "%XEVcvts%XD2ss", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3451
  },
3452
3453
  /* PREFIX_0F5B */
3454
  {
3455
    { "Vcvtdq2ps",  { XM, EXx }, 0 },
3456
    { "Vcvttps2dq", { XM, EXx }, 0 },
3457
    { "Vcvtps2dq",  { XM, EXx }, 0 },
3458
  },
3459
3460
  /* PREFIX_0F5C */
3461
  {
3462
    { "%XEVsubpX",  { XM, Vex, EXx, EXxEVexR }, 0 },
3463
    { "%XEVsubs%XS",  { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3464
    { "%XEVsubpX",  { XM, Vex, EXx, EXxEVexR }, 0 },
3465
    { "%XEVsubs%XD",  { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3466
  },
3467
3468
  /* PREFIX_0F5D */
3469
  {
3470
    { "%XEVminpX",  { XM, Vex, EXx, EXxEVexS }, 0 },
3471
    { "%XEVmins%XS",  { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
3472
    { "%XEVminpX",  { XM, Vex, EXx, EXxEVexS }, 0 },
3473
    { "%XEVmins%XD",  { XMScalar, VexScalar, EXq, EXxEVexS }, 0 },
3474
  },
3475
3476
  /* PREFIX_0F5E */
3477
  {
3478
    { "%XEVdivpX",  { XM, Vex, EXx, EXxEVexR }, 0 },
3479
    { "%XEVdivs%XS",  { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3480
    { "%XEVdivpX",  { XM, Vex, EXx, EXxEVexR }, 0 },
3481
    { "%XEVdivs%XD",  { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3482
  },
3483
3484
  /* PREFIX_0F5F */
3485
  {
3486
    { "%XEVmaxpX",  { XM, Vex, EXx, EXxEVexS }, 0 },
3487
    { "%XEVmaxs%XS",  { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
3488
    { "%XEVmaxpX",  { XM, Vex, EXx, EXxEVexS }, 0 },
3489
    { "%XEVmaxs%XD",  { XMScalar, VexScalar, EXq, EXxEVexS }, 0 },
3490
  },
3491
3492
  /* PREFIX_0F60 */
3493
  {
3494
    { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3495
    { Bad_Opcode },
3496
    { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3497
  },
3498
3499
  /* PREFIX_0F61 */
3500
  {
3501
    { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3502
    { Bad_Opcode },
3503
    { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3504
  },
3505
3506
  /* PREFIX_0F62 */
3507
  {
3508
    { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
3509
    { Bad_Opcode },
3510
    { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
3511
  },
3512
3513
  /* PREFIX_0F6F */
3514
  {
3515
    { "movq", { MX, EM }, PREFIX_OPCODE },
3516
    { "movdqu", { XM, EXx }, PREFIX_OPCODE },
3517
    { "movdqa", { XM, EXx }, PREFIX_OPCODE },
3518
  },
3519
3520
  /* PREFIX_0F70 */
3521
  {
3522
    { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
3523
    { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3524
    { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
3525
    { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3526
  },
3527
3528
  /* PREFIX_0F78 */
3529
  {
3530
    {"vmread",  { Em, Gm }, 0 },
3531
    { Bad_Opcode },
3532
    {"extrq", { Uxmm, Ib, Ib }, 0 },
3533
    {"insertq", { XM, Uxmm, Ib, Ib }, 0 },
3534
  },
3535
3536
  /* PREFIX_0F79 */
3537
  {
3538
    {"vmwrite", { Gm, Em }, 0 },
3539
    { Bad_Opcode },
3540
    {"extrq", { XM, Uxmm }, 0 },
3541
    {"insertq", { XM, Uxmm }, 0 },
3542
  },
3543
3544
  /* PREFIX_0F7C */
3545
  {
3546
    { Bad_Opcode },
3547
    { Bad_Opcode },
3548
    { "Vhaddpd",  { XM, Vex, EXx }, 0 },
3549
    { "Vhaddps",  { XM, Vex, EXx }, 0 },
3550
  },
3551
3552
  /* PREFIX_0F7D */
3553
  {
3554
    { Bad_Opcode },
3555
    { Bad_Opcode },
3556
    { "Vhsubpd",  { XM, Vex, EXx }, 0 },
3557
    { "Vhsubps",  { XM, Vex, EXx }, 0 },
3558
  },
3559
3560
  /* PREFIX_0F7E */
3561
  {
3562
    { "movK", { Edq, MX }, PREFIX_OPCODE },
3563
    { "movq", { XM, EXq }, PREFIX_OPCODE },
3564
    { "movK", { Edq, XM }, PREFIX_OPCODE },
3565
  },
3566
3567
  /* PREFIX_0F7F */
3568
  {
3569
    { "movq", { EMS, MX }, PREFIX_OPCODE },
3570
    { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
3571
    { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
3572
  },
3573
3574
  /* PREFIX_0FA6_REG_0 */
3575
  {
3576
    { Bad_Opcode },
3577
    { "montmul",  { { MONTMUL_Fixup, 0 } }, 0},
3578
    { Bad_Opcode },
3579
    { "sm2",  { Skip_MODRM }, 0 },
3580
  },
3581
3582
  /* PREFIX_0FA6_REG_5 */
3583
  {
3584
    { Bad_Opcode },
3585
    { "sm3",  { Skip_MODRM }, 0 },
3586
  },
3587
3588
  /* PREFIX_0FA7_REG_6 */
3589
  {
3590
    { Bad_Opcode },
3591
    { "sm4",  { Skip_MODRM }, 0 },
3592
  },
3593
3594
  /* PREFIX_0FAE_REG_0_MOD_3 */
3595
  {
3596
    { Bad_Opcode },
3597
    { "rdfsbase", { Ev }, 0 },
3598
  },
3599
3600
  /* PREFIX_0FAE_REG_1_MOD_3 */
3601
  {
3602
    { Bad_Opcode },
3603
    { "rdgsbase", { Ev }, 0 },
3604
  },
3605
3606
  /* PREFIX_0FAE_REG_2_MOD_3 */
3607
  {
3608
    { Bad_Opcode },
3609
    { "wrfsbase", { Ev }, 0 },
3610
  },
3611
3612
  /* PREFIX_0FAE_REG_3_MOD_3 */
3613
  {
3614
    { Bad_Opcode },
3615
    { "wrgsbase", { Ev }, 0 },
3616
  },
3617
3618
  /* PREFIX_0FAE_REG_4_MOD_0 */
3619
  {
3620
    { "xsave",  { FXSAVE }, PREFIX_REX2_ILLEGAL },
3621
    { "ptwrite{%LQ|}", { Edq }, 0 },
3622
  },
3623
3624
  /* PREFIX_0FAE_REG_4_MOD_3 */
3625
  {
3626
    { Bad_Opcode },
3627
    { "ptwrite{%LQ|}", { Edq }, 0 },
3628
  },
3629
3630
  /* PREFIX_0FAE_REG_5_MOD_3 */
3631
  {
3632
    { "lfence",   { Skip_MODRM }, 0 },
3633
    { "incsspK",  { Edq }, PREFIX_OPCODE },
3634
  },
3635
3636
  /* PREFIX_0FAE_REG_6_MOD_0 */
3637
  {
3638
    { "xsaveopt", { FXSAVE }, PREFIX_OPCODE | PREFIX_REX2_ILLEGAL },
3639
    { "clrssbsy", { Mq }, PREFIX_OPCODE },
3640
    { "clwb", { Mb }, PREFIX_OPCODE },
3641
  },
3642
3643
  /* PREFIX_0FAE_REG_6_MOD_3 */
3644
  {
3645
    { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0) },
3646
    { "umonitor", { Eva }, PREFIX_OPCODE },
3647
    { "tpause", { Edq }, PREFIX_OPCODE },
3648
    { "umwait", { Edq }, PREFIX_OPCODE },
3649
  },
3650
3651
  /* PREFIX_0FAE_REG_7_MOD_0 */
3652
  {
3653
    { "clflush",  { Mb }, 0 },
3654
    { Bad_Opcode },
3655
    { "clflushopt", { Mb }, 0 },
3656
  },
3657
3658
  /* PREFIX_0FB8 */
3659
  {
3660
    { Bad_Opcode },
3661
    { "popcntS", { Gv, Ev }, 0 },
3662
  },
3663
3664
  /* PREFIX_0FBC */
3665
  {
3666
    { "bsfS", { Gv, Ev }, 0 },
3667
    { "tzcntS", { Gv, Ev }, 0 },
3668
    { "bsfS", { Gv, Ev }, 0 },
3669
  },
3670
3671
  /* PREFIX_0FBD */
3672
  {
3673
    { "bsrS", { Gv, Ev }, 0 },
3674
    { "lzcntS", { Gv, Ev }, 0 },
3675
    { "bsrS", { Gv, Ev }, 0 },
3676
  },
3677
3678
  /* PREFIX_0FC2 */
3679
  {
3680
    { "VcmppX", { XM, Vex, EXx, CMP }, 0 },
3681
    { "Vcmpss", { XMScalar, VexScalar, EXd, CMP }, 0 },
3682
    { "VcmppX", { XM, Vex, EXx, CMP }, 0 },
3683
    { "Vcmpsd", { XMScalar, VexScalar, EXq, CMP }, 0 },
3684
  },
3685
3686
  /* PREFIX_0FC7_REG_6_MOD_0 */
3687
  {
3688
    { "vmptrld",{ Mq }, 0 },
3689
    { "vmxon",  { Mq }, 0 },
3690
    { "vmclear",{ Mq }, 0 },
3691
  },
3692
3693
  /* PREFIX_0FC7_REG_6_MOD_3 */
3694
  {
3695
    { "rdrand", { Ev }, 0 },
3696
    { X86_64_TABLE (X86_64_0FC7_REG_6_MOD_3_PREFIX_1) },
3697
    { "rdrand", { Ev }, 0 }
3698
  },
3699
3700
  /* PREFIX_0FC7_REG_7_MOD_3 */
3701
  {
3702
    { "rdseed", { Ev }, 0 },
3703
    { "rdpid",  { Em }, 0 },
3704
    { "rdseed", { Ev }, 0 },
3705
  },
3706
3707
  /* PREFIX_0FD0 */
3708
  {
3709
    { Bad_Opcode },
3710
    { Bad_Opcode },
3711
    { "VaddsubpX",  { XM, Vex, EXx }, 0 },
3712
    { "VaddsubpX",  { XM, Vex, EXx }, 0 },
3713
  },
3714
3715
  /* PREFIX_0FD6 */
3716
  {
3717
    { Bad_Opcode },
3718
    { "movq2dq",{ XM, Nq }, 0 },
3719
    { "movq", { EXqS, XM }, 0 },
3720
    { "movdq2q",{ MX, Ux }, 0 },
3721
  },
3722
3723
  /* PREFIX_0FE6 */
3724
  {
3725
    { Bad_Opcode },
3726
    { "Vcvtdq2pd",  { XM, EXxmmq }, 0 },
3727
    { "Vcvttpd2dq%XY",  { XMM, EXx }, 0 },
3728
    { "Vcvtpd2dq%XY", { XMM, EXx }, 0 },
3729
  },
3730
3731
  /* PREFIX_0FE7 */
3732
  {
3733
    { "movntq",   { Mq, MX }, 0 },
3734
    { Bad_Opcode },
3735
    { "movntdq",  { Mx, XM }, 0 },
3736
  },
3737
3738
  /* PREFIX_0FF0 */
3739
  {
3740
    { Bad_Opcode },
3741
    { Bad_Opcode },
3742
    { Bad_Opcode },
3743
    { "Vlddqu",   { XM, M }, 0 },
3744
  },
3745
3746
  /* PREFIX_0FF7 */
3747
  {
3748
    { "maskmovq", { MX, Nq }, PREFIX_OPCODE },
3749
    { Bad_Opcode },
3750
    { "maskmovdqu", { XM, Ux }, PREFIX_OPCODE },
3751
  },
3752
3753
  /* PREFIX_0F38D8 */
3754
  {
3755
    { Bad_Opcode },
3756
    { REG_TABLE (REG_0F38D8_PREFIX_1) },
3757
  },
3758
3759
  /* PREFIX_0F38DC */
3760
  {
3761
    { Bad_Opcode },
3762
    { MOD_TABLE (MOD_0F38DC_PREFIX_1) },
3763
    { "aesenc", { XM, EXx }, 0 },
3764
  },
3765
3766
  /* PREFIX_0F38DD */
3767
  {
3768
    { Bad_Opcode },
3769
    { "aesdec128kl", { XM, M }, 0 },
3770
    { "aesenclast", { XM, EXx }, 0 },
3771
  },
3772
3773
  /* PREFIX_0F38DE */
3774
  {
3775
    { Bad_Opcode },
3776
    { "aesenc256kl", { XM, M }, 0 },
3777
    { "aesdec", { XM, EXx }, 0 },
3778
  },
3779
3780
  /* PREFIX_0F38DF */
3781
  {
3782
    { Bad_Opcode },
3783
    { "aesdec256kl", { XM, M }, 0 },
3784
    { "aesdeclast", { XM, EXx }, 0 },
3785
  },
3786
3787
  /* PREFIX_0F38F0 */
3788
  {
3789
    { "movbeS", { Gv, Mv }, PREFIX_OPCODE },
3790
    { Bad_Opcode },
3791
    { "movbeS", { Gv, Mv }, PREFIX_OPCODE },
3792
    { "crc32A", { Gdq, Eb }, PREFIX_OPCODE },
3793
  },
3794
3795
  /* PREFIX_0F38F1 */
3796
  {
3797
    { "movbeS", { Mv, Gv }, PREFIX_OPCODE },
3798
    { Bad_Opcode },
3799
    { "movbeS", { Mv, Gv }, PREFIX_OPCODE },
3800
    { "crc32Q", { Gdq, Ev }, PREFIX_OPCODE },
3801
  },
3802
3803
  /* PREFIX_0F38F6 */
3804
  {
3805
    { "wrssK",  { M, Gdq }, 0 },
3806
    { "adoxL",  { VexGdq, Gdq, Edq }, 0 },
3807
    { "adcxL",  { VexGdq, Gdq, Edq }, 0 },
3808
    { Bad_Opcode },
3809
  },
3810
3811
  /* PREFIX_0F38F8_M_0 */
3812
  {
3813
    { Bad_Opcode },
3814
    { "enqcmds", { Gva, M }, 0 },
3815
    { "movdir64b", { Gva, M }, 0 },
3816
    { "enqcmd", { Gva, M }, 0 },
3817
  },
3818
3819
  /* PREFIX_0F38F8_M_1_X86_64 */
3820
  {
3821
    { Bad_Opcode },
3822
    { "uwrmsr",   { Gq, Rq }, 0 },
3823
    { Bad_Opcode },
3824
    { "urdmsr",   { Rq, Gq }, 0 },
3825
  },
3826
3827
  /* PREFIX_0F38FA */
3828
  {
3829
    { Bad_Opcode },
3830
    { "encodekey128", { Gd, Rd }, 0 },
3831
  },
3832
3833
  /* PREFIX_0F38FB */
3834
  {
3835
    { Bad_Opcode },
3836
    { "encodekey256", { Gd, Rd }, 0 },
3837
  },
3838
3839
  /* PREFIX_0F38FC */
3840
  {
3841
    { "aadd", { Mdq, Gdq }, 0 },
3842
    { "axor", { Mdq, Gdq }, 0 },
3843
    { "aand", { Mdq, Gdq }, 0 },
3844
    { "aor",  { Mdq, Gdq }, 0 },
3845
  },
3846
3847
  /* PREFIX_0F3A0F */
3848
  {
3849
    { Bad_Opcode },
3850
    { REG_TABLE (REG_0F3A0F_P_1) },
3851
  },
3852
3853
  /* PREFIX_VEX_0F12 */
3854
  {
3855
    { VEX_LEN_TABLE (VEX_LEN_0F12_P_0) },
3856
    { "%XEvmov%XSldup", { XM, EXEvexXNoBcst }, 0 },
3857
    { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
3858
    { "%XEvmov%XDdup",  { XM, EXymmq }, 0 },
3859
  },
3860
3861
  /* PREFIX_VEX_0F16 */
3862
  {
3863
    { VEX_LEN_TABLE (VEX_LEN_0F16_P_0) },
3864
    { "%XEvmov%XShdup", { XM, EXEvexXNoBcst }, 0 },
3865
    { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
3866
  },
3867
3868
  /* PREFIX_VEX_0F2A */
3869
  {
3870
    { Bad_Opcode },
3871
    { "%XEvcvtsi2ssY{%LQ|}",  { XMScalar, VexScalar, EXxEVexR, Edq }, 0 },
3872
    { Bad_Opcode },
3873
    { "%XEvcvtsi2sdY{%LQ|}",  { XMScalar, VexScalar, EXxEVexR64, Edq }, 0 },
3874
  },
3875
3876
  /* PREFIX_VEX_0F2C */
3877
  {
3878
    { Bad_Opcode },
3879
    { "%XEvcvttss2si",  { Gdq, EXd, EXxEVexS }, 0 },
3880
    { Bad_Opcode },
3881
    { "%XEvcvttsd2si",  { Gdq, EXq, EXxEVexS }, 0 },
3882
  },
3883
3884
  /* PREFIX_VEX_0F2D */
3885
  {
3886
    { Bad_Opcode },
3887
    { "%XEvcvtss2si", { Gdq, EXd, EXxEVexR }, 0 },
3888
    { Bad_Opcode },
3889
    { "%XEvcvtsd2si", { Gdq, EXq, EXxEVexR }, 0 },
3890
  },
3891
3892
  /* PREFIX_VEX_0F41_L_1_W_0 */
3893
  {
3894
    { "kandw",          { MaskG, MaskVex, MaskR }, 0 },
3895
    { Bad_Opcode },
3896
    { "kandb",          { MaskG, MaskVex, MaskR }, 0 },
3897
  },
3898
3899
  /* PREFIX_VEX_0F41_L_1_W_1 */
3900
  {
3901
    { "kandq",          { MaskG, MaskVex, MaskR }, 0 },
3902
    { Bad_Opcode },
3903
    { "kandd",          { MaskG, MaskVex, MaskR }, 0 },
3904
  },
3905
3906
  /* PREFIX_VEX_0F42_L_1_W_0 */
3907
  {
3908
    { "kandnw",         { MaskG, MaskVex, MaskR }, 0 },
3909
    { Bad_Opcode },
3910
    { "kandnb",         { MaskG, MaskVex, MaskR }, 0 },
3911
  },
3912
3913
  /* PREFIX_VEX_0F42_L_1_W_1 */
3914
  {
3915
    { "kandnq",         { MaskG, MaskVex, MaskR }, 0 },
3916
    { Bad_Opcode },
3917
    { "kandnd",         { MaskG, MaskVex, MaskR }, 0 },
3918
  },
3919
3920
  /* PREFIX_VEX_0F44_L_0_W_0 */
3921
  {
3922
    { "knotw",          { MaskG, MaskR }, 0 },
3923
    { Bad_Opcode },
3924
    { "knotb",          { MaskG, MaskR }, 0 },
3925
  },
3926
3927
  /* PREFIX_VEX_0F44_L_0_W_1 */
3928
  {
3929
    { "knotq",          { MaskG, MaskR }, 0 },
3930
    { Bad_Opcode },
3931
    { "knotd",          { MaskG, MaskR }, 0 },
3932
  },
3933
3934
  /* PREFIX_VEX_0F45_L_1_W_0 */
3935
  {
3936
    { "korw",       { MaskG, MaskVex, MaskR }, 0 },
3937
    { Bad_Opcode },
3938
    { "korb",       { MaskG, MaskVex, MaskR }, 0 },
3939
  },
3940
3941
  /* PREFIX_VEX_0F45_L_1_W_1 */
3942
  {
3943
    { "korq",       { MaskG, MaskVex, MaskR }, 0 },
3944
    { Bad_Opcode },
3945
    { "kord",       { MaskG, MaskVex, MaskR }, 0 },
3946
  },
3947
3948
  /* PREFIX_VEX_0F46_L_1_W_0 */
3949
  {
3950
    { "kxnorw",     { MaskG, MaskVex, MaskR }, 0 },
3951
    { Bad_Opcode },
3952
    { "kxnorb",     { MaskG, MaskVex, MaskR }, 0 },
3953
  },
3954
3955
  /* PREFIX_VEX_0F46_L_1_W_1 */
3956
  {
3957
    { "kxnorq",     { MaskG, MaskVex, MaskR }, 0 },
3958
    { Bad_Opcode },
3959
    { "kxnord",     { MaskG, MaskVex, MaskR }, 0 },
3960
  },
3961
3962
  /* PREFIX_VEX_0F47_L_1_W_0 */
3963
  {
3964
    { "kxorw",      { MaskG, MaskVex, MaskR }, 0 },
3965
    { Bad_Opcode },
3966
    { "kxorb",      { MaskG, MaskVex, MaskR }, 0 },
3967
  },
3968
3969
  /* PREFIX_VEX_0F47_L_1_W_1 */
3970
  {
3971
    { "kxorq",      { MaskG, MaskVex, MaskR }, 0 },
3972
    { Bad_Opcode },
3973
    { "kxord",      { MaskG, MaskVex, MaskR }, 0 },
3974
  },
3975
3976
  /* PREFIX_VEX_0F4A_L_1_W_0 */
3977
  {
3978
    { "kaddw",          { MaskG, MaskVex, MaskR }, 0 },
3979
    { Bad_Opcode },
3980
    { "kaddb",          { MaskG, MaskVex, MaskR }, 0 },
3981
  },
3982
3983
  /* PREFIX_VEX_0F4A_L_1_W_1 */
3984
  {
3985
    { "kaddq",          { MaskG, MaskVex, MaskR }, 0 },
3986
    { Bad_Opcode },
3987
    { "kaddd",          { MaskG, MaskVex, MaskR }, 0 },
3988
  },
3989
3990
  /* PREFIX_VEX_0F4B_L_1_W_0 */
3991
  {
3992
    { "kunpckwd",   { MaskG, MaskVex, MaskR }, 0 },
3993
    { Bad_Opcode },
3994
    { "kunpckbw",   { MaskG, MaskVex, MaskR }, 0 },
3995
  },
3996
3997
  /* PREFIX_VEX_0F4B_L_1_W_1 */
3998
  {
3999
    { "kunpckdq",   { MaskG, MaskVex, MaskR }, 0 },
4000
  },
4001
4002
  /* PREFIX_VEX_0F6F */
4003
  {
4004
    { Bad_Opcode },
4005
    { "vmovdqu",  { XM, EXx }, 0 },
4006
    { "vmovdqa",  { XM, EXx }, 0 },
4007
  },
4008
4009
  /* PREFIX_VEX_0F70 */
4010
  {
4011
    { Bad_Opcode },
4012
    { "vpshufhw", { XM, EXx, Ib }, 0 },
4013
    { "vpshufd",  { XM, EXx, Ib }, 0 },
4014
    { "vpshuflw", { XM, EXx, Ib }, 0 },
4015
  },
4016
4017
  /* PREFIX_VEX_0F7E */
4018
  {
4019
    { Bad_Opcode },
4020
    { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
4021
    { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
4022
  },
4023
4024
  /* PREFIX_VEX_0F7F */
4025
  {
4026
    { Bad_Opcode },
4027
    { "vmovdqu",  { EXxS, XM }, 0 },
4028
    { "vmovdqa",  { EXxS, XM }, 0 },
4029
  },
4030
4031
  /* PREFIX_VEX_0F90_L_0_W_0 */
4032
  {
4033
    { "%XEkmovw",   { MaskG, MaskE }, 0 },
4034
    { Bad_Opcode },
4035
    { "%XEkmovb",   { MaskG, MaskBDE }, 0 },
4036
  },
4037
4038
  /* PREFIX_VEX_0F90_L_0_W_1 */
4039
  {
4040
    { "%XEkmovq",   { MaskG, MaskE }, 0 },
4041
    { Bad_Opcode },
4042
    { "%XEkmovd",   { MaskG, MaskBDE }, 0 },
4043
  },
4044
4045
  /* PREFIX_VEX_0F91_L_0_W_0 */
4046
  {
4047
    { "%XEkmovw",   { Mw, MaskG }, 0 },
4048
    { Bad_Opcode },
4049
    { "%XEkmovb",   { Mb, MaskG }, 0 },
4050
  },
4051
4052
  /* PREFIX_VEX_0F91_L_0_W_1 */
4053
  {
4054
    { "%XEkmovq",   { Mq, MaskG }, 0 },
4055
    { Bad_Opcode },
4056
    { "%XEkmovd",   { Md, MaskG }, 0 },
4057
  },
4058
4059
  /* PREFIX_VEX_0F92_L_0_W_0 */
4060
  {
4061
    { "%XEkmovw",   { MaskG, Rdq }, 0 },
4062
    { Bad_Opcode },
4063
    { "%XEkmovb",   { MaskG, Rdq }, 0 },
4064
    { "%XEkmovd",   { MaskG, Rdq }, 0 },
4065
  },
4066
4067
  /* PREFIX_VEX_0F92_L_0_W_1 */
4068
  {
4069
    { Bad_Opcode },
4070
    { Bad_Opcode },
4071
    { Bad_Opcode },
4072
    { "%XEkmovK",   { MaskG, Rdq }, 0 },
4073
  },
4074
4075
  /* PREFIX_VEX_0F93_L_0_W_0 */
4076
  {
4077
    { "%XEkmovw",   { Gdq, MaskR }, 0 },
4078
    { Bad_Opcode },
4079
    { "%XEkmovb",   { Gdq, MaskR }, 0 },
4080
    { "%XEkmovd",   { Gdq, MaskR }, 0 },
4081
  },
4082
4083
  /* PREFIX_VEX_0F93_L_0_W_1 */
4084
  {
4085
    { Bad_Opcode },
4086
    { Bad_Opcode },
4087
    { Bad_Opcode },
4088
    { "%XEkmovK",   { Gdq, MaskR }, 0 },
4089
  },
4090
4091
  /* PREFIX_VEX_0F98_L_0_W_0 */
4092
  {
4093
    { "kortestw", { MaskG, MaskR }, 0 },
4094
    { Bad_Opcode },
4095
    { "kortestb", { MaskG, MaskR }, 0 },
4096
  },
4097
4098
  /* PREFIX_VEX_0F98_L_0_W_1 */
4099
  {
4100
    { "kortestq", { MaskG, MaskR }, 0 },
4101
    { Bad_Opcode },
4102
    { "kortestd", { MaskG, MaskR }, 0 },
4103
  },
4104
4105
  /* PREFIX_VEX_0F99_L_0_W_0 */
4106
  {
4107
    { "ktestw", { MaskG, MaskR }, 0 },
4108
    { Bad_Opcode },
4109
    { "ktestb", { MaskG, MaskR }, 0 },
4110
  },
4111
4112
  /* PREFIX_VEX_0F99_L_0_W_1 */
4113
  {
4114
    { "ktestq", { MaskG, MaskR }, 0 },
4115
    { Bad_Opcode },
4116
    { "ktestd", { MaskG, MaskR }, 0 },
4117
  },
4118
4119
  /* PREFIX_VEX_0F3848_X86_64_L_0_W_0 */
4120
  {
4121
    { "ttmmultf32ps", { TMM, Rtmm, VexTmm }, 0 },
4122
    { Bad_Opcode },
4123
    { "tmmultf32ps",  { TMM, Rtmm, VexTmm }, 0 },
4124
  },
4125
4126
  /* PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_0 */
4127
  {
4128
    { "ldtilecfg", { M }, 0 },
4129
    { Bad_Opcode },
4130
    { "sttilecfg", { M }, 0 },
4131
  },
4132
4133
  /* PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_1 */
4134
  {
4135
    { REG_TABLE (REG_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0) },
4136
    { Bad_Opcode },
4137
    { Bad_Opcode },
4138
    { RM_TABLE (RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_3) },
4139
  },
4140
4141
  /* PREFIX_VEX_0F384A_X86_64_W_0_L_0 */
4142
  {
4143
    { Bad_Opcode },
4144
    { Bad_Opcode },
4145
    { "tileloaddrst1",  { TMM, MVexSIBMEM }, 0 },
4146
    { "tileloaddrs",  { TMM, MVexSIBMEM }, 0 },
4147
  },
4148
4149
  /* PREFIX_VEX_0F384B_X86_64_L_0_W_0 */
4150
  {
4151
    { Bad_Opcode },
4152
    { "tilestored", { MVexSIBMEM, TMM }, 0 },
4153
    { "tileloaddt1",  { TMM, MVexSIBMEM }, 0 },
4154
    { "tileloadd",  { TMM, MVexSIBMEM }, 0 },
4155
  },
4156
4157
  /* PREFIX_VEX_0F3850_W_0 */
4158
  {
4159
    { "%XEvpdpbuud",  { XM, Vex, EXx }, 0 },
4160
    { "%XEvpdpbsud",  { XM, Vex, EXx }, 0 },
4161
    { "%XVvpdpbusd",  { XM, Vex, EXx }, 0 },
4162
    { "%XEvpdpbssd",  { XM, Vex, EXx }, 0 },
4163
  },
4164
4165
  /* PREFIX_VEX_0F3851_W_0 */
4166
  {
4167
    { "%XEvpdpbuuds", { XM, Vex, EXx }, 0 },
4168
    { "%XEvpdpbsuds", { XM, Vex, EXx }, 0 },
4169
    { "%XVvpdpbusds", { XM, Vex, EXx }, 0 },
4170
    { "%XEvpdpbssds", { XM, Vex, EXx }, 0 },
4171
  },
4172
  /* PREFIX_VEX_0F385C_X86_64_L_0_W_0 */
4173
  {
4174
    { Bad_Opcode },
4175
    { "tdpbf16ps", { TMM, Rtmm, VexTmm }, 0 },
4176
    { Bad_Opcode },
4177
    { "tdpfp16ps", { TMM, Rtmm, VexTmm }, 0 },
4178
  },
4179
4180
  /* PREFIX_VEX_0F385E_X86_64_L_0_W_0 */
4181
  {
4182
    { "tdpbuud", {TMM, Rtmm, VexTmm }, 0 },
4183
    { "tdpbsud", {TMM, Rtmm, VexTmm }, 0 },
4184
    { "tdpbusd", {TMM, Rtmm, VexTmm }, 0 },
4185
    { "tdpbssd", {TMM, Rtmm, VexTmm }, 0 },
4186
  },
4187
4188
  /* PREFIX_VEX_0F385F_X86_64_L_0_W_0 */
4189
  {
4190
    { Bad_Opcode },
4191
    { "ttransposed",  { TMM, Rtmm }, 0 },
4192
  },
4193
4194
  /* PREFIX_VEX_0F386B_X86_64_L_0_W_0 */
4195
  {
4196
    { "tconjtcmmimfp16ps",  { TMM, Rtmm, VexTmm }, 0 },
4197
    { "ttcmmrlfp16ps",  { TMM, Rtmm, VexTmm }, 0 },
4198
    { "tconjtfp16", { TMM, Rtmm }, 0 },
4199
    { "ttcmmimfp16ps",  { TMM, Rtmm, VexTmm }, 0 },
4200
  },
4201
4202
  /* PREFIX_VEX_0F386C_X86_64_L_0_W_0 */
4203
  {
4204
    { "tcmmrlfp16ps", { TMM, Rtmm, VexTmm }, 0 },
4205
    { "ttdpbf16ps", { TMM, Rtmm, VexTmm }, 0 },
4206
    { "tcmmimfp16ps", { TMM, Rtmm, VexTmm }, 0 },
4207
    { "ttdpfp16ps", { TMM, Rtmm, VexTmm }, 0 },
4208
  },
4209
4210
  /* PREFIX_VEX_0F386E_X86_64_L_0_W_0 */
4211
  {
4212
    { "t2rpntlvwz0",  { TMM, MVexSIBMEM }, 0 },
4213
    { Bad_Opcode },
4214
    { "t2rpntlvwz1",  { TMM, MVexSIBMEM }, 0 },
4215
  },
4216
4217
  /* PREFIX_VEX_0F386F_X86_64_L_0_W_0 */
4218
  {
4219
    { "t2rpntlvwz0t1",  { TMM, MVexSIBMEM }, 0 },
4220
    { Bad_Opcode },
4221
    { "t2rpntlvwz1t1",  { TMM, MVexSIBMEM }, 0 },
4222
  },
4223
4224
  /* PREFIX_VEX_0F3872 */
4225
  {
4226
    { Bad_Opcode },
4227
    { VEX_W_TABLE (VEX_W_0F3872_P_1) },
4228
  },
4229
4230
  /* PREFIX_VEX_0F38B0_W_0 */
4231
  {
4232
    { "vcvtneoph2ps", { XM, Mx }, 0 },
4233
    { "vcvtneebf162ps", { XM, Mx }, 0 },
4234
    { "vcvtneeph2ps", { XM, Mx }, 0 },
4235
    { "vcvtneobf162ps", { XM, Mx }, 0 },
4236
  },
4237
4238
  /* PREFIX_VEX_0F38B1_W_0 */
4239
  {
4240
    { Bad_Opcode },
4241
    { "vbcstnebf162ps", { XM, Mw }, 0 },
4242
    { "vbcstnesh2ps", { XM, Mw }, 0 },
4243
  },
4244
4245
  /* PREFIX_VEX_0F38D2_W_0 */
4246
  {
4247
    { "%XEvpdpwuud",  { XM, Vex, EXx }, 0 },
4248
    { "%XEvpdpwsud",  { XM, Vex, EXx }, 0 },
4249
    { "%XEvpdpwusd",  { XM, Vex, EXx }, 0 },
4250
  },
4251
4252
  /* PREFIX_VEX_0F38D3_W_0 */
4253
  {
4254
    { "%XEvpdpwuuds", { XM, Vex, EXx }, 0 },
4255
    { "%XEvpdpwsuds", { XM, Vex, EXx }, 0 },
4256
    { "%XEvpdpwusds", { XM, Vex, EXx }, 0 },
4257
  },
4258
4259
  /* PREFIX_VEX_0F38CB */
4260
  {
4261
    { Bad_Opcode },
4262
    { Bad_Opcode },
4263
    { Bad_Opcode },
4264
    { VEX_W_TABLE (VEX_W_0F38CB_P_3) },
4265
  },
4266
4267
  /* PREFIX_VEX_0F38CC */
4268
  {
4269
    { Bad_Opcode },
4270
    { Bad_Opcode },
4271
    { Bad_Opcode },
4272
    { VEX_W_TABLE (VEX_W_0F38CC_P_3) },
4273
  },
4274
4275
  /* PREFIX_VEX_0F38CD */
4276
  {
4277
    { Bad_Opcode },
4278
    { Bad_Opcode },
4279
    { Bad_Opcode },
4280
    { VEX_W_TABLE (VEX_W_0F38CD_P_3) },
4281
  },
4282
4283
  /* PREFIX_VEX_0F38DA_W_0 */
4284
  {
4285
    { VEX_LEN_TABLE (VEX_LEN_0F38DA_W_0_P_0) },
4286
    { "%XEvsm4key4",  { XM, Vex, EXx }, 0 },
4287
    { VEX_LEN_TABLE (VEX_LEN_0F38DA_W_0_P_2) },
4288
    { "%XEvsm4rnds4", { XM, Vex, EXx }, 0 },
4289
  },
4290
4291
  /* PREFIX_VEX_0F38F2_L_0 */
4292
  {
4293
    { "%NFandnS",          { Gdq, VexGdq, Edq }, 0 },
4294
  },
4295
4296
  /* PREFIX_VEX_0F38F3_L_0 */
4297
  {
4298
    { REG_TABLE (REG_VEX_0F38F3_L_0_P_0) },
4299
  },
4300
4301
  /* PREFIX_VEX_0F38F5_L_0 */
4302
  {
4303
    { "%NFbzhiS", { Gdq, Edq, VexGdq }, 0 },
4304
    { "%XEpextS",   { Gdq, VexGdq, Edq }, 0 },
4305
    { Bad_Opcode },
4306
    { "%XEpdepS",   { Gdq, VexGdq, Edq }, 0 },
4307
  },
4308
4309
  /* PREFIX_VEX_0F38F6_L_0 */
4310
  {
4311
    { Bad_Opcode },
4312
    { Bad_Opcode },
4313
    { Bad_Opcode },
4314
    { "%XEmulxS",   { Gdq, VexGdq, Edq }, 0 },
4315
  },
4316
4317
  /* PREFIX_VEX_0F38F7_L_0 */
4318
  {
4319
    { "%NFbextrS",  { Gdq, Edq, VexGdq }, 0 },
4320
    { "%XEsarxS",   { Gdq, Edq, VexGdq }, 0 },
4321
    { "%XEshlxS",   { Gdq, Edq, VexGdq }, 0 },
4322
    { "%XEshrxS",   { Gdq, Edq, VexGdq }, 0 },
4323
  },
4324
4325
  /* PREFIX_VEX_0F3AF0_L_0 */
4326
  {
4327
    { Bad_Opcode },
4328
    { Bad_Opcode },
4329
    { Bad_Opcode },
4330
    { "%XErorxS",   { Gdq, Edq, Ib }, 0 },
4331
  },
4332
4333
  /* PREFIX_VEX_MAP5_F8_X86_64_L_0_W_0 */
4334
  {
4335
    { "t2rpntlvwz0rs",  { TMM, MVexSIBMEM }, 0 },
4336
    { Bad_Opcode },
4337
    { "t2rpntlvwz1rs",  { TMM, MVexSIBMEM }, 0 },
4338
  },
4339
4340
  /* PREFIX_VEX_MAP5_F9_X86_64_L_0_W_0 */
4341
  {
4342
    { "t2rpntlvwz0rst1",  { TMM, MVexSIBMEM }, 0 },
4343
    { Bad_Opcode },
4344
    { "t2rpntlvwz1rst1",  { TMM, MVexSIBMEM }, 0 },
4345
  },
4346
4347
  /* PREFIX_VEX_MAP5_FD_X86_64_L_0_W_0 */
4348
  {
4349
    { "tdpbf8ps", { TMM, Rtmm, VexTmm }, 0 },
4350
    { "tdphbf8ps",  { TMM, Rtmm, VexTmm }, 0 },
4351
    { "tdphf8ps", { TMM, Rtmm, VexTmm }, 0 },
4352
    { "tdpbhf8ps",  { TMM, Rtmm, VexTmm }, 0 },
4353
  },
4354
4355
  /* PREFIX_VEX_MAP7_F6_L_0_W_0_R_0_X86_64 */
4356
  {
4357
    { Bad_Opcode },
4358
    { "wrmsrns",  { Skip_MODRM, Id, Rq }, 0 },
4359
    { Bad_Opcode },
4360
    { "rdmsr",    { Rq, Id }, 0 },
4361
  },
4362
4363
  /* PREFIX_VEX_MAP7_F8_L_0_W_0_R_0_X86_64 */
4364
  {
4365
    { Bad_Opcode },
4366
    { "uwrmsr", { Skip_MODRM, Id, Rq }, 0 },
4367
    { Bad_Opcode },
4368
    { "urdmsr", { Rq, Id }, 0 },
4369
  },
4370
4371
#include "i386-dis-evex-prefix.h"
4372
};
4373
4374
static const struct dis386 x86_64_table[][2] = {
4375
  /* X86_64_06 */
4376
  {
4377
    { "pushP", { es }, 0 },
4378
  },
4379
4380
  /* X86_64_07 */
4381
  {
4382
    { "popP", { es }, 0 },
4383
  },
4384
4385
  /* X86_64_0E */
4386
  {
4387
    { "pushP", { cs }, 0 },
4388
  },
4389
4390
  /* X86_64_16 */
4391
  {
4392
    { "pushP", { ss }, 0 },
4393
  },
4394
4395
  /* X86_64_17 */
4396
  {
4397
    { "popP", { ss }, 0 },
4398
  },
4399
4400
  /* X86_64_1E */
4401
  {
4402
    { "pushP", { ds }, 0 },
4403
  },
4404
4405
  /* X86_64_1F */
4406
  {
4407
    { "popP", { ds }, 0 },
4408
  },
4409
4410
  /* X86_64_27 */
4411
  {
4412
    { "daa", { XX }, 0 },
4413
  },
4414
4415
  /* X86_64_2F */
4416
  {
4417
    { "das", { XX }, 0 },
4418
  },
4419
4420
  /* X86_64_37 */
4421
  {
4422
    { "aaa", { XX }, 0 },
4423
  },
4424
4425
  /* X86_64_3F */
4426
  {
4427
    { "aas", { XX }, 0 },
4428
  },
4429
4430
  /* X86_64_60 */
4431
  {
4432
    { "pushaP", { XX }, 0 },
4433
  },
4434
4435
  /* X86_64_61 */
4436
  {
4437
    { "popaP", { XX }, 0 },
4438
  },
4439
4440
  /* X86_64_62 */
4441
  {
4442
    { MOD_TABLE (MOD_62_32BIT) },
4443
    { EVEX_TABLE () },
4444
  },
4445
4446
  /* X86_64_63 */
4447
  {
4448
    { "arplS", { Sv, Gv }, 0 },
4449
    { "movs", { Gv, { MOVSXD_Fixup, movsxd_mode } }, 0 },
4450
  },
4451
4452
  /* X86_64_6D */
4453
  {
4454
    { "ins{R|}", { Yzr, indirDX }, 0 },
4455
    { "ins{G|}", { Yzr, indirDX }, 0 },
4456
  },
4457
4458
  /* X86_64_6F */
4459
  {
4460
    { "outs{R|}", { indirDXr, Xz }, 0 },
4461
    { "outs{G|}", { indirDXr, Xz }, 0 },
4462
  },
4463
4464
  /* X86_64_82 */
4465
  {
4466
    /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode.  */
4467
    { REG_TABLE (REG_80) },
4468
  },
4469
4470
  /* X86_64_9A */
4471
  {
4472
    { "{l|}call{P|}", { Ap }, 0 },
4473
  },
4474
4475
  /* X86_64_C2 */
4476
  {
4477
    { "retP",   { Iw, BND }, 0 },
4478
    { "ret@",   { Iw, BND }, 0 },
4479
  },
4480
4481
  /* X86_64_C3 */
4482
  {
4483
    { "retP",   { BND }, 0 },
4484
    { "ret@",   { BND }, 0 },
4485
  },
4486
4487
  /* X86_64_C4 */
4488
  {
4489
    { MOD_TABLE (MOD_C4_32BIT) },
4490
    { VEX_C4_TABLE () },
4491
  },
4492
4493
  /* X86_64_C5 */
4494
  {
4495
    { MOD_TABLE (MOD_C5_32BIT) },
4496
    { VEX_C5_TABLE () },
4497
  },
4498
4499
  /* X86_64_CE */
4500
  {
4501
    { "into", { XX }, 0 },
4502
  },
4503
4504
  /* X86_64_D4 */
4505
  {
4506
    { "aam", { Ib }, 0 },
4507
  },
4508
4509
  /* X86_64_D5 */
4510
  {
4511
    { "aad", { Ib }, 0 },
4512
  },
4513
4514
  /* X86_64_E8 */
4515
  {
4516
    { "callP",    { Jv, BND }, 0 },
4517
    { "call@",    { Jv, BND }, PREFIX_REX2_ILLEGAL }
4518
  },
4519
4520
  /* X86_64_E9 */
4521
  {
4522
    { "jmpP",   { Jv, BND }, 0 },
4523
    { "jmp@",   { Jv, BND }, PREFIX_REX2_ILLEGAL }
4524
  },
4525
4526
  /* X86_64_EA */
4527
  {
4528
    { "{l|}jmp{P|}", { Ap }, 0 },
4529
  },
4530
4531
  /* X86_64_0F00_REG_6 */
4532
  {
4533
    { Bad_Opcode },
4534
    { PREFIX_TABLE (PREFIX_0F00_REG_6_X86_64) },
4535
  },
4536
4537
  /* X86_64_0F01_REG_0 */
4538
  {
4539
    { "sgdt{Q|Q}", { M }, 0 },
4540
    { "sgdt", { M }, 0 },
4541
  },
4542
4543
  /* X86_64_0F01_REG_0_MOD_3_RM_6_P_1 */
4544
  {
4545
    { Bad_Opcode },
4546
    { "wrmsrlist",  { Skip_MODRM }, 0 },
4547
  },
4548
4549
  /* X86_64_0F01_REG_0_MOD_3_RM_6_P_3 */
4550
  {
4551
    { Bad_Opcode },
4552
    { "rdmsrlist",  { Skip_MODRM }, 0 },
4553
  },
4554
4555
  /* X86_64_0F01_REG_0_MOD_3_RM_7_P_0 */
4556
  {
4557
    { Bad_Opcode },
4558
    { "pbndkb",   { Skip_MODRM }, 0 },
4559
  },
4560
4561
  /* X86_64_0F01_REG_1 */
4562
  {
4563
    { "sidt{Q|Q}", { M }, 0 },
4564
    { "sidt", { M }, 0 },
4565
  },
4566
4567
  /* X86_64_0F01_REG_1_RM_2_PREFIX_1 */
4568
  {
4569
    { Bad_Opcode },
4570
    { "eretu",    { Skip_MODRM }, 0 },
4571
  },
4572
4573
  /* X86_64_0F01_REG_1_RM_2_PREFIX_3 */
4574
  {
4575
    { Bad_Opcode },
4576
    { "erets",    { Skip_MODRM }, 0 },
4577
  },
4578
4579
  /* X86_64_0F01_REG_1_RM_5_PREFIX_2 */
4580
  {
4581
    { Bad_Opcode },
4582
    { "seamret",  { Skip_MODRM }, 0 },
4583
  },
4584
4585
  /* X86_64_0F01_REG_1_RM_6_PREFIX_2 */
4586
  {
4587
    { Bad_Opcode },
4588
    { "seamops",  { Skip_MODRM }, 0 },
4589
  },
4590
4591
  /* X86_64_0F01_REG_1_RM_7_PREFIX_2 */
4592
  {
4593
    { Bad_Opcode },
4594
    { "seamcall", { Skip_MODRM }, 0 },
4595
  },
4596
4597
  /* X86_64_0F01_REG_2 */
4598
  {
4599
    { "lgdt{Q|Q}", { M }, 0 },
4600
    { "lgdt", { M }, 0 },
4601
  },
4602
4603
  /* X86_64_0F01_REG_3 */
4604
  {
4605
    { "lidt{Q|Q}", { M }, 0 },
4606
    { "lidt", { M }, 0 },
4607
  },
4608
4609
  /* X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1 */
4610
  {
4611
    { Bad_Opcode },
4612
    { "uiret",  { Skip_MODRM }, 0 },
4613
  },
4614
4615
  /* X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1 */
4616
  {
4617
    { Bad_Opcode },
4618
    { "testui", { Skip_MODRM }, 0 },
4619
  },
4620
4621
  /* X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1 */
4622
  {
4623
    { Bad_Opcode },
4624
    { "clui", { Skip_MODRM }, 0 },
4625
  },
4626
4627
  /* X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1 */
4628
  {
4629
    { Bad_Opcode },
4630
    { "stui", { Skip_MODRM }, 0 },
4631
  },
4632
4633
  /* X86_64_0F01_REG_7_MOD_3_RM_5_PREFIX_1 */
4634
  {
4635
    { Bad_Opcode },
4636
    { "rmpquery", { Skip_MODRM }, 0 },
4637
  },
4638
4639
  /* X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3 */
4640
  {
4641
    { Bad_Opcode },
4642
    { "rmpread",  { DSCX, RMrAX, Skip_MODRM }, 0 },
4643
  },
4644
4645
  /* X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1 */
4646
  {
4647
    { Bad_Opcode },
4648
    { "rmpadjust",  { Skip_MODRM }, 0 },
4649
  },
4650
4651
  /* X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3 */
4652
  {
4653
    { Bad_Opcode },
4654
    { "rmpupdate",  { RMrAX, DSCX, Skip_MODRM }, 0 },
4655
  },
4656
4657
  /* X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1 */
4658
  {
4659
    { Bad_Opcode },
4660
    { "psmash", { Skip_MODRM }, 0 },
4661
  },
4662
4663
  /* X86_64_0F18_REG_6_MOD_0 */
4664
  {
4665
    { "nopQ",   { Ev }, 0 },
4666
    { PREFIX_TABLE (PREFIX_0F18_REG_6_MOD_0_X86_64) },
4667
  },
4668
4669
  /* X86_64_0F18_REG_7_MOD_0 */
4670
  {
4671
    { "nopQ",   { Ev }, 0 },
4672
    { PREFIX_TABLE (PREFIX_0F18_REG_7_MOD_0_X86_64) },
4673
  },
4674
4675
  {
4676
    /* X86_64_0F24 */
4677
    { "movZ",   { Em, Td }, 0 },
4678
  },
4679
4680
  {
4681
    /* X86_64_0F26 */
4682
    { "movZ",   { Td, Em }, 0 },
4683
  },
4684
4685
  {
4686
    /* X86_64_0F388A */
4687
    { Bad_Opcode },
4688
    { "movrsB",   { Gb, Mb }, PREFIX_OPCODE },
4689
  },
4690
4691
  {
4692
    /* X86_64_0F388B */
4693
    { Bad_Opcode },
4694
    { "movrsS",   { Gv, Mv }, PREFIX_OPCODE },
4695
  },
4696
4697
  {
4698
    /* X86_64_0F38F8_M_1 */
4699
    { Bad_Opcode },
4700
    { PREFIX_TABLE (PREFIX_0F38F8_M_1_X86_64) },
4701
  },
4702
4703
  /* X86_64_0FC7_REG_6_MOD_3_PREFIX_1 */
4704
  {
4705
    { Bad_Opcode },
4706
    { "senduipi", { Eq }, 0 },
4707
  },
4708
4709
  /* X86_64_VEX_0F3848 */
4710
  {
4711
    { Bad_Opcode },
4712
    { VEX_LEN_TABLE (VEX_LEN_0F3848_X86_64) },
4713
  },
4714
4715
  /* X86_64_VEX_0F3849 */
4716
  {
4717
    { Bad_Opcode },
4718
    { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64) },
4719
  },
4720
4721
  /* X86_64_VEX_0F384A */
4722
  {
4723
    { Bad_Opcode },
4724
    { VEX_W_TABLE (VEX_W_0F384A_X86_64) },
4725
  },
4726
4727
  /* X86_64_VEX_0F384B */
4728
  {
4729
    { Bad_Opcode },
4730
    { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64) },
4731
  },
4732
4733
  /* X86_64_VEX_0F385C */
4734
  {
4735
    { Bad_Opcode },
4736
    { VEX_LEN_TABLE (VEX_LEN_0F385C_X86_64) },
4737
  },
4738
4739
  /* X86_64_VEX_0F385E */
4740
  {
4741
    { Bad_Opcode },
4742
    { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64) },
4743
  },
4744
4745
  /* X86_64_VEX_0F385F */
4746
  {
4747
    { Bad_Opcode },
4748
    { VEX_LEN_TABLE (VEX_LEN_0F385F_X86_64) },
4749
  },
4750
4751
  /* X86_64_VEX_0F386B */
4752
  {
4753
    { Bad_Opcode },
4754
    { VEX_LEN_TABLE (VEX_LEN_0F386B_X86_64) },
4755
  },
4756
4757
  /* X86_64_VEX_0F386C */
4758
  {
4759
    { Bad_Opcode },
4760
    { VEX_LEN_TABLE (VEX_LEN_0F386C_X86_64) },
4761
  },
4762
4763
  /* X86_64_VEX_0F386E */
4764
  {
4765
    { Bad_Opcode },
4766
    { VEX_LEN_TABLE (VEX_LEN_0F386E_X86_64) },
4767
  },
4768
4769
  /* X86_64_VEX_0F386F */
4770
  {
4771
    { Bad_Opcode },
4772
    { VEX_LEN_TABLE (VEX_LEN_0F386F_X86_64) },
4773
  },
4774
4775
  /* X86_64_VEX_0F38Ex */
4776
  {
4777
    { Bad_Opcode },
4778
    { "%XEcmp%CCxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4779
  },
4780
4781
  /* X86_64_VEX_MAP5_F8 */
4782
  {
4783
    { Bad_Opcode },
4784
    { VEX_LEN_TABLE (VEX_LEN_MAP5_F8_X86_64) },
4785
  },
4786
4787
  /* X86_64_VEX_MAP5_F9 */
4788
  {
4789
    { Bad_Opcode },
4790
    { VEX_LEN_TABLE (VEX_LEN_MAP5_F9_X86_64) },
4791
  },
4792
4793
  /* X86_64_VEX_MAP5_FD */
4794
  {
4795
    { Bad_Opcode },
4796
    { VEX_LEN_TABLE (VEX_LEN_MAP5_FD_X86_64) },
4797
  },
4798
4799
  /* X86_64_VEX_MAP7_F6_L_0_W_0_R_0 */
4800
  {
4801
    { Bad_Opcode },
4802
    { PREFIX_TABLE (PREFIX_VEX_MAP7_F6_L_0_W_0_R_0_X86_64) },
4803
  },
4804
4805
  /* X86_64_VEX_MAP7_F8_L_0_W_0_R_0 */
4806
  {
4807
    { Bad_Opcode },
4808
    { PREFIX_TABLE (PREFIX_VEX_MAP7_F8_L_0_W_0_R_0_X86_64) },
4809
  },
4810
4811
#include "i386-dis-evex-x86-64.h"
4812
};
4813
4814
static const struct dis386 three_byte_table[][256] = {
4815
4816
  /* THREE_BYTE_0F38 */
4817
  {
4818
    /* 00 */
4819
    { "pshufb",   { MX, EM }, PREFIX_OPCODE },
4820
    { "phaddw",   { MX, EM }, PREFIX_OPCODE },
4821
    { "phaddd",   { MX, EM }, PREFIX_OPCODE },
4822
    { "phaddsw",  { MX, EM }, PREFIX_OPCODE },
4823
    { "pmaddubsw",  { MX, EM }, PREFIX_OPCODE },
4824
    { "phsubw",   { MX, EM }, PREFIX_OPCODE },
4825
    { "phsubd",   { MX, EM }, PREFIX_OPCODE },
4826
    { "phsubsw",  { MX, EM }, PREFIX_OPCODE },
4827
    /* 08 */
4828
    { "psignb",   { MX, EM }, PREFIX_OPCODE },
4829
    { "psignw",   { MX, EM }, PREFIX_OPCODE },
4830
    { "psignd",   { MX, EM }, PREFIX_OPCODE },
4831
    { "pmulhrsw", { MX, EM }, PREFIX_OPCODE },
4832
    { Bad_Opcode },
4833
    { Bad_Opcode },
4834
    { Bad_Opcode },
4835
    { Bad_Opcode },
4836
    /* 10 */
4837
    { "pblendvb", { XM, EXx, XMM0 }, PREFIX_DATA },
4838
    { Bad_Opcode },
4839
    { Bad_Opcode },
4840
    { Bad_Opcode },
4841
    { "blendvps", { XM, EXx, XMM0 }, PREFIX_DATA },
4842
    { "blendvpd", { XM, EXx, XMM0 }, PREFIX_DATA },
4843
    { Bad_Opcode },
4844
    { "ptest",  { XM, EXx }, PREFIX_DATA },
4845
    /* 18 */
4846
    { Bad_Opcode },
4847
    { Bad_Opcode },
4848
    { Bad_Opcode },
4849
    { Bad_Opcode },
4850
    { "pabsb",    { MX, EM }, PREFIX_OPCODE },
4851
    { "pabsw",    { MX, EM }, PREFIX_OPCODE },
4852
    { "pabsd",    { MX, EM }, PREFIX_OPCODE },
4853
    { Bad_Opcode },
4854
    /* 20 */
4855
    { "pmovsxbw", { XM, EXq }, PREFIX_DATA },
4856
    { "pmovsxbd", { XM, EXd }, PREFIX_DATA },
4857
    { "pmovsxbq", { XM, EXw }, PREFIX_DATA },
4858
    { "pmovsxwd", { XM, EXq }, PREFIX_DATA },
4859
    { "pmovsxwq", { XM, EXd }, PREFIX_DATA },
4860
    { "pmovsxdq", { XM, EXq }, PREFIX_DATA },
4861
    { Bad_Opcode },
4862
    { Bad_Opcode },
4863
    /* 28 */
4864
    { "pmuldq", { XM, EXx }, PREFIX_DATA },
4865
    { "pcmpeqq", { XM, EXx }, PREFIX_DATA },
4866
    { "movntdqa", { XM, Mx }, PREFIX_DATA },
4867
    { "packusdw", { XM, EXx }, PREFIX_DATA },
4868
    { Bad_Opcode },
4869
    { Bad_Opcode },
4870
    { Bad_Opcode },
4871
    { Bad_Opcode },
4872
    /* 30 */
4873
    { "pmovzxbw", { XM, EXq }, PREFIX_DATA },
4874
    { "pmovzxbd", { XM, EXd }, PREFIX_DATA },
4875
    { "pmovzxbq", { XM, EXw }, PREFIX_DATA },
4876
    { "pmovzxwd", { XM, EXq }, PREFIX_DATA },
4877
    { "pmovzxwq", { XM, EXd }, PREFIX_DATA },
4878
    { "pmovzxdq", { XM, EXq }, PREFIX_DATA },
4879
    { Bad_Opcode },
4880
    { "pcmpgtq", { XM, EXx }, PREFIX_DATA },
4881
    /* 38 */
4882
    { "pminsb", { XM, EXx }, PREFIX_DATA },
4883
    { "pminsd", { XM, EXx }, PREFIX_DATA },
4884
    { "pminuw", { XM, EXx }, PREFIX_DATA },
4885
    { "pminud", { XM, EXx }, PREFIX_DATA },
4886
    { "pmaxsb", { XM, EXx }, PREFIX_DATA },
4887
    { "pmaxsd", { XM, EXx }, PREFIX_DATA },
4888
    { "pmaxuw", { XM, EXx }, PREFIX_DATA },
4889
    { "pmaxud", { XM, EXx }, PREFIX_DATA },
4890
    /* 40 */
4891
    { "pmulld", { XM, EXx }, PREFIX_DATA },
4892
    { "phminposuw", { XM, EXx }, PREFIX_DATA },
4893
    { Bad_Opcode },
4894
    { Bad_Opcode },
4895
    { Bad_Opcode },
4896
    { Bad_Opcode },
4897
    { Bad_Opcode },
4898
    { Bad_Opcode },
4899
    /* 48 */
4900
    { Bad_Opcode },
4901
    { Bad_Opcode },
4902
    { Bad_Opcode },
4903
    { Bad_Opcode },
4904
    { Bad_Opcode },
4905
    { Bad_Opcode },
4906
    { Bad_Opcode },
4907
    { Bad_Opcode },
4908
    /* 50 */
4909
    { Bad_Opcode },
4910
    { Bad_Opcode },
4911
    { Bad_Opcode },
4912
    { Bad_Opcode },
4913
    { Bad_Opcode },
4914
    { Bad_Opcode },
4915
    { Bad_Opcode },
4916
    { Bad_Opcode },
4917
    /* 58 */
4918
    { Bad_Opcode },
4919
    { Bad_Opcode },
4920
    { Bad_Opcode },
4921
    { Bad_Opcode },
4922
    { Bad_Opcode },
4923
    { Bad_Opcode },
4924
    { Bad_Opcode },
4925
    { Bad_Opcode },
4926
    /* 60 */
4927
    { Bad_Opcode },
4928
    { Bad_Opcode },
4929
    { Bad_Opcode },
4930
    { Bad_Opcode },
4931
    { Bad_Opcode },
4932
    { Bad_Opcode },
4933
    { Bad_Opcode },
4934
    { Bad_Opcode },
4935
    /* 68 */
4936
    { Bad_Opcode },
4937
    { Bad_Opcode },
4938
    { Bad_Opcode },
4939
    { Bad_Opcode },
4940
    { Bad_Opcode },
4941
    { Bad_Opcode },
4942
    { Bad_Opcode },
4943
    { Bad_Opcode },
4944
    /* 70 */
4945
    { Bad_Opcode },
4946
    { Bad_Opcode },
4947
    { Bad_Opcode },
4948
    { Bad_Opcode },
4949
    { Bad_Opcode },
4950
    { Bad_Opcode },
4951
    { Bad_Opcode },
4952
    { Bad_Opcode },
4953
    /* 78 */
4954
    { Bad_Opcode },
4955
    { Bad_Opcode },
4956
    { Bad_Opcode },
4957
    { Bad_Opcode },
4958
    { Bad_Opcode },
4959
    { Bad_Opcode },
4960
    { Bad_Opcode },
4961
    { Bad_Opcode },
4962
    /* 80 */
4963
    { "invept", { Gm, Mo }, PREFIX_DATA },
4964
    { "invvpid", { Gm, Mo }, PREFIX_DATA },
4965
    { "invpcid", { Gm, M }, PREFIX_DATA },
4966
    { Bad_Opcode },
4967
    { Bad_Opcode },
4968
    { Bad_Opcode },
4969
    { Bad_Opcode },
4970
    { Bad_Opcode },
4971
    /* 88 */
4972
    { Bad_Opcode },
4973
    { Bad_Opcode },
4974
    { X86_64_TABLE (X86_64_0F388A) },
4975
    { X86_64_TABLE (X86_64_0F388B) },
4976
    { Bad_Opcode },
4977
    { Bad_Opcode },
4978
    { Bad_Opcode },
4979
    { Bad_Opcode },
4980
    /* 90 */
4981
    { Bad_Opcode },
4982
    { Bad_Opcode },
4983
    { Bad_Opcode },
4984
    { Bad_Opcode },
4985
    { Bad_Opcode },
4986
    { Bad_Opcode },
4987
    { Bad_Opcode },
4988
    { Bad_Opcode },
4989
    /* 98 */
4990
    { Bad_Opcode },
4991
    { Bad_Opcode },
4992
    { Bad_Opcode },
4993
    { Bad_Opcode },
4994
    { Bad_Opcode },
4995
    { Bad_Opcode },
4996
    { Bad_Opcode },
4997
    { Bad_Opcode },
4998
    /* a0 */
4999
    { Bad_Opcode },
5000
    { Bad_Opcode },
5001
    { Bad_Opcode },
5002
    { Bad_Opcode },
5003
    { Bad_Opcode },
5004
    { Bad_Opcode },
5005
    { Bad_Opcode },
5006
    { Bad_Opcode },
5007
    /* a8 */
5008
    { Bad_Opcode },
5009
    { Bad_Opcode },
5010
    { Bad_Opcode },
5011
    { Bad_Opcode },
5012
    { Bad_Opcode },
5013
    { Bad_Opcode },
5014
    { Bad_Opcode },
5015
    { Bad_Opcode },
5016
    /* b0 */
5017
    { Bad_Opcode },
5018
    { Bad_Opcode },
5019
    { Bad_Opcode },
5020
    { Bad_Opcode },
5021
    { Bad_Opcode },
5022
    { Bad_Opcode },
5023
    { Bad_Opcode },
5024
    { Bad_Opcode },
5025
    /* b8 */
5026
    { Bad_Opcode },
5027
    { Bad_Opcode },
5028
    { Bad_Opcode },
5029
    { Bad_Opcode },
5030
    { Bad_Opcode },
5031
    { Bad_Opcode },
5032
    { Bad_Opcode },
5033
    { Bad_Opcode },
5034
    /* c0 */
5035
    { Bad_Opcode },
5036
    { Bad_Opcode },
5037
    { Bad_Opcode },
5038
    { Bad_Opcode },
5039
    { Bad_Opcode },
5040
    { Bad_Opcode },
5041
    { Bad_Opcode },
5042
    { Bad_Opcode },
5043
    /* c8 */
5044
    { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
5045
    { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
5046
    { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
5047
    { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
5048
    { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
5049
    { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
5050
    { Bad_Opcode },
5051
    { "gf2p8mulb", { XM, EXxmm }, PREFIX_DATA },
5052
    /* d0 */
5053
    { Bad_Opcode },
5054
    { Bad_Opcode },
5055
    { Bad_Opcode },
5056
    { Bad_Opcode },
5057
    { Bad_Opcode },
5058
    { Bad_Opcode },
5059
    { Bad_Opcode },
5060
    { Bad_Opcode },
5061
    /* d8 */
5062
    { PREFIX_TABLE (PREFIX_0F38D8) },
5063
    { Bad_Opcode },
5064
    { Bad_Opcode },
5065
    { "aesimc", { XM, EXx }, PREFIX_DATA },
5066
    { PREFIX_TABLE (PREFIX_0F38DC) },
5067
    { PREFIX_TABLE (PREFIX_0F38DD) },
5068
    { PREFIX_TABLE (PREFIX_0F38DE) },
5069
    { PREFIX_TABLE (PREFIX_0F38DF) },
5070
    /* e0 */
5071
    { Bad_Opcode },
5072
    { Bad_Opcode },
5073
    { Bad_Opcode },
5074
    { Bad_Opcode },
5075
    { Bad_Opcode },
5076
    { Bad_Opcode },
5077
    { Bad_Opcode },
5078
    { Bad_Opcode },
5079
    /* e8 */
5080
    { Bad_Opcode },
5081
    { Bad_Opcode },
5082
    { Bad_Opcode },
5083
    { Bad_Opcode },
5084
    { Bad_Opcode },
5085
    { Bad_Opcode },
5086
    { Bad_Opcode },
5087
    { Bad_Opcode },
5088
    /* f0 */
5089
    { PREFIX_TABLE (PREFIX_0F38F0) },
5090
    { PREFIX_TABLE (PREFIX_0F38F1) },
5091
    { Bad_Opcode },
5092
    { Bad_Opcode },
5093
    { Bad_Opcode },
5094
    { "wrussK",   { M, Gdq }, PREFIX_DATA },
5095
    { PREFIX_TABLE (PREFIX_0F38F6) },
5096
    { Bad_Opcode },
5097
    /* f8 */
5098
    { MOD_TABLE (MOD_0F38F8) },
5099
    { "movdiri",  { Mdq, Gdq }, PREFIX_OPCODE },
5100
    { PREFIX_TABLE (PREFIX_0F38FA) },
5101
    { PREFIX_TABLE (PREFIX_0F38FB) },
5102
    { PREFIX_TABLE (PREFIX_0F38FC) },
5103
    { Bad_Opcode },
5104
    { Bad_Opcode },
5105
    { Bad_Opcode },
5106
  },
5107
  /* THREE_BYTE_0F3A */
5108
  {
5109
    /* 00 */
5110
    { Bad_Opcode },
5111
    { Bad_Opcode },
5112
    { Bad_Opcode },
5113
    { Bad_Opcode },
5114
    { Bad_Opcode },
5115
    { Bad_Opcode },
5116
    { Bad_Opcode },
5117
    { Bad_Opcode },
5118
    /* 08 */
5119
    { "roundps", { XM, EXx, Ib }, PREFIX_DATA },
5120
    { "roundpd", { XM, EXx, Ib }, PREFIX_DATA },
5121
    { "roundss", { XM, EXd, Ib }, PREFIX_DATA },
5122
    { "roundsd", { XM, EXq, Ib }, PREFIX_DATA },
5123
    { "blendps", { XM, EXx, Ib }, PREFIX_DATA },
5124
    { "blendpd", { XM, EXx, Ib }, PREFIX_DATA },
5125
    { "pblendw", { XM, EXx, Ib }, PREFIX_DATA },
5126
    { "palignr",  { MX, EM, Ib }, PREFIX_OPCODE },
5127
    /* 10 */
5128
    { Bad_Opcode },
5129
    { Bad_Opcode },
5130
    { Bad_Opcode },
5131
    { Bad_Opcode },
5132
    { "pextrb", { Edb, XM, Ib }, PREFIX_DATA },
5133
    { "pextrw", { Edw, XM, Ib }, PREFIX_DATA },
5134
    { "pextrK", { Edq, XM, Ib }, PREFIX_DATA },
5135
    { "extractps", { Ed, XM, Ib }, PREFIX_DATA },
5136
    /* 18 */
5137
    { Bad_Opcode },
5138
    { Bad_Opcode },
5139
    { Bad_Opcode },
5140
    { Bad_Opcode },
5141
    { Bad_Opcode },
5142
    { Bad_Opcode },
5143
    { Bad_Opcode },
5144
    { Bad_Opcode },
5145
    /* 20 */
5146
    { "pinsrb", { XM, Edb, Ib }, PREFIX_DATA },
5147
    { "insertps", { XM, EXd, Ib }, PREFIX_DATA },
5148
    { "pinsrK", { XM, Edq, Ib }, PREFIX_DATA },
5149
    { Bad_Opcode },
5150
    { Bad_Opcode },
5151
    { Bad_Opcode },
5152
    { Bad_Opcode },
5153
    { Bad_Opcode },
5154
    /* 28 */
5155
    { Bad_Opcode },
5156
    { Bad_Opcode },
5157
    { Bad_Opcode },
5158
    { Bad_Opcode },
5159
    { Bad_Opcode },
5160
    { Bad_Opcode },
5161
    { Bad_Opcode },
5162
    { Bad_Opcode },
5163
    /* 30 */
5164
    { Bad_Opcode },
5165
    { Bad_Opcode },
5166
    { Bad_Opcode },
5167
    { Bad_Opcode },
5168
    { Bad_Opcode },
5169
    { Bad_Opcode },
5170
    { Bad_Opcode },
5171
    { Bad_Opcode },
5172
    /* 38 */
5173
    { Bad_Opcode },
5174
    { Bad_Opcode },
5175
    { Bad_Opcode },
5176
    { Bad_Opcode },
5177
    { Bad_Opcode },
5178
    { Bad_Opcode },
5179
    { Bad_Opcode },
5180
    { Bad_Opcode },
5181
    /* 40 */
5182
    { "dpps", { XM, EXx, Ib }, PREFIX_DATA },
5183
    { "dppd", { XM, EXx, Ib }, PREFIX_DATA },
5184
    { "mpsadbw", { XM, EXx, Ib }, PREFIX_DATA },
5185
    { Bad_Opcode },
5186
    { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_DATA },
5187
    { Bad_Opcode },
5188
    { Bad_Opcode },
5189
    { Bad_Opcode },
5190
    /* 48 */
5191
    { Bad_Opcode },
5192
    { Bad_Opcode },
5193
    { Bad_Opcode },
5194
    { Bad_Opcode },
5195
    { Bad_Opcode },
5196
    { Bad_Opcode },
5197
    { Bad_Opcode },
5198
    { Bad_Opcode },
5199
    /* 50 */
5200
    { Bad_Opcode },
5201
    { Bad_Opcode },
5202
    { Bad_Opcode },
5203
    { Bad_Opcode },
5204
    { Bad_Opcode },
5205
    { Bad_Opcode },
5206
    { Bad_Opcode },
5207
    { Bad_Opcode },
5208
    /* 58 */
5209
    { Bad_Opcode },
5210
    { Bad_Opcode },
5211
    { Bad_Opcode },
5212
    { Bad_Opcode },
5213
    { Bad_Opcode },
5214
    { Bad_Opcode },
5215
    { Bad_Opcode },
5216
    { Bad_Opcode },
5217
    /* 60 */
5218
    { "pcmpestrm!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
5219
    { "pcmpestri!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
5220
    { "pcmpistrm", { XM, EXx, Ib }, PREFIX_DATA },
5221
    { "pcmpistri", { XM, EXx, Ib }, PREFIX_DATA },
5222
    { Bad_Opcode },
5223
    { Bad_Opcode },
5224
    { Bad_Opcode },
5225
    { Bad_Opcode },
5226
    /* 68 */
5227
    { Bad_Opcode },
5228
    { Bad_Opcode },
5229
    { Bad_Opcode },
5230
    { Bad_Opcode },
5231
    { Bad_Opcode },
5232
    { Bad_Opcode },
5233
    { Bad_Opcode },
5234
    { Bad_Opcode },
5235
    /* 70 */
5236
    { Bad_Opcode },
5237
    { Bad_Opcode },
5238
    { Bad_Opcode },
5239
    { Bad_Opcode },
5240
    { Bad_Opcode },
5241
    { Bad_Opcode },
5242
    { Bad_Opcode },
5243
    { Bad_Opcode },
5244
    /* 78 */
5245
    { Bad_Opcode },
5246
    { Bad_Opcode },
5247
    { Bad_Opcode },
5248
    { Bad_Opcode },
5249
    { Bad_Opcode },
5250
    { Bad_Opcode },
5251
    { Bad_Opcode },
5252
    { Bad_Opcode },
5253
    /* 80 */
5254
    { Bad_Opcode },
5255
    { Bad_Opcode },
5256
    { Bad_Opcode },
5257
    { Bad_Opcode },
5258
    { Bad_Opcode },
5259
    { Bad_Opcode },
5260
    { Bad_Opcode },
5261
    { Bad_Opcode },
5262
    /* 88 */
5263
    { Bad_Opcode },
5264
    { Bad_Opcode },
5265
    { Bad_Opcode },
5266
    { Bad_Opcode },
5267
    { Bad_Opcode },
5268
    { Bad_Opcode },
5269
    { Bad_Opcode },
5270
    { Bad_Opcode },
5271
    /* 90 */
5272
    { Bad_Opcode },
5273
    { Bad_Opcode },
5274
    { Bad_Opcode },
5275
    { Bad_Opcode },
5276
    { Bad_Opcode },
5277
    { Bad_Opcode },
5278
    { Bad_Opcode },
5279
    { Bad_Opcode },
5280
    /* 98 */
5281
    { Bad_Opcode },
5282
    { Bad_Opcode },
5283
    { Bad_Opcode },
5284
    { Bad_Opcode },
5285
    { Bad_Opcode },
5286
    { Bad_Opcode },
5287
    { Bad_Opcode },
5288
    { Bad_Opcode },
5289
    /* a0 */
5290
    { Bad_Opcode },
5291
    { Bad_Opcode },
5292
    { Bad_Opcode },
5293
    { Bad_Opcode },
5294
    { Bad_Opcode },
5295
    { Bad_Opcode },
5296
    { Bad_Opcode },
5297
    { Bad_Opcode },
5298
    /* a8 */
5299
    { Bad_Opcode },
5300
    { Bad_Opcode },
5301
    { Bad_Opcode },
5302
    { Bad_Opcode },
5303
    { Bad_Opcode },
5304
    { Bad_Opcode },
5305
    { Bad_Opcode },
5306
    { Bad_Opcode },
5307
    /* b0 */
5308
    { Bad_Opcode },
5309
    { Bad_Opcode },
5310
    { Bad_Opcode },
5311
    { Bad_Opcode },
5312
    { Bad_Opcode },
5313
    { Bad_Opcode },
5314
    { Bad_Opcode },
5315
    { Bad_Opcode },
5316
    /* b8 */
5317
    { Bad_Opcode },
5318
    { Bad_Opcode },
5319
    { Bad_Opcode },
5320
    { Bad_Opcode },
5321
    { Bad_Opcode },
5322
    { Bad_Opcode },
5323
    { Bad_Opcode },
5324
    { Bad_Opcode },
5325
    /* c0 */
5326
    { Bad_Opcode },
5327
    { Bad_Opcode },
5328
    { Bad_Opcode },
5329
    { Bad_Opcode },
5330
    { Bad_Opcode },
5331
    { Bad_Opcode },
5332
    { Bad_Opcode },
5333
    { Bad_Opcode },
5334
    /* c8 */
5335
    { Bad_Opcode },
5336
    { Bad_Opcode },
5337
    { Bad_Opcode },
5338
    { Bad_Opcode },
5339
    { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
5340
    { Bad_Opcode },
5341
    { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_DATA },
5342
    { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_DATA },
5343
    /* d0 */
5344
    { Bad_Opcode },
5345
    { Bad_Opcode },
5346
    { Bad_Opcode },
5347
    { Bad_Opcode },
5348
    { Bad_Opcode },
5349
    { Bad_Opcode },
5350
    { Bad_Opcode },
5351
    { Bad_Opcode },
5352
    /* d8 */
5353
    { Bad_Opcode },
5354
    { Bad_Opcode },
5355
    { Bad_Opcode },
5356
    { Bad_Opcode },
5357
    { Bad_Opcode },
5358
    { Bad_Opcode },
5359
    { Bad_Opcode },
5360
    { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_DATA },
5361
    /* e0 */
5362
    { Bad_Opcode },
5363
    { Bad_Opcode },
5364
    { Bad_Opcode },
5365
    { Bad_Opcode },
5366
    { Bad_Opcode },
5367
    { Bad_Opcode },
5368
    { Bad_Opcode },
5369
    { Bad_Opcode },
5370
    /* e8 */
5371
    { Bad_Opcode },
5372
    { Bad_Opcode },
5373
    { Bad_Opcode },
5374
    { Bad_Opcode },
5375
    { Bad_Opcode },
5376
    { Bad_Opcode },
5377
    { Bad_Opcode },
5378
    { Bad_Opcode },
5379
    /* f0 */
5380
    { PREFIX_TABLE (PREFIX_0F3A0F) },
5381
    { Bad_Opcode },
5382
    { Bad_Opcode },
5383
    { Bad_Opcode },
5384
    { Bad_Opcode },
5385
    { Bad_Opcode },
5386
    { Bad_Opcode },
5387
    { Bad_Opcode },
5388
    /* f8 */
5389
    { Bad_Opcode },
5390
    { Bad_Opcode },
5391
    { Bad_Opcode },
5392
    { Bad_Opcode },
5393
    { Bad_Opcode },
5394
    { Bad_Opcode },
5395
    { Bad_Opcode },
5396
    { Bad_Opcode },
5397
  },
5398
};
5399
5400
static const struct dis386 xop_table[][256] = {
5401
  /* XOP_08 */
5402
  {
5403
    /* 00 */
5404
    { Bad_Opcode },
5405
    { Bad_Opcode },
5406
    { Bad_Opcode },
5407
    { Bad_Opcode },
5408
    { Bad_Opcode },
5409
    { Bad_Opcode },
5410
    { Bad_Opcode },
5411
    { Bad_Opcode },
5412
    /* 08 */
5413
    { Bad_Opcode },
5414
    { Bad_Opcode },
5415
    { Bad_Opcode },
5416
    { Bad_Opcode },
5417
    { Bad_Opcode },
5418
    { Bad_Opcode },
5419
    { Bad_Opcode },
5420
    { Bad_Opcode },
5421
    /* 10 */
5422
    { Bad_Opcode },
5423
    { Bad_Opcode },
5424
    { Bad_Opcode },
5425
    { Bad_Opcode },
5426
    { Bad_Opcode },
5427
    { Bad_Opcode },
5428
    { Bad_Opcode },
5429
    { Bad_Opcode },
5430
    /* 18 */
5431
    { Bad_Opcode },
5432
    { Bad_Opcode },
5433
    { Bad_Opcode },
5434
    { Bad_Opcode },
5435
    { Bad_Opcode },
5436
    { Bad_Opcode },
5437
    { Bad_Opcode },
5438
    { Bad_Opcode },
5439
    /* 20 */
5440
    { Bad_Opcode },
5441
    { Bad_Opcode },
5442
    { Bad_Opcode },
5443
    { Bad_Opcode },
5444
    { Bad_Opcode },
5445
    { Bad_Opcode },
5446
    { Bad_Opcode },
5447
    { Bad_Opcode },
5448
    /* 28 */
5449
    { Bad_Opcode },
5450
    { Bad_Opcode },
5451
    { Bad_Opcode },
5452
    { Bad_Opcode },
5453
    { Bad_Opcode },
5454
    { Bad_Opcode },
5455
    { Bad_Opcode },
5456
    { Bad_Opcode },
5457
    /* 30 */
5458
    { Bad_Opcode },
5459
    { Bad_Opcode },
5460
    { Bad_Opcode },
5461
    { Bad_Opcode },
5462
    { Bad_Opcode },
5463
    { Bad_Opcode },
5464
    { Bad_Opcode },
5465
    { Bad_Opcode },
5466
    /* 38 */
5467
    { Bad_Opcode },
5468
    { Bad_Opcode },
5469
    { Bad_Opcode },
5470
    { Bad_Opcode },
5471
    { Bad_Opcode },
5472
    { Bad_Opcode },
5473
    { Bad_Opcode },
5474
    { Bad_Opcode },
5475
    /* 40 */
5476
    { Bad_Opcode },
5477
    { Bad_Opcode },
5478
    { Bad_Opcode },
5479
    { Bad_Opcode },
5480
    { Bad_Opcode },
5481
    { Bad_Opcode },
5482
    { Bad_Opcode },
5483
    { Bad_Opcode },
5484
    /* 48 */
5485
    { Bad_Opcode },
5486
    { Bad_Opcode },
5487
    { Bad_Opcode },
5488
    { Bad_Opcode },
5489
    { Bad_Opcode },
5490
    { Bad_Opcode },
5491
    { Bad_Opcode },
5492
    { Bad_Opcode },
5493
    /* 50 */
5494
    { Bad_Opcode },
5495
    { Bad_Opcode },
5496
    { Bad_Opcode },
5497
    { Bad_Opcode },
5498
    { Bad_Opcode },
5499
    { Bad_Opcode },
5500
    { Bad_Opcode },
5501
    { Bad_Opcode },
5502
    /* 58 */
5503
    { Bad_Opcode },
5504
    { Bad_Opcode },
5505
    { Bad_Opcode },
5506
    { Bad_Opcode },
5507
    { Bad_Opcode },
5508
    { Bad_Opcode },
5509
    { Bad_Opcode },
5510
    { Bad_Opcode },
5511
    /* 60 */
5512
    { Bad_Opcode },
5513
    { Bad_Opcode },
5514
    { Bad_Opcode },
5515
    { Bad_Opcode },
5516
    { Bad_Opcode },
5517
    { Bad_Opcode },
5518
    { Bad_Opcode },
5519
    { Bad_Opcode },
5520
    /* 68 */
5521
    { Bad_Opcode },
5522
    { Bad_Opcode },
5523
    { Bad_Opcode },
5524
    { Bad_Opcode },
5525
    { Bad_Opcode },
5526
    { Bad_Opcode },
5527
    { Bad_Opcode },
5528
    { Bad_Opcode },
5529
    /* 70 */
5530
    { Bad_Opcode },
5531
    { Bad_Opcode },
5532
    { Bad_Opcode },
5533
    { Bad_Opcode },
5534
    { Bad_Opcode },
5535
    { Bad_Opcode },
5536
    { Bad_Opcode },
5537
    { Bad_Opcode },
5538
    /* 78 */
5539
    { Bad_Opcode },
5540
    { Bad_Opcode },
5541
    { Bad_Opcode },
5542
    { Bad_Opcode },
5543
    { Bad_Opcode },
5544
    { Bad_Opcode },
5545
    { Bad_Opcode },
5546
    { Bad_Opcode },
5547
    /* 80 */
5548
    { Bad_Opcode },
5549
    { Bad_Opcode },
5550
    { Bad_Opcode },
5551
    { Bad_Opcode },
5552
    { Bad_Opcode },
5553
    { VEX_LEN_TABLE (VEX_LEN_XOP_08_85) },
5554
    { VEX_LEN_TABLE (VEX_LEN_XOP_08_86) },
5555
    { VEX_LEN_TABLE (VEX_LEN_XOP_08_87) },
5556
    /* 88 */
5557
    { Bad_Opcode },
5558
    { Bad_Opcode },
5559
    { Bad_Opcode },
5560
    { Bad_Opcode },
5561
    { Bad_Opcode },
5562
    { Bad_Opcode },
5563
    { VEX_LEN_TABLE (VEX_LEN_XOP_08_8E) },
5564
    { VEX_LEN_TABLE (VEX_LEN_XOP_08_8F) },
5565
    /* 90 */
5566
    { Bad_Opcode },
5567
    { Bad_Opcode },
5568
    { Bad_Opcode },
5569
    { Bad_Opcode },
5570
    { Bad_Opcode },
5571
    { VEX_LEN_TABLE (VEX_LEN_XOP_08_95) },
5572
    { VEX_LEN_TABLE (VEX_LEN_XOP_08_96) },
5573
    { VEX_LEN_TABLE (VEX_LEN_XOP_08_97) },
5574
    /* 98 */
5575
    { Bad_Opcode },
5576
    { Bad_Opcode },
5577
    { Bad_Opcode },
5578
    { Bad_Opcode },
5579
    { Bad_Opcode },
5580
    { Bad_Opcode },
5581
    { VEX_LEN_TABLE (VEX_LEN_XOP_08_9E) },
5582
    { VEX_LEN_TABLE (VEX_LEN_XOP_08_9F) },
5583
    /* a0 */
5584
    { Bad_Opcode },
5585
    { Bad_Opcode },
5586
    { "vpcmov",   { XM, Vex, EXx, XMVexI4 }, 0 },
5587
    { VEX_LEN_TABLE (VEX_LEN_XOP_08_A3) },
5588
    { Bad_Opcode },
5589
    { Bad_Opcode },
5590
    { VEX_LEN_TABLE (VEX_LEN_XOP_08_A6) },
5591
    { Bad_Opcode },
5592
    /* a8 */
5593
    { Bad_Opcode },
5594
    { Bad_Opcode },
5595
    { Bad_Opcode },
5596
    { Bad_Opcode },
5597
    { Bad_Opcode },
5598
    { Bad_Opcode },
5599
    { Bad_Opcode },
5600
    { Bad_Opcode },
5601
    /* b0 */
5602
    { Bad_Opcode },
5603
    { Bad_Opcode },
5604
    { Bad_Opcode },
5605
    { Bad_Opcode },
5606
    { Bad_Opcode },
5607
    { Bad_Opcode },
5608
    { VEX_LEN_TABLE (VEX_LEN_XOP_08_B6) },
5609
    { Bad_Opcode },
5610
    /* b8 */
5611
    { Bad_Opcode },
5612
    { Bad_Opcode },
5613
    { Bad_Opcode },
5614
    { Bad_Opcode },
5615
    { Bad_Opcode },
5616
    { Bad_Opcode },
5617
    { Bad_Opcode },
5618
    { Bad_Opcode },
5619
    /* c0 */
5620
    { VEX_LEN_TABLE (VEX_LEN_XOP_08_C0) },
5621
    { VEX_LEN_TABLE (VEX_LEN_XOP_08_C1) },
5622
    { VEX_LEN_TABLE (VEX_LEN_XOP_08_C2) },
5623
    { VEX_LEN_TABLE (VEX_LEN_XOP_08_C3) },
5624
    { Bad_Opcode },
5625
    { Bad_Opcode },
5626
    { Bad_Opcode },
5627
    { Bad_Opcode },
5628
    /* c8 */
5629
    { Bad_Opcode },
5630
    { Bad_Opcode },
5631
    { Bad_Opcode },
5632
    { Bad_Opcode },
5633
    { VEX_LEN_TABLE (VEX_LEN_XOP_08_CC) },
5634
    { VEX_LEN_TABLE (VEX_LEN_XOP_08_CD) },
5635
    { VEX_LEN_TABLE (VEX_LEN_XOP_08_CE) },
5636
    { VEX_LEN_TABLE (VEX_LEN_XOP_08_CF) },
5637
    /* d0 */
5638
    { Bad_Opcode },
5639
    { Bad_Opcode },
5640
    { Bad_Opcode },
5641
    { Bad_Opcode },
5642
    { Bad_Opcode },
5643
    { Bad_Opcode },
5644
    { Bad_Opcode },
5645
    { Bad_Opcode },
5646
    /* d8 */
5647
    { Bad_Opcode },
5648
    { Bad_Opcode },
5649
    { Bad_Opcode },
5650
    { Bad_Opcode },
5651
    { Bad_Opcode },
5652
    { Bad_Opcode },
5653
    { Bad_Opcode },
5654
    { Bad_Opcode },
5655
    /* e0 */
5656
    { Bad_Opcode },
5657
    { Bad_Opcode },
5658
    { Bad_Opcode },
5659
    { Bad_Opcode },
5660
    { Bad_Opcode },
5661
    { Bad_Opcode },
5662
    { Bad_Opcode },
5663
    { Bad_Opcode },
5664
    /* e8 */
5665
    { Bad_Opcode },
5666
    { Bad_Opcode },
5667
    { Bad_Opcode },
5668
    { Bad_Opcode },
5669
    { VEX_LEN_TABLE (VEX_LEN_XOP_08_EC) },
5670
    { VEX_LEN_TABLE (VEX_LEN_XOP_08_ED) },
5671
    { VEX_LEN_TABLE (VEX_LEN_XOP_08_EE) },
5672
    { VEX_LEN_TABLE (VEX_LEN_XOP_08_EF) },
5673
    /* f0 */
5674
    { Bad_Opcode },
5675
    { Bad_Opcode },
5676
    { Bad_Opcode },
5677
    { Bad_Opcode },
5678
    { Bad_Opcode },
5679
    { Bad_Opcode },
5680
    { Bad_Opcode },
5681
    { Bad_Opcode },
5682
    /* f8 */
5683
    { Bad_Opcode },
5684
    { Bad_Opcode },
5685
    { Bad_Opcode },
5686
    { Bad_Opcode },
5687
    { Bad_Opcode },
5688
    { Bad_Opcode },
5689
    { Bad_Opcode },
5690
    { Bad_Opcode },
5691
  },
5692
  /* XOP_09 */
5693
  {
5694
    /* 00 */
5695
    { Bad_Opcode },
5696
    { VEX_LEN_TABLE (VEX_LEN_XOP_09_01) },
5697
    { VEX_LEN_TABLE (VEX_LEN_XOP_09_02) },
5698
    { Bad_Opcode },
5699
    { Bad_Opcode },
5700
    { Bad_Opcode },
5701
    { Bad_Opcode },
5702
    { Bad_Opcode },
5703
    /* 08 */
5704
    { Bad_Opcode },
5705
    { Bad_Opcode },
5706
    { Bad_Opcode },
5707
    { Bad_Opcode },
5708
    { Bad_Opcode },
5709
    { Bad_Opcode },
5710
    { Bad_Opcode },
5711
    { Bad_Opcode },
5712
    /* 10 */
5713
    { Bad_Opcode },
5714
    { Bad_Opcode },
5715
    { VEX_LEN_TABLE (VEX_LEN_XOP_09_12) },
5716
    { Bad_Opcode },
5717
    { Bad_Opcode },
5718
    { Bad_Opcode },
5719
    { Bad_Opcode },
5720
    { Bad_Opcode },
5721
    /* 18 */
5722
    { Bad_Opcode },
5723
    { Bad_Opcode },
5724
    { Bad_Opcode },
5725
    { Bad_Opcode },
5726
    { Bad_Opcode },
5727
    { Bad_Opcode },
5728
    { Bad_Opcode },
5729
    { Bad_Opcode },
5730
    /* 20 */
5731
    { Bad_Opcode },
5732
    { Bad_Opcode },
5733
    { Bad_Opcode },
5734
    { Bad_Opcode },
5735
    { Bad_Opcode },
5736
    { Bad_Opcode },
5737
    { Bad_Opcode },
5738
    { Bad_Opcode },
5739
    /* 28 */
5740
    { Bad_Opcode },
5741
    { Bad_Opcode },
5742
    { Bad_Opcode },
5743
    { Bad_Opcode },
5744
    { Bad_Opcode },
5745
    { Bad_Opcode },
5746
    { Bad_Opcode },
5747
    { Bad_Opcode },
5748
    /* 30 */
5749
    { Bad_Opcode },
5750
    { Bad_Opcode },
5751
    { Bad_Opcode },
5752
    { Bad_Opcode },
5753
    { Bad_Opcode },
5754
    { Bad_Opcode },
5755
    { Bad_Opcode },
5756
    { Bad_Opcode },
5757
    /* 38 */
5758
    { Bad_Opcode },
5759
    { Bad_Opcode },
5760
    { Bad_Opcode },
5761
    { Bad_Opcode },
5762
    { Bad_Opcode },
5763
    { Bad_Opcode },
5764
    { Bad_Opcode },
5765
    { Bad_Opcode },
5766
    /* 40 */
5767
    { Bad_Opcode },
5768
    { Bad_Opcode },
5769
    { Bad_Opcode },
5770
    { Bad_Opcode },
5771
    { Bad_Opcode },
5772
    { Bad_Opcode },
5773
    { Bad_Opcode },
5774
    { Bad_Opcode },
5775
    /* 48 */
5776
    { Bad_Opcode },
5777
    { Bad_Opcode },
5778
    { Bad_Opcode },
5779
    { Bad_Opcode },
5780
    { Bad_Opcode },
5781
    { Bad_Opcode },
5782
    { Bad_Opcode },
5783
    { Bad_Opcode },
5784
    /* 50 */
5785
    { Bad_Opcode },
5786
    { Bad_Opcode },
5787
    { Bad_Opcode },
5788
    { Bad_Opcode },
5789
    { Bad_Opcode },
5790
    { Bad_Opcode },
5791
    { Bad_Opcode },
5792
    { Bad_Opcode },
5793
    /* 58 */
5794
    { Bad_Opcode },
5795
    { Bad_Opcode },
5796
    { Bad_Opcode },
5797
    { Bad_Opcode },
5798
    { Bad_Opcode },
5799
    { Bad_Opcode },
5800
    { Bad_Opcode },
5801
    { Bad_Opcode },
5802
    /* 60 */
5803
    { Bad_Opcode },
5804
    { Bad_Opcode },
5805
    { Bad_Opcode },
5806
    { Bad_Opcode },
5807
    { Bad_Opcode },
5808
    { Bad_Opcode },
5809
    { Bad_Opcode },
5810
    { Bad_Opcode },
5811
    /* 68 */
5812
    { Bad_Opcode },
5813
    { Bad_Opcode },
5814
    { Bad_Opcode },
5815
    { Bad_Opcode },
5816
    { Bad_Opcode },
5817
    { Bad_Opcode },
5818
    { Bad_Opcode },
5819
    { Bad_Opcode },
5820
    /* 70 */
5821
    { Bad_Opcode },
5822
    { Bad_Opcode },
5823
    { Bad_Opcode },
5824
    { Bad_Opcode },
5825
    { Bad_Opcode },
5826
    { Bad_Opcode },
5827
    { Bad_Opcode },
5828
    { Bad_Opcode },
5829
    /* 78 */
5830
    { Bad_Opcode },
5831
    { Bad_Opcode },
5832
    { Bad_Opcode },
5833
    { Bad_Opcode },
5834
    { Bad_Opcode },
5835
    { Bad_Opcode },
5836
    { Bad_Opcode },
5837
    { Bad_Opcode },
5838
    /* 80 */
5839
    { VEX_W_TABLE (VEX_W_XOP_09_80) },
5840
    { VEX_W_TABLE (VEX_W_XOP_09_81) },
5841
    { VEX_W_TABLE (VEX_W_XOP_09_82) },
5842
    { VEX_W_TABLE (VEX_W_XOP_09_83) },
5843
    { Bad_Opcode },
5844
    { Bad_Opcode },
5845
    { Bad_Opcode },
5846
    { Bad_Opcode },
5847
    /* 88 */
5848
    { Bad_Opcode },
5849
    { Bad_Opcode },
5850
    { Bad_Opcode },
5851
    { Bad_Opcode },
5852
    { Bad_Opcode },
5853
    { Bad_Opcode },
5854
    { Bad_Opcode },
5855
    { Bad_Opcode },
5856
    /* 90 */
5857
    { VEX_LEN_TABLE (VEX_LEN_XOP_09_90) },
5858
    { VEX_LEN_TABLE (VEX_LEN_XOP_09_91) },
5859
    { VEX_LEN_TABLE (VEX_LEN_XOP_09_92) },
5860
    { VEX_LEN_TABLE (VEX_LEN_XOP_09_93) },
5861
    { VEX_LEN_TABLE (VEX_LEN_XOP_09_94) },
5862
    { VEX_LEN_TABLE (VEX_LEN_XOP_09_95) },
5863
    { VEX_LEN_TABLE (VEX_LEN_XOP_09_96) },
5864
    { VEX_LEN_TABLE (VEX_LEN_XOP_09_97) },
5865
    /* 98 */
5866
    { VEX_LEN_TABLE (VEX_LEN_XOP_09_98) },
5867
    { VEX_LEN_TABLE (VEX_LEN_XOP_09_99) },
5868
    { VEX_LEN_TABLE (VEX_LEN_XOP_09_9A) },
5869
    { VEX_LEN_TABLE (VEX_LEN_XOP_09_9B) },
5870
    { Bad_Opcode },
5871
    { Bad_Opcode },
5872
    { Bad_Opcode },
5873
    { Bad_Opcode },
5874
    /* a0 */
5875
    { Bad_Opcode },
5876
    { Bad_Opcode },
5877
    { Bad_Opcode },
5878
    { Bad_Opcode },
5879
    { Bad_Opcode },
5880
    { Bad_Opcode },
5881
    { Bad_Opcode },
5882
    { Bad_Opcode },
5883
    /* a8 */
5884
    { Bad_Opcode },
5885
    { Bad_Opcode },
5886
    { Bad_Opcode },
5887
    { Bad_Opcode },
5888
    { Bad_Opcode },
5889
    { Bad_Opcode },
5890
    { Bad_Opcode },
5891
    { Bad_Opcode },
5892
    /* b0 */
5893
    { Bad_Opcode },
5894
    { Bad_Opcode },
5895
    { Bad_Opcode },
5896
    { Bad_Opcode },
5897
    { Bad_Opcode },
5898
    { Bad_Opcode },
5899
    { Bad_Opcode },
5900
    { Bad_Opcode },
5901
    /* b8 */
5902
    { Bad_Opcode },
5903
    { Bad_Opcode },
5904
    { Bad_Opcode },
5905
    { Bad_Opcode },
5906
    { Bad_Opcode },
5907
    { Bad_Opcode },
5908
    { Bad_Opcode },
5909
    { Bad_Opcode },
5910
    /* c0 */
5911
    { Bad_Opcode },
5912
    { VEX_LEN_TABLE (VEX_LEN_XOP_09_C1) },
5913
    { VEX_LEN_TABLE (VEX_LEN_XOP_09_C2) },
5914
    { VEX_LEN_TABLE (VEX_LEN_XOP_09_C3) },
5915
    { Bad_Opcode },
5916
    { Bad_Opcode },
5917
    { VEX_LEN_TABLE (VEX_LEN_XOP_09_C6) },
5918
    { VEX_LEN_TABLE (VEX_LEN_XOP_09_C7) },
5919
    /* c8 */
5920
    { Bad_Opcode },
5921
    { Bad_Opcode },
5922
    { Bad_Opcode },
5923
    { VEX_LEN_TABLE (VEX_LEN_XOP_09_CB) },
5924
    { Bad_Opcode },
5925
    { Bad_Opcode },
5926
    { Bad_Opcode },
5927
    { Bad_Opcode },
5928
    /* d0 */
5929
    { Bad_Opcode },
5930
    { VEX_LEN_TABLE (VEX_LEN_XOP_09_D1) },
5931
    { VEX_LEN_TABLE (VEX_LEN_XOP_09_D2) },
5932
    { VEX_LEN_TABLE (VEX_LEN_XOP_09_D3) },
5933
    { Bad_Opcode },
5934
    { Bad_Opcode },
5935
    { VEX_LEN_TABLE (VEX_LEN_XOP_09_D6) },
5936
    { VEX_LEN_TABLE (VEX_LEN_XOP_09_D7) },
5937
    /* d8 */
5938
    { Bad_Opcode },
5939
    { Bad_Opcode },
5940
    { Bad_Opcode },
5941
    { VEX_LEN_TABLE (VEX_LEN_XOP_09_DB) },
5942
    { Bad_Opcode },
5943
    { Bad_Opcode },
5944
    { Bad_Opcode },
5945
    { Bad_Opcode },
5946
    /* e0 */
5947
    { Bad_Opcode },
5948
    { VEX_LEN_TABLE (VEX_LEN_XOP_09_E1) },
5949
    { VEX_LEN_TABLE (VEX_LEN_XOP_09_E2) },
5950
    { VEX_LEN_TABLE (VEX_LEN_XOP_09_E3) },
5951
    { Bad_Opcode },
5952
    { Bad_Opcode },
5953
    { Bad_Opcode },
5954
    { Bad_Opcode },
5955
    /* e8 */
5956
    { Bad_Opcode },
5957
    { Bad_Opcode },
5958
    { Bad_Opcode },
5959
    { Bad_Opcode },
5960
    { Bad_Opcode },
5961
    { Bad_Opcode },
5962
    { Bad_Opcode },
5963
    { Bad_Opcode },
5964
    /* f0 */
5965
    { Bad_Opcode },
5966
    { Bad_Opcode },
5967
    { Bad_Opcode },
5968
    { Bad_Opcode },
5969
    { Bad_Opcode },
5970
    { Bad_Opcode },
5971
    { Bad_Opcode },
5972
    { Bad_Opcode },
5973
    /* f8 */
5974
    { Bad_Opcode },
5975
    { Bad_Opcode },
5976
    { Bad_Opcode },
5977
    { Bad_Opcode },
5978
    { Bad_Opcode },
5979
    { Bad_Opcode },
5980
    { Bad_Opcode },
5981
    { Bad_Opcode },
5982
  },
5983
  /* XOP_0A */
5984
  {
5985
    /* 00 */
5986
    { Bad_Opcode },
5987
    { Bad_Opcode },
5988
    { Bad_Opcode },
5989
    { Bad_Opcode },
5990
    { Bad_Opcode },
5991
    { Bad_Opcode },
5992
    { Bad_Opcode },
5993
    { Bad_Opcode },
5994
    /* 08 */
5995
    { Bad_Opcode },
5996
    { Bad_Opcode },
5997
    { Bad_Opcode },
5998
    { Bad_Opcode },
5999
    { Bad_Opcode },
6000
    { Bad_Opcode },
6001
    { Bad_Opcode },
6002
    { Bad_Opcode },
6003
    /* 10 */
6004
    { "bextrS", { Gdq, Edq, Id }, 0 },
6005
    { Bad_Opcode },
6006
    { VEX_LEN_TABLE (VEX_LEN_XOP_0A_12) },
6007
    { Bad_Opcode },
6008
    { Bad_Opcode },
6009
    { Bad_Opcode },
6010
    { Bad_Opcode },
6011
    { Bad_Opcode },
6012
    /* 18 */
6013
    { Bad_Opcode },
6014
    { Bad_Opcode },
6015
    { Bad_Opcode },
6016
    { Bad_Opcode },
6017
    { Bad_Opcode },
6018
    { Bad_Opcode },
6019
    { Bad_Opcode },
6020
    { Bad_Opcode },
6021
    /* 20 */
6022
    { Bad_Opcode },
6023
    { Bad_Opcode },
6024
    { Bad_Opcode },
6025
    { Bad_Opcode },
6026
    { Bad_Opcode },
6027
    { Bad_Opcode },
6028
    { Bad_Opcode },
6029
    { Bad_Opcode },
6030
    /* 28 */
6031
    { Bad_Opcode },
6032
    { Bad_Opcode },
6033
    { Bad_Opcode },
6034
    { Bad_Opcode },
6035
    { Bad_Opcode },
6036
    { Bad_Opcode },
6037
    { Bad_Opcode },
6038
    { Bad_Opcode },
6039
    /* 30 */
6040
    { Bad_Opcode },
6041
    { Bad_Opcode },
6042
    { Bad_Opcode },
6043
    { Bad_Opcode },
6044
    { Bad_Opcode },
6045
    { Bad_Opcode },
6046
    { Bad_Opcode },
6047
    { Bad_Opcode },
6048
    /* 38 */
6049
    { Bad_Opcode },
6050
    { Bad_Opcode },
6051
    { Bad_Opcode },
6052
    { Bad_Opcode },
6053
    { Bad_Opcode },
6054
    { Bad_Opcode },
6055
    { Bad_Opcode },
6056
    { Bad_Opcode },
6057
    /* 40 */
6058
    { Bad_Opcode },
6059
    { Bad_Opcode },
6060
    { Bad_Opcode },
6061
    { Bad_Opcode },
6062
    { Bad_Opcode },
6063
    { Bad_Opcode },
6064
    { Bad_Opcode },
6065
    { Bad_Opcode },
6066
    /* 48 */
6067
    { Bad_Opcode },
6068
    { Bad_Opcode },
6069
    { Bad_Opcode },
6070
    { Bad_Opcode },
6071
    { Bad_Opcode },
6072
    { Bad_Opcode },
6073
    { Bad_Opcode },
6074
    { Bad_Opcode },
6075
    /* 50 */
6076
    { Bad_Opcode },
6077
    { Bad_Opcode },
6078
    { Bad_Opcode },
6079
    { Bad_Opcode },
6080
    { Bad_Opcode },
6081
    { Bad_Opcode },
6082
    { Bad_Opcode },
6083
    { Bad_Opcode },
6084
    /* 58 */
6085
    { Bad_Opcode },
6086
    { Bad_Opcode },
6087
    { Bad_Opcode },
6088
    { Bad_Opcode },
6089
    { Bad_Opcode },
6090
    { Bad_Opcode },
6091
    { Bad_Opcode },
6092
    { Bad_Opcode },
6093
    /* 60 */
6094
    { Bad_Opcode },
6095
    { Bad_Opcode },
6096
    { Bad_Opcode },
6097
    { Bad_Opcode },
6098
    { Bad_Opcode },
6099
    { Bad_Opcode },
6100
    { Bad_Opcode },
6101
    { Bad_Opcode },
6102
    /* 68 */
6103
    { Bad_Opcode },
6104
    { Bad_Opcode },
6105
    { Bad_Opcode },
6106
    { Bad_Opcode },
6107
    { Bad_Opcode },
6108
    { Bad_Opcode },
6109
    { Bad_Opcode },
6110
    { Bad_Opcode },
6111
    /* 70 */
6112
    { Bad_Opcode },
6113
    { Bad_Opcode },
6114
    { Bad_Opcode },
6115
    { Bad_Opcode },
6116
    { Bad_Opcode },
6117
    { Bad_Opcode },
6118
    { Bad_Opcode },
6119
    { Bad_Opcode },
6120
    /* 78 */
6121
    { Bad_Opcode },
6122
    { Bad_Opcode },
6123
    { Bad_Opcode },
6124
    { Bad_Opcode },
6125
    { Bad_Opcode },
6126
    { Bad_Opcode },
6127
    { Bad_Opcode },
6128
    { Bad_Opcode },
6129
    /* 80 */
6130
    { Bad_Opcode },
6131
    { Bad_Opcode },
6132
    { Bad_Opcode },
6133
    { Bad_Opcode },
6134
    { Bad_Opcode },
6135
    { Bad_Opcode },
6136
    { Bad_Opcode },
6137
    { Bad_Opcode },
6138
    /* 88 */
6139
    { Bad_Opcode },
6140
    { Bad_Opcode },
6141
    { Bad_Opcode },
6142
    { Bad_Opcode },
6143
    { Bad_Opcode },
6144
    { Bad_Opcode },
6145
    { Bad_Opcode },
6146
    { Bad_Opcode },
6147
    /* 90 */
6148
    { Bad_Opcode },
6149
    { Bad_Opcode },
6150
    { Bad_Opcode },
6151
    { Bad_Opcode },
6152
    { Bad_Opcode },
6153
    { Bad_Opcode },
6154
    { Bad_Opcode },
6155
    { Bad_Opcode },
6156
    /* 98 */
6157
    { Bad_Opcode },
6158
    { Bad_Opcode },
6159
    { Bad_Opcode },
6160
    { Bad_Opcode },
6161
    { Bad_Opcode },
6162
    { Bad_Opcode },
6163
    { Bad_Opcode },
6164
    { Bad_Opcode },
6165
    /* a0 */
6166
    { Bad_Opcode },
6167
    { Bad_Opcode },
6168
    { Bad_Opcode },
6169
    { Bad_Opcode },
6170
    { Bad_Opcode },
6171
    { Bad_Opcode },
6172
    { Bad_Opcode },
6173
    { Bad_Opcode },
6174
    /* a8 */
6175
    { Bad_Opcode },
6176
    { Bad_Opcode },
6177
    { Bad_Opcode },
6178
    { Bad_Opcode },
6179
    { Bad_Opcode },
6180
    { Bad_Opcode },
6181
    { Bad_Opcode },
6182
    { Bad_Opcode },
6183
    /* b0 */
6184
    { Bad_Opcode },
6185
    { Bad_Opcode },
6186
    { Bad_Opcode },
6187
    { Bad_Opcode },
6188
    { Bad_Opcode },
6189
    { Bad_Opcode },
6190
    { Bad_Opcode },
6191
    { Bad_Opcode },
6192
    /* b8 */
6193
    { Bad_Opcode },
6194
    { Bad_Opcode },
6195
    { Bad_Opcode },
6196
    { Bad_Opcode },
6197
    { Bad_Opcode },
6198
    { Bad_Opcode },
6199
    { Bad_Opcode },
6200
    { Bad_Opcode },
6201
    /* c0 */
6202
    { Bad_Opcode },
6203
    { Bad_Opcode },
6204
    { Bad_Opcode },
6205
    { Bad_Opcode },
6206
    { Bad_Opcode },
6207
    { Bad_Opcode },
6208
    { Bad_Opcode },
6209
    { Bad_Opcode },
6210
    /* c8 */
6211
    { Bad_Opcode },
6212
    { Bad_Opcode },
6213
    { Bad_Opcode },
6214
    { Bad_Opcode },
6215
    { Bad_Opcode },
6216
    { Bad_Opcode },
6217
    { Bad_Opcode },
6218
    { Bad_Opcode },
6219
    /* d0 */
6220
    { Bad_Opcode },
6221
    { Bad_Opcode },
6222
    { Bad_Opcode },
6223
    { Bad_Opcode },
6224
    { Bad_Opcode },
6225
    { Bad_Opcode },
6226
    { Bad_Opcode },
6227
    { Bad_Opcode },
6228
    /* d8 */
6229
    { Bad_Opcode },
6230
    { Bad_Opcode },
6231
    { Bad_Opcode },
6232
    { Bad_Opcode },
6233
    { Bad_Opcode },
6234
    { Bad_Opcode },
6235
    { Bad_Opcode },
6236
    { Bad_Opcode },
6237
    /* e0 */
6238
    { Bad_Opcode },
6239
    { Bad_Opcode },
6240
    { Bad_Opcode },
6241
    { Bad_Opcode },
6242
    { Bad_Opcode },
6243
    { Bad_Opcode },
6244
    { Bad_Opcode },
6245
    { Bad_Opcode },
6246
    /* e8 */
6247
    { Bad_Opcode },
6248
    { Bad_Opcode },
6249
    { Bad_Opcode },
6250
    { Bad_Opcode },
6251
    { Bad_Opcode },
6252
    { Bad_Opcode },
6253
    { Bad_Opcode },
6254
    { Bad_Opcode },
6255
    /* f0 */
6256
    { Bad_Opcode },
6257
    { Bad_Opcode },
6258
    { Bad_Opcode },
6259
    { Bad_Opcode },
6260
    { Bad_Opcode },
6261
    { Bad_Opcode },
6262
    { Bad_Opcode },
6263
    { Bad_Opcode },
6264
    /* f8 */
6265
    { Bad_Opcode },
6266
    { Bad_Opcode },
6267
    { Bad_Opcode },
6268
    { Bad_Opcode },
6269
    { Bad_Opcode },
6270
    { Bad_Opcode },
6271
    { Bad_Opcode },
6272
    { Bad_Opcode },
6273
  },
6274
};
6275
6276
static const struct dis386 vex_table[][256] = {
6277
  /* VEX_0F */
6278
  {
6279
    /* 00 */
6280
    { Bad_Opcode },
6281
    { Bad_Opcode },
6282
    { Bad_Opcode },
6283
    { Bad_Opcode },
6284
    { Bad_Opcode },
6285
    { Bad_Opcode },
6286
    { Bad_Opcode },
6287
    { Bad_Opcode },
6288
    /* 08 */
6289
    { Bad_Opcode },
6290
    { Bad_Opcode },
6291
    { Bad_Opcode },
6292
    { Bad_Opcode },
6293
    { Bad_Opcode },
6294
    { Bad_Opcode },
6295
    { Bad_Opcode },
6296
    { Bad_Opcode },
6297
    /* 10 */
6298
    { PREFIX_TABLE (PREFIX_0F10) },
6299
    { PREFIX_TABLE (PREFIX_0F11) },
6300
    { PREFIX_TABLE (PREFIX_VEX_0F12) },
6301
    { VEX_LEN_TABLE (VEX_LEN_0F13) },
6302
    { "vunpcklpX",  { XM, Vex, EXx }, PREFIX_OPCODE },
6303
    { "vunpckhpX",  { XM, Vex, EXx }, PREFIX_OPCODE },
6304
    { PREFIX_TABLE (PREFIX_VEX_0F16) },
6305
    { VEX_LEN_TABLE (VEX_LEN_0F17) },
6306
    /* 18 */
6307
    { Bad_Opcode },
6308
    { Bad_Opcode },
6309
    { Bad_Opcode },
6310
    { Bad_Opcode },
6311
    { Bad_Opcode },
6312
    { Bad_Opcode },
6313
    { Bad_Opcode },
6314
    { Bad_Opcode },
6315
    /* 20 */
6316
    { Bad_Opcode },
6317
    { Bad_Opcode },
6318
    { Bad_Opcode },
6319
    { Bad_Opcode },
6320
    { Bad_Opcode },
6321
    { Bad_Opcode },
6322
    { Bad_Opcode },
6323
    { Bad_Opcode },
6324
    /* 28 */
6325
    { "vmovapX",  { XM, EXx }, PREFIX_OPCODE },
6326
    { "vmovapX",  { EXxS, XM }, PREFIX_OPCODE },
6327
    { PREFIX_TABLE (PREFIX_VEX_0F2A) },
6328
    { "vmovntpX", { Mx, XM }, PREFIX_OPCODE },
6329
    { PREFIX_TABLE (PREFIX_VEX_0F2C) },
6330
    { PREFIX_TABLE (PREFIX_VEX_0F2D) },
6331
    { PREFIX_TABLE (PREFIX_0F2E) },
6332
    { PREFIX_TABLE (PREFIX_0F2F) },
6333
    /* 30 */
6334
    { Bad_Opcode },
6335
    { Bad_Opcode },
6336
    { Bad_Opcode },
6337
    { Bad_Opcode },
6338
    { Bad_Opcode },
6339
    { Bad_Opcode },
6340
    { Bad_Opcode },
6341
    { Bad_Opcode },
6342
    /* 38 */
6343
    { Bad_Opcode },
6344
    { Bad_Opcode },
6345
    { Bad_Opcode },
6346
    { Bad_Opcode },
6347
    { Bad_Opcode },
6348
    { Bad_Opcode },
6349
    { Bad_Opcode },
6350
    { Bad_Opcode },
6351
    /* 40 */
6352
    { Bad_Opcode },
6353
    { VEX_LEN_TABLE (VEX_LEN_0F41) },
6354
    { VEX_LEN_TABLE (VEX_LEN_0F42) },
6355
    { Bad_Opcode },
6356
    { VEX_LEN_TABLE (VEX_LEN_0F44) },
6357
    { VEX_LEN_TABLE (VEX_LEN_0F45) },
6358
    { VEX_LEN_TABLE (VEX_LEN_0F46) },
6359
    { VEX_LEN_TABLE (VEX_LEN_0F47) },
6360
    /* 48 */
6361
    { Bad_Opcode },
6362
    { Bad_Opcode },
6363
    { VEX_LEN_TABLE (VEX_LEN_0F4A) },
6364
    { VEX_LEN_TABLE (VEX_LEN_0F4B) },
6365
    { Bad_Opcode },
6366
    { Bad_Opcode },
6367
    { Bad_Opcode },
6368
    { Bad_Opcode },
6369
    /* 50 */
6370
    { "vmovmskpX",  { Gdq, Ux }, PREFIX_OPCODE },
6371
    { PREFIX_TABLE (PREFIX_0F51) },
6372
    { PREFIX_TABLE (PREFIX_0F52) },
6373
    { PREFIX_TABLE (PREFIX_0F53) },
6374
    { "vandpX",   { XM, Vex, EXx }, PREFIX_OPCODE },
6375
    { "vandnpX",  { XM, Vex, EXx }, PREFIX_OPCODE },
6376
    { "vorpX",    { XM, Vex, EXx }, PREFIX_OPCODE },
6377
    { "vxorpX",   { XM, Vex, EXx }, PREFIX_OPCODE },
6378
    /* 58 */
6379
    { PREFIX_TABLE (PREFIX_0F58) },
6380
    { PREFIX_TABLE (PREFIX_0F59) },
6381
    { PREFIX_TABLE (PREFIX_0F5A) },
6382
    { PREFIX_TABLE (PREFIX_0F5B) },
6383
    { PREFIX_TABLE (PREFIX_0F5C) },
6384
    { PREFIX_TABLE (PREFIX_0F5D) },
6385
    { PREFIX_TABLE (PREFIX_0F5E) },
6386
    { PREFIX_TABLE (PREFIX_0F5F) },
6387
    /* 60 */
6388
    { "vpunpcklbw", { XM, Vex, EXx }, PREFIX_DATA },
6389
    { "vpunpcklwd", { XM, Vex, EXx }, PREFIX_DATA },
6390
    { "vpunpckldq", { XM, Vex, EXx }, PREFIX_DATA },
6391
    { "vpacksswb",  { XM, Vex, EXx }, PREFIX_DATA },
6392
    { "vpcmpgtb", { XM, Vex, EXx }, PREFIX_DATA },
6393
    { "vpcmpgtw", { XM, Vex, EXx }, PREFIX_DATA },
6394
    { "vpcmpgtd", { XM, Vex, EXx }, PREFIX_DATA },
6395
    { "vpackuswb",  { XM, Vex, EXx }, PREFIX_DATA },
6396
    /* 68 */
6397
    { "vpunpckhbw", { XM, Vex, EXx }, PREFIX_DATA },
6398
    { "vpunpckhwd", { XM, Vex, EXx }, PREFIX_DATA },
6399
    { "vpunpckhdq", { XM, Vex, EXx }, PREFIX_DATA },
6400
    { "vpackssdw",  { XM, Vex, EXx }, PREFIX_DATA },
6401
    { "vpunpcklqdq",  { XM, Vex, EXx }, PREFIX_DATA },
6402
    { "vpunpckhqdq",  { XM, Vex, EXx }, PREFIX_DATA },
6403
    { VEX_LEN_TABLE (VEX_LEN_0F6E) },
6404
    { PREFIX_TABLE (PREFIX_VEX_0F6F) },
6405
    /* 70 */
6406
    { PREFIX_TABLE (PREFIX_VEX_0F70) },
6407
    { REG_TABLE (REG_VEX_0F71) },
6408
    { REG_TABLE (REG_VEX_0F72) },
6409
    { REG_TABLE (REG_VEX_0F73) },
6410
    { "vpcmpeqb", { XM, Vex, EXx }, PREFIX_DATA },
6411
    { "vpcmpeqw", { XM, Vex, EXx }, PREFIX_DATA },
6412
    { "vpcmpeqd", { XM, Vex, EXx }, PREFIX_DATA },
6413
    { VEX_LEN_TABLE (VEX_LEN_0F77) },
6414
    /* 78 */
6415
    { Bad_Opcode },
6416
    { Bad_Opcode },
6417
    { Bad_Opcode },
6418
    { Bad_Opcode },
6419
    { PREFIX_TABLE (PREFIX_0F7C) },
6420
    { PREFIX_TABLE (PREFIX_0F7D) },
6421
    { PREFIX_TABLE (PREFIX_VEX_0F7E) },
6422
    { PREFIX_TABLE (PREFIX_VEX_0F7F) },
6423
    /* 80 */
6424
    { Bad_Opcode },
6425
    { Bad_Opcode },
6426
    { Bad_Opcode },
6427
    { Bad_Opcode },
6428
    { Bad_Opcode },
6429
    { Bad_Opcode },
6430
    { Bad_Opcode },
6431
    { Bad_Opcode },
6432
    /* 88 */
6433
    { Bad_Opcode },
6434
    { Bad_Opcode },
6435
    { Bad_Opcode },
6436
    { Bad_Opcode },
6437
    { Bad_Opcode },
6438
    { Bad_Opcode },
6439
    { Bad_Opcode },
6440
    { Bad_Opcode },
6441
    /* 90 */
6442
    { VEX_LEN_TABLE (VEX_LEN_0F90) },
6443
    { VEX_LEN_TABLE (VEX_LEN_0F91) },
6444
    { VEX_LEN_TABLE (VEX_LEN_0F92) },
6445
    { VEX_LEN_TABLE (VEX_LEN_0F93) },
6446
    { Bad_Opcode },
6447
    { Bad_Opcode },
6448
    { Bad_Opcode },
6449
    { Bad_Opcode },
6450
    /* 98 */
6451
    { VEX_LEN_TABLE (VEX_LEN_0F98) },
6452
    { VEX_LEN_TABLE (VEX_LEN_0F99) },
6453
    { Bad_Opcode },
6454
    { Bad_Opcode },
6455
    { Bad_Opcode },
6456
    { Bad_Opcode },
6457
    { Bad_Opcode },
6458
    { Bad_Opcode },
6459
    /* a0 */
6460
    { Bad_Opcode },
6461
    { Bad_Opcode },
6462
    { Bad_Opcode },
6463
    { Bad_Opcode },
6464
    { Bad_Opcode },
6465
    { Bad_Opcode },
6466
    { Bad_Opcode },
6467
    { Bad_Opcode },
6468
    /* a8 */
6469
    { Bad_Opcode },
6470
    { Bad_Opcode },
6471
    { Bad_Opcode },
6472
    { Bad_Opcode },
6473
    { Bad_Opcode },
6474
    { Bad_Opcode },
6475
    { REG_TABLE (REG_VEX_0FAE) },
6476
    { Bad_Opcode },
6477
    /* b0 */
6478
    { Bad_Opcode },
6479
    { Bad_Opcode },
6480
    { Bad_Opcode },
6481
    { Bad_Opcode },
6482
    { Bad_Opcode },
6483
    { Bad_Opcode },
6484
    { Bad_Opcode },
6485
    { Bad_Opcode },
6486
    /* b8 */
6487
    { Bad_Opcode },
6488
    { Bad_Opcode },
6489
    { Bad_Opcode },
6490
    { Bad_Opcode },
6491
    { Bad_Opcode },
6492
    { Bad_Opcode },
6493
    { Bad_Opcode },
6494
    { Bad_Opcode },
6495
    /* c0 */
6496
    { Bad_Opcode },
6497
    { Bad_Opcode },
6498
    { PREFIX_TABLE (PREFIX_0FC2) },
6499
    { Bad_Opcode },
6500
    { VEX_LEN_TABLE (VEX_LEN_0FC4) },
6501
    { "vpextrw",  { Gd, Uxmm, Ib }, PREFIX_DATA },
6502
    { "vshufpX",  { XM, Vex, EXx, Ib }, PREFIX_OPCODE },
6503
    { Bad_Opcode },
6504
    /* c8 */
6505
    { Bad_Opcode },
6506
    { Bad_Opcode },
6507
    { Bad_Opcode },
6508
    { Bad_Opcode },
6509
    { Bad_Opcode },
6510
    { Bad_Opcode },
6511
    { Bad_Opcode },
6512
    { Bad_Opcode },
6513
    /* d0 */
6514
    { PREFIX_TABLE (PREFIX_0FD0) },
6515
    { "vpsrlw",   { XM, Vex, EXxmm }, PREFIX_DATA },
6516
    { "vpsrld",   { XM, Vex, EXxmm }, PREFIX_DATA },
6517
    { "vpsrlq",   { XM, Vex, EXxmm }, PREFIX_DATA },
6518
    { "vpaddq",   { XM, Vex, EXx }, PREFIX_DATA },
6519
    { "vpmullw",  { XM, Vex, EXx }, PREFIX_DATA },
6520
    { VEX_LEN_TABLE (VEX_LEN_0FD6) },
6521
    { "vpmovmskb",  { Gdq, Ux }, PREFIX_DATA },
6522
    /* d8 */
6523
    { "vpsubusb", { XM, Vex, EXx }, PREFIX_DATA },
6524
    { "vpsubusw", { XM, Vex, EXx }, PREFIX_DATA },
6525
    { "vpminub",  { XM, Vex, EXx }, PREFIX_DATA },
6526
    { "vpand",    { XM, Vex, EXx }, PREFIX_DATA },
6527
    { "vpaddusb", { XM, Vex, EXx }, PREFIX_DATA },
6528
    { "vpaddusw", { XM, Vex, EXx }, PREFIX_DATA },
6529
    { "vpmaxub",  { XM, Vex, EXx }, PREFIX_DATA },
6530
    { "vpandn",   { XM, Vex, EXx }, PREFIX_DATA },
6531
    /* e0 */
6532
    { "vpavgb",   { XM, Vex, EXx }, PREFIX_DATA },
6533
    { "vpsraw",   { XM, Vex, EXxmm }, PREFIX_DATA },
6534
    { "vpsrad",   { XM, Vex, EXxmm }, PREFIX_DATA },
6535
    { "vpavgw",   { XM, Vex, EXx }, PREFIX_DATA },
6536
    { "vpmulhuw", { XM, Vex, EXx }, PREFIX_DATA },
6537
    { "vpmulhw",  { XM, Vex, EXx }, PREFIX_DATA },
6538
    { PREFIX_TABLE (PREFIX_0FE6) },
6539
    { "vmovntdq", { Mx, XM }, PREFIX_DATA },
6540
    /* e8 */
6541
    { "vpsubsb",  { XM, Vex, EXx }, PREFIX_DATA },
6542
    { "vpsubsw",  { XM, Vex, EXx }, PREFIX_DATA },
6543
    { "vpminsw",  { XM, Vex, EXx }, PREFIX_DATA },
6544
    { "vpor",   { XM, Vex, EXx }, PREFIX_DATA },
6545
    { "vpaddsb",  { XM, Vex, EXx }, PREFIX_DATA },
6546
    { "vpaddsw",  { XM, Vex, EXx }, PREFIX_DATA },
6547
    { "vpmaxsw",  { XM, Vex, EXx }, PREFIX_DATA },
6548
    { "vpxor",    { XM, Vex, EXx }, PREFIX_DATA },
6549
    /* f0 */
6550
    { PREFIX_TABLE (PREFIX_0FF0) },
6551
    { "vpsllw",   { XM, Vex, EXxmm }, PREFIX_DATA },
6552
    { "vpslld",   { XM, Vex, EXxmm }, PREFIX_DATA },
6553
    { "vpsllq",   { XM, Vex, EXxmm }, PREFIX_DATA },
6554
    { "vpmuludq", { XM, Vex, EXx }, PREFIX_DATA },
6555
    { "vpmaddwd", { XM, Vex, EXx }, PREFIX_DATA },
6556
    { "vpsadbw",  { XM, Vex, EXx }, PREFIX_DATA },
6557
    { "vmaskmovdqu",  { XM, Uxmm }, PREFIX_DATA },
6558
    /* f8 */
6559
    { "vpsubb",   { XM, Vex, EXx }, PREFIX_DATA },
6560
    { "vpsubw",   { XM, Vex, EXx }, PREFIX_DATA },
6561
    { "vpsubd",   { XM, Vex, EXx }, PREFIX_DATA },
6562
    { "vpsubq",   { XM, Vex, EXx }, PREFIX_DATA },
6563
    { "vpaddb",   { XM, Vex, EXx }, PREFIX_DATA },
6564
    { "vpaddw",   { XM, Vex, EXx }, PREFIX_DATA },
6565
    { "vpaddd",   { XM, Vex, EXx }, PREFIX_DATA },
6566
    { Bad_Opcode },
6567
  },
6568
  /* VEX_0F38 */
6569
  {
6570
    /* 00 */
6571
    { "vpshufb",  { XM, Vex, EXx }, PREFIX_DATA },
6572
    { "vphaddw",  { XM, Vex, EXx }, PREFIX_DATA },
6573
    { "vphaddd",  { XM, Vex, EXx }, PREFIX_DATA },
6574
    { "vphaddsw", { XM, Vex, EXx }, PREFIX_DATA },
6575
    { "vpmaddubsw", { XM, Vex, EXx }, PREFIX_DATA },
6576
    { "vphsubw",  { XM, Vex, EXx }, PREFIX_DATA },
6577
    { "vphsubd",  { XM, Vex, EXx }, PREFIX_DATA },
6578
    { "vphsubsw", { XM, Vex, EXx }, PREFIX_DATA },
6579
    /* 08 */
6580
    { "vpsignb",  { XM, Vex, EXx }, PREFIX_DATA },
6581
    { "vpsignw",  { XM, Vex, EXx }, PREFIX_DATA },
6582
    { "vpsignd",  { XM, Vex, EXx }, PREFIX_DATA },
6583
    { "vpmulhrsw",  { XM, Vex, EXx }, PREFIX_DATA },
6584
    { VEX_W_TABLE (VEX_W_0F380C) },
6585
    { VEX_W_TABLE (VEX_W_0F380D) },
6586
    { VEX_W_TABLE (VEX_W_0F380E) },
6587
    { VEX_W_TABLE (VEX_W_0F380F) },
6588
    /* 10 */
6589
    { Bad_Opcode },
6590
    { Bad_Opcode },
6591
    { Bad_Opcode },
6592
    { VEX_W_TABLE (VEX_W_0F3813) },
6593
    { Bad_Opcode },
6594
    { Bad_Opcode },
6595
    { VEX_LEN_TABLE (VEX_LEN_0F3816) },
6596
    { "vptest",   { XM, EXx }, PREFIX_DATA },
6597
    /* 18 */
6598
    { VEX_W_TABLE (VEX_W_0F3818) },
6599
    { VEX_LEN_TABLE (VEX_LEN_0F3819) },
6600
    { VEX_LEN_TABLE (VEX_LEN_0F381A) },
6601
    { Bad_Opcode },
6602
    { "vpabsb",   { XM, EXx }, PREFIX_DATA },
6603
    { "vpabsw",   { XM, EXx }, PREFIX_DATA },
6604
    { "vpabsd",   { XM, EXx }, PREFIX_DATA },
6605
    { Bad_Opcode },
6606
    /* 20 */
6607
    { "vpmovsxbw",  { XM, EXxmmq }, PREFIX_DATA },
6608
    { "vpmovsxbd",  { XM, EXxmmqd }, PREFIX_DATA },
6609
    { "vpmovsxbq",  { XM, EXxmmdw }, PREFIX_DATA },
6610
    { "vpmovsxwd",  { XM, EXxmmq }, PREFIX_DATA },
6611
    { "vpmovsxwq",  { XM, EXxmmqd }, PREFIX_DATA },
6612
    { "vpmovsxdq",  { XM, EXxmmq }, PREFIX_DATA },
6613
    { Bad_Opcode },
6614
    { Bad_Opcode },
6615
    /* 28 */
6616
    { "vpmuldq",  { XM, Vex, EXx }, PREFIX_DATA },
6617
    { "vpcmpeqq", { XM, Vex, EXx }, PREFIX_DATA },
6618
    { "vmovntdqa",  { XM, Mx }, PREFIX_DATA },
6619
    { "vpackusdw",  { XM, Vex, EXx }, PREFIX_DATA },
6620
    { VEX_W_TABLE (VEX_W_0F382C) },
6621
    { VEX_W_TABLE (VEX_W_0F382D) },
6622
    { VEX_W_TABLE (VEX_W_0F382E) },
6623
    { VEX_W_TABLE (VEX_W_0F382F) },
6624
    /* 30 */
6625
    { "vpmovzxbw",  { XM, EXxmmq }, PREFIX_DATA },
6626
    { "vpmovzxbd",  { XM, EXxmmqd }, PREFIX_DATA },
6627
    { "vpmovzxbq",  { XM, EXxmmdw }, PREFIX_DATA },
6628
    { "vpmovzxwd",  { XM, EXxmmq }, PREFIX_DATA },
6629
    { "vpmovzxwq",  { XM, EXxmmqd }, PREFIX_DATA },
6630
    { "vpmovzxdq",  { XM, EXxmmq }, PREFIX_DATA },
6631
    { VEX_LEN_TABLE (VEX_LEN_0F3836) },
6632
    { "vpcmpgtq", { XM, Vex, EXx }, PREFIX_DATA },
6633
    /* 38 */
6634
    { "vpminsb",  { XM, Vex, EXx }, PREFIX_DATA },
6635
    { "vpminsd",  { XM, Vex, EXx }, PREFIX_DATA },
6636
    { "vpminuw",  { XM, Vex, EXx }, PREFIX_DATA },
6637
    { "vpminud",  { XM, Vex, EXx }, PREFIX_DATA },
6638
    { "vpmaxsb",  { XM, Vex, EXx }, PREFIX_DATA },
6639
    { "vpmaxsd",  { XM, Vex, EXx }, PREFIX_DATA },
6640
    { "vpmaxuw",  { XM, Vex, EXx }, PREFIX_DATA },
6641
    { "vpmaxud",  { XM, Vex, EXx }, PREFIX_DATA },
6642
    /* 40 */
6643
    { "vpmulld",  { XM, Vex, EXx }, PREFIX_DATA },
6644
    { VEX_LEN_TABLE (VEX_LEN_0F3841) },
6645
    { Bad_Opcode },
6646
    { Bad_Opcode },
6647
    { Bad_Opcode },
6648
    { "vpsrlv%DQ", { XM, Vex, EXx }, PREFIX_DATA },
6649
    { VEX_W_TABLE (VEX_W_0F3846) },
6650
    { "vpsllv%DQ", { XM, Vex, EXx }, PREFIX_DATA },
6651
    /* 48 */
6652
    { X86_64_TABLE (X86_64_VEX_0F3848) },
6653
    { X86_64_TABLE (X86_64_VEX_0F3849) },
6654
    { X86_64_TABLE (X86_64_VEX_0F384A) },
6655
    { X86_64_TABLE (X86_64_VEX_0F384B) },
6656
    { Bad_Opcode },
6657
    { Bad_Opcode },
6658
    { Bad_Opcode },
6659
    { Bad_Opcode },
6660
    /* 50 */
6661
    { VEX_W_TABLE (VEX_W_0F3850) },
6662
    { VEX_W_TABLE (VEX_W_0F3851) },
6663
    { VEX_W_TABLE (VEX_W_0F3852) },
6664
    { VEX_W_TABLE (VEX_W_0F3853) },
6665
    { Bad_Opcode },
6666
    { Bad_Opcode },
6667
    { Bad_Opcode },
6668
    { Bad_Opcode },
6669
    /* 58 */
6670
    { VEX_W_TABLE (VEX_W_0F3858) },
6671
    { VEX_W_TABLE (VEX_W_0F3859) },
6672
    { VEX_LEN_TABLE (VEX_LEN_0F385A) },
6673
    { Bad_Opcode },
6674
    { X86_64_TABLE (X86_64_VEX_0F385C) },
6675
    { Bad_Opcode },
6676
    { X86_64_TABLE (X86_64_VEX_0F385E) },
6677
    { X86_64_TABLE (X86_64_VEX_0F385F) },
6678
    /* 60 */
6679
    { Bad_Opcode },
6680
    { Bad_Opcode },
6681
    { Bad_Opcode },
6682
    { Bad_Opcode },
6683
    { Bad_Opcode },
6684
    { Bad_Opcode },
6685
    { Bad_Opcode },
6686
    { Bad_Opcode },
6687
    /* 68 */
6688
    { Bad_Opcode },
6689
    { Bad_Opcode },
6690
    { Bad_Opcode },
6691
    { X86_64_TABLE (X86_64_VEX_0F386B) },
6692
    { X86_64_TABLE (X86_64_VEX_0F386C) },
6693
    { Bad_Opcode },
6694
    { X86_64_TABLE (X86_64_VEX_0F386E) },
6695
    { X86_64_TABLE (X86_64_VEX_0F386F) },
6696
    /* 70 */
6697
    { Bad_Opcode },
6698
    { Bad_Opcode },
6699
    { PREFIX_TABLE (PREFIX_VEX_0F3872) },
6700
    { Bad_Opcode },
6701
    { Bad_Opcode },
6702
    { Bad_Opcode },
6703
    { Bad_Opcode },
6704
    { Bad_Opcode },
6705
    /* 78 */
6706
    { VEX_W_TABLE (VEX_W_0F3878) },
6707
    { VEX_W_TABLE (VEX_W_0F3879) },
6708
    { Bad_Opcode },
6709
    { Bad_Opcode },
6710
    { Bad_Opcode },
6711
    { Bad_Opcode },
6712
    { Bad_Opcode },
6713
    { Bad_Opcode },
6714
    /* 80 */
6715
    { Bad_Opcode },
6716
    { Bad_Opcode },
6717
    { Bad_Opcode },
6718
    { Bad_Opcode },
6719
    { Bad_Opcode },
6720
    { Bad_Opcode },
6721
    { Bad_Opcode },
6722
    { Bad_Opcode },
6723
    /* 88 */
6724
    { Bad_Opcode },
6725
    { Bad_Opcode },
6726
    { Bad_Opcode },
6727
    { Bad_Opcode },
6728
    { "vpmaskmov%DQ", { XM, Vex, Mx }, PREFIX_DATA },
6729
    { Bad_Opcode },
6730
    { "vpmaskmov%DQ", { Mx, Vex, XM }, PREFIX_DATA },
6731
    { Bad_Opcode },
6732
    /* 90 */
6733
    { "vpgatherd%DQ", { XM, MVexVSIBDWpX, VexGatherD }, PREFIX_DATA },
6734
    { "vpgatherq%DQ", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, PREFIX_DATA },
6735
    { "vgatherdp%XW", { XM, MVexVSIBDWpX, VexGatherD }, PREFIX_DATA },
6736
    { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, PREFIX_DATA },
6737
    { Bad_Opcode },
6738
    { Bad_Opcode },
6739
    { "vfmaddsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6740
    { "vfmsubadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6741
    /* 98 */
6742
    { "vfmadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6743
    { "vfmadd132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6744
    { "vfmsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6745
    { "vfmsub132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6746
    { "vfnmadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6747
    { "vfnmadd132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6748
    { "vfnmsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6749
    { "vfnmsub132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6750
    /* a0 */
6751
    { Bad_Opcode },
6752
    { Bad_Opcode },
6753
    { Bad_Opcode },
6754
    { Bad_Opcode },
6755
    { Bad_Opcode },
6756
    { Bad_Opcode },
6757
    { "vfmaddsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6758
    { "vfmsubadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6759
    /* a8 */
6760
    { "vfmadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6761
    { "vfmadd213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6762
    { "vfmsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6763
    { "vfmsub213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6764
    { "vfnmadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6765
    { "vfnmadd213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6766
    { "vfnmsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6767
    { "vfnmsub213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6768
    /* b0 */
6769
    { VEX_W_TABLE (VEX_W_0F38B0) },
6770
    { VEX_W_TABLE (VEX_W_0F38B1) },
6771
    { Bad_Opcode },
6772
    { Bad_Opcode },
6773
    { VEX_W_TABLE (VEX_W_0F38B4) },
6774
    { VEX_W_TABLE (VEX_W_0F38B5) },
6775
    { "vfmaddsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6776
    { "vfmsubadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6777
    /* b8 */
6778
    { "vfmadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6779
    { "vfmadd231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6780
    { "vfmsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6781
    { "vfmsub231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6782
    { "vfnmadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6783
    { "vfnmadd231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6784
    { "vfnmsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6785
    { "vfnmsub231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6786
    /* c0 */
6787
    { Bad_Opcode },
6788
    { Bad_Opcode },
6789
    { Bad_Opcode },
6790
    { Bad_Opcode },
6791
    { Bad_Opcode },
6792
    { Bad_Opcode },
6793
    { Bad_Opcode },
6794
    { Bad_Opcode },
6795
    /* c8 */
6796
    { Bad_Opcode },
6797
    { Bad_Opcode },
6798
    { Bad_Opcode },
6799
    { PREFIX_TABLE (PREFIX_VEX_0F38CB) },
6800
    { PREFIX_TABLE (PREFIX_VEX_0F38CC) },
6801
    { PREFIX_TABLE (PREFIX_VEX_0F38CD) },
6802
    { Bad_Opcode },
6803
    { VEX_W_TABLE (VEX_W_0F38CF) },
6804
    /* d0 */
6805
    { Bad_Opcode },
6806
    { Bad_Opcode },
6807
    { VEX_W_TABLE (VEX_W_0F38D2) },
6808
    { VEX_W_TABLE (VEX_W_0F38D3) },
6809
    { Bad_Opcode },
6810
    { Bad_Opcode },
6811
    { Bad_Opcode },
6812
    { Bad_Opcode },
6813
    /* d8 */
6814
    { Bad_Opcode },
6815
    { Bad_Opcode },
6816
    { VEX_W_TABLE (VEX_W_0F38DA) },
6817
    { VEX_LEN_TABLE (VEX_LEN_0F38DB) },
6818
    { "vaesenc",  { XM, Vex, EXx }, PREFIX_DATA },
6819
    { "vaesenclast",  { XM, Vex, EXx }, PREFIX_DATA },
6820
    { "vaesdec",  { XM, Vex, EXx }, PREFIX_DATA },
6821
    { "vaesdeclast",  { XM, Vex, EXx }, PREFIX_DATA },
6822
    /* e0 */
6823
    { X86_64_TABLE (X86_64_VEX_0F38Ex) },
6824
    { X86_64_TABLE (X86_64_VEX_0F38Ex) },
6825
    { X86_64_TABLE (X86_64_VEX_0F38Ex) },
6826
    { X86_64_TABLE (X86_64_VEX_0F38Ex) },
6827
    { X86_64_TABLE (X86_64_VEX_0F38Ex) },
6828
    { X86_64_TABLE (X86_64_VEX_0F38Ex) },
6829
    { X86_64_TABLE (X86_64_VEX_0F38Ex) },
6830
    { X86_64_TABLE (X86_64_VEX_0F38Ex) },
6831
    /* e8 */
6832
    { X86_64_TABLE (X86_64_VEX_0F38Ex) },
6833
    { X86_64_TABLE (X86_64_VEX_0F38Ex) },
6834
    { X86_64_TABLE (X86_64_VEX_0F38Ex) },
6835
    { X86_64_TABLE (X86_64_VEX_0F38Ex) },
6836
    { X86_64_TABLE (X86_64_VEX_0F38Ex) },
6837
    { X86_64_TABLE (X86_64_VEX_0F38Ex) },
6838
    { X86_64_TABLE (X86_64_VEX_0F38Ex) },
6839
    { X86_64_TABLE (X86_64_VEX_0F38Ex) },
6840
    /* f0 */
6841
    { Bad_Opcode },
6842
    { Bad_Opcode },
6843
    { VEX_LEN_TABLE (VEX_LEN_0F38F2) },
6844
    { VEX_LEN_TABLE (VEX_LEN_0F38F3) },
6845
    { Bad_Opcode },
6846
    { VEX_LEN_TABLE (VEX_LEN_0F38F5) },
6847
    { VEX_LEN_TABLE (VEX_LEN_0F38F6) },
6848
    { VEX_LEN_TABLE (VEX_LEN_0F38F7) },
6849
    /* f8 */
6850
    { Bad_Opcode },
6851
    { Bad_Opcode },
6852
    { Bad_Opcode },
6853
    { Bad_Opcode },
6854
    { Bad_Opcode },
6855
    { Bad_Opcode },
6856
    { Bad_Opcode },
6857
    { Bad_Opcode },
6858
  },
6859
  /* VEX_0F3A */
6860
  {
6861
    /* 00 */
6862
    { VEX_LEN_TABLE (VEX_LEN_0F3A00) },
6863
    { VEX_LEN_TABLE (VEX_LEN_0F3A01) },
6864
    { VEX_W_TABLE (VEX_W_0F3A02) },
6865
    { Bad_Opcode },
6866
    { VEX_W_TABLE (VEX_W_0F3A04) },
6867
    { VEX_W_TABLE (VEX_W_0F3A05) },
6868
    { VEX_LEN_TABLE (VEX_LEN_0F3A06) },
6869
    { Bad_Opcode },
6870
    /* 08 */
6871
    { "vroundps", { XM, EXx, Ib }, PREFIX_DATA },
6872
    { "vroundpd", { XM, EXx, Ib }, PREFIX_DATA },
6873
    { "vroundss", { XMScalar, VexScalar, EXd, Ib }, PREFIX_DATA },
6874
    { "vroundsd", { XMScalar, VexScalar, EXq, Ib }, PREFIX_DATA },
6875
    { "vblendps", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6876
    { "vblendpd", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6877
    { "vpblendw", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6878
    { "vpalignr", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6879
    /* 10 */
6880
    { Bad_Opcode },
6881
    { Bad_Opcode },
6882
    { Bad_Opcode },
6883
    { Bad_Opcode },
6884
    { VEX_LEN_TABLE (VEX_LEN_0F3A14) },
6885
    { VEX_LEN_TABLE (VEX_LEN_0F3A15) },
6886
    { VEX_LEN_TABLE (VEX_LEN_0F3A16) },
6887
    { VEX_LEN_TABLE (VEX_LEN_0F3A17) },
6888
    /* 18 */
6889
    { VEX_LEN_TABLE (VEX_LEN_0F3A18) },
6890
    { VEX_LEN_TABLE (VEX_LEN_0F3A19) },
6891
    { Bad_Opcode },
6892
    { Bad_Opcode },
6893
    { Bad_Opcode },
6894
    { VEX_W_TABLE (VEX_W_0F3A1D) },
6895
    { Bad_Opcode },
6896
    { Bad_Opcode },
6897
    /* 20 */
6898
    { VEX_LEN_TABLE (VEX_LEN_0F3A20) },
6899
    { VEX_LEN_TABLE (VEX_LEN_0F3A21) },
6900
    { VEX_LEN_TABLE (VEX_LEN_0F3A22) },
6901
    { Bad_Opcode },
6902
    { Bad_Opcode },
6903
    { Bad_Opcode },
6904
    { Bad_Opcode },
6905
    { Bad_Opcode },
6906
    /* 28 */
6907
    { Bad_Opcode },
6908
    { Bad_Opcode },
6909
    { Bad_Opcode },
6910
    { Bad_Opcode },
6911
    { Bad_Opcode },
6912
    { Bad_Opcode },
6913
    { Bad_Opcode },
6914
    { Bad_Opcode },
6915
    /* 30 */
6916
    { VEX_LEN_TABLE (VEX_LEN_0F3A30) },
6917
    { VEX_LEN_TABLE (VEX_LEN_0F3A31) },
6918
    { VEX_LEN_TABLE (VEX_LEN_0F3A32) },
6919
    { VEX_LEN_TABLE (VEX_LEN_0F3A33) },
6920
    { Bad_Opcode },
6921
    { Bad_Opcode },
6922
    { Bad_Opcode },
6923
    { Bad_Opcode },
6924
    /* 38 */
6925
    { VEX_LEN_TABLE (VEX_LEN_0F3A38) },
6926
    { VEX_LEN_TABLE (VEX_LEN_0F3A39) },
6927
    { Bad_Opcode },
6928
    { Bad_Opcode },
6929
    { Bad_Opcode },
6930
    { Bad_Opcode },
6931
    { Bad_Opcode },
6932
    { Bad_Opcode },
6933
    /* 40 */
6934
    { "vdpps",    { XM, Vex, EXx, Ib }, PREFIX_DATA },
6935
    { VEX_LEN_TABLE (VEX_LEN_0F3A41) },
6936
    { "vmpsadbw", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6937
    { Bad_Opcode },
6938
    { "vpclmulqdq", { XM, Vex, EXx, PCLMUL }, PREFIX_DATA },
6939
    { Bad_Opcode },
6940
    { VEX_LEN_TABLE (VEX_LEN_0F3A46) },
6941
    { Bad_Opcode },
6942
    /* 48 */
6943
    { "vpermil2ps", { XM, Vex, EXx, XMVexI4, VexI4 }, PREFIX_DATA },
6944
    { "vpermil2pd", { XM, Vex, EXx, XMVexI4, VexI4 }, PREFIX_DATA },
6945
    { VEX_W_TABLE (VEX_W_0F3A4A) },
6946
    { VEX_W_TABLE (VEX_W_0F3A4B) },
6947
    { VEX_W_TABLE (VEX_W_0F3A4C) },
6948
    { Bad_Opcode },
6949
    { Bad_Opcode },
6950
    { Bad_Opcode },
6951
    /* 50 */
6952
    { Bad_Opcode },
6953
    { Bad_Opcode },
6954
    { Bad_Opcode },
6955
    { Bad_Opcode },
6956
    { Bad_Opcode },
6957
    { Bad_Opcode },
6958
    { Bad_Opcode },
6959
    { Bad_Opcode },
6960
    /* 58 */
6961
    { Bad_Opcode },
6962
    { Bad_Opcode },
6963
    { Bad_Opcode },
6964
    { Bad_Opcode },
6965
    { "vfmaddsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6966
    { "vfmaddsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6967
    { "vfmsubaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6968
    { "vfmsubaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6969
    /* 60 */
6970
    { VEX_LEN_TABLE (VEX_LEN_0F3A60) },
6971
    { VEX_LEN_TABLE (VEX_LEN_0F3A61) },
6972
    { VEX_LEN_TABLE (VEX_LEN_0F3A62) },
6973
    { VEX_LEN_TABLE (VEX_LEN_0F3A63) },
6974
    { Bad_Opcode },
6975
    { Bad_Opcode },
6976
    { Bad_Opcode },
6977
    { Bad_Opcode },
6978
    /* 68 */
6979
    { "vfmaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6980
    { "vfmaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6981
    { "vfmaddss", { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA },
6982
    { "vfmaddsd", { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA },
6983
    { "vfmsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6984
    { "vfmsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6985
    { "vfmsubss", { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA },
6986
    { "vfmsubsd", { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA },
6987
    /* 70 */
6988
    { Bad_Opcode },
6989
    { Bad_Opcode },
6990
    { Bad_Opcode },
6991
    { Bad_Opcode },
6992
    { Bad_Opcode },
6993
    { Bad_Opcode },
6994
    { Bad_Opcode },
6995
    { Bad_Opcode },
6996
    /* 78 */
6997
    { "vfnmaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6998
    { "vfnmaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6999
    { "vfnmaddss",  { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA },
7000
    { "vfnmaddsd",  { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA },
7001
    { "vfnmsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7002
    { "vfnmsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7003
    { "vfnmsubss",  { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA },
7004
    { "vfnmsubsd",  { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA },
7005
    /* 80 */
7006
    { Bad_Opcode },
7007
    { Bad_Opcode },
7008
    { Bad_Opcode },
7009
    { Bad_Opcode },
7010
    { Bad_Opcode },
7011
    { Bad_Opcode },
7012
    { Bad_Opcode },
7013
    { Bad_Opcode },
7014
    /* 88 */
7015
    { Bad_Opcode },
7016
    { Bad_Opcode },
7017
    { Bad_Opcode },
7018
    { Bad_Opcode },
7019
    { Bad_Opcode },
7020
    { Bad_Opcode },
7021
    { Bad_Opcode },
7022
    { Bad_Opcode },
7023
    /* 90 */
7024
    { Bad_Opcode },
7025
    { Bad_Opcode },
7026
    { Bad_Opcode },
7027
    { Bad_Opcode },
7028
    { Bad_Opcode },
7029
    { Bad_Opcode },
7030
    { Bad_Opcode },
7031
    { Bad_Opcode },
7032
    /* 98 */
7033
    { Bad_Opcode },
7034
    { Bad_Opcode },
7035
    { Bad_Opcode },
7036
    { Bad_Opcode },
7037
    { Bad_Opcode },
7038
    { Bad_Opcode },
7039
    { Bad_Opcode },
7040
    { Bad_Opcode },
7041
    /* a0 */
7042
    { Bad_Opcode },
7043
    { Bad_Opcode },
7044
    { Bad_Opcode },
7045
    { Bad_Opcode },
7046
    { Bad_Opcode },
7047
    { Bad_Opcode },
7048
    { Bad_Opcode },
7049
    { Bad_Opcode },
7050
    /* a8 */
7051
    { Bad_Opcode },
7052
    { Bad_Opcode },
7053
    { Bad_Opcode },
7054
    { Bad_Opcode },
7055
    { Bad_Opcode },
7056
    { Bad_Opcode },
7057
    { Bad_Opcode },
7058
    { Bad_Opcode },
7059
    /* b0 */
7060
    { Bad_Opcode },
7061
    { Bad_Opcode },
7062
    { Bad_Opcode },
7063
    { Bad_Opcode },
7064
    { Bad_Opcode },
7065
    { Bad_Opcode },
7066
    { Bad_Opcode },
7067
    { Bad_Opcode },
7068
    /* b8 */
7069
    { Bad_Opcode },
7070
    { Bad_Opcode },
7071
    { Bad_Opcode },
7072
    { Bad_Opcode },
7073
    { Bad_Opcode },
7074
    { Bad_Opcode },
7075
    { Bad_Opcode },
7076
    { Bad_Opcode },
7077
    /* c0 */
7078
    { Bad_Opcode },
7079
    { Bad_Opcode },
7080
    { Bad_Opcode },
7081
    { Bad_Opcode },
7082
    { Bad_Opcode },
7083
    { Bad_Opcode },
7084
    { Bad_Opcode },
7085
    { Bad_Opcode },
7086
    /* c8 */
7087
    { Bad_Opcode },
7088
    { Bad_Opcode },
7089
    { Bad_Opcode },
7090
    { Bad_Opcode },
7091
    { Bad_Opcode },
7092
    { Bad_Opcode },
7093
    { VEX_W_TABLE (VEX_W_0F3ACE) },
7094
    { VEX_W_TABLE (VEX_W_0F3ACF) },
7095
    /* d0 */
7096
    { Bad_Opcode },
7097
    { Bad_Opcode },
7098
    { Bad_Opcode },
7099
    { Bad_Opcode },
7100
    { Bad_Opcode },
7101
    { Bad_Opcode },
7102
    { Bad_Opcode },
7103
    { Bad_Opcode },
7104
    /* d8 */
7105
    { Bad_Opcode },
7106
    { Bad_Opcode },
7107
    { Bad_Opcode },
7108
    { Bad_Opcode },
7109
    { Bad_Opcode },
7110
    { Bad_Opcode },
7111
    { VEX_W_TABLE (VEX_W_0F3ADE) },
7112
    { VEX_LEN_TABLE (VEX_LEN_0F3ADF) },
7113
    /* e0 */
7114
    { Bad_Opcode },
7115
    { Bad_Opcode },
7116
    { Bad_Opcode },
7117
    { Bad_Opcode },
7118
    { Bad_Opcode },
7119
    { Bad_Opcode },
7120
    { Bad_Opcode },
7121
    { Bad_Opcode },
7122
    /* e8 */
7123
    { Bad_Opcode },
7124
    { Bad_Opcode },
7125
    { Bad_Opcode },
7126
    { Bad_Opcode },
7127
    { Bad_Opcode },
7128
    { Bad_Opcode },
7129
    { Bad_Opcode },
7130
    { Bad_Opcode },
7131
    /* f0 */
7132
    { VEX_LEN_TABLE (VEX_LEN_0F3AF0) },
7133
    { Bad_Opcode },
7134
    { Bad_Opcode },
7135
    { Bad_Opcode },
7136
    { Bad_Opcode },
7137
    { Bad_Opcode },
7138
    { Bad_Opcode },
7139
    { Bad_Opcode },
7140
    /* f8 */
7141
    { Bad_Opcode },
7142
    { Bad_Opcode },
7143
    { Bad_Opcode },
7144
    { Bad_Opcode },
7145
    { Bad_Opcode },
7146
    { Bad_Opcode },
7147
    { Bad_Opcode },
7148
    { Bad_Opcode },
7149
  },
7150
};
7151
7152
#include "i386-dis-evex.h"
7153
7154
static const struct dis386 vex_len_table[][2] = {
7155
  /* VEX_LEN_0F12_P_0 */
7156
  {
7157
    { MOD_TABLE (MOD_0F12_PREFIX_0) },
7158
  },
7159
7160
  /* VEX_LEN_0F12_P_2 */
7161
  {
7162
    { "%XEVmovlpYX",  { XM, Vex, Mq }, 0 },
7163
  },
7164
7165
  /* VEX_LEN_0F13 */
7166
  {
7167
    { "%XEVmovlpYX",  { Mq, XM }, PREFIX_OPCODE },
7168
  },
7169
7170
  /* VEX_LEN_0F16_P_0 */
7171
  {
7172
    { MOD_TABLE (MOD_0F16_PREFIX_0) },
7173
  },
7174
7175
  /* VEX_LEN_0F16_P_2 */
7176
  {
7177
    { "%XEVmovhpYX",  { XM, Vex, Mq }, 0 },
7178
  },
7179
7180
  /* VEX_LEN_0F17 */
7181
  {
7182
    { "%XEVmovhpYX",  { Mq, XM }, PREFIX_OPCODE },
7183
  },
7184
7185
  /* VEX_LEN_0F41 */
7186
  {
7187
    { Bad_Opcode },
7188
    { VEX_W_TABLE (VEX_W_0F41_L_1) },
7189
  },
7190
7191
  /* VEX_LEN_0F42 */
7192
  {
7193
    { Bad_Opcode },
7194
    { VEX_W_TABLE (VEX_W_0F42_L_1) },
7195
  },
7196
7197
  /* VEX_LEN_0F44 */
7198
  {
7199
    { VEX_W_TABLE (VEX_W_0F44_L_0) },
7200
  },
7201
7202
  /* VEX_LEN_0F45 */
7203
  {
7204
    { Bad_Opcode },
7205
    { VEX_W_TABLE (VEX_W_0F45_L_1) },
7206
  },
7207
7208
  /* VEX_LEN_0F46 */
7209
  {
7210
    { Bad_Opcode },
7211
    { VEX_W_TABLE (VEX_W_0F46_L_1) },
7212
  },
7213
7214
  /* VEX_LEN_0F47 */
7215
  {
7216
    { Bad_Opcode },
7217
    { VEX_W_TABLE (VEX_W_0F47_L_1) },
7218
  },
7219
7220
  /* VEX_LEN_0F4A */
7221
  {
7222
    { Bad_Opcode },
7223
    { VEX_W_TABLE (VEX_W_0F4A_L_1) },
7224
  },
7225
7226
  /* VEX_LEN_0F4B */
7227
  {
7228
    { Bad_Opcode },
7229
    { VEX_W_TABLE (VEX_W_0F4B_L_1) },
7230
  },
7231
7232
  /* VEX_LEN_0F6E */
7233
  {
7234
    { "%XEvmovYK",  { XMScalar, Edq }, PREFIX_DATA },
7235
  },
7236
7237
  /* VEX_LEN_0F77 */
7238
  {
7239
    { "vzeroupper", { XX }, 0 },
7240
    { "vzeroall", { XX }, 0 },
7241
  },
7242
7243
  /* VEX_LEN_0F7E_P_1 */
7244
  {
7245
    { "%XEvmovqY",  { XMScalar, EXq }, 0 },
7246
  },
7247
7248
  /* VEX_LEN_0F7E_P_2 */
7249
  {
7250
    { "%XEvmovK", { Edq, XMScalar }, 0 },
7251
  },
7252
7253
  /* VEX_LEN_0F90 */
7254
  {
7255
    { VEX_W_TABLE (VEX_W_0F90_L_0) },
7256
  },
7257
7258
  /* VEX_LEN_0F91 */
7259
  {
7260
    { VEX_W_TABLE (VEX_W_0F91_L_0) },
7261
  },
7262
7263
  /* VEX_LEN_0F92 */
7264
  {
7265
    { VEX_W_TABLE (VEX_W_0F92_L_0) },
7266
  },
7267
7268
  /* VEX_LEN_0F93 */
7269
  {
7270
    { VEX_W_TABLE (VEX_W_0F93_L_0) },
7271
  },
7272
7273
  /* VEX_LEN_0F98 */
7274
  {
7275
    { VEX_W_TABLE (VEX_W_0F98_L_0) },
7276
  },
7277
7278
  /* VEX_LEN_0F99 */
7279
  {
7280
    { VEX_W_TABLE (VEX_W_0F99_L_0) },
7281
  },
7282
7283
  /* VEX_LEN_0FAE_R_2 */
7284
  {
7285
    { "vldmxcsr", { Md }, 0 },
7286
  },
7287
7288
  /* VEX_LEN_0FAE_R_3 */
7289
  {
7290
    { "vstmxcsr", { Md }, 0 },
7291
  },
7292
7293
  /* VEX_LEN_0FC4 */
7294
  {
7295
    { "%XEvpinsrwY",  { XM, Vex, Edw, Ib }, PREFIX_DATA },
7296
  },
7297
7298
  /* VEX_LEN_0FD6 */
7299
  {
7300
    { "%XEvmovqY",  { EXqS, XMScalar }, PREFIX_DATA },
7301
  },
7302
7303
  /* VEX_LEN_0F3816 */
7304
  {
7305
    { Bad_Opcode },
7306
    { VEX_W_TABLE (VEX_W_0F3816_L_1) },
7307
  },
7308
7309
  /* VEX_LEN_0F3819 */
7310
  {
7311
    { Bad_Opcode },
7312
    { VEX_W_TABLE (VEX_W_0F3819_L_1) },
7313
  },
7314
7315
  /* VEX_LEN_0F381A */
7316
  {
7317
    { Bad_Opcode },
7318
    { VEX_W_TABLE (VEX_W_0F381A_L_1) },
7319
  },
7320
7321
  /* VEX_LEN_0F3836 */
7322
  {
7323
    { Bad_Opcode },
7324
    { VEX_W_TABLE (VEX_W_0F3836) },
7325
  },
7326
7327
  /* VEX_LEN_0F3841 */
7328
  {
7329
    { "vphminposuw",  { XM, EXx }, PREFIX_DATA },
7330
  },
7331
7332
  /* VEX_LEN_0F3848_X86_64 */
7333
  {
7334
    { VEX_W_TABLE (VEX_W_0F3848_X86_64_L_0) },
7335
  },
7336
7337
  /* VEX_LEN_0F3849_X86_64 */
7338
  {
7339
    { VEX_W_TABLE (VEX_W_0F3849_X86_64_L_0) },
7340
  },
7341
7342
  /* VEX_LEN_0F384A_X86_64_W_0 */
7343
  {
7344
    { PREFIX_TABLE (PREFIX_VEX_0F384A_X86_64_W_0_L_0) },
7345
  },
7346
7347
  /* VEX_LEN_0F384B_X86_64 */
7348
  {
7349
    { VEX_W_TABLE (VEX_W_0F384B_X86_64_L_0) },
7350
  },
7351
7352
  /* VEX_LEN_0F385A */
7353
  {
7354
    { Bad_Opcode },
7355
    { VEX_W_TABLE (VEX_W_0F385A_L_0) },
7356
  },
7357
7358
  /* VEX_LEN_0F385C_X86_64 */
7359
  {
7360
    { VEX_W_TABLE (VEX_W_0F385C_X86_64_L_0) },
7361
  },
7362
7363
  /* VEX_LEN_0F385E_X86_64 */
7364
  {
7365
    { VEX_W_TABLE (VEX_W_0F385E_X86_64_L_0) },
7366
  },
7367
7368
  /* VEX_LEN_0F385F_X86_64 */
7369
  {
7370
    { VEX_W_TABLE (VEX_W_0F385F_X86_64_L_0) },
7371
  },
7372
7373
  /* VEX_LEN_0F386B_X86_64 */
7374
  {
7375
    { VEX_W_TABLE (VEX_W_0F386B_X86_64_L_0) },
7376
  },
7377
7378
  /* VEX_LEN_0F386C_X86_64 */
7379
  {
7380
    { VEX_W_TABLE (VEX_W_0F386C_X86_64_L_0) },
7381
  },
7382
7383
  /* VEX_LEN_0F386E_X86_64 */
7384
  {
7385
    { VEX_W_TABLE (VEX_W_0F386E_X86_64_L_0) },
7386
  },
7387
7388
  /* VEX_LEN_0F386F_X86_64 */
7389
  {
7390
    { VEX_W_TABLE (VEX_W_0F386F_X86_64_L_0) },
7391
  },
7392
7393
  /* VEX_LEN_0F38CB_P_3_W_0 */
7394
  {
7395
    { Bad_Opcode },
7396
    { "vsha512rnds2", { XM, Vex, Rxmmq }, 0 },
7397
  },
7398
7399
  /* VEX_LEN_0F38CC_P_3_W_0 */
7400
  {
7401
    { Bad_Opcode },
7402
    { "vsha512msg1", { XM, Rxmmq }, 0 },
7403
  },
7404
7405
  /* VEX_LEN_0F38CD_P_3_W_0 */
7406
  {
7407
    { Bad_Opcode },
7408
    { "vsha512msg2", { XM, Rymm }, 0 },
7409
  },
7410
7411
  /* VEX_LEN_0F38DA_W_0_P_0 */
7412
  {
7413
    { "vsm3msg1", { XM, Vex, EXxmm }, 0 },
7414
  },
7415
7416
  /* VEX_LEN_0F38DA_W_0_P_2 */
7417
  {
7418
    { "vsm3msg2", { XM, Vex, EXxmm }, 0 },
7419
  },
7420
7421
  /* VEX_LEN_0F38DB */
7422
  {
7423
    { "vaesimc",  { XM, EXx }, PREFIX_DATA },
7424
  },
7425
7426
  /* VEX_LEN_0F38F2 */
7427
  {
7428
    { PREFIX_TABLE (PREFIX_VEX_0F38F2_L_0) },
7429
  },
7430
7431
  /* VEX_LEN_0F38F3 */
7432
  {
7433
    { PREFIX_TABLE (PREFIX_VEX_0F38F3_L_0) },
7434
  },
7435
7436
  /* VEX_LEN_0F38F5 */
7437
  {
7438
    { PREFIX_TABLE(PREFIX_VEX_0F38F5_L_0) },
7439
  },
7440
7441
  /* VEX_LEN_0F38F6 */
7442
  {
7443
    { PREFIX_TABLE(PREFIX_VEX_0F38F6_L_0) },
7444
  },
7445
7446
  /* VEX_LEN_0F38F7 */
7447
  {
7448
    { PREFIX_TABLE(PREFIX_VEX_0F38F7_L_0) },
7449
  },
7450
7451
  /* VEX_LEN_0F3A00 */
7452
  {
7453
    { Bad_Opcode },
7454
    { VEX_W_TABLE (VEX_W_0F3A00_L_1) },
7455
  },
7456
7457
  /* VEX_LEN_0F3A01 */
7458
  {
7459
    { Bad_Opcode },
7460
    { VEX_W_TABLE (VEX_W_0F3A01_L_1) },
7461
  },
7462
7463
  /* VEX_LEN_0F3A06 */
7464
  {
7465
    { Bad_Opcode },
7466
    { VEX_W_TABLE (VEX_W_0F3A06_L_1) },
7467
  },
7468
7469
  /* VEX_LEN_0F3A14 */
7470
  {
7471
    { "%XEvpextrb", { Edb, XM, Ib }, PREFIX_DATA },
7472
  },
7473
7474
  /* VEX_LEN_0F3A15 */
7475
  {
7476
    { "%XEvpextrw", { Edw, XM, Ib }, PREFIX_DATA },
7477
  },
7478
7479
  /* VEX_LEN_0F3A16  */
7480
  {
7481
    { "%XEvpextrK", { Edq, XM, Ib }, PREFIX_DATA },
7482
  },
7483
7484
  /* VEX_LEN_0F3A17 */
7485
  {
7486
    { "%XEvextractps",  { Ed, XM, Ib }, PREFIX_DATA },
7487
  },
7488
7489
  /* VEX_LEN_0F3A18 */
7490
  {
7491
    { Bad_Opcode },
7492
    { VEX_W_TABLE (VEX_W_0F3A18_L_1) },
7493
  },
7494
7495
  /* VEX_LEN_0F3A19 */
7496
  {
7497
    { Bad_Opcode },
7498
    { VEX_W_TABLE (VEX_W_0F3A19_L_1) },
7499
  },
7500
7501
  /* VEX_LEN_0F3A20 */
7502
  {
7503
    { "%XEvpinsrbY",  { XM, Vex, Edb, Ib }, PREFIX_DATA },
7504
  },
7505
7506
  /* VEX_LEN_0F3A21 */
7507
  {
7508
    { "%XEvinsertpsY",  { XM, Vex, EXd, Ib }, PREFIX_DATA },
7509
  },
7510
7511
  /* VEX_LEN_0F3A22 */
7512
  {
7513
    { "%XEvpinsrYK",  { XM, Vex, Edq, Ib }, PREFIX_DATA },
7514
  },
7515
7516
  /* VEX_LEN_0F3A30 */
7517
  {
7518
    { "kshiftr%BW", { MaskG, MaskR, Ib }, PREFIX_DATA },
7519
  },
7520
7521
  /* VEX_LEN_0F3A31 */
7522
  {
7523
    { "kshiftr%DQ", { MaskG, MaskR, Ib }, PREFIX_DATA },
7524
  },
7525
7526
  /* VEX_LEN_0F3A32 */
7527
  {
7528
    { "kshiftl%BW", { MaskG, MaskR, Ib }, PREFIX_DATA },
7529
  },
7530
7531
  /* VEX_LEN_0F3A33 */
7532
  {
7533
    { "kshiftl%DQ", { MaskG, MaskR, Ib }, PREFIX_DATA },
7534
  },
7535
7536
  /* VEX_LEN_0F3A38 */
7537
  {
7538
    { Bad_Opcode },
7539
    { VEX_W_TABLE (VEX_W_0F3A38_L_1) },
7540
  },
7541
7542
  /* VEX_LEN_0F3A39 */
7543
  {
7544
    { Bad_Opcode },
7545
    { VEX_W_TABLE (VEX_W_0F3A39_L_1) },
7546
  },
7547
7548
  /* VEX_LEN_0F3A41 */
7549
  {
7550
    { "vdppd",    { XM, Vex, EXx, Ib }, PREFIX_DATA },
7551
  },
7552
7553
  /* VEX_LEN_0F3A46 */
7554
  {
7555
    { Bad_Opcode },
7556
    { VEX_W_TABLE (VEX_W_0F3A46_L_1) },
7557
  },
7558
7559
  /* VEX_LEN_0F3A60 */
7560
  {
7561
    { "vpcmpestrm!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
7562
  },
7563
7564
  /* VEX_LEN_0F3A61 */
7565
  {
7566
    { "vpcmpestri!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
7567
  },
7568
7569
  /* VEX_LEN_0F3A62 */
7570
  {
7571
    { "vpcmpistrm", { XM, EXx, Ib }, PREFIX_DATA },
7572
  },
7573
7574
  /* VEX_LEN_0F3A63 */
7575
  {
7576
    { "vpcmpistri", { XM, EXx, Ib }, PREFIX_DATA },
7577
  },
7578
7579
  /* VEX_LEN_0F3ADE_W_0 */
7580
  {
7581
    { "vsm3rnds2", { XM, Vex, EXxmm, Ib }, PREFIX_DATA },
7582
  },
7583
7584
  /* VEX_LEN_0F3ADF */
7585
  {
7586
    { "vaeskeygenassist", { XM, EXx, Ib }, PREFIX_DATA },
7587
  },
7588
7589
  /* VEX_LEN_0F3AF0 */
7590
  {
7591
    { PREFIX_TABLE (PREFIX_VEX_0F3AF0_L_0) },
7592
  },
7593
7594
  /* VEX_LEN_MAP5_F8_X86_64 */
7595
  {
7596
    { VEX_W_TABLE (VEX_W_MAP5_F8_X86_64_L_0) },
7597
  },
7598
7599
  /* VEX_LEN_MAP5_F9_X86_64 */
7600
  {
7601
    { VEX_W_TABLE (VEX_W_MAP5_F9_X86_64_L_0) },
7602
  },
7603
7604
  /* VEX_LEN_MAP5_FD_X86_64 */
7605
  {
7606
    { VEX_W_TABLE (VEX_W_MAP5_FD_X86_64_L_0) },
7607
  },
7608
7609
  /* VEX_LEN_MAP7_F6 */
7610
  {
7611
    { VEX_W_TABLE (VEX_W_MAP7_F6_L_0) },
7612
  },
7613
7614
  /* VEX_LEN_MAP7_F8 */
7615
  {
7616
    { VEX_W_TABLE (VEX_W_MAP7_F8_L_0) },
7617
  },
7618
7619
  /* VEX_LEN_XOP_08_85 */
7620
  {
7621
    { VEX_W_TABLE (VEX_W_XOP_08_85_L_0) },
7622
  },
7623
7624
  /* VEX_LEN_XOP_08_86 */
7625
  {
7626
    { VEX_W_TABLE (VEX_W_XOP_08_86_L_0) },
7627
  },
7628
7629
  /* VEX_LEN_XOP_08_87 */
7630
  {
7631
    { VEX_W_TABLE (VEX_W_XOP_08_87_L_0) },
7632
  },
7633
7634
  /* VEX_LEN_XOP_08_8E */
7635
  {
7636
    { VEX_W_TABLE (VEX_W_XOP_08_8E_L_0) },
7637
  },
7638
7639
  /* VEX_LEN_XOP_08_8F */
7640
  {
7641
    { VEX_W_TABLE (VEX_W_XOP_08_8F_L_0) },
7642
  },
7643
7644
  /* VEX_LEN_XOP_08_95 */
7645
  {
7646
    { VEX_W_TABLE (VEX_W_XOP_08_95_L_0) },
7647
  },
7648
7649
  /* VEX_LEN_XOP_08_96 */
7650
  {
7651
    { VEX_W_TABLE (VEX_W_XOP_08_96_L_0) },
7652
  },
7653
7654
  /* VEX_LEN_XOP_08_97 */
7655
  {
7656
    { VEX_W_TABLE (VEX_W_XOP_08_97_L_0) },
7657
  },
7658
7659
  /* VEX_LEN_XOP_08_9E */
7660
  {
7661
    { VEX_W_TABLE (VEX_W_XOP_08_9E_L_0) },
7662
  },
7663
7664
  /* VEX_LEN_XOP_08_9F */
7665
  {
7666
    { VEX_W_TABLE (VEX_W_XOP_08_9F_L_0) },
7667
  },
7668
7669
  /* VEX_LEN_XOP_08_A3 */
7670
  {
7671
    { "vpperm",   { XM, Vex, EXx, XMVexI4 }, 0 },
7672
  },
7673
7674
  /* VEX_LEN_XOP_08_A6 */
7675
  {
7676
    { VEX_W_TABLE (VEX_W_XOP_08_A6_L_0) },
7677
  },
7678
7679
  /* VEX_LEN_XOP_08_B6 */
7680
  {
7681
    { VEX_W_TABLE (VEX_W_XOP_08_B6_L_0) },
7682
  },
7683
7684
  /* VEX_LEN_XOP_08_C0 */
7685
  {
7686
    { VEX_W_TABLE (VEX_W_XOP_08_C0_L_0) },
7687
  },
7688
7689
  /* VEX_LEN_XOP_08_C1 */
7690
  {
7691
    { VEX_W_TABLE (VEX_W_XOP_08_C1_L_0) },
7692
  },
7693
7694
  /* VEX_LEN_XOP_08_C2 */
7695
  {
7696
    { VEX_W_TABLE (VEX_W_XOP_08_C2_L_0) },
7697
  },
7698
7699
  /* VEX_LEN_XOP_08_C3 */
7700
  {
7701
    { VEX_W_TABLE (VEX_W_XOP_08_C3_L_0) },
7702
  },
7703
7704
  /* VEX_LEN_XOP_08_CC */
7705
  {
7706
    { VEX_W_TABLE (VEX_W_XOP_08_CC_L_0) },
7707
  },
7708
7709
  /* VEX_LEN_XOP_08_CD */
7710
  {
7711
    { VEX_W_TABLE (VEX_W_XOP_08_CD_L_0) },
7712
  },
7713
7714
  /* VEX_LEN_XOP_08_CE */
7715
  {
7716
    { VEX_W_TABLE (VEX_W_XOP_08_CE_L_0) },
7717
  },
7718
7719
  /* VEX_LEN_XOP_08_CF */
7720
  {
7721
    { VEX_W_TABLE (VEX_W_XOP_08_CF_L_0) },
7722
  },
7723
7724
  /* VEX_LEN_XOP_08_EC */
7725
  {
7726
    { VEX_W_TABLE (VEX_W_XOP_08_EC_L_0) },
7727
  },
7728
7729
  /* VEX_LEN_XOP_08_ED */
7730
  {
7731
    { VEX_W_TABLE (VEX_W_XOP_08_ED_L_0) },
7732
  },
7733
7734
  /* VEX_LEN_XOP_08_EE */
7735
  {
7736
    { VEX_W_TABLE (VEX_W_XOP_08_EE_L_0) },
7737
  },
7738
7739
  /* VEX_LEN_XOP_08_EF */
7740
  {
7741
    { VEX_W_TABLE (VEX_W_XOP_08_EF_L_0) },
7742
  },
7743
7744
  /* VEX_LEN_XOP_09_01 */
7745
  {
7746
    { REG_TABLE (REG_XOP_09_01_L_0) },
7747
  },
7748
7749
  /* VEX_LEN_XOP_09_02 */
7750
  {
7751
    { REG_TABLE (REG_XOP_09_02_L_0) },
7752
  },
7753
7754
  /* VEX_LEN_XOP_09_12 */
7755
  {
7756
    { REG_TABLE (REG_XOP_09_12_L_0) },
7757
  },
7758
7759
  /* VEX_LEN_XOP_09_82_W_0 */
7760
  {
7761
    { "vfrczss",  { XM, EXd }, 0 },
7762
  },
7763
7764
  /* VEX_LEN_XOP_09_83_W_0 */
7765
  {
7766
    { "vfrczsd",  { XM, EXq }, 0 },
7767
  },
7768
7769
  /* VEX_LEN_XOP_09_90 */
7770
  {
7771
    { "vprotb",   { XM, EXx, VexW }, 0 },
7772
  },
7773
7774
  /* VEX_LEN_XOP_09_91 */
7775
  {
7776
    { "vprotw",   { XM, EXx, VexW }, 0 },
7777
  },
7778
7779
  /* VEX_LEN_XOP_09_92 */
7780
  {
7781
    { "vprotd",   { XM, EXx, VexW }, 0 },
7782
  },
7783
7784
  /* VEX_LEN_XOP_09_93 */
7785
  {
7786
    { "vprotq",   { XM, EXx, VexW }, 0 },
7787
  },
7788
7789
  /* VEX_LEN_XOP_09_94 */
7790
  {
7791
    { "vpshlb",   { XM, EXx, VexW }, 0 },
7792
  },
7793
7794
  /* VEX_LEN_XOP_09_95 */
7795
  {
7796
    { "vpshlw",   { XM, EXx, VexW }, 0 },
7797
  },
7798
7799
  /* VEX_LEN_XOP_09_96 */
7800
  {
7801
    { "vpshld",   { XM, EXx, VexW }, 0 },
7802
  },
7803
7804
  /* VEX_LEN_XOP_09_97 */
7805
  {
7806
    { "vpshlq",   { XM, EXx, VexW }, 0 },
7807
  },
7808
7809
  /* VEX_LEN_XOP_09_98 */
7810
  {
7811
    { "vpshab",   { XM, EXx, VexW }, 0 },
7812
  },
7813
7814
  /* VEX_LEN_XOP_09_99 */
7815
  {
7816
    { "vpshaw",   { XM, EXx, VexW }, 0 },
7817
  },
7818
7819
  /* VEX_LEN_XOP_09_9A */
7820
  {
7821
    { "vpshad",   { XM, EXx, VexW }, 0 },
7822
  },
7823
7824
  /* VEX_LEN_XOP_09_9B */
7825
  {
7826
    { "vpshaq",   { XM, EXx, VexW }, 0 },
7827
  },
7828
7829
  /* VEX_LEN_XOP_09_C1 */
7830
  {
7831
    { VEX_W_TABLE (VEX_W_XOP_09_C1_L_0) },
7832
  },
7833
7834
  /* VEX_LEN_XOP_09_C2 */
7835
  {
7836
    { VEX_W_TABLE (VEX_W_XOP_09_C2_L_0) },
7837
  },
7838
7839
  /* VEX_LEN_XOP_09_C3 */
7840
  {
7841
    { VEX_W_TABLE (VEX_W_XOP_09_C3_L_0) },
7842
  },
7843
7844
  /* VEX_LEN_XOP_09_C6 */
7845
  {
7846
    { VEX_W_TABLE (VEX_W_XOP_09_C6_L_0) },
7847
  },
7848
7849
  /* VEX_LEN_XOP_09_C7 */
7850
  {
7851
    { VEX_W_TABLE (VEX_W_XOP_09_C7_L_0) },
7852
  },
7853
7854
  /* VEX_LEN_XOP_09_CB */
7855
  {
7856
    { VEX_W_TABLE (VEX_W_XOP_09_CB_L_0) },
7857
  },
7858
7859
  /* VEX_LEN_XOP_09_D1 */
7860
  {
7861
    { VEX_W_TABLE (VEX_W_XOP_09_D1_L_0) },
7862
  },
7863
7864
  /* VEX_LEN_XOP_09_D2 */
7865
  {
7866
    { VEX_W_TABLE (VEX_W_XOP_09_D2_L_0) },
7867
  },
7868
7869
  /* VEX_LEN_XOP_09_D3 */
7870
  {
7871
    { VEX_W_TABLE (VEX_W_XOP_09_D3_L_0) },
7872
  },
7873
7874
  /* VEX_LEN_XOP_09_D6 */
7875
  {
7876
    { VEX_W_TABLE (VEX_W_XOP_09_D6_L_0) },
7877
  },
7878
7879
  /* VEX_LEN_XOP_09_D7 */
7880
  {
7881
    { VEX_W_TABLE (VEX_W_XOP_09_D7_L_0) },
7882
  },
7883
7884
  /* VEX_LEN_XOP_09_DB */
7885
  {
7886
    { VEX_W_TABLE (VEX_W_XOP_09_DB_L_0) },
7887
  },
7888
7889
  /* VEX_LEN_XOP_09_E1 */
7890
  {
7891
    { VEX_W_TABLE (VEX_W_XOP_09_E1_L_0) },
7892
  },
7893
7894
  /* VEX_LEN_XOP_09_E2 */
7895
  {
7896
    { VEX_W_TABLE (VEX_W_XOP_09_E2_L_0) },
7897
  },
7898
7899
  /* VEX_LEN_XOP_09_E3 */
7900
  {
7901
    { VEX_W_TABLE (VEX_W_XOP_09_E3_L_0) },
7902
  },
7903
7904
  /* VEX_LEN_XOP_0A_12 */
7905
  {
7906
    { REG_TABLE (REG_XOP_0A_12_L_0) },
7907
  },
7908
};
7909
7910
#include "i386-dis-evex-len.h"
7911
7912
static const struct dis386 vex_w_table[][2] = {
7913
  {
7914
    /* VEX_W_0F41_L_1_M_1 */
7915
    { PREFIX_TABLE (PREFIX_VEX_0F41_L_1_W_0) },
7916
    { PREFIX_TABLE (PREFIX_VEX_0F41_L_1_W_1) },
7917
  },
7918
  {
7919
    /* VEX_W_0F42_L_1_M_1 */
7920
    { PREFIX_TABLE (PREFIX_VEX_0F42_L_1_W_0) },
7921
    { PREFIX_TABLE (PREFIX_VEX_0F42_L_1_W_1) },
7922
  },
7923
  {
7924
    /* VEX_W_0F44_L_0_M_1 */
7925
    { PREFIX_TABLE (PREFIX_VEX_0F44_L_0_W_0) },
7926
    { PREFIX_TABLE (PREFIX_VEX_0F44_L_0_W_1) },
7927
  },
7928
  {
7929
    /* VEX_W_0F45_L_1_M_1 */
7930
    { PREFIX_TABLE (PREFIX_VEX_0F45_L_1_W_0) },
7931
    { PREFIX_TABLE (PREFIX_VEX_0F45_L_1_W_1) },
7932
  },
7933
  {
7934
    /* VEX_W_0F46_L_1_M_1 */
7935
    { PREFIX_TABLE (PREFIX_VEX_0F46_L_1_W_0) },
7936
    { PREFIX_TABLE (PREFIX_VEX_0F46_L_1_W_1) },
7937
  },
7938
  {
7939
    /* VEX_W_0F47_L_1_M_1 */
7940
    { PREFIX_TABLE (PREFIX_VEX_0F47_L_1_W_0) },
7941
    { PREFIX_TABLE (PREFIX_VEX_0F47_L_1_W_1) },
7942
  },
7943
  {
7944
    /* VEX_W_0F4A_L_1_M_1 */
7945
    { PREFIX_TABLE (PREFIX_VEX_0F4A_L_1_W_0) },
7946
    { PREFIX_TABLE (PREFIX_VEX_0F4A_L_1_W_1) },
7947
  },
7948
  {
7949
    /* VEX_W_0F4B_L_1_M_1 */
7950
    { PREFIX_TABLE (PREFIX_VEX_0F4B_L_1_W_0) },
7951
    { PREFIX_TABLE (PREFIX_VEX_0F4B_L_1_W_1) },
7952
  },
7953
  {
7954
    /* VEX_W_0F90_L_0 */
7955
    { PREFIX_TABLE (PREFIX_VEX_0F90_L_0_W_0) },
7956
    { PREFIX_TABLE (PREFIX_VEX_0F90_L_0_W_1) },
7957
  },
7958
  {
7959
    /* VEX_W_0F91_L_0_M_0 */
7960
    { PREFIX_TABLE (PREFIX_VEX_0F91_L_0_W_0) },
7961
    { PREFIX_TABLE (PREFIX_VEX_0F91_L_0_W_1) },
7962
  },
7963
  {
7964
    /* VEX_W_0F92_L_0_M_1 */
7965
    { PREFIX_TABLE (PREFIX_VEX_0F92_L_0_W_0) },
7966
    { PREFIX_TABLE (PREFIX_VEX_0F92_L_0_W_1) },
7967
  },
7968
  {
7969
    /* VEX_W_0F93_L_0_M_1 */
7970
    { PREFIX_TABLE (PREFIX_VEX_0F93_L_0_W_0) },
7971
    { PREFIX_TABLE (PREFIX_VEX_0F93_L_0_W_1) },
7972
  },
7973
  {
7974
    /* VEX_W_0F98_L_0_M_1 */
7975
    { PREFIX_TABLE (PREFIX_VEX_0F98_L_0_W_0) },
7976
    { PREFIX_TABLE (PREFIX_VEX_0F98_L_0_W_1) },
7977
  },
7978
  {
7979
    /* VEX_W_0F99_L_0_M_1 */
7980
    { PREFIX_TABLE (PREFIX_VEX_0F99_L_0_W_0) },
7981
    { PREFIX_TABLE (PREFIX_VEX_0F99_L_0_W_1) },
7982
  },
7983
  {
7984
    /* VEX_W_0F380C  */
7985
    { "%XEvpermilps", { XM, Vex, EXx }, PREFIX_DATA },
7986
  },
7987
  {
7988
    /* VEX_W_0F380D  */
7989
    { "vpermilpd",  { XM, Vex, EXx }, PREFIX_DATA },
7990
  },
7991
  {
7992
    /* VEX_W_0F380E  */
7993
    { "vtestps",  { XM, EXx }, PREFIX_DATA },
7994
  },
7995
  {
7996
    /* VEX_W_0F380F  */
7997
    { "vtestpd",  { XM, EXx }, PREFIX_DATA },
7998
  },
7999
  {
8000
    /* VEX_W_0F3813 */
8001
    { "vcvtph2ps", { XM, EXxmmq }, PREFIX_DATA },
8002
  },
8003
  {
8004
    /* VEX_W_0F3816_L_1  */
8005
    { "vpermps",  { XM, Vex, EXx }, PREFIX_DATA },
8006
  },
8007
  {
8008
    /* VEX_W_0F3818 */
8009
    { "%XEvbroadcastss",  { XM, EXd }, PREFIX_DATA },
8010
  },
8011
  {
8012
    /* VEX_W_0F3819_L_1 */
8013
    { "vbroadcastsd", { XM, EXq }, PREFIX_DATA },
8014
  },
8015
  {
8016
    /* VEX_W_0F381A_L_1 */
8017
    { "vbroadcastf128", { XM, Mxmm }, PREFIX_DATA },
8018
  },
8019
  {
8020
    /* VEX_W_0F382C */
8021
    { "vmaskmovps", { XM, Vex, Mx }, PREFIX_DATA },
8022
  },
8023
  {
8024
    /* VEX_W_0F382D */
8025
    { "vmaskmovpd", { XM, Vex, Mx }, PREFIX_DATA },
8026
  },
8027
  {
8028
    /* VEX_W_0F382E */
8029
    { "vmaskmovps", { Mx, Vex, XM }, PREFIX_DATA },
8030
  },
8031
  {
8032
    /* VEX_W_0F382F */
8033
    { "vmaskmovpd", { Mx, Vex, XM }, PREFIX_DATA },
8034
  },
8035
  {
8036
    /* VEX_W_0F3836  */
8037
    { "vpermd",   { XM, Vex, EXx }, PREFIX_DATA },
8038
  },
8039
  {
8040
    /* VEX_W_0F3846 */
8041
    { "vpsravd",  { XM, Vex, EXx }, PREFIX_DATA },
8042
  },
8043
  {
8044
    /* VEX_W_0F3848_X86_64_L_0 */
8045
    { PREFIX_TABLE (PREFIX_VEX_0F3848_X86_64_L_0_W_0) },
8046
  },
8047
  {
8048
    /* VEX_W_0F3849_X86_64_L_0 */
8049
    { MOD_TABLE (MOD_VEX_0F3849_X86_64_L_0_W_0) },
8050
  },
8051
  {
8052
    /* VEX_W_0F384A_X86_64 */
8053
    { VEX_LEN_TABLE (VEX_LEN_0F384A_X86_64_W_0) },
8054
  },
8055
  {
8056
    /* VEX_W_0F384B_X86_64_L_0 */
8057
    { PREFIX_TABLE (PREFIX_VEX_0F384B_X86_64_L_0_W_0) },
8058
  },
8059
  {
8060
    /* VEX_W_0F3850 */
8061
    { PREFIX_TABLE (PREFIX_VEX_0F3850_W_0) },
8062
  },
8063
  {
8064
    /* VEX_W_0F3851 */
8065
    { PREFIX_TABLE (PREFIX_VEX_0F3851_W_0) },
8066
  },
8067
  {
8068
    /* VEX_W_0F3852 */
8069
    { "%XVvpdpwssd",  { XM, Vex, EXx }, PREFIX_DATA },
8070
  },
8071
  {
8072
    /* VEX_W_0F3853 */
8073
    { "%XVvpdpwssds", { XM, Vex, EXx }, PREFIX_DATA },
8074
  },
8075
  {
8076
    /* VEX_W_0F3858 */
8077
    { "%XEvpbroadcastd", { XM, EXd }, PREFIX_DATA },
8078
  },
8079
  {
8080
    /* VEX_W_0F3859 */
8081
    { "vpbroadcastq", { XM, EXq }, PREFIX_DATA },
8082
  },
8083
  {
8084
    /* VEX_W_0F385A_L_0 */
8085
    { "vbroadcasti128", { XM, Mxmm }, PREFIX_DATA },
8086
  },
8087
  {
8088
    /* VEX_W_0F385C_X86_64_L_0 */
8089
    { PREFIX_TABLE (PREFIX_VEX_0F385C_X86_64_L_0_W_0) },
8090
  },
8091
  {
8092
    /* VEX_W_0F385E_X86_64_L_0 */
8093
    { PREFIX_TABLE (PREFIX_VEX_0F385E_X86_64_L_0_W_0) },
8094
  },
8095
  {
8096
    /* VEX_W_0F385F_X86_64_L_0 */
8097
    { PREFIX_TABLE (PREFIX_VEX_0F385F_X86_64_L_0_W_0) },
8098
  },
8099
  {
8100
    /* VEX_W_0F386B_X86_64_L_0 */
8101
    { PREFIX_TABLE (PREFIX_VEX_0F386B_X86_64_L_0_W_0) },
8102
  },
8103
  {
8104
    /* VEX_W_0F386C_X86_64_L_0 */
8105
    { PREFIX_TABLE (PREFIX_VEX_0F386C_X86_64_L_0_W_0) },
8106
  },
8107
  {
8108
    /* VEX_W_0F386E_X86_64_L_0 */
8109
    { PREFIX_TABLE (PREFIX_VEX_0F386E_X86_64_L_0_W_0) },
8110
  },
8111
  {
8112
    /* VEX_W_0F386F_X86_64_L_0 */
8113
    { PREFIX_TABLE (PREFIX_VEX_0F386F_X86_64_L_0_W_0) },
8114
  },
8115
  {
8116
    /* VEX_W_0F3872_P_1 */
8117
    { "%XVvcvtneps2bf16%XY", { XMM, EXx }, 0 },
8118
  },
8119
  {
8120
    /* VEX_W_0F3878 */
8121
    { "%XEvpbroadcastb",  { XM, EXb }, PREFIX_DATA },
8122
  },
8123
  {
8124
    /* VEX_W_0F3879 */
8125
    { "%XEvpbroadcastw",  { XM, EXw }, PREFIX_DATA },
8126
  },
8127
  {
8128
    /* VEX_W_0F38B0 */
8129
    { PREFIX_TABLE (PREFIX_VEX_0F38B0_W_0) },
8130
  },
8131
  {
8132
    /* VEX_W_0F38B1 */
8133
    { PREFIX_TABLE (PREFIX_VEX_0F38B1_W_0) },
8134
  },
8135
  {
8136
    /* VEX_W_0F38B4 */
8137
    { Bad_Opcode },
8138
    { "%XVvpmadd52luq", { XM, Vex, EXx }, PREFIX_DATA },
8139
  },
8140
  {
8141
    /* VEX_W_0F38B5 */
8142
    { Bad_Opcode },
8143
    { "%XVvpmadd52huq", { XM, Vex, EXx }, PREFIX_DATA },
8144
  },
8145
  {
8146
    /* VEX_W_0F38CB_P_3 */
8147
    { VEX_LEN_TABLE (VEX_LEN_0F38CB_P_3_W_0) },
8148
  },
8149
  {
8150
    /* VEX_W_0F38CC_P_3 */
8151
    { VEX_LEN_TABLE (VEX_LEN_0F38CC_P_3_W_0) },
8152
  },
8153
  {
8154
    /* VEX_W_0F38CD_P_3 */
8155
    { VEX_LEN_TABLE (VEX_LEN_0F38CD_P_3_W_0) },
8156
  },
8157
  {
8158
    /* VEX_W_0F38CF */
8159
    { "%XEvgf2p8mulb", { XM, Vex, EXx }, PREFIX_DATA },
8160
  },
8161
  {
8162
    /* VEX_W_0F38D2 */
8163
    { PREFIX_TABLE (PREFIX_VEX_0F38D2_W_0) },
8164
  },
8165
  {
8166
    /* VEX_W_0F38D3 */
8167
    { PREFIX_TABLE (PREFIX_VEX_0F38D3_W_0) },
8168
  },
8169
  {
8170
    /* VEX_W_0F38DA */
8171
    { PREFIX_TABLE (PREFIX_VEX_0F38DA_W_0) },
8172
  },
8173
  {
8174
    /* VEX_W_0F3A00_L_1 */
8175
    { Bad_Opcode },
8176
    { "%XEvpermq",    { XM, EXx, Ib }, PREFIX_DATA },
8177
  },
8178
  {
8179
    /* VEX_W_0F3A01_L_1 */
8180
    { Bad_Opcode },
8181
    { "%XEvpermpd", { XM, EXx, Ib }, PREFIX_DATA },
8182
  },
8183
  {
8184
    /* VEX_W_0F3A02 */
8185
    { "vpblendd", { XM, Vex, EXx, Ib }, PREFIX_DATA },
8186
  },
8187
  {
8188
    /* VEX_W_0F3A04 */
8189
    { "%XEvpermilps", { XM, EXx, Ib }, PREFIX_DATA },
8190
  },
8191
  {
8192
    /* VEX_W_0F3A05 */
8193
    { "vpermilpd",  { XM, EXx, Ib }, PREFIX_DATA },
8194
  },
8195
  {
8196
    /* VEX_W_0F3A06_L_1 */
8197
    { "vperm2f128", { XM, Vex, EXx, Ib }, PREFIX_DATA },
8198
  },
8199
  {
8200
    /* VEX_W_0F3A18_L_1 */
8201
    { "vinsertf128",  { XM, Vex, EXxmm, Ib }, PREFIX_DATA },
8202
  },
8203
  {
8204
    /* VEX_W_0F3A19_L_1 */
8205
    { "vextractf128", { EXxmm, XM, Ib }, PREFIX_DATA },
8206
  },
8207
  {
8208
    /* VEX_W_0F3A1D */
8209
    { "%XEvcvtps2ph", { EXxmmq, XM, EXxEVexS, Ib }, PREFIX_DATA },
8210
  },
8211
  {
8212
    /* VEX_W_0F3A38_L_1 */
8213
    { "vinserti128",  { XM, Vex, EXxmm, Ib }, PREFIX_DATA },
8214
  },
8215
  {
8216
    /* VEX_W_0F3A39_L_1 */
8217
    { "vextracti128", { EXxmm, XM, Ib }, PREFIX_DATA },
8218
  },
8219
  {
8220
    /* VEX_W_0F3A46_L_1 */
8221
    { "vperm2i128", { XM, Vex, EXx, Ib }, PREFIX_DATA },
8222
  },
8223
  {
8224
    /* VEX_W_0F3A4A */
8225
    { "vblendvps",  { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
8226
  },
8227
  {
8228
    /* VEX_W_0F3A4B */
8229
    { "vblendvpd",  { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
8230
  },
8231
  {
8232
    /* VEX_W_0F3A4C */
8233
    { "vpblendvb",  { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
8234
  },
8235
  {
8236
    /* VEX_W_0F3ACE */
8237
    { Bad_Opcode },
8238
    { "%XEvgf2p8affineqb", { XM, Vex, EXx, Ib }, PREFIX_DATA },
8239
  },
8240
  {
8241
    /* VEX_W_0F3ACF */
8242
    { Bad_Opcode },
8243
    { "%XEvgf2p8affineinvqb",  { XM, Vex, EXx, Ib }, PREFIX_DATA },
8244
  },
8245
  {
8246
    /* VEX_W_0F3ADE */
8247
    { VEX_LEN_TABLE (VEX_LEN_0F3ADE_W_0) },
8248
  },
8249
  {
8250
    /* VEX_W_MAP5_F8_X86_64 */
8251
    { PREFIX_TABLE (PREFIX_VEX_MAP5_F8_X86_64_L_0_W_0) },
8252
  },
8253
  {
8254
    /* VEX_W_MAP5_F9_X86_64 */
8255
    { PREFIX_TABLE (PREFIX_VEX_MAP5_F9_X86_64_L_0_W_0) },
8256
  },
8257
  {
8258
    /* VEX_W_MAP5_FD_X86_64 */
8259
    { PREFIX_TABLE (PREFIX_VEX_MAP5_FD_X86_64_L_0_W_0) },
8260
  },
8261
  {
8262
    /* VEX_W_MAP7_F6_L_0 */
8263
    { REG_TABLE (REG_VEX_MAP7_F6_L_0_W_0) },
8264
  },
8265
  {
8266
    /* VEX_W_MAP7_F8_L_0 */
8267
    { REG_TABLE (REG_VEX_MAP7_F8_L_0_W_0) },
8268
  },
8269
  /* VEX_W_XOP_08_85_L_0 */
8270
  {
8271
    { "vpmacssww",  { XM, Vex, EXx, XMVexI4 }, 0 },
8272
  },
8273
  /* VEX_W_XOP_08_86_L_0 */
8274
  {
8275
    { "vpmacsswd",  { XM, Vex, EXx, XMVexI4 }, 0 },
8276
  },
8277
  /* VEX_W_XOP_08_87_L_0 */
8278
  {
8279
    { "vpmacssdql",   { XM, Vex, EXx, XMVexI4 }, 0 },
8280
  },
8281
  /* VEX_W_XOP_08_8E_L_0 */
8282
  {
8283
    { "vpmacssdd",  { XM, Vex, EXx, XMVexI4 }, 0 },
8284
  },
8285
  /* VEX_W_XOP_08_8F_L_0 */
8286
  {
8287
    { "vpmacssdqh",   { XM, Vex, EXx, XMVexI4 }, 0 },
8288
  },
8289
  /* VEX_W_XOP_08_95_L_0 */
8290
  {
8291
    { "vpmacsww",   { XM, Vex, EXx, XMVexI4 }, 0 },
8292
  },
8293
  /* VEX_W_XOP_08_96_L_0 */
8294
  {
8295
    { "vpmacswd",   { XM, Vex, EXx, XMVexI4 }, 0 },
8296
  },
8297
  /* VEX_W_XOP_08_97_L_0 */
8298
  {
8299
    { "vpmacsdql",  { XM, Vex, EXx, XMVexI4 }, 0 },
8300
  },
8301
  /* VEX_W_XOP_08_9E_L_0 */
8302
  {
8303
    { "vpmacsdd",   { XM, Vex, EXx, XMVexI4 }, 0 },
8304
  },
8305
  /* VEX_W_XOP_08_9F_L_0 */
8306
  {
8307
    { "vpmacsdqh",  { XM, Vex, EXx, XMVexI4 }, 0 },
8308
  },
8309
  /* VEX_W_XOP_08_A6_L_0 */
8310
  {
8311
    { "vpmadcsswd",   { XM, Vex, EXx, XMVexI4 }, 0 },
8312
  },
8313
  /* VEX_W_XOP_08_B6_L_0 */
8314
  {
8315
    { "vpmadcswd",  { XM, Vex, EXx, XMVexI4 }, 0 },
8316
  },
8317
  /* VEX_W_XOP_08_C0_L_0 */
8318
  {
8319
    { "vprotb",   { XM, EXx, Ib }, 0 },
8320
  },
8321
  /* VEX_W_XOP_08_C1_L_0 */
8322
  {
8323
    { "vprotw",   { XM, EXx, Ib }, 0 },
8324
  },
8325
  /* VEX_W_XOP_08_C2_L_0 */
8326
  {
8327
    { "vprotd",   { XM, EXx, Ib }, 0 },
8328
  },
8329
  /* VEX_W_XOP_08_C3_L_0 */
8330
  {
8331
    { "vprotq",   { XM, EXx, Ib }, 0 },
8332
  },
8333
  /* VEX_W_XOP_08_CC_L_0 */
8334
  {
8335
     { "vpcomb",  { XM, Vex, EXx, VPCOM }, 0 },
8336
  },
8337
  /* VEX_W_XOP_08_CD_L_0 */
8338
  {
8339
     { "vpcomw",  { XM, Vex, EXx, VPCOM }, 0 },
8340
  },
8341
  /* VEX_W_XOP_08_CE_L_0 */
8342
  {
8343
     { "vpcomd",  { XM, Vex, EXx, VPCOM }, 0 },
8344
  },
8345
  /* VEX_W_XOP_08_CF_L_0 */
8346
  {
8347
     { "vpcomq",  { XM, Vex, EXx, VPCOM }, 0 },
8348
  },
8349
  /* VEX_W_XOP_08_EC_L_0 */
8350
  {
8351
     { "vpcomub", { XM, Vex, EXx, VPCOM }, 0 },
8352
  },
8353
  /* VEX_W_XOP_08_ED_L_0 */
8354
  {
8355
     { "vpcomuw", { XM, Vex, EXx, VPCOM }, 0 },
8356
  },
8357
  /* VEX_W_XOP_08_EE_L_0 */
8358
  {
8359
     { "vpcomud", { XM, Vex, EXx, VPCOM }, 0 },
8360
  },
8361
  /* VEX_W_XOP_08_EF_L_0 */
8362
  {
8363
     { "vpcomuq", { XM, Vex, EXx, VPCOM }, 0 },
8364
  },
8365
  /* VEX_W_XOP_09_80 */
8366
  {
8367
    { "vfrczps",  { XM, EXx }, 0 },
8368
  },
8369
  /* VEX_W_XOP_09_81 */
8370
  {
8371
    { "vfrczpd",  { XM, EXx }, 0 },
8372
  },
8373
  /* VEX_W_XOP_09_82 */
8374
  {
8375
    { VEX_LEN_TABLE (VEX_LEN_XOP_09_82_W_0) },
8376
  },
8377
  /* VEX_W_XOP_09_83 */
8378
  {
8379
    { VEX_LEN_TABLE (VEX_LEN_XOP_09_83_W_0) },
8380
  },
8381
  /* VEX_W_XOP_09_C1_L_0 */
8382
  {
8383
    { "vphaddbw", { XM, EXxmm }, 0 },
8384
  },
8385
  /* VEX_W_XOP_09_C2_L_0 */
8386
  {
8387
    { "vphaddbd", { XM, EXxmm }, 0 },
8388
  },
8389
  /* VEX_W_XOP_09_C3_L_0 */
8390
  {
8391
    { "vphaddbq", { XM, EXxmm }, 0 },
8392
  },
8393
  /* VEX_W_XOP_09_C6_L_0 */
8394
  {
8395
    { "vphaddwd", { XM, EXxmm }, 0 },
8396
  },
8397
  /* VEX_W_XOP_09_C7_L_0 */
8398
  {
8399
    { "vphaddwq", { XM, EXxmm }, 0 },
8400
  },
8401
  /* VEX_W_XOP_09_CB_L_0 */
8402
  {
8403
    { "vphadddq", { XM, EXxmm }, 0 },
8404
  },
8405
  /* VEX_W_XOP_09_D1_L_0 */
8406
  {
8407
    { "vphaddubw",  { XM, EXxmm }, 0 },
8408
  },
8409
  /* VEX_W_XOP_09_D2_L_0 */
8410
  {
8411
    { "vphaddubd",  { XM, EXxmm }, 0 },
8412
  },
8413
  /* VEX_W_XOP_09_D3_L_0 */
8414
  {
8415
    { "vphaddubq",  { XM, EXxmm }, 0 },
8416
  },
8417
  /* VEX_W_XOP_09_D6_L_0 */
8418
  {
8419
    { "vphadduwd",  { XM, EXxmm }, 0 },
8420
  },
8421
  /* VEX_W_XOP_09_D7_L_0 */
8422
  {
8423
    { "vphadduwq",  { XM, EXxmm }, 0 },
8424
  },
8425
  /* VEX_W_XOP_09_DB_L_0 */
8426
  {
8427
    { "vphaddudq",  { XM, EXxmm }, 0 },
8428
  },
8429
  /* VEX_W_XOP_09_E1_L_0 */
8430
  {
8431
    { "vphsubbw", { XM, EXxmm }, 0 },
8432
  },
8433
  /* VEX_W_XOP_09_E2_L_0 */
8434
  {
8435
    { "vphsubwd", { XM, EXxmm }, 0 },
8436
  },
8437
  /* VEX_W_XOP_09_E3_L_0 */
8438
  {
8439
    { "vphsubdq", { XM, EXxmm }, 0 },
8440
  },
8441
8442
#include "i386-dis-evex-w.h"
8443
};
8444
8445
static const struct dis386 mod_table[][2] = {
8446
  {
8447
    /* MOD_62_32BIT */
8448
    { "bound{S|}",  { Gv, Ma }, 0 },
8449
    { EVEX_TABLE () },
8450
  },
8451
  {
8452
    /* MOD_C4_32BIT */
8453
    { "lesS",   { Gv, Mp }, 0 },
8454
    { VEX_C4_TABLE () },
8455
  },
8456
  {
8457
    /* MOD_C5_32BIT */
8458
    { "ldsS",   { Gv, Mp }, 0 },
8459
    { VEX_C5_TABLE () },
8460
  },
8461
  {
8462
    /* MOD_0F01_REG_0 */
8463
    { X86_64_TABLE (X86_64_0F01_REG_0) },
8464
    { RM_TABLE (RM_0F01_REG_0) },
8465
  },
8466
  {
8467
    /* MOD_0F01_REG_1 */
8468
    { X86_64_TABLE (X86_64_0F01_REG_1) },
8469
    { RM_TABLE (RM_0F01_REG_1) },
8470
  },
8471
  {
8472
    /* MOD_0F01_REG_2 */
8473
    { X86_64_TABLE (X86_64_0F01_REG_2) },
8474
    { RM_TABLE (RM_0F01_REG_2) },
8475
  },
8476
  {
8477
    /* MOD_0F01_REG_3 */
8478
    { X86_64_TABLE (X86_64_0F01_REG_3) },
8479
    { RM_TABLE (RM_0F01_REG_3) },
8480
  },
8481
  {
8482
    /* MOD_0F01_REG_5 */
8483
    { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0) },
8484
    { RM_TABLE (RM_0F01_REG_5_MOD_3) },
8485
  },
8486
  {
8487
    /* MOD_0F01_REG_7 */
8488
    { "invlpg",   { Mb }, 0 },
8489
    { RM_TABLE (RM_0F01_REG_7_MOD_3) },
8490
  },
8491
  {
8492
    /* MOD_0F12_PREFIX_0 */
8493
    { "%XEVmovlpYX",  { XM, Vex, EXq }, 0 },
8494
    { "%XEVmovhlpY%XS", { XM, Vex, EXq }, 0 },
8495
  },
8496
  {
8497
    /* MOD_0F16_PREFIX_0 */
8498
    { "%XEVmovhpYX",  { XM, Vex, EXq }, 0 },
8499
    { "%XEVmovlhpY%XS", { XM, Vex, EXq }, 0 },
8500
  },
8501
  {
8502
    /* MOD_0F18_REG_0 */
8503
    { "prefetchnta",  { Mb }, 0 },
8504
    { "nopQ",   { Ev }, 0 },
8505
  },
8506
  {
8507
    /* MOD_0F18_REG_1 */
8508
    { "prefetcht0", { Mb }, 0 },
8509
    { "nopQ",   { Ev }, 0 },
8510
  },
8511
  {
8512
    /* MOD_0F18_REG_2 */
8513
    { "prefetcht1", { Mb }, 0 },
8514
    { "nopQ",   { Ev }, 0 },
8515
  },
8516
  {
8517
    /* MOD_0F18_REG_3 */
8518
    { "prefetcht2", { Mb }, 0 },
8519
    { "nopQ",   { Ev }, 0 },
8520
  },
8521
  {
8522
    /* MOD_0F18_REG_4 */
8523
    { "prefetchrst2", { Mb }, 0 },
8524
    { "nopQ",   { Ev }, 0 },
8525
  },
8526
  {
8527
    /* MOD_0F18_REG_6 */
8528
    { X86_64_TABLE (X86_64_0F18_REG_6_MOD_0) },
8529
    { "nopQ",   { Ev }, 0 },
8530
  },
8531
  {
8532
    /* MOD_0F18_REG_7 */
8533
    { X86_64_TABLE (X86_64_0F18_REG_7_MOD_0) },
8534
    { "nopQ",   { Ev }, 0 },
8535
  },
8536
  {
8537
    /* MOD_0F1A_PREFIX_0 */
8538
    { "bndldx",   { Gbnd, Mv_bnd }, 0 },
8539
    { "nopQ",   { Ev }, 0 },
8540
  },
8541
  {
8542
    /* MOD_0F1B_PREFIX_0 */
8543
    { "bndstx",   { Mv_bnd, Gbnd }, 0 },
8544
    { "nopQ",   { Ev }, 0 },
8545
  },
8546
  {
8547
    /* MOD_0F1B_PREFIX_1 */
8548
    { "bndmk",    { Gbnd, Mv_bnd }, 0 },
8549
    { "nopQ",   { Ev }, PREFIX_IGNORED },
8550
  },
8551
  {
8552
    /* MOD_0F1C_PREFIX_0 */
8553
    { REG_TABLE (REG_0F1C_P_0_MOD_0) },
8554
    { "nopQ",   { Ev }, 0 },
8555
  },
8556
  {
8557
    /* MOD_0F1E_PREFIX_1 */
8558
    { "nopQ",   { Ev }, PREFIX_IGNORED },
8559
    { REG_TABLE (REG_0F1E_P_1_MOD_3) },
8560
  },
8561
  {
8562
    /* MOD_0FAE_REG_0 */
8563
    { "fxsave",   { FXSAVE }, 0 },
8564
    { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3) },
8565
  },
8566
  {
8567
    /* MOD_0FAE_REG_1 */
8568
    { "fxrstor",  { FXSAVE }, 0 },
8569
    { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3) },
8570
  },
8571
  {
8572
    /* MOD_0FAE_REG_2 */
8573
    { "ldmxcsr",  { Md }, 0 },
8574
    { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3) },
8575
  },
8576
  {
8577
    /* MOD_0FAE_REG_3 */
8578
    { "stmxcsr",  { Md }, 0 },
8579
    { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3) },
8580
  },
8581
  {
8582
    /* MOD_0FAE_REG_4 */
8583
    { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0) },
8584
    { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3) },
8585
  },
8586
  {
8587
    /* MOD_0FAE_REG_5 */
8588
    { "xrstor",   { FXSAVE }, PREFIX_OPCODE | PREFIX_REX2_ILLEGAL },
8589
    { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3) },
8590
  },
8591
  {
8592
    /* MOD_0FAE_REG_6 */
8593
    { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0) },
8594
    { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3) },
8595
  },
8596
  {
8597
    /* MOD_0FAE_REG_7 */
8598
    { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0) },
8599
    { RM_TABLE (RM_0FAE_REG_7_MOD_3) },
8600
  },
8601
  {
8602
    /* MOD_0FC7_REG_6 */
8603
    { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0) },
8604
    { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3) }
8605
  },
8606
  {
8607
    /* MOD_0FC7_REG_7 */
8608
    { "vmptrst",  { Mq }, 0 },
8609
    { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3) }
8610
  },
8611
  {
8612
    /* MOD_0F38DC_PREFIX_1 */
8613
    { "aesenc128kl",    { XM, M }, 0 },
8614
    { "loadiwkey",      { XM, EXx }, 0 },
8615
  },
8616
  /* MOD_0F38F8 */
8617
  {
8618
    { PREFIX_TABLE (PREFIX_0F38F8_M_0) },
8619
    { X86_64_TABLE (X86_64_0F38F8_M_1) },
8620
  },
8621
  {
8622
    /* MOD_VEX_0F3849_X86_64_L_0_W_0 */
8623
    { PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_0) },
8624
    { PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_1) },
8625
  },
8626
8627
#include "i386-dis-evex-mod.h"
8628
};
8629
8630
static const struct dis386 rm_table[][8] = {
8631
  {
8632
    /* RM_C6_REG_7 */
8633
    { "xabort",   { Skip_MODRM, Ib }, 0 },
8634
  },
8635
  {
8636
    /* RM_C7_REG_7 */
8637
    { "xbeginT",  { Skip_MODRM, Jdqw }, 0 },
8638
  },
8639
  {
8640
    /* RM_0F01_REG_0 */
8641
    { "enclv",    { Skip_MODRM }, 0 },
8642
    { "vmcall",   { Skip_MODRM }, 0 },
8643
    { "vmlaunch", { Skip_MODRM }, 0 },
8644
    { "vmresume", { Skip_MODRM }, 0 },
8645
    { "vmxoff",   { Skip_MODRM }, 0 },
8646
    { "pconfig",  { Skip_MODRM }, 0 },
8647
    { PREFIX_TABLE (PREFIX_0F01_REG_0_MOD_3_RM_6) },
8648
    { PREFIX_TABLE (PREFIX_0F01_REG_0_MOD_3_RM_7) },
8649
  },
8650
  {
8651
    /* RM_0F01_REG_1 */
8652
    { "monitor",  { { OP_Monitor, 0 } }, 0 },
8653
    { "mwait",    { { OP_Mwait, 0 } }, 0 },
8654
    { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_2) },
8655
    { "stac",   { Skip_MODRM }, 0 },
8656
    { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_4) },
8657
    { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_5) },
8658
    { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_6) },
8659
    { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_7) },
8660
  },
8661
  {
8662
    /* RM_0F01_REG_2 */
8663
    { "xgetbv",   { Skip_MODRM }, 0 },
8664
    { "xsetbv",   { Skip_MODRM }, 0 },
8665
    { Bad_Opcode },
8666
    { Bad_Opcode },
8667
    { "vmfunc",   { Skip_MODRM }, 0 },
8668
    { "xend",   { Skip_MODRM }, 0 },
8669
    { "xtest",    { Skip_MODRM }, 0 },
8670
    { "enclu",    { Skip_MODRM }, 0 },
8671
  },
8672
  {
8673
    /* RM_0F01_REG_3 */
8674
    { "vmrun",    { Skip_MODRM }, 0 },
8675
    { PREFIX_TABLE (PREFIX_0F01_REG_3_RM_1) },
8676
    { "vmload",   { Skip_MODRM }, 0 },
8677
    { "vmsave",   { Skip_MODRM }, 0 },
8678
    { "stgi",   { Skip_MODRM }, 0 },
8679
    { "clgi",   { Skip_MODRM }, 0 },
8680
    { "skinit",   { Skip_MODRM }, 0 },
8681
    { "invlpga",  { Skip_MODRM }, 0 },
8682
  },
8683
  {
8684
    /* RM_0F01_REG_5_MOD_3 */
8685
    { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0) },
8686
    { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_1) },
8687
    { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2) },
8688
    { Bad_Opcode },
8689
    { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_4) },
8690
    { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_5) },
8691
    { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_6) },
8692
    { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_7) },
8693
  },
8694
  {
8695
    /* RM_0F01_REG_7_MOD_3 */
8696
    { "swapgs",   { Skip_MODRM }, 0  },
8697
    { "rdtscp",   { Skip_MODRM }, 0  },
8698
    { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2) },
8699
    { "mwaitx",   { { OP_Mwait, eBX_reg } }, PREFIX_OPCODE },
8700
    { "clzero",   { Skip_MODRM }, 0  },
8701
    { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_5) },
8702
    { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_6) },
8703
    { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_7) },
8704
  },
8705
  {
8706
    /* RM_0F1E_P_1_MOD_3_REG_7 */
8707
    { "nopQ",   { Ev }, PREFIX_IGNORED },
8708
    { "nopQ",   { Ev }, PREFIX_IGNORED },
8709
    { "endbr64",  { Skip_MODRM }, 0 },
8710
    { "endbr32",  { Skip_MODRM }, 0 },
8711
    { "nopQ",   { Ev }, PREFIX_IGNORED },
8712
    { "nopQ",   { Ev }, PREFIX_IGNORED },
8713
    { "nopQ",   { Ev }, PREFIX_IGNORED },
8714
    { "nopQ",   { Ev }, PREFIX_IGNORED },
8715
  },
8716
  {
8717
    /* RM_0FAE_REG_6_MOD_3 */
8718
    { "mfence",   { Skip_MODRM }, 0 },
8719
  },
8720
  {
8721
    /* RM_0FAE_REG_7_MOD_3 */
8722
    { "sfence",   { Skip_MODRM }, 0 },
8723
  },
8724
  {
8725
    /* RM_0F3A0F_P_1_R_0 */
8726
    { "hreset",   { Skip_MODRM, Ib }, 0 },
8727
  },
8728
  {
8729
    /* RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0_R_0 */
8730
    { "tilerelease",  { Skip_MODRM }, 0 },
8731
  },
8732
  {
8733
    /* RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_3 */
8734
    { "tilezero", { TMM, Skip_MODRM }, 0 },
8735
  },
8736
};
8737
8738
0
#define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
8739
8740
/* The values used here must be non-zero, fit in 'unsigned char', and not be
8741
   in conflict with actual prefix opcodes.  */
8742
5.10k
#define REP_PREFIX  0x01
8743
3.84k
#define XACQUIRE_PREFIX 0x02
8744
5.20k
#define XRELEASE_PREFIX 0x03
8745
6.23k
#define BND_PREFIX  0x04
8746
4.67k
#define NOTRACK_PREFIX  0x05
8747
8748
static enum {
8749
  ckp_okay,
8750
  ckp_bogus,
8751
  ckp_fetch_error,
8752
}
8753
ckprefix (instr_info *ins)
8754
44.3M
{
8755
44.3M
  int i, length;
8756
44.3M
  uint8_t newrex;
8757
8758
44.3M
  i = 0;
8759
44.3M
  length = 0;
8760
  /* The maximum instruction length is 15bytes.  */
8761
51.3M
  while (length < MAX_CODE_LENGTH - 1)
8762
51.3M
    {
8763
51.3M
      if (!fetch_code (ins->info, ins->codep + 1))
8764
4.20k
  return ckp_fetch_error;
8765
51.3M
      newrex = 0;
8766
51.3M
      switch (*ins->codep)
8767
51.3M
  {
8768
  /* REX prefixes family.  */
8769
245k
  case 0x40:
8770
957k
  case 0x41:
8771
1.09M
  case 0x42:
8772
1.24M
  case 0x43:
8773
1.60M
  case 0x44:
8774
1.93M
  case 0x45:
8775
2.06M
  case 0x46:
8776
2.17M
  case 0x47:
8777
4.21M
  case 0x48:
8778
4.70M
  case 0x49:
8779
4.79M
  case 0x4a:
8780
4.88M
  case 0x4b:
8781
5.42M
  case 0x4c:
8782
5.59M
  case 0x4d:
8783
5.78M
  case 0x4e:
8784
5.94M
  case 0x4f:
8785
5.94M
    if (ins->address_mode == mode_64bit)
8786
5.22M
      newrex = *ins->codep;
8787
718k
    else
8788
718k
      return ckp_okay;
8789
5.22M
    ins->last_rex_prefix = i;
8790
5.22M
    break;
8791
  /* REX2 must be the last prefix. */
8792
60.8k
  case REX2_OPCODE:
8793
60.8k
    if (ins->address_mode == mode_64bit)
8794
53.9k
      {
8795
53.9k
        if (ins->last_rex_prefix >= 0)
8796
625
    return ckp_bogus;
8797
8798
53.2k
        ins->codep++;
8799
53.2k
        if (!fetch_code (ins->info, ins->codep + 1))
8800
98
    return ckp_fetch_error;
8801
53.1k
        ins->rex2_payload = *ins->codep;
8802
53.1k
        ins->rex2 = ins->rex2_payload >> 4;
8803
53.1k
        ins->rex = (ins->rex2_payload & 0xf) | REX_OPCODE;
8804
53.1k
        ins->codep++;
8805
53.1k
        ins->last_rex2_prefix = i;
8806
53.1k
        ins->all_prefixes[i] = REX2_OPCODE;
8807
53.1k
      }
8808
60.0k
    return ckp_okay;
8809
80.1k
  case 0xf3:
8810
80.1k
    ins->prefixes |= PREFIX_REPZ;
8811
80.1k
    ins->last_repz_prefix = i;
8812
80.1k
    break;
8813
104k
  case 0xf2:
8814
104k
    ins->prefixes |= PREFIX_REPNZ;
8815
104k
    ins->last_repnz_prefix = i;
8816
104k
    break;
8817
101k
  case 0xf0:
8818
101k
    ins->prefixes |= PREFIX_LOCK;
8819
101k
    ins->last_lock_prefix = i;
8820
101k
    break;
8821
189k
  case 0x2e:
8822
189k
    ins->prefixes |= PREFIX_CS;
8823
189k
    ins->last_seg_prefix = i;
8824
189k
    if (ins->address_mode != mode_64bit)
8825
44.0k
      ins->active_seg_prefix = PREFIX_CS;
8826
189k
    break;
8827
85.0k
  case 0x36:
8828
85.0k
    ins->prefixes |= PREFIX_SS;
8829
85.0k
    ins->last_seg_prefix = i;
8830
85.0k
    if (ins->address_mode != mode_64bit)
8831
18.9k
      ins->active_seg_prefix = PREFIX_SS;
8832
85.0k
    break;
8833
130k
  case 0x3e:
8834
130k
    ins->prefixes |= PREFIX_DS;
8835
130k
    ins->last_seg_prefix = i;
8836
130k
    if (ins->address_mode != mode_64bit)
8837
27.7k
      ins->active_seg_prefix = PREFIX_DS;
8838
130k
    break;
8839
56.2k
  case 0x26:
8840
56.2k
    ins->prefixes |= PREFIX_ES;
8841
56.2k
    ins->last_seg_prefix = i;
8842
56.2k
    if (ins->address_mode != mode_64bit)
8843
18.7k
      ins->active_seg_prefix = PREFIX_ES;
8844
56.2k
    break;
8845
289k
  case 0x64:
8846
289k
    ins->prefixes |= PREFIX_FS;
8847
289k
    ins->last_seg_prefix = i;
8848
289k
    ins->active_seg_prefix = PREFIX_FS;
8849
289k
    break;
8850
416k
  case 0x65:
8851
416k
    ins->prefixes |= PREFIX_GS;
8852
416k
    ins->last_seg_prefix = i;
8853
416k
    ins->active_seg_prefix = PREFIX_GS;
8854
416k
    break;
8855
559k
  case 0x66:
8856
559k
    ins->prefixes |= PREFIX_DATA;
8857
559k
    ins->last_data_prefix = i;
8858
559k
    break;
8859
167k
  case 0x67:
8860
167k
    ins->prefixes |= PREFIX_ADDR;
8861
167k
    ins->last_addr_prefix = i;
8862
167k
    break;
8863
32.9k
  case FWAIT_OPCODE:
8864
    /* fwait is really an instruction.  If there are prefixes
8865
       before the fwait, they belong to the fwait, *not* to the
8866
       following instruction.  */
8867
32.9k
    ins->fwait_prefix = i;
8868
32.9k
    if (ins->prefixes || ins->rex)
8869
6.07k
      {
8870
6.07k
        ins->prefixes |= PREFIX_FWAIT;
8871
6.07k
        ins->codep++;
8872
        /* This ensures that the previous REX prefixes are noticed
8873
     as unused prefixes, as in the return case below.  */
8874
6.07k
        return ins->rex ? ckp_bogus : ckp_okay;
8875
6.07k
      }
8876
26.8k
    ins->prefixes = PREFIX_FWAIT;
8877
26.8k
    break;
8878
43.0M
  default:
8879
43.0M
    return ckp_okay;
8880
51.3M
  }
8881
      /* Rex is ignored when followed by another prefix.  */
8882
7.43M
      if (ins->rex)
8883
463k
  return ckp_bogus;
8884
6.96M
      if (*ins->codep != FWAIT_OPCODE)
8885
6.94M
  ins->all_prefixes[i++] = *ins->codep;
8886
6.96M
      ins->rex = newrex;
8887
6.96M
      ins->codep++;
8888
6.96M
      length++;
8889
6.96M
    }
8890
5.14k
  return ckp_bogus;
8891
44.3M
}
8892
8893
/* Return the name of the prefix byte PREF, or NULL if PREF is not a
8894
   prefix byte.  */
8895
8896
static const char *
8897
prefix_name (enum address_mode mode, uint8_t pref, int sizeflag)
8898
2.37M
{
8899
2.37M
  static const char *rexes [16] =
8900
2.37M
    {
8901
2.37M
      "rex",    /* 0x40 */
8902
2.37M
      "rex.B",    /* 0x41 */
8903
2.37M
      "rex.X",    /* 0x42 */
8904
2.37M
      "rex.XB",   /* 0x43 */
8905
2.37M
      "rex.R",    /* 0x44 */
8906
2.37M
      "rex.RB",   /* 0x45 */
8907
2.37M
      "rex.RX",   /* 0x46 */
8908
2.37M
      "rex.RXB",  /* 0x47 */
8909
2.37M
      "rex.W",    /* 0x48 */
8910
2.37M
      "rex.WB",   /* 0x49 */
8911
2.37M
      "rex.WX",   /* 0x4a */
8912
2.37M
      "rex.WXB",  /* 0x4b */
8913
2.37M
      "rex.WR",   /* 0x4c */
8914
2.37M
      "rex.WRB",  /* 0x4d */
8915
2.37M
      "rex.WRX",  /* 0x4e */
8916
2.37M
      "rex.WRXB", /* 0x4f */
8917
2.37M
    };
8918
8919
2.37M
  switch (pref)
8920
2.37M
    {
8921
    /* REX prefixes family.  */
8922
112k
    case 0x40:
8923
192k
    case 0x41:
8924
254k
    case 0x42:
8925
328k
    case 0x43:
8926
395k
    case 0x44:
8927
488k
    case 0x45:
8928
556k
    case 0x46:
8929
603k
    case 0x47:
8930
696k
    case 0x48:
8931
790k
    case 0x49:
8932
841k
    case 0x4a:
8933
888k
    case 0x4b:
8934
973k
    case 0x4c:
8935
1.03M
    case 0x4d:
8936
1.12M
    case 0x4e:
8937
1.22M
    case 0x4f:
8938
1.22M
      return rexes [pref - 0x40];
8939
56.7k
    case 0xf3:
8940
56.7k
      return "repz";
8941
79.2k
    case 0xf2:
8942
79.2k
      return "repnz";
8943
92.6k
    case 0xf0:
8944
92.6k
      return "lock";
8945
133k
    case 0x2e:
8946
133k
      return "cs";
8947
70.5k
    case 0x36:
8948
70.5k
      return "ss";
8949
54.2k
    case 0x3e:
8950
54.2k
      return "ds";
8951
40.7k
    case 0x26:
8952
40.7k
      return "es";
8953
154k
    case 0x64:
8954
154k
      return "fs";
8955
249k
    case 0x65:
8956
249k
      return "gs";
8957
101k
    case 0x66:
8958
101k
      return (sizeflag & DFLAG) ? "data16" : "data32";
8959
79.1k
    case 0x67:
8960
79.1k
      if (mode == mode_64bit)
8961
54.1k
  return (sizeflag & AFLAG) ? "addr32" : "addr64";
8962
25.0k
      else
8963
25.0k
  return (sizeflag & AFLAG) ? "addr16" : "addr32";
8964
190
    case FWAIT_OPCODE:
8965
190
      return "fwait";
8966
2.55k
    case REP_PREFIX:
8967
2.55k
      return "rep";
8968
1.86k
    case XACQUIRE_PREFIX:
8969
1.86k
      return "xacquire";
8970
2.51k
    case XRELEASE_PREFIX:
8971
2.51k
      return "xrelease";
8972
3.11k
    case BND_PREFIX:
8973
3.11k
      return "bnd";
8974
2.25k
    case NOTRACK_PREFIX:
8975
2.25k
      return "notrack";
8976
30.5k
    case REX2_OPCODE:
8977
30.5k
      return "rex2";
8978
280
    default:
8979
280
      return NULL;
8980
2.37M
    }
8981
2.37M
}
8982
8983
void
8984
print_i386_disassembler_options (FILE *stream)
8985
0
{
8986
0
  fprintf (stream, _("\n\
8987
0
The following i386/x86-64 specific disassembler options are supported for use\n\
8988
0
with the -M switch (multiple options should be separated by commas):\n"));
8989
8990
0
  fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
8991
0
  fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
8992
0
  fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
8993
0
  fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
8994
0
  fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
8995
0
  fprintf (stream, _("  att-mnemonic  (AT&T syntax only)\n"
8996
0
         "              Display instruction with AT&T mnemonic\n"));
8997
0
  fprintf (stream, _("  intel-mnemonic  (AT&T syntax only)\n"
8998
0
         "              Display instruction with Intel mnemonic\n"));
8999
0
  fprintf (stream, _("  addr64      Assume 64bit address size\n"));
9000
0
  fprintf (stream, _("  addr32      Assume 32bit address size\n"));
9001
0
  fprintf (stream, _("  addr16      Assume 16bit address size\n"));
9002
0
  fprintf (stream, _("  data32      Assume 32bit data size\n"));
9003
0
  fprintf (stream, _("  data16      Assume 16bit data size\n"));
9004
0
  fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
9005
0
  fprintf (stream, _("  amd64       Display instruction in AMD64 ISA\n"));
9006
0
  fprintf (stream, _("  intel64     Display instruction in Intel64 ISA\n"));
9007
0
}
9008
9009
/* Bad opcode.  */
9010
static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
9011
9012
/* Fetch error indicator.  */
9013
static const struct dis386 err_opcode = { NULL, { XX }, 0 };
9014
9015
static const struct dis386 map5_f8_opcode = { X86_64_TABLE (X86_64_VEX_MAP5_F8) };
9016
static const struct dis386 map5_f9_opcode = { X86_64_TABLE (X86_64_VEX_MAP5_F9) };
9017
static const struct dis386 map5_fd_opcode = { X86_64_TABLE (X86_64_VEX_MAP5_FD) };
9018
static const struct dis386 map7_f6_opcode = { VEX_LEN_TABLE (VEX_LEN_MAP7_F6) };
9019
static const struct dis386 map7_f8_opcode = { VEX_LEN_TABLE (VEX_LEN_MAP7_F8) };
9020
9021
/* Get a pointer to struct dis386 with a valid name.  */
9022
9023
static const struct dis386 *
9024
get_valid_dis386 (const struct dis386 *dp, instr_info *ins)
9025
46.9M
{
9026
46.9M
  int vindex, vex_table_index;
9027
9028
46.9M
  if (dp->name != NULL)
9029
33.2M
    return dp;
9030
9031
13.6M
  switch (dp->op[0].bytemode)
9032
13.6M
    {
9033
5.13M
    case USE_REG_TABLE:
9034
5.13M
      dp = &reg_table[dp->op[1].bytemode][ins->modrm.reg];
9035
5.13M
      break;
9036
9037
100k
    case USE_MOD_TABLE:
9038
100k
      vindex = ins->modrm.mod == 0x3 ? 1 : 0;
9039
100k
      dp = &mod_table[dp->op[1].bytemode][vindex];
9040
100k
      break;
9041
9042
16.4k
    case USE_RM_TABLE:
9043
16.4k
      dp = &rm_table[dp->op[1].bytemode][ins->modrm.rm];
9044
16.4k
      break;
9045
9046
927k
    case USE_PREFIX_TABLE:
9047
928k
    use_prefix_table:
9048
928k
      if (ins->need_vex)
9049
52.8k
  {
9050
    /* The prefix in VEX is implicit.  */
9051
52.8k
    switch (ins->vex.prefix)
9052
52.8k
      {
9053
10.4k
      case 0:
9054
10.4k
        vindex = 0;
9055
10.4k
        break;
9056
12.9k
      case REPE_PREFIX_OPCODE:
9057
12.9k
        vindex = 1;
9058
12.9k
        break;
9059
16.2k
      case DATA_PREFIX_OPCODE:
9060
16.2k
        vindex = 2;
9061
16.2k
        break;
9062
13.1k
      case REPNE_PREFIX_OPCODE:
9063
13.1k
        vindex = 3;
9064
13.1k
        break;
9065
0
      default:
9066
0
        abort ();
9067
0
        break;
9068
52.8k
      }
9069
52.8k
  }
9070
875k
      else
9071
875k
  {
9072
875k
    int last_prefix = -1;
9073
875k
    int prefix = 0;
9074
875k
    vindex = 0;
9075
    /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
9076
       When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
9077
       last one wins.  */
9078
875k
    if ((ins->prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
9079
20.3k
      {
9080
20.3k
        if (ins->last_repz_prefix > ins->last_repnz_prefix)
9081
14.2k
    {
9082
14.2k
      vindex = 1;
9083
14.2k
      prefix = PREFIX_REPZ;
9084
14.2k
      last_prefix = ins->last_repz_prefix;
9085
14.2k
    }
9086
6.12k
        else
9087
6.12k
    {
9088
6.12k
      vindex = 3;
9089
6.12k
      prefix = PREFIX_REPNZ;
9090
6.12k
      last_prefix = ins->last_repnz_prefix;
9091
6.12k
    }
9092
9093
        /* Check if prefix should be ignored.  */
9094
20.3k
        if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
9095
20.3k
         & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
9096
20.3k
       & prefix) != 0
9097
20.3k
      && !prefix_table[dp->op[1].bytemode][vindex].name)
9098
377
    vindex = 0;
9099
20.3k
      }
9100
9101
875k
    if (vindex == 0 && (ins->prefixes & PREFIX_DATA) != 0)
9102
22.3k
      {
9103
22.3k
        vindex = 2;
9104
22.3k
        prefix = PREFIX_DATA;
9105
22.3k
        last_prefix = ins->last_data_prefix;
9106
22.3k
      }
9107
9108
875k
    if (vindex != 0)
9109
42.3k
      {
9110
42.3k
        ins->used_prefixes |= prefix;
9111
42.3k
        ins->all_prefixes[last_prefix] = 0;
9112
42.3k
      }
9113
875k
  }
9114
928k
      dp = &prefix_table[dp->op[1].bytemode][vindex];
9115
928k
      break;
9116
9117
2.93k
    case USE_X86_64_EVEX_FROM_VEX_TABLE:
9118
4.26k
    case USE_X86_64_EVEX_PFX_TABLE:
9119
5.71k
    case USE_X86_64_EVEX_W_TABLE:
9120
6.48k
    case USE_X86_64_EVEX_MEM_W_TABLE:
9121
6.48k
      ins->evex_type = evex_from_vex;
9122
      /* EVEX from VEX instructions are 64-bit only and require that EVEX.z,
9123
   EVEX.L'L, EVEX.b, and the lower 2 bits of EVEX.aaa must be 0.  */
9124
6.48k
      if (ins->address_mode != mode_64bit
9125
6.48k
    || (ins->vex.mask_register_specifier & 0x3) != 0
9126
6.48k
    || ins->vex.ll != 0
9127
6.48k
    || ins->vex.zeroing != 0
9128
6.48k
    || ins->vex.b)
9129
3.43k
  return &bad_opcode;
9130
9131
3.04k
      if (dp->op[0].bytemode == USE_X86_64_EVEX_PFX_TABLE)
9132
785
  goto use_prefix_table;
9133
2.26k
      if (dp->op[0].bytemode == USE_X86_64_EVEX_W_TABLE)
9134
1.20k
  goto use_vex_w_table;
9135
1.05k
      if (dp->op[0].bytemode == USE_X86_64_EVEX_MEM_W_TABLE)
9136
490
  {
9137
490
    if (ins->modrm.mod == 3)
9138
225
      return &bad_opcode;
9139
265
    goto use_vex_w_table;
9140
490
  }
9141
9142
      /* Fall through.  */
9143
4.25M
    case USE_X86_64_TABLE:
9144
4.25M
      vindex = ins->address_mode == mode_64bit ? 1 : 0;
9145
4.25M
      dp = &x86_64_table[dp->op[1].bytemode][vindex];
9146
4.25M
      break;
9147
9148
5.95k
    case USE_3BYTE_TABLE:
9149
5.95k
      if (ins->last_rex2_prefix >= 0)
9150
795
  return &err_opcode;
9151
5.15k
      if (!fetch_code (ins->info, ins->codep + 2))
9152
101
  return &err_opcode;
9153
5.05k
      vindex = *ins->codep++;
9154
5.05k
      dp = &three_byte_table[dp->op[1].bytemode][vindex];
9155
5.05k
      ins->end_codep = ins->codep;
9156
5.05k
      if (!fetch_modrm (ins))
9157
0
  return &err_opcode;
9158
5.05k
      break;
9159
9160
17.9k
    case USE_VEX_LEN_TABLE:
9161
17.9k
      if (!ins->need_vex)
9162
0
  abort ();
9163
9164
17.9k
      switch (ins->vex.length)
9165
17.9k
  {
9166
14.1k
  case 128:
9167
14.1k
    vindex = 0;
9168
14.1k
    break;
9169
860
  case 512:
9170
    /* This allows re-using in particular table entries where only
9171
       128-bit operand size (VEX.L=0 / EVEX.L'L=0) are valid.  */
9172
860
    if (ins->vex.evex)
9173
860
      {
9174
3.88k
  case 256:
9175
3.88k
        vindex = 1;
9176
3.88k
        break;
9177
860
      }
9178
  /* Fall through.  */
9179
0
  default:
9180
0
    abort ();
9181
0
    break;
9182
17.9k
  }
9183
9184
17.9k
      dp = &vex_len_table[dp->op[1].bytemode][vindex];
9185
17.9k
      break;
9186
9187
3.90k
    case USE_EVEX_LEN_TABLE:
9188
3.90k
      if (!ins->vex.evex)
9189
0
  abort ();
9190
9191
3.90k
      switch (ins->vex.length)
9192
3.90k
  {
9193
1.54k
  case 128:
9194
1.54k
    vindex = 0;
9195
1.54k
    break;
9196
1.15k
  case 256:
9197
1.15k
    vindex = 1;
9198
1.15k
    break;
9199
1.20k
  case 512:
9200
1.20k
    vindex = 2;
9201
1.20k
    break;
9202
0
  default:
9203
0
    abort ();
9204
0
    break;
9205
3.90k
  }
9206
9207
3.90k
      dp = &evex_len_table[dp->op[1].bytemode][vindex];
9208
3.90k
      break;
9209
9210
21.4k
    case USE_XOP_8F_TABLE:
9211
21.4k
      if (!fetch_code (ins->info, ins->codep + 3))
9212
159
  return &err_opcode;
9213
21.2k
      ins->rex = ~(*ins->codep >> 5) & 0x7;
9214
9215
      /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
9216
21.2k
      switch ((*ins->codep & 0x1f))
9217
21.2k
  {
9218
12.4k
  default:
9219
12.4k
    dp = &bad_opcode;
9220
12.4k
    return dp;
9221
4.55k
  case 0x8:
9222
4.55k
    vex_table_index = XOP_08;
9223
4.55k
    break;
9224
2.38k
  case 0x9:
9225
2.38k
    vex_table_index = XOP_09;
9226
2.38k
    break;
9227
1.90k
  case 0xa:
9228
1.90k
    vex_table_index = XOP_0A;
9229
1.90k
    break;
9230
21.2k
  }
9231
8.83k
      ins->codep++;
9232
8.83k
      ins->vex.w = *ins->codep & 0x80;
9233
8.83k
      if (ins->vex.w && ins->address_mode == mode_64bit)
9234
2.51k
  ins->rex |= REX_W;
9235
9236
8.83k
      ins->vex.register_specifier = (~(*ins->codep >> 3)) & 0xf;
9237
8.83k
      if (ins->address_mode != mode_64bit)
9238
3.04k
  {
9239
    /* In 16/32-bit mode REX_B is silently ignored.  */
9240
3.04k
    ins->rex &= ~REX_B;
9241
3.04k
  }
9242
9243
8.83k
      ins->vex.length = (*ins->codep & 0x4) ? 256 : 128;
9244
8.83k
      switch ((*ins->codep & 0x3))
9245
8.83k
  {
9246
6.10k
  case 0:
9247
6.10k
    break;
9248
544
  case 1:
9249
544
    ins->vex.prefix = DATA_PREFIX_OPCODE;
9250
544
    break;
9251
1.50k
  case 2:
9252
1.50k
    ins->vex.prefix = REPE_PREFIX_OPCODE;
9253
1.50k
    break;
9254
688
  case 3:
9255
688
    ins->vex.prefix = REPNE_PREFIX_OPCODE;
9256
688
    break;
9257
8.83k
  }
9258
8.83k
      ins->need_vex = 3;
9259
8.83k
      ins->codep++;
9260
8.83k
      vindex = *ins->codep++;
9261
8.83k
      dp = &xop_table[vex_table_index][vindex];
9262
9263
8.83k
      ins->end_codep = ins->codep;
9264
8.83k
      if (!fetch_modrm (ins))
9265
240
  return &err_opcode;
9266
9267
      /* No XOP encoding so far allows for a non-zero embedded prefix. Avoid
9268
   having to decode the bits for every otherwise valid encoding.  */
9269
8.59k
      if (ins->vex.prefix)
9270
2.64k
  return &bad_opcode;
9271
5.95k
      break;
9272
9273
64.0k
    case USE_VEX_C4_TABLE:
9274
      /* VEX prefix.  */
9275
64.0k
      if (!fetch_code (ins->info, ins->codep + 3))
9276
316
  return &err_opcode;
9277
63.7k
      ins->rex = ~(*ins->codep >> 5) & 0x7;
9278
63.7k
      switch ((*ins->codep & 0x1f))
9279
63.7k
  {
9280
35.7k
  default:
9281
35.7k
    dp = &bad_opcode;
9282
35.7k
    return dp;
9283
3.99k
  case 0x1:
9284
3.99k
    vex_table_index = VEX_0F;
9285
3.99k
    break;
9286
13.3k
  case 0x2:
9287
13.3k
    vex_table_index = VEX_0F38;
9288
13.3k
    break;
9289
4.90k
  case 0x3:
9290
4.90k
    vex_table_index = VEX_0F3A;
9291
4.90k
    break;
9292
3.50k
  case 0x5:
9293
3.50k
    vex_table_index = VEX_MAP5;
9294
3.50k
    break;
9295
2.22k
  case 0x7:
9296
2.22k
    vex_table_index = VEX_MAP7;
9297
2.22k
    break;
9298
63.7k
  }
9299
27.9k
      ins->codep++;
9300
27.9k
      ins->vex.w = *ins->codep & 0x80;
9301
27.9k
      if (ins->address_mode == mode_64bit)
9302
23.3k
  {
9303
23.3k
    if (ins->vex.w)
9304
8.37k
      ins->rex |= REX_W;
9305
23.3k
  }
9306
4.64k
      else
9307
4.64k
  {
9308
    /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
9309
       is ignored, other REX bits are 0 and the highest bit in
9310
       VEX.vvvv is also ignored (but we mustn't clear it here).  */
9311
4.64k
    ins->rex = 0;
9312
4.64k
  }
9313
27.9k
      ins->vex.register_specifier = (~(*ins->codep >> 3)) & 0xf;
9314
27.9k
      ins->vex.length = (*ins->codep & 0x4) ? 256 : 128;
9315
27.9k
      switch ((*ins->codep & 0x3))
9316
27.9k
  {
9317
9.91k
  case 0:
9318
9.91k
    break;
9319
8.73k
  case 1:
9320
8.73k
    ins->vex.prefix = DATA_PREFIX_OPCODE;
9321
8.73k
    break;
9322
5.27k
  case 2:
9323
5.27k
    ins->vex.prefix = REPE_PREFIX_OPCODE;
9324
5.27k
    break;
9325
4.06k
  case 3:
9326
4.06k
    ins->vex.prefix = REPNE_PREFIX_OPCODE;
9327
4.06k
    break;
9328
27.9k
  }
9329
27.9k
      ins->need_vex = 3;
9330
27.9k
      ins->codep++;
9331
27.9k
      vindex = *ins->codep++;
9332
27.9k
      ins->condition_code = vindex & 0xf;
9333
27.9k
      if (vex_table_index != VEX_MAP7 && vex_table_index != VEX_MAP5)
9334
22.2k
  dp = &vex_table[vex_table_index][vindex];
9335
5.73k
      else if (vindex == 0xf6)
9336
265
  dp = &map7_f6_opcode;
9337
5.47k
      else if (vindex == 0xf8)
9338
1.06k
  {
9339
1.06k
    if (vex_table_index == VEX_MAP5)
9340
315
      dp = &map5_f8_opcode;
9341
754
    else
9342
754
      dp = &map7_f8_opcode;
9343
1.06k
  }
9344
4.40k
      else if (vindex == 0xf9)
9345
267
  dp = &map5_f9_opcode;
9346
4.13k
      else if (vindex == 0xfd)
9347
339
  dp = &map5_fd_opcode;
9348
3.79k
      else
9349
3.79k
  dp = &bad_opcode;
9350
27.9k
      ins->end_codep = ins->codep;
9351
      /* There is no MODRM byte for VEX0F 77.  */
9352
27.9k
      if ((vex_table_index != VEX_0F || vindex != 0x77)
9353
27.9k
    && !fetch_modrm (ins))
9354
621
  return &err_opcode;
9355
27.3k
      break;
9356
9357
36.7k
    case USE_VEX_C5_TABLE:
9358
      /* VEX prefix.  */
9359
36.7k
      if (!fetch_code (ins->info, ins->codep + 2))
9360
225
  return &err_opcode;
9361
36.5k
      ins->rex = (*ins->codep & 0x80) ? 0 : REX_R;
9362
9363
      /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
9364
   VEX.vvvv is 1.  */
9365
36.5k
      ins->vex.register_specifier = (~(*ins->codep >> 3)) & 0xf;
9366
36.5k
      ins->vex.length = (*ins->codep & 0x4) ? 256 : 128;
9367
36.5k
      switch ((*ins->codep & 0x3))
9368
36.5k
  {
9369
6.84k
  case 0:
9370
6.84k
    break;
9371
13.6k
  case 1:
9372
13.6k
    ins->vex.prefix = DATA_PREFIX_OPCODE;
9373
13.6k
    break;
9374
5.83k
  case 2:
9375
5.83k
    ins->vex.prefix = REPE_PREFIX_OPCODE;
9376
5.83k
    break;
9377
10.2k
  case 3:
9378
10.2k
    ins->vex.prefix = REPNE_PREFIX_OPCODE;
9379
10.2k
    break;
9380
36.5k
  }
9381
36.5k
      ins->need_vex = 2;
9382
36.5k
      ins->codep++;
9383
36.5k
      vindex = *ins->codep++;
9384
36.5k
      dp = &vex_table[VEX_0F][vindex];
9385
36.5k
      ins->end_codep = ins->codep;
9386
      /* There is no MODRM byte for VEX 77.  */
9387
36.5k
      if (vindex != 0x77 && !fetch_modrm (ins))
9388
256
  return &err_opcode;
9389
36.2k
      break;
9390
9391
36.2k
    case USE_VEX_W_TABLE:
9392
23.2k
    use_vex_w_table:
9393
23.2k
      if (!ins->need_vex)
9394
0
  abort ();
9395
9396
23.2k
      dp = &vex_w_table[dp->op[1].bytemode][ins->vex.w];
9397
23.2k
      break;
9398
9399
195k
    case USE_EVEX_TABLE:
9400
195k
      ins->two_source_ops = false;
9401
      /* EVEX prefix.  */
9402
195k
      ins->vex.evex = true;
9403
195k
      if (!fetch_code (ins->info, ins->codep + 4))
9404
812
  return &err_opcode;
9405
      /* The first byte after 0x62.  */
9406
194k
      if (*ins->codep & 0x8)
9407
42.3k
  ins->rex2 |= REX_B;
9408
194k
      if (!(*ins->codep & 0x10))
9409
105k
  ins->rex2 |= REX_R;
9410
9411
194k
      ins->rex = ~(*ins->codep >> 5) & 0x7;
9412
194k
      switch (*ins->codep & 0x7)
9413
194k
  {
9414
14.6k
  default:
9415
14.6k
    return &bad_opcode;
9416
28.9k
  case 0x1:
9417
28.9k
    vex_table_index = EVEX_0F;
9418
28.9k
    break;
9419
35.7k
  case 0x2:
9420
35.7k
    vex_table_index = EVEX_0F38;
9421
35.7k
    break;
9422
28.9k
  case 0x3:
9423
28.9k
    vex_table_index = EVEX_0F3A;
9424
28.9k
    break;
9425
28.4k
  case 0x4:
9426
28.4k
    vex_table_index = EVEX_MAP4;
9427
28.4k
    ins->evex_type = evex_from_legacy;
9428
28.4k
    if (ins->address_mode != mode_64bit)
9429
784
      return &bad_opcode;
9430
27.6k
    ins->rex |= REX_OPCODE;
9431
27.6k
    break;
9432
30.1k
  case 0x5:
9433
30.1k
    vex_table_index = EVEX_MAP5;
9434
30.1k
    break;
9435
14.9k
  case 0x6:
9436
14.9k
    vex_table_index = EVEX_MAP6;
9437
14.9k
    break;
9438
12.8k
  case 0x7:
9439
12.8k
    vex_table_index = EVEX_MAP7;
9440
12.8k
    break;
9441
194k
  }
9442
9443
      /* The second byte after 0x62.  */
9444
179k
      ins->codep++;
9445
179k
      ins->vex.w = *ins->codep & 0x80;
9446
179k
      if (ins->vex.w && ins->address_mode == mode_64bit)
9447
39.5k
  ins->rex |= REX_W;
9448
9449
179k
      ins->vex.register_specifier = (~(*ins->codep >> 3)) & 0xf;
9450
9451
179k
      if (!(*ins->codep & 0x4))
9452
58.5k
  ins->rex2 |= REX_X;
9453
9454
179k
      switch ((*ins->codep & 0x3))
9455
179k
  {
9456
47.0k
  case 0:
9457
47.0k
    break;
9458
37.6k
  case 1:
9459
37.6k
    ins->vex.prefix = DATA_PREFIX_OPCODE;
9460
37.6k
    break;
9461
43.9k
  case 2:
9462
43.9k
    ins->vex.prefix = REPE_PREFIX_OPCODE;
9463
43.9k
    break;
9464
50.6k
  case 3:
9465
50.6k
    ins->vex.prefix = REPNE_PREFIX_OPCODE;
9466
50.6k
    break;
9467
179k
  }
9468
9469
      /* The third byte after 0x62.  */
9470
179k
      ins->codep++;
9471
9472
      /* Remember the static rounding bits.  */
9473
179k
      ins->vex.ll = (*ins->codep >> 5) & 3;
9474
179k
      ins->vex.b = *ins->codep & 0x10;
9475
9476
179k
      ins->vex.v = *ins->codep & 0x8;
9477
179k
      ins->vex.mask_register_specifier = *ins->codep & 0x7;
9478
179k
      ins->vex.scc = *ins->codep & 0xf;
9479
179k
      ins->vex.zeroing = *ins->codep & 0x80;
9480
      /* Set the NF bit for EVEX-Promoted instructions, this bit will be cleared
9481
   when it's an evex_default one.  */
9482
179k
      ins->vex.nf = *ins->codep & 0x4;
9483
9484
179k
      if (ins->address_mode != mode_64bit)
9485
11.4k
  {
9486
    /* Report bad for !evex_default and when two fixed values of evex
9487
       change.  */
9488
11.4k
    if (ins->evex_type != evex_default
9489
11.4k
        || (ins->rex2 & (REX_B | REX_X)))
9490
1.86k
      return &bad_opcode;
9491
    /* In 16/32-bit mode silently ignore following bits.  */
9492
9.62k
    ins->rex &= ~REX_B;
9493
9.62k
    ins->rex2 &= ~REX_R;
9494
9.62k
  }
9495
9496
177k
      ins->need_vex = 4;
9497
9498
177k
      ins->codep++;
9499
177k
      vindex = *ins->codep++;
9500
177k
      ins->condition_code = vindex & 0xf;
9501
177k
      if (vex_table_index != EVEX_MAP7)
9502
165k
  dp = &evex_table[vex_table_index][vindex];
9503
12.1k
      else if (vindex == 0xf8)
9504
357
  dp = &map7_f8_opcode;
9505
11.8k
      else if (vindex == 0xf6)
9506
376
  dp = &map7_f6_opcode;
9507
11.4k
      else
9508
11.4k
  dp = &bad_opcode;
9509
177k
      ins->end_codep = ins->codep;
9510
177k
      if (!fetch_modrm (ins))
9511
711
  return &err_opcode;
9512
9513
176k
      if (ins->modrm.mod == 3 && (ins->rex2 & REX_X))
9514
5.29k
  return &bad_opcode;
9515
9516
      /* Set vector length. For EVEX-promoted instructions, evex.ll == 0b00,
9517
   which has the same encoding as vex.length == 128 and they can share
9518
   the same processing with vex.length in OP_VEX.  */
9519
171k
      if (ins->modrm.mod == 3 && ins->vex.b && ins->evex_type != evex_from_legacy)
9520
12.5k
  ins->vex.length = 512;
9521
158k
      else
9522
158k
  {
9523
158k
    switch (ins->vex.ll)
9524
158k
      {
9525
48.6k
      case 0x0:
9526
48.6k
        ins->vex.length = 128;
9527
48.6k
        break;
9528
31.3k
      case 0x1:
9529
31.3k
        ins->vex.length = 256;
9530
31.3k
        break;
9531
35.5k
      case 0x2:
9532
35.5k
        ins->vex.length = 512;
9533
35.5k
        break;
9534
43.2k
      default:
9535
43.2k
        return &bad_opcode;
9536
158k
      }
9537
158k
  }
9538
128k
      break;
9539
9540
2.86M
    case 0:
9541
2.86M
      dp = &bad_opcode;
9542
2.86M
      break;
9543
9544
0
    default:
9545
0
      abort ();
9546
13.6M
    }
9547
9548
13.5M
  if (dp->name != NULL)
9549
10.1M
    return dp;
9550
3.39M
  else
9551
3.39M
    return get_valid_dis386 (dp, ins);
9552
13.5M
}
9553
9554
static bool
9555
get_sib (instr_info *ins, int sizeflag)
9556
43.8M
{
9557
  /* If modrm.mod == 3, operand must be register.  */
9558
43.8M
  if (ins->need_modrm
9559
43.8M
      && ((sizeflag & AFLAG) || ins->address_mode == mode_64bit)
9560
43.8M
      && ins->modrm.mod != 3
9561
43.8M
      && ins->modrm.rm == 4)
9562
2.03M
    {
9563
2.03M
      if (!fetch_code (ins->info, ins->codep + 2))
9564
1.64k
  return false;
9565
2.03M
      ins->sib.index = (ins->codep[1] >> 3) & 7;
9566
2.03M
      ins->sib.scale = (ins->codep[1] >> 6) & 3;
9567
2.03M
      ins->sib.base = ins->codep[1] & 7;
9568
2.03M
      ins->has_sib = true;
9569
2.03M
    }
9570
41.8M
  else
9571
41.8M
    ins->has_sib = false;
9572
9573
43.8M
  return true;
9574
43.8M
}
9575
9576
/* Like oappend_with_style (below) but always with text style.  */
9577
9578
static void
9579
oappend (instr_info *ins, const char *s)
9580
5.46M
{
9581
5.46M
  oappend_with_style (ins, s, dis_style_text);
9582
5.46M
}
9583
9584
/* Like oappend (above), but S is a string starting with '%'.  In
9585
   Intel syntax, the '%' is elided.  */
9586
9587
static void
9588
oappend_register (instr_info *ins, const char *s)
9589
54.9M
{
9590
54.9M
  oappend_with_style (ins, s + ins->intel_syntax, dis_style_register);
9591
54.9M
}
9592
9593
/* Wrap around a call to INS->info->fprintf_styled_func, printing FMT.
9594
   STYLE is the default style to use in the fprintf_styled_func calls,
9595
   however, FMT might include embedded style markers (see oappend_style),
9596
   these embedded markers are not printed, but instead change the style
9597
   used in the next fprintf_styled_func call.  */
9598
9599
static void ATTRIBUTE_PRINTF_3
9600
i386_dis_printf (const disassemble_info *info, enum disassembler_style style,
9601
     const char *fmt, ...)
9602
136M
{
9603
136M
  va_list ap;
9604
136M
  enum disassembler_style curr_style = style;
9605
136M
  const char *start, *curr;
9606
136M
  char staging_area[50];
9607
9608
136M
  va_start (ap, fmt);
9609
  /* In particular print_insn()'s processing of op_txt[] can hand rather long
9610
     strings here.  Bypass vsnprintf() in such cases to avoid capacity issues
9611
     with the staging area.  */
9612
136M
  if (strcmp (fmt, "%s"))
9613
75.2M
    {
9614
75.2M
      int res = vsnprintf (staging_area, sizeof (staging_area), fmt, ap);
9615
9616
75.2M
      va_end (ap);
9617
9618
75.2M
      if (res < 0)
9619
0
  return;
9620
9621
75.2M
      if ((size_t) res >= sizeof (staging_area))
9622
0
  abort ();
9623
9624
75.2M
      start = curr = staging_area;
9625
75.2M
    }
9626
61.3M
  else
9627
61.3M
    {
9628
61.3M
      start = curr = va_arg (ap, const char *);
9629
61.3M
      va_end (ap);
9630
61.3M
    }
9631
9632
136M
  do
9633
943M
    {
9634
943M
      if (*curr == '\0'
9635
943M
    || (*curr == STYLE_MARKER_CHAR
9636
807M
        && ISXDIGIT (*(curr + 1))
9637
807M
        && *(curr + 2) == STYLE_MARKER_CHAR))
9638
261M
  {
9639
    /* Output content between our START position and CURR.  */
9640
261M
    int len = curr - start;
9641
261M
    int n = (*info->fprintf_styled_func) (info->stream, curr_style,
9642
261M
            "%.*s", len, start);
9643
261M
    if (n < 0)
9644
0
      break;
9645
9646
261M
    if (*curr == '\0')
9647
136M
      break;
9648
9649
    /* Skip over the initial STYLE_MARKER_CHAR.  */
9650
125M
    ++curr;
9651
9652
    /* Update the CURR_STYLE.  As there are less than 16 styles, it
9653
       is possible, that if the input is corrupted in some way, that
9654
       we might set CURR_STYLE to an invalid value.  Don't worry
9655
       though, we check for this situation.  */
9656
125M
    if (*curr >= '0' && *curr <= '9')
9657
125M
      curr_style = (enum disassembler_style) (*curr - '0');
9658
0
    else if (*curr >= 'a' && *curr <= 'f')
9659
0
      curr_style = (enum disassembler_style) (*curr - 'a' + 10);
9660
0
    else
9661
0
      curr_style = dis_style_text;
9662
9663
    /* Check for an invalid style having been selected.  This should
9664
       never happen, but it doesn't hurt to be a little paranoid.  */
9665
125M
    if (curr_style > dis_style_comment_start)
9666
0
      curr_style = dis_style_text;
9667
9668
    /* Skip the hex character, and the closing STYLE_MARKER_CHAR.  */
9669
125M
    curr += 2;
9670
9671
    /* Reset the START to after the style marker.  */
9672
125M
    start = curr;
9673
125M
  }
9674
681M
      else
9675
681M
  ++curr;
9676
943M
    }
9677
136M
  while (true);
9678
136M
}
9679
9680
static int
9681
print_insn (bfd_vma pc, disassemble_info *info, int intel_syntax)
9682
44.3M
{
9683
44.3M
  const struct dis386 *dp;
9684
44.3M
  int i;
9685
44.3M
  int ret;
9686
44.3M
  char *op_txt[MAX_OPERANDS];
9687
44.3M
  int needcomma;
9688
44.3M
  bool intel_swap_2_3;
9689
44.3M
  int sizeflag, orig_sizeflag;
9690
44.3M
  const char *p;
9691
44.3M
  struct dis_private priv;
9692
44.3M
  int prefix_length;
9693
44.3M
  int op_count;
9694
44.3M
  instr_info ins = {
9695
44.3M
    .info = info,
9696
44.3M
    .intel_syntax = intel_syntax >= 0
9697
44.3M
        ? intel_syntax
9698
44.3M
        : (info->mach & bfd_mach_i386_intel_syntax) != 0,
9699
44.3M
    .intel_mnemonic = !SYSV386_COMPAT,
9700
44.3M
    .op_index[0 ... MAX_OPERANDS - 1] = -1,
9701
44.3M
    .start_pc = pc,
9702
44.3M
    .start_codep = priv.the_buffer,
9703
44.3M
    .codep = priv.the_buffer,
9704
44.3M
    .obufp = ins.obuf,
9705
44.3M
    .last_lock_prefix = -1,
9706
44.3M
    .last_repz_prefix = -1,
9707
44.3M
    .last_repnz_prefix = -1,
9708
44.3M
    .last_data_prefix = -1,
9709
44.3M
    .last_addr_prefix = -1,
9710
44.3M
    .last_rex_prefix = -1,
9711
44.3M
    .last_rex2_prefix = -1,
9712
44.3M
    .last_seg_prefix = -1,
9713
44.3M
    .fwait_prefix = -1,
9714
44.3M
  };
9715
44.3M
  char op_out[MAX_OPERANDS][MAX_OPERAND_BUFFER_SIZE];
9716
9717
44.3M
  priv.orig_sizeflag = AFLAG | DFLAG;
9718
44.3M
  if ((info->mach & bfd_mach_i386_i386) != 0)
9719
13.2M
    ins.address_mode = mode_32bit;
9720
31.0M
  else if (info->mach == bfd_mach_i386_i8086)
9721
452k
    {
9722
452k
      ins.address_mode = mode_16bit;
9723
452k
      priv.orig_sizeflag = 0;
9724
452k
    }
9725
30.6M
  else
9726
30.6M
    ins.address_mode = mode_64bit;
9727
9728
44.8M
  for (p = info->disassembler_options; p != NULL;)
9729
506k
    {
9730
506k
      if (startswith (p, "amd64"))
9731
1.74k
  ins.isa64 = amd64;
9732
505k
      else if (startswith (p, "intel64"))
9733
13.1k
  ins.isa64 = intel64;
9734
492k
      else if (startswith (p, "x86-64"))
9735
1.28k
  {
9736
1.28k
    ins.address_mode = mode_64bit;
9737
1.28k
    priv.orig_sizeflag |= AFLAG | DFLAG;
9738
1.28k
  }
9739
490k
      else if (startswith (p, "i386"))
9740
3.69k
  {
9741
3.69k
    ins.address_mode = mode_32bit;
9742
3.69k
    priv.orig_sizeflag |= AFLAG | DFLAG;
9743
3.69k
  }
9744
487k
      else if (startswith (p, "i8086"))
9745
21.7k
  {
9746
21.7k
    ins.address_mode = mode_16bit;
9747
21.7k
    priv.orig_sizeflag &= ~(AFLAG | DFLAG);
9748
21.7k
  }
9749
465k
      else if (startswith (p, "intel"))
9750
55.5k
  {
9751
55.5k
    if (startswith (p + 5, "-mnemonic"))
9752
342
      ins.intel_mnemonic = true;
9753
55.1k
    else
9754
55.1k
      ins.intel_syntax = 1;
9755
55.5k
  }
9756
409k
      else if (startswith (p, "att"))
9757
18.4k
  {
9758
18.4k
    ins.intel_syntax = 0;
9759
18.4k
    if (startswith (p + 3, "-mnemonic"))
9760
226
      ins.intel_mnemonic = false;
9761
18.4k
  }
9762
391k
      else if (startswith (p, "addr"))
9763
14.1k
  {
9764
14.1k
    if (ins.address_mode == mode_64bit)
9765
8.77k
      {
9766
8.77k
        if (p[4] == '3' && p[5] == '2')
9767
3.04k
    priv.orig_sizeflag &= ~AFLAG;
9768
5.72k
        else if (p[4] == '6' && p[5] == '4')
9769
262
    priv.orig_sizeflag |= AFLAG;
9770
8.77k
      }
9771
5.41k
    else
9772
5.41k
      {
9773
5.41k
        if (p[4] == '1' && p[5] == '6')
9774
2.34k
    priv.orig_sizeflag &= ~AFLAG;
9775
3.06k
        else if (p[4] == '3' && p[5] == '2')
9776
452
    priv.orig_sizeflag |= AFLAG;
9777
5.41k
      }
9778
14.1k
  }
9779
377k
      else if (startswith (p, "data"))
9780
14.5k
  {
9781
14.5k
    if (p[4] == '1' && p[5] == '6')
9782
8.10k
      priv.orig_sizeflag &= ~DFLAG;
9783
6.40k
    else if (p[4] == '3' && p[5] == '2')
9784
668
      priv.orig_sizeflag |= DFLAG;
9785
14.5k
  }
9786
362k
      else if (startswith (p, "suffix"))
9787
14.4k
  priv.orig_sizeflag |= SUFFIX_ALWAYS;
9788
9789
506k
      p = strchr (p, ',');
9790
506k
      if (p != NULL)
9791
114k
  p++;
9792
506k
    }
9793
9794
44.3M
  if (ins.address_mode == mode_64bit && sizeof (bfd_vma) < 8)
9795
0
    {
9796
0
      i386_dis_printf (info, dis_style_text, _("64-bit address is disabled"));
9797
0
      return -1;
9798
0
    }
9799
9800
44.3M
  if (ins.intel_syntax)
9801
820k
    {
9802
820k
      ins.open_char = '[';
9803
820k
      ins.close_char = ']';
9804
820k
      ins.separator_char = '+';
9805
820k
      ins.scale_char = '*';
9806
820k
    }
9807
43.5M
  else
9808
43.5M
    {
9809
43.5M
      ins.open_char = '(';
9810
43.5M
      ins.close_char =  ')';
9811
43.5M
      ins.separator_char = ',';
9812
43.5M
      ins.scale_char = ',';
9813
43.5M
    }
9814
9815
  /* The output looks better if we put 7 bytes on a line, since that
9816
     puts most long word instructions on a single line.  */
9817
44.3M
  info->bytes_per_line = 7;
9818
9819
44.3M
  info->private_data = &priv;
9820
44.3M
  priv.fetched = 0;
9821
44.3M
  priv.insn_start = pc;
9822
9823
266M
  for (i = 0; i < MAX_OPERANDS; ++i)
9824
221M
    {
9825
221M
      op_out[i][0] = 0;
9826
221M
      ins.op_out[i] = op_out[i];
9827
221M
    }
9828
9829
44.3M
  sizeflag = priv.orig_sizeflag;
9830
9831
44.3M
  switch (ckprefix (&ins))
9832
44.3M
    {
9833
43.8M
    case ckp_okay:
9834
43.8M
      break;
9835
9836
470k
    case ckp_bogus:
9837
      /* Too many prefixes or unused REX prefixes.  */
9838
470k
      for (i = 0;
9839
1.02M
     i < (int) ARRAY_SIZE (ins.all_prefixes) && ins.all_prefixes[i];
9840
553k
     i++)
9841
553k
  i386_dis_printf (info, dis_style_mnemonic, "%s%s",
9842
553k
       (i == 0 ? "" : " "),
9843
553k
       prefix_name (ins.address_mode, ins.all_prefixes[i],
9844
553k
              sizeflag));
9845
470k
      ret = i;
9846
470k
      goto out;
9847
9848
4.30k
    case ckp_fetch_error:
9849
4.30k
      goto fetch_error_out;
9850
44.3M
    }
9851
9852
43.8M
  ins.nr_prefixes = ins.codep - ins.start_codep;
9853
9854
43.8M
  if (!fetch_code (info, ins.codep + 1))
9855
321
    {
9856
57.2k
    fetch_error_out:
9857
57.2k
      ret = fetch_error (&ins);
9858
57.2k
      goto out;
9859
321
    }
9860
9861
43.8M
  ins.two_source_ops = (*ins.codep == 0x62 || *ins.codep == 0xc8);
9862
9863
43.8M
  if ((ins.prefixes & PREFIX_FWAIT)
9864
43.8M
      && (*ins.codep < 0xd8 || *ins.codep > 0xdf))
9865
26.6k
    {
9866
      /* Handle ins.prefixes before fwait.  */
9867
28.0k
      for (i = 0; i < ins.fwait_prefix && ins.all_prefixes[i];
9868
26.6k
     i++)
9869
1.39k
  i386_dis_printf (info, dis_style_mnemonic, "%s ",
9870
1.39k
       prefix_name (ins.address_mode, ins.all_prefixes[i],
9871
1.39k
              sizeflag));
9872
26.6k
      i386_dis_printf (info, dis_style_mnemonic, "fwait");
9873
26.6k
      ret = i + 1;
9874
26.6k
      goto out;
9875
26.6k
    }
9876
9877
  /* REX2.M in rex2 prefix represents map0 or map1.  */
9878
43.8M
  if (ins.last_rex2_prefix < 0 ? *ins.codep == 0x0f : (ins.rex2 & REX2_M))
9879
1.14M
    {
9880
1.14M
      if (!ins.rex2)
9881
1.12M
  {
9882
1.12M
    ins.codep++;
9883
1.12M
    if (!fetch_code (info, ins.codep + 1))
9884
261
      goto fetch_error_out;
9885
1.12M
  }
9886
9887
1.14M
      dp = &dis386_twobyte[*ins.codep];
9888
1.14M
      ins.need_modrm = twobyte_has_modrm[*ins.codep];
9889
1.14M
    }
9890
42.7M
  else
9891
42.7M
    {
9892
42.7M
      dp = &dis386[*ins.codep];
9893
42.7M
      ins.need_modrm = onebyte_has_modrm[*ins.codep];
9894
42.7M
    }
9895
43.8M
  ins.condition_code = *ins.codep & 0xf;
9896
43.8M
  ins.codep++;
9897
9898
  /* Save sizeflag for printing the extra ins.prefixes later before updating
9899
     it for mnemonic and operand processing.  The prefix names depend
9900
     only on the address mode.  */
9901
43.8M
  orig_sizeflag = sizeflag;
9902
43.8M
  if (ins.prefixes & PREFIX_ADDR)
9903
131k
    sizeflag ^= AFLAG;
9904
43.8M
  if ((ins.prefixes & PREFIX_DATA))
9905
504k
    sizeflag ^= DFLAG;
9906
9907
43.8M
  ins.end_codep = ins.codep;
9908
43.8M
  if (ins.need_modrm && !fetch_modrm (&ins))
9909
7.44k
    goto fetch_error_out;
9910
9911
43.8M
  if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
9912
336k
    {
9913
336k
      if (!get_sib (&ins, sizeflag)
9914
336k
    || !dofloat (&ins, sizeflag))
9915
905
  goto fetch_error_out;
9916
336k
    }
9917
43.5M
  else
9918
43.5M
    {
9919
43.5M
      dp = get_valid_dis386 (dp, &ins);
9920
43.5M
      if (dp == &err_opcode)
9921
4.23k
  goto fetch_error_out;
9922
9923
      /* For APX instructions promoted from legacy maps 0/1, embedded prefix
9924
   is interpreted as the operand size override.  */
9925
43.5M
      if (ins.evex_type == evex_from_legacy
9926
43.5M
    && ins.vex.prefix == DATA_PREFIX_OPCODE)
9927
9.69k
  sizeflag ^= DFLAG;
9928
9929
43.5M
      if(ins.evex_type == evex_default)
9930
43.4M
  ins.vex.nf = false;
9931
34.8k
      else
9932
  /* For EVEX-promoted formats, we need to clear EVEX.NF (ccmp and ctest
9933
     are cleared separately.) in mask_register_specifier and keep the low
9934
     2 bits of mask_register_specifier to report errors for invalid cases
9935
     .  */
9936
34.8k
  ins.vex.mask_register_specifier &= 0x3;
9937
9938
43.5M
      if (dp != NULL && putop (&ins, dp->name, sizeflag) == 0)
9939
43.5M
  {
9940
43.5M
    if (!get_sib (&ins, sizeflag))
9941
1.45k
      goto fetch_error_out;
9942
260M
    for (i = 0; i < MAX_OPERANDS; ++i)
9943
217M
      {
9944
217M
        ins.obufp = ins.op_out[i];
9945
217M
        ins.op_ad = MAX_OPERANDS - 1 - i;
9946
217M
        if (dp->op[i].rtn
9947
217M
      && !dp->op[i].rtn (&ins, dp->op[i].bytemode, sizeflag))
9948
38.2k
    goto fetch_error_out;
9949
        /* For EVEX instruction after the last operand masking
9950
     should be printed.  */
9951
217M
        if (i == 0 && ins.vex.evex)
9952
192k
    {
9953
      /* Don't print {%k0}.  */
9954
192k
      if (ins.vex.mask_register_specifier)
9955
128k
        {
9956
128k
          const char *reg_name
9957
128k
      = att_names_mask[ins.vex.mask_register_specifier];
9958
9959
128k
          oappend (&ins, "{");
9960
128k
          oappend_register (&ins, reg_name);
9961
128k
          oappend (&ins, "}");
9962
9963
128k
          if (ins.vex.zeroing)
9964
33.0k
      oappend (&ins, "{z}");
9965
128k
        }
9966
64.3k
      else if (ins.vex.zeroing)
9967
7.32k
        {
9968
7.32k
          oappend (&ins, "{bad}");
9969
7.32k
          continue;
9970
7.32k
        }
9971
9972
      /* Instructions with a mask register destination allow for
9973
         zeroing-masking only (if any masking at all), which is
9974
         _not_ expressed by EVEX.z.  */
9975
185k
      if (ins.vex.zeroing && dp->op[0].bytemode == mask_mode)
9976
2.44k
        ins.illegal_masking = true;
9977
9978
      /* S/G insns require a mask and don't allow
9979
         zeroing-masking.  */
9980
185k
      if ((dp->op[0].bytemode == vex_vsib_d_w_dq_mode
9981
185k
           || dp->op[0].bytemode == vex_vsib_q_w_dq_mode)
9982
185k
          && (ins.vex.mask_register_specifier == 0
9983
4.42k
        || ins.vex.zeroing))
9984
2.31k
        ins.illegal_masking = true;
9985
9986
185k
      if (ins.illegal_masking)
9987
13.6k
        oappend (&ins, "/(bad)");
9988
185k
    }
9989
217M
      }
9990
    /* vex.nf is cleared after being consumed.  */
9991
43.4M
    if (ins.vex.nf)
9992
8.04k
      oappend (&ins, "{bad-nf}");
9993
9994
    /* Check whether rounding control was enabled for an insn not
9995
       supporting it, when evex.b is not treated as evex.nd.  */
9996
43.4M
    if (ins.modrm.mod == 3 && ins.vex.b && ins.evex_type == evex_default
9997
43.4M
        && !(ins.evex_used & EVEX_b_used))
9998
10.9k
      {
9999
27.1k
        for (i = 0; i < MAX_OPERANDS; ++i)
10000
27.1k
    {
10001
27.1k
      ins.obufp = ins.op_out[i];
10002
27.1k
      if (*ins.obufp)
10003
16.1k
        continue;
10004
10.9k
      oappend (&ins, names_rounding[ins.vex.ll]);
10005
10.9k
      oappend (&ins, "bad}");
10006
10.9k
      break;
10007
27.1k
    }
10008
10.9k
      }
10009
43.4M
  }
10010
43.5M
    }
10011
10012
  /* Clear instruction information.  */
10013
43.8M
  info->insn_info_valid = 0;
10014
43.8M
  info->branch_delay_insns = 0;
10015
43.8M
  info->data_size = 0;
10016
43.8M
  info->insn_type = dis_noninsn;
10017
43.8M
  info->target = 0;
10018
43.8M
  info->target2 = 0;
10019
10020
  /* Reset jump operation indicator.  */
10021
43.8M
  ins.op_is_jump = false;
10022
43.8M
  {
10023
43.8M
    int jump_detection = 0;
10024
10025
    /* Extract flags.  */
10026
262M
    for (i = 0; i < MAX_OPERANDS; ++i)
10027
219M
      {
10028
219M
  if ((dp->op[i].rtn == OP_J)
10029
219M
      || (dp->op[i].rtn == OP_indirE))
10030
5.62M
    jump_detection |= 1;
10031
213M
  else if ((dp->op[i].rtn == BND_Fixup)
10032
213M
     || (!dp->op[i].rtn && !dp->op[i].bytemode))
10033
146M
    jump_detection |= 2;
10034
67.1M
  else if ((dp->op[i].bytemode == cond_jump_mode)
10035
67.1M
     || (dp->op[i].bytemode == loop_jcxz_mode))
10036
3.50M
    jump_detection |= 4;
10037
219M
      }
10038
10039
    /* Determine if this is a jump or branch.  */
10040
43.8M
    if ((jump_detection & 0x3) == 0x3)
10041
5.62M
      {
10042
5.62M
  ins.op_is_jump = true;
10043
5.62M
  if (jump_detection & 0x4)
10044
3.50M
    info->insn_type = dis_condbranch;
10045
2.11M
  else
10046
2.11M
    info->insn_type = (dp->name && !strncmp (dp->name, "call", 4))
10047
2.11M
      ? dis_jsr : dis_branch;
10048
5.62M
      }
10049
43.8M
  }
10050
  /* The purpose of placing the check here is to wait for the EVEX prefix for
10051
     conditional CMP and TEST to be consumed and cleared, and then make a
10052
     unified judgment. Because they are both in map4, we can not distinguish
10053
     EVEX prefix for conditional CMP and TEST from others during the
10054
     EVEX prefix stage of parsing.  */
10055
43.8M
  if (ins.evex_type == evex_from_legacy)
10056
25.0k
    {
10057
      /* EVEX from legacy instructions, when the EVEX.ND bit is 0,
10058
   all bits of EVEX.vvvv and EVEX.V' must be 1.  */
10059
25.0k
      if (!ins.vex.nd && (ins.vex.register_specifier || !ins.vex.v))
10060
10.4k
  {
10061
10.4k
    i386_dis_printf (info, dis_style_text, "(bad)");
10062
10.4k
    ret = ins.end_codep - priv.the_buffer;
10063
10.4k
    goto out;
10064
10.4k
  }
10065
10066
      /* EVEX from legacy instructions require that EVEX.z, EVEX.L’L and the
10067
   lower 2 bits of EVEX.aaa must be 0.  */
10068
14.5k
      if ((ins.vex.mask_register_specifier & 0x3) != 0
10069
14.5k
    || ins.vex.ll != 0 || ins.vex.zeroing != 0)
10070
10.0k
  {
10071
10.0k
    i386_dis_printf (info, dis_style_text, "(bad)");
10072
10.0k
    ret = ins.end_codep - priv.the_buffer;
10073
10.0k
    goto out;
10074
10.0k
  }
10075
14.5k
    }
10076
  /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
10077
     are all 0s in inverted form.  */
10078
43.7M
  if (ins.need_vex && ins.vex.register_specifier != 0)
10079
149k
    {
10080
149k
      i386_dis_printf (info, dis_style_text, "(bad)");
10081
149k
      ret = ins.end_codep - priv.the_buffer;
10082
149k
      goto out;
10083
149k
    }
10084
10085
43.6M
  if ((dp->prefix_requirement & PREFIX_REX2_ILLEGAL)
10086
43.6M
      && ins.last_rex2_prefix >= 0 && (ins.rex2 & REX2_SPECIAL) == 0)
10087
5.57k
    {
10088
5.57k
      i386_dis_printf (info, dis_style_text, "(bad)");
10089
5.57k
      ret = ins.end_codep - priv.the_buffer;
10090
5.57k
      goto out;
10091
5.57k
    }
10092
10093
43.6M
  switch (dp->prefix_requirement & ~PREFIX_REX2_ILLEGAL)
10094
43.6M
    {
10095
34.4k
    case PREFIX_DATA:
10096
      /* If only the data prefix is marked as mandatory, its absence renders
10097
   the encoding invalid.  Most other PREFIX_OPCODE rules still apply.  */
10098
34.4k
      if (ins.need_vex ? !ins.vex.prefix : !(ins.prefixes & PREFIX_DATA))
10099
11.6k
  {
10100
11.6k
    i386_dis_printf (info, dis_style_text, "(bad)");
10101
11.6k
    ret = ins.end_codep - priv.the_buffer;
10102
11.6k
    goto out;
10103
11.6k
  }
10104
22.8k
      ins.used_prefixes |= PREFIX_DATA;
10105
      /* Fall through.  */
10106
86.2k
    case PREFIX_OPCODE:
10107
      /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
10108
   unused, opcode is invalid.  Since the PREFIX_DATA prefix may be
10109
   used by putop and MMX/SSE operand and may be overridden by the
10110
   PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
10111
   separately.  */
10112
86.2k
      if (((ins.need_vex
10113
86.2k
      ? ins.vex.prefix == REPE_PREFIX_OPCODE
10114
23.9k
        || ins.vex.prefix == REPNE_PREFIX_OPCODE
10115
86.2k
      : (ins.prefixes
10116
62.3k
         & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
10117
86.2k
     && (ins.used_prefixes
10118
27.0k
         & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
10119
86.2k
    || (((ins.need_vex
10120
70.7k
    ? ins.vex.prefix == DATA_PREFIX_OPCODE
10121
70.7k
    : ((ins.prefixes
10122
61.1k
        & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
10123
61.1k
       == PREFIX_DATA))
10124
70.7k
         && (ins.used_prefixes & PREFIX_DATA) == 0))
10125
86.2k
    || (ins.vex.evex && dp->prefix_requirement != PREFIX_DATA
10126
70.3k
        && !ins.vex.w != !(ins.used_prefixes & PREFIX_DATA)))
10127
16.2k
  {
10128
16.2k
    i386_dis_printf (info, dis_style_text, "(bad)");
10129
16.2k
    ret = ins.end_codep - priv.the_buffer;
10130
16.2k
    goto out;
10131
16.2k
  }
10132
69.9k
      break;
10133
10134
69.9k
    case PREFIX_IGNORED:
10135
      /* Zap data size and rep prefixes from used_prefixes and reinstate their
10136
   origins in all_prefixes.  */
10137
1.89k
      ins.used_prefixes &= ~PREFIX_OPCODE;
10138
1.89k
      if (ins.last_data_prefix >= 0)
10139
703
  ins.all_prefixes[ins.last_data_prefix] = 0x66;
10140
1.89k
      if (ins.last_repz_prefix >= 0)
10141
887
  ins.all_prefixes[ins.last_repz_prefix] = 0xf3;
10142
1.89k
      if (ins.last_repnz_prefix >= 0)
10143
1.25k
  ins.all_prefixes[ins.last_repnz_prefix] = 0xf2;
10144
1.89k
      break;
10145
10146
263k
    case PREFIX_NP_OR_DATA:
10147
263k
      if (ins.vex.prefix == REPE_PREFIX_OPCODE
10148
263k
    || ins.vex.prefix == REPNE_PREFIX_OPCODE)
10149
1.27k
  {
10150
1.27k
    i386_dis_printf (info, dis_style_text, "(bad)");
10151
1.27k
    ret = ins.end_codep - priv.the_buffer;
10152
1.27k
    goto out;
10153
1.27k
  }
10154
262k
      break;
10155
10156
262k
    case NO_PREFIX:
10157
205k
      if (ins.vex.prefix)
10158
699
  {
10159
699
    i386_dis_printf (info, dis_style_text, "(bad)");
10160
699
    ret = ins.end_codep - priv.the_buffer;
10161
699
    goto out;
10162
699
  }
10163
204k
      break;
10164
43.6M
    }
10165
10166
  /* Check if the REX prefix is used.  */
10167
43.5M
  if ((ins.rex ^ ins.rex_used) == 0
10168
43.5M
      && !ins.need_vex && ins.last_rex_prefix >= 0)
10169
3.56M
    ins.all_prefixes[ins.last_rex_prefix] = 0;
10170
10171
  /* Check if the REX2 prefix is used.  */
10172
43.5M
  if (ins.last_rex2_prefix >= 0
10173
43.5M
      && ((ins.rex2 & REX2_SPECIAL)
10174
33.3k
    || (((ins.rex2 & 7) ^ (ins.rex2_used & 7)) == 0
10175
32.4k
        && (ins.rex ^ ins.rex_used) == 0
10176
32.4k
        && (ins.rex2 & 7))))
10177
3.84k
    ins.all_prefixes[ins.last_rex2_prefix] = 0;
10178
10179
  /* Check if the SEG prefix is used.  */
10180
43.5M
  if ((ins.prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
10181
43.5M
           | PREFIX_FS | PREFIX_GS)) != 0
10182
43.5M
      && (ins.used_prefixes & ins.active_seg_prefix) != 0)
10183
307k
    ins.all_prefixes[ins.last_seg_prefix] = 0;
10184
10185
  /* Check if the ADDR prefix is used.  */
10186
43.5M
  if ((ins.prefixes & PREFIX_ADDR) != 0
10187
43.5M
      && (ins.used_prefixes & PREFIX_ADDR) != 0)
10188
71.3k
    ins.all_prefixes[ins.last_addr_prefix] = 0;
10189
10190
  /* Check if the DATA prefix is used.  */
10191
43.5M
  if ((ins.prefixes & PREFIX_DATA) != 0
10192
43.5M
      && (ins.used_prefixes & PREFIX_DATA) != 0
10193
43.5M
      && !ins.need_vex)
10194
442k
    ins.all_prefixes[ins.last_data_prefix] = 0;
10195
10196
  /* Print the extra ins.prefixes.  */
10197
43.5M
  prefix_length = 0;
10198
653M
  for (i = 0; i < (int) ARRAY_SIZE (ins.all_prefixes); i++)
10199
610M
    if (ins.all_prefixes[i])
10200
1.78M
      {
10201
1.78M
  const char *name = prefix_name (ins.address_mode, ins.all_prefixes[i],
10202
1.78M
          orig_sizeflag);
10203
10204
1.78M
  if (name == NULL)
10205
0
    abort ();
10206
1.78M
  prefix_length += strlen (name) + 1;
10207
1.78M
  if (ins.all_prefixes[i] == REX2_OPCODE)
10208
29.4k
    i386_dis_printf (info, dis_style_mnemonic, "{%s 0x%x} ", name,
10209
29.4k
         (unsigned int) ins.rex2_payload);
10210
1.76M
  else
10211
1.76M
    i386_dis_printf (info, dis_style_mnemonic, "%s ", name);
10212
1.78M
      }
10213
10214
  /* Check maximum code length.  */
10215
43.5M
  if ((ins.codep - ins.start_codep) > MAX_CODE_LENGTH)
10216
1.28k
    {
10217
1.28k
      i386_dis_printf (info, dis_style_text, "(bad)");
10218
1.28k
      ret = MAX_CODE_LENGTH;
10219
1.28k
      goto out;
10220
1.28k
    }
10221
10222
  /* Calculate the number of operands this instruction has.  */
10223
43.5M
  op_count = 0;
10224
261M
  for (i = 0; i < MAX_OPERANDS; ++i)
10225
217M
    if (*ins.op_out[i] != '\0')
10226
66.4M
      ++op_count;
10227
10228
  /* Calculate the number of spaces to print after the mnemonic.  */
10229
43.5M
  ins.obufp = ins.mnemonicendp;
10230
43.5M
  if (op_count > 0)
10231
38.3M
    {
10232
38.3M
      i = strlen (ins.obuf) + prefix_length;
10233
38.3M
      if (i < 7)
10234
37.2M
  i = 7 - i;
10235
1.13M
      else
10236
1.13M
  i = 1;
10237
38.3M
    }
10238
5.19M
  else
10239
5.19M
    i = 0;
10240
10241
  /* Print the instruction mnemonic along with any trailing whitespace.  */
10242
43.5M
  i386_dis_printf (info, dis_style_mnemonic, "%s%*s", ins.obuf, i, "");
10243
10244
  /* The enter and bound instructions are printed with operands in the same
10245
     order as the intel book; everything else is printed in reverse order.  */
10246
43.5M
  intel_swap_2_3 = false;
10247
43.5M
  if (ins.intel_syntax || ins.two_source_ops)
10248
820k
    {
10249
4.92M
      for (i = 0; i < MAX_OPERANDS; ++i)
10250
4.10M
  op_txt[i] = ins.op_out[i];
10251
10252
820k
      if (ins.intel_syntax && dp && dp->op[2].rtn == OP_Rounding
10253
820k
          && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
10254
1.01k
  {
10255
1.01k
    op_txt[2] = ins.op_out[3];
10256
1.01k
    op_txt[3] = ins.op_out[2];
10257
1.01k
    intel_swap_2_3 = true;
10258
1.01k
  }
10259
10260
2.46M
      for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
10261
1.64M
  {
10262
1.64M
    bool riprel;
10263
10264
1.64M
    ins.op_ad = ins.op_index[i];
10265
1.64M
    ins.op_index[i] = ins.op_index[MAX_OPERANDS - 1 - i];
10266
1.64M
    ins.op_index[MAX_OPERANDS - 1 - i] = ins.op_ad;
10267
1.64M
    riprel = ins.op_riprel[i];
10268
1.64M
    ins.op_riprel[i] = ins.op_riprel[MAX_OPERANDS - 1 - i];
10269
1.64M
    ins.op_riprel[MAX_OPERANDS - 1 - i] = riprel;
10270
1.64M
  }
10271
820k
    }
10272
42.7M
  else
10273
42.7M
    {
10274
256M
      for (i = 0; i < MAX_OPERANDS; ++i)
10275
213M
  op_txt[MAX_OPERANDS - 1 - i] = ins.op_out[i];
10276
42.7M
    }
10277
10278
43.5M
  needcomma = 0;
10279
261M
  for (i = 0; i < MAX_OPERANDS; ++i)
10280
217M
    if (*op_txt[i])
10281
66.4M
      {
10282
  /* In Intel syntax embedded rounding / SAE are not separate operands.
10283
     Instead they're attached to the prior register operand.  Simply
10284
     suppress emission of the comma to achieve that effect.  */
10285
66.4M
  switch (i & -(ins.intel_syntax && dp))
10286
66.4M
    {
10287
23.4k
    case 2:
10288
23.4k
      if (dp->op[2].rtn == OP_Rounding && !intel_swap_2_3)
10289
225
        needcomma = 0;
10290
23.4k
      break;
10291
2.61k
    case 3:
10292
2.61k
      if (dp->op[3].rtn == OP_Rounding || intel_swap_2_3)
10293
758
        needcomma = 0;
10294
2.61k
      break;
10295
66.4M
    }
10296
66.4M
  if (needcomma)
10297
28.0M
    i386_dis_printf (info, dis_style_text, ",");
10298
66.4M
  if (ins.op_index[i] != -1 && !ins.op_riprel[i])
10299
5.13M
    {
10300
5.13M
      bfd_vma target = (bfd_vma) ins.op_address[ins.op_index[i]];
10301
10302
5.13M
      if (ins.op_is_jump)
10303
5.13M
        {
10304
5.13M
    info->insn_info_valid = 1;
10305
5.13M
    info->branch_delay_insns = 0;
10306
5.13M
    info->data_size = 0;
10307
5.13M
    info->target = target;
10308
5.13M
    info->target2 = 0;
10309
5.13M
        }
10310
5.13M
      (*info->print_address_func) (target, info);
10311
5.13M
    }
10312
61.3M
  else
10313
61.3M
    i386_dis_printf (info, dis_style_text, "%s", op_txt[i]);
10314
66.4M
  needcomma = 1;
10315
66.4M
      }
10316
10317
260M
  for (i = 0; i < MAX_OPERANDS; i++)
10318
217M
    if (ins.op_index[i] != -1 && ins.op_riprel[i])
10319
937k
      {
10320
937k
  i386_dis_printf (info, dis_style_comment_start, "        # ");
10321
937k
  (*info->print_address_func)
10322
937k
    ((bfd_vma)(ins.start_pc + (ins.codep - ins.start_codep)
10323
937k
         + ins.op_address[ins.op_index[i]]),
10324
937k
    info);
10325
937k
  break;
10326
937k
      }
10327
43.5M
  ret = ins.codep - priv.the_buffer;
10328
44.3M
 out:
10329
44.3M
  info->private_data = NULL;
10330
44.3M
  return ret;
10331
43.5M
}
10332
10333
/* Here for backwards compatibility.  When gdb stops using
10334
   print_insn_i386_att and print_insn_i386_intel these functions can
10335
   disappear, and print_insn_i386 be merged into print_insn.  */
10336
int
10337
print_insn_i386_att (bfd_vma pc, disassemble_info *info)
10338
0
{
10339
0
  return print_insn (pc, info, 0);
10340
0
}
10341
10342
int
10343
print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
10344
0
{
10345
0
  return print_insn (pc, info, 1);
10346
0
}
10347
10348
int
10349
print_insn_i386 (bfd_vma pc, disassemble_info *info)
10350
44.3M
{
10351
44.3M
  return print_insn (pc, info, -1);
10352
44.3M
}
10353
10354
static const char *float_mem[] = {
10355
  /* d8 */
10356
  "fadd{s|}",
10357
  "fmul{s|}",
10358
  "fcom{s|}",
10359
  "fcomp{s|}",
10360
  "fsub{s|}",
10361
  "fsubr{s|}",
10362
  "fdiv{s|}",
10363
  "fdivr{s|}",
10364
  /* d9 */
10365
  "fld{s|}",
10366
  "(bad)",
10367
  "fst{s|}",
10368
  "fstp{s|}",
10369
  "fldenv{C|C}",
10370
  "fldcw",
10371
  "fNstenv{C|C}",
10372
  "fNstcw",
10373
  /* da */
10374
  "fiadd{l|}",
10375
  "fimul{l|}",
10376
  "ficom{l|}",
10377
  "ficomp{l|}",
10378
  "fisub{l|}",
10379
  "fisubr{l|}",
10380
  "fidiv{l|}",
10381
  "fidivr{l|}",
10382
  /* db */
10383
  "fild{l|}",
10384
  "fisttp{l|}",
10385
  "fist{l|}",
10386
  "fistp{l|}",
10387
  "(bad)",
10388
  "fld{t|}",
10389
  "(bad)",
10390
  "fstp{t|}",
10391
  /* dc */
10392
  "fadd{l|}",
10393
  "fmul{l|}",
10394
  "fcom{l|}",
10395
  "fcomp{l|}",
10396
  "fsub{l|}",
10397
  "fsubr{l|}",
10398
  "fdiv{l|}",
10399
  "fdivr{l|}",
10400
  /* dd */
10401
  "fld{l|}",
10402
  "fisttp{ll|}",
10403
  "fst{l||}",
10404
  "fstp{l|}",
10405
  "frstor{C|C}",
10406
  "(bad)",
10407
  "fNsave{C|C}",
10408
  "fNstsw",
10409
  /* de */
10410
  "fiadd{s|}",
10411
  "fimul{s|}",
10412
  "ficom{s|}",
10413
  "ficomp{s|}",
10414
  "fisub{s|}",
10415
  "fisubr{s|}",
10416
  "fidiv{s|}",
10417
  "fidivr{s|}",
10418
  /* df */
10419
  "fild{s|}",
10420
  "fisttp{s|}",
10421
  "fist{s|}",
10422
  "fistp{s|}",
10423
  "fbld",
10424
  "fild{ll|}",
10425
  "fbstp",
10426
  "fistp{ll|}",
10427
};
10428
10429
static const unsigned char float_mem_mode[] = {
10430
  /* d8 */
10431
  d_mode,
10432
  d_mode,
10433
  d_mode,
10434
  d_mode,
10435
  d_mode,
10436
  d_mode,
10437
  d_mode,
10438
  d_mode,
10439
  /* d9 */
10440
  d_mode,
10441
  0,
10442
  d_mode,
10443
  d_mode,
10444
  0,
10445
  w_mode,
10446
  0,
10447
  w_mode,
10448
  /* da */
10449
  d_mode,
10450
  d_mode,
10451
  d_mode,
10452
  d_mode,
10453
  d_mode,
10454
  d_mode,
10455
  d_mode,
10456
  d_mode,
10457
  /* db */
10458
  d_mode,
10459
  d_mode,
10460
  d_mode,
10461
  d_mode,
10462
  0,
10463
  t_mode,
10464
  0,
10465
  t_mode,
10466
  /* dc */
10467
  q_mode,
10468
  q_mode,
10469
  q_mode,
10470
  q_mode,
10471
  q_mode,
10472
  q_mode,
10473
  q_mode,
10474
  q_mode,
10475
  /* dd */
10476
  q_mode,
10477
  q_mode,
10478
  q_mode,
10479
  q_mode,
10480
  0,
10481
  0,
10482
  0,
10483
  w_mode,
10484
  /* de */
10485
  w_mode,
10486
  w_mode,
10487
  w_mode,
10488
  w_mode,
10489
  w_mode,
10490
  w_mode,
10491
  w_mode,
10492
  w_mode,
10493
  /* df */
10494
  w_mode,
10495
  w_mode,
10496
  w_mode,
10497
  w_mode,
10498
  t_mode,
10499
  q_mode,
10500
  t_mode,
10501
  q_mode
10502
};
10503
10504
#define ST { OP_ST, 0 }
10505
#define STi { OP_STi, 0 }
10506
10507
#define FGRPd9_2 NULL, { { NULL, 1 } }, 0
10508
#define FGRPd9_4 NULL, { { NULL, 2 } }, 0
10509
#define FGRPd9_5 NULL, { { NULL, 3 } }, 0
10510
#define FGRPd9_6 NULL, { { NULL, 4 } }, 0
10511
#define FGRPd9_7 NULL, { { NULL, 5 } }, 0
10512
#define FGRPda_5 NULL, { { NULL, 6 } }, 0
10513
#define FGRPdb_4 NULL, { { NULL, 7 } }, 0
10514
#define FGRPde_3 NULL, { { NULL, 8 } }, 0
10515
#define FGRPdf_4 NULL, { { NULL, 9 } }, 0
10516
10517
static const struct dis386 float_reg[][8] = {
10518
  /* d8 */
10519
  {
10520
    { "fadd", { ST, STi }, 0 },
10521
    { "fmul", { ST, STi }, 0 },
10522
    { "fcom", { STi }, 0 },
10523
    { "fcomp",  { STi }, 0 },
10524
    { "fsub", { ST, STi }, 0 },
10525
    { "fsubr",  { ST, STi }, 0 },
10526
    { "fdiv", { ST, STi }, 0 },
10527
    { "fdivr",  { ST, STi }, 0 },
10528
  },
10529
  /* d9 */
10530
  {
10531
    { "fld",  { STi }, 0 },
10532
    { "fxch", { STi }, 0 },
10533
    { FGRPd9_2 },
10534
    { Bad_Opcode },
10535
    { FGRPd9_4 },
10536
    { FGRPd9_5 },
10537
    { FGRPd9_6 },
10538
    { FGRPd9_7 },
10539
  },
10540
  /* da */
10541
  {
10542
    { "fcmovb", { ST, STi }, 0 },
10543
    { "fcmove", { ST, STi }, 0 },
10544
    { "fcmovbe",{ ST, STi }, 0 },
10545
    { "fcmovu", { ST, STi }, 0 },
10546
    { Bad_Opcode },
10547
    { FGRPda_5 },
10548
    { Bad_Opcode },
10549
    { Bad_Opcode },
10550
  },
10551
  /* db */
10552
  {
10553
    { "fcmovnb",{ ST, STi }, 0 },
10554
    { "fcmovne",{ ST, STi }, 0 },
10555
    { "fcmovnbe",{ ST, STi }, 0 },
10556
    { "fcmovnu",{ ST, STi }, 0 },
10557
    { FGRPdb_4 },
10558
    { "fucomi", { ST, STi }, 0 },
10559
    { "fcomi",  { ST, STi }, 0 },
10560
    { Bad_Opcode },
10561
  },
10562
  /* dc */
10563
  {
10564
    { "fadd", { STi, ST }, 0 },
10565
    { "fmul", { STi, ST }, 0 },
10566
    { Bad_Opcode },
10567
    { Bad_Opcode },
10568
    { "fsub{!M|r}", { STi, ST }, 0 },
10569
    { "fsub{M|}", { STi, ST }, 0 },
10570
    { "fdiv{!M|r}", { STi, ST }, 0 },
10571
    { "fdiv{M|}", { STi, ST }, 0 },
10572
  },
10573
  /* dd */
10574
  {
10575
    { "ffree",  { STi }, 0 },
10576
    { Bad_Opcode },
10577
    { "fst",  { STi }, 0 },
10578
    { "fstp", { STi }, 0 },
10579
    { "fucom",  { STi }, 0 },
10580
    { "fucomp", { STi }, 0 },
10581
    { Bad_Opcode },
10582
    { Bad_Opcode },
10583
  },
10584
  /* de */
10585
  {
10586
    { "faddp",  { STi, ST }, 0 },
10587
    { "fmulp",  { STi, ST }, 0 },
10588
    { Bad_Opcode },
10589
    { FGRPde_3 },
10590
    { "fsub{!M|r}p",  { STi, ST }, 0 },
10591
    { "fsub{M|}p",  { STi, ST }, 0 },
10592
    { "fdiv{!M|r}p",  { STi, ST }, 0 },
10593
    { "fdiv{M|}p",  { STi, ST }, 0 },
10594
  },
10595
  /* df */
10596
  {
10597
    { "ffreep", { STi }, 0 },
10598
    { Bad_Opcode },
10599
    { Bad_Opcode },
10600
    { Bad_Opcode },
10601
    { FGRPdf_4 },
10602
    { "fucomip", { ST, STi }, 0 },
10603
    { "fcomip", { ST, STi }, 0 },
10604
    { Bad_Opcode },
10605
  },
10606
};
10607
10608
static const char *const fgrps[][8] = {
10609
  /* Bad opcode 0 */
10610
  {
10611
    "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10612
  },
10613
10614
  /* d9_2  1 */
10615
  {
10616
    "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10617
  },
10618
10619
  /* d9_4  2 */
10620
  {
10621
    "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
10622
  },
10623
10624
  /* d9_5  3 */
10625
  {
10626
    "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
10627
  },
10628
10629
  /* d9_6  4 */
10630
  {
10631
    "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
10632
  },
10633
10634
  /* d9_7  5 */
10635
  {
10636
    "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
10637
  },
10638
10639
  /* da_5  6 */
10640
  {
10641
    "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10642
  },
10643
10644
  /* db_4  7 */
10645
  {
10646
    "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
10647
    "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
10648
  },
10649
10650
  /* de_3  8 */
10651
  {
10652
    "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10653
  },
10654
10655
  /* df_4  9 */
10656
  {
10657
    "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10658
  },
10659
};
10660
10661
static const char *const oszc_flags[16] = {
10662
  " {dfv=}", " {dfv=cf}", " {dfv=zf}", " {dfv=zf, cf}", " {dfv=sf}",
10663
  " {dfv=sf, cf}", " {dfv=sf, zf}", " {dfv=sf, zf, cf}", " {dfv=of}",
10664
  " {dfv=of, cf}", " {dfv=of, zf}", " {dfv=of, zf, cf}", " {dfv=of, sf}",
10665
  " {dfv=of, sf, cf}", " {dfv=of, sf, zf}", " {dfv=of, sf, zf, cf}"
10666
};
10667
10668
static const char *const scc_suffix[16] = {
10669
  "o", "no", "b", "ae", "e", "ne", "be", "a", "s", "ns", "t", "f",
10670
  "l", "ge", "le", "g"
10671
};
10672
10673
static void
10674
swap_operand (instr_info *ins)
10675
2.02k
{
10676
2.02k
  char *p = ins->mnemonicendp;
10677
10678
2.02k
  if (p[-1] == '}')
10679
420
    {
10680
5.08k
      while (*--p != '{')
10681
4.66k
  {
10682
4.66k
    if (p <= ins->obuf + 2)
10683
0
      abort ();
10684
4.66k
  }
10685
420
      if (p[-1] == ' ')
10686
228
  --p;
10687
420
    }
10688
2.02k
  memmove (p + 2, p, ins->mnemonicendp - p + 1);
10689
2.02k
  p[0] = '.';
10690
2.02k
  p[1] = 's';
10691
2.02k
  ins->mnemonicendp += 2;
10692
2.02k
}
10693
10694
static bool
10695
dofloat (instr_info *ins, int sizeflag)
10696
336k
{
10697
336k
  const struct dis386 *dp;
10698
336k
  unsigned char floatop = ins->codep[-1];
10699
10700
336k
  if (ins->modrm.mod != 3)
10701
215k
    {
10702
215k
      int fp_indx = (floatop - 0xd8) * 8 + ins->modrm.reg;
10703
10704
215k
      putop (ins, float_mem[fp_indx], sizeflag);
10705
215k
      ins->obufp = ins->op_out[0];
10706
215k
      ins->op_ad = 2;
10707
215k
      return OP_E (ins, float_mem_mode[fp_indx], sizeflag);
10708
215k
    }
10709
  /* Skip mod/rm byte.  */
10710
121k
  MODRM_CHECK;
10711
121k
  ins->codep++;
10712
10713
121k
  dp = &float_reg[floatop - 0xd8][ins->modrm.reg];
10714
121k
  if (dp->name == NULL)
10715
50.9k
    {
10716
50.9k
      putop (ins, fgrps[dp->op[0].bytemode][ins->modrm.rm], sizeflag);
10717
10718
      /* Instruction fnstsw is only one with strange arg.  */
10719
50.9k
      if (floatop == 0xdf && ins->codep[-1] == 0xe0)
10720
4.42k
  strcpy (ins->op_out[0], att_names16[0] + ins->intel_syntax);
10721
50.9k
    }
10722
70.2k
  else
10723
70.2k
    {
10724
70.2k
      putop (ins, dp->name, sizeflag);
10725
10726
70.2k
      ins->obufp = ins->op_out[0];
10727
70.2k
      ins->op_ad = 2;
10728
70.2k
      if (dp->op[0].rtn
10729
70.2k
    && !dp->op[0].rtn (ins, dp->op[0].bytemode, sizeflag))
10730
0
  return false;
10731
10732
70.2k
      ins->obufp = ins->op_out[1];
10733
70.2k
      ins->op_ad = 1;
10734
70.2k
      if (dp->op[1].rtn
10735
70.2k
    && !dp->op[1].rtn (ins, dp->op[1].bytemode, sizeflag))
10736
0
  return false;
10737
70.2k
    }
10738
121k
  return true;
10739
121k
}
10740
10741
static bool
10742
OP_ST (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
10743
       int sizeflag ATTRIBUTE_UNUSED)
10744
46.2k
{
10745
46.2k
  oappend_register (ins, "%st");
10746
46.2k
  return true;
10747
46.2k
}
10748
10749
static bool
10750
OP_STi (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
10751
  int sizeflag ATTRIBUTE_UNUSED)
10752
70.2k
{
10753
70.2k
  char scratch[8];
10754
70.2k
  int res = snprintf (scratch, ARRAY_SIZE (scratch), "%%st(%d)", ins->modrm.rm);
10755
10756
70.2k
  if (res < 0 || (size_t) res >= ARRAY_SIZE (scratch))
10757
0
    abort ();
10758
70.2k
  oappend_register (ins, scratch);
10759
70.2k
  return true;
10760
70.2k
}
10761
10762
/* Capital letters in template are macros.  */
10763
static int
10764
putop (instr_info *ins, const char *in_template, int sizeflag)
10765
43.8M
{
10766
43.8M
  const char *p;
10767
43.8M
  int alt = 0;
10768
43.8M
  int cond = 1;
10769
43.8M
  unsigned int l = 0, len = 0;
10770
43.8M
  char last[4];
10771
43.8M
  bool evex_printed = false;
10772
10773
  /* We don't want to add any prefix or suffix to (bad), so return early.  */
10774
43.8M
  if (!strncmp (in_template, "(bad)", 5))
10775
3.03M
    {
10776
3.03M
      oappend (ins, "(bad)");
10777
3.03M
      *ins->obufp = 0;
10778
3.03M
      ins->mnemonicendp = ins->obufp;
10779
3.03M
      return 0;
10780
3.03M
    }
10781
10782
221M
  for (p = in_template; *p; p++)
10783
180M
    {
10784
180M
      if (len > l)
10785
1.47M
  {
10786
1.47M
    if (l >= sizeof (last) || !ISUPPER (*p))
10787
0
      abort ();
10788
1.47M
    last[l++] = *p;
10789
1.47M
    continue;
10790
1.47M
  }
10791
179M
      switch (*p)
10792
179M
  {
10793
129M
  default:
10794
129M
    if (ins->evex_type == evex_from_legacy && !ins->vex.nd
10795
129M
        && !(ins->rex2 & 7) && !evex_printed)
10796
704
      {
10797
704
        oappend (ins, "{evex} ");
10798
704
        evex_printed = true;
10799
704
      }
10800
129M
    *ins->obufp++ = *p;
10801
129M
    break;
10802
1.47M
  case '%':
10803
1.47M
    len++;
10804
1.47M
    break;
10805
2.53M
  case '!':
10806
2.53M
    cond = 0;
10807
2.53M
    break;
10808
3.16M
  case '{':
10809
3.16M
    if (ins->intel_syntax)
10810
109k
      {
10811
217k
        while (*++p != '|')
10812
107k
    if (*p == '}' || *p == '\0')
10813
0
      abort ();
10814
109k
        alt = 1;
10815
109k
      }
10816
3.16M
    break;
10817
3.16M
  case '|':
10818
3.29M
    while (*++p != '}')
10819
233k
      {
10820
233k
        if (*p == '\0')
10821
0
    abort ();
10822
233k
      }
10823
3.05M
    break;
10824
3.05M
  case '}':
10825
109k
    alt = 0;
10826
109k
    break;
10827
819k
  case 'A':
10828
819k
    if (ins->intel_syntax)
10829
8.03k
      break;
10830
811k
    if ((ins->need_modrm && ins->modrm.mod != 3 && !ins->vex.nd)
10831
811k
        || (sizeflag & SUFFIX_ALWAYS))
10832
647k
      *ins->obufp++ = 'b';
10833
811k
    break;
10834
13.5M
  case 'B':
10835
13.5M
    if (l == 0)
10836
13.4M
      {
10837
13.5M
      case_B:
10838
13.5M
        if (ins->intel_syntax)
10839
179k
    break;
10840
13.3M
        if (sizeflag & SUFFIX_ALWAYS)
10841
500
    *ins->obufp++ = 'b';
10842
13.3M
      }
10843
110k
    else if (l == 1 && last[0] == 'L')
10844
108k
      {
10845
108k
        if (ins->address_mode == mode_64bit
10846
108k
      && !(ins->prefixes & PREFIX_ADDR))
10847
73.4k
    {
10848
73.4k
      *ins->obufp++ = 'a';
10849
73.4k
      *ins->obufp++ = 'b';
10850
73.4k
      *ins->obufp++ = 's';
10851
73.4k
    }
10852
10853
108k
        goto case_B;
10854
108k
      }
10855
1.83k
    else if (l && last[0] == 'X')
10856
1.83k
      {
10857
1.83k
        if (!ins->vex.w)
10858
1.41k
    oappend (ins, "bf16");
10859
416
        else
10860
416
    oappend (ins, "{bad}");
10861
1.83k
      }
10862
0
    else
10863
0
      abort ();
10864
13.3M
    break;
10865
13.3M
  case 'C':
10866
11.9k
    if (l == 1 && last[0] == 'C')
10867
2.97k
      {
10868
        /* Condition code (taken from the map-0 Jcc entries).  */
10869
2.97k
        for (const char *q = dis386[0x70 | ins->condition_code].name + 1;
10870
4.36k
       ISLOWER(*q); ++q)
10871
4.36k
    *ins->obufp++ = *q;
10872
2.97k
        break;
10873
2.97k
      }
10874
8.93k
    else if (l == 1 && last[0] == 'S')
10875
1.41k
      {
10876
        /* Add scc suffix.  */
10877
1.41k
        oappend (ins, scc_suffix[ins->vex.scc]);
10878
10879
        /* For SCC insns, the ND bit is required to be set to 0.  */
10880
1.41k
        if (ins->vex.nd)
10881
1.05k
    oappend (ins, "(bad)");
10882
10883
        /* These bits have been consumed and should be cleared or restored
10884
     to default values.  */
10885
1.41k
        ins->vex.v = 1;
10886
1.41k
        ins->vex.nf = false;
10887
1.41k
        ins->vex.mask_register_specifier = 0;
10888
1.41k
        break;
10889
1.41k
      }
10890
10891
7.52k
    if (l)
10892
0
      abort ();
10893
7.52k
    if (ins->intel_syntax && !alt)
10894
0
      break;
10895
7.52k
    if ((ins->prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
10896
1.43k
      {
10897
1.43k
        if (sizeflag & DFLAG)
10898
561
    *ins->obufp++ = ins->intel_syntax ? 'd' : 'l';
10899
877
        else
10900
877
    *ins->obufp++ = ins->intel_syntax ? 'w' : 's';
10901
1.43k
        ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10902
1.43k
      }
10903
7.52k
    break;
10904
80.9k
  case 'D':
10905
80.9k
    if (l == 1)
10906
7.51k
      {
10907
7.51k
        switch (last[0])
10908
7.51k
        {
10909
7.51k
        case 'X':
10910
7.51k
    if (!ins->vex.evex || ins->vex.w)
10911
6.72k
      *ins->obufp++ = 'd';
10912
793
    else
10913
793
      oappend (ins, "{bad}");
10914
7.51k
    break;
10915
0
        default:
10916
0
    abort ();
10917
7.51k
        }
10918
7.51k
        break;
10919
7.51k
      }
10920
73.3k
    if (l)
10921
0
      abort ();
10922
73.3k
    if (ins->intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
10923
72.2k
      break;
10924
1.09k
    USED_REX (REX_W);
10925
1.09k
    if (ins->modrm.mod == 3)
10926
680
      {
10927
680
        if (ins->rex & REX_W)
10928
236
    *ins->obufp++ = 'q';
10929
444
        else
10930
444
    {
10931
444
      if (sizeflag & DFLAG)
10932
190
        *ins->obufp++ = ins->intel_syntax ? 'd' : 'l';
10933
254
      else
10934
254
        *ins->obufp++ = 'w';
10935
444
      ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10936
444
    }
10937
680
      }
10938
414
    else
10939
414
      *ins->obufp++ = 'w';
10940
1.09k
    break;
10941
101k
  case 'E':
10942
101k
    if (l == 1)
10943
49.8k
      {
10944
49.8k
        switch (last[0])
10945
49.8k
    {
10946
684
    case 'M':
10947
684
      if (ins->modrm.mod != 3)
10948
437
        break;
10949
    /* Fall through.  */
10950
48.0k
    case 'X':
10951
48.0k
      if (!ins->vex.evex || ins->vex.b || ins->vex.ll >= 2
10952
48.0k
          || (ins->rex2 & 7)
10953
48.0k
          || (ins->modrm.mod == 3 && (ins->rex & REX_X))
10954
48.0k
          || !ins->vex.v || ins->vex.mask_register_specifier)
10955
45.4k
        break;
10956
      /* AVX512 extends a number of V*D insns to also have V*Q variants,
10957
         merely distinguished by EVEX.W.  Look for a use of the
10958
         respective macro.  */
10959
2.59k
      if (ins->vex.w)
10960
1.87k
        {
10961
1.87k
          const char *pct = strchr (p + 1, '%');
10962
10963
1.87k
          if (pct != NULL && pct[1] == 'D' && pct[2] == 'Q')
10964
200
      break;
10965
1.87k
        }
10966
2.39k
      *ins->obufp++ = '{';
10967
2.39k
      *ins->obufp++ = 'e';
10968
2.39k
      *ins->obufp++ = 'v';
10969
2.39k
      *ins->obufp++ = 'e';
10970
2.39k
      *ins->obufp++ = 'x';
10971
2.39k
      *ins->obufp++ = '}';
10972
2.39k
      *ins->obufp++ = ' ';
10973
2.39k
      break;
10974
1.41k
    case 'N':
10975
      /* Skip printing {evex} for some special instructions in MAP4.  */
10976
1.41k
      evex_printed = true;
10977
1.41k
      break;
10978
0
    default:
10979
0
      abort ();
10980
49.8k
    }
10981
49.8k
    break;
10982
49.8k
      }
10983
    /* For jcxz/jecxz */
10984
52.0k
    if (ins->address_mode == mode_64bit)
10985
33.6k
      {
10986
33.6k
        if (sizeflag & AFLAG)
10987
33.1k
    *ins->obufp++ = 'r';
10988
454
        else
10989
454
    *ins->obufp++ = 'e';
10990
33.6k
      }
10991
18.4k
    else
10992
18.4k
      if (sizeflag & AFLAG)
10993
17.4k
        *ins->obufp++ = 'e';
10994
52.0k
    ins->used_prefixes |= (ins->prefixes & PREFIX_ADDR);
10995
52.0k
    break;
10996
583k
  case 'F':
10997
583k
    if (l == 0)
10998
157k
      {
10999
157k
        if (ins->intel_syntax)
11000
6.62k
    break;
11001
150k
        if ((ins->prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
11002
800
    {
11003
800
      if (sizeflag & AFLAG)
11004
291
        *ins->obufp++ = ins->address_mode == mode_64bit ? 'q' : 'l';
11005
509
      else
11006
509
        *ins->obufp++ = ins->address_mode == mode_64bit ? 'l' : 'w';
11007
800
      ins->used_prefixes |= (ins->prefixes & PREFIX_ADDR);
11008
800
    }
11009
150k
      }
11010
426k
    else if (l == 1 && last[0] == 'C')
11011
2.09k
      {
11012
2.09k
        if (ins->vex.nd && !ins->vex.nf)
11013
655
    break;
11014
1.44k
        *ins->obufp++ = 'c';
11015
1.44k
        *ins->obufp++ = 'f';
11016
        /* Skip printing {evex} */
11017
1.44k
        evex_printed = true;
11018
1.44k
      }
11019
424k
    else if (l == 1 && last[0] == 'N')
11020
422k
      {
11021
422k
        if (ins->vex.nf)
11022
4.43k
    {
11023
4.43k
      oappend (ins, "{nf} ");
11024
      /* This bit needs to be cleared after it is consumed.  */
11025
4.43k
      ins->vex.nf = false;
11026
4.43k
      evex_printed = true;
11027
4.43k
    }
11028
418k
        else if (ins->evex_type == evex_from_vex && !(ins->rex2 & 7)
11029
418k
           && ins->vex.v)
11030
229
    {
11031
229
      oappend (ins, "{evex} ");
11032
229
      evex_printed = true;
11033
229
    }
11034
422k
      }
11035
1.41k
    else if (l == 1 && last[0] == 'D')
11036
1.41k
      {
11037
        /* Get oszc flags value from register_specifier.  */
11038
1.41k
        int oszc_value = ~ins->vex.register_specifier & 0xf;
11039
11040
        /* Add {dfv=of, sf, zf, cf} flags.  */
11041
1.41k
        oappend (ins, oszc_flags[oszc_value]);
11042
11043
        /* These bits have been consumed and should be cleared.  */
11044
1.41k
        ins->vex.register_specifier = 0;
11045
1.41k
      }
11046
0
    else
11047
0
      abort ();
11048
576k
    break;
11049
576k
  case 'G':
11050
368k
    if (ins->intel_syntax || (ins->obufp[-1] != 's'
11051
361k
            && !(sizeflag & SUFFIX_ALWAYS)))
11052
139k
      break;
11053
229k
    if ((ins->rex & REX_W) || (sizeflag & DFLAG))
11054
222k
      *ins->obufp++ = 'l';
11055
7.28k
    else
11056
7.28k
      *ins->obufp++ = 'w';
11057
229k
    if (!(ins->rex & REX_W))
11058
225k
      ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11059
229k
    break;
11060
3.52M
  case 'H':
11061
3.52M
    if (l == 0)
11062
3.51M
      {
11063
3.51M
        if (ins->intel_syntax)
11064
40.4k
          break;
11065
3.47M
        if ((ins->prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
11066
3.47M
      || (ins->prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
11067
37.8k
    {
11068
37.8k
      ins->used_prefixes |= ins->prefixes & (PREFIX_CS | PREFIX_DS);
11069
37.8k
      *ins->obufp++ = ',';
11070
37.8k
      *ins->obufp++ = 'p';
11071
11072
      /* Set active_seg_prefix even if not set in 64-bit mode
11073
         because here it is a valid branch hint. */
11074
37.8k
      if (ins->prefixes & PREFIX_DS)
11075
3.12k
        {
11076
3.12k
          ins->active_seg_prefix = PREFIX_DS;
11077
3.12k
          *ins->obufp++ = 't';
11078
3.12k
        }
11079
34.7k
      else
11080
34.7k
        {
11081
34.7k
          ins->active_seg_prefix = PREFIX_CS;
11082
34.7k
          *ins->obufp++ = 'n';
11083
34.7k
        }
11084
37.8k
    }
11085
3.47M
      }
11086
13.7k
    else if (l == 1 && last[0] == 'X')
11087
13.7k
      {
11088
13.7k
        if (!ins->vex.w)
11089
6.71k
    *ins->obufp++ = 'h';
11090
7.06k
        else
11091
7.06k
    oappend (ins, "{bad}");
11092
13.7k
      }
11093
0
    else
11094
0
      abort ();
11095
3.48M
    break;
11096
3.48M
  case 'K':
11097
1.96k
    USED_REX (REX_W);
11098
1.96k
    if (ins->rex & REX_W)
11099
743
      *ins->obufp++ = 'q';
11100
1.22k
    else
11101
1.22k
      *ins->obufp++ = 'd';
11102
1.96k
    break;
11103
1.07k
  case 'L':
11104
1.07k
    if (ins->intel_syntax)
11105
266
      break;
11106
812
    if (sizeflag & SUFFIX_ALWAYS)
11107
444
      {
11108
444
        if (ins->rex & REX_W)
11109
190
    *ins->obufp++ = 'q';
11110
254
        else
11111
254
    *ins->obufp++ = 'l';
11112
444
      }
11113
812
    break;
11114
8.68k
  case 'M':
11115
8.68k
    if (ins->intel_mnemonic != cond)
11116
5.65k
      *ins->obufp++ = 'r';
11117
8.68k
    break;
11118
14.5k
  case 'N':
11119
14.5k
    if ((ins->prefixes & PREFIX_FWAIT) == 0)
11120
14.1k
      *ins->obufp++ = 'n';
11121
402
    else
11122
402
      ins->used_prefixes |= PREFIX_FWAIT;
11123
14.5k
    break;
11124
45.7k
  case 'O':
11125
45.7k
    USED_REX (REX_W);
11126
45.7k
    if (ins->rex & REX_W)
11127
2.13k
      *ins->obufp++ = 'o';
11128
43.6k
    else if (ins->intel_syntax && (sizeflag & DFLAG))
11129
3.10k
      *ins->obufp++ = 'q';
11130
40.5k
    else
11131
40.5k
      *ins->obufp++ = 'd';
11132
45.7k
    if (!(ins->rex & REX_W))
11133
43.6k
      ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11134
45.7k
    break;
11135
1.36M
  case '@':
11136
1.36M
    if (ins->address_mode == mode_64bit
11137
1.36M
        && (ins->isa64 == intel64 || (ins->rex & REX_W)
11138
1.22M
      || !(ins->prefixes & PREFIX_DATA)))
11139
1.22M
      {
11140
1.22M
        if (sizeflag & SUFFIX_ALWAYS)
11141
374
    *ins->obufp++ = 'q';
11142
1.22M
        break;
11143
1.22M
      }
11144
    /* Fall through.  */
11145
4.38M
  case 'P':
11146
4.38M
    if (l == 0)
11147
4.27M
      {
11148
4.27M
        if (!cond && ins->last_rex2_prefix >= 0 && (ins->rex & REX_W))
11149
527
    {
11150
      /* For pushp and popp, p is printed and do not print {rex2}
11151
         for them.  */
11152
527
      *ins->obufp++ = 'p';
11153
527
      ins->rex2 |= REX2_SPECIAL;
11154
527
      break;
11155
527
    }
11156
11157
        /* For "!P" print nothing else in Intel syntax.  */
11158
4.27M
        if (!cond && ins->intel_syntax)
11159
35.2k
    break;
11160
11161
4.24M
        if ((ins->modrm.mod == 3 || !cond)
11162
4.24M
      && !(sizeflag & SUFFIX_ALWAYS))
11163
2.54M
    break;
11164
    /* Fall through.  */
11165
1.69M
  case 'T':
11166
1.69M
        if ((!(ins->rex & REX_W) && (ins->prefixes & PREFIX_DATA))
11167
1.69M
      || ((sizeflag & SUFFIX_ALWAYS)
11168
1.68M
          && ins->address_mode != mode_64bit))
11169
7.46k
    {
11170
7.46k
      *ins->obufp++ = (sizeflag & DFLAG)
11171
7.46k
          ? ins->intel_syntax ? 'd' : 'l' : 'w';
11172
7.46k
      ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11173
7.46k
    }
11174
1.68M
        else if (sizeflag & SUFFIX_ALWAYS)
11175
418
    *ins->obufp++ = 'q';
11176
1.69M
      }
11177
104k
    else if (l == 1 && last[0] == 'L')
11178
104k
      {
11179
104k
        if ((ins->prefixes & PREFIX_DATA)
11180
104k
      || (ins->rex & REX_W)
11181
104k
      || (sizeflag & SUFFIX_ALWAYS))
11182
5.60k
    {
11183
5.60k
      USED_REX (REX_W);
11184
5.60k
      if (ins->rex & REX_W)
11185
4.04k
        *ins->obufp++ = 'q';
11186
1.55k
      else
11187
1.55k
        {
11188
1.55k
          if (sizeflag & DFLAG)
11189
266
      *ins->obufp++ = ins->intel_syntax ? 'd' : 'l';
11190
1.29k
          else
11191
1.29k
      *ins->obufp++ = 'w';
11192
1.55k
          ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11193
1.55k
        }
11194
5.60k
    }
11195
104k
      }
11196
0
    else
11197
0
      abort ();
11198
1.79M
    break;
11199
2.07M
  case 'Q':
11200
2.07M
    if (l == 0)
11201
2.05M
      {
11202
2.05M
        if (ins->intel_syntax && !alt)
11203
20.1k
    break;
11204
2.03M
        USED_REX (REX_W);
11205
2.03M
        if ((ins->need_modrm && ins->modrm.mod != 3 && !ins->vex.nd)
11206
2.03M
      || (sizeflag & SUFFIX_ALWAYS))
11207
952k
    {
11208
952k
      if (ins->rex & REX_W)
11209
56.7k
        *ins->obufp++ = 'q';
11210
895k
      else
11211
895k
        {
11212
895k
          if (sizeflag & DFLAG)
11213
841k
      *ins->obufp++ = ins->intel_syntax ? 'd' : 'l';
11214
54.1k
          else
11215
54.1k
      *ins->obufp++ = 'w';
11216
895k
          ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11217
895k
        }
11218
952k
    }
11219
2.03M
      }
11220
13.0k
    else if (l == 1 && last[0] == 'D')
11221
7.52k
      *ins->obufp++ = ins->vex.w ? 'q' : 'd';
11222
5.50k
    else if (l == 1 && last[0] == 'L')
11223
5.50k
      {
11224
5.50k
        if (cond ? ins->modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)
11225
5.50k
           : ins->address_mode != mode_64bit)
11226
1.45k
    break;
11227
4.05k
        if ((ins->rex & REX_W))
11228
1.33k
    {
11229
1.33k
      USED_REX (REX_W);
11230
1.33k
      *ins->obufp++ = 'q';
11231
1.33k
    }
11232
2.71k
        else if ((ins->address_mode == mode_64bit && cond)
11233
2.71k
          || (sizeflag & SUFFIX_ALWAYS))
11234
1.35k
    *ins->obufp++ = ins->intel_syntax? 'd' : 'l';
11235
4.05k
      }
11236
0
    else
11237
0
      abort ();
11238
2.04M
    break;
11239
2.04M
  case 'R':
11240
477k
    USED_REX (REX_W);
11241
477k
    if (ins->rex & REX_W)
11242
8.79k
      *ins->obufp++ = 'q';
11243
469k
    else if (sizeflag & DFLAG)
11244
455k
      {
11245
455k
        if (ins->intel_syntax)
11246
7.23k
      *ins->obufp++ = 'd';
11247
448k
        else
11248
448k
      *ins->obufp++ = 'l';
11249
455k
      }
11250
13.3k
    else
11251
13.3k
      *ins->obufp++ = 'w';
11252
477k
    if (ins->intel_syntax && !p[1]
11253
477k
        && ((ins->rex & REX_W) || (sizeflag & DFLAG)))
11254
4.46k
      *ins->obufp++ = 'e';
11255
477k
    if (!(ins->rex & REX_W))
11256
469k
      ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11257
477k
    break;
11258
11.0M
  case 'S':
11259
11.0M
    if (l == 0)
11260
10.8M
      {
11261
11.6M
      case_S:
11262
11.6M
        if (ins->intel_syntax)
11263
105k
    break;
11264
11.5M
        if (sizeflag & SUFFIX_ALWAYS)
11265
1.43k
    {
11266
1.43k
      if (ins->rex & REX_W)
11267
654
        *ins->obufp++ = 'q';
11268
782
      else
11269
782
        {
11270
782
          if (sizeflag & DFLAG)
11271
450
      *ins->obufp++ = 'l';
11272
332
          else
11273
332
      *ins->obufp++ = 'w';
11274
782
          ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11275
782
        }
11276
1.43k
    }
11277
11.5M
        break;
11278
11.6M
      }
11279
114k
    if (l != 1)
11280
0
      abort ();
11281
114k
    switch (last[0])
11282
114k
      {
11283
109k
      case 'L':
11284
109k
        if (ins->address_mode == mode_64bit
11285
109k
      && !(ins->prefixes & PREFIX_ADDR))
11286
42.1k
    {
11287
42.1k
      *ins->obufp++ = 'a';
11288
42.1k
      *ins->obufp++ = 'b';
11289
42.1k
      *ins->obufp++ = 's';
11290
42.1k
    }
11291
11292
109k
        goto case_S;
11293
5.05k
      case 'X':
11294
5.05k
        if (!ins->vex.evex || !ins->vex.w)
11295
3.78k
    *ins->obufp++ = 's';
11296
1.27k
        else
11297
1.27k
    oappend (ins, "{bad}");
11298
5.05k
        break;
11299
0
      default:
11300
0
        abort ();
11301
114k
      }
11302
5.05k
    break;
11303
5.05k
  case 'U':
11304
4.57k
    if (l == 1 && (last[0] == 'Z'))
11305
4.57k
      {
11306
        /* Although IMUL/SETcc does not support NDD, the EVEX.ND bit is
11307
     used to control whether its destination register has its upper
11308
     bits zeroed.  */
11309
4.57k
        if (ins->vex.nd)
11310
2.81k
    oappend (ins, "zu");
11311
4.57k
      }
11312
0
    else
11313
0
      abort ();
11314
4.57k
    break;
11315
632k
  case 'V':
11316
632k
    if (l == 0)
11317
27.6k
      {
11318
27.6k
        if (ins->need_vex)
11319
8.18k
    *ins->obufp++ = 'v';
11320
27.6k
      }
11321
604k
    else if (l == 1)
11322
604k
      {
11323
604k
        switch (last[0])
11324
604k
    {
11325
442
    case 'X':
11326
442
      if (ins->vex.evex)
11327
244
        break;
11328
198
      *ins->obufp++ = '{';
11329
198
      *ins->obufp++ = 'v';
11330
198
      *ins->obufp++ = 'e';
11331
198
      *ins->obufp++ = 'x';
11332
198
      *ins->obufp++ = '}';
11333
198
      *ins->obufp++ = ' ';
11334
198
      break;
11335
604k
    case 'L':
11336
604k
      if (ins->rex & REX_W)
11337
11.7k
        {
11338
11.7k
          *ins->obufp++ = 'a';
11339
11.7k
          *ins->obufp++ = 'b';
11340
11.7k
          *ins->obufp++ = 's';
11341
11.7k
        }
11342
604k
      goto case_S;
11343
0
    default:
11344
0
      abort ();
11345
604k
    }
11346
604k
      }
11347
0
    else
11348
0
      abort ();
11349
28.1k
    break;
11350
64.3k
  case 'W':
11351
64.3k
    if (l == 0)
11352
54.0k
      {
11353
        /* operand size flag for cwtl, cbtw */
11354
54.0k
        USED_REX (REX_W);
11355
54.0k
        if (ins->rex & REX_W)
11356
5.33k
    {
11357
5.33k
      if (ins->intel_syntax)
11358
330
        *ins->obufp++ = 'd';
11359
5.00k
      else
11360
5.00k
        *ins->obufp++ = 'l';
11361
5.33k
    }
11362
48.6k
        else if (sizeflag & DFLAG)
11363
46.5k
    *ins->obufp++ = 'w';
11364
2.13k
        else
11365
2.13k
    *ins->obufp++ = 'b';
11366
54.0k
        if (!(ins->rex & REX_W))
11367
48.6k
    ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11368
54.0k
      }
11369
10.3k
    else if (l == 1)
11370
10.3k
      {
11371
10.3k
        if (!ins->need_vex)
11372
0
    abort ();
11373
10.3k
        if (last[0] == 'X')
11374
7.73k
    *ins->obufp++ = ins->vex.w ? 'd': 's';
11375
2.56k
        else if (last[0] == 'B')
11376
2.56k
    *ins->obufp++ = ins->vex.w ? 'w': 'b';
11377
0
        else
11378
0
    abort ();
11379
10.3k
      }
11380
0
    else
11381
0
      abort ();
11382
64.3k
    break;
11383
64.3k
  case 'X':
11384
34.6k
    if (l != 0)
11385
0
      abort ();
11386
34.6k
    if (ins->need_vex
11387
34.6k
        ? ins->vex.prefix == DATA_PREFIX_OPCODE
11388
34.6k
        : ins->prefixes & PREFIX_DATA)
11389
3.39k
      {
11390
3.39k
        *ins->obufp++ = 'd';
11391
3.39k
        ins->used_prefixes |= PREFIX_DATA;
11392
3.39k
      }
11393
31.2k
    else
11394
31.2k
      *ins->obufp++ = 's';
11395
34.6k
    break;
11396
11.5k
  case 'Y':
11397
11.5k
    if (l == 0)
11398
7.90k
      {
11399
7.90k
        if (ins->vex.mask_register_specifier)
11400
2.98k
    ins->illegal_masking = true;
11401
7.90k
      }
11402
3.66k
    else if (l == 1 && last[0] == 'X')
11403
3.66k
      {
11404
3.66k
        if (!ins->need_vex)
11405
419
    break;
11406
3.25k
        if (ins->intel_syntax
11407
3.25k
      || ((ins->modrm.mod == 3 || ins->vex.b)
11408
2.41k
          && !(sizeflag & SUFFIX_ALWAYS)))
11409
2.14k
    break;
11410
1.10k
        switch (ins->vex.length)
11411
1.10k
    {
11412
386
    case 128:
11413
386
      *ins->obufp++ = 'x';
11414
386
      break;
11415
490
    case 256:
11416
490
      *ins->obufp++ = 'y';
11417
490
      break;
11418
226
    case 512:
11419
226
      if (!ins->vex.evex)
11420
0
    default:
11421
0
        abort ();
11422
1.10k
    }
11423
1.10k
      }
11424
0
    else
11425
0
      abort ();
11426
9.00k
    break;
11427
9.64k
  case 'Z':
11428
9.64k
    if (l == 0)
11429
6.77k
      {
11430
        /* These insns ignore ModR/M.mod: Force it to 3 for OP_E().  */
11431
6.77k
        ins->modrm.mod = 3;
11432
6.77k
        if (!ins->intel_syntax && (sizeflag & SUFFIX_ALWAYS))
11433
194
    *ins->obufp++ = ins->address_mode == mode_64bit ? 'q' : 'l';
11434
6.77k
      }
11435
2.87k
    else if (l == 1 && last[0] == 'X')
11436
2.87k
      {
11437
2.87k
        if (!ins->vex.evex)
11438
0
    abort ();
11439
2.87k
        if (ins->intel_syntax
11440
2.87k
      || ((ins->modrm.mod == 3 || ins->vex.b)
11441
2.26k
          && !(sizeflag & SUFFIX_ALWAYS)))
11442
1.67k
    break;
11443
1.20k
        switch (ins->vex.length)
11444
1.20k
    {
11445
226
    case 128:
11446
226
      *ins->obufp++ = 'x';
11447
226
      break;
11448
396
    case 256:
11449
396
      *ins->obufp++ = 'y';
11450
396
      break;
11451
579
    case 512:
11452
579
      *ins->obufp++ = 'z';
11453
579
      break;
11454
0
    default:
11455
0
      abort ();
11456
1.20k
    }
11457
1.20k
      }
11458
0
    else
11459
0
      abort ();
11460
7.97k
    break;
11461
96.9k
  case '^':
11462
96.9k
    if (ins->intel_syntax)
11463
4.22k
      break;
11464
92.7k
    if (ins->isa64 == intel64 && (ins->rex & REX_W))
11465
312
      {
11466
312
        USED_REX (REX_W);
11467
312
        *ins->obufp++ = 'q';
11468
312
        break;
11469
312
      }
11470
92.4k
    if ((ins->prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
11471
1.21k
      {
11472
1.21k
        if (sizeflag & DFLAG)
11473
463
    *ins->obufp++ = 'l';
11474
753
        else
11475
753
    *ins->obufp++ = 'w';
11476
1.21k
        ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11477
1.21k
      }
11478
92.4k
    break;
11479
179M
  }
11480
11481
179M
      if (len == l)
11482
177M
  len = l = 0;
11483
179M
    }
11484
40.8M
  *ins->obufp = 0;
11485
40.8M
  ins->mnemonicendp = ins->obufp;
11486
40.8M
  return 0;
11487
40.8M
}
11488
11489
/* Add a style marker to *INS->obufp that encodes STYLE.  This assumes that
11490
   the buffer pointed to by INS->obufp has space.  A style marker is made
11491
   from the STYLE_MARKER_CHAR followed by STYLE converted to a single hex
11492
   digit, followed by another STYLE_MARKER_CHAR.  This function assumes
11493
   that the number of styles is not greater than 16.  */
11494
11495
static void
11496
oappend_insert_style (instr_info *ins, enum disassembler_style style)
11497
131M
{
11498
131M
  unsigned num = (unsigned) style;
11499
11500
  /* We currently assume that STYLE can be encoded as a single hex
11501
     character.  If more styles are added then this might start to fail,
11502
     and we'll need to expand this code.  */
11503
131M
  if (num > 0xf)
11504
0
    abort ();
11505
11506
131M
  *ins->obufp++ = STYLE_MARKER_CHAR;
11507
131M
  *ins->obufp++ = (num < 10 ? ('0' + num)
11508
131M
       : ((num < 16) ? ('a' + (num - 10)) : '0'));
11509
131M
  *ins->obufp++ = STYLE_MARKER_CHAR;
11510
11511
  /* This final null character is not strictly necessary, after inserting a
11512
     style marker we should always be inserting some additional content.
11513
     However, having the buffer null terminated doesn't cost much, and make
11514
     it easier to debug what's going on.  Also, if we do ever forget to add
11515
     any additional content after this style marker, then the buffer will
11516
     still be well formed.  */
11517
131M
  *ins->obufp = '\0';
11518
131M
}
11519
11520
static void
11521
oappend_with_style (instr_info *ins, const char *s,
11522
        enum disassembler_style style)
11523
80.1M
{
11524
80.1M
  oappend_insert_style (ins, style);
11525
80.1M
  ins->obufp = stpcpy (ins->obufp, s);
11526
80.1M
}
11527
11528
/* Add a single character C to the buffer pointer to by INS->obufp, marking
11529
   the style for the character as STYLE.  */
11530
11531
static void
11532
oappend_char_with_style (instr_info *ins, const char c,
11533
       enum disassembler_style style)
11534
51.5M
{
11535
51.5M
  oappend_insert_style (ins, style);
11536
51.5M
  *ins->obufp++ = c;
11537
51.5M
  *ins->obufp = '\0';
11538
51.5M
}
11539
11540
/* Like oappend_char_with_style, but always uses dis_style_text.  */
11541
11542
static void
11543
oappend_char (instr_info *ins, const char c)
11544
42.8M
{
11545
42.8M
  oappend_char_with_style (ins, c, dis_style_text);
11546
42.8M
}
11547
11548
static void
11549
append_seg (instr_info *ins)
11550
20.2M
{
11551
  /* Only print the active segment register.  */
11552
20.2M
  if (!ins->active_seg_prefix)
11553
19.7M
    return;
11554
11555
516k
  ins->used_prefixes |= ins->active_seg_prefix;
11556
516k
  switch (ins->active_seg_prefix)
11557
516k
    {
11558
19.7k
    case PREFIX_CS:
11559
19.7k
      oappend_register (ins, att_names_seg[1]);
11560
19.7k
      break;
11561
251k
    case PREFIX_DS:
11562
251k
      oappend_register (ins, att_names_seg[3]);
11563
251k
      break;
11564
6.29k
    case PREFIX_SS:
11565
6.29k
      oappend_register (ins, att_names_seg[2]);
11566
6.29k
      break;
11567
7.03k
    case PREFIX_ES:
11568
7.03k
      oappend_register (ins, att_names_seg[0]);
11569
7.03k
      break;
11570
93.2k
    case PREFIX_FS:
11571
93.2k
      oappend_register (ins, att_names_seg[4]);
11572
93.2k
      break;
11573
139k
    case PREFIX_GS:
11574
139k
      oappend_register (ins, att_names_seg[5]);
11575
139k
      break;
11576
0
    default:
11577
0
      break;
11578
516k
    }
11579
516k
  oappend_char (ins, ':');
11580
516k
}
11581
11582
static void
11583
print_operand_value (instr_info *ins, bfd_vma disp,
11584
         enum disassembler_style style)
11585
11.5M
{
11586
11.5M
  char tmp[30];
11587
11588
11.5M
  if (ins->address_mode != mode_64bit)
11589
3.96M
    disp &= 0xffffffff;
11590
11.5M
  sprintf (tmp, "0x%" PRIx64, (uint64_t) disp);
11591
11.5M
  oappend_with_style (ins, tmp, style);
11592
11.5M
}
11593
11594
/* Like oappend, but called for immediate operands.  */
11595
11596
static void
11597
oappend_immediate (instr_info *ins, bfd_vma imm)
11598
5.95M
{
11599
5.95M
  if (!ins->intel_syntax)
11600
5.88M
    oappend_char_with_style (ins, '$', dis_style_immediate);
11601
5.95M
  print_operand_value (ins, imm, dis_style_immediate);
11602
5.95M
}
11603
11604
/* Put DISP in BUF as signed hex number.  */
11605
11606
static void
11607
print_displacement (instr_info *ins, bfd_signed_vma val)
11608
7.14M
{
11609
7.14M
  char tmp[30];
11610
11611
7.14M
  if (val < 0)
11612
1.61M
    {
11613
1.61M
      oappend_char_with_style (ins, '-', dis_style_address_offset);
11614
1.61M
      val = (bfd_vma) 0 - val;
11615
11616
      /* Check for possible overflow.  */
11617
1.61M
      if (val < 0)
11618
0
  {
11619
0
    switch (ins->address_mode)
11620
0
      {
11621
0
      case mode_64bit:
11622
0
        oappend_with_style (ins, "0x8000000000000000",
11623
0
          dis_style_address_offset);
11624
0
        break;
11625
0
      case mode_32bit:
11626
0
        oappend_with_style (ins, "0x80000000",
11627
0
          dis_style_address_offset);
11628
0
        break;
11629
0
      case mode_16bit:
11630
0
        oappend_with_style (ins, "0x8000",
11631
0
          dis_style_address_offset);
11632
0
        break;
11633
0
      }
11634
0
    return;
11635
0
  }
11636
1.61M
    }
11637
11638
7.14M
  sprintf (tmp, "0x%" PRIx64, (int64_t) val);
11639
7.14M
  oappend_with_style (ins, tmp, dis_style_address_offset);
11640
7.14M
}
11641
11642
static void
11643
intel_operand_size (instr_info *ins, int bytemode, int sizeflag)
11644
383k
{
11645
  /* Check if there is a broadcast, when evex.b is not treated as evex.nd.  */
11646
383k
  if (ins->vex.b && ins->evex_type == evex_default)
11647
5.71k
    {
11648
5.71k
      if (!ins->vex.no_broadcast)
11649
5.29k
  switch (bytemode)
11650
5.29k
    {
11651
1.65k
    case x_mode:
11652
2.20k
    case evex_half_bcst_xmmq_mode:
11653
2.20k
      if (ins->vex.w)
11654
1.17k
        oappend (ins, "QWORD BCST ");
11655
1.03k
      else
11656
1.03k
        oappend (ins, "DWORD BCST ");
11657
2.20k
      break;
11658
1.02k
    case xh_mode:
11659
1.30k
    case evex_half_bcst_xmmqh_mode:
11660
1.63k
    case evex_half_bcst_xmmqdh_mode:
11661
1.63k
      oappend (ins, "WORD BCST ");
11662
1.63k
      break;
11663
1.44k
    default:
11664
1.44k
      ins->vex.no_broadcast = true;
11665
1.44k
      break;
11666
5.29k
    }
11667
5.71k
      return;
11668
5.71k
    }
11669
377k
  switch (bytemode)
11670
377k
    {
11671
202k
    case b_mode:
11672
213k
    case b_swap_mode:
11673
214k
    case db_mode:
11674
214k
      oappend (ins, "BYTE PTR ");
11675
214k
      break;
11676
5.64k
    case w_mode:
11677
5.84k
    case w_swap_mode:
11678
6.31k
    case dw_mode:
11679
6.31k
      oappend (ins, "WORD PTR ");
11680
6.31k
      break;
11681
6.66k
    case indir_v_mode:
11682
6.66k
      if (ins->address_mode == mode_64bit && ins->isa64 == intel64)
11683
194
  {
11684
194
    oappend (ins, "QWORD PTR ");
11685
194
    break;
11686
194
  }
11687
      /* Fall through.  */
11688
9.03k
    case stack_v_mode:
11689
9.03k
      if (ins->address_mode == mode_64bit && ((sizeflag & DFLAG)
11690
6.74k
                || (ins->rex & REX_W)))
11691
5.84k
  {
11692
5.84k
    oappend (ins, "QWORD PTR ");
11693
5.84k
    break;
11694
5.84k
  }
11695
      /* Fall through.  */
11696
64.1k
    case v_mode:
11697
84.7k
    case v_swap_mode:
11698
86.3k
    case dq_mode:
11699
86.3k
      USED_REX (REX_W);
11700
86.3k
      if (ins->rex & REX_W)
11701
3.77k
  oappend (ins, "QWORD PTR ");
11702
82.5k
      else if (bytemode == dq_mode)
11703
1.11k
  oappend (ins, "DWORD PTR ");
11704
81.4k
      else
11705
81.4k
  {
11706
81.4k
    if (sizeflag & DFLAG)
11707
77.6k
      oappend (ins, "DWORD PTR ");
11708
3.77k
    else
11709
3.77k
      oappend (ins, "WORD PTR ");
11710
81.4k
    ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11711
81.4k
  }
11712
86.3k
      break;
11713
10.3k
    case z_mode:
11714
10.3k
      if ((ins->rex & REX_W) || (sizeflag & DFLAG))
11715
8.31k
  *ins->obufp++ = 'D';
11716
10.3k
      oappend (ins, "WORD PTR ");
11717
10.3k
      if (!(ins->rex & REX_W))
11718
9.69k
  ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11719
10.3k
      break;
11720
3.88k
    case a_mode:
11721
3.88k
      if (sizeflag & DFLAG)
11722
3.04k
  oappend (ins, "QWORD PTR ");
11723
847
      else
11724
847
  oappend (ins, "DWORD PTR ");
11725
3.88k
      ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11726
3.88k
      break;
11727
2.29k
    case movsxd_mode:
11728
2.29k
      if (!(sizeflag & DFLAG) && ins->isa64 == intel64)
11729
192
  oappend (ins, "WORD PTR ");
11730
2.10k
      else
11731
2.10k
  oappend (ins, "DWORD PTR ");
11732
2.29k
      ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11733
2.29k
      break;
11734
2.49k
    case d_mode:
11735
2.75k
    case d_swap_mode:
11736
2.75k
      oappend (ins, "DWORD PTR ");
11737
2.75k
      break;
11738
12.2k
    case q_mode:
11739
12.5k
    case q_swap_mode:
11740
12.5k
      oappend (ins, "QWORD PTR ");
11741
12.5k
      break;
11742
419
    case m_mode:
11743
419
      if (ins->address_mode == mode_64bit)
11744
206
  oappend (ins, "QWORD PTR ");
11745
213
      else
11746
213
  oappend (ins, "DWORD PTR ");
11747
419
      break;
11748
3.61k
    case f_mode:
11749
3.61k
      if (sizeflag & DFLAG)
11750
3.05k
  oappend (ins, "FWORD PTR ");
11751
568
      else
11752
568
  oappend (ins, "DWORD PTR ");
11753
3.61k
      ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11754
3.61k
      break;
11755
594
    case t_mode:
11756
594
      oappend (ins, "TBYTE PTR ");
11757
594
      break;
11758
8.63k
    case x_mode:
11759
9.57k
    case xh_mode:
11760
10.4k
    case x_swap_mode:
11761
10.7k
    case evex_x_gscat_mode:
11762
11.1k
    case evex_x_nobcst_mode:
11763
11.6k
    case bw_unit_mode:
11764
11.6k
      if (ins->need_vex)
11765
8.10k
  {
11766
8.10k
    switch (ins->vex.length)
11767
8.10k
      {
11768
4.06k
      case 128:
11769
4.06k
        oappend (ins, "XMMWORD PTR ");
11770
4.06k
        break;
11771
2.22k
      case 256:
11772
2.22k
        oappend (ins, "YMMWORD PTR ");
11773
2.22k
        break;
11774
1.81k
      case 512:
11775
1.81k
        oappend (ins, "ZMMWORD PTR ");
11776
1.81k
        break;
11777
0
      default:
11778
0
        abort ();
11779
8.10k
      }
11780
8.10k
  }
11781
3.59k
      else
11782
3.59k
  oappend (ins, "XMMWORD PTR ");
11783
11.6k
      break;
11784
11.6k
    case xmm_mode:
11785
376
      oappend (ins, "XMMWORD PTR ");
11786
376
      break;
11787
233
    case ymm_mode:
11788
233
      oappend (ins, "YMMWORD PTR ");
11789
233
      break;
11790
530
    case xmmq_mode:
11791
982
    case evex_half_bcst_xmmqh_mode:
11792
1.78k
    case evex_half_bcst_xmmq_mode:
11793
1.78k
      switch (ins->vex.length)
11794
1.78k
  {
11795
470
  case 0:
11796
811
  case 128:
11797
811
    oappend (ins, "QWORD PTR ");
11798
811
    break;
11799
495
  case 256:
11800
495
    oappend (ins, "XMMWORD PTR ");
11801
495
    break;
11802
480
  case 512:
11803
480
    oappend (ins, "YMMWORD PTR ");
11804
480
    break;
11805
0
  default:
11806
0
    abort ();
11807
1.78k
  }
11808
1.78k
      break;
11809
1.78k
    case xmmdw_mode:
11810
658
      if (!ins->need_vex)
11811
0
  abort ();
11812
11813
658
      switch (ins->vex.length)
11814
658
  {
11815
205
  case 128:
11816
205
    oappend (ins, "WORD PTR ");
11817
205
    break;
11818
242
  case 256:
11819
242
    oappend (ins, "DWORD PTR ");
11820
242
    break;
11821
211
  case 512:
11822
211
    oappend (ins, "QWORD PTR ");
11823
211
    break;
11824
0
  default:
11825
0
    abort ();
11826
658
  }
11827
658
      break;
11828
819
    case xmmqd_mode:
11829
1.04k
    case evex_half_bcst_xmmqdh_mode:
11830
1.04k
      if (!ins->need_vex)
11831
0
  abort ();
11832
11833
1.04k
      switch (ins->vex.length)
11834
1.04k
  {
11835
328
  case 128:
11836
328
    oappend (ins, "DWORD PTR ");
11837
328
    break;
11838
457
  case 256:
11839
457
    oappend (ins, "QWORD PTR ");
11840
457
    break;
11841
256
  case 512:
11842
256
    oappend (ins, "XMMWORD PTR ");
11843
256
    break;
11844
0
  default:
11845
0
    abort ();
11846
1.04k
  }
11847
1.04k
      break;
11848
1.44k
    case ymmq_mode:
11849
1.44k
      if (!ins->need_vex)
11850
0
  abort ();
11851
11852
1.44k
      switch (ins->vex.length)
11853
1.44k
  {
11854
660
  case 128:
11855
660
    oappend (ins, "QWORD PTR ");
11856
660
    break;
11857
515
  case 256:
11858
515
    oappend (ins, "YMMWORD PTR ");
11859
515
    break;
11860
271
  case 512:
11861
271
    oappend (ins, "ZMMWORD PTR ");
11862
271
    break;
11863
0
  default:
11864
0
    abort ();
11865
1.44k
  }
11866
1.44k
      break;
11867
1.44k
    case o_mode:
11868
283
      oappend (ins, "OWORD PTR ");
11869
283
      break;
11870
1.63k
    case vex_vsib_d_w_dq_mode:
11871
2.45k
    case vex_vsib_q_w_dq_mode:
11872
2.45k
      if (!ins->need_vex)
11873
0
  abort ();
11874
2.45k
      if (ins->vex.w)
11875
1.37k
  oappend (ins, "QWORD PTR ");
11876
1.07k
      else
11877
1.07k
  oappend (ins, "DWORD PTR ");
11878
2.45k
      break;
11879
1.41k
    case mask_bd_mode:
11880
1.41k
      if (!ins->need_vex || ins->vex.length != 128)
11881
0
  abort ();
11882
1.41k
      if (ins->vex.w)
11883
575
  oappend (ins, "DWORD PTR ");
11884
836
      else
11885
836
  oappend (ins, "BYTE PTR ");
11886
1.41k
      break;
11887
849
    case mask_mode:
11888
849
      if (!ins->need_vex)
11889
0
  abort ();
11890
849
      if (ins->vex.w)
11891
235
  oappend (ins, "QWORD PTR ");
11892
614
      else
11893
614
  oappend (ins, "WORD PTR ");
11894
849
      break;
11895
898
    case v_bnd_mode:
11896
1.75k
    case v_bndmk_mode:
11897
6.08k
    default:
11898
6.08k
      break;
11899
377k
    }
11900
377k
}
11901
11902
static void
11903
print_register (instr_info *ins, unsigned int reg, unsigned int rexmask,
11904
    int bytemode, int sizeflag)
11905
25.1M
{
11906
25.1M
  const char (*names)[8];
11907
11908
  /* Masking is invalid for insns with GPR destination. Set the flag uniformly,
11909
     as the consumer will inspect it only for the destination operand.  */
11910
25.1M
  if (bytemode != mask_mode && ins->vex.mask_register_specifier)
11911
9.15k
    ins->illegal_masking = true;
11912
11913
25.1M
  USED_REX (rexmask);
11914
25.1M
  if (ins->rex & rexmask)
11915
1.49M
    reg += 8;
11916
25.1M
  if (ins->rex2 & rexmask)
11917
20.9k
    reg += 16;
11918
11919
25.1M
  switch (bytemode)
11920
25.1M
    {
11921
12.6M
    case b_mode:
11922
12.7M
    case b_swap_mode:
11923
12.7M
      if (reg & 4)
11924
2.85M
  USED_REX (0);
11925
12.7M
      if (ins->rex || ins->rex2)
11926
353k
  names = att_names8rex;
11927
12.4M
      else
11928
12.4M
  names = att_names8;
11929
12.7M
      break;
11930
21.1k
    case w_mode:
11931
21.1k
      names = att_names16;
11932
21.1k
      break;
11933
10.5k
    case d_mode:
11934
11.3k
    case dw_mode:
11935
11.9k
    case db_mode:
11936
11.9k
      names = att_names32;
11937
11.9k
      break;
11938
2.39k
    case q_mode:
11939
2.39k
      names = att_names64;
11940
2.39k
      break;
11941
7.25k
    case m_mode:
11942
7.47k
    case v_bnd_mode:
11943
7.47k
      names = ins->address_mode == mode_64bit ? att_names64 : att_names32;
11944
7.47k
      break;
11945
8.01k
    case bnd_mode:
11946
9.34k
    case bnd_swap_mode:
11947
9.34k
      if (reg > 0x3)
11948
5.03k
  {
11949
5.03k
    oappend (ins, "(bad)");
11950
5.03k
    return;
11951
5.03k
  }
11952
4.31k
      names = att_names_bnd;
11953
4.31k
      break;
11954
75.4k
    case indir_v_mode:
11955
75.4k
      if (ins->address_mode == mode_64bit && ins->isa64 == intel64)
11956
224
  {
11957
224
    names = att_names64;
11958
224
    break;
11959
224
  }
11960
      /* Fall through.  */
11961
99.9k
    case stack_v_mode:
11962
99.9k
      if (ins->address_mode == mode_64bit && ((sizeflag & DFLAG)
11963
60.1k
                || (ins->rex & REX_W)))
11964
59.4k
  {
11965
59.4k
    names = att_names64;
11966
59.4k
    break;
11967
59.4k
  }
11968
40.4k
      bytemode = v_mode;
11969
      /* Fall through.  */
11970
10.8M
    case v_mode:
11971
12.2M
    case v_swap_mode:
11972
12.2M
    case dq_mode:
11973
12.2M
      USED_REX (REX_W);
11974
12.2M
      if (ins->rex & REX_W)
11975
3.55M
  names = att_names64;
11976
8.68M
      else if (bytemode != v_mode && bytemode != v_swap_mode)
11977
7.13k
  names = att_names32;
11978
8.67M
      else
11979
8.67M
  {
11980
8.67M
    if (sizeflag & DFLAG)
11981
8.26M
      names = att_names32;
11982
408k
    else
11983
408k
      names = att_names16;
11984
8.67M
    ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11985
8.67M
  }
11986
12.2M
      break;
11987
37.5k
    case movsxd_mode:
11988
37.5k
      if (!(sizeflag & DFLAG) && ins->isa64 == intel64)
11989
318
  names = att_names16;
11990
37.2k
      else
11991
37.2k
  names = att_names32;
11992
37.5k
      ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11993
37.5k
      break;
11994
1.25k
    case va_mode:
11995
1.25k
      names = (ins->address_mode == mode_64bit
11996
1.25k
         ? att_names64 : att_names32);
11997
1.25k
      if (!(ins->prefixes & PREFIX_ADDR))
11998
998
  names = (ins->address_mode == mode_16bit
11999
998
         ? att_names16 : names);
12000
257
      else
12001
257
  {
12002
    /* Remove "addr16/addr32".  */
12003
257
    ins->all_prefixes[ins->last_addr_prefix] = 0;
12004
257
    names = (ins->address_mode != mode_32bit
12005
257
           ? att_names32 : att_names16);
12006
257
    ins->used_prefixes |= PREFIX_ADDR;
12007
257
  }
12008
1.25k
      break;
12009
579
    case mask_bd_mode:
12010
13.3k
    case mask_mode:
12011
13.3k
      if (reg > 0x7)
12012
9.64k
  {
12013
9.64k
    oappend (ins, "(bad)");
12014
9.64k
    return;
12015
9.64k
  }
12016
3.73k
      names = att_names_mask;
12017
3.73k
      break;
12018
316
    case 0:
12019
316
      return;
12020
0
    default:
12021
0
      oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
12022
0
      return;
12023
25.1M
    }
12024
25.1M
  oappend_register (ins, names[reg]);
12025
25.1M
}
12026
12027
static bool
12028
get8s (instr_info *ins, bfd_vma *res)
12029
8.46M
{
12030
8.46M
  if (!fetch_code (ins->info, ins->codep + 1))
12031
8.97k
    return false;
12032
8.45M
  *res = ((bfd_vma) *ins->codep++ ^ 0x80) - 0x80;
12033
8.45M
  return true;
12034
8.46M
}
12035
12036
static bool
12037
get16 (instr_info *ins, bfd_vma *res)
12038
217k
{
12039
217k
  if (!fetch_code (ins->info, ins->codep + 2))
12040
2.82k
    return false;
12041
214k
  *res = *ins->codep++;
12042
214k
  *res |= (bfd_vma) *ins->codep++ << 8;
12043
214k
  return true;
12044
217k
}
12045
12046
static bool
12047
get16s (instr_info *ins, bfd_vma *res)
12048
28.0k
{
12049
28.0k
  if (!get16 (ins, res))
12050
895
    return false;
12051
27.1k
  *res = (*res ^ 0x8000) - 0x8000;
12052
27.1k
  return true;
12053
28.0k
}
12054
12055
static bool
12056
get32 (instr_info *ins, bfd_vma *res)
12057
7.40M
{
12058
7.40M
  if (!fetch_code (ins->info, ins->codep + 4))
12059
19.2k
    return false;
12060
7.38M
  *res = *ins->codep++;
12061
7.38M
  *res |= (bfd_vma) *ins->codep++ << 8;
12062
7.38M
  *res |= (bfd_vma) *ins->codep++ << 16;
12063
7.38M
  *res |= (bfd_vma) *ins->codep++ << 24;
12064
7.38M
  return true;
12065
7.40M
}
12066
12067
static bool
12068
get32s (instr_info *ins, bfd_vma *res)
12069
5.44M
{
12070
5.44M
  if (!get32 (ins, res))
12071
12.3k
    return false;
12072
12073
5.43M
  *res = (*res ^ ((bfd_vma) 1 << 31)) - ((bfd_vma) 1 << 31);
12074
12075
5.43M
  return true;
12076
5.44M
}
12077
12078
static bool
12079
get64 (instr_info *ins, uint64_t *res)
12080
127k
{
12081
127k
  unsigned int a;
12082
127k
  unsigned int b;
12083
12084
127k
  if (!fetch_code (ins->info, ins->codep + 8))
12085
1.38k
    return false;
12086
125k
  a = *ins->codep++;
12087
125k
  a |= (unsigned int) *ins->codep++ << 8;
12088
125k
  a |= (unsigned int) *ins->codep++ << 16;
12089
125k
  a |= (unsigned int) *ins->codep++ << 24;
12090
125k
  b = *ins->codep++;
12091
125k
  b |= (unsigned int) *ins->codep++ << 8;
12092
125k
  b |= (unsigned int) *ins->codep++ << 16;
12093
125k
  b |= (unsigned int) *ins->codep++ << 24;
12094
125k
  *res = a + ((uint64_t) b << 32);
12095
125k
  return true;
12096
127k
}
12097
12098
static void
12099
set_op (instr_info *ins, bfd_vma op, bool riprel)
12100
6.07M
{
12101
6.07M
  ins->op_index[ins->op_ad] = ins->op_ad;
12102
6.07M
  if (ins->address_mode == mode_64bit)
12103
4.35M
    ins->op_address[ins->op_ad] = op;
12104
1.72M
  else /* Mask to get a 32-bit address.  */
12105
1.72M
    ins->op_address[ins->op_ad] = op & 0xffffffff;
12106
6.07M
  ins->op_riprel[ins->op_ad] = riprel;
12107
6.07M
}
12108
12109
static bool
12110
BadOp (instr_info *ins)
12111
81.9k
{
12112
  /* Throw away prefixes and 1st. opcode byte.  */
12113
81.9k
  struct dis_private *priv = ins->info->private_data;
12114
12115
81.9k
  ins->codep = priv->the_buffer + ins->nr_prefixes + ins->need_vex + 1;
12116
81.9k
  ins->obufp = stpcpy (ins->obufp, "(bad)");
12117
81.9k
  return true;
12118
81.9k
}
12119
12120
static bool
12121
OP_Skip_MODRM (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
12122
         int sizeflag ATTRIBUTE_UNUSED)
12123
2.28k
{
12124
2.28k
  if (ins->modrm.mod != 3)
12125
910
    return BadOp (ins);
12126
12127
  /* Skip mod/rm byte.  */
12128
1.37k
  MODRM_CHECK;
12129
1.37k
  ins->codep++;
12130
1.37k
  ins->has_skipped_modrm = true;
12131
1.37k
  return true;
12132
1.37k
}
12133
12134
static bool
12135
OP_E_memory (instr_info *ins, int bytemode, int sizeflag)
12136
19.2M
{
12137
19.2M
  int add = (ins->rex & REX_B) ? 8 : 0;
12138
19.2M
  int riprel = 0;
12139
19.2M
  int shift;
12140
12141
19.2M
  add += (ins->rex2 & REX_B) ? 16 : 0;
12142
12143
  /* Handles EVEX other than APX EVEX-promoted instructions.  */
12144
19.2M
  if (ins->vex.evex && ins->evex_type == evex_default)
12145
44.3k
    {
12146
12147
      /* Zeroing-masking is invalid for memory destinations. Set the flag
12148
   uniformly, as the consumer will inspect it only for the destination
12149
   operand.  */
12150
44.3k
      if (ins->vex.zeroing)
12151
14.9k
  ins->illegal_masking = true;
12152
12153
44.3k
      switch (bytemode)
12154
44.3k
  {
12155
212
  case dw_mode:
12156
1.18k
  case w_mode:
12157
1.40k
  case w_swap_mode:
12158
1.40k
    shift = 1;
12159
1.40k
    break;
12160
346
  case db_mode:
12161
641
  case b_mode:
12162
641
    shift = 0;
12163
641
    break;
12164
1.13k
  case dq_mode:
12165
1.13k
    if (ins->address_mode != mode_64bit)
12166
401
      {
12167
1.98k
  case d_mode:
12168
2.43k
  case d_swap_mode:
12169
2.43k
        shift = 2;
12170
2.43k
        break;
12171
1.98k
      }
12172
      /* fall through */
12173
3.53k
  case vex_vsib_d_w_dq_mode:
12174
4.82k
  case vex_vsib_q_w_dq_mode:
12175
5.26k
  case evex_x_gscat_mode:
12176
5.26k
    shift = ins->vex.w ? 3 : 2;
12177
5.26k
    break;
12178
4.63k
  case xh_mode:
12179
5.93k
  case evex_half_bcst_xmmqh_mode:
12180
7.02k
  case evex_half_bcst_xmmqdh_mode:
12181
7.02k
    if (ins->vex.b)
12182
4.44k
      {
12183
4.44k
        shift = ins->vex.w ? 2 : 1;
12184
4.44k
        break;
12185
4.44k
      }
12186
    /* Fall through.  */
12187
19.1k
  case x_mode:
12188
20.6k
  case evex_half_bcst_xmmq_mode:
12189
20.6k
    if (ins->vex.b)
12190
9.78k
      {
12191
9.78k
        shift = ins->vex.w ? 3 : 2;
12192
9.78k
        break;
12193
9.78k
      }
12194
    /* Fall through.  */
12195
11.2k
  case xmmqd_mode:
12196
11.7k
  case xmmdw_mode:
12197
12.1k
  case xmmq_mode:
12198
14.0k
  case ymmq_mode:
12199
14.5k
  case evex_x_nobcst_mode:
12200
15.1k
  case x_swap_mode:
12201
15.1k
    switch (ins->vex.length)
12202
15.1k
      {
12203
5.61k
      case 128:
12204
5.61k
        shift = 4;
12205
5.61k
        break;
12206
4.50k
      case 256:
12207
4.50k
        shift = 5;
12208
4.50k
        break;
12209
5.07k
      case 512:
12210
5.07k
        shift = 6;
12211
5.07k
        break;
12212
0
      default:
12213
0
        abort ();
12214
15.1k
      }
12215
    /* Make necessary corrections to shift for modes that need it.  */
12216
15.1k
    if (bytemode == xmmq_mode
12217
15.1k
        || bytemode == evex_half_bcst_xmmqh_mode
12218
15.1k
        || bytemode == evex_half_bcst_xmmq_mode
12219
15.1k
        || (bytemode == ymmq_mode && ins->vex.length == 128))
12220
2.51k
      shift -= 1;
12221
12.6k
    else if (bytemode == xmmqd_mode
12222
12.6k
             || bytemode == evex_half_bcst_xmmqdh_mode)
12223
694
      shift -= 2;
12224
11.9k
    else if (bytemode == xmmdw_mode)
12225
444
      shift -= 3;
12226
15.1k
    break;
12227
327
  case ymm_mode:
12228
327
    shift = 5;
12229
327
    break;
12230
1.13k
  case xmm_mode:
12231
1.13k
    shift = 4;
12232
1.13k
    break;
12233
1.13k
  case q_mode:
12234
2.17k
  case q_swap_mode:
12235
2.17k
    shift = 3;
12236
2.17k
    break;
12237
1.49k
  case bw_unit_mode:
12238
1.49k
    shift = ins->vex.w ? 1 : 0;
12239
1.49k
    break;
12240
0
  default:
12241
0
    abort ();
12242
44.3k
  }
12243
44.3k
    }
12244
19.2M
  else
12245
19.2M
    shift = 0;
12246
12247
19.2M
  USED_REX (REX_B);
12248
19.2M
  if (ins->intel_syntax)
12249
277k
    intel_operand_size (ins, bytemode, sizeflag);
12250
19.2M
  append_seg (ins);
12251
12252
19.2M
  if ((sizeflag & AFLAG) || ins->address_mode == mode_64bit)
12253
19.0M
    {
12254
      /* 32/64 bit address mode */
12255
19.0M
      bfd_vma disp = 0;
12256
19.0M
      int havedisp;
12257
19.0M
      int havebase;
12258
19.0M
      int needindex;
12259
19.0M
      int needaddr32;
12260
19.0M
      int base, rbase;
12261
19.0M
      int vindex = 0;
12262
19.0M
      int scale = 0;
12263
19.0M
      int addr32flag = !((sizeflag & AFLAG)
12264
19.0M
       || bytemode == v_bnd_mode
12265
19.0M
       || bytemode == v_bndmk_mode
12266
19.0M
       || bytemode == bnd_mode
12267
19.0M
       || bytemode == bnd_swap_mode);
12268
19.0M
      bool check_gather = false;
12269
19.0M
      const char (*indexes)[8] = NULL;
12270
12271
19.0M
      havebase = 1;
12272
19.0M
      base = ins->modrm.rm;
12273
12274
19.0M
      if (base == 4)
12275
1.99M
  {
12276
1.99M
    vindex = ins->sib.index;
12277
1.99M
    USED_REX (REX_X);
12278
1.99M
    if (ins->rex & REX_X)
12279
36.5k
      vindex += 8;
12280
1.99M
    switch (bytemode)
12281
1.99M
      {
12282
3.40k
      case vex_vsib_d_w_dq_mode:
12283
5.08k
      case vex_vsib_q_w_dq_mode:
12284
5.08k
        if (!ins->need_vex)
12285
0
    abort ();
12286
5.08k
        if (ins->vex.evex)
12287
3.24k
    {
12288
      /* S/G EVEX insns require EVEX.X4 not to be set.  */
12289
3.24k
      if (ins->rex2 & REX_X)
12290
319
        {
12291
319
          oappend (ins, "(bad)");
12292
319
          return true;
12293
319
        }
12294
12295
2.92k
      if (!ins->vex.v)
12296
2.50k
        vindex += 16;
12297
2.92k
      check_gather = ins->obufp == ins->op_out[1];
12298
2.92k
    }
12299
12300
4.76k
        switch (ins->vex.length)
12301
4.76k
    {
12302
1.03k
    case 128:
12303
1.03k
      indexes = att_names_xmm;
12304
1.03k
      break;
12305
2.39k
    case 256:
12306
2.39k
      if (!ins->vex.w
12307
2.39k
          || bytemode == vex_vsib_q_w_dq_mode)
12308
1.74k
        indexes = att_names_ymm;
12309
658
      else
12310
658
        indexes = att_names_xmm;
12311
2.39k
      break;
12312
1.32k
    case 512:
12313
1.32k
      if (!ins->vex.w
12314
1.32k
          || bytemode == vex_vsib_q_w_dq_mode)
12315
1.03k
        indexes = att_names_zmm;
12316
296
      else
12317
296
        indexes = att_names_ymm;
12318
1.32k
      break;
12319
0
    default:
12320
0
      abort ();
12321
4.76k
    }
12322
4.76k
        break;
12323
1.99M
      default:
12324
1.99M
        if (ins->rex2 & REX_X)
12325
3.14k
    vindex += 16;
12326
12327
1.99M
        if (vindex != 4)
12328
1.09M
    indexes = ins->address_mode == mode_64bit && !addr32flag
12329
1.09M
        ? att_names64 : att_names32;
12330
1.99M
        break;
12331
1.99M
      }
12332
1.99M
    scale = ins->sib.scale;
12333
1.99M
    base = ins->sib.base;
12334
1.99M
    ins->codep++;
12335
1.99M
  }
12336
17.0M
      else
12337
17.0M
  {
12338
    /* Check for mandatory SIB.  */
12339
17.0M
    if (bytemode == vex_vsib_d_w_dq_mode
12340
17.0M
        || bytemode == vex_vsib_q_w_dq_mode
12341
17.0M
        || bytemode == vex_sibmem_mode)
12342
2.01k
      {
12343
2.01k
        oappend (ins, "(bad)");
12344
2.01k
        return true;
12345
2.01k
      }
12346
17.0M
  }
12347
19.0M
      rbase = base + add;
12348
12349
19.0M
      switch (ins->modrm.mod)
12350
19.0M
  {
12351
12.9M
  case 0:
12352
12.9M
    if (base == 5)
12353
1.22M
      {
12354
1.22M
        havebase = 0;
12355
1.22M
        if (ins->address_mode == mode_64bit && !ins->has_sib)
12356
942k
    riprel = 1;
12357
1.22M
        if (!get32s (ins, &disp))
12358
3.63k
    return false;
12359
1.21M
        if (riprel && bytemode == v_bndmk_mode)
12360
274
    {
12361
274
      oappend (ins, "(bad)");
12362
274
      return true;
12363
274
    }
12364
1.21M
      }
12365
12.8M
    break;
12366
12.8M
  case 1:
12367
4.20M
    if (!get8s (ins, &disp))
12368
5.55k
      return false;
12369
4.20M
    if (ins->vex.evex && shift > 0)
12370
19.3k
      disp <<= shift;
12371
4.20M
    break;
12372
1.92M
  case 2:
12373
1.92M
    if (!get32s (ins, &disp))
12374
5.93k
      return false;
12375
1.91M
    break;
12376
19.0M
  }
12377
12378
19.0M
      needindex = 0;
12379
19.0M
      needaddr32 = 0;
12380
19.0M
      if (ins->has_sib
12381
19.0M
    && !havebase
12382
19.0M
    && !indexes
12383
19.0M
    && ins->address_mode != mode_16bit)
12384
4.90k
  {
12385
4.90k
    if (ins->address_mode == mode_64bit)
12386
3.82k
      {
12387
3.82k
        if (addr32flag)
12388
482
    {
12389
      /* Without base nor index registers, zero-extend the
12390
         lower 32-bit displacement to 64 bits.  */
12391
482
      disp &= 0xffffffff;
12392
482
      needindex = 1;
12393
482
    }
12394
3.82k
        needaddr32 = 1;
12395
3.82k
      }
12396
1.08k
    else
12397
1.08k
      {
12398
        /* In 32-bit mode, we need index register to tell [offset]
12399
     from [eiz*1 + offset].  */
12400
1.08k
        needindex = 1;
12401
1.08k
      }
12402
4.90k
  }
12403
12404
19.0M
      havedisp = (havebase
12405
19.0M
      || needindex
12406
19.0M
      || (ins->has_sib && (indexes || scale != 0)));
12407
12408
19.0M
      if (!ins->intel_syntax)
12409
18.7M
  if (ins->modrm.mod != 0 || base == 5)
12410
7.24M
    {
12411
7.24M
      if (havedisp || riprel)
12412
7.01M
        print_displacement (ins, disp);
12413
235k
      else
12414
235k
        print_operand_value (ins, disp, dis_style_address_offset);
12415
7.24M
      if (riprel)
12416
934k
        {
12417
934k
    set_op (ins, disp, true);
12418
934k
    oappend_char (ins, '(');
12419
934k
    oappend_with_style (ins, !addr32flag ? "%rip" : "%eip",
12420
934k
            dis_style_register);
12421
934k
    oappend_char (ins, ')');
12422
934k
        }
12423
7.24M
    }
12424
12425
19.0M
      if ((havebase || indexes || needindex || needaddr32 || riprel)
12426
19.0M
    && (ins->address_mode != mode_64bit
12427
18.7M
        || ((bytemode != v_bnd_mode)
12428
13.4M
      && (bytemode != v_bndmk_mode)
12429
13.4M
      && (bytemode != bnd_mode)
12430
13.4M
      && (bytemode != bnd_swap_mode))))
12431
18.7M
  ins->used_prefixes |= PREFIX_ADDR;
12432
12433
19.0M
      if (havedisp || (ins->intel_syntax && riprel))
12434
17.8M
  {
12435
17.8M
    oappend_char (ins, ins->open_char);
12436
17.8M
    if (ins->intel_syntax && riprel)
12437
5.50k
      {
12438
5.50k
        set_op (ins, disp, true);
12439
5.50k
        oappend_with_style (ins, !addr32flag ? "rip" : "eip",
12440
5.50k
          dis_style_register);
12441
5.50k
      }
12442
17.8M
    if (havebase)
12443
17.7M
      oappend_register
12444
17.7M
        (ins,
12445
17.7M
         (ins->address_mode == mode_64bit && !addr32flag
12446
17.7M
    ? att_names64 : att_names32)[rbase]);
12447
17.8M
    if (ins->has_sib)
12448
1.99M
      {
12449
        /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
12450
     print index to tell base + index from base.  */
12451
1.99M
        if (scale != 0
12452
1.99M
      || needindex
12453
1.99M
      || indexes
12454
1.99M
      || (havebase && base != ESP_REG_NUM))
12455
1.23M
    {
12456
1.23M
      if (!ins->intel_syntax || havebase)
12457
1.23M
        oappend_char (ins, ins->separator_char);
12458
1.23M
      if (indexes)
12459
1.09M
        {
12460
1.09M
          if (ins->address_mode == mode_64bit || vindex < 16)
12461
1.09M
      oappend_register (ins, indexes[vindex]);
12462
492
          else
12463
492
      oappend (ins, "(bad)");
12464
1.09M
        }
12465
137k
      else
12466
137k
        oappend_register (ins,
12467
137k
              ins->address_mode == mode_64bit
12468
137k
              && !addr32flag
12469
137k
              ? att_index64
12470
137k
              : att_index32);
12471
12472
1.23M
      oappend_char (ins, ins->scale_char);
12473
1.23M
      oappend_char_with_style (ins, '0' + (1 << scale),
12474
1.23M
             dis_style_immediate);
12475
1.23M
    }
12476
1.99M
      }
12477
17.8M
    if (ins->intel_syntax
12478
17.8M
        && (disp || ins->modrm.mod != 0 || base == 5))
12479
82.8k
      {
12480
82.8k
        if (!havedisp || (bfd_signed_vma) disp >= 0)
12481
56.9k
      oappend_char (ins, '+');
12482
82.8k
        if (havedisp)
12483
77.3k
    print_displacement (ins, disp);
12484
5.50k
        else
12485
5.50k
    print_operand_value (ins, disp, dis_style_address_offset);
12486
82.8k
      }
12487
12488
17.8M
    oappend_char (ins, ins->close_char);
12489
12490
17.8M
    if (check_gather)
12491
2.18k
      {
12492
        /* Both XMM/YMM/ZMM registers must be distinct.  */
12493
2.18k
        int modrm_reg = ins->modrm.reg;
12494
12495
2.18k
        if (ins->rex & REX_R)
12496
1.42k
          modrm_reg += 8;
12497
2.18k
        if (ins->rex2 & REX_R)
12498
1.43k
          modrm_reg += 16;
12499
2.18k
        if (vindex == modrm_reg)
12500
279
    oappend (ins, "/(bad)");
12501
2.18k
      }
12502
17.8M
  }
12503
1.17M
      else if (ins->intel_syntax)
12504
2.10k
  {
12505
2.10k
    if (ins->modrm.mod != 0 || base == 5)
12506
2.10k
      {
12507
2.10k
        if (!ins->active_seg_prefix)
12508
1.79k
    {
12509
1.79k
      oappend_register (ins, att_names_seg[ds_reg - es_reg]);
12510
1.79k
      oappend (ins, ":");
12511
1.79k
    }
12512
2.10k
        print_operand_value (ins, disp, dis_style_text);
12513
2.10k
      }
12514
2.10k
  }
12515
19.0M
    }
12516
228k
  else if (bytemode == v_bnd_mode
12517
228k
     || bytemode == v_bndmk_mode
12518
228k
     || bytemode == bnd_mode
12519
228k
     || bytemode == bnd_swap_mode
12520
228k
     || bytemode == vex_vsib_d_w_dq_mode
12521
228k
     || bytemode == vex_vsib_q_w_dq_mode)
12522
3.58k
    {
12523
3.58k
      oappend (ins, "(bad)");
12524
3.58k
      return true;
12525
3.58k
    }
12526
225k
  else
12527
225k
    {
12528
      /* 16 bit address mode */
12529
225k
      bfd_vma disp = 0;
12530
12531
225k
      ins->used_prefixes |= ins->prefixes & PREFIX_ADDR;
12532
225k
      switch (ins->modrm.mod)
12533
225k
  {
12534
174k
  case 0:
12535
174k
    if (ins->modrm.rm == 6)
12536
8.42k
      {
12537
24.4k
  case 2:
12538
24.4k
        if (!get16s (ins, &disp))
12539
610
    return false;
12540
24.4k
      }
12541
189k
    break;
12542
189k
  case 1:
12543
35.1k
    if (!get8s (ins, &disp))
12544
630
      return false;
12545
34.5k
    if (ins->vex.evex && shift > 0)
12546
812
      disp <<= shift;
12547
34.5k
    break;
12548
225k
  }
12549
12550
224k
      if (!ins->intel_syntax)
12551
216k
  if (ins->modrm.mod != 0 || ins->modrm.rm == 6)
12552
54.5k
    print_displacement (ins, disp);
12553
12554
224k
      if (ins->modrm.mod != 0 || ins->modrm.rm != 6)
12555
215k
  {
12556
215k
    oappend_char (ins, ins->open_char);
12557
215k
    oappend (ins, ins->intel_syntax ? intel_index16[ins->modrm.rm]
12558
215k
            : att_index16[ins->modrm.rm]);
12559
215k
    if (ins->intel_syntax
12560
215k
        && (disp || ins->modrm.mod != 0 || ins->modrm.rm == 6))
12561
3.06k
      {
12562
3.06k
        if ((bfd_signed_vma) disp >= 0)
12563
1.81k
    oappend_char (ins, '+');
12564
3.06k
        print_displacement (ins, disp);
12565
3.06k
      }
12566
12567
215k
    oappend_char (ins, ins->close_char);
12568
215k
  }
12569
8.27k
      else if (ins->intel_syntax)
12570
848
  {
12571
848
    if (!ins->active_seg_prefix)
12572
498
      {
12573
498
        oappend_register (ins, att_names_seg[ds_reg - es_reg]);
12574
498
        oappend (ins, ":");
12575
498
      }
12576
848
    print_operand_value (ins, disp & 0xffff, dis_style_text);
12577
848
  }
12578
224k
    }
12579
19.2M
  if (ins->vex.b && ins->evex_type == evex_default)
12580
19.6k
    {
12581
19.6k
      ins->evex_used |= EVEX_b_used;
12582
12583
      /* Broadcast can only ever be valid for memory sources.  */
12584
19.6k
      if (ins->obufp == ins->op_out[0])
12585
0
  ins->vex.no_broadcast = true;
12586
12587
19.6k
      if (!ins->vex.no_broadcast
12588
19.6k
    && (!ins->intel_syntax || !(ins->evex_used & EVEX_len_used)))
12589
14.4k
  {
12590
14.4k
    if (bytemode == xh_mode)
12591
2.08k
      {
12592
2.08k
        switch (ins->vex.length)
12593
2.08k
    {
12594
452
    case 128:
12595
452
      oappend (ins, "{1to8}");
12596
452
      break;
12597
844
    case 256:
12598
844
      oappend (ins, "{1to16}");
12599
844
      break;
12600
791
    case 512:
12601
791
      oappend (ins, "{1to32}");
12602
791
      break;
12603
0
    default:
12604
0
      abort ();
12605
2.08k
    }
12606
2.08k
      }
12607
12.3k
    else if (bytemode == q_mode
12608
12.3k
       || bytemode == ymmq_mode)
12609
1.32k
      ins->vex.no_broadcast = true;
12610
10.9k
    else if (ins->vex.w
12611
10.9k
       || bytemode == evex_half_bcst_xmmqdh_mode
12612
10.9k
       || bytemode == evex_half_bcst_xmmq_mode)
12613
6.31k
      {
12614
6.31k
        switch (ins->vex.length)
12615
6.31k
    {
12616
1.19k
    case 128:
12617
1.19k
      oappend (ins, "{1to2}");
12618
1.19k
      break;
12619
1.73k
    case 256:
12620
1.73k
      oappend (ins, "{1to4}");
12621
1.73k
      break;
12622
3.38k
    case 512:
12623
3.38k
      oappend (ins, "{1to8}");
12624
3.38k
      break;
12625
0
    default:
12626
0
      abort ();
12627
6.31k
    }
12628
6.31k
      }
12629
4.67k
    else if (bytemode == x_mode
12630
4.67k
       || bytemode == evex_half_bcst_xmmqh_mode)
12631
3.38k
      {
12632
3.38k
        switch (ins->vex.length)
12633
3.38k
    {
12634
747
    case 128:
12635
747
      oappend (ins, "{1to4}");
12636
747
      break;
12637
1.24k
    case 256:
12638
1.24k
      oappend (ins, "{1to8}");
12639
1.24k
      break;
12640
1.39k
    case 512:
12641
1.39k
      oappend (ins, "{1to16}");
12642
1.39k
      break;
12643
0
    default:
12644
0
      abort ();
12645
3.38k
    }
12646
3.38k
      }
12647
1.29k
    else
12648
1.29k
      ins->vex.no_broadcast = true;
12649
14.4k
  }
12650
19.6k
      if (ins->vex.no_broadcast)
12651
5.13k
  oappend (ins, "{bad}");
12652
19.6k
    }
12653
12654
19.2M
  return true;
12655
19.2M
}
12656
12657
static bool
12658
OP_E (instr_info *ins, int bytemode, int sizeflag)
12659
23.2M
{
12660
  /* Skip mod/rm byte.  */
12661
23.2M
  MODRM_CHECK;
12662
23.2M
  if (!ins->has_skipped_modrm)
12663
23.2M
    {
12664
23.2M
      ins->codep++;
12665
23.2M
      ins->has_skipped_modrm = true;
12666
23.2M
    }
12667
12668
23.2M
  if (ins->modrm.mod == 3)
12669
4.95M
    {
12670
4.95M
      if ((sizeflag & SUFFIX_ALWAYS)
12671
4.95M
    && (bytemode == b_swap_mode
12672
2.76k
        || bytemode == bnd_swap_mode
12673
2.76k
        || bytemode == v_swap_mode))
12674
812
  swap_operand (ins);
12675
12676
4.95M
      print_register (ins, ins->modrm.rm, REX_B, bytemode, sizeflag);
12677
4.95M
      return true;
12678
4.95M
    }
12679
12680
  /* Masking is invalid for insns with GPR-like memory destination. Set the
12681
     flag uniformly, as the consumer will inspect it only for the destination
12682
     operand.  */
12683
18.3M
  if (ins->vex.mask_register_specifier)
12684
6.95k
    ins->illegal_masking = true;
12685
12686
18.3M
  return OP_E_memory (ins, bytemode, sizeflag);
12687
23.2M
}
12688
12689
static bool
12690
OP_indirE (instr_info *ins, int bytemode, int sizeflag)
12691
489k
{
12692
489k
  if (ins->modrm.mod == 3 && bytemode == f_mode)
12693
    /* bad lcall/ljmp */
12694
33.4k
    return BadOp (ins);
12695
455k
  if (!ins->intel_syntax)
12696
444k
    oappend (ins, "*");
12697
455k
  return OP_E (ins, bytemode, sizeflag);
12698
489k
}
12699
12700
static bool
12701
OP_G (instr_info *ins, int bytemode, int sizeflag)
12702
20.2M
{
12703
20.2M
  print_register (ins, ins->modrm.reg, REX_R, bytemode, sizeflag);
12704
20.2M
  return true;
12705
20.2M
}
12706
12707
static bool
12708
OP_REG (instr_info *ins, int code, int sizeflag)
12709
4.64M
{
12710
4.64M
  const char *s;
12711
4.64M
  int add = 0;
12712
12713
4.64M
  switch (code)
12714
4.64M
    {
12715
163k
    case es_reg: case ss_reg: case cs_reg:
12716
201k
    case ds_reg: case fs_reg: case gs_reg:
12717
201k
      oappend_register (ins, att_names_seg[code - es_reg]);
12718
201k
      return true;
12719
4.64M
    }
12720
12721
4.44M
  USED_REX (REX_B);
12722
4.44M
  if (ins->rex & REX_B)
12723
353k
    add = 8;
12724
4.44M
  if (ins->rex2 & REX_B)
12725
2.33k
    add += 16;
12726
12727
4.44M
  switch (code)
12728
4.44M
    {
12729
0
    case ax_reg: case cx_reg: case dx_reg: case bx_reg:
12730
0
    case sp_reg: case bp_reg: case si_reg: case di_reg:
12731
0
      s = att_names16[code - ax_reg + add];
12732
0
      break;
12733
114k
    case ah_reg: case ch_reg: case dh_reg: case bh_reg:
12734
114k
      USED_REX (0);
12735
      /* Fall through.  */
12736
259k
    case al_reg: case cl_reg: case dl_reg: case bl_reg:
12737
259k
      if (ins->rex)
12738
7.85k
  s = att_names8rex[code - al_reg + add];
12739
252k
      else
12740
252k
  s = att_names8[code - al_reg];
12741
259k
      break;
12742
1.02M
    case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
12743
2.52M
    case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
12744
2.52M
      if (ins->address_mode == mode_64bit
12745
2.52M
    && ((sizeflag & DFLAG) || (ins->rex & REX_W)))
12746
1.44M
  {
12747
1.44M
    s = att_names64[code - rAX_reg + add];
12748
1.44M
    break;
12749
1.44M
  }
12750
1.08M
      code += eAX_reg - rAX_reg;
12751
      /* Fall through.  */
12752
2.05M
    case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
12753
2.74M
    case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
12754
2.74M
      USED_REX (REX_W);
12755
2.74M
      if (ins->rex & REX_W)
12756
16.7k
  s = att_names64[code - eAX_reg + add];
12757
2.72M
      else
12758
2.72M
  {
12759
2.72M
    if (sizeflag & DFLAG)
12760
2.66M
      s = att_names32[code - eAX_reg + add];
12761
67.0k
    else
12762
67.0k
      s = att_names16[code - eAX_reg + add];
12763
2.72M
    ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12764
2.72M
  }
12765
2.74M
      break;
12766
0
    default:
12767
0
      oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
12768
0
      return true;
12769
4.44M
    }
12770
4.44M
  oappend_register (ins, s);
12771
4.44M
  return true;
12772
4.44M
}
12773
12774
static bool
12775
OP_IMREG (instr_info *ins, int code, int sizeflag)
12776
4.11M
{
12777
4.11M
  const char *s;
12778
12779
4.11M
  switch (code)
12780
4.11M
    {
12781
975k
    case indir_dx_reg:
12782
975k
      if (!ins->intel_syntax)
12783
953k
  {
12784
953k
    oappend (ins, "(%dx)");
12785
953k
    return true;
12786
953k
  }
12787
22.6k
      s = att_names16[dx_reg - ax_reg];
12788
22.6k
      break;
12789
1.63M
    case al_reg: case cl_reg:
12790
1.63M
      s = att_names8[code - al_reg];
12791
1.63M
      break;
12792
1.36M
    case eAX_reg:
12793
1.36M
      USED_REX (REX_W);
12794
1.36M
      if (ins->rex & REX_W)
12795
25.8k
  {
12796
25.8k
    s = *att_names64;
12797
25.8k
    break;
12798
25.8k
  }
12799
      /* Fall through.  */
12800
1.47M
    case z_mode_ax_reg:
12801
1.47M
      if ((ins->rex & REX_W) || (sizeflag & DFLAG))
12802
1.40M
  s = *att_names32;
12803
73.1k
      else
12804
73.1k
  s = *att_names16;
12805
1.47M
      if (!(ins->rex & REX_W))
12806
1.47M
  ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12807
1.47M
      break;
12808
0
    default:
12809
0
      oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
12810
0
      return true;
12811
4.11M
    }
12812
3.16M
  oappend_register (ins, s);
12813
3.16M
  return true;
12814
4.11M
}
12815
12816
static bool
12817
OP_I (instr_info *ins, int bytemode, int sizeflag)
12818
4.77M
{
12819
4.77M
  bfd_vma op;
12820
12821
4.77M
  switch (bytemode)
12822
4.77M
    {
12823
2.55M
    case b_mode:
12824
2.55M
      if (!fetch_code (ins->info, ins->codep + 1))
12825
5.16k
  return false;
12826
2.54M
      op = *ins->codep++;
12827
2.54M
      break;
12828
1.95M
    case v_mode:
12829
1.95M
      USED_REX (REX_W);
12830
1.95M
      if (ins->rex & REX_W)
12831
70.1k
  {
12832
70.1k
    if (!get32s (ins, &op))
12833
1.25k
      return false;
12834
70.1k
  }
12835
1.88M
      else
12836
1.88M
  {
12837
1.88M
    ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12838
1.88M
    if (sizeflag & DFLAG)
12839
1.84M
      {
12840
1.84M
    case d_mode:
12841
1.84M
        if (!get32 (ins, &op))
12842
5.98k
    return false;
12843
1.84M
      }
12844
35.7k
    else
12845
35.7k
      {
12846
        /* Fall through.  */
12847
161k
    case w_mode:
12848
161k
        if (!get16 (ins, &op))
12849
939
    return false;
12850
161k
      }
12851
1.88M
  }
12852
2.07M
      break;
12853
2.07M
    case const_1_mode:
12854
143k
      if (ins->intel_syntax)
12855
1.36k
  oappend_with_style (ins, "1", dis_style_immediate);
12856
141k
      else
12857
141k
  oappend_with_style (ins, "$1", dis_style_immediate);
12858
143k
      return true;
12859
0
    default:
12860
0
      oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
12861
0
      return true;
12862
4.77M
    }
12863
12864
4.61M
  oappend_immediate (ins, op);
12865
4.61M
  return true;
12866
4.77M
}
12867
12868
static bool
12869
OP_I64 (instr_info *ins, int bytemode, int sizeflag)
12870
604k
{
12871
604k
  uint64_t op;
12872
12873
604k
  if (bytemode != v_mode || ins->address_mode != mode_64bit
12874
604k
      || !(ins->rex & REX_W))
12875
592k
    return OP_I (ins, bytemode, sizeflag);
12876
12877
11.7k
  USED_REX (REX_W);
12878
12879
11.7k
  if (!get64 (ins, &op))
12880
136
    return false;
12881
12882
11.5k
  oappend_immediate (ins, op);
12883
11.5k
  return true;
12884
11.7k
}
12885
12886
static bool
12887
OP_sI (instr_info *ins, int bytemode, int sizeflag)
12888
1.32M
{
12889
1.32M
  bfd_vma op;
12890
12891
1.32M
  switch (bytemode)
12892
1.32M
    {
12893
972k
    case b_mode:
12894
1.10M
    case b_T_mode:
12895
1.10M
      if (!get8s (ins, &op))
12896
951
  return false;
12897
1.10M
      if (bytemode == b_T_mode)
12898
133k
  {
12899
133k
    if (ins->address_mode != mode_64bit
12900
133k
        || !((sizeflag & DFLAG) || (ins->rex & REX_W)))
12901
100k
      {
12902
        /* The operand-size prefix is overridden by a REX prefix.  */
12903
100k
        if ((sizeflag & DFLAG) || (ins->rex & REX_W))
12904
98.9k
    op &= 0xffffffff;
12905
1.21k
        else
12906
1.21k
    op &= 0xffff;
12907
100k
    }
12908
133k
  }
12909
972k
      else
12910
972k
  {
12911
972k
    if (!(ins->rex & REX_W))
12912
732k
      {
12913
732k
        if (sizeflag & DFLAG)
12914
668k
    op &= 0xffffffff;
12915
63.8k
        else
12916
63.8k
    op &= 0xffff;
12917
732k
      }
12918
972k
  }
12919
1.10M
      break;
12920
217k
    case v_mode:
12921
      /* The operand-size prefix is overridden by a REX prefix.  */
12922
217k
      if (!(sizeflag & DFLAG) && !(ins->rex & REX_W))
12923
4.56k
  {
12924
4.56k
    if (!get16 (ins, &op))
12925
96
      return false;
12926
4.56k
  }
12927
213k
      else if (!get32s (ins, &op))
12928
457
  return false;
12929
217k
      break;
12930
217k
    default:
12931
0
      oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
12932
0
      return true;
12933
1.32M
    }
12934
12935
1.32M
  oappend_immediate (ins, op);
12936
1.32M
  return true;
12937
1.32M
}
12938
12939
static bool
12940
OP_J (instr_info *ins, int bytemode, int sizeflag)
12941
5.14M
{
12942
5.14M
  bfd_vma disp;
12943
5.14M
  bfd_vma mask = -1;
12944
5.14M
  bfd_vma segment = 0;
12945
12946
5.14M
  switch (bytemode)
12947
5.14M
    {
12948
3.11M
    case b_mode:
12949
3.11M
      if (!get8s (ins, &disp))
12950
1.83k
  return false;
12951
3.11M
      break;
12952
3.11M
    case v_mode:
12953
2.02M
    case dqw_mode:
12954
2.02M
      if ((sizeflag & DFLAG)
12955
2.02M
    || (ins->address_mode == mode_64bit
12956
4.20k
        && ((ins->isa64 == intel64 && bytemode != dqw_mode)
12957
1.79k
      || (ins->rex & REX_W))))
12958
2.02M
  {
12959
2.02M
    if (!get32s (ins, &disp))
12960
1.05k
      return false;
12961
2.02M
  }
12962
3.56k
      else
12963
3.56k
  {
12964
3.56k
    if (!get16s (ins, &disp))
12965
285
      return false;
12966
    /* In 16bit mode, address is wrapped around at 64k within
12967
       the same segment.  Otherwise, a data16 prefix on a jump
12968
       instruction means that the pc is masked to 16 bits after
12969
       the displacement is added!  */
12970
3.27k
    mask = 0xffff;
12971
3.27k
    if ((ins->prefixes & PREFIX_DATA) == 0)
12972
2.80k
      segment = ((ins->start_pc + (ins->codep - ins->start_codep))
12973
2.80k
           & ~((bfd_vma) 0xffff));
12974
3.27k
  }
12975
2.02M
      if (ins->address_mode != mode_64bit
12976
2.02M
    || (ins->isa64 != intel64 && !(ins->rex & REX_W)))
12977
2.02M
  ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12978
2.02M
      break;
12979
0
    default:
12980
0
      oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
12981
0
      return true;
12982
5.14M
    }
12983
5.13M
  disp = ((ins->start_pc + (ins->codep - ins->start_codep) + disp) & mask)
12984
5.13M
   | segment;
12985
5.13M
  set_op (ins, disp, false);
12986
5.13M
  print_operand_value (ins, disp, dis_style_text);
12987
5.13M
  return true;
12988
5.14M
}
12989
12990
static bool
12991
OP_SEG (instr_info *ins, int bytemode, int sizeflag)
12992
183k
{
12993
183k
  if (bytemode == w_mode)
12994
50.7k
    {
12995
50.7k
      oappend_register (ins, att_names_seg[ins->modrm.reg]);
12996
50.7k
      return true;
12997
50.7k
    }
12998
133k
  return OP_E (ins, ins->modrm.mod == 3 ? bytemode : w_mode, sizeflag);
12999
183k
}
13000
13001
static bool
13002
OP_DIR (instr_info *ins, int dummy ATTRIBUTE_UNUSED, int sizeflag)
13003
18.3k
{
13004
18.3k
  bfd_vma seg, offset;
13005
18.3k
  int res;
13006
18.3k
  char scratch[24];
13007
13008
18.3k
  if (sizeflag & DFLAG)
13009
16.3k
    {
13010
16.3k
      if (!get32 (ins, &offset))
13011
16.1k
  return false;;
13012
16.1k
    }
13013
1.95k
  else if (!get16 (ins, &offset))
13014
193
    return false;
13015
17.8k
  if (!get16 (ins, &seg))
13016
17.5k
    return false;;
13017
17.5k
  ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
13018
13019
17.5k
  res = snprintf (scratch, ARRAY_SIZE (scratch),
13020
17.5k
      ins->intel_syntax ? "0x%x:0x%x" : "$0x%x,$0x%x",
13021
17.5k
      (unsigned) seg, (unsigned) offset);
13022
17.5k
  if (res < 0 || (size_t) res >= ARRAY_SIZE (scratch))
13023
0
    abort ();
13024
17.5k
  oappend (ins, scratch);
13025
17.5k
  return true;
13026
17.5k
}
13027
13028
static bool
13029
OP_OFF (instr_info *ins, int bytemode, int sizeflag)
13030
102k
{
13031
102k
  bfd_vma off;
13032
13033
102k
  if (ins->intel_syntax && (sizeflag & SUFFIX_ALWAYS))
13034
416
    intel_operand_size (ins, bytemode, sizeflag);
13035
102k
  append_seg (ins);
13036
13037
102k
  if ((sizeflag & AFLAG) || ins->address_mode == mode_64bit)
13038
99.0k
    {
13039
99.0k
      if (!get32 (ins, &off))
13040
658
  return false;
13041
99.0k
    }
13042
3.80k
  else
13043
3.80k
    {
13044
3.80k
      if (!get16 (ins, &off))
13045
338
  return false;
13046
3.80k
    }
13047
13048
101k
  if (ins->intel_syntax)
13049
3.54k
    {
13050
3.54k
      if (!ins->active_seg_prefix)
13051
3.05k
  {
13052
3.05k
    oappend_register (ins, att_names_seg[ds_reg - es_reg]);
13053
3.05k
    oappend (ins, ":");
13054
3.05k
  }
13055
3.54k
    }
13056
101k
  print_operand_value (ins, off, dis_style_address_offset);
13057
101k
  return true;
13058
102k
}
13059
13060
static bool
13061
OP_OFF64 (instr_info *ins, int bytemode, int sizeflag)
13062
217k
{
13063
217k
  uint64_t off;
13064
13065
217k
  if (ins->address_mode != mode_64bit
13066
217k
      || (ins->prefixes & PREFIX_ADDR))
13067
102k
    return OP_OFF (ins, bytemode, sizeflag);
13068
13069
114k
  if (ins->intel_syntax && (sizeflag & SUFFIX_ALWAYS))
13070
198
    intel_operand_size (ins, bytemode, sizeflag);
13071
114k
  append_seg (ins);
13072
13073
114k
  if (!get64 (ins, &off))
13074
1.18k
    return false;
13075
13076
113k
  if (ins->intel_syntax)
13077
3.94k
    {
13078
3.94k
      if (!ins->active_seg_prefix)
13079
3.65k
  {
13080
3.65k
    oappend_register (ins, att_names_seg[ds_reg - es_reg]);
13081
3.65k
    oappend (ins, ":");
13082
3.65k
  }
13083
3.94k
    }
13084
113k
  print_operand_value (ins, off, dis_style_address_offset);
13085
113k
  return true;
13086
114k
}
13087
13088
static void
13089
ptr_reg (instr_info *ins, int code, int sizeflag)
13090
1.57M
{
13091
1.57M
  const char *s;
13092
13093
1.57M
  *ins->obufp++ = ins->open_char;
13094
1.57M
  ins->used_prefixes |= (ins->prefixes & PREFIX_ADDR);
13095
1.57M
  if (ins->address_mode == mode_64bit)
13096
1.10M
    {
13097
1.10M
      if (!(sizeflag & AFLAG))
13098
14.4k
  s = att_names32[code - eAX_reg];
13099
1.08M
      else
13100
1.08M
  s = att_names64[code - eAX_reg];
13101
1.10M
    }
13102
476k
  else if (sizeflag & AFLAG)
13103
452k
    s = att_names32[code - eAX_reg];
13104
24.0k
  else
13105
24.0k
    s = att_names16[code - eAX_reg];
13106
1.57M
  oappend_register (ins, s);
13107
1.57M
  oappend_char (ins, ins->close_char);
13108
1.57M
}
13109
13110
static bool
13111
OP_ESreg (instr_info *ins, int code, int sizeflag)
13112
781k
{
13113
781k
  if (ins->intel_syntax)
13114
55.6k
    {
13115
55.6k
      switch (ins->codep[-1])
13116
55.6k
  {
13117
5.55k
  case 0x6d:  /* insw/insl */
13118
5.55k
    intel_operand_size (ins, z_mode, sizeflag);
13119
5.55k
    break;
13120
2.47k
  case 0xa5:  /* movsw/movsl/movsq */
13121
5.41k
  case 0xa7:  /* cmpsw/cmpsl/cmpsq */
13122
9.01k
  case 0xab:  /* stosw/stosl */
13123
11.1k
  case 0xaf:  /* scasw/scasl */
13124
11.1k
    intel_operand_size (ins, v_mode, sizeflag);
13125
11.1k
    break;
13126
38.8k
  default:
13127
38.8k
    intel_operand_size (ins, b_mode, sizeflag);
13128
55.6k
  }
13129
55.6k
    }
13130
781k
  if (ins->address_mode != mode_64bit)
13131
217k
    {
13132
217k
      oappend_register (ins, att_names_seg[0]);
13133
217k
      oappend_char (ins, ':');
13134
217k
    }
13135
781k
  ptr_reg (ins, code, sizeflag);
13136
781k
  return true;
13137
781k
}
13138
13139
static bool
13140
OP_DSreg (instr_info *ins, int code, int sizeflag)
13141
796k
{
13142
796k
  if (ins->intel_syntax)
13143
50.1k
    {
13144
50.1k
      switch (ins->codep[-1])
13145
50.1k
  {
13146
190
  case 0x01:  /* rmpupdate/rmpread */
13147
190
    break;
13148
4.74k
  case 0x6f:  /* outsw/outsl */
13149
4.74k
    intel_operand_size (ins, z_mode, sizeflag);
13150
4.74k
    break;
13151
2.47k
  case 0xa5:  /* movsw/movsl/movsq */
13152
5.41k
  case 0xa7:  /* cmpsw/cmpsl/cmpsq */
13153
7.89k
  case 0xad:  /* lodsw/lodsl/lodsq */
13154
7.89k
    intel_operand_size (ins, v_mode, sizeflag);
13155
7.89k
    break;
13156
37.3k
  default:
13157
37.3k
    intel_operand_size (ins, b_mode, sizeflag);
13158
50.1k
  }
13159
50.1k
    }
13160
  /* Outside of 64-bit mode set ins->active_seg_prefix to PREFIX_DS if it
13161
     is unset, so that the default segment register DS is printed.  */
13162
796k
  if (ins->address_mode != mode_64bit && !ins->active_seg_prefix)
13163
239k
    ins->active_seg_prefix = PREFIX_DS;
13164
796k
  append_seg (ins);
13165
796k
  ptr_reg (ins, code, sizeflag);
13166
796k
  return true;
13167
796k
}
13168
13169
static bool
13170
OP_C (instr_info *ins, int dummy ATTRIBUTE_UNUSED,
13171
      int sizeflag ATTRIBUTE_UNUSED)
13172
4.02k
{
13173
4.02k
  int add, res;
13174
4.02k
  char scratch[8];
13175
13176
4.02k
  if (ins->rex & REX_R)
13177
500
    {
13178
500
      USED_REX (REX_R);
13179
500
      add = 8;
13180
500
    }
13181
3.52k
  else if (ins->address_mode != mode_64bit && (ins->prefixes & PREFIX_LOCK))
13182
367
    {
13183
367
      ins->all_prefixes[ins->last_lock_prefix] = 0;
13184
367
      ins->used_prefixes |= PREFIX_LOCK;
13185
367
      add = 8;
13186
367
    }
13187
3.16k
  else
13188
3.16k
    add = 0;
13189
4.02k
  res = snprintf (scratch, ARRAY_SIZE (scratch), "%%cr%d",
13190
4.02k
      ins->modrm.reg + add);
13191
4.02k
  if (res < 0 || (size_t) res >= ARRAY_SIZE (scratch))
13192
0
    abort ();
13193
4.02k
  oappend_register (ins, scratch);
13194
4.02k
  return true;
13195
4.02k
}
13196
13197
static bool
13198
OP_D (instr_info *ins, int dummy ATTRIBUTE_UNUSED,
13199
      int sizeflag ATTRIBUTE_UNUSED)
13200
2.05k
{
13201
2.05k
  int add, res;
13202
2.05k
  char scratch[8];
13203
13204
2.05k
  USED_REX (REX_R);
13205
2.05k
  if (ins->rex & REX_R)
13206
680
    add = 8;
13207
1.37k
  else
13208
1.37k
    add = 0;
13209
2.05k
  res = snprintf (scratch, ARRAY_SIZE (scratch),
13210
2.05k
      ins->intel_syntax ? "dr%d" : "%%db%d",
13211
2.05k
      ins->modrm.reg + add);
13212
2.05k
  if (res < 0 || (size_t) res >= ARRAY_SIZE (scratch))
13213
0
    abort ();
13214
2.05k
  oappend (ins, scratch);
13215
2.05k
  return true;
13216
2.05k
}
13217
13218
static bool
13219
OP_T (instr_info *ins, int dummy ATTRIBUTE_UNUSED,
13220
      int sizeflag ATTRIBUTE_UNUSED)
13221
689
{
13222
689
  int res;
13223
689
  char scratch[8];
13224
13225
689
  res = snprintf (scratch, ARRAY_SIZE (scratch), "%%tr%d", ins->modrm.reg);
13226
689
  if (res < 0 || (size_t) res >= ARRAY_SIZE (scratch))
13227
0
    abort ();
13228
689
  oappend_register (ins, scratch);
13229
689
  return true;
13230
689
}
13231
13232
static bool
13233
OP_MMX (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13234
  int sizeflag ATTRIBUTE_UNUSED)
13235
54.8k
{
13236
54.8k
  int reg = ins->modrm.reg;
13237
54.8k
  const char (*names)[8];
13238
13239
54.8k
  ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
13240
54.8k
  if (ins->prefixes & PREFIX_DATA)
13241
4.82k
    {
13242
4.82k
      names = att_names_xmm;
13243
4.82k
      USED_REX (REX_R);
13244
4.82k
      if (ins->rex & REX_R)
13245
1.83k
  reg += 8;
13246
4.82k
    }
13247
50.0k
  else
13248
50.0k
    names = att_names_mm;
13249
54.8k
  oappend_register (ins, names[reg]);
13250
54.8k
  return true;
13251
54.8k
}
13252
13253
static void
13254
print_vector_reg (instr_info *ins, unsigned int reg, int bytemode)
13255
158k
{
13256
158k
  const char (*names)[8];
13257
13258
158k
  if (bytemode == xmmq_mode
13259
158k
      || bytemode == evex_half_bcst_xmmqh_mode
13260
158k
      || bytemode == evex_half_bcst_xmmq_mode)
13261
4.93k
    {
13262
4.93k
      switch (ins->vex.length)
13263
4.93k
  {
13264
1.04k
  case 0:
13265
1.94k
  case 128:
13266
2.97k
  case 256:
13267
2.97k
    names = att_names_xmm;
13268
2.97k
    break;
13269
1.95k
  case 512:
13270
1.95k
    names = att_names_ymm;
13271
1.95k
    ins->evex_used |= EVEX_len_used;
13272
1.95k
    break;
13273
0
  default:
13274
0
    abort ();
13275
4.93k
  }
13276
4.93k
    }
13277
154k
  else if (bytemode == ymm_mode)
13278
248
    names = att_names_ymm;
13279
153k
  else if (bytemode == tmm_mode)
13280
3.62k
    {
13281
3.62k
      if (reg >= 8)
13282
1.49k
  {
13283
1.49k
    oappend (ins, "(bad)");
13284
1.49k
    return;
13285
1.49k
  }
13286
2.13k
      names = att_names_tmm;
13287
2.13k
    }
13288
150k
  else if (ins->need_vex
13289
150k
     && bytemode != xmm_mode
13290
150k
     && bytemode != scalar_mode
13291
150k
     && bytemode != xmmdw_mode
13292
150k
     && bytemode != xmmqd_mode
13293
150k
     && bytemode != evex_half_bcst_xmmqdh_mode
13294
150k
     && bytemode != w_swap_mode
13295
150k
     && bytemode != b_mode
13296
150k
     && bytemode != w_mode
13297
150k
     && bytemode != d_mode
13298
150k
     && bytemode != q_mode)
13299
71.7k
    {
13300
71.7k
      ins->evex_used |= EVEX_len_used;
13301
71.7k
      switch (ins->vex.length)
13302
71.7k
  {
13303
31.1k
  case 128:
13304
31.1k
    names = att_names_xmm;
13305
31.1k
    break;
13306
21.3k
  case 256:
13307
21.3k
    if (ins->vex.w
13308
21.3k
        || bytemode != vex_vsib_q_w_dq_mode)
13309
20.5k
      names = att_names_ymm;
13310
836
    else
13311
836
      names = att_names_xmm;
13312
21.3k
    break;
13313
19.2k
  case 512:
13314
19.2k
    if (ins->vex.w
13315
19.2k
        || bytemode != vex_vsib_q_w_dq_mode)
13316
18.5k
      names = att_names_zmm;
13317
693
    else
13318
693
      names = att_names_ymm;
13319
19.2k
    break;
13320
0
  default:
13321
0
    abort ();
13322
71.7k
  }
13323
71.7k
    }
13324
78.4k
  else
13325
78.4k
    names = att_names_xmm;
13326
157k
  oappend_register (ins, names[reg]);
13327
157k
}
13328
13329
static bool
13330
OP_XMM (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13331
132k
{
13332
132k
  unsigned int reg = ins->modrm.reg;
13333
13334
132k
  USED_REX (REX_R);
13335
132k
  if (ins->rex & REX_R)
13336
43.0k
    reg += 8;
13337
132k
  if (ins->vex.evex)
13338
45.0k
    {
13339
45.0k
      if (ins->rex2 & REX_R)
13340
23.9k
  reg += 16;
13341
45.0k
    }
13342
13343
132k
  if (bytemode == tmm_mode)
13344
2.05k
    ins->modrm.reg = reg;
13345
130k
  else if (bytemode == scalar_mode)
13346
13.4k
    ins->vex.no_broadcast = true;
13347
13348
132k
  print_vector_reg (ins, reg, bytemode);
13349
132k
  return true;
13350
132k
}
13351
13352
static bool
13353
OP_EM (instr_info *ins, int bytemode, int sizeflag)
13354
54.2k
{
13355
54.2k
  int reg;
13356
54.2k
  const char (*names)[8];
13357
13358
54.2k
  if (ins->modrm.mod != 3)
13359
38.3k
    {
13360
38.3k
      if (ins->intel_syntax
13361
38.3k
    && (bytemode == v_mode || bytemode == v_swap_mode))
13362
9.42k
  {
13363
9.42k
    bytemode = (ins->prefixes & PREFIX_DATA) ? x_mode : q_mode;
13364
9.42k
    ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
13365
9.42k
  }
13366
38.3k
      return OP_E (ins, bytemode, sizeflag);
13367
38.3k
    }
13368
13369
15.8k
  if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
13370
190
    swap_operand (ins);
13371
13372
  /* Skip mod/rm byte.  */
13373
15.8k
  MODRM_CHECK;
13374
15.8k
  ins->codep++;
13375
15.8k
  ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
13376
15.8k
  reg = ins->modrm.rm;
13377
15.8k
  if (ins->prefixes & PREFIX_DATA)
13378
3.90k
    {
13379
3.90k
      names = att_names_xmm;
13380
3.90k
      USED_REX (REX_B);
13381
3.90k
      if (ins->rex & REX_B)
13382
1.90k
  reg += 8;
13383
3.90k
    }
13384
11.9k
  else
13385
11.9k
    names = att_names_mm;
13386
15.8k
  oappend_register (ins, names[reg]);
13387
15.8k
  return true;
13388
15.8k
}
13389
13390
/* cvt* are the only instructions in sse2 which have
13391
   both SSE and MMX operands and also have 0x66 prefix
13392
   in their opcode. 0x66 was originally used to differentiate
13393
   between SSE and MMX instruction(operands). So we have to handle the
13394
   cvt* separately using OP_EMC and OP_MXC */
13395
static bool
13396
OP_EMC (instr_info *ins, int bytemode, int sizeflag)
13397
1.25k
{
13398
1.25k
  if (ins->modrm.mod != 3)
13399
884
    {
13400
884
      if (ins->intel_syntax && bytemode == v_mode)
13401
0
  {
13402
0
    bytemode = (ins->prefixes & PREFIX_DATA) ? x_mode : q_mode;
13403
0
    ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
13404
0
  }
13405
884
      return OP_E (ins, bytemode, sizeflag);
13406
884
    }
13407
13408
  /* Skip mod/rm byte.  */
13409
372
  MODRM_CHECK;
13410
372
  ins->codep++;
13411
372
  ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
13412
372
  oappend_register (ins, att_names_mm[ins->modrm.rm]);
13413
372
  return true;
13414
372
}
13415
13416
static bool
13417
OP_MXC (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13418
  int sizeflag ATTRIBUTE_UNUSED)
13419
799
{
13420
799
  ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
13421
799
  oappend_register (ins, att_names_mm[ins->modrm.reg]);
13422
799
  return true;
13423
799
}
13424
13425
static bool
13426
OP_EX (instr_info *ins, int bytemode, int sizeflag)
13427
124k
{
13428
124k
  int reg;
13429
13430
  /* Skip mod/rm byte.  */
13431
124k
  MODRM_CHECK;
13432
124k
  ins->codep++;
13433
13434
124k
  if (bytemode == dq_mode)
13435
753
    bytemode = ins->vex.w ? q_mode : d_mode;
13436
13437
124k
  if (ins->modrm.mod != 3)
13438
98.0k
    return OP_E_memory (ins, bytemode, sizeflag);
13439
13440
26.7k
  reg = ins->modrm.rm;
13441
26.7k
  USED_REX (REX_B);
13442
26.7k
  if (ins->rex & REX_B)
13443
5.42k
    reg += 8;
13444
26.7k
  if (ins->vex.evex)
13445
9.62k
    {
13446
9.62k
      USED_REX (REX_X);
13447
9.62k
      if ((ins->rex & REX_X))
13448
2.71k
  reg += 16;
13449
9.62k
      ins->rex2_used &= ~REX_B;
13450
9.62k
    }
13451
17.1k
  else if (ins->rex2 & REX_B)
13452
273
    reg += 16;
13453
13454
26.7k
  if ((sizeflag & SUFFIX_ALWAYS)
13455
26.7k
      && (bytemode == x_swap_mode
13456
1.96k
    || bytemode == w_swap_mode
13457
1.96k
    || bytemode == d_swap_mode
13458
1.96k
    || bytemode == q_swap_mode))
13459
1.02k
    swap_operand (ins);
13460
13461
26.7k
  if (bytemode == tmm_mode)
13462
1.56k
    ins->modrm.rm = reg;
13463
13464
26.7k
  print_vector_reg (ins, reg, bytemode);
13465
26.7k
  return true;
13466
124k
}
13467
13468
static bool
13469
OP_R (instr_info *ins, int bytemode, int sizeflag)
13470
15.9k
{
13471
15.9k
  if (ins->modrm.mod != 3)
13472
3.42k
    return BadOp (ins);
13473
13474
12.5k
  switch (bytemode)
13475
12.5k
    {
13476
496
    case d_mode:
13477
854
    case dq_mode:
13478
1.54k
    case q_mode:
13479
2.35k
    case mask_mode:
13480
2.35k
      return OP_E (ins, bytemode, sizeflag);
13481
1.19k
    case q_mm_mode:
13482
1.19k
      return OP_EM (ins, x_mode, sizeflag);
13483
6.86k
    case xmm_mode:
13484
6.86k
      if (ins->vex.length <= 128)
13485
496
  break;
13486
6.36k
      return BadOp (ins);
13487
12.5k
    }
13488
13489
2.64k
  return OP_EX (ins, bytemode, sizeflag);
13490
12.5k
}
13491
13492
static bool
13493
OP_M (instr_info *ins, int bytemode, int sizeflag)
13494
837k
{
13495
  /* Skip mod/rm byte.  */
13496
837k
  MODRM_CHECK;
13497
837k
  ins->codep++;
13498
13499
837k
  if (ins->modrm.mod == 3)
13500
    /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
13501
7.26k
    return BadOp (ins);
13502
13503
830k
  if (bytemode == x_mode)
13504
583
    ins->vex.no_broadcast = true;
13505
13506
830k
  return OP_E_memory (ins, bytemode, sizeflag);
13507
837k
}
13508
13509
static bool
13510
OP_0f07 (instr_info *ins, int bytemode, int sizeflag)
13511
2.43k
{
13512
2.43k
  if (ins->modrm.mod != 3 || ins->modrm.rm != 0)
13513
2.12k
    return BadOp (ins);
13514
316
  return OP_E (ins, bytemode, sizeflag);
13515
2.43k
}
13516
13517
/* montmul instruction need display repz and skip modrm */
13518
13519
static bool
13520
MONTMUL_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13521
611
{
13522
611
  if (ins->modrm.mod != 3 || ins->modrm.rm != 0)
13523
421
    return BadOp (ins);
13524
13525
  /* The 0xf3 prefix should be displayed as "repz" for montmul. */
13526
190
  if (ins->prefixes & PREFIX_REPZ)
13527
190
    ins->all_prefixes[ins->last_repz_prefix] = 0xf3;
13528
13529
  /* Skip mod/rm byte.  */
13530
190
  MODRM_CHECK;
13531
190
  ins->codep++;
13532
190
  return true;
13533
190
}
13534
13535
/* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
13536
   32bit mode and "xchg %rax,%rax" in 64bit mode.  */
13537
13538
static bool
13539
NOP_Fixup (instr_info *ins, int opnd, int sizeflag)
13540
1.62M
{
13541
1.62M
  if ((ins->prefixes & PREFIX_DATA) == 0 && (ins->rex & REX_B) == 0)
13542
1.59M
    {
13543
1.59M
      ins->mnemonicendp = stpcpy (ins->obuf, "nop");
13544
1.59M
      return true;
13545
1.59M
    }
13546
24.2k
  if (opnd == 0)
13547
12.1k
    return OP_REG (ins, eAX_reg, sizeflag);
13548
12.1k
  return OP_IMREG (ins, eAX_reg, sizeflag);
13549
24.2k
}
13550
13551
static const char *const Suffix3DNow[] = {
13552
/* 00 */  NULL,   NULL,   NULL,   NULL,
13553
/* 04 */  NULL,   NULL,   NULL,   NULL,
13554
/* 08 */  NULL,   NULL,   NULL,   NULL,
13555
/* 0C */  "pi2fw",  "pi2fd",  NULL,   NULL,
13556
/* 10 */  NULL,   NULL,   NULL,   NULL,
13557
/* 14 */  NULL,   NULL,   NULL,   NULL,
13558
/* 18 */  NULL,   NULL,   NULL,   NULL,
13559
/* 1C */  "pf2iw",  "pf2id",  NULL,   NULL,
13560
/* 20 */  NULL,   NULL,   NULL,   NULL,
13561
/* 24 */  NULL,   NULL,   NULL,   NULL,
13562
/* 28 */  NULL,   NULL,   NULL,   NULL,
13563
/* 2C */  NULL,   NULL,   NULL,   NULL,
13564
/* 30 */  NULL,   NULL,   NULL,   NULL,
13565
/* 34 */  NULL,   NULL,   NULL,   NULL,
13566
/* 38 */  NULL,   NULL,   NULL,   NULL,
13567
/* 3C */  NULL,   NULL,   NULL,   NULL,
13568
/* 40 */  NULL,   NULL,   NULL,   NULL,
13569
/* 44 */  NULL,   NULL,   NULL,   NULL,
13570
/* 48 */  NULL,   NULL,   NULL,   NULL,
13571
/* 4C */  NULL,   NULL,   NULL,   NULL,
13572
/* 50 */  NULL,   NULL,   NULL,   NULL,
13573
/* 54 */  NULL,   NULL,   NULL,   NULL,
13574
/* 58 */  NULL,   NULL,   NULL,   NULL,
13575
/* 5C */  NULL,   NULL,   NULL,   NULL,
13576
/* 60 */  NULL,   NULL,   NULL,   NULL,
13577
/* 64 */  NULL,   NULL,   NULL,   NULL,
13578
/* 68 */  NULL,   NULL,   NULL,   NULL,
13579
/* 6C */  NULL,   NULL,   NULL,   NULL,
13580
/* 70 */  NULL,   NULL,   NULL,   NULL,
13581
/* 74 */  NULL,   NULL,   NULL,   NULL,
13582
/* 78 */  NULL,   NULL,   NULL,   NULL,
13583
/* 7C */  NULL,   NULL,   NULL,   NULL,
13584
/* 80 */  NULL,   NULL,   NULL,   NULL,
13585
/* 84 */  NULL,   NULL,   NULL,   NULL,
13586
/* 88 */  NULL,   NULL,   "pfnacc", NULL,
13587
/* 8C */  NULL,   NULL,   "pfpnacc",  NULL,
13588
/* 90 */  "pfcmpge",  NULL,   NULL,   NULL,
13589
/* 94 */  "pfmin",  NULL,   "pfrcp",  "pfrsqrt",
13590
/* 98 */  NULL,   NULL,   "pfsub",  NULL,
13591
/* 9C */  NULL,   NULL,   "pfadd",  NULL,
13592
/* A0 */  "pfcmpgt",  NULL,   NULL,   NULL,
13593
/* A4 */  "pfmax",  NULL,   "pfrcpit1", "pfrsqit1",
13594
/* A8 */  NULL,   NULL,   "pfsubr", NULL,
13595
/* AC */  NULL,   NULL,   "pfacc",  NULL,
13596
/* B0 */  "pfcmpeq",  NULL,   NULL,   NULL,
13597
/* B4 */  "pfmul",  NULL,   "pfrcpit2", "pmulhrw",
13598
/* B8 */  NULL,   NULL,   NULL,   "pswapd",
13599
/* BC */  NULL,   NULL,   NULL,   "pavgusb",
13600
/* C0 */  NULL,   NULL,   NULL,   NULL,
13601
/* C4 */  NULL,   NULL,   NULL,   NULL,
13602
/* C8 */  NULL,   NULL,   NULL,   NULL,
13603
/* CC */  NULL,   NULL,   NULL,   NULL,
13604
/* D0 */  NULL,   NULL,   NULL,   NULL,
13605
/* D4 */  NULL,   NULL,   NULL,   NULL,
13606
/* D8 */  NULL,   NULL,   NULL,   NULL,
13607
/* DC */  NULL,   NULL,   NULL,   NULL,
13608
/* E0 */  NULL,   NULL,   NULL,   NULL,
13609
/* E4 */  NULL,   NULL,   NULL,   NULL,
13610
/* E8 */  NULL,   NULL,   NULL,   NULL,
13611
/* EC */  NULL,   NULL,   NULL,   NULL,
13612
/* F0 */  NULL,   NULL,   NULL,   NULL,
13613
/* F4 */  NULL,   NULL,   NULL,   NULL,
13614
/* F8 */  NULL,   NULL,   NULL,   NULL,
13615
/* FC */  NULL,   NULL,   NULL,   NULL,
13616
};
13617
13618
static bool
13619
OP_3DNowSuffix (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13620
    int sizeflag ATTRIBUTE_UNUSED)
13621
29.0k
{
13622
29.0k
  const char *mnemonic;
13623
13624
29.0k
  if (!fetch_code (ins->info, ins->codep + 1))
13625
371
    return false;
13626
  /* AMD 3DNow! instructions are specified by an opcode suffix in the
13627
     place where an 8-bit immediate would normally go.  ie. the last
13628
     byte of the instruction.  */
13629
28.6k
  ins->obufp = ins->mnemonicendp;
13630
28.6k
  mnemonic = Suffix3DNow[*ins->codep++];
13631
28.6k
  if (mnemonic)
13632
827
    ins->obufp = stpcpy (ins->obufp, mnemonic);
13633
27.8k
  else
13634
27.8k
    {
13635
      /* Since a variable sized ins->modrm/ins->sib chunk is between the start
13636
   of the opcode (0x0f0f) and the opcode suffix, we need to do
13637
   all the ins->modrm processing first, and don't know until now that
13638
   we have a bad opcode.  This necessitates some cleaning up.  */
13639
27.8k
      ins->op_out[0][0] = '\0';
13640
27.8k
      ins->op_out[1][0] = '\0';
13641
27.8k
      BadOp (ins);
13642
27.8k
    }
13643
28.6k
  ins->mnemonicendp = ins->obufp;
13644
28.6k
  return true;
13645
29.0k
}
13646
13647
static const struct op simd_cmp_op[] =
13648
{
13649
  { STRING_COMMA_LEN ("eq") },
13650
  { STRING_COMMA_LEN ("lt") },
13651
  { STRING_COMMA_LEN ("le") },
13652
  { STRING_COMMA_LEN ("unord") },
13653
  { STRING_COMMA_LEN ("neq") },
13654
  { STRING_COMMA_LEN ("nlt") },
13655
  { STRING_COMMA_LEN ("nle") },
13656
  { STRING_COMMA_LEN ("ord") }
13657
};
13658
13659
static const struct op vex_cmp_op[] =
13660
{
13661
  { STRING_COMMA_LEN ("eq_uq") },
13662
  { STRING_COMMA_LEN ("nge") },
13663
  { STRING_COMMA_LEN ("ngt") },
13664
  { STRING_COMMA_LEN ("false") },
13665
  { STRING_COMMA_LEN ("neq_oq") },
13666
  { STRING_COMMA_LEN ("ge") },
13667
  { STRING_COMMA_LEN ("gt") },
13668
  { STRING_COMMA_LEN ("true") },
13669
  { STRING_COMMA_LEN ("eq_os") },
13670
  { STRING_COMMA_LEN ("lt_oq") },
13671
  { STRING_COMMA_LEN ("le_oq") },
13672
  { STRING_COMMA_LEN ("unord_s") },
13673
  { STRING_COMMA_LEN ("neq_us") },
13674
  { STRING_COMMA_LEN ("nlt_uq") },
13675
  { STRING_COMMA_LEN ("nle_uq") },
13676
  { STRING_COMMA_LEN ("ord_s") },
13677
  { STRING_COMMA_LEN ("eq_us") },
13678
  { STRING_COMMA_LEN ("nge_uq") },
13679
  { STRING_COMMA_LEN ("ngt_uq") },
13680
  { STRING_COMMA_LEN ("false_os") },
13681
  { STRING_COMMA_LEN ("neq_os") },
13682
  { STRING_COMMA_LEN ("ge_oq") },
13683
  { STRING_COMMA_LEN ("gt_oq") },
13684
  { STRING_COMMA_LEN ("true_us") },
13685
};
13686
13687
static bool
13688
CMP_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13689
     int sizeflag ATTRIBUTE_UNUSED)
13690
2.72k
{
13691
2.72k
  unsigned int cmp_type;
13692
13693
2.72k
  if (!fetch_code (ins->info, ins->codep + 1))
13694
475
    return false;
13695
2.25k
  cmp_type = *ins->codep++;
13696
2.25k
  if (cmp_type < ARRAY_SIZE (simd_cmp_op))
13697
631
    {
13698
631
      char suffix[3];
13699
631
      char *p = ins->mnemonicendp - 2;
13700
631
      suffix[0] = p[0];
13701
631
      suffix[1] = p[1];
13702
631
      suffix[2] = '\0';
13703
631
      sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
13704
631
      ins->mnemonicendp += simd_cmp_op[cmp_type].len;
13705
631
    }
13706
1.61k
  else if (ins->need_vex
13707
1.61k
     && cmp_type < ARRAY_SIZE (simd_cmp_op) + ARRAY_SIZE (vex_cmp_op))
13708
300
    {
13709
300
      char suffix[3];
13710
300
      char *p = ins->mnemonicendp - 2;
13711
300
      suffix[0] = p[0];
13712
300
      suffix[1] = p[1];
13713
300
      suffix[2] = '\0';
13714
300
      cmp_type -= ARRAY_SIZE (simd_cmp_op);
13715
300
      sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
13716
300
      ins->mnemonicendp += vex_cmp_op[cmp_type].len;
13717
300
    }
13718
1.31k
  else
13719
1.31k
    {
13720
      /* We have a reserved extension byte.  Output it directly.  */
13721
1.31k
      oappend_immediate (ins, cmp_type);
13722
1.31k
    }
13723
2.25k
  return true;
13724
2.72k
}
13725
13726
static bool
13727
OP_Mwait (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13728
1.32k
{
13729
  /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx  */
13730
1.32k
  if (!ins->intel_syntax)
13731
622
    {
13732
622
      strcpy (ins->op_out[0], att_names32[0] + ins->intel_syntax);
13733
622
      strcpy (ins->op_out[1], att_names32[1] + ins->intel_syntax);
13734
622
      if (bytemode == eBX_reg)
13735
216
  strcpy (ins->op_out[2], att_names32[3] + ins->intel_syntax);
13736
622
      ins->two_source_ops = true;
13737
622
    }
13738
  /* Skip mod/rm byte.  */
13739
1.32k
  MODRM_CHECK;
13740
1.32k
  ins->codep++;
13741
1.32k
  return true;
13742
1.32k
}
13743
13744
static bool
13745
OP_Monitor (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13746
      int sizeflag ATTRIBUTE_UNUSED)
13747
2.15k
{
13748
  /* monitor %{e,r,}ax,%ecx,%edx"  */
13749
2.15k
  if (!ins->intel_syntax)
13750
1.53k
    {
13751
1.53k
      const char (*names)[8] = (ins->address_mode == mode_64bit
13752
1.53k
        ? att_names64 : att_names32);
13753
13754
1.53k
      if (ins->prefixes & PREFIX_ADDR)
13755
773
  {
13756
    /* Remove "addr16/addr32".  */
13757
773
    ins->all_prefixes[ins->last_addr_prefix] = 0;
13758
773
    names = (ins->address_mode != mode_32bit
13759
773
       ? att_names32 : att_names16);
13760
773
    ins->used_prefixes |= PREFIX_ADDR;
13761
773
  }
13762
762
      else if (ins->address_mode == mode_16bit)
13763
233
  names = att_names16;
13764
1.53k
      strcpy (ins->op_out[0], names[0] + ins->intel_syntax);
13765
1.53k
      strcpy (ins->op_out[1], att_names32[1] + ins->intel_syntax);
13766
1.53k
      strcpy (ins->op_out[2], att_names32[2] + ins->intel_syntax);
13767
1.53k
      ins->two_source_ops = true;
13768
1.53k
    }
13769
  /* Skip mod/rm byte.  */
13770
2.15k
  MODRM_CHECK;
13771
2.15k
  ins->codep++;
13772
2.15k
  return true;
13773
2.15k
}
13774
13775
static bool
13776
REP_Fixup (instr_info *ins, int bytemode, int sizeflag)
13777
1.10M
{
13778
  /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
13779
     lods and stos.  */
13780
1.10M
  if (ins->prefixes & PREFIX_REPZ)
13781
2.55k
    ins->all_prefixes[ins->last_repz_prefix] = REP_PREFIX;
13782
13783
1.10M
  switch (bytemode)
13784
1.10M
    {
13785
34.8k
    case al_reg:
13786
65.2k
    case eAX_reg:
13787
551k
    case indir_dx_reg:
13788
551k
      return OP_IMREG (ins, bytemode, sizeflag);
13789
548k
    case eDI_reg:
13790
548k
      return OP_ESreg (ins, bytemode, sizeflag);
13791
0
    case eSI_reg:
13792
0
      return OP_DSreg (ins, bytemode, sizeflag);
13793
0
    default:
13794
0
      abort ();
13795
0
      break;
13796
1.10M
    }
13797
0
  return true;
13798
1.10M
}
13799
13800
static bool
13801
SEP_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13802
     int sizeflag ATTRIBUTE_UNUSED)
13803
1.76k
{
13804
1.76k
  if (ins->isa64 != amd64)
13805
1.57k
    return true;
13806
13807
194
  ins->obufp = ins->obuf;
13808
194
  BadOp (ins);
13809
194
  ins->mnemonicendp = ins->obufp;
13810
194
  ++ins->codep;
13811
194
  return true;
13812
1.76k
}
13813
13814
/* For BND-prefixed instructions 0xF2 prefix should be displayed as
13815
   "bnd".  */
13816
13817
static bool
13818
BND_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13819
     int sizeflag ATTRIBUTE_UNUSED)
13820
5.55M
{
13821
5.55M
  if (ins->prefixes & PREFIX_REPNZ)
13822
3.11k
    ins->all_prefixes[ins->last_repnz_prefix] = BND_PREFIX;
13823
5.55M
  return true;
13824
5.55M
}
13825
13826
/* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
13827
   "notrack".  */
13828
13829
static bool
13830
NOTRACK_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13831
         int sizeflag ATTRIBUTE_UNUSED)
13832
392k
{
13833
  /* Since active_seg_prefix is not set in 64-bit mode, check whether
13834
     we've seen a PREFIX_DS.  */
13835
392k
  if ((ins->prefixes & PREFIX_DS) != 0
13836
392k
      && (ins->address_mode != mode_64bit || ins->last_data_prefix < 0))
13837
2.42k
    {
13838
      /* NOTRACK prefix is only valid on indirect branch instructions.
13839
   NB: DATA prefix is unsupported for Intel64.  */
13840
2.42k
      ins->active_seg_prefix = 0;
13841
2.42k
      ins->all_prefixes[ins->last_seg_prefix] = NOTRACK_PREFIX;
13842
2.42k
    }
13843
392k
  return true;
13844
392k
}
13845
13846
/* Similar to OP_E.  But the 0xf2/0xf3 ins->prefixes should be displayed as
13847
   "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
13848
 */
13849
13850
static bool
13851
HLE_Fixup1 (instr_info *ins, int bytemode, int sizeflag)
13852
13.5M
{
13853
13.5M
  if (ins->modrm.mod != 3
13854
13.5M
      && (ins->prefixes & PREFIX_LOCK) != 0)
13855
12.3k
    {
13856
12.3k
      if (ins->prefixes & PREFIX_REPZ)
13857
619
  ins->all_prefixes[ins->last_repz_prefix] = XRELEASE_PREFIX;
13858
12.3k
      if (ins->prefixes & PREFIX_REPNZ)
13859
324
  ins->all_prefixes[ins->last_repnz_prefix] = XACQUIRE_PREFIX;
13860
12.3k
    }
13861
13862
13.5M
  return OP_E (ins, bytemode, sizeflag);
13863
13.5M
}
13864
13865
/* Similar to OP_E.  But the 0xf2/0xf3 ins->prefixes should be displayed as
13866
   "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
13867
 */
13868
13869
static bool
13870
HLE_Fixup2 (instr_info *ins, int bytemode, int sizeflag)
13871
71.5k
{
13872
71.5k
  if (ins->modrm.mod != 3)
13873
65.3k
    {
13874
65.3k
      if (ins->prefixes & PREFIX_REPZ)
13875
629
  ins->all_prefixes[ins->last_repz_prefix] = XRELEASE_PREFIX;
13876
65.3k
      if (ins->prefixes & PREFIX_REPNZ)
13877
1.46k
  ins->all_prefixes[ins->last_repnz_prefix] = XACQUIRE_PREFIX;
13878
65.3k
    }
13879
13880
71.5k
  return OP_E (ins, bytemode, sizeflag);
13881
71.5k
}
13882
13883
/* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
13884
   "xrelease" for memory operand.  No check for LOCK prefix.   */
13885
13886
static bool
13887
HLE_Fixup3 (instr_info *ins, int bytemode, int sizeflag)
13888
1.70M
{
13889
1.70M
  if (ins->modrm.mod != 3
13890
1.70M
      && ins->last_repz_prefix > ins->last_repnz_prefix
13891
1.70M
      && (ins->prefixes & PREFIX_REPZ) != 0)
13892
366
    ins->all_prefixes[ins->last_repz_prefix] = XRELEASE_PREFIX;
13893
13894
1.70M
  return OP_E (ins, bytemode, sizeflag);
13895
1.70M
}
13896
13897
static bool
13898
CMPXCHG8B_Fixup (instr_info *ins, int bytemode, int sizeflag)
13899
3.11k
{
13900
3.11k
  USED_REX (REX_W);
13901
3.11k
  if (ins->rex & REX_W)
13902
349
    {
13903
      /* Change cmpxchg8b to cmpxchg16b.  */
13904
349
      char *p = ins->mnemonicendp - 2;
13905
349
      ins->mnemonicendp = stpcpy (p, "16b");
13906
349
      bytemode = o_mode;
13907
349
    }
13908
2.76k
  else if ((ins->prefixes & PREFIX_LOCK) != 0)
13909
1.54k
    {
13910
1.54k
      if (ins->prefixes & PREFIX_REPZ)
13911
1.08k
  ins->all_prefixes[ins->last_repz_prefix] = XRELEASE_PREFIX;
13912
1.54k
      if (ins->prefixes & PREFIX_REPNZ)
13913
197
  ins->all_prefixes[ins->last_repnz_prefix] = XACQUIRE_PREFIX;
13914
1.54k
    }
13915
13916
3.11k
  return OP_M (ins, bytemode, sizeflag);
13917
3.11k
}
13918
13919
static bool
13920
XMM_Fixup (instr_info *ins, int reg, int sizeflag ATTRIBUTE_UNUSED)
13921
454
{
13922
454
  const char (*names)[8] = att_names_xmm;
13923
13924
454
  if (ins->need_vex)
13925
0
    {
13926
0
      switch (ins->vex.length)
13927
0
  {
13928
0
  case 128:
13929
0
    break;
13930
0
  case 256:
13931
0
    names = att_names_ymm;
13932
0
    break;
13933
0
  default:
13934
0
    abort ();
13935
0
  }
13936
0
    }
13937
454
  oappend_register (ins, names[reg]);
13938
454
  return true;
13939
454
}
13940
13941
static bool
13942
FXSAVE_Fixup (instr_info *ins, int bytemode, int sizeflag)
13943
1.19k
{
13944
  /* Add proper suffix to "fxsave" and "fxrstor".  */
13945
1.19k
  USED_REX (REX_W);
13946
1.19k
  if (ins->rex & REX_W)
13947
483
    {
13948
483
      char *p = ins->mnemonicendp;
13949
483
      *p++ = '6';
13950
483
      *p++ = '4';
13951
483
      *p = '\0';
13952
483
      ins->mnemonicendp = p;
13953
483
    }
13954
1.19k
  return OP_M (ins, bytemode, sizeflag);
13955
1.19k
}
13956
13957
/* Display the destination register operand for instructions with
13958
   VEX. */
13959
13960
static bool
13961
OP_VEX (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13962
535k
{
13963
535k
  int reg, modrm_reg, sib_index = -1;
13964
535k
  const char (*names)[8];
13965
13966
535k
  if (!ins->need_vex)
13967
471k
    return true;
13968
13969
63.9k
  if (ins->evex_type == evex_from_legacy)
13970
8.64k
    {
13971
8.64k
      ins->evex_used |= EVEX_b_used;
13972
8.64k
      if (!ins->vex.nd)
13973
3.78k
  return true;
13974
8.64k
    }
13975
13976
60.1k
  reg = ins->vex.register_specifier;
13977
60.1k
  ins->vex.register_specifier = 0;
13978
60.1k
  if (ins->address_mode != mode_64bit)
13979
9.06k
    {
13980
9.06k
      if (ins->vex.evex && !ins->vex.v)
13981
2.52k
  {
13982
2.52k
    oappend (ins, "(bad)");
13983
2.52k
    return true;
13984
2.52k
  }
13985
13986
6.54k
      reg &= 7;
13987
6.54k
    }
13988
51.1k
  else if (ins->vex.evex && !ins->vex.v)
13989
14.7k
    reg += 16;
13990
13991
57.6k
  switch (bytemode)
13992
57.6k
    {
13993
7.63k
    case scalar_mode:
13994
7.63k
      oappend_register (ins, att_names_xmm[reg]);
13995
7.63k
      return true;
13996
13997
2.88k
    case vex_vsib_d_w_dq_mode:
13998
4.80k
    case vex_vsib_q_w_dq_mode:
13999
      /* This must be the 3rd operand.  */
14000
4.80k
      if (ins->obufp != ins->op_out[2])
14001
0
  abort ();
14002
4.80k
      if (ins->vex.length == 128
14003
4.80k
    || (bytemode != vex_vsib_d_w_dq_mode
14004
2.24k
        && !ins->vex.w))
14005
3.24k
  oappend_register (ins, att_names_xmm[reg]);
14006
1.56k
      else
14007
1.56k
  oappend_register (ins, att_names_ymm[reg]);
14008
14009
      /* All 3 XMM/YMM registers must be distinct.  */
14010
4.80k
      modrm_reg = ins->modrm.reg;
14011
4.80k
      if (ins->rex & REX_R)
14012
1.26k
  modrm_reg += 8;
14013
14014
4.80k
      if (ins->has_sib && ins->modrm.rm == 4)
14015
1.71k
  {
14016
1.71k
    sib_index = ins->sib.index;
14017
1.71k
    if (ins->rex & REX_X)
14018
317
      sib_index += 8;
14019
1.71k
  }
14020
14021
4.80k
      if (reg == modrm_reg || reg == sib_index)
14022
692
  strcpy (ins->obufp, "/(bad)");
14023
4.80k
      if (modrm_reg == sib_index || modrm_reg == reg)
14024
1.07k
  strcat (ins->op_out[0], "/(bad)");
14025
4.80k
      if (sib_index == modrm_reg || sib_index == reg)
14026
846
  strcat (ins->op_out[1], "/(bad)");
14027
14028
4.80k
      return true;
14029
14030
1.77k
    case tmm_mode:
14031
      /* All 3 TMM registers must be distinct.  */
14032
1.77k
      if (reg >= 8)
14033
436
  oappend (ins, "(bad)");
14034
1.34k
      else
14035
1.34k
  {
14036
    /* This must be the 3rd operand.  */
14037
1.34k
    if (ins->obufp != ins->op_out[2])
14038
0
      abort ();
14039
1.34k
    oappend_register (ins, att_names_tmm[reg]);
14040
1.34k
    if (reg == ins->modrm.reg || reg == ins->modrm.rm)
14041
771
      strcpy (ins->obufp, "/(bad)");
14042
1.34k
  }
14043
14044
1.77k
      if (ins->modrm.reg == ins->modrm.rm || ins->modrm.reg == reg
14045
1.77k
    || ins->modrm.rm == reg)
14046
1.38k
  {
14047
1.38k
    if (ins->modrm.reg <= 8
14048
1.38k
        && (ins->modrm.reg == ins->modrm.rm || ins->modrm.reg == reg))
14049
742
      strcat (ins->op_out[0], "/(bad)");
14050
1.38k
    if (ins->modrm.rm <= 8
14051
1.38k
        && (ins->modrm.rm == ins->modrm.reg || ins->modrm.rm == reg))
14052
578
      strcat (ins->op_out[1], "/(bad)");
14053
1.38k
  }
14054
14055
1.77k
      return true;
14056
14057
3.12k
    case v_mode:
14058
5.19k
    case dq_mode:
14059
5.19k
      if (ins->rex & REX_W)
14060
1.16k
  oappend_register (ins, att_names64[reg]);
14061
4.02k
      else if (bytemode == v_mode
14062
4.02k
         && !(sizeflag & DFLAG))
14063
529
  oappend_register (ins, att_names16[reg]);
14064
3.49k
      else
14065
3.49k
  oappend_register (ins, att_names32[reg]);
14066
5.19k
      return true;
14067
14068
850
    case b_mode:
14069
850
      oappend_register (ins, att_names8rex[reg]);
14070
850
      return true;
14071
14072
753
    case q_mode:
14073
753
      oappend_register (ins, att_names64[reg]);
14074
753
      return true;
14075
57.6k
    }
14076
14077
36.6k
  switch (ins->vex.length)
14078
36.6k
    {
14079
17.7k
    case 128:
14080
17.7k
      switch (bytemode)
14081
17.7k
  {
14082
17.7k
  case x_mode:
14083
17.7k
    names = att_names_xmm;
14084
17.7k
    ins->evex_used |= EVEX_len_used;
14085
17.7k
    break;
14086
0
  case mask_bd_mode:
14087
0
  case mask_mode:
14088
0
    if (reg > 0x7)
14089
0
      {
14090
0
        oappend (ins, "(bad)");
14091
0
        return true;
14092
0
      }
14093
0
    names = att_names_mask;
14094
0
    break;
14095
0
  default:
14096
0
    abort ();
14097
0
    return true;
14098
17.7k
  }
14099
17.7k
      break;
14100
17.7k
    case 256:
14101
9.43k
      switch (bytemode)
14102
9.43k
  {
14103
8.57k
  case x_mode:
14104
8.57k
    names = att_names_ymm;
14105
8.57k
    ins->evex_used |= EVEX_len_used;
14106
8.57k
    break;
14107
0
  case mask_bd_mode:
14108
851
  case mask_mode:
14109
851
    if (reg <= 0x7)
14110
496
      {
14111
496
        names = att_names_mask;
14112
496
        break;
14113
496
      }
14114
    /* Fall through.  */
14115
355
  default:
14116
    /* See PR binutils/20893 for a reproducer.  */
14117
355
    oappend (ins, "(bad)");
14118
355
    return true;
14119
9.43k
  }
14120
9.07k
      break;
14121
9.43k
    case 512:
14122
9.43k
      names = att_names_zmm;
14123
9.43k
      ins->evex_used |= EVEX_len_used;
14124
9.43k
      break;
14125
0
    default:
14126
0
      abort ();
14127
0
      break;
14128
36.6k
    }
14129
36.2k
  oappend_register (ins, names[reg]);
14130
36.2k
  return true;
14131
36.6k
}
14132
14133
static bool
14134
OP_VexR (instr_info *ins, int bytemode, int sizeflag)
14135
4.11k
{
14136
4.11k
  if (ins->modrm.mod == 3)
14137
1.72k
    return OP_VEX (ins, bytemode, sizeflag);
14138
2.39k
  return true;
14139
4.11k
}
14140
14141
static bool
14142
OP_VexW (instr_info *ins, int bytemode, int sizeflag)
14143
1.13k
{
14144
1.13k
  OP_VEX (ins, bytemode, sizeflag);
14145
14146
1.13k
  if (ins->vex.w)
14147
870
    {
14148
      /* Swap 2nd and 3rd operands.  */
14149
870
      char *tmp = ins->op_out[2];
14150
14151
870
      ins->op_out[2] = ins->op_out[1];
14152
870
      ins->op_out[1] = tmp;
14153
870
    }
14154
1.13k
  return true;
14155
1.13k
}
14156
14157
static bool
14158
OP_REG_VexI4 (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
14159
2.53k
{
14160
2.53k
  int reg;
14161
2.53k
  const char (*names)[8] = att_names_xmm;
14162
14163
2.53k
  if (!fetch_code (ins->info, ins->codep + 1))
14164
128
    return false;
14165
2.40k
  reg = *ins->codep++;
14166
14167
2.40k
  if (bytemode != x_mode && bytemode != scalar_mode)
14168
0
    abort ();
14169
14170
2.40k
  reg >>= 4;
14171
2.40k
  if (ins->address_mode != mode_64bit)
14172
358
    reg &= 7;
14173
14174
2.40k
  if (bytemode == x_mode && ins->vex.length == 256)
14175
1.18k
    names = att_names_ymm;
14176
14177
2.40k
  oappend_register (ins, names[reg]);
14178
14179
2.40k
  if (ins->vex.w)
14180
1.58k
    {
14181
      /* Swap 3rd and 4th operands.  */
14182
1.58k
      char *tmp = ins->op_out[3];
14183
14184
1.58k
      ins->op_out[3] = ins->op_out[2];
14185
1.58k
      ins->op_out[2] = tmp;
14186
1.58k
    }
14187
2.40k
  return true;
14188
2.40k
}
14189
14190
static bool
14191
OP_VexI4 (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
14192
    int sizeflag ATTRIBUTE_UNUSED)
14193
1.82k
{
14194
1.82k
  oappend_immediate (ins, ins->codep[-1] & 0xf);
14195
1.82k
  return true;
14196
1.82k
}
14197
14198
static bool
14199
VPCMP_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
14200
       int sizeflag ATTRIBUTE_UNUSED)
14201
1.92k
{
14202
1.92k
  unsigned int cmp_type;
14203
14204
1.92k
  if (!ins->vex.evex)
14205
0
    abort ();
14206
14207
1.92k
  if (!fetch_code (ins->info, ins->codep + 1))
14208
173
    return false;
14209
1.75k
  cmp_type = *ins->codep++;
14210
  /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
14211
     If it's the case, print suffix, otherwise - print the immediate.  */
14212
1.75k
  if (cmp_type < ARRAY_SIZE (simd_cmp_op)
14213
1.75k
      && cmp_type != 3
14214
1.75k
      && cmp_type != 7)
14215
668
    {
14216
668
      char suffix[3];
14217
668
      char *p = ins->mnemonicendp - 2;
14218
14219
      /* vpcmp* can have both one- and two-lettered suffix.  */
14220
668
      if (p[0] == 'p')
14221
405
  {
14222
405
    p++;
14223
405
    suffix[0] = p[0];
14224
405
    suffix[1] = '\0';
14225
405
  }
14226
263
      else
14227
263
  {
14228
263
    suffix[0] = p[0];
14229
263
    suffix[1] = p[1];
14230
263
    suffix[2] = '\0';
14231
263
  }
14232
14233
668
      sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
14234
668
      ins->mnemonicendp += simd_cmp_op[cmp_type].len;
14235
668
    }
14236
1.08k
  else
14237
1.08k
    {
14238
      /* We have a reserved extension byte.  Output it directly.  */
14239
1.08k
      oappend_immediate (ins, cmp_type);
14240
1.08k
    }
14241
1.75k
  return true;
14242
1.92k
}
14243
14244
static const struct op xop_cmp_op[] =
14245
{
14246
  { STRING_COMMA_LEN ("lt") },
14247
  { STRING_COMMA_LEN ("le") },
14248
  { STRING_COMMA_LEN ("gt") },
14249
  { STRING_COMMA_LEN ("ge") },
14250
  { STRING_COMMA_LEN ("eq") },
14251
  { STRING_COMMA_LEN ("neq") },
14252
  { STRING_COMMA_LEN ("false") },
14253
  { STRING_COMMA_LEN ("true") }
14254
};
14255
14256
static bool
14257
VPCOM_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
14258
       int sizeflag ATTRIBUTE_UNUSED)
14259
1.85k
{
14260
1.85k
  unsigned int cmp_type;
14261
14262
1.85k
  if (!fetch_code (ins->info, ins->codep + 1))
14263
89
    return false;
14264
1.77k
  cmp_type = *ins->codep++;
14265
1.77k
  if (cmp_type < ARRAY_SIZE (xop_cmp_op))
14266
943
    {
14267
943
      char suffix[3];
14268
943
      char *p = ins->mnemonicendp - 2;
14269
14270
      /* vpcom* can have both one- and two-lettered suffix.  */
14271
943
      if (p[0] == 'm')
14272
431
  {
14273
431
    p++;
14274
431
    suffix[0] = p[0];
14275
431
    suffix[1] = '\0';
14276
431
  }
14277
512
      else
14278
512
  {
14279
512
    suffix[0] = p[0];
14280
512
    suffix[1] = p[1];
14281
512
    suffix[2] = '\0';
14282
512
  }
14283
14284
943
      sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix);
14285
943
      ins->mnemonicendp += xop_cmp_op[cmp_type].len;
14286
943
    }
14287
827
  else
14288
827
    {
14289
      /* We have a reserved extension byte.  Output it directly.  */
14290
827
      oappend_immediate (ins, cmp_type);
14291
827
    }
14292
1.77k
  return true;
14293
1.85k
}
14294
14295
static const struct op pclmul_op[] =
14296
{
14297
  { STRING_COMMA_LEN ("lql") },
14298
  { STRING_COMMA_LEN ("hql") },
14299
  { STRING_COMMA_LEN ("lqh") },
14300
  { STRING_COMMA_LEN ("hqh") }
14301
};
14302
14303
static bool
14304
PCLMUL_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
14305
        int sizeflag ATTRIBUTE_UNUSED)
14306
1.91k
{
14307
1.91k
  unsigned int pclmul_type;
14308
14309
1.91k
  if (!fetch_code (ins->info, ins->codep + 1))
14310
212
    return false;
14311
1.70k
  pclmul_type = *ins->codep++;
14312
1.70k
  switch (pclmul_type)
14313
1.70k
    {
14314
230
    case 0x10:
14315
230
      pclmul_type = 2;
14316
230
      break;
14317
406
    case 0x11:
14318
406
      pclmul_type = 3;
14319
406
      break;
14320
1.07k
    default:
14321
1.07k
      break;
14322
1.70k
    }
14323
1.70k
  if (pclmul_type < ARRAY_SIZE (pclmul_op))
14324
818
    {
14325
818
      char suffix[4];
14326
818
      char *p = ins->mnemonicendp - 3;
14327
818
      suffix[0] = p[0];
14328
818
      suffix[1] = p[1];
14329
818
      suffix[2] = p[2];
14330
818
      suffix[3] = '\0';
14331
818
      sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
14332
818
      ins->mnemonicendp += pclmul_op[pclmul_type].len;
14333
818
    }
14334
888
  else
14335
888
    {
14336
      /* We have a reserved extension byte.  Output it directly.  */
14337
888
      oappend_immediate (ins, pclmul_type);
14338
888
    }
14339
1.70k
  return true;
14340
1.70k
}
14341
14342
static bool
14343
MOVSXD_Fixup (instr_info *ins, int bytemode, int sizeflag)
14344
180k
{
14345
  /* Add proper suffix to "movsxd".  */
14346
180k
  char *p = ins->mnemonicendp;
14347
14348
180k
  switch (bytemode)
14349
180k
    {
14350
180k
    case movsxd_mode:
14351
180k
      if (!ins->intel_syntax)
14352
177k
  {
14353
177k
    USED_REX (REX_W);
14354
177k
    if (ins->rex & REX_W)
14355
44.8k
      {
14356
44.8k
        *p++ = 'l';
14357
44.8k
        *p++ = 'q';
14358
44.8k
        break;
14359
44.8k
      }
14360
177k
  }
14361
14362
135k
      *p++ = 'x';
14363
135k
      *p++ = 'd';
14364
135k
      break;
14365
0
    default:
14366
0
      oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
14367
0
      break;
14368
180k
    }
14369
14370
180k
  ins->mnemonicendp = p;
14371
180k
  *p = '\0';
14372
180k
  return OP_E (ins, bytemode, sizeflag);
14373
180k
}
14374
14375
static bool
14376
DistinctDest_Fixup (instr_info *ins, int bytemode, int sizeflag)
14377
5.58k
{
14378
5.58k
  unsigned int reg = ins->vex.register_specifier;
14379
5.58k
  unsigned int modrm_reg = ins->modrm.reg;
14380
5.58k
  unsigned int modrm_rm = ins->modrm.rm;
14381
14382
  /* Calc destination register number.  */
14383
5.58k
  if (ins->rex & REX_R)
14384
471
    modrm_reg += 8;
14385
5.58k
  if (ins->rex2 & REX_R)
14386
1.40k
    modrm_reg += 16;
14387
14388
  /* Calc src1 register number.  */
14389
5.58k
  if (ins->address_mode != mode_64bit)
14390
1.14k
    reg &= 7;
14391
4.43k
  else if (ins->vex.evex && !ins->vex.v)
14392
2.67k
    reg += 16;
14393
14394
  /* Calc src2 register number.  */
14395
5.58k
  if (ins->modrm.mod == 3)
14396
2.00k
    {
14397
2.00k
      if (ins->rex & REX_B)
14398
1.27k
        modrm_rm += 8;
14399
2.00k
      if (ins->rex & REX_X)
14400
608
        modrm_rm += 16;
14401
2.00k
    }
14402
14403
  /* Destination and source registers must be distinct, output bad if
14404
     dest == src1 or dest == src2.  */
14405
5.58k
  if (modrm_reg == reg
14406
5.58k
      || (ins->modrm.mod == 3
14407
3.72k
    && modrm_reg == modrm_rm))
14408
2.25k
    {
14409
2.25k
      oappend (ins, "(bad)");
14410
2.25k
      return true;
14411
2.25k
    }
14412
3.33k
  return OP_XMM (ins, bytemode, sizeflag);
14413
5.58k
}
14414
14415
static bool
14416
OP_Rounding (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
14417
24.6k
{
14418
24.6k
  if (ins->modrm.mod != 3 || !ins->vex.b)
14419
20.3k
    return true;
14420
14421
4.23k
  ins->evex_used |= EVEX_b_used;
14422
4.23k
  switch (bytemode)
14423
4.23k
    {
14424
1.37k
    case evex_rounding_64_mode:
14425
1.37k
      if (ins->address_mode != mode_64bit || !ins->vex.w)
14426
645
        return true;
14427
      /* Fall through.  */
14428
2.86k
    case evex_rounding_mode:
14429
2.86k
      oappend (ins, names_rounding[ins->vex.ll]);
14430
2.86k
      break;
14431
725
    case evex_sae_mode:
14432
725
      oappend (ins, "{");
14433
725
      break;
14434
0
    default:
14435
0
      abort ();
14436
4.23k
    }
14437
3.59k
  oappend (ins, "sae}");
14438
3.59k
  return true;
14439
4.23k
}
14440
14441
static bool
14442
PREFETCHI_Fixup (instr_info *ins, int bytemode, int sizeflag)
14443
2.79k
{
14444
2.79k
  if (ins->modrm.mod != 0 || ins->modrm.rm != 5)
14445
2.48k
    {
14446
2.48k
      if (ins->intel_syntax)
14447
342
  {
14448
342
    ins->mnemonicendp = stpcpy (ins->obuf, "nop   ");
14449
342
  }
14450
2.14k
      else
14451
2.14k
  {
14452
2.14k
    USED_REX (REX_W);
14453
2.14k
    if (ins->rex & REX_W)
14454
311
      ins->mnemonicendp = stpcpy (ins->obuf, "nopq  ");
14455
1.83k
    else
14456
1.83k
      {
14457
1.83k
        if (sizeflag & DFLAG)
14458
1.62k
    ins->mnemonicendp = stpcpy (ins->obuf, "nopl  ");
14459
208
        else
14460
208
    ins->mnemonicendp = stpcpy (ins->obuf, "nopw  ");
14461
1.83k
        ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
14462
1.83k
      }
14463
2.14k
  }
14464
2.48k
      bytemode = v_mode;
14465
2.48k
    }
14466
14467
2.79k
  return OP_M (ins, bytemode, sizeflag);
14468
2.79k
}
14469
14470
static bool
14471
PUSH2_POP2_Fixup (instr_info *ins, int bytemode, int sizeflag)
14472
1.91k
{
14473
1.91k
  if (ins->modrm.mod != 3)
14474
258
    return true;
14475
14476
1.65k
  unsigned int vvvv_reg = ins->vex.register_specifier
14477
1.65k
    | (!ins->vex.v << 4);
14478
1.65k
  unsigned int rm_reg = ins->modrm.rm + (ins->rex & REX_B ? 8 : 0)
14479
1.65k
    + (ins->rex2 & REX_B ? 16 : 0);
14480
14481
  /* Push2/Pop2 cannot use RSP and Pop2 cannot pop two same registers.  */
14482
1.65k
  if (!ins->vex.nd || vvvv_reg == 0x4 || rm_reg == 0x4
14483
1.65k
      || (!ins->modrm.reg
14484
945
    && vvvv_reg == rm_reg))
14485
906
    {
14486
906
      oappend (ins, "(bad)");
14487
906
      return true;
14488
906
    }
14489
14490
753
  return OP_VEX (ins, bytemode, sizeflag);
14491
1.65k
}
14492
14493
static bool
14494
JMPABS_Fixup (instr_info *ins, int bytemode, int sizeflag)
14495
130k
{
14496
130k
  if (ins->last_rex2_prefix >= 0)
14497
1.72k
    {
14498
1.72k
      uint64_t op;
14499
14500
1.72k
      if ((ins->prefixes & (PREFIX_OPCODE | PREFIX_ADDR | PREFIX_LOCK)) != 0x0
14501
1.72k
    || (ins->rex & REX_W) != 0x0)
14502
780
  {
14503
780
    oappend (ins, "(bad)");
14504
780
    return true;
14505
780
  }
14506
14507
948
      if (bytemode == eAX_reg)
14508
474
  return true;
14509
14510
474
      if (!get64 (ins, &op))
14511
67
  return false;
14512
14513
407
      ins->mnemonicendp = stpcpy (ins->obuf, "jmpabs");
14514
407
      ins->rex2 |= REX2_SPECIAL;
14515
407
      oappend_immediate (ins, op);
14516
14517
407
      return true;
14518
474
    }
14519
14520
129k
  if (bytemode == eAX_reg)
14521
64.5k
    return OP_IMREG (ins, bytemode, sizeflag);
14522
64.5k
  return OP_OFF64 (ins, bytemode, sizeflag);
14523
129k
}
14524
14525
static bool
14526
CFCMOV_Fixup (instr_info *ins, int opnd, int sizeflag)
14527
4.10k
{
14528
  /* EVEX.NF is used as a direction bit in the 2-operand case to reverse the
14529
     source and destination operands.  */
14530
4.10k
  bool dstmem = !ins->vex.nd && ins->vex.nf;
14531
14532
4.10k
  if (opnd == 0)
14533
2.09k
    {
14534
2.09k
      if (dstmem)
14535
570
  return OP_E (ins, v_swap_mode, sizeflag);
14536
1.52k
      return OP_G (ins, v_mode, sizeflag);
14537
2.09k
    }
14538
14539
  /* These bits have been consumed and should be cleared.  */
14540
2.00k
  ins->vex.nf = false;
14541
2.00k
  ins->vex.mask_register_specifier = 0;
14542
14543
2.00k
  if (dstmem)
14544
484
    return OP_G (ins, v_mode, sizeflag);
14545
1.52k
  return OP_E (ins, v_mode, sizeflag);
14546
2.00k
}