Coverage Report

Created: 2026-03-10 08:46

next uncovered line (L), next uncovered region (R), next uncovered branch (B)
/src/binutils-gdb/opcodes/avr-dis.c
Line
Count
Source
1
/* Disassemble AVR instructions.
2
   Copyright (C) 1999-2026 Free Software Foundation, Inc.
3
4
   Contributed by Denis Chertykov <denisc@overta.ru>
5
6
   This file is part of libopcodes.
7
8
   This library is free software; you can redistribute it and/or modify
9
   it under the terms of the GNU General Public License as published by
10
   the Free Software Foundation; either version 3, or (at your option)
11
   any later version.
12
13
   It is distributed in the hope that it will be useful, but WITHOUT
14
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
16
   License for more details.
17
18
   You should have received a copy of the GNU General Public License
19
   along with this program; if not, write to the Free Software
20
   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21
   MA 02110-1301, USA.  */
22
23
#include "sysdep.h"
24
#include <assert.h>
25
#include "disassemble.h"
26
#include "opintl.h"
27
#include "libiberty.h"
28
#include <stdint.h>
29
30
struct avr_opcodes_s
31
{
32
  char *name;
33
  char *constraints;
34
  char *opcode;
35
  int insn_size;    /* In words.  */
36
  int isa;
37
  unsigned int bin_opcode;
38
};
39
40
#define AVR_INSN(NAME, CONSTR, OPCODE, SIZE, ISA, BIN) \
41
{#NAME, CONSTR, OPCODE, SIZE, ISA, BIN},
42
43
const struct avr_opcodes_s avr_opcodes[] =
44
{
45
  #include "opcode/avr.h"
46
  {NULL, NULL, NULL, 0, 0, 0}
47
};
48
49
static const char * comment_start = "0x";
50
51
static int
52
avr_operand (unsigned int        insn,
53
       unsigned int        insn2,
54
       unsigned int        pc,
55
       int                 constraint,
56
             char *              opcode_str,
57
       char *              buf,
58
       char *              comment,
59
       enum disassembler_style *  style,
60
       int                 regs,
61
       int *               sym,
62
       bfd_vma *           sym_addr,
63
       disassemble_info *  info)
64
350k
{
65
350k
  int ok = 1;
66
350k
  *sym = 0;
67
68
350k
  switch (constraint)
69
350k
    {
70
      /* Any register operand.  */
71
121k
    case 'r':
72
121k
      if (regs)
73
41.3k
  insn = (insn & 0xf) | ((insn & 0x0200) >> 5); /* Source register.  */
74
80.3k
      else
75
80.3k
  insn = (insn & 0x01f0) >> 4; /* Destination register.  */
76
77
121k
      sprintf (buf, "r%d", insn);
78
121k
      *style = dis_style_register;
79
121k
      break;
80
81
77.7k
    case 'd':
82
77.7k
      if (regs)
83
3.20k
  sprintf (buf, "r%d", 16 + (insn & 0xf));
84
74.5k
      else
85
74.5k
  sprintf (buf, "r%d", 16 + ((insn & 0xf0) >> 4));
86
77.7k
      *style = dis_style_register;
87
77.7k
      break;
88
89
950
    case 'w':
90
950
      sprintf (buf, "r%d", 24 + ((insn & 0x30) >> 3));
91
950
      *style = dis_style_register;
92
950
      break;
93
94
2.30k
    case 'a':
95
2.30k
      if (regs)
96
1.15k
  sprintf (buf, "r%d", 16 + (insn & 7));
97
1.15k
      else
98
1.15k
  sprintf (buf, "r%d", 16 + ((insn >> 4) & 7));
99
2.30k
      *style = dis_style_register;
100
2.30k
      break;
101
102
8.26k
    case 'v':
103
8.26k
      if (regs)
104
4.13k
  sprintf (buf, "r%d", (insn & 0xf) * 2);
105
4.13k
      else
106
4.13k
  sprintf (buf, "r%d", ((insn & 0xf0) >> 3));
107
8.26k
      *style = dis_style_register;
108
8.26k
      break;
109
110
4.91k
    case 'e':
111
4.91k
      {
112
4.91k
  char *xyz;
113
114
4.91k
  switch (insn & 0x100f)
115
4.91k
    {
116
960
      case 0x0000: xyz = "Z";  break;
117
871
      case 0x1001: xyz = "Z+"; break;
118
465
      case 0x1002: xyz = "-Z"; break;
119
247
      case 0x0008: xyz = "Y";  break;
120
106
      case 0x1009: xyz = "Y+"; break;
121
261
      case 0x100a: xyz = "-Y"; break;
122
372
      case 0x100c: xyz = "X";  break;
123
297
      case 0x100d: xyz = "X+"; break;
124
335
      case 0x100e: xyz = "-X"; break;
125
996
      default: xyz = "??"; ok = 0;
126
4.91k
    }
127
4.91k
  strcpy (buf, xyz);
128
129
4.91k
  if (AVR_UNDEF_P (insn))
130
627
    sprintf (comment, _("undefined"));
131
4.91k
      }
132
0
      *style = dis_style_register;
133
4.91k
      break;
134
135
1.14k
    case 'z':
136
1.14k
      *buf++ = 'Z';
137
138
      /* Check for post-increment. */
139
1.14k
      char *s;
140
18.7k
      for (s = opcode_str; *s; ++s)
141
18.3k
        {
142
18.3k
          if (*s == '+')
143
690
            {
144
690
        if (insn & (1 << (15 - (s - opcode_str))))
145
326
    *buf++ = '+';
146
690
              break;
147
690
            }
148
18.3k
        }
149
150
1.14k
      *buf = '\0';
151
1.14k
      if (AVR_UNDEF_P (insn))
152
16
  sprintf (comment, _("undefined"));
153
1.14k
      *style = dis_style_register;
154
1.14k
      break;
155
156
19.2k
    case 'b':
157
19.2k
      {
158
19.2k
  unsigned int x;
159
160
19.2k
  x = (insn & 7);
161
19.2k
  x |= (insn >> 7) & (3 << 3);
162
19.2k
  x |= (insn >> 8) & (1 << 5);
163
164
19.2k
  if (insn & 0x8)
165
9.21k
    *buf++ = 'Y';
166
10.0k
  else
167
10.0k
    *buf++ = 'Z';
168
19.2k
  sprintf (buf, "+%d", x);
169
19.2k
  sprintf (comment, "0x%02x", x);
170
19.2k
  *style = dis_style_register;
171
19.2k
      }
172
19.2k
      break;
173
174
205
    case 'h':
175
205
      *sym = 1;
176
205
      *sym_addr = ((((insn & 1) | ((insn & 0x1f0) >> 3)) << 16) | insn2) * 2;
177
      /* See PR binutils/2454.  Ideally we would like to display the hex
178
   value of the address only once, but this would mean recoding
179
   objdump_print_address() which would affect many targets.  */
180
205
      sprintf (buf, "%#lx", (unsigned long) *sym_addr);
181
205
      strcpy (comment, comment_start);
182
205
      info->insn_info_valid = 1;
183
205
      info->insn_type = dis_jsr;
184
205
      info->target = *sym_addr;
185
205
      *style = dis_style_address;
186
205
      break;
187
188
18.8k
    case 'L':
189
18.8k
      {
190
18.8k
  int rel_addr = (((insn & 0xfff) ^ 0x800) - 0x800) * 2;
191
18.8k
  sprintf (buf, ".%+-8d", rel_addr);
192
18.8k
        *sym = 1;
193
18.8k
        *sym_addr = pc + 2 + rel_addr;
194
18.8k
  strcpy (comment, comment_start);
195
18.8k
        info->insn_info_valid = 1;
196
18.8k
        info->insn_type = dis_branch;
197
18.8k
        info->target = *sym_addr;
198
18.8k
  *style = dis_style_address_offset;
199
18.8k
      }
200
18.8k
      break;
201
202
4.76k
    case 'l':
203
4.76k
      {
204
4.76k
  int rel_addr = ((((insn >> 3) & 0x7f) ^ 0x40) - 0x40) * 2;
205
206
4.76k
  sprintf (buf, ".%+-8d", rel_addr);
207
4.76k
        *sym = 1;
208
4.76k
        *sym_addr = pc + 2 + rel_addr;
209
4.76k
  strcpy (comment, comment_start);
210
4.76k
        info->insn_info_valid = 1;
211
4.76k
        info->insn_type = dis_condbranch;
212
4.76k
        info->target = *sym_addr;
213
4.76k
  *style = dis_style_address_offset;
214
4.76k
      }
215
4.76k
      break;
216
217
404
    case 'i':
218
404
      {
219
404
        unsigned int val = insn2 | 0x800000;
220
404
        *sym = 1;
221
404
        *sym_addr = val;
222
404
        sprintf (buf, "0x%04X", insn2);
223
404
        strcpy (comment, comment_start);
224
404
  *style = dis_style_immediate;
225
404
      }
226
404
      break;
227
228
1.00k
    case 'j':
229
1.00k
      {
230
1.00k
        unsigned int val = ((insn & 0xf) | ((insn & 0x600) >> 5)
231
1.00k
                                         | ((insn & 0x100) >> 2));
232
1.00k
  if ((insn & 0x100) == 0)
233
734
    val |= 0x80;
234
1.00k
        *sym = 1;
235
1.00k
        *sym_addr = val | 0x800000;
236
1.00k
        sprintf (buf, "0x%02x", val);
237
1.00k
        strcpy (comment, comment_start);
238
1.00k
  *style = dis_style_immediate;
239
1.00k
      }
240
1.00k
      break;
241
242
70.3k
    case 'M':
243
70.3k
      sprintf (buf, "0x%02X", ((insn & 0xf00) >> 4) | (insn & 0xf));
244
70.3k
      sprintf (comment, "%d", ((insn & 0xf00) >> 4) | (insn & 0xf));
245
70.3k
      *style = dis_style_immediate;
246
70.3k
      break;
247
248
0
    case 'n':
249
0
      sprintf (buf, "??");
250
      /* xgettext:c-format */
251
0
      opcodes_error_handler (_("internal disassembler error"));
252
0
      ok = 0;
253
0
      *style = dis_style_immediate;
254
0
      break;
255
256
950
    case 'K':
257
950
      {
258
950
  unsigned int x;
259
260
950
  x = (insn & 0xf) | ((insn >> 2) & 0x30);
261
950
  sprintf (buf, "0x%02x", x);
262
950
  sprintf (comment, "%d", x);
263
950
  *style = dis_style_immediate;
264
950
      }
265
950
      break;
266
267
7.08k
    case 's':
268
7.08k
      sprintf (buf, "%d", insn & 7);
269
7.08k
      *style = dis_style_immediate;
270
7.08k
      break;
271
272
0
    case 'S':
273
0
      sprintf (buf, "%d", (insn >> 4) & 7);
274
0
      *style = dis_style_immediate;
275
0
      break;
276
277
8.61k
    case 'P':
278
8.61k
      {
279
8.61k
  unsigned int x;
280
281
8.61k
  x = (insn & 0xf);
282
8.61k
  x |= (insn >> 5) & 0x30;
283
8.61k
  sprintf (buf, "0x%02x", x);
284
8.61k
  sprintf (comment, "%d", x);
285
8.61k
  *style = dis_style_address;
286
8.61k
      }
287
8.61k
      break;
288
289
2.05k
    case 'p':
290
2.05k
      {
291
2.05k
  unsigned int x;
292
293
2.05k
  x = (insn >> 3) & 0x1f;
294
2.05k
  sprintf (buf, "0x%02x", x);
295
2.05k
  sprintf (comment, "%d", x);
296
2.05k
  *style = dis_style_address;
297
2.05k
      }
298
2.05k
      break;
299
300
63
    case 'E':
301
63
      sprintf (buf, "%d", (insn >> 4) & 15);
302
63
      *style = dis_style_immediate;
303
63
      break;
304
305
0
    case '?':
306
0
      *buf = '\0';
307
0
      break;
308
309
0
    default:
310
0
      sprintf (buf, "??");
311
      /* xgettext:c-format */
312
0
      opcodes_error_handler (_("unknown constraint `%c'"), constraint);
313
0
      ok = 0;
314
350k
    }
315
316
350k
    return ok;
317
350k
}
318
319
/* Read the opcode from ADDR.  Return 0 in success and save opcode
320
   in *INSN, otherwise, return -1.  */
321
322
static int
323
avrdis_opcode (bfd_vma addr, disassemble_info *info, uint16_t *insn)
324
271k
{
325
271k
  bfd_byte buffer[2];
326
271k
  int status;
327
328
271k
  status = info->read_memory_func (addr, buffer, 2, info);
329
330
271k
  if (status == 0)
331
271k
    {
332
271k
      *insn = bfd_getl16 (buffer);
333
271k
      return 0;
334
271k
    }
335
336
166
  info->memory_error_func (status, addr, info);
337
166
  return -1;
338
271k
}
339
340
341
int
342
print_insn_avr (bfd_vma addr, disassemble_info *info)
343
270k
{
344
270k
  uint16_t insn, insn2;
345
270k
  const struct avr_opcodes_s *opcode;
346
270k
  static unsigned int *maskptr;
347
270k
  void *stream = info->stream;
348
270k
  fprintf_styled_ftype prin = info->fprintf_styled_func;
349
270k
  static unsigned int *avr_bin_masks;
350
270k
  static int initialized;
351
270k
  int cmd_len = 2;
352
270k
  int ok = 0;
353
270k
  char op1[20], op2[20], comment1[40], comment2[40];
354
270k
  enum disassembler_style style_op1, style_op2;
355
270k
  int sym_op1 = 0, sym_op2 = 0;
356
270k
  bfd_vma sym_addr1, sym_addr2;
357
358
  /* Clear instruction information field.  */
359
270k
  info->insn_info_valid = 0;
360
270k
  info->branch_delay_insns = 0;
361
270k
  info->data_size = 0;
362
270k
  info->insn_type = dis_noninsn;
363
270k
  info->target = 0;
364
270k
  info->target2 = 0;
365
366
270k
  if (!initialized)
367
2
    {
368
2
      unsigned int nopcodes;
369
370
      /* PR 4045: Try to avoid duplicating the 0x prefix that
371
   objdump_print_addr() will put on addresses when there
372
   is no symbol table available.  */
373
2
      if (info->symtab_size == 0)
374
2
  comment_start = " ";
375
376
2
      nopcodes = sizeof (avr_opcodes) / sizeof (struct avr_opcodes_s);
377
378
2
      avr_bin_masks = xmalloc (nopcodes * sizeof (unsigned int));
379
380
2
      for (opcode = avr_opcodes, maskptr = avr_bin_masks;
381
252
     opcode->name;
382
250
     opcode++, maskptr++)
383
250
  {
384
250
    char * s;
385
250
    unsigned int bin = 0;
386
250
    unsigned int mask = 0;
387
388
4.25k
    for (s = opcode->opcode; *s; ++s)
389
4.00k
      {
390
4.00k
        bin <<= 1;
391
4.00k
        mask <<= 1;
392
4.00k
        bin |= (*s == '1');
393
4.00k
        mask |= (*s == '1' || *s == '0');
394
4.00k
      }
395
250
    assert (s - opcode->opcode == 16);
396
250
    assert (opcode->bin_opcode == bin);
397
250
    *maskptr = mask;
398
250
  }
399
400
2
      initialized = 1;
401
2
    }
402
403
270k
  if (avrdis_opcode (addr, info, &insn)  != 0)
404
165
    return -1;
405
406
270k
  for (opcode = avr_opcodes, maskptr = avr_bin_masks;
407
19.3M
       opcode->name;
408
19.1M
       opcode++, maskptr++)
409
19.3M
    {
410
19.3M
      if ((opcode->isa == AVR_ISA_TINY) && (info->mach != bfd_mach_avrtiny))
411
123k
        continue;
412
19.2M
      if ((insn & *maskptr) == opcode->bin_opcode)
413
223k
        break;
414
19.2M
    }
415
416
  /* Special case: disassemble `ldd r,b+0' as `ld r,b', and
417
     `std b+0,r' as `st b,r' (next entry in the table).  */
418
419
270k
  if (AVR_DISP0_P (insn))
420
1.20k
    opcode++;
421
422
270k
  op1[0] = 0;
423
270k
  op2[0] = 0;
424
270k
  comment1[0] = 0;
425
270k
  comment2[0] = 0;
426
270k
  style_op1 = dis_style_text;
427
270k
  style_op2 = dis_style_text;
428
429
270k
  if (opcode->name)
430
223k
    {
431
223k
      char *constraints = opcode->constraints;
432
223k
      char *opcode_str = opcode->opcode;
433
434
223k
      insn2 = 0;
435
223k
      ok = 1;
436
437
223k
      if (opcode->insn_size > 1)
438
610
  {
439
610
    if (avrdis_opcode (addr + 2, info, &insn2) != 0)
440
1
      return -1;
441
609
    cmd_len = 4;
442
609
  }
443
444
223k
      if (*constraints && *constraints != '?')
445
187k
  {
446
187k
    int regs = REGISTER_P (*constraints);
447
448
187k
    ok = avr_operand (insn, insn2, addr, *constraints, opcode_str, op1,
449
187k
          comment1, &style_op1, 0, &sym_op1, &sym_addr1,
450
187k
          info);
451
452
187k
    if (ok && *(++constraints) == ',')
453
162k
      ok = avr_operand (insn, insn2, addr, *(++constraints), opcode_str,
454
162k
            op2, *comment1 ? comment2 : comment1,
455
162k
            &style_op2, regs, &sym_op2, &sym_addr2,
456
162k
            info);
457
187k
  }
458
223k
    }
459
460
270k
  if (!ok)
461
48.2k
    {
462
      /* Unknown opcode, or invalid combination of operands.  */
463
48.2k
      sprintf (op1, "0x%04x", insn);
464
48.2k
      op2[0] = 0;
465
48.2k
      sprintf (comment1, "????");
466
48.2k
      comment2[0] = 0;
467
48.2k
    }
468
469
270k
  (*prin) (stream, ok ? dis_style_mnemonic : dis_style_assembler_directive,
470
270k
     "%s", ok ? opcode->name : ".word");
471
  
472
270k
  if (*op1)
473
235k
    (*prin) (stream, style_op1, "\t%s", op1);
474
475
270k
  if (*op2)
476
162k
    {
477
162k
      (*prin) (stream, dis_style_text, ", ");
478
162k
      (*prin) (stream, style_op2, "%s", op2);
479
162k
    }
480
481
270k
  if (*comment1)
482
175k
    (*prin) (stream, dis_style_comment_start, "\t; %s", comment1);
483
484
270k
  if (sym_op1)
485
24.5k
    info->print_address_func (sym_addr1, info);
486
487
270k
  if (*comment2)
488
0
    (*prin) (stream, dis_style_comment_start, " %s", comment2);
489
490
270k
  if (sym_op2)
491
677
    info->print_address_func (sym_addr2, info);
492
493
270k
  return cmd_len;
494
270k
}